2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * dwc2_dump_channel_info() - Prints the state of a host channel
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
63 * Must be called with interrupt disabled and spinlock held
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
68 static void dwc2_dump_channel_info(struct dwc2_hsotg
*hsotg
,
69 struct dwc2_host_chan
*chan
)
72 int num_channels
= hsotg
->core_params
->host_channels
;
83 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
84 hcsplt
= dwc2_readl(hsotg
->regs
+ HCSPLT(chan
->hc_num
));
85 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
86 hc_dma
= dwc2_readl(hsotg
->regs
+ HCDMA(chan
->hc_num
));
88 dev_dbg(hsotg
->dev
, " Assigned to channel %p:\n", chan
);
89 dev_dbg(hsotg
->dev
, " hcchar 0x%08x, hcsplt 0x%08x\n",
91 dev_dbg(hsotg
->dev
, " hctsiz 0x%08x, hc_dma 0x%08x\n",
93 dev_dbg(hsotg
->dev
, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
95 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
96 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
97 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n", chan
->data_pid_start
);
98 dev_dbg(hsotg
->dev
, " xfer_started: %d\n", chan
->xfer_started
);
99 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
100 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
101 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
102 (unsigned long)chan
->xfer_dma
);
103 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
104 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
105 dev_dbg(hsotg
->dev
, " NP inactive sched:\n");
106 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_inactive
,
108 dev_dbg(hsotg
->dev
, " %p\n", qh
);
109 dev_dbg(hsotg
->dev
, " NP active sched:\n");
110 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_active
,
112 dev_dbg(hsotg
->dev
, " %p\n", qh
);
113 dev_dbg(hsotg
->dev
, " Channels:\n");
114 for (i
= 0; i
< num_channels
; i
++) {
115 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
117 dev_dbg(hsotg
->dev
, " %2d: %p\n", i
, chan
);
119 #endif /* VERBOSE_DEBUG */
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
126 * Must be called with interrupt disabled and spinlock held
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg
*hsotg
,
129 struct list_head
*qh_list
)
131 struct dwc2_qh
*qh
, *qh_tmp
;
132 struct dwc2_qtd
*qtd
, *qtd_tmp
;
134 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
135 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
137 dwc2_host_complete(hsotg
, qtd
, -ECONNRESET
);
138 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
143 static void dwc2_qh_list_free(struct dwc2_hsotg
*hsotg
,
144 struct list_head
*qh_list
)
146 struct dwc2_qtd
*qtd
, *qtd_tmp
;
147 struct dwc2_qh
*qh
, *qh_tmp
;
151 /* The list hasn't been initialized yet */
154 spin_lock_irqsave(&hsotg
->lock
, flags
);
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg
, qh_list
);
159 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
160 dwc2_hcd_qh_unlink(hsotg
, qh
);
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
165 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
167 if (qh
->channel
&& qh
->channel
->qh
== qh
)
168 qh
->channel
->qh
= NULL
;
170 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
171 dwc2_hcd_qh_free(hsotg
, qh
);
172 spin_lock_irqsave(&hsotg
->lock
, flags
);
175 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
179 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
180 * and periodic schedules. The QTD associated with each URB is removed from
181 * the schedule and freed. This function may be called when a disconnect is
182 * detected or when the HCD is being stopped.
184 * Must be called with interrupt disabled and spinlock held
186 static void dwc2_kill_all_urbs(struct dwc2_hsotg
*hsotg
)
188 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_inactive
);
189 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_active
);
190 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_inactive
);
191 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_ready
);
192 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_assigned
);
193 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_queued
);
197 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
199 * @hsotg: Pointer to struct dwc2_hsotg
201 void dwc2_hcd_start(struct dwc2_hsotg
*hsotg
)
205 if (hsotg
->op_state
== OTG_STATE_B_HOST
) {
207 * Reset the port. During a HNP mode switch the reset
208 * needs to occur within 1ms and have a duration of at
211 hprt0
= dwc2_read_hprt0(hsotg
);
213 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
216 queue_delayed_work(hsotg
->wq_otg
, &hsotg
->start_work
,
217 msecs_to_jiffies(50));
220 /* Must be called with interrupt disabled and spinlock held */
221 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg
*hsotg
)
223 int num_channels
= hsotg
->core_params
->host_channels
;
224 struct dwc2_host_chan
*channel
;
228 if (hsotg
->core_params
->dma_enable
<= 0) {
229 /* Flush out any channel requests in slave mode */
230 for (i
= 0; i
< num_channels
; i
++) {
231 channel
= hsotg
->hc_ptr_array
[i
];
232 if (!list_empty(&channel
->hc_list_entry
))
234 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
235 if (hcchar
& HCCHAR_CHENA
) {
236 hcchar
&= ~(HCCHAR_CHENA
| HCCHAR_EPDIR
);
237 hcchar
|= HCCHAR_CHDIS
;
238 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
243 for (i
= 0; i
< num_channels
; i
++) {
244 channel
= hsotg
->hc_ptr_array
[i
];
245 if (!list_empty(&channel
->hc_list_entry
))
247 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
248 if (hcchar
& HCCHAR_CHENA
) {
249 /* Halt the channel */
250 hcchar
|= HCCHAR_CHDIS
;
251 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
254 dwc2_hc_cleanup(hsotg
, channel
);
255 list_add_tail(&channel
->hc_list_entry
, &hsotg
->free_hc_list
);
257 * Added for Descriptor DMA to prevent channel double cleanup in
258 * release_channel_ddma(), which is called from ep_disable when
263 /* All channels have been freed, mark them available */
264 if (hsotg
->core_params
->uframe_sched
> 0) {
265 hsotg
->available_host_channels
=
266 hsotg
->core_params
->host_channels
;
268 hsotg
->non_periodic_channels
= 0;
269 hsotg
->periodic_channels
= 0;
274 * dwc2_hcd_connect() - Handles connect of the HCD
276 * @hsotg: Pointer to struct dwc2_hsotg
278 * Must be called with interrupt disabled and spinlock held
280 void dwc2_hcd_connect(struct dwc2_hsotg
*hsotg
)
282 if (hsotg
->lx_state
!= DWC2_L0
)
283 usb_hcd_resume_root_hub(hsotg
->priv
);
285 hsotg
->flags
.b
.port_connect_status_change
= 1;
286 hsotg
->flags
.b
.port_connect_status
= 1;
290 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
292 * @hsotg: Pointer to struct dwc2_hsotg
293 * @force: If true, we won't try to reconnect even if we see device connected.
295 * Must be called with interrupt disabled and spinlock held
297 void dwc2_hcd_disconnect(struct dwc2_hsotg
*hsotg
, bool force
)
302 /* Set status flags for the hub driver */
303 hsotg
->flags
.b
.port_connect_status_change
= 1;
304 hsotg
->flags
.b
.port_connect_status
= 0;
307 * Shutdown any transfers in process by clearing the Tx FIFO Empty
308 * interrupt mask and status bits and disabling subsequent host
309 * channel interrupts.
311 intr
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
312 intr
&= ~(GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
);
313 dwc2_writel(intr
, hsotg
->regs
+ GINTMSK
);
314 intr
= GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
;
315 dwc2_writel(intr
, hsotg
->regs
+ GINTSTS
);
318 * Turn off the vbus power only if the core has transitioned to device
319 * mode. If still in host mode, need to keep power on to detect a
322 if (dwc2_is_device_mode(hsotg
)) {
323 if (hsotg
->op_state
!= OTG_STATE_A_SUSPEND
) {
324 dev_dbg(hsotg
->dev
, "Disconnect: PortPower off\n");
325 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
328 dwc2_disable_host_interrupts(hsotg
);
331 /* Respond with an error status to all URBs in the schedule */
332 dwc2_kill_all_urbs(hsotg
);
334 if (dwc2_is_host_mode(hsotg
))
335 /* Clean up any host channels that were in use */
336 dwc2_hcd_cleanup_channels(hsotg
);
338 dwc2_host_disconnect(hsotg
);
341 * Add an extra check here to see if we're actually connected but
342 * we don't have a detection interrupt pending. This can happen if:
343 * 1. hardware sees connect
344 * 2. hardware sees disconnect
345 * 3. hardware sees connect
346 * 4. dwc2_port_intr() - clears connect interrupt
347 * 5. dwc2_handle_common_intr() - calls here
349 * Without the extra check here we will end calling disconnect
350 * and won't get any future interrupts to handle the connect.
353 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
354 if (!(hprt0
& HPRT0_CONNDET
) && (hprt0
& HPRT0_CONNSTS
))
355 dwc2_hcd_connect(hsotg
);
360 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
362 * @hsotg: Pointer to struct dwc2_hsotg
364 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg
*hsotg
)
366 if (hsotg
->bus_suspended
) {
367 hsotg
->flags
.b
.port_suspend_change
= 1;
368 usb_hcd_resume_root_hub(hsotg
->priv
);
371 if (hsotg
->lx_state
== DWC2_L1
)
372 hsotg
->flags
.b
.port_l1_change
= 1;
376 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
378 * @hsotg: Pointer to struct dwc2_hsotg
380 * Must be called with interrupt disabled and spinlock held
382 void dwc2_hcd_stop(struct dwc2_hsotg
*hsotg
)
384 dev_dbg(hsotg
->dev
, "DWC OTG HCD STOP\n");
387 * The root hub should be disconnected before this function is called.
388 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
389 * and the QH lists (via ..._hcd_endpoint_disable).
392 /* Turn off all host-specific interrupts */
393 dwc2_disable_host_interrupts(hsotg
);
395 /* Turn off the vbus power */
396 dev_dbg(hsotg
->dev
, "PortPower off\n");
397 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
400 /* Caller must hold driver lock */
401 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg
*hsotg
,
402 struct dwc2_hcd_urb
*urb
, struct dwc2_qh
*qh
,
403 struct dwc2_qtd
*qtd
)
409 if (!hsotg
->flags
.b
.port_connect_status
) {
410 /* No longer connected */
411 dev_err(hsotg
->dev
, "Not connected\n");
415 dev_speed
= dwc2_host_get_speed(hsotg
, urb
->priv
);
417 /* Some configurations cannot support LS traffic on a FS root port */
418 if ((dev_speed
== USB_SPEED_LOW
) &&
419 (hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
) &&
420 (hsotg
->hw_params
.hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
)) {
421 u32 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
422 u32 prtspd
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
424 if (prtspd
== HPRT0_SPD_FULL_SPEED
)
431 dwc2_hcd_qtd_init(qtd
, urb
);
432 retval
= dwc2_hcd_qtd_add(hsotg
, qtd
, qh
);
435 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
440 intr_mask
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
441 if (!(intr_mask
& GINTSTS_SOF
)) {
442 enum dwc2_transaction_type tr_type
;
444 if (qtd
->qh
->ep_type
== USB_ENDPOINT_XFER_BULK
&&
445 !(qtd
->urb
->flags
& URB_GIVEBACK_ASAP
))
447 * Do not schedule SG transactions until qtd has
448 * URB_GIVEBACK_ASAP set
452 tr_type
= dwc2_hcd_select_transactions(hsotg
);
453 if (tr_type
!= DWC2_TRANSACTION_NONE
)
454 dwc2_hcd_queue_transactions(hsotg
, tr_type
);
460 /* Must be called with interrupt disabled and spinlock held */
461 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg
*hsotg
,
462 struct dwc2_hcd_urb
*urb
)
465 struct dwc2_qtd
*urb_qtd
;
469 dev_dbg(hsotg
->dev
, "## Urb QTD is NULL ##\n");
475 dev_dbg(hsotg
->dev
, "## Urb QTD QH is NULL ##\n");
481 if (urb_qtd
->in_process
&& qh
->channel
) {
482 dwc2_dump_channel_info(hsotg
, qh
->channel
);
484 /* The QTD is in process (it has been assigned to a channel) */
485 if (hsotg
->flags
.b
.port_connect_status
)
487 * If still connected (i.e. in host mode), halt the
488 * channel so it can be used for other transfers. If
489 * no longer connected, the host registers can't be
490 * written to halt the channel since the core is in
493 dwc2_hc_halt(hsotg
, qh
->channel
,
494 DWC2_HC_XFER_URB_DEQUEUE
);
498 * Free the QTD and clean up the associated QH. Leave the QH in the
499 * schedule if it has any remaining QTDs.
501 if (hsotg
->core_params
->dma_desc_enable
<= 0) {
502 u8 in_process
= urb_qtd
->in_process
;
504 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
506 dwc2_hcd_qh_deactivate(hsotg
, qh
, 0);
508 } else if (list_empty(&qh
->qtd_list
)) {
509 dwc2_hcd_qh_unlink(hsotg
, qh
);
512 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
518 /* Must NOT be called with interrupt disabled or spinlock held */
519 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg
*hsotg
,
520 struct usb_host_endpoint
*ep
, int retry
)
522 struct dwc2_qtd
*qtd
, *qtd_tmp
;
527 spin_lock_irqsave(&hsotg
->lock
, flags
);
535 while (!list_empty(&qh
->qtd_list
) && retry
--) {
538 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
543 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
544 usleep_range(20000, 40000);
545 spin_lock_irqsave(&hsotg
->lock
, flags
);
553 dwc2_hcd_qh_unlink(hsotg
, qh
);
555 /* Free each QTD in the QH's QTD list */
556 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
, qtd_list_entry
)
557 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
561 if (qh
->channel
&& qh
->channel
->qh
== qh
)
562 qh
->channel
->qh
= NULL
;
564 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
566 dwc2_hcd_qh_free(hsotg
, qh
);
572 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
577 /* Must be called with interrupt disabled and spinlock held */
578 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg
*hsotg
,
579 struct usb_host_endpoint
*ep
)
581 struct dwc2_qh
*qh
= ep
->hcpriv
;
586 qh
->data_toggle
= DWC2_HC_PID_DATA0
;
592 * Initializes dynamic portions of the DWC_otg HCD state
594 * Must be called with interrupt disabled and spinlock held
596 static void dwc2_hcd_reinit(struct dwc2_hsotg
*hsotg
)
598 struct dwc2_host_chan
*chan
, *chan_tmp
;
602 hsotg
->flags
.d32
= 0;
603 hsotg
->non_periodic_qh_ptr
= &hsotg
->non_periodic_sched_active
;
605 if (hsotg
->core_params
->uframe_sched
> 0) {
606 hsotg
->available_host_channels
=
607 hsotg
->core_params
->host_channels
;
609 hsotg
->non_periodic_channels
= 0;
610 hsotg
->periodic_channels
= 0;
614 * Put all channels in the free channel list and clean up channel
617 list_for_each_entry_safe(chan
, chan_tmp
, &hsotg
->free_hc_list
,
619 list_del_init(&chan
->hc_list_entry
);
621 num_channels
= hsotg
->core_params
->host_channels
;
622 for (i
= 0; i
< num_channels
; i
++) {
623 chan
= hsotg
->hc_ptr_array
[i
];
624 list_add_tail(&chan
->hc_list_entry
, &hsotg
->free_hc_list
);
625 dwc2_hc_cleanup(hsotg
, chan
);
628 /* Initialize the DWC core for host mode operation */
629 dwc2_core_host_init(hsotg
);
632 static void dwc2_hc_init_split(struct dwc2_hsotg
*hsotg
,
633 struct dwc2_host_chan
*chan
,
634 struct dwc2_qtd
*qtd
, struct dwc2_hcd_urb
*urb
)
636 int hub_addr
, hub_port
;
639 chan
->xact_pos
= qtd
->isoc_split_pos
;
640 chan
->complete_split
= qtd
->complete_split
;
641 dwc2_host_hub_info(hsotg
, urb
->priv
, &hub_addr
, &hub_port
);
642 chan
->hub_addr
= (u8
)hub_addr
;
643 chan
->hub_port
= (u8
)hub_port
;
646 static void dwc2_hc_init_xfer(struct dwc2_hsotg
*hsotg
,
647 struct dwc2_host_chan
*chan
,
648 struct dwc2_qtd
*qtd
)
650 struct dwc2_hcd_urb
*urb
= qtd
->urb
;
651 struct dwc2_hcd_iso_packet_desc
*frame_desc
;
653 switch (dwc2_hcd_get_pipe_type(&urb
->pipe_info
)) {
654 case USB_ENDPOINT_XFER_CONTROL
:
655 chan
->ep_type
= USB_ENDPOINT_XFER_CONTROL
;
657 switch (qtd
->control_phase
) {
658 case DWC2_CONTROL_SETUP
:
659 dev_vdbg(hsotg
->dev
, " Control setup transaction\n");
662 chan
->data_pid_start
= DWC2_HC_PID_SETUP
;
663 if (hsotg
->core_params
->dma_enable
> 0)
664 chan
->xfer_dma
= urb
->setup_dma
;
666 chan
->xfer_buf
= urb
->setup_packet
;
670 case DWC2_CONTROL_DATA
:
671 dev_vdbg(hsotg
->dev
, " Control data transaction\n");
672 chan
->data_pid_start
= qtd
->data_toggle
;
675 case DWC2_CONTROL_STATUS
:
677 * Direction is opposite of data direction or IN if no
680 dev_vdbg(hsotg
->dev
, " Control status transaction\n");
681 if (urb
->length
== 0)
685 dwc2_hcd_is_pipe_out(&urb
->pipe_info
);
688 chan
->data_pid_start
= DWC2_HC_PID_DATA1
;
690 if (hsotg
->core_params
->dma_enable
> 0)
691 chan
->xfer_dma
= hsotg
->status_buf_dma
;
693 chan
->xfer_buf
= hsotg
->status_buf
;
698 case USB_ENDPOINT_XFER_BULK
:
699 chan
->ep_type
= USB_ENDPOINT_XFER_BULK
;
702 case USB_ENDPOINT_XFER_INT
:
703 chan
->ep_type
= USB_ENDPOINT_XFER_INT
;
706 case USB_ENDPOINT_XFER_ISOC
:
707 chan
->ep_type
= USB_ENDPOINT_XFER_ISOC
;
708 if (hsotg
->core_params
->dma_desc_enable
> 0)
711 frame_desc
= &urb
->iso_descs
[qtd
->isoc_frame_index
];
712 frame_desc
->status
= 0;
714 if (hsotg
->core_params
->dma_enable
> 0) {
715 chan
->xfer_dma
= urb
->dma
;
716 chan
->xfer_dma
+= frame_desc
->offset
+
717 qtd
->isoc_split_offset
;
719 chan
->xfer_buf
= urb
->buf
;
720 chan
->xfer_buf
+= frame_desc
->offset
+
721 qtd
->isoc_split_offset
;
724 chan
->xfer_len
= frame_desc
->length
- qtd
->isoc_split_offset
;
726 if (chan
->xact_pos
== DWC2_HCSPLT_XACTPOS_ALL
) {
727 if (chan
->xfer_len
<= 188)
728 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_ALL
;
730 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_BEGIN
;
736 #define DWC2_USB_DMA_ALIGN 4
738 struct dma_aligned_buffer
{
740 void *old_xfer_buffer
;
744 static void dwc2_free_dma_aligned_buffer(struct urb
*urb
)
746 struct dma_aligned_buffer
*temp
;
748 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
751 temp
= container_of(urb
->transfer_buffer
,
752 struct dma_aligned_buffer
, data
);
754 if (usb_urb_dir_in(urb
))
755 memcpy(temp
->old_xfer_buffer
, temp
->data
,
756 urb
->transfer_buffer_length
);
757 urb
->transfer_buffer
= temp
->old_xfer_buffer
;
758 kfree(temp
->kmalloc_ptr
);
760 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
763 static int dwc2_alloc_dma_aligned_buffer(struct urb
*urb
, gfp_t mem_flags
)
765 struct dma_aligned_buffer
*temp
, *kmalloc_ptr
;
768 if (urb
->num_sgs
|| urb
->sg
||
769 urb
->transfer_buffer_length
== 0 ||
770 !((uintptr_t)urb
->transfer_buffer
& (DWC2_USB_DMA_ALIGN
- 1)))
773 /* Allocate a buffer with enough padding for alignment */
774 kmalloc_size
= urb
->transfer_buffer_length
+
775 sizeof(struct dma_aligned_buffer
) + DWC2_USB_DMA_ALIGN
- 1;
777 kmalloc_ptr
= kmalloc(kmalloc_size
, mem_flags
);
781 /* Position our struct dma_aligned_buffer such that data is aligned */
782 temp
= PTR_ALIGN(kmalloc_ptr
+ 1, DWC2_USB_DMA_ALIGN
) - 1;
783 temp
->kmalloc_ptr
= kmalloc_ptr
;
784 temp
->old_xfer_buffer
= urb
->transfer_buffer
;
785 if (usb_urb_dir_out(urb
))
786 memcpy(temp
->data
, urb
->transfer_buffer
,
787 urb
->transfer_buffer_length
);
788 urb
->transfer_buffer
= temp
->data
;
790 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
795 static int dwc2_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
800 /* We assume setup_dma is always aligned; warn if not */
801 WARN_ON_ONCE(urb
->setup_dma
&&
802 (urb
->setup_dma
& (DWC2_USB_DMA_ALIGN
- 1)));
804 ret
= dwc2_alloc_dma_aligned_buffer(urb
, mem_flags
);
808 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
810 dwc2_free_dma_aligned_buffer(urb
);
815 static void dwc2_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
817 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
818 dwc2_free_dma_aligned_buffer(urb
);
822 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
823 * channel and initializes the host channel to perform the transactions. The
824 * host channel is removed from the free list.
826 * @hsotg: The HCD state structure
827 * @qh: Transactions from the first QTD for this QH are selected and assigned
828 * to a free host channel
830 static int dwc2_assign_and_init_hc(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
832 struct dwc2_host_chan
*chan
;
833 struct dwc2_hcd_urb
*urb
;
834 struct dwc2_qtd
*qtd
;
837 dev_vdbg(hsotg
->dev
, "%s(%p,%p)\n", __func__
, hsotg
, qh
);
839 if (list_empty(&qh
->qtd_list
)) {
840 dev_dbg(hsotg
->dev
, "No QTDs in QH list\n");
844 if (list_empty(&hsotg
->free_hc_list
)) {
845 dev_dbg(hsotg
->dev
, "No free channel to assign\n");
849 chan
= list_first_entry(&hsotg
->free_hc_list
, struct dwc2_host_chan
,
852 /* Remove host channel from free list */
853 list_del_init(&chan
->hc_list_entry
);
855 qtd
= list_first_entry(&qh
->qtd_list
, struct dwc2_qtd
, qtd_list_entry
);
861 * Use usb_pipedevice to determine device address. This address is
862 * 0 before the SET_ADDRESS command and the correct address afterward.
864 chan
->dev_addr
= dwc2_hcd_get_dev_addr(&urb
->pipe_info
);
865 chan
->ep_num
= dwc2_hcd_get_ep_num(&urb
->pipe_info
);
866 chan
->speed
= qh
->dev_speed
;
867 chan
->max_packet
= dwc2_max_packet(qh
->maxp
);
869 chan
->xfer_started
= 0;
870 chan
->halt_status
= DWC2_HC_XFER_NO_HALT_STATUS
;
871 chan
->error_state
= (qtd
->error_count
> 0);
872 chan
->halt_on_queue
= 0;
873 chan
->halt_pending
= 0;
877 * The following values may be modified in the transfer type section
878 * below. The xfer_len value may be reduced when the transfer is
879 * started to accommodate the max widths of the XferSize and PktCnt
880 * fields in the HCTSIZn register.
883 chan
->ep_is_in
= (dwc2_hcd_is_pipe_in(&urb
->pipe_info
) != 0);
887 chan
->do_ping
= qh
->ping_state
;
889 chan
->data_pid_start
= qh
->data_toggle
;
890 chan
->multi_count
= 1;
892 if (urb
->actual_length
> urb
->length
&&
893 !dwc2_hcd_is_pipe_in(&urb
->pipe_info
))
894 urb
->actual_length
= urb
->length
;
896 if (hsotg
->core_params
->dma_enable
> 0)
897 chan
->xfer_dma
= urb
->dma
+ urb
->actual_length
;
899 chan
->xfer_buf
= (u8
*)urb
->buf
+ urb
->actual_length
;
901 chan
->xfer_len
= urb
->length
- urb
->actual_length
;
902 chan
->xfer_count
= 0;
904 /* Set the split attributes if required */
906 dwc2_hc_init_split(hsotg
, chan
, qtd
, urb
);
910 /* Set the transfer attributes */
911 dwc2_hc_init_xfer(hsotg
, chan
, qtd
);
913 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
914 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
916 * This value may be modified when the transfer is started
917 * to reflect the actual transfer length
919 chan
->multi_count
= dwc2_hb_mult(qh
->maxp
);
921 if (hsotg
->core_params
->dma_desc_enable
> 0) {
922 chan
->desc_list_addr
= qh
->desc_list_dma
;
923 chan
->desc_list_sz
= qh
->desc_list_sz
;
926 dwc2_hc_init(hsotg
, chan
);
933 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
934 * schedule and assigns them to available host channels. Called from the HCD
935 * interrupt handler functions.
937 * @hsotg: The HCD state structure
939 * Return: The types of new transactions that were assigned to host channels
941 enum dwc2_transaction_type
dwc2_hcd_select_transactions(
942 struct dwc2_hsotg
*hsotg
)
944 enum dwc2_transaction_type ret_val
= DWC2_TRANSACTION_NONE
;
945 struct list_head
*qh_ptr
;
949 #ifdef DWC2_DEBUG_SOF
950 dev_vdbg(hsotg
->dev
, " Select Transactions\n");
953 /* Process entries in the periodic ready list */
954 qh_ptr
= hsotg
->periodic_sched_ready
.next
;
955 while (qh_ptr
!= &hsotg
->periodic_sched_ready
) {
956 if (list_empty(&hsotg
->free_hc_list
))
958 if (hsotg
->core_params
->uframe_sched
> 0) {
959 if (hsotg
->available_host_channels
<= 1)
961 hsotg
->available_host_channels
--;
963 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
964 if (dwc2_assign_and_init_hc(hsotg
, qh
))
968 * Move the QH from the periodic ready schedule to the
969 * periodic assigned schedule
971 qh_ptr
= qh_ptr
->next
;
972 list_move_tail(&qh
->qh_list_entry
,
973 &hsotg
->periodic_sched_assigned
);
974 ret_val
= DWC2_TRANSACTION_PERIODIC
;
978 * Process entries in the inactive portion of the non-periodic
979 * schedule. Some free host channels may not be used if they are
980 * reserved for periodic transfers.
982 num_channels
= hsotg
->core_params
->host_channels
;
983 qh_ptr
= hsotg
->non_periodic_sched_inactive
.next
;
984 while (qh_ptr
!= &hsotg
->non_periodic_sched_inactive
) {
985 if (hsotg
->core_params
->uframe_sched
<= 0 &&
986 hsotg
->non_periodic_channels
>= num_channels
-
987 hsotg
->periodic_channels
)
989 if (list_empty(&hsotg
->free_hc_list
))
991 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
992 if (hsotg
->core_params
->uframe_sched
> 0) {
993 if (hsotg
->available_host_channels
< 1)
995 hsotg
->available_host_channels
--;
998 if (dwc2_assign_and_init_hc(hsotg
, qh
))
1002 * Move the QH from the non-periodic inactive schedule to the
1003 * non-periodic active schedule
1005 qh_ptr
= qh_ptr
->next
;
1006 list_move_tail(&qh
->qh_list_entry
,
1007 &hsotg
->non_periodic_sched_active
);
1009 if (ret_val
== DWC2_TRANSACTION_NONE
)
1010 ret_val
= DWC2_TRANSACTION_NON_PERIODIC
;
1012 ret_val
= DWC2_TRANSACTION_ALL
;
1014 if (hsotg
->core_params
->uframe_sched
<= 0)
1015 hsotg
->non_periodic_channels
++;
1022 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
1023 * a host channel associated with either a periodic or non-periodic transfer
1025 * @hsotg: The HCD state structure
1026 * @chan: Host channel descriptor associated with either a periodic or
1027 * non-periodic transfer
1028 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
1029 * for periodic transfers or the non-periodic Tx FIFO
1030 * for non-periodic transfers
1032 * Return: 1 if a request is queued and more requests may be needed to
1033 * complete the transfer, 0 if no more requests are required for this
1034 * transfer, -1 if there is insufficient space in the Tx FIFO
1036 * This function assumes that there is space available in the appropriate
1037 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1038 * it checks whether space is available in the appropriate Tx FIFO.
1040 * Must be called with interrupt disabled and spinlock held
1042 static int dwc2_queue_transaction(struct dwc2_hsotg
*hsotg
,
1043 struct dwc2_host_chan
*chan
,
1044 u16 fifo_dwords_avail
)
1049 /* Put ourselves on the list to keep order straight */
1050 list_move_tail(&chan
->split_order_list_entry
,
1051 &hsotg
->split_order
);
1053 if (hsotg
->core_params
->dma_enable
> 0) {
1054 if (hsotg
->core_params
->dma_desc_enable
> 0) {
1055 if (!chan
->xfer_started
||
1056 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
1057 dwc2_hcd_start_xfer_ddma(hsotg
, chan
->qh
);
1058 chan
->qh
->ping_state
= 0;
1060 } else if (!chan
->xfer_started
) {
1061 dwc2_hc_start_transfer(hsotg
, chan
);
1062 chan
->qh
->ping_state
= 0;
1064 } else if (chan
->halt_pending
) {
1065 /* Don't queue a request if the channel has been halted */
1066 } else if (chan
->halt_on_queue
) {
1067 dwc2_hc_halt(hsotg
, chan
, chan
->halt_status
);
1068 } else if (chan
->do_ping
) {
1069 if (!chan
->xfer_started
)
1070 dwc2_hc_start_transfer(hsotg
, chan
);
1071 } else if (!chan
->ep_is_in
||
1072 chan
->data_pid_start
== DWC2_HC_PID_SETUP
) {
1073 if ((fifo_dwords_avail
* 4) >= chan
->max_packet
) {
1074 if (!chan
->xfer_started
) {
1075 dwc2_hc_start_transfer(hsotg
, chan
);
1078 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
1084 if (!chan
->xfer_started
) {
1085 dwc2_hc_start_transfer(hsotg
, chan
);
1088 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
1096 * Processes periodic channels for the next frame and queues transactions for
1097 * these channels to the DWC_otg controller. After queueing transactions, the
1098 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1099 * to queue as Periodic Tx FIFO or request queue space becomes available.
1100 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1102 * Must be called with interrupt disabled and spinlock held
1104 static void dwc2_process_periodic_channels(struct dwc2_hsotg
*hsotg
)
1106 struct list_head
*qh_ptr
;
1112 bool no_queue_space
= false;
1113 bool no_fifo_space
= false;
1116 /* If empty list then just adjust interrupt enables */
1117 if (list_empty(&hsotg
->periodic_sched_assigned
))
1121 dev_vdbg(hsotg
->dev
, "Queue periodic transactions\n");
1123 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1124 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1125 TXSTS_QSPCAVAIL_SHIFT
;
1126 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1127 TXSTS_FSPCAVAIL_SHIFT
;
1130 dev_vdbg(hsotg
->dev
, " P Tx Req Queue Space Avail (before queue): %d\n",
1132 dev_vdbg(hsotg
->dev
, " P Tx FIFO Space Avail (before queue): %d\n",
1136 qh_ptr
= hsotg
->periodic_sched_assigned
.next
;
1137 while (qh_ptr
!= &hsotg
->periodic_sched_assigned
) {
1138 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1139 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1140 TXSTS_QSPCAVAIL_SHIFT
;
1141 if (qspcavail
== 0) {
1146 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
1148 qh_ptr
= qh_ptr
->next
;
1152 /* Make sure EP's TT buffer is clean before queueing qtds */
1153 if (qh
->tt_buffer_dirty
) {
1154 qh_ptr
= qh_ptr
->next
;
1159 * Set a flag if we're queuing high-bandwidth in slave mode.
1160 * The flag prevents any halts to get into the request queue in
1161 * the middle of multiple high-bandwidth packets getting queued.
1163 if (hsotg
->core_params
->dma_enable
<= 0 &&
1164 qh
->channel
->multi_count
> 1)
1165 hsotg
->queuing_high_bandwidth
= 1;
1167 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1168 TXSTS_FSPCAVAIL_SHIFT
;
1169 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
1176 * In Slave mode, stay on the current transfer until there is
1177 * nothing more to do or the high-bandwidth request count is
1178 * reached. In DMA mode, only need to queue one request. The
1179 * controller automatically handles multiple packets for
1180 * high-bandwidth transfers.
1182 if (hsotg
->core_params
->dma_enable
> 0 || status
== 0 ||
1183 qh
->channel
->requests
== qh
->channel
->multi_count
) {
1184 qh_ptr
= qh_ptr
->next
;
1186 * Move the QH from the periodic assigned schedule to
1187 * the periodic queued schedule
1189 list_move_tail(&qh
->qh_list_entry
,
1190 &hsotg
->periodic_sched_queued
);
1192 /* done queuing high bandwidth */
1193 hsotg
->queuing_high_bandwidth
= 0;
1198 if (no_queue_space
|| no_fifo_space
||
1199 (hsotg
->core_params
->dma_enable
<= 0 &&
1200 !list_empty(&hsotg
->periodic_sched_assigned
))) {
1202 * May need to queue more transactions as the request
1203 * queue or Tx FIFO empties. Enable the periodic Tx
1204 * FIFO empty interrupt. (Always use the half-empty
1205 * level to ensure that new requests are loaded as
1206 * soon as possible.)
1208 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1209 if (!(gintmsk
& GINTSTS_PTXFEMP
)) {
1210 gintmsk
|= GINTSTS_PTXFEMP
;
1211 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1215 * Disable the Tx FIFO empty interrupt since there are
1216 * no more transactions that need to be queued right
1217 * now. This function is called from interrupt
1218 * handlers to queue more transactions as transfer
1221 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1222 if (gintmsk
& GINTSTS_PTXFEMP
) {
1223 gintmsk
&= ~GINTSTS_PTXFEMP
;
1224 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1230 * Processes active non-periodic channels and queues transactions for these
1231 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1232 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1233 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1234 * FIFO Empty interrupt is disabled.
1236 * Must be called with interrupt disabled and spinlock held
1238 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg
*hsotg
)
1240 struct list_head
*orig_qh_ptr
;
1247 int no_queue_space
= 0;
1248 int no_fifo_space
= 0;
1251 dev_vdbg(hsotg
->dev
, "Queue non-periodic transactions\n");
1253 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1254 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1255 TXSTS_QSPCAVAIL_SHIFT
;
1256 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1257 TXSTS_FSPCAVAIL_SHIFT
;
1258 dev_vdbg(hsotg
->dev
, " NP Tx Req Queue Space Avail (before queue): %d\n",
1260 dev_vdbg(hsotg
->dev
, " NP Tx FIFO Space Avail (before queue): %d\n",
1264 * Keep track of the starting point. Skip over the start-of-list
1267 if (hsotg
->non_periodic_qh_ptr
== &hsotg
->non_periodic_sched_active
)
1268 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
1269 orig_qh_ptr
= hsotg
->non_periodic_qh_ptr
;
1272 * Process once through the active list or until no more space is
1273 * available in the request queue or the Tx FIFO
1276 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1277 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1278 TXSTS_QSPCAVAIL_SHIFT
;
1279 if (hsotg
->core_params
->dma_enable
<= 0 && qspcavail
== 0) {
1284 qh
= list_entry(hsotg
->non_periodic_qh_ptr
, struct dwc2_qh
,
1289 /* Make sure EP's TT buffer is clean before queueing qtds */
1290 if (qh
->tt_buffer_dirty
)
1293 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1294 TXSTS_FSPCAVAIL_SHIFT
;
1295 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
1299 } else if (status
< 0) {
1304 /* Advance to next QH, skipping start-of-list entry */
1305 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
1306 if (hsotg
->non_periodic_qh_ptr
==
1307 &hsotg
->non_periodic_sched_active
)
1308 hsotg
->non_periodic_qh_ptr
=
1309 hsotg
->non_periodic_qh_ptr
->next
;
1310 } while (hsotg
->non_periodic_qh_ptr
!= orig_qh_ptr
);
1312 if (hsotg
->core_params
->dma_enable
<= 0) {
1313 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1314 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1315 TXSTS_QSPCAVAIL_SHIFT
;
1316 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1317 TXSTS_FSPCAVAIL_SHIFT
;
1318 dev_vdbg(hsotg
->dev
,
1319 " NP Tx Req Queue Space Avail (after queue): %d\n",
1321 dev_vdbg(hsotg
->dev
,
1322 " NP Tx FIFO Space Avail (after queue): %d\n",
1325 if (more_to_do
|| no_queue_space
|| no_fifo_space
) {
1327 * May need to queue more transactions as the request
1328 * queue or Tx FIFO empties. Enable the non-periodic
1329 * Tx FIFO empty interrupt. (Always use the half-empty
1330 * level to ensure that new requests are loaded as
1331 * soon as possible.)
1333 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1334 gintmsk
|= GINTSTS_NPTXFEMP
;
1335 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1338 * Disable the Tx FIFO empty interrupt since there are
1339 * no more transactions that need to be queued right
1340 * now. This function is called from interrupt
1341 * handlers to queue more transactions as transfer
1344 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1345 gintmsk
&= ~GINTSTS_NPTXFEMP
;
1346 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1352 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1353 * and queues transactions for these channels to the DWC_otg controller. Called
1354 * from the HCD interrupt handler functions.
1356 * @hsotg: The HCD state structure
1357 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1360 * Must be called with interrupt disabled and spinlock held
1362 void dwc2_hcd_queue_transactions(struct dwc2_hsotg
*hsotg
,
1363 enum dwc2_transaction_type tr_type
)
1365 #ifdef DWC2_DEBUG_SOF
1366 dev_vdbg(hsotg
->dev
, "Queue Transactions\n");
1368 /* Process host channels associated with periodic transfers */
1369 if (tr_type
== DWC2_TRANSACTION_PERIODIC
||
1370 tr_type
== DWC2_TRANSACTION_ALL
)
1371 dwc2_process_periodic_channels(hsotg
);
1373 /* Process host channels associated with non-periodic transfers */
1374 if (tr_type
== DWC2_TRANSACTION_NON_PERIODIC
||
1375 tr_type
== DWC2_TRANSACTION_ALL
) {
1376 if (!list_empty(&hsotg
->non_periodic_sched_active
)) {
1377 dwc2_process_non_periodic_channels(hsotg
);
1380 * Ensure NP Tx FIFO empty interrupt is disabled when
1381 * there are no non-periodic transfers to process
1383 u32 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1385 gintmsk
&= ~GINTSTS_NPTXFEMP
;
1386 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1391 static void dwc2_conn_id_status_change(struct work_struct
*work
)
1393 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
1397 unsigned long flags
;
1399 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1401 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
1402 dev_dbg(hsotg
->dev
, "gotgctl=%0x\n", gotgctl
);
1403 dev_dbg(hsotg
->dev
, "gotgctl.b.conidsts=%d\n",
1404 !!(gotgctl
& GOTGCTL_CONID_B
));
1406 /* B-Device connector (Device Mode) */
1407 if (gotgctl
& GOTGCTL_CONID_B
) {
1408 /* Wait for switch to device mode */
1409 dev_dbg(hsotg
->dev
, "connId B\n");
1410 while (!dwc2_is_device_mode(hsotg
)) {
1411 dev_info(hsotg
->dev
,
1412 "Waiting for Peripheral Mode, Mode=%s\n",
1413 dwc2_is_host_mode(hsotg
) ? "Host" :
1415 usleep_range(20000, 40000);
1421 "Connection id status change timed out\n");
1422 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
1423 dwc2_core_init(hsotg
, false);
1424 dwc2_enable_global_interrupts(hsotg
);
1425 spin_lock_irqsave(&hsotg
->lock
, flags
);
1426 dwc2_hsotg_core_init_disconnected(hsotg
, false);
1427 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1428 dwc2_hsotg_core_connect(hsotg
);
1430 /* A-Device connector (Host Mode) */
1431 dev_dbg(hsotg
->dev
, "connId A\n");
1432 while (!dwc2_is_host_mode(hsotg
)) {
1433 dev_info(hsotg
->dev
, "Waiting for Host Mode, Mode=%s\n",
1434 dwc2_is_host_mode(hsotg
) ?
1435 "Host" : "Peripheral");
1436 usleep_range(20000, 40000);
1442 "Connection id status change timed out\n");
1443 hsotg
->op_state
= OTG_STATE_A_HOST
;
1445 /* Initialize the Core for Host mode */
1446 dwc2_core_init(hsotg
, false);
1447 dwc2_enable_global_interrupts(hsotg
);
1448 dwc2_hcd_start(hsotg
);
1452 static void dwc2_wakeup_detected(unsigned long data
)
1454 struct dwc2_hsotg
*hsotg
= (struct dwc2_hsotg
*)data
;
1457 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1460 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1461 * so that OPT tests pass with all PHYs.)
1463 hprt0
= dwc2_read_hprt0(hsotg
);
1464 dev_dbg(hsotg
->dev
, "Resume: HPRT0=%0x\n", hprt0
);
1465 hprt0
&= ~HPRT0_RES
;
1466 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1467 dev_dbg(hsotg
->dev
, "Clear Resume: HPRT0=%0x\n",
1468 dwc2_readl(hsotg
->regs
+ HPRT0
));
1470 dwc2_hcd_rem_wakeup(hsotg
);
1471 hsotg
->bus_suspended
= 0;
1473 /* Change to L0 state */
1474 hsotg
->lx_state
= DWC2_L0
;
1477 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg
*hsotg
)
1479 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
1481 return hcd
->self
.b_hnp_enable
;
1484 /* Must NOT be called with interrupt disabled or spinlock held */
1485 static void dwc2_port_suspend(struct dwc2_hsotg
*hsotg
, u16 windex
)
1487 unsigned long flags
;
1492 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1494 spin_lock_irqsave(&hsotg
->lock
, flags
);
1496 if (windex
== hsotg
->otg_port
&& dwc2_host_is_b_hnp_enabled(hsotg
)) {
1497 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
1498 gotgctl
|= GOTGCTL_HSTSETHNPEN
;
1499 dwc2_writel(gotgctl
, hsotg
->regs
+ GOTGCTL
);
1500 hsotg
->op_state
= OTG_STATE_A_SUSPEND
;
1503 hprt0
= dwc2_read_hprt0(hsotg
);
1504 hprt0
|= HPRT0_SUSP
;
1505 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1507 hsotg
->bus_suspended
= 1;
1510 * If hibernation is supported, Phy clock will be suspended
1511 * after registers are backuped.
1513 if (!hsotg
->core_params
->hibernation
) {
1514 /* Suspend the Phy Clock */
1515 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1516 pcgctl
|= PCGCTL_STOPPCLK
;
1517 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1521 /* For HNP the bus must be suspended for at least 200ms */
1522 if (dwc2_host_is_b_hnp_enabled(hsotg
)) {
1523 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1524 pcgctl
&= ~PCGCTL_STOPPCLK
;
1525 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1527 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1529 usleep_range(200000, 250000);
1531 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1535 /* Must NOT be called with interrupt disabled or spinlock held */
1536 static void dwc2_port_resume(struct dwc2_hsotg
*hsotg
)
1538 unsigned long flags
;
1542 spin_lock_irqsave(&hsotg
->lock
, flags
);
1545 * If hibernation is supported, Phy clock is already resumed
1546 * after registers restore.
1548 if (!hsotg
->core_params
->hibernation
) {
1549 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1550 pcgctl
&= ~PCGCTL_STOPPCLK
;
1551 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1552 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1553 usleep_range(20000, 40000);
1554 spin_lock_irqsave(&hsotg
->lock
, flags
);
1557 hprt0
= dwc2_read_hprt0(hsotg
);
1559 hprt0
&= ~HPRT0_SUSP
;
1560 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1561 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1563 msleep(USB_RESUME_TIMEOUT
);
1565 spin_lock_irqsave(&hsotg
->lock
, flags
);
1566 hprt0
= dwc2_read_hprt0(hsotg
);
1567 hprt0
&= ~(HPRT0_RES
| HPRT0_SUSP
);
1568 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1569 hsotg
->bus_suspended
= 0;
1570 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1573 /* Handles hub class-specific requests */
1574 static int dwc2_hcd_hub_control(struct dwc2_hsotg
*hsotg
, u16 typereq
,
1575 u16 wvalue
, u16 windex
, char *buf
, u16 wlength
)
1577 struct usb_hub_descriptor
*hub_desc
;
1585 case ClearHubFeature
:
1586 dev_dbg(hsotg
->dev
, "ClearHubFeature %1xh\n", wvalue
);
1589 case C_HUB_LOCAL_POWER
:
1590 case C_HUB_OVER_CURRENT
:
1591 /* Nothing required here */
1597 "ClearHubFeature request %1xh unknown\n",
1602 case ClearPortFeature
:
1603 if (wvalue
!= USB_PORT_FEAT_L1
)
1604 if (!windex
|| windex
> 1)
1607 case USB_PORT_FEAT_ENABLE
:
1609 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1610 hprt0
= dwc2_read_hprt0(hsotg
);
1612 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1615 case USB_PORT_FEAT_SUSPEND
:
1617 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1619 if (hsotg
->bus_suspended
)
1620 dwc2_port_resume(hsotg
);
1623 case USB_PORT_FEAT_POWER
:
1625 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1626 hprt0
= dwc2_read_hprt0(hsotg
);
1627 hprt0
&= ~HPRT0_PWR
;
1628 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1631 case USB_PORT_FEAT_INDICATOR
:
1633 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1634 /* Port indicator not supported */
1637 case USB_PORT_FEAT_C_CONNECTION
:
1639 * Clears driver's internal Connect Status Change flag
1642 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1643 hsotg
->flags
.b
.port_connect_status_change
= 0;
1646 case USB_PORT_FEAT_C_RESET
:
1647 /* Clears driver's internal Port Reset Change flag */
1649 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1650 hsotg
->flags
.b
.port_reset_change
= 0;
1653 case USB_PORT_FEAT_C_ENABLE
:
1655 * Clears the driver's internal Port Enable/Disable
1659 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1660 hsotg
->flags
.b
.port_enable_change
= 0;
1663 case USB_PORT_FEAT_C_SUSPEND
:
1665 * Clears the driver's internal Port Suspend Change
1666 * flag, which is set when resume signaling on the host
1670 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1671 hsotg
->flags
.b
.port_suspend_change
= 0;
1674 case USB_PORT_FEAT_C_PORT_L1
:
1676 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1677 hsotg
->flags
.b
.port_l1_change
= 0;
1680 case USB_PORT_FEAT_C_OVER_CURRENT
:
1682 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1683 hsotg
->flags
.b
.port_over_current_change
= 0;
1689 "ClearPortFeature request %1xh unknown or unsupported\n",
1694 case GetHubDescriptor
:
1695 dev_dbg(hsotg
->dev
, "GetHubDescriptor\n");
1696 hub_desc
= (struct usb_hub_descriptor
*)buf
;
1697 hub_desc
->bDescLength
= 9;
1698 hub_desc
->bDescriptorType
= USB_DT_HUB
;
1699 hub_desc
->bNbrPorts
= 1;
1700 hub_desc
->wHubCharacteristics
=
1701 cpu_to_le16(HUB_CHAR_COMMON_LPSM
|
1702 HUB_CHAR_INDV_PORT_OCPM
);
1703 hub_desc
->bPwrOn2PwrGood
= 1;
1704 hub_desc
->bHubContrCurrent
= 0;
1705 hub_desc
->u
.hs
.DeviceRemovable
[0] = 0;
1706 hub_desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
1710 dev_dbg(hsotg
->dev
, "GetHubStatus\n");
1715 dev_vdbg(hsotg
->dev
,
1716 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex
,
1718 if (!windex
|| windex
> 1)
1722 if (hsotg
->flags
.b
.port_connect_status_change
)
1723 port_status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1724 if (hsotg
->flags
.b
.port_enable_change
)
1725 port_status
|= USB_PORT_STAT_C_ENABLE
<< 16;
1726 if (hsotg
->flags
.b
.port_suspend_change
)
1727 port_status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1728 if (hsotg
->flags
.b
.port_l1_change
)
1729 port_status
|= USB_PORT_STAT_C_L1
<< 16;
1730 if (hsotg
->flags
.b
.port_reset_change
)
1731 port_status
|= USB_PORT_STAT_C_RESET
<< 16;
1732 if (hsotg
->flags
.b
.port_over_current_change
) {
1733 dev_warn(hsotg
->dev
, "Overcurrent change detected\n");
1734 port_status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
1737 if (!hsotg
->flags
.b
.port_connect_status
) {
1739 * The port is disconnected, which means the core is
1740 * either in device mode or it soon will be. Just
1741 * return 0's for the remainder of the port status
1742 * since the port register can't be read if the core
1743 * is in device mode.
1745 *(__le32
*)buf
= cpu_to_le32(port_status
);
1749 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
1750 dev_vdbg(hsotg
->dev
, " HPRT0: 0x%08x\n", hprt0
);
1752 if (hprt0
& HPRT0_CONNSTS
)
1753 port_status
|= USB_PORT_STAT_CONNECTION
;
1754 if (hprt0
& HPRT0_ENA
)
1755 port_status
|= USB_PORT_STAT_ENABLE
;
1756 if (hprt0
& HPRT0_SUSP
)
1757 port_status
|= USB_PORT_STAT_SUSPEND
;
1758 if (hprt0
& HPRT0_OVRCURRACT
)
1759 port_status
|= USB_PORT_STAT_OVERCURRENT
;
1760 if (hprt0
& HPRT0_RST
)
1761 port_status
|= USB_PORT_STAT_RESET
;
1762 if (hprt0
& HPRT0_PWR
)
1763 port_status
|= USB_PORT_STAT_POWER
;
1765 speed
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
1766 if (speed
== HPRT0_SPD_HIGH_SPEED
)
1767 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
1768 else if (speed
== HPRT0_SPD_LOW_SPEED
)
1769 port_status
|= USB_PORT_STAT_LOW_SPEED
;
1771 if (hprt0
& HPRT0_TSTCTL_MASK
)
1772 port_status
|= USB_PORT_STAT_TEST
;
1773 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1775 if (hsotg
->core_params
->dma_desc_fs_enable
) {
1777 * Enable descriptor DMA only if a full speed
1778 * device is connected.
1780 if (hsotg
->new_connection
&&
1782 (USB_PORT_STAT_CONNECTION
|
1783 USB_PORT_STAT_HIGH_SPEED
|
1784 USB_PORT_STAT_LOW_SPEED
)) ==
1785 USB_PORT_STAT_CONNECTION
)) {
1788 dev_info(hsotg
->dev
, "Enabling descriptor DMA mode\n");
1789 hsotg
->core_params
->dma_desc_enable
= 1;
1790 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
1791 hcfg
|= HCFG_DESCDMA
;
1792 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
1793 hsotg
->new_connection
= false;
1797 dev_vdbg(hsotg
->dev
, "port_status=%08x\n", port_status
);
1798 *(__le32
*)buf
= cpu_to_le32(port_status
);
1802 dev_dbg(hsotg
->dev
, "SetHubFeature\n");
1803 /* No HUB features supported */
1806 case SetPortFeature
:
1807 dev_dbg(hsotg
->dev
, "SetPortFeature\n");
1808 if (wvalue
!= USB_PORT_FEAT_TEST
&& (!windex
|| windex
> 1))
1811 if (!hsotg
->flags
.b
.port_connect_status
) {
1813 * The port is disconnected, which means the core is
1814 * either in device mode or it soon will be. Just
1815 * return without doing anything since the port
1816 * register can't be written if the core is in device
1823 case USB_PORT_FEAT_SUSPEND
:
1825 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1826 if (windex
!= hsotg
->otg_port
)
1828 dwc2_port_suspend(hsotg
, windex
);
1831 case USB_PORT_FEAT_POWER
:
1833 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1834 hprt0
= dwc2_read_hprt0(hsotg
);
1836 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1839 case USB_PORT_FEAT_RESET
:
1840 hprt0
= dwc2_read_hprt0(hsotg
);
1842 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1843 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1844 pcgctl
&= ~(PCGCTL_ENBL_SLEEP_GATING
| PCGCTL_STOPPCLK
);
1845 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1846 /* ??? Original driver does this */
1847 dwc2_writel(0, hsotg
->regs
+ PCGCTL
);
1849 hprt0
= dwc2_read_hprt0(hsotg
);
1850 /* Clear suspend bit if resetting from suspend state */
1851 hprt0
&= ~HPRT0_SUSP
;
1854 * When B-Host the Port reset bit is set in the Start
1855 * HCD Callback function, so that the reset is started
1856 * within 1ms of the HNP success interrupt
1858 if (!dwc2_hcd_is_b_host(hsotg
)) {
1859 hprt0
|= HPRT0_PWR
| HPRT0_RST
;
1861 "In host mode, hprt0=%08x\n", hprt0
);
1862 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1865 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1866 usleep_range(50000, 70000);
1867 hprt0
&= ~HPRT0_RST
;
1868 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1869 hsotg
->lx_state
= DWC2_L0
; /* Now back to On state */
1872 case USB_PORT_FEAT_INDICATOR
:
1874 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1878 case USB_PORT_FEAT_TEST
:
1879 hprt0
= dwc2_read_hprt0(hsotg
);
1881 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1882 hprt0
&= ~HPRT0_TSTCTL_MASK
;
1883 hprt0
|= (windex
>> 8) << HPRT0_TSTCTL_SHIFT
;
1884 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1890 "SetPortFeature %1xh unknown or unsupported\n",
1900 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1901 typereq
, windex
, wvalue
);
1908 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg
*hsotg
, int port
)
1915 retval
= (hsotg
->flags
.b
.port_connect_status_change
||
1916 hsotg
->flags
.b
.port_reset_change
||
1917 hsotg
->flags
.b
.port_enable_change
||
1918 hsotg
->flags
.b
.port_suspend_change
||
1919 hsotg
->flags
.b
.port_over_current_change
);
1923 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1924 dev_dbg(hsotg
->dev
, " port_connect_status_change: %d\n",
1925 hsotg
->flags
.b
.port_connect_status_change
);
1926 dev_dbg(hsotg
->dev
, " port_reset_change: %d\n",
1927 hsotg
->flags
.b
.port_reset_change
);
1928 dev_dbg(hsotg
->dev
, " port_enable_change: %d\n",
1929 hsotg
->flags
.b
.port_enable_change
);
1930 dev_dbg(hsotg
->dev
, " port_suspend_change: %d\n",
1931 hsotg
->flags
.b
.port_suspend_change
);
1932 dev_dbg(hsotg
->dev
, " port_over_current_change: %d\n",
1933 hsotg
->flags
.b
.port_over_current_change
);
1939 int dwc2_hcd_get_frame_number(struct dwc2_hsotg
*hsotg
)
1941 u32 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
1943 #ifdef DWC2_DEBUG_SOF
1944 dev_vdbg(hsotg
->dev
, "DWC OTG HCD GET FRAME NUMBER %d\n",
1945 (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
);
1947 return (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
;
1950 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg
*hsotg
, int us
)
1952 u32 hprt
= dwc2_readl(hsotg
->regs
+ HPRT0
);
1953 u32 hfir
= dwc2_readl(hsotg
->regs
+ HFIR
);
1954 u32 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
1955 unsigned int us_per_frame
;
1956 unsigned int frame_number
;
1957 unsigned int remaining
;
1958 unsigned int interval
;
1959 unsigned int phy_clks
;
1961 /* High speed has 125 us per (micro) frame; others are 1 ms per */
1962 us_per_frame
= (hprt
& HPRT0_SPD_MASK
) ? 1000 : 125;
1964 /* Extract fields */
1965 frame_number
= (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
;
1966 remaining
= (hfnum
& HFNUM_FRREM_MASK
) >> HFNUM_FRREM_SHIFT
;
1967 interval
= (hfir
& HFIR_FRINT_MASK
) >> HFIR_FRINT_SHIFT
;
1970 * Number of phy clocks since the last tick of the frame number after
1973 phy_clks
= (interval
- remaining
) +
1974 DIV_ROUND_UP(interval
* us
, us_per_frame
);
1976 return dwc2_frame_num_inc(frame_number
, phy_clks
/ interval
);
1979 int dwc2_hcd_is_b_host(struct dwc2_hsotg
*hsotg
)
1981 return hsotg
->op_state
== OTG_STATE_B_HOST
;
1984 static struct dwc2_hcd_urb
*dwc2_hcd_urb_alloc(struct dwc2_hsotg
*hsotg
,
1988 struct dwc2_hcd_urb
*urb
;
1989 u32 size
= sizeof(*urb
) + iso_desc_count
*
1990 sizeof(struct dwc2_hcd_iso_packet_desc
);
1992 urb
= kzalloc(size
, mem_flags
);
1994 urb
->packet_count
= iso_desc_count
;
1998 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg
*hsotg
,
1999 struct dwc2_hcd_urb
*urb
, u8 dev_addr
,
2000 u8 ep_num
, u8 ep_type
, u8 ep_dir
, u16 mps
)
2003 ep_type
== USB_ENDPOINT_XFER_BULK
||
2004 ep_type
== USB_ENDPOINT_XFER_CONTROL
)
2005 dev_vdbg(hsotg
->dev
,
2006 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
2007 dev_addr
, ep_num
, ep_dir
, ep_type
, mps
);
2008 urb
->pipe_info
.dev_addr
= dev_addr
;
2009 urb
->pipe_info
.ep_num
= ep_num
;
2010 urb
->pipe_info
.pipe_type
= ep_type
;
2011 urb
->pipe_info
.pipe_dir
= ep_dir
;
2012 urb
->pipe_info
.mps
= mps
;
2016 * NOTE: This function will be removed once the peripheral controller code
2017 * is integrated and the driver is stable
2019 void dwc2_hcd_dump_state(struct dwc2_hsotg
*hsotg
)
2022 struct dwc2_host_chan
*chan
;
2023 struct dwc2_hcd_urb
*urb
;
2024 struct dwc2_qtd
*qtd
;
2030 num_channels
= hsotg
->core_params
->host_channels
;
2031 dev_dbg(hsotg
->dev
, "\n");
2033 "************************************************************\n");
2034 dev_dbg(hsotg
->dev
, "HCD State:\n");
2035 dev_dbg(hsotg
->dev
, " Num channels: %d\n", num_channels
);
2037 for (i
= 0; i
< num_channels
; i
++) {
2038 chan
= hsotg
->hc_ptr_array
[i
];
2039 dev_dbg(hsotg
->dev
, " Channel %d:\n", i
);
2041 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
2042 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
2043 dev_dbg(hsotg
->dev
, " speed: %d\n", chan
->speed
);
2044 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
2045 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
2046 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n",
2047 chan
->data_pid_start
);
2048 dev_dbg(hsotg
->dev
, " multi_count: %d\n", chan
->multi_count
);
2049 dev_dbg(hsotg
->dev
, " xfer_started: %d\n",
2050 chan
->xfer_started
);
2051 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
2052 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
2053 (unsigned long)chan
->xfer_dma
);
2054 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
2055 dev_dbg(hsotg
->dev
, " xfer_count: %d\n", chan
->xfer_count
);
2056 dev_dbg(hsotg
->dev
, " halt_on_queue: %d\n",
2057 chan
->halt_on_queue
);
2058 dev_dbg(hsotg
->dev
, " halt_pending: %d\n",
2059 chan
->halt_pending
);
2060 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
2061 dev_dbg(hsotg
->dev
, " do_split: %d\n", chan
->do_split
);
2062 dev_dbg(hsotg
->dev
, " complete_split: %d\n",
2063 chan
->complete_split
);
2064 dev_dbg(hsotg
->dev
, " hub_addr: %d\n", chan
->hub_addr
);
2065 dev_dbg(hsotg
->dev
, " hub_port: %d\n", chan
->hub_port
);
2066 dev_dbg(hsotg
->dev
, " xact_pos: %d\n", chan
->xact_pos
);
2067 dev_dbg(hsotg
->dev
, " requests: %d\n", chan
->requests
);
2068 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
2070 if (chan
->xfer_started
) {
2071 u32 hfnum
, hcchar
, hctsiz
, hcint
, hcintmsk
;
2073 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
2074 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
2075 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(i
));
2076 hcint
= dwc2_readl(hsotg
->regs
+ HCINT(i
));
2077 hcintmsk
= dwc2_readl(hsotg
->regs
+ HCINTMSK(i
));
2078 dev_dbg(hsotg
->dev
, " hfnum: 0x%08x\n", hfnum
);
2079 dev_dbg(hsotg
->dev
, " hcchar: 0x%08x\n", hcchar
);
2080 dev_dbg(hsotg
->dev
, " hctsiz: 0x%08x\n", hctsiz
);
2081 dev_dbg(hsotg
->dev
, " hcint: 0x%08x\n", hcint
);
2082 dev_dbg(hsotg
->dev
, " hcintmsk: 0x%08x\n", hcintmsk
);
2085 if (!(chan
->xfer_started
&& chan
->qh
))
2088 list_for_each_entry(qtd
, &chan
->qh
->qtd_list
, qtd_list_entry
) {
2089 if (!qtd
->in_process
)
2092 dev_dbg(hsotg
->dev
, " URB Info:\n");
2093 dev_dbg(hsotg
->dev
, " qtd: %p, urb: %p\n",
2097 " Dev: %d, EP: %d %s\n",
2098 dwc2_hcd_get_dev_addr(&urb
->pipe_info
),
2099 dwc2_hcd_get_ep_num(&urb
->pipe_info
),
2100 dwc2_hcd_is_pipe_in(&urb
->pipe_info
) ?
2103 " Max packet size: %d\n",
2104 dwc2_hcd_get_mps(&urb
->pipe_info
));
2106 " transfer_buffer: %p\n",
2109 " transfer_dma: %08lx\n",
2110 (unsigned long)urb
->dma
);
2112 " transfer_buffer_length: %d\n",
2114 dev_dbg(hsotg
->dev
, " actual_length: %d\n",
2115 urb
->actual_length
);
2120 dev_dbg(hsotg
->dev
, " non_periodic_channels: %d\n",
2121 hsotg
->non_periodic_channels
);
2122 dev_dbg(hsotg
->dev
, " periodic_channels: %d\n",
2123 hsotg
->periodic_channels
);
2124 dev_dbg(hsotg
->dev
, " periodic_usecs: %d\n", hsotg
->periodic_usecs
);
2125 np_tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
2126 dev_dbg(hsotg
->dev
, " NP Tx Req Queue Space Avail: %d\n",
2127 (np_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
2128 dev_dbg(hsotg
->dev
, " NP Tx FIFO Space Avail: %d\n",
2129 (np_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
2130 p_tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
2131 dev_dbg(hsotg
->dev
, " P Tx Req Queue Space Avail: %d\n",
2132 (p_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
2133 dev_dbg(hsotg
->dev
, " P Tx FIFO Space Avail: %d\n",
2134 (p_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
2135 dwc2_hcd_dump_frrem(hsotg
);
2136 dwc2_dump_global_registers(hsotg
);
2137 dwc2_dump_host_registers(hsotg
);
2139 "************************************************************\n");
2140 dev_dbg(hsotg
->dev
, "\n");
2145 * NOTE: This function will be removed once the peripheral controller code
2146 * is integrated and the driver is stable
2148 void dwc2_hcd_dump_frrem(struct dwc2_hsotg
*hsotg
)
2150 #ifdef DWC2_DUMP_FRREM
2151 dev_dbg(hsotg
->dev
, "Frame remaining at SOF:\n");
2152 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2153 hsotg
->frrem_samples
, hsotg
->frrem_accum
,
2154 hsotg
->frrem_samples
> 0 ?
2155 hsotg
->frrem_accum
/ hsotg
->frrem_samples
: 0);
2156 dev_dbg(hsotg
->dev
, "\n");
2157 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 7):\n");
2158 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2159 hsotg
->hfnum_7_samples
,
2160 hsotg
->hfnum_7_frrem_accum
,
2161 hsotg
->hfnum_7_samples
> 0 ?
2162 hsotg
->hfnum_7_frrem_accum
/ hsotg
->hfnum_7_samples
: 0);
2163 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 0):\n");
2164 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2165 hsotg
->hfnum_0_samples
,
2166 hsotg
->hfnum_0_frrem_accum
,
2167 hsotg
->hfnum_0_samples
> 0 ?
2168 hsotg
->hfnum_0_frrem_accum
/ hsotg
->hfnum_0_samples
: 0);
2169 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 1-6):\n");
2170 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2171 hsotg
->hfnum_other_samples
,
2172 hsotg
->hfnum_other_frrem_accum
,
2173 hsotg
->hfnum_other_samples
> 0 ?
2174 hsotg
->hfnum_other_frrem_accum
/ hsotg
->hfnum_other_samples
:
2176 dev_dbg(hsotg
->dev
, "\n");
2177 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 7):\n");
2178 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2179 hsotg
->hfnum_7_samples_a
, hsotg
->hfnum_7_frrem_accum_a
,
2180 hsotg
->hfnum_7_samples_a
> 0 ?
2181 hsotg
->hfnum_7_frrem_accum_a
/ hsotg
->hfnum_7_samples_a
: 0);
2182 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 0):\n");
2183 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2184 hsotg
->hfnum_0_samples_a
, hsotg
->hfnum_0_frrem_accum_a
,
2185 hsotg
->hfnum_0_samples_a
> 0 ?
2186 hsotg
->hfnum_0_frrem_accum_a
/ hsotg
->hfnum_0_samples_a
: 0);
2187 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 1-6):\n");
2188 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2189 hsotg
->hfnum_other_samples_a
, hsotg
->hfnum_other_frrem_accum_a
,
2190 hsotg
->hfnum_other_samples_a
> 0 ?
2191 hsotg
->hfnum_other_frrem_accum_a
/ hsotg
->hfnum_other_samples_a
2193 dev_dbg(hsotg
->dev
, "\n");
2194 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 7):\n");
2195 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2196 hsotg
->hfnum_7_samples_b
, hsotg
->hfnum_7_frrem_accum_b
,
2197 hsotg
->hfnum_7_samples_b
> 0 ?
2198 hsotg
->hfnum_7_frrem_accum_b
/ hsotg
->hfnum_7_samples_b
: 0);
2199 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 0):\n");
2200 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2201 hsotg
->hfnum_0_samples_b
, hsotg
->hfnum_0_frrem_accum_b
,
2202 (hsotg
->hfnum_0_samples_b
> 0) ?
2203 hsotg
->hfnum_0_frrem_accum_b
/ hsotg
->hfnum_0_samples_b
: 0);
2204 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 1-6):\n");
2205 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2206 hsotg
->hfnum_other_samples_b
, hsotg
->hfnum_other_frrem_accum_b
,
2207 (hsotg
->hfnum_other_samples_b
> 0) ?
2208 hsotg
->hfnum_other_frrem_accum_b
/ hsotg
->hfnum_other_samples_b
2213 struct wrapper_priv_data
{
2214 struct dwc2_hsotg
*hsotg
;
2217 /* Gets the dwc2_hsotg from a usb_hcd */
2218 static struct dwc2_hsotg
*dwc2_hcd_to_hsotg(struct usb_hcd
*hcd
)
2220 struct wrapper_priv_data
*p
;
2222 p
= (struct wrapper_priv_data
*) &hcd
->hcd_priv
;
2226 static int _dwc2_hcd_start(struct usb_hcd
*hcd
);
2228 void dwc2_host_start(struct dwc2_hsotg
*hsotg
)
2230 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
2232 hcd
->self
.is_b_host
= dwc2_hcd_is_b_host(hsotg
);
2233 _dwc2_hcd_start(hcd
);
2236 void dwc2_host_disconnect(struct dwc2_hsotg
*hsotg
)
2238 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
2240 hcd
->self
.is_b_host
= 0;
2243 void dwc2_host_hub_info(struct dwc2_hsotg
*hsotg
, void *context
, int *hub_addr
,
2246 struct urb
*urb
= context
;
2249 *hub_addr
= urb
->dev
->tt
->hub
->devnum
;
2252 *hub_port
= urb
->dev
->ttport
;
2256 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
2258 * This will get the dwc2_tt structure (and ttport) associated with the given
2259 * context (which is really just a struct urb pointer).
2261 * The first time this is called for a given TT we allocate memory for our
2262 * structure. When everyone is done and has called dwc2_host_put_tt_info()
2263 * then the refcount for the structure will go to 0 and we'll free it.
2265 * @hsotg: The HCD state structure for the DWC OTG controller.
2266 * @qh: The QH structure.
2267 * @context: The priv pointer from a struct dwc2_hcd_urb.
2268 * @mem_flags: Flags for allocating memory.
2269 * @ttport: We'll return this device's port number here. That's used to
2270 * reference into the bitmap if we're on a multi_tt hub.
2272 * Return: a pointer to a struct dwc2_tt. Don't forget to call
2273 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
2276 struct dwc2_tt
*dwc2_host_get_tt_info(struct dwc2_hsotg
*hsotg
, void *context
,
2277 gfp_t mem_flags
, int *ttport
)
2279 struct urb
*urb
= context
;
2280 struct dwc2_tt
*dwc_tt
= NULL
;
2283 *ttport
= urb
->dev
->ttport
;
2285 dwc_tt
= urb
->dev
->tt
->hcpriv
;
2286 if (dwc_tt
== NULL
) {
2290 * For single_tt we need one schedule. For multi_tt
2291 * we need one per port.
2293 bitmap_size
= DWC2_ELEMENTS_PER_LS_BITMAP
*
2294 sizeof(dwc_tt
->periodic_bitmaps
[0]);
2295 if (urb
->dev
->tt
->multi
)
2296 bitmap_size
*= urb
->dev
->tt
->hub
->maxchild
;
2298 dwc_tt
= kzalloc(sizeof(*dwc_tt
) + bitmap_size
,
2303 dwc_tt
->usb_tt
= urb
->dev
->tt
;
2304 dwc_tt
->usb_tt
->hcpriv
= dwc_tt
;
2314 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
2316 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
2317 * of the structure are done.
2319 * It's OK to call this with NULL.
2321 * @hsotg: The HCD state structure for the DWC OTG controller.
2322 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
2324 void dwc2_host_put_tt_info(struct dwc2_hsotg
*hsotg
, struct dwc2_tt
*dwc_tt
)
2326 /* Model kfree and make put of NULL a no-op */
2330 WARN_ON(dwc_tt
->refcount
< 1);
2333 if (!dwc_tt
->refcount
) {
2334 dwc_tt
->usb_tt
->hcpriv
= NULL
;
2339 int dwc2_host_get_speed(struct dwc2_hsotg
*hsotg
, void *context
)
2341 struct urb
*urb
= context
;
2343 return urb
->dev
->speed
;
2346 static void dwc2_allocate_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
2349 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2352 bus
->bandwidth_allocated
+= bw
/ urb
->interval
;
2353 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2354 bus
->bandwidth_isoc_reqs
++;
2356 bus
->bandwidth_int_reqs
++;
2359 static void dwc2_free_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
2362 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2365 bus
->bandwidth_allocated
-= bw
/ urb
->interval
;
2366 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2367 bus
->bandwidth_isoc_reqs
--;
2369 bus
->bandwidth_int_reqs
--;
2373 * Sets the final status of an URB and returns it to the upper layer. Any
2374 * required cleanup of the URB is performed.
2376 * Must be called with interrupt disabled and spinlock held
2378 void dwc2_host_complete(struct dwc2_hsotg
*hsotg
, struct dwc2_qtd
*qtd
,
2385 dev_dbg(hsotg
->dev
, "## %s: qtd is NULL ##\n", __func__
);
2390 dev_dbg(hsotg
->dev
, "## %s: qtd->urb is NULL ##\n", __func__
);
2394 urb
= qtd
->urb
->priv
;
2396 dev_dbg(hsotg
->dev
, "## %s: urb->priv is NULL ##\n", __func__
);
2400 urb
->actual_length
= dwc2_hcd_urb_get_actual_length(qtd
->urb
);
2403 dev_vdbg(hsotg
->dev
,
2404 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2405 __func__
, urb
, usb_pipedevice(urb
->pipe
),
2406 usb_pipeendpoint(urb
->pipe
),
2407 usb_pipein(urb
->pipe
) ? "IN" : "OUT", status
,
2408 urb
->actual_length
);
2411 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2412 urb
->error_count
= dwc2_hcd_urb_get_error_count(qtd
->urb
);
2413 for (i
= 0; i
< urb
->number_of_packets
; ++i
) {
2414 urb
->iso_frame_desc
[i
].actual_length
=
2415 dwc2_hcd_urb_get_iso_desc_actual_length(
2417 urb
->iso_frame_desc
[i
].status
=
2418 dwc2_hcd_urb_get_iso_desc_status(qtd
->urb
, i
);
2422 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
&& dbg_perio()) {
2423 for (i
= 0; i
< urb
->number_of_packets
; i
++)
2424 dev_vdbg(hsotg
->dev
, " ISO Desc %d status %d\n",
2425 i
, urb
->iso_frame_desc
[i
].status
);
2428 urb
->status
= status
;
2430 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) &&
2431 urb
->actual_length
< urb
->transfer_buffer_length
)
2432 urb
->status
= -EREMOTEIO
;
2435 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
2436 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
2437 struct usb_host_endpoint
*ep
= urb
->ep
;
2440 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg
),
2441 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
2445 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg
), urb
);
2450 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg
), urb
, status
);
2454 * Work queue function for starting the HCD when A-Cable is connected
2456 static void dwc2_hcd_start_func(struct work_struct
*work
)
2458 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
2461 dev_dbg(hsotg
->dev
, "%s() %p\n", __func__
, hsotg
);
2462 dwc2_host_start(hsotg
);
2466 * Reset work queue function
2468 static void dwc2_hcd_reset_func(struct work_struct
*work
)
2470 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
2472 unsigned long flags
;
2475 dev_dbg(hsotg
->dev
, "USB RESET function called\n");
2477 spin_lock_irqsave(&hsotg
->lock
, flags
);
2479 hprt0
= dwc2_read_hprt0(hsotg
);
2480 hprt0
&= ~HPRT0_RST
;
2481 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
2482 hsotg
->flags
.b
.port_reset_change
= 1;
2484 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2488 * =========================================================================
2489 * Linux HC Driver Functions
2490 * =========================================================================
2494 * Initializes the DWC_otg controller and its root hub and prepares it for host
2495 * mode operation. Activates the root port. Returns 0 on success and a negative
2496 * error code on failure.
2498 static int _dwc2_hcd_start(struct usb_hcd
*hcd
)
2500 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2501 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2502 unsigned long flags
;
2504 dev_dbg(hsotg
->dev
, "DWC OTG HCD START\n");
2506 spin_lock_irqsave(&hsotg
->lock
, flags
);
2507 hsotg
->lx_state
= DWC2_L0
;
2508 hcd
->state
= HC_STATE_RUNNING
;
2509 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2511 if (dwc2_is_device_mode(hsotg
)) {
2512 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2513 return 0; /* why 0 ?? */
2516 dwc2_hcd_reinit(hsotg
);
2518 /* Initialize and connect root hub if one is not already attached */
2519 if (bus
->root_hub
) {
2520 dev_dbg(hsotg
->dev
, "DWC OTG HCD Has Root Hub\n");
2521 /* Inform the HUB driver to resume */
2522 usb_hcd_resume_root_hub(hcd
);
2525 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2530 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2533 static void _dwc2_hcd_stop(struct usb_hcd
*hcd
)
2535 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2536 unsigned long flags
;
2538 /* Turn off all host-specific interrupts */
2539 dwc2_disable_host_interrupts(hsotg
);
2541 /* Wait for interrupt processing to finish */
2542 synchronize_irq(hcd
->irq
);
2544 spin_lock_irqsave(&hsotg
->lock
, flags
);
2545 /* Ensure hcd is disconnected */
2546 dwc2_hcd_disconnect(hsotg
, true);
2547 dwc2_hcd_stop(hsotg
);
2548 hsotg
->lx_state
= DWC2_L3
;
2549 hcd
->state
= HC_STATE_HALT
;
2550 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2551 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2553 usleep_range(1000, 3000);
2556 static int _dwc2_hcd_suspend(struct usb_hcd
*hcd
)
2558 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2559 unsigned long flags
;
2563 spin_lock_irqsave(&hsotg
->lock
, flags
);
2565 if (hsotg
->lx_state
!= DWC2_L0
)
2568 if (!HCD_HW_ACCESSIBLE(hcd
))
2571 if (!hsotg
->core_params
->hibernation
)
2572 goto skip_power_saving
;
2575 * Drive USB suspend and disable port Power
2576 * if usb bus is not suspended.
2578 if (!hsotg
->bus_suspended
) {
2579 hprt0
= dwc2_read_hprt0(hsotg
);
2580 hprt0
|= HPRT0_SUSP
;
2581 hprt0
&= ~HPRT0_PWR
;
2582 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
2585 /* Enter hibernation */
2586 ret
= dwc2_enter_hibernation(hsotg
);
2588 if (ret
!= -ENOTSUPP
)
2590 "enter hibernation failed\n");
2591 goto skip_power_saving
;
2594 /* Ask phy to be suspended */
2595 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
2596 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2597 usb_phy_set_suspend(hsotg
->uphy
, true);
2598 spin_lock_irqsave(&hsotg
->lock
, flags
);
2601 /* After entering hibernation, hardware is no more accessible */
2602 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2605 hsotg
->lx_state
= DWC2_L2
;
2607 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2612 static int _dwc2_hcd_resume(struct usb_hcd
*hcd
)
2614 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2615 unsigned long flags
;
2618 spin_lock_irqsave(&hsotg
->lock
, flags
);
2620 if (hsotg
->lx_state
!= DWC2_L2
)
2623 if (!hsotg
->core_params
->hibernation
) {
2624 hsotg
->lx_state
= DWC2_L0
;
2629 * Set HW accessible bit before powering on the controller
2630 * since an interrupt may rise.
2632 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2635 * Enable power if not already done.
2636 * This must not be spinlocked since duration
2637 * of this call is unknown.
2639 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
2640 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2641 usb_phy_set_suspend(hsotg
->uphy
, false);
2642 spin_lock_irqsave(&hsotg
->lock
, flags
);
2645 /* Exit hibernation */
2646 ret
= dwc2_exit_hibernation(hsotg
, true);
2647 if (ret
&& (ret
!= -ENOTSUPP
))
2648 dev_err(hsotg
->dev
, "exit hibernation failed\n");
2650 hsotg
->lx_state
= DWC2_L0
;
2652 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2654 if (hsotg
->bus_suspended
) {
2655 spin_lock_irqsave(&hsotg
->lock
, flags
);
2656 hsotg
->flags
.b
.port_suspend_change
= 1;
2657 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2658 dwc2_port_resume(hsotg
);
2660 /* Wait for controller to correctly update D+/D- level */
2661 usleep_range(3000, 5000);
2664 * Clear Port Enable and Port Status changes.
2665 * Enable Port Power.
2667 dwc2_writel(HPRT0_PWR
| HPRT0_CONNDET
|
2668 HPRT0_ENACHG
, hsotg
->regs
+ HPRT0
);
2669 /* Wait for controller to detect Port Connect */
2670 usleep_range(5000, 7000);
2675 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2680 /* Returns the current frame number */
2681 static int _dwc2_hcd_get_frame_number(struct usb_hcd
*hcd
)
2683 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2685 return dwc2_hcd_get_frame_number(hsotg
);
2688 static void dwc2_dump_urb_info(struct usb_hcd
*hcd
, struct urb
*urb
,
2691 #ifdef VERBOSE_DEBUG
2692 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2696 dev_vdbg(hsotg
->dev
, "%s, urb %p\n", fn_name
, urb
);
2697 dev_vdbg(hsotg
->dev
, " Device address: %d\n",
2698 usb_pipedevice(urb
->pipe
));
2699 dev_vdbg(hsotg
->dev
, " Endpoint: %d, %s\n",
2700 usb_pipeendpoint(urb
->pipe
),
2701 usb_pipein(urb
->pipe
) ? "IN" : "OUT");
2703 switch (usb_pipetype(urb
->pipe
)) {
2705 pipetype
= "CONTROL";
2710 case PIPE_INTERRUPT
:
2711 pipetype
= "INTERRUPT";
2713 case PIPE_ISOCHRONOUS
:
2714 pipetype
= "ISOCHRONOUS";
2717 pipetype
= "UNKNOWN";
2721 dev_vdbg(hsotg
->dev
, " Endpoint type: %s %s (%s)\n", pipetype
,
2722 usb_urb_dir_in(urb
) ? "IN" : "OUT", usb_pipein(urb
->pipe
) ?
2725 switch (urb
->dev
->speed
) {
2726 case USB_SPEED_HIGH
:
2729 case USB_SPEED_FULL
:
2740 dev_vdbg(hsotg
->dev
, " Speed: %s\n", speed
);
2741 dev_vdbg(hsotg
->dev
, " Max packet size: %d\n",
2742 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
2743 dev_vdbg(hsotg
->dev
, " Data buffer length: %d\n",
2744 urb
->transfer_buffer_length
);
2745 dev_vdbg(hsotg
->dev
, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2746 urb
->transfer_buffer
, (unsigned long)urb
->transfer_dma
);
2747 dev_vdbg(hsotg
->dev
, " Setup buffer: %p, Setup DMA: %08lx\n",
2748 urb
->setup_packet
, (unsigned long)urb
->setup_dma
);
2749 dev_vdbg(hsotg
->dev
, " Interval: %d\n", urb
->interval
);
2751 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2754 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2755 dev_vdbg(hsotg
->dev
, " ISO Desc %d:\n", i
);
2756 dev_vdbg(hsotg
->dev
, " offset: %d, length %d\n",
2757 urb
->iso_frame_desc
[i
].offset
,
2758 urb
->iso_frame_desc
[i
].length
);
2765 * Starts processing a USB transfer request specified by a USB Request Block
2766 * (URB). mem_flags indicates the type of memory allocation to use while
2767 * processing this URB.
2769 static int _dwc2_hcd_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
,
2772 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2773 struct usb_host_endpoint
*ep
= urb
->ep
;
2774 struct dwc2_hcd_urb
*dwc2_urb
;
2777 int alloc_bandwidth
= 0;
2781 unsigned long flags
;
2783 bool qh_allocated
= false;
2784 struct dwc2_qtd
*qtd
;
2787 dev_vdbg(hsotg
->dev
, "DWC OTG HCD URB Enqueue\n");
2788 dwc2_dump_urb_info(hcd
, urb
, "urb_enqueue");
2794 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
2795 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
2796 spin_lock_irqsave(&hsotg
->lock
, flags
);
2797 if (!dwc2_hcd_is_bandwidth_allocated(hsotg
, ep
))
2798 alloc_bandwidth
= 1;
2799 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2802 switch (usb_pipetype(urb
->pipe
)) {
2804 ep_type
= USB_ENDPOINT_XFER_CONTROL
;
2806 case PIPE_ISOCHRONOUS
:
2807 ep_type
= USB_ENDPOINT_XFER_ISOC
;
2810 ep_type
= USB_ENDPOINT_XFER_BULK
;
2812 case PIPE_INTERRUPT
:
2813 ep_type
= USB_ENDPOINT_XFER_INT
;
2816 dev_warn(hsotg
->dev
, "Wrong ep type\n");
2819 dwc2_urb
= dwc2_hcd_urb_alloc(hsotg
, urb
->number_of_packets
,
2824 dwc2_hcd_urb_set_pipeinfo(hsotg
, dwc2_urb
, usb_pipedevice(urb
->pipe
),
2825 usb_pipeendpoint(urb
->pipe
), ep_type
,
2826 usb_pipein(urb
->pipe
),
2827 usb_maxpacket(urb
->dev
, urb
->pipe
,
2828 !(usb_pipein(urb
->pipe
))));
2830 buf
= urb
->transfer_buffer
;
2832 if (hcd
->self
.uses_dma
) {
2833 if (!buf
&& (urb
->transfer_dma
& 3)) {
2835 "%s: unaligned transfer with no transfer_buffer",
2842 if (!(urb
->transfer_flags
& URB_NO_INTERRUPT
))
2843 tflags
|= URB_GIVEBACK_ASAP
;
2844 if (urb
->transfer_flags
& URB_ZERO_PACKET
)
2845 tflags
|= URB_SEND_ZERO_PACKET
;
2847 dwc2_urb
->priv
= urb
;
2848 dwc2_urb
->buf
= buf
;
2849 dwc2_urb
->dma
= urb
->transfer_dma
;
2850 dwc2_urb
->length
= urb
->transfer_buffer_length
;
2851 dwc2_urb
->setup_packet
= urb
->setup_packet
;
2852 dwc2_urb
->setup_dma
= urb
->setup_dma
;
2853 dwc2_urb
->flags
= tflags
;
2854 dwc2_urb
->interval
= urb
->interval
;
2855 dwc2_urb
->status
= -EINPROGRESS
;
2857 for (i
= 0; i
< urb
->number_of_packets
; ++i
)
2858 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb
, i
,
2859 urb
->iso_frame_desc
[i
].offset
,
2860 urb
->iso_frame_desc
[i
].length
);
2862 urb
->hcpriv
= dwc2_urb
;
2863 qh
= (struct dwc2_qh
*) ep
->hcpriv
;
2864 /* Create QH for the endpoint if it doesn't exist */
2866 qh
= dwc2_hcd_qh_create(hsotg
, dwc2_urb
, mem_flags
);
2872 qh_allocated
= true;
2875 qtd
= kzalloc(sizeof(*qtd
), mem_flags
);
2881 spin_lock_irqsave(&hsotg
->lock
, flags
);
2882 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
2886 retval
= dwc2_hcd_urb_enqueue(hsotg
, dwc2_urb
, qh
, qtd
);
2890 if (alloc_bandwidth
) {
2891 dwc2_allocate_bus_bandwidth(hcd
,
2892 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
2896 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2901 dwc2_urb
->priv
= NULL
;
2902 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
2903 if (qh_allocated
&& qh
->channel
&& qh
->channel
->qh
== qh
)
2904 qh
->channel
->qh
= NULL
;
2906 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2911 struct dwc2_qtd
*qtd2
, *qtd2_tmp
;
2914 dwc2_hcd_qh_unlink(hsotg
, qh
);
2915 /* Free each QTD in the QH's QTD list */
2916 list_for_each_entry_safe(qtd2
, qtd2_tmp
, &qh
->qtd_list
,
2918 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd2
, qh
);
2919 dwc2_hcd_qh_free(hsotg
, qh
);
2928 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2930 static int _dwc2_hcd_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
,
2933 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2935 unsigned long flags
;
2937 dev_dbg(hsotg
->dev
, "DWC OTG HCD URB Dequeue\n");
2938 dwc2_dump_urb_info(hcd
, urb
, "urb_dequeue");
2940 spin_lock_irqsave(&hsotg
->lock
, flags
);
2942 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
2947 dev_dbg(hsotg
->dev
, "## urb->hcpriv is NULL ##\n");
2951 rc
= dwc2_hcd_urb_dequeue(hsotg
, urb
->hcpriv
);
2953 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
2958 /* Higher layer software sets URB status */
2959 spin_unlock(&hsotg
->lock
);
2960 usb_hcd_giveback_urb(hcd
, urb
, status
);
2961 spin_lock(&hsotg
->lock
);
2963 dev_dbg(hsotg
->dev
, "Called usb_hcd_giveback_urb()\n");
2964 dev_dbg(hsotg
->dev
, " urb->status = %d\n", urb
->status
);
2966 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2972 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2973 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2974 * must already be dequeued.
2976 static void _dwc2_hcd_endpoint_disable(struct usb_hcd
*hcd
,
2977 struct usb_host_endpoint
*ep
)
2979 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2982 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2983 ep
->desc
.bEndpointAddress
, ep
->hcpriv
);
2984 dwc2_hcd_endpoint_disable(hsotg
, ep
, 250);
2988 * Resets endpoint specific parameter values, in current version used to reset
2989 * the data toggle (as a WA). This function can be called from usb_clear_halt
2992 static void _dwc2_hcd_endpoint_reset(struct usb_hcd
*hcd
,
2993 struct usb_host_endpoint
*ep
)
2995 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2996 unsigned long flags
;
2999 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
3000 ep
->desc
.bEndpointAddress
);
3002 spin_lock_irqsave(&hsotg
->lock
, flags
);
3003 dwc2_hcd_endpoint_reset(hsotg
, ep
);
3004 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3008 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
3009 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
3012 * This function is called by the USB core when an interrupt occurs
3014 static irqreturn_t
_dwc2_hcd_irq(struct usb_hcd
*hcd
)
3016 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
3018 return dwc2_handle_hcd_intr(hsotg
);
3022 * Creates Status Change bitmap for the root hub and root port. The bitmap is
3023 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
3024 * is the status change indicator for the single root port. Returns 1 if either
3025 * change indicator is 1, otherwise returns 0.
3027 static int _dwc2_hcd_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3029 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
3031 buf
[0] = dwc2_hcd_is_status_changed(hsotg
, 1) << 1;
3035 /* Handles hub class-specific requests */
3036 static int _dwc2_hcd_hub_control(struct usb_hcd
*hcd
, u16 typereq
, u16 wvalue
,
3037 u16 windex
, char *buf
, u16 wlength
)
3039 int retval
= dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd
), typereq
,
3040 wvalue
, windex
, buf
, wlength
);
3044 /* Handles hub TT buffer clear completions */
3045 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd
*hcd
,
3046 struct usb_host_endpoint
*ep
)
3048 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
3050 unsigned long flags
;
3056 spin_lock_irqsave(&hsotg
->lock
, flags
);
3057 qh
->tt_buffer_dirty
= 0;
3059 if (hsotg
->flags
.b
.port_connect_status
)
3060 dwc2_hcd_queue_transactions(hsotg
, DWC2_TRANSACTION_ALL
);
3062 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3065 static struct hc_driver dwc2_hc_driver
= {
3066 .description
= "dwc2_hsotg",
3067 .product_desc
= "DWC OTG Controller",
3068 .hcd_priv_size
= sizeof(struct wrapper_priv_data
),
3070 .irq
= _dwc2_hcd_irq
,
3071 .flags
= HCD_MEMORY
| HCD_USB2
| HCD_BH
,
3073 .start
= _dwc2_hcd_start
,
3074 .stop
= _dwc2_hcd_stop
,
3075 .urb_enqueue
= _dwc2_hcd_urb_enqueue
,
3076 .urb_dequeue
= _dwc2_hcd_urb_dequeue
,
3077 .endpoint_disable
= _dwc2_hcd_endpoint_disable
,
3078 .endpoint_reset
= _dwc2_hcd_endpoint_reset
,
3079 .get_frame_number
= _dwc2_hcd_get_frame_number
,
3081 .hub_status_data
= _dwc2_hcd_hub_status_data
,
3082 .hub_control
= _dwc2_hcd_hub_control
,
3083 .clear_tt_buffer_complete
= _dwc2_hcd_clear_tt_buffer_complete
,
3085 .bus_suspend
= _dwc2_hcd_suspend
,
3086 .bus_resume
= _dwc2_hcd_resume
,
3088 .map_urb_for_dma
= dwc2_map_urb_for_dma
,
3089 .unmap_urb_for_dma
= dwc2_unmap_urb_for_dma
,
3093 * Frees secondary storage associated with the dwc2_hsotg structure contained
3094 * in the struct usb_hcd field
3096 static void dwc2_hcd_free(struct dwc2_hsotg
*hsotg
)
3102 dev_dbg(hsotg
->dev
, "DWC OTG HCD FREE\n");
3104 /* Free memory for QH/QTD lists */
3105 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_inactive
);
3106 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_active
);
3107 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_inactive
);
3108 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_ready
);
3109 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_assigned
);
3110 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_queued
);
3112 /* Free memory for the host channels */
3113 for (i
= 0; i
< MAX_EPS_CHANNELS
; i
++) {
3114 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
3117 dev_dbg(hsotg
->dev
, "HCD Free channel #%i, chan=%p\n",
3119 hsotg
->hc_ptr_array
[i
] = NULL
;
3124 if (hsotg
->core_params
->dma_enable
> 0) {
3125 if (hsotg
->status_buf
) {
3126 dma_free_coherent(hsotg
->dev
, DWC2_HCD_STATUS_BUF_SIZE
,
3128 hsotg
->status_buf_dma
);
3129 hsotg
->status_buf
= NULL
;
3132 kfree(hsotg
->status_buf
);
3133 hsotg
->status_buf
= NULL
;
3136 ahbcfg
= dwc2_readl(hsotg
->regs
+ GAHBCFG
);
3138 /* Disable all interrupts */
3139 ahbcfg
&= ~GAHBCFG_GLBL_INTR_EN
;
3140 dwc2_writel(ahbcfg
, hsotg
->regs
+ GAHBCFG
);
3141 dwc2_writel(0, hsotg
->regs
+ GINTMSK
);
3143 if (hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_3_00a
) {
3144 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
3145 dctl
|= DCTL_SFTDISCON
;
3146 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
3149 if (hsotg
->wq_otg
) {
3150 if (!cancel_work_sync(&hsotg
->wf_otg
))
3151 flush_workqueue(hsotg
->wq_otg
);
3152 destroy_workqueue(hsotg
->wq_otg
);
3155 del_timer(&hsotg
->wkp_timer
);
3158 static void dwc2_hcd_release(struct dwc2_hsotg
*hsotg
)
3160 /* Turn off all host-specific interrupts */
3161 dwc2_disable_host_interrupts(hsotg
);
3163 dwc2_hcd_free(hsotg
);
3167 * Initializes the HCD. This function allocates memory for and initializes the
3168 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
3169 * USB bus with the core and calls the hc_driver->start() function. It returns
3170 * a negative error on failure.
3172 int dwc2_hcd_init(struct dwc2_hsotg
*hsotg
, int irq
)
3174 struct usb_hcd
*hcd
;
3175 struct dwc2_host_chan
*channel
;
3177 int i
, num_channels
;
3183 dev_dbg(hsotg
->dev
, "DWC OTG HCD INIT\n");
3187 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
3188 dev_dbg(hsotg
->dev
, "hcfg=%08x\n", hcfg
);
3190 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3191 hsotg
->frame_num_array
= kzalloc(sizeof(*hsotg
->frame_num_array
) *
3192 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
3193 if (!hsotg
->frame_num_array
)
3195 hsotg
->last_frame_num_array
= kzalloc(
3196 sizeof(*hsotg
->last_frame_num_array
) *
3197 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
3198 if (!hsotg
->last_frame_num_array
)
3201 hsotg
->last_frame_num
= HFNUM_MAX_FRNUM
;
3203 /* Check if the bus driver or platform code has setup a dma_mask */
3204 if (hsotg
->core_params
->dma_enable
> 0 &&
3205 hsotg
->dev
->dma_mask
== NULL
) {
3206 dev_warn(hsotg
->dev
,
3207 "dma_mask not set, disabling DMA\n");
3208 hsotg
->core_params
->dma_enable
= 0;
3209 hsotg
->core_params
->dma_desc_enable
= 0;
3212 /* Set device flags indicating whether the HCD supports DMA */
3213 if (hsotg
->core_params
->dma_enable
> 0) {
3214 if (dma_set_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
3215 dev_warn(hsotg
->dev
, "can't set DMA mask\n");
3216 if (dma_set_coherent_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
3217 dev_warn(hsotg
->dev
, "can't set coherent DMA mask\n");
3220 hcd
= usb_create_hcd(&dwc2_hc_driver
, hsotg
->dev
, dev_name(hsotg
->dev
));
3224 if (hsotg
->core_params
->dma_enable
<= 0)
3225 hcd
->self
.uses_dma
= 0;
3229 ((struct wrapper_priv_data
*) &hcd
->hcd_priv
)->hsotg
= hsotg
;
3233 * Disable the global interrupt until all the interrupt handlers are
3236 dwc2_disable_global_interrupts(hsotg
);
3238 /* Initialize the DWC_otg core, and select the Phy type */
3239 retval
= dwc2_core_init(hsotg
, true);
3243 /* Create new workqueue and init work */
3245 hsotg
->wq_otg
= create_singlethread_workqueue("dwc2");
3246 if (!hsotg
->wq_otg
) {
3247 dev_err(hsotg
->dev
, "Failed to create workqueue\n");
3250 INIT_WORK(&hsotg
->wf_otg
, dwc2_conn_id_status_change
);
3252 setup_timer(&hsotg
->wkp_timer
, dwc2_wakeup_detected
,
3253 (unsigned long)hsotg
);
3255 /* Initialize the non-periodic schedule */
3256 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_inactive
);
3257 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_active
);
3259 /* Initialize the periodic schedule */
3260 INIT_LIST_HEAD(&hsotg
->periodic_sched_inactive
);
3261 INIT_LIST_HEAD(&hsotg
->periodic_sched_ready
);
3262 INIT_LIST_HEAD(&hsotg
->periodic_sched_assigned
);
3263 INIT_LIST_HEAD(&hsotg
->periodic_sched_queued
);
3265 INIT_LIST_HEAD(&hsotg
->split_order
);
3268 * Create a host channel descriptor for each host channel implemented
3269 * in the controller. Initialize the channel descriptor array.
3271 INIT_LIST_HEAD(&hsotg
->free_hc_list
);
3272 num_channels
= hsotg
->core_params
->host_channels
;
3273 memset(&hsotg
->hc_ptr_array
[0], 0, sizeof(hsotg
->hc_ptr_array
));
3275 for (i
= 0; i
< num_channels
; i
++) {
3276 channel
= kzalloc(sizeof(*channel
), GFP_KERNEL
);
3277 if (channel
== NULL
)
3279 channel
->hc_num
= i
;
3280 INIT_LIST_HEAD(&channel
->split_order_list_entry
);
3281 hsotg
->hc_ptr_array
[i
] = channel
;
3284 /* Initialize hsotg start work */
3285 INIT_DELAYED_WORK(&hsotg
->start_work
, dwc2_hcd_start_func
);
3287 /* Initialize port reset work */
3288 INIT_DELAYED_WORK(&hsotg
->reset_work
, dwc2_hcd_reset_func
);
3291 * Allocate space for storing data on status transactions. Normally no
3292 * data is sent, but this space acts as a bit bucket. This must be
3293 * done after usb_add_hcd since that function allocates the DMA buffer
3296 if (hsotg
->core_params
->dma_enable
> 0)
3297 hsotg
->status_buf
= dma_alloc_coherent(hsotg
->dev
,
3298 DWC2_HCD_STATUS_BUF_SIZE
,
3299 &hsotg
->status_buf_dma
, GFP_KERNEL
);
3301 hsotg
->status_buf
= kzalloc(DWC2_HCD_STATUS_BUF_SIZE
,
3304 if (!hsotg
->status_buf
)
3308 * Create kmem caches to handle descriptor buffers in descriptor
3310 * Alignment must be set to 512 bytes.
3312 if (hsotg
->core_params
->dma_desc_enable
||
3313 hsotg
->core_params
->dma_desc_fs_enable
) {
3314 hsotg
->desc_gen_cache
= kmem_cache_create("dwc2-gen-desc",
3315 sizeof(struct dwc2_hcd_dma_desc
) *
3316 MAX_DMA_DESC_NUM_GENERIC
, 512, SLAB_CACHE_DMA
,
3318 if (!hsotg
->desc_gen_cache
) {
3320 "unable to create dwc2 generic desc cache\n");
3323 * Disable descriptor dma mode since it will not be
3326 hsotg
->core_params
->dma_desc_enable
= 0;
3327 hsotg
->core_params
->dma_desc_fs_enable
= 0;
3330 hsotg
->desc_hsisoc_cache
= kmem_cache_create("dwc2-hsisoc-desc",
3331 sizeof(struct dwc2_hcd_dma_desc
) *
3332 MAX_DMA_DESC_NUM_HS_ISOC
, 512, 0, NULL
);
3333 if (!hsotg
->desc_hsisoc_cache
) {
3335 "unable to create dwc2 hs isoc desc cache\n");
3337 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3340 * Disable descriptor dma mode since it will not be
3343 hsotg
->core_params
->dma_desc_enable
= 0;
3344 hsotg
->core_params
->dma_desc_fs_enable
= 0;
3348 hsotg
->otg_port
= 1;
3349 hsotg
->frame_list
= NULL
;
3350 hsotg
->frame_list_dma
= 0;
3351 hsotg
->periodic_qh_count
= 0;
3353 /* Initiate lx_state to L3 disconnected state */
3354 hsotg
->lx_state
= DWC2_L3
;
3356 hcd
->self
.otg_port
= hsotg
->otg_port
;
3358 /* Don't support SG list at this point */
3359 hcd
->self
.sg_tablesize
= 0;
3361 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3362 otg_set_host(hsotg
->uphy
->otg
, &hcd
->self
);
3365 * Finish generic HCD initialization and start the HCD. This function
3366 * allocates the DMA buffer pool, registers the USB bus, requests the
3367 * IRQ line, and calls hcd_start method.
3369 retval
= usb_add_hcd(hcd
, irq
, IRQF_SHARED
);
3373 device_wakeup_enable(hcd
->self
.controller
);
3375 dwc2_hcd_dump_state(hsotg
);
3377 dwc2_enable_global_interrupts(hsotg
);
3382 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3383 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
3385 dwc2_hcd_release(hsotg
);
3389 kfree(hsotg
->core_params
);
3391 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3392 kfree(hsotg
->last_frame_num_array
);
3393 kfree(hsotg
->frame_num_array
);
3396 dev_err(hsotg
->dev
, "%s() FAILED, returning %d\n", __func__
, retval
);
3402 * Frees memory and resources associated with the HCD and deregisters the bus.
3404 void dwc2_hcd_remove(struct dwc2_hsotg
*hsotg
)
3406 struct usb_hcd
*hcd
;
3408 dev_dbg(hsotg
->dev
, "DWC OTG HCD REMOVE\n");
3410 hcd
= dwc2_hsotg_to_hcd(hsotg
);
3411 dev_dbg(hsotg
->dev
, "hsotg->hcd = %p\n", hcd
);
3414 dev_dbg(hsotg
->dev
, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3419 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3420 otg_set_host(hsotg
->uphy
->otg
, NULL
);
3422 usb_remove_hcd(hcd
);
3425 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3426 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
3428 dwc2_hcd_release(hsotg
);
3431 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3432 kfree(hsotg
->last_frame_num_array
);
3433 kfree(hsotg
->frame_num_array
);
3438 * dwc2_backup_host_registers() - Backup controller host registers.
3439 * When suspending usb bus, registers needs to be backuped
3440 * if controller power is disabled once suspended.
3442 * @hsotg: Programming view of the DWC_otg controller
3444 int dwc2_backup_host_registers(struct dwc2_hsotg
*hsotg
)
3446 struct dwc2_hregs_backup
*hr
;
3449 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
3451 /* Backup Host regs */
3452 hr
= &hsotg
->hr_backup
;
3453 hr
->hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
3454 hr
->haintmsk
= dwc2_readl(hsotg
->regs
+ HAINTMSK
);
3455 for (i
= 0; i
< hsotg
->core_params
->host_channels
; ++i
)
3456 hr
->hcintmsk
[i
] = dwc2_readl(hsotg
->regs
+ HCINTMSK(i
));
3458 hr
->hprt0
= dwc2_read_hprt0(hsotg
);
3459 hr
->hfir
= dwc2_readl(hsotg
->regs
+ HFIR
);
3466 * dwc2_restore_host_registers() - Restore controller host registers.
3467 * When resuming usb bus, device registers needs to be restored
3468 * if controller power were disabled.
3470 * @hsotg: Programming view of the DWC_otg controller
3472 int dwc2_restore_host_registers(struct dwc2_hsotg
*hsotg
)
3474 struct dwc2_hregs_backup
*hr
;
3477 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
3479 /* Restore host regs */
3480 hr
= &hsotg
->hr_backup
;
3482 dev_err(hsotg
->dev
, "%s: no host registers to restore\n",
3488 dwc2_writel(hr
->hcfg
, hsotg
->regs
+ HCFG
);
3489 dwc2_writel(hr
->haintmsk
, hsotg
->regs
+ HAINTMSK
);
3491 for (i
= 0; i
< hsotg
->core_params
->host_channels
; ++i
)
3492 dwc2_writel(hr
->hcintmsk
[i
], hsotg
->regs
+ HCINTMSK(i
));
3494 dwc2_writel(hr
->hprt0
, hsotg
->regs
+ HPRT0
);
3495 dwc2_writel(hr
->hfir
, hsotg
->regs
+ HFIR
);
3496 hsotg
->frame_number
= 0;