drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_hi6220 = {
  58         .otg_cap                        = 2,    /* No HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .dma_desc_fs_enable             = 0,
  63         .speed                          = 0,    /* High Speed */
  64         .enable_dynamic_fifo            = 1,
  65         .en_multiple_tx_fifo            = 1,
  66         .host_rx_fifo_size              = 512,
  67         .host_nperio_tx_fifo_size       = 512,
  68         .host_perio_tx_fifo_size        = 512,
  69         .max_transfer_size              = 65535,
  70         .max_packet_count               = 511,
  71         .host_channels                  = 16,
  72         .phy_type                       = 1,    /* UTMI */
  73         .phy_utmi_width                 = 8,
  74         .phy_ulpi_ddr                   = 0,    /* Single */
  75         .phy_ulpi_ext_vbus              = 0,
  76         .i2c_enable                     = 0,
  77         .ulpi_fs_ls                     = 0,
  78         .host_support_fs_ls_low_power   = 0,
  79         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  80         .ts_dline                       = 0,
  81         .reload_ctl                     = 0,
  82         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
  83                                           GAHBCFG_HBSTLEN_SHIFT,
  84         .uframe_sched                   = 0,
  85         .external_id_pin_ctl            = -1,
  86         .hibernation                    = -1,
  87 };
  88
  89 static const struct dwc2_core_params params_bcm2835 = {
  90         .otg_cap                        = 0,    /* HNP/SRP capable */
  91         .otg_ver                        = 0,    /* 1.3 */
  92         .dma_enable                     = 1,
  93         .dma_desc_enable                = 0,
  94         .dma_desc_fs_enable             = 0,
  95         .speed                          = 0,    /* High Speed */
  96         .enable_dynamic_fifo            = 1,
  97         .en_multiple_tx_fifo            = 1,
  98         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  99         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
 100         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
 101         .max_transfer_size              = 65535,
 102         .max_packet_count               = 511,
 103         .host_channels                  = 8,
 104         .phy_type                       = 1,    /* UTMI */
 105         .phy_utmi_width                 = 8,    /* 8 bits */
 106         .phy_ulpi_ddr                   = 0,    /* Single */
 107         .phy_ulpi_ext_vbus              = 0,
 108         .i2c_enable                     = 0,
 109         .ulpi_fs_ls                     = 0,
 110         .host_support_fs_ls_low_power   = 0,
 111         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
 112         .ts_dline                       = 0,
 113         .reload_ctl                     = 0,
 114         .ahbcfg                         = 0x10,
 115         .uframe_sched                   = 0,
 116         .external_id_pin_ctl            = -1,
 117         .hibernation                    = -1,
 118 };
 119
 120 static const struct dwc2_core_params params_rk3066 = {
 121         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 122         .otg_ver                        = -1,
 123         .dma_enable                     = -1,
 124         .dma_desc_enable                = 0,
 125         .dma_desc_fs_enable             = 0,
 126         .speed                          = -1,
 127         .enable_dynamic_fifo            = 1,
 128         .en_multiple_tx_fifo            = -1,
 129         .host_rx_fifo_size              = 520,  /* 520 DWORDs */
 130         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 131         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 132         .max_transfer_size              = 65535,
 133         .max_packet_count               = -1,
 134         .host_channels                  = -1,
 135         .phy_type                       = -1,
 136         .phy_utmi_width                 = -1,
 137         .phy_ulpi_ddr                   = -1,
 138         .phy_ulpi_ext_vbus              = -1,
 139         .i2c_enable                     = -1,
 140         .ulpi_fs_ls                     = -1,
 141         .host_support_fs_ls_low_power   = -1,
 142         .host_ls_low_power_phy_clk      = -1,
 143         .ts_dline                       = -1,
 144         .reload_ctl                     = -1,
 145         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 146                                           GAHBCFG_HBSTLEN_SHIFT,
 147         .uframe_sched                   = -1,
 148         .external_id_pin_ctl            = -1,
 149         .hibernation                    = -1,
 150 };
 151
 152 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 153 {
 154         struct platform_device *pdev = to_platform_device(hsotg->dev);
 155         int ret;
 156
 157         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 158                                     hsotg->supplies);
 159         if (ret)
 160                 return ret;
 161
 162         if (hsotg->clk) {
 163                 ret = clk_prepare_enable(hsotg->clk);
 164                 if (ret)
 165                         return ret;
 166         }
 167
 168         if (hsotg->uphy)
 169                 ret = usb_phy_init(hsotg->uphy);
 170         else if (hsotg->plat && hsotg->plat->phy_init)
 171                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 172         else {
 173                 ret = phy_power_on(hsotg->phy);
 174                 if (ret == 0)
 175                         ret = phy_init(hsotg->phy);
 176         }
 177
 178         return ret;
 179 }
 180
 181 /**
 182  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 183  * @hsotg: The driver state
 184  *
 185  * A wrapper for platform code responsible for controlling
 186  * low-level USB platform resources (phy, clock, regulators)
 187  */
 188 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 189 {
 190         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 191
 192         if (ret == 0)
 193                 hsotg->ll_hw_enabled = true;
 194         return ret;
 195 }
 196
 197 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 198 {
 199         struct platform_device *pdev = to_platform_device(hsotg->dev);
 200         int ret = 0;
 201
 202         if (hsotg->uphy)
 203                 usb_phy_shutdown(hsotg->uphy);
 204         else if (hsotg->plat && hsotg->plat->phy_exit)
 205                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 206         else {
 207                 ret = phy_exit(hsotg->phy);
 208                 if (ret == 0)
 209                         ret = phy_power_off(hsotg->phy);
 210         }
 211         if (ret)
 212                 return ret;
 213
 214         if (hsotg->clk)
 215                 clk_disable_unprepare(hsotg->clk);
 216
 217         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 218                                      hsotg->supplies);
 219
 220         return ret;
 221 }
 222
 223 /**
 224  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 225  * @hsotg: The driver state
 226  *
 227  * A wrapper for platform code responsible for controlling
 228  * low-level USB platform resources (phy, clock, regulators)
 229  */
 230 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 231 {
 232         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 233
 234         if (ret == 0)
 235                 hsotg->ll_hw_enabled = false;
 236         return ret;
 237 }
 238
 239 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 240 {
 241         int i, ret;
 242
 243         /* Set default UTMI width */
 244         hsotg->phyif = GUSBCFG_PHYIF16;
 245
 246         /*
 247          * Attempt to find a generic PHY, then look for an old style
 248          * USB PHY and then fall back to pdata
 249          */
 250         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 251         if (IS_ERR(hsotg->phy)) {
 252                 ret = PTR_ERR(hsotg->phy);
 253                 switch (ret) {
 254                 case -ENODEV:
 255                 case -ENOSYS:
 256                         hsotg->phy = NULL;
 257                         break;
 258                 case -EPROBE_DEFER:
 259                         return ret;
 260                 default:
 261                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 262                         return ret;
 263                 }
 264         }
 265
 266         if (!hsotg->phy) {
 267                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 268                 if (IS_ERR(hsotg->uphy)) {
 269                         ret = PTR_ERR(hsotg->uphy);
 270                         switch (ret) {
 271                         case -ENODEV:
 272                         case -ENXIO:
 273                                 hsotg->uphy = NULL;
 274                                 break;
 275                         case -EPROBE_DEFER:
 276                                 return ret;
 277                         default:
 278                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 279                                         ret);
 280                                 return ret;
 281                         }
 282                 }
 283         }
 284
 285         hsotg->plat = dev_get_platdata(hsotg->dev);
 286
 287         if (hsotg->phy) {
 288                 /*
 289                  * If using the generic PHY framework, check if the PHY bus
 290                  * width is 8-bit and set the phyif appropriately.
 291                  */
 292                 if (phy_get_bus_width(hsotg->phy) == 8)
 293                         hsotg->phyif = GUSBCFG_PHYIF8;
 294         }
 295
 296         /* Clock */
 297         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 298         if (IS_ERR(hsotg->clk)) {
 299                 hsotg->clk = NULL;
 300                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 301         }
 302
 303         /* Regulators */
 304         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 305                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 306
 307         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 308                                       hsotg->supplies);
 309         if (ret) {
 310                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 311                 return ret;
 312         }
 313         return 0;
 314 }
 315
 316 /**
 317  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 318  * DWC_otg driver
 319  *
 320  * @dev: Platform device
 321  *
 322  * This routine is called, for example, when the rmmod command is executed. The
 323  * device may or may not be electrically present. If it is present, the driver
 324  * stops device processing. Any resources used on behalf of this device are
 325  * freed.
 326  */
 327 static int dwc2_driver_remove(struct platform_device *dev)
 328 {
 329         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 330
 331         dwc2_debugfs_exit(hsotg);
 332         if (hsotg->hcd_enabled)
 333                 dwc2_hcd_remove(hsotg);
 334         if (hsotg->gadget_enabled)
 335                 dwc2_hsotg_remove(hsotg);
 336
 337         if (hsotg->ll_hw_enabled)
 338                 dwc2_lowlevel_hw_disable(hsotg);
 339
 340         return 0;
 341 }
 342
 343 static const struct of_device_id dwc2_of_match_table[] = {
 344         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 345         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
 346         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 347         { .compatible = "snps,dwc2", .data = NULL },
 348         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 349         {},
 350 };
 351 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 352
 353 /**
 354  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 355  * driver
 356  *
 357  * @dev: Platform device
 358  *
 359  * This routine creates the driver components required to control the device
 360  * (core, HCD, and PCD) and initializes the device. The driver components are
 361  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 362  * in the device private data. This allows the driver to access the dwc2_hsotg
 363  * structure on subsequent calls to driver methods for this device.
 364  */
 365 static int dwc2_driver_probe(struct platform_device *dev)
 366 {
 367         const struct of_device_id *match;
 368         const struct dwc2_core_params *params;
 369         struct dwc2_core_params defparams;
 370         struct dwc2_hsotg *hsotg;
 371         struct resource *res;
 372         int retval;
 373         int irq;
 374
 375         match = of_match_device(dwc2_of_match_table, &dev->dev);
 376         if (match && match->data) {
 377                 params = match->data;
 378         } else {
 379                 /* Default all params to autodetect */
 380                 dwc2_set_all_params(&defparams, -1);
 381                 params = &defparams;
 382
 383                 /*
 384                  * Disable descriptor dma mode by default as the HW can support
 385                  * it, but does not support it for SPLIT transactions.
 386                  * Disable it for FS devices as well.
 387                  */
 388                 defparams.dma_desc_enable = 0;
 389                 defparams.dma_desc_fs_enable = 0;
 390         }
 391
 392         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 393         if (!hsotg)
 394                 return -ENOMEM;
 395
 396         hsotg->dev = &dev->dev;
 397
 398         /*
 399          * Use reasonable defaults so platforms don't have to provide these.
 400          */
 401         if (!dev->dev.dma_mask)
 402                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 403         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 404         if (retval)
 405                 return retval;
 406
 407         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 408         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 409         if (IS_ERR(hsotg->regs))
 410                 return PTR_ERR(hsotg->regs);
 411
 412         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 413                 (unsigned long)res->start, hsotg->regs);
 414
 415         hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
 416         if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
 417                         hsotg->dr_mode != USB_DR_MODE_HOST) {
 418                 hsotg->dr_mode = USB_DR_MODE_HOST;
 419                 dev_warn(hsotg->dev,
 420                         "Configuration mismatch. Forcing host mode\n");
 421         } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
 422                         hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 423                 hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
 424                 dev_warn(hsotg->dev,
 425                         "Configuration mismatch. Forcing peripheral mode\n");
 426         }
 427
 428         retval = dwc2_lowlevel_hw_init(hsotg);
 429         if (retval)
 430                 return retval;
 431
 432         spin_lock_init(&hsotg->lock);
 433
 434         hsotg->core_params = devm_kzalloc(&dev->dev,
 435                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 436         if (!hsotg->core_params)
 437                 return -ENOMEM;
 438
 439         dwc2_set_all_params(hsotg->core_params, -1);
 440
 441         irq = platform_get_irq(dev, 0);
 442         if (irq < 0) {
 443                 dev_err(&dev->dev, "missing IRQ resource\n");
 444                 return irq;
 445         }
 446
 447         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 448                 irq);
 449         retval = devm_request_irq(hsotg->dev, irq,
 450                                   dwc2_handle_common_intr, IRQF_SHARED,
 451                                   dev_name(hsotg->dev), hsotg);
 452         if (retval)
 453                 return retval;
 454
 455         retval = dwc2_lowlevel_hw_enable(hsotg);
 456         if (retval)
 457                 return retval;
 458
 459         /*
 460          * Reset before dwc2_get_hwparams() then it could get power-on real
 461          * reset value form registers.
 462          */
 463         dwc2_core_reset_and_force_dr_mode(hsotg);
 464
 465         /* Detect config values from hardware */
 466         retval = dwc2_get_hwparams(hsotg);
 467         if (retval)
 468                 goto error;
 469
 470         /* Validate parameter values */
 471         dwc2_set_parameters(hsotg, params);
 472
 473         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 474                 retval = dwc2_gadget_init(hsotg, irq);
 475                 if (retval)
 476                         goto error;
 477                 hsotg->gadget_enabled = 1;
 478         }
 479
 480         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 481                 retval = dwc2_hcd_init(hsotg, irq);
 482                 if (retval) {
 483                         if (hsotg->gadget_enabled)
 484                                 dwc2_hsotg_remove(hsotg);
 485                         goto error;
 486                 }
 487                 hsotg->hcd_enabled = 1;
 488         }
 489
 490         platform_set_drvdata(dev, hsotg);
 491
 492         dwc2_debugfs_init(hsotg);
 493
 494         /* Gadget code manages lowlevel hw on its own */
 495         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 496                 dwc2_lowlevel_hw_disable(hsotg);
 497
 498         return 0;
 499
 500 error:
 501         dwc2_lowlevel_hw_disable(hsotg);
 502         return retval;
 503 }
 504
 505 static int __maybe_unused dwc2_suspend(struct device *dev)
 506 {
 507         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 508         int ret = 0;
 509
 510         if (dwc2_is_device_mode(dwc2))
 511                 dwc2_hsotg_suspend(dwc2);
 512
 513         if (dwc2->ll_hw_enabled)
 514                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 515
 516         return ret;
 517 }
 518
 519 static int __maybe_unused dwc2_resume(struct device *dev)
 520 {
 521         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 522         int ret = 0;
 523
 524         if (dwc2->ll_hw_enabled) {
 525                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 526                 if (ret)
 527                         return ret;
 528         }
 529
 530         if (dwc2_is_device_mode(dwc2))
 531                 ret = dwc2_hsotg_resume(dwc2);
 532
 533         return ret;
 534 }
 535
 536 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 537         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 538 };
 539
 540 static struct platform_driver dwc2_platform_driver = {
 541         .driver = {
 542                 .name = dwc2_driver_name,
 543                 .of_match_table = dwc2_of_match_table,
 544                 .pm = &dwc2_dev_pm_ops,
 545         },
 546         .probe = dwc2_driver_probe,
 547         .remove = dwc2_driver_remove,
 548 };
 549
 550 module_platform_driver(dwc2_platform_driver);
 551
 552 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 553 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 554 MODULE_LICENSE("Dual BSD/GPL");