2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dwc3_trace(trace_dwc3_gadget
,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8
*index
)
159 if (*index
== (DWC3_TRB_NUM
- 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
165 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
168 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
170 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
173 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
176 struct dwc3
*dwc
= dep
->dwc
;
182 dwc3_ep_inc_deq(dep
);
183 } while(++i
< req
->request
.num_mapped_sgs
);
184 req
->started
= false;
186 list_del(&req
->list
);
189 if (req
->request
.status
== -EINPROGRESS
)
190 req
->request
.status
= status
;
192 if (dwc
->ep0_bounced
&& dep
->number
== 0)
193 dwc
->ep0_bounced
= false;
195 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
198 trace_dwc3_gadget_giveback(req
);
200 spin_unlock(&dwc
->lock
);
201 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
202 spin_lock(&dwc
->lock
);
205 pm_runtime_put(dwc
->dev
);
208 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
215 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
216 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
219 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
220 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
221 status
= DWC3_DGCMD_STATUS(reg
);
233 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
238 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
241 struct dwc3_gadget_ep_cmd_params
*params
)
243 struct dwc3
*dwc
= dep
->dwc
;
252 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
253 * we're issuing an endpoint command, we must check if
254 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
256 * We will also set SUSPHY bit to what it was before returning as stated
257 * by the same section on Synopsys databook.
259 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
260 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
261 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
263 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
264 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
268 if (cmd
== DWC3_DEPCMD_STARTTRANSFER
) {
271 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
272 dwc
->link_state
== DWC3_LINK_STATE_U2
||
273 dwc
->link_state
== DWC3_LINK_STATE_U3
);
275 if (unlikely(needs_wakeup
)) {
276 ret
= __dwc3_gadget_wakeup(dwc
);
277 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
282 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
283 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
284 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
286 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
| DWC3_DEPCMD_CMDACT
);
288 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
289 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
290 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
292 switch (cmd_status
) {
296 case DEPEVT_TRANSFER_NO_RESOURCE
:
299 case DEPEVT_TRANSFER_BUS_EXPIRY
:
301 * SW issues START TRANSFER command to
302 * isochronous ep with future frame interval. If
303 * future interval time has already passed when
304 * core receives the command, it will respond
305 * with an error status of 'Bus Expiry'.
307 * Instead of always returning -EINVAL, let's
308 * give a hint to the gadget driver that this is
309 * the case by returning -EAGAIN.
314 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
323 cmd_status
= -ETIMEDOUT
;
326 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
328 if (unlikely(susphy
)) {
329 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
330 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
331 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
339 struct dwc3
*dwc
= dep
->dwc
;
340 struct dwc3_gadget_ep_cmd_params params
;
341 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
344 * As of core revision 2.60a the recommended programming model
345 * is to set the ClearPendIN bit when issuing a Clear Stall EP
346 * command for IN endpoints. This is to prevent an issue where
347 * some (non-compliant) hosts may not send ACK TPs for pending
348 * IN transfers due to a mishandled error condition. Synopsys
351 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
))
352 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
354 memset(¶ms
, 0, sizeof(params
));
356 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
359 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
360 struct dwc3_trb
*trb
)
362 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
364 return dep
->trb_pool_dma
+ offset
;
367 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
369 struct dwc3
*dwc
= dep
->dwc
;
374 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
375 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
376 &dep
->trb_pool_dma
, GFP_KERNEL
);
377 if (!dep
->trb_pool
) {
378 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
386 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
388 struct dwc3
*dwc
= dep
->dwc
;
390 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
391 dep
->trb_pool
, dep
->trb_pool_dma
);
393 dep
->trb_pool
= NULL
;
394 dep
->trb_pool_dma
= 0;
397 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
400 * dwc3_gadget_start_config - Configure EP resources
401 * @dwc: pointer to our controller context structure
402 * @dep: endpoint that is being enabled
404 * The assignment of transfer resources cannot perfectly follow the
405 * data book due to the fact that the controller driver does not have
406 * all knowledge of the configuration in advance. It is given this
407 * information piecemeal by the composite gadget framework after every
408 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
409 * programming model in this scenario can cause errors. For two
412 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
413 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
414 * multiple interfaces.
416 * 2) The databook does not mention doing more DEPXFERCFG for new
417 * endpoint on alt setting (8.1.6).
419 * The following simplified method is used instead:
421 * All hardware endpoints can be assigned a transfer resource and this
422 * setting will stay persistent until either a core reset or
423 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
424 * do DEPXFERCFG for every hardware endpoint as well. We are
425 * guaranteed that there are as many transfer resources as endpoints.
427 * This function is called for each endpoint when it is being enabled
428 * but is triggered only when called for EP0-out, which always happens
429 * first, and which should only happen in one of the above conditions.
431 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
433 struct dwc3_gadget_ep_cmd_params params
;
441 memset(¶ms
, 0x00, sizeof(params
));
442 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
444 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
448 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
449 struct dwc3_ep
*dep
= dwc
->eps
[i
];
454 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
462 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
463 const struct usb_endpoint_descriptor
*desc
,
464 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
465 bool modify
, bool restore
)
467 struct dwc3_gadget_ep_cmd_params params
;
469 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
470 "Can't modify and restore\n"))
473 memset(¶ms
, 0x00, sizeof(params
));
475 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
476 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
478 /* Burst size is only needed in SuperSpeed mode */
479 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
480 u32 burst
= dep
->endpoint
.maxburst
;
481 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
485 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
486 } else if (restore
) {
487 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
488 params
.param2
|= dep
->saved_state
;
490 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
493 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
495 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
496 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
498 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
499 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
500 | DWC3_DEPCFG_STREAM_EVENT_EN
;
501 dep
->stream_capable
= true;
504 if (!usb_endpoint_xfer_control(desc
))
505 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
508 * We are doing 1:1 mapping for endpoints, meaning
509 * Physical Endpoints 2 maps to Logical Endpoint 2 and
510 * so on. We consider the direction bit as part of the physical
511 * endpoint number. So USB endpoint 0x81 is 0x03.
513 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
516 * We must use the lower 16 TX FIFOs even though
520 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
522 if (desc
->bInterval
) {
523 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
524 dep
->interval
= 1 << (desc
->bInterval
- 1);
527 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
530 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
532 struct dwc3_gadget_ep_cmd_params params
;
534 memset(¶ms
, 0x00, sizeof(params
));
536 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
538 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
543 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
544 * @dep: endpoint to be initialized
545 * @desc: USB Endpoint Descriptor
547 * Caller should take care of locking
549 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
550 const struct usb_endpoint_descriptor
*desc
,
551 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
552 bool modify
, bool restore
)
554 struct dwc3
*dwc
= dep
->dwc
;
558 dwc3_trace(trace_dwc3_gadget
, "Enabling %s", dep
->name
);
560 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
561 ret
= dwc3_gadget_start_config(dwc
, dep
);
566 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, modify
,
571 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
572 struct dwc3_trb
*trb_st_hw
;
573 struct dwc3_trb
*trb_link
;
575 dep
->endpoint
.desc
= desc
;
576 dep
->comp_desc
= comp_desc
;
577 dep
->type
= usb_endpoint_type(desc
);
578 dep
->flags
|= DWC3_EP_ENABLED
;
580 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
581 reg
|= DWC3_DALEPENA_EP(dep
->number
);
582 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
584 if (usb_endpoint_xfer_control(desc
))
587 /* Initialize the TRB ring */
588 dep
->trb_dequeue
= 0;
589 dep
->trb_enqueue
= 0;
590 memset(dep
->trb_pool
, 0,
591 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
593 /* Link TRB. The HWO bit is never reset */
594 trb_st_hw
= &dep
->trb_pool
[0];
596 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
597 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
598 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
599 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
600 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
606 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
607 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
609 struct dwc3_request
*req
;
611 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
613 /* - giveback all requests to gadget driver */
614 while (!list_empty(&dep
->started_list
)) {
615 req
= next_request(&dep
->started_list
);
617 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
620 while (!list_empty(&dep
->pending_list
)) {
621 req
= next_request(&dep
->pending_list
);
623 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
628 * __dwc3_gadget_ep_disable - Disables a HW endpoint
629 * @dep: the endpoint to disable
631 * This function also removes requests which are currently processed ny the
632 * hardware and those which are not yet scheduled.
633 * Caller should take care of locking.
635 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
637 struct dwc3
*dwc
= dep
->dwc
;
640 dwc3_trace(trace_dwc3_gadget
, "Disabling %s", dep
->name
);
642 dwc3_remove_requests(dwc
, dep
);
644 /* make sure HW endpoint isn't stalled */
645 if (dep
->flags
& DWC3_EP_STALL
)
646 __dwc3_gadget_ep_set_halt(dep
, 0, false);
648 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
649 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
650 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
652 dep
->stream_capable
= false;
653 dep
->endpoint
.desc
= NULL
;
654 dep
->comp_desc
= NULL
;
661 /* -------------------------------------------------------------------------- */
663 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
664 const struct usb_endpoint_descriptor
*desc
)
669 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
674 /* -------------------------------------------------------------------------- */
676 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
677 const struct usb_endpoint_descriptor
*desc
)
684 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
685 pr_debug("dwc3: invalid parameters\n");
689 if (!desc
->wMaxPacketSize
) {
690 pr_debug("dwc3: missing wMaxPacketSize\n");
694 dep
= to_dwc3_ep(ep
);
697 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
698 "%s is already enabled\n",
702 spin_lock_irqsave(&dwc
->lock
, flags
);
703 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
704 spin_unlock_irqrestore(&dwc
->lock
, flags
);
709 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
717 pr_debug("dwc3: invalid parameters\n");
721 dep
= to_dwc3_ep(ep
);
724 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
725 "%s is already disabled\n",
729 spin_lock_irqsave(&dwc
->lock
, flags
);
730 ret
= __dwc3_gadget_ep_disable(dep
);
731 spin_unlock_irqrestore(&dwc
->lock
, flags
);
736 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
739 struct dwc3_request
*req
;
740 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
742 req
= kzalloc(sizeof(*req
), gfp_flags
);
746 req
->epnum
= dep
->number
;
749 dep
->allocated_requests
++;
751 trace_dwc3_alloc_request(req
);
753 return &req
->request
;
756 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
757 struct usb_request
*request
)
759 struct dwc3_request
*req
= to_dwc3_request(request
);
760 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
762 dep
->allocated_requests
--;
763 trace_dwc3_free_request(req
);
768 * dwc3_prepare_one_trb - setup one TRB from one request
769 * @dep: endpoint for which this request is prepared
770 * @req: dwc3_request pointer
772 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
773 struct dwc3_request
*req
, dma_addr_t dma
,
774 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
776 struct dwc3_trb
*trb
;
778 dwc3_trace(trace_dwc3_gadget
, "%s: req %p dma %08llx length %d%s%s",
779 dep
->name
, req
, (unsigned long long) dma
,
780 length
, last
? " last" : "",
781 chain
? " chain" : "");
784 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
787 dwc3_gadget_move_started_request(req
);
789 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
790 req
->first_trb_index
= dep
->trb_enqueue
;
793 dwc3_ep_inc_enq(dep
);
795 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
796 trb
->bpl
= lower_32_bits(dma
);
797 trb
->bph
= upper_32_bits(dma
);
799 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
800 case USB_ENDPOINT_XFER_CONTROL
:
801 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
804 case USB_ENDPOINT_XFER_ISOC
:
806 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
808 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
810 /* always enable Interrupt on Missed ISOC */
811 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
814 case USB_ENDPOINT_XFER_BULK
:
815 case USB_ENDPOINT_XFER_INT
:
816 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
820 * This is only possible with faulty memory because we
821 * checked it already :)
826 /* always enable Continue on Short Packet */
827 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
829 if (!req
->request
.no_interrupt
&& !chain
)
830 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI
;
832 if (last
&& !usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
833 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
836 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
838 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
839 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
841 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
843 dep
->queued_requests
++;
845 trace_dwc3_prepare_trb(dep
, trb
);
849 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
850 * @dep: The endpoint with the TRB ring
851 * @index: The index of the current TRB in the ring
853 * Returns the TRB prior to the one pointed to by the index. If the
854 * index is 0, we will wrap backwards, skip the link TRB, and return
855 * the one just before that.
857 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
860 index
= DWC3_TRB_NUM
- 2;
862 index
= dep
->trb_enqueue
- 1;
864 return &dep
->trb_pool
[index
];
867 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
869 struct dwc3_trb
*tmp
;
873 * If enqueue & dequeue are equal than it is either full or empty.
875 * One way to know for sure is if the TRB right before us has HWO bit
876 * set or not. If it has, then we're definitely full and can't fit any
877 * more transfers in our ring.
879 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
880 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
881 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
884 return DWC3_TRB_NUM
- 1;
887 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
888 trbs_left
&= (DWC3_TRB_NUM
- 1);
890 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
896 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
897 struct dwc3_request
*req
, unsigned int trbs_left
,
898 unsigned int more_coming
)
900 struct usb_request
*request
= &req
->request
;
901 struct scatterlist
*sg
= request
->sg
;
902 struct scatterlist
*s
;
903 unsigned int last
= false;
908 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
909 unsigned chain
= true;
911 length
= sg_dma_len(s
);
912 dma
= sg_dma_address(s
);
915 if (usb_endpoint_xfer_int(dep
->endpoint
.desc
) ||
928 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
936 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
937 struct dwc3_request
*req
, unsigned int trbs_left
,
938 unsigned int more_coming
)
940 unsigned int last
= false;
944 dma
= req
->request
.dma
;
945 length
= req
->request
.length
;
950 /* Is this the last request? */
951 if (usb_endpoint_xfer_int(dep
->endpoint
.desc
) || !more_coming
)
954 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
959 * dwc3_prepare_trbs - setup TRBs from requests
960 * @dep: endpoint for which requests are being prepared
962 * The function goes through the requests list and sets up TRBs for the
963 * transfers. The function returns once there are no more TRBs available or
964 * it runs out of requests.
966 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
968 struct dwc3_request
*req
, *n
;
969 unsigned int more_coming
;
972 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
974 trbs_left
= dwc3_calc_trbs_left(dep
);
978 more_coming
= dep
->allocated_requests
- dep
->queued_requests
;
980 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
981 if (req
->request
.num_mapped_sgs
> 0)
982 dwc3_prepare_one_trb_sg(dep
, req
, trbs_left
--,
985 dwc3_prepare_one_trb_linear(dep
, req
, trbs_left
--,
993 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
995 struct dwc3_gadget_ep_cmd_params params
;
996 struct dwc3_request
*req
;
997 struct dwc3
*dwc
= dep
->dwc
;
1002 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
1004 dwc3_prepare_trbs(dep
);
1005 req
= next_request(&dep
->started_list
);
1007 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1011 memset(¶ms
, 0, sizeof(params
));
1014 params
.param0
= upper_32_bits(req
->trb_dma
);
1015 params
.param1
= lower_32_bits(req
->trb_dma
);
1016 cmd
= DWC3_DEPCMD_STARTTRANSFER
|
1017 DWC3_DEPCMD_PARAM(cmd_param
);
1019 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1020 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1023 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1026 * FIXME we need to iterate over the list of requests
1027 * here and stop, unmap, free and del each of the linked
1028 * requests instead of what we do now.
1030 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1032 list_del(&req
->list
);
1036 dep
->flags
|= DWC3_EP_BUSY
;
1039 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1040 WARN_ON_ONCE(!dep
->resource_index
);
1046 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1047 struct dwc3_ep
*dep
, u32 cur_uf
)
1051 if (list_empty(&dep
->pending_list
)) {
1052 dwc3_trace(trace_dwc3_gadget
,
1053 "ISOC ep %s run out for requests",
1055 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1059 /* 4 micro frames in the future */
1060 uf
= cur_uf
+ dep
->interval
* 4;
1062 __dwc3_gadget_kick_transfer(dep
, uf
);
1065 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1066 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1070 mask
= ~(dep
->interval
- 1);
1071 cur_uf
= event
->parameters
& mask
;
1073 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1076 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1078 struct dwc3
*dwc
= dep
->dwc
;
1081 if (!dep
->endpoint
.desc
) {
1082 dwc3_trace(trace_dwc3_gadget
,
1083 "trying to queue request %p to disabled %s",
1084 &req
->request
, dep
->endpoint
.name
);
1088 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1089 &req
->request
, req
->dep
->name
)) {
1090 dwc3_trace(trace_dwc3_gadget
, "request %p belongs to '%s'",
1091 &req
->request
, req
->dep
->name
);
1095 pm_runtime_get(dwc
->dev
);
1097 req
->request
.actual
= 0;
1098 req
->request
.status
= -EINPROGRESS
;
1099 req
->direction
= dep
->direction
;
1100 req
->epnum
= dep
->number
;
1102 trace_dwc3_ep_queue(req
);
1105 * We only add to our list of requests now and
1106 * start consuming the list once we get XferNotReady
1109 * That way, we avoid doing anything that we don't need
1110 * to do now and defer it until the point we receive a
1111 * particular token from the Host side.
1113 * This will also avoid Host cancelling URBs due to too
1116 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1121 list_add_tail(&req
->list
, &dep
->pending_list
);
1124 * If there are no pending requests and the endpoint isn't already
1125 * busy, we will just start the request straight away.
1127 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1128 * little bit faster.
1130 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1131 !usb_endpoint_xfer_int(dep
->endpoint
.desc
)) {
1132 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1137 * There are a few special cases:
1139 * 1. XferNotReady with empty list of requests. We need to kick the
1140 * transfer here in that situation, otherwise we will be NAKing
1141 * forever. If we get XferNotReady before gadget driver has a
1142 * chance to queue a request, we will ACK the IRQ but won't be
1143 * able to receive the data until the next request is queued.
1144 * The following code is handling exactly that.
1147 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1149 * If xfernotready is already elapsed and it is a case
1150 * of isoc transfer, then issue END TRANSFER, so that
1151 * you can receive xfernotready again and can have
1152 * notion of current microframe.
1154 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1155 if (list_empty(&dep
->started_list
)) {
1156 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1157 dep
->flags
= DWC3_EP_ENABLED
;
1162 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1164 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1170 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1171 * kick the transfer here after queuing a request, otherwise the
1172 * core may not see the modified TRB(s).
1174 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1175 (dep
->flags
& DWC3_EP_BUSY
) &&
1176 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1177 WARN_ON_ONCE(!dep
->resource_index
);
1178 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
);
1183 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1184 * right away, otherwise host will not know we have streams to be
1187 if (dep
->stream_capable
)
1188 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1191 if (ret
&& ret
!= -EBUSY
)
1192 dwc3_trace(trace_dwc3_gadget
,
1193 "%s: failed to kick transfers",
1201 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1202 struct usb_request
*request
)
1204 dwc3_gadget_ep_free_request(ep
, request
);
1207 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1209 struct dwc3_request
*req
;
1210 struct usb_request
*request
;
1211 struct usb_ep
*ep
= &dep
->endpoint
;
1213 dwc3_trace(trace_dwc3_gadget
, "queueing ZLP");
1214 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1218 request
->length
= 0;
1219 request
->buf
= dwc
->zlp_buf
;
1220 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1222 req
= to_dwc3_request(request
);
1224 return __dwc3_gadget_ep_queue(dep
, req
);
1227 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1230 struct dwc3_request
*req
= to_dwc3_request(request
);
1231 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1232 struct dwc3
*dwc
= dep
->dwc
;
1234 unsigned long flags
;
1238 spin_lock_irqsave(&dwc
->lock
, flags
);
1239 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1242 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1243 * setting request->zero, instead of doing magic, we will just queue an
1244 * extra usb_request ourselves so that it gets handled the same way as
1245 * any other request.
1247 if (ret
== 0 && request
->zero
&& request
->length
&&
1248 (request
->length
% ep
->maxpacket
== 0))
1249 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1251 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1256 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1257 struct usb_request
*request
)
1259 struct dwc3_request
*req
= to_dwc3_request(request
);
1260 struct dwc3_request
*r
= NULL
;
1262 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1263 struct dwc3
*dwc
= dep
->dwc
;
1265 unsigned long flags
;
1268 trace_dwc3_ep_dequeue(req
);
1270 spin_lock_irqsave(&dwc
->lock
, flags
);
1272 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1278 list_for_each_entry(r
, &dep
->started_list
, list
) {
1283 /* wait until it is processed */
1284 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1287 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1294 /* giveback the request */
1295 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1298 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1303 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1305 struct dwc3_gadget_ep_cmd_params params
;
1306 struct dwc3
*dwc
= dep
->dwc
;
1309 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1310 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1314 memset(¶ms
, 0x00, sizeof(params
));
1317 struct dwc3_trb
*trb
;
1319 unsigned transfer_in_flight
;
1322 if (dep
->number
> 1)
1323 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1325 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1327 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1328 started
= !list_empty(&dep
->started_list
);
1330 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1331 (!dep
->direction
&& started
))) {
1332 dwc3_trace(trace_dwc3_gadget
,
1333 "%s: pending request, cannot halt",
1338 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1341 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1344 dep
->flags
|= DWC3_EP_STALL
;
1347 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1349 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1352 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1358 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1360 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1361 struct dwc3
*dwc
= dep
->dwc
;
1363 unsigned long flags
;
1367 spin_lock_irqsave(&dwc
->lock
, flags
);
1368 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1369 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1374 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1376 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1377 struct dwc3
*dwc
= dep
->dwc
;
1378 unsigned long flags
;
1381 spin_lock_irqsave(&dwc
->lock
, flags
);
1382 dep
->flags
|= DWC3_EP_WEDGE
;
1384 if (dep
->number
== 0 || dep
->number
== 1)
1385 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1387 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1388 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1393 /* -------------------------------------------------------------------------- */
1395 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1396 .bLength
= USB_DT_ENDPOINT_SIZE
,
1397 .bDescriptorType
= USB_DT_ENDPOINT
,
1398 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1401 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1402 .enable
= dwc3_gadget_ep0_enable
,
1403 .disable
= dwc3_gadget_ep0_disable
,
1404 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1405 .free_request
= dwc3_gadget_ep_free_request
,
1406 .queue
= dwc3_gadget_ep0_queue
,
1407 .dequeue
= dwc3_gadget_ep_dequeue
,
1408 .set_halt
= dwc3_gadget_ep0_set_halt
,
1409 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1412 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1413 .enable
= dwc3_gadget_ep_enable
,
1414 .disable
= dwc3_gadget_ep_disable
,
1415 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1416 .free_request
= dwc3_gadget_ep_free_request
,
1417 .queue
= dwc3_gadget_ep_queue
,
1418 .dequeue
= dwc3_gadget_ep_dequeue
,
1419 .set_halt
= dwc3_gadget_ep_set_halt
,
1420 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1423 /* -------------------------------------------------------------------------- */
1425 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1427 struct dwc3
*dwc
= gadget_to_dwc(g
);
1430 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1431 return DWC3_DSTS_SOFFN(reg
);
1434 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1436 unsigned long timeout
;
1445 * According to the Databook Remote wakeup request should
1446 * be issued only when the device is in early suspend state.
1448 * We can check that via USB Link State bits in DSTS register.
1450 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1452 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1453 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1454 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
1455 dwc3_trace(trace_dwc3_gadget
, "no wakeup on SuperSpeed");
1459 link_state
= DWC3_DSTS_USBLNKST(reg
);
1461 switch (link_state
) {
1462 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1463 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1466 dwc3_trace(trace_dwc3_gadget
,
1467 "can't wakeup from '%s'",
1468 dwc3_gadget_link_string(link_state
));
1472 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1474 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1478 /* Recent versions do this automatically */
1479 if (dwc
->revision
< DWC3_REVISION_194A
) {
1480 /* write zeroes to Link Change Request */
1481 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1482 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1483 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1486 /* poll until Link State changes to ON */
1487 timeout
= jiffies
+ msecs_to_jiffies(100);
1489 while (!time_after(jiffies
, timeout
)) {
1490 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1492 /* in HS, means ON */
1493 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1497 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1498 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1505 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1507 struct dwc3
*dwc
= gadget_to_dwc(g
);
1508 unsigned long flags
;
1511 spin_lock_irqsave(&dwc
->lock
, flags
);
1512 ret
= __dwc3_gadget_wakeup(dwc
);
1513 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1518 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1521 struct dwc3
*dwc
= gadget_to_dwc(g
);
1522 unsigned long flags
;
1524 spin_lock_irqsave(&dwc
->lock
, flags
);
1525 g
->is_selfpowered
= !!is_selfpowered
;
1526 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1531 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1536 if (pm_runtime_suspended(dwc
->dev
))
1539 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1541 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1542 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1543 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1546 if (dwc
->revision
>= DWC3_REVISION_194A
)
1547 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1548 reg
|= DWC3_DCTL_RUN_STOP
;
1550 if (dwc
->has_hibernation
)
1551 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1553 dwc
->pullups_connected
= true;
1555 reg
&= ~DWC3_DCTL_RUN_STOP
;
1557 if (dwc
->has_hibernation
&& !suspend
)
1558 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1560 dwc
->pullups_connected
= false;
1563 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1566 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1567 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1568 } while (--timeout
&& !(!is_on
^ !reg
));
1573 dwc3_trace(trace_dwc3_gadget
, "gadget %s data soft-%s",
1575 ? dwc
->gadget_driver
->function
: "no-function",
1576 is_on
? "connect" : "disconnect");
1581 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1583 struct dwc3
*dwc
= gadget_to_dwc(g
);
1584 unsigned long flags
;
1589 spin_lock_irqsave(&dwc
->lock
, flags
);
1590 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1591 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1596 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1600 /* Enable all but Start and End of Frame IRQs */
1601 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1602 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1603 DWC3_DEVTEN_CMDCMPLTEN
|
1604 DWC3_DEVTEN_ERRTICERREN
|
1605 DWC3_DEVTEN_WKUPEVTEN
|
1606 DWC3_DEVTEN_ULSTCNGEN
|
1607 DWC3_DEVTEN_CONNECTDONEEN
|
1608 DWC3_DEVTEN_USBRSTEN
|
1609 DWC3_DEVTEN_DISCONNEVTEN
);
1611 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1614 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1616 /* mask all interrupts */
1617 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1620 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1621 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1624 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1625 * dwc: pointer to our context structure
1627 * The following looks like complex but it's actually very simple. In order to
1628 * calculate the number of packets we can burst at once on OUT transfers, we're
1629 * gonna use RxFIFO size.
1631 * To calculate RxFIFO size we need two numbers:
1632 * MDWIDTH = size, in bits, of the internal memory bus
1633 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1635 * Given these two numbers, the formula is simple:
1637 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1639 * 24 bytes is for 3x SETUP packets
1640 * 16 bytes is a clock domain crossing tolerance
1642 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1644 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1651 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1652 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1654 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1655 nump
= min_t(u32
, nump
, 16);
1658 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1659 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1660 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1661 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1664 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1666 struct dwc3_ep
*dep
;
1670 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1671 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1674 * WORKAROUND: DWC3 revision < 2.20a have an issue
1675 * which would cause metastability state on Run/Stop
1676 * bit if we try to force the IP to USB2-only mode.
1678 * Because of that, we cannot configure the IP to any
1679 * speed other than the SuperSpeed
1683 * STAR#9000525659: Clock Domain Crossing on DCTL in
1686 if (dwc
->revision
< DWC3_REVISION_220A
) {
1687 reg
|= DWC3_DCFG_SUPERSPEED
;
1689 switch (dwc
->maximum_speed
) {
1691 reg
|= DWC3_DCFG_LOWSPEED
;
1693 case USB_SPEED_FULL
:
1694 reg
|= DWC3_DCFG_FULLSPEED1
;
1696 case USB_SPEED_HIGH
:
1697 reg
|= DWC3_DCFG_HIGHSPEED
;
1699 case USB_SPEED_SUPER_PLUS
:
1700 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
1703 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1704 dwc
->maximum_speed
);
1706 case USB_SPEED_SUPER
:
1707 reg
|= DWC3_DCFG_SUPERSPEED
;
1711 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1714 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1715 * field instead of letting dwc3 itself calculate that automatically.
1717 * This way, we maximize the chances that we'll be able to get several
1718 * bursts of data without going through any sort of endpoint throttling.
1720 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1721 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1722 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1724 dwc3_gadget_setup_nump(dwc
);
1726 /* Start with SuperSpeed Default */
1727 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1730 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1733 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1738 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1741 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1745 /* begin to receive SETUP packets */
1746 dwc
->ep0state
= EP0_SETUP_PHASE
;
1747 dwc3_ep0_out_start(dwc
);
1749 dwc3_gadget_enable_irq(dwc
);
1754 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1760 static int dwc3_gadget_start(struct usb_gadget
*g
,
1761 struct usb_gadget_driver
*driver
)
1763 struct dwc3
*dwc
= gadget_to_dwc(g
);
1764 unsigned long flags
;
1768 irq
= dwc
->irq_gadget
;
1769 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1770 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1772 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1777 spin_lock_irqsave(&dwc
->lock
, flags
);
1778 if (dwc
->gadget_driver
) {
1779 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1781 dwc
->gadget_driver
->driver
.name
);
1786 dwc
->gadget_driver
= driver
;
1788 if (pm_runtime_active(dwc
->dev
))
1789 __dwc3_gadget_start(dwc
);
1791 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1796 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1803 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1805 if (pm_runtime_suspended(dwc
->dev
))
1808 dwc3_gadget_disable_irq(dwc
);
1809 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1810 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1813 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1815 struct dwc3
*dwc
= gadget_to_dwc(g
);
1816 unsigned long flags
;
1818 spin_lock_irqsave(&dwc
->lock
, flags
);
1819 __dwc3_gadget_stop(dwc
);
1820 dwc
->gadget_driver
= NULL
;
1821 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1823 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1828 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1829 .get_frame
= dwc3_gadget_get_frame
,
1830 .wakeup
= dwc3_gadget_wakeup
,
1831 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1832 .pullup
= dwc3_gadget_pullup
,
1833 .udc_start
= dwc3_gadget_start
,
1834 .udc_stop
= dwc3_gadget_stop
,
1837 /* -------------------------------------------------------------------------- */
1839 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1840 u8 num
, u32 direction
)
1842 struct dwc3_ep
*dep
;
1845 for (i
= 0; i
< num
; i
++) {
1846 u8 epnum
= (i
<< 1) | (direction
? 1 : 0);
1848 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1853 dep
->number
= epnum
;
1854 dep
->direction
= !!direction
;
1855 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1856 dwc
->eps
[epnum
] = dep
;
1858 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1859 (epnum
& 1) ? "in" : "out");
1861 dep
->endpoint
.name
= dep
->name
;
1862 spin_lock_init(&dep
->lock
);
1864 dwc3_trace(trace_dwc3_gadget
, "initializing %s", dep
->name
);
1866 if (epnum
== 0 || epnum
== 1) {
1867 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1868 dep
->endpoint
.maxburst
= 1;
1869 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1871 dwc
->gadget
.ep0
= &dep
->endpoint
;
1875 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1876 dep
->endpoint
.max_streams
= 15;
1877 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1878 list_add_tail(&dep
->endpoint
.ep_list
,
1879 &dwc
->gadget
.ep_list
);
1881 ret
= dwc3_alloc_trb_pool(dep
);
1886 if (epnum
== 0 || epnum
== 1) {
1887 dep
->endpoint
.caps
.type_control
= true;
1889 dep
->endpoint
.caps
.type_iso
= true;
1890 dep
->endpoint
.caps
.type_bulk
= true;
1891 dep
->endpoint
.caps
.type_int
= true;
1894 dep
->endpoint
.caps
.dir_in
= !!direction
;
1895 dep
->endpoint
.caps
.dir_out
= !direction
;
1897 INIT_LIST_HEAD(&dep
->pending_list
);
1898 INIT_LIST_HEAD(&dep
->started_list
);
1904 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1908 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1910 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1912 dwc3_trace(trace_dwc3_gadget
,
1913 "failed to allocate OUT endpoints");
1917 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1919 dwc3_trace(trace_dwc3_gadget
,
1920 "failed to allocate IN endpoints");
1927 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1929 struct dwc3_ep
*dep
;
1932 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1933 dep
= dwc
->eps
[epnum
];
1937 * Physical endpoints 0 and 1 are special; they form the
1938 * bi-directional USB endpoint 0.
1940 * For those two physical endpoints, we don't allocate a TRB
1941 * pool nor do we add them the endpoints list. Due to that, we
1942 * shouldn't do these two operations otherwise we would end up
1943 * with all sorts of bugs when removing dwc3.ko.
1945 if (epnum
!= 0 && epnum
!= 1) {
1946 dwc3_free_trb_pool(dep
);
1947 list_del(&dep
->endpoint
.ep_list
);
1954 /* -------------------------------------------------------------------------- */
1956 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1957 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1958 const struct dwc3_event_depevt
*event
, int status
,
1962 unsigned int s_pkt
= 0;
1963 unsigned int trb_status
;
1965 dep
->queued_requests
--;
1966 trace_dwc3_complete_trb(dep
, trb
);
1969 * If we're in the middle of series of chained TRBs and we
1970 * receive a short transfer along the way, DWC3 will skip
1971 * through all TRBs including the last TRB in the chain (the
1972 * where CHN bit is zero. DWC3 will also avoid clearing HWO
1973 * bit and SW has to do it manually.
1975 * We're going to do that here to avoid problems of HW trying
1976 * to use bogus TRBs for transfers.
1978 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
1979 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1981 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1984 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1986 if (dep
->direction
) {
1988 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1989 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1990 dwc3_trace(trace_dwc3_gadget
,
1991 "%s: incomplete IN transfer",
1994 * If missed isoc occurred and there is
1995 * no request queued then issue END
1996 * TRANSFER, so that core generates
1997 * next xfernotready and we will issue
1998 * a fresh START TRANSFER.
1999 * If there are still queued request
2000 * then wait, do not issue either END
2001 * or UPDATE TRANSFER, just attach next
2002 * request in pending_list during
2003 * giveback.If any future queued request
2004 * is successfully transferred then we
2005 * will issue UPDATE TRANSFER for all
2006 * request in the pending_list.
2008 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
2010 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
2012 status
= -ECONNRESET
;
2015 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
2018 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2022 if (s_pkt
&& !chain
)
2024 if ((event
->status
& DEPEVT_STATUS_LST
) &&
2025 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
2026 DWC3_TRB_CTRL_HWO
)))
2028 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2029 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2034 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2035 const struct dwc3_event_depevt
*event
, int status
)
2037 struct dwc3_request
*req
;
2038 struct dwc3_trb
*trb
;
2047 req
= next_request(&dep
->started_list
);
2048 if (WARN_ON_ONCE(!req
))
2051 chain
= req
->request
.num_mapped_sgs
> 0;
2054 slot
= req
->first_trb_index
+ i
;
2055 if (slot
== DWC3_TRB_NUM
- 1)
2057 slot
%= DWC3_TRB_NUM
;
2058 trb
= &dep
->trb_pool
[slot
];
2059 count
+= trb
->size
& DWC3_TRB_SIZE_MASK
;
2061 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2062 event
, status
, chain
);
2065 } while (++i
< req
->request
.num_mapped_sgs
);
2068 * We assume here we will always receive the entire data block
2069 * which we should receive. Meaning, if we program RX to
2070 * receive 4K but we receive only 2K, we assume that's all we
2071 * should receive and we simply bounce the request back to the
2072 * gadget driver for further processing.
2074 req
->request
.actual
+= req
->request
.length
- count
;
2075 dwc3_gadget_giveback(dep
, req
, status
);
2082 * Our endpoint might get disabled by another thread during
2083 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2084 * early on so DWC3_EP_BUSY flag gets cleared
2086 if (!dep
->endpoint
.desc
)
2089 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2090 list_empty(&dep
->started_list
)) {
2091 if (list_empty(&dep
->pending_list
)) {
2093 * If there is no entry in request list then do
2094 * not issue END TRANSFER now. Just set PENDING
2095 * flag, so that END TRANSFER is issued when an
2096 * entry is added into request list.
2098 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2100 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2101 dep
->flags
= DWC3_EP_ENABLED
;
2106 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2107 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2108 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2113 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2114 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2116 unsigned status
= 0;
2118 u32 is_xfer_complete
;
2120 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2122 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2123 status
= -ECONNRESET
;
2125 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2126 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2127 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2128 dep
->flags
&= ~DWC3_EP_BUSY
;
2131 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2132 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2134 if (dwc
->revision
< DWC3_REVISION_183A
) {
2138 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2141 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2144 if (!list_empty(&dep
->started_list
))
2148 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2150 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2156 * Our endpoint might get disabled by another thread during
2157 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2158 * early on so DWC3_EP_BUSY flag gets cleared
2160 if (!dep
->endpoint
.desc
)
2163 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2166 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2167 if (!ret
|| ret
== -EBUSY
)
2172 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2173 const struct dwc3_event_depevt
*event
)
2175 struct dwc3_ep
*dep
;
2176 u8 epnum
= event
->endpoint_number
;
2178 dep
= dwc
->eps
[epnum
];
2180 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2183 if (epnum
== 0 || epnum
== 1) {
2184 dwc3_ep0_interrupt(dwc
, event
);
2188 switch (event
->endpoint_event
) {
2189 case DWC3_DEPEVT_XFERCOMPLETE
:
2190 dep
->resource_index
= 0;
2192 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2193 dwc3_trace(trace_dwc3_gadget
,
2194 "%s is an Isochronous endpoint",
2199 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2201 case DWC3_DEPEVT_XFERINPROGRESS
:
2202 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2204 case DWC3_DEPEVT_XFERNOTREADY
:
2205 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2206 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2211 active
= event
->status
& DEPEVT_STATUS_TRANSFER_ACTIVE
;
2213 dwc3_trace(trace_dwc3_gadget
, "%s: reason %s",
2214 dep
->name
, active
? "Transfer Active"
2215 : "Transfer Not Active");
2217 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2218 if (!ret
|| ret
== -EBUSY
)
2221 dwc3_trace(trace_dwc3_gadget
,
2222 "%s: failed to kick transfers",
2227 case DWC3_DEPEVT_STREAMEVT
:
2228 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2229 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2234 switch (event
->status
) {
2235 case DEPEVT_STREAMEVT_FOUND
:
2236 dwc3_trace(trace_dwc3_gadget
,
2237 "Stream %d found and started",
2241 case DEPEVT_STREAMEVT_NOTFOUND
:
2244 dwc3_trace(trace_dwc3_gadget
,
2245 "unable to find suitable stream");
2248 case DWC3_DEPEVT_RXTXFIFOEVT
:
2249 dwc3_trace(trace_dwc3_gadget
, "%s FIFO Overrun", dep
->name
);
2251 case DWC3_DEPEVT_EPCMDCMPLT
:
2252 dwc3_trace(trace_dwc3_gadget
, "Endpoint Command Complete");
2257 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2259 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2260 spin_unlock(&dwc
->lock
);
2261 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2262 spin_lock(&dwc
->lock
);
2266 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2268 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2269 spin_unlock(&dwc
->lock
);
2270 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2271 spin_lock(&dwc
->lock
);
2275 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2277 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2278 spin_unlock(&dwc
->lock
);
2279 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2280 spin_lock(&dwc
->lock
);
2284 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2286 if (!dwc
->gadget_driver
)
2289 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2290 spin_unlock(&dwc
->lock
);
2291 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2292 spin_lock(&dwc
->lock
);
2296 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2298 struct dwc3_ep
*dep
;
2299 struct dwc3_gadget_ep_cmd_params params
;
2303 dep
= dwc
->eps
[epnum
];
2305 if (!dep
->resource_index
)
2309 * NOTICE: We are violating what the Databook says about the
2310 * EndTransfer command. Ideally we would _always_ wait for the
2311 * EndTransfer Command Completion IRQ, but that's causing too
2312 * much trouble synchronizing between us and gadget driver.
2314 * We have discussed this with the IP Provider and it was
2315 * suggested to giveback all requests here, but give HW some
2316 * extra time to synchronize with the interconnect. We're using
2317 * an arbitrary 100us delay for that.
2319 * Note also that a similar handling was tested by Synopsys
2320 * (thanks a lot Paul) and nothing bad has come out of it.
2321 * In short, what we're doing is:
2323 * - Issue EndTransfer WITH CMDIOC bit set
2327 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2328 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2329 cmd
|= DWC3_DEPCMD_CMDIOC
;
2330 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2331 memset(¶ms
, 0, sizeof(params
));
2332 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2334 dep
->resource_index
= 0;
2335 dep
->flags
&= ~DWC3_EP_BUSY
;
2339 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2343 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2344 struct dwc3_ep
*dep
;
2346 dep
= dwc
->eps
[epnum
];
2350 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2353 dwc3_remove_requests(dwc
, dep
);
2357 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2361 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2362 struct dwc3_ep
*dep
;
2365 dep
= dwc
->eps
[epnum
];
2369 if (!(dep
->flags
& DWC3_EP_STALL
))
2372 dep
->flags
&= ~DWC3_EP_STALL
;
2374 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2379 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2383 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2384 reg
&= ~DWC3_DCTL_INITU1ENA
;
2385 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2387 reg
&= ~DWC3_DCTL_INITU2ENA
;
2388 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2390 dwc3_disconnect_gadget(dwc
);
2392 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2393 dwc
->setup_packet_pending
= false;
2394 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2396 dwc
->connected
= false;
2399 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2403 dwc
->connected
= true;
2406 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2407 * would cause a missing Disconnect Event if there's a
2408 * pending Setup Packet in the FIFO.
2410 * There's no suggested workaround on the official Bug
2411 * report, which states that "unless the driver/application
2412 * is doing any special handling of a disconnect event,
2413 * there is no functional issue".
2415 * Unfortunately, it turns out that we _do_ some special
2416 * handling of a disconnect event, namely complete all
2417 * pending transfers, notify gadget driver of the
2418 * disconnection, and so on.
2420 * Our suggested workaround is to follow the Disconnect
2421 * Event steps here, instead, based on a setup_packet_pending
2422 * flag. Such flag gets set whenever we have a SETUP_PENDING
2423 * status for EP0 TRBs and gets cleared on XferComplete for the
2428 * STAR#9000466709: RTL: Device : Disconnect event not
2429 * generated if setup packet pending in FIFO
2431 if (dwc
->revision
< DWC3_REVISION_188A
) {
2432 if (dwc
->setup_packet_pending
)
2433 dwc3_gadget_disconnect_interrupt(dwc
);
2436 dwc3_reset_gadget(dwc
);
2438 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2439 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2440 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2441 dwc
->test_mode
= false;
2443 dwc3_stop_active_transfers(dwc
);
2444 dwc3_clear_stall_all_ep(dwc
);
2446 /* Reset device address to zero */
2447 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2448 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2449 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2452 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2455 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2458 * We change the clock only at SS but I dunno why I would want to do
2459 * this. Maybe it becomes part of the power saving plan.
2462 if ((speed
!= DWC3_DSTS_SUPERSPEED
) &&
2463 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
2467 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2468 * each time on Connect Done.
2473 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2474 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2475 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2478 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2480 struct dwc3_ep
*dep
;
2485 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2486 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2489 dwc3_update_ram_clk_sel(dwc
, speed
);
2492 case DWC3_DSTS_SUPERSPEED_PLUS
:
2493 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2494 dwc
->gadget
.ep0
->maxpacket
= 512;
2495 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2497 case DWC3_DSTS_SUPERSPEED
:
2499 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2500 * would cause a missing USB3 Reset event.
2502 * In such situations, we should force a USB3 Reset
2503 * event by calling our dwc3_gadget_reset_interrupt()
2508 * STAR#9000483510: RTL: SS : USB3 reset event may
2509 * not be generated always when the link enters poll
2511 if (dwc
->revision
< DWC3_REVISION_190A
)
2512 dwc3_gadget_reset_interrupt(dwc
);
2514 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2515 dwc
->gadget
.ep0
->maxpacket
= 512;
2516 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2518 case DWC3_DSTS_HIGHSPEED
:
2519 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2520 dwc
->gadget
.ep0
->maxpacket
= 64;
2521 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2523 case DWC3_DSTS_FULLSPEED2
:
2524 case DWC3_DSTS_FULLSPEED1
:
2525 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2526 dwc
->gadget
.ep0
->maxpacket
= 64;
2527 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2529 case DWC3_DSTS_LOWSPEED
:
2530 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2531 dwc
->gadget
.ep0
->maxpacket
= 8;
2532 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2536 /* Enable USB2 LPM Capability */
2538 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2539 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2540 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2541 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2542 reg
|= DWC3_DCFG_LPM_CAP
;
2543 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2545 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2546 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2548 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2551 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2552 * DCFG.LPMCap is set, core responses with an ACK and the
2553 * BESL value in the LPM token is less than or equal to LPM
2556 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2557 && dwc
->has_lpm_erratum
,
2558 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2560 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2561 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2563 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2565 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2566 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2567 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2571 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2574 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2579 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2582 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2587 * Configure PHY via GUSB3PIPECTLn if required.
2589 * Update GTXFIFOSIZn
2591 * In both cases reset values should be sufficient.
2595 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2598 * TODO take core out of low power mode when that's
2602 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2603 spin_unlock(&dwc
->lock
);
2604 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2605 spin_lock(&dwc
->lock
);
2609 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2610 unsigned int evtinfo
)
2612 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2613 unsigned int pwropt
;
2616 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2617 * Hibernation mode enabled which would show up when device detects
2618 * host-initiated U3 exit.
2620 * In that case, device will generate a Link State Change Interrupt
2621 * from U3 to RESUME which is only necessary if Hibernation is
2624 * There are no functional changes due to such spurious event and we
2625 * just need to ignore it.
2629 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2632 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2633 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2634 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2635 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2636 (next
== DWC3_LINK_STATE_RESUME
)) {
2637 dwc3_trace(trace_dwc3_gadget
,
2638 "ignoring transition U3 -> Resume");
2644 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2645 * on the link partner, the USB session might do multiple entry/exit
2646 * of low power states before a transfer takes place.
2648 * Due to this problem, we might experience lower throughput. The
2649 * suggested workaround is to disable DCTL[12:9] bits if we're
2650 * transitioning from U1/U2 to U0 and enable those bits again
2651 * after a transfer completes and there are no pending transfers
2652 * on any of the enabled endpoints.
2654 * This is the first half of that workaround.
2658 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2659 * core send LGO_Ux entering U0
2661 if (dwc
->revision
< DWC3_REVISION_183A
) {
2662 if (next
== DWC3_LINK_STATE_U0
) {
2666 switch (dwc
->link_state
) {
2667 case DWC3_LINK_STATE_U1
:
2668 case DWC3_LINK_STATE_U2
:
2669 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2670 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2671 | DWC3_DCTL_ACCEPTU2ENA
2672 | DWC3_DCTL_INITU1ENA
2673 | DWC3_DCTL_ACCEPTU1ENA
);
2676 dwc
->u1u2
= reg
& u1u2
;
2680 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2690 case DWC3_LINK_STATE_U1
:
2691 if (dwc
->speed
== USB_SPEED_SUPER
)
2692 dwc3_suspend_gadget(dwc
);
2694 case DWC3_LINK_STATE_U2
:
2695 case DWC3_LINK_STATE_U3
:
2696 dwc3_suspend_gadget(dwc
);
2698 case DWC3_LINK_STATE_RESUME
:
2699 dwc3_resume_gadget(dwc
);
2706 dwc
->link_state
= next
;
2709 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2710 unsigned int evtinfo
)
2712 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2714 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2715 dwc3_suspend_gadget(dwc
);
2717 dwc
->link_state
= next
;
2720 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2721 unsigned int evtinfo
)
2723 unsigned int is_ss
= evtinfo
& BIT(4);
2726 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2727 * have a known issue which can cause USB CV TD.9.23 to fail
2730 * Because of this issue, core could generate bogus hibernation
2731 * events which SW needs to ignore.
2735 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2736 * Device Fallback from SuperSpeed
2738 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2741 /* enter hibernation here */
2744 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2745 const struct dwc3_event_devt
*event
)
2747 switch (event
->type
) {
2748 case DWC3_DEVICE_EVENT_DISCONNECT
:
2749 dwc3_gadget_disconnect_interrupt(dwc
);
2751 case DWC3_DEVICE_EVENT_RESET
:
2752 dwc3_gadget_reset_interrupt(dwc
);
2754 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2755 dwc3_gadget_conndone_interrupt(dwc
);
2757 case DWC3_DEVICE_EVENT_WAKEUP
:
2758 dwc3_gadget_wakeup_interrupt(dwc
);
2760 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2761 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2762 "unexpected hibernation event\n"))
2765 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2767 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2768 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2770 case DWC3_DEVICE_EVENT_EOPF
:
2771 /* It changed to be suspend event for version 2.30a and above */
2772 if (dwc
->revision
< DWC3_REVISION_230A
) {
2773 dwc3_trace(trace_dwc3_gadget
, "End of Periodic Frame");
2775 dwc3_trace(trace_dwc3_gadget
, "U3/L1-L2 Suspend Event");
2778 * Ignore suspend event until the gadget enters into
2779 * USB_STATE_CONFIGURED state.
2781 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2782 dwc3_gadget_suspend_interrupt(dwc
,
2786 case DWC3_DEVICE_EVENT_SOF
:
2787 dwc3_trace(trace_dwc3_gadget
, "Start of Periodic Frame");
2789 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2790 dwc3_trace(trace_dwc3_gadget
, "Erratic Error");
2792 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2793 dwc3_trace(trace_dwc3_gadget
, "Command Complete");
2795 case DWC3_DEVICE_EVENT_OVERFLOW
:
2796 dwc3_trace(trace_dwc3_gadget
, "Overflow");
2799 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2803 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2804 const union dwc3_event
*event
)
2806 trace_dwc3_event(event
->raw
);
2808 /* Endpoint IRQ, handle it and return early */
2809 if (event
->type
.is_devspec
== 0) {
2811 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2814 switch (event
->type
.type
) {
2815 case DWC3_EVENT_TYPE_DEV
:
2816 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2818 /* REVISIT what to do with Carkit and I2C events ? */
2820 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2824 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2826 struct dwc3
*dwc
= evt
->dwc
;
2827 irqreturn_t ret
= IRQ_NONE
;
2833 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2837 union dwc3_event event
;
2839 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2841 dwc3_process_event_entry(dwc
, &event
);
2844 * FIXME we wrap around correctly to the next entry as
2845 * almost all entries are 4 bytes in size. There is one
2846 * entry which has 12 bytes which is a regular entry
2847 * followed by 8 bytes data. ATM I don't know how
2848 * things are organized if we get next to the a
2849 * boundary so I worry about that once we try to handle
2852 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2855 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 4);
2859 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2862 /* Unmask interrupt */
2863 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2864 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2865 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2870 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2872 struct dwc3_event_buffer
*evt
= _evt
;
2873 struct dwc3
*dwc
= evt
->dwc
;
2874 unsigned long flags
;
2875 irqreturn_t ret
= IRQ_NONE
;
2877 spin_lock_irqsave(&dwc
->lock
, flags
);
2878 ret
= dwc3_process_event_buf(evt
);
2879 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2884 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2886 struct dwc3
*dwc
= evt
->dwc
;
2890 if (pm_runtime_suspended(dwc
->dev
)) {
2891 pm_runtime_get(dwc
->dev
);
2892 disable_irq_nosync(dwc
->irq_gadget
);
2893 dwc
->pending_events
= true;
2897 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2898 count
&= DWC3_GEVNTCOUNT_MASK
;
2903 evt
->flags
|= DWC3_EVENT_PENDING
;
2905 /* Mask interrupt */
2906 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2907 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2908 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2910 return IRQ_WAKE_THREAD
;
2913 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2915 struct dwc3_event_buffer
*evt
= _evt
;
2917 return dwc3_check_event_buf(evt
);
2921 * dwc3_gadget_init - Initializes gadget related registers
2922 * @dwc: pointer to our controller context structure
2924 * Returns 0 on success otherwise negative errno.
2926 int dwc3_gadget_init(struct dwc3
*dwc
)
2929 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
2931 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
2932 if (irq
== -EPROBE_DEFER
)
2936 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
2937 if (irq
== -EPROBE_DEFER
)
2941 irq
= platform_get_irq(dwc3_pdev
, 0);
2943 if (irq
!= -EPROBE_DEFER
) {
2945 "missing peripheral IRQ\n");
2954 dwc
->irq_gadget
= irq
;
2956 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2957 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2958 if (!dwc
->ctrl_req
) {
2959 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2964 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
2965 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2966 if (!dwc
->ep0_trb
) {
2967 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2972 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2973 if (!dwc
->setup_buf
) {
2978 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2979 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2981 if (!dwc
->ep0_bounce
) {
2982 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2987 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
2988 if (!dwc
->zlp_buf
) {
2993 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2994 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2995 dwc
->gadget
.sg_supported
= true;
2996 dwc
->gadget
.name
= "dwc3-gadget";
2997 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3000 * FIXME We might be setting max_speed to <SUPER, however versions
3001 * <2.20a of dwc3 have an issue with metastability (documented
3002 * elsewhere in this driver) which tells us we can't set max speed to
3003 * anything lower than SUPER.
3005 * Because gadget.max_speed is only used by composite.c and function
3006 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3007 * to happen so we avoid sending SuperSpeed Capability descriptor
3008 * together with our BOS descriptor as that could confuse host into
3009 * thinking we can handle super speed.
3011 * Note that, in fact, we won't even support GetBOS requests when speed
3012 * is less than super speed because we don't have means, yet, to tell
3013 * composite.c that we are USB 2.0 + LPM ECN.
3015 if (dwc
->revision
< DWC3_REVISION_220A
)
3016 dwc3_trace(trace_dwc3_gadget
,
3017 "Changing max_speed on rev %08x",
3020 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3023 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3026 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
3029 * REVISIT: Here we should clear all pending IRQs to be
3030 * sure we're starting from a well known location.
3033 ret
= dwc3_gadget_init_endpoints(dwc
);
3037 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3039 dev_err(dwc
->dev
, "failed to register udc\n");
3046 kfree(dwc
->zlp_buf
);
3049 dwc3_gadget_free_endpoints(dwc
);
3050 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3051 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3054 kfree(dwc
->setup_buf
);
3057 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
3058 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3061 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3062 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3068 /* -------------------------------------------------------------------------- */
3070 void dwc3_gadget_exit(struct dwc3
*dwc
)
3072 usb_del_gadget_udc(&dwc
->gadget
);
3074 dwc3_gadget_free_endpoints(dwc
);
3076 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3077 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3079 kfree(dwc
->setup_buf
);
3080 kfree(dwc
->zlp_buf
);
3082 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
3083 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3085 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3086 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3089 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3093 if (!dwc
->gadget_driver
)
3096 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3100 dwc3_disconnect_gadget(dwc
);
3101 __dwc3_gadget_stop(dwc
);
3106 int dwc3_gadget_resume(struct dwc3
*dwc
)
3110 if (!dwc
->gadget_driver
)
3113 ret
= __dwc3_gadget_start(dwc
);
3117 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3124 __dwc3_gadget_stop(dwc
);
3130 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3132 if (dwc
->pending_events
) {
3133 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3134 dwc
->pending_events
= false;
3135 enable_irq(dwc
->irq_gadget
);