drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 #ifdef CONFIG_DYNAMIC_DEBUG
  42 #define EHCI_STATS
  43 #endif
  44
  45 struct ehci_stats {
  46         /* irq usage */
  47         unsigned long           normal;
  48         unsigned long           error;
  49         unsigned long           iaa;
  50         unsigned long           lost_iaa;
  51
  52         /* termination of urbs from core */
  53         unsigned long           complete;
  54         unsigned long           unlink;
  55 };
  56
  57 /*
  58  * Scheduling and budgeting information for periodic transfers, for both
  59  * high-speed devices and full/low-speed devices lying behind a TT.
  60  */
  61 struct ehci_per_sched {
  62         struct usb_device       *udev;          /* access to the TT */
  63         struct usb_host_endpoint *ep;
  64         struct list_head        ps_list;        /* node on ehci_tt's ps_list */
  65         u16                     tt_usecs;       /* time on the FS/LS bus */
  66         u16                     cs_mask;        /* C-mask and S-mask bytes */
  67         u16                     period;         /* actual period in frames */
  68         u16                     phase;          /* actual phase, frame part */
  69         u8                      bw_phase;       /* same, for bandwidth
  70                                                    reservation */
  71         u8                      phase_uf;       /* uframe part of the phase */
  72         u8                      usecs, c_usecs; /* times on the HS bus */
  73         u8                      bw_uperiod;     /* period in microframes, for
  74                                                    bandwidth reservation */
  75         u8                      bw_period;      /* same, in frames */
  76 };
  77 #define NO_FRAME        29999                   /* frame not assigned yet */
  78
  79 /* ehci_hcd->lock guards shared data against other CPUs:
  80  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  81  *   usb_host_endpoint: hcpriv
  82  *   ehci_qh:   qh_next, qtd_list
  83  *   ehci_qtd:  qtd_list
  84  *
  85  * Also, hold this lock when talking to HC registers or
  86  * when updating hw_* fields in shared qh/qtd/... structures.
  87  */
  88
  89 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  90
  91 /*
  92  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  93  * controller may be doing DMA.  Lower values mean there's no DMA.
  94  */
  95 enum ehci_rh_state {
  96         EHCI_RH_HALTED,
  97         EHCI_RH_SUSPENDED,
  98         EHCI_RH_RUNNING,
  99         EHCI_RH_STOPPING
 100 };
 101
 102 /*
 103  * Timer events, ordered by increasing delay length.
 104  * Always update event_delays_ns[] and event_handlers[] (defined in
 105  * ehci-timer.c) in parallel with this list.
 106  */
 107 enum ehci_hrtimer_event {
 108         EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
 109         EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
 110         EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
 111         EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
 112         EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
 113         EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
 114         EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
 115         EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
 116         EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
 117         EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
 118         EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
 119         EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
 120 };
 121 #define EHCI_HRTIMER_NO_EVENT   99
 122
 123 struct ehci_hcd {                       /* one per controller */
 124         /* timing support */
 125         enum ehci_hrtimer_event next_hrtimer_event;
 126         unsigned                enabled_hrtimer_events;
 127         ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 128         struct hrtimer          hrtimer;
 129
 130         int                     PSS_poll_count;
 131         int                     ASS_poll_count;
 132         int                     died_poll_count;
 133
 134         /* glue to PCI and HCD framework */
 135         struct ehci_caps __iomem *caps;
 136         struct ehci_regs __iomem *regs;
 137         struct ehci_dbg_port __iomem *debug;
 138
 139         __u32                   hcs_params;     /* cached register copy */
 140         spinlock_t              lock;
 141         enum ehci_rh_state      rh_state;
 142
 143         /* general schedule support */
 144         bool                    scanning:1;
 145         bool                    need_rescan:1;
 146         bool                    intr_unlinking:1;
 147         bool                    iaa_in_progress:1;
 148         bool                    async_unlinking:1;
 149         bool                    shutdown:1;
 150         struct ehci_qh          *qh_scan_next;
 151
 152         /* async schedule support */
 153         struct ehci_qh          *async;
 154         struct ehci_qh          *dummy;         /* For AMD quirk use */
 155         struct list_head        async_unlink;
 156         struct list_head        async_idle;
 157         unsigned                async_unlink_cycle;
 158         unsigned                async_count;    /* async activity count */
 159
 160         /* periodic schedule support */
 161 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 162         unsigned                periodic_size;
 163         __hc32                  *periodic;      /* hw periodic table */
 164         dma_addr_t              periodic_dma;
 165         struct list_head        intr_qh_list;
 166         unsigned                i_thresh;       /* uframes HC might cache */
 167
 168         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 169         struct list_head        intr_unlink_wait;
 170         struct list_head        intr_unlink;
 171         unsigned                intr_unlink_wait_cycle;
 172         unsigned                intr_unlink_cycle;
 173         unsigned                now_frame;      /* frame from HC hardware */
 174         unsigned                last_iso_frame; /* last frame scanned for iso */
 175         unsigned                intr_count;     /* intr activity count */
 176         unsigned                isoc_count;     /* isoc activity count */
 177         unsigned                periodic_count; /* periodic activity count */
 178         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 179
 180
 181         /* list of itds & sitds completed while now_frame was still active */
 182         struct list_head        cached_itd_list;
 183         struct ehci_itd         *last_itd_to_free;
 184         struct list_head        cached_sitd_list;
 185         struct ehci_sitd        *last_sitd_to_free;
 186
 187         /* per root hub port */
 188         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 189
 190         /* bit vectors (one bit per port) */
 191         unsigned long           bus_suspended;          /* which ports were
 192                         already suspended at the start of a bus suspend */
 193         unsigned long           companion_ports;        /* which ports are
 194                         dedicated to the companion controller */
 195         unsigned long           owned_ports;            /* which ports are
 196                         owned by the companion during a bus suspend */
 197         unsigned long           port_c_suspend;         /* which ports have
 198                         the change-suspend feature turned on */
 199         unsigned long           suspended_ports;        /* which ports are
 200                         suspended */
 201         unsigned long           resuming_ports;         /* which ports have
 202                         started to resume */
 203
 204         /* per-HC memory pools (could be per-bus, but ...) */
 205         struct dma_pool         *qh_pool;       /* qh per active urb */
 206         struct dma_pool         *qtd_pool;      /* one or more per qh */
 207         struct dma_pool         *itd_pool;      /* itd per iso urb */
 208         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 209
 210         unsigned                random_frame;
 211         unsigned long           next_statechange;
 212         ktime_t                 last_periodic_enable;
 213         u32                     command;
 214
 215         /* SILICON QUIRKS */
 216         unsigned                no_selective_suspend:1;
 217         unsigned                has_fsl_port_bug:1; /* FreeScale */
 218         unsigned                has_fsl_hs_errata:1;    /* Freescale HS quirk */
 219         unsigned                big_endian_mmio:1;
 220         unsigned                big_endian_desc:1;
 221         unsigned                big_endian_capbase:1;
 222         unsigned                has_amcc_usb23:1;
 223         unsigned                need_io_watchdog:1;
 224         unsigned                amd_pll_fix:1;
 225         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 226         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 227         unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 228         unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 229         unsigned                imx28_write_fix:1; /* For Freescale i.MX28 */
 230
 231         /* required for usb32 quirk */
 232         #define OHCI_CTRL_HCFS          (3 << 6)
 233         #define OHCI_USB_OPER           (2 << 6)
 234         #define OHCI_USB_SUSPEND        (3 << 6)
 235
 236         #define OHCI_HCCTRL_OFFSET      0x4
 237         #define OHCI_HCCTRL_LEN         0x4
 238         __hc32                  *ohci_hcctrl_reg;
 239         unsigned                has_hostpc:1;
 240         unsigned                has_tdi_phy_lpm:1;
 241         unsigned                has_ppcd:1; /* support per-port change bits */
 242         u8                      sbrn;           /* packed release number */
 243
 244         /* irq statistics */
 245 #ifdef EHCI_STATS
 246         struct ehci_stats       stats;
 247 #       define COUNT(x) do { (x)++; } while (0)
 248 #else
 249 #       define COUNT(x) do {} while (0)
 250 #endif
 251
 252         /* debug files */
 253 #ifdef CONFIG_DYNAMIC_DEBUG
 254         struct dentry           *debug_dir;
 255 #endif
 256
 257         /* bandwidth usage */
 258 #define EHCI_BANDWIDTH_SIZE     64
 259 #define EHCI_BANDWIDTH_FRAMES   (EHCI_BANDWIDTH_SIZE >> 3)
 260         u8                      bandwidth[EHCI_BANDWIDTH_SIZE];
 261                                                 /* us allocated per uframe */
 262         u8                      tt_budget[EHCI_BANDWIDTH_SIZE];
 263                                                 /* us budgeted per uframe */
 264         struct list_head        tt_list;
 265
 266         /* platform-specific data -- must come last */
 267         unsigned long           priv[0] __aligned(sizeof(s64));
 268 };
 269
 270 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 271 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 272 {
 273         return (struct ehci_hcd *) (hcd->hcd_priv);
 274 }
 275 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 276 {
 277         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 278 }
 279
 280 /*-------------------------------------------------------------------------*/
 281
 282 #include <linux/usb/ehci_def.h>
 283
 284 /*-------------------------------------------------------------------------*/
 285
 286 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 287
 288 /*
 289  * EHCI Specification 0.95 Section 3.5
 290  * QTD: describe data transfer components (buffer, direction, ...)
 291  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 292  *
 293  * These are associated only with "QH" (Queue Head) structures,
 294  * used with control, bulk, and interrupt transfers.
 295  */
 296 struct ehci_qtd {
 297         /* first part defined by EHCI spec */
 298         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 299         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 300         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 301 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 302 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 303 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 304 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 305 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 306 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 307 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 308 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 309 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 310 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 311 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 312 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 313 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 314
 315 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 316 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 317 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 318
 319         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 320         __hc32                  hw_buf_hi [5];        /* Appendix B */
 321
 322         /* the rest is HCD-private */
 323         dma_addr_t              qtd_dma;                /* qtd address */
 324         struct list_head        qtd_list;               /* sw qtd list */
 325         struct urb              *urb;                   /* qtd's urb */
 326         size_t                  length;                 /* length of buffer */
 327 } __attribute__ ((aligned (32)));
 328
 329 /* mask NakCnt+T in qh->hw_alt_next */
 330 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 331
 332 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 333
 334 /*-------------------------------------------------------------------------*/
 335
 336 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 337 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 338
 339 /*
 340  * Now the following defines are not converted using the
 341  * cpu_to_le32() macro anymore, since we have to support
 342  * "dynamic" switching between be and le support, so that the driver
 343  * can be used on one system with SoC EHCI controller using big-endian
 344  * descriptors as well as a normal little-endian PCI EHCI controller.
 345  */
 346 /* values for that type tag */
 347 #define Q_TYPE_ITD      (0 << 1)
 348 #define Q_TYPE_QH       (1 << 1)
 349 #define Q_TYPE_SITD     (2 << 1)
 350 #define Q_TYPE_FSTN     (3 << 1)
 351
 352 /* next async queue entry, or pointer to interrupt/periodic QH */
 353 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 354
 355 /* for periodic/async schedules and qtd lists, mark end of list */
 356 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 357
 358 /*
 359  * Entries in periodic shadow table are pointers to one of four kinds
 360  * of data structure.  That's dictated by the hardware; a type tag is
 361  * encoded in the low bits of the hardware's periodic schedule.  Use
 362  * Q_NEXT_TYPE to get the tag.
 363  *
 364  * For entries in the async schedule, the type tag always says "qh".
 365  */
 366 union ehci_shadow {
 367         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 368         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 369         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 370         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 371         __hc32                  *hw_next;       /* (all types) */
 372         void                    *ptr;
 373 };
 374
 375 /*-------------------------------------------------------------------------*/
 376
 377 /*
 378  * EHCI Specification 0.95 Section 3.6
 379  * QH: describes control/bulk/interrupt endpoints
 380  * See Fig 3-7 "Queue Head Structure Layout".
 381  *
 382  * These appear in both the async and (for interrupt) periodic schedules.
 383  */
 384
 385 /* first part defined by EHCI spec */
 386 struct ehci_qh_hw {
 387         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 388         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 389 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 390 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 391 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 392 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 393 #define QH_LOW_SPEED    (1 << 12)
 394 #define QH_FULL_SPEED   (0 << 12)
 395 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 396         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 397 #define QH_SMASK        0x000000ff
 398 #define QH_CMASK        0x0000ff00
 399 #define QH_HUBADDR      0x007f0000
 400 #define QH_HUBPORT      0x3f800000
 401 #define QH_MULT         0xc0000000
 402         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 403
 404         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 405         __hc32                  hw_qtd_next;
 406         __hc32                  hw_alt_next;
 407         __hc32                  hw_token;
 408         __hc32                  hw_buf [5];
 409         __hc32                  hw_buf_hi [5];
 410 } __attribute__ ((aligned(32)));
 411
 412 struct ehci_qh {
 413         struct ehci_qh_hw       *hw;            /* Must come first */
 414         /* the rest is HCD-private */
 415         dma_addr_t              qh_dma;         /* address of qh */
 416         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 417         struct list_head        qtd_list;       /* sw qtd list */
 418         struct list_head        intr_node;      /* list of intr QHs */
 419         struct ehci_qtd         *dummy;
 420         struct list_head        unlink_node;
 421         struct ehci_per_sched   ps;             /* scheduling info */
 422
 423         unsigned                unlink_cycle;
 424
 425         u8                      qh_state;
 426 #define QH_STATE_LINKED         1               /* HC sees this */
 427 #define QH_STATE_UNLINK         2               /* HC may still see this */
 428 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 429 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 430 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 431
 432         u8                      xacterrs;       /* XactErr retry counter */
 433 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 434
 435         u8                      gap_uf;         /* uframes split/csplit gap */
 436
 437         unsigned                is_out:1;       /* bulk or intr OUT */
 438         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 439         unsigned                dequeue_during_giveback:1;
 440         unsigned                exception:1;    /* got a fault, or an unlink
 441                                                    was requested */
 442         unsigned                should_be_inactive:1;
 443 };
 444
 445 /*-------------------------------------------------------------------------*/
 446
 447 /* description of one iso transaction (up to 3 KB data if highspeed) */
 448 struct ehci_iso_packet {
 449         /* These will be copied to iTD when scheduling */
 450         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 451         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 452         u8                      cross;          /* buf crosses pages */
 453         /* for full speed OUT splits */
 454         u32                     buf1;
 455 };
 456
 457 /* temporary schedule data for packets from iso urbs (both speeds)
 458  * each packet is one logical usb transaction to the device (not TT),
 459  * beginning at stream->next_uframe
 460  */
 461 struct ehci_iso_sched {
 462         struct list_head        td_list;
 463         unsigned                span;
 464         unsigned                first_packet;
 465         struct ehci_iso_packet  packet [0];
 466 };
 467
 468 /*
 469  * ehci_iso_stream - groups all (s)itds for this endpoint.
 470  * acts like a qh would, if EHCI had them for ISO.
 471  */
 472 struct ehci_iso_stream {
 473         /* first field matches ehci_hq, but is NULL */
 474         struct ehci_qh_hw       *hw;
 475
 476         u8                      bEndpointAddress;
 477         u8                      highspeed;
 478         struct list_head        td_list;        /* queued itds/sitds */
 479         struct list_head        free_list;      /* list of unused itds/sitds */
 480
 481         /* output of (re)scheduling */
 482         struct ehci_per_sched   ps;             /* scheduling info */
 483         unsigned                next_uframe;
 484         __hc32                  splits;
 485
 486         /* the rest is derived from the endpoint descriptor,
 487          * including the extra info for hw_bufp[0..2]
 488          */
 489         u16                     uperiod;        /* period in uframes */
 490         u16                     maxp;
 491         unsigned                bandwidth;
 492
 493         /* This is used to initialize iTD's hw_bufp fields */
 494         __hc32                  buf0;
 495         __hc32                  buf1;
 496         __hc32                  buf2;
 497
 498         /* this is used to initialize sITD's tt info */
 499         __hc32                  address;
 500 };
 501
 502 /*-------------------------------------------------------------------------*/
 503
 504 /*
 505  * EHCI Specification 0.95 Section 3.3
 506  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 507  *
 508  * Schedule records for high speed iso xfers
 509  */
 510 struct ehci_itd {
 511         /* first part defined by EHCI spec */
 512         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 513         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 514 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 515 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 516 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 517 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 518 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 519 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 520
 521 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 522
 523         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 524         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 525
 526         /* the rest is HCD-private */
 527         dma_addr_t              itd_dma;        /* for this itd */
 528         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 529
 530         struct urb              *urb;
 531         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 532         struct list_head        itd_list;       /* list of stream's itds */
 533
 534         /* any/all hw_transactions here may be used by that urb */
 535         unsigned                frame;          /* where scheduled */
 536         unsigned                pg;
 537         unsigned                index[8];       /* in urb->iso_frame_desc */
 538 } __attribute__ ((aligned (32)));
 539
 540 /*-------------------------------------------------------------------------*/
 541
 542 /*
 543  * EHCI Specification 0.95 Section 3.4
 544  * siTD, aka split-transaction isochronous Transfer Descriptor
 545  *       ... describe full speed iso xfers through TT in hubs
 546  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 547  */
 548 struct ehci_sitd {
 549         /* first part defined by EHCI spec */
 550         __hc32                  hw_next;
 551 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 552         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 553         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 554         __hc32                  hw_results;             /* EHCI table 3-11 */
 555 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 556 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 557 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 558 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 559 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 560 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 561 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 562 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 563 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 564 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 565
 566 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 567
 568         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 569         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 570         __hc32                  hw_buf_hi [2];          /* Appendix B */
 571
 572         /* the rest is HCD-private */
 573         dma_addr_t              sitd_dma;
 574         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 575
 576         struct urb              *urb;
 577         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 578         struct list_head        sitd_list;      /* list of stream's sitds */
 579         unsigned                frame;
 580         unsigned                index;
 581 } __attribute__ ((aligned (32)));
 582
 583 /*-------------------------------------------------------------------------*/
 584
 585 /*
 586  * EHCI Specification 0.96 Section 3.7
 587  * Periodic Frame Span Traversal Node (FSTN)
 588  *
 589  * Manages split interrupt transactions (using TT) that span frame boundaries
 590  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 591  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 592  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 593  */
 594 struct ehci_fstn {
 595         __hc32                  hw_next;        /* any periodic q entry */
 596         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 597
 598         /* the rest is HCD-private */
 599         dma_addr_t              fstn_dma;
 600         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 601 } __attribute__ ((aligned (32)));
 602
 603 /*-------------------------------------------------------------------------*/
 604
 605 /*
 606  * USB-2.0 Specification Sections 11.14 and 11.18
 607  * Scheduling and budgeting split transactions using TTs
 608  *
 609  * A hub can have a single TT for all its ports, or multiple TTs (one for each
 610  * port).  The bandwidth and budgeting information for the full/low-speed bus
 611  * below each TT is self-contained and independent of the other TTs or the
 612  * high-speed bus.
 613  *
 614  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
 615  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
 616  * the best-case estimate of the number of full-speed bytes allocated to an
 617  * endpoint for each microframe within an allocated frame.
 618  *
 619  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
 620  * keep an up-to-date record, we recompute the budget when it is needed.
 621  */
 622
 623 struct ehci_tt {
 624         u16                     bandwidth[EHCI_BANDWIDTH_FRAMES];
 625
 626         struct list_head        tt_list;        /* List of all ehci_tt's */
 627         struct list_head        ps_list;        /* Items using this TT */
 628         struct usb_tt           *usb_tt;
 629         int                     tt_port;        /* TT port number */
 630 };
 631
 632 /*-------------------------------------------------------------------------*/
 633
 634 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 635
 636 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 637                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 638
 639 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 640                 ehci_adjust_port_wakeup_flags(ehci, false, false);
 641
 642 /*-------------------------------------------------------------------------*/
 643
 644 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 645
 646 /*
 647  * Some EHCI controllers have a Transaction Translator built into the
 648  * root hub. This is a non-standard feature.  Each controller will need
 649  * to add code to the following inline functions, and call them as
 650  * needed (mostly in root hub code).
 651  */
 652
 653 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 654
 655 /* Returns the speed of a device attached to a port on the root hub. */
 656 static inline unsigned int
 657 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 658 {
 659         if (ehci_is_TDI(ehci)) {
 660                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 661                 case 0:
 662                         return 0;
 663                 case 1:
 664                         return USB_PORT_STAT_LOW_SPEED;
 665                 case 2:
 666                 default:
 667                         return USB_PORT_STAT_HIGH_SPEED;
 668                 }
 669         }
 670         return USB_PORT_STAT_HIGH_SPEED;
 671 }
 672
 673 #else
 674
 675 #define ehci_is_TDI(e)                  (0)
 676
 677 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 678 #endif
 679
 680 /*-------------------------------------------------------------------------*/
 681
 682 #ifdef CONFIG_PPC_83xx
 683 /* Some Freescale processors have an erratum in which the TT
 684  * port number in the queue head was 0..N-1 instead of 1..N.
 685  */
 686 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 687 #else
 688 #define ehci_has_fsl_portno_bug(e)              (0)
 689 #endif
 690
 691 #define PORTSC_FSL_PFSC 24      /* Port Force Full-Speed Connect */
 692
 693 #if defined(CONFIG_PPC_85xx)
 694 /* Some Freescale processors have an erratum (USB A-005275) in which
 695  * incoming packets get corrupted in HS mode
 696  */
 697 #define ehci_has_fsl_hs_errata(e)       ((e)->has_fsl_hs_errata)
 698 #else
 699 #define ehci_has_fsl_hs_errata(e)       (0)
 700 #endif
 701
 702 /*
 703  * While most USB host controllers implement their registers in
 704  * little-endian format, a minority (celleb companion chip) implement
 705  * them in big endian format.
 706  *
 707  * This attempts to support either format at compile time without a
 708  * runtime penalty, or both formats with the additional overhead
 709  * of checking a flag bit.
 710  *
 711  * ehci_big_endian_capbase is a special quirk for controllers that
 712  * implement the HC capability registers as separate registers and not
 713  * as fields of a 32-bit register.
 714  */
 715
 716 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 717 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 718 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 719 #else
 720 #define ehci_big_endian_mmio(e)         0
 721 #define ehci_big_endian_capbase(e)      0
 722 #endif
 723
 724 /*
 725  * Big-endian read/write functions are arch-specific.
 726  * Other arches can be added if/when they're needed.
 727  */
 728 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 729 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 730 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 731 #endif
 732
 733 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 734                 __u32 __iomem * regs)
 735 {
 736 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 737         return ehci_big_endian_mmio(ehci) ?
 738                 readl_be(regs) :
 739                 readl(regs);
 740 #else
 741         return readl(regs);
 742 #endif
 743 }
 744
 745 #ifdef CONFIG_SOC_IMX28
 746 static inline void imx28_ehci_writel(const unsigned int val,
 747                 volatile __u32 __iomem *addr)
 748 {
 749         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 750 }
 751 #else
 752 static inline void imx28_ehci_writel(const unsigned int val,
 753                 volatile __u32 __iomem *addr)
 754 {
 755 }
 756 #endif
 757 static inline void ehci_writel(const struct ehci_hcd *ehci,
 758                 const unsigned int val, __u32 __iomem *regs)
 759 {
 760 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 761         ehci_big_endian_mmio(ehci) ?
 762                 writel_be(val, regs) :
 763                 writel(val, regs);
 764 #else
 765         if (ehci->imx28_write_fix)
 766                 imx28_ehci_writel(val, regs);
 767         else
 768                 writel(val, regs);
 769 #endif
 770 }
 771
 772 /*
 773  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 774  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 775  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 776  */
 777 #ifdef CONFIG_44x
 778 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 779 {
 780         u32 hc_control;
 781
 782         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 783         if (operational)
 784                 hc_control |= OHCI_USB_OPER;
 785         else
 786                 hc_control |= OHCI_USB_SUSPEND;
 787
 788         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 789         (void) readl_be(ehci->ohci_hcctrl_reg);
 790 }
 791 #else
 792 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 793 { }
 794 #endif
 795
 796 /*-------------------------------------------------------------------------*/
 797
 798 /*
 799  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 800  * format, but also its DMA data structures (descriptors).
 801  *
 802  * EHCI controllers accessed through PCI work normally (little-endian
 803  * everywhere), so we won't bother supporting a BE-only mode for now.
 804  */
 805 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 806 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 807
 808 /* cpu to ehci */
 809 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 810 {
 811         return ehci_big_endian_desc(ehci)
 812                 ? (__force __hc32)cpu_to_be32(x)
 813                 : (__force __hc32)cpu_to_le32(x);
 814 }
 815
 816 /* ehci to cpu */
 817 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 818 {
 819         return ehci_big_endian_desc(ehci)
 820                 ? be32_to_cpu((__force __be32)x)
 821                 : le32_to_cpu((__force __le32)x);
 822 }
 823
 824 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 825 {
 826         return ehci_big_endian_desc(ehci)
 827                 ? be32_to_cpup((__force __be32 *)x)
 828                 : le32_to_cpup((__force __le32 *)x);
 829 }
 830
 831 #else
 832
 833 /* cpu to ehci */
 834 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 835 {
 836         return cpu_to_le32(x);
 837 }
 838
 839 /* ehci to cpu */
 840 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 841 {
 842         return le32_to_cpu(x);
 843 }
 844
 845 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 846 {
 847         return le32_to_cpup(x);
 848 }
 849
 850 #endif
 851
 852 /*-------------------------------------------------------------------------*/
 853
 854 #define ehci_dbg(ehci, fmt, args...) \
 855         dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 856 #define ehci_err(ehci, fmt, args...) \
 857         dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 858 #define ehci_info(ehci, fmt, args...) \
 859         dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 860 #define ehci_warn(ehci, fmt, args...) \
 861         dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 862
 863
 864 #ifndef CONFIG_DYNAMIC_DEBUG
 865 #define STUB_DEBUG_FILES
 866 #endif
 867
 868 /*-------------------------------------------------------------------------*/
 869
 870 /* Declarations of things exported for use by ehci platform drivers */
 871
 872 struct ehci_driver_overrides {
 873         size_t          extra_priv_size;
 874         int             (*reset)(struct usb_hcd *hcd);
 875         int             (*port_power)(struct usb_hcd *hcd,
 876                                 int portnum, bool enable);
 877 };
 878
 879 extern void     ehci_init_driver(struct hc_driver *drv,
 880                                 const struct ehci_driver_overrides *over);
 881 extern int      ehci_setup(struct usb_hcd *hcd);
 882 extern int      ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
 883                                 u32 mask, u32 done, int usec);
 884 extern int      ehci_reset(struct ehci_hcd *ehci);
 885
 886 #ifdef CONFIG_PM
 887 extern int      ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 888 extern int      ehci_resume(struct usb_hcd *hcd, bool force_reset);
 889 extern void     ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
 890                         bool suspending, bool do_wakeup);
 891 #endif  /* CONFIG_PM */
 892
 893 extern int      ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 894                                  u16 wIndex, char *buf, u16 wLength);
 895
 896 #endif /* __LINUX_EHCI_HCD_H */