2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include <linux/dma-mapping.h>
71 #include "xhci-trace.h"
75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
81 unsigned long segment_offset
;
83 if (!seg
|| !trb
|| trb
< seg
->trbs
)
86 segment_offset
= trb
- seg
->trbs
;
87 if (segment_offset
>= TRBS_PER_SEGMENT
)
89 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
92 static bool trb_is_link(union xhci_trb
*trb
)
94 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
97 static bool last_trb_on_seg(struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
- 1];
102 static bool last_trb_on_ring(struct xhci_ring
*ring
,
103 struct xhci_segment
*seg
, union xhci_trb
*trb
)
105 return last_trb_on_seg(seg
, trb
) && (seg
->next
== ring
->first_seg
);
108 static bool link_trb_toggles_cycle(union xhci_trb
*trb
)
110 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
113 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
114 * TRB is in a new segment. This does not skip over link TRBs, and it does not
115 * effect the ring dequeue or enqueue pointers.
117 static void next_trb(struct xhci_hcd
*xhci
,
118 struct xhci_ring
*ring
,
119 struct xhci_segment
**seg
,
120 union xhci_trb
**trb
)
122 if (trb_is_link(*trb
)) {
124 *trb
= ((*seg
)->trbs
);
131 * See Cycle bit rules. SW is the consumer for the event ring only.
132 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
134 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
138 /* event ring doesn't have link trbs, check for last trb */
139 if (ring
->type
== TYPE_EVENT
) {
140 if (!last_trb_on_seg(ring
->deq_seg
, ring
->dequeue
)) {
144 if (last_trb_on_ring(ring
, ring
->deq_seg
, ring
->dequeue
))
145 ring
->cycle_state
^= 1;
146 ring
->deq_seg
= ring
->deq_seg
->next
;
147 ring
->dequeue
= ring
->deq_seg
->trbs
;
151 /* All other rings have link trbs */
152 if (!trb_is_link(ring
->dequeue
)) {
154 ring
->num_trbs_free
++;
156 while (trb_is_link(ring
->dequeue
)) {
157 ring
->deq_seg
= ring
->deq_seg
->next
;
158 ring
->dequeue
= ring
->deq_seg
->trbs
;
164 * See Cycle bit rules. SW is the consumer for the event ring only.
165 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
167 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
168 * chain bit is set), then set the chain bit in all the following link TRBs.
169 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
170 * have their chain bit cleared (so that each Link TRB is a separate TD).
172 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
173 * set, but other sections talk about dealing with the chain bit set. This was
174 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
175 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
177 * @more_trbs_coming: Will you enqueue more TRBs before calling
178 * prepare_transfer()?
180 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
181 bool more_trbs_coming
)
184 union xhci_trb
*next
;
186 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
187 /* If this is not event ring, there is one less usable TRB */
188 if (!trb_is_link(ring
->enqueue
))
189 ring
->num_trbs_free
--;
190 next
= ++(ring
->enqueue
);
193 /* Update the dequeue pointer further if that was a link TRB */
194 while (trb_is_link(next
)) {
197 * If the caller doesn't plan on enqueueing more TDs before
198 * ringing the doorbell, then we don't want to give the link TRB
199 * to the hardware just yet. We'll give the link TRB back in
200 * prepare_ring() just before we enqueue the TD at the top of
203 if (!chain
&& !more_trbs_coming
)
206 /* If we're not dealing with 0.95 hardware or isoc rings on
207 * AMD 0.96 host, carry over the chain bit of the previous TRB
208 * (which may mean the chain bit is cleared).
210 if (!(ring
->type
== TYPE_ISOC
&&
211 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)) &&
212 !xhci_link_trb_quirk(xhci
)) {
213 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
214 next
->link
.control
|= cpu_to_le32(chain
);
216 /* Give this link TRB to the hardware */
218 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
220 /* Toggle the cycle bit after the last ring segment. */
221 if (link_trb_toggles_cycle(next
))
222 ring
->cycle_state
^= 1;
224 ring
->enq_seg
= ring
->enq_seg
->next
;
225 ring
->enqueue
= ring
->enq_seg
->trbs
;
226 next
= ring
->enqueue
;
231 * Check to see if there's room to enqueue num_trbs on the ring and make sure
232 * enqueue pointer will not advance into dequeue segment. See rules above.
234 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
235 unsigned int num_trbs
)
237 int num_trbs_in_deq_seg
;
239 if (ring
->num_trbs_free
< num_trbs
)
242 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
243 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
244 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
251 /* Ring the host controller doorbell after placing a command on the ring */
252 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
254 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
257 xhci_dbg(xhci
, "// Ding dong!\n");
258 writel(DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
259 /* Flush PCI posted writes */
260 readl(&xhci
->dba
->doorbell
[0]);
263 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
)
268 xhci_dbg(xhci
, "Abort command ring\n");
270 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
271 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
274 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
275 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
276 * but the completion event in never sent. Use the cmd timeout timer to
277 * handle those cases. Use twice the time to cover the bit polling retry
279 mod_timer(&xhci
->cmd_timer
, jiffies
+ (2 * XHCI_CMD_DEFAULT_TIMEOUT
));
280 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
281 &xhci
->op_regs
->cmd_ring
);
283 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
284 * time the completion od all xHCI commands, including
285 * the Command Abort operation. If software doesn't see
286 * CRR negated in a timely manner (e.g. longer than 5
287 * seconds), then it should assume that the there are
288 * larger problems with the xHC and assert HCRST.
290 ret
= xhci_handshake(&xhci
->op_regs
->cmd_ring
,
291 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
293 /* we are about to kill xhci, give it one more chance */
294 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
295 &xhci
->op_regs
->cmd_ring
);
297 ret
= xhci_handshake(&xhci
->op_regs
->cmd_ring
,
298 CMD_RING_RUNNING
, 0, 3 * 1000 * 1000);
302 xhci_err(xhci
, "Stopped the command ring failed, "
303 "maybe the host is dead\n");
304 del_timer(&xhci
->cmd_timer
);
305 xhci
->xhc_state
|= XHCI_STATE_DYING
;
314 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
315 unsigned int slot_id
,
316 unsigned int ep_index
,
317 unsigned int stream_id
)
319 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
320 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
321 unsigned int ep_state
= ep
->ep_state
;
323 /* Don't ring the doorbell for this endpoint if there are pending
324 * cancellations because we don't want to interrupt processing.
325 * We don't want to restart any stream rings if there's a set dequeue
326 * pointer command pending because the device can choose to start any
327 * stream once the endpoint is on the HW schedule.
329 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
330 (ep_state
& EP_HALTED
))
332 writel(DB_VALUE(ep_index
, stream_id
), db_addr
);
333 /* The CPU has better things to do at this point than wait for a
334 * write-posting flush. It'll get there soon enough.
338 /* Ring the doorbell for any rings with pending URBs */
339 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
340 unsigned int slot_id
,
341 unsigned int ep_index
)
343 unsigned int stream_id
;
344 struct xhci_virt_ep
*ep
;
346 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
348 /* A ring has pending URBs if its TD list is not empty */
349 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
350 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
351 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
355 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
357 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
358 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
359 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
364 /* Get the right ring for the given slot_id, ep_index and stream_id.
365 * If the endpoint supports streams, boundary check the URB's stream ID.
366 * If the endpoint doesn't support streams, return the singular endpoint ring.
368 struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
369 unsigned int slot_id
, unsigned int ep_index
,
370 unsigned int stream_id
)
372 struct xhci_virt_ep
*ep
;
374 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
375 /* Common case: no streams */
376 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
379 if (stream_id
== 0) {
381 "WARN: Slot ID %u, ep index %u has streams, "
382 "but URB has no stream ID.\n",
387 if (stream_id
< ep
->stream_info
->num_streams
)
388 return ep
->stream_info
->stream_rings
[stream_id
];
391 "WARN: Slot ID %u, ep index %u has "
392 "stream IDs 1 to %u allocated, "
393 "but stream ID %u is requested.\n",
395 ep
->stream_info
->num_streams
- 1,
401 * Move the xHC's endpoint ring dequeue pointer past cur_td.
402 * Record the new state of the xHC's endpoint ring dequeue segment,
403 * dequeue pointer, and new consumer cycle state in state.
404 * Update our internal representation of the ring's dequeue pointer.
406 * We do this in three jumps:
407 * - First we update our new ring state to be the same as when the xHC stopped.
408 * - Then we traverse the ring to find the segment that contains
409 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
410 * any link TRBs with the toggle cycle bit set.
411 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
412 * if we've moved it past a link TRB with the toggle cycle bit set.
414 * Some of the uses of xhci_generic_trb are grotty, but if they're done
415 * with correct __le32 accesses they should work fine. Only users of this are
418 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
419 unsigned int slot_id
, unsigned int ep_index
,
420 unsigned int stream_id
, struct xhci_td
*cur_td
,
421 struct xhci_dequeue_state
*state
)
423 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
424 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
425 struct xhci_ring
*ep_ring
;
426 struct xhci_segment
*new_seg
;
427 union xhci_trb
*new_deq
;
430 bool cycle_found
= false;
431 bool td_last_trb_found
= false;
433 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
434 ep_index
, stream_id
);
436 xhci_warn(xhci
, "WARN can't find new dequeue state "
437 "for invalid stream ID %u.\n",
442 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
443 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
444 "Finding endpoint context");
445 /* 4.6.9 the css flag is written to the stream context for streams */
446 if (ep
->ep_state
& EP_HAS_STREAMS
) {
447 struct xhci_stream_ctx
*ctx
=
448 &ep
->stream_info
->stream_ctx_array
[stream_id
];
449 hw_dequeue
= le64_to_cpu(ctx
->stream_ring
);
451 struct xhci_ep_ctx
*ep_ctx
452 = xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
453 hw_dequeue
= le64_to_cpu(ep_ctx
->deq
);
456 new_seg
= ep_ring
->deq_seg
;
457 new_deq
= ep_ring
->dequeue
;
458 state
->new_cycle_state
= hw_dequeue
& 0x1;
461 * We want to find the pointer, segment and cycle state of the new trb
462 * (the one after current TD's last_trb). We know the cycle state at
463 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
467 if (!cycle_found
&& xhci_trb_virt_to_dma(new_seg
, new_deq
)
468 == (dma_addr_t
)(hw_dequeue
& ~0xf)) {
470 if (td_last_trb_found
)
473 if (new_deq
== cur_td
->last_trb
)
474 td_last_trb_found
= true;
477 TRB_TYPE_LINK_LE32(new_deq
->generic
.field
[3]) &&
478 new_deq
->generic
.field
[3] & cpu_to_le32(LINK_TOGGLE
))
479 state
->new_cycle_state
^= 0x1;
481 next_trb(xhci
, ep_ring
, &new_seg
, &new_deq
);
483 /* Search wrapped around, bail out */
484 if (new_deq
== ep
->ring
->dequeue
) {
485 xhci_err(xhci
, "Error: Failed finding new dequeue state\n");
486 state
->new_deq_seg
= NULL
;
487 state
->new_deq_ptr
= NULL
;
491 } while (!cycle_found
|| !td_last_trb_found
);
493 state
->new_deq_seg
= new_seg
;
494 state
->new_deq_ptr
= new_deq
;
496 /* Don't update the ring cycle state for the producer (us). */
497 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
498 "Cycle state = 0x%x", state
->new_cycle_state
);
500 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
501 "New dequeue segment = %p (virtual)",
503 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
504 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
505 "New dequeue pointer = 0x%llx (DMA)",
506 (unsigned long long) addr
);
509 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
510 * (The last TRB actually points to the ring enqueue pointer, which is not part
511 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
513 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
514 struct xhci_td
*cur_td
, bool flip_cycle
)
516 struct xhci_segment
*cur_seg
;
517 union xhci_trb
*cur_trb
;
519 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
521 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
522 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
523 /* Unchain any chained Link TRBs, but
524 * leave the pointers intact.
526 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
527 /* Flip the cycle bit (link TRBs can't be the first
531 cur_trb
->generic
.field
[3] ^=
532 cpu_to_le32(TRB_CYCLE
);
533 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
534 "Cancel (unchain) link TRB");
535 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
536 "Address = %p (0x%llx dma); "
537 "in seg %p (0x%llx dma)",
539 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
541 (unsigned long long)cur_seg
->dma
);
543 cur_trb
->generic
.field
[0] = 0;
544 cur_trb
->generic
.field
[1] = 0;
545 cur_trb
->generic
.field
[2] = 0;
546 /* Preserve only the cycle bit of this TRB */
547 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
548 /* Flip the cycle bit except on the first or last TRB */
549 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
550 cur_trb
!= cur_td
->last_trb
)
551 cur_trb
->generic
.field
[3] ^=
552 cpu_to_le32(TRB_CYCLE
);
553 cur_trb
->generic
.field
[3] |= cpu_to_le32(
554 TRB_TYPE(TRB_TR_NOOP
));
555 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
556 "TRB to noop at offset 0x%llx",
558 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
560 if (cur_trb
== cur_td
->last_trb
)
565 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
566 struct xhci_virt_ep
*ep
)
568 ep
->ep_state
&= ~EP_HALT_PENDING
;
569 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
570 * timer is running on another CPU, we don't decrement stop_cmds_pending
571 * (since we didn't successfully stop the watchdog timer).
573 if (del_timer(&ep
->stop_cmd_timer
))
574 ep
->stop_cmds_pending
--;
577 /* Must be called with xhci->lock held in interrupt context */
578 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
579 struct xhci_td
*cur_td
, int status
)
583 struct urb_priv
*urb_priv
;
586 urb_priv
= urb
->hcpriv
;
588 hcd
= bus_to_hcd(urb
->dev
->bus
);
590 /* Only giveback urb when this is the last td in urb */
591 if (urb_priv
->td_cnt
== urb_priv
->length
) {
592 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
593 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
594 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
595 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
596 usb_amd_quirk_pll_enable();
599 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
601 spin_unlock(&xhci
->lock
);
602 usb_hcd_giveback_urb(hcd
, urb
, status
);
603 xhci_urb_free_priv(urb_priv
);
604 spin_lock(&xhci
->lock
);
608 void xhci_unmap_td_bounce_buffer(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
611 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
612 struct xhci_segment
*seg
= td
->bounce_seg
;
613 struct urb
*urb
= td
->urb
;
618 if (usb_urb_dir_out(urb
)) {
619 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
624 /* for in tranfers we need to copy the data from bounce to sg */
625 sg_pcopy_from_buffer(urb
->sg
, urb
->num_mapped_sgs
, seg
->bounce_buf
,
626 seg
->bounce_len
, seg
->bounce_offs
);
627 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
630 seg
->bounce_offs
= 0;
634 * When we get a command completion for a Stop Endpoint Command, we need to
635 * unlink any cancelled TDs from the ring. There are two ways to do that:
637 * 1. If the HW was in the middle of processing the TD that needs to be
638 * cancelled, then we must move the ring's dequeue pointer past the last TRB
639 * in the TD with a Set Dequeue Pointer Command.
640 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
641 * bit cleared) so that the HW will skip over them.
643 static void xhci_handle_cmd_stop_ep(struct xhci_hcd
*xhci
, int slot_id
,
644 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
646 unsigned int ep_index
;
647 struct xhci_ring
*ep_ring
;
648 struct xhci_virt_ep
*ep
;
649 struct list_head
*entry
;
650 struct xhci_td
*cur_td
= NULL
;
651 struct xhci_td
*last_unlinked_td
;
653 struct xhci_dequeue_state deq_state
;
655 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb
->generic
.field
[3])))) {
656 if (!xhci
->devs
[slot_id
])
657 xhci_warn(xhci
, "Stop endpoint command "
658 "completion for disabled slot %u\n",
663 memset(&deq_state
, 0, sizeof(deq_state
));
664 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
665 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
667 if (list_empty(&ep
->cancelled_td_list
)) {
668 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
669 ep
->stopped_td
= NULL
;
670 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
674 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
675 * We have the xHCI lock, so nothing can modify this list until we drop
676 * it. We're also in the event handler, so we can't get re-interrupted
677 * if another Stop Endpoint command completes
679 list_for_each(entry
, &ep
->cancelled_td_list
) {
680 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
681 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
682 "Removing canceled TD starting at 0x%llx (dma).",
683 (unsigned long long)xhci_trb_virt_to_dma(
684 cur_td
->start_seg
, cur_td
->first_trb
));
685 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
687 /* This shouldn't happen unless a driver is mucking
688 * with the stream ID after submission. This will
689 * leave the TD on the hardware ring, and the hardware
690 * will try to execute it, and may access a buffer
691 * that has already been freed. In the best case, the
692 * hardware will execute it, and the event handler will
693 * ignore the completion event for that TD, since it was
694 * removed from the td_list for that endpoint. In
695 * short, don't muck with the stream ID after
698 xhci_warn(xhci
, "WARN Cancelled URB %p "
699 "has invalid stream ID %u.\n",
701 cur_td
->urb
->stream_id
);
702 goto remove_finished_td
;
705 * If we stopped on the TD we need to cancel, then we have to
706 * move the xHC endpoint ring dequeue pointer past this TD.
708 if (cur_td
== ep
->stopped_td
)
709 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
710 cur_td
->urb
->stream_id
,
713 td_to_noop(xhci
, ep_ring
, cur_td
, false);
716 * The event handler won't see a completion for this TD anymore,
717 * so remove it from the endpoint ring's TD list. Keep it in
718 * the cancelled TD list for URB completion later.
720 list_del_init(&cur_td
->td_list
);
722 last_unlinked_td
= cur_td
;
723 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
725 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
726 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
727 xhci_queue_new_dequeue_state(xhci
, slot_id
, ep_index
,
728 ep
->stopped_td
->urb
->stream_id
, &deq_state
);
729 xhci_ring_cmd_db(xhci
);
731 /* Otherwise ring the doorbell(s) to restart queued transfers */
732 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
735 ep
->stopped_td
= NULL
;
738 * Drop the lock and complete the URBs in the cancelled TD list.
739 * New TDs to be cancelled might be added to the end of the list before
740 * we can complete all the URBs for the TDs we already unlinked.
741 * So stop when we've completed the URB for the last TD we unlinked.
744 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
745 struct xhci_td
, cancelled_td_list
);
746 list_del_init(&cur_td
->cancelled_td_list
);
748 /* Clean up the cancelled URB */
749 /* Doesn't matter what we pass for status, since the core will
750 * just overwrite it (because the URB has been unlinked).
752 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
753 if (ep_ring
&& cur_td
->bounce_seg
)
754 xhci_unmap_td_bounce_buffer(xhci
, ep_ring
, cur_td
);
755 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0);
757 /* Stop processing the cancelled list if the watchdog timer is
760 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
762 } while (cur_td
!= last_unlinked_td
);
764 /* Return to the event handler with xhci->lock re-acquired */
767 static void xhci_kill_ring_urbs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
769 struct xhci_td
*cur_td
;
771 while (!list_empty(&ring
->td_list
)) {
772 cur_td
= list_first_entry(&ring
->td_list
,
773 struct xhci_td
, td_list
);
774 list_del_init(&cur_td
->td_list
);
775 if (!list_empty(&cur_td
->cancelled_td_list
))
776 list_del_init(&cur_td
->cancelled_td_list
);
778 if (cur_td
->bounce_seg
)
779 xhci_unmap_td_bounce_buffer(xhci
, ring
, cur_td
);
780 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
784 static void xhci_kill_endpoint_urbs(struct xhci_hcd
*xhci
,
785 int slot_id
, int ep_index
)
787 struct xhci_td
*cur_td
;
788 struct xhci_virt_ep
*ep
;
789 struct xhci_ring
*ring
;
791 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
792 if ((ep
->ep_state
& EP_HAS_STREAMS
) ||
793 (ep
->ep_state
& EP_GETTING_NO_STREAMS
)) {
796 for (stream_id
= 0; stream_id
< ep
->stream_info
->num_streams
;
798 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
799 "Killing URBs for slot ID %u, ep index %u, stream %u",
800 slot_id
, ep_index
, stream_id
+ 1);
801 xhci_kill_ring_urbs(xhci
,
802 ep
->stream_info
->stream_rings
[stream_id
]);
808 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
809 "Killing URBs for slot ID %u, ep index %u",
811 xhci_kill_ring_urbs(xhci
, ring
);
813 while (!list_empty(&ep
->cancelled_td_list
)) {
814 cur_td
= list_first_entry(&ep
->cancelled_td_list
,
815 struct xhci_td
, cancelled_td_list
);
816 list_del_init(&cur_td
->cancelled_td_list
);
817 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
821 /* Watchdog timer function for when a stop endpoint command fails to complete.
822 * In this case, we assume the host controller is broken or dying or dead. The
823 * host may still be completing some other events, so we have to be careful to
824 * let the event ring handler and the URB dequeueing/enqueueing functions know
825 * through xhci->state.
827 * The timer may also fire if the host takes a very long time to respond to the
828 * command, and the stop endpoint command completion handler cannot delete the
829 * timer before the timer function is called. Another endpoint cancellation may
830 * sneak in before the timer function can grab the lock, and that may queue
831 * another stop endpoint command and add the timer back. So we cannot use a
832 * simple flag to say whether there is a pending stop endpoint command for a
833 * particular endpoint.
835 * Instead we use a combination of that flag and a counter for the number of
836 * pending stop endpoint commands. If the timer is the tail end of the last
837 * stop endpoint command, and the endpoint's command is still pending, we assume
840 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
842 struct xhci_hcd
*xhci
;
843 struct xhci_virt_ep
*ep
;
847 ep
= (struct xhci_virt_ep
*) arg
;
850 spin_lock_irqsave(&xhci
->lock
, flags
);
852 ep
->stop_cmds_pending
--;
853 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
854 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
855 "Stop EP timer ran, but another timer marked "
856 "xHCI as DYING, exiting.");
857 spin_unlock_irqrestore(&xhci
->lock
, flags
);
860 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
861 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
862 "Stop EP timer ran, but no command pending, "
864 spin_unlock_irqrestore(&xhci
->lock
, flags
);
868 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
869 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
870 /* Oops, HC is dead or dying or at least not responding to the stop
873 xhci
->xhc_state
|= XHCI_STATE_DYING
;
874 /* Disable interrupts from the host controller and start halting it */
876 spin_unlock_irqrestore(&xhci
->lock
, flags
);
878 ret
= xhci_halt(xhci
);
880 spin_lock_irqsave(&xhci
->lock
, flags
);
882 /* This is bad; the host is not responding to commands and it's
883 * not allowing itself to be halted. At least interrupts are
884 * disabled. If we call usb_hc_died(), it will attempt to
885 * disconnect all device drivers under this host. Those
886 * disconnect() methods will wait for all URBs to be unlinked,
887 * so we must complete them.
889 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
890 xhci_warn(xhci
, "Completing active URBs anyway.\n");
891 /* We could turn all TDs on the rings to no-ops. This won't
892 * help if the host has cached part of the ring, and is slow if
893 * we want to preserve the cycle bit. Skip it and hope the host
894 * doesn't touch the memory.
897 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
900 for (j
= 0; j
< 31; j
++)
901 xhci_kill_endpoint_urbs(xhci
, i
, j
);
903 spin_unlock_irqrestore(&xhci
->lock
, flags
);
904 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
905 "Calling usb_hc_died()");
906 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
907 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
908 "xHCI host controller is dead.");
912 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
913 struct xhci_virt_device
*dev
,
914 struct xhci_ring
*ep_ring
,
915 unsigned int ep_index
)
917 union xhci_trb
*dequeue_temp
;
918 int num_trbs_free_temp
;
921 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
922 dequeue_temp
= ep_ring
->dequeue
;
924 /* If we get two back-to-back stalls, and the first stalled transfer
925 * ends just before a link TRB, the dequeue pointer will be left on
926 * the link TRB by the code in the while loop. So we have to update
927 * the dequeue pointer one segment further, or we'll jump off
928 * the segment into la-la-land.
930 if (trb_is_link(ep_ring
->dequeue
)) {
931 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
932 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
935 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
936 /* We have more usable TRBs */
937 ep_ring
->num_trbs_free
++;
939 if (trb_is_link(ep_ring
->dequeue
)) {
940 if (ep_ring
->dequeue
==
941 dev
->eps
[ep_index
].queued_deq_ptr
)
943 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
944 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
946 if (ep_ring
->dequeue
== dequeue_temp
) {
953 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
954 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
959 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
960 * we need to clear the set deq pending flag in the endpoint ring state, so that
961 * the TD queueing code can ring the doorbell again. We also need to ring the
962 * endpoint doorbell to restart the ring, but only if there aren't more
963 * cancellations pending.
965 static void xhci_handle_cmd_set_deq(struct xhci_hcd
*xhci
, int slot_id
,
966 union xhci_trb
*trb
, u32 cmd_comp_code
)
968 unsigned int ep_index
;
969 unsigned int stream_id
;
970 struct xhci_ring
*ep_ring
;
971 struct xhci_virt_device
*dev
;
972 struct xhci_virt_ep
*ep
;
973 struct xhci_ep_ctx
*ep_ctx
;
974 struct xhci_slot_ctx
*slot_ctx
;
976 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
977 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
978 dev
= xhci
->devs
[slot_id
];
979 ep
= &dev
->eps
[ep_index
];
981 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
983 xhci_warn(xhci
, "WARN Set TR deq ptr command for freed stream ID %u\n",
985 /* XXX: Harmless??? */
989 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
990 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
992 if (cmd_comp_code
!= COMP_SUCCESS
) {
993 unsigned int ep_state
;
994 unsigned int slot_state
;
996 switch (cmd_comp_code
) {
998 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1000 case COMP_CTX_STATE
:
1001 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1002 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
1003 ep_state
&= EP_STATE_MASK
;
1004 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1005 slot_state
= GET_SLOT_STATE(slot_state
);
1006 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1007 "Slot state = %u, EP state = %u",
1008 slot_state
, ep_state
);
1011 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1015 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1019 /* OK what do we do now? The endpoint state is hosed, and we
1020 * should never get to this point if the synchronization between
1021 * queueing, and endpoint state are correct. This might happen
1022 * if the device gets disconnected after we've finished
1023 * cancelling URBs, which might not be an error...
1027 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1028 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1029 struct xhci_stream_ctx
*ctx
=
1030 &ep
->stream_info
->stream_ctx_array
[stream_id
];
1031 deq
= le64_to_cpu(ctx
->stream_ring
) & SCTX_DEQ_MASK
;
1033 deq
= le64_to_cpu(ep_ctx
->deq
) & ~EP_CTX_CYCLE_MASK
;
1035 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1036 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq
);
1037 if (xhci_trb_virt_to_dma(ep
->queued_deq_seg
,
1038 ep
->queued_deq_ptr
) == deq
) {
1039 /* Update the ring's dequeue segment and dequeue pointer
1040 * to reflect the new position.
1042 update_ring_for_set_deq_completion(xhci
, dev
,
1045 xhci_warn(xhci
, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1046 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1047 ep
->queued_deq_seg
, ep
->queued_deq_ptr
);
1052 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1053 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1054 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1055 /* Restart any rings with pending URBs */
1056 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1059 static void xhci_handle_cmd_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1060 union xhci_trb
*trb
, u32 cmd_comp_code
)
1062 unsigned int ep_index
;
1064 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1065 /* This command will only fail if the endpoint wasn't halted,
1066 * but we don't care.
1068 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
1069 "Ignoring reset ep completion code of %u", cmd_comp_code
);
1071 /* HW with the reset endpoint quirk needs to have a configure endpoint
1072 * command complete before the endpoint can be used. Queue that here
1073 * because the HW can't handle two commands being queued in a row.
1075 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1076 struct xhci_command
*command
;
1077 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1079 xhci_warn(xhci
, "WARN Cannot submit cfg ep: ENOMEM\n");
1082 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1083 "Queueing configure endpoint command");
1084 xhci_queue_configure_endpoint(xhci
, command
,
1085 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1087 xhci_ring_cmd_db(xhci
);
1089 /* Clear our internal halted state */
1090 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1094 static void xhci_handle_cmd_enable_slot(struct xhci_hcd
*xhci
, int slot_id
,
1097 if (cmd_comp_code
== COMP_SUCCESS
)
1098 xhci
->slot_id
= slot_id
;
1103 static void xhci_handle_cmd_disable_slot(struct xhci_hcd
*xhci
, int slot_id
)
1105 struct xhci_virt_device
*virt_dev
;
1107 virt_dev
= xhci
->devs
[slot_id
];
1110 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1111 /* Delete default control endpoint resources */
1112 xhci_free_device_endpoint_resources(xhci
, virt_dev
, true);
1113 xhci_free_virt_device(xhci
, slot_id
);
1116 static void xhci_handle_cmd_config_ep(struct xhci_hcd
*xhci
, int slot_id
,
1117 struct xhci_event_cmd
*event
, u32 cmd_comp_code
)
1119 struct xhci_virt_device
*virt_dev
;
1120 struct xhci_input_control_ctx
*ctrl_ctx
;
1121 unsigned int ep_index
;
1122 unsigned int ep_state
;
1123 u32 add_flags
, drop_flags
;
1126 * Configure endpoint commands can come from the USB core
1127 * configuration or alt setting changes, or because the HW
1128 * needed an extra configure endpoint command after a reset
1129 * endpoint command or streams were being configured.
1130 * If the command was for a halted endpoint, the xHCI driver
1131 * is not waiting on the configure endpoint command.
1133 virt_dev
= xhci
->devs
[slot_id
];
1134 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1136 xhci_warn(xhci
, "Could not get input context, bad type.\n");
1140 add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1141 drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1142 /* Input ctx add_flags are the endpoint index plus one */
1143 ep_index
= xhci_last_valid_endpoint(add_flags
) - 1;
1145 /* A usb_set_interface() call directly after clearing a halted
1146 * condition may race on this quirky hardware. Not worth
1147 * worrying about, since this is prototype hardware. Not sure
1148 * if this will work for streams, but streams support was
1149 * untested on this prototype.
1151 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1152 ep_index
!= (unsigned int) -1 &&
1153 add_flags
- SLOT_FLAG
== drop_flags
) {
1154 ep_state
= virt_dev
->eps
[ep_index
].ep_state
;
1155 if (!(ep_state
& EP_HALTED
))
1157 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1158 "Completed config ep cmd - "
1159 "last ep index = %d, state = %d",
1160 ep_index
, ep_state
);
1161 /* Clear internal halted state and restart ring(s) */
1162 virt_dev
->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1163 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1169 static void xhci_handle_cmd_reset_dev(struct xhci_hcd
*xhci
, int slot_id
,
1170 struct xhci_event_cmd
*event
)
1172 xhci_dbg(xhci
, "Completed reset device command.\n");
1173 if (!xhci
->devs
[slot_id
])
1174 xhci_warn(xhci
, "Reset device command completion "
1175 "for disabled slot %u\n", slot_id
);
1178 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd
*xhci
,
1179 struct xhci_event_cmd
*event
)
1181 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1182 xhci
->error_bitmask
|= 1 << 6;
1185 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1186 "NEC firmware version %2x.%02x",
1187 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1188 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1191 static void xhci_complete_del_and_free_cmd(struct xhci_command
*cmd
, u32 status
)
1193 list_del(&cmd
->cmd_list
);
1195 if (cmd
->completion
) {
1196 cmd
->status
= status
;
1197 complete(cmd
->completion
);
1203 void xhci_cleanup_command_queue(struct xhci_hcd
*xhci
)
1205 struct xhci_command
*cur_cmd
, *tmp_cmd
;
1206 list_for_each_entry_safe(cur_cmd
, tmp_cmd
, &xhci
->cmd_list
, cmd_list
)
1207 xhci_complete_del_and_free_cmd(cur_cmd
, COMP_CMD_ABORT
);
1211 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1212 * If there are other commands waiting then restart the ring and kick the timer.
1213 * This must be called with command ring stopped and xhci->lock held.
1215 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
1216 struct xhci_command
*cur_cmd
)
1218 struct xhci_command
*i_cmd
, *tmp_cmd
;
1221 /* Turn all aborted commands in list to no-ops, then restart */
1222 list_for_each_entry_safe(i_cmd
, tmp_cmd
, &xhci
->cmd_list
,
1225 if (i_cmd
->status
!= COMP_CMD_ABORT
)
1228 i_cmd
->status
= COMP_CMD_STOP
;
1230 xhci_dbg(xhci
, "Turn aborted command %p to no-op\n",
1231 i_cmd
->command_trb
);
1232 /* get cycle state from the original cmd trb */
1233 cycle_state
= le32_to_cpu(
1234 i_cmd
->command_trb
->generic
.field
[3]) & TRB_CYCLE
;
1235 /* modify the command trb to no-op command */
1236 i_cmd
->command_trb
->generic
.field
[0] = 0;
1237 i_cmd
->command_trb
->generic
.field
[1] = 0;
1238 i_cmd
->command_trb
->generic
.field
[2] = 0;
1239 i_cmd
->command_trb
->generic
.field
[3] = cpu_to_le32(
1240 TRB_TYPE(TRB_CMD_NOOP
) | cycle_state
);
1243 * caller waiting for completion is called when command
1244 * completion event is received for these no-op commands
1248 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
1250 /* ring command ring doorbell to restart the command ring */
1251 if ((xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
) &&
1252 !(xhci
->xhc_state
& XHCI_STATE_DYING
)) {
1253 xhci
->current_cmd
= cur_cmd
;
1254 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
1255 xhci_ring_cmd_db(xhci
);
1261 void xhci_handle_command_timeout(unsigned long data
)
1263 struct xhci_hcd
*xhci
;
1265 unsigned long flags
;
1267 bool second_timeout
= false;
1268 xhci
= (struct xhci_hcd
*) data
;
1270 /* mark this command to be cancelled */
1271 spin_lock_irqsave(&xhci
->lock
, flags
);
1272 if (xhci
->current_cmd
) {
1273 if (xhci
->current_cmd
->status
== COMP_CMD_ABORT
)
1274 second_timeout
= true;
1275 xhci
->current_cmd
->status
= COMP_CMD_ABORT
;
1278 /* Make sure command ring is running before aborting it */
1279 hw_ring_state
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
1280 if ((xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
) &&
1281 (hw_ring_state
& CMD_RING_RUNNING
)) {
1282 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1283 xhci_dbg(xhci
, "Command timeout\n");
1284 ret
= xhci_abort_cmd_ring(xhci
);
1285 if (unlikely(ret
== -ESHUTDOWN
)) {
1286 xhci_err(xhci
, "Abort command ring failed\n");
1287 xhci_cleanup_command_queue(xhci
);
1288 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
1289 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
1294 /* command ring failed to restart, or host removed. Bail out */
1295 if (second_timeout
|| xhci
->xhc_state
& XHCI_STATE_REMOVING
) {
1296 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1297 xhci_dbg(xhci
, "command timed out twice, ring start fail?\n");
1298 xhci_cleanup_command_queue(xhci
);
1302 /* command timeout on stopped ring, ring can't be aborted */
1303 xhci_dbg(xhci
, "Command timeout on stopped ring\n");
1304 xhci_handle_stopped_cmd_ring(xhci
, xhci
->current_cmd
);
1305 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1309 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1310 struct xhci_event_cmd
*event
)
1312 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1314 dma_addr_t cmd_dequeue_dma
;
1316 union xhci_trb
*cmd_trb
;
1317 struct xhci_command
*cmd
;
1320 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1321 cmd_trb
= xhci
->cmd_ring
->dequeue
;
1322 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1324 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1325 if (cmd_dequeue_dma
== 0) {
1326 xhci
->error_bitmask
|= 1 << 4;
1329 /* Does the DMA address match our internal dequeue pointer address? */
1330 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1331 xhci
->error_bitmask
|= 1 << 5;
1335 cmd
= list_entry(xhci
->cmd_list
.next
, struct xhci_command
, cmd_list
);
1337 del_timer(&xhci
->cmd_timer
);
1339 trace_xhci_cmd_completion(cmd_trb
, (struct xhci_generic_trb
*) event
);
1341 cmd_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1343 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1344 if (cmd_comp_code
== COMP_CMD_STOP
) {
1345 xhci_handle_stopped_cmd_ring(xhci
, cmd
);
1349 if (cmd
->command_trb
!= xhci
->cmd_ring
->dequeue
) {
1351 "Command completion event does not match command\n");
1356 * Host aborted the command ring, check if the current command was
1357 * supposed to be aborted, otherwise continue normally.
1358 * The command ring is stopped now, but the xHC will issue a Command
1359 * Ring Stopped event which will cause us to restart it.
1361 if (cmd_comp_code
== COMP_CMD_ABORT
) {
1362 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1363 if (cmd
->status
== COMP_CMD_ABORT
)
1367 cmd_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb
->generic
.field
[3]));
1369 case TRB_ENABLE_SLOT
:
1370 xhci_handle_cmd_enable_slot(xhci
, slot_id
, cmd_comp_code
);
1372 case TRB_DISABLE_SLOT
:
1373 xhci_handle_cmd_disable_slot(xhci
, slot_id
);
1376 if (!cmd
->completion
)
1377 xhci_handle_cmd_config_ep(xhci
, slot_id
, event
,
1380 case TRB_EVAL_CONTEXT
:
1385 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1386 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1387 xhci_handle_cmd_stop_ep(xhci
, slot_id
, cmd_trb
, event
);
1390 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1391 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1392 xhci_handle_cmd_set_deq(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1395 /* Is this an aborted command turned to NO-OP? */
1396 if (cmd
->status
== COMP_CMD_STOP
)
1397 cmd_comp_code
= COMP_CMD_STOP
;
1400 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1401 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1402 xhci_handle_cmd_reset_ep(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1405 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1406 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1408 slot_id
= TRB_TO_SLOT_ID(
1409 le32_to_cpu(cmd_trb
->generic
.field
[3]));
1410 xhci_handle_cmd_reset_dev(xhci
, slot_id
, event
);
1412 case TRB_NEC_GET_FW
:
1413 xhci_handle_cmd_nec_get_fw(xhci
, event
);
1416 /* Skip over unknown commands on the event ring */
1417 xhci
->error_bitmask
|= 1 << 6;
1421 /* restart timer if this wasn't the last command */
1422 if (cmd
->cmd_list
.next
!= &xhci
->cmd_list
) {
1423 xhci
->current_cmd
= list_entry(cmd
->cmd_list
.next
,
1424 struct xhci_command
, cmd_list
);
1425 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
1429 xhci_complete_del_and_free_cmd(cmd
, cmd_comp_code
);
1431 inc_deq(xhci
, xhci
->cmd_ring
);
1434 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1435 union xhci_trb
*event
)
1439 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1440 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1441 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1442 handle_cmd_completion(xhci
, &event
->event_cmd
);
1445 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1446 * port registers -- USB 3.0 and USB 2.0).
1448 * Returns a zero-based port number, which is suitable for indexing into each of
1449 * the split roothubs' port arrays and bus state arrays.
1450 * Add one to it in order to call xhci_find_slot_id_by_port.
1452 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1453 struct xhci_hcd
*xhci
, u32 port_id
)
1456 unsigned int num_similar_speed_ports
= 0;
1458 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1459 * and usb2_ports are 0-based indexes. Count the number of similar
1460 * speed ports, up to 1 port before this port.
1462 for (i
= 0; i
< (port_id
- 1); i
++) {
1463 u8 port_speed
= xhci
->port_array
[i
];
1466 * Skip ports that don't have known speeds, or have duplicate
1467 * Extended Capabilities port speed entries.
1469 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1473 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1474 * 1.1 ports are under the USB 2.0 hub. If the port speed
1475 * matches the device speed, it's a similar speed port.
1477 if ((port_speed
== 0x03) == (hcd
->speed
>= HCD_USB3
))
1478 num_similar_speed_ports
++;
1480 return num_similar_speed_ports
;
1483 static void handle_device_notification(struct xhci_hcd
*xhci
,
1484 union xhci_trb
*event
)
1487 struct usb_device
*udev
;
1489 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->generic
.field
[3]));
1490 if (!xhci
->devs
[slot_id
]) {
1491 xhci_warn(xhci
, "Device Notification event for "
1492 "unused slot %u\n", slot_id
);
1496 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1498 udev
= xhci
->devs
[slot_id
]->udev
;
1499 if (udev
&& udev
->parent
)
1500 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1503 static void handle_port_status(struct xhci_hcd
*xhci
,
1504 union xhci_trb
*event
)
1506 struct usb_hcd
*hcd
;
1511 unsigned int faked_port_index
;
1513 struct xhci_bus_state
*bus_state
;
1514 __le32 __iomem
**port_array
;
1515 bool bogus_port_status
= false;
1517 /* Port status change events always have a successful completion code */
1518 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1519 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1520 xhci
->error_bitmask
|= 1 << 8;
1522 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1523 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1525 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1526 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1527 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1528 inc_deq(xhci
, xhci
->event_ring
);
1532 /* Figure out which usb_hcd this port is attached to:
1533 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1535 major_revision
= xhci
->port_array
[port_id
- 1];
1537 /* Find the right roothub. */
1538 hcd
= xhci_to_hcd(xhci
);
1539 if ((major_revision
== 0x03) != (hcd
->speed
>= HCD_USB3
))
1540 hcd
= xhci
->shared_hcd
;
1542 if (major_revision
== 0) {
1543 xhci_warn(xhci
, "Event for port %u not in "
1544 "Extended Capabilities, ignoring.\n",
1546 bogus_port_status
= true;
1549 if (major_revision
== DUPLICATE_ENTRY
) {
1550 xhci_warn(xhci
, "Event for port %u duplicated in"
1551 "Extended Capabilities, ignoring.\n",
1553 bogus_port_status
= true;
1558 * Hardware port IDs reported by a Port Status Change Event include USB
1559 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1560 * resume event, but we first need to translate the hardware port ID
1561 * into the index into the ports on the correct split roothub, and the
1562 * correct bus_state structure.
1564 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1565 if (hcd
->speed
>= HCD_USB3
)
1566 port_array
= xhci
->usb3_ports
;
1568 port_array
= xhci
->usb2_ports
;
1569 /* Find the faked port hub number */
1570 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1573 temp
= readl(port_array
[faked_port_index
]);
1574 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1575 xhci_dbg(xhci
, "resume root hub\n");
1576 usb_hcd_resume_root_hub(hcd
);
1579 if (hcd
->speed
>= HCD_USB3
&& (temp
& PORT_PLS_MASK
) == XDEV_INACTIVE
)
1580 bus_state
->port_remote_wakeup
&= ~(1 << faked_port_index
);
1582 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1583 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1585 temp1
= readl(&xhci
->op_regs
->command
);
1586 if (!(temp1
& CMD_RUN
)) {
1587 xhci_warn(xhci
, "xHC is not running.\n");
1591 if (DEV_SUPERSPEED_ANY(temp
)) {
1592 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1593 /* Set a flag to say the port signaled remote wakeup,
1594 * so we can tell the difference between the end of
1595 * device and host initiated resume.
1597 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1598 xhci_test_and_clear_bit(xhci
, port_array
,
1599 faked_port_index
, PORT_PLC
);
1600 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1602 /* Need to wait until the next link state change
1603 * indicates the device is actually in U0.
1605 bogus_port_status
= true;
1607 } else if (!test_bit(faked_port_index
,
1608 &bus_state
->resuming_ports
)) {
1609 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1610 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1611 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1612 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1613 mod_timer(&hcd
->rh_timer
,
1614 bus_state
->resume_done
[faked_port_index
]);
1615 /* Do the rest in GetPortStatus */
1619 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1620 DEV_SUPERSPEED_ANY(temp
)) {
1621 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1622 /* We've just brought the device into U0 through either the
1623 * Resume state after a device remote wakeup, or through the
1624 * U3Exit state after a host-initiated resume. If it's a device
1625 * initiated remote wake, don't pass up the link state change,
1626 * so the roothub behavior is consistent with external
1627 * USB 3.0 hub behavior.
1629 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1630 faked_port_index
+ 1);
1631 if (slot_id
&& xhci
->devs
[slot_id
])
1632 xhci_ring_device(xhci
, slot_id
);
1633 if (bus_state
->port_remote_wakeup
& (1 << faked_port_index
)) {
1634 bus_state
->port_remote_wakeup
&=
1635 ~(1 << faked_port_index
);
1636 xhci_test_and_clear_bit(xhci
, port_array
,
1637 faked_port_index
, PORT_PLC
);
1638 usb_wakeup_notification(hcd
->self
.root_hub
,
1639 faked_port_index
+ 1);
1640 bogus_port_status
= true;
1646 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1647 * RExit to a disconnect state). If so, let the the driver know it's
1648 * out of the RExit state.
1650 if (!DEV_SUPERSPEED_ANY(temp
) &&
1651 test_and_clear_bit(faked_port_index
,
1652 &bus_state
->rexit_ports
)) {
1653 complete(&bus_state
->rexit_done
[faked_port_index
]);
1654 bogus_port_status
= true;
1658 if (hcd
->speed
< HCD_USB3
)
1659 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1663 /* Update event ring dequeue pointer before dropping the lock */
1664 inc_deq(xhci
, xhci
->event_ring
);
1666 /* Don't make the USB core poll the roothub if we got a bad port status
1667 * change event. Besides, at that point we can't tell which roothub
1668 * (USB 2.0 or USB 3.0) to kick.
1670 if (bogus_port_status
)
1674 * xHCI port-status-change events occur when the "or" of all the
1675 * status-change bits in the portsc register changes from 0 to 1.
1676 * New status changes won't cause an event if any other change
1677 * bits are still set. When an event occurs, switch over to
1678 * polling to avoid losing status changes.
1680 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1681 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1682 spin_unlock(&xhci
->lock
);
1683 /* Pass this up to the core */
1684 usb_hcd_poll_rh_status(hcd
);
1685 spin_lock(&xhci
->lock
);
1689 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1690 * at end_trb, which may be in another segment. If the suspect DMA address is a
1691 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1694 struct xhci_segment
*trb_in_td(struct xhci_hcd
*xhci
,
1695 struct xhci_segment
*start_seg
,
1696 union xhci_trb
*start_trb
,
1697 union xhci_trb
*end_trb
,
1698 dma_addr_t suspect_dma
,
1701 dma_addr_t start_dma
;
1702 dma_addr_t end_seg_dma
;
1703 dma_addr_t end_trb_dma
;
1704 struct xhci_segment
*cur_seg
;
1706 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1707 cur_seg
= start_seg
;
1712 /* We may get an event for a Link TRB in the middle of a TD */
1713 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1714 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1715 /* If the end TRB isn't in this segment, this is set to 0 */
1716 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1720 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1721 (unsigned long long)suspect_dma
,
1722 (unsigned long long)start_dma
,
1723 (unsigned long long)end_trb_dma
,
1724 (unsigned long long)cur_seg
->dma
,
1725 (unsigned long long)end_seg_dma
);
1727 if (end_trb_dma
> 0) {
1728 /* The end TRB is in this segment, so suspect should be here */
1729 if (start_dma
<= end_trb_dma
) {
1730 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1733 /* Case for one segment with
1734 * a TD wrapped around to the top
1736 if ((suspect_dma
>= start_dma
&&
1737 suspect_dma
<= end_seg_dma
) ||
1738 (suspect_dma
>= cur_seg
->dma
&&
1739 suspect_dma
<= end_trb_dma
))
1744 /* Might still be somewhere in this segment */
1745 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1748 cur_seg
= cur_seg
->next
;
1749 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1750 } while (cur_seg
!= start_seg
);
1755 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1756 unsigned int slot_id
, unsigned int ep_index
,
1757 unsigned int stream_id
,
1758 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1760 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1761 struct xhci_command
*command
;
1762 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1766 ep
->ep_state
|= EP_HALTED
;
1767 ep
->stopped_stream
= stream_id
;
1769 xhci_queue_reset_ep(xhci
, command
, slot_id
, ep_index
);
1770 xhci_cleanup_stalled_ring(xhci
, ep_index
, td
);
1772 ep
->stopped_stream
= 0;
1774 xhci_ring_cmd_db(xhci
);
1777 /* Check if an error has halted the endpoint ring. The class driver will
1778 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1779 * However, a babble and other errors also halt the endpoint ring, and the class
1780 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1781 * Ring Dequeue Pointer command manually.
1783 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1784 struct xhci_ep_ctx
*ep_ctx
,
1785 unsigned int trb_comp_code
)
1787 /* TRB completion codes that may require a manual halt cleanup */
1788 if (trb_comp_code
== COMP_TX_ERR
||
1789 trb_comp_code
== COMP_BABBLE
||
1790 trb_comp_code
== COMP_SPLIT_ERR
)
1791 /* The 0.95 spec says a babbling control endpoint
1792 * is not halted. The 0.96 spec says it is. Some HW
1793 * claims to be 0.95 compliant, but it halts the control
1794 * endpoint anyway. Check if a babble halted the
1797 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1798 cpu_to_le32(EP_STATE_HALTED
))
1804 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1806 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1807 /* Vendor defined "informational" completion code,
1808 * treat as not-an-error.
1810 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1812 xhci_dbg(xhci
, "Treating code as success.\n");
1819 * Finish the td processing, remove the td from td list;
1820 * Return 1 if the urb can be given back.
1822 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1823 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1824 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1826 struct xhci_virt_device
*xdev
;
1827 struct xhci_ring
*ep_ring
;
1828 unsigned int slot_id
;
1830 struct urb
*urb
= NULL
;
1831 struct xhci_ep_ctx
*ep_ctx
;
1833 struct urb_priv
*urb_priv
;
1836 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1837 xdev
= xhci
->devs
[slot_id
];
1838 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1839 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1840 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1841 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1846 if (trb_comp_code
== COMP_STOP_INVAL
||
1847 trb_comp_code
== COMP_STOP
||
1848 trb_comp_code
== COMP_STOP_SHORT
) {
1849 /* The Endpoint Stop Command completion will take care of any
1850 * stopped TDs. A stopped TD may be restarted, so don't update
1851 * the ring dequeue pointer or take this TD off any lists yet.
1853 ep
->stopped_td
= td
;
1856 if (trb_comp_code
== COMP_STALL
||
1857 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
1859 /* Issue a reset endpoint command to clear the host side
1860 * halt, followed by a set dequeue command to move the
1861 * dequeue pointer past the TD.
1862 * The class driver clears the device side halt later.
1864 xhci_cleanup_halted_endpoint(xhci
, slot_id
, ep_index
,
1865 ep_ring
->stream_id
, td
, event_trb
);
1867 /* Update ring dequeue pointer */
1868 while (ep_ring
->dequeue
!= td
->last_trb
)
1869 inc_deq(xhci
, ep_ring
);
1870 inc_deq(xhci
, ep_ring
);
1874 /* Clean up the endpoint's TD list */
1876 urb_priv
= urb
->hcpriv
;
1878 /* if a bounce buffer was used to align this td then unmap it */
1880 xhci_unmap_td_bounce_buffer(xhci
, ep_ring
, td
);
1882 /* Do one last check of the actual transfer length.
1883 * If the host controller said we transferred more data than the buffer
1884 * length, urb->actual_length will be a very big number (since it's
1885 * unsigned). Play it safe and say we didn't transfer anything.
1887 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1888 xhci_warn(xhci
, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1889 urb
->transfer_buffer_length
,
1890 urb
->actual_length
);
1891 urb
->actual_length
= 0;
1892 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1893 *status
= -EREMOTEIO
;
1897 list_del_init(&td
->td_list
);
1898 /* Was this TD slated to be cancelled but completed anyway? */
1899 if (!list_empty(&td
->cancelled_td_list
))
1900 list_del_init(&td
->cancelled_td_list
);
1903 /* Giveback the urb when all the tds are completed */
1904 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1906 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1907 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1908 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
1909 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1910 usb_amd_quirk_pll_enable();
1919 * Process control tds, update urb status and actual_length.
1921 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1922 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1923 struct xhci_virt_ep
*ep
, int *status
)
1925 struct xhci_virt_device
*xdev
;
1926 struct xhci_ring
*ep_ring
;
1927 unsigned int slot_id
;
1929 struct xhci_ep_ctx
*ep_ctx
;
1932 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1933 xdev
= xhci
->devs
[slot_id
];
1934 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1935 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1936 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1937 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1939 switch (trb_comp_code
) {
1941 if (event_trb
== ep_ring
->dequeue
) {
1942 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1943 "without IOC set??\n");
1944 *status
= -ESHUTDOWN
;
1945 } else if (event_trb
!= td
->last_trb
) {
1946 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1947 "without IOC set??\n");
1948 *status
= -ESHUTDOWN
;
1954 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1955 *status
= -EREMOTEIO
;
1959 case COMP_STOP_SHORT
:
1960 if (event_trb
== ep_ring
->dequeue
|| event_trb
== td
->last_trb
)
1961 xhci_warn(xhci
, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1963 td
->urb
->actual_length
=
1964 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1966 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1968 /* Did we stop at data stage? */
1969 if (event_trb
!= ep_ring
->dequeue
&& event_trb
!= td
->last_trb
)
1970 td
->urb
->actual_length
=
1971 td
->urb
->transfer_buffer_length
-
1972 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1974 case COMP_STOP_INVAL
:
1975 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1977 if (!xhci_requires_manual_halt_cleanup(xhci
,
1978 ep_ctx
, trb_comp_code
))
1980 xhci_dbg(xhci
, "TRB error code %u, "
1981 "halted endpoint index = %u\n",
1982 trb_comp_code
, ep_index
);
1983 /* else fall through */
1985 /* Did we transfer part of the data (middle) phase? */
1986 if (event_trb
!= ep_ring
->dequeue
&&
1987 event_trb
!= td
->last_trb
)
1988 td
->urb
->actual_length
=
1989 td
->urb
->transfer_buffer_length
-
1990 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
1991 else if (!td
->urb_length_set
)
1992 td
->urb
->actual_length
= 0;
1994 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1997 * Did we transfer any data, despite the errors that might have
1998 * happened? I.e. did we get past the setup stage?
2000 if (event_trb
!= ep_ring
->dequeue
) {
2001 /* The event was for the status stage */
2002 if (event_trb
== td
->last_trb
) {
2003 if (td
->urb_length_set
) {
2004 /* Don't overwrite a previously set error code
2006 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
2007 (td
->urb
->transfer_flags
2008 & URB_SHORT_NOT_OK
))
2009 /* Did we already see a short data
2011 *status
= -EREMOTEIO
;
2013 td
->urb
->actual_length
=
2014 td
->urb
->transfer_buffer_length
;
2018 * Maybe the event was for the data stage? If so, update
2019 * already the actual_length of the URB and flag it as
2020 * set, so that it is not overwritten in the event for
2023 td
->urb_length_set
= true;
2024 td
->urb
->actual_length
=
2025 td
->urb
->transfer_buffer_length
-
2026 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2027 xhci_dbg(xhci
, "Waiting for status "
2033 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2037 * Process isochronous tds, update urb packet status and actual_length.
2039 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2040 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2041 struct xhci_virt_ep
*ep
, int *status
)
2043 struct xhci_ring
*ep_ring
;
2044 struct urb_priv
*urb_priv
;
2047 union xhci_trb
*cur_trb
;
2048 struct xhci_segment
*cur_seg
;
2049 struct usb_iso_packet_descriptor
*frame
;
2051 bool skip_td
= false;
2053 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2054 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2055 urb_priv
= td
->urb
->hcpriv
;
2056 idx
= urb_priv
->td_cnt
;
2057 frame
= &td
->urb
->iso_frame_desc
[idx
];
2059 /* handle completion code */
2060 switch (trb_comp_code
) {
2062 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
2066 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2067 trb_comp_code
= COMP_SHORT_TX
;
2069 case COMP_STOP_SHORT
:
2071 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2075 frame
->status
= -ECOMM
;
2078 case COMP_BUFF_OVER
:
2080 frame
->status
= -EOVERFLOW
;
2085 frame
->status
= -EPROTO
;
2089 frame
->status
= -EPROTO
;
2090 if (event_trb
!= td
->last_trb
)
2095 case COMP_STOP_INVAL
:
2102 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
2103 frame
->actual_length
= frame
->length
;
2104 td
->urb
->actual_length
+= frame
->length
;
2105 } else if (trb_comp_code
== COMP_STOP_SHORT
) {
2106 frame
->actual_length
=
2107 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2108 td
->urb
->actual_length
+= frame
->actual_length
;
2110 for (cur_trb
= ep_ring
->dequeue
,
2111 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
2112 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2113 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2114 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2115 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2117 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2118 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2120 if (trb_comp_code
!= COMP_STOP_INVAL
) {
2121 frame
->actual_length
= len
;
2122 td
->urb
->actual_length
+= len
;
2126 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2129 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2130 struct xhci_transfer_event
*event
,
2131 struct xhci_virt_ep
*ep
, int *status
)
2133 struct xhci_ring
*ep_ring
;
2134 struct urb_priv
*urb_priv
;
2135 struct usb_iso_packet_descriptor
*frame
;
2138 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2139 urb_priv
= td
->urb
->hcpriv
;
2140 idx
= urb_priv
->td_cnt
;
2141 frame
= &td
->urb
->iso_frame_desc
[idx
];
2143 /* The transfer is partly done. */
2144 frame
->status
= -EXDEV
;
2146 /* calc actual length */
2147 frame
->actual_length
= 0;
2149 /* Update ring dequeue pointer */
2150 while (ep_ring
->dequeue
!= td
->last_trb
)
2151 inc_deq(xhci
, ep_ring
);
2152 inc_deq(xhci
, ep_ring
);
2154 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
2158 * Process bulk and interrupt tds, update urb status and actual_length.
2160 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2161 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2162 struct xhci_virt_ep
*ep
, int *status
)
2164 struct xhci_ring
*ep_ring
;
2165 union xhci_trb
*cur_trb
;
2166 struct xhci_segment
*cur_seg
;
2169 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2170 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2172 switch (trb_comp_code
) {
2174 /* Double check that the HW transferred everything. */
2175 if (event_trb
!= td
->last_trb
||
2176 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2177 xhci_warn(xhci
, "WARN Successful completion "
2179 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2180 *status
= -EREMOTEIO
;
2183 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2184 trb_comp_code
= COMP_SHORT_TX
;
2189 case COMP_STOP_SHORT
:
2191 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2192 *status
= -EREMOTEIO
;
2197 /* Others already handled above */
2200 if (trb_comp_code
== COMP_SHORT_TX
)
2201 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
2202 "%d bytes untransferred\n",
2203 td
->urb
->ep
->desc
.bEndpointAddress
,
2204 td
->urb
->transfer_buffer_length
,
2205 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2206 /* Stopped - short packet completion */
2207 if (trb_comp_code
== COMP_STOP_SHORT
) {
2208 td
->urb
->actual_length
=
2209 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2211 if (td
->urb
->transfer_buffer_length
<
2212 td
->urb
->actual_length
) {
2213 xhci_warn(xhci
, "HC gave bad length of %d bytes txed\n",
2214 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2215 td
->urb
->actual_length
= 0;
2216 /* status will be set by usb core for canceled urbs */
2218 /* Fast path - was this the last TRB in the TD for this URB? */
2219 } else if (event_trb
== td
->last_trb
) {
2220 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2221 td
->urb
->actual_length
=
2222 td
->urb
->transfer_buffer_length
-
2223 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2224 if (td
->urb
->transfer_buffer_length
<
2225 td
->urb
->actual_length
) {
2226 xhci_warn(xhci
, "HC gave bad length "
2227 "of %d bytes left\n",
2228 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2229 td
->urb
->actual_length
= 0;
2230 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2231 *status
= -EREMOTEIO
;
2235 /* Don't overwrite a previously set error code */
2236 if (*status
== -EINPROGRESS
) {
2237 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2238 *status
= -EREMOTEIO
;
2243 td
->urb
->actual_length
=
2244 td
->urb
->transfer_buffer_length
;
2245 /* Ignore a short packet completion if the
2246 * untransferred length was zero.
2248 if (*status
== -EREMOTEIO
)
2252 /* Slow path - walk the list, starting from the dequeue
2253 * pointer, to get the actual length transferred.
2255 td
->urb
->actual_length
= 0;
2256 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
2257 cur_trb
!= event_trb
;
2258 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2259 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2260 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2261 td
->urb
->actual_length
+=
2262 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2264 /* If the ring didn't stop on a Link or No-op TRB, add
2265 * in the actual bytes transferred from the Normal TRB
2267 if (trb_comp_code
!= COMP_STOP_INVAL
)
2268 td
->urb
->actual_length
+=
2269 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2270 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2273 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2277 * If this function returns an error condition, it means it got a Transfer
2278 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2279 * At this point, the host controller is probably hosed and should be reset.
2281 static int handle_tx_event(struct xhci_hcd
*xhci
,
2282 struct xhci_transfer_event
*event
)
2283 __releases(&xhci
->lock
)
2284 __acquires(&xhci
->lock
)
2286 struct xhci_virt_device
*xdev
;
2287 struct xhci_virt_ep
*ep
;
2288 struct xhci_ring
*ep_ring
;
2289 unsigned int slot_id
;
2291 struct xhci_td
*td
= NULL
;
2292 dma_addr_t event_dma
;
2293 struct xhci_segment
*event_seg
;
2294 union xhci_trb
*event_trb
;
2295 struct urb
*urb
= NULL
;
2296 int status
= -EINPROGRESS
;
2297 struct urb_priv
*urb_priv
;
2298 struct xhci_ep_ctx
*ep_ctx
;
2299 struct list_head
*tmp
;
2303 bool handling_skipped_tds
= false;
2305 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2306 xdev
= xhci
->devs
[slot_id
];
2308 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2309 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2310 (unsigned long long) xhci_trb_virt_to_dma(
2311 xhci
->event_ring
->deq_seg
,
2312 xhci
->event_ring
->dequeue
),
2313 lower_32_bits(le64_to_cpu(event
->buffer
)),
2314 upper_32_bits(le64_to_cpu(event
->buffer
)),
2315 le32_to_cpu(event
->transfer_len
),
2316 le32_to_cpu(event
->flags
));
2317 xhci_dbg(xhci
, "Event ring:\n");
2318 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2322 /* Endpoint ID is 1 based, our index is zero based */
2323 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2324 ep
= &xdev
->eps
[ep_index
];
2325 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2326 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2328 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2329 EP_STATE_DISABLED
) {
2330 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2331 "or incorrect stream ring\n");
2332 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2333 (unsigned long long) xhci_trb_virt_to_dma(
2334 xhci
->event_ring
->deq_seg
,
2335 xhci
->event_ring
->dequeue
),
2336 lower_32_bits(le64_to_cpu(event
->buffer
)),
2337 upper_32_bits(le64_to_cpu(event
->buffer
)),
2338 le32_to_cpu(event
->transfer_len
),
2339 le32_to_cpu(event
->flags
));
2340 xhci_dbg(xhci
, "Event ring:\n");
2341 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2345 /* Count current td numbers if ep->skip is set */
2347 list_for_each(tmp
, &ep_ring
->td_list
)
2351 event_dma
= le64_to_cpu(event
->buffer
);
2352 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2353 /* Look for common error cases */
2354 switch (trb_comp_code
) {
2355 /* Skip codes that require special handling depending on
2359 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2361 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2362 trb_comp_code
= COMP_SHORT_TX
;
2364 xhci_warn_ratelimited(xhci
,
2365 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2369 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2371 case COMP_STOP_INVAL
:
2372 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2374 case COMP_STOP_SHORT
:
2375 xhci_dbg(xhci
, "Stopped with short packet transfer detected\n");
2378 xhci_dbg(xhci
, "Stalled endpoint\n");
2379 ep
->ep_state
|= EP_HALTED
;
2383 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2386 case COMP_SPLIT_ERR
:
2388 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2392 xhci_dbg(xhci
, "Babble error on endpoint\n");
2393 status
= -EOVERFLOW
;
2396 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2400 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2402 case COMP_BUFF_OVER
:
2403 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2407 * When the Isoch ring is empty, the xHC will generate
2408 * a Ring Overrun Event for IN Isoch endpoint or Ring
2409 * Underrun Event for OUT Isoch endpoint.
2411 xhci_dbg(xhci
, "underrun event on endpoint\n");
2412 if (!list_empty(&ep_ring
->td_list
))
2413 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2414 "still with TDs queued?\n",
2415 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2419 xhci_dbg(xhci
, "overrun event on endpoint\n");
2420 if (!list_empty(&ep_ring
->td_list
))
2421 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2422 "still with TDs queued?\n",
2423 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2427 xhci_warn(xhci
, "WARN: detect an incompatible device");
2430 case COMP_MISSED_INT
:
2432 * When encounter missed service error, one or more isoc tds
2433 * may be missed by xHC.
2434 * Set skip flag of the ep_ring; Complete the missed tds as
2435 * short transfer when process the ep_ring next time.
2438 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2442 xhci_dbg(xhci
, "No Ping response error, Skip one Isoc TD\n");
2445 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2449 xhci_warn(xhci
, "ERROR Unknown event condition %u, HC probably busted\n",
2455 /* This TRB should be in the TD at the head of this ring's
2458 if (list_empty(&ep_ring
->td_list
)) {
2460 * A stopped endpoint may generate an extra completion
2461 * event if the device was suspended. Don't print
2464 if (!(trb_comp_code
== COMP_STOP
||
2465 trb_comp_code
== COMP_STOP_INVAL
)) {
2466 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2467 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2469 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2470 (le32_to_cpu(event
->flags
) &
2471 TRB_TYPE_BITMASK
)>>10);
2472 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2476 xhci_dbg(xhci
, "td_list is empty while skip "
2477 "flag set. Clear skip flag.\n");
2483 /* We've skipped all the TDs on the ep ring when ep->skip set */
2484 if (ep
->skip
&& td_num
== 0) {
2486 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2487 "Clear skip flag.\n");
2492 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2496 /* Is this a TRB in the currently executing TD? */
2497 event_seg
= trb_in_td(xhci
, ep_ring
->deq_seg
, ep_ring
->dequeue
,
2498 td
->last_trb
, event_dma
, false);
2501 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2502 * is not in the current TD pointed by ep_ring->dequeue because
2503 * that the hardware dequeue pointer still at the previous TRB
2504 * of the current TD. The previous TRB maybe a Link TD or the
2505 * last TRB of the previous TD. The command completion handle
2506 * will take care the rest.
2508 if (!event_seg
&& (trb_comp_code
== COMP_STOP
||
2509 trb_comp_code
== COMP_STOP_INVAL
)) {
2516 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2517 /* Some host controllers give a spurious
2518 * successful event after a short transfer.
2521 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2522 ep_ring
->last_td_was_short
) {
2523 ep_ring
->last_td_was_short
= false;
2527 /* HC is busted, give up! */
2529 "ERROR Transfer event TRB DMA ptr not "
2530 "part of current TD ep_index %d "
2531 "comp_code %u\n", ep_index
,
2533 trb_in_td(xhci
, ep_ring
->deq_seg
,
2534 ep_ring
->dequeue
, td
->last_trb
,
2539 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2542 if (trb_comp_code
== COMP_SHORT_TX
)
2543 ep_ring
->last_td_was_short
= true;
2545 ep_ring
->last_td_was_short
= false;
2548 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2552 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2553 sizeof(*event_trb
)];
2555 * No-op TRB should not trigger interrupts.
2556 * If event_trb is a no-op TRB, it means the
2557 * corresponding TD has been cancelled. Just ignore
2560 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2562 "event_trb is a no-op TRB. Skip it\n");
2566 /* Now update the urb's actual_length and give back to
2569 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2570 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2572 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2573 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2576 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2582 handling_skipped_tds
= ep
->skip
&&
2583 trb_comp_code
!= COMP_MISSED_INT
&&
2584 trb_comp_code
!= COMP_PING_ERR
;
2587 * Do not update event ring dequeue pointer if we're in a loop
2588 * processing missed tds.
2590 if (!handling_skipped_tds
)
2591 inc_deq(xhci
, xhci
->event_ring
);
2595 urb_priv
= urb
->hcpriv
;
2597 xhci_urb_free_priv(urb_priv
);
2599 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2600 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2601 (urb
->transfer_flags
&
2602 URB_SHORT_NOT_OK
)) ||
2604 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2605 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2606 "expected = %d, status = %d\n",
2607 urb
, urb
->actual_length
,
2608 urb
->transfer_buffer_length
,
2610 spin_unlock(&xhci
->lock
);
2611 /* EHCI, UHCI, and OHCI always unconditionally set the
2612 * urb->status of an isochronous endpoint to 0.
2614 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2616 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2617 spin_lock(&xhci
->lock
);
2621 * If ep->skip is set, it means there are missed tds on the
2622 * endpoint ring need to take care of.
2623 * Process them as short transfer until reach the td pointed by
2626 } while (handling_skipped_tds
);
2632 * This function handles all OS-owned events on the event ring. It may drop
2633 * xhci->lock between event processing (e.g. to pass up port status changes).
2634 * Returns >0 for "possibly more events to process" (caller should call again),
2635 * otherwise 0 if done. In future, <0 returns should indicate error code.
2637 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2639 union xhci_trb
*event
;
2640 int update_ptrs
= 1;
2643 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2644 xhci
->error_bitmask
|= 1 << 1;
2648 event
= xhci
->event_ring
->dequeue
;
2649 /* Does the HC or OS own the TRB? */
2650 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2651 xhci
->event_ring
->cycle_state
) {
2652 xhci
->error_bitmask
|= 1 << 2;
2657 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2658 * speculative reads of the event's flags/data below.
2661 /* FIXME: Handle more event types. */
2662 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2663 case TRB_TYPE(TRB_COMPLETION
):
2664 handle_cmd_completion(xhci
, &event
->event_cmd
);
2666 case TRB_TYPE(TRB_PORT_STATUS
):
2667 handle_port_status(xhci
, event
);
2670 case TRB_TYPE(TRB_TRANSFER
):
2671 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2673 xhci
->error_bitmask
|= 1 << 9;
2677 case TRB_TYPE(TRB_DEV_NOTE
):
2678 handle_device_notification(xhci
, event
);
2681 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2683 handle_vendor_event(xhci
, event
);
2685 xhci
->error_bitmask
|= 1 << 3;
2687 /* Any of the above functions may drop and re-acquire the lock, so check
2688 * to make sure a watchdog timer didn't mark the host as non-responsive.
2690 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2691 xhci_dbg(xhci
, "xHCI host dying, returning from "
2692 "event handler.\n");
2697 /* Update SW event ring dequeue pointer */
2698 inc_deq(xhci
, xhci
->event_ring
);
2700 /* Are there more items on the event ring? Caller will call us again to
2707 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2708 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2709 * indicators of an event TRB error, but we check the status *first* to be safe.
2711 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2713 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2716 union xhci_trb
*event_ring_deq
;
2719 spin_lock(&xhci
->lock
);
2720 /* Check if the xHC generated the interrupt, or the irq is shared */
2721 status
= readl(&xhci
->op_regs
->status
);
2722 if (status
== 0xffffffff)
2725 if (!(status
& STS_EINT
)) {
2726 spin_unlock(&xhci
->lock
);
2729 if (status
& STS_FATAL
) {
2730 xhci_warn(xhci
, "WARNING: Host System Error\n");
2733 spin_unlock(&xhci
->lock
);
2738 * Clear the op reg interrupt status first,
2739 * so we can receive interrupts from other MSI-X interrupters.
2740 * Write 1 to clear the interrupt status.
2743 writel(status
, &xhci
->op_regs
->status
);
2744 /* FIXME when MSI-X is supported and there are multiple vectors */
2745 /* Clear the MSI-X event interrupt status */
2749 /* Acknowledge the PCI interrupt */
2750 irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
2751 irq_pending
|= IMAN_IP
;
2752 writel(irq_pending
, &xhci
->ir_set
->irq_pending
);
2755 if (xhci
->xhc_state
& XHCI_STATE_DYING
||
2756 xhci
->xhc_state
& XHCI_STATE_HALTED
) {
2757 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2758 "Shouldn't IRQs be disabled?\n");
2759 /* Clear the event handler busy flag (RW1C);
2760 * the event ring should be empty.
2762 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2763 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2764 &xhci
->ir_set
->erst_dequeue
);
2765 spin_unlock(&xhci
->lock
);
2770 event_ring_deq
= xhci
->event_ring
->dequeue
;
2771 /* FIXME this should be a delayed service routine
2772 * that clears the EHB.
2774 while (xhci_handle_event(xhci
) > 0) {}
2776 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2777 /* If necessary, update the HW's version of the event ring deq ptr. */
2778 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2779 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2780 xhci
->event_ring
->dequeue
);
2782 xhci_warn(xhci
, "WARN something wrong with SW event "
2783 "ring dequeue ptr.\n");
2784 /* Update HC event ring dequeue pointer */
2785 temp_64
&= ERST_PTR_MASK
;
2786 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2789 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2790 temp_64
|= ERST_EHB
;
2791 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2793 spin_unlock(&xhci
->lock
);
2798 irqreturn_t
xhci_msi_irq(int irq
, void *hcd
)
2800 return xhci_irq(hcd
);
2803 /**** Endpoint Ring Operations ****/
2806 * Generic function for queueing a TRB on a ring.
2807 * The caller must have checked to make sure there's room on the ring.
2809 * @more_trbs_coming: Will you enqueue more TRBs before calling
2810 * prepare_transfer()?
2812 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2813 bool more_trbs_coming
,
2814 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2816 struct xhci_generic_trb
*trb
;
2818 trb
= &ring
->enqueue
->generic
;
2819 trb
->field
[0] = cpu_to_le32(field1
);
2820 trb
->field
[1] = cpu_to_le32(field2
);
2821 trb
->field
[2] = cpu_to_le32(field3
);
2822 trb
->field
[3] = cpu_to_le32(field4
);
2823 inc_enq(xhci
, ring
, more_trbs_coming
);
2827 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2828 * FIXME allocate segments if the ring is full.
2830 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2831 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2833 unsigned int num_trbs_needed
;
2835 /* Make sure the endpoint has been added to xHC schedule */
2837 case EP_STATE_DISABLED
:
2839 * USB core changed config/interfaces without notifying us,
2840 * or hardware is reporting the wrong state.
2842 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2844 case EP_STATE_ERROR
:
2845 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2846 /* FIXME event handling code for error needs to clear it */
2847 /* XXX not sure if this should be -ENOENT or not */
2849 case EP_STATE_HALTED
:
2850 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2851 case EP_STATE_STOPPED
:
2852 case EP_STATE_RUNNING
:
2855 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2857 * FIXME issue Configure Endpoint command to try to get the HC
2858 * back into a known state.
2864 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2867 if (ep_ring
== xhci
->cmd_ring
) {
2868 xhci_err(xhci
, "Do not support expand command ring\n");
2872 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
2873 "ERROR no room on ep ring, try ring expansion");
2874 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2875 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2877 xhci_err(xhci
, "Ring expansion failed\n");
2882 while (trb_is_link(ep_ring
->enqueue
)) {
2883 /* If we're not dealing with 0.95 hardware or isoc rings
2884 * on AMD 0.96 host, clear the chain bit.
2886 if (!xhci_link_trb_quirk(xhci
) &&
2887 !(ep_ring
->type
== TYPE_ISOC
&&
2888 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2889 ep_ring
->enqueue
->link
.control
&=
2890 cpu_to_le32(~TRB_CHAIN
);
2892 ep_ring
->enqueue
->link
.control
|=
2893 cpu_to_le32(TRB_CHAIN
);
2896 ep_ring
->enqueue
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2898 /* Toggle the cycle bit after the last ring segment. */
2899 if (link_trb_toggles_cycle(ep_ring
->enqueue
))
2900 ep_ring
->cycle_state
^= 1;
2902 ep_ring
->enq_seg
= ep_ring
->enq_seg
->next
;
2903 ep_ring
->enqueue
= ep_ring
->enq_seg
->trbs
;
2908 static int prepare_transfer(struct xhci_hcd
*xhci
,
2909 struct xhci_virt_device
*xdev
,
2910 unsigned int ep_index
,
2911 unsigned int stream_id
,
2912 unsigned int num_trbs
,
2914 unsigned int td_index
,
2918 struct urb_priv
*urb_priv
;
2920 struct xhci_ring
*ep_ring
;
2921 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2923 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2925 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2930 ret
= prepare_ring(xhci
, ep_ring
,
2931 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2932 num_trbs
, mem_flags
);
2936 urb_priv
= urb
->hcpriv
;
2937 td
= urb_priv
->td
[td_index
];
2939 INIT_LIST_HEAD(&td
->td_list
);
2940 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2942 if (td_index
== 0) {
2943 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2949 /* Add this TD to the tail of the endpoint ring's TD list */
2950 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2951 td
->start_seg
= ep_ring
->enq_seg
;
2952 td
->first_trb
= ep_ring
->enqueue
;
2954 urb_priv
->td
[td_index
] = td
;
2959 static unsigned int count_trbs(u64 addr
, u64 len
)
2961 unsigned int num_trbs
;
2963 num_trbs
= DIV_ROUND_UP(len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
2971 static inline unsigned int count_trbs_needed(struct urb
*urb
)
2973 return count_trbs(urb
->transfer_dma
, urb
->transfer_buffer_length
);
2976 static unsigned int count_sg_trbs_needed(struct urb
*urb
)
2978 struct scatterlist
*sg
;
2979 unsigned int i
, len
, full_len
, num_trbs
= 0;
2981 full_len
= urb
->transfer_buffer_length
;
2983 for_each_sg(urb
->sg
, sg
, urb
->num_mapped_sgs
, i
) {
2984 len
= sg_dma_len(sg
);
2985 num_trbs
+= count_trbs(sg_dma_address(sg
), len
);
2986 len
= min_t(unsigned int, len
, full_len
);
2995 static unsigned int count_isoc_trbs_needed(struct urb
*urb
, int i
)
2999 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3000 len
= urb
->iso_frame_desc
[i
].length
;
3002 return count_trbs(addr
, len
);
3005 static void check_trb_math(struct urb
*urb
, int running_total
)
3007 if (unlikely(running_total
!= urb
->transfer_buffer_length
))
3008 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3009 "queued %#x (%d), asked for %#x (%d)\n",
3011 urb
->ep
->desc
.bEndpointAddress
,
3012 running_total
, running_total
,
3013 urb
->transfer_buffer_length
,
3014 urb
->transfer_buffer_length
);
3017 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3018 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3019 struct xhci_generic_trb
*start_trb
)
3022 * Pass all the TRBs to the hardware at once and make sure this write
3027 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3029 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3030 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3033 static void check_interval(struct xhci_hcd
*xhci
, struct urb
*urb
,
3034 struct xhci_ep_ctx
*ep_ctx
)
3039 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3040 ep_interval
= urb
->interval
;
3042 /* Convert to microframes */
3043 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3044 urb
->dev
->speed
== USB_SPEED_FULL
)
3047 /* FIXME change this to a warning and a suggestion to use the new API
3048 * to set the polling interval (once the API is added).
3050 if (xhci_interval
!= ep_interval
) {
3051 dev_dbg_ratelimited(&urb
->dev
->dev
,
3052 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3053 ep_interval
, ep_interval
== 1 ? "" : "s",
3054 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3055 urb
->interval
= xhci_interval
;
3056 /* Convert back to frames for LS/FS devices */
3057 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3058 urb
->dev
->speed
== USB_SPEED_FULL
)
3064 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3065 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3066 * (comprised of sg list entries) can take several service intervals to
3069 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3070 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3072 struct xhci_ep_ctx
*ep_ctx
;
3074 ep_ctx
= xhci_get_ep_ctx(xhci
, xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3075 check_interval(xhci
, urb
, ep_ctx
);
3077 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3081 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3082 * packets remaining in the TD (*not* including this TRB).
3084 * Total TD packet count = total_packet_count =
3085 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3087 * Packets transferred up to and including this TRB = packets_transferred =
3088 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3090 * TD size = total_packet_count - packets_transferred
3092 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3093 * including this TRB, right shifted by 10
3095 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3096 * This is taken care of in the TRB_TD_SIZE() macro
3098 * The last TRB in a TD must have the TD size set to zero.
3100 static u32
xhci_td_remainder(struct xhci_hcd
*xhci
, int transferred
,
3101 int trb_buff_len
, unsigned int td_total_len
,
3102 struct urb
*urb
, bool more_trbs_coming
)
3104 u32 maxp
, total_packet_count
;
3106 /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
3107 if (xhci
->hci_version
< 0x100 && !(xhci
->quirks
& XHCI_MTK_HOST
))
3108 return ((td_total_len
- transferred
) >> 10);
3110 /* One TRB with a zero-length data packet. */
3111 if (!more_trbs_coming
|| (transferred
== 0 && trb_buff_len
== 0) ||
3112 trb_buff_len
== td_total_len
)
3115 /* for MTK xHCI, TD size doesn't include this TRB */
3116 if (xhci
->quirks
& XHCI_MTK_HOST
)
3119 maxp
= GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3120 total_packet_count
= DIV_ROUND_UP(td_total_len
, maxp
);
3122 /* Queueing functions don't count the current TRB into transferred */
3123 return (total_packet_count
- ((transferred
+ trb_buff_len
) / maxp
));
3127 static int xhci_align_td(struct xhci_hcd
*xhci
, struct urb
*urb
, u32 enqd_len
,
3128 u32
*trb_buff_len
, struct xhci_segment
*seg
)
3130 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
3131 unsigned int unalign
;
3132 unsigned int max_pkt
;
3135 max_pkt
= GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3136 unalign
= (enqd_len
+ *trb_buff_len
) % max_pkt
;
3138 /* we got lucky, last normal TRB data on segment is packet aligned */
3142 xhci_dbg(xhci
, "Unaligned %d bytes, buff len %d\n",
3143 unalign
, *trb_buff_len
);
3145 /* is the last nornal TRB alignable by splitting it */
3146 if (*trb_buff_len
> unalign
) {
3147 *trb_buff_len
-= unalign
;
3148 xhci_dbg(xhci
, "split align, new buff len %d\n", *trb_buff_len
);
3153 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3154 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3155 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3157 new_buff_len
= max_pkt
- (enqd_len
% max_pkt
);
3159 if (new_buff_len
> (urb
->transfer_buffer_length
- enqd_len
))
3160 new_buff_len
= (urb
->transfer_buffer_length
- enqd_len
);
3162 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3163 if (usb_urb_dir_out(urb
)) {
3164 sg_pcopy_to_buffer(urb
->sg
, urb
->num_mapped_sgs
,
3165 seg
->bounce_buf
, new_buff_len
, enqd_len
);
3166 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3167 max_pkt
, DMA_TO_DEVICE
);
3169 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3170 max_pkt
, DMA_FROM_DEVICE
);
3173 if (dma_mapping_error(dev
, seg
->bounce_dma
)) {
3174 /* try without aligning. Some host controllers survive */
3175 xhci_warn(xhci
, "Failed mapping bounce buffer, not aligning\n");
3178 *trb_buff_len
= new_buff_len
;
3179 seg
->bounce_len
= new_buff_len
;
3180 seg
->bounce_offs
= enqd_len
;
3182 xhci_dbg(xhci
, "Bounce align, new buff len %d\n", *trb_buff_len
);
3187 /* This is very similar to what ehci-q.c qtd_fill() does */
3188 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3189 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3191 struct xhci_ring
*ring
;
3192 struct urb_priv
*urb_priv
;
3194 struct xhci_generic_trb
*start_trb
;
3195 struct scatterlist
*sg
= NULL
;
3196 bool more_trbs_coming
= true;
3197 bool need_zero_pkt
= false;
3198 bool first_trb
= true;
3199 unsigned int num_trbs
;
3200 unsigned int start_cycle
, num_sgs
= 0;
3201 unsigned int enqd_len
, block_len
, trb_buff_len
, full_len
;
3203 u32 field
, length_field
, remainder
;
3204 u64 addr
, send_addr
;
3206 ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3210 full_len
= urb
->transfer_buffer_length
;
3211 /* If we have scatter/gather list, we use it. */
3213 num_sgs
= urb
->num_mapped_sgs
;
3215 addr
= (u64
) sg_dma_address(sg
);
3216 block_len
= sg_dma_len(sg
);
3217 num_trbs
= count_sg_trbs_needed(urb
);
3219 num_trbs
= count_trbs_needed(urb
);
3220 addr
= (u64
) urb
->transfer_dma
;
3221 block_len
= full_len
;
3223 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3224 ep_index
, urb
->stream_id
,
3225 num_trbs
, urb
, 0, mem_flags
);
3226 if (unlikely(ret
< 0))
3229 urb_priv
= urb
->hcpriv
;
3231 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3232 if (urb
->transfer_flags
& URB_ZERO_PACKET
&& urb_priv
->length
> 1)
3233 need_zero_pkt
= true;
3235 td
= urb_priv
->td
[0];
3238 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3239 * until we've finished creating all the other TRBs. The ring's cycle
3240 * state may change as we enqueue the other TRBs, so save it too.
3242 start_trb
= &ring
->enqueue
->generic
;
3243 start_cycle
= ring
->cycle_state
;
3246 /* Queue the TRBs, even if they are zero-length */
3247 for (enqd_len
= 0; first_trb
|| enqd_len
< full_len
;
3248 enqd_len
+= trb_buff_len
) {
3249 field
= TRB_TYPE(TRB_NORMAL
);
3251 /* TRB buffer should not cross 64KB boundaries */
3252 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3253 trb_buff_len
= min_t(unsigned int, trb_buff_len
, block_len
);
3255 if (enqd_len
+ trb_buff_len
> full_len
)
3256 trb_buff_len
= full_len
- enqd_len
;
3258 /* Don't change the cycle bit of the first TRB until later */
3261 if (start_cycle
== 0)
3264 field
|= ring
->cycle_state
;
3266 /* Chain all the TRBs together; clear the chain bit in the last
3267 * TRB to indicate it's the last TRB in the chain.
3269 if (enqd_len
+ trb_buff_len
< full_len
) {
3271 if (trb_is_link(ring
->enqueue
+ 1)) {
3272 if (xhci_align_td(xhci
, urb
, enqd_len
,
3275 send_addr
= ring
->enq_seg
->bounce_dma
;
3276 /* assuming TD won't span 2 segs */
3277 td
->bounce_seg
= ring
->enq_seg
;
3281 if (enqd_len
+ trb_buff_len
>= full_len
) {
3282 field
&= ~TRB_CHAIN
;
3284 more_trbs_coming
= false;
3285 td
->last_trb
= ring
->enqueue
;
3288 /* Only set interrupt on short packet for IN endpoints */
3289 if (usb_urb_dir_in(urb
))
3292 /* Set the TRB length, TD size, and interrupter fields. */
3293 remainder
= xhci_td_remainder(xhci
, enqd_len
, trb_buff_len
,
3294 full_len
, urb
, more_trbs_coming
);
3296 length_field
= TRB_LEN(trb_buff_len
) |
3297 TRB_TD_SIZE(remainder
) |
3300 queue_trb(xhci
, ring
, more_trbs_coming
| need_zero_pkt
,
3301 lower_32_bits(send_addr
),
3302 upper_32_bits(send_addr
),
3306 addr
+= trb_buff_len
;
3307 sent_len
= trb_buff_len
;
3309 while (sg
&& sent_len
>= block_len
) {
3312 sent_len
-= block_len
;
3315 block_len
= sg_dma_len(sg
);
3316 addr
= (u64
) sg_dma_address(sg
);
3320 block_len
-= sent_len
;
3324 if (need_zero_pkt
) {
3325 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3326 ep_index
, urb
->stream_id
,
3327 1, urb
, 1, mem_flags
);
3328 urb_priv
->td
[1]->last_trb
= ring
->enqueue
;
3329 field
= TRB_TYPE(TRB_NORMAL
) | ring
->cycle_state
| TRB_IOC
;
3330 queue_trb(xhci
, ring
, 0, 0, 0, TRB_INTR_TARGET(0), field
);
3333 check_trb_math(urb
, enqd_len
);
3334 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3335 start_cycle
, start_trb
);
3339 /* Caller must have locked xhci->lock */
3340 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3341 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3343 struct xhci_ring
*ep_ring
;
3346 struct usb_ctrlrequest
*setup
;
3347 struct xhci_generic_trb
*start_trb
;
3349 u32 field
, length_field
, remainder
;
3350 struct urb_priv
*urb_priv
;
3353 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3358 * Need to copy setup packet into setup TRB, so we can't use the setup
3361 if (!urb
->setup_packet
)
3364 /* 1 TRB for setup, 1 for status */
3367 * Don't need to check if we need additional event data and normal TRBs,
3368 * since data in control transfers will never get bigger than 16MB
3369 * XXX: can we get a buffer that crosses 64KB boundaries?
3371 if (urb
->transfer_buffer_length
> 0)
3373 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3374 ep_index
, urb
->stream_id
,
3375 num_trbs
, urb
, 0, mem_flags
);
3379 urb_priv
= urb
->hcpriv
;
3380 td
= urb_priv
->td
[0];
3383 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3384 * until we've finished creating all the other TRBs. The ring's cycle
3385 * state may change as we enqueue the other TRBs, so save it too.
3387 start_trb
= &ep_ring
->enqueue
->generic
;
3388 start_cycle
= ep_ring
->cycle_state
;
3390 /* Queue setup TRB - see section 6.4.1.2.1 */
3391 /* FIXME better way to translate setup_packet into two u32 fields? */
3392 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3394 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3395 if (start_cycle
== 0)
3398 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3399 if ((xhci
->hci_version
>= 0x100) || (xhci
->quirks
& XHCI_MTK_HOST
)) {
3400 if (urb
->transfer_buffer_length
> 0) {
3401 if (setup
->bRequestType
& USB_DIR_IN
)
3402 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3404 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3408 queue_trb(xhci
, ep_ring
, true,
3409 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3410 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3411 TRB_LEN(8) | TRB_INTR_TARGET(0),
3412 /* Immediate data in pointer */
3415 /* If there's data, queue data TRBs */
3416 /* Only set interrupt on short packet for IN endpoints */
3417 if (usb_urb_dir_in(urb
))
3418 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3420 field
= TRB_TYPE(TRB_DATA
);
3422 remainder
= xhci_td_remainder(xhci
, 0,
3423 urb
->transfer_buffer_length
,
3424 urb
->transfer_buffer_length
,
3427 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3428 TRB_TD_SIZE(remainder
) |
3431 if (urb
->transfer_buffer_length
> 0) {
3432 if (setup
->bRequestType
& USB_DIR_IN
)
3433 field
|= TRB_DIR_IN
;
3434 queue_trb(xhci
, ep_ring
, true,
3435 lower_32_bits(urb
->transfer_dma
),
3436 upper_32_bits(urb
->transfer_dma
),
3438 field
| ep_ring
->cycle_state
);
3441 /* Save the DMA address of the last TRB in the TD */
3442 td
->last_trb
= ep_ring
->enqueue
;
3444 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3445 /* If the device sent data, the status stage is an OUT transfer */
3446 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3450 queue_trb(xhci
, ep_ring
, false,
3454 /* Event on completion */
3455 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3457 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3458 start_cycle
, start_trb
);
3463 * The transfer burst count field of the isochronous TRB defines the number of
3464 * bursts that are required to move all packets in this TD. Only SuperSpeed
3465 * devices can burst up to bMaxBurst number of packets per service interval.
3466 * This field is zero based, meaning a value of zero in the field means one
3467 * burst. Basically, for everything but SuperSpeed devices, this field will be
3468 * zero. Only xHCI 1.0 host controllers support this field.
3470 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3471 struct urb
*urb
, unsigned int total_packet_count
)
3473 unsigned int max_burst
;
3475 if (xhci
->hci_version
< 0x100 || urb
->dev
->speed
< USB_SPEED_SUPER
)
3478 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3479 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3483 * Returns the number of packets in the last "burst" of packets. This field is
3484 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3485 * the last burst packet count is equal to the total number of packets in the
3486 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3487 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3488 * contain 1 to (bMaxBurst + 1) packets.
3490 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3491 struct urb
*urb
, unsigned int total_packet_count
)
3493 unsigned int max_burst
;
3494 unsigned int residue
;
3496 if (xhci
->hci_version
< 0x100)
3499 if (urb
->dev
->speed
>= USB_SPEED_SUPER
) {
3500 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3501 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3502 residue
= total_packet_count
% (max_burst
+ 1);
3503 /* If residue is zero, the last burst contains (max_burst + 1)
3504 * number of packets, but the TLBPC field is zero-based.
3510 if (total_packet_count
== 0)
3512 return total_packet_count
- 1;
3516 * Calculates Frame ID field of the isochronous TRB identifies the
3517 * target frame that the Interval associated with this Isochronous
3518 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3520 * Returns actual frame id on success, negative value on error.
3522 static int xhci_get_isoc_frame_id(struct xhci_hcd
*xhci
,
3523 struct urb
*urb
, int index
)
3525 int start_frame
, ist
, ret
= 0;
3526 int start_frame_id
, end_frame_id
, current_frame_id
;
3528 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3529 urb
->dev
->speed
== USB_SPEED_FULL
)
3530 start_frame
= urb
->start_frame
+ index
* urb
->interval
;
3532 start_frame
= (urb
->start_frame
+ index
* urb
->interval
) >> 3;
3534 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3536 * If bit [3] of IST is cleared to '0', software can add a TRB no
3537 * later than IST[2:0] Microframes before that TRB is scheduled to
3539 * If bit [3] of IST is set to '1', software can add a TRB no later
3540 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3542 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3543 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3546 /* Software shall not schedule an Isoch TD with a Frame ID value that
3547 * is less than the Start Frame ID or greater than the End Frame ID,
3550 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3551 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3553 * Both the End Frame ID and Start Frame ID values are calculated
3554 * in microframes. When software determines the valid Frame ID value;
3555 * The End Frame ID value should be rounded down to the nearest Frame
3556 * boundary, and the Start Frame ID value should be rounded up to the
3557 * nearest Frame boundary.
3559 current_frame_id
= readl(&xhci
->run_regs
->microframe_index
);
3560 start_frame_id
= roundup(current_frame_id
+ ist
+ 1, 8);
3561 end_frame_id
= rounddown(current_frame_id
+ 895 * 8, 8);
3563 start_frame
&= 0x7ff;
3564 start_frame_id
= (start_frame_id
>> 3) & 0x7ff;
3565 end_frame_id
= (end_frame_id
>> 3) & 0x7ff;
3567 xhci_dbg(xhci
, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3568 __func__
, index
, readl(&xhci
->run_regs
->microframe_index
),
3569 start_frame_id
, end_frame_id
, start_frame
);
3571 if (start_frame_id
< end_frame_id
) {
3572 if (start_frame
> end_frame_id
||
3573 start_frame
< start_frame_id
)
3575 } else if (start_frame_id
> end_frame_id
) {
3576 if ((start_frame
> end_frame_id
&&
3577 start_frame
< start_frame_id
))
3584 if (ret
== -EINVAL
|| start_frame
== start_frame_id
) {
3585 start_frame
= start_frame_id
+ 1;
3586 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3587 urb
->dev
->speed
== USB_SPEED_FULL
)
3588 urb
->start_frame
= start_frame
;
3590 urb
->start_frame
= start_frame
<< 3;
3596 xhci_warn(xhci
, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3597 start_frame
, current_frame_id
, index
,
3598 start_frame_id
, end_frame_id
);
3599 xhci_warn(xhci
, "Ignore frame ID field, use SIA bit instead\n");
3606 /* This is for isoc transfer */
3607 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3608 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3610 struct xhci_ring
*ep_ring
;
3611 struct urb_priv
*urb_priv
;
3613 int num_tds
, trbs_per_td
;
3614 struct xhci_generic_trb
*start_trb
;
3617 u32 field
, length_field
;
3618 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3619 u64 start_addr
, addr
;
3621 bool more_trbs_coming
;
3622 struct xhci_virt_ep
*xep
;
3625 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3626 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3628 num_tds
= urb
->number_of_packets
;
3630 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3633 start_addr
= (u64
) urb
->transfer_dma
;
3634 start_trb
= &ep_ring
->enqueue
->generic
;
3635 start_cycle
= ep_ring
->cycle_state
;
3637 urb_priv
= urb
->hcpriv
;
3638 /* Queue the TRBs for each TD, even if they are zero-length */
3639 for (i
= 0; i
< num_tds
; i
++) {
3640 unsigned int total_pkt_count
, max_pkt
;
3641 unsigned int burst_count
, last_burst_pkt_count
;
3646 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3647 td_len
= urb
->iso_frame_desc
[i
].length
;
3648 td_remain_len
= td_len
;
3649 max_pkt
= GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3650 total_pkt_count
= DIV_ROUND_UP(td_len
, max_pkt
);
3652 /* A zero-length transfer still involves at least one packet. */
3653 if (total_pkt_count
== 0)
3655 burst_count
= xhci_get_burst_count(xhci
, urb
, total_pkt_count
);
3656 last_burst_pkt_count
= xhci_get_last_burst_packet_count(xhci
,
3657 urb
, total_pkt_count
);
3659 trbs_per_td
= count_isoc_trbs_needed(urb
, i
);
3661 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3662 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3668 td
= urb_priv
->td
[i
];
3670 /* use SIA as default, if frame id is used overwrite it */
3671 sia_frame_id
= TRB_SIA
;
3672 if (!(urb
->transfer_flags
& URB_ISO_ASAP
) &&
3673 HCC_CFC(xhci
->hcc_params
)) {
3674 frame_id
= xhci_get_isoc_frame_id(xhci
, urb
, i
);
3676 sia_frame_id
= TRB_FRAME_ID(frame_id
);
3679 * Set isoc specific data for the first TRB in a TD.
3680 * Prevent HW from getting the TRBs by keeping the cycle state
3681 * inverted in the first TDs isoc TRB.
3683 field
= TRB_TYPE(TRB_ISOC
) |
3684 TRB_TLBPC(last_burst_pkt_count
) |
3686 (i
? ep_ring
->cycle_state
: !start_cycle
);
3688 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3689 if (!xep
->use_extended_tbc
)
3690 field
|= TRB_TBC(burst_count
);
3692 /* fill the rest of the TRB fields, and remaining normal TRBs */
3693 for (j
= 0; j
< trbs_per_td
; j
++) {
3696 /* only first TRB is isoc, overwrite otherwise */
3698 field
= TRB_TYPE(TRB_NORMAL
) |
3699 ep_ring
->cycle_state
;
3701 /* Only set interrupt on short packet for IN EPs */
3702 if (usb_urb_dir_in(urb
))
3705 /* Set the chain bit for all except the last TRB */
3706 if (j
< trbs_per_td
- 1) {
3707 more_trbs_coming
= true;
3710 more_trbs_coming
= false;
3711 td
->last_trb
= ep_ring
->enqueue
;
3713 /* set BEI, except for the last TD */
3714 if (xhci
->hci_version
>= 0x100 &&
3715 !(xhci
->quirks
& XHCI_AVOID_BEI
) &&
3719 /* Calculate TRB length */
3720 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3721 if (trb_buff_len
> td_remain_len
)
3722 trb_buff_len
= td_remain_len
;
3724 /* Set the TRB length, TD size, & interrupter fields. */
3725 remainder
= xhci_td_remainder(xhci
, running_total
,
3726 trb_buff_len
, td_len
,
3727 urb
, more_trbs_coming
);
3729 length_field
= TRB_LEN(trb_buff_len
) |
3732 /* xhci 1.1 with ETE uses TD Size field for TBC */
3733 if (first_trb
&& xep
->use_extended_tbc
)
3734 length_field
|= TRB_TD_SIZE_TBC(burst_count
);
3736 length_field
|= TRB_TD_SIZE(remainder
);
3739 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3740 lower_32_bits(addr
),
3741 upper_32_bits(addr
),
3744 running_total
+= trb_buff_len
;
3746 addr
+= trb_buff_len
;
3747 td_remain_len
-= trb_buff_len
;
3750 /* Check TD length */
3751 if (running_total
!= td_len
) {
3752 xhci_err(xhci
, "ISOC TD length unmatch\n");
3758 /* store the next frame id */
3759 if (HCC_CFC(xhci
->hcc_params
))
3760 xep
->next_frame_id
= urb
->start_frame
+ num_tds
* urb
->interval
;
3762 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3763 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3764 usb_amd_quirk_pll_disable();
3766 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3768 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3769 start_cycle
, start_trb
);
3772 /* Clean up a partially enqueued isoc transfer. */
3774 for (i
--; i
>= 0; i
--)
3775 list_del_init(&urb_priv
->td
[i
]->td_list
);
3777 /* Use the first TD as a temporary variable to turn the TDs we've queued
3778 * into No-ops with a software-owned cycle bit. That way the hardware
3779 * won't accidentally start executing bogus TDs when we partially
3780 * overwrite them. td->first_trb and td->start_seg are already set.
3782 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3783 /* Every TRB except the first & last will have its cycle bit flipped. */
3784 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3786 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3787 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3788 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3789 ep_ring
->cycle_state
= start_cycle
;
3790 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3791 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3796 * Check transfer ring to guarantee there is enough room for the urb.
3797 * Update ISO URB start_frame and interval.
3798 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3799 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3800 * Contiguous Frame ID is not supported by HC.
3802 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3803 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3805 struct xhci_virt_device
*xdev
;
3806 struct xhci_ring
*ep_ring
;
3807 struct xhci_ep_ctx
*ep_ctx
;
3809 int num_tds
, num_trbs
, i
;
3811 struct xhci_virt_ep
*xep
;
3814 xdev
= xhci
->devs
[slot_id
];
3815 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3816 ep_ring
= xdev
->eps
[ep_index
].ring
;
3817 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3820 num_tds
= urb
->number_of_packets
;
3821 for (i
= 0; i
< num_tds
; i
++)
3822 num_trbs
+= count_isoc_trbs_needed(urb
, i
);
3824 /* Check the ring to guarantee there is enough room for the whole urb.
3825 * Do not insert any td of the urb to the ring if the check failed.
3827 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3828 num_trbs
, mem_flags
);
3833 * Check interval value. This should be done before we start to
3834 * calculate the start frame value.
3836 check_interval(xhci
, urb
, ep_ctx
);
3838 /* Calculate the start frame and put it in urb->start_frame. */
3839 if (HCC_CFC(xhci
->hcc_params
) && !list_empty(&ep_ring
->td_list
)) {
3840 if ((le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
3842 urb
->start_frame
= xep
->next_frame_id
;
3843 goto skip_start_over
;
3847 start_frame
= readl(&xhci
->run_regs
->microframe_index
);
3848 start_frame
&= 0x3fff;
3850 * Round up to the next frame and consider the time before trb really
3851 * gets scheduled by hardare.
3853 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3854 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3856 start_frame
+= ist
+ XHCI_CFC_DELAY
;
3857 start_frame
= roundup(start_frame
, 8);
3860 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3861 * is greate than 8 microframes.
3863 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3864 urb
->dev
->speed
== USB_SPEED_FULL
) {
3865 start_frame
= roundup(start_frame
, urb
->interval
<< 3);
3866 urb
->start_frame
= start_frame
>> 3;
3868 start_frame
= roundup(start_frame
, urb
->interval
);
3869 urb
->start_frame
= start_frame
;
3873 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3875 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3878 /**** Command Ring Operations ****/
3880 /* Generic function for queueing a command TRB on the command ring.
3881 * Check to make sure there's room on the command ring for one command TRB.
3882 * Also check that there's room reserved for commands that must not fail.
3883 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3884 * then only check for the number of reserved spots.
3885 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3886 * because the command event handler may want to resubmit a failed command.
3888 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3889 u32 field1
, u32 field2
,
3890 u32 field3
, u32 field4
, bool command_must_succeed
)
3892 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3895 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3896 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3897 xhci_dbg(xhci
, "xHCI dying or halted, can't queue_command\n");
3901 if (!command_must_succeed
)
3904 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3905 reserved_trbs
, GFP_ATOMIC
);
3907 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3908 if (command_must_succeed
)
3909 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3910 "unfailable commands failed.\n");
3914 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
3915 list_add_tail(&cmd
->cmd_list
, &xhci
->cmd_list
);
3917 /* if there are no other commands queued we start the timeout timer */
3918 if (xhci
->cmd_list
.next
== &cmd
->cmd_list
&&
3919 !timer_pending(&xhci
->cmd_timer
)) {
3920 xhci
->current_cmd
= cmd
;
3921 mod_timer(&xhci
->cmd_timer
, jiffies
+ XHCI_CMD_DEFAULT_TIMEOUT
);
3924 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3925 field4
| xhci
->cmd_ring
->cycle_state
);
3929 /* Queue a slot enable or disable request on the command ring */
3930 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3931 u32 trb_type
, u32 slot_id
)
3933 return queue_command(xhci
, cmd
, 0, 0, 0,
3934 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3937 /* Queue an address device command TRB */
3938 int xhci_queue_address_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3939 dma_addr_t in_ctx_ptr
, u32 slot_id
, enum xhci_setup_dev setup
)
3941 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3942 upper_32_bits(in_ctx_ptr
), 0,
3943 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
)
3944 | (setup
== SETUP_CONTEXT_ONLY
? TRB_BSR
: 0), false);
3947 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3948 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3950 return queue_command(xhci
, cmd
, field1
, field2
, field3
, field4
, false);
3953 /* Queue a reset device command TRB */
3954 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3957 return queue_command(xhci
, cmd
, 0, 0, 0,
3958 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3962 /* Queue a configure endpoint command TRB */
3963 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
,
3964 struct xhci_command
*cmd
, dma_addr_t in_ctx_ptr
,
3965 u32 slot_id
, bool command_must_succeed
)
3967 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3968 upper_32_bits(in_ctx_ptr
), 0,
3969 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3970 command_must_succeed
);
3973 /* Queue an evaluate context command TRB */
3974 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3975 dma_addr_t in_ctx_ptr
, u32 slot_id
, bool command_must_succeed
)
3977 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
3978 upper_32_bits(in_ctx_ptr
), 0,
3979 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3980 command_must_succeed
);
3984 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3985 * activity on an endpoint that is about to be suspended.
3987 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
3988 int slot_id
, unsigned int ep_index
, int suspend
)
3990 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3991 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3992 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3993 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3995 return queue_command(xhci
, cmd
, 0, 0, 0,
3996 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3999 /* Set Transfer Ring Dequeue Pointer command */
4000 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
4001 unsigned int slot_id
, unsigned int ep_index
,
4002 unsigned int stream_id
,
4003 struct xhci_dequeue_state
*deq_state
)
4006 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4007 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4008 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
4010 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
4011 struct xhci_virt_ep
*ep
;
4012 struct xhci_command
*cmd
;
4015 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
4016 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4017 deq_state
->new_deq_seg
,
4018 (unsigned long long)deq_state
->new_deq_seg
->dma
,
4019 deq_state
->new_deq_ptr
,
4020 (unsigned long long)xhci_trb_virt_to_dma(
4021 deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
4022 deq_state
->new_cycle_state
);
4024 addr
= xhci_trb_virt_to_dma(deq_state
->new_deq_seg
,
4025 deq_state
->new_deq_ptr
);
4027 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4028 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
4029 deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
);
4032 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4033 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
4034 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4035 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
4039 /* This function gets called from contexts where it cannot sleep */
4040 cmd
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
4042 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4046 ep
->queued_deq_seg
= deq_state
->new_deq_seg
;
4047 ep
->queued_deq_ptr
= deq_state
->new_deq_ptr
;
4049 trb_sct
= SCT_FOR_TRB(SCT_PRI_TR
);
4050 ret
= queue_command(xhci
, cmd
,
4051 lower_32_bits(addr
) | trb_sct
| deq_state
->new_cycle_state
,
4052 upper_32_bits(addr
), trb_stream_id
,
4053 trb_slot_id
| trb_ep_index
| type
, false);
4055 xhci_free_command(xhci
, cmd
);
4059 /* Stop the TD queueing code from ringing the doorbell until
4060 * this command completes. The HC won't set the dequeue pointer
4061 * if the ring is running, and ringing the doorbell starts the
4064 ep
->ep_state
|= SET_DEQ_PENDING
;
4067 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4068 int slot_id
, unsigned int ep_index
)
4070 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4071 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4072 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4074 return queue_command(xhci
, cmd
, 0, 0, 0,
4075 trb_slot_id
| trb_ep_index
| type
, false);