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[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
228
229 /*
230 * Load an endpoint's FIFO
231 */
232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
233 {
234 struct musb *musb = hw_ep->musb;
235 void __iomem *fifo = hw_ep->fifo;
236
237 if (unlikely(len == 0))
238 return;
239
240 prefetch((u8 *)src);
241
242 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
243 'T', hw_ep->epnum, fifo, len, src);
244
245 /* we can't assume unaligned reads work */
246 if (likely((0x01 & (unsigned long) src) == 0)) {
247 u16 index = 0;
248
249 /* best case is 32bit-aligned source address */
250 if ((0x02 & (unsigned long) src) == 0) {
251 if (len >= 4) {
252 iowrite32_rep(fifo, src + index, len >> 2);
253 index += len & ~0x03;
254 }
255 if (len & 0x02) {
256 musb_writew(fifo, 0, *(u16 *)&src[index]);
257 index += 2;
258 }
259 } else {
260 if (len >= 2) {
261 iowrite16_rep(fifo, src + index, len >> 1);
262 index += len & ~0x01;
263 }
264 }
265 if (len & 0x01)
266 musb_writeb(fifo, 0, src[index]);
267 } else {
268 /* byte aligned */
269 iowrite8_rep(fifo, src, len);
270 }
271 }
272
273 #if !defined(CONFIG_USB_MUSB_AM35X)
274 /*
275 * Unload an endpoint's FIFO
276 */
277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
278 {
279 struct musb *musb = hw_ep->musb;
280 void __iomem *fifo = hw_ep->fifo;
281
282 if (unlikely(len == 0))
283 return;
284
285 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
286 'R', hw_ep->epnum, fifo, len, dst);
287
288 /* we can't assume unaligned writes work */
289 if (likely((0x01 & (unsigned long) dst) == 0)) {
290 u16 index = 0;
291
292 /* best case is 32bit-aligned destination address */
293 if ((0x02 & (unsigned long) dst) == 0) {
294 if (len >= 4) {
295 ioread32_rep(fifo, dst, len >> 2);
296 index = len & ~0x03;
297 }
298 if (len & 0x02) {
299 *(u16 *)&dst[index] = musb_readw(fifo, 0);
300 index += 2;
301 }
302 } else {
303 if (len >= 2) {
304 ioread16_rep(fifo, dst, len >> 1);
305 index = len & ~0x01;
306 }
307 }
308 if (len & 0x01)
309 dst[index] = musb_readb(fifo, 0);
310 } else {
311 /* byte aligned */
312 ioread8_rep(fifo, dst, len);
313 }
314 }
315 #endif
316
317 #endif /* normal PIO */
318
319
320 /*-------------------------------------------------------------------------*/
321
322 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
323 static const u8 musb_test_packet[53] = {
324 /* implicit SYNC then DATA0 to start */
325
326 /* JKJKJKJK x9 */
327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328 /* JJKKJJKK x8 */
329 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
330 /* JJJJKKKK x8 */
331 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332 /* JJJJJJJKKKKKKK x8 */
333 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
334 /* JJJJJJJK x8 */
335 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336 /* JKKKKKKK x10, JK */
337 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
338
339 /* implicit CRC16 then EOP to end */
340 };
341
342 void musb_load_testpacket(struct musb *musb)
343 {
344 void __iomem *regs = musb->endpoints[0].regs;
345
346 musb_ep_select(musb->mregs, 0);
347 musb_write_fifo(musb->control_ep,
348 sizeof(musb_test_packet), musb_test_packet);
349 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
350 }
351
352 /*-------------------------------------------------------------------------*/
353
354 /*
355 * Handles OTG hnp timeouts, such as b_ase0_brst
356 */
357 static void musb_otg_timer_func(unsigned long data)
358 {
359 struct musb *musb = (struct musb *)data;
360 unsigned long flags;
361
362 spin_lock_irqsave(&musb->lock, flags);
363 switch (musb->xceiv->otg->state) {
364 case OTG_STATE_B_WAIT_ACON:
365 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
366 musb_g_disconnect(musb);
367 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
368 musb->is_active = 0;
369 break;
370 case OTG_STATE_A_SUSPEND:
371 case OTG_STATE_A_WAIT_BCON:
372 dev_dbg(musb->controller, "HNP: %s timeout\n",
373 usb_otg_state_string(musb->xceiv->otg->state));
374 musb_platform_set_vbus(musb, 0);
375 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
376 break;
377 default:
378 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
379 usb_otg_state_string(musb->xceiv->otg->state));
380 }
381 spin_unlock_irqrestore(&musb->lock, flags);
382 }
383
384 /*
385 * Stops the HNP transition. Caller must take care of locking.
386 */
387 void musb_hnp_stop(struct musb *musb)
388 {
389 struct usb_hcd *hcd = musb->hcd;
390 void __iomem *mbase = musb->mregs;
391 u8 reg;
392
393 dev_dbg(musb->controller, "HNP: stop from %s\n",
394 usb_otg_state_string(musb->xceiv->otg->state));
395
396 switch (musb->xceiv->otg->state) {
397 case OTG_STATE_A_PERIPHERAL:
398 musb_g_disconnect(musb);
399 dev_dbg(musb->controller, "HNP: back to %s\n",
400 usb_otg_state_string(musb->xceiv->otg->state));
401 break;
402 case OTG_STATE_B_HOST:
403 dev_dbg(musb->controller, "HNP: Disabling HR\n");
404 if (hcd)
405 hcd->self.is_b_host = 0;
406 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
407 MUSB_DEV_MODE(musb);
408 reg = musb_readb(mbase, MUSB_POWER);
409 reg |= MUSB_POWER_SUSPENDM;
410 musb_writeb(mbase, MUSB_POWER, reg);
411 /* REVISIT: Start SESSION_REQUEST here? */
412 break;
413 default:
414 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
415 usb_otg_state_string(musb->xceiv->otg->state));
416 }
417
418 /*
419 * When returning to A state after HNP, avoid hub_port_rebounce(),
420 * which cause occasional OPT A "Did not receive reset after connect"
421 * errors.
422 */
423 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
424 }
425
426 /*
427 * Interrupt Service Routine to record USB "global" interrupts.
428 * Since these do not happen often and signify things of
429 * paramount importance, it seems OK to check them individually;
430 * the order of the tests is specified in the manual
431 *
432 * @param musb instance pointer
433 * @param int_usb register contents
434 * @param devctl
435 * @param power
436 */
437
438 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
439 u8 devctl)
440 {
441 irqreturn_t handled = IRQ_NONE;
442
443 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
444 int_usb);
445
446 /* in host mode, the peripheral may issue remote wakeup.
447 * in peripheral mode, the host may resume the link.
448 * spurious RESUME irqs happen too, paired with SUSPEND.
449 */
450 if (int_usb & MUSB_INTR_RESUME) {
451 handled = IRQ_HANDLED;
452 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
453
454 if (devctl & MUSB_DEVCTL_HM) {
455 void __iomem *mbase = musb->mregs;
456 u8 power;
457
458 switch (musb->xceiv->otg->state) {
459 case OTG_STATE_A_SUSPEND:
460 /* remote wakeup? later, GetPortStatus
461 * will stop RESUME signaling
462 */
463
464 power = musb_readb(musb->mregs, MUSB_POWER);
465 if (power & MUSB_POWER_SUSPENDM) {
466 /* spurious */
467 musb->int_usb &= ~MUSB_INTR_SUSPEND;
468 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
469 break;
470 }
471
472 power &= ~MUSB_POWER_SUSPENDM;
473 musb_writeb(mbase, MUSB_POWER,
474 power | MUSB_POWER_RESUME);
475
476 musb->port1_status |=
477 (USB_PORT_STAT_C_SUSPEND << 16)
478 | MUSB_PORT_STAT_RESUME;
479 musb->rh_timer = jiffies
480 + msecs_to_jiffies(20);
481 musb->need_finish_resume = 1;
482
483 musb->xceiv->otg->state = OTG_STATE_A_HOST;
484 musb->is_active = 1;
485 break;
486 case OTG_STATE_B_WAIT_ACON:
487 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
488 musb->is_active = 1;
489 MUSB_DEV_MODE(musb);
490 break;
491 default:
492 WARNING("bogus %s RESUME (%s)\n",
493 "host",
494 usb_otg_state_string(musb->xceiv->otg->state));
495 }
496 } else {
497 switch (musb->xceiv->otg->state) {
498 case OTG_STATE_A_SUSPEND:
499 /* possibly DISCONNECT is upcoming */
500 musb->xceiv->otg->state = OTG_STATE_A_HOST;
501 musb_host_resume_root_hub(musb);
502 break;
503 case OTG_STATE_B_WAIT_ACON:
504 case OTG_STATE_B_PERIPHERAL:
505 /* disconnect while suspended? we may
506 * not get a disconnect irq...
507 */
508 if ((devctl & MUSB_DEVCTL_VBUS)
509 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
510 ) {
511 musb->int_usb |= MUSB_INTR_DISCONNECT;
512 musb->int_usb &= ~MUSB_INTR_SUSPEND;
513 break;
514 }
515 musb_g_resume(musb);
516 break;
517 case OTG_STATE_B_IDLE:
518 musb->int_usb &= ~MUSB_INTR_SUSPEND;
519 break;
520 default:
521 WARNING("bogus %s RESUME (%s)\n",
522 "peripheral",
523 usb_otg_state_string(musb->xceiv->otg->state));
524 }
525 }
526 }
527
528 /* see manual for the order of the tests */
529 if (int_usb & MUSB_INTR_SESSREQ) {
530 void __iomem *mbase = musb->mregs;
531
532 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
533 && (devctl & MUSB_DEVCTL_BDEVICE)) {
534 dev_dbg(musb->controller, "SessReq while on B state\n");
535 return IRQ_HANDLED;
536 }
537
538 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
539 usb_otg_state_string(musb->xceiv->otg->state));
540
541 /* IRQ arrives from ID pin sense or (later, if VBUS power
542 * is removed) SRP. responses are time critical:
543 * - turn on VBUS (with silicon-specific mechanism)
544 * - go through A_WAIT_VRISE
545 * - ... to A_WAIT_BCON.
546 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
547 */
548 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
549 musb->ep0_stage = MUSB_EP0_START;
550 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
551 MUSB_HST_MODE(musb);
552 musb_platform_set_vbus(musb, 1);
553
554 handled = IRQ_HANDLED;
555 }
556
557 if (int_usb & MUSB_INTR_VBUSERROR) {
558 int ignore = 0;
559
560 /* During connection as an A-Device, we may see a short
561 * current spikes causing voltage drop, because of cable
562 * and peripheral capacitance combined with vbus draw.
563 * (So: less common with truly self-powered devices, where
564 * vbus doesn't act like a power supply.)
565 *
566 * Such spikes are short; usually less than ~500 usec, max
567 * of ~2 msec. That is, they're not sustained overcurrent
568 * errors, though they're reported using VBUSERROR irqs.
569 *
570 * Workarounds: (a) hardware: use self powered devices.
571 * (b) software: ignore non-repeated VBUS errors.
572 *
573 * REVISIT: do delays from lots of DEBUG_KERNEL checks
574 * make trouble here, keeping VBUS < 4.4V ?
575 */
576 switch (musb->xceiv->otg->state) {
577 case OTG_STATE_A_HOST:
578 /* recovery is dicey once we've gotten past the
579 * initial stages of enumeration, but if VBUS
580 * stayed ok at the other end of the link, and
581 * another reset is due (at least for high speed,
582 * to redo the chirp etc), it might work OK...
583 */
584 case OTG_STATE_A_WAIT_BCON:
585 case OTG_STATE_A_WAIT_VRISE:
586 if (musb->vbuserr_retry) {
587 void __iomem *mbase = musb->mregs;
588
589 musb->vbuserr_retry--;
590 ignore = 1;
591 devctl |= MUSB_DEVCTL_SESSION;
592 musb_writeb(mbase, MUSB_DEVCTL, devctl);
593 } else {
594 musb->port1_status |=
595 USB_PORT_STAT_OVERCURRENT
596 | (USB_PORT_STAT_C_OVERCURRENT << 16);
597 }
598 break;
599 default:
600 break;
601 }
602
603 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
604 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
605 usb_otg_state_string(musb->xceiv->otg->state),
606 devctl,
607 ({ char *s;
608 switch (devctl & MUSB_DEVCTL_VBUS) {
609 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
610 s = "<SessEnd"; break;
611 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
612 s = "<AValid"; break;
613 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
614 s = "<VBusValid"; break;
615 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
616 default:
617 s = "VALID"; break;
618 } s; }),
619 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
620 musb->port1_status);
621
622 /* go through A_WAIT_VFALL then start a new session */
623 if (!ignore)
624 musb_platform_set_vbus(musb, 0);
625 handled = IRQ_HANDLED;
626 }
627
628 if (int_usb & MUSB_INTR_SUSPEND) {
629 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
630 usb_otg_state_string(musb->xceiv->otg->state), devctl);
631 handled = IRQ_HANDLED;
632
633 switch (musb->xceiv->otg->state) {
634 case OTG_STATE_A_PERIPHERAL:
635 /* We also come here if the cable is removed, since
636 * this silicon doesn't report ID-no-longer-grounded.
637 *
638 * We depend on T(a_wait_bcon) to shut us down, and
639 * hope users don't do anything dicey during this
640 * undesired detour through A_WAIT_BCON.
641 */
642 musb_hnp_stop(musb);
643 musb_host_resume_root_hub(musb);
644 musb_root_disconnect(musb);
645 musb_platform_try_idle(musb, jiffies
646 + msecs_to_jiffies(musb->a_wait_bcon
647 ? : OTG_TIME_A_WAIT_BCON));
648
649 break;
650 case OTG_STATE_B_IDLE:
651 if (!musb->is_active)
652 break;
653 case OTG_STATE_B_PERIPHERAL:
654 musb_g_suspend(musb);
655 musb->is_active = musb->g.b_hnp_enable;
656 if (musb->is_active) {
657 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
658 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
659 mod_timer(&musb->otg_timer, jiffies
660 + msecs_to_jiffies(
661 OTG_TIME_B_ASE0_BRST));
662 }
663 break;
664 case OTG_STATE_A_WAIT_BCON:
665 if (musb->a_wait_bcon != 0)
666 musb_platform_try_idle(musb, jiffies
667 + msecs_to_jiffies(musb->a_wait_bcon));
668 break;
669 case OTG_STATE_A_HOST:
670 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
671 musb->is_active = musb->hcd->self.b_hnp_enable;
672 break;
673 case OTG_STATE_B_HOST:
674 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
675 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
676 break;
677 default:
678 /* "should not happen" */
679 musb->is_active = 0;
680 break;
681 }
682 }
683
684 if (int_usb & MUSB_INTR_CONNECT) {
685 struct usb_hcd *hcd = musb->hcd;
686
687 handled = IRQ_HANDLED;
688 musb->is_active = 1;
689
690 musb->ep0_stage = MUSB_EP0_START;
691
692 /* flush endpoints when transitioning from Device Mode */
693 if (is_peripheral_active(musb)) {
694 /* REVISIT HNP; just force disconnect */
695 }
696 musb->intrtxe = musb->epmask;
697 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
698 musb->intrrxe = musb->epmask & 0xfffe;
699 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
700 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
701 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
702 |USB_PORT_STAT_HIGH_SPEED
703 |USB_PORT_STAT_ENABLE
704 );
705 musb->port1_status |= USB_PORT_STAT_CONNECTION
706 |(USB_PORT_STAT_C_CONNECTION << 16);
707
708 /* high vs full speed is just a guess until after reset */
709 if (devctl & MUSB_DEVCTL_LSDEV)
710 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
711
712 /* indicate new connection to OTG machine */
713 switch (musb->xceiv->otg->state) {
714 case OTG_STATE_B_PERIPHERAL:
715 if (int_usb & MUSB_INTR_SUSPEND) {
716 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
717 int_usb &= ~MUSB_INTR_SUSPEND;
718 goto b_host;
719 } else
720 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
721 break;
722 case OTG_STATE_B_WAIT_ACON:
723 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
724 b_host:
725 musb->xceiv->otg->state = OTG_STATE_B_HOST;
726 if (musb->hcd)
727 musb->hcd->self.is_b_host = 1;
728 del_timer(&musb->otg_timer);
729 break;
730 default:
731 if ((devctl & MUSB_DEVCTL_VBUS)
732 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
733 musb->xceiv->otg->state = OTG_STATE_A_HOST;
734 if (hcd)
735 hcd->self.is_b_host = 0;
736 }
737 break;
738 }
739
740 musb_host_poke_root_hub(musb);
741
742 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
743 usb_otg_state_string(musb->xceiv->otg->state), devctl);
744 }
745
746 if (int_usb & MUSB_INTR_DISCONNECT) {
747 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
748 usb_otg_state_string(musb->xceiv->otg->state),
749 MUSB_MODE(musb), devctl);
750 handled = IRQ_HANDLED;
751
752 switch (musb->xceiv->otg->state) {
753 case OTG_STATE_A_HOST:
754 case OTG_STATE_A_SUSPEND:
755 musb_host_resume_root_hub(musb);
756 musb_root_disconnect(musb);
757 if (musb->a_wait_bcon != 0)
758 musb_platform_try_idle(musb, jiffies
759 + msecs_to_jiffies(musb->a_wait_bcon));
760 break;
761 case OTG_STATE_B_HOST:
762 /* REVISIT this behaves for "real disconnect"
763 * cases; make sure the other transitions from
764 * from B_HOST act right too. The B_HOST code
765 * in hnp_stop() is currently not used...
766 */
767 musb_root_disconnect(musb);
768 if (musb->hcd)
769 musb->hcd->self.is_b_host = 0;
770 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
771 MUSB_DEV_MODE(musb);
772 musb_g_disconnect(musb);
773 break;
774 case OTG_STATE_A_PERIPHERAL:
775 musb_hnp_stop(musb);
776 musb_root_disconnect(musb);
777 /* FALLTHROUGH */
778 case OTG_STATE_B_WAIT_ACON:
779 /* FALLTHROUGH */
780 case OTG_STATE_B_PERIPHERAL:
781 case OTG_STATE_B_IDLE:
782 musb_g_disconnect(musb);
783 break;
784 default:
785 WARNING("unhandled DISCONNECT transition (%s)\n",
786 usb_otg_state_string(musb->xceiv->otg->state));
787 break;
788 }
789 }
790
791 /* mentor saves a bit: bus reset and babble share the same irq.
792 * only host sees babble; only peripheral sees bus reset.
793 */
794 if (int_usb & MUSB_INTR_RESET) {
795 handled = IRQ_HANDLED;
796 if ((devctl & MUSB_DEVCTL_HM) != 0) {
797 /*
798 * Looks like non-HS BABBLE can be ignored, but
799 * HS BABBLE is an error condition. For HS the solution
800 * is to avoid babble in the first place and fix what
801 * caused BABBLE. When HS BABBLE happens we can only
802 * stop the session.
803 */
804 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
805 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
806 else {
807 ERR("Stopping host session -- babble\n");
808 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
809 }
810 } else {
811 dev_dbg(musb->controller, "BUS RESET as %s\n",
812 usb_otg_state_string(musb->xceiv->otg->state));
813 switch (musb->xceiv->otg->state) {
814 case OTG_STATE_A_SUSPEND:
815 musb_g_reset(musb);
816 /* FALLTHROUGH */
817 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
818 /* never use invalid T(a_wait_bcon) */
819 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
820 usb_otg_state_string(musb->xceiv->otg->state),
821 TA_WAIT_BCON(musb));
822 mod_timer(&musb->otg_timer, jiffies
823 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
824 break;
825 case OTG_STATE_A_PERIPHERAL:
826 del_timer(&musb->otg_timer);
827 musb_g_reset(musb);
828 break;
829 case OTG_STATE_B_WAIT_ACON:
830 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
831 usb_otg_state_string(musb->xceiv->otg->state));
832 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
833 musb_g_reset(musb);
834 break;
835 case OTG_STATE_B_IDLE:
836 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
837 /* FALLTHROUGH */
838 case OTG_STATE_B_PERIPHERAL:
839 musb_g_reset(musb);
840 break;
841 default:
842 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
843 usb_otg_state_string(musb->xceiv->otg->state));
844 }
845 }
846 }
847
848 /* handle babble condition */
849 if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb))
850 schedule_delayed_work(&musb->recover_work,
851 msecs_to_jiffies(100));
852
853 #if 0
854 /* REVISIT ... this would be for multiplexing periodic endpoints, or
855 * supporting transfer phasing to prevent exceeding ISO bandwidth
856 * limits of a given frame or microframe.
857 *
858 * It's not needed for peripheral side, which dedicates endpoints;
859 * though it _might_ use SOF irqs for other purposes.
860 *
861 * And it's not currently needed for host side, which also dedicates
862 * endpoints, relies on TX/RX interval registers, and isn't claimed
863 * to support ISO transfers yet.
864 */
865 if (int_usb & MUSB_INTR_SOF) {
866 void __iomem *mbase = musb->mregs;
867 struct musb_hw_ep *ep;
868 u8 epnum;
869 u16 frame;
870
871 dev_dbg(musb->controller, "START_OF_FRAME\n");
872 handled = IRQ_HANDLED;
873
874 /* start any periodic Tx transfers waiting for current frame */
875 frame = musb_readw(mbase, MUSB_FRAME);
876 ep = musb->endpoints;
877 for (epnum = 1; (epnum < musb->nr_endpoints)
878 && (musb->epmask >= (1 << epnum));
879 epnum++, ep++) {
880 /*
881 * FIXME handle framecounter wraps (12 bits)
882 * eliminate duplicated StartUrb logic
883 */
884 if (ep->dwWaitFrame >= frame) {
885 ep->dwWaitFrame = 0;
886 pr_debug("SOF --> periodic TX%s on %d\n",
887 ep->tx_channel ? " DMA" : "",
888 epnum);
889 if (!ep->tx_channel)
890 musb_h_tx_start(musb, epnum);
891 else
892 cppi_hostdma_start(musb, epnum);
893 }
894 } /* end of for loop */
895 }
896 #endif
897
898 schedule_work(&musb->irq_work);
899
900 return handled;
901 }
902
903 /*-------------------------------------------------------------------------*/
904
905 static void musb_generic_disable(struct musb *musb)
906 {
907 void __iomem *mbase = musb->mregs;
908 u16 temp;
909
910 /* disable interrupts */
911 musb_writeb(mbase, MUSB_INTRUSBE, 0);
912 musb->intrtxe = 0;
913 musb_writew(mbase, MUSB_INTRTXE, 0);
914 musb->intrrxe = 0;
915 musb_writew(mbase, MUSB_INTRRXE, 0);
916
917 /* off */
918 musb_writeb(mbase, MUSB_DEVCTL, 0);
919
920 /* flush pending interrupts */
921 temp = musb_readb(mbase, MUSB_INTRUSB);
922 temp = musb_readw(mbase, MUSB_INTRTX);
923 temp = musb_readw(mbase, MUSB_INTRRX);
924
925 }
926
927 /*
928 * Program the HDRC to start (enable interrupts, dma, etc.).
929 */
930 void musb_start(struct musb *musb)
931 {
932 void __iomem *regs = musb->mregs;
933 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
934
935 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
936
937 /* Set INT enable registers, enable interrupts */
938 musb->intrtxe = musb->epmask;
939 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
940 musb->intrrxe = musb->epmask & 0xfffe;
941 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
942 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
943
944 musb_writeb(regs, MUSB_TESTMODE, 0);
945
946 /* put into basic highspeed mode and start session */
947 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
948 | MUSB_POWER_HSENAB
949 /* ENSUSPEND wedges tusb */
950 /* | MUSB_POWER_ENSUSPEND */
951 );
952
953 musb->is_active = 0;
954 devctl = musb_readb(regs, MUSB_DEVCTL);
955 devctl &= ~MUSB_DEVCTL_SESSION;
956
957 /* session started after:
958 * (a) ID-grounded irq, host mode;
959 * (b) vbus present/connect IRQ, peripheral mode;
960 * (c) peripheral initiates, using SRP
961 */
962 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
963 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
964 musb->is_active = 1;
965 } else {
966 devctl |= MUSB_DEVCTL_SESSION;
967 }
968
969 musb_platform_enable(musb);
970 musb_writeb(regs, MUSB_DEVCTL, devctl);
971 }
972
973 /*
974 * Make the HDRC stop (disable interrupts, etc.);
975 * reversible by musb_start
976 * called on gadget driver unregister
977 * with controller locked, irqs blocked
978 * acts as a NOP unless some role activated the hardware
979 */
980 void musb_stop(struct musb *musb)
981 {
982 /* stop IRQs, timers, ... */
983 musb_platform_disable(musb);
984 musb_generic_disable(musb);
985 dev_dbg(musb->controller, "HDRC disabled\n");
986
987 /* FIXME
988 * - mark host and/or peripheral drivers unusable/inactive
989 * - disable DMA (and enable it in HdrcStart)
990 * - make sure we can musb_start() after musb_stop(); with
991 * OTG mode, gadget driver module rmmod/modprobe cycles that
992 * - ...
993 */
994 musb_platform_try_idle(musb, 0);
995 }
996
997 static void musb_shutdown(struct platform_device *pdev)
998 {
999 struct musb *musb = dev_to_musb(&pdev->dev);
1000 unsigned long flags;
1001
1002 pm_runtime_get_sync(musb->controller);
1003
1004 musb_host_cleanup(musb);
1005 musb_gadget_cleanup(musb);
1006
1007 spin_lock_irqsave(&musb->lock, flags);
1008 musb_platform_disable(musb);
1009 musb_generic_disable(musb);
1010 spin_unlock_irqrestore(&musb->lock, flags);
1011
1012 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1013 musb_platform_exit(musb);
1014
1015 pm_runtime_put(musb->controller);
1016 /* FIXME power down */
1017 }
1018
1019
1020 /*-------------------------------------------------------------------------*/
1021
1022 /*
1023 * The silicon either has hard-wired endpoint configurations, or else
1024 * "dynamic fifo" sizing. The driver has support for both, though at this
1025 * writing only the dynamic sizing is very well tested. Since we switched
1026 * away from compile-time hardware parameters, we can no longer rely on
1027 * dead code elimination to leave only the relevant one in the object file.
1028 *
1029 * We don't currently use dynamic fifo setup capability to do anything
1030 * more than selecting one of a bunch of predefined configurations.
1031 */
1032 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1033 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1034 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1035 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1036 || defined(CONFIG_USB_MUSB_AM35X) \
1037 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1038 || defined(CONFIG_USB_MUSB_DSPS) \
1039 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1040 static ushort fifo_mode = 4;
1041 #elif defined(CONFIG_USB_MUSB_UX500) \
1042 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1043 static ushort fifo_mode = 5;
1044 #else
1045 static ushort fifo_mode = 2;
1046 #endif
1047
1048 /* "modprobe ... fifo_mode=1" etc */
1049 module_param(fifo_mode, ushort, 0);
1050 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1051
1052 /*
1053 * tables defining fifo_mode values. define more if you like.
1054 * for host side, make sure both halves of ep1 are set up.
1055 */
1056
1057 /* mode 0 - fits in 2KB */
1058 static struct musb_fifo_cfg mode_0_cfg[] = {
1059 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1062 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064 };
1065
1066 /* mode 1 - fits in 4KB */
1067 static struct musb_fifo_cfg mode_1_cfg[] = {
1068 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1069 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1070 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1072 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1073 };
1074
1075 /* mode 2 - fits in 4KB */
1076 static struct musb_fifo_cfg mode_2_cfg[] = {
1077 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1082 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1083 };
1084
1085 /* mode 3 - fits in 4KB */
1086 static struct musb_fifo_cfg mode_3_cfg[] = {
1087 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1088 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1089 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1090 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1091 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1092 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1093 };
1094
1095 /* mode 4 - fits in 16KB */
1096 static struct musb_fifo_cfg mode_4_cfg[] = {
1097 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1098 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1099 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1116 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1117 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1118 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1119 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1120 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1121 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1122 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1123 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1124 };
1125
1126 /* mode 5 - fits in 8KB */
1127 static struct musb_fifo_cfg mode_5_cfg[] = {
1128 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1129 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1130 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1139 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1140 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1141 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1142 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1143 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1144 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1145 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1146 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1147 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1148 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1149 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1150 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1151 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1152 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1153 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1154 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1155 };
1156
1157 /*
1158 * configure a fifo; for non-shared endpoints, this may be called
1159 * once for a tx fifo and once for an rx fifo.
1160 *
1161 * returns negative errno or offset for next fifo.
1162 */
1163 static int
1164 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1165 const struct musb_fifo_cfg *cfg, u16 offset)
1166 {
1167 void __iomem *mbase = musb->mregs;
1168 int size = 0;
1169 u16 maxpacket = cfg->maxpacket;
1170 u16 c_off = offset >> 3;
1171 u8 c_size;
1172
1173 /* expect hw_ep has already been zero-initialized */
1174
1175 size = ffs(max(maxpacket, (u16) 8)) - 1;
1176 maxpacket = 1 << size;
1177
1178 c_size = size - 3;
1179 if (cfg->mode == BUF_DOUBLE) {
1180 if ((offset + (maxpacket << 1)) >
1181 (1 << (musb->config->ram_bits + 2)))
1182 return -EMSGSIZE;
1183 c_size |= MUSB_FIFOSZ_DPB;
1184 } else {
1185 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1186 return -EMSGSIZE;
1187 }
1188
1189 /* configure the FIFO */
1190 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1191
1192 /* EP0 reserved endpoint for control, bidirectional;
1193 * EP1 reserved for bulk, two unidirectional halves.
1194 */
1195 if (hw_ep->epnum == 1)
1196 musb->bulk_ep = hw_ep;
1197 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1198 switch (cfg->style) {
1199 case FIFO_TX:
1200 musb_write_txfifosz(mbase, c_size);
1201 musb_write_txfifoadd(mbase, c_off);
1202 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1203 hw_ep->max_packet_sz_tx = maxpacket;
1204 break;
1205 case FIFO_RX:
1206 musb_write_rxfifosz(mbase, c_size);
1207 musb_write_rxfifoadd(mbase, c_off);
1208 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1209 hw_ep->max_packet_sz_rx = maxpacket;
1210 break;
1211 case FIFO_RXTX:
1212 musb_write_txfifosz(mbase, c_size);
1213 musb_write_txfifoadd(mbase, c_off);
1214 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1215 hw_ep->max_packet_sz_rx = maxpacket;
1216
1217 musb_write_rxfifosz(mbase, c_size);
1218 musb_write_rxfifoadd(mbase, c_off);
1219 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1220 hw_ep->max_packet_sz_tx = maxpacket;
1221
1222 hw_ep->is_shared_fifo = true;
1223 break;
1224 }
1225
1226 /* NOTE rx and tx endpoint irqs aren't managed separately,
1227 * which happens to be ok
1228 */
1229 musb->epmask |= (1 << hw_ep->epnum);
1230
1231 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1232 }
1233
1234 static struct musb_fifo_cfg ep0_cfg = {
1235 .style = FIFO_RXTX, .maxpacket = 64,
1236 };
1237
1238 static int ep_config_from_table(struct musb *musb)
1239 {
1240 const struct musb_fifo_cfg *cfg;
1241 unsigned i, n;
1242 int offset;
1243 struct musb_hw_ep *hw_ep = musb->endpoints;
1244
1245 if (musb->config->fifo_cfg) {
1246 cfg = musb->config->fifo_cfg;
1247 n = musb->config->fifo_cfg_size;
1248 goto done;
1249 }
1250
1251 switch (fifo_mode) {
1252 default:
1253 fifo_mode = 0;
1254 /* FALLTHROUGH */
1255 case 0:
1256 cfg = mode_0_cfg;
1257 n = ARRAY_SIZE(mode_0_cfg);
1258 break;
1259 case 1:
1260 cfg = mode_1_cfg;
1261 n = ARRAY_SIZE(mode_1_cfg);
1262 break;
1263 case 2:
1264 cfg = mode_2_cfg;
1265 n = ARRAY_SIZE(mode_2_cfg);
1266 break;
1267 case 3:
1268 cfg = mode_3_cfg;
1269 n = ARRAY_SIZE(mode_3_cfg);
1270 break;
1271 case 4:
1272 cfg = mode_4_cfg;
1273 n = ARRAY_SIZE(mode_4_cfg);
1274 break;
1275 case 5:
1276 cfg = mode_5_cfg;
1277 n = ARRAY_SIZE(mode_5_cfg);
1278 break;
1279 }
1280
1281 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1282 musb_driver_name, fifo_mode);
1283
1284
1285 done:
1286 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1287 /* assert(offset > 0) */
1288
1289 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1290 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1291 */
1292
1293 for (i = 0; i < n; i++) {
1294 u8 epn = cfg->hw_ep_num;
1295
1296 if (epn >= musb->config->num_eps) {
1297 pr_debug("%s: invalid ep %d\n",
1298 musb_driver_name, epn);
1299 return -EINVAL;
1300 }
1301 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1302 if (offset < 0) {
1303 pr_debug("%s: mem overrun, ep %d\n",
1304 musb_driver_name, epn);
1305 return offset;
1306 }
1307 epn++;
1308 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1309 }
1310
1311 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1312 musb_driver_name,
1313 n + 1, musb->config->num_eps * 2 - 1,
1314 offset, (1 << (musb->config->ram_bits + 2)));
1315
1316 if (!musb->bulk_ep) {
1317 pr_debug("%s: missing bulk\n", musb_driver_name);
1318 return -EINVAL;
1319 }
1320
1321 return 0;
1322 }
1323
1324
1325 /*
1326 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1327 * @param musb the controller
1328 */
1329 static int ep_config_from_hw(struct musb *musb)
1330 {
1331 u8 epnum = 0;
1332 struct musb_hw_ep *hw_ep;
1333 void __iomem *mbase = musb->mregs;
1334 int ret = 0;
1335
1336 dev_dbg(musb->controller, "<== static silicon ep config\n");
1337
1338 /* FIXME pick up ep0 maxpacket size */
1339
1340 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1341 musb_ep_select(mbase, epnum);
1342 hw_ep = musb->endpoints + epnum;
1343
1344 ret = musb_read_fifosize(musb, hw_ep, epnum);
1345 if (ret < 0)
1346 break;
1347
1348 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1349
1350 /* pick an RX/TX endpoint for bulk */
1351 if (hw_ep->max_packet_sz_tx < 512
1352 || hw_ep->max_packet_sz_rx < 512)
1353 continue;
1354
1355 /* REVISIT: this algorithm is lazy, we should at least
1356 * try to pick a double buffered endpoint.
1357 */
1358 if (musb->bulk_ep)
1359 continue;
1360 musb->bulk_ep = hw_ep;
1361 }
1362
1363 if (!musb->bulk_ep) {
1364 pr_debug("%s: missing bulk\n", musb_driver_name);
1365 return -EINVAL;
1366 }
1367
1368 return 0;
1369 }
1370
1371 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1372
1373 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1374 * configure endpoints, or take their config from silicon
1375 */
1376 static int musb_core_init(u16 musb_type, struct musb *musb)
1377 {
1378 u8 reg;
1379 char *type;
1380 char aInfo[90], aRevision[32], aDate[12];
1381 void __iomem *mbase = musb->mregs;
1382 int status = 0;
1383 int i;
1384
1385 /* log core options (read using indexed model) */
1386 reg = musb_read_configdata(mbase);
1387
1388 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1389 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1390 strcat(aInfo, ", dyn FIFOs");
1391 musb->dyn_fifo = true;
1392 }
1393 if (reg & MUSB_CONFIGDATA_MPRXE) {
1394 strcat(aInfo, ", bulk combine");
1395 musb->bulk_combine = true;
1396 }
1397 if (reg & MUSB_CONFIGDATA_MPTXE) {
1398 strcat(aInfo, ", bulk split");
1399 musb->bulk_split = true;
1400 }
1401 if (reg & MUSB_CONFIGDATA_HBRXE) {
1402 strcat(aInfo, ", HB-ISO Rx");
1403 musb->hb_iso_rx = true;
1404 }
1405 if (reg & MUSB_CONFIGDATA_HBTXE) {
1406 strcat(aInfo, ", HB-ISO Tx");
1407 musb->hb_iso_tx = true;
1408 }
1409 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1410 strcat(aInfo, ", SoftConn");
1411
1412 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1413 musb_driver_name, reg, aInfo);
1414
1415 aDate[0] = 0;
1416 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1417 musb->is_multipoint = 1;
1418 type = "M";
1419 } else {
1420 musb->is_multipoint = 0;
1421 type = "";
1422 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1423 printk(KERN_ERR
1424 "%s: kernel must blacklist external hubs\n",
1425 musb_driver_name);
1426 #endif
1427 }
1428
1429 /* log release info */
1430 musb->hwvers = musb_read_hwvers(mbase);
1431 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1432 MUSB_HWVERS_MINOR(musb->hwvers),
1433 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1434 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1435 musb_driver_name, type, aRevision, aDate);
1436
1437 /* configure ep0 */
1438 musb_configure_ep0(musb);
1439
1440 /* discover endpoint configuration */
1441 musb->nr_endpoints = 1;
1442 musb->epmask = 1;
1443
1444 if (musb->dyn_fifo)
1445 status = ep_config_from_table(musb);
1446 else
1447 status = ep_config_from_hw(musb);
1448
1449 if (status < 0)
1450 return status;
1451
1452 /* finish init, and print endpoint config */
1453 for (i = 0; i < musb->nr_endpoints; i++) {
1454 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1455
1456 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1457 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1458 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1459 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1460 hw_ep->fifo_sync_va =
1461 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1462
1463 if (i == 0)
1464 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1465 else
1466 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1467 #endif
1468
1469 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1470 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1471 hw_ep->rx_reinit = 1;
1472 hw_ep->tx_reinit = 1;
1473
1474 if (hw_ep->max_packet_sz_tx) {
1475 dev_dbg(musb->controller,
1476 "%s: hw_ep %d%s, %smax %d\n",
1477 musb_driver_name, i,
1478 hw_ep->is_shared_fifo ? "shared" : "tx",
1479 hw_ep->tx_double_buffered
1480 ? "doublebuffer, " : "",
1481 hw_ep->max_packet_sz_tx);
1482 }
1483 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1484 dev_dbg(musb->controller,
1485 "%s: hw_ep %d%s, %smax %d\n",
1486 musb_driver_name, i,
1487 "rx",
1488 hw_ep->rx_double_buffered
1489 ? "doublebuffer, " : "",
1490 hw_ep->max_packet_sz_rx);
1491 }
1492 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1493 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1494 }
1495
1496 return 0;
1497 }
1498
1499 /*-------------------------------------------------------------------------*/
1500
1501 /*
1502 * handle all the irqs defined by the HDRC core. for now we expect: other
1503 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1504 * will be assigned, and the irq will already have been acked.
1505 *
1506 * called in irq context with spinlock held, irqs blocked
1507 */
1508 irqreturn_t musb_interrupt(struct musb *musb)
1509 {
1510 irqreturn_t retval = IRQ_NONE;
1511 u8 devctl;
1512 int ep_num;
1513 u32 reg;
1514
1515 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1516
1517 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1518 is_host_active(musb) ? "host" : "peripheral",
1519 musb->int_usb, musb->int_tx, musb->int_rx);
1520
1521 /* the core can interrupt us for multiple reasons; docs have
1522 * a generic interrupt flowchart to follow
1523 */
1524 if (musb->int_usb)
1525 retval |= musb_stage0_irq(musb, musb->int_usb,
1526 devctl);
1527
1528 /* "stage 1" is handling endpoint irqs */
1529
1530 /* handle endpoint 0 first */
1531 if (musb->int_tx & 1) {
1532 if (is_host_active(musb))
1533 retval |= musb_h_ep0_irq(musb);
1534 else
1535 retval |= musb_g_ep0_irq(musb);
1536 }
1537
1538 /* RX on endpoints 1-15 */
1539 reg = musb->int_rx >> 1;
1540 ep_num = 1;
1541 while (reg) {
1542 if (reg & 1) {
1543 /* musb_ep_select(musb->mregs, ep_num); */
1544 /* REVISIT just retval = ep->rx_irq(...) */
1545 retval = IRQ_HANDLED;
1546 if (is_host_active(musb))
1547 musb_host_rx(musb, ep_num);
1548 else
1549 musb_g_rx(musb, ep_num);
1550 }
1551
1552 reg >>= 1;
1553 ep_num++;
1554 }
1555
1556 /* TX on endpoints 1-15 */
1557 reg = musb->int_tx >> 1;
1558 ep_num = 1;
1559 while (reg) {
1560 if (reg & 1) {
1561 /* musb_ep_select(musb->mregs, ep_num); */
1562 /* REVISIT just retval |= ep->tx_irq(...) */
1563 retval = IRQ_HANDLED;
1564 if (is_host_active(musb))
1565 musb_host_tx(musb, ep_num);
1566 else
1567 musb_g_tx(musb, ep_num);
1568 }
1569 reg >>= 1;
1570 ep_num++;
1571 }
1572
1573 return retval;
1574 }
1575 EXPORT_SYMBOL_GPL(musb_interrupt);
1576
1577 #ifndef CONFIG_MUSB_PIO_ONLY
1578 static bool use_dma = 1;
1579
1580 /* "modprobe ... use_dma=0" etc */
1581 module_param(use_dma, bool, 0);
1582 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1583
1584 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1585 {
1586 /* called with controller lock already held */
1587
1588 if (!epnum) {
1589 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1590 if (!is_cppi_enabled()) {
1591 /* endpoint 0 */
1592 if (is_host_active(musb))
1593 musb_h_ep0_irq(musb);
1594 else
1595 musb_g_ep0_irq(musb);
1596 }
1597 #endif
1598 } else {
1599 /* endpoints 1..15 */
1600 if (transmit) {
1601 if (is_host_active(musb))
1602 musb_host_tx(musb, epnum);
1603 else
1604 musb_g_tx(musb, epnum);
1605 } else {
1606 /* receive */
1607 if (is_host_active(musb))
1608 musb_host_rx(musb, epnum);
1609 else
1610 musb_g_rx(musb, epnum);
1611 }
1612 }
1613 }
1614 EXPORT_SYMBOL_GPL(musb_dma_completion);
1615
1616 #else
1617 #define use_dma 0
1618 #endif
1619
1620 /*-------------------------------------------------------------------------*/
1621
1622 static ssize_t
1623 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1624 {
1625 struct musb *musb = dev_to_musb(dev);
1626 unsigned long flags;
1627 int ret = -EINVAL;
1628
1629 spin_lock_irqsave(&musb->lock, flags);
1630 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1631 spin_unlock_irqrestore(&musb->lock, flags);
1632
1633 return ret;
1634 }
1635
1636 static ssize_t
1637 musb_mode_store(struct device *dev, struct device_attribute *attr,
1638 const char *buf, size_t n)
1639 {
1640 struct musb *musb = dev_to_musb(dev);
1641 unsigned long flags;
1642 int status;
1643
1644 spin_lock_irqsave(&musb->lock, flags);
1645 if (sysfs_streq(buf, "host"))
1646 status = musb_platform_set_mode(musb, MUSB_HOST);
1647 else if (sysfs_streq(buf, "peripheral"))
1648 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1649 else if (sysfs_streq(buf, "otg"))
1650 status = musb_platform_set_mode(musb, MUSB_OTG);
1651 else
1652 status = -EINVAL;
1653 spin_unlock_irqrestore(&musb->lock, flags);
1654
1655 return (status == 0) ? n : status;
1656 }
1657 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1658
1659 static ssize_t
1660 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1661 const char *buf, size_t n)
1662 {
1663 struct musb *musb = dev_to_musb(dev);
1664 unsigned long flags;
1665 unsigned long val;
1666
1667 if (sscanf(buf, "%lu", &val) < 1) {
1668 dev_err(dev, "Invalid VBUS timeout ms value\n");
1669 return -EINVAL;
1670 }
1671
1672 spin_lock_irqsave(&musb->lock, flags);
1673 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1674 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1675 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1676 musb->is_active = 0;
1677 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1678 spin_unlock_irqrestore(&musb->lock, flags);
1679
1680 return n;
1681 }
1682
1683 static ssize_t
1684 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1685 {
1686 struct musb *musb = dev_to_musb(dev);
1687 unsigned long flags;
1688 unsigned long val;
1689 int vbus;
1690
1691 spin_lock_irqsave(&musb->lock, flags);
1692 val = musb->a_wait_bcon;
1693 /* FIXME get_vbus_status() is normally #defined as false...
1694 * and is effectively TUSB-specific.
1695 */
1696 vbus = musb_platform_get_vbus_status(musb);
1697 spin_unlock_irqrestore(&musb->lock, flags);
1698
1699 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1700 vbus ? "on" : "off", val);
1701 }
1702 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1703
1704 /* Gadget drivers can't know that a host is connected so they might want
1705 * to start SRP, but users can. This allows userspace to trigger SRP.
1706 */
1707 static ssize_t
1708 musb_srp_store(struct device *dev, struct device_attribute *attr,
1709 const char *buf, size_t n)
1710 {
1711 struct musb *musb = dev_to_musb(dev);
1712 unsigned short srp;
1713
1714 if (sscanf(buf, "%hu", &srp) != 1
1715 || (srp != 1)) {
1716 dev_err(dev, "SRP: Value must be 1\n");
1717 return -EINVAL;
1718 }
1719
1720 if (srp == 1)
1721 musb_g_wakeup(musb);
1722
1723 return n;
1724 }
1725 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1726
1727 static struct attribute *musb_attributes[] = {
1728 &dev_attr_mode.attr,
1729 &dev_attr_vbus.attr,
1730 &dev_attr_srp.attr,
1731 NULL
1732 };
1733
1734 static const struct attribute_group musb_attr_group = {
1735 .attrs = musb_attributes,
1736 };
1737
1738 /* Only used to provide driver mode change events */
1739 static void musb_irq_work(struct work_struct *data)
1740 {
1741 struct musb *musb = container_of(data, struct musb, irq_work);
1742
1743 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1744 musb->xceiv_old_state = musb->xceiv->otg->state;
1745 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1746 }
1747 }
1748
1749 /* Recover from babble interrupt conditions */
1750 static void musb_recover_work(struct work_struct *data)
1751 {
1752 struct musb *musb = container_of(data, struct musb, recover_work.work);
1753 int status, ret;
1754
1755 ret = musb_platform_reset(musb);
1756 if (ret)
1757 return;
1758
1759 usb_phy_vbus_off(musb->xceiv);
1760 usleep_range(100, 200);
1761
1762 usb_phy_vbus_on(musb->xceiv);
1763 usleep_range(100, 200);
1764
1765 /*
1766 * When a babble condition occurs, the musb controller
1767 * removes the session bit and the endpoint config is lost.
1768 */
1769 if (musb->dyn_fifo)
1770 status = ep_config_from_table(musb);
1771 else
1772 status = ep_config_from_hw(musb);
1773
1774 /* start the session again */
1775 if (status == 0)
1776 musb_start(musb);
1777 }
1778
1779 /* --------------------------------------------------------------------------
1780 * Init support
1781 */
1782
1783 static struct musb *allocate_instance(struct device *dev,
1784 struct musb_hdrc_config *config, void __iomem *mbase)
1785 {
1786 struct musb *musb;
1787 struct musb_hw_ep *ep;
1788 int epnum;
1789 int ret;
1790
1791 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1792 if (!musb)
1793 return NULL;
1794
1795 INIT_LIST_HEAD(&musb->control);
1796 INIT_LIST_HEAD(&musb->in_bulk);
1797 INIT_LIST_HEAD(&musb->out_bulk);
1798
1799 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1800 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1801 musb->mregs = mbase;
1802 musb->ctrl_base = mbase;
1803 musb->nIrq = -ENODEV;
1804 musb->config = config;
1805 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1806 for (epnum = 0, ep = musb->endpoints;
1807 epnum < musb->config->num_eps;
1808 epnum++, ep++) {
1809 ep->musb = musb;
1810 ep->epnum = epnum;
1811 }
1812
1813 musb->controller = dev;
1814
1815 ret = musb_host_alloc(musb);
1816 if (ret < 0)
1817 goto err_free;
1818
1819 dev_set_drvdata(dev, musb);
1820
1821 return musb;
1822
1823 err_free:
1824 return NULL;
1825 }
1826
1827 static void musb_free(struct musb *musb)
1828 {
1829 /* this has multiple entry modes. it handles fault cleanup after
1830 * probe(), where things may be partially set up, as well as rmmod
1831 * cleanup after everything's been de-activated.
1832 */
1833
1834 #ifdef CONFIG_SYSFS
1835 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1836 #endif
1837
1838 if (musb->nIrq >= 0) {
1839 if (musb->irq_wake)
1840 disable_irq_wake(musb->nIrq);
1841 free_irq(musb->nIrq, musb);
1842 }
1843
1844 musb_host_free(musb);
1845 }
1846
1847 static void musb_deassert_reset(struct work_struct *work)
1848 {
1849 struct musb *musb;
1850 unsigned long flags;
1851
1852 musb = container_of(work, struct musb, deassert_reset_work.work);
1853
1854 spin_lock_irqsave(&musb->lock, flags);
1855
1856 if (musb->port1_status & USB_PORT_STAT_RESET)
1857 musb_port_reset(musb, false);
1858
1859 spin_unlock_irqrestore(&musb->lock, flags);
1860 }
1861
1862 /*
1863 * Perform generic per-controller initialization.
1864 *
1865 * @dev: the controller (already clocked, etc)
1866 * @nIrq: IRQ number
1867 * @ctrl: virtual address of controller registers,
1868 * not yet corrected for platform-specific offsets
1869 */
1870 static int
1871 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1872 {
1873 int status;
1874 struct musb *musb;
1875 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1876
1877 /* The driver might handle more features than the board; OK.
1878 * Fail when the board needs a feature that's not enabled.
1879 */
1880 if (!plat) {
1881 dev_dbg(dev, "no platform_data?\n");
1882 status = -ENODEV;
1883 goto fail0;
1884 }
1885
1886 /* allocate */
1887 musb = allocate_instance(dev, plat->config, ctrl);
1888 if (!musb) {
1889 status = -ENOMEM;
1890 goto fail0;
1891 }
1892
1893 pm_runtime_use_autosuspend(musb->controller);
1894 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1895 pm_runtime_enable(musb->controller);
1896
1897 spin_lock_init(&musb->lock);
1898 musb->board_set_power = plat->set_power;
1899 musb->min_power = plat->min_power;
1900 musb->ops = plat->platform_ops;
1901 musb->port_mode = plat->mode;
1902
1903 /* The musb_platform_init() call:
1904 * - adjusts musb->mregs
1905 * - sets the musb->isr
1906 * - may initialize an integrated transceiver
1907 * - initializes musb->xceiv, usually by otg_get_phy()
1908 * - stops powering VBUS
1909 *
1910 * There are various transceiver configurations. Blackfin,
1911 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1912 * external/discrete ones in various flavors (twl4030 family,
1913 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1914 */
1915 status = musb_platform_init(musb);
1916 if (status < 0)
1917 goto fail1;
1918
1919 if (!musb->isr) {
1920 status = -ENODEV;
1921 goto fail2;
1922 }
1923
1924 if (!musb->xceiv->io_ops) {
1925 musb->xceiv->io_dev = musb->controller;
1926 musb->xceiv->io_priv = musb->mregs;
1927 musb->xceiv->io_ops = &musb_ulpi_access;
1928 }
1929
1930 pm_runtime_get_sync(musb->controller);
1931
1932 if (use_dma && dev->dma_mask) {
1933 musb->dma_controller = dma_controller_create(musb, musb->mregs);
1934 if (IS_ERR(musb->dma_controller)) {
1935 status = PTR_ERR(musb->dma_controller);
1936 goto fail2_5;
1937 }
1938 }
1939
1940 /* be sure interrupts are disabled before connecting ISR */
1941 musb_platform_disable(musb);
1942 musb_generic_disable(musb);
1943
1944 /* Init IRQ workqueue before request_irq */
1945 INIT_WORK(&musb->irq_work, musb_irq_work);
1946 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
1947 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
1948 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
1949
1950 /* setup musb parts of the core (especially endpoints) */
1951 status = musb_core_init(plat->config->multipoint
1952 ? MUSB_CONTROLLER_MHDRC
1953 : MUSB_CONTROLLER_HDRC, musb);
1954 if (status < 0)
1955 goto fail3;
1956
1957 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1958
1959 /* attach to the IRQ */
1960 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1961 dev_err(dev, "request_irq %d failed!\n", nIrq);
1962 status = -ENODEV;
1963 goto fail3;
1964 }
1965 musb->nIrq = nIrq;
1966 /* FIXME this handles wakeup irqs wrong */
1967 if (enable_irq_wake(nIrq) == 0) {
1968 musb->irq_wake = 1;
1969 device_init_wakeup(dev, 1);
1970 } else {
1971 musb->irq_wake = 0;
1972 }
1973
1974 /* program PHY to use external vBus if required */
1975 if (plat->extvbus) {
1976 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1977 busctl |= MUSB_ULPI_USE_EXTVBUS;
1978 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1979 }
1980
1981 if (musb->xceiv->otg->default_a) {
1982 MUSB_HST_MODE(musb);
1983 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
1984 } else {
1985 MUSB_DEV_MODE(musb);
1986 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1987 }
1988
1989 switch (musb->port_mode) {
1990 case MUSB_PORT_MODE_HOST:
1991 status = musb_host_setup(musb, plat->power);
1992 if (status < 0)
1993 goto fail3;
1994 status = musb_platform_set_mode(musb, MUSB_HOST);
1995 break;
1996 case MUSB_PORT_MODE_GADGET:
1997 status = musb_gadget_setup(musb);
1998 if (status < 0)
1999 goto fail3;
2000 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2001 break;
2002 case MUSB_PORT_MODE_DUAL_ROLE:
2003 status = musb_host_setup(musb, plat->power);
2004 if (status < 0)
2005 goto fail3;
2006 status = musb_gadget_setup(musb);
2007 if (status) {
2008 musb_host_cleanup(musb);
2009 goto fail3;
2010 }
2011 status = musb_platform_set_mode(musb, MUSB_OTG);
2012 break;
2013 default:
2014 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2015 break;
2016 }
2017
2018 if (status < 0)
2019 goto fail3;
2020
2021 status = musb_init_debugfs(musb);
2022 if (status < 0)
2023 goto fail4;
2024
2025 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2026 if (status)
2027 goto fail5;
2028
2029 pm_runtime_put(musb->controller);
2030
2031 return 0;
2032
2033 fail5:
2034 musb_exit_debugfs(musb);
2035
2036 fail4:
2037 musb_gadget_cleanup(musb);
2038 musb_host_cleanup(musb);
2039
2040 fail3:
2041 cancel_work_sync(&musb->irq_work);
2042 cancel_delayed_work_sync(&musb->recover_work);
2043 cancel_delayed_work_sync(&musb->finish_resume_work);
2044 cancel_delayed_work_sync(&musb->deassert_reset_work);
2045 if (musb->dma_controller)
2046 dma_controller_destroy(musb->dma_controller);
2047 fail2_5:
2048 pm_runtime_put_sync(musb->controller);
2049
2050 fail2:
2051 if (musb->irq_wake)
2052 device_init_wakeup(dev, 0);
2053 musb_platform_exit(musb);
2054
2055 fail1:
2056 pm_runtime_disable(musb->controller);
2057 dev_err(musb->controller,
2058 "musb_init_controller failed with status %d\n", status);
2059
2060 musb_free(musb);
2061
2062 fail0:
2063
2064 return status;
2065
2066 }
2067
2068 /*-------------------------------------------------------------------------*/
2069
2070 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2071 * bridge to a platform device; this driver then suffices.
2072 */
2073 static int musb_probe(struct platform_device *pdev)
2074 {
2075 struct device *dev = &pdev->dev;
2076 int irq = platform_get_irq_byname(pdev, "mc");
2077 struct resource *iomem;
2078 void __iomem *base;
2079
2080 if (irq <= 0)
2081 return -ENODEV;
2082
2083 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2084 base = devm_ioremap_resource(dev, iomem);
2085 if (IS_ERR(base))
2086 return PTR_ERR(base);
2087
2088 return musb_init_controller(dev, irq, base);
2089 }
2090
2091 static int musb_remove(struct platform_device *pdev)
2092 {
2093 struct device *dev = &pdev->dev;
2094 struct musb *musb = dev_to_musb(dev);
2095
2096 /* this gets called on rmmod.
2097 * - Host mode: host may still be active
2098 * - Peripheral mode: peripheral is deactivated (or never-activated)
2099 * - OTG mode: both roles are deactivated (or never-activated)
2100 */
2101 musb_exit_debugfs(musb);
2102 musb_shutdown(pdev);
2103
2104 if (musb->dma_controller)
2105 dma_controller_destroy(musb->dma_controller);
2106
2107 cancel_work_sync(&musb->irq_work);
2108 cancel_delayed_work_sync(&musb->recover_work);
2109 cancel_delayed_work_sync(&musb->finish_resume_work);
2110 cancel_delayed_work_sync(&musb->deassert_reset_work);
2111 musb_free(musb);
2112 device_init_wakeup(dev, 0);
2113 return 0;
2114 }
2115
2116 #ifdef CONFIG_PM
2117
2118 static void musb_save_context(struct musb *musb)
2119 {
2120 int i;
2121 void __iomem *musb_base = musb->mregs;
2122 void __iomem *epio;
2123
2124 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2125 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2126 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2127 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2128 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2129 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2130 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2131
2132 for (i = 0; i < musb->config->num_eps; ++i) {
2133 struct musb_hw_ep *hw_ep;
2134
2135 hw_ep = &musb->endpoints[i];
2136 if (!hw_ep)
2137 continue;
2138
2139 epio = hw_ep->regs;
2140 if (!epio)
2141 continue;
2142
2143 musb_writeb(musb_base, MUSB_INDEX, i);
2144 musb->context.index_regs[i].txmaxp =
2145 musb_readw(epio, MUSB_TXMAXP);
2146 musb->context.index_regs[i].txcsr =
2147 musb_readw(epio, MUSB_TXCSR);
2148 musb->context.index_regs[i].rxmaxp =
2149 musb_readw(epio, MUSB_RXMAXP);
2150 musb->context.index_regs[i].rxcsr =
2151 musb_readw(epio, MUSB_RXCSR);
2152
2153 if (musb->dyn_fifo) {
2154 musb->context.index_regs[i].txfifoadd =
2155 musb_read_txfifoadd(musb_base);
2156 musb->context.index_regs[i].rxfifoadd =
2157 musb_read_rxfifoadd(musb_base);
2158 musb->context.index_regs[i].txfifosz =
2159 musb_read_txfifosz(musb_base);
2160 musb->context.index_regs[i].rxfifosz =
2161 musb_read_rxfifosz(musb_base);
2162 }
2163
2164 musb->context.index_regs[i].txtype =
2165 musb_readb(epio, MUSB_TXTYPE);
2166 musb->context.index_regs[i].txinterval =
2167 musb_readb(epio, MUSB_TXINTERVAL);
2168 musb->context.index_regs[i].rxtype =
2169 musb_readb(epio, MUSB_RXTYPE);
2170 musb->context.index_regs[i].rxinterval =
2171 musb_readb(epio, MUSB_RXINTERVAL);
2172
2173 musb->context.index_regs[i].txfunaddr =
2174 musb_read_txfunaddr(musb_base, i);
2175 musb->context.index_regs[i].txhubaddr =
2176 musb_read_txhubaddr(musb_base, i);
2177 musb->context.index_regs[i].txhubport =
2178 musb_read_txhubport(musb_base, i);
2179
2180 musb->context.index_regs[i].rxfunaddr =
2181 musb_read_rxfunaddr(musb_base, i);
2182 musb->context.index_regs[i].rxhubaddr =
2183 musb_read_rxhubaddr(musb_base, i);
2184 musb->context.index_regs[i].rxhubport =
2185 musb_read_rxhubport(musb_base, i);
2186 }
2187 }
2188
2189 static void musb_restore_context(struct musb *musb)
2190 {
2191 int i;
2192 void __iomem *musb_base = musb->mregs;
2193 void __iomem *ep_target_regs;
2194 void __iomem *epio;
2195 u8 power;
2196
2197 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2198 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2199 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2200
2201 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2202 power = musb_readb(musb_base, MUSB_POWER);
2203 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2204 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2205 power |= musb->context.power;
2206 musb_writeb(musb_base, MUSB_POWER, power);
2207
2208 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2209 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2210 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2211 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2212
2213 for (i = 0; i < musb->config->num_eps; ++i) {
2214 struct musb_hw_ep *hw_ep;
2215
2216 hw_ep = &musb->endpoints[i];
2217 if (!hw_ep)
2218 continue;
2219
2220 epio = hw_ep->regs;
2221 if (!epio)
2222 continue;
2223
2224 musb_writeb(musb_base, MUSB_INDEX, i);
2225 musb_writew(epio, MUSB_TXMAXP,
2226 musb->context.index_regs[i].txmaxp);
2227 musb_writew(epio, MUSB_TXCSR,
2228 musb->context.index_regs[i].txcsr);
2229 musb_writew(epio, MUSB_RXMAXP,
2230 musb->context.index_regs[i].rxmaxp);
2231 musb_writew(epio, MUSB_RXCSR,
2232 musb->context.index_regs[i].rxcsr);
2233
2234 if (musb->dyn_fifo) {
2235 musb_write_txfifosz(musb_base,
2236 musb->context.index_regs[i].txfifosz);
2237 musb_write_rxfifosz(musb_base,
2238 musb->context.index_regs[i].rxfifosz);
2239 musb_write_txfifoadd(musb_base,
2240 musb->context.index_regs[i].txfifoadd);
2241 musb_write_rxfifoadd(musb_base,
2242 musb->context.index_regs[i].rxfifoadd);
2243 }
2244
2245 musb_writeb(epio, MUSB_TXTYPE,
2246 musb->context.index_regs[i].txtype);
2247 musb_writeb(epio, MUSB_TXINTERVAL,
2248 musb->context.index_regs[i].txinterval);
2249 musb_writeb(epio, MUSB_RXTYPE,
2250 musb->context.index_regs[i].rxtype);
2251 musb_writeb(epio, MUSB_RXINTERVAL,
2252
2253 musb->context.index_regs[i].rxinterval);
2254 musb_write_txfunaddr(musb_base, i,
2255 musb->context.index_regs[i].txfunaddr);
2256 musb_write_txhubaddr(musb_base, i,
2257 musb->context.index_regs[i].txhubaddr);
2258 musb_write_txhubport(musb_base, i,
2259 musb->context.index_regs[i].txhubport);
2260
2261 ep_target_regs =
2262 musb_read_target_reg_base(i, musb_base);
2263
2264 musb_write_rxfunaddr(ep_target_regs,
2265 musb->context.index_regs[i].rxfunaddr);
2266 musb_write_rxhubaddr(ep_target_regs,
2267 musb->context.index_regs[i].rxhubaddr);
2268 musb_write_rxhubport(ep_target_regs,
2269 musb->context.index_regs[i].rxhubport);
2270 }
2271 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2272 }
2273
2274 static int musb_suspend(struct device *dev)
2275 {
2276 struct musb *musb = dev_to_musb(dev);
2277 unsigned long flags;
2278
2279 spin_lock_irqsave(&musb->lock, flags);
2280
2281 if (is_peripheral_active(musb)) {
2282 /* FIXME force disconnect unless we know USB will wake
2283 * the system up quickly enough to respond ...
2284 */
2285 } else if (is_host_active(musb)) {
2286 /* we know all the children are suspended; sometimes
2287 * they will even be wakeup-enabled.
2288 */
2289 }
2290
2291 musb_save_context(musb);
2292
2293 spin_unlock_irqrestore(&musb->lock, flags);
2294 return 0;
2295 }
2296
2297 static int musb_resume(struct device *dev)
2298 {
2299 struct musb *musb = dev_to_musb(dev);
2300 u8 devctl;
2301 u8 mask;
2302
2303 /*
2304 * For static cmos like DaVinci, register values were preserved
2305 * unless for some reason the whole soc powered down or the USB
2306 * module got reset through the PSC (vs just being disabled).
2307 *
2308 * For the DSPS glue layer though, a full register restore has to
2309 * be done. As it shouldn't harm other platforms, we do it
2310 * unconditionally.
2311 */
2312
2313 musb_restore_context(musb);
2314
2315 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2316 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2317 if ((devctl & mask) != (musb->context.devctl & mask))
2318 musb->port1_status = 0;
2319 if (musb->need_finish_resume) {
2320 musb->need_finish_resume = 0;
2321 schedule_delayed_work(&musb->finish_resume_work,
2322 msecs_to_jiffies(20));
2323 }
2324 return 0;
2325 }
2326
2327 static int musb_runtime_suspend(struct device *dev)
2328 {
2329 struct musb *musb = dev_to_musb(dev);
2330
2331 musb_save_context(musb);
2332
2333 return 0;
2334 }
2335
2336 static int musb_runtime_resume(struct device *dev)
2337 {
2338 struct musb *musb = dev_to_musb(dev);
2339 static int first = 1;
2340
2341 /*
2342 * When pm_runtime_get_sync called for the first time in driver
2343 * init, some of the structure is still not initialized which is
2344 * used in restore function. But clock needs to be
2345 * enabled before any register access, so
2346 * pm_runtime_get_sync has to be called.
2347 * Also context restore without save does not make
2348 * any sense
2349 */
2350 if (!first)
2351 musb_restore_context(musb);
2352 first = 0;
2353
2354 return 0;
2355 }
2356
2357 static const struct dev_pm_ops musb_dev_pm_ops = {
2358 .suspend = musb_suspend,
2359 .resume = musb_resume,
2360 .runtime_suspend = musb_runtime_suspend,
2361 .runtime_resume = musb_runtime_resume,
2362 };
2363
2364 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2365 #else
2366 #define MUSB_DEV_PM_OPS NULL
2367 #endif
2368
2369 static struct platform_driver musb_driver = {
2370 .driver = {
2371 .name = (char *)musb_driver_name,
2372 .bus = &platform_bus_type,
2373 .owner = THIS_MODULE,
2374 .pm = MUSB_DEV_PM_OPS,
2375 },
2376 .probe = musb_probe,
2377 .remove = musb_remove,
2378 .shutdown = musb_shutdown,
2379 };
2380
2381 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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