elfcpp/mips.h

   1 // mips.h -- ELF definitions specific to EM_MIPS  -*- C++ -*-
   2
   3 // Copyright (C) 2012-2014 Free Software Foundation, Inc.
   4 // Written by Aleksandar Simeonov <aleksandar.simeonov@rt-rk.com>.
   5
   6 // This file is part of elfcpp.
   7
   8 // This program is free software; you can redistribute it and/or
   9 // modify it under the terms of the GNU Library General Public License
  10 // as published by the Free Software Foundation; either version 2, or
  11 // (at your option) any later version.
  12
  13 // In addition to the permissions in the GNU Library General Public
  14 // License, the Free Software Foundation gives you unlimited
  15 // permission to link the compiled version of this file into
  16 // combinations with other programs, and to distribute those
  17 // combinations without any restriction coming from the use of this
  18 // file.  (The Library Public License restrictions do apply in other
  19 // respects; for example, they cover modification of the file, and
  20 /// distribution when not linked into a combined executable.)
  21
  22 // This program is distributed in the hope that it will be useful, but
  23 // WITHOUT ANY WARRANTY; without even the implied warranty of
  24 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  25 // Library General Public License for more details.
  26
  27 // You should have received a copy of the GNU Library General Public
  28 // License along with this program; if not, write to the Free Software
  29 // Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  30 // 02110-1301, USA.
  31
  32 #ifndef ELFCPP_MIPS_H
  33 #define ELFCPP_MIPS_H
  34
  35 // Documentation for the MIPS relocs is taken from
  36 //   http://math-atlas.sourceforge.net/devel/assembly/mipsabi32.pdf
  37
  38 namespace elfcpp
  39 {
  40
  41 //
  42 // MIPS Relocation Codes
  43 //
  44
  45 enum
  46 {
  47   R_MIPS_NONE = 0,
  48   R_MIPS_16 = 1,
  49   R_MIPS_32 = 2,
  50   R_MIPS_REL32 = 3,
  51   R_MIPS_26 = 4,
  52   R_MIPS_HI16 = 5,
  53   R_MIPS_LO16 = 6,
  54   R_MIPS_GPREL16 = 7,
  55   R_MIPS_LITERAL = 8,
  56   R_MIPS_GOT16 = 9,
  57   R_MIPS_PC16 = 10,
  58   R_MIPS_CALL16 = 11,
  59   R_MIPS_GPREL32 = 12,
  60   R_MIPS_UNUSED1 = 13,
  61   R_MIPS_UNUSED2 = 14,
  62   R_MIPS_UNUSED3 = 15,
  63   R_MIPS_SHIFT5 = 16,
  64   R_MIPS_SHIFT6 = 17,
  65   R_MIPS_64 = 18,
  66   R_MIPS_GOT_DISP = 19,
  67   R_MIPS_GOT_PAGE = 20,
  68   R_MIPS_GOT_OFST = 21,
  69   R_MIPS_GOT_HI16 = 22,
  70   R_MIPS_GOT_LO16 = 23,
  71   R_MIPS_SUB = 24,
  72   R_MIPS_INSERT_A = 25,         // Empty relocation
  73   R_MIPS_INSERT_B = 26,         // Empty relocation
  74   R_MIPS_DELETE = 27,           // Empty relocation
  75   R_MIPS_HIGHER = 28,
  76   R_MIPS_HIGHEST = 29,
  77   R_MIPS_CALL_HI16 = 30,
  78   R_MIPS_CALL_LO16 = 31,
  79   R_MIPS_SCN_DISP = 32,
  80   R_MIPS_REL16 = 33,            // Empty relocation
  81   R_MIPS_ADD_IMMEDIATE = 34,    // Empty relocation
  82   R_MIPS_PJUMP = 35,            // Empty relocation
  83   R_MIPS_RELGOT = 36,           // Empty relocation
  84   R_MIPS_JALR = 37,
  85   R_MIPS_TLS_DTPMOD32 = 38,
  86   R_MIPS_TLS_DTPREL32 = 39,
  87   R_MIPS_TLS_DTPMOD64 = 40,     // Empty relocation
  88   R_MIPS_TLS_DTPREL64 = 41,     // Empty relocation
  89   R_MIPS_TLS_GD = 42,
  90   R_MIPS_TLS_LDM = 43,
  91   R_MIPS_TLS_DTPREL_HI16 = 44,
  92   R_MIPS_TLS_DTPREL_LO16 = 45,
  93   R_MIPS_TLS_GOTTPREL = 46,
  94   R_MIPS_TLS_TPREL32 = 47,
  95   R_MIPS_TLS_TPREL64 = 48,      // Empty relocation
  96   R_MIPS_TLS_TPREL_HI16 = 49,
  97   R_MIPS_TLS_TPREL_LO16 = 50,
  98   R_MIPS_GLOB_DAT = 51,
  99   R_MIPS16_26 = 100,
 100   R_MIPS16_GPREL = 101,
 101   R_MIPS16_GOT16 = 102,
 102   R_MIPS16_CALL16 = 103,
 103   R_MIPS16_HI16 = 104,
 104   R_MIPS16_LO16 = 105,
 105   R_MIPS_COPY = 126,
 106   R_MIPS_JUMP_SLOT = 127,
 107   R_MIPS_PC32 = 248,
 108   R_MIPS_GNU_REL16_S2 = 250,
 109   R_MIPS_GNU_VTINHERIT = 253,
 110   R_MIPS_GNU_VTENTRY = 254
 111 };
 112
 113 // Processor specific flags for the ELF header e_flags field.  */
 114 enum
 115 {
 116   // At least one .noreorder directive appears in the source.
 117   EF_MIPS_NOREORDER = 0x00000001,
 118   // File contains position independent code.
 119   EF_MIPS_PIC = 0x00000002,
 120   // Code in file uses the standard calling sequence for calling
 121   // position independent code.
 122   EF_MIPS_CPIC = 0x00000004,
 123   // ???  Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a.
 124   EF_MIPS_XGOT = 0x00000008,
 125   // Code in file uses UCODE (obsolete)
 126   EF_MIPS_UCODE = 0x00000010,
 127   // Code in file uses new ABI (-n32 on Irix 6).
 128   EF_MIPS_ABI2 = 0x00000020,
 129   // Process the .MIPS.options section first by ld
 130   EF_MIPS_OPTIONS_FIRST = 0x00000080,
 131   // Architectural Extensions used by this file
 132   EF_MIPS_ARCH_ASE = 0x0f000000,
 133   // Use MDMX multimedia extensions
 134   EF_MIPS_ARCH_ASE_MDMX = 0x08000000,
 135   // Use MIPS-16 ISA extensions
 136   EF_MIPS_ARCH_ASE_M16 = 0x04000000,
 137   // Use MICROMIPS ISA extensions.
 138   EF_MIPS_ARCH_ASE_MICROMIPS = 0x02000000,
 139   // Indicates code compiled for a 64-bit machine in 32-bit mode.
 140   // (regs are 32-bits wide.)
 141   EF_MIPS_32BITMODE = 0x00000100,
 142   // MIPS dynamic
 143   EF_MIPS_DYNAMIC = 0x40
 144 };
 145
 146 // Machine variant if we know it.  This field was invented at Cygnus,
 147 // but it is hoped that other vendors will adopt it.  If some standard
 148 // is developed, this code should be changed to follow it.
 149 enum
 150 {
 151   EF_MIPS_MACH = 0x00FF0000,
 152
 153 // Cygnus is choosing values between 80 and 9F;
 154 // 00 - 7F should be left for a future standard;
 155 // the rest are open.
 156
 157   E_MIPS_MACH_3900 = 0x00810000,
 158   E_MIPS_MACH_4010 = 0x00820000,
 159   E_MIPS_MACH_4100 = 0x00830000,
 160   E_MIPS_MACH_4650 = 0x00850000,
 161   E_MIPS_MACH_4120 = 0x00870000,
 162   E_MIPS_MACH_4111 = 0x00880000,
 163   E_MIPS_MACH_SB1 = 0x008a0000,
 164   E_MIPS_MACH_OCTEON = 0x008b0000,
 165   E_MIPS_MACH_XLR = 0x008c0000,
 166   E_MIPS_MACH_OCTEON2 = 0x008d0000,
 167   E_MIPS_MACH_OCTEON3 = 0x008e0000,
 168   E_MIPS_MACH_5400 = 0x00910000,
 169   E_MIPS_MACH_5500 = 0x00980000,
 170   E_MIPS_MACH_9000 = 0x00990000,
 171   E_MIPS_MACH_LS2E = 0x00A00000,
 172   E_MIPS_MACH_LS2F = 0x00A10000,
 173   E_MIPS_MACH_LS3A = 0x00A20000,
 174 };
 175
 176 // MIPS architecture
 177 enum
 178 {
 179   // Four bit MIPS architecture field.
 180   EF_MIPS_ARCH = 0xf0000000,
 181   // -mips1 code.
 182   E_MIPS_ARCH_1 = 0x00000000,
 183   // -mips2 code.
 184   E_MIPS_ARCH_2 = 0x10000000,
 185   // -mips3 code.
 186   E_MIPS_ARCH_3 = 0x20000000,
 187   // -mips4 code.
 188   E_MIPS_ARCH_4 = 0x30000000,
 189   // -mips5 code.
 190   E_MIPS_ARCH_5 = 0x40000000,
 191   // -mips32 code.
 192   E_MIPS_ARCH_32 = 0x50000000,
 193   // -mips64 code.
 194   E_MIPS_ARCH_64 = 0x60000000,
 195   // -mips32r2 code.
 196   E_MIPS_ARCH_32R2 = 0x70000000,
 197   // -mips64r2 code.
 198   E_MIPS_ARCH_64R2 = 0x80000000,
 199 };
 200
 201 enum
 202 {
 203   // Mask to extract ABI version, not really a flag value.
 204   EF_MIPS_ABI = 0x0000F000,
 205
 206   // The original o32 abi.
 207   E_MIPS_ABI_O32 = 0x00001000,
 208   // O32 extended to work on 64 bit architectures
 209   E_MIPS_ABI_O64 = 0x00002000,
 210   // EABI in 32 bit mode
 211   E_MIPS_ABI_EABI32 = 0x00003000,
 212   // EABI in 64 bit mode
 213   E_MIPS_ABI_EABI64 = 0x00004000,
 214 };
 215
 216 // Dynamic section MIPS flags
 217 enum
 218 {
 219   // None
 220   RHF_NONE = 0x00000000,
 221   // Use shortcut pointers
 222   RHF_QUICKSTART = 0x00000001,
 223   // Hash size not power of two
 224   RHF_NOTPOT = 0x00000002,
 225   // Ignore LD_LIBRARY_PATH
 226   RHF_NO_LIBRARY_REPLACEMENT = 0x00000004
 227 };
 228
 229 // Special values for the st_other field in the symbol table.
 230 enum
 231 {
 232   // Two topmost bits denote the MIPS ISA for .text symbols:
 233   // + 00 -- standard MIPS code,
 234   // + 10 -- microMIPS code,
 235   // + 11 -- MIPS16 code; requires the following two bits to be set too.
 236   // Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC.
 237   STO_MIPS_ISA = 0xc0,
 238
 239   // The MIPS psABI was updated in 2008 with support for PLTs and copy
 240   // relocs.  There are therefore two types of nonzero SHN_UNDEF functions:
 241   // PLT entries and traditional MIPS lazy binding stubs.  We mark the former
 242   // with STO_MIPS_PLT to distinguish them from the latter.
 243   STO_MIPS_PLT = 0x8,
 244
 245   // This value is used to mark PIC functions in an object that mixes
 246   // PIC and non-PIC.  Note that this bit overlaps with STO_MIPS16,
 247   // although MIPS16 symbols are never considered to be MIPS_PIC.
 248   STO_MIPS_PIC = 0x20,
 249
 250   // This value is used for a mips16 .text symbol.
 251   STO_MIPS16 = 0xf0,
 252
 253   // This value is used for a microMIPS .text symbol.  To distinguish from
 254   // STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS.  The
 255   // mask is STO_MIPS_ISA.
 256   STO_MICROMIPS  = 0x80
 257 };
 258
 259 // Values for base offsets for thread-local storage
 260 enum
 261 {
 262   TP_OFFSET = 0x7000,
 263   DTP_OFFSET = 0x8000
 264 };
 265
 266 } // End namespace elfcpp.
 267
 268 #endif // !defined(ELFCPP_MIPS_H)