1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
288 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
292 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
293 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: same, plus SVE registers. */ \
296 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
299 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
300 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
302 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
306 /* Typecheck: any [BHSDQ]P FP. */ \
307 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
308 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
309 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
310 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
312 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
313 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
314 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
315 be used for SVE instructions, since Zn and Pn are valid symbols \
316 in other contexts. */ \
317 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
322 | REG_TYPE(ZN) | REG_TYPE(PN)) \
323 /* Any integer register; used for error messages only. */ \
324 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
326 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
327 /* Pseudo type to mark the end of the enumerator sequence. */ \
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
332 #undef MULTI_REG_TYPE
333 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
335 /* Register type enumerators. */
336 typedef enum aarch64_reg_type_
338 /* A list of REG_TYPE_*. */
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
345 #define REG_TYPE(T) (1 << REG_TYPE_##T)
346 #undef MULTI_REG_TYPE
347 #define MULTI_REG_TYPE(T,V) V,
349 /* Structure for a hash table entry for a register. */
353 unsigned char number
;
354 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
355 unsigned char builtin
;
358 /* Values indexed by aarch64_reg_type to assist the type checking. */
359 static const unsigned reg_type_masks
[] =
364 #undef BASIC_REG_TYPE
366 #undef MULTI_REG_TYPE
367 #undef AARCH64_REG_TYPES
369 /* Diagnostics used when we don't get a register of the expected type.
370 Note: this has to synchronized with aarch64_reg_type definitions
373 get_reg_expected_msg (aarch64_reg_type reg_type
)
380 msg
= N_("integer 32-bit register expected");
383 msg
= N_("integer 64-bit register expected");
386 msg
= N_("integer register expected");
388 case REG_TYPE_R64_SP
:
389 msg
= N_("64-bit integer or SP register expected");
391 case REG_TYPE_SVE_BASE
:
392 msg
= N_("base register expected");
395 msg
= N_("integer or zero register expected");
397 case REG_TYPE_SVE_OFFSET
:
398 msg
= N_("offset register expected");
401 msg
= N_("integer or SP register expected");
403 case REG_TYPE_R_Z_SP
:
404 msg
= N_("integer, zero or SP register expected");
407 msg
= N_("8-bit SIMD scalar register expected");
410 msg
= N_("16-bit SIMD scalar or floating-point half precision "
411 "register expected");
414 msg
= N_("32-bit SIMD scalar or floating-point single precision "
415 "register expected");
418 msg
= N_("64-bit SIMD scalar or floating-point double precision "
419 "register expected");
422 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
423 "register expected");
425 case REG_TYPE_R_Z_BHSDQ_V
:
426 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
427 msg
= N_("register expected");
429 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
430 msg
= N_("SIMD scalar or floating-point register expected");
432 case REG_TYPE_VN
: /* any V reg */
433 msg
= N_("vector register expected");
436 msg
= N_("SVE vector register expected");
439 msg
= N_("SVE predicate register expected");
442 as_fatal (_("invalid register type %d"), reg_type
);
447 /* Some well known registers that we refer to directly elsewhere. */
451 /* Instructions take 4 bytes in the object file. */
454 static struct hash_control
*aarch64_ops_hsh
;
455 static struct hash_control
*aarch64_cond_hsh
;
456 static struct hash_control
*aarch64_shift_hsh
;
457 static struct hash_control
*aarch64_sys_regs_hsh
;
458 static struct hash_control
*aarch64_pstatefield_hsh
;
459 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
460 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
461 static struct hash_control
*aarch64_sys_regs_at_hsh
;
462 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
463 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
464 static struct hash_control
*aarch64_reg_hsh
;
465 static struct hash_control
*aarch64_barrier_opt_hsh
;
466 static struct hash_control
*aarch64_nzcv_hsh
;
467 static struct hash_control
*aarch64_pldop_hsh
;
468 static struct hash_control
*aarch64_hint_opt_hsh
;
470 /* Stuff needed to resolve the label ambiguity
479 static symbolS
*last_label_seen
;
481 /* Literal pool structure. Held on a per-section
482 and per-sub-section basis. */
484 #define MAX_LITERAL_POOL_SIZE 1024
485 typedef struct literal_expression
488 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
489 LITTLENUM_TYPE
* bignum
;
490 } literal_expression
;
492 typedef struct literal_pool
494 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
495 unsigned int next_free_entry
;
501 struct literal_pool
*next
;
504 /* Pointer to a linked list of literal pools. */
505 static literal_pool
*list_of_pools
= NULL
;
509 /* This array holds the chars that always start a comment. If the
510 pre-processor is disabled, these aren't very useful. */
511 const char comment_chars
[] = "";
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output. */
516 /* Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output. */
519 /* Also note that comments like this one will always work. */
520 const char line_comment_chars
[] = "#";
522 const char line_separator_chars
[] = ";";
524 /* Chars that can be used to separate mant
525 from exp in floating point numbers. */
526 const char EXP_CHARS
[] = "eE";
528 /* Chars that mean this number is a floating point constant. */
532 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
534 /* Prefix character that indicates the start of an immediate value. */
535 #define is_immediate_prefix(C) ((C) == '#')
537 /* Separator character handling. */
539 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
541 static inline bfd_boolean
542 skip_past_char (char **str
, char c
)
553 #define skip_past_comma(str) skip_past_char (str, ',')
555 /* Arithmetic expressions (possibly involving symbols). */
557 static bfd_boolean in_my_get_expression_p
= FALSE
;
559 /* Third argument to my_get_expression. */
560 #define GE_NO_PREFIX 0
561 #define GE_OPT_PREFIX 1
563 /* Return TRUE if the string pointed by *STR is successfully parsed
564 as an valid expression; *EP will be filled with the information of
565 such an expression. Otherwise return FALSE. */
568 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
573 int prefix_present_p
= 0;
580 if (is_immediate_prefix (**str
))
583 prefix_present_p
= 1;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_my_get_expression_p
= TRUE
;
595 seg
= expression (ep
);
596 in_my_get_expression_p
= FALSE
;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present_p
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
&& seg
!= undefined_section
)
616 set_syntax_error (_("bad segment"));
617 *str
= input_line_pointer
;
618 input_line_pointer
= save_in
;
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
630 /* Turn a string in input_line_pointer into a floating point constant
631 of type TYPE, and store the appropriate bytes in *LITP. The number
632 of LITTLENUMS emitted is stored in *SIZEP. An error message is
633 returned, or NULL on OK. */
636 md_atof (int type
, char *litP
, int *sizeP
)
638 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
641 /* We handle all bad expressions here, so that we can report the faulty
642 instruction in the error message. */
644 md_operand (expressionS
* exp
)
646 if (in_my_get_expression_p
)
647 exp
->X_op
= O_illegal
;
650 /* Immediate values. */
652 /* Errors may be set multiple times during parsing or bit encoding
653 (particularly in the Neon bits), but usually the earliest error which is set
654 will be the most meaningful. Avoid overwriting it with later (cascading)
655 errors by calling this function. */
658 first_error (const char *error
)
661 set_syntax_error (error
);
664 /* Similar to first_error, but this function accepts formatted error
667 first_error_fmt (const char *format
, ...)
672 /* N.B. this single buffer will not cause error messages for different
673 instructions to pollute each other; this is because at the end of
674 processing of each assembly line, error message if any will be
675 collected by as_bad. */
676 static char buffer
[size
];
680 int ret ATTRIBUTE_UNUSED
;
681 va_start (args
, format
);
682 ret
= vsnprintf (buffer
, size
, format
, args
);
683 know (ret
<= size
- 1 && ret
>= 0);
685 set_syntax_error (buffer
);
689 /* Register parsing. */
691 /* Generic register parser which is called by other specialized
693 CCP points to what should be the beginning of a register name.
694 If it is indeed a valid register name, advance CCP over it and
695 return the reg_entry structure; otherwise return NULL.
696 It does not issue diagnostics. */
699 parse_reg (char **ccp
)
705 #ifdef REGISTER_PREFIX
706 if (*start
!= REGISTER_PREFIX
)
712 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
717 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
719 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
728 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
731 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
733 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
736 /* Try to parse a base or offset register. Allow SVE base and offset
737 registers if REG_TYPE includes SVE registers. Return the register
738 entry on success, setting *QUALIFIER to the register qualifier.
739 Return null otherwise.
741 Note that this function does not issue any diagnostics. */
743 static const reg_entry
*
744 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
745 aarch64_opnd_qualifier_t
*qualifier
)
748 const reg_entry
*reg
= parse_reg (&str
);
758 *qualifier
= AARCH64_OPND_QLF_W
;
764 *qualifier
= AARCH64_OPND_QLF_X
;
768 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
771 switch (TOLOWER (str
[1]))
774 *qualifier
= AARCH64_OPND_QLF_S_S
;
777 *qualifier
= AARCH64_OPND_QLF_S_D
;
794 /* Try to parse a base or offset register. Return the register entry
795 on success, setting *QUALIFIER to the register qualifier. Return null
798 Note that this function does not issue any diagnostics. */
800 static const reg_entry
*
801 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
803 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
806 /* Parse the qualifier of a vector register or vector element of type
807 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
808 succeeds; otherwise return FALSE.
810 Accept only one occurrence of:
811 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
814 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
815 struct vector_type_el
*parsed_type
, char **str
)
819 unsigned element_size
;
820 enum vector_el_type type
;
823 gas_assert (*ptr
== '.');
826 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
831 width
= strtoul (ptr
, &ptr
, 10);
832 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
834 first_error_fmt (_("bad size %d in vector width specifier"), width
);
839 switch (TOLOWER (*ptr
))
858 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
867 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
869 first_error (_("missing element size"));
872 if (width
!= 0 && width
* element_size
!= 64
873 && width
* element_size
!= 128
874 && !(width
== 2 && element_size
== 16)
875 && !(width
== 4 && element_size
== 8))
878 ("invalid element size %d and vector size combination %c"),
884 parsed_type
->type
= type
;
885 parsed_type
->width
= width
;
892 /* *STR contains an SVE zero/merge predication suffix. Parse it into
893 *PARSED_TYPE and point *STR at the end of the suffix. */
896 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
901 gas_assert (*ptr
== '/');
903 switch (TOLOWER (*ptr
))
906 parsed_type
->type
= NT_zero
;
909 parsed_type
->type
= NT_merge
;
912 if (*ptr
!= '\0' && *ptr
!= ',')
913 first_error_fmt (_("unexpected character `%c' in predication type"),
916 first_error (_("missing predication type"));
919 parsed_type
->width
= 0;
924 /* Parse a register of the type TYPE.
926 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
927 name or the parsed register is not of TYPE.
929 Otherwise return the register number, and optionally fill in the actual
930 type of the register in *RTYPE when multiple alternatives were given, and
931 return the register shape and element index information in *TYPEINFO.
933 IN_REG_LIST should be set with TRUE if the caller is parsing a register
937 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
938 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
941 const reg_entry
*reg
= parse_reg (&str
);
942 struct vector_type_el atype
;
943 struct vector_type_el parsetype
;
944 bfd_boolean is_typed_vecreg
= FALSE
;
947 atype
.type
= NT_invtype
;
955 set_default_error ();
959 if (! aarch64_check_reg_type (reg
, type
))
961 DEBUG_TRACE ("reg type check failed");
962 set_default_error ();
967 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
968 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
972 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
977 if (!parse_predication_for_operand (&parsetype
, &str
))
981 /* Register if of the form Vn.[bhsdq]. */
982 is_typed_vecreg
= TRUE
;
984 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
986 /* The width is always variable; we don't allow an integer width
988 gas_assert (parsetype
.width
== 0);
989 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
991 else if (parsetype
.width
== 0)
992 /* Expect index. In the new scheme we cannot have
993 Vn.[bhsdq] represent a scalar. Therefore any
994 Vn.[bhsdq] should have an index following it.
995 Except in reglists of course. */
996 atype
.defined
|= NTA_HASINDEX
;
998 atype
.defined
|= NTA_HASTYPE
;
1000 atype
.type
= parsetype
.type
;
1001 atype
.width
= parsetype
.width
;
1004 if (skip_past_char (&str
, '['))
1008 /* Reject Sn[index] syntax. */
1009 if (!is_typed_vecreg
)
1011 first_error (_("this type of register can't be indexed"));
1017 first_error (_("index not allowed inside register list"));
1021 atype
.defined
|= NTA_HASINDEX
;
1023 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1025 if (exp
.X_op
!= O_constant
)
1027 first_error (_("constant expression required"));
1031 if (! skip_past_char (&str
, ']'))
1034 atype
.index
= exp
.X_add_number
;
1036 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1038 /* Indexed vector register expected. */
1039 first_error (_("indexed vector register expected"));
1043 /* A vector reg Vn should be typed or indexed. */
1044 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1046 first_error (_("invalid use of vector register"));
1062 Return the register number on success; return PARSE_FAIL otherwise.
1064 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1065 the register (e.g. NEON double or quad reg when either has been requested).
1067 If this is a NEON vector register with additional type information, fill
1068 in the struct pointed to by VECTYPE (if non-NULL).
1070 This parser does not handle register list. */
1073 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1074 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1076 struct vector_type_el atype
;
1078 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1079 /*in_reg_list= */ FALSE
);
1081 if (reg
== PARSE_FAIL
)
1092 static inline bfd_boolean
1093 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1097 && e1
.defined
== e2
.defined
1098 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1101 /* This function parses a list of vector registers of type TYPE.
1102 On success, it returns the parsed register list information in the
1103 following encoded format:
1105 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1106 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1108 The information of the register shape and/or index is returned in
1111 It returns PARSE_FAIL if the register list is invalid.
1113 The list contains one to four registers.
1114 Each register can be one of:
1117 All <T> should be identical.
1118 All <index> should be identical.
1119 There are restrictions on <Vt> numbers which are checked later
1120 (by reg_list_valid_p). */
1123 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1124 struct vector_type_el
*vectype
)
1128 struct vector_type_el typeinfo
, typeinfo_first
;
1133 bfd_boolean error
= FALSE
;
1134 bfd_boolean expect_index
= FALSE
;
1138 set_syntax_error (_("expecting {"));
1144 typeinfo_first
.defined
= 0;
1145 typeinfo_first
.type
= NT_invtype
;
1146 typeinfo_first
.width
= -1;
1147 typeinfo_first
.index
= 0;
1156 str
++; /* skip over '-' */
1159 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1160 /*in_reg_list= */ TRUE
);
1161 if (val
== PARSE_FAIL
)
1163 set_first_syntax_error (_("invalid vector register in list"));
1167 /* reject [bhsd]n */
1168 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1170 set_first_syntax_error (_("invalid scalar register in list"));
1175 if (typeinfo
.defined
& NTA_HASINDEX
)
1176 expect_index
= TRUE
;
1180 if (val
< val_range
)
1182 set_first_syntax_error
1183 (_("invalid range in vector register list"));
1192 typeinfo_first
= typeinfo
;
1193 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1195 set_first_syntax_error
1196 (_("type mismatch in vector register list"));
1201 for (i
= val_range
; i
<= val
; i
++)
1203 ret_val
|= i
<< (5 * nb_regs
);
1208 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1210 skip_whitespace (str
);
1213 set_first_syntax_error (_("end of vector register list not found"));
1218 skip_whitespace (str
);
1222 if (skip_past_char (&str
, '['))
1226 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1227 if (exp
.X_op
!= O_constant
)
1229 set_first_syntax_error (_("constant expression required."));
1232 if (! skip_past_char (&str
, ']'))
1235 typeinfo_first
.index
= exp
.X_add_number
;
1239 set_first_syntax_error (_("expected index"));
1246 set_first_syntax_error (_("too many registers in vector register list"));
1249 else if (nb_regs
== 0)
1251 set_first_syntax_error (_("empty vector register list"));
1257 *vectype
= typeinfo_first
;
1259 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1262 /* Directives: register aliases. */
1265 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1270 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1273 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1276 /* Only warn about a redefinition if it's not defined as the
1278 else if (new->number
!= number
|| new->type
!= type
)
1279 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1284 name
= xstrdup (str
);
1285 new = XNEW (reg_entry
);
1288 new->number
= number
;
1290 new->builtin
= FALSE
;
1292 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1298 /* Look for the .req directive. This is of the form:
1300 new_register_name .req existing_register_name
1302 If we find one, or if it looks sufficiently like one that we want to
1303 handle any error here, return TRUE. Otherwise return FALSE. */
1306 create_register_alias (char *newname
, char *p
)
1308 const reg_entry
*old
;
1309 char *oldname
, *nbuf
;
1312 /* The input scrubber ensures that whitespace after the mnemonic is
1313 collapsed to single spaces. */
1315 if (strncmp (oldname
, " .req ", 6) != 0)
1319 if (*oldname
== '\0')
1322 old
= hash_find (aarch64_reg_hsh
, oldname
);
1325 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1329 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1330 the desired alias name, and p points to its end. If not, then
1331 the desired alias name is in the global original_case_string. */
1332 #ifdef TC_CASE_SENSITIVE
1335 newname
= original_case_string
;
1336 nlen
= strlen (newname
);
1339 nbuf
= xmemdup0 (newname
, nlen
);
1341 /* Create aliases under the new name as stated; an all-lowercase
1342 version of the new name; and an all-uppercase version of the new
1344 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1346 for (p
= nbuf
; *p
; p
++)
1349 if (strncmp (nbuf
, newname
, nlen
))
1351 /* If this attempt to create an additional alias fails, do not bother
1352 trying to create the all-lower case alias. We will fail and issue
1353 a second, duplicate error message. This situation arises when the
1354 programmer does something like:
1357 The second .req creates the "Foo" alias but then fails to create
1358 the artificial FOO alias because it has already been created by the
1360 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1367 for (p
= nbuf
; *p
; p
++)
1370 if (strncmp (nbuf
, newname
, nlen
))
1371 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1378 /* Should never be called, as .req goes between the alias and the
1379 register name, not at the beginning of the line. */
1381 s_req (int a ATTRIBUTE_UNUSED
)
1383 as_bad (_("invalid syntax for .req directive"));
1386 /* The .unreq directive deletes an alias which was previously defined
1387 by .req. For example:
1393 s_unreq (int a ATTRIBUTE_UNUSED
)
1398 name
= input_line_pointer
;
1400 while (*input_line_pointer
!= 0
1401 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1402 ++input_line_pointer
;
1404 saved_char
= *input_line_pointer
;
1405 *input_line_pointer
= 0;
1408 as_bad (_("invalid syntax for .unreq directive"));
1411 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1414 as_bad (_("unknown register alias '%s'"), name
);
1415 else if (reg
->builtin
)
1416 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1423 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1424 free ((char *) reg
->name
);
1427 /* Also locate the all upper case and all lower case versions.
1428 Do not complain if we cannot find one or the other as it
1429 was probably deleted above. */
1431 nbuf
= strdup (name
);
1432 for (p
= nbuf
; *p
; p
++)
1434 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1437 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1438 free ((char *) reg
->name
);
1442 for (p
= nbuf
; *p
; p
++)
1444 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1447 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1448 free ((char *) reg
->name
);
1456 *input_line_pointer
= saved_char
;
1457 demand_empty_rest_of_line ();
1460 /* Directives: Instruction set selection. */
1463 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1464 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1465 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1466 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1468 /* Create a new mapping symbol for the transition to STATE. */
1471 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1474 const char *symname
;
1481 type
= BSF_NO_FLAGS
;
1485 type
= BSF_NO_FLAGS
;
1491 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1492 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1494 /* Save the mapping symbols for future reference. Also check that
1495 we do not place two mapping symbols at the same offset within a
1496 frag. We'll handle overlap between frags in
1497 check_mapping_symbols.
1499 If .fill or other data filling directive generates zero sized data,
1500 the mapping symbol for the following code will have the same value
1501 as the one generated for the data filling directive. In this case,
1502 we replace the old symbol with the new one at the same address. */
1505 if (frag
->tc_frag_data
.first_map
!= NULL
)
1507 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1508 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1511 frag
->tc_frag_data
.first_map
= symbolP
;
1513 if (frag
->tc_frag_data
.last_map
!= NULL
)
1515 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1516 S_GET_VALUE (symbolP
));
1517 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1518 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1521 frag
->tc_frag_data
.last_map
= symbolP
;
1524 /* We must sometimes convert a region marked as code to data during
1525 code alignment, if an odd number of bytes have to be padded. The
1526 code mapping symbol is pushed to an aligned address. */
1529 insert_data_mapping_symbol (enum mstate state
,
1530 valueT value
, fragS
* frag
, offsetT bytes
)
1532 /* If there was already a mapping symbol, remove it. */
1533 if (frag
->tc_frag_data
.last_map
!= NULL
1534 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1535 frag
->fr_address
+ value
)
1537 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1541 know (frag
->tc_frag_data
.first_map
== symp
);
1542 frag
->tc_frag_data
.first_map
= NULL
;
1544 frag
->tc_frag_data
.last_map
= NULL
;
1545 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1548 make_mapping_symbol (MAP_DATA
, value
, frag
);
1549 make_mapping_symbol (state
, value
+ bytes
, frag
);
1552 static void mapping_state_2 (enum mstate state
, int max_chars
);
1554 /* Set the mapping state to STATE. Only call this when about to
1555 emit some STATE bytes to the file. */
1558 mapping_state (enum mstate state
)
1560 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1562 if (state
== MAP_INSN
)
1563 /* AArch64 instructions require 4-byte alignment. When emitting
1564 instructions into any section, record the appropriate section
1566 record_alignment (now_seg
, 2);
1568 if (mapstate
== state
)
1569 /* The mapping symbol has already been emitted.
1570 There is nothing else to do. */
1573 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1574 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1575 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1576 evaluated later in the next else. */
1578 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1580 /* Only add the symbol if the offset is > 0:
1581 if we're at the first frag, check it's size > 0;
1582 if we're not at the first frag, then for sure
1583 the offset is > 0. */
1584 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1585 const int add_symbol
= (frag_now
!= frag_first
)
1586 || (frag_now_fix () > 0);
1589 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1593 mapping_state_2 (state
, 0);
1596 /* Same as mapping_state, but MAX_CHARS bytes have already been
1597 allocated. Put the mapping symbol that far back. */
1600 mapping_state_2 (enum mstate state
, int max_chars
)
1602 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1604 if (!SEG_NORMAL (now_seg
))
1607 if (mapstate
== state
)
1608 /* The mapping symbol has already been emitted.
1609 There is nothing else to do. */
1612 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1613 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1616 #define mapping_state(x) /* nothing */
1617 #define mapping_state_2(x, y) /* nothing */
1620 /* Directives: sectioning and alignment. */
1623 s_bss (int ignore ATTRIBUTE_UNUSED
)
1625 /* We don't support putting frags in the BSS segment, we fake it by
1626 marking in_bss, then looking at s_skip for clues. */
1627 subseg_set (bss_section
, 0);
1628 demand_empty_rest_of_line ();
1629 mapping_state (MAP_DATA
);
1633 s_even (int ignore ATTRIBUTE_UNUSED
)
1635 /* Never make frag if expect extra pass. */
1637 frag_align (1, 0, 0);
1639 record_alignment (now_seg
, 1);
1641 demand_empty_rest_of_line ();
1644 /* Directives: Literal pools. */
1646 static literal_pool
*
1647 find_literal_pool (int size
)
1651 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1653 if (pool
->section
== now_seg
1654 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1661 static literal_pool
*
1662 find_or_make_literal_pool (int size
)
1664 /* Next literal pool ID number. */
1665 static unsigned int latest_pool_num
= 1;
1668 pool
= find_literal_pool (size
);
1672 /* Create a new pool. */
1673 pool
= XNEW (literal_pool
);
1677 /* Currently we always put the literal pool in the current text
1678 section. If we were generating "small" model code where we
1679 knew that all code and initialised data was within 1MB then
1680 we could output literals to mergeable, read-only data
1683 pool
->next_free_entry
= 0;
1684 pool
->section
= now_seg
;
1685 pool
->sub_section
= now_subseg
;
1687 pool
->next
= list_of_pools
;
1688 pool
->symbol
= NULL
;
1690 /* Add it to the list. */
1691 list_of_pools
= pool
;
1694 /* New pools, and emptied pools, will have a NULL symbol. */
1695 if (pool
->symbol
== NULL
)
1697 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1698 (valueT
) 0, &zero_address_frag
);
1699 pool
->id
= latest_pool_num
++;
1706 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1707 Return TRUE on success, otherwise return FALSE. */
1709 add_to_lit_pool (expressionS
*exp
, int size
)
1714 pool
= find_or_make_literal_pool (size
);
1716 /* Check if this literal value is already in the pool. */
1717 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1719 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1721 if ((litexp
->X_op
== exp
->X_op
)
1722 && (exp
->X_op
== O_constant
)
1723 && (litexp
->X_add_number
== exp
->X_add_number
)
1724 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1727 if ((litexp
->X_op
== exp
->X_op
)
1728 && (exp
->X_op
== O_symbol
)
1729 && (litexp
->X_add_number
== exp
->X_add_number
)
1730 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1731 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1735 /* Do we need to create a new entry? */
1736 if (entry
== pool
->next_free_entry
)
1738 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1740 set_syntax_error (_("literal pool overflow"));
1744 pool
->literals
[entry
].exp
= *exp
;
1745 pool
->next_free_entry
+= 1;
1746 if (exp
->X_op
== O_big
)
1748 /* PR 16688: Bignums are held in a single global array. We must
1749 copy and preserve that value now, before it is overwritten. */
1750 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1752 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1753 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1756 pool
->literals
[entry
].bignum
= NULL
;
1759 exp
->X_op
= O_symbol
;
1760 exp
->X_add_number
= ((int) entry
) * size
;
1761 exp
->X_add_symbol
= pool
->symbol
;
1766 /* Can't use symbol_new here, so have to create a symbol and then at
1767 a later date assign it a value. That's what these functions do. */
1770 symbol_locate (symbolS
* symbolP
,
1771 const char *name
,/* It is copied, the caller can modify. */
1772 segT segment
, /* Segment identifier (SEG_<something>). */
1773 valueT valu
, /* Symbol value. */
1774 fragS
* frag
) /* Associated fragment. */
1777 char *preserved_copy_of_name
;
1779 name_length
= strlen (name
) + 1; /* +1 for \0. */
1780 obstack_grow (¬es
, name
, name_length
);
1781 preserved_copy_of_name
= obstack_finish (¬es
);
1783 #ifdef tc_canonicalize_symbol_name
1784 preserved_copy_of_name
=
1785 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1788 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1790 S_SET_SEGMENT (symbolP
, segment
);
1791 S_SET_VALUE (symbolP
, valu
);
1792 symbol_clear_list_pointers (symbolP
);
1794 symbol_set_frag (symbolP
, frag
);
1796 /* Link to end of symbol chain. */
1798 extern int symbol_table_frozen
;
1800 if (symbol_table_frozen
)
1804 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1806 obj_symbol_new_hook (symbolP
);
1808 #ifdef tc_symbol_new_hook
1809 tc_symbol_new_hook (symbolP
);
1813 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1814 #endif /* DEBUG_SYMS */
1819 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1826 for (align
= 2; align
<= 4; align
++)
1828 int size
= 1 << align
;
1830 pool
= find_literal_pool (size
);
1831 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1834 /* Align pool as you have word accesses.
1835 Only make a frag if we have to. */
1837 frag_align (align
, 0, 0);
1839 mapping_state (MAP_DATA
);
1841 record_alignment (now_seg
, align
);
1843 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1845 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1846 (valueT
) frag_now_fix (), frag_now
);
1847 symbol_table_insert (pool
->symbol
);
1849 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1851 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1853 if (exp
->X_op
== O_big
)
1855 /* PR 16688: Restore the global bignum value. */
1856 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1857 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1858 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1861 /* First output the expression in the instruction to the pool. */
1862 emit_expr (exp
, size
); /* .word|.xword */
1864 if (exp
->X_op
== O_big
)
1866 free (pool
->literals
[entry
].bignum
);
1867 pool
->literals
[entry
].bignum
= NULL
;
1871 /* Mark the pool as empty. */
1872 pool
->next_free_entry
= 0;
1873 pool
->symbol
= NULL
;
1878 /* Forward declarations for functions below, in the MD interface
1880 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1881 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1883 /* Directives: Data. */
1884 /* N.B. the support for relocation suffix in this directive needs to be
1885 implemented properly. */
1888 s_aarch64_elf_cons (int nbytes
)
1892 #ifdef md_flush_pending_output
1893 md_flush_pending_output ();
1896 if (is_it_end_of_statement ())
1898 demand_empty_rest_of_line ();
1902 #ifdef md_cons_align
1903 md_cons_align (nbytes
);
1906 mapping_state (MAP_DATA
);
1909 struct reloc_table_entry
*reloc
;
1913 if (exp
.X_op
!= O_symbol
)
1914 emit_expr (&exp
, (unsigned int) nbytes
);
1917 skip_past_char (&input_line_pointer
, '#');
1918 if (skip_past_char (&input_line_pointer
, ':'))
1920 reloc
= find_reloc_table_entry (&input_line_pointer
);
1922 as_bad (_("unrecognized relocation suffix"));
1924 as_bad (_("unimplemented relocation suffix"));
1925 ignore_rest_of_line ();
1929 emit_expr (&exp
, (unsigned int) nbytes
);
1932 while (*input_line_pointer
++ == ',');
1934 /* Put terminator back into stream. */
1935 input_line_pointer
--;
1936 demand_empty_rest_of_line ();
1939 /* Mark symbol that it follows a variant PCS convention. */
1942 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1948 elf_symbol_type
*elfsym
;
1950 c
= get_symbol_name (&name
);
1952 as_bad (_("Missing symbol name in directive"));
1953 sym
= symbol_find_or_make (name
);
1954 restore_line_pointer (c
);
1955 demand_empty_rest_of_line ();
1956 bfdsym
= symbol_get_bfdsym (sym
);
1957 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
1958 gas_assert (elfsym
);
1959 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1961 #endif /* OBJ_ELF */
1963 /* Output a 32-bit word, but mark as an instruction. */
1966 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1970 #ifdef md_flush_pending_output
1971 md_flush_pending_output ();
1974 if (is_it_end_of_statement ())
1976 demand_empty_rest_of_line ();
1980 /* Sections are assumed to start aligned. In executable section, there is no
1981 MAP_DATA symbol pending. So we only align the address during
1982 MAP_DATA --> MAP_INSN transition.
1983 For other sections, this is not guaranteed. */
1984 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1985 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1986 frag_align_code (2, 0);
1989 mapping_state (MAP_INSN
);
1995 if (exp
.X_op
!= O_constant
)
1997 as_bad (_("constant expression required"));
1998 ignore_rest_of_line ();
2002 if (target_big_endian
)
2004 unsigned int val
= exp
.X_add_number
;
2005 exp
.X_add_number
= SWAP_32 (val
);
2007 emit_expr (&exp
, 4);
2009 while (*input_line_pointer
++ == ',');
2011 /* Put terminator back into stream. */
2012 input_line_pointer
--;
2013 demand_empty_rest_of_line ();
2017 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2019 demand_empty_rest_of_line ();
2020 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2021 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2025 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2028 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2034 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2035 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2037 demand_empty_rest_of_line ();
2040 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2043 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2047 /* Since we're just labelling the code, there's no need to define a
2050 /* Make sure there is enough room in this frag for the following
2051 blr. This trick only works if the blr follows immediately after
2052 the .tlsdesc directive. */
2054 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2055 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2057 demand_empty_rest_of_line ();
2060 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2063 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2069 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2070 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2072 demand_empty_rest_of_line ();
2074 #endif /* OBJ_ELF */
2076 static void s_aarch64_arch (int);
2077 static void s_aarch64_cpu (int);
2078 static void s_aarch64_arch_extension (int);
2080 /* This table describes all the machine specific pseudo-ops the assembler
2081 has to support. The fields are:
2082 pseudo-op name without dot
2083 function to call to execute this pseudo-op
2084 Integer arg to pass to the function. */
2086 const pseudo_typeS md_pseudo_table
[] = {
2087 /* Never called because '.req' does not start a line. */
2089 {"unreq", s_unreq
, 0},
2091 {"even", s_even
, 0},
2092 {"ltorg", s_ltorg
, 0},
2093 {"pool", s_ltorg
, 0},
2094 {"cpu", s_aarch64_cpu
, 0},
2095 {"arch", s_aarch64_arch
, 0},
2096 {"arch_extension", s_aarch64_arch_extension
, 0},
2097 {"inst", s_aarch64_inst
, 0},
2098 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2100 {"tlsdescadd", s_tlsdescadd
, 0},
2101 {"tlsdesccall", s_tlsdesccall
, 0},
2102 {"tlsdescldr", s_tlsdescldr
, 0},
2103 {"word", s_aarch64_elf_cons
, 4},
2104 {"long", s_aarch64_elf_cons
, 4},
2105 {"xword", s_aarch64_elf_cons
, 8},
2106 {"dword", s_aarch64_elf_cons
, 8},
2107 {"variant_pcs", s_variant_pcs
, 0},
2113 /* Check whether STR points to a register name followed by a comma or the
2114 end of line; REG_TYPE indicates which register types are checked
2115 against. Return TRUE if STR is such a register name; otherwise return
2116 FALSE. The function does not intend to produce any diagnostics, but since
2117 the register parser aarch64_reg_parse, which is called by this function,
2118 does produce diagnostics, we call clear_error to clear any diagnostics
2119 that may be generated by aarch64_reg_parse.
2120 Also, the function returns FALSE directly if there is any user error
2121 present at the function entry. This prevents the existing diagnostics
2122 state from being spoiled.
2123 The function currently serves parse_constant_immediate and
2124 parse_big_immediate only. */
2126 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2130 /* Prevent the diagnostics state from being spoiled. */
2134 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2136 /* Clear the parsing error that may be set by the reg parser. */
2139 if (reg
== PARSE_FAIL
)
2142 skip_whitespace (str
);
2143 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2149 /* Parser functions used exclusively in instruction operands. */
2151 /* Parse an immediate expression which may not be constant.
2153 To prevent the expression parser from pushing a register name
2154 into the symbol table as an undefined symbol, firstly a check is
2155 done to find out whether STR is a register of type REG_TYPE followed
2156 by a comma or the end of line. Return FALSE if STR is such a string. */
2159 parse_immediate_expression (char **str
, expressionS
*exp
,
2160 aarch64_reg_type reg_type
)
2162 if (reg_name_p (*str
, reg_type
))
2164 set_recoverable_error (_("immediate operand required"));
2168 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2170 if (exp
->X_op
== O_absent
)
2172 set_fatal_syntax_error (_("missing immediate expression"));
2179 /* Constant immediate-value read function for use in insn parsing.
2180 STR points to the beginning of the immediate (with the optional
2181 leading #); *VAL receives the value. REG_TYPE says which register
2182 names should be treated as registers rather than as symbolic immediates.
2184 Return TRUE on success; otherwise return FALSE. */
2187 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2191 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2194 if (exp
.X_op
!= O_constant
)
2196 set_syntax_error (_("constant expression required"));
2200 *val
= exp
.X_add_number
;
2205 encode_imm_float_bits (uint32_t imm
)
2207 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2208 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2211 /* Return TRUE if the single-precision floating-point value encoded in IMM
2212 can be expressed in the AArch64 8-bit signed floating-point format with
2213 3-bit exponent and normalized 4 bits of precision; in other words, the
2214 floating-point value must be expressable as
2215 (+/-) n / 16 * power (2, r)
2216 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2219 aarch64_imm_float_p (uint32_t imm
)
2221 /* If a single-precision floating-point value has the following bit
2222 pattern, it can be expressed in the AArch64 8-bit floating-point
2225 3 32222222 2221111111111
2226 1 09876543 21098765432109876543210
2227 n Eeeeeexx xxxx0000000000000000000
2229 where n, e and each x are either 0 or 1 independently, with
2234 /* Prepare the pattern for 'Eeeeee'. */
2235 if (((imm
>> 30) & 0x1) == 0)
2236 pattern
= 0x3e000000;
2238 pattern
= 0x40000000;
2240 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2241 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2244 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2245 as an IEEE float without any loss of precision. Store the value in
2249 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2251 /* If a double-precision floating-point value has the following bit
2252 pattern, it can be expressed in a float:
2254 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2255 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2256 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2258 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2259 if Eeee_eeee != 1111_1111
2261 where n, e, s and S are either 0 or 1 independently and where ~ is the
2265 uint32_t high32
= imm
>> 32;
2266 uint32_t low32
= imm
;
2268 /* Lower 29 bits need to be 0s. */
2269 if ((imm
& 0x1fffffff) != 0)
2272 /* Prepare the pattern for 'Eeeeeeeee'. */
2273 if (((high32
>> 30) & 0x1) == 0)
2274 pattern
= 0x38000000;
2276 pattern
= 0x40000000;
2279 if ((high32
& 0x78000000) != pattern
)
2282 /* Check Eeee_eeee != 1111_1111. */
2283 if ((high32
& 0x7ff00000) == 0x47f00000)
2286 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2287 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2288 | (low32
>> 29)); /* 3 S bits. */
2292 /* Return true if we should treat OPERAND as a double-precision
2293 floating-point operand rather than a single-precision one. */
2295 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2297 /* Check for unsuffixed SVE registers, which are allowed
2298 for LDR and STR but not in instructions that require an
2299 immediate. We get better error messages if we arbitrarily
2300 pick one size, parse the immediate normally, and then
2301 report the match failure in the normal way. */
2302 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2303 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2306 /* Parse a floating-point immediate. Return TRUE on success and return the
2307 value in *IMMED in the format of IEEE754 single-precision encoding.
2308 *CCP points to the start of the string; DP_P is TRUE when the immediate
2309 is expected to be in double-precision (N.B. this only matters when
2310 hexadecimal representation is involved). REG_TYPE says which register
2311 names should be treated as registers rather than as symbolic immediates.
2313 This routine accepts any IEEE float; it is up to the callers to reject
2317 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2318 aarch64_reg_type reg_type
)
2322 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2324 unsigned fpword
= 0;
2325 bfd_boolean hex_p
= FALSE
;
2327 skip_past_char (&str
, '#');
2330 skip_whitespace (fpnum
);
2332 if (strncmp (fpnum
, "0x", 2) == 0)
2334 /* Support the hexadecimal representation of the IEEE754 encoding.
2335 Double-precision is expected when DP_P is TRUE, otherwise the
2336 representation should be in single-precision. */
2337 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2342 if (!can_convert_double_to_float (val
, &fpword
))
2345 else if ((uint64_t) val
> 0xffffffff)
2352 else if (reg_name_p (str
, reg_type
))
2354 set_recoverable_error (_("immediate operand required"));
2362 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2365 /* Our FP word must be 32 bits (single-precision FP). */
2366 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2368 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2378 set_fatal_syntax_error (_("invalid floating-point constant"));
2382 /* Less-generic immediate-value read function with the possibility of loading
2383 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2386 To prevent the expression parser from pushing a register name into the
2387 symbol table as an undefined symbol, a check is firstly done to find
2388 out whether STR is a register of type REG_TYPE followed by a comma or
2389 the end of line. Return FALSE if STR is such a register. */
2392 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2396 if (reg_name_p (ptr
, reg_type
))
2398 set_syntax_error (_("immediate operand required"));
2402 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2404 if (inst
.reloc
.exp
.X_op
== O_constant
)
2405 *imm
= inst
.reloc
.exp
.X_add_number
;
2412 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2413 if NEED_LIBOPCODES is non-zero, the fixup will need
2414 assistance from the libopcodes. */
2417 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2418 const aarch64_opnd_info
*operand
,
2419 int need_libopcodes_p
)
2421 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2422 reloc
->opnd
= operand
->type
;
2423 if (need_libopcodes_p
)
2424 reloc
->need_libopcodes_p
= 1;
2427 /* Return TRUE if the instruction needs to be fixed up later internally by
2428 the GAS; otherwise return FALSE. */
2430 static inline bfd_boolean
2431 aarch64_gas_internal_fixup_p (void)
2433 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2436 /* Assign the immediate value to the relevant field in *OPERAND if
2437 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2438 needs an internal fixup in a later stage.
2439 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2440 IMM.VALUE that may get assigned with the constant. */
2442 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2443 aarch64_opnd_info
*operand
,
2445 int need_libopcodes_p
,
2448 if (reloc
->exp
.X_op
== O_constant
)
2451 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2453 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2454 reloc
->type
= BFD_RELOC_UNUSED
;
2458 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2459 /* Tell libopcodes to ignore this operand or not. This is helpful
2460 when one of the operands needs to be fixed up later but we need
2461 libopcodes to check the other operands. */
2462 operand
->skip
= skip_p
;
2466 /* Relocation modifiers. Each entry in the table contains the textual
2467 name for the relocation which may be placed before a symbol used as
2468 a load/store offset, or add immediate. It must be surrounded by a
2469 leading and trailing colon, for example:
2471 ldr x0, [x1, #:rello:varsym]
2472 add x0, x1, #:rello:varsym */
2474 struct reloc_table_entry
2478 bfd_reloc_code_real_type adr_type
;
2479 bfd_reloc_code_real_type adrp_type
;
2480 bfd_reloc_code_real_type movw_type
;
2481 bfd_reloc_code_real_type add_type
;
2482 bfd_reloc_code_real_type ldst_type
;
2483 bfd_reloc_code_real_type ld_literal_type
;
2486 static struct reloc_table_entry reloc_table
[] = {
2487 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2492 BFD_RELOC_AARCH64_ADD_LO12
,
2493 BFD_RELOC_AARCH64_LDST_LO12
,
2496 /* Higher 21 bits of pc-relative page offset: ADRP */
2499 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2505 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2508 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2514 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2518 BFD_RELOC_AARCH64_MOVW_G0
,
2523 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2527 BFD_RELOC_AARCH64_MOVW_G0_S
,
2532 /* Less significant bits 0-15 of address/value: MOVK, no check */
2536 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2541 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2545 BFD_RELOC_AARCH64_MOVW_G1
,
2550 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2554 BFD_RELOC_AARCH64_MOVW_G1_S
,
2559 /* Less significant bits 16-31 of address/value: MOVK, no check */
2563 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2568 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2572 BFD_RELOC_AARCH64_MOVW_G2
,
2577 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2581 BFD_RELOC_AARCH64_MOVW_G2_S
,
2586 /* Less significant bits 32-47 of address/value: MOVK, no check */
2590 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2595 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2599 BFD_RELOC_AARCH64_MOVW_G3
,
2604 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2608 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2613 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2617 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2622 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2626 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2631 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2635 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2640 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2644 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2649 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2653 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2658 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2662 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2667 /* Get to the page containing GOT entry for a symbol. */
2670 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2674 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2676 /* 12 bit offset into the page containing GOT entry for that symbol. */
2682 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2685 /* 0-15 bits of address/value: MOVk, no check. */
2689 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2694 /* Most significant bits 16-31 of address/value: MOVZ. */
2698 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2703 /* 15 bit offset into the page containing GOT entry for that symbol. */
2709 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2712 /* Get to the page containing GOT TLS entry for a symbol */
2713 {"gottprel_g0_nc", 0,
2716 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2721 /* Get to the page containing GOT TLS entry for a symbol */
2725 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2730 /* Get to the page containing GOT TLS entry for a symbol */
2732 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2733 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2739 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2744 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2748 /* Lower 16 bits address/value: MOVk. */
2752 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2757 /* Most significant bits 16-31 of address/value: MOVZ. */
2761 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2766 /* Get to the page containing GOT TLS entry for a symbol */
2768 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2769 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2773 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2775 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2780 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2781 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2784 /* Get to the page containing GOT TLS entry for a symbol.
2785 The same as GD, we allocate two consecutive GOT slots
2786 for module index and module offset, the only difference
2787 with GD is the module offset should be initialized to
2788 zero without any outstanding runtime relocation. */
2790 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2791 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2797 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2798 {"tlsldm_lo12_nc", 0,
2802 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2806 /* 12 bit offset into the module TLS base address. */
2811 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2812 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2815 /* Same as dtprel_lo12, no overflow check. */
2816 {"dtprel_lo12_nc", 0,
2820 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2821 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2824 /* bits[23:12] of offset to the module TLS base address. */
2829 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2833 /* bits[15:0] of offset to the module TLS base address. */
2837 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2842 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2846 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2851 /* bits[31:16] of offset to the module TLS base address. */
2855 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2860 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2864 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2869 /* bits[47:32] of offset to the module TLS base address. */
2873 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2878 /* Lower 16 bit offset into GOT entry for a symbol */
2879 {"tlsdesc_off_g0_nc", 0,
2882 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2887 /* Higher 16 bit offset into GOT entry for a symbol */
2888 {"tlsdesc_off_g1", 0,
2891 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2896 /* Get to the page containing GOT TLS entry for a symbol */
2899 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2903 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2905 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2906 {"gottprel_lo12", 0,
2911 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2914 /* Get tp offset for a symbol. */
2919 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2923 /* Get tp offset for a symbol. */
2928 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2929 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2932 /* Get tp offset for a symbol. */
2937 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2941 /* Get tp offset for a symbol. */
2942 {"tprel_lo12_nc", 0,
2946 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2947 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2950 /* Most significant bits 32-47 of address/value: MOVZ. */
2954 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2959 /* Most significant bits 16-31 of address/value: MOVZ. */
2963 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2968 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2972 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2977 /* Most significant bits 0-15 of address/value: MOVZ. */
2981 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2986 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2990 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2995 /* 15bit offset from got entry to base address of GOT table. */
3001 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3004 /* 14bit offset from got entry to base address of GOT table. */
3010 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3014 /* Given the address of a pointer pointing to the textual name of a
3015 relocation as may appear in assembler source, attempt to find its
3016 details in reloc_table. The pointer will be updated to the character
3017 after the trailing colon. On failure, NULL will be returned;
3018 otherwise return the reloc_table_entry. */
3020 static struct reloc_table_entry
*
3021 find_reloc_table_entry (char **str
)
3024 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3026 int length
= strlen (reloc_table
[i
].name
);
3028 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3029 && (*str
)[length
] == ':')
3031 *str
+= (length
+ 1);
3032 return &reloc_table
[i
];
3039 /* Mode argument to parse_shift and parser_shifter_operand. */
3040 enum parse_shift_mode
3042 SHIFTED_NONE
, /* no shifter allowed */
3043 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3045 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3047 SHIFTED_LSL
, /* bare "lsl #n" */
3048 SHIFTED_MUL
, /* bare "mul #n" */
3049 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3050 SHIFTED_MUL_VL
, /* "mul vl" */
3051 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3054 /* Parse a <shift> operator on an AArch64 data processing instruction.
3055 Return TRUE on success; otherwise return FALSE. */
3057 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3059 const struct aarch64_name_value_pair
*shift_op
;
3060 enum aarch64_modifier_kind kind
;
3066 for (p
= *str
; ISALPHA (*p
); p
++)
3071 set_syntax_error (_("shift expression expected"));
3075 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3077 if (shift_op
== NULL
)
3079 set_syntax_error (_("shift operator expected"));
3083 kind
= aarch64_get_operand_modifier (shift_op
);
3085 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3087 set_syntax_error (_("invalid use of 'MSL'"));
3091 if (kind
== AARCH64_MOD_MUL
3092 && mode
!= SHIFTED_MUL
3093 && mode
!= SHIFTED_MUL_VL
)
3095 set_syntax_error (_("invalid use of 'MUL'"));
3101 case SHIFTED_LOGIC_IMM
:
3102 if (aarch64_extend_operator_p (kind
))
3104 set_syntax_error (_("extending shift is not permitted"));
3109 case SHIFTED_ARITH_IMM
:
3110 if (kind
== AARCH64_MOD_ROR
)
3112 set_syntax_error (_("'ROR' shift is not permitted"));
3118 if (kind
!= AARCH64_MOD_LSL
)
3120 set_syntax_error (_("only 'LSL' shift is permitted"));
3126 if (kind
!= AARCH64_MOD_MUL
)
3128 set_syntax_error (_("only 'MUL' is permitted"));
3133 case SHIFTED_MUL_VL
:
3134 /* "MUL VL" consists of two separate tokens. Require the first
3135 token to be "MUL" and look for a following "VL". */
3136 if (kind
== AARCH64_MOD_MUL
)
3138 skip_whitespace (p
);
3139 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3142 kind
= AARCH64_MOD_MUL_VL
;
3146 set_syntax_error (_("only 'MUL VL' is permitted"));
3149 case SHIFTED_REG_OFFSET
:
3150 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3151 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3153 set_fatal_syntax_error
3154 (_("invalid shift for the register offset addressing mode"));
3159 case SHIFTED_LSL_MSL
:
3160 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3162 set_syntax_error (_("invalid shift operator"));
3171 /* Whitespace can appear here if the next thing is a bare digit. */
3172 skip_whitespace (p
);
3174 /* Parse shift amount. */
3176 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3177 exp
.X_op
= O_absent
;
3180 if (is_immediate_prefix (*p
))
3185 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3187 if (kind
== AARCH64_MOD_MUL_VL
)
3188 /* For consistency, give MUL VL the same shift amount as an implicit
3190 operand
->shifter
.amount
= 1;
3191 else if (exp
.X_op
== O_absent
)
3193 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3195 set_syntax_error (_("missing shift amount"));
3198 operand
->shifter
.amount
= 0;
3200 else if (exp
.X_op
!= O_constant
)
3202 set_syntax_error (_("constant shift amount required"));
3205 /* For parsing purposes, MUL #n has no inherent range. The range
3206 depends on the operand and will be checked by operand-specific
3208 else if (kind
!= AARCH64_MOD_MUL
3209 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3211 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3216 operand
->shifter
.amount
= exp
.X_add_number
;
3217 operand
->shifter
.amount_present
= 1;
3220 operand
->shifter
.operator_present
= 1;
3221 operand
->shifter
.kind
= kind
;
3227 /* Parse a <shifter_operand> for a data processing instruction:
3230 #<immediate>, LSL #imm
3232 Validation of immediate operands is deferred to md_apply_fix.
3234 Return TRUE on success; otherwise return FALSE. */
3237 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3238 enum parse_shift_mode mode
)
3242 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3247 /* Accept an immediate expression. */
3248 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3251 /* Accept optional LSL for arithmetic immediate values. */
3252 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3253 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3256 /* Not accept any shifter for logical immediate values. */
3257 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3258 && parse_shift (&p
, operand
, mode
))
3260 set_syntax_error (_("unexpected shift operator"));
3268 /* Parse a <shifter_operand> for a data processing instruction:
3273 #<immediate>, LSL #imm
3275 where <shift> is handled by parse_shift above, and the last two
3276 cases are handled by the function above.
3278 Validation of immediate operands is deferred to md_apply_fix.
3280 Return TRUE on success; otherwise return FALSE. */
3283 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3284 enum parse_shift_mode mode
)
3286 const reg_entry
*reg
;
3287 aarch64_opnd_qualifier_t qualifier
;
3288 enum aarch64_operand_class opd_class
3289 = aarch64_get_operand_class (operand
->type
);
3291 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3294 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3296 set_syntax_error (_("unexpected register in the immediate operand"));
3300 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3302 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3306 operand
->reg
.regno
= reg
->number
;
3307 operand
->qualifier
= qualifier
;
3309 /* Accept optional shift operation on register. */
3310 if (! skip_past_comma (str
))
3313 if (! parse_shift (str
, operand
, mode
))
3318 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3321 (_("integer register expected in the extended/shifted operand "
3326 /* We have a shifted immediate variable. */
3327 return parse_shifter_operand_imm (str
, operand
, mode
);
3330 /* Return TRUE on success; return FALSE otherwise. */
3333 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3334 enum parse_shift_mode mode
)
3338 /* Determine if we have the sequence of characters #: or just :
3339 coming next. If we do, then we check for a :rello: relocation
3340 modifier. If we don't, punt the whole lot to
3341 parse_shifter_operand. */
3343 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3345 struct reloc_table_entry
*entry
;
3353 /* Try to parse a relocation. Anything else is an error. */
3354 if (!(entry
= find_reloc_table_entry (str
)))
3356 set_syntax_error (_("unknown relocation modifier"));
3360 if (entry
->add_type
== 0)
3363 (_("this relocation modifier is not allowed on this instruction"));
3367 /* Save str before we decompose it. */
3370 /* Next, we parse the expression. */
3371 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3374 /* Record the relocation type (use the ADD variant here). */
3375 inst
.reloc
.type
= entry
->add_type
;
3376 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3378 /* If str is empty, we've reached the end, stop here. */
3382 /* Otherwise, we have a shifted reloc modifier, so rewind to
3383 recover the variable name and continue parsing for the shifter. */
3385 return parse_shifter_operand_imm (str
, operand
, mode
);
3388 return parse_shifter_operand (str
, operand
, mode
);
3391 /* Parse all forms of an address expression. Information is written
3392 to *OPERAND and/or inst.reloc.
3394 The A64 instruction set has the following addressing modes:
3397 [base] // in SIMD ld/st structure
3398 [base{,#0}] // in ld/st exclusive
3400 [base,Xm{,LSL #imm}]
3401 [base,Xm,SXTX {#imm}]
3402 [base,Wm,(S|U)XTW {#imm}]
3407 [base],Xm // in SIMD ld/st structure
3408 PC-relative (literal)
3412 [base,Zm.D{,LSL #imm}]
3413 [base,Zm.S,(S|U)XTW {#imm}]
3414 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3418 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3419 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3420 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3422 (As a convenience, the notation "=immediate" is permitted in conjunction
3423 with the pc-relative literal load instructions to automatically place an
3424 immediate value or symbolic address in a nearby literal pool and generate
3425 a hidden label which references it.)
3427 Upon a successful parsing, the address structure in *OPERAND will be
3428 filled in the following way:
3430 .base_regno = <base>
3431 .offset.is_reg // 1 if the offset is a register
3433 .offset.regno = <Rm>
3435 For different addressing modes defined in the A64 ISA:
3438 .pcrel=0; .preind=1; .postind=0; .writeback=0
3440 .pcrel=0; .preind=1; .postind=0; .writeback=1
3442 .pcrel=0; .preind=0; .postind=1; .writeback=1
3443 PC-relative (literal)
3444 .pcrel=1; .preind=1; .postind=0; .writeback=0
3446 The shift/extension information, if any, will be stored in .shifter.
3447 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3448 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3449 corresponding register.
3451 BASE_TYPE says which types of base register should be accepted and
3452 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3453 is the type of shifter that is allowed for immediate offsets,
3454 or SHIFTED_NONE if none.
3456 In all other respects, it is the caller's responsibility to check
3457 for addressing modes not supported by the instruction, and to set
3461 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3462 aarch64_opnd_qualifier_t
*base_qualifier
,
3463 aarch64_opnd_qualifier_t
*offset_qualifier
,
3464 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3465 enum parse_shift_mode imm_shift_mode
)
3468 const reg_entry
*reg
;
3469 expressionS
*exp
= &inst
.reloc
.exp
;
3471 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3472 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3473 if (! skip_past_char (&p
, '['))
3475 /* =immediate or label. */
3476 operand
->addr
.pcrel
= 1;
3477 operand
->addr
.preind
= 1;
3479 /* #:<reloc_op>:<symbol> */
3480 skip_past_char (&p
, '#');
3481 if (skip_past_char (&p
, ':'))
3483 bfd_reloc_code_real_type ty
;
3484 struct reloc_table_entry
*entry
;
3486 /* Try to parse a relocation modifier. Anything else is
3488 entry
= find_reloc_table_entry (&p
);
3491 set_syntax_error (_("unknown relocation modifier"));
3495 switch (operand
->type
)
3497 case AARCH64_OPND_ADDR_PCREL21
:
3499 ty
= entry
->adr_type
;
3503 ty
= entry
->ld_literal_type
;
3510 (_("this relocation modifier is not allowed on this "
3516 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3518 set_syntax_error (_("invalid relocation expression"));
3522 /* #:<reloc_op>:<expr> */
3523 /* Record the relocation type. */
3524 inst
.reloc
.type
= ty
;
3525 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3530 if (skip_past_char (&p
, '='))
3531 /* =immediate; need to generate the literal in the literal pool. */
3532 inst
.gen_lit_pool
= 1;
3534 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3536 set_syntax_error (_("invalid address"));
3547 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3548 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3550 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3553 operand
->addr
.base_regno
= reg
->number
;
3556 if (skip_past_comma (&p
))
3559 operand
->addr
.preind
= 1;
3561 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3564 if (!aarch64_check_reg_type (reg
, offset_type
))
3566 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3571 operand
->addr
.offset
.regno
= reg
->number
;
3572 operand
->addr
.offset
.is_reg
= 1;
3573 /* Shifted index. */
3574 if (skip_past_comma (&p
))
3577 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3578 /* Use the diagnostics set in parse_shift, so not set new
3579 error message here. */
3583 [base,Xm] # For vector plus scalar SVE2 indexing.
3584 [base,Xm{,LSL #imm}]
3585 [base,Xm,SXTX {#imm}]
3586 [base,Wm,(S|U)XTW {#imm}] */
3587 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3588 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3589 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3591 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3593 set_syntax_error (_("invalid use of 32-bit register offset"));
3596 if (aarch64_get_qualifier_esize (*base_qualifier
)
3597 != aarch64_get_qualifier_esize (*offset_qualifier
)
3598 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3599 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3600 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3602 set_syntax_error (_("offset has different size from base"));
3606 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3608 set_syntax_error (_("invalid use of 64-bit register offset"));
3614 /* [Xn,#:<reloc_op>:<symbol> */
3615 skip_past_char (&p
, '#');
3616 if (skip_past_char (&p
, ':'))
3618 struct reloc_table_entry
*entry
;
3620 /* Try to parse a relocation modifier. Anything else is
3622 if (!(entry
= find_reloc_table_entry (&p
)))
3624 set_syntax_error (_("unknown relocation modifier"));
3628 if (entry
->ldst_type
== 0)
3631 (_("this relocation modifier is not allowed on this "
3636 /* [Xn,#:<reloc_op>: */
3637 /* We now have the group relocation table entry corresponding to
3638 the name in the assembler source. Next, we parse the
3640 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3642 set_syntax_error (_("invalid relocation expression"));
3646 /* [Xn,#:<reloc_op>:<expr> */
3647 /* Record the load/store relocation type. */
3648 inst
.reloc
.type
= entry
->ldst_type
;
3649 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3653 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3655 set_syntax_error (_("invalid expression in the address"));
3659 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3660 /* [Xn,<expr>,<shifter> */
3661 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3667 if (! skip_past_char (&p
, ']'))
3669 set_syntax_error (_("']' expected"));
3673 if (skip_past_char (&p
, '!'))
3675 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3677 set_syntax_error (_("register offset not allowed in pre-indexed "
3678 "addressing mode"));
3682 operand
->addr
.writeback
= 1;
3684 else if (skip_past_comma (&p
))
3687 operand
->addr
.postind
= 1;
3688 operand
->addr
.writeback
= 1;
3690 if (operand
->addr
.preind
)
3692 set_syntax_error (_("cannot combine pre- and post-indexing"));
3696 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3700 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3702 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3706 operand
->addr
.offset
.regno
= reg
->number
;
3707 operand
->addr
.offset
.is_reg
= 1;
3709 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3712 set_syntax_error (_("invalid expression in the address"));
3717 /* If at this point neither .preind nor .postind is set, we have a
3718 bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].
3719 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3721 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3723 if (operand
->addr
.writeback
)
3726 set_syntax_error (_("missing offset in the pre-indexed address"));
3730 operand
->addr
.preind
= 1;
3731 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3733 operand
->addr
.offset
.is_reg
= 1;
3734 operand
->addr
.offset
.regno
= REG_ZR
;
3735 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3739 inst
.reloc
.exp
.X_op
= O_constant
;
3740 inst
.reloc
.exp
.X_add_number
= 0;
3748 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3751 parse_address (char **str
, aarch64_opnd_info
*operand
)
3753 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3754 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3755 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3758 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3759 The arguments have the same meaning as for parse_address_main.
3760 Return TRUE on success. */
3762 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3763 aarch64_opnd_qualifier_t
*base_qualifier
,
3764 aarch64_opnd_qualifier_t
*offset_qualifier
)
3766 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3767 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3771 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3772 Return TRUE on success; otherwise return FALSE. */
3774 parse_half (char **str
, int *internal_fixup_p
)
3778 skip_past_char (&p
, '#');
3780 gas_assert (internal_fixup_p
);
3781 *internal_fixup_p
= 0;
3785 struct reloc_table_entry
*entry
;
3787 /* Try to parse a relocation. Anything else is an error. */
3789 if (!(entry
= find_reloc_table_entry (&p
)))
3791 set_syntax_error (_("unknown relocation modifier"));
3795 if (entry
->movw_type
== 0)
3798 (_("this relocation modifier is not allowed on this instruction"));
3802 inst
.reloc
.type
= entry
->movw_type
;
3805 *internal_fixup_p
= 1;
3807 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3814 /* Parse an operand for an ADRP instruction:
3816 Return TRUE on success; otherwise return FALSE. */
3819 parse_adrp (char **str
)
3826 struct reloc_table_entry
*entry
;
3828 /* Try to parse a relocation. Anything else is an error. */
3830 if (!(entry
= find_reloc_table_entry (&p
)))
3832 set_syntax_error (_("unknown relocation modifier"));
3836 if (entry
->adrp_type
== 0)
3839 (_("this relocation modifier is not allowed on this instruction"));
3843 inst
.reloc
.type
= entry
->adrp_type
;
3846 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3848 inst
.reloc
.pc_rel
= 1;
3850 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3857 /* Miscellaneous. */
3859 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3860 of SIZE tokens in which index I gives the token for field value I,
3861 or is null if field value I is invalid. REG_TYPE says which register
3862 names should be treated as registers rather than as symbolic immediates.
3864 Return true on success, moving *STR past the operand and storing the
3865 field value in *VAL. */
3868 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3869 size_t size
, aarch64_reg_type reg_type
)
3875 /* Match C-like tokens. */
3877 while (ISALNUM (*q
))
3880 for (i
= 0; i
< size
; ++i
)
3882 && strncasecmp (array
[i
], p
, q
- p
) == 0
3883 && array
[i
][q
- p
] == 0)
3890 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3893 if (exp
.X_op
== O_constant
3894 && (uint64_t) exp
.X_add_number
< size
)
3896 *val
= exp
.X_add_number
;
3901 /* Use the default error for this operand. */
3905 /* Parse an option for a preload instruction. Returns the encoding for the
3906 option, or PARSE_FAIL. */
3909 parse_pldop (char **str
)
3912 const struct aarch64_name_value_pair
*o
;
3915 while (ISALNUM (*q
))
3918 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3926 /* Parse an option for a barrier instruction. Returns the encoding for the
3927 option, or PARSE_FAIL. */
3930 parse_barrier (char **str
)
3933 const asm_barrier_opt
*o
;
3936 while (ISALPHA (*q
))
3939 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3947 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3948 return 0 if successful. Otherwise return PARSE_FAIL. */
3951 parse_barrier_psb (char **str
,
3952 const struct aarch64_name_value_pair
** hint_opt
)
3955 const struct aarch64_name_value_pair
*o
;
3958 while (ISALPHA (*q
))
3961 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3964 set_fatal_syntax_error
3965 ( _("unknown or missing option to PSB"));
3969 if (o
->value
!= 0x11)
3971 /* PSB only accepts option name 'CSYNC'. */
3973 (_("the specified option is not accepted for PSB"));
3982 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3983 return 0 if successful. Otherwise return PARSE_FAIL. */
3986 parse_bti_operand (char **str
,
3987 const struct aarch64_name_value_pair
** hint_opt
)
3990 const struct aarch64_name_value_pair
*o
;
3993 while (ISALPHA (*q
))
3996 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3999 set_fatal_syntax_error
4000 ( _("unknown option to BTI"));
4006 /* Valid BTI operands. */
4014 (_("unknown option to BTI"));
4023 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4024 Returns the encoding for the option, or PARSE_FAIL.
4026 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4027 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4029 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4030 field, otherwise as a system register.
4034 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
4035 int imple_defined_p
, int pstatefield_p
,
4040 const aarch64_sys_reg
*o
;
4044 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4046 *p
++ = TOLOWER (*q
);
4048 /* Assert that BUF be large enough. */
4049 gas_assert (p
- buf
== q
- *str
);
4051 o
= hash_find (sys_regs
, buf
);
4054 if (!imple_defined_p
)
4058 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4059 unsigned int op0
, op1
, cn
, cm
, op2
;
4061 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4064 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4066 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4073 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4074 as_bad (_("selected processor does not support PSTATE field "
4076 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4077 as_bad (_("selected processor does not support system register "
4079 if (aarch64_sys_reg_deprecated_p (o
))
4080 as_warn (_("system register name '%s' is deprecated and may be "
4081 "removed in a future release"), buf
);
4091 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4092 for the option, or NULL. */
4094 static const aarch64_sys_ins_reg
*
4095 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4099 const aarch64_sys_ins_reg
*o
;
4102 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4104 *p
++ = TOLOWER (*q
);
4107 o
= hash_find (sys_ins_regs
, buf
);
4111 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4112 as_bad (_("selected processor does not support system register "
4119 #define po_char_or_fail(chr) do { \
4120 if (! skip_past_char (&str, chr)) \
4124 #define po_reg_or_fail(regtype) do { \
4125 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4126 if (val == PARSE_FAIL) \
4128 set_default_error (); \
4133 #define po_int_reg_or_fail(reg_type) do { \
4134 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4135 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4137 set_default_error (); \
4140 info->reg.regno = reg->number; \
4141 info->qualifier = qualifier; \
4144 #define po_imm_nc_or_fail() do { \
4145 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4149 #define po_imm_or_fail(min, max) do { \
4150 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4152 if (val < min || val > max) \
4154 set_fatal_syntax_error (_("immediate value out of range "\
4155 #min " to "#max)); \
4160 #define po_enum_or_fail(array) do { \
4161 if (!parse_enum_string (&str, &val, array, \
4162 ARRAY_SIZE (array), imm_reg_type)) \
4166 #define po_misc_or_fail(expr) do { \
4171 /* encode the 12-bit imm field of Add/sub immediate */
4172 static inline uint32_t
4173 encode_addsub_imm (uint32_t imm
)
4178 /* encode the shift amount field of Add/sub immediate */
4179 static inline uint32_t
4180 encode_addsub_imm_shift_amount (uint32_t cnt
)
4186 /* encode the imm field of Adr instruction */
4187 static inline uint32_t
4188 encode_adr_imm (uint32_t imm
)
4190 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4191 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4194 /* encode the immediate field of Move wide immediate */
4195 static inline uint32_t
4196 encode_movw_imm (uint32_t imm
)
4201 /* encode the 26-bit offset of unconditional branch */
4202 static inline uint32_t
4203 encode_branch_ofs_26 (uint32_t ofs
)
4205 return ofs
& ((1 << 26) - 1);
4208 /* encode the 19-bit offset of conditional branch and compare & branch */
4209 static inline uint32_t
4210 encode_cond_branch_ofs_19 (uint32_t ofs
)
4212 return (ofs
& ((1 << 19) - 1)) << 5;
4215 /* encode the 19-bit offset of ld literal */
4216 static inline uint32_t
4217 encode_ld_lit_ofs_19 (uint32_t ofs
)
4219 return (ofs
& ((1 << 19) - 1)) << 5;
4222 /* Encode the 14-bit offset of test & branch. */
4223 static inline uint32_t
4224 encode_tst_branch_ofs_14 (uint32_t ofs
)
4226 return (ofs
& ((1 << 14) - 1)) << 5;
4229 /* Encode the 16-bit imm field of svc/hvc/smc. */
4230 static inline uint32_t
4231 encode_svc_imm (uint32_t imm
)
4236 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4237 static inline uint32_t
4238 reencode_addsub_switch_add_sub (uint32_t opcode
)
4240 return opcode
^ (1 << 30);
4243 static inline uint32_t
4244 reencode_movzn_to_movz (uint32_t opcode
)
4246 return opcode
| (1 << 30);
4249 static inline uint32_t
4250 reencode_movzn_to_movn (uint32_t opcode
)
4252 return opcode
& ~(1 << 30);
4255 /* Overall per-instruction processing. */
4257 /* We need to be able to fix up arbitrary expressions in some statements.
4258 This is so that we can handle symbols that are an arbitrary distance from
4259 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4260 which returns part of an address in a form which will be valid for
4261 a data instruction. We do this by pushing the expression into a symbol
4262 in the expr_section, and creating a fix for that. */
4265 fix_new_aarch64 (fragS
* frag
,
4267 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4277 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4281 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4288 /* Diagnostics on operands errors. */
4290 /* By default, output verbose error message.
4291 Disable the verbose error message by -mno-verbose-error. */
4292 static int verbose_error_p
= 1;
4294 #ifdef DEBUG_AARCH64
4295 /* N.B. this is only for the purpose of debugging. */
4296 const char* operand_mismatch_kind_names
[] =
4299 "AARCH64_OPDE_RECOVERABLE",
4300 "AARCH64_OPDE_SYNTAX_ERROR",
4301 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4302 "AARCH64_OPDE_INVALID_VARIANT",
4303 "AARCH64_OPDE_OUT_OF_RANGE",
4304 "AARCH64_OPDE_UNALIGNED",
4305 "AARCH64_OPDE_REG_LIST",
4306 "AARCH64_OPDE_OTHER_ERROR",
4308 #endif /* DEBUG_AARCH64 */
4310 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4312 When multiple errors of different kinds are found in the same assembly
4313 line, only the error of the highest severity will be picked up for
4314 issuing the diagnostics. */
4316 static inline bfd_boolean
4317 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4318 enum aarch64_operand_error_kind rhs
)
4320 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4321 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4322 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4323 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4324 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4325 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4326 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4327 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4331 /* Helper routine to get the mnemonic name from the assembly instruction
4332 line; should only be called for the diagnosis purpose, as there is
4333 string copy operation involved, which may affect the runtime
4334 performance if used in elsewhere. */
4337 get_mnemonic_name (const char *str
)
4339 static char mnemonic
[32];
4342 /* Get the first 15 bytes and assume that the full name is included. */
4343 strncpy (mnemonic
, str
, 31);
4344 mnemonic
[31] = '\0';
4346 /* Scan up to the end of the mnemonic, which must end in white space,
4347 '.', or end of string. */
4348 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4353 /* Append '...' to the truncated long name. */
4354 if (ptr
- mnemonic
== 31)
4355 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4361 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4363 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4364 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4367 /* Data structures storing one user error in the assembly code related to
4370 struct operand_error_record
4372 const aarch64_opcode
*opcode
;
4373 aarch64_operand_error detail
;
4374 struct operand_error_record
*next
;
4377 typedef struct operand_error_record operand_error_record
;
4379 struct operand_errors
4381 operand_error_record
*head
;
4382 operand_error_record
*tail
;
4385 typedef struct operand_errors operand_errors
;
4387 /* Top-level data structure reporting user errors for the current line of
4389 The way md_assemble works is that all opcodes sharing the same mnemonic
4390 name are iterated to find a match to the assembly line. In this data
4391 structure, each of the such opcodes will have one operand_error_record
4392 allocated and inserted. In other words, excessive errors related with
4393 a single opcode are disregarded. */
4394 operand_errors operand_error_report
;
4396 /* Free record nodes. */
4397 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4399 /* Initialize the data structure that stores the operand mismatch
4400 information on assembling one line of the assembly code. */
4402 init_operand_error_report (void)
4404 if (operand_error_report
.head
!= NULL
)
4406 gas_assert (operand_error_report
.tail
!= NULL
);
4407 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4408 free_opnd_error_record_nodes
= operand_error_report
.head
;
4409 operand_error_report
.head
= NULL
;
4410 operand_error_report
.tail
= NULL
;
4413 gas_assert (operand_error_report
.tail
== NULL
);
4416 /* Return TRUE if some operand error has been recorded during the
4417 parsing of the current assembly line using the opcode *OPCODE;
4418 otherwise return FALSE. */
4419 static inline bfd_boolean
4420 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4422 operand_error_record
*record
= operand_error_report
.head
;
4423 return record
&& record
->opcode
== opcode
;
4426 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4427 OPCODE field is initialized with OPCODE.
4428 N.B. only one record for each opcode, i.e. the maximum of one error is
4429 recorded for each instruction template. */
4432 add_operand_error_record (const operand_error_record
* new_record
)
4434 const aarch64_opcode
*opcode
= new_record
->opcode
;
4435 operand_error_record
* record
= operand_error_report
.head
;
4437 /* The record may have been created for this opcode. If not, we need
4439 if (! opcode_has_operand_error_p (opcode
))
4441 /* Get one empty record. */
4442 if (free_opnd_error_record_nodes
== NULL
)
4444 record
= XNEW (operand_error_record
);
4448 record
= free_opnd_error_record_nodes
;
4449 free_opnd_error_record_nodes
= record
->next
;
4451 record
->opcode
= opcode
;
4452 /* Insert at the head. */
4453 record
->next
= operand_error_report
.head
;
4454 operand_error_report
.head
= record
;
4455 if (operand_error_report
.tail
== NULL
)
4456 operand_error_report
.tail
= record
;
4458 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4459 && record
->detail
.index
<= new_record
->detail
.index
4460 && operand_error_higher_severity_p (record
->detail
.kind
,
4461 new_record
->detail
.kind
))
4463 /* In the case of multiple errors found on operands related with a
4464 single opcode, only record the error of the leftmost operand and
4465 only if the error is of higher severity. */
4466 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4467 " the existing error %s on operand %d",
4468 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4469 new_record
->detail
.index
,
4470 operand_mismatch_kind_names
[record
->detail
.kind
],
4471 record
->detail
.index
);
4475 record
->detail
= new_record
->detail
;
4479 record_operand_error_info (const aarch64_opcode
*opcode
,
4480 aarch64_operand_error
*error_info
)
4482 operand_error_record record
;
4483 record
.opcode
= opcode
;
4484 record
.detail
= *error_info
;
4485 add_operand_error_record (&record
);
4488 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4489 error message *ERROR, for operand IDX (count from 0). */
4492 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4493 enum aarch64_operand_error_kind kind
,
4496 aarch64_operand_error info
;
4497 memset(&info
, 0, sizeof (info
));
4501 info
.non_fatal
= FALSE
;
4502 record_operand_error_info (opcode
, &info
);
4506 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4507 enum aarch64_operand_error_kind kind
,
4508 const char* error
, const int *extra_data
)
4510 aarch64_operand_error info
;
4514 info
.data
[0] = extra_data
[0];
4515 info
.data
[1] = extra_data
[1];
4516 info
.data
[2] = extra_data
[2];
4517 info
.non_fatal
= FALSE
;
4518 record_operand_error_info (opcode
, &info
);
4522 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4523 const char* error
, int lower_bound
,
4526 int data
[3] = {lower_bound
, upper_bound
, 0};
4527 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4531 /* Remove the operand error record for *OPCODE. */
4532 static void ATTRIBUTE_UNUSED
4533 remove_operand_error_record (const aarch64_opcode
*opcode
)
4535 if (opcode_has_operand_error_p (opcode
))
4537 operand_error_record
* record
= operand_error_report
.head
;
4538 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4539 operand_error_report
.head
= record
->next
;
4540 record
->next
= free_opnd_error_record_nodes
;
4541 free_opnd_error_record_nodes
= record
;
4542 if (operand_error_report
.head
== NULL
)
4544 gas_assert (operand_error_report
.tail
== record
);
4545 operand_error_report
.tail
= NULL
;
4550 /* Given the instruction in *INSTR, return the index of the best matched
4551 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4553 Return -1 if there is no qualifier sequence; return the first match
4554 if there is multiple matches found. */
4557 find_best_match (const aarch64_inst
*instr
,
4558 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4560 int i
, num_opnds
, max_num_matched
, idx
;
4562 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4565 DEBUG_TRACE ("no operand");
4569 max_num_matched
= 0;
4572 /* For each pattern. */
4573 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4576 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4578 /* Most opcodes has much fewer patterns in the list. */
4579 if (empty_qualifier_sequence_p (qualifiers
))
4581 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4585 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4586 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4589 if (num_matched
> max_num_matched
)
4591 max_num_matched
= num_matched
;
4596 DEBUG_TRACE ("return with %d", idx
);
4600 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4601 corresponding operands in *INSTR. */
4604 assign_qualifier_sequence (aarch64_inst
*instr
,
4605 const aarch64_opnd_qualifier_t
*qualifiers
)
4608 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4609 gas_assert (num_opnds
);
4610 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4611 instr
->operands
[i
].qualifier
= *qualifiers
;
4614 /* Print operands for the diagnosis purpose. */
4617 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4618 const aarch64_opnd_info
*opnds
)
4622 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4626 /* We regard the opcode operand info more, however we also look into
4627 the inst->operands to support the disassembling of the optional
4629 The two operand code should be the same in all cases, apart from
4630 when the operand can be optional. */
4631 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4632 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4635 /* Generate the operand string in STR. */
4636 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4641 strcat (buf
, i
== 0 ? " " : ", ");
4643 /* Append the operand string. */
4648 /* Send to stderr a string as information. */
4651 output_info (const char *format
, ...)
4657 file
= as_where (&line
);
4661 fprintf (stderr
, "%s:%u: ", file
, line
);
4663 fprintf (stderr
, "%s: ", file
);
4665 fprintf (stderr
, _("Info: "));
4666 va_start (args
, format
);
4667 vfprintf (stderr
, format
, args
);
4669 (void) putc ('\n', stderr
);
4672 /* Output one operand error record. */
4675 output_operand_error_record (const operand_error_record
*record
, char *str
)
4677 const aarch64_operand_error
*detail
= &record
->detail
;
4678 int idx
= detail
->index
;
4679 const aarch64_opcode
*opcode
= record
->opcode
;
4680 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4681 : AARCH64_OPND_NIL
);
4683 typedef void (*handler_t
)(const char *format
, ...);
4684 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4686 switch (detail
->kind
)
4688 case AARCH64_OPDE_NIL
:
4691 case AARCH64_OPDE_SYNTAX_ERROR
:
4692 case AARCH64_OPDE_RECOVERABLE
:
4693 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4694 case AARCH64_OPDE_OTHER_ERROR
:
4695 /* Use the prepared error message if there is, otherwise use the
4696 operand description string to describe the error. */
4697 if (detail
->error
!= NULL
)
4700 handler (_("%s -- `%s'"), detail
->error
, str
);
4702 handler (_("%s at operand %d -- `%s'"),
4703 detail
->error
, idx
+ 1, str
);
4707 gas_assert (idx
>= 0);
4708 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4709 aarch64_get_operand_desc (opd_code
), str
);
4713 case AARCH64_OPDE_INVALID_VARIANT
:
4714 handler (_("operand mismatch -- `%s'"), str
);
4715 if (verbose_error_p
)
4717 /* We will try to correct the erroneous instruction and also provide
4718 more information e.g. all other valid variants.
4720 The string representation of the corrected instruction and other
4721 valid variants are generated by
4723 1) obtaining the intermediate representation of the erroneous
4725 2) manipulating the IR, e.g. replacing the operand qualifier;
4726 3) printing out the instruction by calling the printer functions
4727 shared with the disassembler.
4729 The limitation of this method is that the exact input assembly
4730 line cannot be accurately reproduced in some cases, for example an
4731 optional operand present in the actual assembly line will be
4732 omitted in the output; likewise for the optional syntax rules,
4733 e.g. the # before the immediate. Another limitation is that the
4734 assembly symbols and relocation operations in the assembly line
4735 currently cannot be printed out in the error report. Last but not
4736 least, when there is other error(s) co-exist with this error, the
4737 'corrected' instruction may be still incorrect, e.g. given
4738 'ldnp h0,h1,[x0,#6]!'
4739 this diagnosis will provide the version:
4740 'ldnp s0,s1,[x0,#6]!'
4741 which is still not right. */
4742 size_t len
= strlen (get_mnemonic_name (str
));
4746 aarch64_inst
*inst_base
= &inst
.base
;
4747 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4750 reset_aarch64_instruction (&inst
);
4751 inst_base
->opcode
= opcode
;
4753 /* Reset the error report so that there is no side effect on the
4754 following operand parsing. */
4755 init_operand_error_report ();
4758 result
= parse_operands (str
+ len
, opcode
)
4759 && programmer_friendly_fixup (&inst
);
4760 gas_assert (result
);
4761 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4762 NULL
, NULL
, insn_sequence
);
4763 gas_assert (!result
);
4765 /* Find the most matched qualifier sequence. */
4766 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4767 gas_assert (qlf_idx
> -1);
4769 /* Assign the qualifiers. */
4770 assign_qualifier_sequence (inst_base
,
4771 opcode
->qualifiers_list
[qlf_idx
]);
4773 /* Print the hint. */
4774 output_info (_(" did you mean this?"));
4775 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4776 print_operands (buf
, opcode
, inst_base
->operands
);
4777 output_info (_(" %s"), buf
);
4779 /* Print out other variant(s) if there is any. */
4781 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4782 output_info (_(" other valid variant(s):"));
4784 /* For each pattern. */
4785 qualifiers_list
= opcode
->qualifiers_list
;
4786 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4788 /* Most opcodes has much fewer patterns in the list.
4789 First NIL qualifier indicates the end in the list. */
4790 if (empty_qualifier_sequence_p (*qualifiers_list
))
4795 /* Mnemonics name. */
4796 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4798 /* Assign the qualifiers. */
4799 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4801 /* Print instruction. */
4802 print_operands (buf
, opcode
, inst_base
->operands
);
4804 output_info (_(" %s"), buf
);
4810 case AARCH64_OPDE_UNTIED_OPERAND
:
4811 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4812 detail
->index
+ 1, str
);
4815 case AARCH64_OPDE_OUT_OF_RANGE
:
4816 if (detail
->data
[0] != detail
->data
[1])
4817 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4818 detail
->error
? detail
->error
: _("immediate value"),
4819 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4821 handler (_("%s must be %d at operand %d -- `%s'"),
4822 detail
->error
? detail
->error
: _("immediate value"),
4823 detail
->data
[0], idx
+ 1, str
);
4826 case AARCH64_OPDE_REG_LIST
:
4827 if (detail
->data
[0] == 1)
4828 handler (_("invalid number of registers in the list; "
4829 "only 1 register is expected at operand %d -- `%s'"),
4832 handler (_("invalid number of registers in the list; "
4833 "%d registers are expected at operand %d -- `%s'"),
4834 detail
->data
[0], idx
+ 1, str
);
4837 case AARCH64_OPDE_UNALIGNED
:
4838 handler (_("immediate value must be a multiple of "
4839 "%d at operand %d -- `%s'"),
4840 detail
->data
[0], idx
+ 1, str
);
4849 /* Process and output the error message about the operand mismatching.
4851 When this function is called, the operand error information had
4852 been collected for an assembly line and there will be multiple
4853 errors in the case of multiple instruction templates; output the
4854 error message that most closely describes the problem.
4856 The errors to be printed can be filtered on printing all errors
4857 or only non-fatal errors. This distinction has to be made because
4858 the error buffer may already be filled with fatal errors we don't want to
4859 print due to the different instruction templates. */
4862 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4864 int largest_error_pos
;
4865 const char *msg
= NULL
;
4866 enum aarch64_operand_error_kind kind
;
4867 operand_error_record
*curr
;
4868 operand_error_record
*head
= operand_error_report
.head
;
4869 operand_error_record
*record
= NULL
;
4871 /* No error to report. */
4875 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4877 /* Only one error. */
4878 if (head
== operand_error_report
.tail
)
4880 /* If the only error is a non-fatal one and we don't want to print it,
4882 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4884 DEBUG_TRACE ("single opcode entry with error kind: %s",
4885 operand_mismatch_kind_names
[head
->detail
.kind
]);
4886 output_operand_error_record (head
, str
);
4891 /* Find the error kind of the highest severity. */
4892 DEBUG_TRACE ("multiple opcode entries with error kind");
4893 kind
= AARCH64_OPDE_NIL
;
4894 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4896 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4897 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4898 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4899 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4900 kind
= curr
->detail
.kind
;
4903 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4905 /* Pick up one of errors of KIND to report. */
4906 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4907 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4909 /* If we don't want to print non-fatal errors then don't consider them
4911 if (curr
->detail
.kind
!= kind
4912 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4914 /* If there are multiple errors, pick up the one with the highest
4915 mismatching operand index. In the case of multiple errors with
4916 the equally highest operand index, pick up the first one or the
4917 first one with non-NULL error message. */
4918 if (curr
->detail
.index
> largest_error_pos
4919 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4920 && curr
->detail
.error
!= NULL
))
4922 largest_error_pos
= curr
->detail
.index
;
4924 msg
= record
->detail
.error
;
4928 /* The way errors are collected in the back-end is a bit non-intuitive. But
4929 essentially, because each operand template is tried recursively you may
4930 always have errors collected from the previous tried OPND. These are
4931 usually skipped if there is one successful match. However now with the
4932 non-fatal errors we have to ignore those previously collected hard errors
4933 when we're only interested in printing the non-fatal ones. This condition
4934 prevents us from printing errors that are not appropriate, since we did
4935 match a condition, but it also has warnings that it wants to print. */
4936 if (non_fatal_only
&& !record
)
4939 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4940 DEBUG_TRACE ("Pick up error kind %s to report",
4941 operand_mismatch_kind_names
[record
->detail
.kind
]);
4944 output_operand_error_record (record
, str
);
4947 /* Write an AARCH64 instruction to buf - always little-endian. */
4949 put_aarch64_insn (char *buf
, uint32_t insn
)
4951 unsigned char *where
= (unsigned char *) buf
;
4953 where
[1] = insn
>> 8;
4954 where
[2] = insn
>> 16;
4955 where
[3] = insn
>> 24;
4959 get_aarch64_insn (char *buf
)
4961 unsigned char *where
= (unsigned char *) buf
;
4963 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4968 output_inst (struct aarch64_inst
*new_inst
)
4972 to
= frag_more (INSN_SIZE
);
4974 frag_now
->tc_frag_data
.recorded
= 1;
4976 put_aarch64_insn (to
, inst
.base
.value
);
4978 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4980 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4981 INSN_SIZE
, &inst
.reloc
.exp
,
4984 DEBUG_TRACE ("Prepared relocation fix up");
4985 /* Don't check the addend value against the instruction size,
4986 that's the job of our code in md_apply_fix(). */
4987 fixp
->fx_no_overflow
= 1;
4988 if (new_inst
!= NULL
)
4989 fixp
->tc_fix_data
.inst
= new_inst
;
4990 if (aarch64_gas_internal_fixup_p ())
4992 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4993 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4994 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4998 dwarf2_emit_insn (INSN_SIZE
);
5001 /* Link together opcodes of the same name. */
5005 aarch64_opcode
*opcode
;
5006 struct templates
*next
;
5009 typedef struct templates templates
;
5012 lookup_mnemonic (const char *start
, int len
)
5014 templates
*templ
= NULL
;
5016 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
5020 /* Subroutine of md_assemble, responsible for looking up the primary
5021 opcode from the mnemonic the user wrote. STR points to the
5022 beginning of the mnemonic. */
5025 opcode_lookup (char **str
)
5027 char *end
, *base
, *dot
;
5028 const aarch64_cond
*cond
;
5032 /* Scan up to the end of the mnemonic, which must end in white space,
5033 '.', or end of string. */
5035 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5036 if (*end
== '.' && !dot
)
5039 if (end
== base
|| dot
== base
)
5042 inst
.cond
= COND_ALWAYS
;
5044 /* Handle a possible condition. */
5047 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5050 inst
.cond
= cond
->value
;
5066 if (inst
.cond
== COND_ALWAYS
)
5068 /* Look for unaffixed mnemonic. */
5069 return lookup_mnemonic (base
, len
);
5073 /* append ".c" to mnemonic if conditional */
5074 memcpy (condname
, base
, len
);
5075 memcpy (condname
+ len
, ".c", 2);
5078 return lookup_mnemonic (base
, len
);
5084 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5085 to a corresponding operand qualifier. */
5087 static inline aarch64_opnd_qualifier_t
5088 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5090 /* Element size in bytes indexed by vector_el_type. */
5091 const unsigned char ele_size
[5]
5093 const unsigned int ele_base
[5] =
5095 AARCH64_OPND_QLF_V_4B
,
5096 AARCH64_OPND_QLF_V_2H
,
5097 AARCH64_OPND_QLF_V_2S
,
5098 AARCH64_OPND_QLF_V_1D
,
5099 AARCH64_OPND_QLF_V_1Q
5102 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5103 goto vectype_conversion_fail
;
5105 if (vectype
->type
== NT_zero
)
5106 return AARCH64_OPND_QLF_P_Z
;
5107 if (vectype
->type
== NT_merge
)
5108 return AARCH64_OPND_QLF_P_M
;
5110 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5112 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5114 /* Special case S_4B. */
5115 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5116 return AARCH64_OPND_QLF_S_4B
;
5118 /* Vector element register. */
5119 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5123 /* Vector register. */
5124 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5127 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5128 goto vectype_conversion_fail
;
5130 /* The conversion is by calculating the offset from the base operand
5131 qualifier for the vector type. The operand qualifiers are regular
5132 enough that the offset can established by shifting the vector width by
5133 a vector-type dependent amount. */
5135 if (vectype
->type
== NT_b
)
5137 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5139 else if (vectype
->type
>= NT_d
)
5144 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5145 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5146 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5150 vectype_conversion_fail
:
5151 first_error (_("bad vector arrangement type"));
5152 return AARCH64_OPND_QLF_NIL
;
5155 /* Process an optional operand that is found omitted from the assembly line.
5156 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5157 instruction's opcode entry while IDX is the index of this omitted operand.
5161 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5162 int idx
, aarch64_opnd_info
*operand
)
5164 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5165 gas_assert (optional_operand_p (opcode
, idx
));
5166 gas_assert (!operand
->present
);
5170 case AARCH64_OPND_Rd
:
5171 case AARCH64_OPND_Rn
:
5172 case AARCH64_OPND_Rm
:
5173 case AARCH64_OPND_Rt
:
5174 case AARCH64_OPND_Rt2
:
5175 case AARCH64_OPND_Rt_SP
:
5176 case AARCH64_OPND_Rs
:
5177 case AARCH64_OPND_Ra
:
5178 case AARCH64_OPND_Rt_SYS
:
5179 case AARCH64_OPND_Rd_SP
:
5180 case AARCH64_OPND_Rn_SP
:
5181 case AARCH64_OPND_Rm_SP
:
5182 case AARCH64_OPND_Fd
:
5183 case AARCH64_OPND_Fn
:
5184 case AARCH64_OPND_Fm
:
5185 case AARCH64_OPND_Fa
:
5186 case AARCH64_OPND_Ft
:
5187 case AARCH64_OPND_Ft2
:
5188 case AARCH64_OPND_Sd
:
5189 case AARCH64_OPND_Sn
:
5190 case AARCH64_OPND_Sm
:
5191 case AARCH64_OPND_Va
:
5192 case AARCH64_OPND_Vd
:
5193 case AARCH64_OPND_Vn
:
5194 case AARCH64_OPND_Vm
:
5195 case AARCH64_OPND_VdD1
:
5196 case AARCH64_OPND_VnD1
:
5197 operand
->reg
.regno
= default_value
;
5200 case AARCH64_OPND_Ed
:
5201 case AARCH64_OPND_En
:
5202 case AARCH64_OPND_Em
:
5203 case AARCH64_OPND_Em16
:
5204 case AARCH64_OPND_SM3_IMM2
:
5205 operand
->reglane
.regno
= default_value
;
5208 case AARCH64_OPND_IDX
:
5209 case AARCH64_OPND_BIT_NUM
:
5210 case AARCH64_OPND_IMMR
:
5211 case AARCH64_OPND_IMMS
:
5212 case AARCH64_OPND_SHLL_IMM
:
5213 case AARCH64_OPND_IMM_VLSL
:
5214 case AARCH64_OPND_IMM_VLSR
:
5215 case AARCH64_OPND_CCMP_IMM
:
5216 case AARCH64_OPND_FBITS
:
5217 case AARCH64_OPND_UIMM4
:
5218 case AARCH64_OPND_UIMM3_OP1
:
5219 case AARCH64_OPND_UIMM3_OP2
:
5220 case AARCH64_OPND_IMM
:
5221 case AARCH64_OPND_IMM_2
:
5222 case AARCH64_OPND_WIDTH
:
5223 case AARCH64_OPND_UIMM7
:
5224 case AARCH64_OPND_NZCV
:
5225 case AARCH64_OPND_SVE_PATTERN
:
5226 case AARCH64_OPND_SVE_PRFOP
:
5227 operand
->imm
.value
= default_value
;
5230 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5231 operand
->imm
.value
= default_value
;
5232 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5233 operand
->shifter
.amount
= 1;
5236 case AARCH64_OPND_EXCEPTION
:
5237 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5240 case AARCH64_OPND_BARRIER_ISB
:
5241 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5244 case AARCH64_OPND_BTI_TARGET
:
5245 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5253 /* Process the relocation type for move wide instructions.
5254 Return TRUE on success; otherwise return FALSE. */
5257 process_movw_reloc_info (void)
5262 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5264 if (inst
.base
.opcode
->op
== OP_MOVK
)
5265 switch (inst
.reloc
.type
)
5267 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5268 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5269 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5270 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5271 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5272 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5273 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5274 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5275 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5277 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5279 (_("the specified relocation type is not allowed for MOVK"));
5285 switch (inst
.reloc
.type
)
5287 case BFD_RELOC_AARCH64_MOVW_G0
:
5288 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5289 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5290 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5291 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5292 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5293 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5294 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5295 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5296 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5297 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5298 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5299 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5302 case BFD_RELOC_AARCH64_MOVW_G1
:
5303 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5304 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5305 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5306 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5307 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5308 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5309 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5310 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5311 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5312 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5313 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5314 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5317 case BFD_RELOC_AARCH64_MOVW_G2
:
5318 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5319 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5320 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5321 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5322 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5323 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5326 set_fatal_syntax_error
5327 (_("the specified relocation type is not allowed for 32-bit "
5333 case BFD_RELOC_AARCH64_MOVW_G3
:
5334 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5337 set_fatal_syntax_error
5338 (_("the specified relocation type is not allowed for 32-bit "
5345 /* More cases should be added when more MOVW-related relocation types
5346 are supported in GAS. */
5347 gas_assert (aarch64_gas_internal_fixup_p ());
5348 /* The shift amount should have already been set by the parser. */
5351 inst
.base
.operands
[1].shifter
.amount
= shift
;
5355 /* A primitive log calculator. */
5357 static inline unsigned int
5358 get_logsz (unsigned int size
)
5360 const unsigned char ls
[16] =
5361 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5367 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5368 return ls
[size
- 1];
5371 /* Determine and return the real reloc type code for an instruction
5372 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5374 static inline bfd_reloc_code_real_type
5375 ldst_lo12_determine_real_reloc_type (void)
5378 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5379 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5381 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5383 BFD_RELOC_AARCH64_LDST8_LO12
,
5384 BFD_RELOC_AARCH64_LDST16_LO12
,
5385 BFD_RELOC_AARCH64_LDST32_LO12
,
5386 BFD_RELOC_AARCH64_LDST64_LO12
,
5387 BFD_RELOC_AARCH64_LDST128_LO12
5390 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5391 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5392 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5393 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5394 BFD_RELOC_AARCH64_NONE
5397 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5398 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5399 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5400 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5401 BFD_RELOC_AARCH64_NONE
5404 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5405 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5406 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5407 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5408 BFD_RELOC_AARCH64_NONE
5411 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5412 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5413 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5414 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5415 BFD_RELOC_AARCH64_NONE
5419 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5420 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5422 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5424 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5426 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5427 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5429 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5431 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5433 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5435 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5436 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5437 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5438 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5439 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5440 gas_assert (logsz
<= 3);
5442 gas_assert (logsz
<= 4);
5444 /* In reloc.c, these pseudo relocation types should be defined in similar
5445 order as above reloc_ldst_lo12 array. Because the array index calculation
5446 below relies on this. */
5447 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5450 /* Check whether a register list REGINFO is valid. The registers must be
5451 numbered in increasing order (modulo 32), in increments of one or two.
5453 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5456 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5459 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5461 uint32_t i
, nb_regs
, prev_regno
, incr
;
5463 nb_regs
= 1 + (reginfo
& 0x3);
5465 prev_regno
= reginfo
& 0x1f;
5466 incr
= accept_alternate
? 2 : 1;
5468 for (i
= 1; i
< nb_regs
; ++i
)
5470 uint32_t curr_regno
;
5472 curr_regno
= reginfo
& 0x1f;
5473 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5475 prev_regno
= curr_regno
;
5481 /* Generic instruction operand parser. This does no encoding and no
5482 semantic validation; it merely squirrels values away in the inst
5483 structure. Returns TRUE or FALSE depending on whether the
5484 specified grammar matched. */
5487 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5490 char *backtrack_pos
= 0;
5491 const enum aarch64_opnd
*operands
= opcode
->operands
;
5492 aarch64_reg_type imm_reg_type
;
5495 skip_whitespace (str
);
5497 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5498 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5500 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5502 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5505 const reg_entry
*reg
;
5506 int comma_skipped_p
= 0;
5507 aarch64_reg_type rtype
;
5508 struct vector_type_el vectype
;
5509 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5510 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5511 aarch64_reg_type reg_type
;
5513 DEBUG_TRACE ("parse operand %d", i
);
5515 /* Assign the operand code. */
5516 info
->type
= operands
[i
];
5518 if (optional_operand_p (opcode
, i
))
5520 /* Remember where we are in case we need to backtrack. */
5521 gas_assert (!backtrack_pos
);
5522 backtrack_pos
= str
;
5525 /* Expect comma between operands; the backtrack mechanism will take
5526 care of cases of omitted optional operand. */
5527 if (i
> 0 && ! skip_past_char (&str
, ','))
5529 set_syntax_error (_("comma expected between operands"));
5533 comma_skipped_p
= 1;
5535 switch (operands
[i
])
5537 case AARCH64_OPND_Rd
:
5538 case AARCH64_OPND_Rn
:
5539 case AARCH64_OPND_Rm
:
5540 case AARCH64_OPND_Rt
:
5541 case AARCH64_OPND_Rt2
:
5542 case AARCH64_OPND_Rs
:
5543 case AARCH64_OPND_Ra
:
5544 case AARCH64_OPND_Rt_SYS
:
5545 case AARCH64_OPND_PAIRREG
:
5546 case AARCH64_OPND_SVE_Rm
:
5547 po_int_reg_or_fail (REG_TYPE_R_Z
);
5550 case AARCH64_OPND_Rd_SP
:
5551 case AARCH64_OPND_Rn_SP
:
5552 case AARCH64_OPND_Rt_SP
:
5553 case AARCH64_OPND_SVE_Rn_SP
:
5554 case AARCH64_OPND_Rm_SP
:
5555 po_int_reg_or_fail (REG_TYPE_R_SP
);
5558 case AARCH64_OPND_Rm_EXT
:
5559 case AARCH64_OPND_Rm_SFT
:
5560 po_misc_or_fail (parse_shifter_operand
5561 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5563 : SHIFTED_LOGIC_IMM
)));
5564 if (!info
->shifter
.operator_present
)
5566 /* Default to LSL if not present. Libopcodes prefers shifter
5567 kind to be explicit. */
5568 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5569 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5570 /* For Rm_EXT, libopcodes will carry out further check on whether
5571 or not stack pointer is used in the instruction (Recall that
5572 "the extend operator is not optional unless at least one of
5573 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5577 case AARCH64_OPND_Fd
:
5578 case AARCH64_OPND_Fn
:
5579 case AARCH64_OPND_Fm
:
5580 case AARCH64_OPND_Fa
:
5581 case AARCH64_OPND_Ft
:
5582 case AARCH64_OPND_Ft2
:
5583 case AARCH64_OPND_Sd
:
5584 case AARCH64_OPND_Sn
:
5585 case AARCH64_OPND_Sm
:
5586 case AARCH64_OPND_SVE_VZn
:
5587 case AARCH64_OPND_SVE_Vd
:
5588 case AARCH64_OPND_SVE_Vm
:
5589 case AARCH64_OPND_SVE_Vn
:
5590 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5591 if (val
== PARSE_FAIL
)
5593 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5596 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5598 info
->reg
.regno
= val
;
5599 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5602 case AARCH64_OPND_SVE_Pd
:
5603 case AARCH64_OPND_SVE_Pg3
:
5604 case AARCH64_OPND_SVE_Pg4_5
:
5605 case AARCH64_OPND_SVE_Pg4_10
:
5606 case AARCH64_OPND_SVE_Pg4_16
:
5607 case AARCH64_OPND_SVE_Pm
:
5608 case AARCH64_OPND_SVE_Pn
:
5609 case AARCH64_OPND_SVE_Pt
:
5610 reg_type
= REG_TYPE_PN
;
5613 case AARCH64_OPND_SVE_Za_5
:
5614 case AARCH64_OPND_SVE_Za_16
:
5615 case AARCH64_OPND_SVE_Zd
:
5616 case AARCH64_OPND_SVE_Zm_5
:
5617 case AARCH64_OPND_SVE_Zm_16
:
5618 case AARCH64_OPND_SVE_Zn
:
5619 case AARCH64_OPND_SVE_Zt
:
5620 reg_type
= REG_TYPE_ZN
;
5623 case AARCH64_OPND_Va
:
5624 case AARCH64_OPND_Vd
:
5625 case AARCH64_OPND_Vn
:
5626 case AARCH64_OPND_Vm
:
5627 reg_type
= REG_TYPE_VN
;
5629 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5630 if (val
== PARSE_FAIL
)
5632 first_error (_(get_reg_expected_msg (reg_type
)));
5635 if (vectype
.defined
& NTA_HASINDEX
)
5638 info
->reg
.regno
= val
;
5639 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5640 && vectype
.type
== NT_invtype
)
5641 /* Unqualified Pn and Zn registers are allowed in certain
5642 contexts. Rely on F_STRICT qualifier checking to catch
5644 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5647 info
->qualifier
= vectype_to_qualifier (&vectype
);
5648 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5653 case AARCH64_OPND_VdD1
:
5654 case AARCH64_OPND_VnD1
:
5655 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5656 if (val
== PARSE_FAIL
)
5658 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5661 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5663 set_fatal_syntax_error
5664 (_("the top half of a 128-bit FP/SIMD register is expected"));
5667 info
->reg
.regno
= val
;
5668 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5669 here; it is correct for the purpose of encoding/decoding since
5670 only the register number is explicitly encoded in the related
5671 instructions, although this appears a bit hacky. */
5672 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5675 case AARCH64_OPND_SVE_Zm3_INDEX
:
5676 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5677 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5678 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5679 case AARCH64_OPND_SVE_Zm4_INDEX
:
5680 case AARCH64_OPND_SVE_Zn_INDEX
:
5681 reg_type
= REG_TYPE_ZN
;
5682 goto vector_reg_index
;
5684 case AARCH64_OPND_Ed
:
5685 case AARCH64_OPND_En
:
5686 case AARCH64_OPND_Em
:
5687 case AARCH64_OPND_Em16
:
5688 case AARCH64_OPND_SM3_IMM2
:
5689 reg_type
= REG_TYPE_VN
;
5691 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5692 if (val
== PARSE_FAIL
)
5694 first_error (_(get_reg_expected_msg (reg_type
)));
5697 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5700 info
->reglane
.regno
= val
;
5701 info
->reglane
.index
= vectype
.index
;
5702 info
->qualifier
= vectype_to_qualifier (&vectype
);
5703 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5707 case AARCH64_OPND_SVE_ZnxN
:
5708 case AARCH64_OPND_SVE_ZtxN
:
5709 reg_type
= REG_TYPE_ZN
;
5710 goto vector_reg_list
;
5712 case AARCH64_OPND_LVn
:
5713 case AARCH64_OPND_LVt
:
5714 case AARCH64_OPND_LVt_AL
:
5715 case AARCH64_OPND_LEt
:
5716 reg_type
= REG_TYPE_VN
;
5718 if (reg_type
== REG_TYPE_ZN
5719 && get_opcode_dependent_value (opcode
) == 1
5722 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5723 if (val
== PARSE_FAIL
)
5725 first_error (_(get_reg_expected_msg (reg_type
)));
5728 info
->reglist
.first_regno
= val
;
5729 info
->reglist
.num_regs
= 1;
5733 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5734 if (val
== PARSE_FAIL
)
5736 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5738 set_fatal_syntax_error (_("invalid register list"));
5741 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5742 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5744 if (operands
[i
] == AARCH64_OPND_LEt
)
5746 if (!(vectype
.defined
& NTA_HASINDEX
))
5748 info
->reglist
.has_index
= 1;
5749 info
->reglist
.index
= vectype
.index
;
5753 if (vectype
.defined
& NTA_HASINDEX
)
5755 if (!(vectype
.defined
& NTA_HASTYPE
))
5757 if (reg_type
== REG_TYPE_ZN
)
5758 set_fatal_syntax_error (_("missing type suffix"));
5762 info
->qualifier
= vectype_to_qualifier (&vectype
);
5763 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5767 case AARCH64_OPND_CRn
:
5768 case AARCH64_OPND_CRm
:
5770 char prefix
= *(str
++);
5771 if (prefix
!= 'c' && prefix
!= 'C')
5774 po_imm_nc_or_fail ();
5777 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5780 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5781 info
->imm
.value
= val
;
5785 case AARCH64_OPND_SHLL_IMM
:
5786 case AARCH64_OPND_IMM_VLSR
:
5787 po_imm_or_fail (1, 64);
5788 info
->imm
.value
= val
;
5791 case AARCH64_OPND_CCMP_IMM
:
5792 case AARCH64_OPND_SIMM5
:
5793 case AARCH64_OPND_FBITS
:
5794 case AARCH64_OPND_TME_UIMM16
:
5795 case AARCH64_OPND_UIMM4
:
5796 case AARCH64_OPND_UIMM4_ADDG
:
5797 case AARCH64_OPND_UIMM10
:
5798 case AARCH64_OPND_UIMM3_OP1
:
5799 case AARCH64_OPND_UIMM3_OP2
:
5800 case AARCH64_OPND_IMM_VLSL
:
5801 case AARCH64_OPND_IMM
:
5802 case AARCH64_OPND_IMM_2
:
5803 case AARCH64_OPND_WIDTH
:
5804 case AARCH64_OPND_SVE_INV_LIMM
:
5805 case AARCH64_OPND_SVE_LIMM
:
5806 case AARCH64_OPND_SVE_LIMM_MOV
:
5807 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5808 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5809 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5810 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5811 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5812 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5813 case AARCH64_OPND_SVE_SIMM5
:
5814 case AARCH64_OPND_SVE_SIMM5B
:
5815 case AARCH64_OPND_SVE_SIMM6
:
5816 case AARCH64_OPND_SVE_SIMM8
:
5817 case AARCH64_OPND_SVE_UIMM3
:
5818 case AARCH64_OPND_SVE_UIMM7
:
5819 case AARCH64_OPND_SVE_UIMM8
:
5820 case AARCH64_OPND_SVE_UIMM8_53
:
5821 case AARCH64_OPND_IMM_ROT1
:
5822 case AARCH64_OPND_IMM_ROT2
:
5823 case AARCH64_OPND_IMM_ROT3
:
5824 case AARCH64_OPND_SVE_IMM_ROT1
:
5825 case AARCH64_OPND_SVE_IMM_ROT2
:
5826 case AARCH64_OPND_SVE_IMM_ROT3
:
5827 po_imm_nc_or_fail ();
5828 info
->imm
.value
= val
;
5831 case AARCH64_OPND_SVE_AIMM
:
5832 case AARCH64_OPND_SVE_ASIMM
:
5833 po_imm_nc_or_fail ();
5834 info
->imm
.value
= val
;
5835 skip_whitespace (str
);
5836 if (skip_past_comma (&str
))
5837 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5839 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5842 case AARCH64_OPND_SVE_PATTERN
:
5843 po_enum_or_fail (aarch64_sve_pattern_array
);
5844 info
->imm
.value
= val
;
5847 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5848 po_enum_or_fail (aarch64_sve_pattern_array
);
5849 info
->imm
.value
= val
;
5850 if (skip_past_comma (&str
)
5851 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5853 if (!info
->shifter
.operator_present
)
5855 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5856 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5857 info
->shifter
.amount
= 1;
5861 case AARCH64_OPND_SVE_PRFOP
:
5862 po_enum_or_fail (aarch64_sve_prfop_array
);
5863 info
->imm
.value
= val
;
5866 case AARCH64_OPND_UIMM7
:
5867 po_imm_or_fail (0, 127);
5868 info
->imm
.value
= val
;
5871 case AARCH64_OPND_IDX
:
5872 case AARCH64_OPND_MASK
:
5873 case AARCH64_OPND_BIT_NUM
:
5874 case AARCH64_OPND_IMMR
:
5875 case AARCH64_OPND_IMMS
:
5876 po_imm_or_fail (0, 63);
5877 info
->imm
.value
= val
;
5880 case AARCH64_OPND_IMM0
:
5881 po_imm_nc_or_fail ();
5884 set_fatal_syntax_error (_("immediate zero expected"));
5887 info
->imm
.value
= 0;
5890 case AARCH64_OPND_FPIMM0
:
5893 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5894 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5895 it is probably not worth the effort to support it. */
5896 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5899 || !(res2
= parse_constant_immediate (&str
, &val
,
5902 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5904 info
->imm
.value
= 0;
5905 info
->imm
.is_fp
= 1;
5908 set_fatal_syntax_error (_("immediate zero expected"));
5912 case AARCH64_OPND_IMM_MOV
:
5915 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5916 reg_name_p (str
, REG_TYPE_VN
))
5919 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5921 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5922 later. fix_mov_imm_insn will try to determine a machine
5923 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5924 message if the immediate cannot be moved by a single
5926 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5927 inst
.base
.operands
[i
].skip
= 1;
5931 case AARCH64_OPND_SIMD_IMM
:
5932 case AARCH64_OPND_SIMD_IMM_SFT
:
5933 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5935 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5937 /* need_libopcodes_p */ 1,
5940 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5941 shift, we don't check it here; we leave the checking to
5942 the libopcodes (operand_general_constraint_met_p). By
5943 doing this, we achieve better diagnostics. */
5944 if (skip_past_comma (&str
)
5945 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5947 if (!info
->shifter
.operator_present
5948 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5950 /* Default to LSL if not present. Libopcodes prefers shifter
5951 kind to be explicit. */
5952 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5953 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5957 case AARCH64_OPND_FPIMM
:
5958 case AARCH64_OPND_SIMD_FPIMM
:
5959 case AARCH64_OPND_SVE_FPIMM8
:
5964 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5965 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5966 || !aarch64_imm_float_p (qfloat
))
5969 set_fatal_syntax_error (_("invalid floating-point"
5973 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5974 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5978 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5979 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5980 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5985 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5986 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5989 set_fatal_syntax_error (_("invalid floating-point"
5993 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5994 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5998 case AARCH64_OPND_LIMM
:
5999 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6000 SHIFTED_LOGIC_IMM
));
6001 if (info
->shifter
.operator_present
)
6003 set_fatal_syntax_error
6004 (_("shift not allowed for bitmask immediate"));
6007 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6009 /* need_libopcodes_p */ 1,
6013 case AARCH64_OPND_AIMM
:
6014 if (opcode
->op
== OP_ADD
)
6015 /* ADD may have relocation types. */
6016 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6017 SHIFTED_ARITH_IMM
));
6019 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6020 SHIFTED_ARITH_IMM
));
6021 switch (inst
.reloc
.type
)
6023 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6024 info
->shifter
.amount
= 12;
6026 case BFD_RELOC_UNUSED
:
6027 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6028 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6029 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6030 inst
.reloc
.pc_rel
= 0;
6035 info
->imm
.value
= 0;
6036 if (!info
->shifter
.operator_present
)
6038 /* Default to LSL if not present. Libopcodes prefers shifter
6039 kind to be explicit. */
6040 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6041 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6045 case AARCH64_OPND_HALF
:
6047 /* #<imm16> or relocation. */
6048 int internal_fixup_p
;
6049 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6050 if (internal_fixup_p
)
6051 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6052 skip_whitespace (str
);
6053 if (skip_past_comma (&str
))
6055 /* {, LSL #<shift>} */
6056 if (! aarch64_gas_internal_fixup_p ())
6058 set_fatal_syntax_error (_("can't mix relocation modifier "
6059 "with explicit shift"));
6062 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6065 inst
.base
.operands
[i
].shifter
.amount
= 0;
6066 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6067 inst
.base
.operands
[i
].imm
.value
= 0;
6068 if (! process_movw_reloc_info ())
6073 case AARCH64_OPND_EXCEPTION
:
6074 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6076 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6078 /* need_libopcodes_p */ 0,
6082 case AARCH64_OPND_NZCV
:
6084 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6088 info
->imm
.value
= nzcv
->value
;
6091 po_imm_or_fail (0, 15);
6092 info
->imm
.value
= val
;
6096 case AARCH64_OPND_COND
:
6097 case AARCH64_OPND_COND1
:
6102 while (ISALPHA (*str
));
6103 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6104 if (info
->cond
== NULL
)
6106 set_syntax_error (_("invalid condition"));
6109 else if (operands
[i
] == AARCH64_OPND_COND1
6110 && (info
->cond
->value
& 0xe) == 0xe)
6112 /* Do not allow AL or NV. */
6113 set_default_error ();
6119 case AARCH64_OPND_ADDR_ADRP
:
6120 po_misc_or_fail (parse_adrp (&str
));
6121 /* Clear the value as operand needs to be relocated. */
6122 info
->imm
.value
= 0;
6125 case AARCH64_OPND_ADDR_PCREL14
:
6126 case AARCH64_OPND_ADDR_PCREL19
:
6127 case AARCH64_OPND_ADDR_PCREL21
:
6128 case AARCH64_OPND_ADDR_PCREL26
:
6129 po_misc_or_fail (parse_address (&str
, info
));
6130 if (!info
->addr
.pcrel
)
6132 set_syntax_error (_("invalid pc-relative address"));
6135 if (inst
.gen_lit_pool
6136 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6138 /* Only permit "=value" in the literal load instructions.
6139 The literal will be generated by programmer_friendly_fixup. */
6140 set_syntax_error (_("invalid use of \"=immediate\""));
6143 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6145 set_syntax_error (_("unrecognized relocation suffix"));
6148 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6150 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6151 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6155 info
->imm
.value
= 0;
6156 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6157 switch (opcode
->iclass
)
6161 /* e.g. CBZ or B.COND */
6162 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6163 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6167 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6168 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6172 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6174 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6175 : BFD_RELOC_AARCH64_JUMP26
;
6178 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6179 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6182 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6183 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6189 inst
.reloc
.pc_rel
= 1;
6193 case AARCH64_OPND_ADDR_SIMPLE
:
6194 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6196 /* [<Xn|SP>{, #<simm>}] */
6198 /* First use the normal address-parsing routines, to get
6199 the usual syntax errors. */
6200 po_misc_or_fail (parse_address (&str
, info
));
6201 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6202 || !info
->addr
.preind
|| info
->addr
.postind
6203 || info
->addr
.writeback
)
6205 set_syntax_error (_("invalid addressing mode"));
6209 /* Then retry, matching the specific syntax of these addresses. */
6211 po_char_or_fail ('[');
6212 po_reg_or_fail (REG_TYPE_R64_SP
);
6213 /* Accept optional ", #0". */
6214 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6215 && skip_past_char (&str
, ','))
6217 skip_past_char (&str
, '#');
6218 if (! skip_past_char (&str
, '0'))
6220 set_fatal_syntax_error
6221 (_("the optional immediate offset can only be 0"));
6225 po_char_or_fail (']');
6229 case AARCH64_OPND_ADDR_REGOFF
:
6230 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6231 po_misc_or_fail (parse_address (&str
, info
));
6233 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6234 || !info
->addr
.preind
|| info
->addr
.postind
6235 || info
->addr
.writeback
)
6237 set_syntax_error (_("invalid addressing mode"));
6240 if (!info
->shifter
.operator_present
)
6242 /* Default to LSL if not present. Libopcodes prefers shifter
6243 kind to be explicit. */
6244 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6245 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6247 /* Qualifier to be deduced by libopcodes. */
6250 case AARCH64_OPND_ADDR_SIMM7
:
6251 po_misc_or_fail (parse_address (&str
, info
));
6252 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6253 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6255 set_syntax_error (_("invalid addressing mode"));
6258 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6260 set_syntax_error (_("relocation not allowed"));
6263 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6265 /* need_libopcodes_p */ 1,
6269 case AARCH64_OPND_ADDR_SIMM9
:
6270 case AARCH64_OPND_ADDR_SIMM9_2
:
6271 case AARCH64_OPND_ADDR_SIMM11
:
6272 case AARCH64_OPND_ADDR_SIMM13
:
6273 po_misc_or_fail (parse_address (&str
, info
));
6274 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6275 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6276 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6277 && info
->addr
.writeback
))
6279 set_syntax_error (_("invalid addressing mode"));
6282 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6284 set_syntax_error (_("relocation not allowed"));
6287 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6289 /* need_libopcodes_p */ 1,
6293 case AARCH64_OPND_ADDR_SIMM10
:
6294 case AARCH64_OPND_ADDR_OFFSET
:
6295 po_misc_or_fail (parse_address (&str
, info
));
6296 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6297 || !info
->addr
.preind
|| info
->addr
.postind
)
6299 set_syntax_error (_("invalid addressing mode"));
6302 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6304 set_syntax_error (_("relocation not allowed"));
6307 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6309 /* need_libopcodes_p */ 1,
6313 case AARCH64_OPND_ADDR_UIMM12
:
6314 po_misc_or_fail (parse_address (&str
, info
));
6315 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6316 || !info
->addr
.preind
|| info
->addr
.writeback
)
6318 set_syntax_error (_("invalid addressing mode"));
6321 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6322 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6323 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6325 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6327 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6329 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6331 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6332 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6333 /* Leave qualifier to be determined by libopcodes. */
6336 case AARCH64_OPND_SIMD_ADDR_POST
:
6337 /* [<Xn|SP>], <Xm|#<amount>> */
6338 po_misc_or_fail (parse_address (&str
, info
));
6339 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6341 set_syntax_error (_("invalid addressing mode"));
6344 if (!info
->addr
.offset
.is_reg
)
6346 if (inst
.reloc
.exp
.X_op
== O_constant
)
6347 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6350 set_fatal_syntax_error
6351 (_("writeback value must be an immediate constant"));
6358 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6359 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6360 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6361 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6362 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6363 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6364 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6365 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6366 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6367 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6368 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6369 /* [X<n>{, #imm, MUL VL}]
6371 but recognizing SVE registers. */
6372 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6373 &offset_qualifier
));
6374 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6376 set_syntax_error (_("invalid addressing mode"));
6380 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6381 || !info
->addr
.preind
|| info
->addr
.writeback
)
6383 set_syntax_error (_("invalid addressing mode"));
6386 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6387 || inst
.reloc
.exp
.X_op
!= O_constant
)
6389 /* Make sure this has priority over
6390 "invalid addressing mode". */
6391 set_fatal_syntax_error (_("constant offset required"));
6394 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6397 case AARCH64_OPND_SVE_ADDR_R
:
6398 /* [<Xn|SP>{, <R><m>}]
6399 but recognizing SVE registers. */
6400 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6401 &offset_qualifier
));
6402 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6404 offset_qualifier
= AARCH64_OPND_QLF_X
;
6405 info
->addr
.offset
.is_reg
= 1;
6406 info
->addr
.offset
.regno
= 31;
6408 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6409 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6411 set_syntax_error (_("invalid addressing mode"));
6416 case AARCH64_OPND_SVE_ADDR_RR
:
6417 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6418 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6419 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6420 case AARCH64_OPND_SVE_ADDR_RX
:
6421 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6422 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6423 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6424 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6425 but recognizing SVE registers. */
6426 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6427 &offset_qualifier
));
6428 if (base_qualifier
!= AARCH64_OPND_QLF_X
6429 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6431 set_syntax_error (_("invalid addressing mode"));
6436 case AARCH64_OPND_SVE_ADDR_RZ
:
6437 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6438 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6439 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6440 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6441 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6442 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6443 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6444 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6445 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6446 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6447 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6448 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6449 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6450 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6451 &offset_qualifier
));
6452 if (base_qualifier
!= AARCH64_OPND_QLF_X
6453 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6454 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6456 set_syntax_error (_("invalid addressing mode"));
6459 info
->qualifier
= offset_qualifier
;
6462 case AARCH64_OPND_SVE_ADDR_ZX
:
6463 /* [Zn.<T>{, <Xm>}]. */
6464 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6465 &offset_qualifier
));
6467 base_qualifier either S_S or S_D
6468 offset_qualifier must be X
6470 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6471 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6472 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6474 set_syntax_error (_("invalid addressing mode"));
6477 info
->qualifier
= base_qualifier
;
6478 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6479 || !info
->addr
.preind
|| info
->addr
.writeback
6480 || info
->shifter
.operator_present
!= 0)
6482 set_syntax_error (_("invalid addressing mode"));
6485 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6489 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6490 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6491 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6492 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6493 /* [Z<n>.<T>{, #imm}] */
6494 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6495 &offset_qualifier
));
6496 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6497 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6499 set_syntax_error (_("invalid addressing mode"));
6502 info
->qualifier
= base_qualifier
;
6505 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6506 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6507 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6508 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6509 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6513 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6515 here since we get better error messages by leaving it to
6516 the qualifier checking routines. */
6517 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6518 &offset_qualifier
));
6519 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6520 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6521 || offset_qualifier
!= base_qualifier
)
6523 set_syntax_error (_("invalid addressing mode"));
6526 info
->qualifier
= base_qualifier
;
6529 case AARCH64_OPND_SYSREG
:
6531 uint32_t sysreg_flags
;
6532 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6533 &sysreg_flags
)) == PARSE_FAIL
)
6535 set_syntax_error (_("unknown or missing system register name"));
6538 inst
.base
.operands
[i
].sysreg
.value
= val
;
6539 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6543 case AARCH64_OPND_PSTATEFIELD
:
6544 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6547 set_syntax_error (_("unknown or missing PSTATE field name"));
6550 inst
.base
.operands
[i
].pstatefield
= val
;
6553 case AARCH64_OPND_SYSREG_IC
:
6554 inst
.base
.operands
[i
].sysins_op
=
6555 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6558 case AARCH64_OPND_SYSREG_DC
:
6559 inst
.base
.operands
[i
].sysins_op
=
6560 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6563 case AARCH64_OPND_SYSREG_AT
:
6564 inst
.base
.operands
[i
].sysins_op
=
6565 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6568 case AARCH64_OPND_SYSREG_SR
:
6569 inst
.base
.operands
[i
].sysins_op
=
6570 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6573 case AARCH64_OPND_SYSREG_TLBI
:
6574 inst
.base
.operands
[i
].sysins_op
=
6575 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6577 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6579 set_fatal_syntax_error ( _("unknown or missing operation name"));
6584 case AARCH64_OPND_BARRIER
:
6585 case AARCH64_OPND_BARRIER_ISB
:
6586 val
= parse_barrier (&str
);
6587 if (val
!= PARSE_FAIL
6588 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6590 /* ISB only accepts options name 'sy'. */
6592 (_("the specified option is not accepted in ISB"));
6593 /* Turn off backtrack as this optional operand is present. */
6597 /* This is an extension to accept a 0..15 immediate. */
6598 if (val
== PARSE_FAIL
)
6599 po_imm_or_fail (0, 15);
6600 info
->barrier
= aarch64_barrier_options
+ val
;
6603 case AARCH64_OPND_PRFOP
:
6604 val
= parse_pldop (&str
);
6605 /* This is an extension to accept a 0..31 immediate. */
6606 if (val
== PARSE_FAIL
)
6607 po_imm_or_fail (0, 31);
6608 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6611 case AARCH64_OPND_BARRIER_PSB
:
6612 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6613 if (val
== PARSE_FAIL
)
6617 case AARCH64_OPND_BTI_TARGET
:
6618 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6619 if (val
== PARSE_FAIL
)
6624 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6627 /* If we get here, this operand was successfully parsed. */
6628 inst
.base
.operands
[i
].present
= 1;
6632 /* The parse routine should already have set the error, but in case
6633 not, set a default one here. */
6635 set_default_error ();
6637 if (! backtrack_pos
)
6638 goto parse_operands_return
;
6641 /* We reach here because this operand is marked as optional, and
6642 either no operand was supplied or the operand was supplied but it
6643 was syntactically incorrect. In the latter case we report an
6644 error. In the former case we perform a few more checks before
6645 dropping through to the code to insert the default operand. */
6647 char *tmp
= backtrack_pos
;
6648 char endchar
= END_OF_INSN
;
6650 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6652 skip_past_char (&tmp
, ',');
6654 if (*tmp
!= endchar
)
6655 /* The user has supplied an operand in the wrong format. */
6656 goto parse_operands_return
;
6658 /* Make sure there is not a comma before the optional operand.
6659 For example the fifth operand of 'sys' is optional:
6661 sys #0,c0,c0,#0, <--- wrong
6662 sys #0,c0,c0,#0 <--- correct. */
6663 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6665 set_fatal_syntax_error
6666 (_("unexpected comma before the omitted optional operand"));
6667 goto parse_operands_return
;
6671 /* Reaching here means we are dealing with an optional operand that is
6672 omitted from the assembly line. */
6673 gas_assert (optional_operand_p (opcode
, i
));
6675 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6677 /* Try again, skipping the optional operand at backtrack_pos. */
6678 str
= backtrack_pos
;
6681 /* Clear any error record after the omitted optional operand has been
6682 successfully handled. */
6686 /* Check if we have parsed all the operands. */
6687 if (*str
!= '\0' && ! error_p ())
6689 /* Set I to the index of the last present operand; this is
6690 for the purpose of diagnostics. */
6691 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6693 set_fatal_syntax_error
6694 (_("unexpected characters following instruction"));
6697 parse_operands_return
:
6701 DEBUG_TRACE ("parsing FAIL: %s - %s",
6702 operand_mismatch_kind_names
[get_error_kind ()],
6703 get_error_message ());
6704 /* Record the operand error properly; this is useful when there
6705 are multiple instruction templates for a mnemonic name, so that
6706 later on, we can select the error that most closely describes
6708 record_operand_error (opcode
, i
, get_error_kind (),
6709 get_error_message ());
6714 DEBUG_TRACE ("parsing SUCCESS");
6719 /* It does some fix-up to provide some programmer friendly feature while
6720 keeping the libopcodes happy, i.e. libopcodes only accepts
6721 the preferred architectural syntax.
6722 Return FALSE if there is any failure; otherwise return TRUE. */
6725 programmer_friendly_fixup (aarch64_instruction
*instr
)
6727 aarch64_inst
*base
= &instr
->base
;
6728 const aarch64_opcode
*opcode
= base
->opcode
;
6729 enum aarch64_op op
= opcode
->op
;
6730 aarch64_opnd_info
*operands
= base
->operands
;
6732 DEBUG_TRACE ("enter");
6734 switch (opcode
->iclass
)
6737 /* TBNZ Xn|Wn, #uimm6, label
6738 Test and Branch Not Zero: conditionally jumps to label if bit number
6739 uimm6 in register Xn is not zero. The bit number implies the width of
6740 the register, which may be written and should be disassembled as Wn if
6741 uimm is less than 32. */
6742 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6744 if (operands
[1].imm
.value
>= 32)
6746 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6750 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6754 /* LDR Wt, label | =value
6755 As a convenience assemblers will typically permit the notation
6756 "=value" in conjunction with the pc-relative literal load instructions
6757 to automatically place an immediate value or symbolic address in a
6758 nearby literal pool and generate a hidden label which references it.
6759 ISREG has been set to 0 in the case of =value. */
6760 if (instr
->gen_lit_pool
6761 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6763 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6764 if (op
== OP_LDRSW_LIT
)
6766 if (instr
->reloc
.exp
.X_op
!= O_constant
6767 && instr
->reloc
.exp
.X_op
!= O_big
6768 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6770 record_operand_error (opcode
, 1,
6771 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6772 _("constant expression expected"));
6775 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6777 record_operand_error (opcode
, 1,
6778 AARCH64_OPDE_OTHER_ERROR
,
6779 _("literal pool insertion failed"));
6787 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6788 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6789 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6790 A programmer-friendly assembler should accept a destination Xd in
6791 place of Wd, however that is not the preferred form for disassembly.
6793 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6794 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6795 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6796 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6801 /* In the 64-bit form, the final register operand is written as Wm
6802 for all but the (possibly omitted) UXTX/LSL and SXTX
6804 As a programmer-friendly assembler, we accept e.g.
6805 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6806 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6807 int idx
= aarch64_operand_index (opcode
->operands
,
6808 AARCH64_OPND_Rm_EXT
);
6809 gas_assert (idx
== 1 || idx
== 2);
6810 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6811 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6812 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6813 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6814 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6815 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6823 DEBUG_TRACE ("exit with SUCCESS");
6827 /* Check for loads and stores that will cause unpredictable behavior. */
6830 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6832 aarch64_inst
*base
= &instr
->base
;
6833 const aarch64_opcode
*opcode
= base
->opcode
;
6834 const aarch64_opnd_info
*opnds
= base
->operands
;
6835 switch (opcode
->iclass
)
6842 /* Loading/storing the base register is unpredictable if writeback. */
6843 if ((aarch64_get_operand_class (opnds
[0].type
)
6844 == AARCH64_OPND_CLASS_INT_REG
)
6845 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6846 && opnds
[1].addr
.base_regno
!= REG_SP
6847 /* Exempt STG/STZG/ST2G/STZ2G. */
6848 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6849 && opnds
[1].addr
.writeback
)
6850 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6854 case ldstnapair_offs
:
6855 case ldstpair_indexed
:
6856 /* Loading/storing the base register is unpredictable if writeback. */
6857 if ((aarch64_get_operand_class (opnds
[0].type
)
6858 == AARCH64_OPND_CLASS_INT_REG
)
6859 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6860 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6861 && opnds
[2].addr
.base_regno
!= REG_SP
6863 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6864 && opnds
[2].addr
.writeback
)
6865 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6866 /* Load operations must load different registers. */
6867 if ((opcode
->opcode
& (1 << 22))
6868 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6869 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6873 /* It is unpredictable if the destination and status registers are the
6875 if ((aarch64_get_operand_class (opnds
[0].type
)
6876 == AARCH64_OPND_CLASS_INT_REG
)
6877 && (aarch64_get_operand_class (opnds
[1].type
)
6878 == AARCH64_OPND_CLASS_INT_REG
)
6879 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6880 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6881 as_warn (_("unpredictable: identical transfer and status registers"
6893 force_automatic_sequence_close (void)
6895 if (now_instr_sequence
.instr
)
6897 as_warn (_("previous `%s' sequence has not been closed"),
6898 now_instr_sequence
.instr
->opcode
->name
);
6899 init_insn_sequence (NULL
, &now_instr_sequence
);
6903 /* A wrapper function to interface with libopcodes on encoding and
6904 record the error message if there is any.
6906 Return TRUE on success; otherwise return FALSE. */
6909 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6912 aarch64_operand_error error_info
;
6913 memset (&error_info
, '\0', sizeof (error_info
));
6914 error_info
.kind
= AARCH64_OPDE_NIL
;
6915 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6916 && !error_info
.non_fatal
)
6919 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6920 record_operand_error_info (opcode
, &error_info
);
6921 return error_info
.non_fatal
;
6924 #ifdef DEBUG_AARCH64
6926 dump_opcode_operands (const aarch64_opcode
*opcode
)
6929 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6931 aarch64_verbose ("\t\t opnd%d: %s", i
,
6932 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6933 ? aarch64_get_operand_name (opcode
->operands
[i
])
6934 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6938 #endif /* DEBUG_AARCH64 */
6940 /* This is the guts of the machine-dependent assembler. STR points to a
6941 machine dependent instruction. This function is supposed to emit
6942 the frags/bytes it assembles to. */
6945 md_assemble (char *str
)
6948 templates
*template;
6949 aarch64_opcode
*opcode
;
6950 aarch64_inst
*inst_base
;
6951 unsigned saved_cond
;
6953 /* Align the previous label if needed. */
6954 if (last_label_seen
!= NULL
)
6956 symbol_set_frag (last_label_seen
, frag_now
);
6957 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6958 S_SET_SEGMENT (last_label_seen
, now_seg
);
6961 /* Update the current insn_sequence from the segment. */
6962 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6964 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6966 DEBUG_TRACE ("\n\n");
6967 DEBUG_TRACE ("==============================");
6968 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6970 template = opcode_lookup (&p
);
6973 /* It wasn't an instruction, but it might be a register alias of
6974 the form alias .req reg directive. */
6975 if (!create_register_alias (str
, p
))
6976 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6981 skip_whitespace (p
);
6984 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6985 get_mnemonic_name (str
), str
);
6989 init_operand_error_report ();
6991 /* Sections are assumed to start aligned. In executable section, there is no
6992 MAP_DATA symbol pending. So we only align the address during
6993 MAP_DATA --> MAP_INSN transition.
6994 For other sections, this is not guaranteed. */
6995 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6996 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6997 frag_align_code (2, 0);
6999 saved_cond
= inst
.cond
;
7000 reset_aarch64_instruction (&inst
);
7001 inst
.cond
= saved_cond
;
7003 /* Iterate through all opcode entries with the same mnemonic name. */
7006 opcode
= template->opcode
;
7008 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7009 #ifdef DEBUG_AARCH64
7011 dump_opcode_operands (opcode
);
7012 #endif /* DEBUG_AARCH64 */
7014 mapping_state (MAP_INSN
);
7016 inst_base
= &inst
.base
;
7017 inst_base
->opcode
= opcode
;
7019 /* Truly conditionally executed instructions, e.g. b.cond. */
7020 if (opcode
->flags
& F_COND
)
7022 gas_assert (inst
.cond
!= COND_ALWAYS
);
7023 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7024 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7026 else if (inst
.cond
!= COND_ALWAYS
)
7028 /* It shouldn't arrive here, where the assembly looks like a
7029 conditional instruction but the found opcode is unconditional. */
7034 if (parse_operands (p
, opcode
)
7035 && programmer_friendly_fixup (&inst
)
7036 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7038 /* Check that this instruction is supported for this CPU. */
7039 if (!opcode
->avariant
7040 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7042 as_bad (_("selected processor does not support `%s'"), str
);
7046 warn_unpredictable_ldst (&inst
, str
);
7048 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7049 || !inst
.reloc
.need_libopcodes_p
)
7053 /* If there is relocation generated for the instruction,
7054 store the instruction information for the future fix-up. */
7055 struct aarch64_inst
*copy
;
7056 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7057 copy
= XNEW (struct aarch64_inst
);
7058 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7062 /* Issue non-fatal messages if any. */
7063 output_operand_error_report (str
, TRUE
);
7067 template = template->next
;
7068 if (template != NULL
)
7070 reset_aarch64_instruction (&inst
);
7071 inst
.cond
= saved_cond
;
7074 while (template != NULL
);
7076 /* Issue the error messages if any. */
7077 output_operand_error_report (str
, FALSE
);
7080 /* Various frobbings of labels and their addresses. */
7083 aarch64_start_line_hook (void)
7085 last_label_seen
= NULL
;
7089 aarch64_frob_label (symbolS
* sym
)
7091 last_label_seen
= sym
;
7093 dwarf2_emit_label (sym
);
7097 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7099 /* Check to see if we have a block to close. */
7100 force_automatic_sequence_close ();
7104 aarch64_data_in_code (void)
7106 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7108 *input_line_pointer
= '/';
7109 input_line_pointer
+= 5;
7110 *input_line_pointer
= 0;
7118 aarch64_canonicalize_symbol_name (char *name
)
7122 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7123 *(name
+ len
- 5) = 0;
7128 /* Table of all register names defined by default. The user can
7129 define additional names with .req. Note that all register names
7130 should appear in both upper and lowercase variants. Some registers
7131 also have mixed-case names. */
7133 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7134 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7135 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7136 #define REGSET16(p,t) \
7137 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7138 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7139 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7140 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7141 #define REGSET31(p,t) \
7143 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7144 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7145 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7146 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7147 #define REGSET(p,t) \
7148 REGSET31(p,t), REGNUM(p,31,t)
7150 /* These go into aarch64_reg_hsh hash-table. */
7151 static const reg_entry reg_names
[] = {
7152 /* Integer registers. */
7153 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7154 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7156 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7157 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7158 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7159 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7160 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7161 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7163 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7164 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7166 /* Floating-point single precision registers. */
7167 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7169 /* Floating-point double precision registers. */
7170 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7172 /* Floating-point half precision registers. */
7173 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7175 /* Floating-point byte precision registers. */
7176 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7178 /* Floating-point quad precision registers. */
7179 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7181 /* FP/SIMD registers. */
7182 REGSET (v
, VN
), REGSET (V
, VN
),
7184 /* SVE vector registers. */
7185 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7187 /* SVE predicate registers. */
7188 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7206 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7207 static const asm_nzcv nzcv_names
[] = {
7208 {"nzcv", B (n
, z
, c
, v
)},
7209 {"nzcV", B (n
, z
, c
, V
)},
7210 {"nzCv", B (n
, z
, C
, v
)},
7211 {"nzCV", B (n
, z
, C
, V
)},
7212 {"nZcv", B (n
, Z
, c
, v
)},
7213 {"nZcV", B (n
, Z
, c
, V
)},
7214 {"nZCv", B (n
, Z
, C
, v
)},
7215 {"nZCV", B (n
, Z
, C
, V
)},
7216 {"Nzcv", B (N
, z
, c
, v
)},
7217 {"NzcV", B (N
, z
, c
, V
)},
7218 {"NzCv", B (N
, z
, C
, v
)},
7219 {"NzCV", B (N
, z
, C
, V
)},
7220 {"NZcv", B (N
, Z
, c
, v
)},
7221 {"NZcV", B (N
, Z
, c
, V
)},
7222 {"NZCv", B (N
, Z
, C
, v
)},
7223 {"NZCV", B (N
, Z
, C
, V
)}
7236 /* MD interface: bits in the object file. */
7238 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7239 for use in the a.out file, and stores them in the array pointed to by buf.
7240 This knows about the endian-ness of the target machine and does
7241 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7242 2 (short) and 4 (long) Floating numbers are put out as a series of
7243 LITTLENUMS (shorts, here at least). */
7246 md_number_to_chars (char *buf
, valueT val
, int n
)
7248 if (target_big_endian
)
7249 number_to_chars_bigendian (buf
, val
, n
);
7251 number_to_chars_littleendian (buf
, val
, n
);
7254 /* MD interface: Sections. */
7256 /* Estimate the size of a frag before relaxing. Assume everything fits in
7260 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7266 /* Round up a section size to the appropriate boundary. */
7269 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7274 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7275 of an rs_align_code fragment.
7277 Here we fill the frag with the appropriate info for padding the
7278 output stream. The resulting frag will consist of a fixed (fr_fix)
7279 and of a repeating (fr_var) part.
7281 The fixed content is always emitted before the repeating content and
7282 these two parts are used as follows in constructing the output:
7283 - the fixed part will be used to align to a valid instruction word
7284 boundary, in case that we start at a misaligned address; as no
7285 executable instruction can live at the misaligned location, we
7286 simply fill with zeros;
7287 - the variable part will be used to cover the remaining padding and
7288 we fill using the AArch64 NOP instruction.
7290 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7291 enough storage space for up to 3 bytes for padding the back to a valid
7292 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7295 aarch64_handle_align (fragS
* fragP
)
7297 /* NOP = d503201f */
7298 /* AArch64 instructions are always little-endian. */
7299 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7301 int bytes
, fix
, noop_size
;
7304 if (fragP
->fr_type
!= rs_align_code
)
7307 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7308 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7311 gas_assert (fragP
->tc_frag_data
.recorded
);
7314 noop_size
= sizeof (aarch64_noop
);
7316 fix
= bytes
& (noop_size
- 1);
7320 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7324 fragP
->fr_fix
+= fix
;
7328 memcpy (p
, aarch64_noop
, noop_size
);
7329 fragP
->fr_var
= noop_size
;
7332 /* Perform target specific initialisation of a frag.
7333 Note - despite the name this initialisation is not done when the frag
7334 is created, but only when its type is assigned. A frag can be created
7335 and used a long time before its type is set, so beware of assuming that
7336 this initialisation is performed first. */
7340 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7341 int max_chars ATTRIBUTE_UNUSED
)
7345 #else /* OBJ_ELF is defined. */
7347 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7349 /* Record a mapping symbol for alignment frags. We will delete this
7350 later if the alignment ends up empty. */
7351 if (!fragP
->tc_frag_data
.recorded
)
7352 fragP
->tc_frag_data
.recorded
= 1;
7354 /* PR 21809: Do not set a mapping state for debug sections
7355 - it just confuses other tools. */
7356 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7359 switch (fragP
->fr_type
)
7363 mapping_state_2 (MAP_DATA
, max_chars
);
7366 /* PR 20364: We can get alignment frags in code sections,
7367 so do not just assume that we should use the MAP_DATA state. */
7368 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7371 mapping_state_2 (MAP_INSN
, max_chars
);
7378 /* Initialize the DWARF-2 unwind information for this procedure. */
7381 tc_aarch64_frame_initial_instructions (void)
7383 cfi_add_CFA_def_cfa (REG_SP
, 0);
7385 #endif /* OBJ_ELF */
7387 /* Convert REGNAME to a DWARF-2 register number. */
7390 tc_aarch64_regname_to_dw2regnum (char *regname
)
7392 const reg_entry
*reg
= parse_reg (®name
);
7398 case REG_TYPE_SP_32
:
7399 case REG_TYPE_SP_64
:
7409 return reg
->number
+ 64;
7417 /* Implement DWARF2_ADDR_SIZE. */
7420 aarch64_dwarf2_addr_size (void)
7422 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7426 return bfd_arch_bits_per_address (stdoutput
) / 8;
7429 /* MD interface: Symbol and relocation handling. */
7431 /* Return the address within the segment that a PC-relative fixup is
7432 relative to. For AArch64 PC-relative fixups applied to instructions
7433 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7436 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7438 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7440 /* If this is pc-relative and we are going to emit a relocation
7441 then we just want to put out any pipeline compensation that the linker
7442 will need. Otherwise we want to use the calculated base. */
7444 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7445 || aarch64_force_relocation (fixP
)))
7448 /* AArch64 should be consistent for all pc-relative relocations. */
7449 return base
+ AARCH64_PCREL_OFFSET
;
7452 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7453 Otherwise we have no need to default values of symbols. */
7456 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7459 if (name
[0] == '_' && name
[1] == 'G'
7460 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7464 if (symbol_find (name
))
7465 as_bad (_("GOT already in the symbol table"));
7467 GOT_symbol
= symbol_new (name
, undefined_section
,
7468 (valueT
) 0, &zero_address_frag
);
7478 /* Return non-zero if the indicated VALUE has overflowed the maximum
7479 range expressible by a unsigned number with the indicated number of
7483 unsigned_overflow (valueT value
, unsigned bits
)
7486 if (bits
>= sizeof (valueT
) * 8)
7488 lim
= (valueT
) 1 << bits
;
7489 return (value
>= lim
);
7493 /* Return non-zero if the indicated VALUE has overflowed the maximum
7494 range expressible by an signed number with the indicated number of
7498 signed_overflow (offsetT value
, unsigned bits
)
7501 if (bits
>= sizeof (offsetT
) * 8)
7503 lim
= (offsetT
) 1 << (bits
- 1);
7504 return (value
< -lim
|| value
>= lim
);
7507 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7508 unsigned immediate offset load/store instruction, try to encode it as
7509 an unscaled, 9-bit, signed immediate offset load/store instruction.
7510 Return TRUE if it is successful; otherwise return FALSE.
7512 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7513 in response to the standard LDR/STR mnemonics when the immediate offset is
7514 unambiguous, i.e. when it is negative or unaligned. */
7517 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7520 enum aarch64_op new_op
;
7521 const aarch64_opcode
*new_opcode
;
7523 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7525 switch (instr
->opcode
->op
)
7527 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7528 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7529 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7530 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7531 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7532 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7533 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7534 case OP_STR_POS
: new_op
= OP_STUR
; break;
7535 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7536 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7537 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7538 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7539 default: new_op
= OP_NIL
; break;
7542 if (new_op
== OP_NIL
)
7545 new_opcode
= aarch64_get_opcode (new_op
);
7546 gas_assert (new_opcode
!= NULL
);
7548 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7549 instr
->opcode
->op
, new_opcode
->op
);
7551 aarch64_replace_opcode (instr
, new_opcode
);
7553 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7554 qualifier matching may fail because the out-of-date qualifier will
7555 prevent the operand being updated with a new and correct qualifier. */
7556 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7557 AARCH64_OPND_ADDR_SIMM9
);
7558 gas_assert (idx
== 1);
7559 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7561 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7563 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7570 /* Called by fix_insn to fix a MOV immediate alias instruction.
7572 Operand for a generic move immediate instruction, which is an alias
7573 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7574 a 32-bit/64-bit immediate value into general register. An assembler error
7575 shall result if the immediate cannot be created by a single one of these
7576 instructions. If there is a choice, then to ensure reversability an
7577 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7580 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7582 const aarch64_opcode
*opcode
;
7584 /* Need to check if the destination is SP/ZR. The check has to be done
7585 before any aarch64_replace_opcode. */
7586 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7587 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7589 instr
->operands
[1].imm
.value
= value
;
7590 instr
->operands
[1].skip
= 0;
7594 /* Try the MOVZ alias. */
7595 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7596 aarch64_replace_opcode (instr
, opcode
);
7597 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7598 &instr
->value
, NULL
, NULL
, insn_sequence
))
7600 put_aarch64_insn (buf
, instr
->value
);
7603 /* Try the MOVK alias. */
7604 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7605 aarch64_replace_opcode (instr
, opcode
);
7606 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7607 &instr
->value
, NULL
, NULL
, insn_sequence
))
7609 put_aarch64_insn (buf
, instr
->value
);
7614 if (try_mov_bitmask_p
)
7616 /* Try the ORR alias. */
7617 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7618 aarch64_replace_opcode (instr
, opcode
);
7619 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7620 &instr
->value
, NULL
, NULL
, insn_sequence
))
7622 put_aarch64_insn (buf
, instr
->value
);
7627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7628 _("immediate cannot be moved by a single instruction"));
7631 /* An instruction operand which is immediate related may have symbol used
7632 in the assembly, e.g.
7635 .set u32, 0x00ffff00
7637 At the time when the assembly instruction is parsed, a referenced symbol,
7638 like 'u32' in the above example may not have been seen; a fixS is created
7639 in such a case and is handled here after symbols have been resolved.
7640 Instruction is fixed up with VALUE using the information in *FIXP plus
7641 extra information in FLAGS.
7643 This function is called by md_apply_fix to fix up instructions that need
7644 a fix-up described above but does not involve any linker-time relocation. */
7647 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7651 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7652 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7653 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7657 /* Now the instruction is about to be fixed-up, so the operand that
7658 was previously marked as 'ignored' needs to be unmarked in order
7659 to get the encoding done properly. */
7660 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7661 new_inst
->operands
[idx
].skip
= 0;
7664 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7668 case AARCH64_OPND_EXCEPTION
:
7669 if (unsigned_overflow (value
, 16))
7670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7671 _("immediate out of range"));
7672 insn
= get_aarch64_insn (buf
);
7673 insn
|= encode_svc_imm (value
);
7674 put_aarch64_insn (buf
, insn
);
7677 case AARCH64_OPND_AIMM
:
7678 /* ADD or SUB with immediate.
7679 NOTE this assumes we come here with a add/sub shifted reg encoding
7680 3 322|2222|2 2 2 21111 111111
7681 1 098|7654|3 2 1 09876 543210 98765 43210
7682 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7683 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7684 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7685 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7687 3 322|2222|2 2 221111111111
7688 1 098|7654|3 2 109876543210 98765 43210
7689 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7690 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7691 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7692 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7693 Fields sf Rn Rd are already set. */
7694 insn
= get_aarch64_insn (buf
);
7698 insn
= reencode_addsub_switch_add_sub (insn
);
7702 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7703 && unsigned_overflow (value
, 12))
7705 /* Try to shift the value by 12 to make it fit. */
7706 if (((value
>> 12) << 12) == value
7707 && ! unsigned_overflow (value
, 12 + 12))
7710 insn
|= encode_addsub_imm_shift_amount (1);
7714 if (unsigned_overflow (value
, 12))
7715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7716 _("immediate out of range"));
7718 insn
|= encode_addsub_imm (value
);
7720 put_aarch64_insn (buf
, insn
);
7723 case AARCH64_OPND_SIMD_IMM
:
7724 case AARCH64_OPND_SIMD_IMM_SFT
:
7725 case AARCH64_OPND_LIMM
:
7726 /* Bit mask immediate. */
7727 gas_assert (new_inst
!= NULL
);
7728 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7729 new_inst
->operands
[idx
].imm
.value
= value
;
7730 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7731 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7732 put_aarch64_insn (buf
, new_inst
->value
);
7734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7735 _("invalid immediate"));
7738 case AARCH64_OPND_HALF
:
7739 /* 16-bit unsigned immediate. */
7740 if (unsigned_overflow (value
, 16))
7741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7742 _("immediate out of range"));
7743 insn
= get_aarch64_insn (buf
);
7744 insn
|= encode_movw_imm (value
& 0xffff);
7745 put_aarch64_insn (buf
, insn
);
7748 case AARCH64_OPND_IMM_MOV
:
7749 /* Operand for a generic move immediate instruction, which is
7750 an alias instruction that generates a single MOVZ, MOVN or ORR
7751 instruction to loads a 32-bit/64-bit immediate value into general
7752 register. An assembler error shall result if the immediate cannot be
7753 created by a single one of these instructions. If there is a choice,
7754 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7755 and MOVZ or MOVN to ORR. */
7756 gas_assert (new_inst
!= NULL
);
7757 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7760 case AARCH64_OPND_ADDR_SIMM7
:
7761 case AARCH64_OPND_ADDR_SIMM9
:
7762 case AARCH64_OPND_ADDR_SIMM9_2
:
7763 case AARCH64_OPND_ADDR_SIMM10
:
7764 case AARCH64_OPND_ADDR_UIMM12
:
7765 case AARCH64_OPND_ADDR_SIMM11
:
7766 case AARCH64_OPND_ADDR_SIMM13
:
7767 /* Immediate offset in an address. */
7768 insn
= get_aarch64_insn (buf
);
7770 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7771 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7772 || new_inst
->opcode
->operands
[2] == opnd
);
7774 /* Get the index of the address operand. */
7775 if (new_inst
->opcode
->operands
[1] == opnd
)
7776 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7779 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7782 /* Update the resolved offset value. */
7783 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7785 /* Encode/fix-up. */
7786 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7787 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7789 put_aarch64_insn (buf
, new_inst
->value
);
7792 else if (new_inst
->opcode
->iclass
== ldst_pos
7793 && try_to_encode_as_unscaled_ldst (new_inst
))
7795 put_aarch64_insn (buf
, new_inst
->value
);
7799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7800 _("immediate offset out of range"));
7805 as_fatal (_("unhandled operand code %d"), opnd
);
7809 /* Apply a fixup (fixP) to segment data, once it has been determined
7810 by our caller that we have all the info we need to fix it up.
7812 Parameter valP is the pointer to the value of the bits. */
7815 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7817 offsetT value
= *valP
;
7819 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7821 unsigned flags
= fixP
->fx_addnumber
;
7823 DEBUG_TRACE ("\n\n");
7824 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7825 DEBUG_TRACE ("Enter md_apply_fix");
7827 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7829 /* Note whether this will delete the relocation. */
7831 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7834 /* Process the relocations. */
7835 switch (fixP
->fx_r_type
)
7837 case BFD_RELOC_NONE
:
7838 /* This will need to go in the object file. */
7843 case BFD_RELOC_8_PCREL
:
7844 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7845 md_number_to_chars (buf
, value
, 1);
7849 case BFD_RELOC_16_PCREL
:
7850 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7851 md_number_to_chars (buf
, value
, 2);
7855 case BFD_RELOC_32_PCREL
:
7856 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7857 md_number_to_chars (buf
, value
, 4);
7861 case BFD_RELOC_64_PCREL
:
7862 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7863 md_number_to_chars (buf
, value
, 8);
7866 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7867 /* We claim that these fixups have been processed here, even if
7868 in fact we generate an error because we do not have a reloc
7869 for them, so tc_gen_reloc() will reject them. */
7871 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7874 _("undefined symbol %s used as an immediate value"),
7875 S_GET_NAME (fixP
->fx_addsy
));
7876 goto apply_fix_return
;
7878 fix_insn (fixP
, flags
, value
);
7881 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7882 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7886 _("pc-relative load offset not word aligned"));
7887 if (signed_overflow (value
, 21))
7888 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7889 _("pc-relative load offset out of range"));
7890 insn
= get_aarch64_insn (buf
);
7891 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7892 put_aarch64_insn (buf
, insn
);
7896 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7899 if (signed_overflow (value
, 21))
7900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7901 _("pc-relative address offset out of range"));
7902 insn
= get_aarch64_insn (buf
);
7903 insn
|= encode_adr_imm (value
);
7904 put_aarch64_insn (buf
, insn
);
7908 case BFD_RELOC_AARCH64_BRANCH19
:
7909 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7913 _("conditional branch target not word aligned"));
7914 if (signed_overflow (value
, 21))
7915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7916 _("conditional branch out of range"));
7917 insn
= get_aarch64_insn (buf
);
7918 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7919 put_aarch64_insn (buf
, insn
);
7923 case BFD_RELOC_AARCH64_TSTBR14
:
7924 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7928 _("conditional branch target not word aligned"));
7929 if (signed_overflow (value
, 16))
7930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7931 _("conditional branch out of range"));
7932 insn
= get_aarch64_insn (buf
);
7933 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7934 put_aarch64_insn (buf
, insn
);
7938 case BFD_RELOC_AARCH64_CALL26
:
7939 case BFD_RELOC_AARCH64_JUMP26
:
7940 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7944 _("branch target not word aligned"));
7945 if (signed_overflow (value
, 28))
7946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7947 _("branch out of range"));
7948 insn
= get_aarch64_insn (buf
);
7949 insn
|= encode_branch_ofs_26 (value
>> 2);
7950 put_aarch64_insn (buf
, insn
);
7954 case BFD_RELOC_AARCH64_MOVW_G0
:
7955 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7956 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7957 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7958 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7959 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7962 case BFD_RELOC_AARCH64_MOVW_G1
:
7963 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7964 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7965 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7966 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7967 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7970 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7972 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7973 /* Should always be exported to object file, see
7974 aarch64_force_relocation(). */
7975 gas_assert (!fixP
->fx_done
);
7976 gas_assert (seg
->use_rela_p
);
7978 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7980 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7981 /* Should always be exported to object file, see
7982 aarch64_force_relocation(). */
7983 gas_assert (!fixP
->fx_done
);
7984 gas_assert (seg
->use_rela_p
);
7986 case BFD_RELOC_AARCH64_MOVW_G2
:
7987 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7988 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7989 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7990 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7993 case BFD_RELOC_AARCH64_MOVW_G3
:
7994 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7997 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7999 insn
= get_aarch64_insn (buf
);
8003 /* REL signed addend must fit in 16 bits */
8004 if (signed_overflow (value
, 16))
8005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8006 _("offset out of range"));
8010 /* Check for overflow and scale. */
8011 switch (fixP
->fx_r_type
)
8013 case BFD_RELOC_AARCH64_MOVW_G0
:
8014 case BFD_RELOC_AARCH64_MOVW_G1
:
8015 case BFD_RELOC_AARCH64_MOVW_G2
:
8016 case BFD_RELOC_AARCH64_MOVW_G3
:
8017 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8018 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8019 if (unsigned_overflow (value
, scale
+ 16))
8020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8021 _("unsigned value out of range"));
8023 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8024 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8025 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8026 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8027 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8028 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8029 /* NOTE: We can only come here with movz or movn. */
8030 if (signed_overflow (value
, scale
+ 16))
8031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8032 _("signed value out of range"));
8035 /* Force use of MOVN. */
8037 insn
= reencode_movzn_to_movn (insn
);
8041 /* Force use of MOVZ. */
8042 insn
= reencode_movzn_to_movz (insn
);
8046 /* Unchecked relocations. */
8052 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8053 insn
|= encode_movw_imm (value
& 0xffff);
8055 put_aarch64_insn (buf
, insn
);
8059 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8060 fixP
->fx_r_type
= (ilp32_p
8061 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8062 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8063 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8064 /* Should always be exported to object file, see
8065 aarch64_force_relocation(). */
8066 gas_assert (!fixP
->fx_done
);
8067 gas_assert (seg
->use_rela_p
);
8070 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8071 fixP
->fx_r_type
= (ilp32_p
8072 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8073 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8074 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8075 /* Should always be exported to object file, see
8076 aarch64_force_relocation(). */
8077 gas_assert (!fixP
->fx_done
);
8078 gas_assert (seg
->use_rela_p
);
8081 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8082 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8083 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8084 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8085 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8086 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8087 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8088 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8089 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8090 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8091 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8092 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8093 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8094 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8095 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8096 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8097 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8098 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8099 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8100 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8101 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8102 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8103 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8104 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8105 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8106 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8107 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8108 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8109 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8110 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8111 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8112 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8113 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8114 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8115 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8116 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8117 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8118 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8119 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8120 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8121 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8122 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8123 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8124 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8125 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8126 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8127 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8128 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8129 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8130 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8131 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8132 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8133 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8134 /* Should always be exported to object file, see
8135 aarch64_force_relocation(). */
8136 gas_assert (!fixP
->fx_done
);
8137 gas_assert (seg
->use_rela_p
);
8140 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8141 /* Should always be exported to object file, see
8142 aarch64_force_relocation(). */
8143 fixP
->fx_r_type
= (ilp32_p
8144 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8145 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8146 gas_assert (!fixP
->fx_done
);
8147 gas_assert (seg
->use_rela_p
);
8150 case BFD_RELOC_AARCH64_ADD_LO12
:
8151 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8152 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8153 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8154 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8155 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8156 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8157 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8158 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8159 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8160 case BFD_RELOC_AARCH64_LDST128_LO12
:
8161 case BFD_RELOC_AARCH64_LDST16_LO12
:
8162 case BFD_RELOC_AARCH64_LDST32_LO12
:
8163 case BFD_RELOC_AARCH64_LDST64_LO12
:
8164 case BFD_RELOC_AARCH64_LDST8_LO12
:
8165 /* Should always be exported to object file, see
8166 aarch64_force_relocation(). */
8167 gas_assert (!fixP
->fx_done
);
8168 gas_assert (seg
->use_rela_p
);
8171 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8172 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8173 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8176 case BFD_RELOC_UNUSED
:
8177 /* An error will already have been reported. */
8181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8182 _("unexpected %s fixup"),
8183 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8188 /* Free the allocated the struct aarch64_inst.
8189 N.B. currently there are very limited number of fix-up types actually use
8190 this field, so the impact on the performance should be minimal . */
8191 if (fixP
->tc_fix_data
.inst
!= NULL
)
8192 free (fixP
->tc_fix_data
.inst
);
8197 /* Translate internal representation of relocation info to BFD target
8201 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8204 bfd_reloc_code_real_type code
;
8206 reloc
= XNEW (arelent
);
8208 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8209 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8210 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8214 if (section
->use_rela_p
)
8215 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8217 fixp
->fx_offset
= reloc
->address
;
8219 reloc
->addend
= fixp
->fx_offset
;
8221 code
= fixp
->fx_r_type
;
8226 code
= BFD_RELOC_16_PCREL
;
8231 code
= BFD_RELOC_32_PCREL
;
8236 code
= BFD_RELOC_64_PCREL
;
8243 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8244 if (reloc
->howto
== NULL
)
8246 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8248 ("cannot represent %s relocation in this object file format"),
8249 bfd_get_reloc_code_name (code
));
8256 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8259 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8261 bfd_reloc_code_real_type type
;
8265 FIXME: @@ Should look at CPU word size. */
8272 type
= BFD_RELOC_16
;
8275 type
= BFD_RELOC_32
;
8278 type
= BFD_RELOC_64
;
8281 as_bad (_("cannot do %u-byte relocation"), size
);
8282 type
= BFD_RELOC_UNUSED
;
8286 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8290 aarch64_force_relocation (struct fix
*fixp
)
8292 switch (fixp
->fx_r_type
)
8294 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8295 /* Perform these "immediate" internal relocations
8296 even if the symbol is extern or weak. */
8299 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8300 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8301 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8302 /* Pseudo relocs that need to be fixed up according to
8306 case BFD_RELOC_AARCH64_ADD_LO12
:
8307 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8308 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8309 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8310 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8311 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8312 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8313 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8314 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8315 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8316 case BFD_RELOC_AARCH64_LDST128_LO12
:
8317 case BFD_RELOC_AARCH64_LDST16_LO12
:
8318 case BFD_RELOC_AARCH64_LDST32_LO12
:
8319 case BFD_RELOC_AARCH64_LDST64_LO12
:
8320 case BFD_RELOC_AARCH64_LDST8_LO12
:
8321 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8322 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8323 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8324 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8325 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8326 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8327 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8328 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8329 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8330 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8331 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8332 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8333 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8334 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8335 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8336 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8337 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8338 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8339 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8340 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8341 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8342 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8343 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8344 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8345 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8346 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8347 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8348 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8349 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8350 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8351 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8352 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8353 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8354 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8355 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8356 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8357 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8358 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8359 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8360 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8361 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8362 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8363 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8364 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8365 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8366 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8367 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8368 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8369 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8370 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8371 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8372 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8373 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8374 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8375 /* Always leave these relocations for the linker. */
8382 return generic_force_reloc (fixp
);
8387 /* Implement md_after_parse_args. This is the earliest time we need to decide
8388 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8391 aarch64_after_parse_args (void)
8393 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8396 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8397 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8398 aarch64_abi
= AARCH64_ABI_ILP32
;
8400 aarch64_abi
= AARCH64_ABI_LP64
;
8404 elf64_aarch64_target_format (void)
8407 /* FIXME: What to do for ilp32_p ? */
8408 if (target_big_endian
)
8409 return "elf64-bigaarch64-cloudabi";
8411 return "elf64-littleaarch64-cloudabi";
8413 if (target_big_endian
)
8414 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8416 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8421 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8423 elf_frob_symbol (symp
, puntp
);
8427 /* MD interface: Finalization. */
8429 /* A good place to do this, although this was probably not intended
8430 for this kind of use. We need to dump the literal pool before
8431 references are made to a null symbol pointer. */
8434 aarch64_cleanup (void)
8438 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8440 /* Put it at the end of the relevant section. */
8441 subseg_set (pool
->section
, pool
->sub_section
);
8447 /* Remove any excess mapping symbols generated for alignment frags in
8448 SEC. We may have created a mapping symbol before a zero byte
8449 alignment; remove it if there's a mapping symbol after the
8452 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8453 void *dummy ATTRIBUTE_UNUSED
)
8455 segment_info_type
*seginfo
= seg_info (sec
);
8458 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8461 for (fragp
= seginfo
->frchainP
->frch_root
;
8462 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8464 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8465 fragS
*next
= fragp
->fr_next
;
8467 /* Variable-sized frags have been converted to fixed size by
8468 this point. But if this was variable-sized to start with,
8469 there will be a fixed-size frag after it. So don't handle
8471 if (sym
== NULL
|| next
== NULL
)
8474 if (S_GET_VALUE (sym
) < next
->fr_address
)
8475 /* Not at the end of this frag. */
8477 know (S_GET_VALUE (sym
) == next
->fr_address
);
8481 if (next
->tc_frag_data
.first_map
!= NULL
)
8483 /* Next frag starts with a mapping symbol. Discard this
8485 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8489 if (next
->fr_next
== NULL
)
8491 /* This mapping symbol is at the end of the section. Discard
8493 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8494 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8498 /* As long as we have empty frags without any mapping symbols,
8500 /* If the next frag is non-empty and does not start with a
8501 mapping symbol, then this mapping symbol is required. */
8502 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8505 next
= next
->fr_next
;
8507 while (next
!= NULL
);
8512 /* Adjust the symbol table. */
8515 aarch64_adjust_symtab (void)
8518 /* Remove any overlapping mapping symbols generated by alignment frags. */
8519 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8520 /* Now do generic ELF adjustments. */
8521 elf_adjust_symtab ();
8526 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8528 const char *hash_err
;
8530 hash_err
= hash_insert (table
, key
, value
);
8532 printf ("Internal Error: Can't hash %s\n", key
);
8536 fill_instruction_hash_table (void)
8538 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8540 while (opcode
->name
!= NULL
)
8542 templates
*templ
, *new_templ
;
8543 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8545 new_templ
= XNEW (templates
);
8546 new_templ
->opcode
= opcode
;
8547 new_templ
->next
= NULL
;
8550 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8553 new_templ
->next
= templ
->next
;
8554 templ
->next
= new_templ
;
8561 convert_to_upper (char *dst
, const char *src
, size_t num
)
8564 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8565 *dst
= TOUPPER (*src
);
8569 /* Assume STR point to a lower-case string, allocate, convert and return
8570 the corresponding upper-case string. */
8571 static inline const char*
8572 get_upper_str (const char *str
)
8575 size_t len
= strlen (str
);
8576 ret
= XNEWVEC (char, len
+ 1);
8577 convert_to_upper (ret
, str
, len
);
8581 /* MD interface: Initialization. */
8589 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8590 || (aarch64_cond_hsh
= hash_new ()) == NULL
8591 || (aarch64_shift_hsh
= hash_new ()) == NULL
8592 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8593 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8594 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8595 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8596 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8597 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8598 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8599 || (aarch64_reg_hsh
= hash_new ()) == NULL
8600 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8601 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8602 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8603 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8604 as_fatal (_("virtual memory exhausted"));
8606 fill_instruction_hash_table ();
8608 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8609 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8610 (void *) (aarch64_sys_regs
+ i
));
8612 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8613 checked_hash_insert (aarch64_pstatefield_hsh
,
8614 aarch64_pstatefields
[i
].name
,
8615 (void *) (aarch64_pstatefields
+ i
));
8617 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8618 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8619 aarch64_sys_regs_ic
[i
].name
,
8620 (void *) (aarch64_sys_regs_ic
+ i
));
8622 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8623 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8624 aarch64_sys_regs_dc
[i
].name
,
8625 (void *) (aarch64_sys_regs_dc
+ i
));
8627 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8628 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8629 aarch64_sys_regs_at
[i
].name
,
8630 (void *) (aarch64_sys_regs_at
+ i
));
8632 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8633 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8634 aarch64_sys_regs_tlbi
[i
].name
,
8635 (void *) (aarch64_sys_regs_tlbi
+ i
));
8637 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8638 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8639 aarch64_sys_regs_sr
[i
].name
,
8640 (void *) (aarch64_sys_regs_sr
+ i
));
8642 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8643 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8644 (void *) (reg_names
+ i
));
8646 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8647 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8648 (void *) (nzcv_names
+ i
));
8650 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8652 const char *name
= aarch64_operand_modifiers
[i
].name
;
8653 checked_hash_insert (aarch64_shift_hsh
, name
,
8654 (void *) (aarch64_operand_modifiers
+ i
));
8655 /* Also hash the name in the upper case. */
8656 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8657 (void *) (aarch64_operand_modifiers
+ i
));
8660 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8663 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8664 the same condition code. */
8665 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8667 const char *name
= aarch64_conds
[i
].names
[j
];
8670 checked_hash_insert (aarch64_cond_hsh
, name
,
8671 (void *) (aarch64_conds
+ i
));
8672 /* Also hash the name in the upper case. */
8673 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8674 (void *) (aarch64_conds
+ i
));
8678 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8680 const char *name
= aarch64_barrier_options
[i
].name
;
8681 /* Skip xx00 - the unallocated values of option. */
8684 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8685 (void *) (aarch64_barrier_options
+ i
));
8686 /* Also hash the name in the upper case. */
8687 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8688 (void *) (aarch64_barrier_options
+ i
));
8691 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8693 const char* name
= aarch64_prfops
[i
].name
;
8694 /* Skip the unallocated hint encodings. */
8697 checked_hash_insert (aarch64_pldop_hsh
, name
,
8698 (void *) (aarch64_prfops
+ i
));
8699 /* Also hash the name in the upper case. */
8700 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8701 (void *) (aarch64_prfops
+ i
));
8704 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8706 const char* name
= aarch64_hint_options
[i
].name
;
8708 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8709 (void *) (aarch64_hint_options
+ i
));
8710 /* Also hash the name in the upper case. */
8711 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8712 (void *) (aarch64_hint_options
+ i
));
8715 /* Set the cpu variant based on the command-line options. */
8717 mcpu_cpu_opt
= march_cpu_opt
;
8720 mcpu_cpu_opt
= &cpu_default
;
8722 cpu_variant
= *mcpu_cpu_opt
;
8724 /* Record the CPU type. */
8725 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8727 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8730 /* Command line processing. */
8732 const char *md_shortopts
= "m:";
8734 #ifdef AARCH64_BI_ENDIAN
8735 #define OPTION_EB (OPTION_MD_BASE + 0)
8736 #define OPTION_EL (OPTION_MD_BASE + 1)
8738 #if TARGET_BYTES_BIG_ENDIAN
8739 #define OPTION_EB (OPTION_MD_BASE + 0)
8741 #define OPTION_EL (OPTION_MD_BASE + 1)
8745 struct option md_longopts
[] = {
8747 {"EB", no_argument
, NULL
, OPTION_EB
},
8750 {"EL", no_argument
, NULL
, OPTION_EL
},
8752 {NULL
, no_argument
, NULL
, 0}
8755 size_t md_longopts_size
= sizeof (md_longopts
);
8757 struct aarch64_option_table
8759 const char *option
; /* Option name to match. */
8760 const char *help
; /* Help information. */
8761 int *var
; /* Variable to change. */
8762 int value
; /* What to change it to. */
8763 char *deprecated
; /* If non-null, print this message. */
8766 static struct aarch64_option_table aarch64_opts
[] = {
8767 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8768 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8770 #ifdef DEBUG_AARCH64
8771 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8772 #endif /* DEBUG_AARCH64 */
8773 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8775 {"mno-verbose-error", N_("do not output verbose error messages"),
8776 &verbose_error_p
, 0, NULL
},
8777 {NULL
, NULL
, NULL
, 0, NULL
}
8780 struct aarch64_cpu_option_table
8783 const aarch64_feature_set value
;
8784 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8786 const char *canonical_name
;
8789 /* This list should, at a minimum, contain all the cpu names
8790 recognized by GCC. */
8791 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8792 {"all", AARCH64_ANY
, NULL
},
8793 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8794 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8795 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8796 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8797 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8798 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8799 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8800 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8801 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8802 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8803 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8804 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8806 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8807 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8809 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8810 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8812 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8813 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8814 | AARCH64_FEATURE_DOTPROD
8815 | AARCH64_FEATURE_PROFILE
),
8817 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8818 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8819 "Samsung Exynos M1"},
8820 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8821 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8822 | AARCH64_FEATURE_RDMA
),
8824 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8825 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8826 | AARCH64_FEATURE_DOTPROD
8827 | AARCH64_FEATURE_SSBS
),
8829 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8830 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8831 | AARCH64_FEATURE_DOTPROD
8832 | AARCH64_FEATURE_PROFILE
),
8834 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8835 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8836 | AARCH64_FEATURE_RDMA
),
8837 "Qualcomm QDF24XX"},
8838 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8839 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8840 "Qualcomm Saphira"},
8841 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8842 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8844 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8845 AARCH64_FEATURE_CRYPTO
),
8847 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8848 in earlier releases and is superseded by 'xgene1' in all
8850 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8851 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8852 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8853 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8854 {"generic", AARCH64_ARCH_V8
, NULL
},
8856 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8859 struct aarch64_arch_option_table
8862 const aarch64_feature_set value
;
8865 /* This list should, at a minimum, contain all the architecture names
8866 recognized by GCC. */
8867 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8868 {"all", AARCH64_ANY
},
8869 {"armv8-a", AARCH64_ARCH_V8
},
8870 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8871 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8872 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8873 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8874 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8875 {NULL
, AARCH64_ARCH_NONE
}
8878 /* ISA extensions. */
8879 struct aarch64_option_cpu_value_table
8882 const aarch64_feature_set value
;
8883 const aarch64_feature_set require
; /* Feature dependencies. */
8886 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8887 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8889 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8890 | AARCH64_FEATURE_AES
8891 | AARCH64_FEATURE_SHA2
, 0),
8892 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8893 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8895 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8897 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8898 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8899 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8901 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8903 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8905 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8906 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8907 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8908 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8909 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8910 AARCH64_FEATURE (AARCH64_FEATURE_FP
8911 | AARCH64_FEATURE_F16
, 0)},
8912 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8914 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8915 AARCH64_FEATURE (AARCH64_FEATURE_F16
8916 | AARCH64_FEATURE_SIMD
8917 | AARCH64_FEATURE_COMPNUM
, 0)},
8918 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
8920 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8921 AARCH64_FEATURE (AARCH64_FEATURE_F16
8922 | AARCH64_FEATURE_SIMD
, 0)},
8923 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8925 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8927 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8929 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8931 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8933 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8935 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8937 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8938 | AARCH64_FEATURE_SHA3
, 0),
8940 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8942 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8944 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8946 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
8947 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
8948 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
8949 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8950 | AARCH64_FEATURE_SM4
, 0)},
8951 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
8952 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8953 | AARCH64_FEATURE_AES
, 0)},
8954 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
8955 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8956 | AARCH64_FEATURE_SHA3
, 0)},
8957 {"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
8958 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
8959 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8962 struct aarch64_long_option_table
8964 const char *option
; /* Substring to match. */
8965 const char *help
; /* Help information. */
8966 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8967 char *deprecated
; /* If non-null, print this message. */
8970 /* Transitive closure of features depending on set. */
8971 static aarch64_feature_set
8972 aarch64_feature_disable_set (aarch64_feature_set set
)
8974 const struct aarch64_option_cpu_value_table
*opt
;
8975 aarch64_feature_set prev
= 0;
8977 while (prev
!= set
) {
8979 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8980 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8981 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8986 /* Transitive closure of dependencies of set. */
8987 static aarch64_feature_set
8988 aarch64_feature_enable_set (aarch64_feature_set set
)
8990 const struct aarch64_option_cpu_value_table
*opt
;
8991 aarch64_feature_set prev
= 0;
8993 while (prev
!= set
) {
8995 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8996 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8997 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9003 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9004 bfd_boolean ext_only
)
9006 /* We insist on extensions being added before being removed. We achieve
9007 this by using the ADDING_VALUE variable to indicate whether we are
9008 adding an extension (1) or removing it (0) and only allowing it to
9009 change in the order -1 -> 1 -> 0. */
9010 int adding_value
= -1;
9011 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9013 /* Copy the feature set, so that we can modify it. */
9017 while (str
!= NULL
&& *str
!= 0)
9019 const struct aarch64_option_cpu_value_table
*opt
;
9020 const char *ext
= NULL
;
9027 as_bad (_("invalid architectural extension"));
9031 ext
= strchr (++str
, '+');
9037 optlen
= strlen (str
);
9039 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9041 if (adding_value
!= 0)
9046 else if (optlen
> 0)
9048 if (adding_value
== -1)
9050 else if (adding_value
!= 1)
9052 as_bad (_("must specify extensions to add before specifying "
9053 "those to remove"));
9060 as_bad (_("missing architectural extension"));
9064 gas_assert (adding_value
!= -1);
9066 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9067 if (strncmp (opt
->name
, str
, optlen
) == 0)
9069 aarch64_feature_set set
;
9071 /* Add or remove the extension. */
9074 set
= aarch64_feature_enable_set (opt
->value
);
9075 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9079 set
= aarch64_feature_disable_set (opt
->value
);
9080 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9085 if (opt
->name
== NULL
)
9087 as_bad (_("unknown architectural extension `%s'"), str
);
9098 aarch64_parse_cpu (const char *str
)
9100 const struct aarch64_cpu_option_table
*opt
;
9101 const char *ext
= strchr (str
, '+');
9107 optlen
= strlen (str
);
9111 as_bad (_("missing cpu name `%s'"), str
);
9115 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9116 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9118 mcpu_cpu_opt
= &opt
->value
;
9120 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9125 as_bad (_("unknown cpu `%s'"), str
);
9130 aarch64_parse_arch (const char *str
)
9132 const struct aarch64_arch_option_table
*opt
;
9133 const char *ext
= strchr (str
, '+');
9139 optlen
= strlen (str
);
9143 as_bad (_("missing architecture name `%s'"), str
);
9147 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9148 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9150 march_cpu_opt
= &opt
->value
;
9152 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9157 as_bad (_("unknown architecture `%s'\n"), str
);
9162 struct aarch64_option_abi_value_table
9165 enum aarch64_abi_type value
;
9168 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9169 {"ilp32", AARCH64_ABI_ILP32
},
9170 {"lp64", AARCH64_ABI_LP64
},
9174 aarch64_parse_abi (const char *str
)
9180 as_bad (_("missing abi name `%s'"), str
);
9184 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9185 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9187 aarch64_abi
= aarch64_abis
[i
].value
;
9191 as_bad (_("unknown abi `%s'\n"), str
);
9195 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9197 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9198 aarch64_parse_abi
, NULL
},
9199 #endif /* OBJ_ELF */
9200 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9201 aarch64_parse_cpu
, NULL
},
9202 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9203 aarch64_parse_arch
, NULL
},
9204 {NULL
, NULL
, 0, NULL
}
9208 md_parse_option (int c
, const char *arg
)
9210 struct aarch64_option_table
*opt
;
9211 struct aarch64_long_option_table
*lopt
;
9217 target_big_endian
= 1;
9223 target_big_endian
= 0;
9228 /* Listing option. Just ignore these, we don't support additional
9233 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9235 if (c
== opt
->option
[0]
9236 && ((arg
== NULL
&& opt
->option
[1] == 0)
9237 || streq (arg
, opt
->option
+ 1)))
9239 /* If the option is deprecated, tell the user. */
9240 if (opt
->deprecated
!= NULL
)
9241 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9242 arg
? arg
: "", _(opt
->deprecated
));
9244 if (opt
->var
!= NULL
)
9245 *opt
->var
= opt
->value
;
9251 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9253 /* These options are expected to have an argument. */
9254 if (c
== lopt
->option
[0]
9256 && strncmp (arg
, lopt
->option
+ 1,
9257 strlen (lopt
->option
+ 1)) == 0)
9259 /* If the option is deprecated, tell the user. */
9260 if (lopt
->deprecated
!= NULL
)
9261 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9262 _(lopt
->deprecated
));
9264 /* Call the sup-option parser. */
9265 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9276 md_show_usage (FILE * fp
)
9278 struct aarch64_option_table
*opt
;
9279 struct aarch64_long_option_table
*lopt
;
9281 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9283 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9284 if (opt
->help
!= NULL
)
9285 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9287 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9288 if (lopt
->help
!= NULL
)
9289 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9293 -EB assemble code for a big-endian cpu\n"));
9298 -EL assemble code for a little-endian cpu\n"));
9302 /* Parse a .cpu directive. */
9305 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9307 const struct aarch64_cpu_option_table
*opt
;
9313 name
= input_line_pointer
;
9314 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9315 input_line_pointer
++;
9316 saved_char
= *input_line_pointer
;
9317 *input_line_pointer
= 0;
9319 ext
= strchr (name
, '+');
9322 optlen
= ext
- name
;
9324 optlen
= strlen (name
);
9326 /* Skip the first "all" entry. */
9327 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9328 if (strlen (opt
->name
) == optlen
9329 && strncmp (name
, opt
->name
, optlen
) == 0)
9331 mcpu_cpu_opt
= &opt
->value
;
9333 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9336 cpu_variant
= *mcpu_cpu_opt
;
9338 *input_line_pointer
= saved_char
;
9339 demand_empty_rest_of_line ();
9342 as_bad (_("unknown cpu `%s'"), name
);
9343 *input_line_pointer
= saved_char
;
9344 ignore_rest_of_line ();
9348 /* Parse a .arch directive. */
9351 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9353 const struct aarch64_arch_option_table
*opt
;
9359 name
= input_line_pointer
;
9360 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9361 input_line_pointer
++;
9362 saved_char
= *input_line_pointer
;
9363 *input_line_pointer
= 0;
9365 ext
= strchr (name
, '+');
9368 optlen
= ext
- name
;
9370 optlen
= strlen (name
);
9372 /* Skip the first "all" entry. */
9373 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9374 if (strlen (opt
->name
) == optlen
9375 && strncmp (name
, opt
->name
, optlen
) == 0)
9377 mcpu_cpu_opt
= &opt
->value
;
9379 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9382 cpu_variant
= *mcpu_cpu_opt
;
9384 *input_line_pointer
= saved_char
;
9385 demand_empty_rest_of_line ();
9389 as_bad (_("unknown architecture `%s'\n"), name
);
9390 *input_line_pointer
= saved_char
;
9391 ignore_rest_of_line ();
9394 /* Parse a .arch_extension directive. */
9397 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9400 char *ext
= input_line_pointer
;;
9402 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9403 input_line_pointer
++;
9404 saved_char
= *input_line_pointer
;
9405 *input_line_pointer
= 0;
9407 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9410 cpu_variant
= *mcpu_cpu_opt
;
9412 *input_line_pointer
= saved_char
;
9413 demand_empty_rest_of_line ();
9416 /* Copy symbol information. */
9419 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9421 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);