1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
288 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
292 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
293 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: same, plus SVE registers. */ \
296 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
299 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
300 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
302 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
306 /* Typecheck: any [BHSDQ]P FP. */ \
307 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
308 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
309 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
310 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
312 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
313 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
314 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
315 be used for SVE instructions, since Zn and Pn are valid symbols \
316 in other contexts. */ \
317 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
322 | REG_TYPE(ZN) | REG_TYPE(PN)) \
323 /* Any integer register; used for error messages only. */ \
324 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
326 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
327 /* Pseudo type to mark the end of the enumerator sequence. */ \
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
332 #undef MULTI_REG_TYPE
333 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
335 /* Register type enumerators. */
336 typedef enum aarch64_reg_type_
338 /* A list of REG_TYPE_*. */
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
345 #define REG_TYPE(T) (1 << REG_TYPE_##T)
346 #undef MULTI_REG_TYPE
347 #define MULTI_REG_TYPE(T,V) V,
349 /* Structure for a hash table entry for a register. */
353 unsigned char number
;
354 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
355 unsigned char builtin
;
358 /* Values indexed by aarch64_reg_type to assist the type checking. */
359 static const unsigned reg_type_masks
[] =
364 #undef BASIC_REG_TYPE
366 #undef MULTI_REG_TYPE
367 #undef AARCH64_REG_TYPES
369 /* Diagnostics used when we don't get a register of the expected type.
370 Note: this has to synchronized with aarch64_reg_type definitions
373 get_reg_expected_msg (aarch64_reg_type reg_type
)
380 msg
= N_("integer 32-bit register expected");
383 msg
= N_("integer 64-bit register expected");
386 msg
= N_("integer register expected");
388 case REG_TYPE_R64_SP
:
389 msg
= N_("64-bit integer or SP register expected");
391 case REG_TYPE_SVE_BASE
:
392 msg
= N_("base register expected");
395 msg
= N_("integer or zero register expected");
397 case REG_TYPE_SVE_OFFSET
:
398 msg
= N_("offset register expected");
401 msg
= N_("integer or SP register expected");
403 case REG_TYPE_R_Z_SP
:
404 msg
= N_("integer, zero or SP register expected");
407 msg
= N_("8-bit SIMD scalar register expected");
410 msg
= N_("16-bit SIMD scalar or floating-point half precision "
411 "register expected");
414 msg
= N_("32-bit SIMD scalar or floating-point single precision "
415 "register expected");
418 msg
= N_("64-bit SIMD scalar or floating-point double precision "
419 "register expected");
422 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
423 "register expected");
425 case REG_TYPE_R_Z_BHSDQ_V
:
426 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
427 msg
= N_("register expected");
429 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
430 msg
= N_("SIMD scalar or floating-point register expected");
432 case REG_TYPE_VN
: /* any V reg */
433 msg
= N_("vector register expected");
436 msg
= N_("SVE vector register expected");
439 msg
= N_("SVE predicate register expected");
442 as_fatal (_("invalid register type %d"), reg_type
);
447 /* Some well known registers that we refer to directly elsewhere. */
451 /* Instructions take 4 bytes in the object file. */
454 static struct hash_control
*aarch64_ops_hsh
;
455 static struct hash_control
*aarch64_cond_hsh
;
456 static struct hash_control
*aarch64_shift_hsh
;
457 static struct hash_control
*aarch64_sys_regs_hsh
;
458 static struct hash_control
*aarch64_pstatefield_hsh
;
459 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
460 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
461 static struct hash_control
*aarch64_sys_regs_at_hsh
;
462 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
463 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
464 static struct hash_control
*aarch64_reg_hsh
;
465 static struct hash_control
*aarch64_barrier_opt_hsh
;
466 static struct hash_control
*aarch64_nzcv_hsh
;
467 static struct hash_control
*aarch64_pldop_hsh
;
468 static struct hash_control
*aarch64_hint_opt_hsh
;
470 /* Stuff needed to resolve the label ambiguity
479 static symbolS
*last_label_seen
;
481 /* Literal pool structure. Held on a per-section
482 and per-sub-section basis. */
484 #define MAX_LITERAL_POOL_SIZE 1024
485 typedef struct literal_expression
488 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
489 LITTLENUM_TYPE
* bignum
;
490 } literal_expression
;
492 typedef struct literal_pool
494 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
495 unsigned int next_free_entry
;
501 struct literal_pool
*next
;
504 /* Pointer to a linked list of literal pools. */
505 static literal_pool
*list_of_pools
= NULL
;
509 /* This array holds the chars that always start a comment. If the
510 pre-processor is disabled, these aren't very useful. */
511 const char comment_chars
[] = "";
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output. */
516 /* Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output. */
519 /* Also note that comments like this one will always work. */
520 const char line_comment_chars
[] = "#";
522 const char line_separator_chars
[] = ";";
524 /* Chars that can be used to separate mant
525 from exp in floating point numbers. */
526 const char EXP_CHARS
[] = "eE";
528 /* Chars that mean this number is a floating point constant. */
532 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
534 /* Prefix character that indicates the start of an immediate value. */
535 #define is_immediate_prefix(C) ((C) == '#')
537 /* Separator character handling. */
539 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
541 static inline bfd_boolean
542 skip_past_char (char **str
, char c
)
553 #define skip_past_comma(str) skip_past_char (str, ',')
555 /* Arithmetic expressions (possibly involving symbols). */
557 static bfd_boolean in_my_get_expression_p
= FALSE
;
559 /* Third argument to my_get_expression. */
560 #define GE_NO_PREFIX 0
561 #define GE_OPT_PREFIX 1
563 /* Return TRUE if the string pointed by *STR is successfully parsed
564 as an valid expression; *EP will be filled with the information of
565 such an expression. Otherwise return FALSE. */
568 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
573 int prefix_present_p
= 0;
580 if (is_immediate_prefix (**str
))
583 prefix_present_p
= 1;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_my_get_expression_p
= TRUE
;
595 seg
= expression (ep
);
596 in_my_get_expression_p
= FALSE
;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present_p
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
&& seg
!= undefined_section
)
616 set_syntax_error (_("bad segment"));
617 *str
= input_line_pointer
;
618 input_line_pointer
= save_in
;
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
630 /* Turn a string in input_line_pointer into a floating point constant
631 of type TYPE, and store the appropriate bytes in *LITP. The number
632 of LITTLENUMS emitted is stored in *SIZEP. An error message is
633 returned, or NULL on OK. */
636 md_atof (int type
, char *litP
, int *sizeP
)
638 /* If this is a bfloat16 type, then parse it slightly differently -
639 as it does not follow the IEEE standard exactly. */
643 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
644 FLONUM_TYPE generic_float
;
646 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
649 input_line_pointer
= t
;
651 return _("invalid floating point number");
653 switch (generic_float
.sign
)
666 /* bfloat16 has two types of NaN - quiet and signalling.
667 Quiet NaN has bit[6] == 1 && faction != 0, whereas
668 signalling Nan's have bit[0] == 0 && fraction != 0.
669 Chose this specific encoding as it is the same form
670 as used by other IEEE 754 encodings in GAS. */
681 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
686 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
689 /* We handle all bad expressions here, so that we can report the faulty
690 instruction in the error message. */
692 md_operand (expressionS
* exp
)
694 if (in_my_get_expression_p
)
695 exp
->X_op
= O_illegal
;
698 /* Immediate values. */
700 /* Errors may be set multiple times during parsing or bit encoding
701 (particularly in the Neon bits), but usually the earliest error which is set
702 will be the most meaningful. Avoid overwriting it with later (cascading)
703 errors by calling this function. */
706 first_error (const char *error
)
709 set_syntax_error (error
);
712 /* Similar to first_error, but this function accepts formatted error
715 first_error_fmt (const char *format
, ...)
720 /* N.B. this single buffer will not cause error messages for different
721 instructions to pollute each other; this is because at the end of
722 processing of each assembly line, error message if any will be
723 collected by as_bad. */
724 static char buffer
[size
];
728 int ret ATTRIBUTE_UNUSED
;
729 va_start (args
, format
);
730 ret
= vsnprintf (buffer
, size
, format
, args
);
731 know (ret
<= size
- 1 && ret
>= 0);
733 set_syntax_error (buffer
);
737 /* Register parsing. */
739 /* Generic register parser which is called by other specialized
741 CCP points to what should be the beginning of a register name.
742 If it is indeed a valid register name, advance CCP over it and
743 return the reg_entry structure; otherwise return NULL.
744 It does not issue diagnostics. */
747 parse_reg (char **ccp
)
753 #ifdef REGISTER_PREFIX
754 if (*start
!= REGISTER_PREFIX
)
760 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
765 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
767 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
776 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
779 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
781 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
784 /* Try to parse a base or offset register. Allow SVE base and offset
785 registers if REG_TYPE includes SVE registers. Return the register
786 entry on success, setting *QUALIFIER to the register qualifier.
787 Return null otherwise.
789 Note that this function does not issue any diagnostics. */
791 static const reg_entry
*
792 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
793 aarch64_opnd_qualifier_t
*qualifier
)
796 const reg_entry
*reg
= parse_reg (&str
);
806 *qualifier
= AARCH64_OPND_QLF_W
;
812 *qualifier
= AARCH64_OPND_QLF_X
;
816 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
819 switch (TOLOWER (str
[1]))
822 *qualifier
= AARCH64_OPND_QLF_S_S
;
825 *qualifier
= AARCH64_OPND_QLF_S_D
;
842 /* Try to parse a base or offset register. Return the register entry
843 on success, setting *QUALIFIER to the register qualifier. Return null
846 Note that this function does not issue any diagnostics. */
848 static const reg_entry
*
849 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
851 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
854 /* Parse the qualifier of a vector register or vector element of type
855 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
856 succeeds; otherwise return FALSE.
858 Accept only one occurrence of:
859 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
862 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
863 struct vector_type_el
*parsed_type
, char **str
)
867 unsigned element_size
;
868 enum vector_el_type type
;
871 gas_assert (*ptr
== '.');
874 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
879 width
= strtoul (ptr
, &ptr
, 10);
880 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
882 first_error_fmt (_("bad size %d in vector width specifier"), width
);
887 switch (TOLOWER (*ptr
))
906 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
915 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
917 first_error (_("missing element size"));
920 if (width
!= 0 && width
* element_size
!= 64
921 && width
* element_size
!= 128
922 && !(width
== 2 && element_size
== 16)
923 && !(width
== 4 && element_size
== 8))
926 ("invalid element size %d and vector size combination %c"),
932 parsed_type
->type
= type
;
933 parsed_type
->width
= width
;
940 /* *STR contains an SVE zero/merge predication suffix. Parse it into
941 *PARSED_TYPE and point *STR at the end of the suffix. */
944 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
949 gas_assert (*ptr
== '/');
951 switch (TOLOWER (*ptr
))
954 parsed_type
->type
= NT_zero
;
957 parsed_type
->type
= NT_merge
;
960 if (*ptr
!= '\0' && *ptr
!= ',')
961 first_error_fmt (_("unexpected character `%c' in predication type"),
964 first_error (_("missing predication type"));
967 parsed_type
->width
= 0;
972 /* Parse a register of the type TYPE.
974 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
975 name or the parsed register is not of TYPE.
977 Otherwise return the register number, and optionally fill in the actual
978 type of the register in *RTYPE when multiple alternatives were given, and
979 return the register shape and element index information in *TYPEINFO.
981 IN_REG_LIST should be set with TRUE if the caller is parsing a register
985 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
986 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
989 const reg_entry
*reg
= parse_reg (&str
);
990 struct vector_type_el atype
;
991 struct vector_type_el parsetype
;
992 bfd_boolean is_typed_vecreg
= FALSE
;
995 atype
.type
= NT_invtype
;
1003 set_default_error ();
1007 if (! aarch64_check_reg_type (reg
, type
))
1009 DEBUG_TRACE ("reg type check failed");
1010 set_default_error ();
1015 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1016 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1020 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1025 if (!parse_predication_for_operand (&parsetype
, &str
))
1029 /* Register if of the form Vn.[bhsdq]. */
1030 is_typed_vecreg
= TRUE
;
1032 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1034 /* The width is always variable; we don't allow an integer width
1036 gas_assert (parsetype
.width
== 0);
1037 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1039 else if (parsetype
.width
== 0)
1040 /* Expect index. In the new scheme we cannot have
1041 Vn.[bhsdq] represent a scalar. Therefore any
1042 Vn.[bhsdq] should have an index following it.
1043 Except in reglists of course. */
1044 atype
.defined
|= NTA_HASINDEX
;
1046 atype
.defined
|= NTA_HASTYPE
;
1048 atype
.type
= parsetype
.type
;
1049 atype
.width
= parsetype
.width
;
1052 if (skip_past_char (&str
, '['))
1056 /* Reject Sn[index] syntax. */
1057 if (!is_typed_vecreg
)
1059 first_error (_("this type of register can't be indexed"));
1065 first_error (_("index not allowed inside register list"));
1069 atype
.defined
|= NTA_HASINDEX
;
1071 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1073 if (exp
.X_op
!= O_constant
)
1075 first_error (_("constant expression required"));
1079 if (! skip_past_char (&str
, ']'))
1082 atype
.index
= exp
.X_add_number
;
1084 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1086 /* Indexed vector register expected. */
1087 first_error (_("indexed vector register expected"));
1091 /* A vector reg Vn should be typed or indexed. */
1092 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1094 first_error (_("invalid use of vector register"));
1110 Return the register number on success; return PARSE_FAIL otherwise.
1112 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1113 the register (e.g. NEON double or quad reg when either has been requested).
1115 If this is a NEON vector register with additional type information, fill
1116 in the struct pointed to by VECTYPE (if non-NULL).
1118 This parser does not handle register list. */
1121 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1122 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1124 struct vector_type_el atype
;
1126 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1127 /*in_reg_list= */ FALSE
);
1129 if (reg
== PARSE_FAIL
)
1140 static inline bfd_boolean
1141 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1145 && e1
.defined
== e2
.defined
1146 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1149 /* This function parses a list of vector registers of type TYPE.
1150 On success, it returns the parsed register list information in the
1151 following encoded format:
1153 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1154 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1156 The information of the register shape and/or index is returned in
1159 It returns PARSE_FAIL if the register list is invalid.
1161 The list contains one to four registers.
1162 Each register can be one of:
1165 All <T> should be identical.
1166 All <index> should be identical.
1167 There are restrictions on <Vt> numbers which are checked later
1168 (by reg_list_valid_p). */
1171 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1172 struct vector_type_el
*vectype
)
1176 struct vector_type_el typeinfo
, typeinfo_first
;
1181 bfd_boolean error
= FALSE
;
1182 bfd_boolean expect_index
= FALSE
;
1186 set_syntax_error (_("expecting {"));
1192 typeinfo_first
.defined
= 0;
1193 typeinfo_first
.type
= NT_invtype
;
1194 typeinfo_first
.width
= -1;
1195 typeinfo_first
.index
= 0;
1204 str
++; /* skip over '-' */
1207 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1208 /*in_reg_list= */ TRUE
);
1209 if (val
== PARSE_FAIL
)
1211 set_first_syntax_error (_("invalid vector register in list"));
1215 /* reject [bhsd]n */
1216 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1218 set_first_syntax_error (_("invalid scalar register in list"));
1223 if (typeinfo
.defined
& NTA_HASINDEX
)
1224 expect_index
= TRUE
;
1228 if (val
< val_range
)
1230 set_first_syntax_error
1231 (_("invalid range in vector register list"));
1240 typeinfo_first
= typeinfo
;
1241 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1243 set_first_syntax_error
1244 (_("type mismatch in vector register list"));
1249 for (i
= val_range
; i
<= val
; i
++)
1251 ret_val
|= i
<< (5 * nb_regs
);
1256 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1258 skip_whitespace (str
);
1261 set_first_syntax_error (_("end of vector register list not found"));
1266 skip_whitespace (str
);
1270 if (skip_past_char (&str
, '['))
1274 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1275 if (exp
.X_op
!= O_constant
)
1277 set_first_syntax_error (_("constant expression required."));
1280 if (! skip_past_char (&str
, ']'))
1283 typeinfo_first
.index
= exp
.X_add_number
;
1287 set_first_syntax_error (_("expected index"));
1294 set_first_syntax_error (_("too many registers in vector register list"));
1297 else if (nb_regs
== 0)
1299 set_first_syntax_error (_("empty vector register list"));
1305 *vectype
= typeinfo_first
;
1307 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1310 /* Directives: register aliases. */
1313 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1318 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1321 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1324 /* Only warn about a redefinition if it's not defined as the
1326 else if (new->number
!= number
|| new->type
!= type
)
1327 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1332 name
= xstrdup (str
);
1333 new = XNEW (reg_entry
);
1336 new->number
= number
;
1338 new->builtin
= FALSE
;
1340 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1346 /* Look for the .req directive. This is of the form:
1348 new_register_name .req existing_register_name
1350 If we find one, or if it looks sufficiently like one that we want to
1351 handle any error here, return TRUE. Otherwise return FALSE. */
1354 create_register_alias (char *newname
, char *p
)
1356 const reg_entry
*old
;
1357 char *oldname
, *nbuf
;
1360 /* The input scrubber ensures that whitespace after the mnemonic is
1361 collapsed to single spaces. */
1363 if (strncmp (oldname
, " .req ", 6) != 0)
1367 if (*oldname
== '\0')
1370 old
= hash_find (aarch64_reg_hsh
, oldname
);
1373 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1377 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1378 the desired alias name, and p points to its end. If not, then
1379 the desired alias name is in the global original_case_string. */
1380 #ifdef TC_CASE_SENSITIVE
1383 newname
= original_case_string
;
1384 nlen
= strlen (newname
);
1387 nbuf
= xmemdup0 (newname
, nlen
);
1389 /* Create aliases under the new name as stated; an all-lowercase
1390 version of the new name; and an all-uppercase version of the new
1392 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1394 for (p
= nbuf
; *p
; p
++)
1397 if (strncmp (nbuf
, newname
, nlen
))
1399 /* If this attempt to create an additional alias fails, do not bother
1400 trying to create the all-lower case alias. We will fail and issue
1401 a second, duplicate error message. This situation arises when the
1402 programmer does something like:
1405 The second .req creates the "Foo" alias but then fails to create
1406 the artificial FOO alias because it has already been created by the
1408 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1415 for (p
= nbuf
; *p
; p
++)
1418 if (strncmp (nbuf
, newname
, nlen
))
1419 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1426 /* Should never be called, as .req goes between the alias and the
1427 register name, not at the beginning of the line. */
1429 s_req (int a ATTRIBUTE_UNUSED
)
1431 as_bad (_("invalid syntax for .req directive"));
1434 /* The .unreq directive deletes an alias which was previously defined
1435 by .req. For example:
1441 s_unreq (int a ATTRIBUTE_UNUSED
)
1446 name
= input_line_pointer
;
1448 while (*input_line_pointer
!= 0
1449 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1450 ++input_line_pointer
;
1452 saved_char
= *input_line_pointer
;
1453 *input_line_pointer
= 0;
1456 as_bad (_("invalid syntax for .unreq directive"));
1459 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1462 as_bad (_("unknown register alias '%s'"), name
);
1463 else if (reg
->builtin
)
1464 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1471 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1472 free ((char *) reg
->name
);
1475 /* Also locate the all upper case and all lower case versions.
1476 Do not complain if we cannot find one or the other as it
1477 was probably deleted above. */
1479 nbuf
= strdup (name
);
1480 for (p
= nbuf
; *p
; p
++)
1482 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1485 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1486 free ((char *) reg
->name
);
1490 for (p
= nbuf
; *p
; p
++)
1492 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1495 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1496 free ((char *) reg
->name
);
1504 *input_line_pointer
= saved_char
;
1505 demand_empty_rest_of_line ();
1508 /* Directives: Instruction set selection. */
1511 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1512 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1513 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1514 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1516 /* Create a new mapping symbol for the transition to STATE. */
1519 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1522 const char *symname
;
1529 type
= BSF_NO_FLAGS
;
1533 type
= BSF_NO_FLAGS
;
1539 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1540 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1542 /* Save the mapping symbols for future reference. Also check that
1543 we do not place two mapping symbols at the same offset within a
1544 frag. We'll handle overlap between frags in
1545 check_mapping_symbols.
1547 If .fill or other data filling directive generates zero sized data,
1548 the mapping symbol for the following code will have the same value
1549 as the one generated for the data filling directive. In this case,
1550 we replace the old symbol with the new one at the same address. */
1553 if (frag
->tc_frag_data
.first_map
!= NULL
)
1555 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1556 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1559 frag
->tc_frag_data
.first_map
= symbolP
;
1561 if (frag
->tc_frag_data
.last_map
!= NULL
)
1563 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1564 S_GET_VALUE (symbolP
));
1565 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1566 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1569 frag
->tc_frag_data
.last_map
= symbolP
;
1572 /* We must sometimes convert a region marked as code to data during
1573 code alignment, if an odd number of bytes have to be padded. The
1574 code mapping symbol is pushed to an aligned address. */
1577 insert_data_mapping_symbol (enum mstate state
,
1578 valueT value
, fragS
* frag
, offsetT bytes
)
1580 /* If there was already a mapping symbol, remove it. */
1581 if (frag
->tc_frag_data
.last_map
!= NULL
1582 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1583 frag
->fr_address
+ value
)
1585 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1589 know (frag
->tc_frag_data
.first_map
== symp
);
1590 frag
->tc_frag_data
.first_map
= NULL
;
1592 frag
->tc_frag_data
.last_map
= NULL
;
1593 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1596 make_mapping_symbol (MAP_DATA
, value
, frag
);
1597 make_mapping_symbol (state
, value
+ bytes
, frag
);
1600 static void mapping_state_2 (enum mstate state
, int max_chars
);
1602 /* Set the mapping state to STATE. Only call this when about to
1603 emit some STATE bytes to the file. */
1606 mapping_state (enum mstate state
)
1608 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1610 if (state
== MAP_INSN
)
1611 /* AArch64 instructions require 4-byte alignment. When emitting
1612 instructions into any section, record the appropriate section
1614 record_alignment (now_seg
, 2);
1616 if (mapstate
== state
)
1617 /* The mapping symbol has already been emitted.
1618 There is nothing else to do. */
1621 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1622 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1623 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1624 evaluated later in the next else. */
1626 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1628 /* Only add the symbol if the offset is > 0:
1629 if we're at the first frag, check it's size > 0;
1630 if we're not at the first frag, then for sure
1631 the offset is > 0. */
1632 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1633 const int add_symbol
= (frag_now
!= frag_first
)
1634 || (frag_now_fix () > 0);
1637 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1641 mapping_state_2 (state
, 0);
1644 /* Same as mapping_state, but MAX_CHARS bytes have already been
1645 allocated. Put the mapping symbol that far back. */
1648 mapping_state_2 (enum mstate state
, int max_chars
)
1650 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1652 if (!SEG_NORMAL (now_seg
))
1655 if (mapstate
== state
)
1656 /* The mapping symbol has already been emitted.
1657 There is nothing else to do. */
1660 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1661 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1664 #define mapping_state(x) /* nothing */
1665 #define mapping_state_2(x, y) /* nothing */
1668 /* Directives: sectioning and alignment. */
1671 s_bss (int ignore ATTRIBUTE_UNUSED
)
1673 /* We don't support putting frags in the BSS segment, we fake it by
1674 marking in_bss, then looking at s_skip for clues. */
1675 subseg_set (bss_section
, 0);
1676 demand_empty_rest_of_line ();
1677 mapping_state (MAP_DATA
);
1681 s_even (int ignore ATTRIBUTE_UNUSED
)
1683 /* Never make frag if expect extra pass. */
1685 frag_align (1, 0, 0);
1687 record_alignment (now_seg
, 1);
1689 demand_empty_rest_of_line ();
1692 /* Directives: Literal pools. */
1694 static literal_pool
*
1695 find_literal_pool (int size
)
1699 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1701 if (pool
->section
== now_seg
1702 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1709 static literal_pool
*
1710 find_or_make_literal_pool (int size
)
1712 /* Next literal pool ID number. */
1713 static unsigned int latest_pool_num
= 1;
1716 pool
= find_literal_pool (size
);
1720 /* Create a new pool. */
1721 pool
= XNEW (literal_pool
);
1725 /* Currently we always put the literal pool in the current text
1726 section. If we were generating "small" model code where we
1727 knew that all code and initialised data was within 1MB then
1728 we could output literals to mergeable, read-only data
1731 pool
->next_free_entry
= 0;
1732 pool
->section
= now_seg
;
1733 pool
->sub_section
= now_subseg
;
1735 pool
->next
= list_of_pools
;
1736 pool
->symbol
= NULL
;
1738 /* Add it to the list. */
1739 list_of_pools
= pool
;
1742 /* New pools, and emptied pools, will have a NULL symbol. */
1743 if (pool
->symbol
== NULL
)
1745 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1746 (valueT
) 0, &zero_address_frag
);
1747 pool
->id
= latest_pool_num
++;
1754 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1755 Return TRUE on success, otherwise return FALSE. */
1757 add_to_lit_pool (expressionS
*exp
, int size
)
1762 pool
= find_or_make_literal_pool (size
);
1764 /* Check if this literal value is already in the pool. */
1765 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1767 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1769 if ((litexp
->X_op
== exp
->X_op
)
1770 && (exp
->X_op
== O_constant
)
1771 && (litexp
->X_add_number
== exp
->X_add_number
)
1772 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1775 if ((litexp
->X_op
== exp
->X_op
)
1776 && (exp
->X_op
== O_symbol
)
1777 && (litexp
->X_add_number
== exp
->X_add_number
)
1778 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1779 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1783 /* Do we need to create a new entry? */
1784 if (entry
== pool
->next_free_entry
)
1786 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1788 set_syntax_error (_("literal pool overflow"));
1792 pool
->literals
[entry
].exp
= *exp
;
1793 pool
->next_free_entry
+= 1;
1794 if (exp
->X_op
== O_big
)
1796 /* PR 16688: Bignums are held in a single global array. We must
1797 copy and preserve that value now, before it is overwritten. */
1798 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1800 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1801 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1804 pool
->literals
[entry
].bignum
= NULL
;
1807 exp
->X_op
= O_symbol
;
1808 exp
->X_add_number
= ((int) entry
) * size
;
1809 exp
->X_add_symbol
= pool
->symbol
;
1814 /* Can't use symbol_new here, so have to create a symbol and then at
1815 a later date assign it a value. That's what these functions do. */
1818 symbol_locate (symbolS
* symbolP
,
1819 const char *name
,/* It is copied, the caller can modify. */
1820 segT segment
, /* Segment identifier (SEG_<something>). */
1821 valueT valu
, /* Symbol value. */
1822 fragS
* frag
) /* Associated fragment. */
1825 char *preserved_copy_of_name
;
1827 name_length
= strlen (name
) + 1; /* +1 for \0. */
1828 obstack_grow (¬es
, name
, name_length
);
1829 preserved_copy_of_name
= obstack_finish (¬es
);
1831 #ifdef tc_canonicalize_symbol_name
1832 preserved_copy_of_name
=
1833 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1836 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1838 S_SET_SEGMENT (symbolP
, segment
);
1839 S_SET_VALUE (symbolP
, valu
);
1840 symbol_clear_list_pointers (symbolP
);
1842 symbol_set_frag (symbolP
, frag
);
1844 /* Link to end of symbol chain. */
1846 extern int symbol_table_frozen
;
1848 if (symbol_table_frozen
)
1852 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1854 obj_symbol_new_hook (symbolP
);
1856 #ifdef tc_symbol_new_hook
1857 tc_symbol_new_hook (symbolP
);
1861 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1862 #endif /* DEBUG_SYMS */
1867 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1874 for (align
= 2; align
<= 4; align
++)
1876 int size
= 1 << align
;
1878 pool
= find_literal_pool (size
);
1879 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1882 /* Align pool as you have word accesses.
1883 Only make a frag if we have to. */
1885 frag_align (align
, 0, 0);
1887 mapping_state (MAP_DATA
);
1889 record_alignment (now_seg
, align
);
1891 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1893 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1894 (valueT
) frag_now_fix (), frag_now
);
1895 symbol_table_insert (pool
->symbol
);
1897 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1899 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1901 if (exp
->X_op
== O_big
)
1903 /* PR 16688: Restore the global bignum value. */
1904 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1905 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1906 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1909 /* First output the expression in the instruction to the pool. */
1910 emit_expr (exp
, size
); /* .word|.xword */
1912 if (exp
->X_op
== O_big
)
1914 free (pool
->literals
[entry
].bignum
);
1915 pool
->literals
[entry
].bignum
= NULL
;
1919 /* Mark the pool as empty. */
1920 pool
->next_free_entry
= 0;
1921 pool
->symbol
= NULL
;
1926 /* Forward declarations for functions below, in the MD interface
1928 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1929 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1931 /* Directives: Data. */
1932 /* N.B. the support for relocation suffix in this directive needs to be
1933 implemented properly. */
1936 s_aarch64_elf_cons (int nbytes
)
1940 #ifdef md_flush_pending_output
1941 md_flush_pending_output ();
1944 if (is_it_end_of_statement ())
1946 demand_empty_rest_of_line ();
1950 #ifdef md_cons_align
1951 md_cons_align (nbytes
);
1954 mapping_state (MAP_DATA
);
1957 struct reloc_table_entry
*reloc
;
1961 if (exp
.X_op
!= O_symbol
)
1962 emit_expr (&exp
, (unsigned int) nbytes
);
1965 skip_past_char (&input_line_pointer
, '#');
1966 if (skip_past_char (&input_line_pointer
, ':'))
1968 reloc
= find_reloc_table_entry (&input_line_pointer
);
1970 as_bad (_("unrecognized relocation suffix"));
1972 as_bad (_("unimplemented relocation suffix"));
1973 ignore_rest_of_line ();
1977 emit_expr (&exp
, (unsigned int) nbytes
);
1980 while (*input_line_pointer
++ == ',');
1982 /* Put terminator back into stream. */
1983 input_line_pointer
--;
1984 demand_empty_rest_of_line ();
1987 /* Mark symbol that it follows a variant PCS convention. */
1990 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1996 elf_symbol_type
*elfsym
;
1998 c
= get_symbol_name (&name
);
2000 as_bad (_("Missing symbol name in directive"));
2001 sym
= symbol_find_or_make (name
);
2002 restore_line_pointer (c
);
2003 demand_empty_rest_of_line ();
2004 bfdsym
= symbol_get_bfdsym (sym
);
2005 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2006 gas_assert (elfsym
);
2007 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2009 #endif /* OBJ_ELF */
2011 /* Output a 32-bit word, but mark as an instruction. */
2014 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2018 #ifdef md_flush_pending_output
2019 md_flush_pending_output ();
2022 if (is_it_end_of_statement ())
2024 demand_empty_rest_of_line ();
2028 /* Sections are assumed to start aligned. In executable section, there is no
2029 MAP_DATA symbol pending. So we only align the address during
2030 MAP_DATA --> MAP_INSN transition.
2031 For other sections, this is not guaranteed. */
2032 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2033 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2034 frag_align_code (2, 0);
2037 mapping_state (MAP_INSN
);
2043 if (exp
.X_op
!= O_constant
)
2045 as_bad (_("constant expression required"));
2046 ignore_rest_of_line ();
2050 if (target_big_endian
)
2052 unsigned int val
= exp
.X_add_number
;
2053 exp
.X_add_number
= SWAP_32 (val
);
2055 emit_expr (&exp
, 4);
2057 while (*input_line_pointer
++ == ',');
2059 /* Put terminator back into stream. */
2060 input_line_pointer
--;
2061 demand_empty_rest_of_line ();
2065 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2067 demand_empty_rest_of_line ();
2068 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2069 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2073 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2076 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2082 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2083 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2085 demand_empty_rest_of_line ();
2088 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2091 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2095 /* Since we're just labelling the code, there's no need to define a
2098 /* Make sure there is enough room in this frag for the following
2099 blr. This trick only works if the blr follows immediately after
2100 the .tlsdesc directive. */
2102 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2103 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2105 demand_empty_rest_of_line ();
2108 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2111 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2117 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2118 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2120 demand_empty_rest_of_line ();
2122 #endif /* OBJ_ELF */
2124 static void s_aarch64_arch (int);
2125 static void s_aarch64_cpu (int);
2126 static void s_aarch64_arch_extension (int);
2128 /* This table describes all the machine specific pseudo-ops the assembler
2129 has to support. The fields are:
2130 pseudo-op name without dot
2131 function to call to execute this pseudo-op
2132 Integer arg to pass to the function. */
2134 const pseudo_typeS md_pseudo_table
[] = {
2135 /* Never called because '.req' does not start a line. */
2137 {"unreq", s_unreq
, 0},
2139 {"even", s_even
, 0},
2140 {"ltorg", s_ltorg
, 0},
2141 {"pool", s_ltorg
, 0},
2142 {"cpu", s_aarch64_cpu
, 0},
2143 {"arch", s_aarch64_arch
, 0},
2144 {"arch_extension", s_aarch64_arch_extension
, 0},
2145 {"inst", s_aarch64_inst
, 0},
2146 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2148 {"tlsdescadd", s_tlsdescadd
, 0},
2149 {"tlsdesccall", s_tlsdesccall
, 0},
2150 {"tlsdescldr", s_tlsdescldr
, 0},
2151 {"word", s_aarch64_elf_cons
, 4},
2152 {"long", s_aarch64_elf_cons
, 4},
2153 {"xword", s_aarch64_elf_cons
, 8},
2154 {"dword", s_aarch64_elf_cons
, 8},
2155 {"variant_pcs", s_variant_pcs
, 0},
2157 {"float16", float_cons
, 'h'},
2158 {"bfloat16", float_cons
, 'b'},
2163 /* Check whether STR points to a register name followed by a comma or the
2164 end of line; REG_TYPE indicates which register types are checked
2165 against. Return TRUE if STR is such a register name; otherwise return
2166 FALSE. The function does not intend to produce any diagnostics, but since
2167 the register parser aarch64_reg_parse, which is called by this function,
2168 does produce diagnostics, we call clear_error to clear any diagnostics
2169 that may be generated by aarch64_reg_parse.
2170 Also, the function returns FALSE directly if there is any user error
2171 present at the function entry. This prevents the existing diagnostics
2172 state from being spoiled.
2173 The function currently serves parse_constant_immediate and
2174 parse_big_immediate only. */
2176 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2180 /* Prevent the diagnostics state from being spoiled. */
2184 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2186 /* Clear the parsing error that may be set by the reg parser. */
2189 if (reg
== PARSE_FAIL
)
2192 skip_whitespace (str
);
2193 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2199 /* Parser functions used exclusively in instruction operands. */
2201 /* Parse an immediate expression which may not be constant.
2203 To prevent the expression parser from pushing a register name
2204 into the symbol table as an undefined symbol, firstly a check is
2205 done to find out whether STR is a register of type REG_TYPE followed
2206 by a comma or the end of line. Return FALSE if STR is such a string. */
2209 parse_immediate_expression (char **str
, expressionS
*exp
,
2210 aarch64_reg_type reg_type
)
2212 if (reg_name_p (*str
, reg_type
))
2214 set_recoverable_error (_("immediate operand required"));
2218 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2220 if (exp
->X_op
== O_absent
)
2222 set_fatal_syntax_error (_("missing immediate expression"));
2229 /* Constant immediate-value read function for use in insn parsing.
2230 STR points to the beginning of the immediate (with the optional
2231 leading #); *VAL receives the value. REG_TYPE says which register
2232 names should be treated as registers rather than as symbolic immediates.
2234 Return TRUE on success; otherwise return FALSE. */
2237 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2241 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2244 if (exp
.X_op
!= O_constant
)
2246 set_syntax_error (_("constant expression required"));
2250 *val
= exp
.X_add_number
;
2255 encode_imm_float_bits (uint32_t imm
)
2257 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2258 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2261 /* Return TRUE if the single-precision floating-point value encoded in IMM
2262 can be expressed in the AArch64 8-bit signed floating-point format with
2263 3-bit exponent and normalized 4 bits of precision; in other words, the
2264 floating-point value must be expressable as
2265 (+/-) n / 16 * power (2, r)
2266 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2269 aarch64_imm_float_p (uint32_t imm
)
2271 /* If a single-precision floating-point value has the following bit
2272 pattern, it can be expressed in the AArch64 8-bit floating-point
2275 3 32222222 2221111111111
2276 1 09876543 21098765432109876543210
2277 n Eeeeeexx xxxx0000000000000000000
2279 where n, e and each x are either 0 or 1 independently, with
2284 /* Prepare the pattern for 'Eeeeee'. */
2285 if (((imm
>> 30) & 0x1) == 0)
2286 pattern
= 0x3e000000;
2288 pattern
= 0x40000000;
2290 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2291 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2294 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2295 as an IEEE float without any loss of precision. Store the value in
2299 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2301 /* If a double-precision floating-point value has the following bit
2302 pattern, it can be expressed in a float:
2304 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2305 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2306 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2308 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2309 if Eeee_eeee != 1111_1111
2311 where n, e, s and S are either 0 or 1 independently and where ~ is the
2315 uint32_t high32
= imm
>> 32;
2316 uint32_t low32
= imm
;
2318 /* Lower 29 bits need to be 0s. */
2319 if ((imm
& 0x1fffffff) != 0)
2322 /* Prepare the pattern for 'Eeeeeeeee'. */
2323 if (((high32
>> 30) & 0x1) == 0)
2324 pattern
= 0x38000000;
2326 pattern
= 0x40000000;
2329 if ((high32
& 0x78000000) != pattern
)
2332 /* Check Eeee_eeee != 1111_1111. */
2333 if ((high32
& 0x7ff00000) == 0x47f00000)
2336 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2337 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2338 | (low32
>> 29)); /* 3 S bits. */
2342 /* Return true if we should treat OPERAND as a double-precision
2343 floating-point operand rather than a single-precision one. */
2345 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2347 /* Check for unsuffixed SVE registers, which are allowed
2348 for LDR and STR but not in instructions that require an
2349 immediate. We get better error messages if we arbitrarily
2350 pick one size, parse the immediate normally, and then
2351 report the match failure in the normal way. */
2352 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2353 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2356 /* Parse a floating-point immediate. Return TRUE on success and return the
2357 value in *IMMED in the format of IEEE754 single-precision encoding.
2358 *CCP points to the start of the string; DP_P is TRUE when the immediate
2359 is expected to be in double-precision (N.B. this only matters when
2360 hexadecimal representation is involved). REG_TYPE says which register
2361 names should be treated as registers rather than as symbolic immediates.
2363 This routine accepts any IEEE float; it is up to the callers to reject
2367 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2368 aarch64_reg_type reg_type
)
2372 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2374 unsigned fpword
= 0;
2375 bfd_boolean hex_p
= FALSE
;
2377 skip_past_char (&str
, '#');
2380 skip_whitespace (fpnum
);
2382 if (strncmp (fpnum
, "0x", 2) == 0)
2384 /* Support the hexadecimal representation of the IEEE754 encoding.
2385 Double-precision is expected when DP_P is TRUE, otherwise the
2386 representation should be in single-precision. */
2387 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2392 if (!can_convert_double_to_float (val
, &fpword
))
2395 else if ((uint64_t) val
> 0xffffffff)
2402 else if (reg_name_p (str
, reg_type
))
2404 set_recoverable_error (_("immediate operand required"));
2412 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2415 /* Our FP word must be 32 bits (single-precision FP). */
2416 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2418 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2428 set_fatal_syntax_error (_("invalid floating-point constant"));
2432 /* Less-generic immediate-value read function with the possibility of loading
2433 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2436 To prevent the expression parser from pushing a register name into the
2437 symbol table as an undefined symbol, a check is firstly done to find
2438 out whether STR is a register of type REG_TYPE followed by a comma or
2439 the end of line. Return FALSE if STR is such a register. */
2442 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2446 if (reg_name_p (ptr
, reg_type
))
2448 set_syntax_error (_("immediate operand required"));
2452 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2454 if (inst
.reloc
.exp
.X_op
== O_constant
)
2455 *imm
= inst
.reloc
.exp
.X_add_number
;
2462 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2463 if NEED_LIBOPCODES is non-zero, the fixup will need
2464 assistance from the libopcodes. */
2467 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2468 const aarch64_opnd_info
*operand
,
2469 int need_libopcodes_p
)
2471 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2472 reloc
->opnd
= operand
->type
;
2473 if (need_libopcodes_p
)
2474 reloc
->need_libopcodes_p
= 1;
2477 /* Return TRUE if the instruction needs to be fixed up later internally by
2478 the GAS; otherwise return FALSE. */
2480 static inline bfd_boolean
2481 aarch64_gas_internal_fixup_p (void)
2483 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2486 /* Assign the immediate value to the relevant field in *OPERAND if
2487 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2488 needs an internal fixup in a later stage.
2489 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2490 IMM.VALUE that may get assigned with the constant. */
2492 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2493 aarch64_opnd_info
*operand
,
2495 int need_libopcodes_p
,
2498 if (reloc
->exp
.X_op
== O_constant
)
2501 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2503 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2504 reloc
->type
= BFD_RELOC_UNUSED
;
2508 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2509 /* Tell libopcodes to ignore this operand or not. This is helpful
2510 when one of the operands needs to be fixed up later but we need
2511 libopcodes to check the other operands. */
2512 operand
->skip
= skip_p
;
2516 /* Relocation modifiers. Each entry in the table contains the textual
2517 name for the relocation which may be placed before a symbol used as
2518 a load/store offset, or add immediate. It must be surrounded by a
2519 leading and trailing colon, for example:
2521 ldr x0, [x1, #:rello:varsym]
2522 add x0, x1, #:rello:varsym */
2524 struct reloc_table_entry
2528 bfd_reloc_code_real_type adr_type
;
2529 bfd_reloc_code_real_type adrp_type
;
2530 bfd_reloc_code_real_type movw_type
;
2531 bfd_reloc_code_real_type add_type
;
2532 bfd_reloc_code_real_type ldst_type
;
2533 bfd_reloc_code_real_type ld_literal_type
;
2536 static struct reloc_table_entry reloc_table
[] = {
2537 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2542 BFD_RELOC_AARCH64_ADD_LO12
,
2543 BFD_RELOC_AARCH64_LDST_LO12
,
2546 /* Higher 21 bits of pc-relative page offset: ADRP */
2549 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2555 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2558 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2564 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2568 BFD_RELOC_AARCH64_MOVW_G0
,
2573 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2577 BFD_RELOC_AARCH64_MOVW_G0_S
,
2582 /* Less significant bits 0-15 of address/value: MOVK, no check */
2586 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2591 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2595 BFD_RELOC_AARCH64_MOVW_G1
,
2600 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2604 BFD_RELOC_AARCH64_MOVW_G1_S
,
2609 /* Less significant bits 16-31 of address/value: MOVK, no check */
2613 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2618 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2622 BFD_RELOC_AARCH64_MOVW_G2
,
2627 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2631 BFD_RELOC_AARCH64_MOVW_G2_S
,
2636 /* Less significant bits 32-47 of address/value: MOVK, no check */
2640 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2645 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2649 BFD_RELOC_AARCH64_MOVW_G3
,
2654 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2658 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2663 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2667 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2672 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2676 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2681 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2685 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2690 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2694 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2699 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2703 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2708 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2712 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2717 /* Get to the page containing GOT entry for a symbol. */
2720 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2724 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2726 /* 12 bit offset into the page containing GOT entry for that symbol. */
2732 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2735 /* 0-15 bits of address/value: MOVk, no check. */
2739 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2744 /* Most significant bits 16-31 of address/value: MOVZ. */
2748 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2753 /* 15 bit offset into the page containing GOT entry for that symbol. */
2759 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2762 /* Get to the page containing GOT TLS entry for a symbol */
2763 {"gottprel_g0_nc", 0,
2766 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2771 /* Get to the page containing GOT TLS entry for a symbol */
2775 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2780 /* Get to the page containing GOT TLS entry for a symbol */
2782 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2783 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2789 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2794 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2798 /* Lower 16 bits address/value: MOVk. */
2802 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2807 /* Most significant bits 16-31 of address/value: MOVZ. */
2811 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2816 /* Get to the page containing GOT TLS entry for a symbol */
2818 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2819 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2823 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2825 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2830 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2831 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2834 /* Get to the page containing GOT TLS entry for a symbol.
2835 The same as GD, we allocate two consecutive GOT slots
2836 for module index and module offset, the only difference
2837 with GD is the module offset should be initialized to
2838 zero without any outstanding runtime relocation. */
2840 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2841 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2847 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2848 {"tlsldm_lo12_nc", 0,
2852 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2856 /* 12 bit offset into the module TLS base address. */
2861 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2862 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2865 /* Same as dtprel_lo12, no overflow check. */
2866 {"dtprel_lo12_nc", 0,
2870 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2871 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2874 /* bits[23:12] of offset to the module TLS base address. */
2879 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2883 /* bits[15:0] of offset to the module TLS base address. */
2887 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2892 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2896 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2901 /* bits[31:16] of offset to the module TLS base address. */
2905 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2910 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2914 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2919 /* bits[47:32] of offset to the module TLS base address. */
2923 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2928 /* Lower 16 bit offset into GOT entry for a symbol */
2929 {"tlsdesc_off_g0_nc", 0,
2932 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2937 /* Higher 16 bit offset into GOT entry for a symbol */
2938 {"tlsdesc_off_g1", 0,
2941 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2946 /* Get to the page containing GOT TLS entry for a symbol */
2949 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2953 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2955 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2956 {"gottprel_lo12", 0,
2961 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2964 /* Get tp offset for a symbol. */
2969 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2973 /* Get tp offset for a symbol. */
2978 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2979 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2982 /* Get tp offset for a symbol. */
2987 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2991 /* Get tp offset for a symbol. */
2992 {"tprel_lo12_nc", 0,
2996 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2997 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3000 /* Most significant bits 32-47 of address/value: MOVZ. */
3004 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3009 /* Most significant bits 16-31 of address/value: MOVZ. */
3013 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3018 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3022 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3027 /* Most significant bits 0-15 of address/value: MOVZ. */
3031 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3036 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3040 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3045 /* 15bit offset from got entry to base address of GOT table. */
3051 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3054 /* 14bit offset from got entry to base address of GOT table. */
3060 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3064 /* Given the address of a pointer pointing to the textual name of a
3065 relocation as may appear in assembler source, attempt to find its
3066 details in reloc_table. The pointer will be updated to the character
3067 after the trailing colon. On failure, NULL will be returned;
3068 otherwise return the reloc_table_entry. */
3070 static struct reloc_table_entry
*
3071 find_reloc_table_entry (char **str
)
3074 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3076 int length
= strlen (reloc_table
[i
].name
);
3078 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3079 && (*str
)[length
] == ':')
3081 *str
+= (length
+ 1);
3082 return &reloc_table
[i
];
3089 /* Mode argument to parse_shift and parser_shifter_operand. */
3090 enum parse_shift_mode
3092 SHIFTED_NONE
, /* no shifter allowed */
3093 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3095 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3097 SHIFTED_LSL
, /* bare "lsl #n" */
3098 SHIFTED_MUL
, /* bare "mul #n" */
3099 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3100 SHIFTED_MUL_VL
, /* "mul vl" */
3101 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3104 /* Parse a <shift> operator on an AArch64 data processing instruction.
3105 Return TRUE on success; otherwise return FALSE. */
3107 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3109 const struct aarch64_name_value_pair
*shift_op
;
3110 enum aarch64_modifier_kind kind
;
3116 for (p
= *str
; ISALPHA (*p
); p
++)
3121 set_syntax_error (_("shift expression expected"));
3125 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3127 if (shift_op
== NULL
)
3129 set_syntax_error (_("shift operator expected"));
3133 kind
= aarch64_get_operand_modifier (shift_op
);
3135 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3137 set_syntax_error (_("invalid use of 'MSL'"));
3141 if (kind
== AARCH64_MOD_MUL
3142 && mode
!= SHIFTED_MUL
3143 && mode
!= SHIFTED_MUL_VL
)
3145 set_syntax_error (_("invalid use of 'MUL'"));
3151 case SHIFTED_LOGIC_IMM
:
3152 if (aarch64_extend_operator_p (kind
))
3154 set_syntax_error (_("extending shift is not permitted"));
3159 case SHIFTED_ARITH_IMM
:
3160 if (kind
== AARCH64_MOD_ROR
)
3162 set_syntax_error (_("'ROR' shift is not permitted"));
3168 if (kind
!= AARCH64_MOD_LSL
)
3170 set_syntax_error (_("only 'LSL' shift is permitted"));
3176 if (kind
!= AARCH64_MOD_MUL
)
3178 set_syntax_error (_("only 'MUL' is permitted"));
3183 case SHIFTED_MUL_VL
:
3184 /* "MUL VL" consists of two separate tokens. Require the first
3185 token to be "MUL" and look for a following "VL". */
3186 if (kind
== AARCH64_MOD_MUL
)
3188 skip_whitespace (p
);
3189 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3192 kind
= AARCH64_MOD_MUL_VL
;
3196 set_syntax_error (_("only 'MUL VL' is permitted"));
3199 case SHIFTED_REG_OFFSET
:
3200 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3201 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3203 set_fatal_syntax_error
3204 (_("invalid shift for the register offset addressing mode"));
3209 case SHIFTED_LSL_MSL
:
3210 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3212 set_syntax_error (_("invalid shift operator"));
3221 /* Whitespace can appear here if the next thing is a bare digit. */
3222 skip_whitespace (p
);
3224 /* Parse shift amount. */
3226 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3227 exp
.X_op
= O_absent
;
3230 if (is_immediate_prefix (*p
))
3235 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3237 if (kind
== AARCH64_MOD_MUL_VL
)
3238 /* For consistency, give MUL VL the same shift amount as an implicit
3240 operand
->shifter
.amount
= 1;
3241 else if (exp
.X_op
== O_absent
)
3243 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3245 set_syntax_error (_("missing shift amount"));
3248 operand
->shifter
.amount
= 0;
3250 else if (exp
.X_op
!= O_constant
)
3252 set_syntax_error (_("constant shift amount required"));
3255 /* For parsing purposes, MUL #n has no inherent range. The range
3256 depends on the operand and will be checked by operand-specific
3258 else if (kind
!= AARCH64_MOD_MUL
3259 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3261 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3266 operand
->shifter
.amount
= exp
.X_add_number
;
3267 operand
->shifter
.amount_present
= 1;
3270 operand
->shifter
.operator_present
= 1;
3271 operand
->shifter
.kind
= kind
;
3277 /* Parse a <shifter_operand> for a data processing instruction:
3280 #<immediate>, LSL #imm
3282 Validation of immediate operands is deferred to md_apply_fix.
3284 Return TRUE on success; otherwise return FALSE. */
3287 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3288 enum parse_shift_mode mode
)
3292 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3297 /* Accept an immediate expression. */
3298 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3301 /* Accept optional LSL for arithmetic immediate values. */
3302 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3303 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3306 /* Not accept any shifter for logical immediate values. */
3307 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3308 && parse_shift (&p
, operand
, mode
))
3310 set_syntax_error (_("unexpected shift operator"));
3318 /* Parse a <shifter_operand> for a data processing instruction:
3323 #<immediate>, LSL #imm
3325 where <shift> is handled by parse_shift above, and the last two
3326 cases are handled by the function above.
3328 Validation of immediate operands is deferred to md_apply_fix.
3330 Return TRUE on success; otherwise return FALSE. */
3333 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3334 enum parse_shift_mode mode
)
3336 const reg_entry
*reg
;
3337 aarch64_opnd_qualifier_t qualifier
;
3338 enum aarch64_operand_class opd_class
3339 = aarch64_get_operand_class (operand
->type
);
3341 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3344 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3346 set_syntax_error (_("unexpected register in the immediate operand"));
3350 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3352 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3356 operand
->reg
.regno
= reg
->number
;
3357 operand
->qualifier
= qualifier
;
3359 /* Accept optional shift operation on register. */
3360 if (! skip_past_comma (str
))
3363 if (! parse_shift (str
, operand
, mode
))
3368 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3371 (_("integer register expected in the extended/shifted operand "
3376 /* We have a shifted immediate variable. */
3377 return parse_shifter_operand_imm (str
, operand
, mode
);
3380 /* Return TRUE on success; return FALSE otherwise. */
3383 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3384 enum parse_shift_mode mode
)
3388 /* Determine if we have the sequence of characters #: or just :
3389 coming next. If we do, then we check for a :rello: relocation
3390 modifier. If we don't, punt the whole lot to
3391 parse_shifter_operand. */
3393 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3395 struct reloc_table_entry
*entry
;
3403 /* Try to parse a relocation. Anything else is an error. */
3404 if (!(entry
= find_reloc_table_entry (str
)))
3406 set_syntax_error (_("unknown relocation modifier"));
3410 if (entry
->add_type
== 0)
3413 (_("this relocation modifier is not allowed on this instruction"));
3417 /* Save str before we decompose it. */
3420 /* Next, we parse the expression. */
3421 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3424 /* Record the relocation type (use the ADD variant here). */
3425 inst
.reloc
.type
= entry
->add_type
;
3426 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3428 /* If str is empty, we've reached the end, stop here. */
3432 /* Otherwise, we have a shifted reloc modifier, so rewind to
3433 recover the variable name and continue parsing for the shifter. */
3435 return parse_shifter_operand_imm (str
, operand
, mode
);
3438 return parse_shifter_operand (str
, operand
, mode
);
3441 /* Parse all forms of an address expression. Information is written
3442 to *OPERAND and/or inst.reloc.
3444 The A64 instruction set has the following addressing modes:
3447 [base] // in SIMD ld/st structure
3448 [base{,#0}] // in ld/st exclusive
3450 [base,Xm{,LSL #imm}]
3451 [base,Xm,SXTX {#imm}]
3452 [base,Wm,(S|U)XTW {#imm}]
3454 [base]! // in ldraa/ldrab exclusive
3458 [base],Xm // in SIMD ld/st structure
3459 PC-relative (literal)
3463 [base,Zm.D{,LSL #imm}]
3464 [base,Zm.S,(S|U)XTW {#imm}]
3465 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3469 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3470 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3471 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3473 (As a convenience, the notation "=immediate" is permitted in conjunction
3474 with the pc-relative literal load instructions to automatically place an
3475 immediate value or symbolic address in a nearby literal pool and generate
3476 a hidden label which references it.)
3478 Upon a successful parsing, the address structure in *OPERAND will be
3479 filled in the following way:
3481 .base_regno = <base>
3482 .offset.is_reg // 1 if the offset is a register
3484 .offset.regno = <Rm>
3486 For different addressing modes defined in the A64 ISA:
3489 .pcrel=0; .preind=1; .postind=0; .writeback=0
3491 .pcrel=0; .preind=1; .postind=0; .writeback=1
3493 .pcrel=0; .preind=0; .postind=1; .writeback=1
3494 PC-relative (literal)
3495 .pcrel=1; .preind=1; .postind=0; .writeback=0
3497 The shift/extension information, if any, will be stored in .shifter.
3498 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3499 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3500 corresponding register.
3502 BASE_TYPE says which types of base register should be accepted and
3503 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3504 is the type of shifter that is allowed for immediate offsets,
3505 or SHIFTED_NONE if none.
3507 In all other respects, it is the caller's responsibility to check
3508 for addressing modes not supported by the instruction, and to set
3512 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3513 aarch64_opnd_qualifier_t
*base_qualifier
,
3514 aarch64_opnd_qualifier_t
*offset_qualifier
,
3515 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3516 enum parse_shift_mode imm_shift_mode
)
3519 const reg_entry
*reg
;
3520 expressionS
*exp
= &inst
.reloc
.exp
;
3522 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3523 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3524 if (! skip_past_char (&p
, '['))
3526 /* =immediate or label. */
3527 operand
->addr
.pcrel
= 1;
3528 operand
->addr
.preind
= 1;
3530 /* #:<reloc_op>:<symbol> */
3531 skip_past_char (&p
, '#');
3532 if (skip_past_char (&p
, ':'))
3534 bfd_reloc_code_real_type ty
;
3535 struct reloc_table_entry
*entry
;
3537 /* Try to parse a relocation modifier. Anything else is
3539 entry
= find_reloc_table_entry (&p
);
3542 set_syntax_error (_("unknown relocation modifier"));
3546 switch (operand
->type
)
3548 case AARCH64_OPND_ADDR_PCREL21
:
3550 ty
= entry
->adr_type
;
3554 ty
= entry
->ld_literal_type
;
3561 (_("this relocation modifier is not allowed on this "
3567 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3569 set_syntax_error (_("invalid relocation expression"));
3573 /* #:<reloc_op>:<expr> */
3574 /* Record the relocation type. */
3575 inst
.reloc
.type
= ty
;
3576 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3581 if (skip_past_char (&p
, '='))
3582 /* =immediate; need to generate the literal in the literal pool. */
3583 inst
.gen_lit_pool
= 1;
3585 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3587 set_syntax_error (_("invalid address"));
3598 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3599 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3601 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3604 operand
->addr
.base_regno
= reg
->number
;
3607 if (skip_past_comma (&p
))
3610 operand
->addr
.preind
= 1;
3612 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3615 if (!aarch64_check_reg_type (reg
, offset_type
))
3617 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3622 operand
->addr
.offset
.regno
= reg
->number
;
3623 operand
->addr
.offset
.is_reg
= 1;
3624 /* Shifted index. */
3625 if (skip_past_comma (&p
))
3628 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3629 /* Use the diagnostics set in parse_shift, so not set new
3630 error message here. */
3634 [base,Xm] # For vector plus scalar SVE2 indexing.
3635 [base,Xm{,LSL #imm}]
3636 [base,Xm,SXTX {#imm}]
3637 [base,Wm,(S|U)XTW {#imm}] */
3638 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3639 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3640 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3642 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3644 set_syntax_error (_("invalid use of 32-bit register offset"));
3647 if (aarch64_get_qualifier_esize (*base_qualifier
)
3648 != aarch64_get_qualifier_esize (*offset_qualifier
)
3649 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3650 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3651 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3653 set_syntax_error (_("offset has different size from base"));
3657 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3659 set_syntax_error (_("invalid use of 64-bit register offset"));
3665 /* [Xn,#:<reloc_op>:<symbol> */
3666 skip_past_char (&p
, '#');
3667 if (skip_past_char (&p
, ':'))
3669 struct reloc_table_entry
*entry
;
3671 /* Try to parse a relocation modifier. Anything else is
3673 if (!(entry
= find_reloc_table_entry (&p
)))
3675 set_syntax_error (_("unknown relocation modifier"));
3679 if (entry
->ldst_type
== 0)
3682 (_("this relocation modifier is not allowed on this "
3687 /* [Xn,#:<reloc_op>: */
3688 /* We now have the group relocation table entry corresponding to
3689 the name in the assembler source. Next, we parse the
3691 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3693 set_syntax_error (_("invalid relocation expression"));
3697 /* [Xn,#:<reloc_op>:<expr> */
3698 /* Record the load/store relocation type. */
3699 inst
.reloc
.type
= entry
->ldst_type
;
3700 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3704 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3706 set_syntax_error (_("invalid expression in the address"));
3710 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3711 /* [Xn,<expr>,<shifter> */
3712 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3718 if (! skip_past_char (&p
, ']'))
3720 set_syntax_error (_("']' expected"));
3724 if (skip_past_char (&p
, '!'))
3726 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3728 set_syntax_error (_("register offset not allowed in pre-indexed "
3729 "addressing mode"));
3733 operand
->addr
.writeback
= 1;
3735 else if (skip_past_comma (&p
))
3738 operand
->addr
.postind
= 1;
3739 operand
->addr
.writeback
= 1;
3741 if (operand
->addr
.preind
)
3743 set_syntax_error (_("cannot combine pre- and post-indexing"));
3747 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3751 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3753 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3757 operand
->addr
.offset
.regno
= reg
->number
;
3758 operand
->addr
.offset
.is_reg
= 1;
3760 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3763 set_syntax_error (_("invalid expression in the address"));
3768 /* If at this point neither .preind nor .postind is set, we have a
3769 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3770 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3771 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3773 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3775 if (operand
->addr
.writeback
)
3777 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3779 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3780 operand
->addr
.offset
.is_reg
= 0;
3781 operand
->addr
.offset
.imm
= 0;
3782 operand
->addr
.preind
= 1;
3787 set_syntax_error (_("missing offset in the pre-indexed address"));
3793 operand
->addr
.preind
= 1;
3794 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3796 operand
->addr
.offset
.is_reg
= 1;
3797 operand
->addr
.offset
.regno
= REG_ZR
;
3798 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3802 inst
.reloc
.exp
.X_op
= O_constant
;
3803 inst
.reloc
.exp
.X_add_number
= 0;
3812 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3815 parse_address (char **str
, aarch64_opnd_info
*operand
)
3817 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3818 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3819 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3822 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3823 The arguments have the same meaning as for parse_address_main.
3824 Return TRUE on success. */
3826 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3827 aarch64_opnd_qualifier_t
*base_qualifier
,
3828 aarch64_opnd_qualifier_t
*offset_qualifier
)
3830 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3831 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3835 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3836 Return TRUE on success; otherwise return FALSE. */
3838 parse_half (char **str
, int *internal_fixup_p
)
3842 skip_past_char (&p
, '#');
3844 gas_assert (internal_fixup_p
);
3845 *internal_fixup_p
= 0;
3849 struct reloc_table_entry
*entry
;
3851 /* Try to parse a relocation. Anything else is an error. */
3853 if (!(entry
= find_reloc_table_entry (&p
)))
3855 set_syntax_error (_("unknown relocation modifier"));
3859 if (entry
->movw_type
== 0)
3862 (_("this relocation modifier is not allowed on this instruction"));
3866 inst
.reloc
.type
= entry
->movw_type
;
3869 *internal_fixup_p
= 1;
3871 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3878 /* Parse an operand for an ADRP instruction:
3880 Return TRUE on success; otherwise return FALSE. */
3883 parse_adrp (char **str
)
3890 struct reloc_table_entry
*entry
;
3892 /* Try to parse a relocation. Anything else is an error. */
3894 if (!(entry
= find_reloc_table_entry (&p
)))
3896 set_syntax_error (_("unknown relocation modifier"));
3900 if (entry
->adrp_type
== 0)
3903 (_("this relocation modifier is not allowed on this instruction"));
3907 inst
.reloc
.type
= entry
->adrp_type
;
3910 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3912 inst
.reloc
.pc_rel
= 1;
3914 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3921 /* Miscellaneous. */
3923 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3924 of SIZE tokens in which index I gives the token for field value I,
3925 or is null if field value I is invalid. REG_TYPE says which register
3926 names should be treated as registers rather than as symbolic immediates.
3928 Return true on success, moving *STR past the operand and storing the
3929 field value in *VAL. */
3932 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3933 size_t size
, aarch64_reg_type reg_type
)
3939 /* Match C-like tokens. */
3941 while (ISALNUM (*q
))
3944 for (i
= 0; i
< size
; ++i
)
3946 && strncasecmp (array
[i
], p
, q
- p
) == 0
3947 && array
[i
][q
- p
] == 0)
3954 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3957 if (exp
.X_op
== O_constant
3958 && (uint64_t) exp
.X_add_number
< size
)
3960 *val
= exp
.X_add_number
;
3965 /* Use the default error for this operand. */
3969 /* Parse an option for a preload instruction. Returns the encoding for the
3970 option, or PARSE_FAIL. */
3973 parse_pldop (char **str
)
3976 const struct aarch64_name_value_pair
*o
;
3979 while (ISALNUM (*q
))
3982 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3990 /* Parse an option for a barrier instruction. Returns the encoding for the
3991 option, or PARSE_FAIL. */
3994 parse_barrier (char **str
)
3997 const asm_barrier_opt
*o
;
4000 while (ISALPHA (*q
))
4003 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4011 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4012 return 0 if successful. Otherwise return PARSE_FAIL. */
4015 parse_barrier_psb (char **str
,
4016 const struct aarch64_name_value_pair
** hint_opt
)
4019 const struct aarch64_name_value_pair
*o
;
4022 while (ISALPHA (*q
))
4025 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4028 set_fatal_syntax_error
4029 ( _("unknown or missing option to PSB"));
4033 if (o
->value
!= 0x11)
4035 /* PSB only accepts option name 'CSYNC'. */
4037 (_("the specified option is not accepted for PSB"));
4046 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4047 return 0 if successful. Otherwise return PARSE_FAIL. */
4050 parse_bti_operand (char **str
,
4051 const struct aarch64_name_value_pair
** hint_opt
)
4054 const struct aarch64_name_value_pair
*o
;
4057 while (ISALPHA (*q
))
4060 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4063 set_fatal_syntax_error
4064 ( _("unknown option to BTI"));
4070 /* Valid BTI operands. */
4078 (_("unknown option to BTI"));
4087 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4088 Returns the encoding for the option, or PARSE_FAIL.
4090 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4091 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4093 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4094 field, otherwise as a system register.
4098 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
4099 int imple_defined_p
, int pstatefield_p
,
4104 const aarch64_sys_reg
*o
;
4108 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4110 *p
++ = TOLOWER (*q
);
4112 /* Assert that BUF be large enough. */
4113 gas_assert (p
- buf
== q
- *str
);
4115 o
= hash_find (sys_regs
, buf
);
4118 if (!imple_defined_p
)
4122 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4123 unsigned int op0
, op1
, cn
, cm
, op2
;
4125 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4128 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4130 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4137 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4138 as_bad (_("selected processor does not support PSTATE field "
4140 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4141 as_bad (_("selected processor does not support system register "
4143 if (aarch64_sys_reg_deprecated_p (o
))
4144 as_warn (_("system register name '%s' is deprecated and may be "
4145 "removed in a future release"), buf
);
4155 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4156 for the option, or NULL. */
4158 static const aarch64_sys_ins_reg
*
4159 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4163 const aarch64_sys_ins_reg
*o
;
4166 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4168 *p
++ = TOLOWER (*q
);
4171 o
= hash_find (sys_ins_regs
, buf
);
4175 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4176 as_bad (_("selected processor does not support system register "
4183 #define po_char_or_fail(chr) do { \
4184 if (! skip_past_char (&str, chr)) \
4188 #define po_reg_or_fail(regtype) do { \
4189 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4190 if (val == PARSE_FAIL) \
4192 set_default_error (); \
4197 #define po_int_reg_or_fail(reg_type) do { \
4198 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4199 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4201 set_default_error (); \
4204 info->reg.regno = reg->number; \
4205 info->qualifier = qualifier; \
4208 #define po_imm_nc_or_fail() do { \
4209 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4213 #define po_imm_or_fail(min, max) do { \
4214 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4216 if (val < min || val > max) \
4218 set_fatal_syntax_error (_("immediate value out of range "\
4219 #min " to "#max)); \
4224 #define po_enum_or_fail(array) do { \
4225 if (!parse_enum_string (&str, &val, array, \
4226 ARRAY_SIZE (array), imm_reg_type)) \
4230 #define po_misc_or_fail(expr) do { \
4235 /* encode the 12-bit imm field of Add/sub immediate */
4236 static inline uint32_t
4237 encode_addsub_imm (uint32_t imm
)
4242 /* encode the shift amount field of Add/sub immediate */
4243 static inline uint32_t
4244 encode_addsub_imm_shift_amount (uint32_t cnt
)
4250 /* encode the imm field of Adr instruction */
4251 static inline uint32_t
4252 encode_adr_imm (uint32_t imm
)
4254 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4255 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4258 /* encode the immediate field of Move wide immediate */
4259 static inline uint32_t
4260 encode_movw_imm (uint32_t imm
)
4265 /* encode the 26-bit offset of unconditional branch */
4266 static inline uint32_t
4267 encode_branch_ofs_26 (uint32_t ofs
)
4269 return ofs
& ((1 << 26) - 1);
4272 /* encode the 19-bit offset of conditional branch and compare & branch */
4273 static inline uint32_t
4274 encode_cond_branch_ofs_19 (uint32_t ofs
)
4276 return (ofs
& ((1 << 19) - 1)) << 5;
4279 /* encode the 19-bit offset of ld literal */
4280 static inline uint32_t
4281 encode_ld_lit_ofs_19 (uint32_t ofs
)
4283 return (ofs
& ((1 << 19) - 1)) << 5;
4286 /* Encode the 14-bit offset of test & branch. */
4287 static inline uint32_t
4288 encode_tst_branch_ofs_14 (uint32_t ofs
)
4290 return (ofs
& ((1 << 14) - 1)) << 5;
4293 /* Encode the 16-bit imm field of svc/hvc/smc. */
4294 static inline uint32_t
4295 encode_svc_imm (uint32_t imm
)
4300 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4301 static inline uint32_t
4302 reencode_addsub_switch_add_sub (uint32_t opcode
)
4304 return opcode
^ (1 << 30);
4307 static inline uint32_t
4308 reencode_movzn_to_movz (uint32_t opcode
)
4310 return opcode
| (1 << 30);
4313 static inline uint32_t
4314 reencode_movzn_to_movn (uint32_t opcode
)
4316 return opcode
& ~(1 << 30);
4319 /* Overall per-instruction processing. */
4321 /* We need to be able to fix up arbitrary expressions in some statements.
4322 This is so that we can handle symbols that are an arbitrary distance from
4323 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4324 which returns part of an address in a form which will be valid for
4325 a data instruction. We do this by pushing the expression into a symbol
4326 in the expr_section, and creating a fix for that. */
4329 fix_new_aarch64 (fragS
* frag
,
4331 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4341 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4345 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4352 /* Diagnostics on operands errors. */
4354 /* By default, output verbose error message.
4355 Disable the verbose error message by -mno-verbose-error. */
4356 static int verbose_error_p
= 1;
4358 #ifdef DEBUG_AARCH64
4359 /* N.B. this is only for the purpose of debugging. */
4360 const char* operand_mismatch_kind_names
[] =
4363 "AARCH64_OPDE_RECOVERABLE",
4364 "AARCH64_OPDE_SYNTAX_ERROR",
4365 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4366 "AARCH64_OPDE_INVALID_VARIANT",
4367 "AARCH64_OPDE_OUT_OF_RANGE",
4368 "AARCH64_OPDE_UNALIGNED",
4369 "AARCH64_OPDE_REG_LIST",
4370 "AARCH64_OPDE_OTHER_ERROR",
4372 #endif /* DEBUG_AARCH64 */
4374 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4376 When multiple errors of different kinds are found in the same assembly
4377 line, only the error of the highest severity will be picked up for
4378 issuing the diagnostics. */
4380 static inline bfd_boolean
4381 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4382 enum aarch64_operand_error_kind rhs
)
4384 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4385 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4386 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4387 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4388 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4389 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4390 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4391 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4395 /* Helper routine to get the mnemonic name from the assembly instruction
4396 line; should only be called for the diagnosis purpose, as there is
4397 string copy operation involved, which may affect the runtime
4398 performance if used in elsewhere. */
4401 get_mnemonic_name (const char *str
)
4403 static char mnemonic
[32];
4406 /* Get the first 15 bytes and assume that the full name is included. */
4407 strncpy (mnemonic
, str
, 31);
4408 mnemonic
[31] = '\0';
4410 /* Scan up to the end of the mnemonic, which must end in white space,
4411 '.', or end of string. */
4412 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4417 /* Append '...' to the truncated long name. */
4418 if (ptr
- mnemonic
== 31)
4419 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4425 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4427 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4428 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4431 /* Data structures storing one user error in the assembly code related to
4434 struct operand_error_record
4436 const aarch64_opcode
*opcode
;
4437 aarch64_operand_error detail
;
4438 struct operand_error_record
*next
;
4441 typedef struct operand_error_record operand_error_record
;
4443 struct operand_errors
4445 operand_error_record
*head
;
4446 operand_error_record
*tail
;
4449 typedef struct operand_errors operand_errors
;
4451 /* Top-level data structure reporting user errors for the current line of
4453 The way md_assemble works is that all opcodes sharing the same mnemonic
4454 name are iterated to find a match to the assembly line. In this data
4455 structure, each of the such opcodes will have one operand_error_record
4456 allocated and inserted. In other words, excessive errors related with
4457 a single opcode are disregarded. */
4458 operand_errors operand_error_report
;
4460 /* Free record nodes. */
4461 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4463 /* Initialize the data structure that stores the operand mismatch
4464 information on assembling one line of the assembly code. */
4466 init_operand_error_report (void)
4468 if (operand_error_report
.head
!= NULL
)
4470 gas_assert (operand_error_report
.tail
!= NULL
);
4471 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4472 free_opnd_error_record_nodes
= operand_error_report
.head
;
4473 operand_error_report
.head
= NULL
;
4474 operand_error_report
.tail
= NULL
;
4477 gas_assert (operand_error_report
.tail
== NULL
);
4480 /* Return TRUE if some operand error has been recorded during the
4481 parsing of the current assembly line using the opcode *OPCODE;
4482 otherwise return FALSE. */
4483 static inline bfd_boolean
4484 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4486 operand_error_record
*record
= operand_error_report
.head
;
4487 return record
&& record
->opcode
== opcode
;
4490 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4491 OPCODE field is initialized with OPCODE.
4492 N.B. only one record for each opcode, i.e. the maximum of one error is
4493 recorded for each instruction template. */
4496 add_operand_error_record (const operand_error_record
* new_record
)
4498 const aarch64_opcode
*opcode
= new_record
->opcode
;
4499 operand_error_record
* record
= operand_error_report
.head
;
4501 /* The record may have been created for this opcode. If not, we need
4503 if (! opcode_has_operand_error_p (opcode
))
4505 /* Get one empty record. */
4506 if (free_opnd_error_record_nodes
== NULL
)
4508 record
= XNEW (operand_error_record
);
4512 record
= free_opnd_error_record_nodes
;
4513 free_opnd_error_record_nodes
= record
->next
;
4515 record
->opcode
= opcode
;
4516 /* Insert at the head. */
4517 record
->next
= operand_error_report
.head
;
4518 operand_error_report
.head
= record
;
4519 if (operand_error_report
.tail
== NULL
)
4520 operand_error_report
.tail
= record
;
4522 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4523 && record
->detail
.index
<= new_record
->detail
.index
4524 && operand_error_higher_severity_p (record
->detail
.kind
,
4525 new_record
->detail
.kind
))
4527 /* In the case of multiple errors found on operands related with a
4528 single opcode, only record the error of the leftmost operand and
4529 only if the error is of higher severity. */
4530 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4531 " the existing error %s on operand %d",
4532 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4533 new_record
->detail
.index
,
4534 operand_mismatch_kind_names
[record
->detail
.kind
],
4535 record
->detail
.index
);
4539 record
->detail
= new_record
->detail
;
4543 record_operand_error_info (const aarch64_opcode
*opcode
,
4544 aarch64_operand_error
*error_info
)
4546 operand_error_record record
;
4547 record
.opcode
= opcode
;
4548 record
.detail
= *error_info
;
4549 add_operand_error_record (&record
);
4552 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4553 error message *ERROR, for operand IDX (count from 0). */
4556 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4557 enum aarch64_operand_error_kind kind
,
4560 aarch64_operand_error info
;
4561 memset(&info
, 0, sizeof (info
));
4565 info
.non_fatal
= FALSE
;
4566 record_operand_error_info (opcode
, &info
);
4570 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4571 enum aarch64_operand_error_kind kind
,
4572 const char* error
, const int *extra_data
)
4574 aarch64_operand_error info
;
4578 info
.data
[0] = extra_data
[0];
4579 info
.data
[1] = extra_data
[1];
4580 info
.data
[2] = extra_data
[2];
4581 info
.non_fatal
= FALSE
;
4582 record_operand_error_info (opcode
, &info
);
4586 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4587 const char* error
, int lower_bound
,
4590 int data
[3] = {lower_bound
, upper_bound
, 0};
4591 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4595 /* Remove the operand error record for *OPCODE. */
4596 static void ATTRIBUTE_UNUSED
4597 remove_operand_error_record (const aarch64_opcode
*opcode
)
4599 if (opcode_has_operand_error_p (opcode
))
4601 operand_error_record
* record
= operand_error_report
.head
;
4602 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4603 operand_error_report
.head
= record
->next
;
4604 record
->next
= free_opnd_error_record_nodes
;
4605 free_opnd_error_record_nodes
= record
;
4606 if (operand_error_report
.head
== NULL
)
4608 gas_assert (operand_error_report
.tail
== record
);
4609 operand_error_report
.tail
= NULL
;
4614 /* Given the instruction in *INSTR, return the index of the best matched
4615 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4617 Return -1 if there is no qualifier sequence; return the first match
4618 if there is multiple matches found. */
4621 find_best_match (const aarch64_inst
*instr
,
4622 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4624 int i
, num_opnds
, max_num_matched
, idx
;
4626 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4629 DEBUG_TRACE ("no operand");
4633 max_num_matched
= 0;
4636 /* For each pattern. */
4637 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4640 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4642 /* Most opcodes has much fewer patterns in the list. */
4643 if (empty_qualifier_sequence_p (qualifiers
))
4645 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4649 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4650 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4653 if (num_matched
> max_num_matched
)
4655 max_num_matched
= num_matched
;
4660 DEBUG_TRACE ("return with %d", idx
);
4664 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4665 corresponding operands in *INSTR. */
4668 assign_qualifier_sequence (aarch64_inst
*instr
,
4669 const aarch64_opnd_qualifier_t
*qualifiers
)
4672 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4673 gas_assert (num_opnds
);
4674 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4675 instr
->operands
[i
].qualifier
= *qualifiers
;
4678 /* Print operands for the diagnosis purpose. */
4681 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4682 const aarch64_opnd_info
*opnds
)
4686 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4690 /* We regard the opcode operand info more, however we also look into
4691 the inst->operands to support the disassembling of the optional
4693 The two operand code should be the same in all cases, apart from
4694 when the operand can be optional. */
4695 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4696 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4699 /* Generate the operand string in STR. */
4700 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4705 strcat (buf
, i
== 0 ? " " : ", ");
4707 /* Append the operand string. */
4712 /* Send to stderr a string as information. */
4715 output_info (const char *format
, ...)
4721 file
= as_where (&line
);
4725 fprintf (stderr
, "%s:%u: ", file
, line
);
4727 fprintf (stderr
, "%s: ", file
);
4729 fprintf (stderr
, _("Info: "));
4730 va_start (args
, format
);
4731 vfprintf (stderr
, format
, args
);
4733 (void) putc ('\n', stderr
);
4736 /* Output one operand error record. */
4739 output_operand_error_record (const operand_error_record
*record
, char *str
)
4741 const aarch64_operand_error
*detail
= &record
->detail
;
4742 int idx
= detail
->index
;
4743 const aarch64_opcode
*opcode
= record
->opcode
;
4744 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4745 : AARCH64_OPND_NIL
);
4747 typedef void (*handler_t
)(const char *format
, ...);
4748 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4750 switch (detail
->kind
)
4752 case AARCH64_OPDE_NIL
:
4755 case AARCH64_OPDE_SYNTAX_ERROR
:
4756 case AARCH64_OPDE_RECOVERABLE
:
4757 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4758 case AARCH64_OPDE_OTHER_ERROR
:
4759 /* Use the prepared error message if there is, otherwise use the
4760 operand description string to describe the error. */
4761 if (detail
->error
!= NULL
)
4764 handler (_("%s -- `%s'"), detail
->error
, str
);
4766 handler (_("%s at operand %d -- `%s'"),
4767 detail
->error
, idx
+ 1, str
);
4771 gas_assert (idx
>= 0);
4772 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4773 aarch64_get_operand_desc (opd_code
), str
);
4777 case AARCH64_OPDE_INVALID_VARIANT
:
4778 handler (_("operand mismatch -- `%s'"), str
);
4779 if (verbose_error_p
)
4781 /* We will try to correct the erroneous instruction and also provide
4782 more information e.g. all other valid variants.
4784 The string representation of the corrected instruction and other
4785 valid variants are generated by
4787 1) obtaining the intermediate representation of the erroneous
4789 2) manipulating the IR, e.g. replacing the operand qualifier;
4790 3) printing out the instruction by calling the printer functions
4791 shared with the disassembler.
4793 The limitation of this method is that the exact input assembly
4794 line cannot be accurately reproduced in some cases, for example an
4795 optional operand present in the actual assembly line will be
4796 omitted in the output; likewise for the optional syntax rules,
4797 e.g. the # before the immediate. Another limitation is that the
4798 assembly symbols and relocation operations in the assembly line
4799 currently cannot be printed out in the error report. Last but not
4800 least, when there is other error(s) co-exist with this error, the
4801 'corrected' instruction may be still incorrect, e.g. given
4802 'ldnp h0,h1,[x0,#6]!'
4803 this diagnosis will provide the version:
4804 'ldnp s0,s1,[x0,#6]!'
4805 which is still not right. */
4806 size_t len
= strlen (get_mnemonic_name (str
));
4810 aarch64_inst
*inst_base
= &inst
.base
;
4811 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4814 reset_aarch64_instruction (&inst
);
4815 inst_base
->opcode
= opcode
;
4817 /* Reset the error report so that there is no side effect on the
4818 following operand parsing. */
4819 init_operand_error_report ();
4822 result
= parse_operands (str
+ len
, opcode
)
4823 && programmer_friendly_fixup (&inst
);
4824 gas_assert (result
);
4825 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4826 NULL
, NULL
, insn_sequence
);
4827 gas_assert (!result
);
4829 /* Find the most matched qualifier sequence. */
4830 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4831 gas_assert (qlf_idx
> -1);
4833 /* Assign the qualifiers. */
4834 assign_qualifier_sequence (inst_base
,
4835 opcode
->qualifiers_list
[qlf_idx
]);
4837 /* Print the hint. */
4838 output_info (_(" did you mean this?"));
4839 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4840 print_operands (buf
, opcode
, inst_base
->operands
);
4841 output_info (_(" %s"), buf
);
4843 /* Print out other variant(s) if there is any. */
4845 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4846 output_info (_(" other valid variant(s):"));
4848 /* For each pattern. */
4849 qualifiers_list
= opcode
->qualifiers_list
;
4850 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4852 /* Most opcodes has much fewer patterns in the list.
4853 First NIL qualifier indicates the end in the list. */
4854 if (empty_qualifier_sequence_p (*qualifiers_list
))
4859 /* Mnemonics name. */
4860 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4862 /* Assign the qualifiers. */
4863 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4865 /* Print instruction. */
4866 print_operands (buf
, opcode
, inst_base
->operands
);
4868 output_info (_(" %s"), buf
);
4874 case AARCH64_OPDE_UNTIED_OPERAND
:
4875 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4876 detail
->index
+ 1, str
);
4879 case AARCH64_OPDE_OUT_OF_RANGE
:
4880 if (detail
->data
[0] != detail
->data
[1])
4881 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4882 detail
->error
? detail
->error
: _("immediate value"),
4883 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4885 handler (_("%s must be %d at operand %d -- `%s'"),
4886 detail
->error
? detail
->error
: _("immediate value"),
4887 detail
->data
[0], idx
+ 1, str
);
4890 case AARCH64_OPDE_REG_LIST
:
4891 if (detail
->data
[0] == 1)
4892 handler (_("invalid number of registers in the list; "
4893 "only 1 register is expected at operand %d -- `%s'"),
4896 handler (_("invalid number of registers in the list; "
4897 "%d registers are expected at operand %d -- `%s'"),
4898 detail
->data
[0], idx
+ 1, str
);
4901 case AARCH64_OPDE_UNALIGNED
:
4902 handler (_("immediate value must be a multiple of "
4903 "%d at operand %d -- `%s'"),
4904 detail
->data
[0], idx
+ 1, str
);
4913 /* Process and output the error message about the operand mismatching.
4915 When this function is called, the operand error information had
4916 been collected for an assembly line and there will be multiple
4917 errors in the case of multiple instruction templates; output the
4918 error message that most closely describes the problem.
4920 The errors to be printed can be filtered on printing all errors
4921 or only non-fatal errors. This distinction has to be made because
4922 the error buffer may already be filled with fatal errors we don't want to
4923 print due to the different instruction templates. */
4926 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4928 int largest_error_pos
;
4929 const char *msg
= NULL
;
4930 enum aarch64_operand_error_kind kind
;
4931 operand_error_record
*curr
;
4932 operand_error_record
*head
= operand_error_report
.head
;
4933 operand_error_record
*record
= NULL
;
4935 /* No error to report. */
4939 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4941 /* Only one error. */
4942 if (head
== operand_error_report
.tail
)
4944 /* If the only error is a non-fatal one and we don't want to print it,
4946 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4948 DEBUG_TRACE ("single opcode entry with error kind: %s",
4949 operand_mismatch_kind_names
[head
->detail
.kind
]);
4950 output_operand_error_record (head
, str
);
4955 /* Find the error kind of the highest severity. */
4956 DEBUG_TRACE ("multiple opcode entries with error kind");
4957 kind
= AARCH64_OPDE_NIL
;
4958 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4960 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4961 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4962 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4963 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4964 kind
= curr
->detail
.kind
;
4967 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4969 /* Pick up one of errors of KIND to report. */
4970 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4971 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4973 /* If we don't want to print non-fatal errors then don't consider them
4975 if (curr
->detail
.kind
!= kind
4976 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4978 /* If there are multiple errors, pick up the one with the highest
4979 mismatching operand index. In the case of multiple errors with
4980 the equally highest operand index, pick up the first one or the
4981 first one with non-NULL error message. */
4982 if (curr
->detail
.index
> largest_error_pos
4983 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4984 && curr
->detail
.error
!= NULL
))
4986 largest_error_pos
= curr
->detail
.index
;
4988 msg
= record
->detail
.error
;
4992 /* The way errors are collected in the back-end is a bit non-intuitive. But
4993 essentially, because each operand template is tried recursively you may
4994 always have errors collected from the previous tried OPND. These are
4995 usually skipped if there is one successful match. However now with the
4996 non-fatal errors we have to ignore those previously collected hard errors
4997 when we're only interested in printing the non-fatal ones. This condition
4998 prevents us from printing errors that are not appropriate, since we did
4999 match a condition, but it also has warnings that it wants to print. */
5000 if (non_fatal_only
&& !record
)
5003 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5004 DEBUG_TRACE ("Pick up error kind %s to report",
5005 operand_mismatch_kind_names
[record
->detail
.kind
]);
5008 output_operand_error_record (record
, str
);
5011 /* Write an AARCH64 instruction to buf - always little-endian. */
5013 put_aarch64_insn (char *buf
, uint32_t insn
)
5015 unsigned char *where
= (unsigned char *) buf
;
5017 where
[1] = insn
>> 8;
5018 where
[2] = insn
>> 16;
5019 where
[3] = insn
>> 24;
5023 get_aarch64_insn (char *buf
)
5025 unsigned char *where
= (unsigned char *) buf
;
5027 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
5032 output_inst (struct aarch64_inst
*new_inst
)
5036 to
= frag_more (INSN_SIZE
);
5038 frag_now
->tc_frag_data
.recorded
= 1;
5040 put_aarch64_insn (to
, inst
.base
.value
);
5042 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5044 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5045 INSN_SIZE
, &inst
.reloc
.exp
,
5048 DEBUG_TRACE ("Prepared relocation fix up");
5049 /* Don't check the addend value against the instruction size,
5050 that's the job of our code in md_apply_fix(). */
5051 fixp
->fx_no_overflow
= 1;
5052 if (new_inst
!= NULL
)
5053 fixp
->tc_fix_data
.inst
= new_inst
;
5054 if (aarch64_gas_internal_fixup_p ())
5056 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5057 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5058 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5062 dwarf2_emit_insn (INSN_SIZE
);
5065 /* Link together opcodes of the same name. */
5069 aarch64_opcode
*opcode
;
5070 struct templates
*next
;
5073 typedef struct templates templates
;
5076 lookup_mnemonic (const char *start
, int len
)
5078 templates
*templ
= NULL
;
5080 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
5084 /* Subroutine of md_assemble, responsible for looking up the primary
5085 opcode from the mnemonic the user wrote. STR points to the
5086 beginning of the mnemonic. */
5089 opcode_lookup (char **str
)
5091 char *end
, *base
, *dot
;
5092 const aarch64_cond
*cond
;
5096 /* Scan up to the end of the mnemonic, which must end in white space,
5097 '.', or end of string. */
5099 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5100 if (*end
== '.' && !dot
)
5103 if (end
== base
|| dot
== base
)
5106 inst
.cond
= COND_ALWAYS
;
5108 /* Handle a possible condition. */
5111 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5114 inst
.cond
= cond
->value
;
5130 if (inst
.cond
== COND_ALWAYS
)
5132 /* Look for unaffixed mnemonic. */
5133 return lookup_mnemonic (base
, len
);
5137 /* append ".c" to mnemonic if conditional */
5138 memcpy (condname
, base
, len
);
5139 memcpy (condname
+ len
, ".c", 2);
5142 return lookup_mnemonic (base
, len
);
5148 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5149 to a corresponding operand qualifier. */
5151 static inline aarch64_opnd_qualifier_t
5152 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5154 /* Element size in bytes indexed by vector_el_type. */
5155 const unsigned char ele_size
[5]
5157 const unsigned int ele_base
[5] =
5159 AARCH64_OPND_QLF_V_4B
,
5160 AARCH64_OPND_QLF_V_2H
,
5161 AARCH64_OPND_QLF_V_2S
,
5162 AARCH64_OPND_QLF_V_1D
,
5163 AARCH64_OPND_QLF_V_1Q
5166 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5167 goto vectype_conversion_fail
;
5169 if (vectype
->type
== NT_zero
)
5170 return AARCH64_OPND_QLF_P_Z
;
5171 if (vectype
->type
== NT_merge
)
5172 return AARCH64_OPND_QLF_P_M
;
5174 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5176 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5178 /* Special case S_4B. */
5179 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5180 return AARCH64_OPND_QLF_S_4B
;
5182 /* Special case S_2H. */
5183 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5184 return AARCH64_OPND_QLF_S_2H
;
5186 /* Vector element register. */
5187 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5191 /* Vector register. */
5192 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5195 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5196 goto vectype_conversion_fail
;
5198 /* The conversion is by calculating the offset from the base operand
5199 qualifier for the vector type. The operand qualifiers are regular
5200 enough that the offset can established by shifting the vector width by
5201 a vector-type dependent amount. */
5203 if (vectype
->type
== NT_b
)
5205 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5207 else if (vectype
->type
>= NT_d
)
5212 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5213 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5214 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5218 vectype_conversion_fail
:
5219 first_error (_("bad vector arrangement type"));
5220 return AARCH64_OPND_QLF_NIL
;
5223 /* Process an optional operand that is found omitted from the assembly line.
5224 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5225 instruction's opcode entry while IDX is the index of this omitted operand.
5229 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5230 int idx
, aarch64_opnd_info
*operand
)
5232 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5233 gas_assert (optional_operand_p (opcode
, idx
));
5234 gas_assert (!operand
->present
);
5238 case AARCH64_OPND_Rd
:
5239 case AARCH64_OPND_Rn
:
5240 case AARCH64_OPND_Rm
:
5241 case AARCH64_OPND_Rt
:
5242 case AARCH64_OPND_Rt2
:
5243 case AARCH64_OPND_Rt_SP
:
5244 case AARCH64_OPND_Rs
:
5245 case AARCH64_OPND_Ra
:
5246 case AARCH64_OPND_Rt_SYS
:
5247 case AARCH64_OPND_Rd_SP
:
5248 case AARCH64_OPND_Rn_SP
:
5249 case AARCH64_OPND_Rm_SP
:
5250 case AARCH64_OPND_Fd
:
5251 case AARCH64_OPND_Fn
:
5252 case AARCH64_OPND_Fm
:
5253 case AARCH64_OPND_Fa
:
5254 case AARCH64_OPND_Ft
:
5255 case AARCH64_OPND_Ft2
:
5256 case AARCH64_OPND_Sd
:
5257 case AARCH64_OPND_Sn
:
5258 case AARCH64_OPND_Sm
:
5259 case AARCH64_OPND_Va
:
5260 case AARCH64_OPND_Vd
:
5261 case AARCH64_OPND_Vn
:
5262 case AARCH64_OPND_Vm
:
5263 case AARCH64_OPND_VdD1
:
5264 case AARCH64_OPND_VnD1
:
5265 operand
->reg
.regno
= default_value
;
5268 case AARCH64_OPND_Ed
:
5269 case AARCH64_OPND_En
:
5270 case AARCH64_OPND_Em
:
5271 case AARCH64_OPND_Em16
:
5272 case AARCH64_OPND_SM3_IMM2
:
5273 operand
->reglane
.regno
= default_value
;
5276 case AARCH64_OPND_IDX
:
5277 case AARCH64_OPND_BIT_NUM
:
5278 case AARCH64_OPND_IMMR
:
5279 case AARCH64_OPND_IMMS
:
5280 case AARCH64_OPND_SHLL_IMM
:
5281 case AARCH64_OPND_IMM_VLSL
:
5282 case AARCH64_OPND_IMM_VLSR
:
5283 case AARCH64_OPND_CCMP_IMM
:
5284 case AARCH64_OPND_FBITS
:
5285 case AARCH64_OPND_UIMM4
:
5286 case AARCH64_OPND_UIMM3_OP1
:
5287 case AARCH64_OPND_UIMM3_OP2
:
5288 case AARCH64_OPND_IMM
:
5289 case AARCH64_OPND_IMM_2
:
5290 case AARCH64_OPND_WIDTH
:
5291 case AARCH64_OPND_UIMM7
:
5292 case AARCH64_OPND_NZCV
:
5293 case AARCH64_OPND_SVE_PATTERN
:
5294 case AARCH64_OPND_SVE_PRFOP
:
5295 operand
->imm
.value
= default_value
;
5298 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5299 operand
->imm
.value
= default_value
;
5300 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5301 operand
->shifter
.amount
= 1;
5304 case AARCH64_OPND_EXCEPTION
:
5305 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5308 case AARCH64_OPND_BARRIER_ISB
:
5309 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5312 case AARCH64_OPND_BTI_TARGET
:
5313 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5321 /* Process the relocation type for move wide instructions.
5322 Return TRUE on success; otherwise return FALSE. */
5325 process_movw_reloc_info (void)
5330 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5332 if (inst
.base
.opcode
->op
== OP_MOVK
)
5333 switch (inst
.reloc
.type
)
5335 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5336 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5337 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5338 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5339 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5340 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5341 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5342 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5343 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5344 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5345 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5347 (_("the specified relocation type is not allowed for MOVK"));
5353 switch (inst
.reloc
.type
)
5355 case BFD_RELOC_AARCH64_MOVW_G0
:
5356 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5357 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5358 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5359 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5360 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5361 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5362 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5363 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5364 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5365 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5366 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5367 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5370 case BFD_RELOC_AARCH64_MOVW_G1
:
5371 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5372 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5373 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5374 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5375 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5376 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5377 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5378 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5379 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5380 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5381 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5382 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5385 case BFD_RELOC_AARCH64_MOVW_G2
:
5386 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5387 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5388 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5389 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5390 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5391 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5394 set_fatal_syntax_error
5395 (_("the specified relocation type is not allowed for 32-bit "
5401 case BFD_RELOC_AARCH64_MOVW_G3
:
5402 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5405 set_fatal_syntax_error
5406 (_("the specified relocation type is not allowed for 32-bit "
5413 /* More cases should be added when more MOVW-related relocation types
5414 are supported in GAS. */
5415 gas_assert (aarch64_gas_internal_fixup_p ());
5416 /* The shift amount should have already been set by the parser. */
5419 inst
.base
.operands
[1].shifter
.amount
= shift
;
5423 /* A primitive log calculator. */
5425 static inline unsigned int
5426 get_logsz (unsigned int size
)
5428 const unsigned char ls
[16] =
5429 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5435 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5436 return ls
[size
- 1];
5439 /* Determine and return the real reloc type code for an instruction
5440 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5442 static inline bfd_reloc_code_real_type
5443 ldst_lo12_determine_real_reloc_type (void)
5446 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5447 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5449 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5451 BFD_RELOC_AARCH64_LDST8_LO12
,
5452 BFD_RELOC_AARCH64_LDST16_LO12
,
5453 BFD_RELOC_AARCH64_LDST32_LO12
,
5454 BFD_RELOC_AARCH64_LDST64_LO12
,
5455 BFD_RELOC_AARCH64_LDST128_LO12
5458 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5459 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5460 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5461 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5462 BFD_RELOC_AARCH64_NONE
5465 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5466 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5467 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5468 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5469 BFD_RELOC_AARCH64_NONE
5472 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5473 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5474 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5475 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5476 BFD_RELOC_AARCH64_NONE
5479 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5480 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5481 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5482 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5483 BFD_RELOC_AARCH64_NONE
5487 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5488 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5490 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5492 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5494 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5495 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5497 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5499 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5501 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5503 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5504 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5505 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5506 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5507 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5508 gas_assert (logsz
<= 3);
5510 gas_assert (logsz
<= 4);
5512 /* In reloc.c, these pseudo relocation types should be defined in similar
5513 order as above reloc_ldst_lo12 array. Because the array index calculation
5514 below relies on this. */
5515 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5518 /* Check whether a register list REGINFO is valid. The registers must be
5519 numbered in increasing order (modulo 32), in increments of one or two.
5521 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5524 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5527 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5529 uint32_t i
, nb_regs
, prev_regno
, incr
;
5531 nb_regs
= 1 + (reginfo
& 0x3);
5533 prev_regno
= reginfo
& 0x1f;
5534 incr
= accept_alternate
? 2 : 1;
5536 for (i
= 1; i
< nb_regs
; ++i
)
5538 uint32_t curr_regno
;
5540 curr_regno
= reginfo
& 0x1f;
5541 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5543 prev_regno
= curr_regno
;
5549 /* Generic instruction operand parser. This does no encoding and no
5550 semantic validation; it merely squirrels values away in the inst
5551 structure. Returns TRUE or FALSE depending on whether the
5552 specified grammar matched. */
5555 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5558 char *backtrack_pos
= 0;
5559 const enum aarch64_opnd
*operands
= opcode
->operands
;
5560 aarch64_reg_type imm_reg_type
;
5563 skip_whitespace (str
);
5565 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5566 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5568 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5570 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5573 const reg_entry
*reg
;
5574 int comma_skipped_p
= 0;
5575 aarch64_reg_type rtype
;
5576 struct vector_type_el vectype
;
5577 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5578 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5579 aarch64_reg_type reg_type
;
5581 DEBUG_TRACE ("parse operand %d", i
);
5583 /* Assign the operand code. */
5584 info
->type
= operands
[i
];
5586 if (optional_operand_p (opcode
, i
))
5588 /* Remember where we are in case we need to backtrack. */
5589 gas_assert (!backtrack_pos
);
5590 backtrack_pos
= str
;
5593 /* Expect comma between operands; the backtrack mechanism will take
5594 care of cases of omitted optional operand. */
5595 if (i
> 0 && ! skip_past_char (&str
, ','))
5597 set_syntax_error (_("comma expected between operands"));
5601 comma_skipped_p
= 1;
5603 switch (operands
[i
])
5605 case AARCH64_OPND_Rd
:
5606 case AARCH64_OPND_Rn
:
5607 case AARCH64_OPND_Rm
:
5608 case AARCH64_OPND_Rt
:
5609 case AARCH64_OPND_Rt2
:
5610 case AARCH64_OPND_Rs
:
5611 case AARCH64_OPND_Ra
:
5612 case AARCH64_OPND_Rt_SYS
:
5613 case AARCH64_OPND_PAIRREG
:
5614 case AARCH64_OPND_SVE_Rm
:
5615 po_int_reg_or_fail (REG_TYPE_R_Z
);
5618 case AARCH64_OPND_Rd_SP
:
5619 case AARCH64_OPND_Rn_SP
:
5620 case AARCH64_OPND_Rt_SP
:
5621 case AARCH64_OPND_SVE_Rn_SP
:
5622 case AARCH64_OPND_Rm_SP
:
5623 po_int_reg_or_fail (REG_TYPE_R_SP
);
5626 case AARCH64_OPND_Rm_EXT
:
5627 case AARCH64_OPND_Rm_SFT
:
5628 po_misc_or_fail (parse_shifter_operand
5629 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5631 : SHIFTED_LOGIC_IMM
)));
5632 if (!info
->shifter
.operator_present
)
5634 /* Default to LSL if not present. Libopcodes prefers shifter
5635 kind to be explicit. */
5636 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5637 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5638 /* For Rm_EXT, libopcodes will carry out further check on whether
5639 or not stack pointer is used in the instruction (Recall that
5640 "the extend operator is not optional unless at least one of
5641 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5645 case AARCH64_OPND_Fd
:
5646 case AARCH64_OPND_Fn
:
5647 case AARCH64_OPND_Fm
:
5648 case AARCH64_OPND_Fa
:
5649 case AARCH64_OPND_Ft
:
5650 case AARCH64_OPND_Ft2
:
5651 case AARCH64_OPND_Sd
:
5652 case AARCH64_OPND_Sn
:
5653 case AARCH64_OPND_Sm
:
5654 case AARCH64_OPND_SVE_VZn
:
5655 case AARCH64_OPND_SVE_Vd
:
5656 case AARCH64_OPND_SVE_Vm
:
5657 case AARCH64_OPND_SVE_Vn
:
5658 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5659 if (val
== PARSE_FAIL
)
5661 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5664 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5666 info
->reg
.regno
= val
;
5667 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5670 case AARCH64_OPND_SVE_Pd
:
5671 case AARCH64_OPND_SVE_Pg3
:
5672 case AARCH64_OPND_SVE_Pg4_5
:
5673 case AARCH64_OPND_SVE_Pg4_10
:
5674 case AARCH64_OPND_SVE_Pg4_16
:
5675 case AARCH64_OPND_SVE_Pm
:
5676 case AARCH64_OPND_SVE_Pn
:
5677 case AARCH64_OPND_SVE_Pt
:
5678 reg_type
= REG_TYPE_PN
;
5681 case AARCH64_OPND_SVE_Za_5
:
5682 case AARCH64_OPND_SVE_Za_16
:
5683 case AARCH64_OPND_SVE_Zd
:
5684 case AARCH64_OPND_SVE_Zm_5
:
5685 case AARCH64_OPND_SVE_Zm_16
:
5686 case AARCH64_OPND_SVE_Zn
:
5687 case AARCH64_OPND_SVE_Zt
:
5688 reg_type
= REG_TYPE_ZN
;
5691 case AARCH64_OPND_Va
:
5692 case AARCH64_OPND_Vd
:
5693 case AARCH64_OPND_Vn
:
5694 case AARCH64_OPND_Vm
:
5695 reg_type
= REG_TYPE_VN
;
5697 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5698 if (val
== PARSE_FAIL
)
5700 first_error (_(get_reg_expected_msg (reg_type
)));
5703 if (vectype
.defined
& NTA_HASINDEX
)
5706 info
->reg
.regno
= val
;
5707 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5708 && vectype
.type
== NT_invtype
)
5709 /* Unqualified Pn and Zn registers are allowed in certain
5710 contexts. Rely on F_STRICT qualifier checking to catch
5712 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5715 info
->qualifier
= vectype_to_qualifier (&vectype
);
5716 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5721 case AARCH64_OPND_VdD1
:
5722 case AARCH64_OPND_VnD1
:
5723 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5724 if (val
== PARSE_FAIL
)
5726 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5729 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5731 set_fatal_syntax_error
5732 (_("the top half of a 128-bit FP/SIMD register is expected"));
5735 info
->reg
.regno
= val
;
5736 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5737 here; it is correct for the purpose of encoding/decoding since
5738 only the register number is explicitly encoded in the related
5739 instructions, although this appears a bit hacky. */
5740 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5743 case AARCH64_OPND_SVE_Zm3_INDEX
:
5744 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5745 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5746 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5747 case AARCH64_OPND_SVE_Zm4_INDEX
:
5748 case AARCH64_OPND_SVE_Zn_INDEX
:
5749 reg_type
= REG_TYPE_ZN
;
5750 goto vector_reg_index
;
5752 case AARCH64_OPND_Ed
:
5753 case AARCH64_OPND_En
:
5754 case AARCH64_OPND_Em
:
5755 case AARCH64_OPND_Em16
:
5756 case AARCH64_OPND_SM3_IMM2
:
5757 reg_type
= REG_TYPE_VN
;
5759 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5760 if (val
== PARSE_FAIL
)
5762 first_error (_(get_reg_expected_msg (reg_type
)));
5765 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5768 info
->reglane
.regno
= val
;
5769 info
->reglane
.index
= vectype
.index
;
5770 info
->qualifier
= vectype_to_qualifier (&vectype
);
5771 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5775 case AARCH64_OPND_SVE_ZnxN
:
5776 case AARCH64_OPND_SVE_ZtxN
:
5777 reg_type
= REG_TYPE_ZN
;
5778 goto vector_reg_list
;
5780 case AARCH64_OPND_LVn
:
5781 case AARCH64_OPND_LVt
:
5782 case AARCH64_OPND_LVt_AL
:
5783 case AARCH64_OPND_LEt
:
5784 reg_type
= REG_TYPE_VN
;
5786 if (reg_type
== REG_TYPE_ZN
5787 && get_opcode_dependent_value (opcode
) == 1
5790 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5791 if (val
== PARSE_FAIL
)
5793 first_error (_(get_reg_expected_msg (reg_type
)));
5796 info
->reglist
.first_regno
= val
;
5797 info
->reglist
.num_regs
= 1;
5801 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5802 if (val
== PARSE_FAIL
)
5805 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5807 set_fatal_syntax_error (_("invalid register list"));
5811 if (vectype
.width
!= 0 && *str
!= ',')
5813 set_fatal_syntax_error
5814 (_("expected element type rather than vector type"));
5818 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5819 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5821 if (operands
[i
] == AARCH64_OPND_LEt
)
5823 if (!(vectype
.defined
& NTA_HASINDEX
))
5825 info
->reglist
.has_index
= 1;
5826 info
->reglist
.index
= vectype
.index
;
5830 if (vectype
.defined
& NTA_HASINDEX
)
5832 if (!(vectype
.defined
& NTA_HASTYPE
))
5834 if (reg_type
== REG_TYPE_ZN
)
5835 set_fatal_syntax_error (_("missing type suffix"));
5839 info
->qualifier
= vectype_to_qualifier (&vectype
);
5840 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5844 case AARCH64_OPND_CRn
:
5845 case AARCH64_OPND_CRm
:
5847 char prefix
= *(str
++);
5848 if (prefix
!= 'c' && prefix
!= 'C')
5851 po_imm_nc_or_fail ();
5854 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5857 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5858 info
->imm
.value
= val
;
5862 case AARCH64_OPND_SHLL_IMM
:
5863 case AARCH64_OPND_IMM_VLSR
:
5864 po_imm_or_fail (1, 64);
5865 info
->imm
.value
= val
;
5868 case AARCH64_OPND_CCMP_IMM
:
5869 case AARCH64_OPND_SIMM5
:
5870 case AARCH64_OPND_FBITS
:
5871 case AARCH64_OPND_TME_UIMM16
:
5872 case AARCH64_OPND_UIMM4
:
5873 case AARCH64_OPND_UIMM4_ADDG
:
5874 case AARCH64_OPND_UIMM10
:
5875 case AARCH64_OPND_UIMM3_OP1
:
5876 case AARCH64_OPND_UIMM3_OP2
:
5877 case AARCH64_OPND_IMM_VLSL
:
5878 case AARCH64_OPND_IMM
:
5879 case AARCH64_OPND_IMM_2
:
5880 case AARCH64_OPND_WIDTH
:
5881 case AARCH64_OPND_SVE_INV_LIMM
:
5882 case AARCH64_OPND_SVE_LIMM
:
5883 case AARCH64_OPND_SVE_LIMM_MOV
:
5884 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5885 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5886 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5887 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5888 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5889 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5890 case AARCH64_OPND_SVE_SIMM5
:
5891 case AARCH64_OPND_SVE_SIMM5B
:
5892 case AARCH64_OPND_SVE_SIMM6
:
5893 case AARCH64_OPND_SVE_SIMM8
:
5894 case AARCH64_OPND_SVE_UIMM3
:
5895 case AARCH64_OPND_SVE_UIMM7
:
5896 case AARCH64_OPND_SVE_UIMM8
:
5897 case AARCH64_OPND_SVE_UIMM8_53
:
5898 case AARCH64_OPND_IMM_ROT1
:
5899 case AARCH64_OPND_IMM_ROT2
:
5900 case AARCH64_OPND_IMM_ROT3
:
5901 case AARCH64_OPND_SVE_IMM_ROT1
:
5902 case AARCH64_OPND_SVE_IMM_ROT2
:
5903 case AARCH64_OPND_SVE_IMM_ROT3
:
5904 po_imm_nc_or_fail ();
5905 info
->imm
.value
= val
;
5908 case AARCH64_OPND_SVE_AIMM
:
5909 case AARCH64_OPND_SVE_ASIMM
:
5910 po_imm_nc_or_fail ();
5911 info
->imm
.value
= val
;
5912 skip_whitespace (str
);
5913 if (skip_past_comma (&str
))
5914 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5916 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5919 case AARCH64_OPND_SVE_PATTERN
:
5920 po_enum_or_fail (aarch64_sve_pattern_array
);
5921 info
->imm
.value
= val
;
5924 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5925 po_enum_or_fail (aarch64_sve_pattern_array
);
5926 info
->imm
.value
= val
;
5927 if (skip_past_comma (&str
)
5928 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5930 if (!info
->shifter
.operator_present
)
5932 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5933 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5934 info
->shifter
.amount
= 1;
5938 case AARCH64_OPND_SVE_PRFOP
:
5939 po_enum_or_fail (aarch64_sve_prfop_array
);
5940 info
->imm
.value
= val
;
5943 case AARCH64_OPND_UIMM7
:
5944 po_imm_or_fail (0, 127);
5945 info
->imm
.value
= val
;
5948 case AARCH64_OPND_IDX
:
5949 case AARCH64_OPND_MASK
:
5950 case AARCH64_OPND_BIT_NUM
:
5951 case AARCH64_OPND_IMMR
:
5952 case AARCH64_OPND_IMMS
:
5953 po_imm_or_fail (0, 63);
5954 info
->imm
.value
= val
;
5957 case AARCH64_OPND_IMM0
:
5958 po_imm_nc_or_fail ();
5961 set_fatal_syntax_error (_("immediate zero expected"));
5964 info
->imm
.value
= 0;
5967 case AARCH64_OPND_FPIMM0
:
5970 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5971 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5972 it is probably not worth the effort to support it. */
5973 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5976 || !(res2
= parse_constant_immediate (&str
, &val
,
5979 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5981 info
->imm
.value
= 0;
5982 info
->imm
.is_fp
= 1;
5985 set_fatal_syntax_error (_("immediate zero expected"));
5989 case AARCH64_OPND_IMM_MOV
:
5992 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5993 reg_name_p (str
, REG_TYPE_VN
))
5996 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5998 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5999 later. fix_mov_imm_insn will try to determine a machine
6000 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6001 message if the immediate cannot be moved by a single
6003 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6004 inst
.base
.operands
[i
].skip
= 1;
6008 case AARCH64_OPND_SIMD_IMM
:
6009 case AARCH64_OPND_SIMD_IMM_SFT
:
6010 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6012 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6014 /* need_libopcodes_p */ 1,
6017 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6018 shift, we don't check it here; we leave the checking to
6019 the libopcodes (operand_general_constraint_met_p). By
6020 doing this, we achieve better diagnostics. */
6021 if (skip_past_comma (&str
)
6022 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6024 if (!info
->shifter
.operator_present
6025 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6027 /* Default to LSL if not present. Libopcodes prefers shifter
6028 kind to be explicit. */
6029 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6030 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6034 case AARCH64_OPND_FPIMM
:
6035 case AARCH64_OPND_SIMD_FPIMM
:
6036 case AARCH64_OPND_SVE_FPIMM8
:
6041 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6042 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6043 || !aarch64_imm_float_p (qfloat
))
6046 set_fatal_syntax_error (_("invalid floating-point"
6050 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6051 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6055 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6056 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6057 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6062 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6063 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6066 set_fatal_syntax_error (_("invalid floating-point"
6070 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6071 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6075 case AARCH64_OPND_LIMM
:
6076 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6077 SHIFTED_LOGIC_IMM
));
6078 if (info
->shifter
.operator_present
)
6080 set_fatal_syntax_error
6081 (_("shift not allowed for bitmask immediate"));
6084 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6086 /* need_libopcodes_p */ 1,
6090 case AARCH64_OPND_AIMM
:
6091 if (opcode
->op
== OP_ADD
)
6092 /* ADD may have relocation types. */
6093 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6094 SHIFTED_ARITH_IMM
));
6096 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6097 SHIFTED_ARITH_IMM
));
6098 switch (inst
.reloc
.type
)
6100 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6101 info
->shifter
.amount
= 12;
6103 case BFD_RELOC_UNUSED
:
6104 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6105 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6106 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6107 inst
.reloc
.pc_rel
= 0;
6112 info
->imm
.value
= 0;
6113 if (!info
->shifter
.operator_present
)
6115 /* Default to LSL if not present. Libopcodes prefers shifter
6116 kind to be explicit. */
6117 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6118 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6122 case AARCH64_OPND_HALF
:
6124 /* #<imm16> or relocation. */
6125 int internal_fixup_p
;
6126 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6127 if (internal_fixup_p
)
6128 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6129 skip_whitespace (str
);
6130 if (skip_past_comma (&str
))
6132 /* {, LSL #<shift>} */
6133 if (! aarch64_gas_internal_fixup_p ())
6135 set_fatal_syntax_error (_("can't mix relocation modifier "
6136 "with explicit shift"));
6139 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6142 inst
.base
.operands
[i
].shifter
.amount
= 0;
6143 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6144 inst
.base
.operands
[i
].imm
.value
= 0;
6145 if (! process_movw_reloc_info ())
6150 case AARCH64_OPND_EXCEPTION
:
6151 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6153 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6155 /* need_libopcodes_p */ 0,
6159 case AARCH64_OPND_NZCV
:
6161 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6165 info
->imm
.value
= nzcv
->value
;
6168 po_imm_or_fail (0, 15);
6169 info
->imm
.value
= val
;
6173 case AARCH64_OPND_COND
:
6174 case AARCH64_OPND_COND1
:
6179 while (ISALPHA (*str
));
6180 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6181 if (info
->cond
== NULL
)
6183 set_syntax_error (_("invalid condition"));
6186 else if (operands
[i
] == AARCH64_OPND_COND1
6187 && (info
->cond
->value
& 0xe) == 0xe)
6189 /* Do not allow AL or NV. */
6190 set_default_error ();
6196 case AARCH64_OPND_ADDR_ADRP
:
6197 po_misc_or_fail (parse_adrp (&str
));
6198 /* Clear the value as operand needs to be relocated. */
6199 info
->imm
.value
= 0;
6202 case AARCH64_OPND_ADDR_PCREL14
:
6203 case AARCH64_OPND_ADDR_PCREL19
:
6204 case AARCH64_OPND_ADDR_PCREL21
:
6205 case AARCH64_OPND_ADDR_PCREL26
:
6206 po_misc_or_fail (parse_address (&str
, info
));
6207 if (!info
->addr
.pcrel
)
6209 set_syntax_error (_("invalid pc-relative address"));
6212 if (inst
.gen_lit_pool
6213 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6215 /* Only permit "=value" in the literal load instructions.
6216 The literal will be generated by programmer_friendly_fixup. */
6217 set_syntax_error (_("invalid use of \"=immediate\""));
6220 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6222 set_syntax_error (_("unrecognized relocation suffix"));
6225 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6227 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6228 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6232 info
->imm
.value
= 0;
6233 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6234 switch (opcode
->iclass
)
6238 /* e.g. CBZ or B.COND */
6239 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6240 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6244 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6245 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6249 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6251 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6252 : BFD_RELOC_AARCH64_JUMP26
;
6255 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6256 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6259 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6260 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6266 inst
.reloc
.pc_rel
= 1;
6270 case AARCH64_OPND_ADDR_SIMPLE
:
6271 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6273 /* [<Xn|SP>{, #<simm>}] */
6275 /* First use the normal address-parsing routines, to get
6276 the usual syntax errors. */
6277 po_misc_or_fail (parse_address (&str
, info
));
6278 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6279 || !info
->addr
.preind
|| info
->addr
.postind
6280 || info
->addr
.writeback
)
6282 set_syntax_error (_("invalid addressing mode"));
6286 /* Then retry, matching the specific syntax of these addresses. */
6288 po_char_or_fail ('[');
6289 po_reg_or_fail (REG_TYPE_R64_SP
);
6290 /* Accept optional ", #0". */
6291 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6292 && skip_past_char (&str
, ','))
6294 skip_past_char (&str
, '#');
6295 if (! skip_past_char (&str
, '0'))
6297 set_fatal_syntax_error
6298 (_("the optional immediate offset can only be 0"));
6302 po_char_or_fail (']');
6306 case AARCH64_OPND_ADDR_REGOFF
:
6307 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6308 po_misc_or_fail (parse_address (&str
, info
));
6310 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6311 || !info
->addr
.preind
|| info
->addr
.postind
6312 || info
->addr
.writeback
)
6314 set_syntax_error (_("invalid addressing mode"));
6317 if (!info
->shifter
.operator_present
)
6319 /* Default to LSL if not present. Libopcodes prefers shifter
6320 kind to be explicit. */
6321 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6322 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6324 /* Qualifier to be deduced by libopcodes. */
6327 case AARCH64_OPND_ADDR_SIMM7
:
6328 po_misc_or_fail (parse_address (&str
, info
));
6329 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6330 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6332 set_syntax_error (_("invalid addressing mode"));
6335 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6337 set_syntax_error (_("relocation not allowed"));
6340 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6342 /* need_libopcodes_p */ 1,
6346 case AARCH64_OPND_ADDR_SIMM9
:
6347 case AARCH64_OPND_ADDR_SIMM9_2
:
6348 case AARCH64_OPND_ADDR_SIMM11
:
6349 case AARCH64_OPND_ADDR_SIMM13
:
6350 po_misc_or_fail (parse_address (&str
, info
));
6351 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6352 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6353 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6354 && info
->addr
.writeback
))
6356 set_syntax_error (_("invalid addressing mode"));
6359 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6361 set_syntax_error (_("relocation not allowed"));
6364 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6366 /* need_libopcodes_p */ 1,
6370 case AARCH64_OPND_ADDR_SIMM10
:
6371 case AARCH64_OPND_ADDR_OFFSET
:
6372 po_misc_or_fail (parse_address (&str
, info
));
6373 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6374 || !info
->addr
.preind
|| info
->addr
.postind
)
6376 set_syntax_error (_("invalid addressing mode"));
6379 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6381 set_syntax_error (_("relocation not allowed"));
6384 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6386 /* need_libopcodes_p */ 1,
6390 case AARCH64_OPND_ADDR_UIMM12
:
6391 po_misc_or_fail (parse_address (&str
, info
));
6392 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6393 || !info
->addr
.preind
|| info
->addr
.writeback
)
6395 set_syntax_error (_("invalid addressing mode"));
6398 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6399 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6400 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6402 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6404 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6406 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6408 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6409 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6410 /* Leave qualifier to be determined by libopcodes. */
6413 case AARCH64_OPND_SIMD_ADDR_POST
:
6414 /* [<Xn|SP>], <Xm|#<amount>> */
6415 po_misc_or_fail (parse_address (&str
, info
));
6416 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6418 set_syntax_error (_("invalid addressing mode"));
6421 if (!info
->addr
.offset
.is_reg
)
6423 if (inst
.reloc
.exp
.X_op
== O_constant
)
6424 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6427 set_fatal_syntax_error
6428 (_("writeback value must be an immediate constant"));
6435 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6436 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6437 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6438 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6439 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6440 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6441 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6442 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6443 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6444 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6445 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6446 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6447 /* [X<n>{, #imm, MUL VL}]
6449 but recognizing SVE registers. */
6450 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6451 &offset_qualifier
));
6452 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6454 set_syntax_error (_("invalid addressing mode"));
6458 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6459 || !info
->addr
.preind
|| info
->addr
.writeback
)
6461 set_syntax_error (_("invalid addressing mode"));
6464 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6465 || inst
.reloc
.exp
.X_op
!= O_constant
)
6467 /* Make sure this has priority over
6468 "invalid addressing mode". */
6469 set_fatal_syntax_error (_("constant offset required"));
6472 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6475 case AARCH64_OPND_SVE_ADDR_R
:
6476 /* [<Xn|SP>{, <R><m>}]
6477 but recognizing SVE registers. */
6478 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6479 &offset_qualifier
));
6480 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6482 offset_qualifier
= AARCH64_OPND_QLF_X
;
6483 info
->addr
.offset
.is_reg
= 1;
6484 info
->addr
.offset
.regno
= 31;
6486 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6487 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6489 set_syntax_error (_("invalid addressing mode"));
6494 case AARCH64_OPND_SVE_ADDR_RR
:
6495 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6496 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6497 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6498 case AARCH64_OPND_SVE_ADDR_RX
:
6499 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6500 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6501 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6502 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6503 but recognizing SVE registers. */
6504 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6505 &offset_qualifier
));
6506 if (base_qualifier
!= AARCH64_OPND_QLF_X
6507 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6509 set_syntax_error (_("invalid addressing mode"));
6514 case AARCH64_OPND_SVE_ADDR_RZ
:
6515 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6516 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6517 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6518 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6519 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6520 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6521 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6522 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6523 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6524 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6525 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6526 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6527 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6528 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6529 &offset_qualifier
));
6530 if (base_qualifier
!= AARCH64_OPND_QLF_X
6531 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6532 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6534 set_syntax_error (_("invalid addressing mode"));
6537 info
->qualifier
= offset_qualifier
;
6540 case AARCH64_OPND_SVE_ADDR_ZX
:
6541 /* [Zn.<T>{, <Xm>}]. */
6542 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6543 &offset_qualifier
));
6545 base_qualifier either S_S or S_D
6546 offset_qualifier must be X
6548 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6549 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6550 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6552 set_syntax_error (_("invalid addressing mode"));
6555 info
->qualifier
= base_qualifier
;
6556 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6557 || !info
->addr
.preind
|| info
->addr
.writeback
6558 || info
->shifter
.operator_present
!= 0)
6560 set_syntax_error (_("invalid addressing mode"));
6563 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6567 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6568 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6569 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6570 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6571 /* [Z<n>.<T>{, #imm}] */
6572 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6573 &offset_qualifier
));
6574 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6575 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6577 set_syntax_error (_("invalid addressing mode"));
6580 info
->qualifier
= base_qualifier
;
6583 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6584 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6585 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6586 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6587 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6591 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6593 here since we get better error messages by leaving it to
6594 the qualifier checking routines. */
6595 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6596 &offset_qualifier
));
6597 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6598 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6599 || offset_qualifier
!= base_qualifier
)
6601 set_syntax_error (_("invalid addressing mode"));
6604 info
->qualifier
= base_qualifier
;
6607 case AARCH64_OPND_SYSREG
:
6609 uint32_t sysreg_flags
;
6610 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6611 &sysreg_flags
)) == PARSE_FAIL
)
6613 set_syntax_error (_("unknown or missing system register name"));
6616 inst
.base
.operands
[i
].sysreg
.value
= val
;
6617 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6621 case AARCH64_OPND_PSTATEFIELD
:
6622 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6625 set_syntax_error (_("unknown or missing PSTATE field name"));
6628 inst
.base
.operands
[i
].pstatefield
= val
;
6631 case AARCH64_OPND_SYSREG_IC
:
6632 inst
.base
.operands
[i
].sysins_op
=
6633 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6636 case AARCH64_OPND_SYSREG_DC
:
6637 inst
.base
.operands
[i
].sysins_op
=
6638 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6641 case AARCH64_OPND_SYSREG_AT
:
6642 inst
.base
.operands
[i
].sysins_op
=
6643 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6646 case AARCH64_OPND_SYSREG_SR
:
6647 inst
.base
.operands
[i
].sysins_op
=
6648 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6651 case AARCH64_OPND_SYSREG_TLBI
:
6652 inst
.base
.operands
[i
].sysins_op
=
6653 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6655 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6657 set_fatal_syntax_error ( _("unknown or missing operation name"));
6662 case AARCH64_OPND_BARRIER
:
6663 case AARCH64_OPND_BARRIER_ISB
:
6664 val
= parse_barrier (&str
);
6665 if (val
!= PARSE_FAIL
6666 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6668 /* ISB only accepts options name 'sy'. */
6670 (_("the specified option is not accepted in ISB"));
6671 /* Turn off backtrack as this optional operand is present. */
6675 /* This is an extension to accept a 0..15 immediate. */
6676 if (val
== PARSE_FAIL
)
6677 po_imm_or_fail (0, 15);
6678 info
->barrier
= aarch64_barrier_options
+ val
;
6681 case AARCH64_OPND_PRFOP
:
6682 val
= parse_pldop (&str
);
6683 /* This is an extension to accept a 0..31 immediate. */
6684 if (val
== PARSE_FAIL
)
6685 po_imm_or_fail (0, 31);
6686 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6689 case AARCH64_OPND_BARRIER_PSB
:
6690 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6691 if (val
== PARSE_FAIL
)
6695 case AARCH64_OPND_BTI_TARGET
:
6696 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6697 if (val
== PARSE_FAIL
)
6702 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6705 /* If we get here, this operand was successfully parsed. */
6706 inst
.base
.operands
[i
].present
= 1;
6710 /* The parse routine should already have set the error, but in case
6711 not, set a default one here. */
6713 set_default_error ();
6715 if (! backtrack_pos
)
6716 goto parse_operands_return
;
6719 /* We reach here because this operand is marked as optional, and
6720 either no operand was supplied or the operand was supplied but it
6721 was syntactically incorrect. In the latter case we report an
6722 error. In the former case we perform a few more checks before
6723 dropping through to the code to insert the default operand. */
6725 char *tmp
= backtrack_pos
;
6726 char endchar
= END_OF_INSN
;
6728 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6730 skip_past_char (&tmp
, ',');
6732 if (*tmp
!= endchar
)
6733 /* The user has supplied an operand in the wrong format. */
6734 goto parse_operands_return
;
6736 /* Make sure there is not a comma before the optional operand.
6737 For example the fifth operand of 'sys' is optional:
6739 sys #0,c0,c0,#0, <--- wrong
6740 sys #0,c0,c0,#0 <--- correct. */
6741 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6743 set_fatal_syntax_error
6744 (_("unexpected comma before the omitted optional operand"));
6745 goto parse_operands_return
;
6749 /* Reaching here means we are dealing with an optional operand that is
6750 omitted from the assembly line. */
6751 gas_assert (optional_operand_p (opcode
, i
));
6753 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6755 /* Try again, skipping the optional operand at backtrack_pos. */
6756 str
= backtrack_pos
;
6759 /* Clear any error record after the omitted optional operand has been
6760 successfully handled. */
6764 /* Check if we have parsed all the operands. */
6765 if (*str
!= '\0' && ! error_p ())
6767 /* Set I to the index of the last present operand; this is
6768 for the purpose of diagnostics. */
6769 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6771 set_fatal_syntax_error
6772 (_("unexpected characters following instruction"));
6775 parse_operands_return
:
6779 DEBUG_TRACE ("parsing FAIL: %s - %s",
6780 operand_mismatch_kind_names
[get_error_kind ()],
6781 get_error_message ());
6782 /* Record the operand error properly; this is useful when there
6783 are multiple instruction templates for a mnemonic name, so that
6784 later on, we can select the error that most closely describes
6786 record_operand_error (opcode
, i
, get_error_kind (),
6787 get_error_message ());
6792 DEBUG_TRACE ("parsing SUCCESS");
6797 /* It does some fix-up to provide some programmer friendly feature while
6798 keeping the libopcodes happy, i.e. libopcodes only accepts
6799 the preferred architectural syntax.
6800 Return FALSE if there is any failure; otherwise return TRUE. */
6803 programmer_friendly_fixup (aarch64_instruction
*instr
)
6805 aarch64_inst
*base
= &instr
->base
;
6806 const aarch64_opcode
*opcode
= base
->opcode
;
6807 enum aarch64_op op
= opcode
->op
;
6808 aarch64_opnd_info
*operands
= base
->operands
;
6810 DEBUG_TRACE ("enter");
6812 switch (opcode
->iclass
)
6815 /* TBNZ Xn|Wn, #uimm6, label
6816 Test and Branch Not Zero: conditionally jumps to label if bit number
6817 uimm6 in register Xn is not zero. The bit number implies the width of
6818 the register, which may be written and should be disassembled as Wn if
6819 uimm is less than 32. */
6820 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6822 if (operands
[1].imm
.value
>= 32)
6824 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6828 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6832 /* LDR Wt, label | =value
6833 As a convenience assemblers will typically permit the notation
6834 "=value" in conjunction with the pc-relative literal load instructions
6835 to automatically place an immediate value or symbolic address in a
6836 nearby literal pool and generate a hidden label which references it.
6837 ISREG has been set to 0 in the case of =value. */
6838 if (instr
->gen_lit_pool
6839 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6841 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6842 if (op
== OP_LDRSW_LIT
)
6844 if (instr
->reloc
.exp
.X_op
!= O_constant
6845 && instr
->reloc
.exp
.X_op
!= O_big
6846 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6848 record_operand_error (opcode
, 1,
6849 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6850 _("constant expression expected"));
6853 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6855 record_operand_error (opcode
, 1,
6856 AARCH64_OPDE_OTHER_ERROR
,
6857 _("literal pool insertion failed"));
6865 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6866 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6867 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6868 A programmer-friendly assembler should accept a destination Xd in
6869 place of Wd, however that is not the preferred form for disassembly.
6871 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6872 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6873 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6874 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6879 /* In the 64-bit form, the final register operand is written as Wm
6880 for all but the (possibly omitted) UXTX/LSL and SXTX
6882 As a programmer-friendly assembler, we accept e.g.
6883 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6884 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6885 int idx
= aarch64_operand_index (opcode
->operands
,
6886 AARCH64_OPND_Rm_EXT
);
6887 gas_assert (idx
== 1 || idx
== 2);
6888 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6889 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6890 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6891 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6892 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6893 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6901 DEBUG_TRACE ("exit with SUCCESS");
6905 /* Check for loads and stores that will cause unpredictable behavior. */
6908 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6910 aarch64_inst
*base
= &instr
->base
;
6911 const aarch64_opcode
*opcode
= base
->opcode
;
6912 const aarch64_opnd_info
*opnds
= base
->operands
;
6913 switch (opcode
->iclass
)
6920 /* Loading/storing the base register is unpredictable if writeback. */
6921 if ((aarch64_get_operand_class (opnds
[0].type
)
6922 == AARCH64_OPND_CLASS_INT_REG
)
6923 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6924 && opnds
[1].addr
.base_regno
!= REG_SP
6925 /* Exempt STG/STZG/ST2G/STZ2G. */
6926 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6927 && opnds
[1].addr
.writeback
)
6928 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6932 case ldstnapair_offs
:
6933 case ldstpair_indexed
:
6934 /* Loading/storing the base register is unpredictable if writeback. */
6935 if ((aarch64_get_operand_class (opnds
[0].type
)
6936 == AARCH64_OPND_CLASS_INT_REG
)
6937 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6938 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6939 && opnds
[2].addr
.base_regno
!= REG_SP
6941 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6942 && opnds
[2].addr
.writeback
)
6943 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6944 /* Load operations must load different registers. */
6945 if ((opcode
->opcode
& (1 << 22))
6946 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6947 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6951 /* It is unpredictable if the destination and status registers are the
6953 if ((aarch64_get_operand_class (opnds
[0].type
)
6954 == AARCH64_OPND_CLASS_INT_REG
)
6955 && (aarch64_get_operand_class (opnds
[1].type
)
6956 == AARCH64_OPND_CLASS_INT_REG
)
6957 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6958 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6959 as_warn (_("unpredictable: identical transfer and status registers"
6971 force_automatic_sequence_close (void)
6973 if (now_instr_sequence
.instr
)
6975 as_warn (_("previous `%s' sequence has not been closed"),
6976 now_instr_sequence
.instr
->opcode
->name
);
6977 init_insn_sequence (NULL
, &now_instr_sequence
);
6981 /* A wrapper function to interface with libopcodes on encoding and
6982 record the error message if there is any.
6984 Return TRUE on success; otherwise return FALSE. */
6987 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6990 aarch64_operand_error error_info
;
6991 memset (&error_info
, '\0', sizeof (error_info
));
6992 error_info
.kind
= AARCH64_OPDE_NIL
;
6993 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6994 && !error_info
.non_fatal
)
6997 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6998 record_operand_error_info (opcode
, &error_info
);
6999 return error_info
.non_fatal
;
7002 #ifdef DEBUG_AARCH64
7004 dump_opcode_operands (const aarch64_opcode
*opcode
)
7007 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7009 aarch64_verbose ("\t\t opnd%d: %s", i
,
7010 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7011 ? aarch64_get_operand_name (opcode
->operands
[i
])
7012 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7016 #endif /* DEBUG_AARCH64 */
7018 /* This is the guts of the machine-dependent assembler. STR points to a
7019 machine dependent instruction. This function is supposed to emit
7020 the frags/bytes it assembles to. */
7023 md_assemble (char *str
)
7026 templates
*template;
7027 aarch64_opcode
*opcode
;
7028 aarch64_inst
*inst_base
;
7029 unsigned saved_cond
;
7031 /* Align the previous label if needed. */
7032 if (last_label_seen
!= NULL
)
7034 symbol_set_frag (last_label_seen
, frag_now
);
7035 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7036 S_SET_SEGMENT (last_label_seen
, now_seg
);
7039 /* Update the current insn_sequence from the segment. */
7040 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7042 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7044 DEBUG_TRACE ("\n\n");
7045 DEBUG_TRACE ("==============================");
7046 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7048 template = opcode_lookup (&p
);
7051 /* It wasn't an instruction, but it might be a register alias of
7052 the form alias .req reg directive. */
7053 if (!create_register_alias (str
, p
))
7054 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7059 skip_whitespace (p
);
7062 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7063 get_mnemonic_name (str
), str
);
7067 init_operand_error_report ();
7069 /* Sections are assumed to start aligned. In executable section, there is no
7070 MAP_DATA symbol pending. So we only align the address during
7071 MAP_DATA --> MAP_INSN transition.
7072 For other sections, this is not guaranteed. */
7073 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7074 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7075 frag_align_code (2, 0);
7077 saved_cond
= inst
.cond
;
7078 reset_aarch64_instruction (&inst
);
7079 inst
.cond
= saved_cond
;
7081 /* Iterate through all opcode entries with the same mnemonic name. */
7084 opcode
= template->opcode
;
7086 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7087 #ifdef DEBUG_AARCH64
7089 dump_opcode_operands (opcode
);
7090 #endif /* DEBUG_AARCH64 */
7092 mapping_state (MAP_INSN
);
7094 inst_base
= &inst
.base
;
7095 inst_base
->opcode
= opcode
;
7097 /* Truly conditionally executed instructions, e.g. b.cond. */
7098 if (opcode
->flags
& F_COND
)
7100 gas_assert (inst
.cond
!= COND_ALWAYS
);
7101 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7102 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7104 else if (inst
.cond
!= COND_ALWAYS
)
7106 /* It shouldn't arrive here, where the assembly looks like a
7107 conditional instruction but the found opcode is unconditional. */
7112 if (parse_operands (p
, opcode
)
7113 && programmer_friendly_fixup (&inst
)
7114 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7116 /* Check that this instruction is supported for this CPU. */
7117 if (!opcode
->avariant
7118 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7120 as_bad (_("selected processor does not support `%s'"), str
);
7124 warn_unpredictable_ldst (&inst
, str
);
7126 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7127 || !inst
.reloc
.need_libopcodes_p
)
7131 /* If there is relocation generated for the instruction,
7132 store the instruction information for the future fix-up. */
7133 struct aarch64_inst
*copy
;
7134 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7135 copy
= XNEW (struct aarch64_inst
);
7136 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7140 /* Issue non-fatal messages if any. */
7141 output_operand_error_report (str
, TRUE
);
7145 template = template->next
;
7146 if (template != NULL
)
7148 reset_aarch64_instruction (&inst
);
7149 inst
.cond
= saved_cond
;
7152 while (template != NULL
);
7154 /* Issue the error messages if any. */
7155 output_operand_error_report (str
, FALSE
);
7158 /* Various frobbings of labels and their addresses. */
7161 aarch64_start_line_hook (void)
7163 last_label_seen
= NULL
;
7167 aarch64_frob_label (symbolS
* sym
)
7169 last_label_seen
= sym
;
7171 dwarf2_emit_label (sym
);
7175 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7177 /* Check to see if we have a block to close. */
7178 force_automatic_sequence_close ();
7182 aarch64_data_in_code (void)
7184 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7186 *input_line_pointer
= '/';
7187 input_line_pointer
+= 5;
7188 *input_line_pointer
= 0;
7196 aarch64_canonicalize_symbol_name (char *name
)
7200 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7201 *(name
+ len
- 5) = 0;
7206 /* Table of all register names defined by default. The user can
7207 define additional names with .req. Note that all register names
7208 should appear in both upper and lowercase variants. Some registers
7209 also have mixed-case names. */
7211 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7212 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7213 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7214 #define REGSET16(p,t) \
7215 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7216 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7217 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7218 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7219 #define REGSET31(p,t) \
7221 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7222 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7223 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7224 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7225 #define REGSET(p,t) \
7226 REGSET31(p,t), REGNUM(p,31,t)
7228 /* These go into aarch64_reg_hsh hash-table. */
7229 static const reg_entry reg_names
[] = {
7230 /* Integer registers. */
7231 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7232 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7234 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7235 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7236 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7237 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7238 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7239 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7241 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7242 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7244 /* Floating-point single precision registers. */
7245 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7247 /* Floating-point double precision registers. */
7248 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7250 /* Floating-point half precision registers. */
7251 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7253 /* Floating-point byte precision registers. */
7254 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7256 /* Floating-point quad precision registers. */
7257 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7259 /* FP/SIMD registers. */
7260 REGSET (v
, VN
), REGSET (V
, VN
),
7262 /* SVE vector registers. */
7263 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7265 /* SVE predicate registers. */
7266 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7284 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7285 static const asm_nzcv nzcv_names
[] = {
7286 {"nzcv", B (n
, z
, c
, v
)},
7287 {"nzcV", B (n
, z
, c
, V
)},
7288 {"nzCv", B (n
, z
, C
, v
)},
7289 {"nzCV", B (n
, z
, C
, V
)},
7290 {"nZcv", B (n
, Z
, c
, v
)},
7291 {"nZcV", B (n
, Z
, c
, V
)},
7292 {"nZCv", B (n
, Z
, C
, v
)},
7293 {"nZCV", B (n
, Z
, C
, V
)},
7294 {"Nzcv", B (N
, z
, c
, v
)},
7295 {"NzcV", B (N
, z
, c
, V
)},
7296 {"NzCv", B (N
, z
, C
, v
)},
7297 {"NzCV", B (N
, z
, C
, V
)},
7298 {"NZcv", B (N
, Z
, c
, v
)},
7299 {"NZcV", B (N
, Z
, c
, V
)},
7300 {"NZCv", B (N
, Z
, C
, v
)},
7301 {"NZCV", B (N
, Z
, C
, V
)}
7314 /* MD interface: bits in the object file. */
7316 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7317 for use in the a.out file, and stores them in the array pointed to by buf.
7318 This knows about the endian-ness of the target machine and does
7319 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7320 2 (short) and 4 (long) Floating numbers are put out as a series of
7321 LITTLENUMS (shorts, here at least). */
7324 md_number_to_chars (char *buf
, valueT val
, int n
)
7326 if (target_big_endian
)
7327 number_to_chars_bigendian (buf
, val
, n
);
7329 number_to_chars_littleendian (buf
, val
, n
);
7332 /* MD interface: Sections. */
7334 /* Estimate the size of a frag before relaxing. Assume everything fits in
7338 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7344 /* Round up a section size to the appropriate boundary. */
7347 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7352 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7353 of an rs_align_code fragment.
7355 Here we fill the frag with the appropriate info for padding the
7356 output stream. The resulting frag will consist of a fixed (fr_fix)
7357 and of a repeating (fr_var) part.
7359 The fixed content is always emitted before the repeating content and
7360 these two parts are used as follows in constructing the output:
7361 - the fixed part will be used to align to a valid instruction word
7362 boundary, in case that we start at a misaligned address; as no
7363 executable instruction can live at the misaligned location, we
7364 simply fill with zeros;
7365 - the variable part will be used to cover the remaining padding and
7366 we fill using the AArch64 NOP instruction.
7368 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7369 enough storage space for up to 3 bytes for padding the back to a valid
7370 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7373 aarch64_handle_align (fragS
* fragP
)
7375 /* NOP = d503201f */
7376 /* AArch64 instructions are always little-endian. */
7377 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7379 int bytes
, fix
, noop_size
;
7382 if (fragP
->fr_type
!= rs_align_code
)
7385 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7386 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7389 gas_assert (fragP
->tc_frag_data
.recorded
);
7392 noop_size
= sizeof (aarch64_noop
);
7394 fix
= bytes
& (noop_size
- 1);
7398 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7402 fragP
->fr_fix
+= fix
;
7406 memcpy (p
, aarch64_noop
, noop_size
);
7407 fragP
->fr_var
= noop_size
;
7410 /* Perform target specific initialisation of a frag.
7411 Note - despite the name this initialisation is not done when the frag
7412 is created, but only when its type is assigned. A frag can be created
7413 and used a long time before its type is set, so beware of assuming that
7414 this initialisation is performed first. */
7418 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7419 int max_chars ATTRIBUTE_UNUSED
)
7423 #else /* OBJ_ELF is defined. */
7425 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7427 /* Record a mapping symbol for alignment frags. We will delete this
7428 later if the alignment ends up empty. */
7429 if (!fragP
->tc_frag_data
.recorded
)
7430 fragP
->tc_frag_data
.recorded
= 1;
7432 /* PR 21809: Do not set a mapping state for debug sections
7433 - it just confuses other tools. */
7434 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7437 switch (fragP
->fr_type
)
7441 mapping_state_2 (MAP_DATA
, max_chars
);
7444 /* PR 20364: We can get alignment frags in code sections,
7445 so do not just assume that we should use the MAP_DATA state. */
7446 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7449 mapping_state_2 (MAP_INSN
, max_chars
);
7456 /* Initialize the DWARF-2 unwind information for this procedure. */
7459 tc_aarch64_frame_initial_instructions (void)
7461 cfi_add_CFA_def_cfa (REG_SP
, 0);
7463 #endif /* OBJ_ELF */
7465 /* Convert REGNAME to a DWARF-2 register number. */
7468 tc_aarch64_regname_to_dw2regnum (char *regname
)
7470 const reg_entry
*reg
= parse_reg (®name
);
7476 case REG_TYPE_SP_32
:
7477 case REG_TYPE_SP_64
:
7487 return reg
->number
+ 64;
7495 /* Implement DWARF2_ADDR_SIZE. */
7498 aarch64_dwarf2_addr_size (void)
7500 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7504 return bfd_arch_bits_per_address (stdoutput
) / 8;
7507 /* MD interface: Symbol and relocation handling. */
7509 /* Return the address within the segment that a PC-relative fixup is
7510 relative to. For AArch64 PC-relative fixups applied to instructions
7511 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7514 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7516 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7518 /* If this is pc-relative and we are going to emit a relocation
7519 then we just want to put out any pipeline compensation that the linker
7520 will need. Otherwise we want to use the calculated base. */
7522 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7523 || aarch64_force_relocation (fixP
)))
7526 /* AArch64 should be consistent for all pc-relative relocations. */
7527 return base
+ AARCH64_PCREL_OFFSET
;
7530 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7531 Otherwise we have no need to default values of symbols. */
7534 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7537 if (name
[0] == '_' && name
[1] == 'G'
7538 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7542 if (symbol_find (name
))
7543 as_bad (_("GOT already in the symbol table"));
7545 GOT_symbol
= symbol_new (name
, undefined_section
,
7546 (valueT
) 0, &zero_address_frag
);
7556 /* Return non-zero if the indicated VALUE has overflowed the maximum
7557 range expressible by a unsigned number with the indicated number of
7561 unsigned_overflow (valueT value
, unsigned bits
)
7564 if (bits
>= sizeof (valueT
) * 8)
7566 lim
= (valueT
) 1 << bits
;
7567 return (value
>= lim
);
7571 /* Return non-zero if the indicated VALUE has overflowed the maximum
7572 range expressible by an signed number with the indicated number of
7576 signed_overflow (offsetT value
, unsigned bits
)
7579 if (bits
>= sizeof (offsetT
) * 8)
7581 lim
= (offsetT
) 1 << (bits
- 1);
7582 return (value
< -lim
|| value
>= lim
);
7585 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7586 unsigned immediate offset load/store instruction, try to encode it as
7587 an unscaled, 9-bit, signed immediate offset load/store instruction.
7588 Return TRUE if it is successful; otherwise return FALSE.
7590 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7591 in response to the standard LDR/STR mnemonics when the immediate offset is
7592 unambiguous, i.e. when it is negative or unaligned. */
7595 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7598 enum aarch64_op new_op
;
7599 const aarch64_opcode
*new_opcode
;
7601 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7603 switch (instr
->opcode
->op
)
7605 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7606 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7607 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7608 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7609 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7610 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7611 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7612 case OP_STR_POS
: new_op
= OP_STUR
; break;
7613 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7614 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7615 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7616 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7617 default: new_op
= OP_NIL
; break;
7620 if (new_op
== OP_NIL
)
7623 new_opcode
= aarch64_get_opcode (new_op
);
7624 gas_assert (new_opcode
!= NULL
);
7626 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7627 instr
->opcode
->op
, new_opcode
->op
);
7629 aarch64_replace_opcode (instr
, new_opcode
);
7631 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7632 qualifier matching may fail because the out-of-date qualifier will
7633 prevent the operand being updated with a new and correct qualifier. */
7634 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7635 AARCH64_OPND_ADDR_SIMM9
);
7636 gas_assert (idx
== 1);
7637 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7639 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7641 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7648 /* Called by fix_insn to fix a MOV immediate alias instruction.
7650 Operand for a generic move immediate instruction, which is an alias
7651 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7652 a 32-bit/64-bit immediate value into general register. An assembler error
7653 shall result if the immediate cannot be created by a single one of these
7654 instructions. If there is a choice, then to ensure reversability an
7655 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7658 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7660 const aarch64_opcode
*opcode
;
7662 /* Need to check if the destination is SP/ZR. The check has to be done
7663 before any aarch64_replace_opcode. */
7664 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7665 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7667 instr
->operands
[1].imm
.value
= value
;
7668 instr
->operands
[1].skip
= 0;
7672 /* Try the MOVZ alias. */
7673 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7674 aarch64_replace_opcode (instr
, opcode
);
7675 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7676 &instr
->value
, NULL
, NULL
, insn_sequence
))
7678 put_aarch64_insn (buf
, instr
->value
);
7681 /* Try the MOVK alias. */
7682 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7683 aarch64_replace_opcode (instr
, opcode
);
7684 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7685 &instr
->value
, NULL
, NULL
, insn_sequence
))
7687 put_aarch64_insn (buf
, instr
->value
);
7692 if (try_mov_bitmask_p
)
7694 /* Try the ORR alias. */
7695 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7696 aarch64_replace_opcode (instr
, opcode
);
7697 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7698 &instr
->value
, NULL
, NULL
, insn_sequence
))
7700 put_aarch64_insn (buf
, instr
->value
);
7705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7706 _("immediate cannot be moved by a single instruction"));
7709 /* An instruction operand which is immediate related may have symbol used
7710 in the assembly, e.g.
7713 .set u32, 0x00ffff00
7715 At the time when the assembly instruction is parsed, a referenced symbol,
7716 like 'u32' in the above example may not have been seen; a fixS is created
7717 in such a case and is handled here after symbols have been resolved.
7718 Instruction is fixed up with VALUE using the information in *FIXP plus
7719 extra information in FLAGS.
7721 This function is called by md_apply_fix to fix up instructions that need
7722 a fix-up described above but does not involve any linker-time relocation. */
7725 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7729 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7730 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7731 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7735 /* Now the instruction is about to be fixed-up, so the operand that
7736 was previously marked as 'ignored' needs to be unmarked in order
7737 to get the encoding done properly. */
7738 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7739 new_inst
->operands
[idx
].skip
= 0;
7742 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7746 case AARCH64_OPND_EXCEPTION
:
7747 if (unsigned_overflow (value
, 16))
7748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7749 _("immediate out of range"));
7750 insn
= get_aarch64_insn (buf
);
7751 insn
|= encode_svc_imm (value
);
7752 put_aarch64_insn (buf
, insn
);
7755 case AARCH64_OPND_AIMM
:
7756 /* ADD or SUB with immediate.
7757 NOTE this assumes we come here with a add/sub shifted reg encoding
7758 3 322|2222|2 2 2 21111 111111
7759 1 098|7654|3 2 1 09876 543210 98765 43210
7760 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7761 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7762 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7763 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7765 3 322|2222|2 2 221111111111
7766 1 098|7654|3 2 109876543210 98765 43210
7767 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7768 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7769 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7770 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7771 Fields sf Rn Rd are already set. */
7772 insn
= get_aarch64_insn (buf
);
7776 insn
= reencode_addsub_switch_add_sub (insn
);
7780 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7781 && unsigned_overflow (value
, 12))
7783 /* Try to shift the value by 12 to make it fit. */
7784 if (((value
>> 12) << 12) == value
7785 && ! unsigned_overflow (value
, 12 + 12))
7788 insn
|= encode_addsub_imm_shift_amount (1);
7792 if (unsigned_overflow (value
, 12))
7793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7794 _("immediate out of range"));
7796 insn
|= encode_addsub_imm (value
);
7798 put_aarch64_insn (buf
, insn
);
7801 case AARCH64_OPND_SIMD_IMM
:
7802 case AARCH64_OPND_SIMD_IMM_SFT
:
7803 case AARCH64_OPND_LIMM
:
7804 /* Bit mask immediate. */
7805 gas_assert (new_inst
!= NULL
);
7806 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7807 new_inst
->operands
[idx
].imm
.value
= value
;
7808 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7809 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7810 put_aarch64_insn (buf
, new_inst
->value
);
7812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7813 _("invalid immediate"));
7816 case AARCH64_OPND_HALF
:
7817 /* 16-bit unsigned immediate. */
7818 if (unsigned_overflow (value
, 16))
7819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7820 _("immediate out of range"));
7821 insn
= get_aarch64_insn (buf
);
7822 insn
|= encode_movw_imm (value
& 0xffff);
7823 put_aarch64_insn (buf
, insn
);
7826 case AARCH64_OPND_IMM_MOV
:
7827 /* Operand for a generic move immediate instruction, which is
7828 an alias instruction that generates a single MOVZ, MOVN or ORR
7829 instruction to loads a 32-bit/64-bit immediate value into general
7830 register. An assembler error shall result if the immediate cannot be
7831 created by a single one of these instructions. If there is a choice,
7832 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7833 and MOVZ or MOVN to ORR. */
7834 gas_assert (new_inst
!= NULL
);
7835 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7838 case AARCH64_OPND_ADDR_SIMM7
:
7839 case AARCH64_OPND_ADDR_SIMM9
:
7840 case AARCH64_OPND_ADDR_SIMM9_2
:
7841 case AARCH64_OPND_ADDR_SIMM10
:
7842 case AARCH64_OPND_ADDR_UIMM12
:
7843 case AARCH64_OPND_ADDR_SIMM11
:
7844 case AARCH64_OPND_ADDR_SIMM13
:
7845 /* Immediate offset in an address. */
7846 insn
= get_aarch64_insn (buf
);
7848 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7849 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7850 || new_inst
->opcode
->operands
[2] == opnd
);
7852 /* Get the index of the address operand. */
7853 if (new_inst
->opcode
->operands
[1] == opnd
)
7854 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7857 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7860 /* Update the resolved offset value. */
7861 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7863 /* Encode/fix-up. */
7864 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7865 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7867 put_aarch64_insn (buf
, new_inst
->value
);
7870 else if (new_inst
->opcode
->iclass
== ldst_pos
7871 && try_to_encode_as_unscaled_ldst (new_inst
))
7873 put_aarch64_insn (buf
, new_inst
->value
);
7877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7878 _("immediate offset out of range"));
7883 as_fatal (_("unhandled operand code %d"), opnd
);
7887 /* Apply a fixup (fixP) to segment data, once it has been determined
7888 by our caller that we have all the info we need to fix it up.
7890 Parameter valP is the pointer to the value of the bits. */
7893 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7895 offsetT value
= *valP
;
7897 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7899 unsigned flags
= fixP
->fx_addnumber
;
7901 DEBUG_TRACE ("\n\n");
7902 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7903 DEBUG_TRACE ("Enter md_apply_fix");
7905 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7907 /* Note whether this will delete the relocation. */
7909 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7912 /* Process the relocations. */
7913 switch (fixP
->fx_r_type
)
7915 case BFD_RELOC_NONE
:
7916 /* This will need to go in the object file. */
7921 case BFD_RELOC_8_PCREL
:
7922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7923 md_number_to_chars (buf
, value
, 1);
7927 case BFD_RELOC_16_PCREL
:
7928 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7929 md_number_to_chars (buf
, value
, 2);
7933 case BFD_RELOC_32_PCREL
:
7934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7935 md_number_to_chars (buf
, value
, 4);
7939 case BFD_RELOC_64_PCREL
:
7940 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7941 md_number_to_chars (buf
, value
, 8);
7944 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7945 /* We claim that these fixups have been processed here, even if
7946 in fact we generate an error because we do not have a reloc
7947 for them, so tc_gen_reloc() will reject them. */
7949 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7952 _("undefined symbol %s used as an immediate value"),
7953 S_GET_NAME (fixP
->fx_addsy
));
7954 goto apply_fix_return
;
7956 fix_insn (fixP
, flags
, value
);
7959 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7960 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7964 _("pc-relative load offset not word aligned"));
7965 if (signed_overflow (value
, 21))
7966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7967 _("pc-relative load offset out of range"));
7968 insn
= get_aarch64_insn (buf
);
7969 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7970 put_aarch64_insn (buf
, insn
);
7974 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7977 if (signed_overflow (value
, 21))
7978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7979 _("pc-relative address offset out of range"));
7980 insn
= get_aarch64_insn (buf
);
7981 insn
|= encode_adr_imm (value
);
7982 put_aarch64_insn (buf
, insn
);
7986 case BFD_RELOC_AARCH64_BRANCH19
:
7987 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7991 _("conditional branch target not word aligned"));
7992 if (signed_overflow (value
, 21))
7993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7994 _("conditional branch out of range"));
7995 insn
= get_aarch64_insn (buf
);
7996 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7997 put_aarch64_insn (buf
, insn
);
8001 case BFD_RELOC_AARCH64_TSTBR14
:
8002 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8006 _("conditional branch target not word aligned"));
8007 if (signed_overflow (value
, 16))
8008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8009 _("conditional branch out of range"));
8010 insn
= get_aarch64_insn (buf
);
8011 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8012 put_aarch64_insn (buf
, insn
);
8016 case BFD_RELOC_AARCH64_CALL26
:
8017 case BFD_RELOC_AARCH64_JUMP26
:
8018 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8022 _("branch target not word aligned"));
8023 if (signed_overflow (value
, 28))
8024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8025 _("branch out of range"));
8026 insn
= get_aarch64_insn (buf
);
8027 insn
|= encode_branch_ofs_26 (value
>> 2);
8028 put_aarch64_insn (buf
, insn
);
8032 case BFD_RELOC_AARCH64_MOVW_G0
:
8033 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8034 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8035 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8036 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8037 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8040 case BFD_RELOC_AARCH64_MOVW_G1
:
8041 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8042 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8043 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8044 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8045 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8048 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8050 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8051 /* Should always be exported to object file, see
8052 aarch64_force_relocation(). */
8053 gas_assert (!fixP
->fx_done
);
8054 gas_assert (seg
->use_rela_p
);
8056 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8058 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8059 /* Should always be exported to object file, see
8060 aarch64_force_relocation(). */
8061 gas_assert (!fixP
->fx_done
);
8062 gas_assert (seg
->use_rela_p
);
8064 case BFD_RELOC_AARCH64_MOVW_G2
:
8065 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8066 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8067 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8068 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8071 case BFD_RELOC_AARCH64_MOVW_G3
:
8072 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8075 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8077 insn
= get_aarch64_insn (buf
);
8081 /* REL signed addend must fit in 16 bits */
8082 if (signed_overflow (value
, 16))
8083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8084 _("offset out of range"));
8088 /* Check for overflow and scale. */
8089 switch (fixP
->fx_r_type
)
8091 case BFD_RELOC_AARCH64_MOVW_G0
:
8092 case BFD_RELOC_AARCH64_MOVW_G1
:
8093 case BFD_RELOC_AARCH64_MOVW_G2
:
8094 case BFD_RELOC_AARCH64_MOVW_G3
:
8095 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8096 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8097 if (unsigned_overflow (value
, scale
+ 16))
8098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8099 _("unsigned value out of range"));
8101 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8102 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8103 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8104 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8105 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8106 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8107 /* NOTE: We can only come here with movz or movn. */
8108 if (signed_overflow (value
, scale
+ 16))
8109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8110 _("signed value out of range"));
8113 /* Force use of MOVN. */
8115 insn
= reencode_movzn_to_movn (insn
);
8119 /* Force use of MOVZ. */
8120 insn
= reencode_movzn_to_movz (insn
);
8124 /* Unchecked relocations. */
8130 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8131 insn
|= encode_movw_imm (value
& 0xffff);
8133 put_aarch64_insn (buf
, insn
);
8137 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8138 fixP
->fx_r_type
= (ilp32_p
8139 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8140 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8141 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8142 /* Should always be exported to object file, see
8143 aarch64_force_relocation(). */
8144 gas_assert (!fixP
->fx_done
);
8145 gas_assert (seg
->use_rela_p
);
8148 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8149 fixP
->fx_r_type
= (ilp32_p
8150 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8151 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8152 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8153 /* Should always be exported to object file, see
8154 aarch64_force_relocation(). */
8155 gas_assert (!fixP
->fx_done
);
8156 gas_assert (seg
->use_rela_p
);
8159 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8160 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8161 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8162 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8163 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8164 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8165 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8166 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8167 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8168 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8169 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8170 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8171 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8172 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8173 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8174 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8175 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8176 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8177 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8178 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8179 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8180 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8181 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8182 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8183 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8184 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8185 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8186 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8187 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8188 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8189 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8190 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8191 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8192 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8193 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8194 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8195 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8196 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8197 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8198 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8199 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8200 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8201 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8202 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8203 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8204 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8205 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8206 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8207 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8208 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8209 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8210 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8211 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8212 /* Should always be exported to object file, see
8213 aarch64_force_relocation(). */
8214 gas_assert (!fixP
->fx_done
);
8215 gas_assert (seg
->use_rela_p
);
8218 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8219 /* Should always be exported to object file, see
8220 aarch64_force_relocation(). */
8221 fixP
->fx_r_type
= (ilp32_p
8222 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8223 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8224 gas_assert (!fixP
->fx_done
);
8225 gas_assert (seg
->use_rela_p
);
8228 case BFD_RELOC_AARCH64_ADD_LO12
:
8229 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8230 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8231 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8232 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8233 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8234 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8235 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8236 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8237 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8238 case BFD_RELOC_AARCH64_LDST128_LO12
:
8239 case BFD_RELOC_AARCH64_LDST16_LO12
:
8240 case BFD_RELOC_AARCH64_LDST32_LO12
:
8241 case BFD_RELOC_AARCH64_LDST64_LO12
:
8242 case BFD_RELOC_AARCH64_LDST8_LO12
:
8243 /* Should always be exported to object file, see
8244 aarch64_force_relocation(). */
8245 gas_assert (!fixP
->fx_done
);
8246 gas_assert (seg
->use_rela_p
);
8249 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8250 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8251 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8254 case BFD_RELOC_UNUSED
:
8255 /* An error will already have been reported. */
8259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8260 _("unexpected %s fixup"),
8261 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8266 /* Free the allocated the struct aarch64_inst.
8267 N.B. currently there are very limited number of fix-up types actually use
8268 this field, so the impact on the performance should be minimal . */
8269 if (fixP
->tc_fix_data
.inst
!= NULL
)
8270 free (fixP
->tc_fix_data
.inst
);
8275 /* Translate internal representation of relocation info to BFD target
8279 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8282 bfd_reloc_code_real_type code
;
8284 reloc
= XNEW (arelent
);
8286 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8287 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8288 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8292 if (section
->use_rela_p
)
8293 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8295 fixp
->fx_offset
= reloc
->address
;
8297 reloc
->addend
= fixp
->fx_offset
;
8299 code
= fixp
->fx_r_type
;
8304 code
= BFD_RELOC_16_PCREL
;
8309 code
= BFD_RELOC_32_PCREL
;
8314 code
= BFD_RELOC_64_PCREL
;
8321 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8322 if (reloc
->howto
== NULL
)
8324 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8326 ("cannot represent %s relocation in this object file format"),
8327 bfd_get_reloc_code_name (code
));
8334 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8337 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8339 bfd_reloc_code_real_type type
;
8343 FIXME: @@ Should look at CPU word size. */
8350 type
= BFD_RELOC_16
;
8353 type
= BFD_RELOC_32
;
8356 type
= BFD_RELOC_64
;
8359 as_bad (_("cannot do %u-byte relocation"), size
);
8360 type
= BFD_RELOC_UNUSED
;
8364 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8368 aarch64_force_relocation (struct fix
*fixp
)
8370 switch (fixp
->fx_r_type
)
8372 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8373 /* Perform these "immediate" internal relocations
8374 even if the symbol is extern or weak. */
8377 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8378 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8379 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8380 /* Pseudo relocs that need to be fixed up according to
8384 case BFD_RELOC_AARCH64_ADD_LO12
:
8385 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8386 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8387 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8388 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8389 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8390 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8391 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8392 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8393 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8394 case BFD_RELOC_AARCH64_LDST128_LO12
:
8395 case BFD_RELOC_AARCH64_LDST16_LO12
:
8396 case BFD_RELOC_AARCH64_LDST32_LO12
:
8397 case BFD_RELOC_AARCH64_LDST64_LO12
:
8398 case BFD_RELOC_AARCH64_LDST8_LO12
:
8399 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8400 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8401 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8402 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8403 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8404 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8405 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8406 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8407 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8408 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8409 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8410 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8411 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8412 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8413 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8414 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8415 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8416 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8417 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8418 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8419 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8420 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8421 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8422 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8423 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8424 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8425 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8426 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8427 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8428 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8429 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8430 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8431 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8432 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8433 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8434 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8435 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8436 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8437 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8438 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8439 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8440 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8441 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8442 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8443 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8444 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8445 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8446 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8447 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8448 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8449 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8450 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8451 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8452 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8453 /* Always leave these relocations for the linker. */
8460 return generic_force_reloc (fixp
);
8465 /* Implement md_after_parse_args. This is the earliest time we need to decide
8466 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8469 aarch64_after_parse_args (void)
8471 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8474 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8475 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8476 aarch64_abi
= AARCH64_ABI_ILP32
;
8478 aarch64_abi
= AARCH64_ABI_LP64
;
8482 elf64_aarch64_target_format (void)
8485 /* FIXME: What to do for ilp32_p ? */
8486 if (target_big_endian
)
8487 return "elf64-bigaarch64-cloudabi";
8489 return "elf64-littleaarch64-cloudabi";
8491 if (target_big_endian
)
8492 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8494 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8499 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8501 elf_frob_symbol (symp
, puntp
);
8505 /* MD interface: Finalization. */
8507 /* A good place to do this, although this was probably not intended
8508 for this kind of use. We need to dump the literal pool before
8509 references are made to a null symbol pointer. */
8512 aarch64_cleanup (void)
8516 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8518 /* Put it at the end of the relevant section. */
8519 subseg_set (pool
->section
, pool
->sub_section
);
8525 /* Remove any excess mapping symbols generated for alignment frags in
8526 SEC. We may have created a mapping symbol before a zero byte
8527 alignment; remove it if there's a mapping symbol after the
8530 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8531 void *dummy ATTRIBUTE_UNUSED
)
8533 segment_info_type
*seginfo
= seg_info (sec
);
8536 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8539 for (fragp
= seginfo
->frchainP
->frch_root
;
8540 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8542 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8543 fragS
*next
= fragp
->fr_next
;
8545 /* Variable-sized frags have been converted to fixed size by
8546 this point. But if this was variable-sized to start with,
8547 there will be a fixed-size frag after it. So don't handle
8549 if (sym
== NULL
|| next
== NULL
)
8552 if (S_GET_VALUE (sym
) < next
->fr_address
)
8553 /* Not at the end of this frag. */
8555 know (S_GET_VALUE (sym
) == next
->fr_address
);
8559 if (next
->tc_frag_data
.first_map
!= NULL
)
8561 /* Next frag starts with a mapping symbol. Discard this
8563 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8567 if (next
->fr_next
== NULL
)
8569 /* This mapping symbol is at the end of the section. Discard
8571 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8572 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8576 /* As long as we have empty frags without any mapping symbols,
8578 /* If the next frag is non-empty and does not start with a
8579 mapping symbol, then this mapping symbol is required. */
8580 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8583 next
= next
->fr_next
;
8585 while (next
!= NULL
);
8590 /* Adjust the symbol table. */
8593 aarch64_adjust_symtab (void)
8596 /* Remove any overlapping mapping symbols generated by alignment frags. */
8597 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8598 /* Now do generic ELF adjustments. */
8599 elf_adjust_symtab ();
8604 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8606 const char *hash_err
;
8608 hash_err
= hash_insert (table
, key
, value
);
8610 printf ("Internal Error: Can't hash %s\n", key
);
8614 fill_instruction_hash_table (void)
8616 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8618 while (opcode
->name
!= NULL
)
8620 templates
*templ
, *new_templ
;
8621 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8623 new_templ
= XNEW (templates
);
8624 new_templ
->opcode
= opcode
;
8625 new_templ
->next
= NULL
;
8628 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8631 new_templ
->next
= templ
->next
;
8632 templ
->next
= new_templ
;
8639 convert_to_upper (char *dst
, const char *src
, size_t num
)
8642 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8643 *dst
= TOUPPER (*src
);
8647 /* Assume STR point to a lower-case string, allocate, convert and return
8648 the corresponding upper-case string. */
8649 static inline const char*
8650 get_upper_str (const char *str
)
8653 size_t len
= strlen (str
);
8654 ret
= XNEWVEC (char, len
+ 1);
8655 convert_to_upper (ret
, str
, len
);
8659 /* MD interface: Initialization. */
8667 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8668 || (aarch64_cond_hsh
= hash_new ()) == NULL
8669 || (aarch64_shift_hsh
= hash_new ()) == NULL
8670 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8671 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8672 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8673 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8674 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8675 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8676 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8677 || (aarch64_reg_hsh
= hash_new ()) == NULL
8678 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8679 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8680 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8681 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8682 as_fatal (_("virtual memory exhausted"));
8684 fill_instruction_hash_table ();
8686 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8687 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8688 (void *) (aarch64_sys_regs
+ i
));
8690 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8691 checked_hash_insert (aarch64_pstatefield_hsh
,
8692 aarch64_pstatefields
[i
].name
,
8693 (void *) (aarch64_pstatefields
+ i
));
8695 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8696 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8697 aarch64_sys_regs_ic
[i
].name
,
8698 (void *) (aarch64_sys_regs_ic
+ i
));
8700 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8701 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8702 aarch64_sys_regs_dc
[i
].name
,
8703 (void *) (aarch64_sys_regs_dc
+ i
));
8705 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8706 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8707 aarch64_sys_regs_at
[i
].name
,
8708 (void *) (aarch64_sys_regs_at
+ i
));
8710 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8711 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8712 aarch64_sys_regs_tlbi
[i
].name
,
8713 (void *) (aarch64_sys_regs_tlbi
+ i
));
8715 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8716 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8717 aarch64_sys_regs_sr
[i
].name
,
8718 (void *) (aarch64_sys_regs_sr
+ i
));
8720 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8721 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8722 (void *) (reg_names
+ i
));
8724 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8725 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8726 (void *) (nzcv_names
+ i
));
8728 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8730 const char *name
= aarch64_operand_modifiers
[i
].name
;
8731 checked_hash_insert (aarch64_shift_hsh
, name
,
8732 (void *) (aarch64_operand_modifiers
+ i
));
8733 /* Also hash the name in the upper case. */
8734 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8735 (void *) (aarch64_operand_modifiers
+ i
));
8738 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8741 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8742 the same condition code. */
8743 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8745 const char *name
= aarch64_conds
[i
].names
[j
];
8748 checked_hash_insert (aarch64_cond_hsh
, name
,
8749 (void *) (aarch64_conds
+ i
));
8750 /* Also hash the name in the upper case. */
8751 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8752 (void *) (aarch64_conds
+ i
));
8756 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8758 const char *name
= aarch64_barrier_options
[i
].name
;
8759 /* Skip xx00 - the unallocated values of option. */
8762 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8763 (void *) (aarch64_barrier_options
+ i
));
8764 /* Also hash the name in the upper case. */
8765 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8766 (void *) (aarch64_barrier_options
+ i
));
8769 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8771 const char* name
= aarch64_prfops
[i
].name
;
8772 /* Skip the unallocated hint encodings. */
8775 checked_hash_insert (aarch64_pldop_hsh
, name
,
8776 (void *) (aarch64_prfops
+ i
));
8777 /* Also hash the name in the upper case. */
8778 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8779 (void *) (aarch64_prfops
+ i
));
8782 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8784 const char* name
= aarch64_hint_options
[i
].name
;
8785 const char* upper_name
= get_upper_str(name
);
8787 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8788 (void *) (aarch64_hint_options
+ i
));
8790 /* Also hash the name in the upper case if not the same. */
8791 if (strcmp (name
, upper_name
) != 0)
8792 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8793 (void *) (aarch64_hint_options
+ i
));
8796 /* Set the cpu variant based on the command-line options. */
8798 mcpu_cpu_opt
= march_cpu_opt
;
8801 mcpu_cpu_opt
= &cpu_default
;
8803 cpu_variant
= *mcpu_cpu_opt
;
8805 /* Record the CPU type. */
8806 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8808 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8811 /* Command line processing. */
8813 const char *md_shortopts
= "m:";
8815 #ifdef AARCH64_BI_ENDIAN
8816 #define OPTION_EB (OPTION_MD_BASE + 0)
8817 #define OPTION_EL (OPTION_MD_BASE + 1)
8819 #if TARGET_BYTES_BIG_ENDIAN
8820 #define OPTION_EB (OPTION_MD_BASE + 0)
8822 #define OPTION_EL (OPTION_MD_BASE + 1)
8826 struct option md_longopts
[] = {
8828 {"EB", no_argument
, NULL
, OPTION_EB
},
8831 {"EL", no_argument
, NULL
, OPTION_EL
},
8833 {NULL
, no_argument
, NULL
, 0}
8836 size_t md_longopts_size
= sizeof (md_longopts
);
8838 struct aarch64_option_table
8840 const char *option
; /* Option name to match. */
8841 const char *help
; /* Help information. */
8842 int *var
; /* Variable to change. */
8843 int value
; /* What to change it to. */
8844 char *deprecated
; /* If non-null, print this message. */
8847 static struct aarch64_option_table aarch64_opts
[] = {
8848 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8849 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8851 #ifdef DEBUG_AARCH64
8852 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8853 #endif /* DEBUG_AARCH64 */
8854 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8856 {"mno-verbose-error", N_("do not output verbose error messages"),
8857 &verbose_error_p
, 0, NULL
},
8858 {NULL
, NULL
, NULL
, 0, NULL
}
8861 struct aarch64_cpu_option_table
8864 const aarch64_feature_set value
;
8865 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8867 const char *canonical_name
;
8870 /* This list should, at a minimum, contain all the cpu names
8871 recognized by GCC. */
8872 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8873 {"all", AARCH64_ANY
, NULL
},
8874 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8875 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8876 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8877 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8878 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8879 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8880 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8881 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8882 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8883 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8884 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8885 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8886 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8887 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8889 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8890 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8892 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8893 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8895 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8896 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8897 | AARCH64_FEATURE_DOTPROD
8898 | AARCH64_FEATURE_SSBS
),
8900 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8901 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8902 | AARCH64_FEATURE_DOTPROD
8903 | AARCH64_FEATURE_SSBS
),
8905 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8906 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8907 | AARCH64_FEATURE_DOTPROD
8908 | AARCH64_FEATURE_SSBS
),
8910 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8911 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8912 | AARCH64_FEATURE_DOTPROD
8913 | AARCH64_FEATURE_SSBS
),
8915 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8916 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8917 | AARCH64_FEATURE_DOTPROD
8918 | AARCH64_FEATURE_PROFILE
),
8920 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8921 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8922 "Samsung Exynos M1"},
8923 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8924 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8925 | AARCH64_FEATURE_RDMA
),
8927 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8928 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8929 | AARCH64_FEATURE_DOTPROD
8930 | AARCH64_FEATURE_SSBS
),
8932 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8933 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8934 | AARCH64_FEATURE_DOTPROD
8935 | AARCH64_FEATURE_PROFILE
),
8937 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8938 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8939 | AARCH64_FEATURE_RDMA
),
8940 "Qualcomm QDF24XX"},
8941 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8942 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8943 "Qualcomm Saphira"},
8944 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8945 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8947 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8948 AARCH64_FEATURE_CRYPTO
),
8950 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8951 in earlier releases and is superseded by 'xgene1' in all
8953 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8954 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8955 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8956 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8957 {"generic", AARCH64_ARCH_V8
, NULL
},
8959 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8962 struct aarch64_arch_option_table
8965 const aarch64_feature_set value
;
8968 /* This list should, at a minimum, contain all the architecture names
8969 recognized by GCC. */
8970 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8971 {"all", AARCH64_ANY
},
8972 {"armv8-a", AARCH64_ARCH_V8
},
8973 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8974 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8975 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8976 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8977 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8978 {"armv8.6-a", AARCH64_ARCH_V8_6
},
8979 {NULL
, AARCH64_ARCH_NONE
}
8982 /* ISA extensions. */
8983 struct aarch64_option_cpu_value_table
8986 const aarch64_feature_set value
;
8987 const aarch64_feature_set require
; /* Feature dependencies. */
8990 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8991 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8993 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
8994 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8995 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8997 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8999 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9000 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9001 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9003 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9005 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9007 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9008 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9009 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9010 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9011 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9012 AARCH64_FEATURE (AARCH64_FEATURE_FP
9013 | AARCH64_FEATURE_F16
, 0)},
9014 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9016 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9017 AARCH64_FEATURE (AARCH64_FEATURE_F16
9018 | AARCH64_FEATURE_SIMD
9019 | AARCH64_FEATURE_COMPNUM
, 0)},
9020 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9022 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9023 AARCH64_FEATURE (AARCH64_FEATURE_F16
9024 | AARCH64_FEATURE_SIMD
, 0)},
9025 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9027 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9029 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9031 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9033 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9035 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9037 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9039 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9040 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9041 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9043 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9045 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9047 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9048 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9049 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9050 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9051 | AARCH64_FEATURE_SM4
, 0)},
9052 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9053 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9054 | AARCH64_FEATURE_AES
, 0)},
9055 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9056 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9057 | AARCH64_FEATURE_SHA3
, 0)},
9058 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9059 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9060 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9062 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9064 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9066 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9068 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9071 struct aarch64_long_option_table
9073 const char *option
; /* Substring to match. */
9074 const char *help
; /* Help information. */
9075 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9076 char *deprecated
; /* If non-null, print this message. */
9079 /* Transitive closure of features depending on set. */
9080 static aarch64_feature_set
9081 aarch64_feature_disable_set (aarch64_feature_set set
)
9083 const struct aarch64_option_cpu_value_table
*opt
;
9084 aarch64_feature_set prev
= 0;
9086 while (prev
!= set
) {
9088 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9089 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9090 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9095 /* Transitive closure of dependencies of set. */
9096 static aarch64_feature_set
9097 aarch64_feature_enable_set (aarch64_feature_set set
)
9099 const struct aarch64_option_cpu_value_table
*opt
;
9100 aarch64_feature_set prev
= 0;
9102 while (prev
!= set
) {
9104 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9105 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9106 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9112 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9113 bfd_boolean ext_only
)
9115 /* We insist on extensions being added before being removed. We achieve
9116 this by using the ADDING_VALUE variable to indicate whether we are
9117 adding an extension (1) or removing it (0) and only allowing it to
9118 change in the order -1 -> 1 -> 0. */
9119 int adding_value
= -1;
9120 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9122 /* Copy the feature set, so that we can modify it. */
9126 while (str
!= NULL
&& *str
!= 0)
9128 const struct aarch64_option_cpu_value_table
*opt
;
9129 const char *ext
= NULL
;
9136 as_bad (_("invalid architectural extension"));
9140 ext
= strchr (++str
, '+');
9146 optlen
= strlen (str
);
9148 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9150 if (adding_value
!= 0)
9155 else if (optlen
> 0)
9157 if (adding_value
== -1)
9159 else if (adding_value
!= 1)
9161 as_bad (_("must specify extensions to add before specifying "
9162 "those to remove"));
9169 as_bad (_("missing architectural extension"));
9173 gas_assert (adding_value
!= -1);
9175 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9176 if (strncmp (opt
->name
, str
, optlen
) == 0)
9178 aarch64_feature_set set
;
9180 /* Add or remove the extension. */
9183 set
= aarch64_feature_enable_set (opt
->value
);
9184 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9188 set
= aarch64_feature_disable_set (opt
->value
);
9189 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9194 if (opt
->name
== NULL
)
9196 as_bad (_("unknown architectural extension `%s'"), str
);
9207 aarch64_parse_cpu (const char *str
)
9209 const struct aarch64_cpu_option_table
*opt
;
9210 const char *ext
= strchr (str
, '+');
9216 optlen
= strlen (str
);
9220 as_bad (_("missing cpu name `%s'"), str
);
9224 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9225 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9227 mcpu_cpu_opt
= &opt
->value
;
9229 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9234 as_bad (_("unknown cpu `%s'"), str
);
9239 aarch64_parse_arch (const char *str
)
9241 const struct aarch64_arch_option_table
*opt
;
9242 const char *ext
= strchr (str
, '+');
9248 optlen
= strlen (str
);
9252 as_bad (_("missing architecture name `%s'"), str
);
9256 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9257 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9259 march_cpu_opt
= &opt
->value
;
9261 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9266 as_bad (_("unknown architecture `%s'\n"), str
);
9271 struct aarch64_option_abi_value_table
9274 enum aarch64_abi_type value
;
9277 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9278 {"ilp32", AARCH64_ABI_ILP32
},
9279 {"lp64", AARCH64_ABI_LP64
},
9283 aarch64_parse_abi (const char *str
)
9289 as_bad (_("missing abi name `%s'"), str
);
9293 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9294 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9296 aarch64_abi
= aarch64_abis
[i
].value
;
9300 as_bad (_("unknown abi `%s'\n"), str
);
9304 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9306 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9307 aarch64_parse_abi
, NULL
},
9308 #endif /* OBJ_ELF */
9309 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9310 aarch64_parse_cpu
, NULL
},
9311 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9312 aarch64_parse_arch
, NULL
},
9313 {NULL
, NULL
, 0, NULL
}
9317 md_parse_option (int c
, const char *arg
)
9319 struct aarch64_option_table
*opt
;
9320 struct aarch64_long_option_table
*lopt
;
9326 target_big_endian
= 1;
9332 target_big_endian
= 0;
9337 /* Listing option. Just ignore these, we don't support additional
9342 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9344 if (c
== opt
->option
[0]
9345 && ((arg
== NULL
&& opt
->option
[1] == 0)
9346 || streq (arg
, opt
->option
+ 1)))
9348 /* If the option is deprecated, tell the user. */
9349 if (opt
->deprecated
!= NULL
)
9350 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9351 arg
? arg
: "", _(opt
->deprecated
));
9353 if (opt
->var
!= NULL
)
9354 *opt
->var
= opt
->value
;
9360 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9362 /* These options are expected to have an argument. */
9363 if (c
== lopt
->option
[0]
9365 && strncmp (arg
, lopt
->option
+ 1,
9366 strlen (lopt
->option
+ 1)) == 0)
9368 /* If the option is deprecated, tell the user. */
9369 if (lopt
->deprecated
!= NULL
)
9370 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9371 _(lopt
->deprecated
));
9373 /* Call the sup-option parser. */
9374 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9385 md_show_usage (FILE * fp
)
9387 struct aarch64_option_table
*opt
;
9388 struct aarch64_long_option_table
*lopt
;
9390 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9392 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9393 if (opt
->help
!= NULL
)
9394 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9396 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9397 if (lopt
->help
!= NULL
)
9398 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9402 -EB assemble code for a big-endian cpu\n"));
9407 -EL assemble code for a little-endian cpu\n"));
9411 /* Parse a .cpu directive. */
9414 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9416 const struct aarch64_cpu_option_table
*opt
;
9422 name
= input_line_pointer
;
9423 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9424 input_line_pointer
++;
9425 saved_char
= *input_line_pointer
;
9426 *input_line_pointer
= 0;
9428 ext
= strchr (name
, '+');
9431 optlen
= ext
- name
;
9433 optlen
= strlen (name
);
9435 /* Skip the first "all" entry. */
9436 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9437 if (strlen (opt
->name
) == optlen
9438 && strncmp (name
, opt
->name
, optlen
) == 0)
9440 mcpu_cpu_opt
= &opt
->value
;
9442 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9445 cpu_variant
= *mcpu_cpu_opt
;
9447 *input_line_pointer
= saved_char
;
9448 demand_empty_rest_of_line ();
9451 as_bad (_("unknown cpu `%s'"), name
);
9452 *input_line_pointer
= saved_char
;
9453 ignore_rest_of_line ();
9457 /* Parse a .arch directive. */
9460 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9462 const struct aarch64_arch_option_table
*opt
;
9468 name
= input_line_pointer
;
9469 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9470 input_line_pointer
++;
9471 saved_char
= *input_line_pointer
;
9472 *input_line_pointer
= 0;
9474 ext
= strchr (name
, '+');
9477 optlen
= ext
- name
;
9479 optlen
= strlen (name
);
9481 /* Skip the first "all" entry. */
9482 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9483 if (strlen (opt
->name
) == optlen
9484 && strncmp (name
, opt
->name
, optlen
) == 0)
9486 mcpu_cpu_opt
= &opt
->value
;
9488 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9491 cpu_variant
= *mcpu_cpu_opt
;
9493 *input_line_pointer
= saved_char
;
9494 demand_empty_rest_of_line ();
9498 as_bad (_("unknown architecture `%s'\n"), name
);
9499 *input_line_pointer
= saved_char
;
9500 ignore_rest_of_line ();
9503 /* Parse a .arch_extension directive. */
9506 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9509 char *ext
= input_line_pointer
;;
9511 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9512 input_line_pointer
++;
9513 saved_char
= *input_line_pointer
;
9514 *input_line_pointer
= 0;
9516 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9519 cpu_variant
= *mcpu_cpu_opt
;
9521 *input_line_pointer
= saved_char
;
9522 demand_empty_rest_of_line ();
9525 /* Copy symbol information. */
9528 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9530 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9534 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9535 This is needed so AArch64 specific st_other values can be independently
9536 specified for an IFUNC resolver (that is called by the dynamic linker)
9537 and the symbol it resolves (aliased to the resolver). In particular,
9538 if a function symbol has special st_other value set via directives,
9539 then attaching an IFUNC resolver to that symbol should not override
9540 the st_other setting. Requiring the directive on the IFUNC resolver
9541 symbol would be unexpected and problematic in C code, where the two
9542 symbols appear as two independent function declarations. */
9545 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9547 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9548 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9551 if (destelf
->size
== NULL
)
9552 destelf
->size
= XNEW (expressionS
);
9553 *destelf
->size
= *srcelf
->size
;
9557 if (destelf
->size
!= NULL
)
9558 free (destelf
->size
);
9559 destelf
->size
= NULL
;
9561 S_SET_SIZE (dest
, S_GET_SIZE (src
));