1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type
;
99 unsigned char defined
;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type
;
111 enum aarch64_opnd opnd
;
113 unsigned need_libopcodes_p
: 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind
;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool
: 1;
134 typedef struct aarch64_instruction aarch64_instruction
;
136 static aarch64_instruction inst
;
138 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
139 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
162 inst
.parsing_error
.error
= NULL
;
165 static inline bfd_boolean
168 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
171 static inline const char *
172 get_error_message (void)
174 return inst
.parsing_error
.error
;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst
.parsing_error
.kind
;
184 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
186 inst
.parsing_error
.kind
= kind
;
187 inst
.parsing_error
.error
= error
;
191 set_recoverable_error (const char *error
)
193 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
205 set_syntax_error (const char *error
)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
211 set_first_syntax_error (const char *error
)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
218 set_fatal_syntax_error (const char *error
)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc
;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(CN) /* c[0-7] */ \
270 BASIC_REG_TYPE(VN) /* v[0-31] */ \
271 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
272 BASIC_REG_TYPE(PN) /* p[0-15] */ \
273 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
274 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
275 /* Typecheck: same, plus SVE registers. */ \
276 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
278 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
279 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
280 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
281 /* Typecheck: same, plus SVE registers. */ \
282 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
283 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
285 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
286 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
288 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
289 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
292 /* Typecheck: any [BHSDQ]P FP. */ \
293 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
294 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
295 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
298 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
299 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
300 /* Typecheck: as above, but also Zn and Pn. This should only be \
301 used for SVE instructions, since Zn and Pn are valid symbols \
302 in other contexts. */ \
303 MULTI_REG_TYPE(R_Z_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
305 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
306 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
307 | REG_TYPE(ZN) | REG_TYPE(PN)) \
308 /* Any integer register; used for error messages only. */ \
309 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
310 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
312 /* Pseudo type to mark the end of the enumerator sequence. */ \
315 #undef BASIC_REG_TYPE
316 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
317 #undef MULTI_REG_TYPE
318 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
320 /* Register type enumerators. */
321 typedef enum aarch64_reg_type_
323 /* A list of REG_TYPE_*. */
327 #undef BASIC_REG_TYPE
328 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
330 #define REG_TYPE(T) (1 << REG_TYPE_##T)
331 #undef MULTI_REG_TYPE
332 #define MULTI_REG_TYPE(T,V) V,
334 /* Structure for a hash table entry for a register. */
338 unsigned char number
;
339 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
340 unsigned char builtin
;
343 /* Values indexed by aarch64_reg_type to assist the type checking. */
344 static const unsigned reg_type_masks
[] =
349 #undef BASIC_REG_TYPE
351 #undef MULTI_REG_TYPE
352 #undef AARCH64_REG_TYPES
354 /* Diagnostics used when we don't get a register of the expected type.
355 Note: this has to synchronized with aarch64_reg_type definitions
358 get_reg_expected_msg (aarch64_reg_type reg_type
)
365 msg
= N_("integer 32-bit register expected");
368 msg
= N_("integer 64-bit register expected");
371 msg
= N_("integer register expected");
373 case REG_TYPE_R64_SP
:
374 msg
= N_("64-bit integer or SP register expected");
376 case REG_TYPE_SVE_BASE
:
377 msg
= N_("base register expected");
380 msg
= N_("integer or zero register expected");
382 case REG_TYPE_SVE_OFFSET
:
383 msg
= N_("offset register expected");
386 msg
= N_("integer or SP register expected");
388 case REG_TYPE_R_Z_SP
:
389 msg
= N_("integer, zero or SP register expected");
392 msg
= N_("8-bit SIMD scalar register expected");
395 msg
= N_("16-bit SIMD scalar or floating-point half precision "
396 "register expected");
399 msg
= N_("32-bit SIMD scalar or floating-point single precision "
400 "register expected");
403 msg
= N_("64-bit SIMD scalar or floating-point double precision "
404 "register expected");
407 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
408 "register expected");
411 msg
= N_("C0 - C15 expected");
413 case REG_TYPE_R_Z_BHSDQ_V
:
414 case REG_TYPE_R_Z_BHSDQ_VZP
:
415 msg
= N_("register expected");
417 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
418 msg
= N_("SIMD scalar or floating-point register expected");
420 case REG_TYPE_VN
: /* any V reg */
421 msg
= N_("vector register expected");
424 msg
= N_("SVE vector register expected");
427 msg
= N_("SVE predicate register expected");
430 as_fatal (_("invalid register type %d"), reg_type
);
435 /* Some well known registers that we refer to directly elsewhere. */
438 /* Instructions take 4 bytes in the object file. */
441 static struct hash_control
*aarch64_ops_hsh
;
442 static struct hash_control
*aarch64_cond_hsh
;
443 static struct hash_control
*aarch64_shift_hsh
;
444 static struct hash_control
*aarch64_sys_regs_hsh
;
445 static struct hash_control
*aarch64_pstatefield_hsh
;
446 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
447 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
448 static struct hash_control
*aarch64_sys_regs_at_hsh
;
449 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
450 static struct hash_control
*aarch64_reg_hsh
;
451 static struct hash_control
*aarch64_barrier_opt_hsh
;
452 static struct hash_control
*aarch64_nzcv_hsh
;
453 static struct hash_control
*aarch64_pldop_hsh
;
454 static struct hash_control
*aarch64_hint_opt_hsh
;
456 /* Stuff needed to resolve the label ambiguity
465 static symbolS
*last_label_seen
;
467 /* Literal pool structure. Held on a per-section
468 and per-sub-section basis. */
470 #define MAX_LITERAL_POOL_SIZE 1024
471 typedef struct literal_expression
474 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
475 LITTLENUM_TYPE
* bignum
;
476 } literal_expression
;
478 typedef struct literal_pool
480 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
481 unsigned int next_free_entry
;
487 struct literal_pool
*next
;
490 /* Pointer to a linked list of literal pools. */
491 static literal_pool
*list_of_pools
= NULL
;
495 /* This array holds the chars that always start a comment. If the
496 pre-processor is disabled, these aren't very useful. */
497 const char comment_chars
[] = "";
499 /* This array holds the chars that only start a comment at the beginning of
500 a line. If the line seems to have the form '# 123 filename'
501 .line and .file directives will appear in the pre-processed output. */
502 /* Note that input_file.c hand checks for '#' at the beginning of the
503 first line of the input file. This is because the compiler outputs
504 #NO_APP at the beginning of its output. */
505 /* Also note that comments like this one will always work. */
506 const char line_comment_chars
[] = "#";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant
511 from exp in floating point numbers. */
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant. */
518 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
520 /* Prefix character that indicates the start of an immediate value. */
521 #define is_immediate_prefix(C) ((C) == '#')
523 /* Separator character handling. */
525 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
527 static inline bfd_boolean
528 skip_past_char (char **str
, char c
)
539 #define skip_past_comma(str) skip_past_char (str, ',')
541 /* Arithmetic expressions (possibly involving symbols). */
543 static bfd_boolean in_my_get_expression_p
= FALSE
;
545 /* Third argument to my_get_expression. */
546 #define GE_NO_PREFIX 0
547 #define GE_OPT_PREFIX 1
549 /* Return TRUE if the string pointed by *STR is successfully parsed
550 as an valid expression; *EP will be filled with the information of
551 such an expression. Otherwise return FALSE. */
554 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
559 int prefix_present_p
= 0;
566 if (is_immediate_prefix (**str
))
569 prefix_present_p
= 1;
576 memset (ep
, 0, sizeof (expressionS
));
578 save_in
= input_line_pointer
;
579 input_line_pointer
= *str
;
580 in_my_get_expression_p
= TRUE
;
581 seg
= expression (ep
);
582 in_my_get_expression_p
= FALSE
;
584 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
586 /* We found a bad expression in md_operand(). */
587 *str
= input_line_pointer
;
588 input_line_pointer
= save_in
;
589 if (prefix_present_p
&& ! error_p ())
590 set_fatal_syntax_error (_("bad expression"));
592 set_first_syntax_error (_("bad expression"));
597 if (seg
!= absolute_section
598 && seg
!= text_section
599 && seg
!= data_section
600 && seg
!= bss_section
&& seg
!= undefined_section
)
602 set_syntax_error (_("bad segment"));
603 *str
= input_line_pointer
;
604 input_line_pointer
= save_in
;
611 *str
= input_line_pointer
;
612 input_line_pointer
= save_in
;
616 /* Turn a string in input_line_pointer into a floating point constant
617 of type TYPE, and store the appropriate bytes in *LITP. The number
618 of LITTLENUMS emitted is stored in *SIZEP. An error message is
619 returned, or NULL on OK. */
622 md_atof (int type
, char *litP
, int *sizeP
)
624 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
627 /* We handle all bad expressions here, so that we can report the faulty
628 instruction in the error message. */
630 md_operand (expressionS
* exp
)
632 if (in_my_get_expression_p
)
633 exp
->X_op
= O_illegal
;
636 /* Immediate values. */
638 /* Errors may be set multiple times during parsing or bit encoding
639 (particularly in the Neon bits), but usually the earliest error which is set
640 will be the most meaningful. Avoid overwriting it with later (cascading)
641 errors by calling this function. */
644 first_error (const char *error
)
647 set_syntax_error (error
);
650 /* Similiar to first_error, but this function accepts formatted error
653 first_error_fmt (const char *format
, ...)
658 /* N.B. this single buffer will not cause error messages for different
659 instructions to pollute each other; this is because at the end of
660 processing of each assembly line, error message if any will be
661 collected by as_bad. */
662 static char buffer
[size
];
666 int ret ATTRIBUTE_UNUSED
;
667 va_start (args
, format
);
668 ret
= vsnprintf (buffer
, size
, format
, args
);
669 know (ret
<= size
- 1 && ret
>= 0);
671 set_syntax_error (buffer
);
675 /* Register parsing. */
677 /* Generic register parser which is called by other specialized
679 CCP points to what should be the beginning of a register name.
680 If it is indeed a valid register name, advance CCP over it and
681 return the reg_entry structure; otherwise return NULL.
682 It does not issue diagnostics. */
685 parse_reg (char **ccp
)
691 #ifdef REGISTER_PREFIX
692 if (*start
!= REGISTER_PREFIX
)
698 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
703 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
705 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
714 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
717 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
719 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
722 /* Try to parse a base or offset register. Allow SVE base and offset
723 registers if REG_TYPE includes SVE registers. Return the register
724 entry on success, setting *QUALIFIER to the register qualifier.
725 Return null otherwise.
727 Note that this function does not issue any diagnostics. */
729 static const reg_entry
*
730 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
731 aarch64_opnd_qualifier_t
*qualifier
)
734 const reg_entry
*reg
= parse_reg (&str
);
744 *qualifier
= AARCH64_OPND_QLF_W
;
750 *qualifier
= AARCH64_OPND_QLF_X
;
754 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
757 switch (TOLOWER (str
[1]))
760 *qualifier
= AARCH64_OPND_QLF_S_S
;
763 *qualifier
= AARCH64_OPND_QLF_S_D
;
780 /* Try to parse a base or offset register. Return the register entry
781 on success, setting *QUALIFIER to the register qualifier. Return null
784 Note that this function does not issue any diagnostics. */
786 static const reg_entry
*
787 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
789 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
792 /* Parse the qualifier of a vector register or vector element of type
793 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
794 succeeds; otherwise return FALSE.
796 Accept only one occurrence of:
797 8b 16b 2h 4h 8h 2s 4s 1d 2d
800 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
801 struct vector_type_el
*parsed_type
, char **str
)
805 unsigned element_size
;
806 enum vector_el_type type
;
809 gas_assert (*ptr
== '.');
812 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
817 width
= strtoul (ptr
, &ptr
, 10);
818 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
820 first_error_fmt (_("bad size %d in vector width specifier"), width
);
825 switch (TOLOWER (*ptr
))
853 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
855 first_error (_("missing element size"));
858 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
859 && !(width
== 2 && element_size
== 16))
862 ("invalid element size %d and vector size combination %c"),
868 parsed_type
->type
= type
;
869 parsed_type
->width
= width
;
876 /* *STR contains an SVE zero/merge predication suffix. Parse it into
877 *PARSED_TYPE and point *STR at the end of the suffix. */
880 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
885 gas_assert (*ptr
== '/');
887 switch (TOLOWER (*ptr
))
890 parsed_type
->type
= NT_zero
;
893 parsed_type
->type
= NT_merge
;
896 if (*ptr
!= '\0' && *ptr
!= ',')
897 first_error_fmt (_("unexpected character `%c' in predication type"),
900 first_error (_("missing predication type"));
903 parsed_type
->width
= 0;
908 /* Parse a register of the type TYPE.
910 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
911 name or the parsed register is not of TYPE.
913 Otherwise return the register number, and optionally fill in the actual
914 type of the register in *RTYPE when multiple alternatives were given, and
915 return the register shape and element index information in *TYPEINFO.
917 IN_REG_LIST should be set with TRUE if the caller is parsing a register
921 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
922 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
925 const reg_entry
*reg
= parse_reg (&str
);
926 struct vector_type_el atype
;
927 struct vector_type_el parsetype
;
928 bfd_boolean is_typed_vecreg
= FALSE
;
931 atype
.type
= NT_invtype
;
939 set_default_error ();
943 if (! aarch64_check_reg_type (reg
, type
))
945 DEBUG_TRACE ("reg type check failed");
946 set_default_error ();
951 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
952 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
956 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
961 if (!parse_predication_for_operand (&parsetype
, &str
))
965 /* Register if of the form Vn.[bhsdq]. */
966 is_typed_vecreg
= TRUE
;
968 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
970 /* The width is always variable; we don't allow an integer width
972 gas_assert (parsetype
.width
== 0);
973 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
975 else if (parsetype
.width
== 0)
976 /* Expect index. In the new scheme we cannot have
977 Vn.[bhsdq] represent a scalar. Therefore any
978 Vn.[bhsdq] should have an index following it.
979 Except in reglists ofcourse. */
980 atype
.defined
|= NTA_HASINDEX
;
982 atype
.defined
|= NTA_HASTYPE
;
984 atype
.type
= parsetype
.type
;
985 atype
.width
= parsetype
.width
;
988 if (skip_past_char (&str
, '['))
992 /* Reject Sn[index] syntax. */
993 if (!is_typed_vecreg
)
995 first_error (_("this type of register can't be indexed"));
999 if (in_reg_list
== TRUE
)
1001 first_error (_("index not allowed inside register list"));
1005 atype
.defined
|= NTA_HASINDEX
;
1007 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1009 if (exp
.X_op
!= O_constant
)
1011 first_error (_("constant expression required"));
1015 if (! skip_past_char (&str
, ']'))
1018 atype
.index
= exp
.X_add_number
;
1020 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1022 /* Indexed vector register expected. */
1023 first_error (_("indexed vector register expected"));
1027 /* A vector reg Vn should be typed or indexed. */
1028 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1030 first_error (_("invalid use of vector register"));
1046 Return the register number on success; return PARSE_FAIL otherwise.
1048 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1049 the register (e.g. NEON double or quad reg when either has been requested).
1051 If this is a NEON vector register with additional type information, fill
1052 in the struct pointed to by VECTYPE (if non-NULL).
1054 This parser does not handle register list. */
1057 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1058 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1060 struct vector_type_el atype
;
1062 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1063 /*in_reg_list= */ FALSE
);
1065 if (reg
== PARSE_FAIL
)
1076 static inline bfd_boolean
1077 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1081 && e1
.defined
== e2
.defined
1082 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1085 /* This function parses a list of vector registers of type TYPE.
1086 On success, it returns the parsed register list information in the
1087 following encoded format:
1089 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1090 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1092 The information of the register shape and/or index is returned in
1095 It returns PARSE_FAIL if the register list is invalid.
1097 The list contains one to four registers.
1098 Each register can be one of:
1101 All <T> should be identical.
1102 All <index> should be identical.
1103 There are restrictions on <Vt> numbers which are checked later
1104 (by reg_list_valid_p). */
1107 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1108 struct vector_type_el
*vectype
)
1112 struct vector_type_el typeinfo
, typeinfo_first
;
1117 bfd_boolean error
= FALSE
;
1118 bfd_boolean expect_index
= FALSE
;
1122 set_syntax_error (_("expecting {"));
1128 typeinfo_first
.defined
= 0;
1129 typeinfo_first
.type
= NT_invtype
;
1130 typeinfo_first
.width
= -1;
1131 typeinfo_first
.index
= 0;
1140 str
++; /* skip over '-' */
1143 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1144 /*in_reg_list= */ TRUE
);
1145 if (val
== PARSE_FAIL
)
1147 set_first_syntax_error (_("invalid vector register in list"));
1151 /* reject [bhsd]n */
1152 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1154 set_first_syntax_error (_("invalid scalar register in list"));
1159 if (typeinfo
.defined
& NTA_HASINDEX
)
1160 expect_index
= TRUE
;
1164 if (val
< val_range
)
1166 set_first_syntax_error
1167 (_("invalid range in vector register list"));
1176 typeinfo_first
= typeinfo
;
1177 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1179 set_first_syntax_error
1180 (_("type mismatch in vector register list"));
1185 for (i
= val_range
; i
<= val
; i
++)
1187 ret_val
|= i
<< (5 * nb_regs
);
1192 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1194 skip_whitespace (str
);
1197 set_first_syntax_error (_("end of vector register list not found"));
1202 skip_whitespace (str
);
1206 if (skip_past_char (&str
, '['))
1210 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1211 if (exp
.X_op
!= O_constant
)
1213 set_first_syntax_error (_("constant expression required."));
1216 if (! skip_past_char (&str
, ']'))
1219 typeinfo_first
.index
= exp
.X_add_number
;
1223 set_first_syntax_error (_("expected index"));
1230 set_first_syntax_error (_("too many registers in vector register list"));
1233 else if (nb_regs
== 0)
1235 set_first_syntax_error (_("empty vector register list"));
1241 *vectype
= typeinfo_first
;
1243 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1246 /* Directives: register aliases. */
1249 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1254 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1257 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1260 /* Only warn about a redefinition if it's not defined as the
1262 else if (new->number
!= number
|| new->type
!= type
)
1263 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1268 name
= xstrdup (str
);
1269 new = XNEW (reg_entry
);
1272 new->number
= number
;
1274 new->builtin
= FALSE
;
1276 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1282 /* Look for the .req directive. This is of the form:
1284 new_register_name .req existing_register_name
1286 If we find one, or if it looks sufficiently like one that we want to
1287 handle any error here, return TRUE. Otherwise return FALSE. */
1290 create_register_alias (char *newname
, char *p
)
1292 const reg_entry
*old
;
1293 char *oldname
, *nbuf
;
1296 /* The input scrubber ensures that whitespace after the mnemonic is
1297 collapsed to single spaces. */
1299 if (strncmp (oldname
, " .req ", 6) != 0)
1303 if (*oldname
== '\0')
1306 old
= hash_find (aarch64_reg_hsh
, oldname
);
1309 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1313 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1314 the desired alias name, and p points to its end. If not, then
1315 the desired alias name is in the global original_case_string. */
1316 #ifdef TC_CASE_SENSITIVE
1319 newname
= original_case_string
;
1320 nlen
= strlen (newname
);
1323 nbuf
= xmemdup0 (newname
, nlen
);
1325 /* Create aliases under the new name as stated; an all-lowercase
1326 version of the new name; and an all-uppercase version of the new
1328 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1330 for (p
= nbuf
; *p
; p
++)
1333 if (strncmp (nbuf
, newname
, nlen
))
1335 /* If this attempt to create an additional alias fails, do not bother
1336 trying to create the all-lower case alias. We will fail and issue
1337 a second, duplicate error message. This situation arises when the
1338 programmer does something like:
1341 The second .req creates the "Foo" alias but then fails to create
1342 the artificial FOO alias because it has already been created by the
1344 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1351 for (p
= nbuf
; *p
; p
++)
1354 if (strncmp (nbuf
, newname
, nlen
))
1355 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1362 /* Should never be called, as .req goes between the alias and the
1363 register name, not at the beginning of the line. */
1365 s_req (int a ATTRIBUTE_UNUSED
)
1367 as_bad (_("invalid syntax for .req directive"));
1370 /* The .unreq directive deletes an alias which was previously defined
1371 by .req. For example:
1377 s_unreq (int a ATTRIBUTE_UNUSED
)
1382 name
= input_line_pointer
;
1384 while (*input_line_pointer
!= 0
1385 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1386 ++input_line_pointer
;
1388 saved_char
= *input_line_pointer
;
1389 *input_line_pointer
= 0;
1392 as_bad (_("invalid syntax for .unreq directive"));
1395 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1398 as_bad (_("unknown register alias '%s'"), name
);
1399 else if (reg
->builtin
)
1400 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1407 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1408 free ((char *) reg
->name
);
1411 /* Also locate the all upper case and all lower case versions.
1412 Do not complain if we cannot find one or the other as it
1413 was probably deleted above. */
1415 nbuf
= strdup (name
);
1416 for (p
= nbuf
; *p
; p
++)
1418 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1421 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1422 free ((char *) reg
->name
);
1426 for (p
= nbuf
; *p
; p
++)
1428 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1431 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1432 free ((char *) reg
->name
);
1440 *input_line_pointer
= saved_char
;
1441 demand_empty_rest_of_line ();
1444 /* Directives: Instruction set selection. */
1447 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1448 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1449 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1450 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1452 /* Create a new mapping symbol for the transition to STATE. */
1455 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1458 const char *symname
;
1465 type
= BSF_NO_FLAGS
;
1469 type
= BSF_NO_FLAGS
;
1475 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1476 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1478 /* Save the mapping symbols for future reference. Also check that
1479 we do not place two mapping symbols at the same offset within a
1480 frag. We'll handle overlap between frags in
1481 check_mapping_symbols.
1483 If .fill or other data filling directive generates zero sized data,
1484 the mapping symbol for the following code will have the same value
1485 as the one generated for the data filling directive. In this case,
1486 we replace the old symbol with the new one at the same address. */
1489 if (frag
->tc_frag_data
.first_map
!= NULL
)
1491 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1492 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1495 frag
->tc_frag_data
.first_map
= symbolP
;
1497 if (frag
->tc_frag_data
.last_map
!= NULL
)
1499 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1500 S_GET_VALUE (symbolP
));
1501 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1502 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1505 frag
->tc_frag_data
.last_map
= symbolP
;
1508 /* We must sometimes convert a region marked as code to data during
1509 code alignment, if an odd number of bytes have to be padded. The
1510 code mapping symbol is pushed to an aligned address. */
1513 insert_data_mapping_symbol (enum mstate state
,
1514 valueT value
, fragS
* frag
, offsetT bytes
)
1516 /* If there was already a mapping symbol, remove it. */
1517 if (frag
->tc_frag_data
.last_map
!= NULL
1518 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1519 frag
->fr_address
+ value
)
1521 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1525 know (frag
->tc_frag_data
.first_map
== symp
);
1526 frag
->tc_frag_data
.first_map
= NULL
;
1528 frag
->tc_frag_data
.last_map
= NULL
;
1529 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1532 make_mapping_symbol (MAP_DATA
, value
, frag
);
1533 make_mapping_symbol (state
, value
+ bytes
, frag
);
1536 static void mapping_state_2 (enum mstate state
, int max_chars
);
1538 /* Set the mapping state to STATE. Only call this when about to
1539 emit some STATE bytes to the file. */
1542 mapping_state (enum mstate state
)
1544 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1546 if (state
== MAP_INSN
)
1547 /* AArch64 instructions require 4-byte alignment. When emitting
1548 instructions into any section, record the appropriate section
1550 record_alignment (now_seg
, 2);
1552 if (mapstate
== state
)
1553 /* The mapping symbol has already been emitted.
1554 There is nothing else to do. */
1557 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1558 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1559 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1560 evaluated later in the next else. */
1562 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1564 /* Only add the symbol if the offset is > 0:
1565 if we're at the first frag, check it's size > 0;
1566 if we're not at the first frag, then for sure
1567 the offset is > 0. */
1568 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1569 const int add_symbol
= (frag_now
!= frag_first
)
1570 || (frag_now_fix () > 0);
1573 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1577 mapping_state_2 (state
, 0);
1580 /* Same as mapping_state, but MAX_CHARS bytes have already been
1581 allocated. Put the mapping symbol that far back. */
1584 mapping_state_2 (enum mstate state
, int max_chars
)
1586 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1588 if (!SEG_NORMAL (now_seg
))
1591 if (mapstate
== state
)
1592 /* The mapping symbol has already been emitted.
1593 There is nothing else to do. */
1596 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1597 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1600 #define mapping_state(x) /* nothing */
1601 #define mapping_state_2(x, y) /* nothing */
1604 /* Directives: sectioning and alignment. */
1607 s_bss (int ignore ATTRIBUTE_UNUSED
)
1609 /* We don't support putting frags in the BSS segment, we fake it by
1610 marking in_bss, then looking at s_skip for clues. */
1611 subseg_set (bss_section
, 0);
1612 demand_empty_rest_of_line ();
1613 mapping_state (MAP_DATA
);
1617 s_even (int ignore ATTRIBUTE_UNUSED
)
1619 /* Never make frag if expect extra pass. */
1621 frag_align (1, 0, 0);
1623 record_alignment (now_seg
, 1);
1625 demand_empty_rest_of_line ();
1628 /* Directives: Literal pools. */
1630 static literal_pool
*
1631 find_literal_pool (int size
)
1635 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1637 if (pool
->section
== now_seg
1638 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1645 static literal_pool
*
1646 find_or_make_literal_pool (int size
)
1648 /* Next literal pool ID number. */
1649 static unsigned int latest_pool_num
= 1;
1652 pool
= find_literal_pool (size
);
1656 /* Create a new pool. */
1657 pool
= XNEW (literal_pool
);
1661 /* Currently we always put the literal pool in the current text
1662 section. If we were generating "small" model code where we
1663 knew that all code and initialised data was within 1MB then
1664 we could output literals to mergeable, read-only data
1667 pool
->next_free_entry
= 0;
1668 pool
->section
= now_seg
;
1669 pool
->sub_section
= now_subseg
;
1671 pool
->next
= list_of_pools
;
1672 pool
->symbol
= NULL
;
1674 /* Add it to the list. */
1675 list_of_pools
= pool
;
1678 /* New pools, and emptied pools, will have a NULL symbol. */
1679 if (pool
->symbol
== NULL
)
1681 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1682 (valueT
) 0, &zero_address_frag
);
1683 pool
->id
= latest_pool_num
++;
1690 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1691 Return TRUE on success, otherwise return FALSE. */
1693 add_to_lit_pool (expressionS
*exp
, int size
)
1698 pool
= find_or_make_literal_pool (size
);
1700 /* Check if this literal value is already in the pool. */
1701 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1703 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1705 if ((litexp
->X_op
== exp
->X_op
)
1706 && (exp
->X_op
== O_constant
)
1707 && (litexp
->X_add_number
== exp
->X_add_number
)
1708 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1711 if ((litexp
->X_op
== exp
->X_op
)
1712 && (exp
->X_op
== O_symbol
)
1713 && (litexp
->X_add_number
== exp
->X_add_number
)
1714 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1715 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1719 /* Do we need to create a new entry? */
1720 if (entry
== pool
->next_free_entry
)
1722 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1724 set_syntax_error (_("literal pool overflow"));
1728 pool
->literals
[entry
].exp
= *exp
;
1729 pool
->next_free_entry
+= 1;
1730 if (exp
->X_op
== O_big
)
1732 /* PR 16688: Bignums are held in a single global array. We must
1733 copy and preserve that value now, before it is overwritten. */
1734 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1736 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1737 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1740 pool
->literals
[entry
].bignum
= NULL
;
1743 exp
->X_op
= O_symbol
;
1744 exp
->X_add_number
= ((int) entry
) * size
;
1745 exp
->X_add_symbol
= pool
->symbol
;
1750 /* Can't use symbol_new here, so have to create a symbol and then at
1751 a later date assign it a value. Thats what these functions do. */
1754 symbol_locate (symbolS
* symbolP
,
1755 const char *name
,/* It is copied, the caller can modify. */
1756 segT segment
, /* Segment identifier (SEG_<something>). */
1757 valueT valu
, /* Symbol value. */
1758 fragS
* frag
) /* Associated fragment. */
1761 char *preserved_copy_of_name
;
1763 name_length
= strlen (name
) + 1; /* +1 for \0. */
1764 obstack_grow (¬es
, name
, name_length
);
1765 preserved_copy_of_name
= obstack_finish (¬es
);
1767 #ifdef tc_canonicalize_symbol_name
1768 preserved_copy_of_name
=
1769 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1772 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1774 S_SET_SEGMENT (symbolP
, segment
);
1775 S_SET_VALUE (symbolP
, valu
);
1776 symbol_clear_list_pointers (symbolP
);
1778 symbol_set_frag (symbolP
, frag
);
1780 /* Link to end of symbol chain. */
1782 extern int symbol_table_frozen
;
1784 if (symbol_table_frozen
)
1788 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1790 obj_symbol_new_hook (symbolP
);
1792 #ifdef tc_symbol_new_hook
1793 tc_symbol_new_hook (symbolP
);
1797 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1798 #endif /* DEBUG_SYMS */
1803 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1810 for (align
= 2; align
<= 4; align
++)
1812 int size
= 1 << align
;
1814 pool
= find_literal_pool (size
);
1815 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1818 /* Align pool as you have word accesses.
1819 Only make a frag if we have to. */
1821 frag_align (align
, 0, 0);
1823 mapping_state (MAP_DATA
);
1825 record_alignment (now_seg
, align
);
1827 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1829 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1830 (valueT
) frag_now_fix (), frag_now
);
1831 symbol_table_insert (pool
->symbol
);
1833 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1835 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1837 if (exp
->X_op
== O_big
)
1839 /* PR 16688: Restore the global bignum value. */
1840 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1841 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1842 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1845 /* First output the expression in the instruction to the pool. */
1846 emit_expr (exp
, size
); /* .word|.xword */
1848 if (exp
->X_op
== O_big
)
1850 free (pool
->literals
[entry
].bignum
);
1851 pool
->literals
[entry
].bignum
= NULL
;
1855 /* Mark the pool as empty. */
1856 pool
->next_free_entry
= 0;
1857 pool
->symbol
= NULL
;
1862 /* Forward declarations for functions below, in the MD interface
1864 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1865 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1867 /* Directives: Data. */
1868 /* N.B. the support for relocation suffix in this directive needs to be
1869 implemented properly. */
1872 s_aarch64_elf_cons (int nbytes
)
1876 #ifdef md_flush_pending_output
1877 md_flush_pending_output ();
1880 if (is_it_end_of_statement ())
1882 demand_empty_rest_of_line ();
1886 #ifdef md_cons_align
1887 md_cons_align (nbytes
);
1890 mapping_state (MAP_DATA
);
1893 struct reloc_table_entry
*reloc
;
1897 if (exp
.X_op
!= O_symbol
)
1898 emit_expr (&exp
, (unsigned int) nbytes
);
1901 skip_past_char (&input_line_pointer
, '#');
1902 if (skip_past_char (&input_line_pointer
, ':'))
1904 reloc
= find_reloc_table_entry (&input_line_pointer
);
1906 as_bad (_("unrecognized relocation suffix"));
1908 as_bad (_("unimplemented relocation suffix"));
1909 ignore_rest_of_line ();
1913 emit_expr (&exp
, (unsigned int) nbytes
);
1916 while (*input_line_pointer
++ == ',');
1918 /* Put terminator back into stream. */
1919 input_line_pointer
--;
1920 demand_empty_rest_of_line ();
1923 #endif /* OBJ_ELF */
1925 /* Output a 32-bit word, but mark as an instruction. */
1928 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1932 #ifdef md_flush_pending_output
1933 md_flush_pending_output ();
1936 if (is_it_end_of_statement ())
1938 demand_empty_rest_of_line ();
1942 /* Sections are assumed to start aligned. In executable section, there is no
1943 MAP_DATA symbol pending. So we only align the address during
1944 MAP_DATA --> MAP_INSN transition.
1945 For other sections, this is not guaranteed. */
1946 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1947 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1948 frag_align_code (2, 0);
1951 mapping_state (MAP_INSN
);
1957 if (exp
.X_op
!= O_constant
)
1959 as_bad (_("constant expression required"));
1960 ignore_rest_of_line ();
1964 if (target_big_endian
)
1966 unsigned int val
= exp
.X_add_number
;
1967 exp
.X_add_number
= SWAP_32 (val
);
1969 emit_expr (&exp
, 4);
1971 while (*input_line_pointer
++ == ',');
1973 /* Put terminator back into stream. */
1974 input_line_pointer
--;
1975 demand_empty_rest_of_line ();
1979 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1982 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1988 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1989 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1991 demand_empty_rest_of_line ();
1994 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1997 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2001 /* Since we're just labelling the code, there's no need to define a
2004 /* Make sure there is enough room in this frag for the following
2005 blr. This trick only works if the blr follows immediately after
2006 the .tlsdesc directive. */
2008 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2009 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2011 demand_empty_rest_of_line ();
2014 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2017 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2023 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2024 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2026 demand_empty_rest_of_line ();
2028 #endif /* OBJ_ELF */
2030 static void s_aarch64_arch (int);
2031 static void s_aarch64_cpu (int);
2032 static void s_aarch64_arch_extension (int);
2034 /* This table describes all the machine specific pseudo-ops the assembler
2035 has to support. The fields are:
2036 pseudo-op name without dot
2037 function to call to execute this pseudo-op
2038 Integer arg to pass to the function. */
2040 const pseudo_typeS md_pseudo_table
[] = {
2041 /* Never called because '.req' does not start a line. */
2043 {"unreq", s_unreq
, 0},
2045 {"even", s_even
, 0},
2046 {"ltorg", s_ltorg
, 0},
2047 {"pool", s_ltorg
, 0},
2048 {"cpu", s_aarch64_cpu
, 0},
2049 {"arch", s_aarch64_arch
, 0},
2050 {"arch_extension", s_aarch64_arch_extension
, 0},
2051 {"inst", s_aarch64_inst
, 0},
2053 {"tlsdescadd", s_tlsdescadd
, 0},
2054 {"tlsdesccall", s_tlsdesccall
, 0},
2055 {"tlsdescldr", s_tlsdescldr
, 0},
2056 {"word", s_aarch64_elf_cons
, 4},
2057 {"long", s_aarch64_elf_cons
, 4},
2058 {"xword", s_aarch64_elf_cons
, 8},
2059 {"dword", s_aarch64_elf_cons
, 8},
2065 /* Check whether STR points to a register name followed by a comma or the
2066 end of line; REG_TYPE indicates which register types are checked
2067 against. Return TRUE if STR is such a register name; otherwise return
2068 FALSE. The function does not intend to produce any diagnostics, but since
2069 the register parser aarch64_reg_parse, which is called by this function,
2070 does produce diagnostics, we call clear_error to clear any diagnostics
2071 that may be generated by aarch64_reg_parse.
2072 Also, the function returns FALSE directly if there is any user error
2073 present at the function entry. This prevents the existing diagnostics
2074 state from being spoiled.
2075 The function currently serves parse_constant_immediate and
2076 parse_big_immediate only. */
2078 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2082 /* Prevent the diagnostics state from being spoiled. */
2086 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2088 /* Clear the parsing error that may be set by the reg parser. */
2091 if (reg
== PARSE_FAIL
)
2094 skip_whitespace (str
);
2095 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2101 /* Parser functions used exclusively in instruction operands. */
2103 /* Parse an immediate expression which may not be constant.
2105 To prevent the expression parser from pushing a register name
2106 into the symbol table as an undefined symbol, firstly a check is
2107 done to find out whether STR is a register of type REG_TYPE followed
2108 by a comma or the end of line. Return FALSE if STR is such a string. */
2111 parse_immediate_expression (char **str
, expressionS
*exp
,
2112 aarch64_reg_type reg_type
)
2114 if (reg_name_p (*str
, reg_type
))
2116 set_recoverable_error (_("immediate operand required"));
2120 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2122 if (exp
->X_op
== O_absent
)
2124 set_fatal_syntax_error (_("missing immediate expression"));
2131 /* Constant immediate-value read function for use in insn parsing.
2132 STR points to the beginning of the immediate (with the optional
2133 leading #); *VAL receives the value. REG_TYPE says which register
2134 names should be treated as registers rather than as symbolic immediates.
2136 Return TRUE on success; otherwise return FALSE. */
2139 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2143 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2146 if (exp
.X_op
!= O_constant
)
2148 set_syntax_error (_("constant expression required"));
2152 *val
= exp
.X_add_number
;
2157 encode_imm_float_bits (uint32_t imm
)
2159 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2160 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2163 /* Return TRUE if the single-precision floating-point value encoded in IMM
2164 can be expressed in the AArch64 8-bit signed floating-point format with
2165 3-bit exponent and normalized 4 bits of precision; in other words, the
2166 floating-point value must be expressable as
2167 (+/-) n / 16 * power (2, r)
2168 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2171 aarch64_imm_float_p (uint32_t imm
)
2173 /* If a single-precision floating-point value has the following bit
2174 pattern, it can be expressed in the AArch64 8-bit floating-point
2177 3 32222222 2221111111111
2178 1 09876543 21098765432109876543210
2179 n Eeeeeexx xxxx0000000000000000000
2181 where n, e and each x are either 0 or 1 independently, with
2186 /* Prepare the pattern for 'Eeeeee'. */
2187 if (((imm
>> 30) & 0x1) == 0)
2188 pattern
= 0x3e000000;
2190 pattern
= 0x40000000;
2192 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2193 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2196 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2197 as an IEEE float without any loss of precision. Store the value in
2201 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2203 /* If a double-precision floating-point value has the following bit
2204 pattern, it can be expressed in a float:
2206 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2207 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2208 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2210 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2211 if Eeee_eeee != 1111_1111
2213 where n, e, s and S are either 0 or 1 independently and where ~ is the
2217 uint32_t high32
= imm
>> 32;
2218 uint32_t low32
= imm
;
2220 /* Lower 29 bits need to be 0s. */
2221 if ((imm
& 0x1fffffff) != 0)
2224 /* Prepare the pattern for 'Eeeeeeeee'. */
2225 if (((high32
>> 30) & 0x1) == 0)
2226 pattern
= 0x38000000;
2228 pattern
= 0x40000000;
2231 if ((high32
& 0x78000000) != pattern
)
2234 /* Check Eeee_eeee != 1111_1111. */
2235 if ((high32
& 0x7ff00000) == 0x47f00000)
2238 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2239 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2240 | (low32
>> 29)); /* 3 S bits. */
2244 /* Return true if we should treat OPERAND as a double-precision
2245 floating-point operand rather than a single-precision one. */
2247 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2249 /* Check for unsuffixed SVE registers, which are allowed
2250 for LDR and STR but not in instructions that require an
2251 immediate. We get better error messages if we arbitrarily
2252 pick one size, parse the immediate normally, and then
2253 report the match failure in the normal way. */
2254 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2255 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2258 /* Parse a floating-point immediate. Return TRUE on success and return the
2259 value in *IMMED in the format of IEEE754 single-precision encoding.
2260 *CCP points to the start of the string; DP_P is TRUE when the immediate
2261 is expected to be in double-precision (N.B. this only matters when
2262 hexadecimal representation is involved). REG_TYPE says which register
2263 names should be treated as registers rather than as symbolic immediates.
2265 This routine accepts any IEEE float; it is up to the callers to reject
2269 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2270 aarch64_reg_type reg_type
)
2274 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2275 int found_fpchar
= 0;
2277 unsigned fpword
= 0;
2278 bfd_boolean hex_p
= FALSE
;
2280 skip_past_char (&str
, '#');
2283 skip_whitespace (fpnum
);
2285 if (strncmp (fpnum
, "0x", 2) == 0)
2287 /* Support the hexadecimal representation of the IEEE754 encoding.
2288 Double-precision is expected when DP_P is TRUE, otherwise the
2289 representation should be in single-precision. */
2290 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2295 if (!can_convert_double_to_float (val
, &fpword
))
2298 else if ((uint64_t) val
> 0xffffffff)
2307 if (reg_name_p (str
, reg_type
))
2309 set_recoverable_error (_("immediate operand required"));
2313 /* We must not accidentally parse an integer as a floating-point number.
2314 Make sure that the value we parse is not an integer by checking for
2315 special characters '.' or 'e'. */
2316 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2317 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2331 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2334 /* Our FP word must be 32 bits (single-precision FP). */
2335 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2337 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2347 set_fatal_syntax_error (_("invalid floating-point constant"));
2351 /* Less-generic immediate-value read function with the possibility of loading
2352 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2355 To prevent the expression parser from pushing a register name into the
2356 symbol table as an undefined symbol, a check is firstly done to find
2357 out whether STR is a register of type REG_TYPE followed by a comma or
2358 the end of line. Return FALSE if STR is such a register. */
2361 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2365 if (reg_name_p (ptr
, reg_type
))
2367 set_syntax_error (_("immediate operand required"));
2371 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2373 if (inst
.reloc
.exp
.X_op
== O_constant
)
2374 *imm
= inst
.reloc
.exp
.X_add_number
;
2381 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2382 if NEED_LIBOPCODES is non-zero, the fixup will need
2383 assistance from the libopcodes. */
2386 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2387 const aarch64_opnd_info
*operand
,
2388 int need_libopcodes_p
)
2390 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2391 reloc
->opnd
= operand
->type
;
2392 if (need_libopcodes_p
)
2393 reloc
->need_libopcodes_p
= 1;
2396 /* Return TRUE if the instruction needs to be fixed up later internally by
2397 the GAS; otherwise return FALSE. */
2399 static inline bfd_boolean
2400 aarch64_gas_internal_fixup_p (void)
2402 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2405 /* Assign the immediate value to the relavant field in *OPERAND if
2406 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2407 needs an internal fixup in a later stage.
2408 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2409 IMM.VALUE that may get assigned with the constant. */
2411 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2412 aarch64_opnd_info
*operand
,
2414 int need_libopcodes_p
,
2417 if (reloc
->exp
.X_op
== O_constant
)
2420 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2422 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2423 reloc
->type
= BFD_RELOC_UNUSED
;
2427 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2428 /* Tell libopcodes to ignore this operand or not. This is helpful
2429 when one of the operands needs to be fixed up later but we need
2430 libopcodes to check the other operands. */
2431 operand
->skip
= skip_p
;
2435 /* Relocation modifiers. Each entry in the table contains the textual
2436 name for the relocation which may be placed before a symbol used as
2437 a load/store offset, or add immediate. It must be surrounded by a
2438 leading and trailing colon, for example:
2440 ldr x0, [x1, #:rello:varsym]
2441 add x0, x1, #:rello:varsym */
2443 struct reloc_table_entry
2447 bfd_reloc_code_real_type adr_type
;
2448 bfd_reloc_code_real_type adrp_type
;
2449 bfd_reloc_code_real_type movw_type
;
2450 bfd_reloc_code_real_type add_type
;
2451 bfd_reloc_code_real_type ldst_type
;
2452 bfd_reloc_code_real_type ld_literal_type
;
2455 static struct reloc_table_entry reloc_table
[] = {
2456 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2461 BFD_RELOC_AARCH64_ADD_LO12
,
2462 BFD_RELOC_AARCH64_LDST_LO12
,
2465 /* Higher 21 bits of pc-relative page offset: ADRP */
2468 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2474 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2477 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2483 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2487 BFD_RELOC_AARCH64_MOVW_G0
,
2492 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2496 BFD_RELOC_AARCH64_MOVW_G0_S
,
2501 /* Less significant bits 0-15 of address/value: MOVK, no check */
2505 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2510 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2514 BFD_RELOC_AARCH64_MOVW_G1
,
2519 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2523 BFD_RELOC_AARCH64_MOVW_G1_S
,
2528 /* Less significant bits 16-31 of address/value: MOVK, no check */
2532 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2537 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2541 BFD_RELOC_AARCH64_MOVW_G2
,
2546 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2550 BFD_RELOC_AARCH64_MOVW_G2_S
,
2555 /* Less significant bits 32-47 of address/value: MOVK, no check */
2559 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2564 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2568 BFD_RELOC_AARCH64_MOVW_G3
,
2573 /* Get to the page containing GOT entry for a symbol. */
2576 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2580 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2582 /* 12 bit offset into the page containing GOT entry for that symbol. */
2588 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2591 /* 0-15 bits of address/value: MOVk, no check. */
2595 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2600 /* Most significant bits 16-31 of address/value: MOVZ. */
2604 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2609 /* 15 bit offset into the page containing GOT entry for that symbol. */
2615 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2618 /* Get to the page containing GOT TLS entry for a symbol */
2619 {"gottprel_g0_nc", 0,
2622 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2627 /* Get to the page containing GOT TLS entry for a symbol */
2631 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2636 /* Get to the page containing GOT TLS entry for a symbol */
2638 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2639 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2645 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2650 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2654 /* Lower 16 bits address/value: MOVk. */
2658 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2663 /* Most significant bits 16-31 of address/value: MOVZ. */
2667 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2672 /* Get to the page containing GOT TLS entry for a symbol */
2674 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2675 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2679 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2681 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2686 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2687 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2690 /* Get to the page containing GOT TLS entry for a symbol.
2691 The same as GD, we allocate two consecutive GOT slots
2692 for module index and module offset, the only difference
2693 with GD is the module offset should be intialized to
2694 zero without any outstanding runtime relocation. */
2696 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2697 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2703 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2704 {"tlsldm_lo12_nc", 0,
2708 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2712 /* 12 bit offset into the module TLS base address. */
2717 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2718 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2721 /* Same as dtprel_lo12, no overflow check. */
2722 {"dtprel_lo12_nc", 0,
2726 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2727 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2730 /* bits[23:12] of offset to the module TLS base address. */
2735 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2739 /* bits[15:0] of offset to the module TLS base address. */
2743 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2748 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2752 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2757 /* bits[31:16] of offset to the module TLS base address. */
2761 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2766 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2770 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2775 /* bits[47:32] of offset to the module TLS base address. */
2779 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2784 /* Lower 16 bit offset into GOT entry for a symbol */
2785 {"tlsdesc_off_g0_nc", 0,
2788 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2793 /* Higher 16 bit offset into GOT entry for a symbol */
2794 {"tlsdesc_off_g1", 0,
2797 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2802 /* Get to the page containing GOT TLS entry for a symbol */
2805 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2809 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2811 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2812 {"gottprel_lo12", 0,
2817 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2820 /* Get tp offset for a symbol. */
2825 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2829 /* Get tp offset for a symbol. */
2834 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2838 /* Get tp offset for a symbol. */
2843 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2847 /* Get tp offset for a symbol. */
2848 {"tprel_lo12_nc", 0,
2852 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2856 /* Most significant bits 32-47 of address/value: MOVZ. */
2860 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2865 /* Most significant bits 16-31 of address/value: MOVZ. */
2869 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2874 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2878 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2883 /* Most significant bits 0-15 of address/value: MOVZ. */
2887 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2892 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2896 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2901 /* 15bit offset from got entry to base address of GOT table. */
2907 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2910 /* 14bit offset from got entry to base address of GOT table. */
2916 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2920 /* Given the address of a pointer pointing to the textual name of a
2921 relocation as may appear in assembler source, attempt to find its
2922 details in reloc_table. The pointer will be updated to the character
2923 after the trailing colon. On failure, NULL will be returned;
2924 otherwise return the reloc_table_entry. */
2926 static struct reloc_table_entry
*
2927 find_reloc_table_entry (char **str
)
2930 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2932 int length
= strlen (reloc_table
[i
].name
);
2934 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2935 && (*str
)[length
] == ':')
2937 *str
+= (length
+ 1);
2938 return &reloc_table
[i
];
2945 /* Mode argument to parse_shift and parser_shifter_operand. */
2946 enum parse_shift_mode
2948 SHIFTED_NONE
, /* no shifter allowed */
2949 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2951 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2953 SHIFTED_LSL
, /* bare "lsl #n" */
2954 SHIFTED_MUL
, /* bare "mul #n" */
2955 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2956 SHIFTED_MUL_VL
, /* "mul vl" */
2957 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2960 /* Parse a <shift> operator on an AArch64 data processing instruction.
2961 Return TRUE on success; otherwise return FALSE. */
2963 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2965 const struct aarch64_name_value_pair
*shift_op
;
2966 enum aarch64_modifier_kind kind
;
2972 for (p
= *str
; ISALPHA (*p
); p
++)
2977 set_syntax_error (_("shift expression expected"));
2981 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2983 if (shift_op
== NULL
)
2985 set_syntax_error (_("shift operator expected"));
2989 kind
= aarch64_get_operand_modifier (shift_op
);
2991 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2993 set_syntax_error (_("invalid use of 'MSL'"));
2997 if (kind
== AARCH64_MOD_MUL
2998 && mode
!= SHIFTED_MUL
2999 && mode
!= SHIFTED_MUL_VL
)
3001 set_syntax_error (_("invalid use of 'MUL'"));
3007 case SHIFTED_LOGIC_IMM
:
3008 if (aarch64_extend_operator_p (kind
) == TRUE
)
3010 set_syntax_error (_("extending shift is not permitted"));
3015 case SHIFTED_ARITH_IMM
:
3016 if (kind
== AARCH64_MOD_ROR
)
3018 set_syntax_error (_("'ROR' shift is not permitted"));
3024 if (kind
!= AARCH64_MOD_LSL
)
3026 set_syntax_error (_("only 'LSL' shift is permitted"));
3032 if (kind
!= AARCH64_MOD_MUL
)
3034 set_syntax_error (_("only 'MUL' is permitted"));
3039 case SHIFTED_MUL_VL
:
3040 /* "MUL VL" consists of two separate tokens. Require the first
3041 token to be "MUL" and look for a following "VL". */
3042 if (kind
== AARCH64_MOD_MUL
)
3044 skip_whitespace (p
);
3045 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3048 kind
= AARCH64_MOD_MUL_VL
;
3052 set_syntax_error (_("only 'MUL VL' is permitted"));
3055 case SHIFTED_REG_OFFSET
:
3056 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3057 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3059 set_fatal_syntax_error
3060 (_("invalid shift for the register offset addressing mode"));
3065 case SHIFTED_LSL_MSL
:
3066 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3068 set_syntax_error (_("invalid shift operator"));
3077 /* Whitespace can appear here if the next thing is a bare digit. */
3078 skip_whitespace (p
);
3080 /* Parse shift amount. */
3082 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3083 exp
.X_op
= O_absent
;
3086 if (is_immediate_prefix (*p
))
3091 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3093 if (kind
== AARCH64_MOD_MUL_VL
)
3094 /* For consistency, give MUL VL the same shift amount as an implicit
3096 operand
->shifter
.amount
= 1;
3097 else if (exp
.X_op
== O_absent
)
3099 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
3101 set_syntax_error (_("missing shift amount"));
3104 operand
->shifter
.amount
= 0;
3106 else if (exp
.X_op
!= O_constant
)
3108 set_syntax_error (_("constant shift amount required"));
3111 /* For parsing purposes, MUL #n has no inherent range. The range
3112 depends on the operand and will be checked by operand-specific
3114 else if (kind
!= AARCH64_MOD_MUL
3115 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3117 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3122 operand
->shifter
.amount
= exp
.X_add_number
;
3123 operand
->shifter
.amount_present
= 1;
3126 operand
->shifter
.operator_present
= 1;
3127 operand
->shifter
.kind
= kind
;
3133 /* Parse a <shifter_operand> for a data processing instruction:
3136 #<immediate>, LSL #imm
3138 Validation of immediate operands is deferred to md_apply_fix.
3140 Return TRUE on success; otherwise return FALSE. */
3143 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3144 enum parse_shift_mode mode
)
3148 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3153 /* Accept an immediate expression. */
3154 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3157 /* Accept optional LSL for arithmetic immediate values. */
3158 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3159 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3162 /* Not accept any shifter for logical immediate values. */
3163 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3164 && parse_shift (&p
, operand
, mode
))
3166 set_syntax_error (_("unexpected shift operator"));
3174 /* Parse a <shifter_operand> for a data processing instruction:
3179 #<immediate>, LSL #imm
3181 where <shift> is handled by parse_shift above, and the last two
3182 cases are handled by the function above.
3184 Validation of immediate operands is deferred to md_apply_fix.
3186 Return TRUE on success; otherwise return FALSE. */
3189 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3190 enum parse_shift_mode mode
)
3192 const reg_entry
*reg
;
3193 aarch64_opnd_qualifier_t qualifier
;
3194 enum aarch64_operand_class opd_class
3195 = aarch64_get_operand_class (operand
->type
);
3197 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3200 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3202 set_syntax_error (_("unexpected register in the immediate operand"));
3206 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3208 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3212 operand
->reg
.regno
= reg
->number
;
3213 operand
->qualifier
= qualifier
;
3215 /* Accept optional shift operation on register. */
3216 if (! skip_past_comma (str
))
3219 if (! parse_shift (str
, operand
, mode
))
3224 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3227 (_("integer register expected in the extended/shifted operand "
3232 /* We have a shifted immediate variable. */
3233 return parse_shifter_operand_imm (str
, operand
, mode
);
3236 /* Return TRUE on success; return FALSE otherwise. */
3239 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3240 enum parse_shift_mode mode
)
3244 /* Determine if we have the sequence of characters #: or just :
3245 coming next. If we do, then we check for a :rello: relocation
3246 modifier. If we don't, punt the whole lot to
3247 parse_shifter_operand. */
3249 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3251 struct reloc_table_entry
*entry
;
3259 /* Try to parse a relocation. Anything else is an error. */
3260 if (!(entry
= find_reloc_table_entry (str
)))
3262 set_syntax_error (_("unknown relocation modifier"));
3266 if (entry
->add_type
== 0)
3269 (_("this relocation modifier is not allowed on this instruction"));
3273 /* Save str before we decompose it. */
3276 /* Next, we parse the expression. */
3277 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3280 /* Record the relocation type (use the ADD variant here). */
3281 inst
.reloc
.type
= entry
->add_type
;
3282 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3284 /* If str is empty, we've reached the end, stop here. */
3288 /* Otherwise, we have a shifted reloc modifier, so rewind to
3289 recover the variable name and continue parsing for the shifter. */
3291 return parse_shifter_operand_imm (str
, operand
, mode
);
3294 return parse_shifter_operand (str
, operand
, mode
);
3297 /* Parse all forms of an address expression. Information is written
3298 to *OPERAND and/or inst.reloc.
3300 The A64 instruction set has the following addressing modes:
3303 [base] // in SIMD ld/st structure
3304 [base{,#0}] // in ld/st exclusive
3306 [base,Xm{,LSL #imm}]
3307 [base,Xm,SXTX {#imm}]
3308 [base,Wm,(S|U)XTW {#imm}]
3313 [base],Xm // in SIMD ld/st structure
3314 PC-relative (literal)
3318 [base,Zm.D{,LSL #imm}]
3319 [base,Zm.S,(S|U)XTW {#imm}]
3320 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3323 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3324 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3325 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3327 (As a convenience, the notation "=immediate" is permitted in conjunction
3328 with the pc-relative literal load instructions to automatically place an
3329 immediate value or symbolic address in a nearby literal pool and generate
3330 a hidden label which references it.)
3332 Upon a successful parsing, the address structure in *OPERAND will be
3333 filled in the following way:
3335 .base_regno = <base>
3336 .offset.is_reg // 1 if the offset is a register
3338 .offset.regno = <Rm>
3340 For different addressing modes defined in the A64 ISA:
3343 .pcrel=0; .preind=1; .postind=0; .writeback=0
3345 .pcrel=0; .preind=1; .postind=0; .writeback=1
3347 .pcrel=0; .preind=0; .postind=1; .writeback=1
3348 PC-relative (literal)
3349 .pcrel=1; .preind=1; .postind=0; .writeback=0
3351 The shift/extension information, if any, will be stored in .shifter.
3352 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3353 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3354 corresponding register.
3356 BASE_TYPE says which types of base register should be accepted and
3357 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3358 is the type of shifter that is allowed for immediate offsets,
3359 or SHIFTED_NONE if none.
3361 In all other respects, it is the caller's responsibility to check
3362 for addressing modes not supported by the instruction, and to set
3366 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3367 aarch64_opnd_qualifier_t
*base_qualifier
,
3368 aarch64_opnd_qualifier_t
*offset_qualifier
,
3369 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3370 enum parse_shift_mode imm_shift_mode
)
3373 const reg_entry
*reg
;
3374 expressionS
*exp
= &inst
.reloc
.exp
;
3376 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3377 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3378 if (! skip_past_char (&p
, '['))
3380 /* =immediate or label. */
3381 operand
->addr
.pcrel
= 1;
3382 operand
->addr
.preind
= 1;
3384 /* #:<reloc_op>:<symbol> */
3385 skip_past_char (&p
, '#');
3386 if (skip_past_char (&p
, ':'))
3388 bfd_reloc_code_real_type ty
;
3389 struct reloc_table_entry
*entry
;
3391 /* Try to parse a relocation modifier. Anything else is
3393 entry
= find_reloc_table_entry (&p
);
3396 set_syntax_error (_("unknown relocation modifier"));
3400 switch (operand
->type
)
3402 case AARCH64_OPND_ADDR_PCREL21
:
3404 ty
= entry
->adr_type
;
3408 ty
= entry
->ld_literal_type
;
3415 (_("this relocation modifier is not allowed on this "
3421 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3423 set_syntax_error (_("invalid relocation expression"));
3427 /* #:<reloc_op>:<expr> */
3428 /* Record the relocation type. */
3429 inst
.reloc
.type
= ty
;
3430 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3435 if (skip_past_char (&p
, '='))
3436 /* =immediate; need to generate the literal in the literal pool. */
3437 inst
.gen_lit_pool
= 1;
3439 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3441 set_syntax_error (_("invalid address"));
3452 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3453 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3455 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3458 operand
->addr
.base_regno
= reg
->number
;
3461 if (skip_past_comma (&p
))
3464 operand
->addr
.preind
= 1;
3466 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3469 if (!aarch64_check_reg_type (reg
, offset_type
))
3471 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3476 operand
->addr
.offset
.regno
= reg
->number
;
3477 operand
->addr
.offset
.is_reg
= 1;
3478 /* Shifted index. */
3479 if (skip_past_comma (&p
))
3482 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3483 /* Use the diagnostics set in parse_shift, so not set new
3484 error message here. */
3488 [base,Xm{,LSL #imm}]
3489 [base,Xm,SXTX {#imm}]
3490 [base,Wm,(S|U)XTW {#imm}] */
3491 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3492 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3493 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3495 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3497 set_syntax_error (_("invalid use of 32-bit register offset"));
3500 if (aarch64_get_qualifier_esize (*base_qualifier
)
3501 != aarch64_get_qualifier_esize (*offset_qualifier
))
3503 set_syntax_error (_("offset has different size from base"));
3507 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3509 set_syntax_error (_("invalid use of 64-bit register offset"));
3515 /* [Xn,#:<reloc_op>:<symbol> */
3516 skip_past_char (&p
, '#');
3517 if (skip_past_char (&p
, ':'))
3519 struct reloc_table_entry
*entry
;
3521 /* Try to parse a relocation modifier. Anything else is
3523 if (!(entry
= find_reloc_table_entry (&p
)))
3525 set_syntax_error (_("unknown relocation modifier"));
3529 if (entry
->ldst_type
== 0)
3532 (_("this relocation modifier is not allowed on this "
3537 /* [Xn,#:<reloc_op>: */
3538 /* We now have the group relocation table entry corresponding to
3539 the name in the assembler source. Next, we parse the
3541 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3543 set_syntax_error (_("invalid relocation expression"));
3547 /* [Xn,#:<reloc_op>:<expr> */
3548 /* Record the load/store relocation type. */
3549 inst
.reloc
.type
= entry
->ldst_type
;
3550 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3554 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3556 set_syntax_error (_("invalid expression in the address"));
3560 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3561 /* [Xn,<expr>,<shifter> */
3562 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3568 if (! skip_past_char (&p
, ']'))
3570 set_syntax_error (_("']' expected"));
3574 if (skip_past_char (&p
, '!'))
3576 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3578 set_syntax_error (_("register offset not allowed in pre-indexed "
3579 "addressing mode"));
3583 operand
->addr
.writeback
= 1;
3585 else if (skip_past_comma (&p
))
3588 operand
->addr
.postind
= 1;
3589 operand
->addr
.writeback
= 1;
3591 if (operand
->addr
.preind
)
3593 set_syntax_error (_("cannot combine pre- and post-indexing"));
3597 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3601 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3603 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3607 operand
->addr
.offset
.regno
= reg
->number
;
3608 operand
->addr
.offset
.is_reg
= 1;
3610 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3613 set_syntax_error (_("invalid expression in the address"));
3618 /* If at this point neither .preind nor .postind is set, we have a
3619 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3620 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3622 if (operand
->addr
.writeback
)
3625 set_syntax_error (_("missing offset in the pre-indexed address"));
3628 operand
->addr
.preind
= 1;
3629 inst
.reloc
.exp
.X_op
= O_constant
;
3630 inst
.reloc
.exp
.X_add_number
= 0;
3637 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3640 parse_address (char **str
, aarch64_opnd_info
*operand
)
3642 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3643 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3644 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3647 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3648 The arguments have the same meaning as for parse_address_main.
3649 Return TRUE on success. */
3651 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3652 aarch64_opnd_qualifier_t
*base_qualifier
,
3653 aarch64_opnd_qualifier_t
*offset_qualifier
)
3655 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3656 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3660 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3661 Return TRUE on success; otherwise return FALSE. */
3663 parse_half (char **str
, int *internal_fixup_p
)
3667 skip_past_char (&p
, '#');
3669 gas_assert (internal_fixup_p
);
3670 *internal_fixup_p
= 0;
3674 struct reloc_table_entry
*entry
;
3676 /* Try to parse a relocation. Anything else is an error. */
3678 if (!(entry
= find_reloc_table_entry (&p
)))
3680 set_syntax_error (_("unknown relocation modifier"));
3684 if (entry
->movw_type
== 0)
3687 (_("this relocation modifier is not allowed on this instruction"));
3691 inst
.reloc
.type
= entry
->movw_type
;
3694 *internal_fixup_p
= 1;
3696 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3703 /* Parse an operand for an ADRP instruction:
3705 Return TRUE on success; otherwise return FALSE. */
3708 parse_adrp (char **str
)
3715 struct reloc_table_entry
*entry
;
3717 /* Try to parse a relocation. Anything else is an error. */
3719 if (!(entry
= find_reloc_table_entry (&p
)))
3721 set_syntax_error (_("unknown relocation modifier"));
3725 if (entry
->adrp_type
== 0)
3728 (_("this relocation modifier is not allowed on this instruction"));
3732 inst
.reloc
.type
= entry
->adrp_type
;
3735 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3737 inst
.reloc
.pc_rel
= 1;
3739 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3746 /* Miscellaneous. */
3748 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3749 of SIZE tokens in which index I gives the token for field value I,
3750 or is null if field value I is invalid. REG_TYPE says which register
3751 names should be treated as registers rather than as symbolic immediates.
3753 Return true on success, moving *STR past the operand and storing the
3754 field value in *VAL. */
3757 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3758 size_t size
, aarch64_reg_type reg_type
)
3764 /* Match C-like tokens. */
3766 while (ISALNUM (*q
))
3769 for (i
= 0; i
< size
; ++i
)
3771 && strncasecmp (array
[i
], p
, q
- p
) == 0
3772 && array
[i
][q
- p
] == 0)
3779 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3782 if (exp
.X_op
== O_constant
3783 && (uint64_t) exp
.X_add_number
< size
)
3785 *val
= exp
.X_add_number
;
3790 /* Use the default error for this operand. */
3794 /* Parse an option for a preload instruction. Returns the encoding for the
3795 option, or PARSE_FAIL. */
3798 parse_pldop (char **str
)
3801 const struct aarch64_name_value_pair
*o
;
3804 while (ISALNUM (*q
))
3807 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3815 /* Parse an option for a barrier instruction. Returns the encoding for the
3816 option, or PARSE_FAIL. */
3819 parse_barrier (char **str
)
3822 const asm_barrier_opt
*o
;
3825 while (ISALPHA (*q
))
3828 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3836 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3837 return 0 if successful. Otherwise return PARSE_FAIL. */
3840 parse_barrier_psb (char **str
,
3841 const struct aarch64_name_value_pair
** hint_opt
)
3844 const struct aarch64_name_value_pair
*o
;
3847 while (ISALPHA (*q
))
3850 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3853 set_fatal_syntax_error
3854 ( _("unknown or missing option to PSB"));
3858 if (o
->value
!= 0x11)
3860 /* PSB only accepts option name 'CSYNC'. */
3862 (_("the specified option is not accepted for PSB"));
3871 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3872 Returns the encoding for the option, or PARSE_FAIL.
3874 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3875 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3877 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3878 field, otherwise as a system register.
3882 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3883 int imple_defined_p
, int pstatefield_p
)
3887 const aarch64_sys_reg
*o
;
3891 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3893 *p
++ = TOLOWER (*q
);
3895 /* Assert that BUF be large enough. */
3896 gas_assert (p
- buf
== q
- *str
);
3898 o
= hash_find (sys_regs
, buf
);
3901 if (!imple_defined_p
)
3905 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3906 unsigned int op0
, op1
, cn
, cm
, op2
;
3908 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3911 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3913 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3918 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3919 as_bad (_("selected processor does not support PSTATE field "
3921 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3922 as_bad (_("selected processor does not support system register "
3924 if (aarch64_sys_reg_deprecated_p (o
))
3925 as_warn (_("system register name '%s' is deprecated and may be "
3926 "removed in a future release"), buf
);
3934 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3935 for the option, or NULL. */
3937 static const aarch64_sys_ins_reg
*
3938 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3942 const aarch64_sys_ins_reg
*o
;
3945 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3947 *p
++ = TOLOWER (*q
);
3950 o
= hash_find (sys_ins_regs
, buf
);
3954 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3955 as_bad (_("selected processor does not support system register "
3962 #define po_char_or_fail(chr) do { \
3963 if (! skip_past_char (&str, chr)) \
3967 #define po_reg_or_fail(regtype) do { \
3968 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3969 if (val == PARSE_FAIL) \
3971 set_default_error (); \
3976 #define po_int_reg_or_fail(reg_type) do { \
3977 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3978 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3980 set_default_error (); \
3983 info->reg.regno = reg->number; \
3984 info->qualifier = qualifier; \
3987 #define po_imm_nc_or_fail() do { \
3988 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3992 #define po_imm_or_fail(min, max) do { \
3993 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3995 if (val < min || val > max) \
3997 set_fatal_syntax_error (_("immediate value out of range "\
3998 #min " to "#max)); \
4003 #define po_enum_or_fail(array) do { \
4004 if (!parse_enum_string (&str, &val, array, \
4005 ARRAY_SIZE (array), imm_reg_type)) \
4009 #define po_misc_or_fail(expr) do { \
4014 /* encode the 12-bit imm field of Add/sub immediate */
4015 static inline uint32_t
4016 encode_addsub_imm (uint32_t imm
)
4021 /* encode the shift amount field of Add/sub immediate */
4022 static inline uint32_t
4023 encode_addsub_imm_shift_amount (uint32_t cnt
)
4029 /* encode the imm field of Adr instruction */
4030 static inline uint32_t
4031 encode_adr_imm (uint32_t imm
)
4033 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4034 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4037 /* encode the immediate field of Move wide immediate */
4038 static inline uint32_t
4039 encode_movw_imm (uint32_t imm
)
4044 /* encode the 26-bit offset of unconditional branch */
4045 static inline uint32_t
4046 encode_branch_ofs_26 (uint32_t ofs
)
4048 return ofs
& ((1 << 26) - 1);
4051 /* encode the 19-bit offset of conditional branch and compare & branch */
4052 static inline uint32_t
4053 encode_cond_branch_ofs_19 (uint32_t ofs
)
4055 return (ofs
& ((1 << 19) - 1)) << 5;
4058 /* encode the 19-bit offset of ld literal */
4059 static inline uint32_t
4060 encode_ld_lit_ofs_19 (uint32_t ofs
)
4062 return (ofs
& ((1 << 19) - 1)) << 5;
4065 /* Encode the 14-bit offset of test & branch. */
4066 static inline uint32_t
4067 encode_tst_branch_ofs_14 (uint32_t ofs
)
4069 return (ofs
& ((1 << 14) - 1)) << 5;
4072 /* Encode the 16-bit imm field of svc/hvc/smc. */
4073 static inline uint32_t
4074 encode_svc_imm (uint32_t imm
)
4079 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4080 static inline uint32_t
4081 reencode_addsub_switch_add_sub (uint32_t opcode
)
4083 return opcode
^ (1 << 30);
4086 static inline uint32_t
4087 reencode_movzn_to_movz (uint32_t opcode
)
4089 return opcode
| (1 << 30);
4092 static inline uint32_t
4093 reencode_movzn_to_movn (uint32_t opcode
)
4095 return opcode
& ~(1 << 30);
4098 /* Overall per-instruction processing. */
4100 /* We need to be able to fix up arbitrary expressions in some statements.
4101 This is so that we can handle symbols that are an arbitrary distance from
4102 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4103 which returns part of an address in a form which will be valid for
4104 a data instruction. We do this by pushing the expression into a symbol
4105 in the expr_section, and creating a fix for that. */
4108 fix_new_aarch64 (fragS
* frag
,
4110 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4120 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4124 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4131 /* Diagnostics on operands errors. */
4133 /* By default, output verbose error message.
4134 Disable the verbose error message by -mno-verbose-error. */
4135 static int verbose_error_p
= 1;
4137 #ifdef DEBUG_AARCH64
4138 /* N.B. this is only for the purpose of debugging. */
4139 const char* operand_mismatch_kind_names
[] =
4142 "AARCH64_OPDE_RECOVERABLE",
4143 "AARCH64_OPDE_SYNTAX_ERROR",
4144 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4145 "AARCH64_OPDE_INVALID_VARIANT",
4146 "AARCH64_OPDE_OUT_OF_RANGE",
4147 "AARCH64_OPDE_UNALIGNED",
4148 "AARCH64_OPDE_REG_LIST",
4149 "AARCH64_OPDE_OTHER_ERROR",
4151 #endif /* DEBUG_AARCH64 */
4153 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4155 When multiple errors of different kinds are found in the same assembly
4156 line, only the error of the highest severity will be picked up for
4157 issuing the diagnostics. */
4159 static inline bfd_boolean
4160 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4161 enum aarch64_operand_error_kind rhs
)
4163 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4164 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4165 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4166 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4167 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4168 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4169 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4170 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4174 /* Helper routine to get the mnemonic name from the assembly instruction
4175 line; should only be called for the diagnosis purpose, as there is
4176 string copy operation involved, which may affect the runtime
4177 performance if used in elsewhere. */
4180 get_mnemonic_name (const char *str
)
4182 static char mnemonic
[32];
4185 /* Get the first 15 bytes and assume that the full name is included. */
4186 strncpy (mnemonic
, str
, 31);
4187 mnemonic
[31] = '\0';
4189 /* Scan up to the end of the mnemonic, which must end in white space,
4190 '.', or end of string. */
4191 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4196 /* Append '...' to the truncated long name. */
4197 if (ptr
- mnemonic
== 31)
4198 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4204 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4206 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4207 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4210 /* Data strutures storing one user error in the assembly code related to
4213 struct operand_error_record
4215 const aarch64_opcode
*opcode
;
4216 aarch64_operand_error detail
;
4217 struct operand_error_record
*next
;
4220 typedef struct operand_error_record operand_error_record
;
4222 struct operand_errors
4224 operand_error_record
*head
;
4225 operand_error_record
*tail
;
4228 typedef struct operand_errors operand_errors
;
4230 /* Top-level data structure reporting user errors for the current line of
4232 The way md_assemble works is that all opcodes sharing the same mnemonic
4233 name are iterated to find a match to the assembly line. In this data
4234 structure, each of the such opcodes will have one operand_error_record
4235 allocated and inserted. In other words, excessive errors related with
4236 a single opcode are disregarded. */
4237 operand_errors operand_error_report
;
4239 /* Free record nodes. */
4240 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4242 /* Initialize the data structure that stores the operand mismatch
4243 information on assembling one line of the assembly code. */
4245 init_operand_error_report (void)
4247 if (operand_error_report
.head
!= NULL
)
4249 gas_assert (operand_error_report
.tail
!= NULL
);
4250 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4251 free_opnd_error_record_nodes
= operand_error_report
.head
;
4252 operand_error_report
.head
= NULL
;
4253 operand_error_report
.tail
= NULL
;
4256 gas_assert (operand_error_report
.tail
== NULL
);
4259 /* Return TRUE if some operand error has been recorded during the
4260 parsing of the current assembly line using the opcode *OPCODE;
4261 otherwise return FALSE. */
4262 static inline bfd_boolean
4263 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4265 operand_error_record
*record
= operand_error_report
.head
;
4266 return record
&& record
->opcode
== opcode
;
4269 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4270 OPCODE field is initialized with OPCODE.
4271 N.B. only one record for each opcode, i.e. the maximum of one error is
4272 recorded for each instruction template. */
4275 add_operand_error_record (const operand_error_record
* new_record
)
4277 const aarch64_opcode
*opcode
= new_record
->opcode
;
4278 operand_error_record
* record
= operand_error_report
.head
;
4280 /* The record may have been created for this opcode. If not, we need
4282 if (! opcode_has_operand_error_p (opcode
))
4284 /* Get one empty record. */
4285 if (free_opnd_error_record_nodes
== NULL
)
4287 record
= XNEW (operand_error_record
);
4291 record
= free_opnd_error_record_nodes
;
4292 free_opnd_error_record_nodes
= record
->next
;
4294 record
->opcode
= opcode
;
4295 /* Insert at the head. */
4296 record
->next
= operand_error_report
.head
;
4297 operand_error_report
.head
= record
;
4298 if (operand_error_report
.tail
== NULL
)
4299 operand_error_report
.tail
= record
;
4301 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4302 && record
->detail
.index
<= new_record
->detail
.index
4303 && operand_error_higher_severity_p (record
->detail
.kind
,
4304 new_record
->detail
.kind
))
4306 /* In the case of multiple errors found on operands related with a
4307 single opcode, only record the error of the leftmost operand and
4308 only if the error is of higher severity. */
4309 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4310 " the existing error %s on operand %d",
4311 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4312 new_record
->detail
.index
,
4313 operand_mismatch_kind_names
[record
->detail
.kind
],
4314 record
->detail
.index
);
4318 record
->detail
= new_record
->detail
;
4322 record_operand_error_info (const aarch64_opcode
*opcode
,
4323 aarch64_operand_error
*error_info
)
4325 operand_error_record record
;
4326 record
.opcode
= opcode
;
4327 record
.detail
= *error_info
;
4328 add_operand_error_record (&record
);
4331 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4332 error message *ERROR, for operand IDX (count from 0). */
4335 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4336 enum aarch64_operand_error_kind kind
,
4339 aarch64_operand_error info
;
4340 memset(&info
, 0, sizeof (info
));
4344 record_operand_error_info (opcode
, &info
);
4348 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4349 enum aarch64_operand_error_kind kind
,
4350 const char* error
, const int *extra_data
)
4352 aarch64_operand_error info
;
4356 info
.data
[0] = extra_data
[0];
4357 info
.data
[1] = extra_data
[1];
4358 info
.data
[2] = extra_data
[2];
4359 record_operand_error_info (opcode
, &info
);
4363 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4364 const char* error
, int lower_bound
,
4367 int data
[3] = {lower_bound
, upper_bound
, 0};
4368 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4372 /* Remove the operand error record for *OPCODE. */
4373 static void ATTRIBUTE_UNUSED
4374 remove_operand_error_record (const aarch64_opcode
*opcode
)
4376 if (opcode_has_operand_error_p (opcode
))
4378 operand_error_record
* record
= operand_error_report
.head
;
4379 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4380 operand_error_report
.head
= record
->next
;
4381 record
->next
= free_opnd_error_record_nodes
;
4382 free_opnd_error_record_nodes
= record
;
4383 if (operand_error_report
.head
== NULL
)
4385 gas_assert (operand_error_report
.tail
== record
);
4386 operand_error_report
.tail
= NULL
;
4391 /* Given the instruction in *INSTR, return the index of the best matched
4392 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4394 Return -1 if there is no qualifier sequence; return the first match
4395 if there is multiple matches found. */
4398 find_best_match (const aarch64_inst
*instr
,
4399 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4401 int i
, num_opnds
, max_num_matched
, idx
;
4403 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4406 DEBUG_TRACE ("no operand");
4410 max_num_matched
= 0;
4413 /* For each pattern. */
4414 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4417 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4419 /* Most opcodes has much fewer patterns in the list. */
4420 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4422 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4426 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4427 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4430 if (num_matched
> max_num_matched
)
4432 max_num_matched
= num_matched
;
4437 DEBUG_TRACE ("return with %d", idx
);
4441 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4442 corresponding operands in *INSTR. */
4445 assign_qualifier_sequence (aarch64_inst
*instr
,
4446 const aarch64_opnd_qualifier_t
*qualifiers
)
4449 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4450 gas_assert (num_opnds
);
4451 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4452 instr
->operands
[i
].qualifier
= *qualifiers
;
4455 /* Print operands for the diagnosis purpose. */
4458 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4459 const aarch64_opnd_info
*opnds
)
4463 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4467 /* We regard the opcode operand info more, however we also look into
4468 the inst->operands to support the disassembling of the optional
4470 The two operand code should be the same in all cases, apart from
4471 when the operand can be optional. */
4472 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4473 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4476 /* Generate the operand string in STR. */
4477 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4481 strcat (buf
, i
== 0 ? " " : ", ");
4483 /* Append the operand string. */
4488 /* Send to stderr a string as information. */
4491 output_info (const char *format
, ...)
4497 file
= as_where (&line
);
4501 fprintf (stderr
, "%s:%u: ", file
, line
);
4503 fprintf (stderr
, "%s: ", file
);
4505 fprintf (stderr
, _("Info: "));
4506 va_start (args
, format
);
4507 vfprintf (stderr
, format
, args
);
4509 (void) putc ('\n', stderr
);
4512 /* Output one operand error record. */
4515 output_operand_error_record (const operand_error_record
*record
, char *str
)
4517 const aarch64_operand_error
*detail
= &record
->detail
;
4518 int idx
= detail
->index
;
4519 const aarch64_opcode
*opcode
= record
->opcode
;
4520 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4521 : AARCH64_OPND_NIL
);
4523 switch (detail
->kind
)
4525 case AARCH64_OPDE_NIL
:
4529 case AARCH64_OPDE_SYNTAX_ERROR
:
4530 case AARCH64_OPDE_RECOVERABLE
:
4531 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4532 case AARCH64_OPDE_OTHER_ERROR
:
4533 /* Use the prepared error message if there is, otherwise use the
4534 operand description string to describe the error. */
4535 if (detail
->error
!= NULL
)
4538 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4540 as_bad (_("%s at operand %d -- `%s'"),
4541 detail
->error
, idx
+ 1, str
);
4545 gas_assert (idx
>= 0);
4546 as_bad (_("operand %d must be %s -- `%s'"), idx
+ 1,
4547 aarch64_get_operand_desc (opd_code
), str
);
4551 case AARCH64_OPDE_INVALID_VARIANT
:
4552 as_bad (_("operand mismatch -- `%s'"), str
);
4553 if (verbose_error_p
)
4555 /* We will try to correct the erroneous instruction and also provide
4556 more information e.g. all other valid variants.
4558 The string representation of the corrected instruction and other
4559 valid variants are generated by
4561 1) obtaining the intermediate representation of the erroneous
4563 2) manipulating the IR, e.g. replacing the operand qualifier;
4564 3) printing out the instruction by calling the printer functions
4565 shared with the disassembler.
4567 The limitation of this method is that the exact input assembly
4568 line cannot be accurately reproduced in some cases, for example an
4569 optional operand present in the actual assembly line will be
4570 omitted in the output; likewise for the optional syntax rules,
4571 e.g. the # before the immediate. Another limitation is that the
4572 assembly symbols and relocation operations in the assembly line
4573 currently cannot be printed out in the error report. Last but not
4574 least, when there is other error(s) co-exist with this error, the
4575 'corrected' instruction may be still incorrect, e.g. given
4576 'ldnp h0,h1,[x0,#6]!'
4577 this diagnosis will provide the version:
4578 'ldnp s0,s1,[x0,#6]!'
4579 which is still not right. */
4580 size_t len
= strlen (get_mnemonic_name (str
));
4584 aarch64_inst
*inst_base
= &inst
.base
;
4585 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4588 reset_aarch64_instruction (&inst
);
4589 inst_base
->opcode
= opcode
;
4591 /* Reset the error report so that there is no side effect on the
4592 following operand parsing. */
4593 init_operand_error_report ();
4596 result
= parse_operands (str
+ len
, opcode
)
4597 && programmer_friendly_fixup (&inst
);
4598 gas_assert (result
);
4599 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4601 gas_assert (!result
);
4603 /* Find the most matched qualifier sequence. */
4604 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4605 gas_assert (qlf_idx
> -1);
4607 /* Assign the qualifiers. */
4608 assign_qualifier_sequence (inst_base
,
4609 opcode
->qualifiers_list
[qlf_idx
]);
4611 /* Print the hint. */
4612 output_info (_(" did you mean this?"));
4613 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4614 print_operands (buf
, opcode
, inst_base
->operands
);
4615 output_info (_(" %s"), buf
);
4617 /* Print out other variant(s) if there is any. */
4619 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4620 output_info (_(" other valid variant(s):"));
4622 /* For each pattern. */
4623 qualifiers_list
= opcode
->qualifiers_list
;
4624 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4626 /* Most opcodes has much fewer patterns in the list.
4627 First NIL qualifier indicates the end in the list. */
4628 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4633 /* Mnemonics name. */
4634 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4636 /* Assign the qualifiers. */
4637 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4639 /* Print instruction. */
4640 print_operands (buf
, opcode
, inst_base
->operands
);
4642 output_info (_(" %s"), buf
);
4648 case AARCH64_OPDE_UNTIED_OPERAND
:
4649 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4650 detail
->index
+ 1, str
);
4653 case AARCH64_OPDE_OUT_OF_RANGE
:
4654 if (detail
->data
[0] != detail
->data
[1])
4655 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4656 detail
->error
? detail
->error
: _("immediate value"),
4657 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4659 as_bad (_("%s must be %d at operand %d -- `%s'"),
4660 detail
->error
? detail
->error
: _("immediate value"),
4661 detail
->data
[0], idx
+ 1, str
);
4664 case AARCH64_OPDE_REG_LIST
:
4665 if (detail
->data
[0] == 1)
4666 as_bad (_("invalid number of registers in the list; "
4667 "only 1 register is expected at operand %d -- `%s'"),
4670 as_bad (_("invalid number of registers in the list; "
4671 "%d registers are expected at operand %d -- `%s'"),
4672 detail
->data
[0], idx
+ 1, str
);
4675 case AARCH64_OPDE_UNALIGNED
:
4676 as_bad (_("immediate value must be a multiple of "
4677 "%d at operand %d -- `%s'"),
4678 detail
->data
[0], idx
+ 1, str
);
4687 /* Process and output the error message about the operand mismatching.
4689 When this function is called, the operand error information had
4690 been collected for an assembly line and there will be multiple
4691 errors in the case of mulitple instruction templates; output the
4692 error message that most closely describes the problem. */
4695 output_operand_error_report (char *str
)
4697 int largest_error_pos
;
4698 const char *msg
= NULL
;
4699 enum aarch64_operand_error_kind kind
;
4700 operand_error_record
*curr
;
4701 operand_error_record
*head
= operand_error_report
.head
;
4702 operand_error_record
*record
= NULL
;
4704 /* No error to report. */
4708 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4710 /* Only one error. */
4711 if (head
== operand_error_report
.tail
)
4713 DEBUG_TRACE ("single opcode entry with error kind: %s",
4714 operand_mismatch_kind_names
[head
->detail
.kind
]);
4715 output_operand_error_record (head
, str
);
4719 /* Find the error kind of the highest severity. */
4720 DEBUG_TRACE ("multiple opcode entres with error kind");
4721 kind
= AARCH64_OPDE_NIL
;
4722 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4724 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4725 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4726 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4727 kind
= curr
->detail
.kind
;
4729 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4731 /* Pick up one of errors of KIND to report. */
4732 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4733 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4735 if (curr
->detail
.kind
!= kind
)
4737 /* If there are multiple errors, pick up the one with the highest
4738 mismatching operand index. In the case of multiple errors with
4739 the equally highest operand index, pick up the first one or the
4740 first one with non-NULL error message. */
4741 if (curr
->detail
.index
> largest_error_pos
4742 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4743 && curr
->detail
.error
!= NULL
))
4745 largest_error_pos
= curr
->detail
.index
;
4747 msg
= record
->detail
.error
;
4751 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4752 DEBUG_TRACE ("Pick up error kind %s to report",
4753 operand_mismatch_kind_names
[record
->detail
.kind
]);
4756 output_operand_error_record (record
, str
);
4759 /* Write an AARCH64 instruction to buf - always little-endian. */
4761 put_aarch64_insn (char *buf
, uint32_t insn
)
4763 unsigned char *where
= (unsigned char *) buf
;
4765 where
[1] = insn
>> 8;
4766 where
[2] = insn
>> 16;
4767 where
[3] = insn
>> 24;
4771 get_aarch64_insn (char *buf
)
4773 unsigned char *where
= (unsigned char *) buf
;
4775 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4780 output_inst (struct aarch64_inst
*new_inst
)
4784 to
= frag_more (INSN_SIZE
);
4786 frag_now
->tc_frag_data
.recorded
= 1;
4788 put_aarch64_insn (to
, inst
.base
.value
);
4790 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4792 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4793 INSN_SIZE
, &inst
.reloc
.exp
,
4796 DEBUG_TRACE ("Prepared relocation fix up");
4797 /* Don't check the addend value against the instruction size,
4798 that's the job of our code in md_apply_fix(). */
4799 fixp
->fx_no_overflow
= 1;
4800 if (new_inst
!= NULL
)
4801 fixp
->tc_fix_data
.inst
= new_inst
;
4802 if (aarch64_gas_internal_fixup_p ())
4804 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4805 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4806 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4810 dwarf2_emit_insn (INSN_SIZE
);
4813 /* Link together opcodes of the same name. */
4817 aarch64_opcode
*opcode
;
4818 struct templates
*next
;
4821 typedef struct templates templates
;
4824 lookup_mnemonic (const char *start
, int len
)
4826 templates
*templ
= NULL
;
4828 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4832 /* Subroutine of md_assemble, responsible for looking up the primary
4833 opcode from the mnemonic the user wrote. STR points to the
4834 beginning of the mnemonic. */
4837 opcode_lookup (char **str
)
4839 char *end
, *base
, *dot
;
4840 const aarch64_cond
*cond
;
4844 /* Scan up to the end of the mnemonic, which must end in white space,
4845 '.', or end of string. */
4847 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4848 if (*end
== '.' && !dot
)
4851 if (end
== base
|| dot
== base
)
4854 inst
.cond
= COND_ALWAYS
;
4856 /* Handle a possible condition. */
4859 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4862 inst
.cond
= cond
->value
;
4878 if (inst
.cond
== COND_ALWAYS
)
4880 /* Look for unaffixed mnemonic. */
4881 return lookup_mnemonic (base
, len
);
4885 /* append ".c" to mnemonic if conditional */
4886 memcpy (condname
, base
, len
);
4887 memcpy (condname
+ len
, ".c", 2);
4890 return lookup_mnemonic (base
, len
);
4896 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4897 to a corresponding operand qualifier. */
4899 static inline aarch64_opnd_qualifier_t
4900 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4902 /* Element size in bytes indexed by vector_el_type. */
4903 const unsigned char ele_size
[5]
4905 const unsigned int ele_base
[5] =
4907 AARCH64_OPND_QLF_V_8B
,
4908 AARCH64_OPND_QLF_V_2H
,
4909 AARCH64_OPND_QLF_V_2S
,
4910 AARCH64_OPND_QLF_V_1D
,
4911 AARCH64_OPND_QLF_V_1Q
4914 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4915 goto vectype_conversion_fail
;
4917 if (vectype
->type
== NT_zero
)
4918 return AARCH64_OPND_QLF_P_Z
;
4919 if (vectype
->type
== NT_merge
)
4920 return AARCH64_OPND_QLF_P_M
;
4922 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4924 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4925 /* Vector element register. */
4926 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4929 /* Vector register. */
4930 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4933 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4934 goto vectype_conversion_fail
;
4936 /* The conversion is by calculating the offset from the base operand
4937 qualifier for the vector type. The operand qualifiers are regular
4938 enough that the offset can established by shifting the vector width by
4939 a vector-type dependent amount. */
4941 if (vectype
->type
== NT_b
)
4943 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4945 else if (vectype
->type
>= NT_d
)
4950 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4951 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4952 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4956 vectype_conversion_fail
:
4957 first_error (_("bad vector arrangement type"));
4958 return AARCH64_OPND_QLF_NIL
;
4961 /* Process an optional operand that is found omitted from the assembly line.
4962 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4963 instruction's opcode entry while IDX is the index of this omitted operand.
4967 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4968 int idx
, aarch64_opnd_info
*operand
)
4970 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4971 gas_assert (optional_operand_p (opcode
, idx
));
4972 gas_assert (!operand
->present
);
4976 case AARCH64_OPND_Rd
:
4977 case AARCH64_OPND_Rn
:
4978 case AARCH64_OPND_Rm
:
4979 case AARCH64_OPND_Rt
:
4980 case AARCH64_OPND_Rt2
:
4981 case AARCH64_OPND_Rs
:
4982 case AARCH64_OPND_Ra
:
4983 case AARCH64_OPND_Rt_SYS
:
4984 case AARCH64_OPND_Rd_SP
:
4985 case AARCH64_OPND_Rn_SP
:
4986 case AARCH64_OPND_Rm_SP
:
4987 case AARCH64_OPND_Fd
:
4988 case AARCH64_OPND_Fn
:
4989 case AARCH64_OPND_Fm
:
4990 case AARCH64_OPND_Fa
:
4991 case AARCH64_OPND_Ft
:
4992 case AARCH64_OPND_Ft2
:
4993 case AARCH64_OPND_Sd
:
4994 case AARCH64_OPND_Sn
:
4995 case AARCH64_OPND_Sm
:
4996 case AARCH64_OPND_Vd
:
4997 case AARCH64_OPND_Vn
:
4998 case AARCH64_OPND_Vm
:
4999 case AARCH64_OPND_VdD1
:
5000 case AARCH64_OPND_VnD1
:
5001 operand
->reg
.regno
= default_value
;
5004 case AARCH64_OPND_Ed
:
5005 case AARCH64_OPND_En
:
5006 case AARCH64_OPND_Em
:
5007 operand
->reglane
.regno
= default_value
;
5010 case AARCH64_OPND_IDX
:
5011 case AARCH64_OPND_BIT_NUM
:
5012 case AARCH64_OPND_IMMR
:
5013 case AARCH64_OPND_IMMS
:
5014 case AARCH64_OPND_SHLL_IMM
:
5015 case AARCH64_OPND_IMM_VLSL
:
5016 case AARCH64_OPND_IMM_VLSR
:
5017 case AARCH64_OPND_CCMP_IMM
:
5018 case AARCH64_OPND_FBITS
:
5019 case AARCH64_OPND_UIMM4
:
5020 case AARCH64_OPND_UIMM3_OP1
:
5021 case AARCH64_OPND_UIMM3_OP2
:
5022 case AARCH64_OPND_IMM
:
5023 case AARCH64_OPND_WIDTH
:
5024 case AARCH64_OPND_UIMM7
:
5025 case AARCH64_OPND_NZCV
:
5026 case AARCH64_OPND_SVE_PATTERN
:
5027 case AARCH64_OPND_SVE_PRFOP
:
5028 operand
->imm
.value
= default_value
;
5031 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5032 operand
->imm
.value
= default_value
;
5033 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5034 operand
->shifter
.amount
= 1;
5037 case AARCH64_OPND_EXCEPTION
:
5038 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5041 case AARCH64_OPND_BARRIER_ISB
:
5042 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5049 /* Process the relocation type for move wide instructions.
5050 Return TRUE on success; otherwise return FALSE. */
5053 process_movw_reloc_info (void)
5058 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5060 if (inst
.base
.opcode
->op
== OP_MOVK
)
5061 switch (inst
.reloc
.type
)
5063 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5064 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5065 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5066 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5067 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5068 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5069 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5071 (_("the specified relocation type is not allowed for MOVK"));
5077 switch (inst
.reloc
.type
)
5079 case BFD_RELOC_AARCH64_MOVW_G0
:
5080 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5081 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5082 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5083 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5084 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5085 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5086 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5087 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5088 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5089 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5092 case BFD_RELOC_AARCH64_MOVW_G1
:
5093 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5094 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5095 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5096 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5097 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5098 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5099 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5100 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5101 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5102 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5105 case BFD_RELOC_AARCH64_MOVW_G2
:
5106 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5107 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5108 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5109 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5112 set_fatal_syntax_error
5113 (_("the specified relocation type is not allowed for 32-bit "
5119 case BFD_RELOC_AARCH64_MOVW_G3
:
5122 set_fatal_syntax_error
5123 (_("the specified relocation type is not allowed for 32-bit "
5130 /* More cases should be added when more MOVW-related relocation types
5131 are supported in GAS. */
5132 gas_assert (aarch64_gas_internal_fixup_p ());
5133 /* The shift amount should have already been set by the parser. */
5136 inst
.base
.operands
[1].shifter
.amount
= shift
;
5140 /* A primitive log caculator. */
5142 static inline unsigned int
5143 get_logsz (unsigned int size
)
5145 const unsigned char ls
[16] =
5146 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5152 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5153 return ls
[size
- 1];
5156 /* Determine and return the real reloc type code for an instruction
5157 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5159 static inline bfd_reloc_code_real_type
5160 ldst_lo12_determine_real_reloc_type (void)
5163 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5164 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5166 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5168 BFD_RELOC_AARCH64_LDST8_LO12
,
5169 BFD_RELOC_AARCH64_LDST16_LO12
,
5170 BFD_RELOC_AARCH64_LDST32_LO12
,
5171 BFD_RELOC_AARCH64_LDST64_LO12
,
5172 BFD_RELOC_AARCH64_LDST128_LO12
5175 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5176 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5177 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5178 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5179 BFD_RELOC_AARCH64_NONE
5182 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5183 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5184 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5185 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5186 BFD_RELOC_AARCH64_NONE
5190 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5191 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5193 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5194 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5196 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5198 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5200 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5202 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5203 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5204 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5205 gas_assert (logsz
<= 3);
5207 gas_assert (logsz
<= 4);
5209 /* In reloc.c, these pseudo relocation types should be defined in similar
5210 order as above reloc_ldst_lo12 array. Because the array index calcuation
5211 below relies on this. */
5212 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5215 /* Check whether a register list REGINFO is valid. The registers must be
5216 numbered in increasing order (modulo 32), in increments of one or two.
5218 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5221 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5224 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5226 uint32_t i
, nb_regs
, prev_regno
, incr
;
5228 nb_regs
= 1 + (reginfo
& 0x3);
5230 prev_regno
= reginfo
& 0x1f;
5231 incr
= accept_alternate
? 2 : 1;
5233 for (i
= 1; i
< nb_regs
; ++i
)
5235 uint32_t curr_regno
;
5237 curr_regno
= reginfo
& 0x1f;
5238 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5240 prev_regno
= curr_regno
;
5246 /* Generic instruction operand parser. This does no encoding and no
5247 semantic validation; it merely squirrels values away in the inst
5248 structure. Returns TRUE or FALSE depending on whether the
5249 specified grammar matched. */
5252 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5255 char *backtrack_pos
= 0;
5256 const enum aarch64_opnd
*operands
= opcode
->operands
;
5257 aarch64_reg_type imm_reg_type
;
5260 skip_whitespace (str
);
5262 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5263 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_VZP
;
5265 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5267 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5270 const reg_entry
*reg
;
5271 int comma_skipped_p
= 0;
5272 aarch64_reg_type rtype
;
5273 struct vector_type_el vectype
;
5274 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5275 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5276 aarch64_reg_type reg_type
;
5278 DEBUG_TRACE ("parse operand %d", i
);
5280 /* Assign the operand code. */
5281 info
->type
= operands
[i
];
5283 if (optional_operand_p (opcode
, i
))
5285 /* Remember where we are in case we need to backtrack. */
5286 gas_assert (!backtrack_pos
);
5287 backtrack_pos
= str
;
5290 /* Expect comma between operands; the backtrack mechanizm will take
5291 care of cases of omitted optional operand. */
5292 if (i
> 0 && ! skip_past_char (&str
, ','))
5294 set_syntax_error (_("comma expected between operands"));
5298 comma_skipped_p
= 1;
5300 switch (operands
[i
])
5302 case AARCH64_OPND_Rd
:
5303 case AARCH64_OPND_Rn
:
5304 case AARCH64_OPND_Rm
:
5305 case AARCH64_OPND_Rt
:
5306 case AARCH64_OPND_Rt2
:
5307 case AARCH64_OPND_Rs
:
5308 case AARCH64_OPND_Ra
:
5309 case AARCH64_OPND_Rt_SYS
:
5310 case AARCH64_OPND_PAIRREG
:
5311 case AARCH64_OPND_SVE_Rm
:
5312 po_int_reg_or_fail (REG_TYPE_R_Z
);
5315 case AARCH64_OPND_Rd_SP
:
5316 case AARCH64_OPND_Rn_SP
:
5317 case AARCH64_OPND_SVE_Rn_SP
:
5318 case AARCH64_OPND_Rm_SP
:
5319 po_int_reg_or_fail (REG_TYPE_R_SP
);
5322 case AARCH64_OPND_Rm_EXT
:
5323 case AARCH64_OPND_Rm_SFT
:
5324 po_misc_or_fail (parse_shifter_operand
5325 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5327 : SHIFTED_LOGIC_IMM
)));
5328 if (!info
->shifter
.operator_present
)
5330 /* Default to LSL if not present. Libopcodes prefers shifter
5331 kind to be explicit. */
5332 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5333 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5334 /* For Rm_EXT, libopcodes will carry out further check on whether
5335 or not stack pointer is used in the instruction (Recall that
5336 "the extend operator is not optional unless at least one of
5337 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5341 case AARCH64_OPND_Fd
:
5342 case AARCH64_OPND_Fn
:
5343 case AARCH64_OPND_Fm
:
5344 case AARCH64_OPND_Fa
:
5345 case AARCH64_OPND_Ft
:
5346 case AARCH64_OPND_Ft2
:
5347 case AARCH64_OPND_Sd
:
5348 case AARCH64_OPND_Sn
:
5349 case AARCH64_OPND_Sm
:
5350 case AARCH64_OPND_SVE_VZn
:
5351 case AARCH64_OPND_SVE_Vd
:
5352 case AARCH64_OPND_SVE_Vm
:
5353 case AARCH64_OPND_SVE_Vn
:
5354 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5355 if (val
== PARSE_FAIL
)
5357 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5360 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5362 info
->reg
.regno
= val
;
5363 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5366 case AARCH64_OPND_SVE_Pd
:
5367 case AARCH64_OPND_SVE_Pg3
:
5368 case AARCH64_OPND_SVE_Pg4_5
:
5369 case AARCH64_OPND_SVE_Pg4_10
:
5370 case AARCH64_OPND_SVE_Pg4_16
:
5371 case AARCH64_OPND_SVE_Pm
:
5372 case AARCH64_OPND_SVE_Pn
:
5373 case AARCH64_OPND_SVE_Pt
:
5374 reg_type
= REG_TYPE_PN
;
5377 case AARCH64_OPND_SVE_Za_5
:
5378 case AARCH64_OPND_SVE_Za_16
:
5379 case AARCH64_OPND_SVE_Zd
:
5380 case AARCH64_OPND_SVE_Zm_5
:
5381 case AARCH64_OPND_SVE_Zm_16
:
5382 case AARCH64_OPND_SVE_Zn
:
5383 case AARCH64_OPND_SVE_Zt
:
5384 reg_type
= REG_TYPE_ZN
;
5387 case AARCH64_OPND_Vd
:
5388 case AARCH64_OPND_Vn
:
5389 case AARCH64_OPND_Vm
:
5390 reg_type
= REG_TYPE_VN
;
5392 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5393 if (val
== PARSE_FAIL
)
5395 first_error (_(get_reg_expected_msg (reg_type
)));
5398 if (vectype
.defined
& NTA_HASINDEX
)
5401 info
->reg
.regno
= val
;
5402 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5403 && vectype
.type
== NT_invtype
)
5404 /* Unqualified Pn and Zn registers are allowed in certain
5405 contexts. Rely on F_STRICT qualifier checking to catch
5407 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5410 info
->qualifier
= vectype_to_qualifier (&vectype
);
5411 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5416 case AARCH64_OPND_VdD1
:
5417 case AARCH64_OPND_VnD1
:
5418 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5419 if (val
== PARSE_FAIL
)
5421 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5424 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5426 set_fatal_syntax_error
5427 (_("the top half of a 128-bit FP/SIMD register is expected"));
5430 info
->reg
.regno
= val
;
5431 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5432 here; it is correct for the purpose of encoding/decoding since
5433 only the register number is explicitly encoded in the related
5434 instructions, although this appears a bit hacky. */
5435 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5438 case AARCH64_OPND_SVE_Zn_INDEX
:
5439 reg_type
= REG_TYPE_ZN
;
5440 goto vector_reg_index
;
5442 case AARCH64_OPND_Ed
:
5443 case AARCH64_OPND_En
:
5444 case AARCH64_OPND_Em
:
5445 reg_type
= REG_TYPE_VN
;
5447 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5448 if (val
== PARSE_FAIL
)
5450 first_error (_(get_reg_expected_msg (reg_type
)));
5453 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5456 info
->reglane
.regno
= val
;
5457 info
->reglane
.index
= vectype
.index
;
5458 info
->qualifier
= vectype_to_qualifier (&vectype
);
5459 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5463 case AARCH64_OPND_SVE_ZnxN
:
5464 case AARCH64_OPND_SVE_ZtxN
:
5465 reg_type
= REG_TYPE_ZN
;
5466 goto vector_reg_list
;
5468 case AARCH64_OPND_LVn
:
5469 case AARCH64_OPND_LVt
:
5470 case AARCH64_OPND_LVt_AL
:
5471 case AARCH64_OPND_LEt
:
5472 reg_type
= REG_TYPE_VN
;
5474 if (reg_type
== REG_TYPE_ZN
5475 && get_opcode_dependent_value (opcode
) == 1
5478 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5479 if (val
== PARSE_FAIL
)
5481 first_error (_(get_reg_expected_msg (reg_type
)));
5484 info
->reglist
.first_regno
= val
;
5485 info
->reglist
.num_regs
= 1;
5489 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5490 if (val
== PARSE_FAIL
)
5492 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5494 set_fatal_syntax_error (_("invalid register list"));
5497 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5498 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5500 if (operands
[i
] == AARCH64_OPND_LEt
)
5502 if (!(vectype
.defined
& NTA_HASINDEX
))
5504 info
->reglist
.has_index
= 1;
5505 info
->reglist
.index
= vectype
.index
;
5509 if (vectype
.defined
& NTA_HASINDEX
)
5511 if (!(vectype
.defined
& NTA_HASTYPE
))
5513 if (reg_type
== REG_TYPE_ZN
)
5514 set_fatal_syntax_error (_("missing type suffix"));
5518 info
->qualifier
= vectype_to_qualifier (&vectype
);
5519 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5523 case AARCH64_OPND_Cn
:
5524 case AARCH64_OPND_Cm
:
5525 po_reg_or_fail (REG_TYPE_CN
);
5528 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5531 inst
.base
.operands
[i
].reg
.regno
= val
;
5534 case AARCH64_OPND_SHLL_IMM
:
5535 case AARCH64_OPND_IMM_VLSR
:
5536 po_imm_or_fail (1, 64);
5537 info
->imm
.value
= val
;
5540 case AARCH64_OPND_CCMP_IMM
:
5541 case AARCH64_OPND_SIMM5
:
5542 case AARCH64_OPND_FBITS
:
5543 case AARCH64_OPND_UIMM4
:
5544 case AARCH64_OPND_UIMM3_OP1
:
5545 case AARCH64_OPND_UIMM3_OP2
:
5546 case AARCH64_OPND_IMM_VLSL
:
5547 case AARCH64_OPND_IMM
:
5548 case AARCH64_OPND_WIDTH
:
5549 case AARCH64_OPND_SVE_INV_LIMM
:
5550 case AARCH64_OPND_SVE_LIMM
:
5551 case AARCH64_OPND_SVE_LIMM_MOV
:
5552 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5553 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5554 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5555 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5556 case AARCH64_OPND_SVE_SIMM5
:
5557 case AARCH64_OPND_SVE_SIMM5B
:
5558 case AARCH64_OPND_SVE_SIMM6
:
5559 case AARCH64_OPND_SVE_SIMM8
:
5560 case AARCH64_OPND_SVE_UIMM3
:
5561 case AARCH64_OPND_SVE_UIMM7
:
5562 case AARCH64_OPND_SVE_UIMM8
:
5563 case AARCH64_OPND_SVE_UIMM8_53
:
5564 po_imm_nc_or_fail ();
5565 info
->imm
.value
= val
;
5568 case AARCH64_OPND_SVE_AIMM
:
5569 case AARCH64_OPND_SVE_ASIMM
:
5570 po_imm_nc_or_fail ();
5571 info
->imm
.value
= val
;
5572 skip_whitespace (str
);
5573 if (skip_past_comma (&str
))
5574 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5576 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5579 case AARCH64_OPND_SVE_PATTERN
:
5580 po_enum_or_fail (aarch64_sve_pattern_array
);
5581 info
->imm
.value
= val
;
5584 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5585 po_enum_or_fail (aarch64_sve_pattern_array
);
5586 info
->imm
.value
= val
;
5587 if (skip_past_comma (&str
)
5588 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5590 if (!info
->shifter
.operator_present
)
5592 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5593 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5594 info
->shifter
.amount
= 1;
5598 case AARCH64_OPND_SVE_PRFOP
:
5599 po_enum_or_fail (aarch64_sve_prfop_array
);
5600 info
->imm
.value
= val
;
5603 case AARCH64_OPND_UIMM7
:
5604 po_imm_or_fail (0, 127);
5605 info
->imm
.value
= val
;
5608 case AARCH64_OPND_IDX
:
5609 case AARCH64_OPND_BIT_NUM
:
5610 case AARCH64_OPND_IMMR
:
5611 case AARCH64_OPND_IMMS
:
5612 po_imm_or_fail (0, 63);
5613 info
->imm
.value
= val
;
5616 case AARCH64_OPND_IMM0
:
5617 po_imm_nc_or_fail ();
5620 set_fatal_syntax_error (_("immediate zero expected"));
5623 info
->imm
.value
= 0;
5626 case AARCH64_OPND_FPIMM0
:
5629 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5630 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5631 it is probably not worth the effort to support it. */
5632 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5635 || !(res2
= parse_constant_immediate (&str
, &val
,
5638 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5640 info
->imm
.value
= 0;
5641 info
->imm
.is_fp
= 1;
5644 set_fatal_syntax_error (_("immediate zero expected"));
5648 case AARCH64_OPND_IMM_MOV
:
5651 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5652 reg_name_p (str
, REG_TYPE_VN
))
5655 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5657 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5658 later. fix_mov_imm_insn will try to determine a machine
5659 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5660 message if the immediate cannot be moved by a single
5662 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5663 inst
.base
.operands
[i
].skip
= 1;
5667 case AARCH64_OPND_SIMD_IMM
:
5668 case AARCH64_OPND_SIMD_IMM_SFT
:
5669 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5671 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5673 /* need_libopcodes_p */ 1,
5676 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5677 shift, we don't check it here; we leave the checking to
5678 the libopcodes (operand_general_constraint_met_p). By
5679 doing this, we achieve better diagnostics. */
5680 if (skip_past_comma (&str
)
5681 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5683 if (!info
->shifter
.operator_present
5684 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5686 /* Default to LSL if not present. Libopcodes prefers shifter
5687 kind to be explicit. */
5688 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5689 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5693 case AARCH64_OPND_FPIMM
:
5694 case AARCH64_OPND_SIMD_FPIMM
:
5695 case AARCH64_OPND_SVE_FPIMM8
:
5700 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5701 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5702 || !aarch64_imm_float_p (qfloat
))
5705 set_fatal_syntax_error (_("invalid floating-point"
5709 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5710 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5714 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5715 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5716 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5721 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5722 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5725 set_fatal_syntax_error (_("invalid floating-point"
5729 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5730 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5734 case AARCH64_OPND_LIMM
:
5735 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5736 SHIFTED_LOGIC_IMM
));
5737 if (info
->shifter
.operator_present
)
5739 set_fatal_syntax_error
5740 (_("shift not allowed for bitmask immediate"));
5743 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5745 /* need_libopcodes_p */ 1,
5749 case AARCH64_OPND_AIMM
:
5750 if (opcode
->op
== OP_ADD
)
5751 /* ADD may have relocation types. */
5752 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5753 SHIFTED_ARITH_IMM
));
5755 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5756 SHIFTED_ARITH_IMM
));
5757 switch (inst
.reloc
.type
)
5759 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5760 info
->shifter
.amount
= 12;
5762 case BFD_RELOC_UNUSED
:
5763 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5764 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5765 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5766 inst
.reloc
.pc_rel
= 0;
5771 info
->imm
.value
= 0;
5772 if (!info
->shifter
.operator_present
)
5774 /* Default to LSL if not present. Libopcodes prefers shifter
5775 kind to be explicit. */
5776 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5777 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5781 case AARCH64_OPND_HALF
:
5783 /* #<imm16> or relocation. */
5784 int internal_fixup_p
;
5785 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5786 if (internal_fixup_p
)
5787 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5788 skip_whitespace (str
);
5789 if (skip_past_comma (&str
))
5791 /* {, LSL #<shift>} */
5792 if (! aarch64_gas_internal_fixup_p ())
5794 set_fatal_syntax_error (_("can't mix relocation modifier "
5795 "with explicit shift"));
5798 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5801 inst
.base
.operands
[i
].shifter
.amount
= 0;
5802 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5803 inst
.base
.operands
[i
].imm
.value
= 0;
5804 if (! process_movw_reloc_info ())
5809 case AARCH64_OPND_EXCEPTION
:
5810 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5812 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5814 /* need_libopcodes_p */ 0,
5818 case AARCH64_OPND_NZCV
:
5820 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5824 info
->imm
.value
= nzcv
->value
;
5827 po_imm_or_fail (0, 15);
5828 info
->imm
.value
= val
;
5832 case AARCH64_OPND_COND
:
5833 case AARCH64_OPND_COND1
:
5838 while (ISALPHA (*str
));
5839 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
5840 if (info
->cond
== NULL
)
5842 set_syntax_error (_("invalid condition"));
5845 else if (operands
[i
] == AARCH64_OPND_COND1
5846 && (info
->cond
->value
& 0xe) == 0xe)
5848 /* Do not allow AL or NV. */
5849 set_default_error ();
5855 case AARCH64_OPND_ADDR_ADRP
:
5856 po_misc_or_fail (parse_adrp (&str
));
5857 /* Clear the value as operand needs to be relocated. */
5858 info
->imm
.value
= 0;
5861 case AARCH64_OPND_ADDR_PCREL14
:
5862 case AARCH64_OPND_ADDR_PCREL19
:
5863 case AARCH64_OPND_ADDR_PCREL21
:
5864 case AARCH64_OPND_ADDR_PCREL26
:
5865 po_misc_or_fail (parse_address (&str
, info
));
5866 if (!info
->addr
.pcrel
)
5868 set_syntax_error (_("invalid pc-relative address"));
5871 if (inst
.gen_lit_pool
5872 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5874 /* Only permit "=value" in the literal load instructions.
5875 The literal will be generated by programmer_friendly_fixup. */
5876 set_syntax_error (_("invalid use of \"=immediate\""));
5879 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5881 set_syntax_error (_("unrecognized relocation suffix"));
5884 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5886 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5887 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5891 info
->imm
.value
= 0;
5892 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5893 switch (opcode
->iclass
)
5897 /* e.g. CBZ or B.COND */
5898 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5899 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5903 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5904 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5908 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5910 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5911 : BFD_RELOC_AARCH64_JUMP26
;
5914 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5915 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5918 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5919 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5925 inst
.reloc
.pc_rel
= 1;
5929 case AARCH64_OPND_ADDR_SIMPLE
:
5930 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5932 /* [<Xn|SP>{, #<simm>}] */
5934 /* First use the normal address-parsing routines, to get
5935 the usual syntax errors. */
5936 po_misc_or_fail (parse_address (&str
, info
));
5937 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5938 || !info
->addr
.preind
|| info
->addr
.postind
5939 || info
->addr
.writeback
)
5941 set_syntax_error (_("invalid addressing mode"));
5945 /* Then retry, matching the specific syntax of these addresses. */
5947 po_char_or_fail ('[');
5948 po_reg_or_fail (REG_TYPE_R64_SP
);
5949 /* Accept optional ", #0". */
5950 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5951 && skip_past_char (&str
, ','))
5953 skip_past_char (&str
, '#');
5954 if (! skip_past_char (&str
, '0'))
5956 set_fatal_syntax_error
5957 (_("the optional immediate offset can only be 0"));
5961 po_char_or_fail (']');
5965 case AARCH64_OPND_ADDR_REGOFF
:
5966 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5967 po_misc_or_fail (parse_address (&str
, info
));
5969 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5970 || !info
->addr
.preind
|| info
->addr
.postind
5971 || info
->addr
.writeback
)
5973 set_syntax_error (_("invalid addressing mode"));
5976 if (!info
->shifter
.operator_present
)
5978 /* Default to LSL if not present. Libopcodes prefers shifter
5979 kind to be explicit. */
5980 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5981 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5983 /* Qualifier to be deduced by libopcodes. */
5986 case AARCH64_OPND_ADDR_SIMM7
:
5987 po_misc_or_fail (parse_address (&str
, info
));
5988 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5989 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5991 set_syntax_error (_("invalid addressing mode"));
5994 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5996 set_syntax_error (_("relocation not allowed"));
5999 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6001 /* need_libopcodes_p */ 1,
6005 case AARCH64_OPND_ADDR_SIMM9
:
6006 case AARCH64_OPND_ADDR_SIMM9_2
:
6007 po_misc_or_fail (parse_address (&str
, info
));
6008 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6009 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6010 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6011 && info
->addr
.writeback
))
6013 set_syntax_error (_("invalid addressing mode"));
6016 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6018 set_syntax_error (_("relocation not allowed"));
6021 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6023 /* need_libopcodes_p */ 1,
6027 case AARCH64_OPND_ADDR_UIMM12
:
6028 po_misc_or_fail (parse_address (&str
, info
));
6029 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6030 || !info
->addr
.preind
|| info
->addr
.writeback
)
6032 set_syntax_error (_("invalid addressing mode"));
6035 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6036 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6037 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6039 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6041 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
6042 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6043 /* Leave qualifier to be determined by libopcodes. */
6046 case AARCH64_OPND_SIMD_ADDR_POST
:
6047 /* [<Xn|SP>], <Xm|#<amount>> */
6048 po_misc_or_fail (parse_address (&str
, info
));
6049 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6051 set_syntax_error (_("invalid addressing mode"));
6054 if (!info
->addr
.offset
.is_reg
)
6056 if (inst
.reloc
.exp
.X_op
== O_constant
)
6057 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6060 set_fatal_syntax_error
6061 (_("writeback value must be an immediate constant"));
6068 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6069 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6070 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6071 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6072 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6073 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6074 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6075 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6076 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6077 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6078 /* [X<n>{, #imm, MUL VL}]
6080 but recognizing SVE registers. */
6081 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6082 &offset_qualifier
));
6083 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6085 set_syntax_error (_("invalid addressing mode"));
6089 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6090 || !info
->addr
.preind
|| info
->addr
.writeback
)
6092 set_syntax_error (_("invalid addressing mode"));
6095 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6096 || inst
.reloc
.exp
.X_op
!= O_constant
)
6098 /* Make sure this has priority over
6099 "invalid addressing mode". */
6100 set_fatal_syntax_error (_("constant offset required"));
6103 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6106 case AARCH64_OPND_SVE_ADDR_RR
:
6107 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6108 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6109 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6110 case AARCH64_OPND_SVE_ADDR_RX
:
6111 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6112 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6113 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6114 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6115 but recognizing SVE registers. */
6116 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6117 &offset_qualifier
));
6118 if (base_qualifier
!= AARCH64_OPND_QLF_X
6119 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6121 set_syntax_error (_("invalid addressing mode"));
6126 case AARCH64_OPND_SVE_ADDR_RZ
:
6127 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6128 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6129 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6130 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6131 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6132 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6133 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6134 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6135 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6136 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6137 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6138 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6139 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6140 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6141 &offset_qualifier
));
6142 if (base_qualifier
!= AARCH64_OPND_QLF_X
6143 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6144 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6146 set_syntax_error (_("invalid addressing mode"));
6149 info
->qualifier
= offset_qualifier
;
6152 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6153 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6154 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6155 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6156 /* [Z<n>.<T>{, #imm}] */
6157 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6158 &offset_qualifier
));
6159 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6160 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6162 set_syntax_error (_("invalid addressing mode"));
6165 info
->qualifier
= base_qualifier
;
6168 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6169 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6170 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6171 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6172 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6176 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6178 here since we get better error messages by leaving it to
6179 the qualifier checking routines. */
6180 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6181 &offset_qualifier
));
6182 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6183 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6184 || offset_qualifier
!= base_qualifier
)
6186 set_syntax_error (_("invalid addressing mode"));
6189 info
->qualifier
= base_qualifier
;
6192 case AARCH64_OPND_SYSREG
:
6193 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
6196 set_syntax_error (_("unknown or missing system register name"));
6199 inst
.base
.operands
[i
].sysreg
= val
;
6202 case AARCH64_OPND_PSTATEFIELD
:
6203 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
6206 set_syntax_error (_("unknown or missing PSTATE field name"));
6209 inst
.base
.operands
[i
].pstatefield
= val
;
6212 case AARCH64_OPND_SYSREG_IC
:
6213 inst
.base
.operands
[i
].sysins_op
=
6214 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6216 case AARCH64_OPND_SYSREG_DC
:
6217 inst
.base
.operands
[i
].sysins_op
=
6218 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6220 case AARCH64_OPND_SYSREG_AT
:
6221 inst
.base
.operands
[i
].sysins_op
=
6222 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6224 case AARCH64_OPND_SYSREG_TLBI
:
6225 inst
.base
.operands
[i
].sysins_op
=
6226 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6228 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6230 set_fatal_syntax_error ( _("unknown or missing operation name"));
6235 case AARCH64_OPND_BARRIER
:
6236 case AARCH64_OPND_BARRIER_ISB
:
6237 val
= parse_barrier (&str
);
6238 if (val
!= PARSE_FAIL
6239 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6241 /* ISB only accepts options name 'sy'. */
6243 (_("the specified option is not accepted in ISB"));
6244 /* Turn off backtrack as this optional operand is present. */
6248 /* This is an extension to accept a 0..15 immediate. */
6249 if (val
== PARSE_FAIL
)
6250 po_imm_or_fail (0, 15);
6251 info
->barrier
= aarch64_barrier_options
+ val
;
6254 case AARCH64_OPND_PRFOP
:
6255 val
= parse_pldop (&str
);
6256 /* This is an extension to accept a 0..31 immediate. */
6257 if (val
== PARSE_FAIL
)
6258 po_imm_or_fail (0, 31);
6259 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6262 case AARCH64_OPND_BARRIER_PSB
:
6263 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6264 if (val
== PARSE_FAIL
)
6269 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6272 /* If we get here, this operand was successfully parsed. */
6273 inst
.base
.operands
[i
].present
= 1;
6277 /* The parse routine should already have set the error, but in case
6278 not, set a default one here. */
6280 set_default_error ();
6282 if (! backtrack_pos
)
6283 goto parse_operands_return
;
6286 /* We reach here because this operand is marked as optional, and
6287 either no operand was supplied or the operand was supplied but it
6288 was syntactically incorrect. In the latter case we report an
6289 error. In the former case we perform a few more checks before
6290 dropping through to the code to insert the default operand. */
6292 char *tmp
= backtrack_pos
;
6293 char endchar
= END_OF_INSN
;
6295 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6297 skip_past_char (&tmp
, ',');
6299 if (*tmp
!= endchar
)
6300 /* The user has supplied an operand in the wrong format. */
6301 goto parse_operands_return
;
6303 /* Make sure there is not a comma before the optional operand.
6304 For example the fifth operand of 'sys' is optional:
6306 sys #0,c0,c0,#0, <--- wrong
6307 sys #0,c0,c0,#0 <--- correct. */
6308 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6310 set_fatal_syntax_error
6311 (_("unexpected comma before the omitted optional operand"));
6312 goto parse_operands_return
;
6316 /* Reaching here means we are dealing with an optional operand that is
6317 omitted from the assembly line. */
6318 gas_assert (optional_operand_p (opcode
, i
));
6320 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6322 /* Try again, skipping the optional operand at backtrack_pos. */
6323 str
= backtrack_pos
;
6326 /* Clear any error record after the omitted optional operand has been
6327 successfully handled. */
6331 /* Check if we have parsed all the operands. */
6332 if (*str
!= '\0' && ! error_p ())
6334 /* Set I to the index of the last present operand; this is
6335 for the purpose of diagnostics. */
6336 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6338 set_fatal_syntax_error
6339 (_("unexpected characters following instruction"));
6342 parse_operands_return
:
6346 DEBUG_TRACE ("parsing FAIL: %s - %s",
6347 operand_mismatch_kind_names
[get_error_kind ()],
6348 get_error_message ());
6349 /* Record the operand error properly; this is useful when there
6350 are multiple instruction templates for a mnemonic name, so that
6351 later on, we can select the error that most closely describes
6353 record_operand_error (opcode
, i
, get_error_kind (),
6354 get_error_message ());
6359 DEBUG_TRACE ("parsing SUCCESS");
6364 /* It does some fix-up to provide some programmer friendly feature while
6365 keeping the libopcodes happy, i.e. libopcodes only accepts
6366 the preferred architectural syntax.
6367 Return FALSE if there is any failure; otherwise return TRUE. */
6370 programmer_friendly_fixup (aarch64_instruction
*instr
)
6372 aarch64_inst
*base
= &instr
->base
;
6373 const aarch64_opcode
*opcode
= base
->opcode
;
6374 enum aarch64_op op
= opcode
->op
;
6375 aarch64_opnd_info
*operands
= base
->operands
;
6377 DEBUG_TRACE ("enter");
6379 switch (opcode
->iclass
)
6382 /* TBNZ Xn|Wn, #uimm6, label
6383 Test and Branch Not Zero: conditionally jumps to label if bit number
6384 uimm6 in register Xn is not zero. The bit number implies the width of
6385 the register, which may be written and should be disassembled as Wn if
6386 uimm is less than 32. */
6387 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6389 if (operands
[1].imm
.value
>= 32)
6391 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6395 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6399 /* LDR Wt, label | =value
6400 As a convenience assemblers will typically permit the notation
6401 "=value" in conjunction with the pc-relative literal load instructions
6402 to automatically place an immediate value or symbolic address in a
6403 nearby literal pool and generate a hidden label which references it.
6404 ISREG has been set to 0 in the case of =value. */
6405 if (instr
->gen_lit_pool
6406 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6408 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6409 if (op
== OP_LDRSW_LIT
)
6411 if (instr
->reloc
.exp
.X_op
!= O_constant
6412 && instr
->reloc
.exp
.X_op
!= O_big
6413 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6415 record_operand_error (opcode
, 1,
6416 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6417 _("constant expression expected"));
6420 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6422 record_operand_error (opcode
, 1,
6423 AARCH64_OPDE_OTHER_ERROR
,
6424 _("literal pool insertion failed"));
6432 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6433 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6434 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6435 A programmer-friendly assembler should accept a destination Xd in
6436 place of Wd, however that is not the preferred form for disassembly.
6438 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6439 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6440 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6441 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6446 /* In the 64-bit form, the final register operand is written as Wm
6447 for all but the (possibly omitted) UXTX/LSL and SXTX
6449 As a programmer-friendly assembler, we accept e.g.
6450 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6451 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6452 int idx
= aarch64_operand_index (opcode
->operands
,
6453 AARCH64_OPND_Rm_EXT
);
6454 gas_assert (idx
== 1 || idx
== 2);
6455 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6456 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6457 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6458 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6459 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6460 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6468 DEBUG_TRACE ("exit with SUCCESS");
6472 /* Check for loads and stores that will cause unpredictable behavior. */
6475 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6477 aarch64_inst
*base
= &instr
->base
;
6478 const aarch64_opcode
*opcode
= base
->opcode
;
6479 const aarch64_opnd_info
*opnds
= base
->operands
;
6480 switch (opcode
->iclass
)
6486 /* Loading/storing the base register is unpredictable if writeback. */
6487 if ((aarch64_get_operand_class (opnds
[0].type
)
6488 == AARCH64_OPND_CLASS_INT_REG
)
6489 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6490 && opnds
[1].addr
.base_regno
!= REG_SP
6491 && opnds
[1].addr
.writeback
)
6492 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6495 case ldstnapair_offs
:
6496 case ldstpair_indexed
:
6497 /* Loading/storing the base register is unpredictable if writeback. */
6498 if ((aarch64_get_operand_class (opnds
[0].type
)
6499 == AARCH64_OPND_CLASS_INT_REG
)
6500 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6501 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6502 && opnds
[2].addr
.base_regno
!= REG_SP
6503 && opnds
[2].addr
.writeback
)
6504 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6505 /* Load operations must load different registers. */
6506 if ((opcode
->opcode
& (1 << 22))
6507 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6508 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6515 /* A wrapper function to interface with libopcodes on encoding and
6516 record the error message if there is any.
6518 Return TRUE on success; otherwise return FALSE. */
6521 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6524 aarch64_operand_error error_info
;
6525 error_info
.kind
= AARCH64_OPDE_NIL
;
6526 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6530 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6531 record_operand_error_info (opcode
, &error_info
);
6536 #ifdef DEBUG_AARCH64
6538 dump_opcode_operands (const aarch64_opcode
*opcode
)
6541 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6543 aarch64_verbose ("\t\t opnd%d: %s", i
,
6544 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6545 ? aarch64_get_operand_name (opcode
->operands
[i
])
6546 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6550 #endif /* DEBUG_AARCH64 */
6552 /* This is the guts of the machine-dependent assembler. STR points to a
6553 machine dependent instruction. This function is supposed to emit
6554 the frags/bytes it assembles to. */
6557 md_assemble (char *str
)
6560 templates
*template;
6561 aarch64_opcode
*opcode
;
6562 aarch64_inst
*inst_base
;
6563 unsigned saved_cond
;
6565 /* Align the previous label if needed. */
6566 if (last_label_seen
!= NULL
)
6568 symbol_set_frag (last_label_seen
, frag_now
);
6569 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6570 S_SET_SEGMENT (last_label_seen
, now_seg
);
6573 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6575 DEBUG_TRACE ("\n\n");
6576 DEBUG_TRACE ("==============================");
6577 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6579 template = opcode_lookup (&p
);
6582 /* It wasn't an instruction, but it might be a register alias of
6583 the form alias .req reg directive. */
6584 if (!create_register_alias (str
, p
))
6585 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6590 skip_whitespace (p
);
6593 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6594 get_mnemonic_name (str
), str
);
6598 init_operand_error_report ();
6600 /* Sections are assumed to start aligned. In executable section, there is no
6601 MAP_DATA symbol pending. So we only align the address during
6602 MAP_DATA --> MAP_INSN transition.
6603 For other sections, this is not guaranteed. */
6604 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6605 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6606 frag_align_code (2, 0);
6608 saved_cond
= inst
.cond
;
6609 reset_aarch64_instruction (&inst
);
6610 inst
.cond
= saved_cond
;
6612 /* Iterate through all opcode entries with the same mnemonic name. */
6615 opcode
= template->opcode
;
6617 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6618 #ifdef DEBUG_AARCH64
6620 dump_opcode_operands (opcode
);
6621 #endif /* DEBUG_AARCH64 */
6623 mapping_state (MAP_INSN
);
6625 inst_base
= &inst
.base
;
6626 inst_base
->opcode
= opcode
;
6628 /* Truly conditionally executed instructions, e.g. b.cond. */
6629 if (opcode
->flags
& F_COND
)
6631 gas_assert (inst
.cond
!= COND_ALWAYS
);
6632 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6633 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6635 else if (inst
.cond
!= COND_ALWAYS
)
6637 /* It shouldn't arrive here, where the assembly looks like a
6638 conditional instruction but the found opcode is unconditional. */
6643 if (parse_operands (p
, opcode
)
6644 && programmer_friendly_fixup (&inst
)
6645 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6647 /* Check that this instruction is supported for this CPU. */
6648 if (!opcode
->avariant
6649 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6651 as_bad (_("selected processor does not support `%s'"), str
);
6655 warn_unpredictable_ldst (&inst
, str
);
6657 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6658 || !inst
.reloc
.need_libopcodes_p
)
6662 /* If there is relocation generated for the instruction,
6663 store the instruction information for the future fix-up. */
6664 struct aarch64_inst
*copy
;
6665 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6666 copy
= XNEW (struct aarch64_inst
);
6667 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6673 template = template->next
;
6674 if (template != NULL
)
6676 reset_aarch64_instruction (&inst
);
6677 inst
.cond
= saved_cond
;
6680 while (template != NULL
);
6682 /* Issue the error messages if any. */
6683 output_operand_error_report (str
);
6686 /* Various frobbings of labels and their addresses. */
6689 aarch64_start_line_hook (void)
6691 last_label_seen
= NULL
;
6695 aarch64_frob_label (symbolS
* sym
)
6697 last_label_seen
= sym
;
6699 dwarf2_emit_label (sym
);
6703 aarch64_data_in_code (void)
6705 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6707 *input_line_pointer
= '/';
6708 input_line_pointer
+= 5;
6709 *input_line_pointer
= 0;
6717 aarch64_canonicalize_symbol_name (char *name
)
6721 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6722 *(name
+ len
- 5) = 0;
6727 /* Table of all register names defined by default. The user can
6728 define additional names with .req. Note that all register names
6729 should appear in both upper and lowercase variants. Some registers
6730 also have mixed-case names. */
6732 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6733 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6734 #define REGSET16(p,t) \
6735 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6736 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6737 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6738 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6739 #define REGSET31(p,t) \
6741 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6742 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6743 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6744 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6745 #define REGSET(p,t) \
6746 REGSET31(p,t), REGNUM(p,31,t)
6748 /* These go into aarch64_reg_hsh hash-table. */
6749 static const reg_entry reg_names
[] = {
6750 /* Integer registers. */
6751 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6752 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6754 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6755 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6757 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6758 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6760 /* Coprocessor register numbers. */
6761 REGSET (c
, CN
), REGSET (C
, CN
),
6763 /* Floating-point single precision registers. */
6764 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6766 /* Floating-point double precision registers. */
6767 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6769 /* Floating-point half precision registers. */
6770 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6772 /* Floating-point byte precision registers. */
6773 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6775 /* Floating-point quad precision registers. */
6776 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6778 /* FP/SIMD registers. */
6779 REGSET (v
, VN
), REGSET (V
, VN
),
6781 /* SVE vector registers. */
6782 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6784 /* SVE predicate registers. */
6785 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6802 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6803 static const asm_nzcv nzcv_names
[] = {
6804 {"nzcv", B (n
, z
, c
, v
)},
6805 {"nzcV", B (n
, z
, c
, V
)},
6806 {"nzCv", B (n
, z
, C
, v
)},
6807 {"nzCV", B (n
, z
, C
, V
)},
6808 {"nZcv", B (n
, Z
, c
, v
)},
6809 {"nZcV", B (n
, Z
, c
, V
)},
6810 {"nZCv", B (n
, Z
, C
, v
)},
6811 {"nZCV", B (n
, Z
, C
, V
)},
6812 {"Nzcv", B (N
, z
, c
, v
)},
6813 {"NzcV", B (N
, z
, c
, V
)},
6814 {"NzCv", B (N
, z
, C
, v
)},
6815 {"NzCV", B (N
, z
, C
, V
)},
6816 {"NZcv", B (N
, Z
, c
, v
)},
6817 {"NZcV", B (N
, Z
, c
, V
)},
6818 {"NZCv", B (N
, Z
, C
, v
)},
6819 {"NZCV", B (N
, Z
, C
, V
)}
6832 /* MD interface: bits in the object file. */
6834 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6835 for use in the a.out file, and stores them in the array pointed to by buf.
6836 This knows about the endian-ness of the target machine and does
6837 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6838 2 (short) and 4 (long) Floating numbers are put out as a series of
6839 LITTLENUMS (shorts, here at least). */
6842 md_number_to_chars (char *buf
, valueT val
, int n
)
6844 if (target_big_endian
)
6845 number_to_chars_bigendian (buf
, val
, n
);
6847 number_to_chars_littleendian (buf
, val
, n
);
6850 /* MD interface: Sections. */
6852 /* Estimate the size of a frag before relaxing. Assume everything fits in
6856 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6862 /* Round up a section size to the appropriate boundary. */
6865 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6870 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6871 of an rs_align_code fragment.
6873 Here we fill the frag with the appropriate info for padding the
6874 output stream. The resulting frag will consist of a fixed (fr_fix)
6875 and of a repeating (fr_var) part.
6877 The fixed content is always emitted before the repeating content and
6878 these two parts are used as follows in constructing the output:
6879 - the fixed part will be used to align to a valid instruction word
6880 boundary, in case that we start at a misaligned address; as no
6881 executable instruction can live at the misaligned location, we
6882 simply fill with zeros;
6883 - the variable part will be used to cover the remaining padding and
6884 we fill using the AArch64 NOP instruction.
6886 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6887 enough storage space for up to 3 bytes for padding the back to a valid
6888 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6891 aarch64_handle_align (fragS
* fragP
)
6893 /* NOP = d503201f */
6894 /* AArch64 instructions are always little-endian. */
6895 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6897 int bytes
, fix
, noop_size
;
6900 if (fragP
->fr_type
!= rs_align_code
)
6903 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6904 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6907 gas_assert (fragP
->tc_frag_data
.recorded
);
6910 noop_size
= sizeof (aarch64_noop
);
6912 fix
= bytes
& (noop_size
- 1);
6916 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6920 fragP
->fr_fix
+= fix
;
6924 memcpy (p
, aarch64_noop
, noop_size
);
6925 fragP
->fr_var
= noop_size
;
6928 /* Perform target specific initialisation of a frag.
6929 Note - despite the name this initialisation is not done when the frag
6930 is created, but only when its type is assigned. A frag can be created
6931 and used a long time before its type is set, so beware of assuming that
6932 this initialisationis performed first. */
6936 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6937 int max_chars ATTRIBUTE_UNUSED
)
6941 #else /* OBJ_ELF is defined. */
6943 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6945 /* Record a mapping symbol for alignment frags. We will delete this
6946 later if the alignment ends up empty. */
6947 if (!fragP
->tc_frag_data
.recorded
)
6948 fragP
->tc_frag_data
.recorded
= 1;
6950 switch (fragP
->fr_type
)
6954 mapping_state_2 (MAP_DATA
, max_chars
);
6957 /* PR 20364: We can get alignment frags in code sections,
6958 so do not just assume that we should use the MAP_DATA state. */
6959 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6962 mapping_state_2 (MAP_INSN
, max_chars
);
6969 /* Initialize the DWARF-2 unwind information for this procedure. */
6972 tc_aarch64_frame_initial_instructions (void)
6974 cfi_add_CFA_def_cfa (REG_SP
, 0);
6976 #endif /* OBJ_ELF */
6978 /* Convert REGNAME to a DWARF-2 register number. */
6981 tc_aarch64_regname_to_dw2regnum (char *regname
)
6983 const reg_entry
*reg
= parse_reg (®name
);
6989 case REG_TYPE_SP_32
:
6990 case REG_TYPE_SP_64
:
7000 return reg
->number
+ 64;
7008 /* Implement DWARF2_ADDR_SIZE. */
7011 aarch64_dwarf2_addr_size (void)
7013 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7017 return bfd_arch_bits_per_address (stdoutput
) / 8;
7020 /* MD interface: Symbol and relocation handling. */
7022 /* Return the address within the segment that a PC-relative fixup is
7023 relative to. For AArch64 PC-relative fixups applied to instructions
7024 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7027 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7029 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7031 /* If this is pc-relative and we are going to emit a relocation
7032 then we just want to put out any pipeline compensation that the linker
7033 will need. Otherwise we want to use the calculated base. */
7035 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7036 || aarch64_force_relocation (fixP
)))
7039 /* AArch64 should be consistent for all pc-relative relocations. */
7040 return base
+ AARCH64_PCREL_OFFSET
;
7043 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7044 Otherwise we have no need to default values of symbols. */
7047 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7050 if (name
[0] == '_' && name
[1] == 'G'
7051 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7055 if (symbol_find (name
))
7056 as_bad (_("GOT already in the symbol table"));
7058 GOT_symbol
= symbol_new (name
, undefined_section
,
7059 (valueT
) 0, &zero_address_frag
);
7069 /* Return non-zero if the indicated VALUE has overflowed the maximum
7070 range expressible by a unsigned number with the indicated number of
7074 unsigned_overflow (valueT value
, unsigned bits
)
7077 if (bits
>= sizeof (valueT
) * 8)
7079 lim
= (valueT
) 1 << bits
;
7080 return (value
>= lim
);
7084 /* Return non-zero if the indicated VALUE has overflowed the maximum
7085 range expressible by an signed number with the indicated number of
7089 signed_overflow (offsetT value
, unsigned bits
)
7092 if (bits
>= sizeof (offsetT
) * 8)
7094 lim
= (offsetT
) 1 << (bits
- 1);
7095 return (value
< -lim
|| value
>= lim
);
7098 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7099 unsigned immediate offset load/store instruction, try to encode it as
7100 an unscaled, 9-bit, signed immediate offset load/store instruction.
7101 Return TRUE if it is successful; otherwise return FALSE.
7103 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7104 in response to the standard LDR/STR mnemonics when the immediate offset is
7105 unambiguous, i.e. when it is negative or unaligned. */
7108 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7111 enum aarch64_op new_op
;
7112 const aarch64_opcode
*new_opcode
;
7114 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7116 switch (instr
->opcode
->op
)
7118 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7119 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7120 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7121 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7122 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7123 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7124 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7125 case OP_STR_POS
: new_op
= OP_STUR
; break;
7126 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7127 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7128 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7129 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7130 default: new_op
= OP_NIL
; break;
7133 if (new_op
== OP_NIL
)
7136 new_opcode
= aarch64_get_opcode (new_op
);
7137 gas_assert (new_opcode
!= NULL
);
7139 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7140 instr
->opcode
->op
, new_opcode
->op
);
7142 aarch64_replace_opcode (instr
, new_opcode
);
7144 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7145 qualifier matching may fail because the out-of-date qualifier will
7146 prevent the operand being updated with a new and correct qualifier. */
7147 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7148 AARCH64_OPND_ADDR_SIMM9
);
7149 gas_assert (idx
== 1);
7150 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7152 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7154 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7160 /* Called by fix_insn to fix a MOV immediate alias instruction.
7162 Operand for a generic move immediate instruction, which is an alias
7163 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7164 a 32-bit/64-bit immediate value into general register. An assembler error
7165 shall result if the immediate cannot be created by a single one of these
7166 instructions. If there is a choice, then to ensure reversability an
7167 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7170 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7172 const aarch64_opcode
*opcode
;
7174 /* Need to check if the destination is SP/ZR. The check has to be done
7175 before any aarch64_replace_opcode. */
7176 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7177 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7179 instr
->operands
[1].imm
.value
= value
;
7180 instr
->operands
[1].skip
= 0;
7184 /* Try the MOVZ alias. */
7185 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7186 aarch64_replace_opcode (instr
, opcode
);
7187 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7188 &instr
->value
, NULL
, NULL
))
7190 put_aarch64_insn (buf
, instr
->value
);
7193 /* Try the MOVK alias. */
7194 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7195 aarch64_replace_opcode (instr
, opcode
);
7196 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7197 &instr
->value
, NULL
, NULL
))
7199 put_aarch64_insn (buf
, instr
->value
);
7204 if (try_mov_bitmask_p
)
7206 /* Try the ORR alias. */
7207 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7208 aarch64_replace_opcode (instr
, opcode
);
7209 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7210 &instr
->value
, NULL
, NULL
))
7212 put_aarch64_insn (buf
, instr
->value
);
7217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7218 _("immediate cannot be moved by a single instruction"));
7221 /* An instruction operand which is immediate related may have symbol used
7222 in the assembly, e.g.
7225 .set u32, 0x00ffff00
7227 At the time when the assembly instruction is parsed, a referenced symbol,
7228 like 'u32' in the above example may not have been seen; a fixS is created
7229 in such a case and is handled here after symbols have been resolved.
7230 Instruction is fixed up with VALUE using the information in *FIXP plus
7231 extra information in FLAGS.
7233 This function is called by md_apply_fix to fix up instructions that need
7234 a fix-up described above but does not involve any linker-time relocation. */
7237 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7241 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7242 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7243 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7247 /* Now the instruction is about to be fixed-up, so the operand that
7248 was previously marked as 'ignored' needs to be unmarked in order
7249 to get the encoding done properly. */
7250 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7251 new_inst
->operands
[idx
].skip
= 0;
7254 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7258 case AARCH64_OPND_EXCEPTION
:
7259 if (unsigned_overflow (value
, 16))
7260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7261 _("immediate out of range"));
7262 insn
= get_aarch64_insn (buf
);
7263 insn
|= encode_svc_imm (value
);
7264 put_aarch64_insn (buf
, insn
);
7267 case AARCH64_OPND_AIMM
:
7268 /* ADD or SUB with immediate.
7269 NOTE this assumes we come here with a add/sub shifted reg encoding
7270 3 322|2222|2 2 2 21111 111111
7271 1 098|7654|3 2 1 09876 543210 98765 43210
7272 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7273 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7274 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7275 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7277 3 322|2222|2 2 221111111111
7278 1 098|7654|3 2 109876543210 98765 43210
7279 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7280 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7281 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7282 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7283 Fields sf Rn Rd are already set. */
7284 insn
= get_aarch64_insn (buf
);
7288 insn
= reencode_addsub_switch_add_sub (insn
);
7292 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7293 && unsigned_overflow (value
, 12))
7295 /* Try to shift the value by 12 to make it fit. */
7296 if (((value
>> 12) << 12) == value
7297 && ! unsigned_overflow (value
, 12 + 12))
7300 insn
|= encode_addsub_imm_shift_amount (1);
7304 if (unsigned_overflow (value
, 12))
7305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7306 _("immediate out of range"));
7308 insn
|= encode_addsub_imm (value
);
7310 put_aarch64_insn (buf
, insn
);
7313 case AARCH64_OPND_SIMD_IMM
:
7314 case AARCH64_OPND_SIMD_IMM_SFT
:
7315 case AARCH64_OPND_LIMM
:
7316 /* Bit mask immediate. */
7317 gas_assert (new_inst
!= NULL
);
7318 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7319 new_inst
->operands
[idx
].imm
.value
= value
;
7320 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7321 &new_inst
->value
, NULL
, NULL
))
7322 put_aarch64_insn (buf
, new_inst
->value
);
7324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7325 _("invalid immediate"));
7328 case AARCH64_OPND_HALF
:
7329 /* 16-bit unsigned immediate. */
7330 if (unsigned_overflow (value
, 16))
7331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7332 _("immediate out of range"));
7333 insn
= get_aarch64_insn (buf
);
7334 insn
|= encode_movw_imm (value
& 0xffff);
7335 put_aarch64_insn (buf
, insn
);
7338 case AARCH64_OPND_IMM_MOV
:
7339 /* Operand for a generic move immediate instruction, which is
7340 an alias instruction that generates a single MOVZ, MOVN or ORR
7341 instruction to loads a 32-bit/64-bit immediate value into general
7342 register. An assembler error shall result if the immediate cannot be
7343 created by a single one of these instructions. If there is a choice,
7344 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7345 and MOVZ or MOVN to ORR. */
7346 gas_assert (new_inst
!= NULL
);
7347 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7350 case AARCH64_OPND_ADDR_SIMM7
:
7351 case AARCH64_OPND_ADDR_SIMM9
:
7352 case AARCH64_OPND_ADDR_SIMM9_2
:
7353 case AARCH64_OPND_ADDR_UIMM12
:
7354 /* Immediate offset in an address. */
7355 insn
= get_aarch64_insn (buf
);
7357 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7358 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7359 || new_inst
->opcode
->operands
[2] == opnd
);
7361 /* Get the index of the address operand. */
7362 if (new_inst
->opcode
->operands
[1] == opnd
)
7363 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7366 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7369 /* Update the resolved offset value. */
7370 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7372 /* Encode/fix-up. */
7373 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7374 &new_inst
->value
, NULL
, NULL
))
7376 put_aarch64_insn (buf
, new_inst
->value
);
7379 else if (new_inst
->opcode
->iclass
== ldst_pos
7380 && try_to_encode_as_unscaled_ldst (new_inst
))
7382 put_aarch64_insn (buf
, new_inst
->value
);
7386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7387 _("immediate offset out of range"));
7392 as_fatal (_("unhandled operand code %d"), opnd
);
7396 /* Apply a fixup (fixP) to segment data, once it has been determined
7397 by our caller that we have all the info we need to fix it up.
7399 Parameter valP is the pointer to the value of the bits. */
7402 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7404 offsetT value
= *valP
;
7406 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7408 unsigned flags
= fixP
->fx_addnumber
;
7410 DEBUG_TRACE ("\n\n");
7411 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7412 DEBUG_TRACE ("Enter md_apply_fix");
7414 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7416 /* Note whether this will delete the relocation. */
7418 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7421 /* Process the relocations. */
7422 switch (fixP
->fx_r_type
)
7424 case BFD_RELOC_NONE
:
7425 /* This will need to go in the object file. */
7430 case BFD_RELOC_8_PCREL
:
7431 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7432 md_number_to_chars (buf
, value
, 1);
7436 case BFD_RELOC_16_PCREL
:
7437 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7438 md_number_to_chars (buf
, value
, 2);
7442 case BFD_RELOC_32_PCREL
:
7443 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7444 md_number_to_chars (buf
, value
, 4);
7448 case BFD_RELOC_64_PCREL
:
7449 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7450 md_number_to_chars (buf
, value
, 8);
7453 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7454 /* We claim that these fixups have been processed here, even if
7455 in fact we generate an error because we do not have a reloc
7456 for them, so tc_gen_reloc() will reject them. */
7458 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7461 _("undefined symbol %s used as an immediate value"),
7462 S_GET_NAME (fixP
->fx_addsy
));
7463 goto apply_fix_return
;
7465 fix_insn (fixP
, flags
, value
);
7468 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7469 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7473 _("pc-relative load offset not word aligned"));
7474 if (signed_overflow (value
, 21))
7475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7476 _("pc-relative load offset out of range"));
7477 insn
= get_aarch64_insn (buf
);
7478 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7479 put_aarch64_insn (buf
, insn
);
7483 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7484 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7486 if (signed_overflow (value
, 21))
7487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7488 _("pc-relative address offset out of range"));
7489 insn
= get_aarch64_insn (buf
);
7490 insn
|= encode_adr_imm (value
);
7491 put_aarch64_insn (buf
, insn
);
7495 case BFD_RELOC_AARCH64_BRANCH19
:
7496 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7500 _("conditional branch target not word aligned"));
7501 if (signed_overflow (value
, 21))
7502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7503 _("conditional branch out of range"));
7504 insn
= get_aarch64_insn (buf
);
7505 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7506 put_aarch64_insn (buf
, insn
);
7510 case BFD_RELOC_AARCH64_TSTBR14
:
7511 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7514 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7515 _("conditional branch target not word aligned"));
7516 if (signed_overflow (value
, 16))
7517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7518 _("conditional branch out of range"));
7519 insn
= get_aarch64_insn (buf
);
7520 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7521 put_aarch64_insn (buf
, insn
);
7525 case BFD_RELOC_AARCH64_CALL26
:
7526 case BFD_RELOC_AARCH64_JUMP26
:
7527 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7531 _("branch target not word aligned"));
7532 if (signed_overflow (value
, 28))
7533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7534 _("branch out of range"));
7535 insn
= get_aarch64_insn (buf
);
7536 insn
|= encode_branch_ofs_26 (value
>> 2);
7537 put_aarch64_insn (buf
, insn
);
7541 case BFD_RELOC_AARCH64_MOVW_G0
:
7542 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7543 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7544 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7547 case BFD_RELOC_AARCH64_MOVW_G1
:
7548 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7549 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7550 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7553 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7555 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7556 /* Should always be exported to object file, see
7557 aarch64_force_relocation(). */
7558 gas_assert (!fixP
->fx_done
);
7559 gas_assert (seg
->use_rela_p
);
7561 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7563 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7564 /* Should always be exported to object file, see
7565 aarch64_force_relocation(). */
7566 gas_assert (!fixP
->fx_done
);
7567 gas_assert (seg
->use_rela_p
);
7569 case BFD_RELOC_AARCH64_MOVW_G2
:
7570 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7571 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7574 case BFD_RELOC_AARCH64_MOVW_G3
:
7577 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7579 insn
= get_aarch64_insn (buf
);
7583 /* REL signed addend must fit in 16 bits */
7584 if (signed_overflow (value
, 16))
7585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7586 _("offset out of range"));
7590 /* Check for overflow and scale. */
7591 switch (fixP
->fx_r_type
)
7593 case BFD_RELOC_AARCH64_MOVW_G0
:
7594 case BFD_RELOC_AARCH64_MOVW_G1
:
7595 case BFD_RELOC_AARCH64_MOVW_G2
:
7596 case BFD_RELOC_AARCH64_MOVW_G3
:
7597 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7598 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7599 if (unsigned_overflow (value
, scale
+ 16))
7600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7601 _("unsigned value out of range"));
7603 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7604 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7605 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7606 /* NOTE: We can only come here with movz or movn. */
7607 if (signed_overflow (value
, scale
+ 16))
7608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7609 _("signed value out of range"));
7612 /* Force use of MOVN. */
7614 insn
= reencode_movzn_to_movn (insn
);
7618 /* Force use of MOVZ. */
7619 insn
= reencode_movzn_to_movz (insn
);
7623 /* Unchecked relocations. */
7629 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7630 insn
|= encode_movw_imm (value
& 0xffff);
7632 put_aarch64_insn (buf
, insn
);
7636 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7637 fixP
->fx_r_type
= (ilp32_p
7638 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7639 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7640 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7641 /* Should always be exported to object file, see
7642 aarch64_force_relocation(). */
7643 gas_assert (!fixP
->fx_done
);
7644 gas_assert (seg
->use_rela_p
);
7647 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7648 fixP
->fx_r_type
= (ilp32_p
7649 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7650 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7651 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7652 /* Should always be exported to object file, see
7653 aarch64_force_relocation(). */
7654 gas_assert (!fixP
->fx_done
);
7655 gas_assert (seg
->use_rela_p
);
7658 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7659 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7660 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7661 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7662 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7663 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7664 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7665 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7666 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7667 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7668 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7669 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7670 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7671 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7672 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7673 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7674 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7675 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7676 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7677 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7678 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7679 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7680 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7681 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7682 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7683 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7684 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7685 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7686 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7687 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7688 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7689 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7690 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7691 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7692 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7693 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7694 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7695 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7696 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7697 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7698 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7699 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7700 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7701 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7702 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7703 /* Should always be exported to object file, see
7704 aarch64_force_relocation(). */
7705 gas_assert (!fixP
->fx_done
);
7706 gas_assert (seg
->use_rela_p
);
7709 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7710 /* Should always be exported to object file, see
7711 aarch64_force_relocation(). */
7712 fixP
->fx_r_type
= (ilp32_p
7713 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7714 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7715 gas_assert (!fixP
->fx_done
);
7716 gas_assert (seg
->use_rela_p
);
7719 case BFD_RELOC_AARCH64_ADD_LO12
:
7720 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7721 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7722 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7723 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7724 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7725 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7726 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7727 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7728 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7729 case BFD_RELOC_AARCH64_LDST128_LO12
:
7730 case BFD_RELOC_AARCH64_LDST16_LO12
:
7731 case BFD_RELOC_AARCH64_LDST32_LO12
:
7732 case BFD_RELOC_AARCH64_LDST64_LO12
:
7733 case BFD_RELOC_AARCH64_LDST8_LO12
:
7734 /* Should always be exported to object file, see
7735 aarch64_force_relocation(). */
7736 gas_assert (!fixP
->fx_done
);
7737 gas_assert (seg
->use_rela_p
);
7740 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7741 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7742 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7745 case BFD_RELOC_UNUSED
:
7746 /* An error will already have been reported. */
7750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7751 _("unexpected %s fixup"),
7752 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7757 /* Free the allocated the struct aarch64_inst.
7758 N.B. currently there are very limited number of fix-up types actually use
7759 this field, so the impact on the performance should be minimal . */
7760 if (fixP
->tc_fix_data
.inst
!= NULL
)
7761 free (fixP
->tc_fix_data
.inst
);
7766 /* Translate internal representation of relocation info to BFD target
7770 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7773 bfd_reloc_code_real_type code
;
7775 reloc
= XNEW (arelent
);
7777 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7778 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7779 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7783 if (section
->use_rela_p
)
7784 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7786 fixp
->fx_offset
= reloc
->address
;
7788 reloc
->addend
= fixp
->fx_offset
;
7790 code
= fixp
->fx_r_type
;
7795 code
= BFD_RELOC_16_PCREL
;
7800 code
= BFD_RELOC_32_PCREL
;
7805 code
= BFD_RELOC_64_PCREL
;
7812 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7813 if (reloc
->howto
== NULL
)
7815 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7817 ("cannot represent %s relocation in this object file format"),
7818 bfd_get_reloc_code_name (code
));
7825 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7828 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7830 bfd_reloc_code_real_type type
;
7834 FIXME: @@ Should look at CPU word size. */
7841 type
= BFD_RELOC_16
;
7844 type
= BFD_RELOC_32
;
7847 type
= BFD_RELOC_64
;
7850 as_bad (_("cannot do %u-byte relocation"), size
);
7851 type
= BFD_RELOC_UNUSED
;
7855 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7859 aarch64_force_relocation (struct fix
*fixp
)
7861 switch (fixp
->fx_r_type
)
7863 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7864 /* Perform these "immediate" internal relocations
7865 even if the symbol is extern or weak. */
7868 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7869 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7870 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7871 /* Pseudo relocs that need to be fixed up according to
7875 case BFD_RELOC_AARCH64_ADD_LO12
:
7876 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7877 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7878 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7879 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7880 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7881 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7882 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7883 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7884 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7885 case BFD_RELOC_AARCH64_LDST128_LO12
:
7886 case BFD_RELOC_AARCH64_LDST16_LO12
:
7887 case BFD_RELOC_AARCH64_LDST32_LO12
:
7888 case BFD_RELOC_AARCH64_LDST64_LO12
:
7889 case BFD_RELOC_AARCH64_LDST8_LO12
:
7890 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7891 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7892 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7893 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7894 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7895 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7896 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7897 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7898 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7899 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7900 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7901 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7902 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7903 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7904 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7905 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7906 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7907 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7908 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7909 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7910 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7911 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7912 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7913 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7914 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7915 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7916 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7917 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7918 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7919 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7920 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7921 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7922 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7923 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7924 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7925 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7926 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7927 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7928 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7929 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7930 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7931 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7932 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7933 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7934 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7935 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7936 /* Always leave these relocations for the linker. */
7943 return generic_force_reloc (fixp
);
7949 elf64_aarch64_target_format (void)
7951 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7953 /* FIXME: What to do for ilp32_p ? */
7954 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7956 if (target_big_endian
)
7957 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7959 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7963 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7965 elf_frob_symbol (symp
, puntp
);
7969 /* MD interface: Finalization. */
7971 /* A good place to do this, although this was probably not intended
7972 for this kind of use. We need to dump the literal pool before
7973 references are made to a null symbol pointer. */
7976 aarch64_cleanup (void)
7980 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7982 /* Put it at the end of the relevant section. */
7983 subseg_set (pool
->section
, pool
->sub_section
);
7989 /* Remove any excess mapping symbols generated for alignment frags in
7990 SEC. We may have created a mapping symbol before a zero byte
7991 alignment; remove it if there's a mapping symbol after the
7994 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7995 void *dummy ATTRIBUTE_UNUSED
)
7997 segment_info_type
*seginfo
= seg_info (sec
);
8000 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8003 for (fragp
= seginfo
->frchainP
->frch_root
;
8004 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8006 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8007 fragS
*next
= fragp
->fr_next
;
8009 /* Variable-sized frags have been converted to fixed size by
8010 this point. But if this was variable-sized to start with,
8011 there will be a fixed-size frag after it. So don't handle
8013 if (sym
== NULL
|| next
== NULL
)
8016 if (S_GET_VALUE (sym
) < next
->fr_address
)
8017 /* Not at the end of this frag. */
8019 know (S_GET_VALUE (sym
) == next
->fr_address
);
8023 if (next
->tc_frag_data
.first_map
!= NULL
)
8025 /* Next frag starts with a mapping symbol. Discard this
8027 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8031 if (next
->fr_next
== NULL
)
8033 /* This mapping symbol is at the end of the section. Discard
8035 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8036 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8040 /* As long as we have empty frags without any mapping symbols,
8042 /* If the next frag is non-empty and does not start with a
8043 mapping symbol, then this mapping symbol is required. */
8044 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8047 next
= next
->fr_next
;
8049 while (next
!= NULL
);
8054 /* Adjust the symbol table. */
8057 aarch64_adjust_symtab (void)
8060 /* Remove any overlapping mapping symbols generated by alignment frags. */
8061 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8062 /* Now do generic ELF adjustments. */
8063 elf_adjust_symtab ();
8068 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8070 const char *hash_err
;
8072 hash_err
= hash_insert (table
, key
, value
);
8074 printf ("Internal Error: Can't hash %s\n", key
);
8078 fill_instruction_hash_table (void)
8080 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8082 while (opcode
->name
!= NULL
)
8084 templates
*templ
, *new_templ
;
8085 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8087 new_templ
= XNEW (templates
);
8088 new_templ
->opcode
= opcode
;
8089 new_templ
->next
= NULL
;
8092 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8095 new_templ
->next
= templ
->next
;
8096 templ
->next
= new_templ
;
8103 convert_to_upper (char *dst
, const char *src
, size_t num
)
8106 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8107 *dst
= TOUPPER (*src
);
8111 /* Assume STR point to a lower-case string, allocate, convert and return
8112 the corresponding upper-case string. */
8113 static inline const char*
8114 get_upper_str (const char *str
)
8117 size_t len
= strlen (str
);
8118 ret
= XNEWVEC (char, len
+ 1);
8119 convert_to_upper (ret
, str
, len
);
8123 /* MD interface: Initialization. */
8131 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8132 || (aarch64_cond_hsh
= hash_new ()) == NULL
8133 || (aarch64_shift_hsh
= hash_new ()) == NULL
8134 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8135 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8136 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8137 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8138 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8139 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8140 || (aarch64_reg_hsh
= hash_new ()) == NULL
8141 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8142 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8143 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8144 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8145 as_fatal (_("virtual memory exhausted"));
8147 fill_instruction_hash_table ();
8149 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8150 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8151 (void *) (aarch64_sys_regs
+ i
));
8153 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8154 checked_hash_insert (aarch64_pstatefield_hsh
,
8155 aarch64_pstatefields
[i
].name
,
8156 (void *) (aarch64_pstatefields
+ i
));
8158 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8159 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8160 aarch64_sys_regs_ic
[i
].name
,
8161 (void *) (aarch64_sys_regs_ic
+ i
));
8163 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8164 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8165 aarch64_sys_regs_dc
[i
].name
,
8166 (void *) (aarch64_sys_regs_dc
+ i
));
8168 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8169 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8170 aarch64_sys_regs_at
[i
].name
,
8171 (void *) (aarch64_sys_regs_at
+ i
));
8173 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8174 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8175 aarch64_sys_regs_tlbi
[i
].name
,
8176 (void *) (aarch64_sys_regs_tlbi
+ i
));
8178 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8179 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8180 (void *) (reg_names
+ i
));
8182 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8183 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8184 (void *) (nzcv_names
+ i
));
8186 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8188 const char *name
= aarch64_operand_modifiers
[i
].name
;
8189 checked_hash_insert (aarch64_shift_hsh
, name
,
8190 (void *) (aarch64_operand_modifiers
+ i
));
8191 /* Also hash the name in the upper case. */
8192 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8193 (void *) (aarch64_operand_modifiers
+ i
));
8196 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8199 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8200 the same condition code. */
8201 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8203 const char *name
= aarch64_conds
[i
].names
[j
];
8206 checked_hash_insert (aarch64_cond_hsh
, name
,
8207 (void *) (aarch64_conds
+ i
));
8208 /* Also hash the name in the upper case. */
8209 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8210 (void *) (aarch64_conds
+ i
));
8214 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8216 const char *name
= aarch64_barrier_options
[i
].name
;
8217 /* Skip xx00 - the unallocated values of option. */
8220 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8221 (void *) (aarch64_barrier_options
+ i
));
8222 /* Also hash the name in the upper case. */
8223 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8224 (void *) (aarch64_barrier_options
+ i
));
8227 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8229 const char* name
= aarch64_prfops
[i
].name
;
8230 /* Skip the unallocated hint encodings. */
8233 checked_hash_insert (aarch64_pldop_hsh
, name
,
8234 (void *) (aarch64_prfops
+ i
));
8235 /* Also hash the name in the upper case. */
8236 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8237 (void *) (aarch64_prfops
+ i
));
8240 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8242 const char* name
= aarch64_hint_options
[i
].name
;
8244 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8245 (void *) (aarch64_hint_options
+ i
));
8246 /* Also hash the name in the upper case. */
8247 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8248 (void *) (aarch64_hint_options
+ i
));
8251 /* Set the cpu variant based on the command-line options. */
8253 mcpu_cpu_opt
= march_cpu_opt
;
8256 mcpu_cpu_opt
= &cpu_default
;
8258 cpu_variant
= *mcpu_cpu_opt
;
8260 /* Record the CPU type. */
8261 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8263 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8266 /* Command line processing. */
8268 const char *md_shortopts
= "m:";
8270 #ifdef AARCH64_BI_ENDIAN
8271 #define OPTION_EB (OPTION_MD_BASE + 0)
8272 #define OPTION_EL (OPTION_MD_BASE + 1)
8274 #if TARGET_BYTES_BIG_ENDIAN
8275 #define OPTION_EB (OPTION_MD_BASE + 0)
8277 #define OPTION_EL (OPTION_MD_BASE + 1)
8281 struct option md_longopts
[] = {
8283 {"EB", no_argument
, NULL
, OPTION_EB
},
8286 {"EL", no_argument
, NULL
, OPTION_EL
},
8288 {NULL
, no_argument
, NULL
, 0}
8291 size_t md_longopts_size
= sizeof (md_longopts
);
8293 struct aarch64_option_table
8295 const char *option
; /* Option name to match. */
8296 const char *help
; /* Help information. */
8297 int *var
; /* Variable to change. */
8298 int value
; /* What to change it to. */
8299 char *deprecated
; /* If non-null, print this message. */
8302 static struct aarch64_option_table aarch64_opts
[] = {
8303 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8304 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8306 #ifdef DEBUG_AARCH64
8307 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8308 #endif /* DEBUG_AARCH64 */
8309 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8311 {"mno-verbose-error", N_("do not output verbose error messages"),
8312 &verbose_error_p
, 0, NULL
},
8313 {NULL
, NULL
, NULL
, 0, NULL
}
8316 struct aarch64_cpu_option_table
8319 const aarch64_feature_set value
;
8320 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8322 const char *canonical_name
;
8325 /* This list should, at a minimum, contain all the cpu names
8326 recognized by GCC. */
8327 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8328 {"all", AARCH64_ANY
, NULL
},
8329 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8330 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8331 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8332 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8333 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8334 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8335 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8336 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8337 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8338 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8339 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8340 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8341 "Samsung Exynos M1"},
8342 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8343 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8345 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8346 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8347 "Qualcomm QDF24XX"},
8348 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8349 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8351 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8352 AARCH64_FEATURE_CRYPTO
),
8354 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8355 in earlier releases and is superseded by 'xgene1' in all
8357 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8358 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8359 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8360 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8361 {"generic", AARCH64_ARCH_V8
, NULL
},
8363 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8366 struct aarch64_arch_option_table
8369 const aarch64_feature_set value
;
8372 /* This list should, at a minimum, contain all the architecture names
8373 recognized by GCC. */
8374 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8375 {"all", AARCH64_ANY
},
8376 {"armv8-a", AARCH64_ARCH_V8
},
8377 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8378 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8379 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8380 {NULL
, AARCH64_ARCH_NONE
}
8383 /* ISA extensions. */
8384 struct aarch64_option_cpu_value_table
8387 const aarch64_feature_set value
;
8388 const aarch64_feature_set require
; /* Feature dependencies. */
8391 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8392 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8394 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
8395 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8396 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8398 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8400 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8401 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8402 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8404 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8406 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8408 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8409 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8410 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8411 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8412 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8414 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8415 AARCH64_FEATURE (AARCH64_FEATURE_FP
8416 | AARCH64_FEATURE_SIMD
, 0)},
8417 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8420 struct aarch64_long_option_table
8422 const char *option
; /* Substring to match. */
8423 const char *help
; /* Help information. */
8424 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8425 char *deprecated
; /* If non-null, print this message. */
8428 /* Transitive closure of features depending on set. */
8429 static aarch64_feature_set
8430 aarch64_feature_disable_set (aarch64_feature_set set
)
8432 const struct aarch64_option_cpu_value_table
*opt
;
8433 aarch64_feature_set prev
= 0;
8435 while (prev
!= set
) {
8437 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8438 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8439 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8444 /* Transitive closure of dependencies of set. */
8445 static aarch64_feature_set
8446 aarch64_feature_enable_set (aarch64_feature_set set
)
8448 const struct aarch64_option_cpu_value_table
*opt
;
8449 aarch64_feature_set prev
= 0;
8451 while (prev
!= set
) {
8453 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8454 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8455 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8461 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8462 bfd_boolean ext_only
)
8464 /* We insist on extensions being added before being removed. We achieve
8465 this by using the ADDING_VALUE variable to indicate whether we are
8466 adding an extension (1) or removing it (0) and only allowing it to
8467 change in the order -1 -> 1 -> 0. */
8468 int adding_value
= -1;
8469 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8471 /* Copy the feature set, so that we can modify it. */
8475 while (str
!= NULL
&& *str
!= 0)
8477 const struct aarch64_option_cpu_value_table
*opt
;
8478 const char *ext
= NULL
;
8485 as_bad (_("invalid architectural extension"));
8489 ext
= strchr (++str
, '+');
8495 optlen
= strlen (str
);
8497 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8499 if (adding_value
!= 0)
8504 else if (optlen
> 0)
8506 if (adding_value
== -1)
8508 else if (adding_value
!= 1)
8510 as_bad (_("must specify extensions to add before specifying "
8511 "those to remove"));
8518 as_bad (_("missing architectural extension"));
8522 gas_assert (adding_value
!= -1);
8524 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8525 if (strncmp (opt
->name
, str
, optlen
) == 0)
8527 aarch64_feature_set set
;
8529 /* Add or remove the extension. */
8532 set
= aarch64_feature_enable_set (opt
->value
);
8533 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8537 set
= aarch64_feature_disable_set (opt
->value
);
8538 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8543 if (opt
->name
== NULL
)
8545 as_bad (_("unknown architectural extension `%s'"), str
);
8556 aarch64_parse_cpu (const char *str
)
8558 const struct aarch64_cpu_option_table
*opt
;
8559 const char *ext
= strchr (str
, '+');
8565 optlen
= strlen (str
);
8569 as_bad (_("missing cpu name `%s'"), str
);
8573 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8574 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8576 mcpu_cpu_opt
= &opt
->value
;
8578 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8583 as_bad (_("unknown cpu `%s'"), str
);
8588 aarch64_parse_arch (const char *str
)
8590 const struct aarch64_arch_option_table
*opt
;
8591 const char *ext
= strchr (str
, '+');
8597 optlen
= strlen (str
);
8601 as_bad (_("missing architecture name `%s'"), str
);
8605 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8606 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8608 march_cpu_opt
= &opt
->value
;
8610 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8615 as_bad (_("unknown architecture `%s'\n"), str
);
8620 struct aarch64_option_abi_value_table
8623 enum aarch64_abi_type value
;
8626 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8627 {"ilp32", AARCH64_ABI_ILP32
},
8628 {"lp64", AARCH64_ABI_LP64
},
8632 aarch64_parse_abi (const char *str
)
8638 as_bad (_("missing abi name `%s'"), str
);
8642 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8643 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8645 aarch64_abi
= aarch64_abis
[i
].value
;
8649 as_bad (_("unknown abi `%s'\n"), str
);
8653 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8655 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8656 aarch64_parse_abi
, NULL
},
8657 #endif /* OBJ_ELF */
8658 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8659 aarch64_parse_cpu
, NULL
},
8660 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8661 aarch64_parse_arch
, NULL
},
8662 {NULL
, NULL
, 0, NULL
}
8666 md_parse_option (int c
, const char *arg
)
8668 struct aarch64_option_table
*opt
;
8669 struct aarch64_long_option_table
*lopt
;
8675 target_big_endian
= 1;
8681 target_big_endian
= 0;
8686 /* Listing option. Just ignore these, we don't support additional
8691 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8693 if (c
== opt
->option
[0]
8694 && ((arg
== NULL
&& opt
->option
[1] == 0)
8695 || streq (arg
, opt
->option
+ 1)))
8697 /* If the option is deprecated, tell the user. */
8698 if (opt
->deprecated
!= NULL
)
8699 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8700 arg
? arg
: "", _(opt
->deprecated
));
8702 if (opt
->var
!= NULL
)
8703 *opt
->var
= opt
->value
;
8709 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8711 /* These options are expected to have an argument. */
8712 if (c
== lopt
->option
[0]
8714 && strncmp (arg
, lopt
->option
+ 1,
8715 strlen (lopt
->option
+ 1)) == 0)
8717 /* If the option is deprecated, tell the user. */
8718 if (lopt
->deprecated
!= NULL
)
8719 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8720 _(lopt
->deprecated
));
8722 /* Call the sup-option parser. */
8723 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8734 md_show_usage (FILE * fp
)
8736 struct aarch64_option_table
*opt
;
8737 struct aarch64_long_option_table
*lopt
;
8739 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8741 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8742 if (opt
->help
!= NULL
)
8743 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8745 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8746 if (lopt
->help
!= NULL
)
8747 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8751 -EB assemble code for a big-endian cpu\n"));
8756 -EL assemble code for a little-endian cpu\n"));
8760 /* Parse a .cpu directive. */
8763 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8765 const struct aarch64_cpu_option_table
*opt
;
8771 name
= input_line_pointer
;
8772 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8773 input_line_pointer
++;
8774 saved_char
= *input_line_pointer
;
8775 *input_line_pointer
= 0;
8777 ext
= strchr (name
, '+');
8780 optlen
= ext
- name
;
8782 optlen
= strlen (name
);
8784 /* Skip the first "all" entry. */
8785 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8786 if (strlen (opt
->name
) == optlen
8787 && strncmp (name
, opt
->name
, optlen
) == 0)
8789 mcpu_cpu_opt
= &opt
->value
;
8791 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8794 cpu_variant
= *mcpu_cpu_opt
;
8796 *input_line_pointer
= saved_char
;
8797 demand_empty_rest_of_line ();
8800 as_bad (_("unknown cpu `%s'"), name
);
8801 *input_line_pointer
= saved_char
;
8802 ignore_rest_of_line ();
8806 /* Parse a .arch directive. */
8809 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8811 const struct aarch64_arch_option_table
*opt
;
8817 name
= input_line_pointer
;
8818 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8819 input_line_pointer
++;
8820 saved_char
= *input_line_pointer
;
8821 *input_line_pointer
= 0;
8823 ext
= strchr (name
, '+');
8826 optlen
= ext
- name
;
8828 optlen
= strlen (name
);
8830 /* Skip the first "all" entry. */
8831 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8832 if (strlen (opt
->name
) == optlen
8833 && strncmp (name
, opt
->name
, optlen
) == 0)
8835 mcpu_cpu_opt
= &opt
->value
;
8837 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8840 cpu_variant
= *mcpu_cpu_opt
;
8842 *input_line_pointer
= saved_char
;
8843 demand_empty_rest_of_line ();
8847 as_bad (_("unknown architecture `%s'\n"), name
);
8848 *input_line_pointer
= saved_char
;
8849 ignore_rest_of_line ();
8852 /* Parse a .arch_extension directive. */
8855 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8858 char *ext
= input_line_pointer
;;
8860 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8861 input_line_pointer
++;
8862 saved_char
= *input_line_pointer
;
8863 *input_line_pointer
= 0;
8865 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8868 cpu_variant
= *mcpu_cpu_opt
;
8870 *input_line_pointer
= saved_char
;
8871 demand_empty_rest_of_line ();
8874 /* Copy symbol information. */
8877 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8879 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);