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arc/gas: default mach is arc700, initialised in md_begin
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "subsegs.h"
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
29
30 #include "opcode/arc.h"
31 #include "elf/arc.h"
32
33 /* Defines section. */
34
35 #define MAX_INSN_FIXUPS 2
36 #define MAX_CONSTR_STR 20
37 #define FRAG_MAX_GROWTH 8
38
39 #ifdef DEBUG
40 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
41 #else
42 # define pr_debug(fmt, args...)
43 #endif
44
45 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
46 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
47 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
48 (SUB_OPCODE (x) == 0x28))
49
50 /* Equal to MAX_PRECISION in atof-ieee.c. */
51 #define MAX_LITTLENUMS 6
52
53 /* Enum used to enumerate the relaxable ins operands. */
54 enum rlx_operand_type
55 {
56 EMPTY = 0,
57 REGISTER,
58 REGISTER_S, /* Register for short instruction(s). */
59 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
60 REGISTER_DUP, /* Duplication of previous operand of type register. */
61 IMMEDIATE,
62 BRACKET
63 };
64
65 enum arc_rlx_types
66 {
67 ARC_RLX_NONE = 0,
68 ARC_RLX_BL_S,
69 ARC_RLX_BL,
70 ARC_RLX_B_S,
71 ARC_RLX_B,
72 ARC_RLX_ADD_U3,
73 ARC_RLX_ADD_U6,
74 ARC_RLX_ADD_LIMM,
75 ARC_RLX_LD_U7,
76 ARC_RLX_LD_S9,
77 ARC_RLX_LD_LIMM,
78 ARC_RLX_MOV_U8,
79 ARC_RLX_MOV_S12,
80 ARC_RLX_MOV_LIMM,
81 ARC_RLX_SUB_U3,
82 ARC_RLX_SUB_U6,
83 ARC_RLX_SUB_LIMM,
84 ARC_RLX_MPY_U6,
85 ARC_RLX_MPY_LIMM,
86 ARC_RLX_MOV_RU6,
87 ARC_RLX_MOV_RLIMM,
88 ARC_RLX_ADD_RRU6,
89 ARC_RLX_ADD_RRLIMM,
90 };
91
92 /* Macros section. */
93
94 #define regno(x) ((x) & 0x3F)
95 #define is_ir_num(x) (((x) & ~0x3F) == 0)
96 #define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2))
97 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
98 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
99
100 /* Generic assembler global variables which must be defined by all
101 targets. */
102
103 /* Characters which always start a comment. */
104 const char comment_chars[] = "#;";
105
106 /* Characters which start a comment at the beginning of a line. */
107 const char line_comment_chars[] = "#";
108
109 /* Characters which may be used to separate multiple commands on a
110 single line. */
111 const char line_separator_chars[] = "`";
112
113 /* Characters which are used to indicate an exponent in a floating
114 point number. */
115 const char EXP_CHARS[] = "eE";
116
117 /* Chars that mean this number is a floating point constant
118 As in 0f12.456 or 0d1.2345e12. */
119 const char FLT_CHARS[] = "rRsSfFdD";
120
121 /* Byte order. */
122 extern int target_big_endian;
123 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
124 static int byte_order = DEFAULT_BYTE_ORDER;
125
126 /* By default relaxation is disabled. */
127 static int relaxation_state = 0;
128
129 extern int arc_get_mach (char *);
130
131 /* Forward declarations. */
132 static void arc_lcomm (int);
133 static void arc_option (int);
134 static void arc_extra_reloc (int);
135
136
137 const pseudo_typeS md_pseudo_table[] =
138 {
139 /* Make sure that .word is 32 bits. */
140 { "word", cons, 4 },
141
142 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
143 { "lcomm", arc_lcomm, 0 },
144 { "lcommon", arc_lcomm, 0 },
145 { "cpu", arc_option, 0 },
146
147 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
148 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
149
150 { NULL, NULL, 0 }
151 };
152
153 const char *md_shortopts = "";
154
155 enum options
156 {
157 OPTION_EB = OPTION_MD_BASE,
158 OPTION_EL,
159
160 OPTION_ARC600,
161 OPTION_ARC601,
162 OPTION_ARC700,
163 OPTION_ARCEM,
164 OPTION_ARCHS,
165
166 OPTION_MCPU,
167 OPTION_CD,
168 OPTION_RELAX,
169
170 /* The following options are deprecated and provided here only for
171 compatibility reasons. */
172 OPTION_USER_MODE,
173 OPTION_LD_EXT_MASK,
174 OPTION_SWAP,
175 OPTION_NORM,
176 OPTION_BARREL_SHIFT,
177 OPTION_MIN_MAX,
178 OPTION_NO_MPY,
179 OPTION_EA,
180 OPTION_MUL64,
181 OPTION_SIMD,
182 OPTION_SPFP,
183 OPTION_DPFP,
184 OPTION_XMAC_D16,
185 OPTION_XMAC_24,
186 OPTION_DSP_PACKA,
187 OPTION_CRC,
188 OPTION_DVBF,
189 OPTION_TELEPHONY,
190 OPTION_XYMEMORY,
191 OPTION_LOCK,
192 OPTION_SWAPE,
193 OPTION_RTSC,
194 OPTION_FPUDA
195 };
196
197 struct option md_longopts[] =
198 {
199 { "EB", no_argument, NULL, OPTION_EB },
200 { "EL", no_argument, NULL, OPTION_EL },
201 { "mcpu", required_argument, NULL, OPTION_MCPU },
202 { "mA6", no_argument, NULL, OPTION_ARC600 },
203 { "mARC600", no_argument, NULL, OPTION_ARC600 },
204 { "mARC601", no_argument, NULL, OPTION_ARC601 },
205 { "mARC700", no_argument, NULL, OPTION_ARC700 },
206 { "mA7", no_argument, NULL, OPTION_ARC700 },
207 { "mEM", no_argument, NULL, OPTION_ARCEM },
208 { "mHS", no_argument, NULL, OPTION_ARCHS },
209 { "mcode-density", no_argument, NULL, OPTION_CD },
210 { "mrelax", no_argument, NULL, OPTION_RELAX },
211
212 /* The following options are deprecated and provided here only for
213 compatibility reasons. */
214 { "mav2em", no_argument, NULL, OPTION_ARCEM },
215 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
216 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
217 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
218 { "mswap", no_argument, NULL, OPTION_SWAP },
219 { "mnorm", no_argument, NULL, OPTION_NORM },
220 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
221 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
222 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
223 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
224 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
225 { "mea", no_argument, NULL, OPTION_EA },
226 { "mEA", no_argument, NULL, OPTION_EA },
227 { "mmul64", no_argument, NULL, OPTION_MUL64 },
228 { "msimd", no_argument, NULL, OPTION_SIMD},
229 { "mspfp", no_argument, NULL, OPTION_SPFP},
230 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
231 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
232 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
233 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
234 { "mdpfp", no_argument, NULL, OPTION_DPFP},
235 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
236 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
237 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
238 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
239 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
240 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
241 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
242 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
243 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
244 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
245 { "mcrc", no_argument, NULL, OPTION_CRC},
246 { "mdvbf", no_argument, NULL, OPTION_DVBF},
247 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
248 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
249 { "mlock", no_argument, NULL, OPTION_LOCK},
250 { "mswape", no_argument, NULL, OPTION_SWAPE},
251 { "mrtsc", no_argument, NULL, OPTION_RTSC},
252 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
253
254 { NULL, no_argument, NULL, 0 }
255 };
256
257 size_t md_longopts_size = sizeof (md_longopts);
258
259 /* Local data and data types. */
260
261 /* Used since new relocation types are introduced in this
262 file (DUMMY_RELOC_LITUSE_*). */
263 typedef int extended_bfd_reloc_code_real_type;
264
265 struct arc_fixup
266 {
267 expressionS exp;
268
269 extended_bfd_reloc_code_real_type reloc;
270
271 /* index into arc_operands. */
272 unsigned int opindex;
273
274 /* PC-relative, used by internals fixups. */
275 unsigned char pcrel;
276
277 /* TRUE if this fixup is for LIMM operand. */
278 bfd_boolean islong;
279 };
280
281 struct arc_insn
282 {
283 unsigned int insn;
284 int nfixups;
285 struct arc_fixup fixups[MAX_INSN_FIXUPS];
286 long limm;
287 bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
288 short. */
289 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
290 valid. */
291 bfd_boolean relax; /* Boolean value: TRUE if needs
292 relaxation. */
293 };
294
295 /* Structure to hold any last two instructions. */
296 static struct arc_last_insn
297 {
298 /* Saved instruction opcode. */
299 const struct arc_opcode *opcode;
300
301 /* Boolean value: TRUE if current insn is short. */
302 bfd_boolean has_limm;
303
304 /* Boolean value: TRUE if current insn has delay slot. */
305 bfd_boolean has_delay_slot;
306 } arc_last_insns[2];
307
308 /* Forward declaration. */
309 static void assemble_insn
310 (const struct arc_opcode *, const expressionS *, int,
311 const struct arc_flags *, int, struct arc_insn *);
312
313 /* The cpu for which we are generating code. */
314 static unsigned arc_target;
315 static const char *arc_target_name;
316 static unsigned arc_features;
317
318 /* The default architecture. */
319 static int arc_mach_type;
320
321 /* Non-zero if the cpu type has been explicitly specified. */
322 static int mach_type_specified_p = 0;
323
324 /* The hash table of instruction opcodes. */
325 static struct hash_control *arc_opcode_hash;
326
327 /* The hash table of register symbols. */
328 static struct hash_control *arc_reg_hash;
329
330 /* A table of CPU names and opcode sets. */
331 static const struct cpu_type
332 {
333 const char *name;
334 unsigned flags;
335 int mach;
336 unsigned eflags;
337 unsigned features;
338 }
339 cpu_types[] =
340 {
341 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
342 E_ARC_MACH_ARC600, 0x00},
343 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
344 E_ARC_MACH_ARC700, 0x00},
345 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
346 EF_ARC_CPU_ARCV2EM, ARC_CD},
347 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
348 EF_ARC_CPU_ARCV2HS, ARC_CD},
349 { 0, 0, 0, 0, 0 }
350 };
351
352 /* Used by the arc_reloc_op table. Order is important. */
353 #define O_gotoff O_md1 /* @gotoff relocation. */
354 #define O_gotpc O_md2 /* @gotpc relocation. */
355 #define O_plt O_md3 /* @plt relocation. */
356 #define O_sda O_md4 /* @sda relocation. */
357 #define O_pcl O_md5 /* @pcl relocation. */
358 #define O_tlsgd O_md6 /* @tlsgd relocation. */
359 #define O_tlsie O_md7 /* @tlsie relocation. */
360 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
361 #define O_tpoff O_md9 /* @tpoff relocation. */
362 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
363 #define O_dtpoff O_md11 /* @dtpoff relocation. */
364 #define O_last O_dtpoff
365
366 /* Used to define a bracket as operand in tokens. */
367 #define O_bracket O_md32
368
369 /* Dummy relocation, to be sorted out. */
370 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
371
372 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
373
374 /* A table to map the spelling of a relocation operand into an appropriate
375 bfd_reloc_code_real_type type. The table is assumed to be ordered such
376 that op-O_literal indexes into it. */
377 #define ARC_RELOC_TABLE(op) \
378 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
379 ? (abort (), 0) \
380 : (int) (op) - (int) O_gotoff) ])
381
382 #define DEF(NAME, RELOC, REQ) \
383 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
384
385 static const struct arc_reloc_op_tag
386 {
387 /* String to lookup. */
388 const char *name;
389 /* Size of the string. */
390 size_t length;
391 /* Which operator to use. */
392 operatorT op;
393 extended_bfd_reloc_code_real_type reloc;
394 /* Allows complex relocation expression like identifier@reloc +
395 const. */
396 unsigned int complex_expr : 1;
397 }
398 arc_reloc_op[] =
399 {
400 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
401 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
402 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
403 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
404 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
405 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
406 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
407 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
408 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
409 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
410 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
411 };
412
413 static const int arc_num_reloc_op
414 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
415
416 /* Structure for relaxable instruction that have to be swapped with a
417 smaller alternative instruction. */
418 struct arc_relaxable_ins
419 {
420 /* Mnemonic that should be checked. */
421 const char *mnemonic_r;
422
423 /* Operands that should be checked.
424 Indexes of operands from operand array. */
425 enum rlx_operand_type operands[6];
426
427 /* Flags that should be checked. */
428 unsigned flag_classes[5];
429
430 /* Mnemonic (smaller) alternative to be used later for relaxation. */
431 const char *mnemonic_alt;
432
433 /* Index of operand that generic relaxation has to check. */
434 unsigned opcheckidx;
435
436 /* Base subtype index used. */
437 enum arc_rlx_types subtype;
438 };
439
440 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
441 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
442 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
443 (SIZE), \
444 (NEXT) } \
445
446 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
447 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
448 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
449 (SIZE), \
450 (NEXT) } \
451
452
453 /* ARC relaxation table. */
454 const relax_typeS md_relax_table[] =
455 {
456 /* Fake entry. */
457 {0, 0, 0, 0},
458
459 /* BL_S s13 ->
460 BL s25. */
461 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL),
462 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
463
464 /* B_S s10 ->
465 B s25. */
466 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B),
467 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
468
469 /* ADD_S c,b, u3 ->
470 ADD<.f> a,b,u6 ->
471 ADD<.f> a,b,limm. */
472 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6),
473 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM),
474 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
475
476 /* LD_S a, [b, u7] ->
477 LD<zz><.x><.aa><.di> a, [b, s9] ->
478 LD<zz><.x><.aa><.di> a, [b, limm] */
479 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9),
480 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM),
481 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE),
482
483 /* MOV_S b, u8 ->
484 MOV<.f> b, s12 ->
485 MOV<.f> b, limm. */
486 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12),
487 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM),
488 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
489
490 /* SUB_S c, b, u3 ->
491 SUB<.f> a, b, u6 ->
492 SUB<.f> a, b, limm. */
493 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6),
494 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM),
495 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
496
497 /* MPY<.f> a, b, u6 ->
498 MPY<.f> a, b, limm. */
499 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM),
500 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
501
502 /* MOV<.f><.cc> b, u6 ->
503 MOV<.f><.cc> b, limm. */
504 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM),
505 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
506
507 /* ADD<.f><.cc> b, b, u6 ->
508 ADD<.f><.cc> b, b, limm. */
509 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM),
510 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
511 };
512
513 /* Order of this table's entries matters! */
514 const struct arc_relaxable_ins arc_relaxable_insns[] =
515 {
516 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
517 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
518 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
519 2, ARC_RLX_ADD_RRU6},
520 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
521 ARC_RLX_ADD_U3 },
522 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
523 ARC_RLX_ADD_U6 },
524 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
525 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
526 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
527 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
528 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
529 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
530 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
531 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
532 ARC_RLX_SUB_U3 },
533 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
534 ARC_RLX_SUB_U6 },
535 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
536 ARC_RLX_MPY_U6 },
537 };
538
539 const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
540
541 /* Flags to set in the elf header. */
542 static flagword arc_eflag = 0x00;
543
544 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
545 symbolS * GOT_symbol = 0;
546
547 /* Set to TRUE when we assemble instructions. */
548 static bfd_boolean assembling_insn = FALSE;
549
550 /* Functions implementation. */
551
552 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
553 is encoded as 'middle-endian' for a little-endian target. FIXME!
554 this function is used for regular 4 byte instructions as well. */
555
556 static void
557 md_number_to_chars_midend (char *buf, valueT val, int n)
558 {
559 if (n == 4)
560 {
561 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
562 md_number_to_chars (buf + 2, (val & 0xffff), 2);
563 }
564 else
565 {
566 md_number_to_chars (buf, val, n);
567 }
568 }
569
570 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
571 the relevant static global variables. */
572
573 static void
574 arc_select_cpu (const char *arg)
575 {
576 int cpu_flags = EF_ARC_CPU_GENERIC;
577 int i;
578
579 for (i = 0; cpu_types[i].name; ++i)
580 {
581 if (!strcasecmp (cpu_types[i].name, arg))
582 {
583 arc_target = cpu_types[i].flags;
584 arc_target_name = cpu_types[i].name;
585 arc_features = cpu_types[i].features;
586 arc_mach_type = cpu_types[i].mach;
587 cpu_flags = cpu_types[i].eflags;
588 break;
589 }
590 }
591
592 if (!cpu_types[i].name)
593 as_fatal (_("unknown architecture: %s\n"), arg);
594
595 if (cpu_flags != EF_ARC_CPU_GENERIC)
596 arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
597 }
598
599 /* Here ends all the ARCompact extension instruction assembling
600 stuff. */
601
602 static void
603 arc_extra_reloc (int r_type)
604 {
605 char *sym_name, c;
606 symbolS *sym, *lab = NULL;
607
608 if (*input_line_pointer == '@')
609 input_line_pointer++;
610 c = get_symbol_name (&sym_name);
611 sym = symbol_find_or_make (sym_name);
612 restore_line_pointer (c);
613 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
614 {
615 ++input_line_pointer;
616 char *lab_name;
617 c = get_symbol_name (&lab_name);
618 lab = symbol_find_or_make (lab_name);
619 restore_line_pointer (c);
620 }
621
622 /* These relocations exist as a mechanism for the compiler to tell the
623 linker how to patch the code if the tls model is optimised. However,
624 the relocation itself does not require any space within the assembler
625 fragment, and so we pass a size of 0.
626
627 The lines that generate these relocations look like this:
628
629 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
630
631 The '.tls_gd_ld @.tdata' is processed first and generates the
632 additional relocation, while the 'bl __tls_get_addr@plt' is processed
633 second and generates the additional branch.
634
635 It is possible that the additional relocation generated by the
636 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
637 while the 'bl __tls_get_addr@plt' will be generated as the first thing
638 in the next fragment. This will be fine; both relocations will still
639 appear to be at the same address in the generated object file.
640 However, this only works as the additional relocation is generated
641 with size of 0 bytes. */
642 fixS *fixP
643 = fix_new (frag_now, /* Which frag? */
644 frag_now_fix (), /* Where in that frag? */
645 0, /* size: 1, 2, or 4 usually. */
646 sym, /* X_add_symbol. */
647 0, /* X_add_number. */
648 FALSE, /* TRUE if PC-relative relocation. */
649 r_type /* Relocation type. */);
650 fixP->fx_subsy = lab;
651 }
652
653 static symbolS *
654 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
655 symbolS *symbolP, addressT size)
656 {
657 addressT align = 0;
658 SKIP_WHITESPACE ();
659
660 if (*input_line_pointer == ',')
661 {
662 align = parse_align (1);
663
664 if (align == (addressT) -1)
665 return NULL;
666 }
667 else
668 {
669 if (size >= 8)
670 align = 3;
671 else if (size >= 4)
672 align = 2;
673 else if (size >= 2)
674 align = 1;
675 else
676 align = 0;
677 }
678
679 bss_alloc (symbolP, size, align);
680 S_CLEAR_EXTERNAL (symbolP);
681
682 return symbolP;
683 }
684
685 static void
686 arc_lcomm (int ignore)
687 {
688 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
689
690 if (symbolP)
691 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
692 }
693
694 /* Select the cpu we're assembling for. */
695
696 static void
697 arc_option (int ignore ATTRIBUTE_UNUSED)
698 {
699 int mach = -1;
700 char c;
701 char *cpu;
702
703 c = get_symbol_name (&cpu);
704 mach = arc_get_mach (cpu);
705
706 if (mach == -1)
707 goto bad_cpu;
708
709 if (!mach_type_specified_p)
710 {
711 if ((!strcmp ("ARC600", cpu))
712 || (!strcmp ("ARC601", cpu))
713 || (!strcmp ("A6", cpu)))
714 {
715 md_parse_option (OPTION_MCPU, "arc600");
716 }
717 else if ((!strcmp ("ARC700", cpu))
718 || (!strcmp ("A7", cpu)))
719 {
720 md_parse_option (OPTION_MCPU, "arc700");
721 }
722 else if (!strcmp ("EM", cpu))
723 {
724 md_parse_option (OPTION_MCPU, "arcem");
725 }
726 else if (!strcmp ("HS", cpu))
727 {
728 md_parse_option (OPTION_MCPU, "archs");
729 }
730 else
731 as_fatal ("could not find the architecture");
732
733 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
734 as_fatal ("could not set architecture and machine");
735 }
736 else
737 if (arc_mach_type != mach)
738 as_warn ("Command-line value overrides \".cpu\" directive");
739
740 restore_line_pointer (c);
741 demand_empty_rest_of_line ();
742 return;
743
744 bad_cpu:
745 restore_line_pointer (c);
746 as_bad ("invalid identifier for \".cpu\"");
747 ignore_rest_of_line ();
748 }
749
750 /* Smartly print an expression. */
751
752 static void
753 debug_exp (expressionS *t)
754 {
755 const char *name ATTRIBUTE_UNUSED;
756 const char *namemd ATTRIBUTE_UNUSED;
757
758 pr_debug ("debug_exp: ");
759
760 switch (t->X_op)
761 {
762 default: name = "unknown"; break;
763 case O_illegal: name = "O_illegal"; break;
764 case O_absent: name = "O_absent"; break;
765 case O_constant: name = "O_constant"; break;
766 case O_symbol: name = "O_symbol"; break;
767 case O_symbol_rva: name = "O_symbol_rva"; break;
768 case O_register: name = "O_register"; break;
769 case O_big: name = "O_big"; break;
770 case O_uminus: name = "O_uminus"; break;
771 case O_bit_not: name = "O_bit_not"; break;
772 case O_logical_not: name = "O_logical_not"; break;
773 case O_multiply: name = "O_multiply"; break;
774 case O_divide: name = "O_divide"; break;
775 case O_modulus: name = "O_modulus"; break;
776 case O_left_shift: name = "O_left_shift"; break;
777 case O_right_shift: name = "O_right_shift"; break;
778 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
779 case O_bit_or_not: name = "O_bit_or_not"; break;
780 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
781 case O_bit_and: name = "O_bit_and"; break;
782 case O_add: name = "O_add"; break;
783 case O_subtract: name = "O_subtract"; break;
784 case O_eq: name = "O_eq"; break;
785 case O_ne: name = "O_ne"; break;
786 case O_lt: name = "O_lt"; break;
787 case O_le: name = "O_le"; break;
788 case O_ge: name = "O_ge"; break;
789 case O_gt: name = "O_gt"; break;
790 case O_logical_and: name = "O_logical_and"; break;
791 case O_logical_or: name = "O_logical_or"; break;
792 case O_index: name = "O_index"; break;
793 case O_bracket: name = "O_bracket"; break;
794 }
795
796 switch (t->X_md)
797 {
798 default: namemd = "unknown"; break;
799 case O_gotoff: namemd = "O_gotoff"; break;
800 case O_gotpc: namemd = "O_gotpc"; break;
801 case O_plt: namemd = "O_plt"; break;
802 case O_sda: namemd = "O_sda"; break;
803 case O_pcl: namemd = "O_pcl"; break;
804 case O_tlsgd: namemd = "O_tlsgd"; break;
805 case O_tlsie: namemd = "O_tlsie"; break;
806 case O_tpoff9: namemd = "O_tpoff9"; break;
807 case O_tpoff: namemd = "O_tpoff"; break;
808 case O_dtpoff9: namemd = "O_dtpoff9"; break;
809 case O_dtpoff: namemd = "O_dtpoff"; break;
810 }
811
812 pr_debug ("%s (%s, %s, %d, %s)", name,
813 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
814 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
815 (int) t->X_add_number,
816 (t->X_md) ? namemd : "--");
817 pr_debug ("\n");
818 fflush (stderr);
819 }
820
821 /* Parse the arguments to an opcode. */
822
823 static int
824 tokenize_arguments (char *str,
825 expressionS *tok,
826 int ntok)
827 {
828 char *old_input_line_pointer;
829 bfd_boolean saw_comma = FALSE;
830 bfd_boolean saw_arg = FALSE;
831 int brk_lvl = 0;
832 int num_args = 0;
833 int i;
834 size_t len;
835 const struct arc_reloc_op_tag *r;
836 expressionS tmpE;
837 char *reloc_name, c;
838
839 memset (tok, 0, sizeof (*tok) * ntok);
840
841 /* Save and restore input_line_pointer around this function. */
842 old_input_line_pointer = input_line_pointer;
843 input_line_pointer = str;
844
845 while (*input_line_pointer)
846 {
847 SKIP_WHITESPACE ();
848 switch (*input_line_pointer)
849 {
850 case '\0':
851 goto fini;
852
853 case ',':
854 input_line_pointer++;
855 if (saw_comma || !saw_arg)
856 goto err;
857 saw_comma = TRUE;
858 break;
859
860 case '}':
861 case ']':
862 ++input_line_pointer;
863 --brk_lvl;
864 if (!saw_arg)
865 goto err;
866 tok->X_op = O_bracket;
867 ++tok;
868 ++num_args;
869 break;
870
871 case '{':
872 case '[':
873 input_line_pointer++;
874 if (brk_lvl)
875 goto err;
876 ++brk_lvl;
877 tok->X_op = O_bracket;
878 ++tok;
879 ++num_args;
880 break;
881
882 case '@':
883 /* We have labels, function names and relocations, all
884 starting with @ symbol. Sort them out. */
885 if (saw_arg && !saw_comma)
886 goto err;
887
888 /* Parse @label. */
889 tok->X_op = O_symbol;
890 tok->X_md = O_absent;
891 expression (tok);
892 if (*input_line_pointer != '@')
893 goto normalsymbol; /* This is not a relocation. */
894
895 relocationsym:
896
897 /* A relocation opernad has the following form
898 @identifier@relocation_type. The identifier is already
899 in tok! */
900 if (tok->X_op != O_symbol)
901 {
902 as_bad (_("No valid label relocation operand"));
903 goto err;
904 }
905
906 /* Parse @relocation_type. */
907 input_line_pointer++;
908 c = get_symbol_name (&reloc_name);
909 len = input_line_pointer - reloc_name;
910 if (len == 0)
911 {
912 as_bad (_("No relocation operand"));
913 goto err;
914 }
915
916 /* Go through known relocation and try to find a match. */
917 r = &arc_reloc_op[0];
918 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
919 if (len == r->length
920 && memcmp (reloc_name, r->name, len) == 0)
921 break;
922 if (i < 0)
923 {
924 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
925 goto err;
926 }
927
928 *input_line_pointer = c;
929 SKIP_WHITESPACE_AFTER_NAME ();
930 /* Extra check for TLS: base. */
931 if (*input_line_pointer == '@')
932 {
933 symbolS *base;
934 if (tok->X_op_symbol != NULL
935 || tok->X_op != O_symbol)
936 {
937 as_bad (_("Unable to parse TLS base: %s"),
938 input_line_pointer);
939 goto err;
940 }
941 input_line_pointer++;
942 char *sym_name;
943 c = get_symbol_name (&sym_name);
944 base = symbol_find_or_make (sym_name);
945 tok->X_op = O_subtract;
946 tok->X_op_symbol = base;
947 restore_line_pointer (c);
948 tmpE.X_add_number = 0;
949 }
950 else if ((*input_line_pointer != '+')
951 && (*input_line_pointer != '-'))
952 {
953 tmpE.X_add_number = 0;
954 }
955 else
956 {
957 /* Parse the constant of a complex relocation expression
958 like @identifier@reloc +/- const. */
959 if (! r->complex_expr)
960 {
961 as_bad (_("@%s is not a complex relocation."), r->name);
962 goto err;
963 }
964 expression (&tmpE);
965 if (tmpE.X_op != O_constant)
966 {
967 as_bad (_("Bad expression: @%s + %s."),
968 r->name, input_line_pointer);
969 goto err;
970 }
971 }
972
973 tok->X_md = r->op;
974 tok->X_add_number = tmpE.X_add_number;
975
976 debug_exp (tok);
977
978 saw_comma = FALSE;
979 saw_arg = TRUE;
980 tok++;
981 num_args++;
982 break;
983
984 case '%':
985 /* Can be a register. */
986 ++input_line_pointer;
987 /* Fall through. */
988 default:
989
990 if (saw_arg && !saw_comma)
991 goto err;
992
993 tok->X_op = O_absent;
994 tok->X_md = O_absent;
995 expression (tok);
996
997 /* Legacy: There are cases when we have
998 identifier@relocation_type, if it is the case parse the
999 relocation type as well. */
1000 if (*input_line_pointer == '@')
1001 goto relocationsym;
1002
1003 normalsymbol:
1004 debug_exp (tok);
1005
1006 if (tok->X_op == O_illegal || tok->X_op == O_absent)
1007 goto err;
1008
1009 saw_comma = FALSE;
1010 saw_arg = TRUE;
1011 tok++;
1012 num_args++;
1013 break;
1014 }
1015 }
1016
1017 fini:
1018 if (saw_comma || brk_lvl)
1019 goto err;
1020 input_line_pointer = old_input_line_pointer;
1021
1022 return num_args;
1023
1024 err:
1025 if (brk_lvl)
1026 as_bad (_("Brackets in operand field incorrect"));
1027 else if (saw_comma)
1028 as_bad (_("extra comma"));
1029 else if (!saw_arg)
1030 as_bad (_("missing argument"));
1031 else
1032 as_bad (_("missing comma or colon"));
1033 input_line_pointer = old_input_line_pointer;
1034 return -1;
1035 }
1036
1037 /* Parse the flags to a structure. */
1038
1039 static int
1040 tokenize_flags (const char *str,
1041 struct arc_flags flags[],
1042 int nflg)
1043 {
1044 char *old_input_line_pointer;
1045 bfd_boolean saw_flg = FALSE;
1046 bfd_boolean saw_dot = FALSE;
1047 int num_flags = 0;
1048 size_t flgnamelen;
1049
1050 memset (flags, 0, sizeof (*flags) * nflg);
1051
1052 /* Save and restore input_line_pointer around this function. */
1053 old_input_line_pointer = input_line_pointer;
1054 input_line_pointer = (char *) str;
1055
1056 while (*input_line_pointer)
1057 {
1058 switch (*input_line_pointer)
1059 {
1060 case ' ':
1061 case '\0':
1062 goto fini;
1063
1064 case '.':
1065 input_line_pointer++;
1066 if (saw_dot)
1067 goto err;
1068 saw_dot = TRUE;
1069 saw_flg = FALSE;
1070 break;
1071
1072 default:
1073 if (saw_flg && !saw_dot)
1074 goto err;
1075
1076 if (num_flags >= nflg)
1077 goto err;
1078
1079 flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz");
1080 if (flgnamelen > MAX_FLAG_NAME_LENGHT)
1081 goto err;
1082
1083 memcpy (flags->name, input_line_pointer, flgnamelen);
1084
1085 input_line_pointer += flgnamelen;
1086 flags++;
1087 saw_dot = FALSE;
1088 saw_flg = TRUE;
1089 num_flags++;
1090 break;
1091 }
1092 }
1093
1094 fini:
1095 input_line_pointer = old_input_line_pointer;
1096 return num_flags;
1097
1098 err:
1099 if (saw_dot)
1100 as_bad (_("extra dot"));
1101 else if (!saw_flg)
1102 as_bad (_("unrecognized flag"));
1103 else
1104 as_bad (_("failed to parse flags"));
1105 input_line_pointer = old_input_line_pointer;
1106 return -1;
1107 }
1108
1109 /* Apply the fixups in order. */
1110
1111 static void
1112 apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
1113 {
1114 int i;
1115
1116 for (i = 0; i < insn->nfixups; i++)
1117 {
1118 struct arc_fixup *fixup = &insn->fixups[i];
1119 int size, pcrel, offset = 0;
1120
1121 /* FIXME! the reloc size is wrong in the BFD file.
1122 When it is fixed please delete me. */
1123 size = (insn->short_insn && !fixup->islong) ? 2 : 4;
1124
1125 if (fixup->islong)
1126 offset = (insn->short_insn) ? 2 : 4;
1127
1128 /* Some fixups are only used internally, thus no howto. */
1129 if ((int) fixup->reloc == 0)
1130 as_fatal (_("Unhandled reloc type"));
1131
1132 if ((int) fixup->reloc < 0)
1133 {
1134 /* FIXME! the reloc size is wrong in the BFD file.
1135 When it is fixed please enable me.
1136 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1137 pcrel = fixup->pcrel;
1138 }
1139 else
1140 {
1141 reloc_howto_type *reloc_howto =
1142 bfd_reloc_type_lookup (stdoutput,
1143 (bfd_reloc_code_real_type) fixup->reloc);
1144 gas_assert (reloc_howto);
1145
1146 /* FIXME! the reloc size is wrong in the BFD file.
1147 When it is fixed please enable me.
1148 size = bfd_get_reloc_size (reloc_howto); */
1149 pcrel = reloc_howto->pc_relative;
1150 }
1151
1152 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1153 offset %d + %d\n",
1154 fragP->fr_file, fragP->fr_line,
1155 (fixup->reloc < 0) ? "Internal" :
1156 bfd_get_reloc_code_name (fixup->reloc),
1157 pcrel ? "Y" : "N",
1158 size, fix, offset);
1159 fix_new_exp (fragP, fix + offset,
1160 size, &fixup->exp, pcrel, fixup->reloc);
1161
1162 /* Check for ZOLs, and update symbol info if any. */
1163 if (LP_INSN (insn->insn))
1164 {
1165 gas_assert (fixup->exp.X_add_symbol);
1166 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
1167 }
1168 }
1169 }
1170
1171 /* Actually output an instruction with its fixup. */
1172
1173 static void
1174 emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
1175 {
1176 char *f = where;
1177
1178 pr_debug ("Emit insn : 0x%x\n", insn->insn);
1179 pr_debug ("\tShort : 0x%d\n", insn->short_insn);
1180 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
1181
1182 /* Write out the instruction. */
1183 if (insn->short_insn)
1184 {
1185 if (insn->has_limm)
1186 {
1187 if (!relax)
1188 f = frag_more (6);
1189 md_number_to_chars (f, insn->insn, 2);
1190 md_number_to_chars_midend (f + 2, insn->limm, 4);
1191 dwarf2_emit_insn (6);
1192 }
1193 else
1194 {
1195 if (!relax)
1196 f = frag_more (2);
1197 md_number_to_chars (f, insn->insn, 2);
1198 dwarf2_emit_insn (2);
1199 }
1200 }
1201 else
1202 {
1203 if (insn->has_limm)
1204 {
1205 if (!relax)
1206 f = frag_more (8);
1207 md_number_to_chars_midend (f, insn->insn, 4);
1208 md_number_to_chars_midend (f + 4, insn->limm, 4);
1209 dwarf2_emit_insn (8);
1210 }
1211 else
1212 {
1213 if (!relax)
1214 f = frag_more (4);
1215 md_number_to_chars_midend (f, insn->insn, 4);
1216 dwarf2_emit_insn (4);
1217 }
1218 }
1219
1220 if (!relax)
1221 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1222 }
1223
1224 static void
1225 emit_insn1 (struct arc_insn *insn)
1226 {
1227 /* How frag_var's args are currently configured:
1228 - rs_machine_dependent, to dictate it's a relaxation frag.
1229 - FRAG_MAX_GROWTH, maximum size of instruction
1230 - 0, variable size that might grow...unused by generic relaxation.
1231 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1232 - s, opand expression.
1233 - 0, offset but it's unused.
1234 - 0, opcode but it's unused. */
1235 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1236 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1237
1238 if (frag_room () < FRAG_MAX_GROWTH)
1239 {
1240 /* Handle differently when frag literal memory is exhausted.
1241 This is used because when there's not enough memory left in
1242 the current frag, a new frag is created and the information
1243 we put into frag_now->tc_frag_data is disregarded. */
1244
1245 struct arc_relax_type relax_info_copy;
1246 relax_substateT subtype = frag_now->fr_subtype;
1247
1248 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1249 sizeof (struct arc_relax_type));
1250
1251 frag_wane (frag_now);
1252 frag_grow (FRAG_MAX_GROWTH);
1253
1254 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1255 sizeof (struct arc_relax_type));
1256
1257 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1258 subtype, s, 0, 0);
1259 }
1260 else
1261 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1262 frag_now->fr_subtype, s, 0, 0);
1263 }
1264
1265 static void
1266 emit_insn (struct arc_insn *insn)
1267 {
1268 if (insn->relax)
1269 emit_insn1 (insn);
1270 else
1271 emit_insn0 (insn, NULL, FALSE);
1272 }
1273
1274 /* Check whether a symbol involves a register. */
1275
1276 static bfd_boolean
1277 contains_register (symbolS *sym)
1278 {
1279 if (sym)
1280 {
1281 expressionS *ex = symbol_get_value_expression (sym);
1282
1283 return ((O_register == ex->X_op)
1284 && !contains_register (ex->X_add_symbol)
1285 && !contains_register (ex->X_op_symbol));
1286 }
1287
1288 return FALSE;
1289 }
1290
1291 /* Returns the register number within a symbol. */
1292
1293 static int
1294 get_register (symbolS *sym)
1295 {
1296 if (!contains_register (sym))
1297 return -1;
1298
1299 expressionS *ex = symbol_get_value_expression (sym);
1300 return regno (ex->X_add_number);
1301 }
1302
1303 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1304 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1305
1306 static bfd_boolean
1307 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1308 {
1309 if (!reloc)
1310 return FALSE;
1311
1312 switch (reloc)
1313 {
1314 case BFD_RELOC_ARC_SDA_LDST:
1315 case BFD_RELOC_ARC_SDA_LDST1:
1316 case BFD_RELOC_ARC_SDA_LDST2:
1317 case BFD_RELOC_ARC_SDA16_LD:
1318 case BFD_RELOC_ARC_SDA16_LD1:
1319 case BFD_RELOC_ARC_SDA16_LD2:
1320 case BFD_RELOC_ARC_SDA16_ST2:
1321 case BFD_RELOC_ARC_SDA32_ME:
1322 return FALSE;
1323 default:
1324 return TRUE;
1325 }
1326 }
1327
1328 /* Allocates a tok entry. */
1329
1330 static int
1331 allocate_tok (expressionS *tok, int ntok, int cidx)
1332 {
1333 if (ntok > MAX_INSN_ARGS - 2)
1334 return 0; /* No space left. */
1335
1336 if (cidx > ntok)
1337 return 0; /* Incorect args. */
1338
1339 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
1340
1341 if (cidx == ntok)
1342 return 1; /* Success. */
1343 return allocate_tok (tok, ntok - 1, cidx);
1344 }
1345
1346 /* Search forward through all variants of an opcode looking for a
1347 syntax match. */
1348
1349 static const struct arc_opcode *
1350 find_opcode_match (const struct arc_opcode *first_opcode,
1351 expressionS *tok,
1352 int *pntok,
1353 struct arc_flags *first_pflag,
1354 int nflgs,
1355 int *pcpumatch)
1356 {
1357 const struct arc_opcode *opcode = first_opcode;
1358 int ntok = *pntok;
1359 int got_cpu_match = 0;
1360 expressionS bktok[MAX_INSN_ARGS];
1361 int bkntok;
1362 expressionS emptyE;
1363
1364 memset (&emptyE, 0, sizeof (emptyE));
1365 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1366 bkntok = ntok;
1367
1368 do
1369 {
1370 const unsigned char *opidx;
1371 const unsigned char *flgidx;
1372 int tokidx = 0;
1373 const expressionS *t = &emptyE;
1374
1375 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1376 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
1377
1378 /* Don't match opcodes that don't exist on this
1379 architecture. */
1380 if (!(opcode->cpu & arc_target))
1381 goto match_failed;
1382
1383 if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
1384 goto match_failed;
1385
1386 got_cpu_match = 1;
1387 pr_debug ("cpu ");
1388
1389 /* Check the operands. */
1390 for (opidx = opcode->operands; *opidx; ++opidx)
1391 {
1392 const struct arc_operand *operand = &arc_operands[*opidx];
1393
1394 /* Only take input from real operands. */
1395 if ((operand->flags & ARC_OPERAND_FAKE)
1396 && !(operand->flags & ARC_OPERAND_BRAKET))
1397 continue;
1398
1399 /* When we expect input, make sure we have it. */
1400 if (tokidx >= ntok)
1401 goto match_failed;
1402
1403 /* Match operand type with expression type. */
1404 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1405 {
1406 case ARC_OPERAND_IR:
1407 /* Check to be a register. */
1408 if ((tok[tokidx].X_op != O_register
1409 || !is_ir_num (tok[tokidx].X_add_number))
1410 && !(operand->flags & ARC_OPERAND_IGNORE))
1411 goto match_failed;
1412
1413 /* If expect duplicate, make sure it is duplicate. */
1414 if (operand->flags & ARC_OPERAND_DUPLICATE)
1415 {
1416 /* Check for duplicate. */
1417 if (t->X_op != O_register
1418 || !is_ir_num (t->X_add_number)
1419 || (regno (t->X_add_number) !=
1420 regno (tok[tokidx].X_add_number)))
1421 goto match_failed;
1422 }
1423
1424 /* Special handling? */
1425 if (operand->insert)
1426 {
1427 const char *errmsg = NULL;
1428 (*operand->insert)(0,
1429 regno (tok[tokidx].X_add_number),
1430 &errmsg);
1431 if (errmsg)
1432 {
1433 if (operand->flags & ARC_OPERAND_IGNORE)
1434 {
1435 /* Missing argument, create one. */
1436 if (!allocate_tok (tok, ntok - 1, tokidx))
1437 goto match_failed;
1438
1439 tok[tokidx].X_op = O_absent;
1440 ++ntok;
1441 }
1442 else
1443 goto match_failed;
1444 }
1445 }
1446
1447 t = &tok[tokidx];
1448 break;
1449
1450 case ARC_OPERAND_BRAKET:
1451 /* Check if bracket is also in opcode table as
1452 operand. */
1453 if (tok[tokidx].X_op != O_bracket)
1454 goto match_failed;
1455 break;
1456
1457 case ARC_OPERAND_LIMM:
1458 case ARC_OPERAND_SIGNED:
1459 case ARC_OPERAND_UNSIGNED:
1460 switch (tok[tokidx].X_op)
1461 {
1462 case O_illegal:
1463 case O_absent:
1464 case O_register:
1465 goto match_failed;
1466
1467 case O_bracket:
1468 /* Got an (too) early bracket, check if it is an
1469 ignored operand. N.B. This procedure works only
1470 when bracket is the last operand! */
1471 if (!(operand->flags & ARC_OPERAND_IGNORE))
1472 goto match_failed;
1473 /* Insert the missing operand. */
1474 if (!allocate_tok (tok, ntok - 1, tokidx))
1475 goto match_failed;
1476
1477 tok[tokidx].X_op = O_absent;
1478 ++ntok;
1479 break;
1480
1481 case O_constant:
1482 /* Check the range. */
1483 if (operand->bits != 32
1484 && !(operand->flags & ARC_OPERAND_NCHK))
1485 {
1486 offsetT min, max, val;
1487 val = tok[tokidx].X_add_number;
1488
1489 if (operand->flags & ARC_OPERAND_SIGNED)
1490 {
1491 max = (1 << (operand->bits - 1)) - 1;
1492 min = -(1 << (operand->bits - 1));
1493 }
1494 else
1495 {
1496 max = (1 << operand->bits) - 1;
1497 min = 0;
1498 }
1499
1500 if (val < min || val > max)
1501 goto match_failed;
1502
1503 /* Check alignmets. */
1504 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1505 && (val & 0x03))
1506 goto match_failed;
1507
1508 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1509 && (val & 0x01))
1510 goto match_failed;
1511 }
1512 else if (operand->flags & ARC_OPERAND_NCHK)
1513 {
1514 if (operand->insert)
1515 {
1516 const char *errmsg = NULL;
1517 (*operand->insert)(0,
1518 tok[tokidx].X_add_number,
1519 &errmsg);
1520 if (errmsg)
1521 goto match_failed;
1522 }
1523 else
1524 goto match_failed;
1525 }
1526 break;
1527
1528 case O_subtract:
1529 /* Check if it is register range. */
1530 if ((tok[tokidx].X_add_number == 0)
1531 && contains_register (tok[tokidx].X_add_symbol)
1532 && contains_register (tok[tokidx].X_op_symbol))
1533 {
1534 int regs;
1535
1536 regs = get_register (tok[tokidx].X_add_symbol);
1537 regs <<= 16;
1538 regs |= get_register (tok[tokidx].X_op_symbol);
1539 if (operand->insert)
1540 {
1541 const char *errmsg = NULL;
1542 (*operand->insert)(0,
1543 regs,
1544 &errmsg);
1545 if (errmsg)
1546 goto match_failed;
1547 }
1548 else
1549 goto match_failed;
1550 break;
1551 }
1552 default:
1553 if (operand->default_reloc == 0)
1554 goto match_failed; /* The operand needs relocation. */
1555
1556 /* Relocs requiring long immediate. FIXME! make it
1557 generic and move it to a function. */
1558 switch (tok[tokidx].X_md)
1559 {
1560 case O_gotoff:
1561 case O_gotpc:
1562 case O_pcl:
1563 case O_tpoff:
1564 case O_dtpoff:
1565 case O_tlsgd:
1566 case O_tlsie:
1567 if (!(operand->flags & ARC_OPERAND_LIMM))
1568 goto match_failed;
1569 case O_absent:
1570 if (!generic_reloc_p (operand->default_reloc))
1571 goto match_failed;
1572 default:
1573 break;
1574 }
1575 break;
1576 }
1577 /* If expect duplicate, make sure it is duplicate. */
1578 if (operand->flags & ARC_OPERAND_DUPLICATE)
1579 {
1580 if (t->X_op == O_illegal
1581 || t->X_op == O_absent
1582 || t->X_op == O_register
1583 || (t->X_add_number != tok[tokidx].X_add_number))
1584 goto match_failed;
1585 }
1586 t = &tok[tokidx];
1587 break;
1588
1589 default:
1590 /* Everything else should have been fake. */
1591 abort ();
1592 }
1593
1594 ++tokidx;
1595 }
1596 pr_debug ("opr ");
1597
1598 /* Check the flags. Iterate over the valid flag classes. */
1599 int lnflg = nflgs;
1600
1601 for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
1602 {
1603 /* Get a valid flag class. */
1604 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1605 const unsigned *flgopridx;
1606
1607 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1608 {
1609 const struct arc_flag_operand *flg_operand;
1610 struct arc_flags *pflag = first_pflag;
1611 int i;
1612
1613 flg_operand = &arc_flag_operands[*flgopridx];
1614 for (i = 0; i < nflgs; i++, pflag++)
1615 {
1616 /* Match against the parsed flags. */
1617 if (!strcmp (flg_operand->name, pflag->name))
1618 {
1619 /*TODO: Check if it is duplicated. */
1620 pflag->code = *flgopridx;
1621 lnflg--;
1622 break; /* goto next flag class and parsed flag. */
1623 }
1624 }
1625 }
1626 }
1627 /* Did I check all the parsed flags? */
1628 if (lnflg)
1629 goto match_failed;
1630
1631 pr_debug ("flg");
1632 /* Possible match -- did we use all of our input? */
1633 if (tokidx == ntok)
1634 {
1635 *pntok = ntok;
1636 pr_debug ("\n");
1637 return opcode;
1638 }
1639
1640 match_failed:;
1641 pr_debug ("\n");
1642 /* Restore the original parameters. */
1643 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
1644 ntok = bkntok;
1645 }
1646 while (++opcode - arc_opcodes < (int) arc_num_opcodes
1647 && !strcmp (opcode->name, first_opcode->name));
1648
1649 if (*pcpumatch)
1650 *pcpumatch = got_cpu_match;
1651
1652 return NULL;
1653 }
1654
1655 /* Swap operand tokens. */
1656
1657 static void
1658 swap_operand (expressionS *operand_array,
1659 unsigned source,
1660 unsigned destination)
1661 {
1662 expressionS cpy_operand;
1663 expressionS *src_operand;
1664 expressionS *dst_operand;
1665 size_t size;
1666
1667 if (source == destination)
1668 return;
1669
1670 src_operand = &operand_array[source];
1671 dst_operand = &operand_array[destination];
1672 size = sizeof (expressionS);
1673
1674 /* Make copy of operand to swap with and swap. */
1675 memcpy (&cpy_operand, dst_operand, size);
1676 memcpy (dst_operand, src_operand, size);
1677 memcpy (src_operand, &cpy_operand, size);
1678 }
1679
1680 /* Check if *op matches *tok type.
1681 Returns FALSE if they don't match, TRUE if they match. */
1682
1683 static bfd_boolean
1684 pseudo_operand_match (const expressionS *tok,
1685 const struct arc_operand_operation *op)
1686 {
1687 offsetT min, max, val;
1688 bfd_boolean ret;
1689 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
1690
1691 ret = FALSE;
1692 switch (tok->X_op)
1693 {
1694 case O_constant:
1695 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
1696 ret = 1;
1697 else if (!(operand_real->flags & ARC_OPERAND_IR))
1698 {
1699 val = tok->X_add_number + op->count;
1700 if (operand_real->flags & ARC_OPERAND_SIGNED)
1701 {
1702 max = (1 << (operand_real->bits - 1)) - 1;
1703 min = -(1 << (operand_real->bits - 1));
1704 }
1705 else
1706 {
1707 max = (1 << operand_real->bits) - 1;
1708 min = 0;
1709 }
1710 if (min <= val && val <= max)
1711 ret = TRUE;
1712 }
1713 break;
1714
1715 case O_symbol:
1716 /* Handle all symbols as long immediates or signed 9. */
1717 if (operand_real->flags & ARC_OPERAND_LIMM ||
1718 ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
1719 ret = TRUE;
1720 break;
1721
1722 case O_register:
1723 if (operand_real->flags & ARC_OPERAND_IR)
1724 ret = TRUE;
1725 break;
1726
1727 case O_bracket:
1728 if (operand_real->flags & ARC_OPERAND_BRAKET)
1729 ret = TRUE;
1730 break;
1731
1732 default:
1733 /* Unknown. */
1734 break;
1735 }
1736 return ret;
1737 }
1738
1739 /* Find pseudo instruction in array. */
1740
1741 static const struct arc_pseudo_insn *
1742 find_pseudo_insn (const char *opname,
1743 int ntok,
1744 const expressionS *tok)
1745 {
1746 const struct arc_pseudo_insn *pseudo_insn = NULL;
1747 const struct arc_operand_operation *op;
1748 unsigned int i;
1749 int j;
1750
1751 for (i = 0; i < arc_num_pseudo_insn; ++i)
1752 {
1753 pseudo_insn = &arc_pseudo_insns[i];
1754 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
1755 {
1756 op = pseudo_insn->operand;
1757 for (j = 0; j < ntok; ++j)
1758 if (!pseudo_operand_match (&tok[j], &op[j]))
1759 break;
1760
1761 /* Found the right instruction. */
1762 if (j == ntok)
1763 return pseudo_insn;
1764 }
1765 }
1766 return NULL;
1767 }
1768
1769 /* Assumes the expressionS *tok is of sufficient size. */
1770
1771 static const struct arc_opcode *
1772 find_special_case_pseudo (const char *opname,
1773 int *ntok,
1774 expressionS *tok,
1775 int *nflgs,
1776 struct arc_flags *pflags)
1777 {
1778 const struct arc_pseudo_insn *pseudo_insn = NULL;
1779 const struct arc_operand_operation *operand_pseudo;
1780 const struct arc_operand *operand_real;
1781 unsigned i;
1782 char construct_operand[MAX_CONSTR_STR];
1783
1784 /* Find whether opname is in pseudo instruction array. */
1785 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
1786
1787 if (pseudo_insn == NULL)
1788 return NULL;
1789
1790 /* Handle flag, Limited to one flag at the moment. */
1791 if (pseudo_insn->flag_r != NULL)
1792 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
1793 MAX_INSN_FLGS - *nflgs);
1794
1795 /* Handle operand operations. */
1796 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
1797 {
1798 operand_pseudo = &pseudo_insn->operand[i];
1799 operand_real = &arc_operands[operand_pseudo->operand_idx];
1800
1801 if (operand_real->flags & ARC_OPERAND_BRAKET &&
1802 !operand_pseudo->needs_insert)
1803 continue;
1804
1805 /* Has to be inserted (i.e. this token does not exist yet). */
1806 if (operand_pseudo->needs_insert)
1807 {
1808 if (operand_real->flags & ARC_OPERAND_BRAKET)
1809 {
1810 tok[i].X_op = O_bracket;
1811 ++(*ntok);
1812 continue;
1813 }
1814
1815 /* Check if operand is a register or constant and handle it
1816 by type. */
1817 if (operand_real->flags & ARC_OPERAND_IR)
1818 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
1819 operand_pseudo->count);
1820 else
1821 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
1822 operand_pseudo->count);
1823
1824 tokenize_arguments (construct_operand, &tok[i], 1);
1825 ++(*ntok);
1826 }
1827
1828 else if (operand_pseudo->count)
1829 {
1830 /* Operand number has to be adjusted accordingly (by operand
1831 type). */
1832 switch (tok[i].X_op)
1833 {
1834 case O_constant:
1835 tok[i].X_add_number += operand_pseudo->count;
1836 break;
1837
1838 case O_symbol:
1839 break;
1840
1841 default:
1842 /* Ignored. */
1843 break;
1844 }
1845 }
1846 }
1847
1848 /* Swap operands if necessary. Only supports one swap at the
1849 moment. */
1850 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
1851 {
1852 operand_pseudo = &pseudo_insn->operand[i];
1853
1854 if (operand_pseudo->swap_operand_idx == i)
1855 continue;
1856
1857 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
1858
1859 /* Prevent a swap back later by breaking out. */
1860 break;
1861 }
1862
1863 return (const struct arc_opcode *)
1864 hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r);
1865 }
1866
1867 static const struct arc_opcode *
1868 find_special_case_flag (const char *opname,
1869 int *nflgs,
1870 struct arc_flags *pflags)
1871 {
1872 unsigned int i;
1873 const char *flagnm;
1874 unsigned flag_idx, flag_arr_idx;
1875 size_t flaglen, oplen;
1876 const struct arc_flag_special *arc_flag_special_opcode;
1877 const struct arc_opcode *opcode;
1878
1879 /* Search for special case instruction. */
1880 for (i = 0; i < arc_num_flag_special; i++)
1881 {
1882 arc_flag_special_opcode = &arc_flag_special_cases[i];
1883 oplen = strlen (arc_flag_special_opcode->name);
1884
1885 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
1886 continue;
1887
1888 /* Found a potential special case instruction, now test for
1889 flags. */
1890 for (flag_arr_idx = 0;; ++flag_arr_idx)
1891 {
1892 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
1893 if (flag_idx == 0)
1894 break; /* End of array, nothing found. */
1895
1896 flagnm = arc_flag_operands[flag_idx].name;
1897 flaglen = strlen (flagnm);
1898 if (strcmp (opname + oplen, flagnm) == 0)
1899 {
1900 opcode = (const struct arc_opcode *)
1901 hash_find (arc_opcode_hash,
1902 arc_flag_special_opcode->name);
1903
1904 if (*nflgs + 1 > MAX_INSN_FLGS)
1905 break;
1906 memcpy (pflags[*nflgs].name, flagnm, flaglen);
1907 pflags[*nflgs].name[flaglen] = '\0';
1908 (*nflgs)++;
1909 return opcode;
1910 }
1911 }
1912 }
1913 return NULL;
1914 }
1915
1916 /* Used to find special case opcode. */
1917
1918 static const struct arc_opcode *
1919 find_special_case (const char *opname,
1920 int *nflgs,
1921 struct arc_flags *pflags,
1922 expressionS *tok,
1923 int *ntok)
1924 {
1925 const struct arc_opcode *opcode;
1926
1927 opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
1928
1929 if (opcode == NULL)
1930 opcode = find_special_case_flag (opname, nflgs, pflags);
1931
1932 return opcode;
1933 }
1934
1935 static void
1936 preprocess_operands (const struct arc_opcode *opcode,
1937 expressionS *tok,
1938 int ntok)
1939 {
1940 int i;
1941 size_t len;
1942 const char *p;
1943 unsigned j;
1944 const struct arc_aux_reg *auxr;
1945
1946 for (i = 0; i < ntok; i++)
1947 {
1948 switch (tok[i].X_op)
1949 {
1950 case O_illegal:
1951 case O_absent:
1952 break; /* Throw and error. */
1953
1954 case O_symbol:
1955 if (opcode->class != AUXREG)
1956 break;
1957 /* Convert the symbol to a constant if possible. */
1958 p = S_GET_NAME (tok[i].X_add_symbol);
1959 len = strlen (p);
1960
1961 auxr = &arc_aux_regs[0];
1962 for (j = 0; j < arc_num_aux_regs; j++, auxr++)
1963 if (len == auxr->length
1964 && strcasecmp (auxr->name, p) == 0)
1965 {
1966 tok[i].X_op = O_constant;
1967 tok[i].X_add_number = auxr->address;
1968 break;
1969 }
1970 break;
1971 default:
1972 break;
1973 }
1974 }
1975 }
1976
1977 /* Given an opcode name, pre-tockenized set of argumenst and the
1978 opcode flags, take it all the way through emission. */
1979
1980 static void
1981 assemble_tokens (const char *opname,
1982 expressionS *tok,
1983 int ntok,
1984 struct arc_flags *pflags,
1985 int nflgs)
1986 {
1987 bfd_boolean found_something = FALSE;
1988 const struct arc_opcode *opcode;
1989 int cpumatch = 1;
1990
1991 /* Search opcodes. */
1992 opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname);
1993
1994 /* Couldn't find opcode conventional way, try special cases. */
1995 if (!opcode)
1996 opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
1997
1998 if (opcode)
1999 {
2000 pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
2001 frag_now->fr_file, frag_now->fr_line, opcode->name,
2002 opcode->opcode);
2003
2004 preprocess_operands (opcode, tok, ntok);
2005
2006 found_something = TRUE;
2007 opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
2008 if (opcode)
2009 {
2010 struct arc_insn insn;
2011 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2012 emit_insn (&insn);
2013 return;
2014 }
2015 }
2016
2017 if (found_something)
2018 {
2019 if (cpumatch)
2020 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2021 else
2022 as_bad (_("opcode '%s' not supported for target %s"), opname,
2023 arc_target_name);
2024 }
2025 else
2026 as_bad (_("unknown opcode '%s'"), opname);
2027 }
2028
2029 /* The public interface to the instruction assembler. */
2030
2031 void
2032 md_assemble (char *str)
2033 {
2034 char *opname;
2035 expressionS tok[MAX_INSN_ARGS];
2036 int ntok, nflg;
2037 size_t opnamelen;
2038 struct arc_flags flags[MAX_INSN_FLGS];
2039
2040 /* Split off the opcode. */
2041 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2042 opname = xmalloc (opnamelen + 1);
2043 memcpy (opname, str, opnamelen);
2044 opname[opnamelen] = '\0';
2045
2046 /* Signalize we are assmbling the instructions. */
2047 assembling_insn = TRUE;
2048
2049 /* Tokenize the flags. */
2050 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2051 {
2052 as_bad (_("syntax error"));
2053 return;
2054 }
2055
2056 /* Scan up to the end of the mnemonic which must end in space or end
2057 of string. */
2058 str += opnamelen;
2059 for (; *str != '\0'; str++)
2060 if (*str == ' ')
2061 break;
2062
2063 /* Tokenize the rest of the line. */
2064 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
2065 {
2066 as_bad (_("syntax error"));
2067 return;
2068 }
2069
2070 /* Finish it off. */
2071 assemble_tokens (opname, tok, ntok, flags, nflg);
2072 assembling_insn = FALSE;
2073 }
2074
2075 /* Callback to insert a register into the hash table. */
2076
2077 static void
2078 declare_register (const char *name, int number)
2079 {
2080 const char *err;
2081 symbolS *regS = symbol_create (name, reg_section,
2082 number, &zero_address_frag);
2083
2084 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2085 if (err)
2086 as_fatal ("Inserting \"%s\" into register table failed: %s",
2087 name, err);
2088 }
2089
2090 /* Construct symbols for each of the general registers. */
2091
2092 static void
2093 declare_register_set (void)
2094 {
2095 int i;
2096 for (i = 0; i < 64; ++i)
2097 {
2098 char name[7];
2099
2100 sprintf (name, "r%d", i);
2101 declare_register (name, i);
2102 if ((i & 0x01) == 0)
2103 {
2104 sprintf (name, "r%dr%d", i, i+1);
2105 declare_register (name, i);
2106 }
2107 }
2108 }
2109
2110 /* Port-specific assembler initialization. This function is called
2111 once, at assembler startup time. */
2112
2113 void
2114 md_begin (void)
2115 {
2116 unsigned int i;
2117
2118 if (!mach_type_specified_p)
2119 arc_select_cpu ("arc700");
2120
2121 /* The endianness can be chosen "at the factory". */
2122 target_big_endian = byte_order == BIG_ENDIAN;
2123
2124 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
2125 as_warn (_("could not set architecture and machine"));
2126
2127 /* Set elf header flags. */
2128 bfd_set_private_flags (stdoutput, arc_eflag);
2129
2130 /* Set up a hash table for the instructions. */
2131 arc_opcode_hash = hash_new ();
2132 if (arc_opcode_hash == NULL)
2133 as_fatal (_("Virtual memory exhausted"));
2134
2135 /* Initialize the hash table with the insns. */
2136 for (i = 0; i < arc_num_opcodes;)
2137 {
2138 const char *name, *retval;
2139
2140 name = arc_opcodes[i].name;
2141 retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]);
2142 if (retval)
2143 as_fatal (_("internal error: can't hash opcode '%s': %s"),
2144 name, retval);
2145
2146 while (++i < arc_num_opcodes
2147 && (arc_opcodes[i].name == name
2148 || !strcmp (arc_opcodes[i].name, name)))
2149 continue;
2150 }
2151
2152 /* Register declaration. */
2153 arc_reg_hash = hash_new ();
2154 if (arc_reg_hash == NULL)
2155 as_fatal (_("Virtual memory exhausted"));
2156
2157 declare_register_set ();
2158 declare_register ("gp", 26);
2159 declare_register ("fp", 27);
2160 declare_register ("sp", 28);
2161 declare_register ("ilink", 29);
2162 declare_register ("ilink1", 29);
2163 declare_register ("ilink2", 30);
2164 declare_register ("blink", 31);
2165
2166 declare_register ("mlo", 57);
2167 declare_register ("mmid", 58);
2168 declare_register ("mhi", 59);
2169
2170 declare_register ("acc1", 56);
2171 declare_register ("acc2", 57);
2172
2173 declare_register ("lp_count", 60);
2174 declare_register ("pcl", 63);
2175
2176 /* Initialize the last instructions. */
2177 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
2178 }
2179
2180 /* Write a value out to the object file, using the appropriate
2181 endianness. */
2182
2183 void
2184 md_number_to_chars (char *buf,
2185 valueT val,
2186 int n)
2187 {
2188 if (target_big_endian)
2189 number_to_chars_bigendian (buf, val, n);
2190 else
2191 number_to_chars_littleendian (buf, val, n);
2192 }
2193
2194 /* Round up a section size to the appropriate boundary. */
2195
2196 valueT
2197 md_section_align (segT segment,
2198 valueT size)
2199 {
2200 int align = bfd_get_section_alignment (stdoutput, segment);
2201
2202 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
2203 }
2204
2205 /* The location from which a PC relative jump should be calculated,
2206 given a PC relative reloc. */
2207
2208 long
2209 md_pcrel_from_section (fixS *fixP,
2210 segT sec)
2211 {
2212 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
2213
2214 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
2215
2216 if (fixP->fx_addsy != (symbolS *) NULL
2217 && (!S_IS_DEFINED (fixP->fx_addsy)
2218 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2219 {
2220 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
2221
2222 /* The symbol is undefined (or is defined but not in this section).
2223 Let the linker figure it out. */
2224 return 0;
2225 }
2226
2227 if ((int) fixP->fx_r_type < 0)
2228 {
2229 /* These are the "internal" relocations. Align them to
2230 32 bit boundary (PCL), for the moment. */
2231 base &= ~3;
2232 }
2233 else
2234 {
2235 switch (fixP->fx_r_type)
2236 {
2237 case BFD_RELOC_ARC_PC32:
2238 /* The hardware calculates relative to the start of the
2239 insn, but this relocation is relative to location of the
2240 LIMM, compensate. The base always needs to be
2241 substracted by 4 as we do not support this type of PCrel
2242 relocation for short instructions. */
2243 base -= 4;
2244 /* Fall through. */
2245 case BFD_RELOC_ARC_PLT32:
2246 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2247 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2248 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2249 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2250
2251 case BFD_RELOC_ARC_S21H_PCREL:
2252 case BFD_RELOC_ARC_S25H_PCREL:
2253 case BFD_RELOC_ARC_S13_PCREL:
2254 case BFD_RELOC_ARC_S21W_PCREL:
2255 case BFD_RELOC_ARC_S25W_PCREL:
2256 base &= ~3;
2257 break;
2258 default:
2259 as_bad_where (fixP->fx_file, fixP->fx_line,
2260 _("unhandled reloc %s in md_pcrel_from_section"),
2261 bfd_get_reloc_code_name (fixP->fx_r_type));
2262 break;
2263 }
2264 }
2265
2266 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2267 fixP->fx_frag->fr_address, fixP->fx_where, base,
2268 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2269 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2270
2271 return base;
2272 }
2273
2274 /* Given a BFD relocation find the coresponding operand. */
2275
2276 static const struct arc_operand *
2277 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2278 {
2279 unsigned i;
2280
2281 for (i = 0; i < arc_num_operands; i++)
2282 if (arc_operands[i].default_reloc == reloc)
2283 return &arc_operands[i];
2284 return NULL;
2285 }
2286
2287 /* Insert an operand value into an instruction. */
2288
2289 static unsigned
2290 insert_operand (unsigned insn,
2291 const struct arc_operand *operand,
2292 offsetT val,
2293 const char *file,
2294 unsigned line)
2295 {
2296 offsetT min = 0, max = 0;
2297
2298 if (operand->bits != 32
2299 && !(operand->flags & ARC_OPERAND_NCHK)
2300 && !(operand->flags & ARC_OPERAND_FAKE))
2301 {
2302 if (operand->flags & ARC_OPERAND_SIGNED)
2303 {
2304 max = (1 << (operand->bits - 1)) - 1;
2305 min = -(1 << (operand->bits - 1));
2306 }
2307 else
2308 {
2309 max = (1 << operand->bits) - 1;
2310 min = 0;
2311 }
2312
2313 if (val < min || val > max)
2314 as_bad_value_out_of_range (_("operand"),
2315 val, min, max, file, line);
2316 }
2317
2318 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2319 min, val, max, insn);
2320
2321 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2322 && (val & 0x03))
2323 as_bad_where (file, line,
2324 _("Unaligned operand. Needs to be 32bit aligned"));
2325
2326 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2327 && (val & 0x01))
2328 as_bad_where (file, line,
2329 _("Unaligned operand. Needs to be 16bit aligned"));
2330
2331 if (operand->insert)
2332 {
2333 const char *errmsg = NULL;
2334
2335 insn = (*operand->insert) (insn, val, &errmsg);
2336 if (errmsg)
2337 as_warn_where (file, line, "%s", errmsg);
2338 }
2339 else
2340 {
2341 if (operand->flags & ARC_OPERAND_TRUNCATE)
2342 {
2343 if (operand->flags & ARC_OPERAND_ALIGNED32)
2344 val >>= 2;
2345 if (operand->flags & ARC_OPERAND_ALIGNED16)
2346 val >>= 1;
2347 }
2348 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2349 }
2350 return insn;
2351 }
2352
2353 /* Apply a fixup to the object code. At this point all symbol values
2354 should be fully resolved, and we attempt to completely resolve the
2355 reloc. If we can not do that, we determine the correct reloc code
2356 and put it back in the fixup. To indicate that a fixup has been
2357 eliminated, set fixP->fx_done. */
2358
2359 void
2360 md_apply_fix (fixS *fixP,
2361 valueT *valP,
2362 segT seg)
2363 {
2364 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2365 valueT value = *valP;
2366 unsigned insn = 0;
2367 symbolS *fx_addsy, *fx_subsy;
2368 offsetT fx_offset;
2369 segT add_symbol_segment = absolute_section;
2370 segT sub_symbol_segment = absolute_section;
2371 const struct arc_operand *operand = NULL;
2372 extended_bfd_reloc_code_real_type reloc;
2373
2374 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2375 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2376 ((int) fixP->fx_r_type < 0) ? "Internal":
2377 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2378 fixP->fx_offset);
2379
2380 fx_addsy = fixP->fx_addsy;
2381 fx_subsy = fixP->fx_subsy;
2382 fx_offset = 0;
2383
2384 if (fx_addsy)
2385 {
2386 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
2387 }
2388
2389 if (fx_subsy
2390 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2391 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2392 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2393 {
2394 resolve_symbol_value (fx_subsy);
2395 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
2396
2397 if (sub_symbol_segment == absolute_section)
2398 {
2399 /* The symbol is really a constant. */
2400 fx_offset -= S_GET_VALUE (fx_subsy);
2401 fx_subsy = NULL;
2402 }
2403 else
2404 {
2405 as_bad_where (fixP->fx_file, fixP->fx_line,
2406 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2407 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2408 segment_name (add_symbol_segment),
2409 S_GET_NAME (fx_subsy),
2410 segment_name (sub_symbol_segment));
2411 return;
2412 }
2413 }
2414
2415 if (fx_addsy
2416 && !S_IS_WEAK (fx_addsy))
2417 {
2418 if (add_symbol_segment == seg
2419 && fixP->fx_pcrel)
2420 {
2421 value += S_GET_VALUE (fx_addsy);
2422 value -= md_pcrel_from_section (fixP, seg);
2423 fx_addsy = NULL;
2424 fixP->fx_pcrel = FALSE;
2425 }
2426 else if (add_symbol_segment == absolute_section)
2427 {
2428 value = fixP->fx_offset;
2429 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2430 fx_addsy = NULL;
2431 fixP->fx_pcrel = FALSE;
2432 }
2433 }
2434
2435 if (!fx_addsy)
2436 fixP->fx_done = TRUE;
2437
2438 if (fixP->fx_pcrel)
2439 {
2440 if (fx_addsy
2441 && ((S_IS_DEFINED (fx_addsy)
2442 && S_GET_SEGMENT (fx_addsy) != seg)
2443 || S_IS_WEAK (fx_addsy)))
2444 value += md_pcrel_from_section (fixP, seg);
2445
2446 switch (fixP->fx_r_type)
2447 {
2448 case BFD_RELOC_ARC_32_ME:
2449 /* This is a pc-relative value in a LIMM. Adjust it to the
2450 address of the instruction not to the address of the
2451 LIMM. Note: it is not anylonger valid this afirmation as
2452 the linker consider ARC_PC32 a fixup to entire 64 bit
2453 insn. */
2454 fixP->fx_offset += fixP->fx_frag->fr_address;
2455 /* Fall through. */
2456 case BFD_RELOC_32:
2457 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2458 /* Fall through. */
2459 case BFD_RELOC_ARC_PC32:
2460 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2461 break;
2462 default:
2463 if ((int) fixP->fx_r_type < 0)
2464 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2465 fixP->fx_r_type);
2466 break;
2467 }
2468 }
2469
2470 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2471 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2472 ((int) fixP->fx_r_type < 0) ? "Internal":
2473 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2474 fixP->fx_offset);
2475
2476
2477 /* Now check for TLS relocations. */
2478 reloc = fixP->fx_r_type;
2479 switch (reloc)
2480 {
2481 case BFD_RELOC_ARC_TLS_DTPOFF:
2482 case BFD_RELOC_ARC_TLS_LE_32:
2483 if (fixP->fx_done)
2484 break;
2485 /* Fall through. */
2486 case BFD_RELOC_ARC_TLS_GD_GOT:
2487 case BFD_RELOC_ARC_TLS_IE_GOT:
2488 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2489 break;
2490
2491 case BFD_RELOC_ARC_TLS_GD_LD:
2492 gas_assert (!fixP->fx_offset);
2493 if (fixP->fx_subsy)
2494 fixP->fx_offset
2495 = (S_GET_VALUE (fixP->fx_subsy)
2496 - fixP->fx_frag->fr_address- fixP->fx_where);
2497 fixP->fx_subsy = NULL;
2498 /* Fall through. */
2499 case BFD_RELOC_ARC_TLS_GD_CALL:
2500 /* These two relocs are there just to allow ld to change the tls
2501 model for this symbol, by patching the code. The offset -
2502 and scale, if any - will be installed by the linker. */
2503 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2504 break;
2505
2506 case BFD_RELOC_ARC_TLS_LE_S9:
2507 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2508 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2509 break;
2510
2511 default:
2512 break;
2513 }
2514
2515 if (!fixP->fx_done)
2516 {
2517 return;
2518 }
2519
2520 /* Addjust the value if we have a constant. */
2521 value += fx_offset;
2522
2523 /* For hosts with longs bigger than 32-bits make sure that the top
2524 bits of a 32-bit negative value read in by the parser are set,
2525 so that the correct comparisons are made. */
2526 if (value & 0x80000000)
2527 value |= (-1L << 31);
2528
2529 reloc = fixP->fx_r_type;
2530 switch (reloc)
2531 {
2532 case BFD_RELOC_8:
2533 case BFD_RELOC_16:
2534 case BFD_RELOC_24:
2535 case BFD_RELOC_32:
2536 case BFD_RELOC_64:
2537 case BFD_RELOC_ARC_32_PCREL:
2538 md_number_to_chars (fixpos, value, fixP->fx_size);
2539 return;
2540
2541 case BFD_RELOC_ARC_GOTPC32:
2542 /* I cannot fix an GOTPC relocation because I need to relax it
2543 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2544 as_bad (_("Unsupported operation on reloc"));
2545 return;
2546
2547 case BFD_RELOC_ARC_TLS_DTPOFF:
2548 case BFD_RELOC_ARC_TLS_LE_32:
2549 gas_assert (!fixP->fx_addsy);
2550 gas_assert (!fixP->fx_subsy);
2551
2552 case BFD_RELOC_ARC_GOTOFF:
2553 case BFD_RELOC_ARC_32_ME:
2554 case BFD_RELOC_ARC_PC32:
2555 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2556 return;
2557
2558 case BFD_RELOC_ARC_PLT32:
2559 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2560 return;
2561
2562 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2563 reloc = BFD_RELOC_ARC_S25W_PCREL;
2564 goto solve_plt;
2565
2566 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2567 reloc = BFD_RELOC_ARC_S21H_PCREL;
2568 goto solve_plt;
2569
2570 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2571 reloc = BFD_RELOC_ARC_S25W_PCREL;
2572 goto solve_plt;
2573
2574 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2575 reloc = BFD_RELOC_ARC_S21W_PCREL;
2576
2577 case BFD_RELOC_ARC_S25W_PCREL:
2578 case BFD_RELOC_ARC_S21W_PCREL:
2579 case BFD_RELOC_ARC_S21H_PCREL:
2580 case BFD_RELOC_ARC_S25H_PCREL:
2581 case BFD_RELOC_ARC_S13_PCREL:
2582 solve_plt:
2583 operand = find_operand_for_reloc (reloc);
2584 gas_assert (operand);
2585 break;
2586
2587 default:
2588 {
2589 if ((int) fixP->fx_r_type >= 0)
2590 as_fatal (_("unhandled relocation type %s"),
2591 bfd_get_reloc_code_name (fixP->fx_r_type));
2592
2593 /* The rest of these fixups needs to be completely resolved as
2594 constants. */
2595 if (fixP->fx_addsy != 0
2596 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
2597 as_bad_where (fixP->fx_file, fixP->fx_line,
2598 _("non-absolute expression in constant field"));
2599
2600 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
2601 operand = &arc_operands[-(int) fixP->fx_r_type];
2602 break;
2603 }
2604 }
2605
2606 if (target_big_endian)
2607 {
2608 switch (fixP->fx_size)
2609 {
2610 case 4:
2611 insn = bfd_getb32 (fixpos);
2612 break;
2613 case 2:
2614 insn = bfd_getb16 (fixpos);
2615 break;
2616 default:
2617 as_bad_where (fixP->fx_file, fixP->fx_line,
2618 _("unknown fixup size"));
2619 }
2620 }
2621 else
2622 {
2623 insn = 0;
2624 switch (fixP->fx_size)
2625 {
2626 case 4:
2627 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
2628 break;
2629 case 2:
2630 insn = bfd_getl16 (fixpos);
2631 break;
2632 default:
2633 as_bad_where (fixP->fx_file, fixP->fx_line,
2634 _("unknown fixup size"));
2635 }
2636 }
2637
2638 insn = insert_operand (insn, operand, (offsetT) value,
2639 fixP->fx_file, fixP->fx_line);
2640
2641 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
2642 }
2643
2644 /* Prepare machine-dependent frags for relaxation.
2645
2646 Called just before relaxation starts. Any symbol that is now undefined
2647 will not become defined.
2648
2649 Return the correct fr_subtype in the frag.
2650
2651 Return the initial "guess for fr_var" to caller. The guess for fr_var
2652 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2653 or fr_var contributes to our returned value.
2654
2655 Although it may not be explicit in the frag, pretend
2656 fr_var starts with a value. */
2657
2658 int
2659 md_estimate_size_before_relax (fragS *fragP,
2660 segT segment)
2661 {
2662 int growth;
2663
2664 /* If the symbol is not located within the same section AND it's not
2665 an absolute section, use the maximum. OR if the symbol is a
2666 constant AND the insn is by nature not pc-rel, use the maximum.
2667 OR if the symbol is being equated against another symbol, use the
2668 maximum. OR if the symbol is weak use the maximum. */
2669 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
2670 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
2671 || (symbol_constant_p (fragP->fr_symbol)
2672 && !fragP->tc_frag_data.pcrel)
2673 || symbol_equated_p (fragP->fr_symbol)
2674 || S_IS_WEAK (fragP->fr_symbol))
2675 {
2676 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
2677 ++fragP->fr_subtype;
2678 }
2679
2680 growth = md_relax_table[fragP->fr_subtype].rlx_length;
2681 fragP->fr_var = growth;
2682
2683 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2684 fragP->fr_file, fragP->fr_line, growth);
2685
2686 return growth;
2687 }
2688
2689 /* Translate internal representation of relocation info to BFD target
2690 format. */
2691
2692 arelent *
2693 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
2694 fixS *fixP)
2695 {
2696 arelent *reloc;
2697 bfd_reloc_code_real_type code;
2698
2699 reloc = (arelent *) xmalloc (sizeof (* reloc));
2700 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2701 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2702 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2703
2704 /* Make sure none of our internal relocations make it this far.
2705 They'd better have been fully resolved by this point. */
2706 gas_assert ((int) fixP->fx_r_type > 0);
2707
2708 code = fixP->fx_r_type;
2709
2710 /* if we have something like add gp, pcl,
2711 _GLOBAL_OFFSET_TABLE_@gotpc. */
2712 if (code == BFD_RELOC_ARC_GOTPC32
2713 && GOT_symbol
2714 && fixP->fx_addsy == GOT_symbol)
2715 code = BFD_RELOC_ARC_GOTPC;
2716
2717 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2718 if (reloc->howto == NULL)
2719 {
2720 as_bad_where (fixP->fx_file, fixP->fx_line,
2721 _("cannot represent `%s' relocation in object file"),
2722 bfd_get_reloc_code_name (code));
2723 return NULL;
2724 }
2725
2726 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
2727 as_fatal (_("internal error? cannot generate `%s' relocation"),
2728 bfd_get_reloc_code_name (code));
2729
2730 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
2731
2732 if (code == BFD_RELOC_ARC_TLS_DTPOFF
2733 || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
2734 {
2735 asymbol *sym
2736 = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
2737 /* We just want to store a 24 bit index, but we have to wait
2738 till after write_contents has been called via
2739 bfd_map_over_sections before we can get the index from
2740 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2741 function is elf32-arc.c has to pick up the slack.
2742 Unfortunately, this leads to problems with hosts that have
2743 pointers wider than long (bfd_vma). There would be various
2744 ways to handle this, all error-prone :-( */
2745 reloc->addend = (bfd_vma) sym;
2746 if ((asymbol *) reloc->addend != sym)
2747 {
2748 as_bad ("Can't store pointer\n");
2749 return NULL;
2750 }
2751 }
2752 else
2753 reloc->addend = fixP->fx_offset;
2754
2755 return reloc;
2756 }
2757
2758 /* Perform post-processing of machine-dependent frags after relaxation.
2759 Called after relaxation is finished.
2760 In: Address of frag.
2761 fr_type == rs_machine_dependent.
2762 fr_subtype is what the address relaxed to.
2763
2764 Out: Any fixS:s and constants are set up. */
2765
2766 void
2767 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
2768 segT segment ATTRIBUTE_UNUSED,
2769 fragS *fragP)
2770 {
2771 const relax_typeS *table_entry;
2772 char *dest;
2773 const struct arc_opcode *opcode;
2774 struct arc_insn insn;
2775 int size, fix;
2776 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
2777
2778 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
2779 dest = fragP->fr_literal + fix;
2780 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
2781
2782 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2783 fragP->fr_file, fragP->fr_line,
2784 fragP->fr_subtype, fix, fragP->fr_var);
2785
2786 if (fragP->fr_subtype <= 0
2787 && fragP->fr_subtype >= arc_num_relax_opcodes)
2788 as_fatal (_("no relaxation found for this instruction."));
2789
2790 opcode = &arc_relax_opcodes[fragP->fr_subtype];
2791
2792 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
2793 relax_arg->nflg, &insn);
2794
2795 apply_fixups (&insn, fragP, fix);
2796
2797 size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
2798 gas_assert (table_entry->rlx_length == size);
2799 emit_insn0 (&insn, dest, TRUE);
2800
2801 fragP->fr_fix += table_entry->rlx_length;
2802 fragP->fr_var = 0;
2803 }
2804
2805 /* We have no need to default values of symbols. We could catch
2806 register names here, but that is handled by inserting them all in
2807 the symbol table to begin with. */
2808
2809 symbolS *
2810 md_undefined_symbol (char *name)
2811 {
2812 /* The arc abi demands that a GOT[0] should be referencible as
2813 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2814 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2815 if (((*name == '_')
2816 && (*(name+1) == 'G')
2817 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
2818 || ((*name == '_')
2819 && (*(name+1) == 'D')
2820 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
2821 {
2822 if (!GOT_symbol)
2823 {
2824 if (symbol_find (name))
2825 as_bad ("GOT already in symbol table");
2826
2827 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
2828 (valueT) 0, &zero_address_frag);
2829 };
2830 return GOT_symbol;
2831 }
2832 return NULL;
2833 }
2834
2835 /* Turn a string in input_line_pointer into a floating point constant
2836 of type type, and store the appropriate bytes in *litP. The number
2837 of LITTLENUMS emitted is stored in *sizeP. An error message is
2838 returned, or NULL on OK. */
2839
2840 char *
2841 md_atof (int type, char *litP, int *sizeP)
2842 {
2843 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2844 }
2845
2846 /* Called for any expression that can not be recognized. When the
2847 function is called, `input_line_pointer' will point to the start of
2848 the expression. */
2849
2850 void
2851 md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
2852 {
2853 char *p = input_line_pointer;
2854 if (*p == '@')
2855 {
2856 input_line_pointer++;
2857 expressionP->X_op = O_symbol;
2858 expression (expressionP);
2859 }
2860 }
2861
2862 /* This function is called from the function 'expression', it attempts
2863 to parse special names (in our case register names). It fills in
2864 the expression with the identified register. It returns TRUE if
2865 it is a register and FALSE otherwise. */
2866
2867 bfd_boolean
2868 arc_parse_name (const char *name,
2869 struct expressionS *e)
2870 {
2871 struct symbol *sym;
2872
2873 if (!assembling_insn)
2874 return FALSE;
2875
2876 /* Handle only registers. */
2877 if (e->X_op != O_absent)
2878 return FALSE;
2879
2880 sym = hash_find (arc_reg_hash, name);
2881 if (sym)
2882 {
2883 e->X_op = O_register;
2884 e->X_add_number = S_GET_VALUE (sym);
2885 return TRUE;
2886 }
2887 return FALSE;
2888 }
2889
2890 /* md_parse_option
2891 Invocation line includes a switch not recognized by the base assembler.
2892 See if it's a processor-specific option.
2893
2894 New options (supported) are:
2895
2896 -mcpu=<cpu name> Assemble for selected processor
2897 -EB/-mbig-endian Big-endian
2898 -EL/-mlittle-endian Little-endian
2899 -mrelax Enable relaxation
2900
2901 The following CPU names are recognized:
2902 arc700, av2em, av2hs. */
2903
2904 int
2905 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
2906 {
2907 switch (c)
2908 {
2909 case OPTION_ARC600:
2910 case OPTION_ARC601:
2911 return md_parse_option (OPTION_MCPU, "arc600");
2912
2913 case OPTION_ARC700:
2914 return md_parse_option (OPTION_MCPU, "arc700");
2915
2916 case OPTION_ARCEM:
2917 return md_parse_option (OPTION_MCPU, "arcem");
2918
2919 case OPTION_ARCHS:
2920 return md_parse_option (OPTION_MCPU, "archs");
2921
2922 case OPTION_MCPU:
2923 {
2924 arc_select_cpu (arg);
2925 mach_type_specified_p = 1;
2926 break;
2927 }
2928
2929 case OPTION_EB:
2930 arc_target_format = "elf32-bigarc";
2931 byte_order = BIG_ENDIAN;
2932 break;
2933
2934 case OPTION_EL:
2935 arc_target_format = "elf32-littlearc";
2936 byte_order = LITTLE_ENDIAN;
2937 break;
2938
2939 case OPTION_CD:
2940 /* This option has an effect only on ARC EM. */
2941 if (arc_target & ARC_OPCODE_ARCv2EM)
2942 arc_features |= ARC_CD;
2943 break;
2944
2945 case OPTION_RELAX:
2946 relaxation_state = 1;
2947 break;
2948
2949 case OPTION_USER_MODE:
2950 case OPTION_LD_EXT_MASK:
2951 case OPTION_SWAP:
2952 case OPTION_NORM:
2953 case OPTION_BARREL_SHIFT:
2954 case OPTION_MIN_MAX:
2955 case OPTION_NO_MPY:
2956 case OPTION_EA:
2957 case OPTION_MUL64:
2958 case OPTION_SIMD:
2959 case OPTION_SPFP:
2960 case OPTION_DPFP:
2961 case OPTION_XMAC_D16:
2962 case OPTION_XMAC_24:
2963 case OPTION_DSP_PACKA:
2964 case OPTION_CRC:
2965 case OPTION_DVBF:
2966 case OPTION_TELEPHONY:
2967 case OPTION_XYMEMORY:
2968 case OPTION_LOCK:
2969 case OPTION_SWAPE:
2970 case OPTION_RTSC:
2971 case OPTION_FPUDA:
2972 /* Dummy options are accepted but have no effect. */
2973 break;
2974
2975 default:
2976 return 0;
2977 }
2978
2979 return 1;
2980 }
2981
2982 void
2983 md_show_usage (FILE *stream)
2984 {
2985 fprintf (stream, _("ARC-specific assembler options:\n"));
2986
2987 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
2988 fprintf (stream,
2989 " -mcode-density\t enable code density option for ARC EM\n");
2990
2991 fprintf (stream, _("\
2992 -EB assemble code for a big-endian cpu\n"));
2993 fprintf (stream, _("\
2994 -EL assemble code for a little-endian cpu\n"));
2995 fprintf (stream, _("\
2996 -mrelax Enable relaxation\n"));
2997
2998 }
2999
3000 /* Find the proper relocation for the given opcode. */
3001
3002 static extended_bfd_reloc_code_real_type
3003 find_reloc (const char *name,
3004 const char *opcodename,
3005 const struct arc_flags *pflags,
3006 int nflg,
3007 extended_bfd_reloc_code_real_type reloc)
3008 {
3009 unsigned int i;
3010 int j;
3011 bfd_boolean found_flag, tmp;
3012 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3013
3014 for (i = 0; i < arc_num_equiv_tab; i++)
3015 {
3016 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3017
3018 /* Find the entry. */
3019 if (strcmp (name, r->name))
3020 continue;
3021 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3022 continue;
3023 if (r->flags[0])
3024 {
3025 if (!nflg)
3026 continue;
3027 found_flag = FALSE;
3028 unsigned * psflg = (unsigned *)r->flags;
3029 do
3030 {
3031 tmp = FALSE;
3032 for (j = 0; j < nflg; j++)
3033 if (!strcmp (pflags[j].name,
3034 arc_flag_operands[*psflg].name))
3035 {
3036 tmp = TRUE;
3037 break;
3038 }
3039 if (!tmp)
3040 {
3041 found_flag = FALSE;
3042 break;
3043 }
3044 else
3045 {
3046 found_flag = TRUE;
3047 }
3048 ++ psflg;
3049 } while (*psflg);
3050
3051 if (!found_flag)
3052 continue;
3053 }
3054
3055 if (reloc != r->oldreloc)
3056 continue;
3057 /* Found it. */
3058 ret = r->newreloc;
3059 break;
3060 }
3061
3062 if (ret == BFD_RELOC_UNUSED)
3063 as_bad (_("Unable to find %s relocation for instruction %s"),
3064 name, opcodename);
3065 return ret;
3066 }
3067
3068 /* All the symbol types that are allowed to be used for
3069 relaxation. */
3070
3071 static bfd_boolean
3072 may_relax_expr (expressionS tok)
3073 {
3074 /* Check if we have unrelaxable relocs. */
3075 switch (tok.X_md)
3076 {
3077 default:
3078 break;
3079 case O_plt:
3080 return FALSE;
3081 }
3082
3083 switch (tok.X_op)
3084 {
3085 case O_symbol:
3086 case O_multiply:
3087 case O_divide:
3088 case O_modulus:
3089 case O_add:
3090 case O_subtract:
3091 break;
3092
3093 default:
3094 return FALSE;
3095 }
3096 return TRUE;
3097 }
3098
3099 /* Checks if flags are in line with relaxable insn. */
3100
3101 static bfd_boolean
3102 relaxable_flag (const struct arc_relaxable_ins *ins,
3103 const struct arc_flags *pflags,
3104 int nflgs)
3105 {
3106 unsigned flag_class,
3107 flag,
3108 flag_class_idx = 0,
3109 flag_idx = 0;
3110
3111 const struct arc_flag_operand *flag_opand;
3112 int i, counttrue = 0;
3113
3114 /* Iterate through flags classes. */
3115 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3116 {
3117 /* Iterate through flags in flag class. */
3118 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3119 != 0)
3120 {
3121 flag_opand = &arc_flag_operands[flag];
3122 /* Iterate through flags in ins to compare. */
3123 for (i = 0; i < nflgs; ++i)
3124 {
3125 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3126 ++counttrue;
3127 }
3128
3129 ++flag_idx;
3130 }
3131
3132 ++flag_class_idx;
3133 flag_idx = 0;
3134 }
3135
3136 /* If counttrue == nflgs, then all flags have been found. */
3137 return (counttrue == nflgs ? TRUE : FALSE);
3138 }
3139
3140 /* Checks if operands are in line with relaxable insn. */
3141
3142 static bfd_boolean
3143 relaxable_operand (const struct arc_relaxable_ins *ins,
3144 const expressionS *tok,
3145 int ntok)
3146 {
3147 const enum rlx_operand_type *operand = &ins->operands[0];
3148 int i = 0;
3149
3150 while (*operand != EMPTY)
3151 {
3152 const expressionS *epr = &tok[i];
3153
3154 if (i != 0 && i >= ntok)
3155 return FALSE;
3156
3157 switch (*operand)
3158 {
3159 case IMMEDIATE:
3160 if (!(epr->X_op == O_multiply
3161 || epr->X_op == O_divide
3162 || epr->X_op == O_modulus
3163 || epr->X_op == O_add
3164 || epr->X_op == O_subtract
3165 || epr->X_op == O_symbol))
3166 return FALSE;
3167 break;
3168
3169 case REGISTER_DUP:
3170 if ((i <= 0)
3171 || (epr->X_add_number != tok[i - 1].X_add_number))
3172 return FALSE;
3173 /* Fall through. */
3174 case REGISTER:
3175 if (epr->X_op != O_register)
3176 return FALSE;
3177 break;
3178
3179 case REGISTER_S:
3180 if (epr->X_op != O_register)
3181 return FALSE;
3182
3183 switch (epr->X_add_number)
3184 {
3185 case 0: case 1: case 2: case 3:
3186 case 12: case 13: case 14: case 15:
3187 break;
3188 default:
3189 return FALSE;
3190 }
3191 break;
3192
3193 case REGISTER_NO_GP:
3194 if ((epr->X_op != O_register)
3195 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3196 return FALSE;
3197 break;
3198
3199 case BRACKET:
3200 if (epr->X_op != O_bracket)
3201 return FALSE;
3202 break;
3203
3204 default:
3205 /* Don't understand, bail out. */
3206 return FALSE;
3207 break;
3208 }
3209
3210 ++i;
3211 operand = &ins->operands[i];
3212 }
3213
3214 return (i == ntok ? TRUE : FALSE);
3215 }
3216
3217 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3218
3219 static bfd_boolean
3220 relax_insn_p (const struct arc_opcode *opcode,
3221 const expressionS *tok,
3222 int ntok,
3223 const struct arc_flags *pflags,
3224 int nflg)
3225 {
3226 unsigned i;
3227 bfd_boolean rv = FALSE;
3228
3229 /* Check the relaxation table. */
3230 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3231 {
3232 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3233
3234 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3235 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3236 && relaxable_operand (arc_rlx_ins, tok, ntok)
3237 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3238 {
3239 rv = TRUE;
3240 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3241 memcpy (&frag_now->tc_frag_data.tok, tok,
3242 sizeof (expressionS) * ntok);
3243 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3244 sizeof (struct arc_flags) * nflg);
3245 frag_now->tc_frag_data.nflg = nflg;
3246 frag_now->tc_frag_data.ntok = ntok;
3247 break;
3248 }
3249 }
3250
3251 return rv;
3252 }
3253
3254 /* Turn an opcode description and a set of arguments into
3255 an instruction and a fixup. */
3256
3257 static void
3258 assemble_insn (const struct arc_opcode *opcode,
3259 const expressionS *tok,
3260 int ntok,
3261 const struct arc_flags *pflags,
3262 int nflg,
3263 struct arc_insn *insn)
3264 {
3265 const expressionS *reloc_exp = NULL;
3266 unsigned image;
3267 const unsigned char *argidx;
3268 int i;
3269 int tokidx = 0;
3270 unsigned char pcrel = 0;
3271 bfd_boolean needGOTSymbol;
3272 bfd_boolean has_delay_slot = FALSE;
3273 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3274
3275 memset (insn, 0, sizeof (*insn));
3276 image = opcode->opcode;
3277
3278 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3279 frag_now->fr_file, frag_now->fr_line, opcode->name,
3280 opcode->opcode);
3281
3282 /* Handle operands. */
3283 for (argidx = opcode->operands; *argidx; ++argidx)
3284 {
3285 const struct arc_operand *operand = &arc_operands[*argidx];
3286 const expressionS *t = (const expressionS *) 0;
3287
3288 if ((operand->flags & ARC_OPERAND_FAKE)
3289 && !(operand->flags & ARC_OPERAND_BRAKET))
3290 continue;
3291
3292 if (operand->flags & ARC_OPERAND_DUPLICATE)
3293 {
3294 /* Duplicate operand, already inserted. */
3295 tokidx ++;
3296 continue;
3297 }
3298
3299 if (tokidx >= ntok)
3300 {
3301 abort ();
3302 }
3303 else
3304 t = &tok[tokidx++];
3305
3306 /* Regardless if we have a reloc or not mark the instruction
3307 limm if it is the case. */
3308 if (operand->flags & ARC_OPERAND_LIMM)
3309 insn->has_limm = TRUE;
3310
3311 switch (t->X_op)
3312 {
3313 case O_register:
3314 image = insert_operand (image, operand, regno (t->X_add_number),
3315 NULL, 0);
3316 break;
3317
3318 case O_constant:
3319 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3320 reloc_exp = t;
3321 if (operand->flags & ARC_OPERAND_LIMM)
3322 insn->limm = t->X_add_number;
3323 break;
3324
3325 case O_bracket:
3326 /* Ignore brackets. */
3327 break;
3328
3329 case O_absent:
3330 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3331 break;
3332
3333 case O_subtract:
3334 /* Maybe register range. */
3335 if ((t->X_add_number == 0)
3336 && contains_register (t->X_add_symbol)
3337 && contains_register (t->X_op_symbol))
3338 {
3339 int regs;
3340
3341 regs = get_register (t->X_add_symbol);
3342 regs <<= 16;
3343 regs |= get_register (t->X_op_symbol);
3344 image = insert_operand (image, operand, regs, NULL, 0);
3345 break;
3346 }
3347
3348 default:
3349 /* This operand needs a relocation. */
3350 needGOTSymbol = FALSE;
3351
3352 switch (t->X_md)
3353 {
3354 case O_plt:
3355 needGOTSymbol = TRUE;
3356 reloc = find_reloc ("plt", opcode->name,
3357 pflags, nflg,
3358 operand->default_reloc);
3359 break;
3360
3361 case O_gotoff:
3362 case O_gotpc:
3363 needGOTSymbol = TRUE;
3364 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3365 break;
3366 case O_pcl:
3367 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3368 if (ARC_SHORT (opcode->mask))
3369 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3370 _("Unable to use @pcl relocation for insn %s"),
3371 opcode->name);
3372 break;
3373 case O_sda:
3374 reloc = find_reloc ("sda", opcode->name,
3375 pflags, nflg,
3376 operand->default_reloc);
3377 break;
3378 case O_tlsgd:
3379 case O_tlsie:
3380 needGOTSymbol = TRUE;
3381 /* Fall-through. */
3382
3383 case O_tpoff:
3384 case O_dtpoff:
3385 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3386 break;
3387
3388 case O_tpoff9: /*FIXME! Check for the conditionality of
3389 the insn. */
3390 case O_dtpoff9: /*FIXME! Check for the conditionality of
3391 the insn. */
3392 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3393 break;
3394
3395 default:
3396 /* Just consider the default relocation. */
3397 reloc = operand->default_reloc;
3398 break;
3399 }
3400
3401 if (needGOTSymbol && (GOT_symbol == NULL))
3402 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3403
3404 reloc_exp = t;
3405
3406 #if 0
3407 if (reloc > 0)
3408 {
3409 /* sanity checks. */
3410 reloc_howto_type *reloc_howto
3411 = bfd_reloc_type_lookup (stdoutput,
3412 (bfd_reloc_code_real_type) reloc);
3413 unsigned reloc_bitsize = reloc_howto->bitsize;
3414 if (reloc_howto->rightshift)
3415 reloc_bitsize -= reloc_howto->rightshift;
3416 if (reloc_bitsize != operand->bits)
3417 {
3418 as_bad (_("invalid relocation %s for field"),
3419 bfd_get_reloc_code_name (reloc));
3420 return;
3421 }
3422 }
3423 #endif
3424 if (insn->nfixups >= MAX_INSN_FIXUPS)
3425 as_fatal (_("too many fixups"));
3426
3427 struct arc_fixup *fixup;
3428 fixup = &insn->fixups[insn->nfixups++];
3429 fixup->exp = *t;
3430 fixup->reloc = reloc;
3431 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3432 fixup->pcrel = pcrel;
3433 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3434 TRUE : FALSE;
3435 break;
3436 }
3437 }
3438
3439 /* Handle flags. */
3440 for (i = 0; i < nflg; i++)
3441 {
3442 const struct arc_flag_operand *flg_operand =
3443 &arc_flag_operands[pflags[i].code];
3444
3445 /* Check if the instruction has a delay slot. */
3446 if (!strcmp (flg_operand->name, "d"))
3447 has_delay_slot = TRUE;
3448
3449 /* There is an exceptional case when we cannot insert a flag
3450 just as it is. The .T flag must be handled in relation with
3451 the relative address. */
3452 if (!strcmp (flg_operand->name, "t")
3453 || !strcmp (flg_operand->name, "nt"))
3454 {
3455 unsigned bitYoperand = 0;
3456 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3457 if (!strcmp (flg_operand->name, "t"))
3458 if (!strcmp (opcode->name, "bbit0")
3459 || !strcmp (opcode->name, "bbit1"))
3460 bitYoperand = arc_NToperand;
3461 else
3462 bitYoperand = arc_Toperand;
3463 else
3464 if (!strcmp (opcode->name, "bbit0")
3465 || !strcmp (opcode->name, "bbit1"))
3466 bitYoperand = arc_Toperand;
3467 else
3468 bitYoperand = arc_NToperand;
3469
3470 gas_assert (reloc_exp != NULL);
3471 if (reloc_exp->X_op == O_constant)
3472 {
3473 /* Check if we have a constant and solved it
3474 immediately. */
3475 offsetT val = reloc_exp->X_add_number;
3476 image |= insert_operand (image, &arc_operands[bitYoperand],
3477 val, NULL, 0);
3478 }
3479 else
3480 {
3481 struct arc_fixup *fixup;
3482
3483 if (insn->nfixups >= MAX_INSN_FIXUPS)
3484 as_fatal (_("too many fixups"));
3485
3486 fixup = &insn->fixups[insn->nfixups++];
3487 fixup->exp = *reloc_exp;
3488 fixup->reloc = -bitYoperand;
3489 fixup->pcrel = pcrel;
3490 fixup->islong = FALSE;
3491 }
3492 }
3493 else
3494 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3495 << flg_operand->shift;
3496 }
3497
3498 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3499
3500 /* Short instruction? */
3501 insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
3502
3503 insn->insn = image;
3504
3505 /* Update last insn status. */
3506 arc_last_insns[1] = arc_last_insns[0];
3507 arc_last_insns[0].opcode = opcode;
3508 arc_last_insns[0].has_limm = insn->has_limm;
3509 arc_last_insns[0].has_delay_slot = has_delay_slot;
3510
3511 /* Check if the current instruction is legally used. */
3512 if (arc_last_insns[1].has_delay_slot
3513 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3514 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3515 _("A jump/branch instruction in delay slot."));
3516 }
3517
3518 void
3519 arc_handle_align (fragS* fragP)
3520 {
3521 if ((fragP)->fr_type == rs_align_code)
3522 {
3523 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3524 valueT count = ((fragP)->fr_next->fr_address
3525 - (fragP)->fr_address - (fragP)->fr_fix);
3526
3527 (fragP)->fr_var = 2;
3528
3529 if (count & 1)/* Padding in the gap till the next 2-byte
3530 boundary with 0s. */
3531 {
3532 (fragP)->fr_fix++;
3533 *dest++ = 0;
3534 }
3535 /* Writing nop_s. */
3536 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3537 }
3538 }
3539
3540 /* Here we decide which fixups can be adjusted to make them relative
3541 to the beginning of the section instead of the symbol. Basically
3542 we need to make sure that the dynamic relocations are done
3543 correctly, so in some cases we force the original symbol to be
3544 used. */
3545
3546 int
3547 tc_arc_fix_adjustable (fixS *fixP)
3548 {
3549
3550 /* Prevent all adjustments to global symbols. */
3551 if (S_IS_EXTERNAL (fixP->fx_addsy))
3552 return 0;
3553 if (S_IS_WEAK (fixP->fx_addsy))
3554 return 0;
3555
3556 /* Adjust_reloc_syms doesn't know about the GOT. */
3557 switch (fixP->fx_r_type)
3558 {
3559 case BFD_RELOC_ARC_GOTPC32:
3560 case BFD_RELOC_ARC_PLT32:
3561 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3562 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3563 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3564 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3565 return 0;
3566
3567 default:
3568 break;
3569 }
3570
3571 return 1;
3572 }
3573
3574 /* Compute the reloc type of an expression EXP. */
3575
3576 static void
3577 arc_check_reloc (expressionS *exp,
3578 bfd_reloc_code_real_type *r_type_p)
3579 {
3580 if (*r_type_p == BFD_RELOC_32
3581 && exp->X_op == O_subtract
3582 && exp->X_op_symbol != NULL
3583 && exp->X_op_symbol->bsym->section == now_seg)
3584 *r_type_p = BFD_RELOC_ARC_32_PCREL;
3585 }
3586
3587
3588 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3589
3590 void
3591 arc_cons_fix_new (fragS *frag,
3592 int off,
3593 int size,
3594 expressionS *exp,
3595 bfd_reloc_code_real_type r_type)
3596 {
3597 r_type = BFD_RELOC_UNUSED;
3598
3599 switch (size)
3600 {
3601 case 1:
3602 r_type = BFD_RELOC_8;
3603 break;
3604
3605 case 2:
3606 r_type = BFD_RELOC_16;
3607 break;
3608
3609 case 3:
3610 r_type = BFD_RELOC_24;
3611 break;
3612
3613 case 4:
3614 r_type = BFD_RELOC_32;
3615 arc_check_reloc (exp, &r_type);
3616 break;
3617
3618 case 8:
3619 r_type = BFD_RELOC_64;
3620 break;
3621
3622 default:
3623 as_bad (_("unsupported BFD relocation size %u"), size);
3624 r_type = BFD_RELOC_UNUSED;
3625 }
3626
3627 fix_new_exp (frag, off, size, exp, 0, r_type);
3628 }
3629
3630 /* The actual routine that checks the ZOL conditions. */
3631
3632 static void
3633 check_zol (symbolS *s)
3634 {
3635 switch (arc_mach_type)
3636 {
3637 case bfd_mach_arc_arcv2:
3638 if (arc_target & ARC_OPCODE_ARCv2EM)
3639 return;
3640
3641 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
3642 || arc_last_insns[1].has_delay_slot)
3643 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3644 S_GET_NAME (s));
3645
3646 break;
3647 case bfd_mach_arc_arc600:
3648
3649 if (is_kernel_insn_p (arc_last_insns[0].opcode))
3650 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3651 S_GET_NAME (s));
3652
3653 if (arc_last_insns[0].has_limm
3654 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3655 as_bad (_("A jump instruction with long immediate detected at the \
3656 end of the ZOL label @%s"), S_GET_NAME (s));
3657
3658 /* Fall through. */
3659 case bfd_mach_arc_arc700:
3660 if (arc_last_insns[0].has_delay_slot)
3661 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3662 S_GET_NAME (s));
3663
3664 break;
3665 default:
3666 break;
3667 }
3668 }
3669
3670 /* If ZOL end check the last two instruction for illegals. */
3671 void
3672 arc_frob_label (symbolS * sym)
3673 {
3674 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
3675 check_zol (sym);
3676
3677 dwarf2_emit_label (sym);
3678 }
3679
3680 /* Used because generic relaxation assumes a pc-rel value whilst we
3681 also relax instructions that use an absolute value resolved out of
3682 relative values (if that makes any sense). An example: 'add r1,
3683 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3684 but if they're in the same section we can subtract the section
3685 offset relocation which ends up in a resolved value. So if @.L2 is
3686 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3687 .text + 0x40 = 0x10. */
3688 int
3689 arc_pcrel_adjust (fragS *fragP)
3690 {
3691 if (!fragP->tc_frag_data.pcrel)
3692 return fragP->fr_address + fragP->fr_fix;
3693
3694 return 0;
3695 }
3696
3697 /* Initialize the DWARF-2 unwind information for this procedure. */
3698
3699 void
3700 tc_arc_frame_initial_instructions (void)
3701 {
3702 /* Stack pointer is register 28. */
3703 cfi_add_CFA_def_cfa_register (28);
3704 }
3705
3706 int
3707 tc_arc_regname_to_dw2regnum (char *regname)
3708 {
3709 struct symbol *sym;
3710
3711 sym = hash_find (arc_reg_hash, regname);
3712 if (sym)
3713 return S_GET_VALUE (sym);
3714
3715 return -1;
3716 }
GDB Binutils - Deliverables
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