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[ARC] Add arc-cpu.def with processor definitions
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "subsegs.h"
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
29
30 #include "opcode/arc.h"
31 #include "opcode/arc-attrs.h"
32 #include "elf/arc.h"
33 #include "../opcodes/arc-ext.h"
34
35 /* Defines section. */
36
37 #define MAX_INSN_FIXUPS 2
38 #define MAX_CONSTR_STR 20
39 #define FRAG_MAX_GROWTH 8
40
41 #ifdef DEBUG
42 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 #else
44 # define pr_debug(fmt, args...)
45 #endif
46
47 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
49 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
51
52 /* Equal to MAX_PRECISION in atof-ieee.c. */
53 #define MAX_LITTLENUMS 6
54
55 #ifndef TARGET_WITH_CPU
56 #define TARGET_WITH_CPU "arc700"
57 #endif /* TARGET_WITH_CPU */
58
59 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61 #define streq(a, b) (strcmp (a, b) == 0)
62
63 /* Enum used to enumerate the relaxable ins operands. */
64 enum rlx_operand_type
65 {
66 EMPTY = 0,
67 REGISTER,
68 REGISTER_S, /* Register for short instruction(s). */
69 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
70 REGISTER_DUP, /* Duplication of previous operand of type register. */
71 IMMEDIATE,
72 BRACKET
73 };
74
75 enum arc_rlx_types
76 {
77 ARC_RLX_NONE = 0,
78 ARC_RLX_BL_S,
79 ARC_RLX_BL,
80 ARC_RLX_B_S,
81 ARC_RLX_B,
82 ARC_RLX_ADD_U3,
83 ARC_RLX_ADD_U6,
84 ARC_RLX_ADD_LIMM,
85 ARC_RLX_LD_U7,
86 ARC_RLX_LD_S9,
87 ARC_RLX_LD_LIMM,
88 ARC_RLX_MOV_U8,
89 ARC_RLX_MOV_S12,
90 ARC_RLX_MOV_LIMM,
91 ARC_RLX_SUB_U3,
92 ARC_RLX_SUB_U6,
93 ARC_RLX_SUB_LIMM,
94 ARC_RLX_MPY_U6,
95 ARC_RLX_MPY_LIMM,
96 ARC_RLX_MOV_RU6,
97 ARC_RLX_MOV_RLIMM,
98 ARC_RLX_ADD_RRU6,
99 ARC_RLX_ADD_RRLIMM,
100 };
101
102 /* Macros section. */
103
104 #define regno(x) ((x) & 0x3F)
105 #define is_ir_num(x) (((x) & ~0x3F) == 0)
106 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107 #define is_spfp_p(op) (((sc) == SPX))
108 #define is_dpfp_p(op) (((sc) == DPX))
109 #define is_fpuda_p(op) (((sc) == DPA))
110 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP))
112 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
113 #define is_nps400_p(op) (((sc) == NPS400))
114
115 /* Generic assembler global variables which must be defined by all
116 targets. */
117
118 /* Characters which always start a comment. */
119 const char comment_chars[] = "#;";
120
121 /* Characters which start a comment at the beginning of a line. */
122 const char line_comment_chars[] = "#";
123
124 /* Characters which may be used to separate multiple commands on a
125 single line. */
126 const char line_separator_chars[] = "`";
127
128 /* Characters which are used to indicate an exponent in a floating
129 point number. */
130 const char EXP_CHARS[] = "eE";
131
132 /* Chars that mean this number is a floating point constant
133 As in 0f12.456 or 0d1.2345e12. */
134 const char FLT_CHARS[] = "rRsSfFdD";
135
136 /* Byte order. */
137 extern int target_big_endian;
138 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
139 static int byte_order = DEFAULT_BYTE_ORDER;
140
141 /* Arc extension section. */
142 static segT arcext_section;
143
144 /* By default relaxation is disabled. */
145 static int relaxation_state = 0;
146
147 extern int arc_get_mach (char *);
148
149 /* Forward declarations. */
150 static void arc_lcomm (int);
151 static void arc_option (int);
152 static void arc_extra_reloc (int);
153 static void arc_extinsn (int);
154 static void arc_extcorereg (int);
155 static void arc_attribute (int);
156
157 const pseudo_typeS md_pseudo_table[] =
158 {
159 /* Make sure that .word is 32 bits. */
160 { "word", cons, 4 },
161
162 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
163 { "lcomm", arc_lcomm, 0 },
164 { "lcommon", arc_lcomm, 0 },
165 { "cpu", arc_option, 0 },
166
167 { "arc_attribute", arc_attribute, 0 },
168 { "extinstruction", arc_extinsn, 0 },
169 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
170 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
171 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
172
173 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
174 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
175
176 { NULL, NULL, 0 }
177 };
178
179 const char *md_shortopts = "";
180
181 enum options
182 {
183 OPTION_EB = OPTION_MD_BASE,
184 OPTION_EL,
185
186 OPTION_ARC600,
187 OPTION_ARC601,
188 OPTION_ARC700,
189 OPTION_ARCEM,
190 OPTION_ARCHS,
191
192 OPTION_MCPU,
193 OPTION_CD,
194 OPTION_RELAX,
195 OPTION_NPS400,
196
197 OPTION_SPFP,
198 OPTION_DPFP,
199 OPTION_FPUDA,
200
201 /* The following options are deprecated and provided here only for
202 compatibility reasons. */
203 OPTION_USER_MODE,
204 OPTION_LD_EXT_MASK,
205 OPTION_SWAP,
206 OPTION_NORM,
207 OPTION_BARREL_SHIFT,
208 OPTION_MIN_MAX,
209 OPTION_NO_MPY,
210 OPTION_EA,
211 OPTION_MUL64,
212 OPTION_SIMD,
213 OPTION_XMAC_D16,
214 OPTION_XMAC_24,
215 OPTION_DSP_PACKA,
216 OPTION_CRC,
217 OPTION_DVBF,
218 OPTION_TELEPHONY,
219 OPTION_XYMEMORY,
220 OPTION_LOCK,
221 OPTION_SWAPE,
222 OPTION_RTSC
223 };
224
225 struct option md_longopts[] =
226 {
227 { "EB", no_argument, NULL, OPTION_EB },
228 { "EL", no_argument, NULL, OPTION_EL },
229 { "mcpu", required_argument, NULL, OPTION_MCPU },
230 { "mA6", no_argument, NULL, OPTION_ARC600 },
231 { "mARC600", no_argument, NULL, OPTION_ARC600 },
232 { "mARC601", no_argument, NULL, OPTION_ARC601 },
233 { "mARC700", no_argument, NULL, OPTION_ARC700 },
234 { "mA7", no_argument, NULL, OPTION_ARC700 },
235 { "mEM", no_argument, NULL, OPTION_ARCEM },
236 { "mHS", no_argument, NULL, OPTION_ARCHS },
237 { "mcode-density", no_argument, NULL, OPTION_CD },
238 { "mrelax", no_argument, NULL, OPTION_RELAX },
239 { "mnps400", no_argument, NULL, OPTION_NPS400 },
240
241 /* Floating point options */
242 { "mspfp", no_argument, NULL, OPTION_SPFP},
243 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
244 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
245 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
246 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
247 { "mdpfp", no_argument, NULL, OPTION_DPFP},
248 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
249 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
250 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
251 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
252 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
253
254 /* The following options are deprecated and provided here only for
255 compatibility reasons. */
256 { "mav2em", no_argument, NULL, OPTION_ARCEM },
257 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
258 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
259 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
260 { "mswap", no_argument, NULL, OPTION_SWAP },
261 { "mnorm", no_argument, NULL, OPTION_NORM },
262 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
263 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
264 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
265 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
266 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
267 { "mea", no_argument, NULL, OPTION_EA },
268 { "mEA", no_argument, NULL, OPTION_EA },
269 { "mmul64", no_argument, NULL, OPTION_MUL64 },
270 { "msimd", no_argument, NULL, OPTION_SIMD},
271 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
272 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
273 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
274 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
275 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
276 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
277 { "mcrc", no_argument, NULL, OPTION_CRC},
278 { "mdvbf", no_argument, NULL, OPTION_DVBF},
279 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
280 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
281 { "mlock", no_argument, NULL, OPTION_LOCK},
282 { "mswape", no_argument, NULL, OPTION_SWAPE},
283 { "mrtsc", no_argument, NULL, OPTION_RTSC},
284
285 { NULL, no_argument, NULL, 0 }
286 };
287
288 size_t md_longopts_size = sizeof (md_longopts);
289
290 /* Local data and data types. */
291
292 /* Used since new relocation types are introduced in this
293 file (DUMMY_RELOC_LITUSE_*). */
294 typedef int extended_bfd_reloc_code_real_type;
295
296 struct arc_fixup
297 {
298 expressionS exp;
299
300 extended_bfd_reloc_code_real_type reloc;
301
302 /* index into arc_operands. */
303 unsigned int opindex;
304
305 /* PC-relative, used by internals fixups. */
306 unsigned char pcrel;
307
308 /* TRUE if this fixup is for LIMM operand. */
309 bfd_boolean islong;
310 };
311
312 struct arc_insn
313 {
314 unsigned long long int insn;
315 int nfixups;
316 struct arc_fixup fixups[MAX_INSN_FIXUPS];
317 long limm;
318 unsigned int len; /* Length of instruction in bytes. */
319 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
320 valid. */
321 bfd_boolean relax; /* Boolean value: TRUE if needs
322 relaxation. */
323 };
324
325 /* Structure to hold any last two instructions. */
326 static struct arc_last_insn
327 {
328 /* Saved instruction opcode. */
329 const struct arc_opcode *opcode;
330
331 /* Boolean value: TRUE if current insn is short. */
332 bfd_boolean has_limm;
333
334 /* Boolean value: TRUE if current insn has delay slot. */
335 bfd_boolean has_delay_slot;
336 } arc_last_insns[2];
337
338 /* Extension instruction suffix classes. */
339 typedef struct
340 {
341 const char *name;
342 int len;
343 int attr_class;
344 } attributes_t;
345
346 static const attributes_t suffixclass[] =
347 {
348 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
349 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
350 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
351 };
352
353 /* Extension instruction syntax classes. */
354 static const attributes_t syntaxclass[] =
355 {
356 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
357 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
358 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
359 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
360 };
361
362 /* Extension instruction syntax classes modifiers. */
363 static const attributes_t syntaxclassmod[] =
364 {
365 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
366 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
367 };
368
369 /* Extension register type. */
370 typedef struct
371 {
372 char *name;
373 int number;
374 int imode;
375 } extRegister_t;
376
377 /* A structure to hold the additional conditional codes. */
378 static struct
379 {
380 struct arc_flag_operand *arc_ext_condcode;
381 int size;
382 } ext_condcode = { NULL, 0 };
383
384 /* Structure to hold an entry in ARC_OPCODE_HASH. */
385 struct arc_opcode_hash_entry
386 {
387 /* The number of pointers in the OPCODE list. */
388 size_t count;
389
390 /* Points to a list of opcode pointers. */
391 const struct arc_opcode **opcode;
392 };
393
394 /* Structure used for iterating through an arc_opcode_hash_entry. */
395 struct arc_opcode_hash_entry_iterator
396 {
397 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
398 size_t index;
399
400 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
401 returned by this iterator. */
402 const struct arc_opcode *opcode;
403 };
404
405 /* Forward declaration. */
406 static void assemble_insn
407 (const struct arc_opcode *, const expressionS *, int,
408 const struct arc_flags *, int, struct arc_insn *);
409
410 /* The selection of the machine type can come from different sources. This
411 enum is used to track how the selection was made in order to perform
412 error checks. */
413 enum mach_selection_type
414 {
415 MACH_SELECTION_NONE,
416 MACH_SELECTION_FROM_DEFAULT,
417 MACH_SELECTION_FROM_CPU_DIRECTIVE,
418 MACH_SELECTION_FROM_COMMAND_LINE
419 };
420
421 /* How the current machine type was selected. */
422 static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
423
424 /* The hash table of instruction opcodes. */
425 static struct hash_control *arc_opcode_hash;
426
427 /* The hash table of register symbols. */
428 static struct hash_control *arc_reg_hash;
429
430 /* The hash table of aux register symbols. */
431 static struct hash_control *arc_aux_hash;
432
433 /* The hash table of address types. */
434 static struct hash_control *arc_addrtype_hash;
435
436 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
437 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
438 E_ARC_MACH_ARC600, EXTRA}
439 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
440 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
441 E_ARC_MACH_ARC700, EXTRA}
442 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
444 EF_ARC_CPU_ARCV2EM, EXTRA}
445 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
447 EF_ARC_CPU_ARCV2HS, EXTRA}
448 #define ARC_CPU_TYPE_NONE \
449 { 0, 0, 0, 0, 0 }
450
451 /* A table of CPU names and opcode sets. */
452 static const struct cpu_type
453 {
454 const char *name;
455 unsigned flags;
456 int mach;
457 unsigned eflags;
458 unsigned features;
459 }
460 cpu_types[] =
461 {
462 #include "elf/arc-cpu.def"
463 };
464
465 /* Information about the cpu/variant we're assembling for. */
466 static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
467
468 /* MPY option. */
469 static unsigned mpy_option = 0;
470
471 /* Use PIC. */
472 static unsigned pic_option = 0;
473
474 /* Use small data. */
475 static unsigned sda_option = 0;
476
477 /* Use TLS. */
478 static unsigned tls_option = 0;
479
480 /* Command line given features. */
481 static unsigned cl_features = 0;
482
483 /* Used by the arc_reloc_op table. Order is important. */
484 #define O_gotoff O_md1 /* @gotoff relocation. */
485 #define O_gotpc O_md2 /* @gotpc relocation. */
486 #define O_plt O_md3 /* @plt relocation. */
487 #define O_sda O_md4 /* @sda relocation. */
488 #define O_pcl O_md5 /* @pcl relocation. */
489 #define O_tlsgd O_md6 /* @tlsgd relocation. */
490 #define O_tlsie O_md7 /* @tlsie relocation. */
491 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
492 #define O_tpoff O_md9 /* @tpoff relocation. */
493 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
494 #define O_dtpoff O_md11 /* @dtpoff relocation. */
495 #define O_last O_dtpoff
496
497 /* Used to define a bracket as operand in tokens. */
498 #define O_bracket O_md32
499
500 /* Used to define a colon as an operand in tokens. */
501 #define O_colon O_md31
502
503 /* Used to define address types in nps400. */
504 #define O_addrtype O_md30
505
506 /* Dummy relocation, to be sorted out. */
507 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
508
509 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
510
511 /* A table to map the spelling of a relocation operand into an appropriate
512 bfd_reloc_code_real_type type. The table is assumed to be ordered such
513 that op-O_literal indexes into it. */
514 #define ARC_RELOC_TABLE(op) \
515 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
516 ? (abort (), 0) \
517 : (int) (op) - (int) O_gotoff) ])
518
519 #define DEF(NAME, RELOC, REQ) \
520 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
521
522 static const struct arc_reloc_op_tag
523 {
524 /* String to lookup. */
525 const char *name;
526 /* Size of the string. */
527 size_t length;
528 /* Which operator to use. */
529 operatorT op;
530 extended_bfd_reloc_code_real_type reloc;
531 /* Allows complex relocation expression like identifier@reloc +
532 const. */
533 unsigned int complex_expr : 1;
534 }
535 arc_reloc_op[] =
536 {
537 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
538 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
539 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
540 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
541 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
542 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
543 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
544 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
545 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
546 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
547 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
548 };
549
550 static const int arc_num_reloc_op
551 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
552
553 /* Structure for relaxable instruction that have to be swapped with a
554 smaller alternative instruction. */
555 struct arc_relaxable_ins
556 {
557 /* Mnemonic that should be checked. */
558 const char *mnemonic_r;
559
560 /* Operands that should be checked.
561 Indexes of operands from operand array. */
562 enum rlx_operand_type operands[6];
563
564 /* Flags that should be checked. */
565 unsigned flag_classes[5];
566
567 /* Mnemonic (smaller) alternative to be used later for relaxation. */
568 const char *mnemonic_alt;
569
570 /* Index of operand that generic relaxation has to check. */
571 unsigned opcheckidx;
572
573 /* Base subtype index used. */
574 enum arc_rlx_types subtype;
575 };
576
577 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
578 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
579 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
580 (SIZE), \
581 (NEXT) } \
582
583 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
584 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
585 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
586 (SIZE), \
587 (NEXT) } \
588
589
590 /* ARC relaxation table. */
591 const relax_typeS md_relax_table[] =
592 {
593 /* Fake entry. */
594 {0, 0, 0, 0},
595
596 /* BL_S s13 ->
597 BL s25. */
598 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
599 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
600
601 /* B_S s10 ->
602 B s25. */
603 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
604 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
605
606 /* ADD_S c,b, u3 ->
607 ADD<.f> a,b,u6 ->
608 ADD<.f> a,b,limm. */
609 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
610 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
611 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
612
613 /* LD_S a, [b, u7] ->
614 LD<zz><.x><.aa><.di> a, [b, s9] ->
615 LD<zz><.x><.aa><.di> a, [b, limm] */
616 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
617 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
618 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
619
620 /* MOV_S b, u8 ->
621 MOV<.f> b, s12 ->
622 MOV<.f> b, limm. */
623 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
624 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
625 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
626
627 /* SUB_S c, b, u3 ->
628 SUB<.f> a, b, u6 ->
629 SUB<.f> a, b, limm. */
630 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
631 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
633
634 /* MPY<.f> a, b, u6 ->
635 MPY<.f> a, b, limm. */
636 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
637 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
638
639 /* MOV<.f><.cc> b, u6 ->
640 MOV<.f><.cc> b, limm. */
641 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
642 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
643
644 /* ADD<.f><.cc> b, b, u6 ->
645 ADD<.f><.cc> b, b, limm. */
646 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
647 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
648 };
649
650 /* Order of this table's entries matters! */
651 const struct arc_relaxable_ins arc_relaxable_insns[] =
652 {
653 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
654 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
655 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
656 2, ARC_RLX_ADD_RRU6},
657 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
658 ARC_RLX_ADD_U3 },
659 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
660 ARC_RLX_ADD_U6 },
661 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
662 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
663 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
664 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
665 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
666 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
667 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
668 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
669 ARC_RLX_SUB_U3 },
670 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
671 ARC_RLX_SUB_U6 },
672 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
673 ARC_RLX_MPY_U6 },
674 };
675
676 const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
677
678 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
679 symbolS * GOT_symbol = 0;
680
681 /* Set to TRUE when we assemble instructions. */
682 static bfd_boolean assembling_insn = FALSE;
683
684 /* List with attributes set explicitly. */
685 static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
686
687 /* Functions implementation. */
688
689 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
690 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
691 are no matching entries in ARC_OPCODE_HASH. */
692
693 static const struct arc_opcode_hash_entry *
694 arc_find_opcode (const char *name)
695 {
696 const struct arc_opcode_hash_entry *entry;
697
698 entry = hash_find (arc_opcode_hash, name);
699 return entry;
700 }
701
702 /* Initialise the iterator ITER. */
703
704 static void
705 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
706 {
707 iter->index = 0;
708 iter->opcode = NULL;
709 }
710
711 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
712 calls to this function. Return NULL when all ARC_OPCODE entries have
713 been returned. */
714
715 static const struct arc_opcode *
716 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
717 struct arc_opcode_hash_entry_iterator *iter)
718 {
719 if (iter->opcode == NULL && iter->index == 0)
720 {
721 gas_assert (entry->count > 0);
722 iter->opcode = entry->opcode[iter->index];
723 }
724 else if (iter->opcode != NULL)
725 {
726 const char *old_name = iter->opcode->name;
727
728 iter->opcode++;
729 if (iter->opcode->name == NULL
730 || strcmp (old_name, iter->opcode->name) != 0)
731 {
732 iter->index++;
733 if (iter->index == entry->count)
734 iter->opcode = NULL;
735 else
736 iter->opcode = entry->opcode[iter->index];
737 }
738 }
739
740 return iter->opcode;
741 }
742
743 /* Insert an opcode into opcode hash structure. */
744
745 static void
746 arc_insert_opcode (const struct arc_opcode *opcode)
747 {
748 const char *name, *retval;
749 struct arc_opcode_hash_entry *entry;
750 name = opcode->name;
751
752 entry = hash_find (arc_opcode_hash, name);
753 if (entry == NULL)
754 {
755 entry = XNEW (struct arc_opcode_hash_entry);
756 entry->count = 0;
757 entry->opcode = NULL;
758
759 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
760 if (retval)
761 as_fatal (_("internal error: can't hash opcode '%s': %s"),
762 name, retval);
763 }
764
765 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
766 entry->count + 1);
767
768 if (entry->opcode == NULL)
769 as_fatal (_("Virtual memory exhausted"));
770
771 entry->opcode[entry->count] = opcode;
772 entry->count++;
773 }
774
775
776 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
777 value, is encoded as 'middle-endian' for a little-endian target. This
778 function is used for regular 4, 6, and 8 byte instructions as well. */
779
780 static void
781 md_number_to_chars_midend (char *buf, unsigned long long val, int n)
782 {
783 switch (n)
784 {
785 case 2:
786 md_number_to_chars (buf, val, n);
787 break;
788 case 6:
789 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
790 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
791 break;
792 case 4:
793 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
794 md_number_to_chars (buf + 2, (val & 0xffff), 2);
795 break;
796 case 8:
797 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
798 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
799 break;
800 default:
801 abort ();
802 }
803 }
804
805 /* Check if a feature is allowed for a specific CPU. */
806
807 static void
808 arc_check_feature (void)
809 {
810 unsigned i;
811
812 if (!selected_cpu.features
813 || !selected_cpu.name)
814 return;
815
816 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
817 if ((selected_cpu.features & feature_list[i].feature)
818 && !(selected_cpu.flags & feature_list[i].cpus))
819 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
820 selected_cpu.name);
821
822 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
823 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
824 as_bad(_("conflicting ISA extension attributes."));
825 }
826
827 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
828 the relevant static global variables. Parameter SEL describes where
829 this selection originated from. */
830
831 static void
832 arc_select_cpu (const char *arg, enum mach_selection_type sel)
833 {
834 int i;
835
836 /* We should only set a default if we've not made a selection from some
837 other source. */
838 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
839 || mach_selection_mode == MACH_SELECTION_NONE);
840
841 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
842 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
843 as_bad (_("Multiple .cpu directives found"));
844
845 /* Look for a matching entry in CPU_TYPES array. */
846 for (i = 0; cpu_types[i].name; ++i)
847 {
848 if (!strcasecmp (cpu_types[i].name, arg))
849 {
850 /* If a previous selection was made on the command line, then we
851 allow later selections on the command line to override earlier
852 ones. However, a selection from a '.cpu NAME' directive must
853 match the command line selection, or we give a warning. */
854 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
855 {
856 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
857 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
858 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
859 && selected_cpu.mach != cpu_types[i].mach)
860 {
861 as_warn (_("Command-line value overrides \".cpu\" directive"));
862 }
863 return;
864 }
865
866 /* Initialise static global data about selected machine type. */
867 selected_cpu.flags = cpu_types[i].flags;
868 selected_cpu.name = cpu_types[i].name;
869 selected_cpu.features = cpu_types[i].features | cl_features;
870 selected_cpu.mach = cpu_types[i].mach;
871 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
872 | cpu_types[i].eflags);
873 break;
874 }
875 }
876
877 if (!cpu_types[i].name)
878 as_fatal (_("unknown architecture: %s\n"), arg);
879
880 /* Check if set features are compatible with the chosen CPU. */
881 arc_check_feature ();
882
883 mach_selection_mode = sel;
884 }
885
886 /* Here ends all the ARCompact extension instruction assembling
887 stuff. */
888
889 static void
890 arc_extra_reloc (int r_type)
891 {
892 char *sym_name, c;
893 symbolS *sym, *lab = NULL;
894
895 if (*input_line_pointer == '@')
896 input_line_pointer++;
897 c = get_symbol_name (&sym_name);
898 sym = symbol_find_or_make (sym_name);
899 restore_line_pointer (c);
900 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
901 {
902 ++input_line_pointer;
903 char *lab_name;
904 c = get_symbol_name (&lab_name);
905 lab = symbol_find_or_make (lab_name);
906 restore_line_pointer (c);
907 }
908
909 /* These relocations exist as a mechanism for the compiler to tell the
910 linker how to patch the code if the tls model is optimised. However,
911 the relocation itself does not require any space within the assembler
912 fragment, and so we pass a size of 0.
913
914 The lines that generate these relocations look like this:
915
916 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
917
918 The '.tls_gd_ld @.tdata' is processed first and generates the
919 additional relocation, while the 'bl __tls_get_addr@plt' is processed
920 second and generates the additional branch.
921
922 It is possible that the additional relocation generated by the
923 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
924 while the 'bl __tls_get_addr@plt' will be generated as the first thing
925 in the next fragment. This will be fine; both relocations will still
926 appear to be at the same address in the generated object file.
927 However, this only works as the additional relocation is generated
928 with size of 0 bytes. */
929 fixS *fixP
930 = fix_new (frag_now, /* Which frag? */
931 frag_now_fix (), /* Where in that frag? */
932 0, /* size: 1, 2, or 4 usually. */
933 sym, /* X_add_symbol. */
934 0, /* X_add_number. */
935 FALSE, /* TRUE if PC-relative relocation. */
936 r_type /* Relocation type. */);
937 fixP->fx_subsy = lab;
938 }
939
940 static symbolS *
941 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
942 symbolS *symbolP, addressT size)
943 {
944 addressT align = 0;
945 SKIP_WHITESPACE ();
946
947 if (*input_line_pointer == ',')
948 {
949 align = parse_align (1);
950
951 if (align == (addressT) -1)
952 return NULL;
953 }
954 else
955 {
956 if (size >= 8)
957 align = 3;
958 else if (size >= 4)
959 align = 2;
960 else if (size >= 2)
961 align = 1;
962 else
963 align = 0;
964 }
965
966 bss_alloc (symbolP, size, align);
967 S_CLEAR_EXTERNAL (symbolP);
968
969 return symbolP;
970 }
971
972 static void
973 arc_lcomm (int ignore)
974 {
975 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
976
977 if (symbolP)
978 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
979 }
980
981 /* Select the cpu we're assembling for. */
982
983 static void
984 arc_option (int ignore ATTRIBUTE_UNUSED)
985 {
986 char c;
987 char *cpu;
988 const char *cpu_name;
989
990 c = get_symbol_name (&cpu);
991
992 cpu_name = cpu;
993 if ((!strcmp ("ARC600", cpu))
994 || (!strcmp ("ARC601", cpu))
995 || (!strcmp ("A6", cpu)))
996 cpu_name = "arc600";
997 else if ((!strcmp ("ARC700", cpu))
998 || (!strcmp ("A7", cpu)))
999 cpu_name = "arc700";
1000 else if (!strcmp ("EM", cpu))
1001 cpu_name = "arcem";
1002 else if (!strcmp ("HS", cpu))
1003 cpu_name = "archs";
1004 else if (!strcmp ("NPS400", cpu))
1005 cpu_name = "nps400";
1006
1007 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
1008
1009 restore_line_pointer (c);
1010 demand_empty_rest_of_line ();
1011 }
1012
1013 /* Smartly print an expression. */
1014
1015 static void
1016 debug_exp (expressionS *t)
1017 {
1018 const char *name ATTRIBUTE_UNUSED;
1019 const char *namemd ATTRIBUTE_UNUSED;
1020
1021 pr_debug ("debug_exp: ");
1022
1023 switch (t->X_op)
1024 {
1025 default: name = "unknown"; break;
1026 case O_illegal: name = "O_illegal"; break;
1027 case O_absent: name = "O_absent"; break;
1028 case O_constant: name = "O_constant"; break;
1029 case O_symbol: name = "O_symbol"; break;
1030 case O_symbol_rva: name = "O_symbol_rva"; break;
1031 case O_register: name = "O_register"; break;
1032 case O_big: name = "O_big"; break;
1033 case O_uminus: name = "O_uminus"; break;
1034 case O_bit_not: name = "O_bit_not"; break;
1035 case O_logical_not: name = "O_logical_not"; break;
1036 case O_multiply: name = "O_multiply"; break;
1037 case O_divide: name = "O_divide"; break;
1038 case O_modulus: name = "O_modulus"; break;
1039 case O_left_shift: name = "O_left_shift"; break;
1040 case O_right_shift: name = "O_right_shift"; break;
1041 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1042 case O_bit_or_not: name = "O_bit_or_not"; break;
1043 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1044 case O_bit_and: name = "O_bit_and"; break;
1045 case O_add: name = "O_add"; break;
1046 case O_subtract: name = "O_subtract"; break;
1047 case O_eq: name = "O_eq"; break;
1048 case O_ne: name = "O_ne"; break;
1049 case O_lt: name = "O_lt"; break;
1050 case O_le: name = "O_le"; break;
1051 case O_ge: name = "O_ge"; break;
1052 case O_gt: name = "O_gt"; break;
1053 case O_logical_and: name = "O_logical_and"; break;
1054 case O_logical_or: name = "O_logical_or"; break;
1055 case O_index: name = "O_index"; break;
1056 case O_bracket: name = "O_bracket"; break;
1057 case O_colon: name = "O_colon"; break;
1058 case O_addrtype: name = "O_addrtype"; break;
1059 }
1060
1061 switch (t->X_md)
1062 {
1063 default: namemd = "unknown"; break;
1064 case O_gotoff: namemd = "O_gotoff"; break;
1065 case O_gotpc: namemd = "O_gotpc"; break;
1066 case O_plt: namemd = "O_plt"; break;
1067 case O_sda: namemd = "O_sda"; break;
1068 case O_pcl: namemd = "O_pcl"; break;
1069 case O_tlsgd: namemd = "O_tlsgd"; break;
1070 case O_tlsie: namemd = "O_tlsie"; break;
1071 case O_tpoff9: namemd = "O_tpoff9"; break;
1072 case O_tpoff: namemd = "O_tpoff"; break;
1073 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1074 case O_dtpoff: namemd = "O_dtpoff"; break;
1075 }
1076
1077 pr_debug ("%s (%s, %s, %d, %s)", name,
1078 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1079 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1080 (int) t->X_add_number,
1081 (t->X_md) ? namemd : "--");
1082 pr_debug ("\n");
1083 fflush (stderr);
1084 }
1085
1086 /* Parse the arguments to an opcode. */
1087
1088 static int
1089 tokenize_arguments (char *str,
1090 expressionS *tok,
1091 int ntok)
1092 {
1093 char *old_input_line_pointer;
1094 bfd_boolean saw_comma = FALSE;
1095 bfd_boolean saw_arg = FALSE;
1096 int brk_lvl = 0;
1097 int num_args = 0;
1098 int i;
1099 size_t len;
1100 const struct arc_reloc_op_tag *r;
1101 expressionS tmpE;
1102 char *reloc_name, c;
1103
1104 memset (tok, 0, sizeof (*tok) * ntok);
1105
1106 /* Save and restore input_line_pointer around this function. */
1107 old_input_line_pointer = input_line_pointer;
1108 input_line_pointer = str;
1109
1110 while (*input_line_pointer)
1111 {
1112 SKIP_WHITESPACE ();
1113 switch (*input_line_pointer)
1114 {
1115 case '\0':
1116 goto fini;
1117
1118 case ',':
1119 input_line_pointer++;
1120 if (saw_comma || !saw_arg)
1121 goto err;
1122 saw_comma = TRUE;
1123 break;
1124
1125 case '}':
1126 case ']':
1127 ++input_line_pointer;
1128 --brk_lvl;
1129 if (!saw_arg || num_args == ntok)
1130 goto err;
1131 tok->X_op = O_bracket;
1132 ++tok;
1133 ++num_args;
1134 break;
1135
1136 case '{':
1137 case '[':
1138 input_line_pointer++;
1139 if (brk_lvl || num_args == ntok)
1140 goto err;
1141 ++brk_lvl;
1142 tok->X_op = O_bracket;
1143 ++tok;
1144 ++num_args;
1145 break;
1146
1147 case ':':
1148 input_line_pointer++;
1149 if (!saw_arg || num_args == ntok)
1150 goto err;
1151 tok->X_op = O_colon;
1152 saw_arg = FALSE;
1153 ++tok;
1154 ++num_args;
1155 break;
1156
1157 case '@':
1158 /* We have labels, function names and relocations, all
1159 starting with @ symbol. Sort them out. */
1160 if ((saw_arg && !saw_comma) || num_args == ntok)
1161 goto err;
1162
1163 /* Parse @label. */
1164 tok->X_op = O_symbol;
1165 tok->X_md = O_absent;
1166 expression (tok);
1167 if (*input_line_pointer != '@')
1168 goto normalsymbol; /* This is not a relocation. */
1169
1170 relocationsym:
1171
1172 /* A relocation operand has the following form
1173 @identifier@relocation_type. The identifier is already
1174 in tok! */
1175 if (tok->X_op != O_symbol)
1176 {
1177 as_bad (_("No valid label relocation operand"));
1178 goto err;
1179 }
1180
1181 /* Parse @relocation_type. */
1182 input_line_pointer++;
1183 c = get_symbol_name (&reloc_name);
1184 len = input_line_pointer - reloc_name;
1185 if (len == 0)
1186 {
1187 as_bad (_("No relocation operand"));
1188 goto err;
1189 }
1190
1191 /* Go through known relocation and try to find a match. */
1192 r = &arc_reloc_op[0];
1193 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1194 if (len == r->length
1195 && memcmp (reloc_name, r->name, len) == 0)
1196 break;
1197 if (i < 0)
1198 {
1199 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1200 goto err;
1201 }
1202
1203 *input_line_pointer = c;
1204 SKIP_WHITESPACE_AFTER_NAME ();
1205 /* Extra check for TLS: base. */
1206 if (*input_line_pointer == '@')
1207 {
1208 symbolS *base;
1209 if (tok->X_op_symbol != NULL
1210 || tok->X_op != O_symbol)
1211 {
1212 as_bad (_("Unable to parse TLS base: %s"),
1213 input_line_pointer);
1214 goto err;
1215 }
1216 input_line_pointer++;
1217 char *sym_name;
1218 c = get_symbol_name (&sym_name);
1219 base = symbol_find_or_make (sym_name);
1220 tok->X_op = O_subtract;
1221 tok->X_op_symbol = base;
1222 restore_line_pointer (c);
1223 tmpE.X_add_number = 0;
1224 }
1225 if ((*input_line_pointer != '+')
1226 && (*input_line_pointer != '-'))
1227 {
1228 tmpE.X_add_number = 0;
1229 }
1230 else
1231 {
1232 /* Parse the constant of a complex relocation expression
1233 like @identifier@reloc +/- const. */
1234 if (! r->complex_expr)
1235 {
1236 as_bad (_("@%s is not a complex relocation."), r->name);
1237 goto err;
1238 }
1239 expression (&tmpE);
1240 if (tmpE.X_op != O_constant)
1241 {
1242 as_bad (_("Bad expression: @%s + %s."),
1243 r->name, input_line_pointer);
1244 goto err;
1245 }
1246 }
1247
1248 tok->X_md = r->op;
1249 tok->X_add_number = tmpE.X_add_number;
1250
1251 debug_exp (tok);
1252
1253 saw_comma = FALSE;
1254 saw_arg = TRUE;
1255 tok++;
1256 num_args++;
1257 break;
1258
1259 case '%':
1260 /* Can be a register. */
1261 ++input_line_pointer;
1262 /* Fall through. */
1263 default:
1264
1265 if ((saw_arg && !saw_comma) || num_args == ntok)
1266 goto err;
1267
1268 tok->X_op = O_absent;
1269 tok->X_md = O_absent;
1270 expression (tok);
1271
1272 /* Legacy: There are cases when we have
1273 identifier@relocation_type, if it is the case parse the
1274 relocation type as well. */
1275 if (*input_line_pointer == '@')
1276 goto relocationsym;
1277
1278 normalsymbol:
1279 debug_exp (tok);
1280
1281 if (tok->X_op == O_illegal
1282 || tok->X_op == O_absent
1283 || num_args == ntok)
1284 goto err;
1285
1286 saw_comma = FALSE;
1287 saw_arg = TRUE;
1288 tok++;
1289 num_args++;
1290 break;
1291 }
1292 }
1293
1294 fini:
1295 if (saw_comma || brk_lvl)
1296 goto err;
1297 input_line_pointer = old_input_line_pointer;
1298
1299 return num_args;
1300
1301 err:
1302 if (brk_lvl)
1303 as_bad (_("Brackets in operand field incorrect"));
1304 else if (saw_comma)
1305 as_bad (_("extra comma"));
1306 else if (!saw_arg)
1307 as_bad (_("missing argument"));
1308 else
1309 as_bad (_("missing comma or colon"));
1310 input_line_pointer = old_input_line_pointer;
1311 return -1;
1312 }
1313
1314 /* Parse the flags to a structure. */
1315
1316 static int
1317 tokenize_flags (const char *str,
1318 struct arc_flags flags[],
1319 int nflg)
1320 {
1321 char *old_input_line_pointer;
1322 bfd_boolean saw_flg = FALSE;
1323 bfd_boolean saw_dot = FALSE;
1324 int num_flags = 0;
1325 size_t flgnamelen;
1326
1327 memset (flags, 0, sizeof (*flags) * nflg);
1328
1329 /* Save and restore input_line_pointer around this function. */
1330 old_input_line_pointer = input_line_pointer;
1331 input_line_pointer = (char *) str;
1332
1333 while (*input_line_pointer)
1334 {
1335 switch (*input_line_pointer)
1336 {
1337 case ' ':
1338 case '\0':
1339 goto fini;
1340
1341 case '.':
1342 input_line_pointer++;
1343 if (saw_dot)
1344 goto err;
1345 saw_dot = TRUE;
1346 saw_flg = FALSE;
1347 break;
1348
1349 default:
1350 if (saw_flg && !saw_dot)
1351 goto err;
1352
1353 if (num_flags >= nflg)
1354 goto err;
1355
1356 flgnamelen = strspn (input_line_pointer,
1357 "abcdefghijklmnopqrstuvwxyz0123456789");
1358 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
1359 goto err;
1360
1361 memcpy (flags->name, input_line_pointer, flgnamelen);
1362
1363 input_line_pointer += flgnamelen;
1364 flags++;
1365 saw_dot = FALSE;
1366 saw_flg = TRUE;
1367 num_flags++;
1368 break;
1369 }
1370 }
1371
1372 fini:
1373 input_line_pointer = old_input_line_pointer;
1374 return num_flags;
1375
1376 err:
1377 if (saw_dot)
1378 as_bad (_("extra dot"));
1379 else if (!saw_flg)
1380 as_bad (_("unrecognized flag"));
1381 else
1382 as_bad (_("failed to parse flags"));
1383 input_line_pointer = old_input_line_pointer;
1384 return -1;
1385 }
1386
1387 /* Apply the fixups in order. */
1388
1389 static void
1390 apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
1391 {
1392 int i;
1393
1394 for (i = 0; i < insn->nfixups; i++)
1395 {
1396 struct arc_fixup *fixup = &insn->fixups[i];
1397 int size, pcrel, offset = 0;
1398
1399 /* FIXME! the reloc size is wrong in the BFD file.
1400 When it is fixed please delete me. */
1401 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
1402
1403 if (fixup->islong)
1404 offset = insn->len;
1405
1406 /* Some fixups are only used internally, thus no howto. */
1407 if ((int) fixup->reloc == 0)
1408 as_fatal (_("Unhandled reloc type"));
1409
1410 if ((int) fixup->reloc < 0)
1411 {
1412 /* FIXME! the reloc size is wrong in the BFD file.
1413 When it is fixed please enable me.
1414 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1415 pcrel = fixup->pcrel;
1416 }
1417 else
1418 {
1419 reloc_howto_type *reloc_howto =
1420 bfd_reloc_type_lookup (stdoutput,
1421 (bfd_reloc_code_real_type) fixup->reloc);
1422 gas_assert (reloc_howto);
1423
1424 /* FIXME! the reloc size is wrong in the BFD file.
1425 When it is fixed please enable me.
1426 size = bfd_get_reloc_size (reloc_howto); */
1427 pcrel = reloc_howto->pc_relative;
1428 }
1429
1430 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1431 offset %d + %d\n",
1432 fragP->fr_file, fragP->fr_line,
1433 (fixup->reloc < 0) ? "Internal" :
1434 bfd_get_reloc_code_name (fixup->reloc),
1435 pcrel ? "Y" : "N",
1436 size, fix, offset);
1437 fix_new_exp (fragP, fix + offset,
1438 size, &fixup->exp, pcrel, fixup->reloc);
1439
1440 /* Check for ZOLs, and update symbol info if any. */
1441 if (LP_INSN (insn->insn))
1442 {
1443 gas_assert (fixup->exp.X_add_symbol);
1444 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
1445 }
1446 }
1447 }
1448
1449 /* Actually output an instruction with its fixup. */
1450
1451 static void
1452 emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
1453 {
1454 char *f = where;
1455 size_t total_len;
1456
1457 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1458 pr_debug ("\tLength : 0x%d\n", insn->len);
1459 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
1460
1461 /* Write out the instruction. */
1462 total_len = insn->len + (insn->has_limm ? 4 : 0);
1463 if (!relax)
1464 f = frag_more (total_len);
1465
1466 md_number_to_chars_midend(f, insn->insn, insn->len);
1467
1468 if (insn->has_limm)
1469 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1470 dwarf2_emit_insn (total_len);
1471
1472 if (!relax)
1473 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1474 }
1475
1476 static void
1477 emit_insn1 (struct arc_insn *insn)
1478 {
1479 /* How frag_var's args are currently configured:
1480 - rs_machine_dependent, to dictate it's a relaxation frag.
1481 - FRAG_MAX_GROWTH, maximum size of instruction
1482 - 0, variable size that might grow...unused by generic relaxation.
1483 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1484 - s, opand expression.
1485 - 0, offset but it's unused.
1486 - 0, opcode but it's unused. */
1487 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1488 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1489
1490 if (frag_room () < FRAG_MAX_GROWTH)
1491 {
1492 /* Handle differently when frag literal memory is exhausted.
1493 This is used because when there's not enough memory left in
1494 the current frag, a new frag is created and the information
1495 we put into frag_now->tc_frag_data is disregarded. */
1496
1497 struct arc_relax_type relax_info_copy;
1498 relax_substateT subtype = frag_now->fr_subtype;
1499
1500 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1501 sizeof (struct arc_relax_type));
1502
1503 frag_wane (frag_now);
1504 frag_grow (FRAG_MAX_GROWTH);
1505
1506 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1507 sizeof (struct arc_relax_type));
1508
1509 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1510 subtype, s, 0, 0);
1511 }
1512 else
1513 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1514 frag_now->fr_subtype, s, 0, 0);
1515 }
1516
1517 static void
1518 emit_insn (struct arc_insn *insn)
1519 {
1520 if (insn->relax)
1521 emit_insn1 (insn);
1522 else
1523 emit_insn0 (insn, NULL, FALSE);
1524 }
1525
1526 /* Check whether a symbol involves a register. */
1527
1528 static bfd_boolean
1529 contains_register (symbolS *sym)
1530 {
1531 if (sym)
1532 {
1533 expressionS *ex = symbol_get_value_expression (sym);
1534
1535 return ((O_register == ex->X_op)
1536 && !contains_register (ex->X_add_symbol)
1537 && !contains_register (ex->X_op_symbol));
1538 }
1539
1540 return FALSE;
1541 }
1542
1543 /* Returns the register number within a symbol. */
1544
1545 static int
1546 get_register (symbolS *sym)
1547 {
1548 if (!contains_register (sym))
1549 return -1;
1550
1551 expressionS *ex = symbol_get_value_expression (sym);
1552 return regno (ex->X_add_number);
1553 }
1554
1555 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1556 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1557
1558 static bfd_boolean
1559 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1560 {
1561 if (!reloc)
1562 return FALSE;
1563
1564 switch (reloc)
1565 {
1566 case BFD_RELOC_ARC_SDA_LDST:
1567 case BFD_RELOC_ARC_SDA_LDST1:
1568 case BFD_RELOC_ARC_SDA_LDST2:
1569 case BFD_RELOC_ARC_SDA16_LD:
1570 case BFD_RELOC_ARC_SDA16_LD1:
1571 case BFD_RELOC_ARC_SDA16_LD2:
1572 case BFD_RELOC_ARC_SDA16_ST2:
1573 case BFD_RELOC_ARC_SDA32_ME:
1574 return FALSE;
1575 default:
1576 return TRUE;
1577 }
1578 }
1579
1580 /* Allocates a tok entry. */
1581
1582 static int
1583 allocate_tok (expressionS *tok, int ntok, int cidx)
1584 {
1585 if (ntok > MAX_INSN_ARGS - 2)
1586 return 0; /* No space left. */
1587
1588 if (cidx > ntok)
1589 return 0; /* Incorrect args. */
1590
1591 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
1592
1593 if (cidx == ntok)
1594 return 1; /* Success. */
1595 return allocate_tok (tok, ntok - 1, cidx);
1596 }
1597
1598 /* Check if an particular ARC feature is enabled. */
1599
1600 static bfd_boolean
1601 check_cpu_feature (insn_subclass_t sc)
1602 {
1603 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
1604 return FALSE;
1605
1606 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
1607 return FALSE;
1608
1609 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
1610 return FALSE;
1611
1612 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
1613 return FALSE;
1614
1615 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
1616 return FALSE;
1617
1618 return TRUE;
1619 }
1620
1621 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1622 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1623 array and returns TRUE if the flag operands all match, otherwise,
1624 returns FALSE, in which case the FIRST_PFLAG array may have been
1625 modified. */
1626
1627 static bfd_boolean
1628 parse_opcode_flags (const struct arc_opcode *opcode,
1629 int nflgs,
1630 struct arc_flags *first_pflag)
1631 {
1632 int lnflg, i;
1633 const unsigned char *flgidx;
1634
1635 lnflg = nflgs;
1636 for (i = 0; i < nflgs; i++)
1637 first_pflag[i].flgp = NULL;
1638
1639 /* Check the flags. Iterate over the valid flag classes. */
1640 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1641 {
1642 /* Get a valid flag class. */
1643 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1644 const unsigned *flgopridx;
1645 int cl_matches = 0;
1646 struct arc_flags *pflag = NULL;
1647
1648 /* Check if opcode has implicit flag classes. */
1649 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1650 continue;
1651
1652 /* Check for extension conditional codes. */
1653 if (ext_condcode.arc_ext_condcode
1654 && cl_flags->flag_class & F_CLASS_EXTEND)
1655 {
1656 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1657 while (pf->name)
1658 {
1659 pflag = first_pflag;
1660 for (i = 0; i < nflgs; i++, pflag++)
1661 {
1662 if (!strcmp (pf->name, pflag->name))
1663 {
1664 if (pflag->flgp != NULL)
1665 return FALSE;
1666 /* Found it. */
1667 cl_matches++;
1668 pflag->flgp = pf;
1669 lnflg--;
1670 break;
1671 }
1672 }
1673 pf++;
1674 }
1675 }
1676
1677 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1678 {
1679 const struct arc_flag_operand *flg_operand;
1680
1681 pflag = first_pflag;
1682 flg_operand = &arc_flag_operands[*flgopridx];
1683 for (i = 0; i < nflgs; i++, pflag++)
1684 {
1685 /* Match against the parsed flags. */
1686 if (!strcmp (flg_operand->name, pflag->name))
1687 {
1688 if (pflag->flgp != NULL)
1689 return FALSE;
1690 cl_matches++;
1691 pflag->flgp = flg_operand;
1692 lnflg--;
1693 break; /* goto next flag class and parsed flag. */
1694 }
1695 }
1696 }
1697
1698 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1699 return FALSE;
1700 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1701 return FALSE;
1702 }
1703
1704 /* Did I check all the parsed flags? */
1705 return lnflg ? FALSE : TRUE;
1706 }
1707
1708
1709 /* Search forward through all variants of an opcode looking for a
1710 syntax match. */
1711
1712 static const struct arc_opcode *
1713 find_opcode_match (const struct arc_opcode_hash_entry *entry,
1714 expressionS *tok,
1715 int *pntok,
1716 struct arc_flags *first_pflag,
1717 int nflgs,
1718 int *pcpumatch,
1719 const char **errmsg)
1720 {
1721 const struct arc_opcode *opcode;
1722 struct arc_opcode_hash_entry_iterator iter;
1723 int ntok = *pntok;
1724 int got_cpu_match = 0;
1725 expressionS bktok[MAX_INSN_ARGS];
1726 int bkntok;
1727 expressionS emptyE;
1728
1729 arc_opcode_hash_entry_iterator_init (&iter);
1730 memset (&emptyE, 0, sizeof (emptyE));
1731 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1732 bkntok = ntok;
1733
1734 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1735 opcode != NULL;
1736 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
1737 {
1738 const unsigned char *opidx;
1739 int tokidx = 0;
1740 const expressionS *t = &emptyE;
1741
1742 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1743 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
1744
1745 /* Don't match opcodes that don't exist on this
1746 architecture. */
1747 if (!(opcode->cpu & selected_cpu.flags))
1748 goto match_failed;
1749
1750 if (!check_cpu_feature (opcode->subclass))
1751 goto match_failed;
1752
1753 got_cpu_match = 1;
1754 pr_debug ("cpu ");
1755
1756 /* Check the operands. */
1757 for (opidx = opcode->operands; *opidx; ++opidx)
1758 {
1759 const struct arc_operand *operand = &arc_operands[*opidx];
1760
1761 /* Only take input from real operands. */
1762 if (ARC_OPERAND_IS_FAKE (operand))
1763 continue;
1764
1765 /* When we expect input, make sure we have it. */
1766 if (tokidx >= ntok)
1767 goto match_failed;
1768
1769 /* Match operand type with expression type. */
1770 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1771 {
1772 case ARC_OPERAND_ADDRTYPE:
1773 {
1774 *errmsg = NULL;
1775
1776 /* Check to be an address type. */
1777 if (tok[tokidx].X_op != O_addrtype)
1778 goto match_failed;
1779
1780 /* All address type operands need to have an insert
1781 method in order to check that we have the correct
1782 address type. */
1783 gas_assert (operand->insert != NULL);
1784 (*operand->insert) (0, tok[tokidx].X_add_number,
1785 errmsg);
1786 if (*errmsg != NULL)
1787 goto match_failed;
1788 }
1789 break;
1790
1791 case ARC_OPERAND_IR:
1792 /* Check to be a register. */
1793 if ((tok[tokidx].X_op != O_register
1794 || !is_ir_num (tok[tokidx].X_add_number))
1795 && !(operand->flags & ARC_OPERAND_IGNORE))
1796 goto match_failed;
1797
1798 /* If expect duplicate, make sure it is duplicate. */
1799 if (operand->flags & ARC_OPERAND_DUPLICATE)
1800 {
1801 /* Check for duplicate. */
1802 if (t->X_op != O_register
1803 || !is_ir_num (t->X_add_number)
1804 || (regno (t->X_add_number) !=
1805 regno (tok[tokidx].X_add_number)))
1806 goto match_failed;
1807 }
1808
1809 /* Special handling? */
1810 if (operand->insert)
1811 {
1812 *errmsg = NULL;
1813 (*operand->insert)(0,
1814 regno (tok[tokidx].X_add_number),
1815 errmsg);
1816 if (*errmsg)
1817 {
1818 if (operand->flags & ARC_OPERAND_IGNORE)
1819 {
1820 /* Missing argument, create one. */
1821 if (!allocate_tok (tok, ntok - 1, tokidx))
1822 goto match_failed;
1823
1824 tok[tokidx].X_op = O_absent;
1825 ++ntok;
1826 }
1827 else
1828 goto match_failed;
1829 }
1830 }
1831
1832 t = &tok[tokidx];
1833 break;
1834
1835 case ARC_OPERAND_BRAKET:
1836 /* Check if bracket is also in opcode table as
1837 operand. */
1838 if (tok[tokidx].X_op != O_bracket)
1839 goto match_failed;
1840 break;
1841
1842 case ARC_OPERAND_COLON:
1843 /* Check if colon is also in opcode table as operand. */
1844 if (tok[tokidx].X_op != O_colon)
1845 goto match_failed;
1846 break;
1847
1848 case ARC_OPERAND_LIMM:
1849 case ARC_OPERAND_SIGNED:
1850 case ARC_OPERAND_UNSIGNED:
1851 switch (tok[tokidx].X_op)
1852 {
1853 case O_illegal:
1854 case O_absent:
1855 case O_register:
1856 goto match_failed;
1857
1858 case O_bracket:
1859 /* Got an (too) early bracket, check if it is an
1860 ignored operand. N.B. This procedure works only
1861 when bracket is the last operand! */
1862 if (!(operand->flags & ARC_OPERAND_IGNORE))
1863 goto match_failed;
1864 /* Insert the missing operand. */
1865 if (!allocate_tok (tok, ntok - 1, tokidx))
1866 goto match_failed;
1867
1868 tok[tokidx].X_op = O_absent;
1869 ++ntok;
1870 break;
1871
1872 case O_symbol:
1873 {
1874 const char *p;
1875 const struct arc_aux_reg *auxr;
1876
1877 if (opcode->insn_class != AUXREG)
1878 goto de_fault;
1879 p = S_GET_NAME (tok[tokidx].X_add_symbol);
1880
1881 auxr = hash_find (arc_aux_hash, p);
1882 if (auxr)
1883 {
1884 /* We modify the token array here, safe in the
1885 knowledge, that if this was the wrong
1886 choice then the original contents will be
1887 restored from BKTOK. */
1888 tok[tokidx].X_op = O_constant;
1889 tok[tokidx].X_add_number = auxr->address;
1890 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1891 }
1892
1893 if (tok[tokidx].X_op != O_constant)
1894 goto de_fault;
1895 }
1896 /* Fall through. */
1897 case O_constant:
1898 /* Check the range. */
1899 if (operand->bits != 32
1900 && !(operand->flags & ARC_OPERAND_NCHK))
1901 {
1902 offsetT min, max, val;
1903 val = tok[tokidx].X_add_number;
1904
1905 if (operand->flags & ARC_OPERAND_SIGNED)
1906 {
1907 max = (1 << (operand->bits - 1)) - 1;
1908 min = -(1 << (operand->bits - 1));
1909 }
1910 else
1911 {
1912 max = (1 << operand->bits) - 1;
1913 min = 0;
1914 }
1915
1916 if (val < min || val > max)
1917 goto match_failed;
1918
1919 /* Check alignments. */
1920 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1921 && (val & 0x03))
1922 goto match_failed;
1923
1924 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1925 && (val & 0x01))
1926 goto match_failed;
1927 }
1928 else if (operand->flags & ARC_OPERAND_NCHK)
1929 {
1930 if (operand->insert)
1931 {
1932 *errmsg = NULL;
1933 (*operand->insert)(0,
1934 tok[tokidx].X_add_number,
1935 errmsg);
1936 if (*errmsg)
1937 goto match_failed;
1938 }
1939 else if (!(operand->flags & ARC_OPERAND_IGNORE))
1940 goto match_failed;
1941 }
1942 break;
1943
1944 case O_subtract:
1945 /* Check if it is register range. */
1946 if ((tok[tokidx].X_add_number == 0)
1947 && contains_register (tok[tokidx].X_add_symbol)
1948 && contains_register (tok[tokidx].X_op_symbol))
1949 {
1950 int regs;
1951
1952 regs = get_register (tok[tokidx].X_add_symbol);
1953 regs <<= 16;
1954 regs |= get_register (tok[tokidx].X_op_symbol);
1955 if (operand->insert)
1956 {
1957 *errmsg = NULL;
1958 (*operand->insert)(0,
1959 regs,
1960 errmsg);
1961 if (*errmsg)
1962 goto match_failed;
1963 }
1964 else
1965 goto match_failed;
1966 break;
1967 }
1968 /* Fall through. */
1969 default:
1970 de_fault:
1971 if (operand->default_reloc == 0)
1972 goto match_failed; /* The operand needs relocation. */
1973
1974 /* Relocs requiring long immediate. FIXME! make it
1975 generic and move it to a function. */
1976 switch (tok[tokidx].X_md)
1977 {
1978 case O_gotoff:
1979 case O_gotpc:
1980 case O_pcl:
1981 case O_tpoff:
1982 case O_dtpoff:
1983 case O_tlsgd:
1984 case O_tlsie:
1985 if (!(operand->flags & ARC_OPERAND_LIMM))
1986 goto match_failed;
1987 /* Fall through. */
1988 case O_absent:
1989 if (!generic_reloc_p (operand->default_reloc))
1990 goto match_failed;
1991 break;
1992 default:
1993 break;
1994 }
1995 break;
1996 }
1997 /* If expect duplicate, make sure it is duplicate. */
1998 if (operand->flags & ARC_OPERAND_DUPLICATE)
1999 {
2000 if (t->X_op == O_illegal
2001 || t->X_op == O_absent
2002 || t->X_op == O_register
2003 || (t->X_add_number != tok[tokidx].X_add_number))
2004 goto match_failed;
2005 }
2006 t = &tok[tokidx];
2007 break;
2008
2009 default:
2010 /* Everything else should have been fake. */
2011 abort ();
2012 }
2013
2014 ++tokidx;
2015 }
2016 pr_debug ("opr ");
2017
2018 /* Setup ready for flag parsing. */
2019 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
2020 goto match_failed;
2021
2022 pr_debug ("flg");
2023 /* Possible match -- did we use all of our input? */
2024 if (tokidx == ntok)
2025 {
2026 *pntok = ntok;
2027 pr_debug ("\n");
2028 return opcode;
2029 }
2030
2031 match_failed:;
2032 pr_debug ("\n");
2033 /* Restore the original parameters. */
2034 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2035 ntok = bkntok;
2036 }
2037
2038 if (*pcpumatch)
2039 *pcpumatch = got_cpu_match;
2040
2041 return NULL;
2042 }
2043
2044 /* Swap operand tokens. */
2045
2046 static void
2047 swap_operand (expressionS *operand_array,
2048 unsigned source,
2049 unsigned destination)
2050 {
2051 expressionS cpy_operand;
2052 expressionS *src_operand;
2053 expressionS *dst_operand;
2054 size_t size;
2055
2056 if (source == destination)
2057 return;
2058
2059 src_operand = &operand_array[source];
2060 dst_operand = &operand_array[destination];
2061 size = sizeof (expressionS);
2062
2063 /* Make copy of operand to swap with and swap. */
2064 memcpy (&cpy_operand, dst_operand, size);
2065 memcpy (dst_operand, src_operand, size);
2066 memcpy (src_operand, &cpy_operand, size);
2067 }
2068
2069 /* Check if *op matches *tok type.
2070 Returns FALSE if they don't match, TRUE if they match. */
2071
2072 static bfd_boolean
2073 pseudo_operand_match (const expressionS *tok,
2074 const struct arc_operand_operation *op)
2075 {
2076 offsetT min, max, val;
2077 bfd_boolean ret;
2078 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2079
2080 ret = FALSE;
2081 switch (tok->X_op)
2082 {
2083 case O_constant:
2084 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2085 ret = 1;
2086 else if (!(operand_real->flags & ARC_OPERAND_IR))
2087 {
2088 val = tok->X_add_number + op->count;
2089 if (operand_real->flags & ARC_OPERAND_SIGNED)
2090 {
2091 max = (1 << (operand_real->bits - 1)) - 1;
2092 min = -(1 << (operand_real->bits - 1));
2093 }
2094 else
2095 {
2096 max = (1 << operand_real->bits) - 1;
2097 min = 0;
2098 }
2099 if (min <= val && val <= max)
2100 ret = TRUE;
2101 }
2102 break;
2103
2104 case O_symbol:
2105 /* Handle all symbols as long immediates or signed 9. */
2106 if (operand_real->flags & ARC_OPERAND_LIMM
2107 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2108 && operand_real->bits == 9))
2109 ret = TRUE;
2110 break;
2111
2112 case O_register:
2113 if (operand_real->flags & ARC_OPERAND_IR)
2114 ret = TRUE;
2115 break;
2116
2117 case O_bracket:
2118 if (operand_real->flags & ARC_OPERAND_BRAKET)
2119 ret = TRUE;
2120 break;
2121
2122 default:
2123 /* Unknown. */
2124 break;
2125 }
2126 return ret;
2127 }
2128
2129 /* Find pseudo instruction in array. */
2130
2131 static const struct arc_pseudo_insn *
2132 find_pseudo_insn (const char *opname,
2133 int ntok,
2134 const expressionS *tok)
2135 {
2136 const struct arc_pseudo_insn *pseudo_insn = NULL;
2137 const struct arc_operand_operation *op;
2138 unsigned int i;
2139 int j;
2140
2141 for (i = 0; i < arc_num_pseudo_insn; ++i)
2142 {
2143 pseudo_insn = &arc_pseudo_insns[i];
2144 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2145 {
2146 op = pseudo_insn->operand;
2147 for (j = 0; j < ntok; ++j)
2148 if (!pseudo_operand_match (&tok[j], &op[j]))
2149 break;
2150
2151 /* Found the right instruction. */
2152 if (j == ntok)
2153 return pseudo_insn;
2154 }
2155 }
2156 return NULL;
2157 }
2158
2159 /* Assumes the expressionS *tok is of sufficient size. */
2160
2161 static const struct arc_opcode_hash_entry *
2162 find_special_case_pseudo (const char *opname,
2163 int *ntok,
2164 expressionS *tok,
2165 int *nflgs,
2166 struct arc_flags *pflags)
2167 {
2168 const struct arc_pseudo_insn *pseudo_insn = NULL;
2169 const struct arc_operand_operation *operand_pseudo;
2170 const struct arc_operand *operand_real;
2171 unsigned i;
2172 char construct_operand[MAX_CONSTR_STR];
2173
2174 /* Find whether opname is in pseudo instruction array. */
2175 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2176
2177 if (pseudo_insn == NULL)
2178 return NULL;
2179
2180 /* Handle flag, Limited to one flag at the moment. */
2181 if (pseudo_insn->flag_r != NULL)
2182 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2183 MAX_INSN_FLGS - *nflgs);
2184
2185 /* Handle operand operations. */
2186 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2187 {
2188 operand_pseudo = &pseudo_insn->operand[i];
2189 operand_real = &arc_operands[operand_pseudo->operand_idx];
2190
2191 if (operand_real->flags & ARC_OPERAND_BRAKET
2192 && !operand_pseudo->needs_insert)
2193 continue;
2194
2195 /* Has to be inserted (i.e. this token does not exist yet). */
2196 if (operand_pseudo->needs_insert)
2197 {
2198 if (operand_real->flags & ARC_OPERAND_BRAKET)
2199 {
2200 tok[i].X_op = O_bracket;
2201 ++(*ntok);
2202 continue;
2203 }
2204
2205 /* Check if operand is a register or constant and handle it
2206 by type. */
2207 if (operand_real->flags & ARC_OPERAND_IR)
2208 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2209 operand_pseudo->count);
2210 else
2211 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2212 operand_pseudo->count);
2213
2214 tokenize_arguments (construct_operand, &tok[i], 1);
2215 ++(*ntok);
2216 }
2217
2218 else if (operand_pseudo->count)
2219 {
2220 /* Operand number has to be adjusted accordingly (by operand
2221 type). */
2222 switch (tok[i].X_op)
2223 {
2224 case O_constant:
2225 tok[i].X_add_number += operand_pseudo->count;
2226 break;
2227
2228 case O_symbol:
2229 break;
2230
2231 default:
2232 /* Ignored. */
2233 break;
2234 }
2235 }
2236 }
2237
2238 /* Swap operands if necessary. Only supports one swap at the
2239 moment. */
2240 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2241 {
2242 operand_pseudo = &pseudo_insn->operand[i];
2243
2244 if (operand_pseudo->swap_operand_idx == i)
2245 continue;
2246
2247 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2248
2249 /* Prevent a swap back later by breaking out. */
2250 break;
2251 }
2252
2253 return arc_find_opcode (pseudo_insn->mnemonic_r);
2254 }
2255
2256 static const struct arc_opcode_hash_entry *
2257 find_special_case_flag (const char *opname,
2258 int *nflgs,
2259 struct arc_flags *pflags)
2260 {
2261 unsigned int i;
2262 const char *flagnm;
2263 unsigned flag_idx, flag_arr_idx;
2264 size_t flaglen, oplen;
2265 const struct arc_flag_special *arc_flag_special_opcode;
2266 const struct arc_opcode_hash_entry *entry;
2267
2268 /* Search for special case instruction. */
2269 for (i = 0; i < arc_num_flag_special; i++)
2270 {
2271 arc_flag_special_opcode = &arc_flag_special_cases[i];
2272 oplen = strlen (arc_flag_special_opcode->name);
2273
2274 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2275 continue;
2276
2277 /* Found a potential special case instruction, now test for
2278 flags. */
2279 for (flag_arr_idx = 0;; ++flag_arr_idx)
2280 {
2281 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2282 if (flag_idx == 0)
2283 break; /* End of array, nothing found. */
2284
2285 flagnm = arc_flag_operands[flag_idx].name;
2286 flaglen = strlen (flagnm);
2287 if (strcmp (opname + oplen, flagnm) == 0)
2288 {
2289 entry = arc_find_opcode (arc_flag_special_opcode->name);
2290
2291 if (*nflgs + 1 > MAX_INSN_FLGS)
2292 break;
2293 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2294 pflags[*nflgs].name[flaglen] = '\0';
2295 (*nflgs)++;
2296 return entry;
2297 }
2298 }
2299 }
2300 return NULL;
2301 }
2302
2303 /* Used to find special case opcode. */
2304
2305 static const struct arc_opcode_hash_entry *
2306 find_special_case (const char *opname,
2307 int *nflgs,
2308 struct arc_flags *pflags,
2309 expressionS *tok,
2310 int *ntok)
2311 {
2312 const struct arc_opcode_hash_entry *entry;
2313
2314 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
2315
2316 if (entry == NULL)
2317 entry = find_special_case_flag (opname, nflgs, pflags);
2318
2319 return entry;
2320 }
2321
2322 /* Autodetect cpu attribute list. */
2323
2324 static void
2325 autodetect_attributes (const struct arc_opcode *opcode,
2326 const expressionS *tok,
2327 int ntok)
2328 {
2329 unsigned i;
2330 struct mpy_type
2331 {
2332 unsigned feature;
2333 unsigned encoding;
2334 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2335 { MPY9E, 9 }};
2336
2337 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2338 if (opcode->subclass == feature_list[i].feature)
2339 selected_cpu.features |= feature_list[i].feature;
2340
2341 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2342 if (opcode->subclass == mpy_list[i].feature)
2343 mpy_option = mpy_list[i].encoding;
2344
2345 for (i = 0; i < (unsigned) ntok; i++)
2346 {
2347 switch (tok[i].X_md)
2348 {
2349 case O_gotoff:
2350 case O_gotpc:
2351 case O_plt:
2352 pic_option = 2;
2353 break;
2354 case O_sda:
2355 sda_option = 2;
2356 break;
2357 case O_tlsgd:
2358 case O_tlsie:
2359 case O_tpoff9:
2360 case O_tpoff:
2361 case O_dtpoff9:
2362 case O_dtpoff:
2363 tls_option = 1;
2364 break;
2365 default:
2366 break;
2367 }
2368 }
2369 }
2370
2371 /* Given an opcode name, pre-tockenized set of argumenst and the
2372 opcode flags, take it all the way through emission. */
2373
2374 static void
2375 assemble_tokens (const char *opname,
2376 expressionS *tok,
2377 int ntok,
2378 struct arc_flags *pflags,
2379 int nflgs)
2380 {
2381 bfd_boolean found_something = FALSE;
2382 const struct arc_opcode_hash_entry *entry;
2383 int cpumatch = 1;
2384 const char *errmsg = NULL;
2385
2386 /* Search opcodes. */
2387 entry = arc_find_opcode (opname);
2388
2389 /* Couldn't find opcode conventional way, try special cases. */
2390 if (entry == NULL)
2391 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
2392
2393 if (entry != NULL)
2394 {
2395 const struct arc_opcode *opcode;
2396
2397 pr_debug ("%s:%d: assemble_tokens: %s\n",
2398 frag_now->fr_file, frag_now->fr_line, opname);
2399 found_something = TRUE;
2400 opcode = find_opcode_match (entry, tok, &ntok, pflags,
2401 nflgs, &cpumatch, &errmsg);
2402 if (opcode != NULL)
2403 {
2404 struct arc_insn insn;
2405
2406 autodetect_attributes (opcode, tok, ntok);
2407 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2408 emit_insn (&insn);
2409 return;
2410 }
2411 }
2412
2413 if (found_something)
2414 {
2415 if (cpumatch)
2416 if (errmsg)
2417 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2418 else
2419 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2420 else
2421 as_bad (_("opcode '%s' not supported for target %s"), opname,
2422 selected_cpu.name);
2423 }
2424 else
2425 as_bad (_("unknown opcode '%s'"), opname);
2426 }
2427
2428 /* The public interface to the instruction assembler. */
2429
2430 void
2431 md_assemble (char *str)
2432 {
2433 char *opname;
2434 expressionS tok[MAX_INSN_ARGS];
2435 int ntok, nflg;
2436 size_t opnamelen;
2437 struct arc_flags flags[MAX_INSN_FLGS];
2438
2439 /* Split off the opcode. */
2440 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2441 opname = xmemdup0 (str, opnamelen);
2442
2443 /* Signalize we are assembling the instructions. */
2444 assembling_insn = TRUE;
2445
2446 /* Tokenize the flags. */
2447 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2448 {
2449 as_bad (_("syntax error"));
2450 return;
2451 }
2452
2453 /* Scan up to the end of the mnemonic which must end in space or end
2454 of string. */
2455 str += opnamelen;
2456 for (; *str != '\0'; str++)
2457 if (*str == ' ')
2458 break;
2459
2460 /* Tokenize the rest of the line. */
2461 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
2462 {
2463 as_bad (_("syntax error"));
2464 return;
2465 }
2466
2467 /* Finish it off. */
2468 assemble_tokens (opname, tok, ntok, flags, nflg);
2469 assembling_insn = FALSE;
2470 }
2471
2472 /* Callback to insert a register into the hash table. */
2473
2474 static void
2475 declare_register (const char *name, int number)
2476 {
2477 const char *err;
2478 symbolS *regS = symbol_create (name, reg_section,
2479 number, &zero_address_frag);
2480
2481 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2482 if (err)
2483 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2484 name, err);
2485 }
2486
2487 /* Construct symbols for each of the general registers. */
2488
2489 static void
2490 declare_register_set (void)
2491 {
2492 int i;
2493 for (i = 0; i < 64; ++i)
2494 {
2495 char name[7];
2496
2497 sprintf (name, "r%d", i);
2498 declare_register (name, i);
2499 if ((i & 0x01) == 0)
2500 {
2501 sprintf (name, "r%dr%d", i, i+1);
2502 declare_register (name, i);
2503 }
2504 }
2505 }
2506
2507 /* Construct a symbol for an address type. */
2508
2509 static void
2510 declare_addrtype (const char *name, int number)
2511 {
2512 const char *err;
2513 symbolS *addrtypeS = symbol_create (name, undefined_section,
2514 number, &zero_address_frag);
2515
2516 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2517 (void *) addrtypeS);
2518 if (err)
2519 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2520 name, err);
2521 }
2522
2523 /* Port-specific assembler initialization. This function is called
2524 once, at assembler startup time. */
2525
2526 void
2527 md_begin (void)
2528 {
2529 const struct arc_opcode *opcode = arc_opcodes;
2530
2531 if (mach_selection_mode == MACH_SELECTION_NONE)
2532 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
2533
2534 /* The endianness can be chosen "at the factory". */
2535 target_big_endian = byte_order == BIG_ENDIAN;
2536
2537 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
2538 as_warn (_("could not set architecture and machine"));
2539
2540 /* Set elf header flags. */
2541 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
2542
2543 /* Set up a hash table for the instructions. */
2544 arc_opcode_hash = hash_new ();
2545 if (arc_opcode_hash == NULL)
2546 as_fatal (_("Virtual memory exhausted"));
2547
2548 /* Initialize the hash table with the insns. */
2549 do
2550 {
2551 const char *name = opcode->name;
2552
2553 arc_insert_opcode (opcode);
2554
2555 while (++opcode && opcode->name
2556 && (opcode->name == name
2557 || !strcmp (opcode->name, name)))
2558 continue;
2559 }while (opcode->name);
2560
2561 /* Register declaration. */
2562 arc_reg_hash = hash_new ();
2563 if (arc_reg_hash == NULL)
2564 as_fatal (_("Virtual memory exhausted"));
2565
2566 declare_register_set ();
2567 declare_register ("gp", 26);
2568 declare_register ("fp", 27);
2569 declare_register ("sp", 28);
2570 declare_register ("ilink", 29);
2571 declare_register ("ilink1", 29);
2572 declare_register ("ilink2", 30);
2573 declare_register ("blink", 31);
2574
2575 /* XY memory registers. */
2576 declare_register ("x0_u0", 32);
2577 declare_register ("x0_u1", 33);
2578 declare_register ("x1_u0", 34);
2579 declare_register ("x1_u1", 35);
2580 declare_register ("x2_u0", 36);
2581 declare_register ("x2_u1", 37);
2582 declare_register ("x3_u0", 38);
2583 declare_register ("x3_u1", 39);
2584 declare_register ("y0_u0", 40);
2585 declare_register ("y0_u1", 41);
2586 declare_register ("y1_u0", 42);
2587 declare_register ("y1_u1", 43);
2588 declare_register ("y2_u0", 44);
2589 declare_register ("y2_u1", 45);
2590 declare_register ("y3_u0", 46);
2591 declare_register ("y3_u1", 47);
2592 declare_register ("x0_nu", 48);
2593 declare_register ("x1_nu", 49);
2594 declare_register ("x2_nu", 50);
2595 declare_register ("x3_nu", 51);
2596 declare_register ("y0_nu", 52);
2597 declare_register ("y1_nu", 53);
2598 declare_register ("y2_nu", 54);
2599 declare_register ("y3_nu", 55);
2600
2601 declare_register ("mlo", 57);
2602 declare_register ("mmid", 58);
2603 declare_register ("mhi", 59);
2604
2605 declare_register ("acc1", 56);
2606 declare_register ("acc2", 57);
2607
2608 declare_register ("lp_count", 60);
2609 declare_register ("pcl", 63);
2610
2611 /* Initialize the last instructions. */
2612 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
2613
2614 /* Aux register declaration. */
2615 arc_aux_hash = hash_new ();
2616 if (arc_aux_hash == NULL)
2617 as_fatal (_("Virtual memory exhausted"));
2618
2619 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2620 unsigned int i;
2621 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2622 {
2623 const char *retval;
2624
2625 if (!(auxr->cpu & selected_cpu.flags))
2626 continue;
2627
2628 if ((auxr->subclass != NONE)
2629 && !check_cpu_feature (auxr->subclass))
2630 continue;
2631
2632 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2633 if (retval)
2634 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2635 auxr->name, retval);
2636 }
2637
2638 /* Address type declaration. */
2639 arc_addrtype_hash = hash_new ();
2640 if (arc_addrtype_hash == NULL)
2641 as_fatal (_("Virtual memory exhausted"));
2642
2643 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2644 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2645 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2646 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2647 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2648 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2649 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2650 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2651 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2652 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2653 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2654 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2655 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2656 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2657 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2658 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
2659 }
2660
2661 /* Write a value out to the object file, using the appropriate
2662 endianness. */
2663
2664 void
2665 md_number_to_chars (char *buf,
2666 valueT val,
2667 int n)
2668 {
2669 if (target_big_endian)
2670 number_to_chars_bigendian (buf, val, n);
2671 else
2672 number_to_chars_littleendian (buf, val, n);
2673 }
2674
2675 /* Round up a section size to the appropriate boundary. */
2676
2677 valueT
2678 md_section_align (segT segment,
2679 valueT size)
2680 {
2681 int align = bfd_get_section_alignment (stdoutput, segment);
2682
2683 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
2684 }
2685
2686 /* The location from which a PC relative jump should be calculated,
2687 given a PC relative reloc. */
2688
2689 long
2690 md_pcrel_from_section (fixS *fixP,
2691 segT sec)
2692 {
2693 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
2694
2695 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
2696
2697 if (fixP->fx_addsy != (symbolS *) NULL
2698 && (!S_IS_DEFINED (fixP->fx_addsy)
2699 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2700 {
2701 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
2702
2703 /* The symbol is undefined (or is defined but not in this section).
2704 Let the linker figure it out. */
2705 return 0;
2706 }
2707
2708 if ((int) fixP->fx_r_type < 0)
2709 {
2710 /* These are the "internal" relocations. Align them to
2711 32 bit boundary (PCL), for the moment. */
2712 base &= ~3;
2713 }
2714 else
2715 {
2716 switch (fixP->fx_r_type)
2717 {
2718 case BFD_RELOC_ARC_PC32:
2719 /* The hardware calculates relative to the start of the
2720 insn, but this relocation is relative to location of the
2721 LIMM, compensate. The base always needs to be
2722 subtracted by 4 as we do not support this type of PCrel
2723 relocation for short instructions. */
2724 base -= 4;
2725 /* Fall through. */
2726 case BFD_RELOC_ARC_PLT32:
2727 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2728 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2729 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2730 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2731
2732 case BFD_RELOC_ARC_S21H_PCREL:
2733 case BFD_RELOC_ARC_S25H_PCREL:
2734 case BFD_RELOC_ARC_S13_PCREL:
2735 case BFD_RELOC_ARC_S21W_PCREL:
2736 case BFD_RELOC_ARC_S25W_PCREL:
2737 base &= ~3;
2738 break;
2739 default:
2740 as_bad_where (fixP->fx_file, fixP->fx_line,
2741 _("unhandled reloc %s in md_pcrel_from_section"),
2742 bfd_get_reloc_code_name (fixP->fx_r_type));
2743 break;
2744 }
2745 }
2746
2747 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2748 "symbol: %s (%"BFD_VMA_FMT"x)\n",
2749 fixP->fx_frag->fr_address, fixP->fx_where, base,
2750 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2751 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2752
2753 return base;
2754 }
2755
2756 /* Given a BFD relocation find the corresponding operand. */
2757
2758 static const struct arc_operand *
2759 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2760 {
2761 unsigned i;
2762
2763 for (i = 0; i < arc_num_operands; i++)
2764 if (arc_operands[i].default_reloc == reloc)
2765 return &arc_operands[i];
2766 return NULL;
2767 }
2768
2769 /* Insert an operand value into an instruction. */
2770
2771 static unsigned long long
2772 insert_operand (unsigned long long insn,
2773 const struct arc_operand *operand,
2774 long long val,
2775 const char *file,
2776 unsigned line)
2777 {
2778 offsetT min = 0, max = 0;
2779
2780 if (operand->bits != 32
2781 && !(operand->flags & ARC_OPERAND_NCHK)
2782 && !(operand->flags & ARC_OPERAND_FAKE))
2783 {
2784 if (operand->flags & ARC_OPERAND_SIGNED)
2785 {
2786 max = (1 << (operand->bits - 1)) - 1;
2787 min = -(1 << (operand->bits - 1));
2788 }
2789 else
2790 {
2791 max = (1 << operand->bits) - 1;
2792 min = 0;
2793 }
2794
2795 if (val < min || val > max)
2796 as_bad_value_out_of_range (_("operand"),
2797 val, min, max, file, line);
2798 }
2799
2800 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2801 min, val, max, insn);
2802
2803 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2804 && (val & 0x03))
2805 as_bad_where (file, line,
2806 _("Unaligned operand. Needs to be 32bit aligned"));
2807
2808 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2809 && (val & 0x01))
2810 as_bad_where (file, line,
2811 _("Unaligned operand. Needs to be 16bit aligned"));
2812
2813 if (operand->insert)
2814 {
2815 const char *errmsg = NULL;
2816
2817 insn = (*operand->insert) (insn, val, &errmsg);
2818 if (errmsg)
2819 as_warn_where (file, line, "%s", errmsg);
2820 }
2821 else
2822 {
2823 if (operand->flags & ARC_OPERAND_TRUNCATE)
2824 {
2825 if (operand->flags & ARC_OPERAND_ALIGNED32)
2826 val >>= 2;
2827 if (operand->flags & ARC_OPERAND_ALIGNED16)
2828 val >>= 1;
2829 }
2830 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2831 }
2832 return insn;
2833 }
2834
2835 /* Apply a fixup to the object code. At this point all symbol values
2836 should be fully resolved, and we attempt to completely resolve the
2837 reloc. If we can not do that, we determine the correct reloc code
2838 and put it back in the fixup. To indicate that a fixup has been
2839 eliminated, set fixP->fx_done. */
2840
2841 void
2842 md_apply_fix (fixS *fixP,
2843 valueT *valP,
2844 segT seg)
2845 {
2846 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2847 valueT value = *valP;
2848 unsigned insn = 0;
2849 symbolS *fx_addsy, *fx_subsy;
2850 offsetT fx_offset;
2851 segT add_symbol_segment = absolute_section;
2852 segT sub_symbol_segment = absolute_section;
2853 const struct arc_operand *operand = NULL;
2854 extended_bfd_reloc_code_real_type reloc;
2855
2856 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2857 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2858 ((int) fixP->fx_r_type < 0) ? "Internal":
2859 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2860 fixP->fx_offset);
2861
2862 fx_addsy = fixP->fx_addsy;
2863 fx_subsy = fixP->fx_subsy;
2864 fx_offset = 0;
2865
2866 if (fx_addsy)
2867 {
2868 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
2869 }
2870
2871 if (fx_subsy
2872 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2873 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2874 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2875 {
2876 resolve_symbol_value (fx_subsy);
2877 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
2878
2879 if (sub_symbol_segment == absolute_section)
2880 {
2881 /* The symbol is really a constant. */
2882 fx_offset -= S_GET_VALUE (fx_subsy);
2883 fx_subsy = NULL;
2884 }
2885 else
2886 {
2887 as_bad_where (fixP->fx_file, fixP->fx_line,
2888 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2889 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2890 segment_name (add_symbol_segment),
2891 S_GET_NAME (fx_subsy),
2892 segment_name (sub_symbol_segment));
2893 return;
2894 }
2895 }
2896
2897 if (fx_addsy
2898 && !S_IS_WEAK (fx_addsy))
2899 {
2900 if (add_symbol_segment == seg
2901 && fixP->fx_pcrel)
2902 {
2903 value += S_GET_VALUE (fx_addsy);
2904 value -= md_pcrel_from_section (fixP, seg);
2905 fx_addsy = NULL;
2906 fixP->fx_pcrel = FALSE;
2907 }
2908 else if (add_symbol_segment == absolute_section)
2909 {
2910 value = fixP->fx_offset;
2911 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2912 fx_addsy = NULL;
2913 fixP->fx_pcrel = FALSE;
2914 }
2915 }
2916
2917 if (!fx_addsy)
2918 fixP->fx_done = TRUE;
2919
2920 if (fixP->fx_pcrel)
2921 {
2922 if (fx_addsy
2923 && ((S_IS_DEFINED (fx_addsy)
2924 && S_GET_SEGMENT (fx_addsy) != seg)
2925 || S_IS_WEAK (fx_addsy)))
2926 value += md_pcrel_from_section (fixP, seg);
2927
2928 switch (fixP->fx_r_type)
2929 {
2930 case BFD_RELOC_ARC_32_ME:
2931 /* This is a pc-relative value in a LIMM. Adjust it to the
2932 address of the instruction not to the address of the
2933 LIMM. Note: it is not any longer valid this affirmation as
2934 the linker consider ARC_PC32 a fixup to entire 64 bit
2935 insn. */
2936 fixP->fx_offset += fixP->fx_frag->fr_address;
2937 /* Fall through. */
2938 case BFD_RELOC_32:
2939 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2940 /* Fall through. */
2941 case BFD_RELOC_ARC_PC32:
2942 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2943 break;
2944 default:
2945 if ((int) fixP->fx_r_type < 0)
2946 as_bad_where (fixP->fx_file, fixP->fx_line,
2947 _("PC relative relocation not allowed for (internal)"
2948 " type %d"),
2949 fixP->fx_r_type);
2950 break;
2951 }
2952 }
2953
2954 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2955 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2956 ((int) fixP->fx_r_type < 0) ? "Internal":
2957 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2958 fixP->fx_offset);
2959
2960
2961 /* Now check for TLS relocations. */
2962 reloc = fixP->fx_r_type;
2963 switch (reloc)
2964 {
2965 case BFD_RELOC_ARC_TLS_DTPOFF:
2966 case BFD_RELOC_ARC_TLS_LE_32:
2967 if (fixP->fx_done)
2968 break;
2969 /* Fall through. */
2970 case BFD_RELOC_ARC_TLS_GD_GOT:
2971 case BFD_RELOC_ARC_TLS_IE_GOT:
2972 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2973 break;
2974
2975 case BFD_RELOC_ARC_TLS_GD_LD:
2976 gas_assert (!fixP->fx_offset);
2977 if (fixP->fx_subsy)
2978 fixP->fx_offset
2979 = (S_GET_VALUE (fixP->fx_subsy)
2980 - fixP->fx_frag->fr_address- fixP->fx_where);
2981 fixP->fx_subsy = NULL;
2982 /* Fall through. */
2983 case BFD_RELOC_ARC_TLS_GD_CALL:
2984 /* These two relocs are there just to allow ld to change the tls
2985 model for this symbol, by patching the code. The offset -
2986 and scale, if any - will be installed by the linker. */
2987 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2988 break;
2989
2990 case BFD_RELOC_ARC_TLS_LE_S9:
2991 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2992 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2993 break;
2994
2995 default:
2996 break;
2997 }
2998
2999 if (!fixP->fx_done)
3000 {
3001 return;
3002 }
3003
3004 /* Adjust the value if we have a constant. */
3005 value += fx_offset;
3006
3007 /* For hosts with longs bigger than 32-bits make sure that the top
3008 bits of a 32-bit negative value read in by the parser are set,
3009 so that the correct comparisons are made. */
3010 if (value & 0x80000000)
3011 value |= (-1UL << 31);
3012
3013 reloc = fixP->fx_r_type;
3014 switch (reloc)
3015 {
3016 case BFD_RELOC_8:
3017 case BFD_RELOC_16:
3018 case BFD_RELOC_24:
3019 case BFD_RELOC_32:
3020 case BFD_RELOC_64:
3021 case BFD_RELOC_ARC_32_PCREL:
3022 md_number_to_chars (fixpos, value, fixP->fx_size);
3023 return;
3024
3025 case BFD_RELOC_ARC_GOTPC32:
3026 /* I cannot fix an GOTPC relocation because I need to relax it
3027 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3028 as_bad (_("Unsupported operation on reloc"));
3029 return;
3030
3031 case BFD_RELOC_ARC_TLS_DTPOFF:
3032 case BFD_RELOC_ARC_TLS_LE_32:
3033 gas_assert (!fixP->fx_addsy);
3034 gas_assert (!fixP->fx_subsy);
3035 /* Fall through. */
3036
3037 case BFD_RELOC_ARC_GOTOFF:
3038 case BFD_RELOC_ARC_32_ME:
3039 case BFD_RELOC_ARC_PC32:
3040 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3041 return;
3042
3043 case BFD_RELOC_ARC_PLT32:
3044 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3045 return;
3046
3047 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3048 reloc = BFD_RELOC_ARC_S25W_PCREL;
3049 goto solve_plt;
3050
3051 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3052 reloc = BFD_RELOC_ARC_S21H_PCREL;
3053 goto solve_plt;
3054
3055 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3056 reloc = BFD_RELOC_ARC_S25W_PCREL;
3057 goto solve_plt;
3058
3059 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3060 reloc = BFD_RELOC_ARC_S21W_PCREL;
3061 /* Fall through. */
3062
3063 case BFD_RELOC_ARC_S25W_PCREL:
3064 case BFD_RELOC_ARC_S21W_PCREL:
3065 case BFD_RELOC_ARC_S21H_PCREL:
3066 case BFD_RELOC_ARC_S25H_PCREL:
3067 case BFD_RELOC_ARC_S13_PCREL:
3068 solve_plt:
3069 operand = find_operand_for_reloc (reloc);
3070 gas_assert (operand);
3071 break;
3072
3073 default:
3074 {
3075 if ((int) fixP->fx_r_type >= 0)
3076 as_fatal (_("unhandled relocation type %s"),
3077 bfd_get_reloc_code_name (fixP->fx_r_type));
3078
3079 /* The rest of these fixups needs to be completely resolved as
3080 constants. */
3081 if (fixP->fx_addsy != 0
3082 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3083 as_bad_where (fixP->fx_file, fixP->fx_line,
3084 _("non-absolute expression in constant field"));
3085
3086 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3087 operand = &arc_operands[-(int) fixP->fx_r_type];
3088 break;
3089 }
3090 }
3091
3092 if (target_big_endian)
3093 {
3094 switch (fixP->fx_size)
3095 {
3096 case 4:
3097 insn = bfd_getb32 (fixpos);
3098 break;
3099 case 2:
3100 insn = bfd_getb16 (fixpos);
3101 break;
3102 default:
3103 as_bad_where (fixP->fx_file, fixP->fx_line,
3104 _("unknown fixup size"));
3105 }
3106 }
3107 else
3108 {
3109 insn = 0;
3110 switch (fixP->fx_size)
3111 {
3112 case 4:
3113 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3114 break;
3115 case 2:
3116 insn = bfd_getl16 (fixpos);
3117 break;
3118 default:
3119 as_bad_where (fixP->fx_file, fixP->fx_line,
3120 _("unknown fixup size"));
3121 }
3122 }
3123
3124 insn = insert_operand (insn, operand, (offsetT) value,
3125 fixP->fx_file, fixP->fx_line);
3126
3127 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3128 }
3129
3130 /* Prepare machine-dependent frags for relaxation.
3131
3132 Called just before relaxation starts. Any symbol that is now undefined
3133 will not become defined.
3134
3135 Return the correct fr_subtype in the frag.
3136
3137 Return the initial "guess for fr_var" to caller. The guess for fr_var
3138 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3139 or fr_var contributes to our returned value.
3140
3141 Although it may not be explicit in the frag, pretend
3142 fr_var starts with a value. */
3143
3144 int
3145 md_estimate_size_before_relax (fragS *fragP,
3146 segT segment)
3147 {
3148 int growth;
3149
3150 /* If the symbol is not located within the same section AND it's not
3151 an absolute section, use the maximum. OR if the symbol is a
3152 constant AND the insn is by nature not pc-rel, use the maximum.
3153 OR if the symbol is being equated against another symbol, use the
3154 maximum. OR if the symbol is weak use the maximum. */
3155 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3156 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3157 || (symbol_constant_p (fragP->fr_symbol)
3158 && !fragP->tc_frag_data.pcrel)
3159 || symbol_equated_p (fragP->fr_symbol)
3160 || S_IS_WEAK (fragP->fr_symbol))
3161 {
3162 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3163 ++fragP->fr_subtype;
3164 }
3165
3166 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3167 fragP->fr_var = growth;
3168
3169 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3170 fragP->fr_file, fragP->fr_line, growth);
3171
3172 return growth;
3173 }
3174
3175 /* Translate internal representation of relocation info to BFD target
3176 format. */
3177
3178 arelent *
3179 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3180 fixS *fixP)
3181 {
3182 arelent *reloc;
3183 bfd_reloc_code_real_type code;
3184
3185 reloc = XNEW (arelent);
3186 reloc->sym_ptr_ptr = XNEW (asymbol *);
3187 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3188 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
3189
3190 /* Make sure none of our internal relocations make it this far.
3191 They'd better have been fully resolved by this point. */
3192 gas_assert ((int) fixP->fx_r_type > 0);
3193
3194 code = fixP->fx_r_type;
3195
3196 /* if we have something like add gp, pcl,
3197 _GLOBAL_OFFSET_TABLE_@gotpc. */
3198 if (code == BFD_RELOC_ARC_GOTPC32
3199 && GOT_symbol
3200 && fixP->fx_addsy == GOT_symbol)
3201 code = BFD_RELOC_ARC_GOTPC;
3202
3203 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3204 if (reloc->howto == NULL)
3205 {
3206 as_bad_where (fixP->fx_file, fixP->fx_line,
3207 _("cannot represent `%s' relocation in object file"),
3208 bfd_get_reloc_code_name (code));
3209 return NULL;
3210 }
3211
3212 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3213 as_fatal (_("internal error? cannot generate `%s' relocation"),
3214 bfd_get_reloc_code_name (code));
3215
3216 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
3217
3218 reloc->addend = fixP->fx_offset;
3219
3220 return reloc;
3221 }
3222
3223 /* Perform post-processing of machine-dependent frags after relaxation.
3224 Called after relaxation is finished.
3225 In: Address of frag.
3226 fr_type == rs_machine_dependent.
3227 fr_subtype is what the address relaxed to.
3228
3229 Out: Any fixS:s and constants are set up. */
3230
3231 void
3232 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3233 segT segment ATTRIBUTE_UNUSED,
3234 fragS *fragP)
3235 {
3236 const relax_typeS *table_entry;
3237 char *dest;
3238 const struct arc_opcode *opcode;
3239 struct arc_insn insn;
3240 int size, fix;
3241 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
3242
3243 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3244 dest = fragP->fr_literal + fix;
3245 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
3246
3247 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3248 "var: %"BFD_VMA_FMT"d\n",
3249 fragP->fr_file, fragP->fr_line,
3250 fragP->fr_subtype, fix, fragP->fr_var);
3251
3252 if (fragP->fr_subtype <= 0
3253 && fragP->fr_subtype >= arc_num_relax_opcodes)
3254 as_fatal (_("no relaxation found for this instruction."));
3255
3256 opcode = &arc_relax_opcodes[fragP->fr_subtype];
3257
3258 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3259 relax_arg->nflg, &insn);
3260
3261 apply_fixups (&insn, fragP, fix);
3262
3263 size = insn.len + (insn.has_limm ? 4 : 0);
3264 gas_assert (table_entry->rlx_length == size);
3265 emit_insn0 (&insn, dest, TRUE);
3266
3267 fragP->fr_fix += table_entry->rlx_length;
3268 fragP->fr_var = 0;
3269 }
3270
3271 /* We have no need to default values of symbols. We could catch
3272 register names here, but that is handled by inserting them all in
3273 the symbol table to begin with. */
3274
3275 symbolS *
3276 md_undefined_symbol (char *name)
3277 {
3278 /* The arc abi demands that a GOT[0] should be referencible as
3279 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3280 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3281 if (((*name == '_')
3282 && (*(name+1) == 'G')
3283 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3284 || ((*name == '_')
3285 && (*(name+1) == 'D')
3286 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
3287 {
3288 if (!GOT_symbol)
3289 {
3290 if (symbol_find (name))
3291 as_bad ("GOT already in symbol table");
3292
3293 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3294 (valueT) 0, &zero_address_frag);
3295 };
3296 return GOT_symbol;
3297 }
3298 return NULL;
3299 }
3300
3301 /* Turn a string in input_line_pointer into a floating point constant
3302 of type type, and store the appropriate bytes in *litP. The number
3303 of LITTLENUMS emitted is stored in *sizeP. An error message is
3304 returned, or NULL on OK. */
3305
3306 const char *
3307 md_atof (int type, char *litP, int *sizeP)
3308 {
3309 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3310 }
3311
3312 /* Called for any expression that can not be recognized. When the
3313 function is called, `input_line_pointer' will point to the start of
3314 the expression. */
3315
3316 void
3317 md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3318 {
3319 char *p = input_line_pointer;
3320 if (*p == '@')
3321 {
3322 input_line_pointer++;
3323 expressionP->X_op = O_symbol;
3324 expression (expressionP);
3325 }
3326 }
3327
3328 /* This function is called from the function 'expression', it attempts
3329 to parse special names (in our case register names). It fills in
3330 the expression with the identified register. It returns TRUE if
3331 it is a register and FALSE otherwise. */
3332
3333 bfd_boolean
3334 arc_parse_name (const char *name,
3335 struct expressionS *e)
3336 {
3337 struct symbol *sym;
3338
3339 if (!assembling_insn)
3340 return FALSE;
3341
3342 if (e->X_op == O_symbol)
3343 return FALSE;
3344
3345 sym = hash_find (arc_reg_hash, name);
3346 if (sym)
3347 {
3348 e->X_op = O_register;
3349 e->X_add_number = S_GET_VALUE (sym);
3350 return TRUE;
3351 }
3352
3353 sym = hash_find (arc_addrtype_hash, name);
3354 if (sym)
3355 {
3356 e->X_op = O_addrtype;
3357 e->X_add_number = S_GET_VALUE (sym);
3358 return TRUE;
3359 }
3360
3361 return FALSE;
3362 }
3363
3364 /* md_parse_option
3365 Invocation line includes a switch not recognized by the base assembler.
3366 See if it's a processor-specific option.
3367
3368 New options (supported) are:
3369
3370 -mcpu=<cpu name> Assemble for selected processor
3371 -EB/-mbig-endian Big-endian
3372 -EL/-mlittle-endian Little-endian
3373 -mrelax Enable relaxation
3374
3375 The following CPU names are recognized:
3376 arc600, arc700, arcem, archs, nps400. */
3377
3378 int
3379 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
3380 {
3381 switch (c)
3382 {
3383 case OPTION_ARC600:
3384 case OPTION_ARC601:
3385 return md_parse_option (OPTION_MCPU, "arc600");
3386
3387 case OPTION_ARC700:
3388 return md_parse_option (OPTION_MCPU, "arc700");
3389
3390 case OPTION_ARCEM:
3391 return md_parse_option (OPTION_MCPU, "arcem");
3392
3393 case OPTION_ARCHS:
3394 return md_parse_option (OPTION_MCPU, "archs");
3395
3396 case OPTION_MCPU:
3397 {
3398 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
3399 break;
3400 }
3401
3402 case OPTION_EB:
3403 arc_target_format = "elf32-bigarc";
3404 byte_order = BIG_ENDIAN;
3405 break;
3406
3407 case OPTION_EL:
3408 arc_target_format = "elf32-littlearc";
3409 byte_order = LITTLE_ENDIAN;
3410 break;
3411
3412 case OPTION_CD:
3413 selected_cpu.features |= CD;
3414 cl_features |= CD;
3415 arc_check_feature ();
3416 break;
3417
3418 case OPTION_RELAX:
3419 relaxation_state = 1;
3420 break;
3421
3422 case OPTION_NPS400:
3423 selected_cpu.features |= NPS400;
3424 cl_features |= NPS400;
3425 arc_check_feature ();
3426 break;
3427
3428 case OPTION_SPFP:
3429 selected_cpu.features |= SPX;
3430 cl_features |= SPX;
3431 arc_check_feature ();
3432 break;
3433
3434 case OPTION_DPFP:
3435 selected_cpu.features |= DPX;
3436 cl_features |= DPX;
3437 arc_check_feature ();
3438 break;
3439
3440 case OPTION_FPUDA:
3441 selected_cpu.features |= DPA;
3442 cl_features |= DPA;
3443 arc_check_feature ();
3444 break;
3445
3446 /* Dummy options are accepted but have no effect. */
3447 case OPTION_USER_MODE:
3448 case OPTION_LD_EXT_MASK:
3449 case OPTION_SWAP:
3450 case OPTION_NORM:
3451 case OPTION_BARREL_SHIFT:
3452 case OPTION_MIN_MAX:
3453 case OPTION_NO_MPY:
3454 case OPTION_EA:
3455 case OPTION_MUL64:
3456 case OPTION_SIMD:
3457 case OPTION_XMAC_D16:
3458 case OPTION_XMAC_24:
3459 case OPTION_DSP_PACKA:
3460 case OPTION_CRC:
3461 case OPTION_DVBF:
3462 case OPTION_TELEPHONY:
3463 case OPTION_XYMEMORY:
3464 case OPTION_LOCK:
3465 case OPTION_SWAPE:
3466 case OPTION_RTSC:
3467 break;
3468
3469 default:
3470 return 0;
3471 }
3472
3473 return 1;
3474 }
3475
3476 /* Display the list of cpu names for use in the help text. */
3477
3478 static void
3479 arc_show_cpu_list (FILE *stream)
3480 {
3481 int i, offset;
3482 static const char *space_buf = " ";
3483
3484 fprintf (stream, "%s", space_buf);
3485 offset = strlen (space_buf);
3486 for (i = 0; cpu_types[i].name != NULL; ++i)
3487 {
3488 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3489
3490 /* If displaying the new cpu name string, and the ', ' (for all
3491 but the last one) will take us past a target width of 80
3492 characters, then it's time for a new line. */
3493 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3494 {
3495 fprintf (stream, "\n%s", space_buf);
3496 offset = strlen (space_buf);
3497 }
3498
3499 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3500 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3501 }
3502 }
3503
3504 void
3505 md_show_usage (FILE *stream)
3506 {
3507 fprintf (stream, _("ARC-specific assembler options:\n"));
3508
3509 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3510 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3511 arc_show_cpu_list (stream);
3512 fprintf (stream, "\n");
3513 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3514 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3515 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3516 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3517
3518 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
3519 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3520 " instructions\n");
3521 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3522 " instructions\n");
3523 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3524 "point\n\t\t\t instructions for ARC EM\n");
3525
3526 fprintf (stream,
3527 " -mcode-density\t enable code density option for ARC EM\n");
3528
3529 fprintf (stream, _("\
3530 -EB assemble code for a big-endian cpu\n"));
3531 fprintf (stream, _("\
3532 -EL assemble code for a little-endian cpu\n"));
3533 fprintf (stream, _("\
3534 -mrelax enable relaxation\n"));
3535
3536 fprintf (stream, _("The following ARC-specific assembler options are "
3537 "deprecated and are accepted\nfor compatibility only:\n"));
3538
3539 fprintf (stream, _(" -mEA\n"
3540 " -mbarrel-shifter\n"
3541 " -mbarrel_shifter\n"
3542 " -mcrc\n"
3543 " -mdsp-packa\n"
3544 " -mdsp_packa\n"
3545 " -mdvbf\n"
3546 " -mld-extension-reg-mask\n"
3547 " -mlock\n"
3548 " -mmac-24\n"
3549 " -mmac-d16\n"
3550 " -mmac_24\n"
3551 " -mmac_d16\n"
3552 " -mmin-max\n"
3553 " -mmin_max\n"
3554 " -mmul64\n"
3555 " -mno-mpy\n"
3556 " -mnorm\n"
3557 " -mrtsc\n"
3558 " -msimd\n"
3559 " -mswap\n"
3560 " -mswape\n"
3561 " -mtelephony\n"
3562 " -muser-mode-only\n"
3563 " -mxy\n"));
3564 }
3565
3566 /* Find the proper relocation for the given opcode. */
3567
3568 static extended_bfd_reloc_code_real_type
3569 find_reloc (const char *name,
3570 const char *opcodename,
3571 const struct arc_flags *pflags,
3572 int nflg,
3573 extended_bfd_reloc_code_real_type reloc)
3574 {
3575 unsigned int i;
3576 int j;
3577 bfd_boolean found_flag, tmp;
3578 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3579
3580 for (i = 0; i < arc_num_equiv_tab; i++)
3581 {
3582 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3583
3584 /* Find the entry. */
3585 if (strcmp (name, r->name))
3586 continue;
3587 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3588 continue;
3589 if (r->flags[0])
3590 {
3591 if (!nflg)
3592 continue;
3593 found_flag = FALSE;
3594 unsigned * psflg = (unsigned *)r->flags;
3595 do
3596 {
3597 tmp = FALSE;
3598 for (j = 0; j < nflg; j++)
3599 if (!strcmp (pflags[j].name,
3600 arc_flag_operands[*psflg].name))
3601 {
3602 tmp = TRUE;
3603 break;
3604 }
3605 if (!tmp)
3606 {
3607 found_flag = FALSE;
3608 break;
3609 }
3610 else
3611 {
3612 found_flag = TRUE;
3613 }
3614 ++ psflg;
3615 } while (*psflg);
3616
3617 if (!found_flag)
3618 continue;
3619 }
3620
3621 if (reloc != r->oldreloc)
3622 continue;
3623 /* Found it. */
3624 ret = r->newreloc;
3625 break;
3626 }
3627
3628 if (ret == BFD_RELOC_UNUSED)
3629 as_bad (_("Unable to find %s relocation for instruction %s"),
3630 name, opcodename);
3631 return ret;
3632 }
3633
3634 /* All the symbol types that are allowed to be used for
3635 relaxation. */
3636
3637 static bfd_boolean
3638 may_relax_expr (expressionS tok)
3639 {
3640 /* Check if we have unrelaxable relocs. */
3641 switch (tok.X_md)
3642 {
3643 default:
3644 break;
3645 case O_plt:
3646 return FALSE;
3647 }
3648
3649 switch (tok.X_op)
3650 {
3651 case O_symbol:
3652 case O_multiply:
3653 case O_divide:
3654 case O_modulus:
3655 case O_add:
3656 case O_subtract:
3657 break;
3658
3659 default:
3660 return FALSE;
3661 }
3662 return TRUE;
3663 }
3664
3665 /* Checks if flags are in line with relaxable insn. */
3666
3667 static bfd_boolean
3668 relaxable_flag (const struct arc_relaxable_ins *ins,
3669 const struct arc_flags *pflags,
3670 int nflgs)
3671 {
3672 unsigned flag_class,
3673 flag,
3674 flag_class_idx = 0,
3675 flag_idx = 0;
3676
3677 const struct arc_flag_operand *flag_opand;
3678 int i, counttrue = 0;
3679
3680 /* Iterate through flags classes. */
3681 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3682 {
3683 /* Iterate through flags in flag class. */
3684 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3685 != 0)
3686 {
3687 flag_opand = &arc_flag_operands[flag];
3688 /* Iterate through flags in ins to compare. */
3689 for (i = 0; i < nflgs; ++i)
3690 {
3691 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3692 ++counttrue;
3693 }
3694
3695 ++flag_idx;
3696 }
3697
3698 ++flag_class_idx;
3699 flag_idx = 0;
3700 }
3701
3702 /* If counttrue == nflgs, then all flags have been found. */
3703 return (counttrue == nflgs ? TRUE : FALSE);
3704 }
3705
3706 /* Checks if operands are in line with relaxable insn. */
3707
3708 static bfd_boolean
3709 relaxable_operand (const struct arc_relaxable_ins *ins,
3710 const expressionS *tok,
3711 int ntok)
3712 {
3713 const enum rlx_operand_type *operand = &ins->operands[0];
3714 int i = 0;
3715
3716 while (*operand != EMPTY)
3717 {
3718 const expressionS *epr = &tok[i];
3719
3720 if (i != 0 && i >= ntok)
3721 return FALSE;
3722
3723 switch (*operand)
3724 {
3725 case IMMEDIATE:
3726 if (!(epr->X_op == O_multiply
3727 || epr->X_op == O_divide
3728 || epr->X_op == O_modulus
3729 || epr->X_op == O_add
3730 || epr->X_op == O_subtract
3731 || epr->X_op == O_symbol))
3732 return FALSE;
3733 break;
3734
3735 case REGISTER_DUP:
3736 if ((i <= 0)
3737 || (epr->X_add_number != tok[i - 1].X_add_number))
3738 return FALSE;
3739 /* Fall through. */
3740 case REGISTER:
3741 if (epr->X_op != O_register)
3742 return FALSE;
3743 break;
3744
3745 case REGISTER_S:
3746 if (epr->X_op != O_register)
3747 return FALSE;
3748
3749 switch (epr->X_add_number)
3750 {
3751 case 0: case 1: case 2: case 3:
3752 case 12: case 13: case 14: case 15:
3753 break;
3754 default:
3755 return FALSE;
3756 }
3757 break;
3758
3759 case REGISTER_NO_GP:
3760 if ((epr->X_op != O_register)
3761 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3762 return FALSE;
3763 break;
3764
3765 case BRACKET:
3766 if (epr->X_op != O_bracket)
3767 return FALSE;
3768 break;
3769
3770 default:
3771 /* Don't understand, bail out. */
3772 return FALSE;
3773 break;
3774 }
3775
3776 ++i;
3777 operand = &ins->operands[i];
3778 }
3779
3780 return (i == ntok ? TRUE : FALSE);
3781 }
3782
3783 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3784
3785 static bfd_boolean
3786 relax_insn_p (const struct arc_opcode *opcode,
3787 const expressionS *tok,
3788 int ntok,
3789 const struct arc_flags *pflags,
3790 int nflg)
3791 {
3792 unsigned i;
3793 bfd_boolean rv = FALSE;
3794
3795 /* Check the relaxation table. */
3796 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3797 {
3798 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3799
3800 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3801 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3802 && relaxable_operand (arc_rlx_ins, tok, ntok)
3803 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3804 {
3805 rv = TRUE;
3806 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3807 memcpy (&frag_now->tc_frag_data.tok, tok,
3808 sizeof (expressionS) * ntok);
3809 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3810 sizeof (struct arc_flags) * nflg);
3811 frag_now->tc_frag_data.nflg = nflg;
3812 frag_now->tc_frag_data.ntok = ntok;
3813 break;
3814 }
3815 }
3816
3817 return rv;
3818 }
3819
3820 /* Turn an opcode description and a set of arguments into
3821 an instruction and a fixup. */
3822
3823 static void
3824 assemble_insn (const struct arc_opcode *opcode,
3825 const expressionS *tok,
3826 int ntok,
3827 const struct arc_flags *pflags,
3828 int nflg,
3829 struct arc_insn *insn)
3830 {
3831 const expressionS *reloc_exp = NULL;
3832 unsigned long long image;
3833 const unsigned char *argidx;
3834 int i;
3835 int tokidx = 0;
3836 unsigned char pcrel = 0;
3837 bfd_boolean needGOTSymbol;
3838 bfd_boolean has_delay_slot = FALSE;
3839 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3840
3841 memset (insn, 0, sizeof (*insn));
3842 image = opcode->opcode;
3843
3844 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3845 frag_now->fr_file, frag_now->fr_line, opcode->name,
3846 opcode->opcode);
3847
3848 /* Handle operands. */
3849 for (argidx = opcode->operands; *argidx; ++argidx)
3850 {
3851 const struct arc_operand *operand = &arc_operands[*argidx];
3852 const expressionS *t = (const expressionS *) 0;
3853
3854 if (ARC_OPERAND_IS_FAKE (operand))
3855 continue;
3856
3857 if (operand->flags & ARC_OPERAND_DUPLICATE)
3858 {
3859 /* Duplicate operand, already inserted. */
3860 tokidx ++;
3861 continue;
3862 }
3863
3864 if (tokidx >= ntok)
3865 {
3866 abort ();
3867 }
3868 else
3869 t = &tok[tokidx++];
3870
3871 /* Regardless if we have a reloc or not mark the instruction
3872 limm if it is the case. */
3873 if (operand->flags & ARC_OPERAND_LIMM)
3874 insn->has_limm = TRUE;
3875
3876 switch (t->X_op)
3877 {
3878 case O_register:
3879 image = insert_operand (image, operand, regno (t->X_add_number),
3880 NULL, 0);
3881 break;
3882
3883 case O_constant:
3884 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3885 reloc_exp = t;
3886 if (operand->flags & ARC_OPERAND_LIMM)
3887 insn->limm = t->X_add_number;
3888 break;
3889
3890 case O_bracket:
3891 case O_colon:
3892 case O_addrtype:
3893 /* Ignore brackets, colons, and address types. */
3894 break;
3895
3896 case O_absent:
3897 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3898 break;
3899
3900 case O_subtract:
3901 /* Maybe register range. */
3902 if ((t->X_add_number == 0)
3903 && contains_register (t->X_add_symbol)
3904 && contains_register (t->X_op_symbol))
3905 {
3906 int regs;
3907
3908 regs = get_register (t->X_add_symbol);
3909 regs <<= 16;
3910 regs |= get_register (t->X_op_symbol);
3911 image = insert_operand (image, operand, regs, NULL, 0);
3912 break;
3913 }
3914 /* Fall through. */
3915
3916 default:
3917 /* This operand needs a relocation. */
3918 needGOTSymbol = FALSE;
3919
3920 switch (t->X_md)
3921 {
3922 case O_plt:
3923 if (opcode->insn_class == JUMP)
3924 as_bad (_("Unable to use @plt relocation for insn %s"),
3925 opcode->name);
3926 needGOTSymbol = TRUE;
3927 reloc = find_reloc ("plt", opcode->name,
3928 pflags, nflg,
3929 operand->default_reloc);
3930 break;
3931
3932 case O_gotoff:
3933 case O_gotpc:
3934 needGOTSymbol = TRUE;
3935 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3936 break;
3937 case O_pcl:
3938 if (operand->flags & ARC_OPERAND_LIMM)
3939 {
3940 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3941 if (arc_opcode_len (opcode) == 2
3942 || opcode->insn_class == JUMP)
3943 as_bad (_("Unable to use @pcl relocation for insn %s"),
3944 opcode->name);
3945 }
3946 else
3947 {
3948 /* This is a relaxed operand which initially was
3949 limm, choose whatever we have defined in the
3950 opcode as reloc. */
3951 reloc = operand->default_reloc;
3952 }
3953 break;
3954 case O_sda:
3955 reloc = find_reloc ("sda", opcode->name,
3956 pflags, nflg,
3957 operand->default_reloc);
3958 break;
3959 case O_tlsgd:
3960 case O_tlsie:
3961 needGOTSymbol = TRUE;
3962 /* Fall-through. */
3963
3964 case O_tpoff:
3965 case O_dtpoff:
3966 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3967 break;
3968
3969 case O_tpoff9: /*FIXME! Check for the conditionality of
3970 the insn. */
3971 case O_dtpoff9: /*FIXME! Check for the conditionality of
3972 the insn. */
3973 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3974 break;
3975
3976 default:
3977 /* Just consider the default relocation. */
3978 reloc = operand->default_reloc;
3979 break;
3980 }
3981
3982 if (needGOTSymbol && (GOT_symbol == NULL))
3983 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3984
3985 reloc_exp = t;
3986
3987 #if 0
3988 if (reloc > 0)
3989 {
3990 /* sanity checks. */
3991 reloc_howto_type *reloc_howto
3992 = bfd_reloc_type_lookup (stdoutput,
3993 (bfd_reloc_code_real_type) reloc);
3994 unsigned reloc_bitsize = reloc_howto->bitsize;
3995 if (reloc_howto->rightshift)
3996 reloc_bitsize -= reloc_howto->rightshift;
3997 if (reloc_bitsize != operand->bits)
3998 {
3999 as_bad (_("invalid relocation %s for field"),
4000 bfd_get_reloc_code_name (reloc));
4001 return;
4002 }
4003 }
4004 #endif
4005 if (insn->nfixups >= MAX_INSN_FIXUPS)
4006 as_fatal (_("too many fixups"));
4007
4008 struct arc_fixup *fixup;
4009 fixup = &insn->fixups[insn->nfixups++];
4010 fixup->exp = *t;
4011 fixup->reloc = reloc;
4012 if ((int) reloc < 0)
4013 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4014 else
4015 {
4016 reloc_howto_type *reloc_howto =
4017 bfd_reloc_type_lookup (stdoutput,
4018 (bfd_reloc_code_real_type) fixup->reloc);
4019 pcrel = reloc_howto->pc_relative;
4020 }
4021 fixup->pcrel = pcrel;
4022 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4023 TRUE : FALSE;
4024 break;
4025 }
4026 }
4027
4028 /* Handle flags. */
4029 for (i = 0; i < nflg; i++)
4030 {
4031 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
4032
4033 /* Check if the instruction has a delay slot. */
4034 if (!strcmp (flg_operand->name, "d"))
4035 has_delay_slot = TRUE;
4036
4037 /* There is an exceptional case when we cannot insert a flag just as
4038 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4039 relation with the relative address. Unfortunately, some of the
4040 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4041 handled in the normal way.
4042
4043 Flag operands don't have an architecture field, so we can't
4044 directly validate that FLAG_OPERAND is valid for the current
4045 architecture, what we do instead is just validate that we're
4046 assembling for an ARCv2 architecture. */
4047 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4048 && (!strcmp (flg_operand->name, "t")
4049 || !strcmp (flg_operand->name, "nt")))
4050 {
4051 unsigned bitYoperand = 0;
4052 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4053 if (!strcmp (flg_operand->name, "t"))
4054 if (!strcmp (opcode->name, "bbit0")
4055 || !strcmp (opcode->name, "bbit1"))
4056 bitYoperand = arc_NToperand;
4057 else
4058 bitYoperand = arc_Toperand;
4059 else
4060 if (!strcmp (opcode->name, "bbit0")
4061 || !strcmp (opcode->name, "bbit1"))
4062 bitYoperand = arc_Toperand;
4063 else
4064 bitYoperand = arc_NToperand;
4065
4066 gas_assert (reloc_exp != NULL);
4067 if (reloc_exp->X_op == O_constant)
4068 {
4069 /* Check if we have a constant and solved it
4070 immediately. */
4071 offsetT val = reloc_exp->X_add_number;
4072 image |= insert_operand (image, &arc_operands[bitYoperand],
4073 val, NULL, 0);
4074 }
4075 else
4076 {
4077 struct arc_fixup *fixup;
4078
4079 if (insn->nfixups >= MAX_INSN_FIXUPS)
4080 as_fatal (_("too many fixups"));
4081
4082 fixup = &insn->fixups[insn->nfixups++];
4083 fixup->exp = *reloc_exp;
4084 fixup->reloc = -bitYoperand;
4085 fixup->pcrel = pcrel;
4086 fixup->islong = FALSE;
4087 }
4088 }
4089 else
4090 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4091 << flg_operand->shift;
4092 }
4093
4094 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4095
4096 /* Instruction length. */
4097 insn->len = arc_opcode_len (opcode);
4098
4099 insn->insn = image;
4100
4101 /* Update last insn status. */
4102 arc_last_insns[1] = arc_last_insns[0];
4103 arc_last_insns[0].opcode = opcode;
4104 arc_last_insns[0].has_limm = insn->has_limm;
4105 arc_last_insns[0].has_delay_slot = has_delay_slot;
4106
4107 /* Check if the current instruction is legally used. */
4108 if (arc_last_insns[1].has_delay_slot
4109 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4110 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4111 arc_last_insns[1].opcode->name,
4112 arc_last_insns[0].opcode->name);
4113 }
4114
4115 void
4116 arc_handle_align (fragS* fragP)
4117 {
4118 if ((fragP)->fr_type == rs_align_code)
4119 {
4120 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4121 valueT count = ((fragP)->fr_next->fr_address
4122 - (fragP)->fr_address - (fragP)->fr_fix);
4123
4124 (fragP)->fr_var = 2;
4125
4126 if (count & 1)/* Padding in the gap till the next 2-byte
4127 boundary with 0s. */
4128 {
4129 (fragP)->fr_fix++;
4130 *dest++ = 0;
4131 }
4132 /* Writing nop_s. */
4133 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4134 }
4135 }
4136
4137 /* Here we decide which fixups can be adjusted to make them relative
4138 to the beginning of the section instead of the symbol. Basically
4139 we need to make sure that the dynamic relocations are done
4140 correctly, so in some cases we force the original symbol to be
4141 used. */
4142
4143 int
4144 tc_arc_fix_adjustable (fixS *fixP)
4145 {
4146
4147 /* Prevent all adjustments to global symbols. */
4148 if (S_IS_EXTERNAL (fixP->fx_addsy))
4149 return 0;
4150 if (S_IS_WEAK (fixP->fx_addsy))
4151 return 0;
4152
4153 /* Adjust_reloc_syms doesn't know about the GOT. */
4154 switch (fixP->fx_r_type)
4155 {
4156 case BFD_RELOC_ARC_GOTPC32:
4157 case BFD_RELOC_ARC_PLT32:
4158 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4159 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4160 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4161 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4162 return 0;
4163
4164 default:
4165 break;
4166 }
4167
4168 return 1;
4169 }
4170
4171 /* Compute the reloc type of an expression EXP. */
4172
4173 static void
4174 arc_check_reloc (expressionS *exp,
4175 bfd_reloc_code_real_type *r_type_p)
4176 {
4177 if (*r_type_p == BFD_RELOC_32
4178 && exp->X_op == O_subtract
4179 && exp->X_op_symbol != NULL
4180 && exp->X_op_symbol->bsym->section == now_seg)
4181 *r_type_p = BFD_RELOC_ARC_32_PCREL;
4182 }
4183
4184
4185 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4186
4187 void
4188 arc_cons_fix_new (fragS *frag,
4189 int off,
4190 int size,
4191 expressionS *exp,
4192 bfd_reloc_code_real_type r_type)
4193 {
4194 r_type = BFD_RELOC_UNUSED;
4195
4196 switch (size)
4197 {
4198 case 1:
4199 r_type = BFD_RELOC_8;
4200 break;
4201
4202 case 2:
4203 r_type = BFD_RELOC_16;
4204 break;
4205
4206 case 3:
4207 r_type = BFD_RELOC_24;
4208 break;
4209
4210 case 4:
4211 r_type = BFD_RELOC_32;
4212 arc_check_reloc (exp, &r_type);
4213 break;
4214
4215 case 8:
4216 r_type = BFD_RELOC_64;
4217 break;
4218
4219 default:
4220 as_bad (_("unsupported BFD relocation size %u"), size);
4221 r_type = BFD_RELOC_UNUSED;
4222 }
4223
4224 fix_new_exp (frag, off, size, exp, 0, r_type);
4225 }
4226
4227 /* The actual routine that checks the ZOL conditions. */
4228
4229 static void
4230 check_zol (symbolS *s)
4231 {
4232 switch (selected_cpu.mach)
4233 {
4234 case bfd_mach_arc_arcv2:
4235 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
4236 return;
4237
4238 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4239 || arc_last_insns[1].has_delay_slot)
4240 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4241 S_GET_NAME (s));
4242
4243 break;
4244 case bfd_mach_arc_arc600:
4245
4246 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4247 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4248 S_GET_NAME (s));
4249
4250 if (arc_last_insns[0].has_limm
4251 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4252 as_bad (_("A jump instruction with long immediate detected at the \
4253 end of the ZOL label @%s"), S_GET_NAME (s));
4254
4255 /* Fall through. */
4256 case bfd_mach_arc_arc700:
4257 if (arc_last_insns[0].has_delay_slot)
4258 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4259 S_GET_NAME (s));
4260
4261 break;
4262 default:
4263 break;
4264 }
4265 }
4266
4267 /* If ZOL end check the last two instruction for illegals. */
4268 void
4269 arc_frob_label (symbolS * sym)
4270 {
4271 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4272 check_zol (sym);
4273
4274 dwarf2_emit_label (sym);
4275 }
4276
4277 /* Used because generic relaxation assumes a pc-rel value whilst we
4278 also relax instructions that use an absolute value resolved out of
4279 relative values (if that makes any sense). An example: 'add r1,
4280 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4281 but if they're in the same section we can subtract the section
4282 offset relocation which ends up in a resolved value. So if @.L2 is
4283 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4284 .text + 0x40 = 0x10. */
4285 int
4286 arc_pcrel_adjust (fragS *fragP)
4287 {
4288 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4289 fragP->fr_address, fragP->fr_fix,
4290 fragP->tc_frag_data.pcrel ? "Y" : "N");
4291
4292 if (!fragP->tc_frag_data.pcrel)
4293 return fragP->fr_address + fragP->fr_fix;
4294
4295 /* Take into account the PCL rounding. */
4296 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4297 }
4298
4299 /* Initialize the DWARF-2 unwind information for this procedure. */
4300
4301 void
4302 tc_arc_frame_initial_instructions (void)
4303 {
4304 /* Stack pointer is register 28. */
4305 cfi_add_CFA_def_cfa (28, 0);
4306 }
4307
4308 int
4309 tc_arc_regname_to_dw2regnum (char *regname)
4310 {
4311 struct symbol *sym;
4312
4313 sym = hash_find (arc_reg_hash, regname);
4314 if (sym)
4315 return S_GET_VALUE (sym);
4316
4317 return -1;
4318 }
4319
4320 /* Adjust the symbol table. Delete found AUX register symbols. */
4321
4322 void
4323 arc_adjust_symtab (void)
4324 {
4325 symbolS * sym;
4326
4327 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4328 {
4329 /* I've created a symbol during parsing process. Now, remove
4330 the symbol as it is found to be an AUX register. */
4331 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4332 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4333 }
4334
4335 /* Now do generic ELF adjustments. */
4336 elf_adjust_symtab ();
4337 }
4338
4339 static void
4340 tokenize_extinsn (extInstruction_t *einsn)
4341 {
4342 char *p, c;
4343 char *insn_name;
4344 unsigned char major_opcode;
4345 unsigned char sub_opcode;
4346 unsigned char syntax_class = 0;
4347 unsigned char syntax_class_modifiers = 0;
4348 unsigned char suffix_class = 0;
4349 unsigned int i;
4350
4351 SKIP_WHITESPACE ();
4352
4353 /* 1st: get instruction name. */
4354 p = input_line_pointer;
4355 c = get_symbol_name (&p);
4356
4357 insn_name = xstrdup (p);
4358 restore_line_pointer (c);
4359
4360 /* 2nd: get major opcode. */
4361 if (*input_line_pointer != ',')
4362 {
4363 as_bad (_("expected comma after instruction name"));
4364 ignore_rest_of_line ();
4365 return;
4366 }
4367 input_line_pointer++;
4368 major_opcode = get_absolute_expression ();
4369
4370 /* 3rd: get sub-opcode. */
4371 SKIP_WHITESPACE ();
4372
4373 if (*input_line_pointer != ',')
4374 {
4375 as_bad (_("expected comma after major opcode"));
4376 ignore_rest_of_line ();
4377 return;
4378 }
4379 input_line_pointer++;
4380 sub_opcode = get_absolute_expression ();
4381
4382 /* 4th: get suffix class. */
4383 SKIP_WHITESPACE ();
4384
4385 if (*input_line_pointer != ',')
4386 {
4387 as_bad ("expected comma after sub opcode");
4388 ignore_rest_of_line ();
4389 return;
4390 }
4391 input_line_pointer++;
4392
4393 while (1)
4394 {
4395 SKIP_WHITESPACE ();
4396
4397 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4398 {
4399 if (!strncmp (suffixclass[i].name, input_line_pointer,
4400 suffixclass[i].len))
4401 {
4402 suffix_class |= suffixclass[i].attr_class;
4403 input_line_pointer += suffixclass[i].len;
4404 break;
4405 }
4406 }
4407
4408 if (i == ARRAY_SIZE (suffixclass))
4409 {
4410 as_bad ("invalid suffix class");
4411 ignore_rest_of_line ();
4412 return;
4413 }
4414
4415 SKIP_WHITESPACE ();
4416
4417 if (*input_line_pointer == '|')
4418 input_line_pointer++;
4419 else
4420 break;
4421 }
4422
4423 /* 5th: get syntax class and syntax class modifiers. */
4424 if (*input_line_pointer != ',')
4425 {
4426 as_bad ("expected comma after suffix class");
4427 ignore_rest_of_line ();
4428 return;
4429 }
4430 input_line_pointer++;
4431
4432 while (1)
4433 {
4434 SKIP_WHITESPACE ();
4435
4436 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4437 {
4438 if (!strncmp (syntaxclassmod[i].name,
4439 input_line_pointer,
4440 syntaxclassmod[i].len))
4441 {
4442 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
4443 input_line_pointer += syntaxclassmod[i].len;
4444 break;
4445 }
4446 }
4447
4448 if (i == ARRAY_SIZE (syntaxclassmod))
4449 {
4450 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4451 {
4452 if (!strncmp (syntaxclass[i].name,
4453 input_line_pointer,
4454 syntaxclass[i].len))
4455 {
4456 syntax_class |= syntaxclass[i].attr_class;
4457 input_line_pointer += syntaxclass[i].len;
4458 break;
4459 }
4460 }
4461
4462 if (i == ARRAY_SIZE (syntaxclass))
4463 {
4464 as_bad ("missing syntax class");
4465 ignore_rest_of_line ();
4466 return;
4467 }
4468 }
4469
4470 SKIP_WHITESPACE ();
4471
4472 if (*input_line_pointer == '|')
4473 input_line_pointer++;
4474 else
4475 break;
4476 }
4477
4478 demand_empty_rest_of_line ();
4479
4480 einsn->name = insn_name;
4481 einsn->major = major_opcode;
4482 einsn->minor = sub_opcode;
4483 einsn->syntax = syntax_class;
4484 einsn->modsyn = syntax_class_modifiers;
4485 einsn->suffix = suffix_class;
4486 einsn->flags = syntax_class
4487 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4488 }
4489
4490 /* Generate an extension section. */
4491
4492 static int
4493 arc_set_ext_seg (void)
4494 {
4495 if (!arcext_section)
4496 {
4497 arcext_section = subseg_new (".arcextmap", 0);
4498 bfd_set_section_flags (stdoutput, arcext_section,
4499 SEC_READONLY | SEC_HAS_CONTENTS);
4500 }
4501 else
4502 subseg_set (arcext_section, 0);
4503 return 1;
4504 }
4505
4506 /* Create an extension instruction description in the arc extension
4507 section of the output file.
4508 The structure for an instruction is like this:
4509 [0]: Length of the record.
4510 [1]: Type of the record.
4511
4512 [2]: Major opcode.
4513 [3]: Sub-opcode.
4514 [4]: Syntax (flags).
4515 [5]+ Name instruction.
4516
4517 The sequence is terminated by an empty entry. */
4518
4519 static void
4520 create_extinst_section (extInstruction_t *einsn)
4521 {
4522
4523 segT old_sec = now_seg;
4524 int old_subsec = now_subseg;
4525 char *p;
4526 int name_len = strlen (einsn->name);
4527
4528 arc_set_ext_seg ();
4529
4530 p = frag_more (1);
4531 *p = 5 + name_len + 1;
4532 p = frag_more (1);
4533 *p = EXT_INSTRUCTION;
4534 p = frag_more (1);
4535 *p = einsn->major;
4536 p = frag_more (1);
4537 *p = einsn->minor;
4538 p = frag_more (1);
4539 *p = einsn->flags;
4540 p = frag_more (name_len + 1);
4541 strcpy (p, einsn->name);
4542
4543 subseg_set (old_sec, old_subsec);
4544 }
4545
4546 /* Handler .extinstruction pseudo-op. */
4547
4548 static void
4549 arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4550 {
4551 extInstruction_t einsn;
4552 struct arc_opcode *arc_ext_opcodes;
4553 const char *errmsg = NULL;
4554 unsigned char moplow, mophigh;
4555
4556 memset (&einsn, 0, sizeof (einsn));
4557 tokenize_extinsn (&einsn);
4558
4559 /* Check if the name is already used. */
4560 if (arc_find_opcode (einsn.name))
4561 as_warn (_("Pseudocode already used %s"), einsn.name);
4562
4563 /* Check the opcode ranges. */
4564 moplow = 0x05;
4565 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4566 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
4567
4568 if ((einsn.major > mophigh) || (einsn.major < moplow))
4569 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4570
4571 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4572 && (einsn.major != 5) && (einsn.major != 9))
4573 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4574
4575 switch (einsn.syntax & ARC_SYNTAX_MASK)
4576 {
4577 case ARC_SYNTAX_3OP:
4578 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4579 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4580 break;
4581 case ARC_SYNTAX_2OP:
4582 case ARC_SYNTAX_1OP:
4583 case ARC_SYNTAX_NOP:
4584 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4585 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4586 break;
4587 default:
4588 break;
4589 }
4590
4591 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
4592 if (arc_ext_opcodes == NULL)
4593 {
4594 if (errmsg)
4595 as_fatal ("%s", errmsg);
4596 else
4597 as_fatal (_("Couldn't generate extension instruction opcodes"));
4598 }
4599 else if (errmsg)
4600 as_warn ("%s", errmsg);
4601
4602 /* Insert the extension instruction. */
4603 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4604
4605 create_extinst_section (&einsn);
4606 }
4607
4608 static bfd_boolean
4609 tokenize_extregister (extRegister_t *ereg, int opertype)
4610 {
4611 char *name;
4612 char *mode;
4613 char c;
4614 char *p;
4615 int number, imode = 0;
4616 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4617 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4618 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4619
4620 /* 1st: get register name. */
4621 SKIP_WHITESPACE ();
4622 p = input_line_pointer;
4623 c = get_symbol_name (&p);
4624
4625 name = xstrdup (p);
4626 restore_line_pointer (c);
4627
4628 /* 2nd: get register number. */
4629 SKIP_WHITESPACE ();
4630
4631 if (*input_line_pointer != ',')
4632 {
4633 as_bad (_("expected comma after name"));
4634 ignore_rest_of_line ();
4635 free (name);
4636 return FALSE;
4637 }
4638 input_line_pointer++;
4639 number = get_absolute_expression ();
4640
4641 if ((number < 0)
4642 && (opertype != EXT_AUX_REGISTER))
4643 {
4644 as_bad (_("%s second argument cannot be a negative number %d"),
4645 isCore_p ? "extCoreRegister's" : "extCondCode's",
4646 number);
4647 ignore_rest_of_line ();
4648 free (name);
4649 return FALSE;
4650 }
4651
4652 if (isReg_p)
4653 {
4654 /* 3rd: get register mode. */
4655 SKIP_WHITESPACE ();
4656
4657 if (*input_line_pointer != ',')
4658 {
4659 as_bad (_("expected comma after register number"));
4660 ignore_rest_of_line ();
4661 free (name);
4662 return FALSE;
4663 }
4664
4665 input_line_pointer++;
4666 mode = input_line_pointer;
4667
4668 if (!strncmp (mode, "r|w", 3))
4669 {
4670 imode = 0;
4671 input_line_pointer += 3;
4672 }
4673 else if (!strncmp (mode, "r", 1))
4674 {
4675 imode = ARC_REGISTER_READONLY;
4676 input_line_pointer += 1;
4677 }
4678 else if (strncmp (mode, "w", 1))
4679 {
4680 as_bad (_("invalid mode"));
4681 ignore_rest_of_line ();
4682 free (name);
4683 return FALSE;
4684 }
4685 else
4686 {
4687 imode = ARC_REGISTER_WRITEONLY;
4688 input_line_pointer += 1;
4689 }
4690 }
4691
4692 if (isCore_p)
4693 {
4694 /* 4th: get core register shortcut. */
4695 SKIP_WHITESPACE ();
4696 if (*input_line_pointer != ',')
4697 {
4698 as_bad (_("expected comma after register mode"));
4699 ignore_rest_of_line ();
4700 free (name);
4701 return FALSE;
4702 }
4703
4704 input_line_pointer++;
4705
4706 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4707 {
4708 imode |= ARC_REGISTER_NOSHORT_CUT;
4709 input_line_pointer += 15;
4710 }
4711 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4712 {
4713 as_bad (_("shortcut designator invalid"));
4714 ignore_rest_of_line ();
4715 free (name);
4716 return FALSE;
4717 }
4718 else
4719 {
4720 input_line_pointer += 12;
4721 }
4722 }
4723 demand_empty_rest_of_line ();
4724
4725 ereg->name = name;
4726 ereg->number = number;
4727 ereg->imode = imode;
4728 return TRUE;
4729 }
4730
4731 /* Create an extension register/condition description in the arc
4732 extension section of the output file.
4733
4734 The structure for an instruction is like this:
4735 [0]: Length of the record.
4736 [1]: Type of the record.
4737
4738 For core regs and condition codes:
4739 [2]: Value.
4740 [3]+ Name.
4741
4742 For auxiliary registers:
4743 [2..5]: Value.
4744 [6]+ Name
4745
4746 The sequence is terminated by an empty entry. */
4747
4748 static void
4749 create_extcore_section (extRegister_t *ereg, int opertype)
4750 {
4751 segT old_sec = now_seg;
4752 int old_subsec = now_subseg;
4753 char *p;
4754 int name_len = strlen (ereg->name);
4755
4756 arc_set_ext_seg ();
4757
4758 switch (opertype)
4759 {
4760 case EXT_COND_CODE:
4761 case EXT_CORE_REGISTER:
4762 p = frag_more (1);
4763 *p = 3 + name_len + 1;
4764 p = frag_more (1);
4765 *p = opertype;
4766 p = frag_more (1);
4767 *p = ereg->number;
4768 break;
4769 case EXT_AUX_REGISTER:
4770 p = frag_more (1);
4771 *p = 6 + name_len + 1;
4772 p = frag_more (1);
4773 *p = EXT_AUX_REGISTER;
4774 p = frag_more (1);
4775 *p = (ereg->number >> 24) & 0xff;
4776 p = frag_more (1);
4777 *p = (ereg->number >> 16) & 0xff;
4778 p = frag_more (1);
4779 *p = (ereg->number >> 8) & 0xff;
4780 p = frag_more (1);
4781 *p = (ereg->number) & 0xff;
4782 break;
4783 default:
4784 break;
4785 }
4786
4787 p = frag_more (name_len + 1);
4788 strcpy (p, ereg->name);
4789
4790 subseg_set (old_sec, old_subsec);
4791 }
4792
4793 /* Handler .extCoreRegister pseudo-op. */
4794
4795 static void
4796 arc_extcorereg (int opertype)
4797 {
4798 extRegister_t ereg;
4799 struct arc_aux_reg *auxr;
4800 const char *retval;
4801 struct arc_flag_operand *ccode;
4802
4803 memset (&ereg, 0, sizeof (ereg));
4804 if (!tokenize_extregister (&ereg, opertype))
4805 return;
4806
4807 switch (opertype)
4808 {
4809 case EXT_CORE_REGISTER:
4810 /* Core register. */
4811 if (ereg.number > 60)
4812 as_bad (_("core register %s value (%d) too large"), ereg.name,
4813 ereg.number);
4814 declare_register (ereg.name, ereg.number);
4815 break;
4816 case EXT_AUX_REGISTER:
4817 /* Auxiliary register. */
4818 auxr = XNEW (struct arc_aux_reg);
4819 auxr->name = ereg.name;
4820 auxr->cpu = selected_cpu.flags;
4821 auxr->subclass = NONE;
4822 auxr->address = ereg.number;
4823 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4824 if (retval)
4825 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4826 auxr->name, retval);
4827 break;
4828 case EXT_COND_CODE:
4829 /* Condition code. */
4830 if (ereg.number > 31)
4831 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4832 ereg.number);
4833 ext_condcode.size ++;
4834 ext_condcode.arc_ext_condcode =
4835 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4836 ext_condcode.size + 1);
4837 if (ext_condcode.arc_ext_condcode == NULL)
4838 as_fatal (_("Virtual memory exhausted"));
4839
4840 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4841 ccode->name = ereg.name;
4842 ccode->code = ereg.number;
4843 ccode->bits = 5;
4844 ccode->shift = 0;
4845 ccode->favail = 0; /* not used. */
4846 ccode++;
4847 memset (ccode, 0, sizeof (struct arc_flag_operand));
4848 break;
4849 default:
4850 as_bad (_("Unknown extension"));
4851 break;
4852 }
4853 create_extcore_section (&ereg, opertype);
4854 }
4855
4856 /* Parse a .arc_attribute directive. */
4857
4858 static void
4859 arc_attribute (int ignored ATTRIBUTE_UNUSED)
4860 {
4861 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4862
4863 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4864 attributes_set_explicitly[tag] = TRUE;
4865 }
4866
4867 /* Set an attribute if it has not already been set by the user. */
4868
4869 static void
4870 arc_set_attribute_int (int tag, int value)
4871 {
4872 if (tag < 1
4873 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4874 || !attributes_set_explicitly[tag])
4875 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4876 }
4877
4878 static void
4879 arc_set_attribute_string (int tag, const char *value)
4880 {
4881 if (tag < 1
4882 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4883 || !attributes_set_explicitly[tag])
4884 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4885 }
4886
4887 /* Allocate and concatenate two strings. s1 can be NULL but not
4888 s2. s1 pointer is freed at end of this procedure. */
4889
4890 static char *
4891 arc_stralloc (char * s1, const char * s2)
4892 {
4893 char * p;
4894 int len = 0;
4895
4896 if (s1)
4897 len = strlen (s1) + 1;
4898
4899 /* Only s1 can be null. */
4900 gas_assert (s2);
4901 len += strlen (s2) + 1;
4902
4903 p = (char *) xmalloc (len);
4904 if (p == NULL)
4905 as_fatal (_("Virtual memory exhausted"));
4906
4907 if (s1)
4908 {
4909 strcpy (p, s1);
4910 strcat (p, ",");
4911 strcat (p, s2);
4912 free (s1);
4913 }
4914 else
4915 strcpy (p, s2);
4916
4917 return p;
4918 }
4919
4920 /* Set the public ARC object attributes. */
4921
4922 static void
4923 arc_set_public_attributes (void)
4924 {
4925 int base = 0;
4926 char *s = NULL;
4927 unsigned int i;
4928
4929 /* Tag_ARC_CPU_name. */
4930 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4931
4932 /* Tag_ARC_CPU_base. */
4933 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4934 {
4935 case E_ARC_MACH_ARC600:
4936 case E_ARC_MACH_ARC601:
4937 base = TAG_CPU_ARC6xx;
4938 break;
4939 case E_ARC_MACH_ARC700:
4940 base = TAG_CPU_ARC7xx;
4941 break;
4942 case EF_ARC_CPU_ARCV2EM:
4943 base = TAG_CPU_ARCEM;
4944 break;
4945 case EF_ARC_CPU_ARCV2HS:
4946 base = TAG_CPU_ARCHS;
4947 break;
4948 default:
4949 base = 0;
4950 break;
4951 }
4952 if (attributes_set_explicitly[Tag_ARC_CPU_base]
4953 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4954 Tag_ARC_CPU_base)))
4955 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4956 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
4957
4958 /* Tag_ARC_ABI_osver. */
4959 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
4960 {
4961 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4962 Tag_ARC_ABI_osver);
4963
4964 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
4965 | (val & 0x0f << 8));
4966 }
4967 else
4968 {
4969 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
4970 }
4971
4972 /* Tag_ARC_ISA_config. */
4973 arc_check_feature();
4974
4975 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
4976 if (selected_cpu.features & feature_list[i].feature)
4977 s = arc_stralloc (s, feature_list[i].attr);
4978
4979 if (s)
4980 arc_set_attribute_string (Tag_ARC_ISA_config, s);
4981
4982 /* Tag_ARC_ISA_mpy_option. */
4983 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
4984
4985 /* Tag_ARC_ABI_pic. */
4986 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
4987
4988 /* Tag_ARC_ABI_sda. */
4989 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
4990
4991 /* Tag_ARC_ABI_tls. */
4992 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
4993 }
4994
4995 /* Add the default contents for the .ARC.attributes section. */
4996
4997 void
4998 arc_md_end (void)
4999 {
5000 arc_set_public_attributes ();
5001
5002 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5003 as_fatal (_("could not set architecture and machine"));
5004
5005 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5006 }
5007
5008 void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5009 {
5010 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5011 }
5012
5013 int arc_convert_symbolic_attribute (const char *name)
5014 {
5015 static const struct
5016 {
5017 const char * name;
5018 const int tag;
5019 }
5020 attribute_table[] =
5021 {
5022 #define T(tag) {#tag, tag}
5023 T (Tag_ARC_PCS_config),
5024 T (Tag_ARC_CPU_base),
5025 T (Tag_ARC_CPU_variation),
5026 T (Tag_ARC_CPU_name),
5027 T (Tag_ARC_ABI_rf16),
5028 T (Tag_ARC_ABI_osver),
5029 T (Tag_ARC_ABI_sda),
5030 T (Tag_ARC_ABI_pic),
5031 T (Tag_ARC_ABI_tls),
5032 T (Tag_ARC_ABI_enumsize),
5033 T (Tag_ARC_ABI_exceptions),
5034 T (Tag_ARC_ABI_double_size),
5035 T (Tag_ARC_ISA_config),
5036 T (Tag_ARC_ISA_apex),
5037 T (Tag_ARC_ISA_mpy_option)
5038 #undef T
5039 };
5040 unsigned int i;
5041
5042 if (name == NULL)
5043 return -1;
5044
5045 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5046 if (streq (name, attribute_table[i].name))
5047 return attribute_table[i].tag;
5048
5049 return -1;
5050 }
5051
5052 /* Local variables:
5053 eval: (c-set-style "gnu")
5054 indent-tabs-mode: t
5055 End: */
GDB Binutils - Deliverables
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