1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_arch_any
= ARM_ANY
;
239 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
240 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
241 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
243 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
246 static const arm_feature_set arm_cext_iwmmxt2
=
247 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
248 static const arm_feature_set arm_cext_iwmmxt
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
250 static const arm_feature_set arm_cext_xscale
=
251 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
252 static const arm_feature_set arm_cext_maverick
=
253 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
254 static const arm_feature_set fpu_fpa_ext_v1
=
255 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
256 static const arm_feature_set fpu_fpa_ext_v2
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
258 static const arm_feature_set fpu_vfp_ext_v1xd
=
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
260 static const arm_feature_set fpu_vfp_ext_v1
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
262 static const arm_feature_set fpu_vfp_ext_v2
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
264 static const arm_feature_set fpu_vfp_ext_v3xd
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
266 static const arm_feature_set fpu_vfp_ext_v3
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
268 static const arm_feature_set fpu_vfp_ext_d32
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
270 static const arm_feature_set fpu_neon_ext_v1
=
271 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
272 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
275 static const arm_feature_set fpu_vfp_fp16
=
276 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
277 static const arm_feature_set fpu_neon_ext_fma
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
280 static const arm_feature_set fpu_vfp_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_armv8
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
284 static const arm_feature_set fpu_vfp_ext_armv8xd
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
286 static const arm_feature_set fpu_neon_ext_armv8
=
287 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
288 static const arm_feature_set fpu_crypto_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
290 static const arm_feature_set crc_ext_armv8
=
291 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
292 static const arm_feature_set fpu_neon_ext_v8_1
=
293 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
295 static int mfloat_abi_opt
= -1;
296 /* Record user cpu selection for object attributes. */
297 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
298 /* Must be long enough to hold any of the names in arm_cpus. */
299 static char selected_cpu_name
[20];
301 extern FLONUM_TYPE generic_floating_point_number
;
303 /* Return if no cpu was selected on command-line. */
305 no_cpu_selected (void)
307 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
312 static int meabi_flags
= EABI_DEFAULT
;
314 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
317 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
322 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
327 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
328 symbolS
* GOT_symbol
;
331 /* 0: assemble for ARM,
332 1: assemble for Thumb,
333 2: assemble for Thumb even though target CPU does not support thumb
335 static int thumb_mode
= 0;
336 /* A value distinct from the possible values for thumb_mode that we
337 can use to record whether thumb_mode has been copied into the
338 tc_frag_data field of a frag. */
339 #define MODE_RECORDED (1 << 4)
341 /* Specifies the intrinsic IT insn behavior mode. */
342 enum implicit_it_mode
344 IMPLICIT_IT_MODE_NEVER
= 0x00,
345 IMPLICIT_IT_MODE_ARM
= 0x01,
346 IMPLICIT_IT_MODE_THUMB
= 0x02,
347 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
349 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
351 /* If unified_syntax is true, we are processing the new unified
352 ARM/Thumb syntax. Important differences from the old ARM mode:
354 - Immediate operands do not require a # prefix.
355 - Conditional affixes always appear at the end of the
356 instruction. (For backward compatibility, those instructions
357 that formerly had them in the middle, continue to accept them
359 - The IT instruction may appear, and if it does is validated
360 against subsequent conditional affixes. It does not generate
363 Important differences from the old Thumb mode:
365 - Immediate operands do not require a # prefix.
366 - Most of the V6T2 instructions are only available in unified mode.
367 - The .N and .W suffixes are recognized and honored (it is an error
368 if they cannot be honored).
369 - All instructions set the flags if and only if they have an 's' affix.
370 - Conditional affixes may be used. They are validated against
371 preceding IT instructions. Unlike ARM mode, you cannot use a
372 conditional affix except in the scope of an IT instruction. */
374 static bfd_boolean unified_syntax
= FALSE
;
376 /* An immediate operand can start with #, and ld*, st*, pld operands
377 can contain [ and ]. We need to tell APP not to elide whitespace
378 before a [, which can appear as the first operand for pld.
379 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
380 const char arm_symbol_chars
[] = "#[]{}";
395 enum neon_el_type type
;
399 #define NEON_MAX_TYPE_ELS 4
403 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
407 enum it_instruction_type
412 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
413 if inside, should be the last one. */
414 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
415 i.e. BKPT and NOP. */
416 IT_INSN
/* The IT insn has been parsed. */
419 /* The maximum number of operands we need. */
420 #define ARM_IT_MAX_OPERANDS 6
425 unsigned long instruction
;
429 /* "uncond_value" is set to the value in place of the conditional field in
430 unconditional versions of the instruction, or -1 if nothing is
433 struct neon_type vectype
;
434 /* This does not indicate an actual NEON instruction, only that
435 the mnemonic accepts neon-style type suffixes. */
437 /* Set to the opcode if the instruction needs relaxation.
438 Zero if the instruction is not relaxed. */
442 bfd_reloc_code_real_type type
;
447 enum it_instruction_type it_insn_type
;
453 struct neon_type_el vectype
;
454 unsigned present
: 1; /* Operand present. */
455 unsigned isreg
: 1; /* Operand was a register. */
456 unsigned immisreg
: 1; /* .imm field is a second register. */
457 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
458 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
459 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
460 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
461 instructions. This allows us to disambiguate ARM <-> vector insns. */
462 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
463 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
464 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
465 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
466 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
467 unsigned writeback
: 1; /* Operand has trailing ! */
468 unsigned preind
: 1; /* Preindexed address. */
469 unsigned postind
: 1; /* Postindexed address. */
470 unsigned negative
: 1; /* Index register was negated. */
471 unsigned shifted
: 1; /* Shift applied to operation. */
472 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
473 } operands
[ARM_IT_MAX_OPERANDS
];
476 static struct arm_it inst
;
478 #define NUM_FLOAT_VALS 8
480 const char * fp_const
[] =
482 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
485 /* Number of littlenums required to hold an extended precision number. */
486 #define MAX_LITTLENUMS 6
488 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
498 #define CP_T_X 0x00008000
499 #define CP_T_Y 0x00400000
501 #define CONDS_BIT 0x00100000
502 #define LOAD_BIT 0x00100000
504 #define DOUBLE_LOAD_FLAG 0x00000001
508 const char * template_name
;
512 #define COND_ALWAYS 0xE
516 const char * template_name
;
520 struct asm_barrier_opt
522 const char * template_name
;
524 const arm_feature_set arch
;
527 /* The bit that distinguishes CPSR and SPSR. */
528 #define SPSR_BIT (1 << 22)
530 /* The individual PSR flag bits. */
531 #define PSR_c (1 << 16)
532 #define PSR_x (1 << 17)
533 #define PSR_s (1 << 18)
534 #define PSR_f (1 << 19)
539 bfd_reloc_code_real_type reloc
;
544 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
545 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
550 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
553 /* Bits for DEFINED field in neon_typed_alias. */
554 #define NTA_HASTYPE 1
555 #define NTA_HASINDEX 2
557 struct neon_typed_alias
559 unsigned char defined
;
561 struct neon_type_el eltype
;
564 /* ARM register categories. This includes coprocessor numbers and various
565 architecture extensions' registers. */
592 /* Structure for a hash table entry for a register.
593 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
594 information which states whether a vector type or index is specified (for a
595 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
601 unsigned char builtin
;
602 struct neon_typed_alias
* neon
;
605 /* Diagnostics used when we don't get a register of the expected type. */
606 const char * const reg_expected_msgs
[] =
608 N_("ARM register expected"),
609 N_("bad or missing co-processor number"),
610 N_("co-processor register expected"),
611 N_("FPA register expected"),
612 N_("VFP single precision register expected"),
613 N_("VFP/Neon double precision register expected"),
614 N_("Neon quad precision register expected"),
615 N_("VFP single or double precision register expected"),
616 N_("Neon double or quad precision register expected"),
617 N_("VFP single, double or Neon quad precision register expected"),
618 N_("VFP system register expected"),
619 N_("Maverick MVF register expected"),
620 N_("Maverick MVD register expected"),
621 N_("Maverick MVFX register expected"),
622 N_("Maverick MVDX register expected"),
623 N_("Maverick MVAX register expected"),
624 N_("Maverick DSPSC register expected"),
625 N_("iWMMXt data register expected"),
626 N_("iWMMXt control register expected"),
627 N_("iWMMXt scalar register expected"),
628 N_("XScale accumulator register expected"),
631 /* Some well known registers that we refer to directly elsewhere. */
637 /* ARM instructions take 4bytes in the object file, Thumb instructions
643 /* Basic string to match. */
644 const char * template_name
;
646 /* Parameters to instruction. */
647 unsigned int operands
[8];
649 /* Conditional tag - see opcode_lookup. */
650 unsigned int tag
: 4;
652 /* Basic instruction code. */
653 unsigned int avalue
: 28;
655 /* Thumb-format instruction code. */
658 /* Which architecture variant provides this instruction. */
659 const arm_feature_set
* avariant
;
660 const arm_feature_set
* tvariant
;
662 /* Function to call to encode instruction in ARM format. */
663 void (* aencode
) (void);
665 /* Function to call to encode instruction in Thumb format. */
666 void (* tencode
) (void);
669 /* Defines for various bits that we will want to toggle. */
670 #define INST_IMMEDIATE 0x02000000
671 #define OFFSET_REG 0x02000000
672 #define HWOFFSET_IMM 0x00400000
673 #define SHIFT_BY_REG 0x00000010
674 #define PRE_INDEX 0x01000000
675 #define INDEX_UP 0x00800000
676 #define WRITE_BACK 0x00200000
677 #define LDM_TYPE_2_OR_3 0x00400000
678 #define CPSI_MMOD 0x00020000
680 #define LITERAL_MASK 0xf000f000
681 #define OPCODE_MASK 0xfe1fffff
682 #define V4_STR_BIT 0x00000020
683 #define VLDR_VMOV_SAME 0x0040f000
685 #define T2_SUBS_PC_LR 0xf3de8f00
687 #define DATA_OP_SHIFT 21
689 #define T2_OPCODE_MASK 0xfe1fffff
690 #define T2_DATA_OP_SHIFT 21
692 #define A_COND_MASK 0xf0000000
693 #define A_PUSH_POP_OP_MASK 0x0fff0000
695 /* Opcodes for pushing/poping registers to/from the stack. */
696 #define A1_OPCODE_PUSH 0x092d0000
697 #define A2_OPCODE_PUSH 0x052d0004
698 #define A2_OPCODE_POP 0x049d0004
700 /* Codes to distinguish the arithmetic instructions. */
711 #define OPCODE_CMP 10
712 #define OPCODE_CMN 11
713 #define OPCODE_ORR 12
714 #define OPCODE_MOV 13
715 #define OPCODE_BIC 14
716 #define OPCODE_MVN 15
718 #define T2_OPCODE_AND 0
719 #define T2_OPCODE_BIC 1
720 #define T2_OPCODE_ORR 2
721 #define T2_OPCODE_ORN 3
722 #define T2_OPCODE_EOR 4
723 #define T2_OPCODE_ADD 8
724 #define T2_OPCODE_ADC 10
725 #define T2_OPCODE_SBC 11
726 #define T2_OPCODE_SUB 13
727 #define T2_OPCODE_RSB 14
729 #define T_OPCODE_MUL 0x4340
730 #define T_OPCODE_TST 0x4200
731 #define T_OPCODE_CMN 0x42c0
732 #define T_OPCODE_NEG 0x4240
733 #define T_OPCODE_MVN 0x43c0
735 #define T_OPCODE_ADD_R3 0x1800
736 #define T_OPCODE_SUB_R3 0x1a00
737 #define T_OPCODE_ADD_HI 0x4400
738 #define T_OPCODE_ADD_ST 0xb000
739 #define T_OPCODE_SUB_ST 0xb080
740 #define T_OPCODE_ADD_SP 0xa800
741 #define T_OPCODE_ADD_PC 0xa000
742 #define T_OPCODE_ADD_I8 0x3000
743 #define T_OPCODE_SUB_I8 0x3800
744 #define T_OPCODE_ADD_I3 0x1c00
745 #define T_OPCODE_SUB_I3 0x1e00
747 #define T_OPCODE_ASR_R 0x4100
748 #define T_OPCODE_LSL_R 0x4080
749 #define T_OPCODE_LSR_R 0x40c0
750 #define T_OPCODE_ROR_R 0x41c0
751 #define T_OPCODE_ASR_I 0x1000
752 #define T_OPCODE_LSL_I 0x0000
753 #define T_OPCODE_LSR_I 0x0800
755 #define T_OPCODE_MOV_I8 0x2000
756 #define T_OPCODE_CMP_I8 0x2800
757 #define T_OPCODE_CMP_LR 0x4280
758 #define T_OPCODE_MOV_HR 0x4600
759 #define T_OPCODE_CMP_HR 0x4500
761 #define T_OPCODE_LDR_PC 0x4800
762 #define T_OPCODE_LDR_SP 0x9800
763 #define T_OPCODE_STR_SP 0x9000
764 #define T_OPCODE_LDR_IW 0x6800
765 #define T_OPCODE_STR_IW 0x6000
766 #define T_OPCODE_LDR_IH 0x8800
767 #define T_OPCODE_STR_IH 0x8000
768 #define T_OPCODE_LDR_IB 0x7800
769 #define T_OPCODE_STR_IB 0x7000
770 #define T_OPCODE_LDR_RW 0x5800
771 #define T_OPCODE_STR_RW 0x5000
772 #define T_OPCODE_LDR_RH 0x5a00
773 #define T_OPCODE_STR_RH 0x5200
774 #define T_OPCODE_LDR_RB 0x5c00
775 #define T_OPCODE_STR_RB 0x5400
777 #define T_OPCODE_PUSH 0xb400
778 #define T_OPCODE_POP 0xbc00
780 #define T_OPCODE_BRANCH 0xe000
782 #define THUMB_SIZE 2 /* Size of thumb instruction. */
783 #define THUMB_PP_PC_LR 0x0100
784 #define THUMB_LOAD_BIT 0x0800
785 #define THUMB2_LOAD_BIT 0x00100000
787 #define BAD_ARGS _("bad arguments to instruction")
788 #define BAD_SP _("r13 not allowed here")
789 #define BAD_PC _("r15 not allowed here")
790 #define BAD_COND _("instruction cannot be conditional")
791 #define BAD_OVERLAP _("registers may not be the same")
792 #define BAD_HIREG _("lo register required")
793 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
794 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
795 #define BAD_BRANCH _("branch must be last instruction in IT block")
796 #define BAD_NOT_IT _("instruction not allowed in IT block")
797 #define BAD_FPU _("selected FPU does not support instruction")
798 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
799 #define BAD_IT_COND _("incorrect condition in IT block")
800 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
801 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
802 #define BAD_PC_ADDRESSING \
803 _("cannot use register index with PC-relative addressing")
804 #define BAD_PC_WRITEBACK \
805 _("cannot use writeback with PC-relative addressing")
806 #define BAD_RANGE _("branch out of range")
807 #define BAD_FP16 _("selected processor does not support fp16 instruction")
808 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
809 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
811 static struct hash_control
* arm_ops_hsh
;
812 static struct hash_control
* arm_cond_hsh
;
813 static struct hash_control
* arm_shift_hsh
;
814 static struct hash_control
* arm_psr_hsh
;
815 static struct hash_control
* arm_v7m_psr_hsh
;
816 static struct hash_control
* arm_reg_hsh
;
817 static struct hash_control
* arm_reloc_hsh
;
818 static struct hash_control
* arm_barrier_opt_hsh
;
820 /* Stuff needed to resolve the label ambiguity
829 symbolS
* last_label_seen
;
830 static int label_is_thumb_function_name
= FALSE
;
832 /* Literal pool structure. Held on a per-section
833 and per-sub-section basis. */
835 #define MAX_LITERAL_POOL_SIZE 1024
836 typedef struct literal_pool
838 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
839 unsigned int next_free_entry
;
845 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
847 struct literal_pool
* next
;
848 unsigned int alignment
;
851 /* Pointer to a linked list of literal pools. */
852 literal_pool
* list_of_pools
= NULL
;
854 typedef enum asmfunc_states
857 WAITING_ASMFUNC_NAME
,
861 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
864 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
866 static struct current_it now_it
;
870 now_it_compatible (int cond
)
872 return (cond
& ~1) == (now_it
.cc
& ~1);
876 conditional_insn (void)
878 return inst
.cond
!= COND_ALWAYS
;
881 static int in_it_block (void);
883 static int handle_it_state (void);
885 static void force_automatic_it_block_close (void);
887 static void it_fsm_post_encode (void);
889 #define set_it_insn_type(type) \
892 inst.it_insn_type = type; \
893 if (handle_it_state () == FAIL) \
898 #define set_it_insn_type_nonvoid(type, failret) \
901 inst.it_insn_type = type; \
902 if (handle_it_state () == FAIL) \
907 #define set_it_insn_type_last() \
910 if (inst.cond == COND_ALWAYS) \
911 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
913 set_it_insn_type (INSIDE_IT_LAST_INSN); \
919 /* This array holds the chars that always start a comment. If the
920 pre-processor is disabled, these aren't very useful. */
921 char arm_comment_chars
[] = "@";
923 /* This array holds the chars that only start a comment at the beginning of
924 a line. If the line seems to have the form '# 123 filename'
925 .line and .file directives will appear in the pre-processed output. */
926 /* Note that input_file.c hand checks for '#' at the beginning of the
927 first line of the input file. This is because the compiler outputs
928 #NO_APP at the beginning of its output. */
929 /* Also note that comments like this one will always work. */
930 const char line_comment_chars
[] = "#";
932 char arm_line_separator_chars
[] = ";";
934 /* Chars that can be used to separate mant
935 from exp in floating point numbers. */
936 const char EXP_CHARS
[] = "eE";
938 /* Chars that mean this number is a floating point constant. */
942 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
944 /* Prefix characters that indicate the start of an immediate
946 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
948 /* Separator character handling. */
950 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
953 skip_past_char (char ** str
, char c
)
955 /* PR gas/14987: Allow for whitespace before the expected character. */
956 skip_whitespace (*str
);
967 #define skip_past_comma(str) skip_past_char (str, ',')
969 /* Arithmetic expressions (possibly involving symbols). */
971 /* Return TRUE if anything in the expression is a bignum. */
974 walk_no_bignums (symbolS
* sp
)
976 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
979 if (symbol_get_value_expression (sp
)->X_add_symbol
)
981 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
982 || (symbol_get_value_expression (sp
)->X_op_symbol
983 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
989 static int in_my_get_expression
= 0;
991 /* Third argument to my_get_expression. */
992 #define GE_NO_PREFIX 0
993 #define GE_IMM_PREFIX 1
994 #define GE_OPT_PREFIX 2
995 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
996 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
997 #define GE_OPT_PREFIX_BIG 3
1000 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1005 /* In unified syntax, all prefixes are optional. */
1007 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1010 switch (prefix_mode
)
1012 case GE_NO_PREFIX
: break;
1014 if (!is_immediate_prefix (**str
))
1016 inst
.error
= _("immediate expression requires a # prefix");
1022 case GE_OPT_PREFIX_BIG
:
1023 if (is_immediate_prefix (**str
))
1029 memset (ep
, 0, sizeof (expressionS
));
1031 save_in
= input_line_pointer
;
1032 input_line_pointer
= *str
;
1033 in_my_get_expression
= 1;
1034 seg
= expression (ep
);
1035 in_my_get_expression
= 0;
1037 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1039 /* We found a bad or missing expression in md_operand(). */
1040 *str
= input_line_pointer
;
1041 input_line_pointer
= save_in
;
1042 if (inst
.error
== NULL
)
1043 inst
.error
= (ep
->X_op
== O_absent
1044 ? _("missing expression") :_("bad expression"));
1049 if (seg
!= absolute_section
1050 && seg
!= text_section
1051 && seg
!= data_section
1052 && seg
!= bss_section
1053 && seg
!= undefined_section
)
1055 inst
.error
= _("bad segment");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1064 /* Get rid of any bignums now, so that we don't generate an error for which
1065 we can't establish a line number later on. Big numbers are never valid
1066 in instructions, which is where this routine is always called. */
1067 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1068 && (ep
->X_op
== O_big
1069 || (ep
->X_add_symbol
1070 && (walk_no_bignums (ep
->X_add_symbol
)
1072 && walk_no_bignums (ep
->X_op_symbol
))))))
1074 inst
.error
= _("invalid constant");
1075 *str
= input_line_pointer
;
1076 input_line_pointer
= save_in
;
1080 *str
= input_line_pointer
;
1081 input_line_pointer
= save_in
;
1085 /* Turn a string in input_line_pointer into a floating point constant
1086 of type TYPE, and store the appropriate bytes in *LITP. The number
1087 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1088 returned, or NULL on OK.
1090 Note that fp constants aren't represent in the normal way on the ARM.
1091 In big endian mode, things are as expected. However, in little endian
1092 mode fp constants are big-endian word-wise, and little-endian byte-wise
1093 within the words. For example, (double) 1.1 in big endian mode is
1094 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1095 the byte sequence 99 99 f1 3f 9a 99 99 99.
1097 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1100 md_atof (int type
, char * litP
, int * sizeP
)
1103 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1135 return _("Unrecognized or unsupported floating point constant");
1138 t
= atof_ieee (input_line_pointer
, type
, words
);
1140 input_line_pointer
= t
;
1141 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1143 if (target_big_endian
)
1145 for (i
= 0; i
< prec
; i
++)
1147 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1148 litP
+= sizeof (LITTLENUM_TYPE
);
1153 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1154 for (i
= prec
- 1; i
>= 0; i
--)
1156 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1157 litP
+= sizeof (LITTLENUM_TYPE
);
1160 /* For a 4 byte float the order of elements in `words' is 1 0.
1161 For an 8 byte float the order is 1 0 3 2. */
1162 for (i
= 0; i
< prec
; i
+= 2)
1164 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1165 sizeof (LITTLENUM_TYPE
));
1166 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1167 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1168 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1175 /* We handle all bad expressions here, so that we can report the faulty
1176 instruction in the error message. */
1178 md_operand (expressionS
* exp
)
1180 if (in_my_get_expression
)
1181 exp
->X_op
= O_illegal
;
1184 /* Immediate values. */
1186 /* Generic immediate-value read function for use in directives.
1187 Accepts anything that 'expression' can fold to a constant.
1188 *val receives the number. */
1191 immediate_for_directive (int *val
)
1194 exp
.X_op
= O_illegal
;
1196 if (is_immediate_prefix (*input_line_pointer
))
1198 input_line_pointer
++;
1202 if (exp
.X_op
!= O_constant
)
1204 as_bad (_("expected #constant"));
1205 ignore_rest_of_line ();
1208 *val
= exp
.X_add_number
;
1213 /* Register parsing. */
1215 /* Generic register parser. CCP points to what should be the
1216 beginning of a register name. If it is indeed a valid register
1217 name, advance CCP over it and return the reg_entry structure;
1218 otherwise return NULL. Does not issue diagnostics. */
1220 static struct reg_entry
*
1221 arm_reg_parse_multi (char **ccp
)
1225 struct reg_entry
*reg
;
1227 skip_whitespace (start
);
1229 #ifdef REGISTER_PREFIX
1230 if (*start
!= REGISTER_PREFIX
)
1234 #ifdef OPTIONAL_REGISTER_PREFIX
1235 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1240 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1245 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1247 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1257 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1258 enum arm_reg_type type
)
1260 /* Alternative syntaxes are accepted for a few register classes. */
1267 /* Generic coprocessor register names are allowed for these. */
1268 if (reg
&& reg
->type
== REG_TYPE_CN
)
1273 /* For backward compatibility, a bare number is valid here. */
1275 unsigned long processor
= strtoul (start
, ccp
, 10);
1276 if (*ccp
!= start
&& processor
<= 15)
1281 case REG_TYPE_MMXWC
:
1282 /* WC includes WCG. ??? I'm not sure this is true for all
1283 instructions that take WC registers. */
1284 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1295 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1296 return value is the register number or FAIL. */
1299 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1302 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1305 /* Do not allow a scalar (reg+index) to parse as a register. */
1306 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1309 if (reg
&& reg
->type
== type
)
1312 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1319 /* Parse a Neon type specifier. *STR should point at the leading '.'
1320 character. Does no verification at this stage that the type fits the opcode
1327 Can all be legally parsed by this function.
1329 Fills in neon_type struct pointer with parsed information, and updates STR
1330 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1331 type, FAIL if not. */
1334 parse_neon_type (struct neon_type
*type
, char **str
)
1341 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1343 enum neon_el_type thistype
= NT_untyped
;
1344 unsigned thissize
= -1u;
1351 /* Just a size without an explicit type. */
1355 switch (TOLOWER (*ptr
))
1357 case 'i': thistype
= NT_integer
; break;
1358 case 'f': thistype
= NT_float
; break;
1359 case 'p': thistype
= NT_poly
; break;
1360 case 's': thistype
= NT_signed
; break;
1361 case 'u': thistype
= NT_unsigned
; break;
1363 thistype
= NT_float
;
1368 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1374 /* .f is an abbreviation for .f32. */
1375 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1380 thissize
= strtoul (ptr
, &ptr
, 10);
1382 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1385 as_bad (_("bad size %d in type specifier"), thissize
);
1393 type
->el
[type
->elems
].type
= thistype
;
1394 type
->el
[type
->elems
].size
= thissize
;
1399 /* Empty/missing type is not a successful parse. */
1400 if (type
->elems
== 0)
1408 /* Errors may be set multiple times during parsing or bit encoding
1409 (particularly in the Neon bits), but usually the earliest error which is set
1410 will be the most meaningful. Avoid overwriting it with later (cascading)
1411 errors by calling this function. */
1414 first_error (const char *err
)
1420 /* Parse a single type, e.g. ".s32", leading period included. */
1422 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1425 struct neon_type optype
;
1429 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1431 if (optype
.elems
== 1)
1432 *vectype
= optype
.el
[0];
1435 first_error (_("only one type should be specified for operand"));
1441 first_error (_("vector type expected"));
1453 /* Special meanings for indices (which have a range of 0-7), which will fit into
1456 #define NEON_ALL_LANES 15
1457 #define NEON_INTERLEAVE_LANES 14
1459 /* Parse either a register or a scalar, with an optional type. Return the
1460 register number, and optionally fill in the actual type of the register
1461 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1462 type/index information in *TYPEINFO. */
1465 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1466 enum arm_reg_type
*rtype
,
1467 struct neon_typed_alias
*typeinfo
)
1470 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1471 struct neon_typed_alias atype
;
1472 struct neon_type_el parsetype
;
1476 atype
.eltype
.type
= NT_invtype
;
1477 atype
.eltype
.size
= -1;
1479 /* Try alternate syntax for some types of register. Note these are mutually
1480 exclusive with the Neon syntax extensions. */
1483 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1491 /* Undo polymorphism when a set of register types may be accepted. */
1492 if ((type
== REG_TYPE_NDQ
1493 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1494 || (type
== REG_TYPE_VFSD
1495 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1496 || (type
== REG_TYPE_NSDQ
1497 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1498 || reg
->type
== REG_TYPE_NQ
))
1499 || (type
== REG_TYPE_MMXWC
1500 && (reg
->type
== REG_TYPE_MMXWCG
)))
1501 type
= (enum arm_reg_type
) reg
->type
;
1503 if (type
!= reg
->type
)
1509 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1511 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1513 first_error (_("can't redefine type for operand"));
1516 atype
.defined
|= NTA_HASTYPE
;
1517 atype
.eltype
= parsetype
;
1520 if (skip_past_char (&str
, '[') == SUCCESS
)
1522 if (type
!= REG_TYPE_VFD
)
1524 first_error (_("only D registers may be indexed"));
1528 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1530 first_error (_("can't change index for operand"));
1534 atype
.defined
|= NTA_HASINDEX
;
1536 if (skip_past_char (&str
, ']') == SUCCESS
)
1537 atype
.index
= NEON_ALL_LANES
;
1542 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1544 if (exp
.X_op
!= O_constant
)
1546 first_error (_("constant expression required"));
1550 if (skip_past_char (&str
, ']') == FAIL
)
1553 atype
.index
= exp
.X_add_number
;
1568 /* Like arm_reg_parse, but allow allow the following extra features:
1569 - If RTYPE is non-zero, return the (possibly restricted) type of the
1570 register (e.g. Neon double or quad reg when either has been requested).
1571 - If this is a Neon vector type with additional type information, fill
1572 in the struct pointed to by VECTYPE (if non-NULL).
1573 This function will fault on encountering a scalar. */
1576 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1577 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1579 struct neon_typed_alias atype
;
1581 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1586 /* Do not allow regname(... to parse as a register. */
1590 /* Do not allow a scalar (reg+index) to parse as a register. */
1591 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1593 first_error (_("register operand expected, but got scalar"));
1598 *vectype
= atype
.eltype
;
1605 #define NEON_SCALAR_REG(X) ((X) >> 4)
1606 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1608 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1609 have enough information to be able to do a good job bounds-checking. So, we
1610 just do easy checks here, and do further checks later. */
1613 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1617 struct neon_typed_alias atype
;
1619 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1621 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1624 if (atype
.index
== NEON_ALL_LANES
)
1626 first_error (_("scalar must have an index"));
1629 else if (atype
.index
>= 64 / elsize
)
1631 first_error (_("scalar index out of range"));
1636 *type
= atype
.eltype
;
1640 return reg
* 16 + atype
.index
;
1643 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1646 parse_reg_list (char ** strp
)
1648 char * str
= * strp
;
1652 /* We come back here if we get ranges concatenated by '+' or '|'. */
1655 skip_whitespace (str
);
1669 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1671 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1681 first_error (_("bad range in register list"));
1685 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1687 if (range
& (1 << i
))
1689 (_("Warning: duplicated register (r%d) in register list"),
1697 if (range
& (1 << reg
))
1698 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1700 else if (reg
<= cur_reg
)
1701 as_tsktsk (_("Warning: register range not in ascending order"));
1706 while (skip_past_comma (&str
) != FAIL
1707 || (in_range
= 1, *str
++ == '-'));
1710 if (skip_past_char (&str
, '}') == FAIL
)
1712 first_error (_("missing `}'"));
1720 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1723 if (exp
.X_op
== O_constant
)
1725 if (exp
.X_add_number
1726 != (exp
.X_add_number
& 0x0000ffff))
1728 inst
.error
= _("invalid register mask");
1732 if ((range
& exp
.X_add_number
) != 0)
1734 int regno
= range
& exp
.X_add_number
;
1737 regno
= (1 << regno
) - 1;
1739 (_("Warning: duplicated register (r%d) in register list"),
1743 range
|= exp
.X_add_number
;
1747 if (inst
.reloc
.type
!= 0)
1749 inst
.error
= _("expression too complex");
1753 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1754 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1755 inst
.reloc
.pc_rel
= 0;
1759 if (*str
== '|' || *str
== '+')
1765 while (another_range
);
1771 /* Types of registers in a list. */
1780 /* Parse a VFP register list. If the string is invalid return FAIL.
1781 Otherwise return the number of registers, and set PBASE to the first
1782 register. Parses registers of type ETYPE.
1783 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1784 - Q registers can be used to specify pairs of D registers
1785 - { } can be omitted from around a singleton register list
1786 FIXME: This is not implemented, as it would require backtracking in
1789 This could be done (the meaning isn't really ambiguous), but doesn't
1790 fit in well with the current parsing framework.
1791 - 32 D registers may be used (also true for VFPv3).
1792 FIXME: Types are ignored in these register lists, which is probably a
1796 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1801 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1805 unsigned long mask
= 0;
1808 if (skip_past_char (&str
, '{') == FAIL
)
1810 inst
.error
= _("expecting {");
1817 regtype
= REG_TYPE_VFS
;
1822 regtype
= REG_TYPE_VFD
;
1825 case REGLIST_NEON_D
:
1826 regtype
= REG_TYPE_NDQ
;
1830 if (etype
!= REGLIST_VFP_S
)
1832 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1833 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1837 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1840 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1847 base_reg
= max_regs
;
1851 int setmask
= 1, addregs
= 1;
1853 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1855 if (new_base
== FAIL
)
1857 first_error (_(reg_expected_msgs
[regtype
]));
1861 if (new_base
>= max_regs
)
1863 first_error (_("register out of range in list"));
1867 /* Note: a value of 2 * n is returned for the register Q<n>. */
1868 if (regtype
== REG_TYPE_NQ
)
1874 if (new_base
< base_reg
)
1875 base_reg
= new_base
;
1877 if (mask
& (setmask
<< new_base
))
1879 first_error (_("invalid register list"));
1883 if ((mask
>> new_base
) != 0 && ! warned
)
1885 as_tsktsk (_("register list not in ascending order"));
1889 mask
|= setmask
<< new_base
;
1892 if (*str
== '-') /* We have the start of a range expression */
1898 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1901 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1905 if (high_range
>= max_regs
)
1907 first_error (_("register out of range in list"));
1911 if (regtype
== REG_TYPE_NQ
)
1912 high_range
= high_range
+ 1;
1914 if (high_range
<= new_base
)
1916 inst
.error
= _("register range not in ascending order");
1920 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1922 if (mask
& (setmask
<< new_base
))
1924 inst
.error
= _("invalid register list");
1928 mask
|= setmask
<< new_base
;
1933 while (skip_past_comma (&str
) != FAIL
);
1937 /* Sanity check -- should have raised a parse error above. */
1938 if (count
== 0 || count
> max_regs
)
1943 /* Final test -- the registers must be consecutive. */
1945 for (i
= 0; i
< count
; i
++)
1947 if ((mask
& (1u << i
)) == 0)
1949 inst
.error
= _("non-contiguous register range");
1959 /* True if two alias types are the same. */
1962 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1970 if (a
->defined
!= b
->defined
)
1973 if ((a
->defined
& NTA_HASTYPE
) != 0
1974 && (a
->eltype
.type
!= b
->eltype
.type
1975 || a
->eltype
.size
!= b
->eltype
.size
))
1978 if ((a
->defined
& NTA_HASINDEX
) != 0
1979 && (a
->index
!= b
->index
))
1985 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1986 The base register is put in *PBASE.
1987 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1989 The register stride (minus one) is put in bit 4 of the return value.
1990 Bits [6:5] encode the list length (minus one).
1991 The type of the list elements is put in *ELTYPE, if non-NULL. */
1993 #define NEON_LANE(X) ((X) & 0xf)
1994 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1995 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1998 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1999 struct neon_type_el
*eltype
)
2006 int leading_brace
= 0;
2007 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2008 const char *const incr_error
= _("register stride must be 1 or 2");
2009 const char *const type_error
= _("mismatched element/structure types in list");
2010 struct neon_typed_alias firsttype
;
2011 firsttype
.defined
= 0;
2012 firsttype
.eltype
.type
= NT_invtype
;
2013 firsttype
.eltype
.size
= -1;
2014 firsttype
.index
= -1;
2016 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2021 struct neon_typed_alias atype
;
2022 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2026 first_error (_(reg_expected_msgs
[rtype
]));
2033 if (rtype
== REG_TYPE_NQ
)
2039 else if (reg_incr
== -1)
2041 reg_incr
= getreg
- base_reg
;
2042 if (reg_incr
< 1 || reg_incr
> 2)
2044 first_error (_(incr_error
));
2048 else if (getreg
!= base_reg
+ reg_incr
* count
)
2050 first_error (_(incr_error
));
2054 if (! neon_alias_types_same (&atype
, &firsttype
))
2056 first_error (_(type_error
));
2060 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2064 struct neon_typed_alias htype
;
2065 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2067 lane
= NEON_INTERLEAVE_LANES
;
2068 else if (lane
!= NEON_INTERLEAVE_LANES
)
2070 first_error (_(type_error
));
2075 else if (reg_incr
!= 1)
2077 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2081 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2084 first_error (_(reg_expected_msgs
[rtype
]));
2087 if (! neon_alias_types_same (&htype
, &firsttype
))
2089 first_error (_(type_error
));
2092 count
+= hireg
+ dregs
- getreg
;
2096 /* If we're using Q registers, we can't use [] or [n] syntax. */
2097 if (rtype
== REG_TYPE_NQ
)
2103 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2107 else if (lane
!= atype
.index
)
2109 first_error (_(type_error
));
2113 else if (lane
== -1)
2114 lane
= NEON_INTERLEAVE_LANES
;
2115 else if (lane
!= NEON_INTERLEAVE_LANES
)
2117 first_error (_(type_error
));
2122 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2124 /* No lane set by [x]. We must be interleaving structures. */
2126 lane
= NEON_INTERLEAVE_LANES
;
2129 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2130 || (count
> 1 && reg_incr
== -1))
2132 first_error (_("error parsing element/structure list"));
2136 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2138 first_error (_("expected }"));
2146 *eltype
= firsttype
.eltype
;
2151 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2154 /* Parse an explicit relocation suffix on an expression. This is
2155 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2156 arm_reloc_hsh contains no entries, so this function can only
2157 succeed if there is no () after the word. Returns -1 on error,
2158 BFD_RELOC_UNUSED if there wasn't any suffix. */
2161 parse_reloc (char **str
)
2163 struct reloc_entry
*r
;
2167 return BFD_RELOC_UNUSED
;
2172 while (*q
&& *q
!= ')' && *q
!= ',')
2177 if ((r
= (struct reloc_entry
*)
2178 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2185 /* Directives: register aliases. */
2187 static struct reg_entry
*
2188 insert_reg_alias (char *str
, unsigned number
, int type
)
2190 struct reg_entry
*new_reg
;
2193 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2195 if (new_reg
->builtin
)
2196 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2198 /* Only warn about a redefinition if it's not defined as the
2200 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2201 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2206 name
= xstrdup (str
);
2207 new_reg
= XNEW (struct reg_entry
);
2209 new_reg
->name
= name
;
2210 new_reg
->number
= number
;
2211 new_reg
->type
= type
;
2212 new_reg
->builtin
= FALSE
;
2213 new_reg
->neon
= NULL
;
2215 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2222 insert_neon_reg_alias (char *str
, int number
, int type
,
2223 struct neon_typed_alias
*atype
)
2225 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2229 first_error (_("attempt to redefine typed alias"));
2235 reg
->neon
= XNEW (struct neon_typed_alias
);
2236 *reg
->neon
= *atype
;
2240 /* Look for the .req directive. This is of the form:
2242 new_register_name .req existing_register_name
2244 If we find one, or if it looks sufficiently like one that we want to
2245 handle any error here, return TRUE. Otherwise return FALSE. */
2248 create_register_alias (char * newname
, char *p
)
2250 struct reg_entry
*old
;
2251 char *oldname
, *nbuf
;
2254 /* The input scrubber ensures that whitespace after the mnemonic is
2255 collapsed to single spaces. */
2257 if (strncmp (oldname
, " .req ", 6) != 0)
2261 if (*oldname
== '\0')
2264 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2267 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2271 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2272 the desired alias name, and p points to its end. If not, then
2273 the desired alias name is in the global original_case_string. */
2274 #ifdef TC_CASE_SENSITIVE
2277 newname
= original_case_string
;
2278 nlen
= strlen (newname
);
2281 nbuf
= xmemdup0 (newname
, nlen
);
2283 /* Create aliases under the new name as stated; an all-lowercase
2284 version of the new name; and an all-uppercase version of the new
2286 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2288 for (p
= nbuf
; *p
; p
++)
2291 if (strncmp (nbuf
, newname
, nlen
))
2293 /* If this attempt to create an additional alias fails, do not bother
2294 trying to create the all-lower case alias. We will fail and issue
2295 a second, duplicate error message. This situation arises when the
2296 programmer does something like:
2299 The second .req creates the "Foo" alias but then fails to create
2300 the artificial FOO alias because it has already been created by the
2302 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2309 for (p
= nbuf
; *p
; p
++)
2312 if (strncmp (nbuf
, newname
, nlen
))
2313 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2320 /* Create a Neon typed/indexed register alias using directives, e.g.:
2325 These typed registers can be used instead of the types specified after the
2326 Neon mnemonic, so long as all operands given have types. Types can also be
2327 specified directly, e.g.:
2328 vadd d0.s32, d1.s32, d2.s32 */
2331 create_neon_reg_alias (char *newname
, char *p
)
2333 enum arm_reg_type basetype
;
2334 struct reg_entry
*basereg
;
2335 struct reg_entry mybasereg
;
2336 struct neon_type ntype
;
2337 struct neon_typed_alias typeinfo
;
2338 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2341 typeinfo
.defined
= 0;
2342 typeinfo
.eltype
.type
= NT_invtype
;
2343 typeinfo
.eltype
.size
= -1;
2344 typeinfo
.index
= -1;
2348 if (strncmp (p
, " .dn ", 5) == 0)
2349 basetype
= REG_TYPE_VFD
;
2350 else if (strncmp (p
, " .qn ", 5) == 0)
2351 basetype
= REG_TYPE_NQ
;
2360 basereg
= arm_reg_parse_multi (&p
);
2362 if (basereg
&& basereg
->type
!= basetype
)
2364 as_bad (_("bad type for register"));
2368 if (basereg
== NULL
)
2371 /* Try parsing as an integer. */
2372 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2373 if (exp
.X_op
!= O_constant
)
2375 as_bad (_("expression must be constant"));
2378 basereg
= &mybasereg
;
2379 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2385 typeinfo
= *basereg
->neon
;
2387 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2389 /* We got a type. */
2390 if (typeinfo
.defined
& NTA_HASTYPE
)
2392 as_bad (_("can't redefine the type of a register alias"));
2396 typeinfo
.defined
|= NTA_HASTYPE
;
2397 if (ntype
.elems
!= 1)
2399 as_bad (_("you must specify a single type only"));
2402 typeinfo
.eltype
= ntype
.el
[0];
2405 if (skip_past_char (&p
, '[') == SUCCESS
)
2408 /* We got a scalar index. */
2410 if (typeinfo
.defined
& NTA_HASINDEX
)
2412 as_bad (_("can't redefine the index of a scalar alias"));
2416 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2418 if (exp
.X_op
!= O_constant
)
2420 as_bad (_("scalar index must be constant"));
2424 typeinfo
.defined
|= NTA_HASINDEX
;
2425 typeinfo
.index
= exp
.X_add_number
;
2427 if (skip_past_char (&p
, ']') == FAIL
)
2429 as_bad (_("expecting ]"));
2434 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2435 the desired alias name, and p points to its end. If not, then
2436 the desired alias name is in the global original_case_string. */
2437 #ifdef TC_CASE_SENSITIVE
2438 namelen
= nameend
- newname
;
2440 newname
= original_case_string
;
2441 namelen
= strlen (newname
);
2444 namebuf
= xmemdup0 (newname
, namelen
);
2446 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2447 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2449 /* Insert name in all uppercase. */
2450 for (p
= namebuf
; *p
; p
++)
2453 if (strncmp (namebuf
, newname
, namelen
))
2454 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2455 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2457 /* Insert name in all lowercase. */
2458 for (p
= namebuf
; *p
; p
++)
2461 if (strncmp (namebuf
, newname
, namelen
))
2462 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2463 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2469 /* Should never be called, as .req goes between the alias and the
2470 register name, not at the beginning of the line. */
2473 s_req (int a ATTRIBUTE_UNUSED
)
2475 as_bad (_("invalid syntax for .req directive"));
2479 s_dn (int a ATTRIBUTE_UNUSED
)
2481 as_bad (_("invalid syntax for .dn directive"));
2485 s_qn (int a ATTRIBUTE_UNUSED
)
2487 as_bad (_("invalid syntax for .qn directive"));
2490 /* The .unreq directive deletes an alias which was previously defined
2491 by .req. For example:
2497 s_unreq (int a ATTRIBUTE_UNUSED
)
2502 name
= input_line_pointer
;
2504 while (*input_line_pointer
!= 0
2505 && *input_line_pointer
!= ' '
2506 && *input_line_pointer
!= '\n')
2507 ++input_line_pointer
;
2509 saved_char
= *input_line_pointer
;
2510 *input_line_pointer
= 0;
2513 as_bad (_("invalid syntax for .unreq directive"));
2516 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2520 as_bad (_("unknown register alias '%s'"), name
);
2521 else if (reg
->builtin
)
2522 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2529 hash_delete (arm_reg_hsh
, name
, FALSE
);
2530 free ((char *) reg
->name
);
2535 /* Also locate the all upper case and all lower case versions.
2536 Do not complain if we cannot find one or the other as it
2537 was probably deleted above. */
2539 nbuf
= strdup (name
);
2540 for (p
= nbuf
; *p
; p
++)
2542 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2545 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2546 free ((char *) reg
->name
);
2552 for (p
= nbuf
; *p
; p
++)
2554 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2557 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2558 free ((char *) reg
->name
);
2568 *input_line_pointer
= saved_char
;
2569 demand_empty_rest_of_line ();
2572 /* Directives: Instruction set selection. */
2575 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2576 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2577 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2578 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2580 /* Create a new mapping symbol for the transition to STATE. */
2583 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2586 const char * symname
;
2593 type
= BSF_NO_FLAGS
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2607 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2608 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2613 THUMB_SET_FUNC (symbolP
, 0);
2614 ARM_SET_THUMB (symbolP
, 0);
2615 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2619 THUMB_SET_FUNC (symbolP
, 1);
2620 ARM_SET_THUMB (symbolP
, 1);
2621 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2629 /* Save the mapping symbols for future reference. Also check that
2630 we do not place two mapping symbols at the same offset within a
2631 frag. We'll handle overlap between frags in
2632 check_mapping_symbols.
2634 If .fill or other data filling directive generates zero sized data,
2635 the mapping symbol for the following code will have the same value
2636 as the one generated for the data filling directive. In this case,
2637 we replace the old symbol with the new one at the same address. */
2640 if (frag
->tc_frag_data
.first_map
!= NULL
)
2642 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2643 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2645 frag
->tc_frag_data
.first_map
= symbolP
;
2647 if (frag
->tc_frag_data
.last_map
!= NULL
)
2649 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2650 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2651 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2653 frag
->tc_frag_data
.last_map
= symbolP
;
2656 /* We must sometimes convert a region marked as code to data during
2657 code alignment, if an odd number of bytes have to be padded. The
2658 code mapping symbol is pushed to an aligned address. */
2661 insert_data_mapping_symbol (enum mstate state
,
2662 valueT value
, fragS
*frag
, offsetT bytes
)
2664 /* If there was already a mapping symbol, remove it. */
2665 if (frag
->tc_frag_data
.last_map
!= NULL
2666 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2668 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2672 know (frag
->tc_frag_data
.first_map
== symp
);
2673 frag
->tc_frag_data
.first_map
= NULL
;
2675 frag
->tc_frag_data
.last_map
= NULL
;
2676 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2679 make_mapping_symbol (MAP_DATA
, value
, frag
);
2680 make_mapping_symbol (state
, value
+ bytes
, frag
);
2683 static void mapping_state_2 (enum mstate state
, int max_chars
);
2685 /* Set the mapping state to STATE. Only call this when about to
2686 emit some STATE bytes to the file. */
2688 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2690 mapping_state (enum mstate state
)
2692 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2694 if (mapstate
== state
)
2695 /* The mapping symbol has already been emitted.
2696 There is nothing else to do. */
2699 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2701 All ARM instructions require 4-byte alignment.
2702 (Almost) all Thumb instructions require 2-byte alignment.
2704 When emitting instructions into any section, mark the section
2707 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2708 but themselves require 2-byte alignment; this applies to some
2709 PC- relative forms. However, these cases will invovle implicit
2710 literal pool generation or an explicit .align >=2, both of
2711 which will cause the section to me marked with sufficient
2712 alignment. Thus, we don't handle those cases here. */
2713 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2715 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2716 /* This case will be evaluated later. */
2719 mapping_state_2 (state
, 0);
2722 /* Same as mapping_state, but MAX_CHARS bytes have already been
2723 allocated. Put the mapping symbol that far back. */
2726 mapping_state_2 (enum mstate state
, int max_chars
)
2728 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2730 if (!SEG_NORMAL (now_seg
))
2733 if (mapstate
== state
)
2734 /* The mapping symbol has already been emitted.
2735 There is nothing else to do. */
2738 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2739 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2741 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2742 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2745 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2748 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2749 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2753 #define mapping_state(x) ((void)0)
2754 #define mapping_state_2(x, y) ((void)0)
2757 /* Find the real, Thumb encoded start of a Thumb function. */
2761 find_real_start (symbolS
* symbolP
)
2764 const char * name
= S_GET_NAME (symbolP
);
2765 symbolS
* new_target
;
2767 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2768 #define STUB_NAME ".real_start_of"
2773 /* The compiler may generate BL instructions to local labels because
2774 it needs to perform a branch to a far away location. These labels
2775 do not have a corresponding ".real_start_of" label. We check
2776 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2777 the ".real_start_of" convention for nonlocal branches. */
2778 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2781 real_start
= concat (STUB_NAME
, name
, NULL
);
2782 new_target
= symbol_find (real_start
);
2785 if (new_target
== NULL
)
2787 as_warn (_("Failed to find real start of function: %s\n"), name
);
2788 new_target
= symbolP
;
2796 opcode_select (int width
)
2803 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2804 as_bad (_("selected processor does not support THUMB opcodes"));
2807 /* No need to force the alignment, since we will have been
2808 coming from ARM mode, which is word-aligned. */
2809 record_alignment (now_seg
, 1);
2816 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2817 as_bad (_("selected processor does not support ARM opcodes"));
2822 frag_align (2, 0, 0);
2824 record_alignment (now_seg
, 1);
2829 as_bad (_("invalid instruction size selected (%d)"), width
);
2834 s_arm (int ignore ATTRIBUTE_UNUSED
)
2837 demand_empty_rest_of_line ();
2841 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2844 demand_empty_rest_of_line ();
2848 s_code (int unused ATTRIBUTE_UNUSED
)
2852 temp
= get_absolute_expression ();
2857 opcode_select (temp
);
2861 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2866 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2868 /* If we are not already in thumb mode go into it, EVEN if
2869 the target processor does not support thumb instructions.
2870 This is used by gcc/config/arm/lib1funcs.asm for example
2871 to compile interworking support functions even if the
2872 target processor should not support interworking. */
2876 record_alignment (now_seg
, 1);
2879 demand_empty_rest_of_line ();
2883 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2887 /* The following label is the name/address of the start of a Thumb function.
2888 We need to know this for the interworking support. */
2889 label_is_thumb_function_name
= TRUE
;
2892 /* Perform a .set directive, but also mark the alias as
2893 being a thumb function. */
2896 s_thumb_set (int equiv
)
2898 /* XXX the following is a duplicate of the code for s_set() in read.c
2899 We cannot just call that code as we need to get at the symbol that
2906 /* Especial apologies for the random logic:
2907 This just grew, and could be parsed much more simply!
2909 delim
= get_symbol_name (& name
);
2910 end_name
= input_line_pointer
;
2911 (void) restore_line_pointer (delim
);
2913 if (*input_line_pointer
!= ',')
2916 as_bad (_("expected comma after name \"%s\""), name
);
2918 ignore_rest_of_line ();
2922 input_line_pointer
++;
2925 if (name
[0] == '.' && name
[1] == '\0')
2927 /* XXX - this should not happen to .thumb_set. */
2931 if ((symbolP
= symbol_find (name
)) == NULL
2932 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2935 /* When doing symbol listings, play games with dummy fragments living
2936 outside the normal fragment chain to record the file and line info
2938 if (listing
& LISTING_SYMBOLS
)
2940 extern struct list_info_struct
* listing_tail
;
2941 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2943 memset (dummy_frag
, 0, sizeof (fragS
));
2944 dummy_frag
->fr_type
= rs_fill
;
2945 dummy_frag
->line
= listing_tail
;
2946 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2947 dummy_frag
->fr_symbol
= symbolP
;
2951 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2954 /* "set" symbols are local unless otherwise specified. */
2955 SF_SET_LOCAL (symbolP
);
2956 #endif /* OBJ_COFF */
2957 } /* Make a new symbol. */
2959 symbol_table_insert (symbolP
);
2964 && S_IS_DEFINED (symbolP
)
2965 && S_GET_SEGMENT (symbolP
) != reg_section
)
2966 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2968 pseudo_set (symbolP
);
2970 demand_empty_rest_of_line ();
2972 /* XXX Now we come to the Thumb specific bit of code. */
2974 THUMB_SET_FUNC (symbolP
, 1);
2975 ARM_SET_THUMB (symbolP
, 1);
2976 #if defined OBJ_ELF || defined OBJ_COFF
2977 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2981 /* Directives: Mode selection. */
2983 /* .syntax [unified|divided] - choose the new unified syntax
2984 (same for Arm and Thumb encoding, modulo slight differences in what
2985 can be represented) or the old divergent syntax for each mode. */
2987 s_syntax (int unused ATTRIBUTE_UNUSED
)
2991 delim
= get_symbol_name (& name
);
2993 if (!strcasecmp (name
, "unified"))
2994 unified_syntax
= TRUE
;
2995 else if (!strcasecmp (name
, "divided"))
2996 unified_syntax
= FALSE
;
2999 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3002 (void) restore_line_pointer (delim
);
3003 demand_empty_rest_of_line ();
3006 /* Directives: sectioning and alignment. */
3009 s_bss (int ignore ATTRIBUTE_UNUSED
)
3011 /* We don't support putting frags in the BSS segment, we fake it by
3012 marking in_bss, then looking at s_skip for clues. */
3013 subseg_set (bss_section
, 0);
3014 demand_empty_rest_of_line ();
3016 #ifdef md_elf_section_change_hook
3017 md_elf_section_change_hook ();
3022 s_even (int ignore ATTRIBUTE_UNUSED
)
3024 /* Never make frag if expect extra pass. */
3026 frag_align (1, 0, 0);
3028 record_alignment (now_seg
, 1);
3030 demand_empty_rest_of_line ();
3033 /* Directives: CodeComposer Studio. */
3035 /* .ref (for CodeComposer Studio syntax only). */
3037 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3039 if (codecomposer_syntax
)
3040 ignore_rest_of_line ();
3042 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3045 /* If name is not NULL, then it is used for marking the beginning of a
3046 function, wherease if it is NULL then it means the function end. */
3048 asmfunc_debug (const char * name
)
3050 static const char * last_name
= NULL
;
3054 gas_assert (last_name
== NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_func (name
, name
);
3062 gas_assert (last_name
!= NULL
);
3064 if (debug_type
== DEBUG_STABS
)
3065 stabs_generate_asm_endfunc (last_name
, last_name
);
3072 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3074 if (codecomposer_syntax
)
3076 switch (asmfunc_state
)
3078 case OUTSIDE_ASMFUNC
:
3079 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3082 case WAITING_ASMFUNC_NAME
:
3083 as_bad (_(".asmfunc repeated."));
3086 case WAITING_ENDASMFUNC
:
3087 as_bad (_(".asmfunc without function."));
3090 demand_empty_rest_of_line ();
3093 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3097 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3099 if (codecomposer_syntax
)
3101 switch (asmfunc_state
)
3103 case OUTSIDE_ASMFUNC
:
3104 as_bad (_(".endasmfunc without a .asmfunc."));
3107 case WAITING_ASMFUNC_NAME
:
3108 as_bad (_(".endasmfunc without function."));
3111 case WAITING_ENDASMFUNC
:
3112 asmfunc_state
= OUTSIDE_ASMFUNC
;
3113 asmfunc_debug (NULL
);
3116 demand_empty_rest_of_line ();
3119 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3123 s_ccs_def (int name
)
3125 if (codecomposer_syntax
)
3128 as_bad (_(".def pseudo-op only available with -mccs flag."));
3131 /* Directives: Literal pools. */
3133 static literal_pool
*
3134 find_literal_pool (void)
3136 literal_pool
* pool
;
3138 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3140 if (pool
->section
== now_seg
3141 && pool
->sub_section
== now_subseg
)
3148 static literal_pool
*
3149 find_or_make_literal_pool (void)
3151 /* Next literal pool ID number. */
3152 static unsigned int latest_pool_num
= 1;
3153 literal_pool
* pool
;
3155 pool
= find_literal_pool ();
3159 /* Create a new pool. */
3160 pool
= XNEW (literal_pool
);
3164 pool
->next_free_entry
= 0;
3165 pool
->section
= now_seg
;
3166 pool
->sub_section
= now_subseg
;
3167 pool
->next
= list_of_pools
;
3168 pool
->symbol
= NULL
;
3169 pool
->alignment
= 2;
3171 /* Add it to the list. */
3172 list_of_pools
= pool
;
3175 /* New pools, and emptied pools, will have a NULL symbol. */
3176 if (pool
->symbol
== NULL
)
3178 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3179 (valueT
) 0, &zero_address_frag
);
3180 pool
->id
= latest_pool_num
++;
3187 /* Add the literal in the global 'inst'
3188 structure to the relevant literal pool. */
3191 add_to_lit_pool (unsigned int nbytes
)
3193 #define PADDING_SLOT 0x1
3194 #define LIT_ENTRY_SIZE_MASK 0xFF
3195 literal_pool
* pool
;
3196 unsigned int entry
, pool_size
= 0;
3197 bfd_boolean padding_slot_p
= FALSE
;
3203 imm1
= inst
.operands
[1].imm
;
3204 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3205 : inst
.reloc
.exp
.X_unsigned
? 0
3206 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3207 if (target_big_endian
)
3210 imm2
= inst
.operands
[1].imm
;
3214 pool
= find_or_make_literal_pool ();
3216 /* Check if this literal value is already in the pool. */
3217 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3221 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3222 && (inst
.reloc
.exp
.X_op
== O_constant
)
3223 && (pool
->literals
[entry
].X_add_number
3224 == inst
.reloc
.exp
.X_add_number
)
3225 && (pool
->literals
[entry
].X_md
== nbytes
)
3226 && (pool
->literals
[entry
].X_unsigned
3227 == inst
.reloc
.exp
.X_unsigned
))
3230 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3231 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3232 && (pool
->literals
[entry
].X_add_number
3233 == inst
.reloc
.exp
.X_add_number
)
3234 && (pool
->literals
[entry
].X_add_symbol
3235 == inst
.reloc
.exp
.X_add_symbol
)
3236 && (pool
->literals
[entry
].X_op_symbol
3237 == inst
.reloc
.exp
.X_op_symbol
)
3238 && (pool
->literals
[entry
].X_md
== nbytes
))
3241 else if ((nbytes
== 8)
3242 && !(pool_size
& 0x7)
3243 && ((entry
+ 1) != pool
->next_free_entry
)
3244 && (pool
->literals
[entry
].X_op
== O_constant
)
3245 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3246 && (pool
->literals
[entry
].X_unsigned
3247 == inst
.reloc
.exp
.X_unsigned
)
3248 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3249 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3250 && (pool
->literals
[entry
+ 1].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
))
3254 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3255 if (padding_slot_p
&& (nbytes
== 4))
3261 /* Do we need to create a new entry? */
3262 if (entry
== pool
->next_free_entry
)
3264 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3266 inst
.error
= _("literal pool overflow");
3272 /* For 8-byte entries, we align to an 8-byte boundary,
3273 and split it into two 4-byte entries, because on 32-bit
3274 host, 8-byte constants are treated as big num, thus
3275 saved in "generic_bignum" which will be overwritten
3276 by later assignments.
3278 We also need to make sure there is enough space for
3281 We also check to make sure the literal operand is a
3283 if (!(inst
.reloc
.exp
.X_op
== O_constant
3284 || inst
.reloc
.exp
.X_op
== O_big
))
3286 inst
.error
= _("invalid type for literal pool");
3289 else if (pool_size
& 0x7)
3291 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3293 inst
.error
= _("literal pool overflow");
3297 pool
->literals
[entry
] = inst
.reloc
.exp
;
3298 pool
->literals
[entry
].X_op
= O_constant
;
3299 pool
->literals
[entry
].X_add_number
= 0;
3300 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3301 pool
->next_free_entry
+= 1;
3304 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3306 inst
.error
= _("literal pool overflow");
3310 pool
->literals
[entry
] = inst
.reloc
.exp
;
3311 pool
->literals
[entry
].X_op
= O_constant
;
3312 pool
->literals
[entry
].X_add_number
= imm1
;
3313 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3314 pool
->literals
[entry
++].X_md
= 4;
3315 pool
->literals
[entry
] = inst
.reloc
.exp
;
3316 pool
->literals
[entry
].X_op
= O_constant
;
3317 pool
->literals
[entry
].X_add_number
= imm2
;
3318 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3319 pool
->literals
[entry
].X_md
= 4;
3320 pool
->alignment
= 3;
3321 pool
->next_free_entry
+= 1;
3325 pool
->literals
[entry
] = inst
.reloc
.exp
;
3326 pool
->literals
[entry
].X_md
= 4;
3330 /* PR ld/12974: Record the location of the first source line to reference
3331 this entry in the literal pool. If it turns out during linking that the
3332 symbol does not exist we will be able to give an accurate line number for
3333 the (first use of the) missing reference. */
3334 if (debug_type
== DEBUG_DWARF2
)
3335 dwarf2_where (pool
->locs
+ entry
);
3337 pool
->next_free_entry
+= 1;
3339 else if (padding_slot_p
)
3341 pool
->literals
[entry
] = inst
.reloc
.exp
;
3342 pool
->literals
[entry
].X_md
= nbytes
;
3345 inst
.reloc
.exp
.X_op
= O_symbol
;
3346 inst
.reloc
.exp
.X_add_number
= pool_size
;
3347 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3353 tc_start_label_without_colon (void)
3355 bfd_boolean ret
= TRUE
;
3357 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3359 const char *label
= input_line_pointer
;
3361 while (!is_end_of_line
[(int) label
[-1]])
3366 as_bad (_("Invalid label '%s'"), label
);
3370 asmfunc_debug (label
);
3372 asmfunc_state
= WAITING_ENDASMFUNC
;
3378 /* Can't use symbol_new here, so have to create a symbol and then at
3379 a later date assign it a value. Thats what these functions do. */
3382 symbol_locate (symbolS
* symbolP
,
3383 const char * name
, /* It is copied, the caller can modify. */
3384 segT segment
, /* Segment identifier (SEG_<something>). */
3385 valueT valu
, /* Symbol value. */
3386 fragS
* frag
) /* Associated fragment. */
3389 char * preserved_copy_of_name
;
3391 name_length
= strlen (name
) + 1; /* +1 for \0. */
3392 obstack_grow (¬es
, name
, name_length
);
3393 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3395 #ifdef tc_canonicalize_symbol_name
3396 preserved_copy_of_name
=
3397 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3400 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3402 S_SET_SEGMENT (symbolP
, segment
);
3403 S_SET_VALUE (symbolP
, valu
);
3404 symbol_clear_list_pointers (symbolP
);
3406 symbol_set_frag (symbolP
, frag
);
3408 /* Link to end of symbol chain. */
3410 extern int symbol_table_frozen
;
3412 if (symbol_table_frozen
)
3416 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3418 obj_symbol_new_hook (symbolP
);
3420 #ifdef tc_symbol_new_hook
3421 tc_symbol_new_hook (symbolP
);
3425 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3426 #endif /* DEBUG_SYMS */
3430 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3433 literal_pool
* pool
;
3436 pool
= find_literal_pool ();
3438 || pool
->symbol
== NULL
3439 || pool
->next_free_entry
== 0)
3442 /* Align pool as you have word accesses.
3443 Only make a frag if we have to. */
3445 frag_align (pool
->alignment
, 0, 0);
3447 record_alignment (now_seg
, 2);
3450 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3451 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3453 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3455 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3456 (valueT
) frag_now_fix (), frag_now
);
3457 symbol_table_insert (pool
->symbol
);
3459 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3461 #if defined OBJ_COFF || defined OBJ_ELF
3462 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3465 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if (debug_type
== DEBUG_DWARF2
)
3469 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3471 /* First output the expression in the instruction to the pool. */
3472 emit_expr (&(pool
->literals
[entry
]),
3473 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3476 /* Mark the pool as empty. */
3477 pool
->next_free_entry
= 0;
3478 pool
->symbol
= NULL
;
3482 /* Forward declarations for functions below, in the MD interface
3484 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3485 static valueT
create_unwind_entry (int);
3486 static void start_unwind_section (const segT
, int);
3487 static void add_unwind_opcode (valueT
, int);
3488 static void flush_pending_unwind (void);
3490 /* Directives: Data. */
3493 s_arm_elf_cons (int nbytes
)
3497 #ifdef md_flush_pending_output
3498 md_flush_pending_output ();
3501 if (is_it_end_of_statement ())
3503 demand_empty_rest_of_line ();
3507 #ifdef md_cons_align
3508 md_cons_align (nbytes
);
3511 mapping_state (MAP_DATA
);
3515 char *base
= input_line_pointer
;
3519 if (exp
.X_op
!= O_symbol
)
3520 emit_expr (&exp
, (unsigned int) nbytes
);
3523 char *before_reloc
= input_line_pointer
;
3524 reloc
= parse_reloc (&input_line_pointer
);
3527 as_bad (_("unrecognized relocation suffix"));
3528 ignore_rest_of_line ();
3531 else if (reloc
== BFD_RELOC_UNUSED
)
3532 emit_expr (&exp
, (unsigned int) nbytes
);
3535 reloc_howto_type
*howto
= (reloc_howto_type
*)
3536 bfd_reloc_type_lookup (stdoutput
,
3537 (bfd_reloc_code_real_type
) reloc
);
3538 int size
= bfd_get_reloc_size (howto
);
3540 if (reloc
== BFD_RELOC_ARM_PLT32
)
3542 as_bad (_("(plt) is only valid on branch targets"));
3543 reloc
= BFD_RELOC_UNUSED
;
3548 as_bad (_("%s relocations do not fit in %d bytes"),
3549 howto
->name
, nbytes
);
3552 /* We've parsed an expression stopping at O_symbol.
3553 But there may be more expression left now that we
3554 have parsed the relocation marker. Parse it again.
3555 XXX Surely there is a cleaner way to do this. */
3556 char *p
= input_line_pointer
;
3558 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3560 memcpy (save_buf
, base
, input_line_pointer
- base
);
3561 memmove (base
+ (input_line_pointer
- before_reloc
),
3562 base
, before_reloc
- base
);
3564 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3566 memcpy (base
, save_buf
, p
- base
);
3568 offset
= nbytes
- size
;
3569 p
= frag_more (nbytes
);
3570 memset (p
, 0, nbytes
);
3571 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3572 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3578 while (*input_line_pointer
++ == ',');
3580 /* Put terminator back into stream. */
3581 input_line_pointer
--;
3582 demand_empty_rest_of_line ();
3585 /* Emit an expression containing a 32-bit thumb instruction.
3586 Implementation based on put_thumb32_insn. */
3589 emit_thumb32_expr (expressionS
* exp
)
3591 expressionS exp_high
= *exp
;
3593 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3594 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3595 exp
->X_add_number
&= 0xffff;
3596 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3599 /* Guess the instruction size based on the opcode. */
3602 thumb_insn_size (int opcode
)
3604 if ((unsigned int) opcode
< 0xe800u
)
3606 else if ((unsigned int) opcode
>= 0xe8000000u
)
3613 emit_insn (expressionS
*exp
, int nbytes
)
3617 if (exp
->X_op
== O_constant
)
3622 size
= thumb_insn_size (exp
->X_add_number
);
3626 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3628 as_bad (_(".inst.n operand too big. "\
3629 "Use .inst.w instead"));
3634 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3635 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3637 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3639 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3640 emit_thumb32_expr (exp
);
3642 emit_expr (exp
, (unsigned int) size
);
3644 it_fsm_post_encode ();
3648 as_bad (_("cannot determine Thumb instruction size. " \
3649 "Use .inst.n/.inst.w instead"));
3652 as_bad (_("constant expression required"));
3657 /* Like s_arm_elf_cons but do not use md_cons_align and
3658 set the mapping state to MAP_ARM/MAP_THUMB. */
3661 s_arm_elf_inst (int nbytes
)
3663 if (is_it_end_of_statement ())
3665 demand_empty_rest_of_line ();
3669 /* Calling mapping_state () here will not change ARM/THUMB,
3670 but will ensure not to be in DATA state. */
3673 mapping_state (MAP_THUMB
);
3678 as_bad (_("width suffixes are invalid in ARM mode"));
3679 ignore_rest_of_line ();
3685 mapping_state (MAP_ARM
);
3694 if (! emit_insn (& exp
, nbytes
))
3696 ignore_rest_of_line ();
3700 while (*input_line_pointer
++ == ',');
3702 /* Put terminator back into stream. */
3703 input_line_pointer
--;
3704 demand_empty_rest_of_line ();
3707 /* Parse a .rel31 directive. */
3710 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3717 if (*input_line_pointer
== '1')
3718 highbit
= 0x80000000;
3719 else if (*input_line_pointer
!= '0')
3720 as_bad (_("expected 0 or 1"));
3722 input_line_pointer
++;
3723 if (*input_line_pointer
!= ',')
3724 as_bad (_("missing comma"));
3725 input_line_pointer
++;
3727 #ifdef md_flush_pending_output
3728 md_flush_pending_output ();
3731 #ifdef md_cons_align
3735 mapping_state (MAP_DATA
);
3740 md_number_to_chars (p
, highbit
, 4);
3741 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3742 BFD_RELOC_ARM_PREL31
);
3744 demand_empty_rest_of_line ();
3747 /* Directives: AEABI stack-unwind tables. */
3749 /* Parse an unwind_fnstart directive. Simply records the current location. */
3752 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3754 demand_empty_rest_of_line ();
3755 if (unwind
.proc_start
)
3757 as_bad (_("duplicate .fnstart directive"));
3761 /* Mark the start of the function. */
3762 unwind
.proc_start
= expr_build_dot ();
3764 /* Reset the rest of the unwind info. */
3765 unwind
.opcode_count
= 0;
3766 unwind
.table_entry
= NULL
;
3767 unwind
.personality_routine
= NULL
;
3768 unwind
.personality_index
= -1;
3769 unwind
.frame_size
= 0;
3770 unwind
.fp_offset
= 0;
3771 unwind
.fp_reg
= REG_SP
;
3773 unwind
.sp_restored
= 0;
3777 /* Parse a handlerdata directive. Creates the exception handling table entry
3778 for the function. */
3781 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3783 demand_empty_rest_of_line ();
3784 if (!unwind
.proc_start
)
3785 as_bad (MISSING_FNSTART
);
3787 if (unwind
.table_entry
)
3788 as_bad (_("duplicate .handlerdata directive"));
3790 create_unwind_entry (1);
3793 /* Parse an unwind_fnend directive. Generates the index table entry. */
3796 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3801 unsigned int marked_pr_dependency
;
3803 demand_empty_rest_of_line ();
3805 if (!unwind
.proc_start
)
3807 as_bad (_(".fnend directive without .fnstart"));
3811 /* Add eh table entry. */
3812 if (unwind
.table_entry
== NULL
)
3813 val
= create_unwind_entry (0);
3817 /* Add index table entry. This is two words. */
3818 start_unwind_section (unwind
.saved_seg
, 1);
3819 frag_align (2, 0, 0);
3820 record_alignment (now_seg
, 2);
3822 ptr
= frag_more (8);
3824 where
= frag_now_fix () - 8;
3826 /* Self relative offset of the function start. */
3827 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3828 BFD_RELOC_ARM_PREL31
);
3830 /* Indicate dependency on EHABI-defined personality routines to the
3831 linker, if it hasn't been done already. */
3832 marked_pr_dependency
3833 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3834 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3835 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3837 static const char *const name
[] =
3839 "__aeabi_unwind_cpp_pr0",
3840 "__aeabi_unwind_cpp_pr1",
3841 "__aeabi_unwind_cpp_pr2"
3843 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3844 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3845 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3846 |= 1 << unwind
.personality_index
;
3850 /* Inline exception table entry. */
3851 md_number_to_chars (ptr
+ 4, val
, 4);
3853 /* Self relative offset of the table entry. */
3854 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3855 BFD_RELOC_ARM_PREL31
);
3857 /* Restore the original section. */
3858 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3860 unwind
.proc_start
= NULL
;
3864 /* Parse an unwind_cantunwind directive. */
3867 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3869 demand_empty_rest_of_line ();
3870 if (!unwind
.proc_start
)
3871 as_bad (MISSING_FNSTART
);
3873 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3874 as_bad (_("personality routine specified for cantunwind frame"));
3876 unwind
.personality_index
= -2;
3880 /* Parse a personalityindex directive. */
3883 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3887 if (!unwind
.proc_start
)
3888 as_bad (MISSING_FNSTART
);
3890 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3891 as_bad (_("duplicate .personalityindex directive"));
3895 if (exp
.X_op
!= O_constant
3896 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3898 as_bad (_("bad personality routine number"));
3899 ignore_rest_of_line ();
3903 unwind
.personality_index
= exp
.X_add_number
;
3905 demand_empty_rest_of_line ();
3909 /* Parse a personality directive. */
3912 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3916 if (!unwind
.proc_start
)
3917 as_bad (MISSING_FNSTART
);
3919 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3920 as_bad (_("duplicate .personality directive"));
3922 c
= get_symbol_name (& name
);
3923 p
= input_line_pointer
;
3925 ++ input_line_pointer
;
3926 unwind
.personality_routine
= symbol_find_or_make (name
);
3928 demand_empty_rest_of_line ();
3932 /* Parse a directive saving core registers. */
3935 s_arm_unwind_save_core (void)
3941 range
= parse_reg_list (&input_line_pointer
);
3944 as_bad (_("expected register list"));
3945 ignore_rest_of_line ();
3949 demand_empty_rest_of_line ();
3951 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3952 into .unwind_save {..., sp...}. We aren't bothered about the value of
3953 ip because it is clobbered by calls. */
3954 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3955 && (range
& 0x3000) == 0x1000)
3957 unwind
.opcode_count
--;
3958 unwind
.sp_restored
= 0;
3959 range
= (range
| 0x2000) & ~0x1000;
3960 unwind
.pending_offset
= 0;
3966 /* See if we can use the short opcodes. These pop a block of up to 8
3967 registers starting with r4, plus maybe r14. */
3968 for (n
= 0; n
< 8; n
++)
3970 /* Break at the first non-saved register. */
3971 if ((range
& (1 << (n
+ 4))) == 0)
3974 /* See if there are any other bits set. */
3975 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3977 /* Use the long form. */
3978 op
= 0x8000 | ((range
>> 4) & 0xfff);
3979 add_unwind_opcode (op
, 2);
3983 /* Use the short form. */
3985 op
= 0xa8; /* Pop r14. */
3987 op
= 0xa0; /* Do not pop r14. */
3989 add_unwind_opcode (op
, 1);
3996 op
= 0xb100 | (range
& 0xf);
3997 add_unwind_opcode (op
, 2);
4000 /* Record the number of bytes pushed. */
4001 for (n
= 0; n
< 16; n
++)
4003 if (range
& (1 << n
))
4004 unwind
.frame_size
+= 4;
4009 /* Parse a directive saving FPA registers. */
4012 s_arm_unwind_save_fpa (int reg
)
4018 /* Get Number of registers to transfer. */
4019 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4022 exp
.X_op
= O_illegal
;
4024 if (exp
.X_op
!= O_constant
)
4026 as_bad (_("expected , <constant>"));
4027 ignore_rest_of_line ();
4031 num_regs
= exp
.X_add_number
;
4033 if (num_regs
< 1 || num_regs
> 4)
4035 as_bad (_("number of registers must be in the range [1:4]"));
4036 ignore_rest_of_line ();
4040 demand_empty_rest_of_line ();
4045 op
= 0xb4 | (num_regs
- 1);
4046 add_unwind_opcode (op
, 1);
4051 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4052 add_unwind_opcode (op
, 2);
4054 unwind
.frame_size
+= num_regs
* 12;
4058 /* Parse a directive saving VFP registers for ARMv6 and above. */
4061 s_arm_unwind_save_vfp_armv6 (void)
4066 int num_vfpv3_regs
= 0;
4067 int num_regs_below_16
;
4069 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4072 as_bad (_("expected register list"));
4073 ignore_rest_of_line ();
4077 demand_empty_rest_of_line ();
4079 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4080 than FSTMX/FLDMX-style ones). */
4082 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4084 num_vfpv3_regs
= count
;
4085 else if (start
+ count
> 16)
4086 num_vfpv3_regs
= start
+ count
- 16;
4088 if (num_vfpv3_regs
> 0)
4090 int start_offset
= start
> 16 ? start
- 16 : 0;
4091 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4092 add_unwind_opcode (op
, 2);
4095 /* Generate opcode for registers numbered in the range 0 .. 15. */
4096 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4097 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4098 if (num_regs_below_16
> 0)
4100 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4101 add_unwind_opcode (op
, 2);
4104 unwind
.frame_size
+= count
* 8;
4108 /* Parse a directive saving VFP registers for pre-ARMv6. */
4111 s_arm_unwind_save_vfp (void)
4117 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4120 as_bad (_("expected register list"));
4121 ignore_rest_of_line ();
4125 demand_empty_rest_of_line ();
4130 op
= 0xb8 | (count
- 1);
4131 add_unwind_opcode (op
, 1);
4136 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4137 add_unwind_opcode (op
, 2);
4139 unwind
.frame_size
+= count
* 8 + 4;
4143 /* Parse a directive saving iWMMXt data registers. */
4146 s_arm_unwind_save_mmxwr (void)
4154 if (*input_line_pointer
== '{')
4155 input_line_pointer
++;
4159 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4163 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4168 as_tsktsk (_("register list not in ascending order"));
4171 if (*input_line_pointer
== '-')
4173 input_line_pointer
++;
4174 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4177 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4180 else if (reg
>= hi_reg
)
4182 as_bad (_("bad register range"));
4185 for (; reg
< hi_reg
; reg
++)
4189 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4191 skip_past_char (&input_line_pointer
, '}');
4193 demand_empty_rest_of_line ();
4195 /* Generate any deferred opcodes because we're going to be looking at
4197 flush_pending_unwind ();
4199 for (i
= 0; i
< 16; i
++)
4201 if (mask
& (1 << i
))
4202 unwind
.frame_size
+= 8;
4205 /* Attempt to combine with a previous opcode. We do this because gcc
4206 likes to output separate unwind directives for a single block of
4208 if (unwind
.opcode_count
> 0)
4210 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4211 if ((i
& 0xf8) == 0xc0)
4214 /* Only merge if the blocks are contiguous. */
4217 if ((mask
& 0xfe00) == (1 << 9))
4219 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4220 unwind
.opcode_count
--;
4223 else if (i
== 6 && unwind
.opcode_count
>= 2)
4225 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4229 op
= 0xffff << (reg
- 1);
4231 && ((mask
& op
) == (1u << (reg
- 1))))
4233 op
= (1 << (reg
+ i
+ 1)) - 1;
4234 op
&= ~((1 << reg
) - 1);
4236 unwind
.opcode_count
-= 2;
4243 /* We want to generate opcodes in the order the registers have been
4244 saved, ie. descending order. */
4245 for (reg
= 15; reg
>= -1; reg
--)
4247 /* Save registers in blocks. */
4249 || !(mask
& (1 << reg
)))
4251 /* We found an unsaved reg. Generate opcodes to save the
4258 op
= 0xc0 | (hi_reg
- 10);
4259 add_unwind_opcode (op
, 1);
4264 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4265 add_unwind_opcode (op
, 2);
4274 ignore_rest_of_line ();
4278 s_arm_unwind_save_mmxwcg (void)
4285 if (*input_line_pointer
== '{')
4286 input_line_pointer
++;
4288 skip_whitespace (input_line_pointer
);
4292 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4296 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4302 as_tsktsk (_("register list not in ascending order"));
4305 if (*input_line_pointer
== '-')
4307 input_line_pointer
++;
4308 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4311 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4314 else if (reg
>= hi_reg
)
4316 as_bad (_("bad register range"));
4319 for (; reg
< hi_reg
; reg
++)
4323 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4325 skip_past_char (&input_line_pointer
, '}');
4327 demand_empty_rest_of_line ();
4329 /* Generate any deferred opcodes because we're going to be looking at
4331 flush_pending_unwind ();
4333 for (reg
= 0; reg
< 16; reg
++)
4335 if (mask
& (1 << reg
))
4336 unwind
.frame_size
+= 4;
4339 add_unwind_opcode (op
, 2);
4342 ignore_rest_of_line ();
4346 /* Parse an unwind_save directive.
4347 If the argument is non-zero, this is a .vsave directive. */
4350 s_arm_unwind_save (int arch_v6
)
4353 struct reg_entry
*reg
;
4354 bfd_boolean had_brace
= FALSE
;
4356 if (!unwind
.proc_start
)
4357 as_bad (MISSING_FNSTART
);
4359 /* Figure out what sort of save we have. */
4360 peek
= input_line_pointer
;
4368 reg
= arm_reg_parse_multi (&peek
);
4372 as_bad (_("register expected"));
4373 ignore_rest_of_line ();
4382 as_bad (_("FPA .unwind_save does not take a register list"));
4383 ignore_rest_of_line ();
4386 input_line_pointer
= peek
;
4387 s_arm_unwind_save_fpa (reg
->number
);
4391 s_arm_unwind_save_core ();
4396 s_arm_unwind_save_vfp_armv6 ();
4398 s_arm_unwind_save_vfp ();
4401 case REG_TYPE_MMXWR
:
4402 s_arm_unwind_save_mmxwr ();
4405 case REG_TYPE_MMXWCG
:
4406 s_arm_unwind_save_mmxwcg ();
4410 as_bad (_(".unwind_save does not support this kind of register"));
4411 ignore_rest_of_line ();
4416 /* Parse an unwind_movsp directive. */
4419 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4425 if (!unwind
.proc_start
)
4426 as_bad (MISSING_FNSTART
);
4428 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4431 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4432 ignore_rest_of_line ();
4436 /* Optional constant. */
4437 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4439 if (immediate_for_directive (&offset
) == FAIL
)
4445 demand_empty_rest_of_line ();
4447 if (reg
== REG_SP
|| reg
== REG_PC
)
4449 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4453 if (unwind
.fp_reg
!= REG_SP
)
4454 as_bad (_("unexpected .unwind_movsp directive"));
4456 /* Generate opcode to restore the value. */
4458 add_unwind_opcode (op
, 1);
4460 /* Record the information for later. */
4461 unwind
.fp_reg
= reg
;
4462 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4463 unwind
.sp_restored
= 1;
4466 /* Parse an unwind_pad directive. */
4469 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4473 if (!unwind
.proc_start
)
4474 as_bad (MISSING_FNSTART
);
4476 if (immediate_for_directive (&offset
) == FAIL
)
4481 as_bad (_("stack increment must be multiple of 4"));
4482 ignore_rest_of_line ();
4486 /* Don't generate any opcodes, just record the details for later. */
4487 unwind
.frame_size
+= offset
;
4488 unwind
.pending_offset
+= offset
;
4490 demand_empty_rest_of_line ();
4493 /* Parse an unwind_setfp directive. */
4496 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4502 if (!unwind
.proc_start
)
4503 as_bad (MISSING_FNSTART
);
4505 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4506 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4509 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4511 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4513 as_bad (_("expected <reg>, <reg>"));
4514 ignore_rest_of_line ();
4518 /* Optional constant. */
4519 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4521 if (immediate_for_directive (&offset
) == FAIL
)
4527 demand_empty_rest_of_line ();
4529 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4531 as_bad (_("register must be either sp or set by a previous"
4532 "unwind_movsp directive"));
4536 /* Don't generate any opcodes, just record the information for later. */
4537 unwind
.fp_reg
= fp_reg
;
4539 if (sp_reg
== REG_SP
)
4540 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4542 unwind
.fp_offset
-= offset
;
4545 /* Parse an unwind_raw directive. */
4548 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4551 /* This is an arbitrary limit. */
4552 unsigned char op
[16];
4555 if (!unwind
.proc_start
)
4556 as_bad (MISSING_FNSTART
);
4559 if (exp
.X_op
== O_constant
4560 && skip_past_comma (&input_line_pointer
) != FAIL
)
4562 unwind
.frame_size
+= exp
.X_add_number
;
4566 exp
.X_op
= O_illegal
;
4568 if (exp
.X_op
!= O_constant
)
4570 as_bad (_("expected <offset>, <opcode>"));
4571 ignore_rest_of_line ();
4577 /* Parse the opcode. */
4582 as_bad (_("unwind opcode too long"));
4583 ignore_rest_of_line ();
4585 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4587 as_bad (_("invalid unwind opcode"));
4588 ignore_rest_of_line ();
4591 op
[count
++] = exp
.X_add_number
;
4593 /* Parse the next byte. */
4594 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4600 /* Add the opcode bytes in reverse order. */
4602 add_unwind_opcode (op
[count
], 1);
4604 demand_empty_rest_of_line ();
4608 /* Parse a .eabi_attribute directive. */
4611 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4613 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4615 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4616 attributes_set_explicitly
[tag
] = 1;
4619 /* Emit a tls fix for the symbol. */
4622 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4626 #ifdef md_flush_pending_output
4627 md_flush_pending_output ();
4630 #ifdef md_cons_align
4634 /* Since we're just labelling the code, there's no need to define a
4637 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4638 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4639 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4640 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4642 #endif /* OBJ_ELF */
4644 static void s_arm_arch (int);
4645 static void s_arm_object_arch (int);
4646 static void s_arm_cpu (int);
4647 static void s_arm_fpu (int);
4648 static void s_arm_arch_extension (int);
4653 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4660 if (exp
.X_op
== O_symbol
)
4661 exp
.X_op
= O_secrel
;
4663 emit_expr (&exp
, 4);
4665 while (*input_line_pointer
++ == ',');
4667 input_line_pointer
--;
4668 demand_empty_rest_of_line ();
4672 /* This table describes all the machine specific pseudo-ops the assembler
4673 has to support. The fields are:
4674 pseudo-op name without dot
4675 function to call to execute this pseudo-op
4676 Integer arg to pass to the function. */
4678 const pseudo_typeS md_pseudo_table
[] =
4680 /* Never called because '.req' does not start a line. */
4681 { "req", s_req
, 0 },
4682 /* Following two are likewise never called. */
4685 { "unreq", s_unreq
, 0 },
4686 { "bss", s_bss
, 0 },
4687 { "align", s_align_ptwo
, 2 },
4688 { "arm", s_arm
, 0 },
4689 { "thumb", s_thumb
, 0 },
4690 { "code", s_code
, 0 },
4691 { "force_thumb", s_force_thumb
, 0 },
4692 { "thumb_func", s_thumb_func
, 0 },
4693 { "thumb_set", s_thumb_set
, 0 },
4694 { "even", s_even
, 0 },
4695 { "ltorg", s_ltorg
, 0 },
4696 { "pool", s_ltorg
, 0 },
4697 { "syntax", s_syntax
, 0 },
4698 { "cpu", s_arm_cpu
, 0 },
4699 { "arch", s_arm_arch
, 0 },
4700 { "object_arch", s_arm_object_arch
, 0 },
4701 { "fpu", s_arm_fpu
, 0 },
4702 { "arch_extension", s_arm_arch_extension
, 0 },
4704 { "word", s_arm_elf_cons
, 4 },
4705 { "long", s_arm_elf_cons
, 4 },
4706 { "inst.n", s_arm_elf_inst
, 2 },
4707 { "inst.w", s_arm_elf_inst
, 4 },
4708 { "inst", s_arm_elf_inst
, 0 },
4709 { "rel31", s_arm_rel31
, 0 },
4710 { "fnstart", s_arm_unwind_fnstart
, 0 },
4711 { "fnend", s_arm_unwind_fnend
, 0 },
4712 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4713 { "personality", s_arm_unwind_personality
, 0 },
4714 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4715 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4716 { "save", s_arm_unwind_save
, 0 },
4717 { "vsave", s_arm_unwind_save
, 1 },
4718 { "movsp", s_arm_unwind_movsp
, 0 },
4719 { "pad", s_arm_unwind_pad
, 0 },
4720 { "setfp", s_arm_unwind_setfp
, 0 },
4721 { "unwind_raw", s_arm_unwind_raw
, 0 },
4722 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4723 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4727 /* These are used for dwarf. */
4731 /* These are used for dwarf2. */
4732 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4733 { "loc", dwarf2_directive_loc
, 0 },
4734 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4736 { "extend", float_cons
, 'x' },
4737 { "ldouble", float_cons
, 'x' },
4738 { "packed", float_cons
, 'p' },
4740 {"secrel32", pe_directive_secrel
, 0},
4743 /* These are for compatibility with CodeComposer Studio. */
4744 {"ref", s_ccs_ref
, 0},
4745 {"def", s_ccs_def
, 0},
4746 {"asmfunc", s_ccs_asmfunc
, 0},
4747 {"endasmfunc", s_ccs_endasmfunc
, 0},
4752 /* Parser functions used exclusively in instruction operands. */
4754 /* Generic immediate-value read function for use in insn parsing.
4755 STR points to the beginning of the immediate (the leading #);
4756 VAL receives the value; if the value is outside [MIN, MAX]
4757 issue an error. PREFIX_OPT is true if the immediate prefix is
4761 parse_immediate (char **str
, int *val
, int min
, int max
,
4762 bfd_boolean prefix_opt
)
4765 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4766 if (exp
.X_op
!= O_constant
)
4768 inst
.error
= _("constant expression required");
4772 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4774 inst
.error
= _("immediate value out of range");
4778 *val
= exp
.X_add_number
;
4782 /* Less-generic immediate-value read function with the possibility of loading a
4783 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4784 instructions. Puts the result directly in inst.operands[i]. */
4787 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4788 bfd_boolean allow_symbol_p
)
4791 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4794 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4796 if (exp_p
->X_op
== O_constant
)
4798 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4799 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4800 O_constant. We have to be careful not to break compilation for
4801 32-bit X_add_number, though. */
4802 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4804 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4805 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4807 inst
.operands
[i
].regisimm
= 1;
4810 else if (exp_p
->X_op
== O_big
4811 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4813 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4815 /* Bignums have their least significant bits in
4816 generic_bignum[0]. Make sure we put 32 bits in imm and
4817 32 bits in reg, in a (hopefully) portable way. */
4818 gas_assert (parts
!= 0);
4820 /* Make sure that the number is not too big.
4821 PR 11972: Bignums can now be sign-extended to the
4822 size of a .octa so check that the out of range bits
4823 are all zero or all one. */
4824 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4826 LITTLENUM_TYPE m
= -1;
4828 if (generic_bignum
[parts
* 2] != 0
4829 && generic_bignum
[parts
* 2] != m
)
4832 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4833 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4837 inst
.operands
[i
].imm
= 0;
4838 for (j
= 0; j
< parts
; j
++, idx
++)
4839 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4840 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4841 inst
.operands
[i
].reg
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].regisimm
= 1;
4847 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4855 /* Returns the pseudo-register number of an FPA immediate constant,
4856 or FAIL if there isn't a valid constant here. */
4859 parse_fpa_immediate (char ** str
)
4861 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4867 /* First try and match exact strings, this is to guarantee
4868 that some formats will work even for cross assembly. */
4870 for (i
= 0; fp_const
[i
]; i
++)
4872 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4876 *str
+= strlen (fp_const
[i
]);
4877 if (is_end_of_line
[(unsigned char) **str
])
4883 /* Just because we didn't get a match doesn't mean that the constant
4884 isn't valid, just that it is in a format that we don't
4885 automatically recognize. Try parsing it with the standard
4886 expression routines. */
4888 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4890 /* Look for a raw floating point number. */
4891 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4892 && is_end_of_line
[(unsigned char) *save_in
])
4894 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4896 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4898 if (words
[j
] != fp_values
[i
][j
])
4902 if (j
== MAX_LITTLENUMS
)
4910 /* Try and parse a more complex expression, this will probably fail
4911 unless the code uses a floating point prefix (eg "0f"). */
4912 save_in
= input_line_pointer
;
4913 input_line_pointer
= *str
;
4914 if (expression (&exp
) == absolute_section
4915 && exp
.X_op
== O_big
4916 && exp
.X_add_number
< 0)
4918 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4920 #define X_PRECISION 5
4921 #define E_PRECISION 15L
4922 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4924 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4926 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4928 if (words
[j
] != fp_values
[i
][j
])
4932 if (j
== MAX_LITTLENUMS
)
4934 *str
= input_line_pointer
;
4935 input_line_pointer
= save_in
;
4942 *str
= input_line_pointer
;
4943 input_line_pointer
= save_in
;
4944 inst
.error
= _("invalid FPA immediate expression");
4948 /* Returns 1 if a number has "quarter-precision" float format
4949 0baBbbbbbc defgh000 00000000 00000000. */
4952 is_quarter_float (unsigned imm
)
4954 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4955 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4959 /* Detect the presence of a floating point or integer zero constant,
4963 parse_ifimm_zero (char **in
)
4967 if (!is_immediate_prefix (**in
))
4972 /* Accept #0x0 as a synonym for #0. */
4973 if (strncmp (*in
, "0x", 2) == 0)
4976 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4981 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4982 &generic_floating_point_number
);
4985 && generic_floating_point_number
.sign
== '+'
4986 && (generic_floating_point_number
.low
4987 > generic_floating_point_number
.leader
))
4993 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4994 0baBbbbbbc defgh000 00000000 00000000.
4995 The zero and minus-zero cases need special handling, since they can't be
4996 encoded in the "quarter-precision" float format, but can nonetheless be
4997 loaded as integer constants. */
5000 parse_qfloat_immediate (char **ccp
, int *immed
)
5004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5005 int found_fpchar
= 0;
5007 skip_past_char (&str
, '#');
5009 /* We must not accidentally parse an integer as a floating-point number. Make
5010 sure that the value we parse is not an integer by checking for special
5011 characters '.' or 'e'.
5012 FIXME: This is a horrible hack, but doing better is tricky because type
5013 information isn't in a very usable state at parse time. */
5015 skip_whitespace (fpnum
);
5017 if (strncmp (fpnum
, "0x", 2) == 0)
5021 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5022 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5032 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5034 unsigned fpword
= 0;
5037 /* Our FP word must be 32 bits (single-precision FP). */
5038 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5040 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5044 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5057 /* Shift operands. */
5060 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5063 struct asm_shift_name
5066 enum shift_kind kind
;
5069 /* Third argument to parse_shift. */
5070 enum parse_shift_mode
5072 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5073 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5074 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5075 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5076 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5079 /* Parse a <shift> specifier on an ARM data processing instruction.
5080 This has three forms:
5082 (LSL|LSR|ASL|ASR|ROR) Rs
5083 (LSL|LSR|ASL|ASR|ROR) #imm
5086 Note that ASL is assimilated to LSL in the instruction encoding, and
5087 RRX to ROR #0 (which cannot be written as such). */
5090 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5092 const struct asm_shift_name
*shift_name
;
5093 enum shift_kind shift
;
5098 for (p
= *str
; ISALPHA (*p
); p
++)
5103 inst
.error
= _("shift expression expected");
5107 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5110 if (shift_name
== NULL
)
5112 inst
.error
= _("shift expression expected");
5116 shift
= shift_name
->kind
;
5120 case NO_SHIFT_RESTRICT
:
5121 case SHIFT_IMMEDIATE
: break;
5123 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5124 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5126 inst
.error
= _("'LSL' or 'ASR' required");
5131 case SHIFT_LSL_IMMEDIATE
:
5132 if (shift
!= SHIFT_LSL
)
5134 inst
.error
= _("'LSL' required");
5139 case SHIFT_ASR_IMMEDIATE
:
5140 if (shift
!= SHIFT_ASR
)
5142 inst
.error
= _("'ASR' required");
5150 if (shift
!= SHIFT_RRX
)
5152 /* Whitespace can appear here if the next thing is a bare digit. */
5153 skip_whitespace (p
);
5155 if (mode
== NO_SHIFT_RESTRICT
5156 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5158 inst
.operands
[i
].imm
= reg
;
5159 inst
.operands
[i
].immisreg
= 1;
5161 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5164 inst
.operands
[i
].shift_kind
= shift
;
5165 inst
.operands
[i
].shifted
= 1;
5170 /* Parse a <shifter_operand> for an ARM data processing instruction:
5173 #<immediate>, <rotate>
5177 where <shift> is defined by parse_shift above, and <rotate> is a
5178 multiple of 2 between 0 and 30. Validation of immediate operands
5179 is deferred to md_apply_fix. */
5182 parse_shifter_operand (char **str
, int i
)
5187 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5189 inst
.operands
[i
].reg
= value
;
5190 inst
.operands
[i
].isreg
= 1;
5192 /* parse_shift will override this if appropriate */
5193 inst
.reloc
.exp
.X_op
= O_constant
;
5194 inst
.reloc
.exp
.X_add_number
= 0;
5196 if (skip_past_comma (str
) == FAIL
)
5199 /* Shift operation on register. */
5200 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5203 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5206 if (skip_past_comma (str
) == SUCCESS
)
5208 /* #x, y -- ie explicit rotation by Y. */
5209 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5212 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5214 inst
.error
= _("constant expression expected");
5218 value
= exp
.X_add_number
;
5219 if (value
< 0 || value
> 30 || value
% 2 != 0)
5221 inst
.error
= _("invalid rotation");
5224 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5226 inst
.error
= _("invalid constant");
5230 /* Encode as specified. */
5231 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5235 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5236 inst
.reloc
.pc_rel
= 0;
5240 /* Group relocation information. Each entry in the table contains the
5241 textual name of the relocation as may appear in assembler source
5242 and must end with a colon.
5243 Along with this textual name are the relocation codes to be used if
5244 the corresponding instruction is an ALU instruction (ADD or SUB only),
5245 an LDR, an LDRS, or an LDC. */
5247 struct group_reloc_table_entry
5258 /* Varieties of non-ALU group relocation. */
5265 static struct group_reloc_table_entry group_reloc_table
[] =
5266 { /* Program counter relative: */
5268 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5273 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5274 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5278 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5283 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5284 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5285 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5286 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5288 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5289 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5290 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5291 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5292 /* Section base relative */
5294 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5299 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5300 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5301 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5302 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5304 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5309 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5310 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5311 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5312 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5314 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5315 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5316 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5317 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5318 /* Absolute thumb alu relocations. */
5320 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5325 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5330 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5335 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5340 /* Given the address of a pointer pointing to the textual name of a group
5341 relocation as may appear in assembler source, attempt to find its details
5342 in group_reloc_table. The pointer will be updated to the character after
5343 the trailing colon. On failure, FAIL will be returned; SUCCESS
5344 otherwise. On success, *entry will be updated to point at the relevant
5345 group_reloc_table entry. */
5348 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5351 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5353 int length
= strlen (group_reloc_table
[i
].name
);
5355 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5356 && (*str
)[length
] == ':')
5358 *out
= &group_reloc_table
[i
];
5359 *str
+= (length
+ 1);
5367 /* Parse a <shifter_operand> for an ARM data processing instruction
5368 (as for parse_shifter_operand) where group relocations are allowed:
5371 #<immediate>, <rotate>
5372 #:<group_reloc>:<expression>
5376 where <group_reloc> is one of the strings defined in group_reloc_table.
5377 The hashes are optional.
5379 Everything else is as for parse_shifter_operand. */
5381 static parse_operand_result
5382 parse_shifter_operand_group_reloc (char **str
, int i
)
5384 /* Determine if we have the sequence of characters #: or just :
5385 coming next. If we do, then we check for a group relocation.
5386 If we don't, punt the whole lot to parse_shifter_operand. */
5388 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5389 || (*str
)[0] == ':')
5391 struct group_reloc_table_entry
*entry
;
5393 if ((*str
)[0] == '#')
5398 /* Try to parse a group relocation. Anything else is an error. */
5399 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5401 inst
.error
= _("unknown group relocation");
5402 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5405 /* We now have the group relocation table entry corresponding to
5406 the name in the assembler source. Next, we parse the expression. */
5407 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5408 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5410 /* Record the relocation type (always the ALU variant here). */
5411 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5412 gas_assert (inst
.reloc
.type
!= 0);
5414 return PARSE_OPERAND_SUCCESS
;
5417 return parse_shifter_operand (str
, i
) == SUCCESS
5418 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5420 /* Never reached. */
5423 /* Parse a Neon alignment expression. Information is written to
5424 inst.operands[i]. We assume the initial ':' has been skipped.
5426 align .imm = align << 8, .immisalign=1, .preind=0 */
5427 static parse_operand_result
5428 parse_neon_alignment (char **str
, int i
)
5433 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5435 if (exp
.X_op
!= O_constant
)
5437 inst
.error
= _("alignment must be constant");
5438 return PARSE_OPERAND_FAIL
;
5441 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5442 inst
.operands
[i
].immisalign
= 1;
5443 /* Alignments are not pre-indexes. */
5444 inst
.operands
[i
].preind
= 0;
5447 return PARSE_OPERAND_SUCCESS
;
5450 /* Parse all forms of an ARM address expression. Information is written
5451 to inst.operands[i] and/or inst.reloc.
5453 Preindexed addressing (.preind=1):
5455 [Rn, #offset] .reg=Rn .reloc.exp=offset
5456 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5457 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5458 .shift_kind=shift .reloc.exp=shift_imm
5460 These three may have a trailing ! which causes .writeback to be set also.
5462 Postindexed addressing (.postind=1, .writeback=1):
5464 [Rn], #offset .reg=Rn .reloc.exp=offset
5465 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5467 .shift_kind=shift .reloc.exp=shift_imm
5469 Unindexed addressing (.preind=0, .postind=0):
5471 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5475 [Rn]{!} shorthand for [Rn,#0]{!}
5476 =immediate .isreg=0 .reloc.exp=immediate
5477 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5479 It is the caller's responsibility to check for addressing modes not
5480 supported by the instruction, and to set inst.reloc.type. */
5482 static parse_operand_result
5483 parse_address_main (char **str
, int i
, int group_relocations
,
5484 group_reloc_type group_type
)
5489 if (skip_past_char (&p
, '[') == FAIL
)
5491 if (skip_past_char (&p
, '=') == FAIL
)
5493 /* Bare address - translate to PC-relative offset. */
5494 inst
.reloc
.pc_rel
= 1;
5495 inst
.operands
[i
].reg
= REG_PC
;
5496 inst
.operands
[i
].isreg
= 1;
5497 inst
.operands
[i
].preind
= 1;
5499 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5500 return PARSE_OPERAND_FAIL
;
5502 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5503 /*allow_symbol_p=*/TRUE
))
5504 return PARSE_OPERAND_FAIL
;
5507 return PARSE_OPERAND_SUCCESS
;
5510 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5511 skip_whitespace (p
);
5513 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5515 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5516 return PARSE_OPERAND_FAIL
;
5518 inst
.operands
[i
].reg
= reg
;
5519 inst
.operands
[i
].isreg
= 1;
5521 if (skip_past_comma (&p
) == SUCCESS
)
5523 inst
.operands
[i
].preind
= 1;
5526 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5528 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5530 inst
.operands
[i
].imm
= reg
;
5531 inst
.operands
[i
].immisreg
= 1;
5533 if (skip_past_comma (&p
) == SUCCESS
)
5534 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5535 return PARSE_OPERAND_FAIL
;
5537 else if (skip_past_char (&p
, ':') == SUCCESS
)
5539 /* FIXME: '@' should be used here, but it's filtered out by generic
5540 code before we get to see it here. This may be subject to
5542 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5544 if (result
!= PARSE_OPERAND_SUCCESS
)
5549 if (inst
.operands
[i
].negative
)
5551 inst
.operands
[i
].negative
= 0;
5555 if (group_relocations
5556 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5558 struct group_reloc_table_entry
*entry
;
5560 /* Skip over the #: or : sequence. */
5566 /* Try to parse a group relocation. Anything else is an
5568 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5570 inst
.error
= _("unknown group relocation");
5571 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5574 /* We now have the group relocation table entry corresponding to
5575 the name in the assembler source. Next, we parse the
5577 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5578 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5580 /* Record the relocation type. */
5584 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5588 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5599 if (inst
.reloc
.type
== 0)
5601 inst
.error
= _("this group relocation is not allowed on this instruction");
5602 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5608 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5609 return PARSE_OPERAND_FAIL
;
5610 /* If the offset is 0, find out if it's a +0 or -0. */
5611 if (inst
.reloc
.exp
.X_op
== O_constant
5612 && inst
.reloc
.exp
.X_add_number
== 0)
5614 skip_whitespace (q
);
5618 skip_whitespace (q
);
5621 inst
.operands
[i
].negative
= 1;
5626 else if (skip_past_char (&p
, ':') == SUCCESS
)
5628 /* FIXME: '@' should be used here, but it's filtered out by generic code
5629 before we get to see it here. This may be subject to change. */
5630 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5632 if (result
!= PARSE_OPERAND_SUCCESS
)
5636 if (skip_past_char (&p
, ']') == FAIL
)
5638 inst
.error
= _("']' expected");
5639 return PARSE_OPERAND_FAIL
;
5642 if (skip_past_char (&p
, '!') == SUCCESS
)
5643 inst
.operands
[i
].writeback
= 1;
5645 else if (skip_past_comma (&p
) == SUCCESS
)
5647 if (skip_past_char (&p
, '{') == SUCCESS
)
5649 /* [Rn], {expr} - unindexed, with option */
5650 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5651 0, 255, TRUE
) == FAIL
)
5652 return PARSE_OPERAND_FAIL
;
5654 if (skip_past_char (&p
, '}') == FAIL
)
5656 inst
.error
= _("'}' expected at end of 'option' field");
5657 return PARSE_OPERAND_FAIL
;
5659 if (inst
.operands
[i
].preind
)
5661 inst
.error
= _("cannot combine index with option");
5662 return PARSE_OPERAND_FAIL
;
5665 return PARSE_OPERAND_SUCCESS
;
5669 inst
.operands
[i
].postind
= 1;
5670 inst
.operands
[i
].writeback
= 1;
5672 if (inst
.operands
[i
].preind
)
5674 inst
.error
= _("cannot combine pre- and post-indexing");
5675 return PARSE_OPERAND_FAIL
;
5679 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5681 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5683 /* We might be using the immediate for alignment already. If we
5684 are, OR the register number into the low-order bits. */
5685 if (inst
.operands
[i
].immisalign
)
5686 inst
.operands
[i
].imm
|= reg
;
5688 inst
.operands
[i
].imm
= reg
;
5689 inst
.operands
[i
].immisreg
= 1;
5691 if (skip_past_comma (&p
) == SUCCESS
)
5692 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5693 return PARSE_OPERAND_FAIL
;
5698 if (inst
.operands
[i
].negative
)
5700 inst
.operands
[i
].negative
= 0;
5703 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5704 return PARSE_OPERAND_FAIL
;
5705 /* If the offset is 0, find out if it's a +0 or -0. */
5706 if (inst
.reloc
.exp
.X_op
== O_constant
5707 && inst
.reloc
.exp
.X_add_number
== 0)
5709 skip_whitespace (q
);
5713 skip_whitespace (q
);
5716 inst
.operands
[i
].negative
= 1;
5722 /* If at this point neither .preind nor .postind is set, we have a
5723 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5724 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5726 inst
.operands
[i
].preind
= 1;
5727 inst
.reloc
.exp
.X_op
= O_constant
;
5728 inst
.reloc
.exp
.X_add_number
= 0;
5731 return PARSE_OPERAND_SUCCESS
;
5735 parse_address (char **str
, int i
)
5737 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5741 static parse_operand_result
5742 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5744 return parse_address_main (str
, i
, 1, type
);
5747 /* Parse an operand for a MOVW or MOVT instruction. */
5749 parse_half (char **str
)
5754 skip_past_char (&p
, '#');
5755 if (strncasecmp (p
, ":lower16:", 9) == 0)
5756 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5757 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5758 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5760 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5763 skip_whitespace (p
);
5766 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5769 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5771 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5773 inst
.error
= _("constant expression expected");
5776 if (inst
.reloc
.exp
.X_add_number
< 0
5777 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5779 inst
.error
= _("immediate value out of range");
5787 /* Miscellaneous. */
5789 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5790 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5792 parse_psr (char **str
, bfd_boolean lhs
)
5795 unsigned long psr_field
;
5796 const struct asm_psr
*psr
;
5798 bfd_boolean is_apsr
= FALSE
;
5799 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5801 /* PR gas/12698: If the user has specified -march=all then m_profile will
5802 be TRUE, but we want to ignore it in this case as we are building for any
5803 CPU type, including non-m variants. */
5804 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5807 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5808 feature for ease of use and backwards compatibility. */
5810 if (strncasecmp (p
, "SPSR", 4) == 0)
5813 goto unsupported_psr
;
5815 psr_field
= SPSR_BIT
;
5817 else if (strncasecmp (p
, "CPSR", 4) == 0)
5820 goto unsupported_psr
;
5824 else if (strncasecmp (p
, "APSR", 4) == 0)
5826 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5827 and ARMv7-R architecture CPUs. */
5836 while (ISALNUM (*p
) || *p
== '_');
5838 if (strncasecmp (start
, "iapsr", 5) == 0
5839 || strncasecmp (start
, "eapsr", 5) == 0
5840 || strncasecmp (start
, "xpsr", 4) == 0
5841 || strncasecmp (start
, "psr", 3) == 0)
5842 p
= start
+ strcspn (start
, "rR") + 1;
5844 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5850 /* If APSR is being written, a bitfield may be specified. Note that
5851 APSR itself is handled above. */
5852 if (psr
->field
<= 3)
5854 psr_field
= psr
->field
;
5860 /* M-profile MSR instructions have the mask field set to "10", except
5861 *PSR variants which modify APSR, which may use a different mask (and
5862 have been handled already). Do that by setting the PSR_f field
5864 return psr
->field
| (lhs
? PSR_f
: 0);
5867 goto unsupported_psr
;
5873 /* A suffix follows. */
5879 while (ISALNUM (*p
) || *p
== '_');
5883 /* APSR uses a notation for bits, rather than fields. */
5884 unsigned int nzcvq_bits
= 0;
5885 unsigned int g_bit
= 0;
5888 for (bit
= start
; bit
!= p
; bit
++)
5890 switch (TOLOWER (*bit
))
5893 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5897 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5901 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5913 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5917 inst
.error
= _("unexpected bit specified after APSR");
5922 if (nzcvq_bits
== 0x1f)
5927 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5929 inst
.error
= _("selected processor does not "
5930 "support DSP extension");
5937 if ((nzcvq_bits
& 0x20) != 0
5938 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5939 || (g_bit
& 0x2) != 0)
5941 inst
.error
= _("bad bitmask specified after APSR");
5947 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5952 psr_field
|= psr
->field
;
5958 goto error
; /* Garbage after "[CS]PSR". */
5960 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5961 is deprecated, but allow it anyway. */
5965 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5968 else if (!m_profile
)
5969 /* These bits are never right for M-profile devices: don't set them
5970 (only code paths which read/write APSR reach here). */
5971 psr_field
|= (PSR_c
| PSR_f
);
5977 inst
.error
= _("selected processor does not support requested special "
5978 "purpose register");
5982 inst
.error
= _("flag for {c}psr instruction expected");
5986 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5987 value suitable for splatting into the AIF field of the instruction. */
5990 parse_cps_flags (char **str
)
5999 case '\0': case ',':
6002 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6003 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6004 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6007 inst
.error
= _("unrecognized CPS flag");
6012 if (saw_a_flag
== 0)
6014 inst
.error
= _("missing CPS flags");
6022 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6023 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6026 parse_endian_specifier (char **str
)
6031 if (strncasecmp (s
, "BE", 2))
6033 else if (strncasecmp (s
, "LE", 2))
6037 inst
.error
= _("valid endian specifiers are be or le");
6041 if (ISALNUM (s
[2]) || s
[2] == '_')
6043 inst
.error
= _("valid endian specifiers are be or le");
6048 return little_endian
;
6051 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6052 value suitable for poking into the rotate field of an sxt or sxta
6053 instruction, or FAIL on error. */
6056 parse_ror (char **str
)
6061 if (strncasecmp (s
, "ROR", 3) == 0)
6065 inst
.error
= _("missing rotation field after comma");
6069 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6074 case 0: *str
= s
; return 0x0;
6075 case 8: *str
= s
; return 0x1;
6076 case 16: *str
= s
; return 0x2;
6077 case 24: *str
= s
; return 0x3;
6080 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6085 /* Parse a conditional code (from conds[] below). The value returned is in the
6086 range 0 .. 14, or FAIL. */
6088 parse_cond (char **str
)
6091 const struct asm_cond
*c
;
6093 /* Condition codes are always 2 characters, so matching up to
6094 3 characters is sufficient. */
6099 while (ISALPHA (*q
) && n
< 3)
6101 cond
[n
] = TOLOWER (*q
);
6106 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6109 inst
.error
= _("condition required");
6117 /* Record a use of the given feature. */
6119 record_feature_use (const arm_feature_set
*feature
)
6122 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6124 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6127 /* If the given feature available in the selected CPU, mark it as used.
6128 Returns TRUE iff feature is available. */
6130 mark_feature_used (const arm_feature_set
*feature
)
6132 /* Ensure the option is valid on the current architecture. */
6133 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6136 /* Add the appropriate architecture feature for the barrier option used.
6138 record_feature_use (feature
);
6143 /* Parse an option for a barrier instruction. Returns the encoding for the
6146 parse_barrier (char **str
)
6149 const struct asm_barrier_opt
*o
;
6152 while (ISALPHA (*q
))
6155 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6160 if (!mark_feature_used (&o
->arch
))
6167 /* Parse the operands of a table branch instruction. Similar to a memory
6170 parse_tb (char **str
)
6175 if (skip_past_char (&p
, '[') == FAIL
)
6177 inst
.error
= _("'[' expected");
6181 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6183 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6186 inst
.operands
[0].reg
= reg
;
6188 if (skip_past_comma (&p
) == FAIL
)
6190 inst
.error
= _("',' expected");
6194 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6196 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6199 inst
.operands
[0].imm
= reg
;
6201 if (skip_past_comma (&p
) == SUCCESS
)
6203 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6205 if (inst
.reloc
.exp
.X_add_number
!= 1)
6207 inst
.error
= _("invalid shift");
6210 inst
.operands
[0].shifted
= 1;
6213 if (skip_past_char (&p
, ']') == FAIL
)
6215 inst
.error
= _("']' expected");
6222 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6223 information on the types the operands can take and how they are encoded.
6224 Up to four operands may be read; this function handles setting the
6225 ".present" field for each read operand itself.
6226 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6227 else returns FAIL. */
6230 parse_neon_mov (char **str
, int *which_operand
)
6232 int i
= *which_operand
, val
;
6233 enum arm_reg_type rtype
;
6235 struct neon_type_el optype
;
6237 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6239 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6240 inst
.operands
[i
].reg
= val
;
6241 inst
.operands
[i
].isscalar
= 1;
6242 inst
.operands
[i
].vectype
= optype
;
6243 inst
.operands
[i
++].present
= 1;
6245 if (skip_past_comma (&ptr
) == FAIL
)
6248 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isreg
= 1;
6253 inst
.operands
[i
].present
= 1;
6255 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6258 /* Cases 0, 1, 2, 3, 5 (D only). */
6259 if (skip_past_comma (&ptr
) == FAIL
)
6262 inst
.operands
[i
].reg
= val
;
6263 inst
.operands
[i
].isreg
= 1;
6264 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6265 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6266 inst
.operands
[i
].isvec
= 1;
6267 inst
.operands
[i
].vectype
= optype
;
6268 inst
.operands
[i
++].present
= 1;
6270 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6272 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6273 Case 13: VMOV <Sd>, <Rm> */
6274 inst
.operands
[i
].reg
= val
;
6275 inst
.operands
[i
].isreg
= 1;
6276 inst
.operands
[i
].present
= 1;
6278 if (rtype
== REG_TYPE_NQ
)
6280 first_error (_("can't use Neon quad register here"));
6283 else if (rtype
!= REG_TYPE_VFS
)
6286 if (skip_past_comma (&ptr
) == FAIL
)
6288 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6290 inst
.operands
[i
].reg
= val
;
6291 inst
.operands
[i
].isreg
= 1;
6292 inst
.operands
[i
].present
= 1;
6295 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6298 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6299 Case 1: VMOV<c><q> <Dd>, <Dm>
6300 Case 8: VMOV.F32 <Sd>, <Sm>
6301 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6306 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6307 inst
.operands
[i
].isvec
= 1;
6308 inst
.operands
[i
].vectype
= optype
;
6309 inst
.operands
[i
].present
= 1;
6311 if (skip_past_comma (&ptr
) == SUCCESS
)
6316 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6319 inst
.operands
[i
].reg
= val
;
6320 inst
.operands
[i
].isreg
= 1;
6321 inst
.operands
[i
++].present
= 1;
6323 if (skip_past_comma (&ptr
) == FAIL
)
6326 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6329 inst
.operands
[i
].reg
= val
;
6330 inst
.operands
[i
].isreg
= 1;
6331 inst
.operands
[i
].present
= 1;
6334 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6335 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6336 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6337 Case 10: VMOV.F32 <Sd>, #<imm>
6338 Case 11: VMOV.F64 <Dd>, #<imm> */
6339 inst
.operands
[i
].immisfloat
= 1;
6340 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6342 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6343 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6347 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6351 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6354 inst
.operands
[i
].reg
= val
;
6355 inst
.operands
[i
].isreg
= 1;
6356 inst
.operands
[i
++].present
= 1;
6358 if (skip_past_comma (&ptr
) == FAIL
)
6361 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6363 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6364 inst
.operands
[i
].reg
= val
;
6365 inst
.operands
[i
].isscalar
= 1;
6366 inst
.operands
[i
].present
= 1;
6367 inst
.operands
[i
].vectype
= optype
;
6369 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6371 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isreg
= 1;
6374 inst
.operands
[i
++].present
= 1;
6376 if (skip_past_comma (&ptr
) == FAIL
)
6379 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6382 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6386 inst
.operands
[i
].reg
= val
;
6387 inst
.operands
[i
].isreg
= 1;
6388 inst
.operands
[i
].isvec
= 1;
6389 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6390 inst
.operands
[i
].vectype
= optype
;
6391 inst
.operands
[i
].present
= 1;
6393 if (rtype
== REG_TYPE_VFS
)
6397 if (skip_past_comma (&ptr
) == FAIL
)
6399 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6402 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6405 inst
.operands
[i
].reg
= val
;
6406 inst
.operands
[i
].isreg
= 1;
6407 inst
.operands
[i
].isvec
= 1;
6408 inst
.operands
[i
].issingle
= 1;
6409 inst
.operands
[i
].vectype
= optype
;
6410 inst
.operands
[i
].present
= 1;
6413 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6417 inst
.operands
[i
].reg
= val
;
6418 inst
.operands
[i
].isreg
= 1;
6419 inst
.operands
[i
].isvec
= 1;
6420 inst
.operands
[i
].issingle
= 1;
6421 inst
.operands
[i
].vectype
= optype
;
6422 inst
.operands
[i
].present
= 1;
6427 first_error (_("parse error"));
6431 /* Successfully parsed the operands. Update args. */
6437 first_error (_("expected comma"));
6441 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6445 /* Use this macro when the operand constraints are different
6446 for ARM and THUMB (e.g. ldrd). */
6447 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6448 ((arm_operand) | ((thumb_operand) << 16))
6450 /* Matcher codes for parse_operands. */
6451 enum operand_parse_code
6453 OP_stop
, /* end of line */
6455 OP_RR
, /* ARM register */
6456 OP_RRnpc
, /* ARM register, not r15 */
6457 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6458 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6459 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6460 optional trailing ! */
6461 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6462 OP_RCP
, /* Coprocessor number */
6463 OP_RCN
, /* Coprocessor register */
6464 OP_RF
, /* FPA register */
6465 OP_RVS
, /* VFP single precision register */
6466 OP_RVD
, /* VFP double precision register (0..15) */
6467 OP_RND
, /* Neon double precision register (0..31) */
6468 OP_RNQ
, /* Neon quad precision register */
6469 OP_RVSD
, /* VFP single or double precision register */
6470 OP_RNDQ
, /* Neon double or quad precision register */
6471 OP_RNSDQ
, /* Neon single, double or quad precision register */
6472 OP_RNSC
, /* Neon scalar D[X] */
6473 OP_RVC
, /* VFP control register */
6474 OP_RMF
, /* Maverick F register */
6475 OP_RMD
, /* Maverick D register */
6476 OP_RMFX
, /* Maverick FX register */
6477 OP_RMDX
, /* Maverick DX register */
6478 OP_RMAX
, /* Maverick AX register */
6479 OP_RMDS
, /* Maverick DSPSC register */
6480 OP_RIWR
, /* iWMMXt wR register */
6481 OP_RIWC
, /* iWMMXt wC register */
6482 OP_RIWG
, /* iWMMXt wCG register */
6483 OP_RXA
, /* XScale accumulator register */
6485 OP_REGLST
, /* ARM register list */
6486 OP_VRSLST
, /* VFP single-precision register list */
6487 OP_VRDLST
, /* VFP double-precision register list */
6488 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6489 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6490 OP_NSTRLST
, /* Neon element/structure list */
6492 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6493 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6494 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6495 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6496 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6497 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6498 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6499 OP_VMOV
, /* Neon VMOV operands. */
6500 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6501 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6502 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6504 OP_I0
, /* immediate zero */
6505 OP_I7
, /* immediate value 0 .. 7 */
6506 OP_I15
, /* 0 .. 15 */
6507 OP_I16
, /* 1 .. 16 */
6508 OP_I16z
, /* 0 .. 16 */
6509 OP_I31
, /* 0 .. 31 */
6510 OP_I31w
, /* 0 .. 31, optional trailing ! */
6511 OP_I32
, /* 1 .. 32 */
6512 OP_I32z
, /* 0 .. 32 */
6513 OP_I63
, /* 0 .. 63 */
6514 OP_I63s
, /* -64 .. 63 */
6515 OP_I64
, /* 1 .. 64 */
6516 OP_I64z
, /* 0 .. 64 */
6517 OP_I255
, /* 0 .. 255 */
6519 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6520 OP_I7b
, /* 0 .. 7 */
6521 OP_I15b
, /* 0 .. 15 */
6522 OP_I31b
, /* 0 .. 31 */
6524 OP_SH
, /* shifter operand */
6525 OP_SHG
, /* shifter operand with possible group relocation */
6526 OP_ADDR
, /* Memory address expression (any mode) */
6527 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6528 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6529 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6530 OP_EXP
, /* arbitrary expression */
6531 OP_EXPi
, /* same, with optional immediate prefix */
6532 OP_EXPr
, /* same, with optional relocation suffix */
6533 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6535 OP_CPSF
, /* CPS flags */
6536 OP_ENDI
, /* Endianness specifier */
6537 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6538 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6539 OP_COND
, /* conditional code */
6540 OP_TB
, /* Table branch. */
6542 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6544 OP_RRnpc_I0
, /* ARM register or literal 0 */
6545 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6546 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6547 OP_RF_IF
, /* FPA register or immediate */
6548 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6549 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6551 /* Optional operands. */
6552 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6553 OP_oI31b
, /* 0 .. 31 */
6554 OP_oI32b
, /* 1 .. 32 */
6555 OP_oI32z
, /* 0 .. 32 */
6556 OP_oIffffb
, /* 0 .. 65535 */
6557 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6559 OP_oRR
, /* ARM register */
6560 OP_oRRnpc
, /* ARM register, not the PC */
6561 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6562 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6563 OP_oRND
, /* Optional Neon double precision register */
6564 OP_oRNQ
, /* Optional Neon quad precision register */
6565 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6566 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6567 OP_oSHll
, /* LSL immediate */
6568 OP_oSHar
, /* ASR immediate */
6569 OP_oSHllar
, /* LSL or ASR immediate */
6570 OP_oROR
, /* ROR 0/8/16/24 */
6571 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6573 /* Some pre-defined mixed (ARM/THUMB) operands. */
6574 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6575 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6576 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6578 OP_FIRST_OPTIONAL
= OP_oI7b
6581 /* Generic instruction operand parser. This does no encoding and no
6582 semantic validation; it merely squirrels values away in the inst
6583 structure. Returns SUCCESS or FAIL depending on whether the
6584 specified grammar matched. */
6586 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6588 unsigned const int *upat
= pattern
;
6589 char *backtrack_pos
= 0;
6590 const char *backtrack_error
= 0;
6591 int i
, val
= 0, backtrack_index
= 0;
6592 enum arm_reg_type rtype
;
6593 parse_operand_result result
;
6594 unsigned int op_parse_code
;
6596 #define po_char_or_fail(chr) \
6599 if (skip_past_char (&str, chr) == FAIL) \
6604 #define po_reg_or_fail(regtype) \
6607 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6608 & inst.operands[i].vectype); \
6611 first_error (_(reg_expected_msgs[regtype])); \
6614 inst.operands[i].reg = val; \
6615 inst.operands[i].isreg = 1; \
6616 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6617 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6618 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6619 || rtype == REG_TYPE_VFD \
6620 || rtype == REG_TYPE_NQ); \
6624 #define po_reg_or_goto(regtype, label) \
6627 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6628 & inst.operands[i].vectype); \
6632 inst.operands[i].reg = val; \
6633 inst.operands[i].isreg = 1; \
6634 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6635 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6636 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6637 || rtype == REG_TYPE_VFD \
6638 || rtype == REG_TYPE_NQ); \
6642 #define po_imm_or_fail(min, max, popt) \
6645 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6647 inst.operands[i].imm = val; \
6651 #define po_scalar_or_goto(elsz, label) \
6654 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6657 inst.operands[i].reg = val; \
6658 inst.operands[i].isscalar = 1; \
6662 #define po_misc_or_fail(expr) \
6670 #define po_misc_or_fail_no_backtrack(expr) \
6674 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6675 backtrack_pos = 0; \
6676 if (result != PARSE_OPERAND_SUCCESS) \
6681 #define po_barrier_or_imm(str) \
6684 val = parse_barrier (&str); \
6685 if (val == FAIL && ! ISALPHA (*str)) \
6688 /* ISB can only take SY as an option. */ \
6689 || ((inst.instruction & 0xf0) == 0x60 \
6692 inst.error = _("invalid barrier type"); \
6693 backtrack_pos = 0; \
6699 skip_whitespace (str
);
6701 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6703 op_parse_code
= upat
[i
];
6704 if (op_parse_code
>= 1<<16)
6705 op_parse_code
= thumb
? (op_parse_code
>> 16)
6706 : (op_parse_code
& ((1<<16)-1));
6708 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6710 /* Remember where we are in case we need to backtrack. */
6711 gas_assert (!backtrack_pos
);
6712 backtrack_pos
= str
;
6713 backtrack_error
= inst
.error
;
6714 backtrack_index
= i
;
6717 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6718 po_char_or_fail (',');
6720 switch (op_parse_code
)
6728 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6729 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6730 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6731 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6732 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6733 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6735 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6737 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6739 /* Also accept generic coprocessor regs for unknown registers. */
6741 po_reg_or_fail (REG_TYPE_CN
);
6743 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6744 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6745 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6746 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6747 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6748 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6749 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6750 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6751 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6752 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6754 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6756 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6757 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6759 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6761 /* Neon scalar. Using an element size of 8 means that some invalid
6762 scalars are accepted here, so deal with those in later code. */
6763 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6767 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6770 po_imm_or_fail (0, 0, TRUE
);
6775 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6780 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6783 if (parse_ifimm_zero (&str
))
6784 inst
.operands
[i
].imm
= 0;
6788 = _("only floating point zero is allowed as immediate value");
6796 po_scalar_or_goto (8, try_rr
);
6799 po_reg_or_fail (REG_TYPE_RN
);
6805 po_scalar_or_goto (8, try_nsdq
);
6808 po_reg_or_fail (REG_TYPE_NSDQ
);
6814 po_scalar_or_goto (8, try_ndq
);
6817 po_reg_or_fail (REG_TYPE_NDQ
);
6823 po_scalar_or_goto (8, try_vfd
);
6826 po_reg_or_fail (REG_TYPE_VFD
);
6831 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6832 not careful then bad things might happen. */
6833 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6838 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6841 /* There's a possibility of getting a 64-bit immediate here, so
6842 we need special handling. */
6843 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6846 inst
.error
= _("immediate value is out of range");
6854 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6857 po_imm_or_fail (0, 63, TRUE
);
6862 po_char_or_fail ('[');
6863 po_reg_or_fail (REG_TYPE_RN
);
6864 po_char_or_fail (']');
6870 po_reg_or_fail (REG_TYPE_RN
);
6871 if (skip_past_char (&str
, '!') == SUCCESS
)
6872 inst
.operands
[i
].writeback
= 1;
6876 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6877 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6878 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6879 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6880 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6881 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6882 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6883 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6884 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6885 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6886 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6887 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6889 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6891 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6892 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6894 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6895 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6896 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6897 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6899 /* Immediate variants */
6901 po_char_or_fail ('{');
6902 po_imm_or_fail (0, 255, TRUE
);
6903 po_char_or_fail ('}');
6907 /* The expression parser chokes on a trailing !, so we have
6908 to find it first and zap it. */
6911 while (*s
&& *s
!= ',')
6916 inst
.operands
[i
].writeback
= 1;
6918 po_imm_or_fail (0, 31, TRUE
);
6926 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6931 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6938 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6940 val
= parse_reloc (&str
);
6943 inst
.error
= _("unrecognized relocation suffix");
6946 else if (val
!= BFD_RELOC_UNUSED
)
6948 inst
.operands
[i
].imm
= val
;
6949 inst
.operands
[i
].hasreloc
= 1;
6954 /* Operand for MOVW or MOVT. */
6956 po_misc_or_fail (parse_half (&str
));
6959 /* Register or expression. */
6960 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6961 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6963 /* Register or immediate. */
6964 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6965 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6967 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6969 if (!is_immediate_prefix (*str
))
6972 val
= parse_fpa_immediate (&str
);
6975 /* FPA immediates are encoded as registers 8-15.
6976 parse_fpa_immediate has already applied the offset. */
6977 inst
.operands
[i
].reg
= val
;
6978 inst
.operands
[i
].isreg
= 1;
6981 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6982 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6984 /* Two kinds of register. */
6987 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6989 || (rege
->type
!= REG_TYPE_MMXWR
6990 && rege
->type
!= REG_TYPE_MMXWC
6991 && rege
->type
!= REG_TYPE_MMXWCG
))
6993 inst
.error
= _("iWMMXt data or control register expected");
6996 inst
.operands
[i
].reg
= rege
->number
;
6997 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7003 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7005 || (rege
->type
!= REG_TYPE_MMXWC
7006 && rege
->type
!= REG_TYPE_MMXWCG
))
7008 inst
.error
= _("iWMMXt control register expected");
7011 inst
.operands
[i
].reg
= rege
->number
;
7012 inst
.operands
[i
].isreg
= 1;
7017 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7018 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7019 case OP_oROR
: val
= parse_ror (&str
); break;
7020 case OP_COND
: val
= parse_cond (&str
); break;
7021 case OP_oBARRIER_I15
:
7022 po_barrier_or_imm (str
); break;
7024 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7030 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7031 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7033 inst
.error
= _("Banked registers are not available with this "
7039 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7043 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7046 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7048 if (strncasecmp (str
, "APSR_", 5) == 0)
7055 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7056 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7057 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7058 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7059 default: found
= 16;
7063 inst
.operands
[i
].isvec
= 1;
7064 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7065 inst
.operands
[i
].reg
= REG_PC
;
7072 po_misc_or_fail (parse_tb (&str
));
7075 /* Register lists. */
7077 val
= parse_reg_list (&str
);
7080 inst
.operands
[i
].writeback
= 1;
7086 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7090 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7094 /* Allow Q registers too. */
7095 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7102 inst
.operands
[i
].issingle
= 1;
7107 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7112 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7113 &inst
.operands
[i
].vectype
);
7116 /* Addressing modes */
7118 po_misc_or_fail (parse_address (&str
, i
));
7122 po_misc_or_fail_no_backtrack (
7123 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7127 po_misc_or_fail_no_backtrack (
7128 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7132 po_misc_or_fail_no_backtrack (
7133 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7137 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7141 po_misc_or_fail_no_backtrack (
7142 parse_shifter_operand_group_reloc (&str
, i
));
7146 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7150 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7154 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7158 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7161 /* Various value-based sanity checks and shared operations. We
7162 do not signal immediate failures for the register constraints;
7163 this allows a syntax error to take precedence. */
7164 switch (op_parse_code
)
7172 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7173 inst
.error
= BAD_PC
;
7178 if (inst
.operands
[i
].isreg
)
7180 if (inst
.operands
[i
].reg
== REG_PC
)
7181 inst
.error
= BAD_PC
;
7182 else if (inst
.operands
[i
].reg
== REG_SP
)
7183 inst
.error
= BAD_SP
;
7188 if (inst
.operands
[i
].isreg
7189 && inst
.operands
[i
].reg
== REG_PC
7190 && (inst
.operands
[i
].writeback
|| thumb
))
7191 inst
.error
= BAD_PC
;
7200 case OP_oBARRIER_I15
:
7209 inst
.operands
[i
].imm
= val
;
7216 /* If we get here, this operand was successfully parsed. */
7217 inst
.operands
[i
].present
= 1;
7221 inst
.error
= BAD_ARGS
;
7226 /* The parse routine should already have set inst.error, but set a
7227 default here just in case. */
7229 inst
.error
= _("syntax error");
7233 /* Do not backtrack over a trailing optional argument that
7234 absorbed some text. We will only fail again, with the
7235 'garbage following instruction' error message, which is
7236 probably less helpful than the current one. */
7237 if (backtrack_index
== i
&& backtrack_pos
!= str
7238 && upat
[i
+1] == OP_stop
)
7241 inst
.error
= _("syntax error");
7245 /* Try again, skipping the optional argument at backtrack_pos. */
7246 str
= backtrack_pos
;
7247 inst
.error
= backtrack_error
;
7248 inst
.operands
[backtrack_index
].present
= 0;
7249 i
= backtrack_index
;
7253 /* Check that we have parsed all the arguments. */
7254 if (*str
!= '\0' && !inst
.error
)
7255 inst
.error
= _("garbage following instruction");
7257 return inst
.error
? FAIL
: SUCCESS
;
7260 #undef po_char_or_fail
7261 #undef po_reg_or_fail
7262 #undef po_reg_or_goto
7263 #undef po_imm_or_fail
7264 #undef po_scalar_or_fail
7265 #undef po_barrier_or_imm
7267 /* Shorthand macro for instruction encoding functions issuing errors. */
7268 #define constraint(expr, err) \
7279 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7280 instructions are unpredictable if these registers are used. This
7281 is the BadReg predicate in ARM's Thumb-2 documentation. */
7282 #define reject_bad_reg(reg) \
7284 if (reg == REG_SP || reg == REG_PC) \
7286 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7291 /* If REG is R13 (the stack pointer), warn that its use is
7293 #define warn_deprecated_sp(reg) \
7295 if (warn_on_deprecated && reg == REG_SP) \
7296 as_tsktsk (_("use of r13 is deprecated")); \
7299 /* Functions for operand encoding. ARM, then Thumb. */
7301 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7303 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7305 The only binary encoding difference is the Coprocessor number. Coprocessor
7306 9 is used for half-precision calculations or conversions. The format of the
7307 instruction is the same as the equivalent Coprocessor 10 instuction that
7308 exists for Single-Precision operation. */
7311 do_scalar_fp16_v82_encode (void)
7313 if (inst
.cond
!= COND_ALWAYS
)
7314 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7315 " the behaviour is UNPREDICTABLE"));
7316 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7319 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7320 mark_feature_used (&arm_ext_fp16
);
7323 /* If VAL can be encoded in the immediate field of an ARM instruction,
7324 return the encoded form. Otherwise, return FAIL. */
7327 encode_arm_immediate (unsigned int val
)
7334 for (i
= 2; i
< 32; i
+= 2)
7335 if ((a
= rotate_left (val
, i
)) <= 0xff)
7336 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7341 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7342 return the encoded form. Otherwise, return FAIL. */
7344 encode_thumb32_immediate (unsigned int val
)
7351 for (i
= 1; i
<= 24; i
++)
7354 if ((val
& ~(0xff << i
)) == 0)
7355 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7359 if (val
== ((a
<< 16) | a
))
7361 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7365 if (val
== ((a
<< 16) | a
))
7366 return 0x200 | (a
>> 8);
7370 /* Encode a VFP SP or DP register number into inst.instruction. */
7373 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7375 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7378 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7381 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7384 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7389 first_error (_("D register out of range for selected VFP version"));
7397 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7401 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7405 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7409 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7413 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7417 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7425 /* Encode a <shift> in an ARM-format instruction. The immediate,
7426 if any, is handled by md_apply_fix. */
7428 encode_arm_shift (int i
)
7430 /* register-shifted register. */
7431 if (inst
.operands
[i
].immisreg
)
7434 for (index
= 0; index
<= i
; ++index
)
7436 gas_assert (inst
.operands
[index
].present
);
7437 if (inst
.operands
[index
].isreg
&& inst
.operands
[index
].reg
== REG_PC
)
7438 as_warn (UNPRED_REG ("r15"));
7441 if (inst
.operands
[i
].imm
== REG_PC
)
7442 as_warn (UNPRED_REG ("r15"));
7445 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7446 inst
.instruction
|= SHIFT_ROR
<< 5;
7449 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7450 if (inst
.operands
[i
].immisreg
)
7452 inst
.instruction
|= SHIFT_BY_REG
;
7453 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7456 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7461 encode_arm_shifter_operand (int i
)
7463 if (inst
.operands
[i
].isreg
)
7465 inst
.instruction
|= inst
.operands
[i
].reg
;
7466 encode_arm_shift (i
);
7470 inst
.instruction
|= INST_IMMEDIATE
;
7471 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7472 inst
.instruction
|= inst
.operands
[i
].imm
;
7476 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7478 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7481 Generate an error if the operand is not a register. */
7482 constraint (!inst
.operands
[i
].isreg
,
7483 _("Instruction does not support =N addresses"));
7485 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7487 if (inst
.operands
[i
].preind
)
7491 inst
.error
= _("instruction does not accept preindexed addressing");
7494 inst
.instruction
|= PRE_INDEX
;
7495 if (inst
.operands
[i
].writeback
)
7496 inst
.instruction
|= WRITE_BACK
;
7499 else if (inst
.operands
[i
].postind
)
7501 gas_assert (inst
.operands
[i
].writeback
);
7503 inst
.instruction
|= WRITE_BACK
;
7505 else /* unindexed - only for coprocessor */
7507 inst
.error
= _("instruction does not accept unindexed addressing");
7511 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7512 && (((inst
.instruction
& 0x000f0000) >> 16)
7513 == ((inst
.instruction
& 0x0000f000) >> 12)))
7514 as_warn ((inst
.instruction
& LOAD_BIT
)
7515 ? _("destination register same as write-back base")
7516 : _("source register same as write-back base"));
7519 /* inst.operands[i] was set up by parse_address. Encode it into an
7520 ARM-format mode 2 load or store instruction. If is_t is true,
7521 reject forms that cannot be used with a T instruction (i.e. not
7524 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7526 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7528 encode_arm_addr_mode_common (i
, is_t
);
7530 if (inst
.operands
[i
].immisreg
)
7532 constraint ((inst
.operands
[i
].imm
== REG_PC
7533 || (is_pc
&& inst
.operands
[i
].writeback
)),
7535 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7536 inst
.instruction
|= inst
.operands
[i
].imm
;
7537 if (!inst
.operands
[i
].negative
)
7538 inst
.instruction
|= INDEX_UP
;
7539 if (inst
.operands
[i
].shifted
)
7541 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7542 inst
.instruction
|= SHIFT_ROR
<< 5;
7545 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7546 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7550 else /* immediate offset in inst.reloc */
7552 if (is_pc
&& !inst
.reloc
.pc_rel
)
7554 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7556 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7557 cannot use PC in addressing.
7558 PC cannot be used in writeback addressing, either. */
7559 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7562 /* Use of PC in str is deprecated for ARMv7. */
7563 if (warn_on_deprecated
7565 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7566 as_tsktsk (_("use of PC in this instruction is deprecated"));
7569 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7571 /* Prefer + for zero encoded value. */
7572 if (!inst
.operands
[i
].negative
)
7573 inst
.instruction
|= INDEX_UP
;
7574 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7579 /* inst.operands[i] was set up by parse_address. Encode it into an
7580 ARM-format mode 3 load or store instruction. Reject forms that
7581 cannot be used with such instructions. If is_t is true, reject
7582 forms that cannot be used with a T instruction (i.e. not
7585 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7587 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7589 inst
.error
= _("instruction does not accept scaled register index");
7593 encode_arm_addr_mode_common (i
, is_t
);
7595 if (inst
.operands
[i
].immisreg
)
7597 constraint ((inst
.operands
[i
].imm
== REG_PC
7598 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7600 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7602 inst
.instruction
|= inst
.operands
[i
].imm
;
7603 if (!inst
.operands
[i
].negative
)
7604 inst
.instruction
|= INDEX_UP
;
7606 else /* immediate offset in inst.reloc */
7608 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7609 && inst
.operands
[i
].writeback
),
7611 inst
.instruction
|= HWOFFSET_IMM
;
7612 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7614 /* Prefer + for zero encoded value. */
7615 if (!inst
.operands
[i
].negative
)
7616 inst
.instruction
|= INDEX_UP
;
7618 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7623 /* Write immediate bits [7:0] to the following locations:
7625 |28/24|23 19|18 16|15 4|3 0|
7626 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7628 This function is used by VMOV/VMVN/VORR/VBIC. */
7631 neon_write_immbits (unsigned immbits
)
7633 inst
.instruction
|= immbits
& 0xf;
7634 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7635 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7638 /* Invert low-order SIZE bits of XHI:XLO. */
7641 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7643 unsigned immlo
= xlo
? *xlo
: 0;
7644 unsigned immhi
= xhi
? *xhi
: 0;
7649 immlo
= (~immlo
) & 0xff;
7653 immlo
= (~immlo
) & 0xffff;
7657 immhi
= (~immhi
) & 0xffffffff;
7661 immlo
= (~immlo
) & 0xffffffff;
7675 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7679 neon_bits_same_in_bytes (unsigned imm
)
7681 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7682 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7683 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7684 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7687 /* For immediate of above form, return 0bABCD. */
7690 neon_squash_bits (unsigned imm
)
7692 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7693 | ((imm
& 0x01000000) >> 21);
7696 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7699 neon_qfloat_bits (unsigned imm
)
7701 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7704 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7705 the instruction. *OP is passed as the initial value of the op field, and
7706 may be set to a different value depending on the constant (i.e.
7707 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7708 MVN). If the immediate looks like a repeated pattern then also
7709 try smaller element sizes. */
7712 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7713 unsigned *immbits
, int *op
, int size
,
7714 enum neon_el_type type
)
7716 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7718 if (type
== NT_float
&& !float_p
)
7721 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7723 if (size
!= 32 || *op
== 1)
7725 *immbits
= neon_qfloat_bits (immlo
);
7731 if (neon_bits_same_in_bytes (immhi
)
7732 && neon_bits_same_in_bytes (immlo
))
7736 *immbits
= (neon_squash_bits (immhi
) << 4)
7737 | neon_squash_bits (immlo
);
7748 if (immlo
== (immlo
& 0x000000ff))
7753 else if (immlo
== (immlo
& 0x0000ff00))
7755 *immbits
= immlo
>> 8;
7758 else if (immlo
== (immlo
& 0x00ff0000))
7760 *immbits
= immlo
>> 16;
7763 else if (immlo
== (immlo
& 0xff000000))
7765 *immbits
= immlo
>> 24;
7768 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7770 *immbits
= (immlo
>> 8) & 0xff;
7773 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7775 *immbits
= (immlo
>> 16) & 0xff;
7779 if ((immlo
& 0xffff) != (immlo
>> 16))
7786 if (immlo
== (immlo
& 0x000000ff))
7791 else if (immlo
== (immlo
& 0x0000ff00))
7793 *immbits
= immlo
>> 8;
7797 if ((immlo
& 0xff) != (immlo
>> 8))
7802 if (immlo
== (immlo
& 0x000000ff))
7804 /* Don't allow MVN with 8-bit immediate. */
7814 #if defined BFD_HOST_64_BIT
7815 /* Returns TRUE if double precision value V may be cast
7816 to single precision without loss of accuracy. */
7819 is_double_a_single (bfd_int64_t v
)
7821 int exp
= (int)((v
>> 52) & 0x7FF);
7822 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7824 return (exp
== 0 || exp
== 0x7FF
7825 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7826 && (mantissa
& 0x1FFFFFFFl
) == 0;
7829 /* Returns a double precision value casted to single precision
7830 (ignoring the least significant bits in exponent and mantissa). */
7833 double_to_single (bfd_int64_t v
)
7835 int sign
= (int) ((v
>> 63) & 1l);
7836 int exp
= (int) ((v
>> 52) & 0x7FF);
7837 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7843 exp
= exp
- 1023 + 127;
7852 /* No denormalized numbers. */
7858 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7860 #endif /* BFD_HOST_64_BIT */
7869 static void do_vfp_nsyn_opcode (const char *);
7871 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7872 Determine whether it can be performed with a move instruction; if
7873 it can, convert inst.instruction to that move instruction and
7874 return TRUE; if it can't, convert inst.instruction to a literal-pool
7875 load and return FALSE. If this is not a valid thing to do in the
7876 current context, set inst.error and return TRUE.
7878 inst.operands[i] describes the destination register. */
7881 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7884 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7885 bfd_boolean arm_p
= (t
== CONST_ARM
);
7888 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7892 if ((inst
.instruction
& tbit
) == 0)
7894 inst
.error
= _("invalid pseudo operation");
7898 if (inst
.reloc
.exp
.X_op
!= O_constant
7899 && inst
.reloc
.exp
.X_op
!= O_symbol
7900 && inst
.reloc
.exp
.X_op
!= O_big
)
7902 inst
.error
= _("constant expression expected");
7906 if (inst
.reloc
.exp
.X_op
== O_constant
7907 || inst
.reloc
.exp
.X_op
== O_big
)
7909 #if defined BFD_HOST_64_BIT
7914 if (inst
.reloc
.exp
.X_op
== O_big
)
7916 LITTLENUM_TYPE w
[X_PRECISION
];
7919 if (inst
.reloc
.exp
.X_add_number
== -1)
7921 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7923 /* FIXME: Should we check words w[2..5] ? */
7928 #if defined BFD_HOST_64_BIT
7930 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7931 << LITTLENUM_NUMBER_OF_BITS
)
7932 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7933 << LITTLENUM_NUMBER_OF_BITS
)
7934 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7935 << LITTLENUM_NUMBER_OF_BITS
)
7936 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7938 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7939 | (l
[0] & LITTLENUM_MASK
);
7943 v
= inst
.reloc
.exp
.X_add_number
;
7945 if (!inst
.operands
[i
].issingle
)
7949 /* This can be encoded only for a low register. */
7950 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7952 /* This can be done with a mov(1) instruction. */
7953 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7954 inst
.instruction
|= v
;
7958 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7959 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7961 /* Check if on thumb2 it can be done with a mov.w, mvn or
7962 movw instruction. */
7963 unsigned int newimm
;
7964 bfd_boolean isNegated
;
7966 newimm
= encode_thumb32_immediate (v
);
7967 if (newimm
!= (unsigned int) FAIL
)
7971 newimm
= encode_thumb32_immediate (~v
);
7972 if (newimm
!= (unsigned int) FAIL
)
7976 /* The number can be loaded with a mov.w or mvn
7978 if (newimm
!= (unsigned int) FAIL
7979 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7981 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7982 | (inst
.operands
[i
].reg
<< 8));
7983 /* Change to MOVN. */
7984 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7985 inst
.instruction
|= (newimm
& 0x800) << 15;
7986 inst
.instruction
|= (newimm
& 0x700) << 4;
7987 inst
.instruction
|= (newimm
& 0x0ff);
7990 /* The number can be loaded with a movw instruction. */
7991 else if ((v
& ~0xFFFF) == 0
7992 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7994 int imm
= v
& 0xFFFF;
7996 inst
.instruction
= 0xf2400000; /* MOVW. */
7997 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7998 inst
.instruction
|= (imm
& 0xf000) << 4;
7999 inst
.instruction
|= (imm
& 0x0800) << 15;
8000 inst
.instruction
|= (imm
& 0x0700) << 4;
8001 inst
.instruction
|= (imm
& 0x00ff);
8008 int value
= encode_arm_immediate (v
);
8012 /* This can be done with a mov instruction. */
8013 inst
.instruction
&= LITERAL_MASK
;
8014 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8015 inst
.instruction
|= value
& 0xfff;
8019 value
= encode_arm_immediate (~ v
);
8022 /* This can be done with a mvn instruction. */
8023 inst
.instruction
&= LITERAL_MASK
;
8024 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8025 inst
.instruction
|= value
& 0xfff;
8029 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8032 unsigned immbits
= 0;
8033 unsigned immlo
= inst
.operands
[1].imm
;
8034 unsigned immhi
= inst
.operands
[1].regisimm
8035 ? inst
.operands
[1].reg
8036 : inst
.reloc
.exp
.X_unsigned
8038 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8039 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8040 &op
, 64, NT_invtype
);
8044 neon_invert_size (&immlo
, &immhi
, 64);
8046 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8047 &op
, 64, NT_invtype
);
8052 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8058 /* Fill other bits in vmov encoding for both thumb and arm. */
8060 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8062 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8063 neon_write_immbits (immbits
);
8071 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8072 if (inst
.operands
[i
].issingle
8073 && is_quarter_float (inst
.operands
[1].imm
)
8074 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8076 inst
.operands
[1].imm
=
8077 neon_qfloat_bits (v
);
8078 do_vfp_nsyn_opcode ("fconsts");
8082 /* If our host does not support a 64-bit type then we cannot perform
8083 the following optimization. This mean that there will be a
8084 discrepancy between the output produced by an assembler built for
8085 a 32-bit-only host and the output produced from a 64-bit host, but
8086 this cannot be helped. */
8087 #if defined BFD_HOST_64_BIT
8088 else if (!inst
.operands
[1].issingle
8089 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8091 if (is_double_a_single (v
)
8092 && is_quarter_float (double_to_single (v
)))
8094 inst
.operands
[1].imm
=
8095 neon_qfloat_bits (double_to_single (v
));
8096 do_vfp_nsyn_opcode ("fconstd");
8104 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8105 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8108 inst
.operands
[1].reg
= REG_PC
;
8109 inst
.operands
[1].isreg
= 1;
8110 inst
.operands
[1].preind
= 1;
8111 inst
.reloc
.pc_rel
= 1;
8112 inst
.reloc
.type
= (thumb_p
8113 ? BFD_RELOC_ARM_THUMB_OFFSET
8115 ? BFD_RELOC_ARM_HWLITERAL
8116 : BFD_RELOC_ARM_LITERAL
));
8120 /* inst.operands[i] was set up by parse_address. Encode it into an
8121 ARM-format instruction. Reject all forms which cannot be encoded
8122 into a coprocessor load/store instruction. If wb_ok is false,
8123 reject use of writeback; if unind_ok is false, reject use of
8124 unindexed addressing. If reloc_override is not 0, use it instead
8125 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8126 (in which case it is preserved). */
8129 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8131 if (!inst
.operands
[i
].isreg
)
8134 if (! inst
.operands
[0].isvec
)
8136 inst
.error
= _("invalid co-processor operand");
8139 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8143 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8145 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8147 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8149 gas_assert (!inst
.operands
[i
].writeback
);
8152 inst
.error
= _("instruction does not support unindexed addressing");
8155 inst
.instruction
|= inst
.operands
[i
].imm
;
8156 inst
.instruction
|= INDEX_UP
;
8160 if (inst
.operands
[i
].preind
)
8161 inst
.instruction
|= PRE_INDEX
;
8163 if (inst
.operands
[i
].writeback
)
8165 if (inst
.operands
[i
].reg
== REG_PC
)
8167 inst
.error
= _("pc may not be used with write-back");
8172 inst
.error
= _("instruction does not support writeback");
8175 inst
.instruction
|= WRITE_BACK
;
8179 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8180 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8181 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8182 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8185 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8187 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8190 /* Prefer + for zero encoded value. */
8191 if (!inst
.operands
[i
].negative
)
8192 inst
.instruction
|= INDEX_UP
;
8197 /* Functions for instruction encoding, sorted by sub-architecture.
8198 First some generics; their names are taken from the conventional
8199 bit positions for register arguments in ARM format instructions. */
8209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8215 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8222 inst
.instruction
|= inst
.operands
[1].reg
;
8228 inst
.instruction
|= inst
.operands
[0].reg
;
8229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8242 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8243 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8250 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8254 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8256 if (ARM_CPU_IS_ANY (cpu_variant
))
8258 as_tsktsk ("%s", msg
);
8261 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8273 unsigned Rn
= inst
.operands
[2].reg
;
8274 /* Enforce restrictions on SWP instruction. */
8275 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8277 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8278 _("Rn must not overlap other operands"));
8280 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8282 if (!check_obsolete (&arm_ext_v8
,
8283 _("swp{b} use is obsoleted for ARMv8 and later"))
8284 && warn_on_deprecated
8285 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8286 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8290 inst
.instruction
|= inst
.operands
[1].reg
;
8291 inst
.instruction
|= Rn
<< 16;
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8299 inst
.instruction
|= inst
.operands
[2].reg
;
8305 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8306 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8307 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8308 || inst
.reloc
.exp
.X_add_number
!= 0),
8310 inst
.instruction
|= inst
.operands
[0].reg
;
8311 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8312 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8318 inst
.instruction
|= inst
.operands
[0].imm
;
8324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8325 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8328 /* ARM instructions, in alphabetical order by function name (except
8329 that wrapper functions appear immediately after the function they
8332 /* This is a pseudo-op of the form "adr rd, label" to be converted
8333 into a relative address of the form "add rd, pc, #label-.-8". */
8338 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8340 /* Frag hacking will turn this into a sub instruction if the offset turns
8341 out to be negative. */
8342 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8343 inst
.reloc
.pc_rel
= 1;
8344 inst
.reloc
.exp
.X_add_number
-= 8;
8347 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8348 into a relative address of the form:
8349 add rd, pc, #low(label-.-8)"
8350 add rd, rd, #high(label-.-8)" */
8355 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8357 /* Frag hacking will turn this into a sub instruction if the offset turns
8358 out to be negative. */
8359 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8360 inst
.reloc
.pc_rel
= 1;
8361 inst
.size
= INSN_SIZE
* 2;
8362 inst
.reloc
.exp
.X_add_number
-= 8;
8368 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8369 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8371 if (!inst
.operands
[1].present
)
8372 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8374 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8375 encode_arm_shifter_operand (2);
8381 if (inst
.operands
[0].present
)
8382 inst
.instruction
|= inst
.operands
[0].imm
;
8384 inst
.instruction
|= 0xf;
8390 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8391 constraint (msb
> 32, _("bit-field extends past end of register"));
8392 /* The instruction encoding stores the LSB and MSB,
8393 not the LSB and width. */
8394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8395 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8396 inst
.instruction
|= (msb
- 1) << 16;
8404 /* #0 in second position is alternative syntax for bfc, which is
8405 the same instruction but with REG_PC in the Rm field. */
8406 if (!inst
.operands
[1].isreg
)
8407 inst
.operands
[1].reg
= REG_PC
;
8409 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8410 constraint (msb
> 32, _("bit-field extends past end of register"));
8411 /* The instruction encoding stores the LSB and MSB,
8412 not the LSB and width. */
8413 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8414 inst
.instruction
|= inst
.operands
[1].reg
;
8415 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8416 inst
.instruction
|= (msb
- 1) << 16;
8422 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8423 _("bit-field extends past end of register"));
8424 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8425 inst
.instruction
|= inst
.operands
[1].reg
;
8426 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8427 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8430 /* ARM V5 breakpoint instruction (argument parse)
8431 BKPT <16 bit unsigned immediate>
8432 Instruction is not conditional.
8433 The bit pattern given in insns[] has the COND_ALWAYS condition,
8434 and it is an error if the caller tried to override that. */
8439 /* Top 12 of 16 bits to bits 19:8. */
8440 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8442 /* Bottom 4 of 16 bits to bits 3:0. */
8443 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8447 encode_branch (int default_reloc
)
8449 if (inst
.operands
[0].hasreloc
)
8451 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8452 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8453 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8454 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8455 ? BFD_RELOC_ARM_PLT32
8456 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8459 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8460 inst
.reloc
.pc_rel
= 1;
8467 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8468 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8471 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8478 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8480 if (inst
.cond
== COND_ALWAYS
)
8481 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8483 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8487 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8490 /* ARM V5 branch-link-exchange instruction (argument parse)
8491 BLX <target_addr> ie BLX(1)
8492 BLX{<condition>} <Rm> ie BLX(2)
8493 Unfortunately, there are two different opcodes for this mnemonic.
8494 So, the insns[].value is not used, and the code here zaps values
8495 into inst.instruction.
8496 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8501 if (inst
.operands
[0].isreg
)
8503 /* Arg is a register; the opcode provided by insns[] is correct.
8504 It is not illegal to do "blx pc", just useless. */
8505 if (inst
.operands
[0].reg
== REG_PC
)
8506 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8508 inst
.instruction
|= inst
.operands
[0].reg
;
8512 /* Arg is an address; this instruction cannot be executed
8513 conditionally, and the opcode must be adjusted.
8514 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8515 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8516 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8517 inst
.instruction
= 0xfa000000;
8518 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8525 bfd_boolean want_reloc
;
8527 if (inst
.operands
[0].reg
== REG_PC
)
8528 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8530 inst
.instruction
|= inst
.operands
[0].reg
;
8531 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8532 it is for ARMv4t or earlier. */
8533 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8534 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8538 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8543 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8547 /* ARM v5TEJ. Jump to Jazelle code. */
8552 if (inst
.operands
[0].reg
== REG_PC
)
8553 as_tsktsk (_("use of r15 in bxj is not really useful"));
8555 inst
.instruction
|= inst
.operands
[0].reg
;
8558 /* Co-processor data operation:
8559 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8560 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8564 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8565 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8566 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8567 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8568 inst
.instruction
|= inst
.operands
[4].reg
;
8569 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8575 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8576 encode_arm_shifter_operand (1);
8579 /* Transfer between coprocessor and ARM registers.
8580 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8585 No special properties. */
8587 struct deprecated_coproc_regs_s
8594 arm_feature_set deprecated
;
8595 arm_feature_set obsoleted
;
8596 const char *dep_msg
;
8597 const char *obs_msg
;
8600 #define DEPR_ACCESS_V8 \
8601 N_("This coprocessor register access is deprecated in ARMv8")
8603 /* Table of all deprecated coprocessor registers. */
8604 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8606 {15, 0, 7, 10, 5, /* CP15DMB. */
8607 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8608 DEPR_ACCESS_V8
, NULL
},
8609 {15, 0, 7, 10, 4, /* CP15DSB. */
8610 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8611 DEPR_ACCESS_V8
, NULL
},
8612 {15, 0, 7, 5, 4, /* CP15ISB. */
8613 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8614 DEPR_ACCESS_V8
, NULL
},
8615 {14, 6, 1, 0, 0, /* TEEHBR. */
8616 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8617 DEPR_ACCESS_V8
, NULL
},
8618 {14, 6, 0, 0, 0, /* TEECR. */
8619 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8620 DEPR_ACCESS_V8
, NULL
},
8623 #undef DEPR_ACCESS_V8
8625 static const size_t deprecated_coproc_reg_count
=
8626 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8634 Rd
= inst
.operands
[2].reg
;
8637 if (inst
.instruction
== 0xee000010
8638 || inst
.instruction
== 0xfe000010)
8640 reject_bad_reg (Rd
);
8643 constraint (Rd
== REG_SP
, BAD_SP
);
8648 if (inst
.instruction
== 0xe000010)
8649 constraint (Rd
== REG_PC
, BAD_PC
);
8652 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8654 const struct deprecated_coproc_regs_s
*r
=
8655 deprecated_coproc_regs
+ i
;
8657 if (inst
.operands
[0].reg
== r
->cp
8658 && inst
.operands
[1].imm
== r
->opc1
8659 && inst
.operands
[3].reg
== r
->crn
8660 && inst
.operands
[4].reg
== r
->crm
8661 && inst
.operands
[5].imm
== r
->opc2
)
8663 if (! ARM_CPU_IS_ANY (cpu_variant
)
8664 && warn_on_deprecated
8665 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8666 as_tsktsk ("%s", r
->dep_msg
);
8670 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8671 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8672 inst
.instruction
|= Rd
<< 12;
8673 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8674 inst
.instruction
|= inst
.operands
[4].reg
;
8675 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8678 /* Transfer between coprocessor register and pair of ARM registers.
8679 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8684 Two XScale instructions are special cases of these:
8686 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8687 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8689 Result unpredictable if Rd or Rn is R15. */
8696 Rd
= inst
.operands
[2].reg
;
8697 Rn
= inst
.operands
[3].reg
;
8701 reject_bad_reg (Rd
);
8702 reject_bad_reg (Rn
);
8706 constraint (Rd
== REG_PC
, BAD_PC
);
8707 constraint (Rn
== REG_PC
, BAD_PC
);
8710 /* Only check the MRRC{2} variants. */
8711 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8713 /* If Rd == Rn, error that the operation is
8714 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8715 constraint (Rd
== Rn
, BAD_OVERLAP
);
8718 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8719 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8720 inst
.instruction
|= Rd
<< 12;
8721 inst
.instruction
|= Rn
<< 16;
8722 inst
.instruction
|= inst
.operands
[4].reg
;
8728 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8729 if (inst
.operands
[1].present
)
8731 inst
.instruction
|= CPSI_MMOD
;
8732 inst
.instruction
|= inst
.operands
[1].imm
;
8739 inst
.instruction
|= inst
.operands
[0].imm
;
8745 unsigned Rd
, Rn
, Rm
;
8747 Rd
= inst
.operands
[0].reg
;
8748 Rn
= (inst
.operands
[1].present
8749 ? inst
.operands
[1].reg
: Rd
);
8750 Rm
= inst
.operands
[2].reg
;
8752 constraint ((Rd
== REG_PC
), BAD_PC
);
8753 constraint ((Rn
== REG_PC
), BAD_PC
);
8754 constraint ((Rm
== REG_PC
), BAD_PC
);
8756 inst
.instruction
|= Rd
<< 16;
8757 inst
.instruction
|= Rn
<< 0;
8758 inst
.instruction
|= Rm
<< 8;
8764 /* There is no IT instruction in ARM mode. We
8765 process it to do the validation as if in
8766 thumb mode, just in case the code gets
8767 assembled for thumb using the unified syntax. */
8772 set_it_insn_type (IT_INSN
);
8773 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8774 now_it
.cc
= inst
.operands
[0].imm
;
8778 /* If there is only one register in the register list,
8779 then return its register number. Otherwise return -1. */
8781 only_one_reg_in_list (int range
)
8783 int i
= ffs (range
) - 1;
8784 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8788 encode_ldmstm(int from_push_pop_mnem
)
8790 int base_reg
= inst
.operands
[0].reg
;
8791 int range
= inst
.operands
[1].imm
;
8794 inst
.instruction
|= base_reg
<< 16;
8795 inst
.instruction
|= range
;
8797 if (inst
.operands
[1].writeback
)
8798 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8800 if (inst
.operands
[0].writeback
)
8802 inst
.instruction
|= WRITE_BACK
;
8803 /* Check for unpredictable uses of writeback. */
8804 if (inst
.instruction
& LOAD_BIT
)
8806 /* Not allowed in LDM type 2. */
8807 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8808 && ((range
& (1 << REG_PC
)) == 0))
8809 as_warn (_("writeback of base register is UNPREDICTABLE"));
8810 /* Only allowed if base reg not in list for other types. */
8811 else if (range
& (1 << base_reg
))
8812 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8816 /* Not allowed for type 2. */
8817 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8818 as_warn (_("writeback of base register is UNPREDICTABLE"));
8819 /* Only allowed if base reg not in list, or first in list. */
8820 else if ((range
& (1 << base_reg
))
8821 && (range
& ((1 << base_reg
) - 1)))
8822 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8826 /* If PUSH/POP has only one register, then use the A2 encoding. */
8827 one_reg
= only_one_reg_in_list (range
);
8828 if (from_push_pop_mnem
&& one_reg
>= 0)
8830 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8832 inst
.instruction
&= A_COND_MASK
;
8833 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8834 inst
.instruction
|= one_reg
<< 12;
8841 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8844 /* ARMv5TE load-consecutive (argument parse)
8853 constraint (inst
.operands
[0].reg
% 2 != 0,
8854 _("first transfer register must be even"));
8855 constraint (inst
.operands
[1].present
8856 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8857 _("can only transfer two consecutive registers"));
8858 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8859 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8861 if (!inst
.operands
[1].present
)
8862 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8864 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8865 register and the first register written; we have to diagnose
8866 overlap between the base and the second register written here. */
8868 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8869 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8870 as_warn (_("base register written back, and overlaps "
8871 "second transfer register"));
8873 if (!(inst
.instruction
& V4_STR_BIT
))
8875 /* For an index-register load, the index register must not overlap the
8876 destination (even if not write-back). */
8877 if (inst
.operands
[2].immisreg
8878 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8879 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8880 as_warn (_("index register overlaps transfer register"));
8882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8883 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8889 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8890 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8891 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8892 || inst
.operands
[1].negative
8893 /* This can arise if the programmer has written
8895 or if they have mistakenly used a register name as the last
8898 It is very difficult to distinguish between these two cases
8899 because "rX" might actually be a label. ie the register
8900 name has been occluded by a symbol of the same name. So we
8901 just generate a general 'bad addressing mode' type error
8902 message and leave it up to the programmer to discover the
8903 true cause and fix their mistake. */
8904 || (inst
.operands
[1].reg
== REG_PC
),
8907 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8908 || inst
.reloc
.exp
.X_add_number
!= 0,
8909 _("offset must be zero in ARM encoding"));
8911 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8914 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8915 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8921 constraint (inst
.operands
[0].reg
% 2 != 0,
8922 _("even register required"));
8923 constraint (inst
.operands
[1].present
8924 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8925 _("can only load two consecutive registers"));
8926 /* If op 1 were present and equal to PC, this function wouldn't
8927 have been called in the first place. */
8928 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8931 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8934 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8935 which is not a multiple of four is UNPREDICTABLE. */
8937 check_ldr_r15_aligned (void)
8939 constraint (!(inst
.operands
[1].immisreg
)
8940 && (inst
.operands
[0].reg
== REG_PC
8941 && inst
.operands
[1].reg
== REG_PC
8942 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8943 _("ldr to register 15 must be 4-byte alligned"));
8949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8950 if (!inst
.operands
[1].isreg
)
8951 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8953 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8954 check_ldr_r15_aligned ();
8960 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8962 if (inst
.operands
[1].preind
)
8964 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8965 || inst
.reloc
.exp
.X_add_number
!= 0,
8966 _("this instruction requires a post-indexed address"));
8968 inst
.operands
[1].preind
= 0;
8969 inst
.operands
[1].postind
= 1;
8970 inst
.operands
[1].writeback
= 1;
8972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8973 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8976 /* Halfword and signed-byte load/store operations. */
8981 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8983 if (!inst
.operands
[1].isreg
)
8984 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8986 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8992 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8994 if (inst
.operands
[1].preind
)
8996 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8997 || inst
.reloc
.exp
.X_add_number
!= 0,
8998 _("this instruction requires a post-indexed address"));
9000 inst
.operands
[1].preind
= 0;
9001 inst
.operands
[1].postind
= 1;
9002 inst
.operands
[1].writeback
= 1;
9004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9005 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9008 /* Co-processor register load/store.
9009 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9013 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9014 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9015 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9021 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9022 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9023 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9024 && !(inst
.instruction
& 0x00400000))
9025 as_tsktsk (_("Rd and Rm should be different in mla"));
9027 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9028 inst
.instruction
|= inst
.operands
[1].reg
;
9029 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9030 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9036 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9037 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9040 encode_arm_shifter_operand (1);
9043 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9050 top
= (inst
.instruction
& 0x00400000) != 0;
9051 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9052 _(":lower16: not allowed this instruction"));
9053 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9054 _(":upper16: not allowed instruction"));
9055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9056 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9058 imm
= inst
.reloc
.exp
.X_add_number
;
9059 /* The value is in two pieces: 0:11, 16:19. */
9060 inst
.instruction
|= (imm
& 0x00000fff);
9061 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9066 do_vfp_nsyn_mrs (void)
9068 if (inst
.operands
[0].isvec
)
9070 if (inst
.operands
[1].reg
!= 1)
9071 first_error (_("operand 1 must be FPSCR"));
9072 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9073 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9074 do_vfp_nsyn_opcode ("fmstat");
9076 else if (inst
.operands
[1].isvec
)
9077 do_vfp_nsyn_opcode ("fmrx");
9085 do_vfp_nsyn_msr (void)
9087 if (inst
.operands
[0].isvec
)
9088 do_vfp_nsyn_opcode ("fmxr");
9098 unsigned Rt
= inst
.operands
[0].reg
;
9100 if (thumb_mode
&& Rt
== REG_SP
)
9102 inst
.error
= BAD_SP
;
9106 /* APSR_ sets isvec. All other refs to PC are illegal. */
9107 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9109 inst
.error
= BAD_PC
;
9113 /* If we get through parsing the register name, we just insert the number
9114 generated into the instruction without further validation. */
9115 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9116 inst
.instruction
|= (Rt
<< 12);
9122 unsigned Rt
= inst
.operands
[1].reg
;
9125 reject_bad_reg (Rt
);
9126 else if (Rt
== REG_PC
)
9128 inst
.error
= BAD_PC
;
9132 /* If we get through parsing the register name, we just insert the number
9133 generated into the instruction without further validation. */
9134 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9135 inst
.instruction
|= (Rt
<< 12);
9143 if (do_vfp_nsyn_mrs () == SUCCESS
)
9146 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9149 if (inst
.operands
[1].isreg
)
9151 br
= inst
.operands
[1].reg
;
9152 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9153 as_bad (_("bad register for mrs"));
9157 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9158 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9160 _("'APSR', 'CPSR' or 'SPSR' expected"));
9161 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9164 inst
.instruction
|= br
;
9167 /* Two possible forms:
9168 "{C|S}PSR_<field>, Rm",
9169 "{C|S}PSR_f, #expression". */
9174 if (do_vfp_nsyn_msr () == SUCCESS
)
9177 inst
.instruction
|= inst
.operands
[0].imm
;
9178 if (inst
.operands
[1].isreg
)
9179 inst
.instruction
|= inst
.operands
[1].reg
;
9182 inst
.instruction
|= INST_IMMEDIATE
;
9183 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9184 inst
.reloc
.pc_rel
= 0;
9191 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9193 if (!inst
.operands
[2].present
)
9194 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9195 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9196 inst
.instruction
|= inst
.operands
[1].reg
;
9197 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9199 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9200 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9201 as_tsktsk (_("Rd and Rm should be different in mul"));
9204 /* Long Multiply Parser
9205 UMULL RdLo, RdHi, Rm, Rs
9206 SMULL RdLo, RdHi, Rm, Rs
9207 UMLAL RdLo, RdHi, Rm, Rs
9208 SMLAL RdLo, RdHi, Rm, Rs. */
9213 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9214 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9215 inst
.instruction
|= inst
.operands
[2].reg
;
9216 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9218 /* rdhi and rdlo must be different. */
9219 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9220 as_tsktsk (_("rdhi and rdlo must be different"));
9222 /* rdhi, rdlo and rm must all be different before armv6. */
9223 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9224 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9225 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9226 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9232 if (inst
.operands
[0].present
9233 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9235 /* Architectural NOP hints are CPSR sets with no bits selected. */
9236 inst
.instruction
&= 0xf0000000;
9237 inst
.instruction
|= 0x0320f000;
9238 if (inst
.operands
[0].present
)
9239 inst
.instruction
|= inst
.operands
[0].imm
;
9243 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9244 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9245 Condition defaults to COND_ALWAYS.
9246 Error if Rd, Rn or Rm are R15. */
9251 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9252 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9253 inst
.instruction
|= inst
.operands
[2].reg
;
9254 if (inst
.operands
[3].present
)
9255 encode_arm_shift (3);
9258 /* ARM V6 PKHTB (Argument Parse). */
9263 if (!inst
.operands
[3].present
)
9265 /* If the shift specifier is omitted, turn the instruction
9266 into pkhbt rd, rm, rn. */
9267 inst
.instruction
&= 0xfff00010;
9268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9269 inst
.instruction
|= inst
.operands
[1].reg
;
9270 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9275 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9276 inst
.instruction
|= inst
.operands
[2].reg
;
9277 encode_arm_shift (3);
9281 /* ARMv5TE: Preload-Cache
9282 MP Extensions: Preload for write
9286 Syntactically, like LDR with B=1, W=0, L=1. */
9291 constraint (!inst
.operands
[0].isreg
,
9292 _("'[' expected after PLD mnemonic"));
9293 constraint (inst
.operands
[0].postind
,
9294 _("post-indexed expression used in preload instruction"));
9295 constraint (inst
.operands
[0].writeback
,
9296 _("writeback used in preload instruction"));
9297 constraint (!inst
.operands
[0].preind
,
9298 _("unindexed addressing used in preload instruction"));
9299 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9302 /* ARMv7: PLI <addr_mode> */
9306 constraint (!inst
.operands
[0].isreg
,
9307 _("'[' expected after PLI mnemonic"));
9308 constraint (inst
.operands
[0].postind
,
9309 _("post-indexed expression used in preload instruction"));
9310 constraint (inst
.operands
[0].writeback
,
9311 _("writeback used in preload instruction"));
9312 constraint (!inst
.operands
[0].preind
,
9313 _("unindexed addressing used in preload instruction"));
9314 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9315 inst
.instruction
&= ~PRE_INDEX
;
9321 constraint (inst
.operands
[0].writeback
,
9322 _("push/pop do not support {reglist}^"));
9323 inst
.operands
[1] = inst
.operands
[0];
9324 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9325 inst
.operands
[0].isreg
= 1;
9326 inst
.operands
[0].writeback
= 1;
9327 inst
.operands
[0].reg
= REG_SP
;
9328 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9331 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9332 word at the specified address and the following word
9334 Unconditionally executed.
9335 Error if Rn is R15. */
9340 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9341 if (inst
.operands
[0].writeback
)
9342 inst
.instruction
|= WRITE_BACK
;
9345 /* ARM V6 ssat (argument parse). */
9350 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9351 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9352 inst
.instruction
|= inst
.operands
[2].reg
;
9354 if (inst
.operands
[3].present
)
9355 encode_arm_shift (3);
9358 /* ARM V6 usat (argument parse). */
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9365 inst
.instruction
|= inst
.operands
[2].reg
;
9367 if (inst
.operands
[3].present
)
9368 encode_arm_shift (3);
9371 /* ARM V6 ssat16 (argument parse). */
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9377 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9378 inst
.instruction
|= inst
.operands
[2].reg
;
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9385 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9386 inst
.instruction
|= inst
.operands
[2].reg
;
9389 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9390 preserving the other bits.
9392 setend <endian_specifier>, where <endian_specifier> is either
9398 if (warn_on_deprecated
9399 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9400 as_tsktsk (_("setend use is deprecated for ARMv8"));
9402 if (inst
.operands
[0].imm
)
9403 inst
.instruction
|= 0x200;
9409 unsigned int Rm
= (inst
.operands
[1].present
9410 ? inst
.operands
[1].reg
9411 : inst
.operands
[0].reg
);
9413 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9414 inst
.instruction
|= Rm
;
9415 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9417 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9418 inst
.instruction
|= SHIFT_BY_REG
;
9419 /* PR 12854: Error on extraneous shifts. */
9420 constraint (inst
.operands
[2].shifted
,
9421 _("extraneous shift as part of operand to shift insn"));
9424 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9430 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9431 inst
.reloc
.pc_rel
= 0;
9437 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9438 inst
.reloc
.pc_rel
= 0;
9444 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9445 inst
.reloc
.pc_rel
= 0;
9451 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9452 _("selected processor does not support SETPAN instruction"));
9454 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9460 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9461 _("selected processor does not support SETPAN instruction"));
9463 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9466 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9467 SMLAxy{cond} Rd,Rm,Rs,Rn
9468 SMLAWy{cond} Rd,Rm,Rs,Rn
9469 Error if any register is R15. */
9474 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9475 inst
.instruction
|= inst
.operands
[1].reg
;
9476 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9477 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9480 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9481 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9482 Error if any register is R15.
9483 Warning if Rdlo == Rdhi. */
9488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9489 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9490 inst
.instruction
|= inst
.operands
[2].reg
;
9491 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9493 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9494 as_tsktsk (_("rdhi and rdlo must be different"));
9497 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9498 SMULxy{cond} Rd,Rm,Rs
9499 Error if any register is R15. */
9504 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9505 inst
.instruction
|= inst
.operands
[1].reg
;
9506 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9509 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9510 the same for both ARM and Thumb-2. */
9517 if (inst
.operands
[0].present
)
9519 reg
= inst
.operands
[0].reg
;
9520 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9525 inst
.instruction
|= reg
<< 16;
9526 inst
.instruction
|= inst
.operands
[1].imm
;
9527 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9528 inst
.instruction
|= WRITE_BACK
;
9531 /* ARM V6 strex (argument parse). */
9536 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9537 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9538 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9539 || inst
.operands
[2].negative
9540 /* See comment in do_ldrex(). */
9541 || (inst
.operands
[2].reg
== REG_PC
),
9544 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9545 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9547 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9548 || inst
.reloc
.exp
.X_add_number
!= 0,
9549 _("offset must be zero in ARM encoding"));
9551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9552 inst
.instruction
|= inst
.operands
[1].reg
;
9553 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9554 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9560 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9561 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9562 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9563 || inst
.operands
[2].negative
,
9566 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9567 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9575 constraint (inst
.operands
[1].reg
% 2 != 0,
9576 _("even register required"));
9577 constraint (inst
.operands
[2].present
9578 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9579 _("can only store two consecutive registers"));
9580 /* If op 2 were present and equal to PC, this function wouldn't
9581 have been called in the first place. */
9582 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9584 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9585 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9586 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9590 inst
.instruction
|= inst
.operands
[1].reg
;
9591 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9598 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9599 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9607 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9608 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9613 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9614 extends it to 32-bits, and adds the result to a value in another
9615 register. You can specify a rotation by 0, 8, 16, or 24 bits
9616 before extracting the 16-bit value.
9617 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9618 Condition defaults to COND_ALWAYS.
9619 Error if any register uses R15. */
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9625 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9626 inst
.instruction
|= inst
.operands
[2].reg
;
9627 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9632 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9633 Condition defaults to COND_ALWAYS.
9634 Error if any register uses R15. */
9639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9640 inst
.instruction
|= inst
.operands
[1].reg
;
9641 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9644 /* VFP instructions. In a logical order: SP variant first, monad
9645 before dyad, arithmetic then move then load/store. */
9648 do_vfp_sp_monadic (void)
9650 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9651 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9655 do_vfp_sp_dyadic (void)
9657 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9658 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9659 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9663 do_vfp_sp_compare_z (void)
9665 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9669 do_vfp_dp_sp_cvt (void)
9671 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9672 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9676 do_vfp_sp_dp_cvt (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9679 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9683 do_vfp_reg_from_sp (void)
9685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9690 do_vfp_reg2_from_sp2 (void)
9692 constraint (inst
.operands
[2].imm
!= 2,
9693 _("only two consecutive VFP SP registers allowed here"));
9694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9695 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9696 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9700 do_vfp_sp_from_reg (void)
9702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9703 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9707 do_vfp_sp2_from_reg2 (void)
9709 constraint (inst
.operands
[0].imm
!= 2,
9710 _("only two consecutive VFP SP registers allowed here"));
9711 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9712 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9713 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9717 do_vfp_sp_ldst (void)
9719 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9720 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9724 do_vfp_dp_ldst (void)
9726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9727 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9732 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9734 if (inst
.operands
[0].writeback
)
9735 inst
.instruction
|= WRITE_BACK
;
9737 constraint (ldstm_type
!= VFP_LDSTMIA
,
9738 _("this addressing mode requires base-register writeback"));
9739 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9740 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9741 inst
.instruction
|= inst
.operands
[1].imm
;
9745 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9749 if (inst
.operands
[0].writeback
)
9750 inst
.instruction
|= WRITE_BACK
;
9752 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9753 _("this addressing mode requires base-register writeback"));
9755 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9756 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9758 count
= inst
.operands
[1].imm
<< 1;
9759 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9762 inst
.instruction
|= count
;
9766 do_vfp_sp_ldstmia (void)
9768 vfp_sp_ldstm (VFP_LDSTMIA
);
9772 do_vfp_sp_ldstmdb (void)
9774 vfp_sp_ldstm (VFP_LDSTMDB
);
9778 do_vfp_dp_ldstmia (void)
9780 vfp_dp_ldstm (VFP_LDSTMIA
);
9784 do_vfp_dp_ldstmdb (void)
9786 vfp_dp_ldstm (VFP_LDSTMDB
);
9790 do_vfp_xp_ldstmia (void)
9792 vfp_dp_ldstm (VFP_LDSTMIAX
);
9796 do_vfp_xp_ldstmdb (void)
9798 vfp_dp_ldstm (VFP_LDSTMDBX
);
9802 do_vfp_dp_rd_rm (void)
9804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9805 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9809 do_vfp_dp_rn_rd (void)
9811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9812 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9816 do_vfp_dp_rd_rn (void)
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9819 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9823 do_vfp_dp_rd_rn_rm (void)
9825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9826 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9827 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9833 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9837 do_vfp_dp_rm_rd_rn (void)
9839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9841 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9844 /* VFPv3 instructions. */
9846 do_vfp_sp_const (void)
9848 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9849 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9850 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9854 do_vfp_dp_const (void)
9856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9857 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9858 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9862 vfp_conv (int srcsize
)
9864 int immbits
= srcsize
- inst
.operands
[1].imm
;
9866 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9868 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9869 i.e. immbits must be in range 0 - 16. */
9870 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9873 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9875 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9876 i.e. immbits must be in range 0 - 31. */
9877 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9881 inst
.instruction
|= (immbits
& 1) << 5;
9882 inst
.instruction
|= (immbits
>> 1);
9886 do_vfp_sp_conv_16 (void)
9888 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9893 do_vfp_dp_conv_16 (void)
9895 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9900 do_vfp_sp_conv_32 (void)
9902 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9907 do_vfp_dp_conv_32 (void)
9909 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9913 /* FPA instructions. Also in a logical order. */
9918 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9919 inst
.instruction
|= inst
.operands
[1].reg
;
9923 do_fpa_ldmstm (void)
9925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9926 switch (inst
.operands
[1].imm
)
9928 case 1: inst
.instruction
|= CP_T_X
; break;
9929 case 2: inst
.instruction
|= CP_T_Y
; break;
9930 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9935 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9937 /* The instruction specified "ea" or "fd", so we can only accept
9938 [Rn]{!}. The instruction does not really support stacking or
9939 unstacking, so we have to emulate these by setting appropriate
9940 bits and offsets. */
9941 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9942 || inst
.reloc
.exp
.X_add_number
!= 0,
9943 _("this instruction does not support indexing"));
9945 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9946 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9948 if (!(inst
.instruction
& INDEX_UP
))
9949 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9951 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9953 inst
.operands
[2].preind
= 0;
9954 inst
.operands
[2].postind
= 1;
9958 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9961 /* iWMMXt instructions: strictly in alphabetical order. */
9964 do_iwmmxt_tandorc (void)
9966 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9970 do_iwmmxt_textrc (void)
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9973 inst
.instruction
|= inst
.operands
[1].imm
;
9977 do_iwmmxt_textrm (void)
9979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9981 inst
.instruction
|= inst
.operands
[2].imm
;
9985 do_iwmmxt_tinsr (void)
9987 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9988 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9989 inst
.instruction
|= inst
.operands
[2].imm
;
9993 do_iwmmxt_tmia (void)
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9996 inst
.instruction
|= inst
.operands
[1].reg
;
9997 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10001 do_iwmmxt_waligni (void)
10003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10004 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10005 inst
.instruction
|= inst
.operands
[2].reg
;
10006 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10010 do_iwmmxt_wmerge (void)
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10013 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10014 inst
.instruction
|= inst
.operands
[2].reg
;
10015 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10019 do_iwmmxt_wmov (void)
10021 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10024 inst
.instruction
|= inst
.operands
[1].reg
;
10028 do_iwmmxt_wldstbh (void)
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10033 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10035 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10036 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10040 do_iwmmxt_wldstw (void)
10042 /* RIWR_RIWC clears .isreg for a control register. */
10043 if (!inst
.operands
[0].isreg
)
10045 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10046 inst
.instruction
|= 0xf0000000;
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10050 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10054 do_iwmmxt_wldstd (void)
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10057 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10058 && inst
.operands
[1].immisreg
)
10060 inst
.instruction
&= ~0x1a000ff;
10061 inst
.instruction
|= (0xfU
<< 28);
10062 if (inst
.operands
[1].preind
)
10063 inst
.instruction
|= PRE_INDEX
;
10064 if (!inst
.operands
[1].negative
)
10065 inst
.instruction
|= INDEX_UP
;
10066 if (inst
.operands
[1].writeback
)
10067 inst
.instruction
|= WRITE_BACK
;
10068 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10069 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10070 inst
.instruction
|= inst
.operands
[1].imm
;
10073 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10077 do_iwmmxt_wshufh (void)
10079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10080 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10081 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10082 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10086 do_iwmmxt_wzero (void)
10088 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10089 inst
.instruction
|= inst
.operands
[0].reg
;
10090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10091 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10095 do_iwmmxt_wrwrwr_or_imm5 (void)
10097 if (inst
.operands
[2].isreg
)
10100 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10101 _("immediate operand requires iWMMXt2"));
10103 if (inst
.operands
[2].imm
== 0)
10105 switch ((inst
.instruction
>> 20) & 0xf)
10111 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10112 inst
.operands
[2].imm
= 16;
10113 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10119 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10120 inst
.operands
[2].imm
= 32;
10121 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10128 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10130 wrn
= (inst
.instruction
>> 16) & 0xf;
10131 inst
.instruction
&= 0xff0fff0f;
10132 inst
.instruction
|= wrn
;
10133 /* Bail out here; the instruction is now assembled. */
10138 /* Map 32 -> 0, etc. */
10139 inst
.operands
[2].imm
&= 0x1f;
10140 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10144 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10145 operations first, then control, shift, and load/store. */
10147 /* Insns like "foo X,Y,Z". */
10150 do_mav_triple (void)
10152 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10153 inst
.instruction
|= inst
.operands
[1].reg
;
10154 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10157 /* Insns like "foo W,X,Y,Z".
10158 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10163 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10164 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10165 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10166 inst
.instruction
|= inst
.operands
[3].reg
;
10169 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10171 do_mav_dspsc (void)
10173 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10176 /* Maverick shift immediate instructions.
10177 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10178 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10181 do_mav_shift (void)
10183 int imm
= inst
.operands
[2].imm
;
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10188 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10189 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10190 Bit 4 should be 0. */
10191 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10193 inst
.instruction
|= imm
;
10196 /* XScale instructions. Also sorted arithmetic before move. */
10198 /* Xscale multiply-accumulate (argument parse)
10201 MIAxycc acc0,Rm,Rs. */
10206 inst
.instruction
|= inst
.operands
[1].reg
;
10207 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10210 /* Xscale move-accumulator-register (argument parse)
10212 MARcc acc0,RdLo,RdHi. */
10217 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10218 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10221 /* Xscale move-register-accumulator (argument parse)
10223 MRAcc RdLo,RdHi,acc0. */
10228 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10230 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10233 /* Encoding functions relevant only to Thumb. */
10235 /* inst.operands[i] is a shifted-register operand; encode
10236 it into inst.instruction in the format used by Thumb32. */
10239 encode_thumb32_shifted_operand (int i
)
10241 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10242 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10244 constraint (inst
.operands
[i
].immisreg
,
10245 _("shift by register not allowed in thumb mode"));
10246 inst
.instruction
|= inst
.operands
[i
].reg
;
10247 if (shift
== SHIFT_RRX
)
10248 inst
.instruction
|= SHIFT_ROR
<< 4;
10251 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10252 _("expression too complex"));
10254 constraint (value
> 32
10255 || (value
== 32 && (shift
== SHIFT_LSL
10256 || shift
== SHIFT_ROR
)),
10257 _("shift expression is too large"));
10261 else if (value
== 32)
10264 inst
.instruction
|= shift
<< 4;
10265 inst
.instruction
|= (value
& 0x1c) << 10;
10266 inst
.instruction
|= (value
& 0x03) << 6;
10271 /* inst.operands[i] was set up by parse_address. Encode it into a
10272 Thumb32 format load or store instruction. Reject forms that cannot
10273 be used with such instructions. If is_t is true, reject forms that
10274 cannot be used with a T instruction; if is_d is true, reject forms
10275 that cannot be used with a D instruction. If it is a store insn,
10276 reject PC in Rn. */
10279 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10281 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10283 constraint (!inst
.operands
[i
].isreg
,
10284 _("Instruction does not support =N addresses"));
10286 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10287 if (inst
.operands
[i
].immisreg
)
10289 constraint (is_pc
, BAD_PC_ADDRESSING
);
10290 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10291 constraint (inst
.operands
[i
].negative
,
10292 _("Thumb does not support negative register indexing"));
10293 constraint (inst
.operands
[i
].postind
,
10294 _("Thumb does not support register post-indexing"));
10295 constraint (inst
.operands
[i
].writeback
,
10296 _("Thumb does not support register indexing with writeback"));
10297 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10298 _("Thumb supports only LSL in shifted register indexing"));
10300 inst
.instruction
|= inst
.operands
[i
].imm
;
10301 if (inst
.operands
[i
].shifted
)
10303 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10304 _("expression too complex"));
10305 constraint (inst
.reloc
.exp
.X_add_number
< 0
10306 || inst
.reloc
.exp
.X_add_number
> 3,
10307 _("shift out of range"));
10308 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10310 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10312 else if (inst
.operands
[i
].preind
)
10314 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10315 constraint (is_t
&& inst
.operands
[i
].writeback
,
10316 _("cannot use writeback with this instruction"));
10317 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10318 BAD_PC_ADDRESSING
);
10322 inst
.instruction
|= 0x01000000;
10323 if (inst
.operands
[i
].writeback
)
10324 inst
.instruction
|= 0x00200000;
10328 inst
.instruction
|= 0x00000c00;
10329 if (inst
.operands
[i
].writeback
)
10330 inst
.instruction
|= 0x00000100;
10332 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10334 else if (inst
.operands
[i
].postind
)
10336 gas_assert (inst
.operands
[i
].writeback
);
10337 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10338 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10341 inst
.instruction
|= 0x00200000;
10343 inst
.instruction
|= 0x00000900;
10344 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10346 else /* unindexed - only for coprocessor */
10347 inst
.error
= _("instruction does not accept unindexed addressing");
10350 /* Table of Thumb instructions which exist in both 16- and 32-bit
10351 encodings (the latter only in post-V6T2 cores). The index is the
10352 value used in the insns table below. When there is more than one
10353 possible 16-bit encoding for the instruction, this table always
10355 Also contains several pseudo-instructions used during relaxation. */
10356 #define T16_32_TAB \
10357 X(_adc, 4140, eb400000), \
10358 X(_adcs, 4140, eb500000), \
10359 X(_add, 1c00, eb000000), \
10360 X(_adds, 1c00, eb100000), \
10361 X(_addi, 0000, f1000000), \
10362 X(_addis, 0000, f1100000), \
10363 X(_add_pc,000f, f20f0000), \
10364 X(_add_sp,000d, f10d0000), \
10365 X(_adr, 000f, f20f0000), \
10366 X(_and, 4000, ea000000), \
10367 X(_ands, 4000, ea100000), \
10368 X(_asr, 1000, fa40f000), \
10369 X(_asrs, 1000, fa50f000), \
10370 X(_b, e000, f000b000), \
10371 X(_bcond, d000, f0008000), \
10372 X(_bic, 4380, ea200000), \
10373 X(_bics, 4380, ea300000), \
10374 X(_cmn, 42c0, eb100f00), \
10375 X(_cmp, 2800, ebb00f00), \
10376 X(_cpsie, b660, f3af8400), \
10377 X(_cpsid, b670, f3af8600), \
10378 X(_cpy, 4600, ea4f0000), \
10379 X(_dec_sp,80dd, f1ad0d00), \
10380 X(_eor, 4040, ea800000), \
10381 X(_eors, 4040, ea900000), \
10382 X(_inc_sp,00dd, f10d0d00), \
10383 X(_ldmia, c800, e8900000), \
10384 X(_ldr, 6800, f8500000), \
10385 X(_ldrb, 7800, f8100000), \
10386 X(_ldrh, 8800, f8300000), \
10387 X(_ldrsb, 5600, f9100000), \
10388 X(_ldrsh, 5e00, f9300000), \
10389 X(_ldr_pc,4800, f85f0000), \
10390 X(_ldr_pc2,4800, f85f0000), \
10391 X(_ldr_sp,9800, f85d0000), \
10392 X(_lsl, 0000, fa00f000), \
10393 X(_lsls, 0000, fa10f000), \
10394 X(_lsr, 0800, fa20f000), \
10395 X(_lsrs, 0800, fa30f000), \
10396 X(_mov, 2000, ea4f0000), \
10397 X(_movs, 2000, ea5f0000), \
10398 X(_mul, 4340, fb00f000), \
10399 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10400 X(_mvn, 43c0, ea6f0000), \
10401 X(_mvns, 43c0, ea7f0000), \
10402 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10403 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10404 X(_orr, 4300, ea400000), \
10405 X(_orrs, 4300, ea500000), \
10406 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10407 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10408 X(_rev, ba00, fa90f080), \
10409 X(_rev16, ba40, fa90f090), \
10410 X(_revsh, bac0, fa90f0b0), \
10411 X(_ror, 41c0, fa60f000), \
10412 X(_rors, 41c0, fa70f000), \
10413 X(_sbc, 4180, eb600000), \
10414 X(_sbcs, 4180, eb700000), \
10415 X(_stmia, c000, e8800000), \
10416 X(_str, 6000, f8400000), \
10417 X(_strb, 7000, f8000000), \
10418 X(_strh, 8000, f8200000), \
10419 X(_str_sp,9000, f84d0000), \
10420 X(_sub, 1e00, eba00000), \
10421 X(_subs, 1e00, ebb00000), \
10422 X(_subi, 8000, f1a00000), \
10423 X(_subis, 8000, f1b00000), \
10424 X(_sxtb, b240, fa4ff080), \
10425 X(_sxth, b200, fa0ff080), \
10426 X(_tst, 4200, ea100f00), \
10427 X(_uxtb, b2c0, fa5ff080), \
10428 X(_uxth, b280, fa1ff080), \
10429 X(_nop, bf00, f3af8000), \
10430 X(_yield, bf10, f3af8001), \
10431 X(_wfe, bf20, f3af8002), \
10432 X(_wfi, bf30, f3af8003), \
10433 X(_sev, bf40, f3af8004), \
10434 X(_sevl, bf50, f3af8005), \
10435 X(_udf, de00, f7f0a000)
10437 /* To catch errors in encoding functions, the codes are all offset by
10438 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10439 as 16-bit instructions. */
10440 #define X(a,b,c) T_MNEM##a
10441 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10444 #define X(a,b,c) 0x##b
10445 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10446 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10449 #define X(a,b,c) 0x##c
10450 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10451 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10452 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10456 /* Thumb instruction encoders, in alphabetical order. */
10458 /* ADDW or SUBW. */
10461 do_t_add_sub_w (void)
10465 Rd
= inst
.operands
[0].reg
;
10466 Rn
= inst
.operands
[1].reg
;
10468 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10469 is the SP-{plus,minus}-immediate form of the instruction. */
10471 constraint (Rd
== REG_PC
, BAD_PC
);
10473 reject_bad_reg (Rd
);
10475 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10476 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10479 /* Parse an add or subtract instruction. We get here with inst.instruction
10480 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10483 do_t_add_sub (void)
10487 Rd
= inst
.operands
[0].reg
;
10488 Rs
= (inst
.operands
[1].present
10489 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10490 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10493 set_it_insn_type_last ();
10495 if (unified_syntax
)
10498 bfd_boolean narrow
;
10501 flags
= (inst
.instruction
== T_MNEM_adds
10502 || inst
.instruction
== T_MNEM_subs
);
10504 narrow
= !in_it_block ();
10506 narrow
= in_it_block ();
10507 if (!inst
.operands
[2].isreg
)
10511 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10513 add
= (inst
.instruction
== T_MNEM_add
10514 || inst
.instruction
== T_MNEM_adds
);
10516 if (inst
.size_req
!= 4)
10518 /* Attempt to use a narrow opcode, with relaxation if
10520 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10521 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10522 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10523 opcode
= T_MNEM_add_sp
;
10524 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10525 opcode
= T_MNEM_add_pc
;
10526 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10529 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10531 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10535 inst
.instruction
= THUMB_OP16(opcode
);
10536 inst
.instruction
|= (Rd
<< 4) | Rs
;
10537 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10538 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10540 if (inst
.size_req
== 2)
10541 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10543 inst
.relax
= opcode
;
10547 constraint (inst
.size_req
== 2, BAD_HIREG
);
10549 if (inst
.size_req
== 4
10550 || (inst
.size_req
!= 2 && !opcode
))
10552 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10553 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10554 THUMB1_RELOC_ONLY
);
10557 constraint (add
, BAD_PC
);
10558 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10559 _("only SUBS PC, LR, #const allowed"));
10560 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10561 _("expression too complex"));
10562 constraint (inst
.reloc
.exp
.X_add_number
< 0
10563 || inst
.reloc
.exp
.X_add_number
> 0xff,
10564 _("immediate value out of range"));
10565 inst
.instruction
= T2_SUBS_PC_LR
10566 | inst
.reloc
.exp
.X_add_number
;
10567 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10570 else if (Rs
== REG_PC
)
10572 /* Always use addw/subw. */
10573 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10574 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10578 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10579 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10582 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10584 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10586 inst
.instruction
|= Rd
<< 8;
10587 inst
.instruction
|= Rs
<< 16;
10592 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10593 unsigned int shift
= inst
.operands
[2].shift_kind
;
10595 Rn
= inst
.operands
[2].reg
;
10596 /* See if we can do this with a 16-bit instruction. */
10597 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10599 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10604 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10605 || inst
.instruction
== T_MNEM_add
)
10607 : T_OPCODE_SUB_R3
);
10608 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10612 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10614 /* Thumb-1 cores (except v6-M) require at least one high
10615 register in a narrow non flag setting add. */
10616 if (Rd
> 7 || Rn
> 7
10617 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10618 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10625 inst
.instruction
= T_OPCODE_ADD_HI
;
10626 inst
.instruction
|= (Rd
& 8) << 4;
10627 inst
.instruction
|= (Rd
& 7);
10628 inst
.instruction
|= Rn
<< 3;
10634 constraint (Rd
== REG_PC
, BAD_PC
);
10635 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10636 constraint (Rs
== REG_PC
, BAD_PC
);
10637 reject_bad_reg (Rn
);
10639 /* If we get here, it can't be done in 16 bits. */
10640 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10641 _("shift must be constant"));
10642 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10643 inst
.instruction
|= Rd
<< 8;
10644 inst
.instruction
|= Rs
<< 16;
10645 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10646 _("shift value over 3 not allowed in thumb mode"));
10647 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10648 _("only LSL shift allowed in thumb mode"));
10649 encode_thumb32_shifted_operand (2);
10654 constraint (inst
.instruction
== T_MNEM_adds
10655 || inst
.instruction
== T_MNEM_subs
,
10658 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10660 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10661 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10664 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10665 ? 0x0000 : 0x8000);
10666 inst
.instruction
|= (Rd
<< 4) | Rs
;
10667 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10671 Rn
= inst
.operands
[2].reg
;
10672 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10674 /* We now have Rd, Rs, and Rn set to registers. */
10675 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10677 /* Can't do this for SUB. */
10678 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10679 inst
.instruction
= T_OPCODE_ADD_HI
;
10680 inst
.instruction
|= (Rd
& 8) << 4;
10681 inst
.instruction
|= (Rd
& 7);
10683 inst
.instruction
|= Rn
<< 3;
10685 inst
.instruction
|= Rs
<< 3;
10687 constraint (1, _("dest must overlap one source register"));
10691 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10692 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10693 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10703 Rd
= inst
.operands
[0].reg
;
10704 reject_bad_reg (Rd
);
10706 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10708 /* Defer to section relaxation. */
10709 inst
.relax
= inst
.instruction
;
10710 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10711 inst
.instruction
|= Rd
<< 4;
10713 else if (unified_syntax
&& inst
.size_req
!= 2)
10715 /* Generate a 32-bit opcode. */
10716 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10717 inst
.instruction
|= Rd
<< 8;
10718 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10719 inst
.reloc
.pc_rel
= 1;
10723 /* Generate a 16-bit opcode. */
10724 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10725 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10726 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10727 inst
.reloc
.pc_rel
= 1;
10729 inst
.instruction
|= Rd
<< 4;
10733 /* Arithmetic instructions for which there is just one 16-bit
10734 instruction encoding, and it allows only two low registers.
10735 For maximal compatibility with ARM syntax, we allow three register
10736 operands even when Thumb-32 instructions are not available, as long
10737 as the first two are identical. For instance, both "sbc r0,r1" and
10738 "sbc r0,r0,r1" are allowed. */
10744 Rd
= inst
.operands
[0].reg
;
10745 Rs
= (inst
.operands
[1].present
10746 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10747 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10748 Rn
= inst
.operands
[2].reg
;
10750 reject_bad_reg (Rd
);
10751 reject_bad_reg (Rs
);
10752 if (inst
.operands
[2].isreg
)
10753 reject_bad_reg (Rn
);
10755 if (unified_syntax
)
10757 if (!inst
.operands
[2].isreg
)
10759 /* For an immediate, we always generate a 32-bit opcode;
10760 section relaxation will shrink it later if possible. */
10761 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10762 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10763 inst
.instruction
|= Rd
<< 8;
10764 inst
.instruction
|= Rs
<< 16;
10765 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10769 bfd_boolean narrow
;
10771 /* See if we can do this with a 16-bit instruction. */
10772 if (THUMB_SETS_FLAGS (inst
.instruction
))
10773 narrow
= !in_it_block ();
10775 narrow
= in_it_block ();
10777 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10779 if (inst
.operands
[2].shifted
)
10781 if (inst
.size_req
== 4)
10787 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10788 inst
.instruction
|= Rd
;
10789 inst
.instruction
|= Rn
<< 3;
10793 /* If we get here, it can't be done in 16 bits. */
10794 constraint (inst
.operands
[2].shifted
10795 && inst
.operands
[2].immisreg
,
10796 _("shift must be constant"));
10797 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10798 inst
.instruction
|= Rd
<< 8;
10799 inst
.instruction
|= Rs
<< 16;
10800 encode_thumb32_shifted_operand (2);
10805 /* On its face this is a lie - the instruction does set the
10806 flags. However, the only supported mnemonic in this mode
10807 says it doesn't. */
10808 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10810 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10811 _("unshifted register required"));
10812 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10813 constraint (Rd
!= Rs
,
10814 _("dest and source1 must be the same register"));
10816 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10817 inst
.instruction
|= Rd
;
10818 inst
.instruction
|= Rn
<< 3;
10822 /* Similarly, but for instructions where the arithmetic operation is
10823 commutative, so we can allow either of them to be different from
10824 the destination operand in a 16-bit instruction. For instance, all
10825 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10832 Rd
= inst
.operands
[0].reg
;
10833 Rs
= (inst
.operands
[1].present
10834 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10835 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10836 Rn
= inst
.operands
[2].reg
;
10838 reject_bad_reg (Rd
);
10839 reject_bad_reg (Rs
);
10840 if (inst
.operands
[2].isreg
)
10841 reject_bad_reg (Rn
);
10843 if (unified_syntax
)
10845 if (!inst
.operands
[2].isreg
)
10847 /* For an immediate, we always generate a 32-bit opcode;
10848 section relaxation will shrink it later if possible. */
10849 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10850 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10851 inst
.instruction
|= Rd
<< 8;
10852 inst
.instruction
|= Rs
<< 16;
10853 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10857 bfd_boolean narrow
;
10859 /* See if we can do this with a 16-bit instruction. */
10860 if (THUMB_SETS_FLAGS (inst
.instruction
))
10861 narrow
= !in_it_block ();
10863 narrow
= in_it_block ();
10865 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10867 if (inst
.operands
[2].shifted
)
10869 if (inst
.size_req
== 4)
10876 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10877 inst
.instruction
|= Rd
;
10878 inst
.instruction
|= Rn
<< 3;
10883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10884 inst
.instruction
|= Rd
;
10885 inst
.instruction
|= Rs
<< 3;
10890 /* If we get here, it can't be done in 16 bits. */
10891 constraint (inst
.operands
[2].shifted
10892 && inst
.operands
[2].immisreg
,
10893 _("shift must be constant"));
10894 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10895 inst
.instruction
|= Rd
<< 8;
10896 inst
.instruction
|= Rs
<< 16;
10897 encode_thumb32_shifted_operand (2);
10902 /* On its face this is a lie - the instruction does set the
10903 flags. However, the only supported mnemonic in this mode
10904 says it doesn't. */
10905 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10907 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10908 _("unshifted register required"));
10909 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10911 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10912 inst
.instruction
|= Rd
;
10915 inst
.instruction
|= Rn
<< 3;
10917 inst
.instruction
|= Rs
<< 3;
10919 constraint (1, _("dest must overlap one source register"));
10927 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10928 constraint (msb
> 32, _("bit-field extends past end of register"));
10929 /* The instruction encoding stores the LSB and MSB,
10930 not the LSB and width. */
10931 Rd
= inst
.operands
[0].reg
;
10932 reject_bad_reg (Rd
);
10933 inst
.instruction
|= Rd
<< 8;
10934 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10935 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10936 inst
.instruction
|= msb
- 1;
10945 Rd
= inst
.operands
[0].reg
;
10946 reject_bad_reg (Rd
);
10948 /* #0 in second position is alternative syntax for bfc, which is
10949 the same instruction but with REG_PC in the Rm field. */
10950 if (!inst
.operands
[1].isreg
)
10954 Rn
= inst
.operands
[1].reg
;
10955 reject_bad_reg (Rn
);
10958 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10959 constraint (msb
> 32, _("bit-field extends past end of register"));
10960 /* The instruction encoding stores the LSB and MSB,
10961 not the LSB and width. */
10962 inst
.instruction
|= Rd
<< 8;
10963 inst
.instruction
|= Rn
<< 16;
10964 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10965 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10966 inst
.instruction
|= msb
- 1;
10974 Rd
= inst
.operands
[0].reg
;
10975 Rn
= inst
.operands
[1].reg
;
10977 reject_bad_reg (Rd
);
10978 reject_bad_reg (Rn
);
10980 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10981 _("bit-field extends past end of register"));
10982 inst
.instruction
|= Rd
<< 8;
10983 inst
.instruction
|= Rn
<< 16;
10984 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10985 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10986 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10989 /* ARM V5 Thumb BLX (argument parse)
10990 BLX <target_addr> which is BLX(1)
10991 BLX <Rm> which is BLX(2)
10992 Unfortunately, there are two different opcodes for this mnemonic.
10993 So, the insns[].value is not used, and the code here zaps values
10994 into inst.instruction.
10996 ??? How to take advantage of the additional two bits of displacement
10997 available in Thumb32 mode? Need new relocation? */
11002 set_it_insn_type_last ();
11004 if (inst
.operands
[0].isreg
)
11006 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11007 /* We have a register, so this is BLX(2). */
11008 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11012 /* No register. This must be BLX(1). */
11013 inst
.instruction
= 0xf000e800;
11014 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11023 bfd_reloc_code_real_type reloc
;
11026 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11028 if (in_it_block ())
11030 /* Conditional branches inside IT blocks are encoded as unconditional
11032 cond
= COND_ALWAYS
;
11037 if (cond
!= COND_ALWAYS
)
11038 opcode
= T_MNEM_bcond
;
11040 opcode
= inst
.instruction
;
11043 && (inst
.size_req
== 4
11044 || (inst
.size_req
!= 2
11045 && (inst
.operands
[0].hasreloc
11046 || inst
.reloc
.exp
.X_op
== O_constant
))))
11048 inst
.instruction
= THUMB_OP32(opcode
);
11049 if (cond
== COND_ALWAYS
)
11050 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11054 _("selected architecture does not support "
11055 "wide conditional branch instruction"));
11057 gas_assert (cond
!= 0xF);
11058 inst
.instruction
|= cond
<< 22;
11059 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11064 inst
.instruction
= THUMB_OP16(opcode
);
11065 if (cond
== COND_ALWAYS
)
11066 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11069 inst
.instruction
|= cond
<< 8;
11070 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11072 /* Allow section relaxation. */
11073 if (unified_syntax
&& inst
.size_req
!= 2)
11074 inst
.relax
= opcode
;
11076 inst
.reloc
.type
= reloc
;
11077 inst
.reloc
.pc_rel
= 1;
11080 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11081 between the two is the maximum immediate allowed - which is passed in
11084 do_t_bkpt_hlt1 (int range
)
11086 constraint (inst
.cond
!= COND_ALWAYS
,
11087 _("instruction is always unconditional"));
11088 if (inst
.operands
[0].present
)
11090 constraint (inst
.operands
[0].imm
> range
,
11091 _("immediate value out of range"));
11092 inst
.instruction
|= inst
.operands
[0].imm
;
11095 set_it_insn_type (NEUTRAL_IT_INSN
);
11101 do_t_bkpt_hlt1 (63);
11107 do_t_bkpt_hlt1 (255);
11111 do_t_branch23 (void)
11113 set_it_insn_type_last ();
11114 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11116 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11117 this file. We used to simply ignore the PLT reloc type here --
11118 the branch encoding is now needed to deal with TLSCALL relocs.
11119 So if we see a PLT reloc now, put it back to how it used to be to
11120 keep the preexisting behaviour. */
11121 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11122 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11124 #if defined(OBJ_COFF)
11125 /* If the destination of the branch is a defined symbol which does not have
11126 the THUMB_FUNC attribute, then we must be calling a function which has
11127 the (interfacearm) attribute. We look for the Thumb entry point to that
11128 function and change the branch to refer to that function instead. */
11129 if ( inst
.reloc
.exp
.X_op
== O_symbol
11130 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11131 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11132 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11133 inst
.reloc
.exp
.X_add_symbol
=
11134 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11141 set_it_insn_type_last ();
11142 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11143 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11144 should cause the alignment to be checked once it is known. This is
11145 because BX PC only works if the instruction is word aligned. */
11153 set_it_insn_type_last ();
11154 Rm
= inst
.operands
[0].reg
;
11155 reject_bad_reg (Rm
);
11156 inst
.instruction
|= Rm
<< 16;
11165 Rd
= inst
.operands
[0].reg
;
11166 Rm
= inst
.operands
[1].reg
;
11168 reject_bad_reg (Rd
);
11169 reject_bad_reg (Rm
);
11171 inst
.instruction
|= Rd
<< 8;
11172 inst
.instruction
|= Rm
<< 16;
11173 inst
.instruction
|= Rm
;
11179 set_it_insn_type (OUTSIDE_IT_INSN
);
11180 inst
.instruction
|= inst
.operands
[0].imm
;
11186 set_it_insn_type (OUTSIDE_IT_INSN
);
11188 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11189 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11191 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11192 inst
.instruction
= 0xf3af8000;
11193 inst
.instruction
|= imod
<< 9;
11194 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11195 if (inst
.operands
[1].present
)
11196 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11200 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11201 && (inst
.operands
[0].imm
& 4),
11202 _("selected processor does not support 'A' form "
11203 "of this instruction"));
11204 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11205 _("Thumb does not support the 2-argument "
11206 "form of this instruction"));
11207 inst
.instruction
|= inst
.operands
[0].imm
;
11211 /* THUMB CPY instruction (argument parse). */
11216 if (inst
.size_req
== 4)
11218 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11219 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11220 inst
.instruction
|= inst
.operands
[1].reg
;
11224 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11225 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11226 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11233 set_it_insn_type (OUTSIDE_IT_INSN
);
11234 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11235 inst
.instruction
|= inst
.operands
[0].reg
;
11236 inst
.reloc
.pc_rel
= 1;
11237 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11243 inst
.instruction
|= inst
.operands
[0].imm
;
11249 unsigned Rd
, Rn
, Rm
;
11251 Rd
= inst
.operands
[0].reg
;
11252 Rn
= (inst
.operands
[1].present
11253 ? inst
.operands
[1].reg
: Rd
);
11254 Rm
= inst
.operands
[2].reg
;
11256 reject_bad_reg (Rd
);
11257 reject_bad_reg (Rn
);
11258 reject_bad_reg (Rm
);
11260 inst
.instruction
|= Rd
<< 8;
11261 inst
.instruction
|= Rn
<< 16;
11262 inst
.instruction
|= Rm
;
11268 if (unified_syntax
&& inst
.size_req
== 4)
11269 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11271 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11277 unsigned int cond
= inst
.operands
[0].imm
;
11279 set_it_insn_type (IT_INSN
);
11280 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11282 now_it
.warn_deprecated
= FALSE
;
11284 /* If the condition is a negative condition, invert the mask. */
11285 if ((cond
& 0x1) == 0x0)
11287 unsigned int mask
= inst
.instruction
& 0x000f;
11289 if ((mask
& 0x7) == 0)
11291 /* No conversion needed. */
11292 now_it
.block_length
= 1;
11294 else if ((mask
& 0x3) == 0)
11297 now_it
.block_length
= 2;
11299 else if ((mask
& 0x1) == 0)
11302 now_it
.block_length
= 3;
11307 now_it
.block_length
= 4;
11310 inst
.instruction
&= 0xfff0;
11311 inst
.instruction
|= mask
;
11314 inst
.instruction
|= cond
<< 4;
11317 /* Helper function used for both push/pop and ldm/stm. */
11319 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11323 load
= (inst
.instruction
& (1 << 20)) != 0;
11325 if (mask
& (1 << 13))
11326 inst
.error
= _("SP not allowed in register list");
11328 if ((mask
& (1 << base
)) != 0
11330 inst
.error
= _("having the base register in the register list when "
11331 "using write back is UNPREDICTABLE");
11335 if (mask
& (1 << 15))
11337 if (mask
& (1 << 14))
11338 inst
.error
= _("LR and PC should not both be in register list");
11340 set_it_insn_type_last ();
11345 if (mask
& (1 << 15))
11346 inst
.error
= _("PC not allowed in register list");
11349 if ((mask
& (mask
- 1)) == 0)
11351 /* Single register transfers implemented as str/ldr. */
11354 if (inst
.instruction
& (1 << 23))
11355 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11357 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11361 if (inst
.instruction
& (1 << 23))
11362 inst
.instruction
= 0x00800000; /* ia -> [base] */
11364 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11367 inst
.instruction
|= 0xf8400000;
11369 inst
.instruction
|= 0x00100000;
11371 mask
= ffs (mask
) - 1;
11374 else if (writeback
)
11375 inst
.instruction
|= WRITE_BACK
;
11377 inst
.instruction
|= mask
;
11378 inst
.instruction
|= base
<< 16;
11384 /* This really doesn't seem worth it. */
11385 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11386 _("expression too complex"));
11387 constraint (inst
.operands
[1].writeback
,
11388 _("Thumb load/store multiple does not support {reglist}^"));
11390 if (unified_syntax
)
11392 bfd_boolean narrow
;
11396 /* See if we can use a 16-bit instruction. */
11397 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11398 && inst
.size_req
!= 4
11399 && !(inst
.operands
[1].imm
& ~0xff))
11401 mask
= 1 << inst
.operands
[0].reg
;
11403 if (inst
.operands
[0].reg
<= 7)
11405 if (inst
.instruction
== T_MNEM_stmia
11406 ? inst
.operands
[0].writeback
11407 : (inst
.operands
[0].writeback
11408 == !(inst
.operands
[1].imm
& mask
)))
11410 if (inst
.instruction
== T_MNEM_stmia
11411 && (inst
.operands
[1].imm
& mask
)
11412 && (inst
.operands
[1].imm
& (mask
- 1)))
11413 as_warn (_("value stored for r%d is UNKNOWN"),
11414 inst
.operands
[0].reg
);
11416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11417 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11418 inst
.instruction
|= inst
.operands
[1].imm
;
11421 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11423 /* This means 1 register in reg list one of 3 situations:
11424 1. Instruction is stmia, but without writeback.
11425 2. lmdia without writeback, but with Rn not in
11427 3. ldmia with writeback, but with Rn in reglist.
11428 Case 3 is UNPREDICTABLE behaviour, so we handle
11429 case 1 and 2 which can be converted into a 16-bit
11430 str or ldr. The SP cases are handled below. */
11431 unsigned long opcode
;
11432 /* First, record an error for Case 3. */
11433 if (inst
.operands
[1].imm
& mask
11434 && inst
.operands
[0].writeback
)
11436 _("having the base register in the register list when "
11437 "using write back is UNPREDICTABLE");
11439 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11441 inst
.instruction
= THUMB_OP16 (opcode
);
11442 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11443 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11447 else if (inst
.operands
[0] .reg
== REG_SP
)
11449 if (inst
.operands
[0].writeback
)
11452 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11453 ? T_MNEM_push
: T_MNEM_pop
);
11454 inst
.instruction
|= inst
.operands
[1].imm
;
11457 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11460 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11461 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11462 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11470 if (inst
.instruction
< 0xffff)
11471 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11473 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11474 inst
.operands
[0].writeback
);
11479 constraint (inst
.operands
[0].reg
> 7
11480 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11481 constraint (inst
.instruction
!= T_MNEM_ldmia
11482 && inst
.instruction
!= T_MNEM_stmia
,
11483 _("Thumb-2 instruction only valid in unified syntax"));
11484 if (inst
.instruction
== T_MNEM_stmia
)
11486 if (!inst
.operands
[0].writeback
)
11487 as_warn (_("this instruction will write back the base register"));
11488 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11489 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11490 as_warn (_("value stored for r%d is UNKNOWN"),
11491 inst
.operands
[0].reg
);
11495 if (!inst
.operands
[0].writeback
11496 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11497 as_warn (_("this instruction will write back the base register"));
11498 else if (inst
.operands
[0].writeback
11499 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11500 as_warn (_("this instruction will not write back the base register"));
11503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11504 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11505 inst
.instruction
|= inst
.operands
[1].imm
;
11512 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11513 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11514 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11515 || inst
.operands
[1].negative
,
11518 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11521 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11522 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11528 if (!inst
.operands
[1].present
)
11530 constraint (inst
.operands
[0].reg
== REG_LR
,
11531 _("r14 not allowed as first register "
11532 "when second register is omitted"));
11533 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11535 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11539 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11540 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11546 unsigned long opcode
;
11549 if (inst
.operands
[0].isreg
11550 && !inst
.operands
[0].preind
11551 && inst
.operands
[0].reg
== REG_PC
)
11552 set_it_insn_type_last ();
11554 opcode
= inst
.instruction
;
11555 if (unified_syntax
)
11557 if (!inst
.operands
[1].isreg
)
11559 if (opcode
<= 0xffff)
11560 inst
.instruction
= THUMB_OP32 (opcode
);
11561 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11564 if (inst
.operands
[1].isreg
11565 && !inst
.operands
[1].writeback
11566 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11567 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11568 && opcode
<= 0xffff
11569 && inst
.size_req
!= 4)
11571 /* Insn may have a 16-bit form. */
11572 Rn
= inst
.operands
[1].reg
;
11573 if (inst
.operands
[1].immisreg
)
11575 inst
.instruction
= THUMB_OP16 (opcode
);
11577 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11579 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11580 reject_bad_reg (inst
.operands
[1].imm
);
11582 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11583 && opcode
!= T_MNEM_ldrsb
)
11584 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11585 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11592 if (inst
.reloc
.pc_rel
)
11593 opcode
= T_MNEM_ldr_pc2
;
11595 opcode
= T_MNEM_ldr_pc
;
11599 if (opcode
== T_MNEM_ldr
)
11600 opcode
= T_MNEM_ldr_sp
;
11602 opcode
= T_MNEM_str_sp
;
11604 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11608 inst
.instruction
= inst
.operands
[0].reg
;
11609 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11611 inst
.instruction
|= THUMB_OP16 (opcode
);
11612 if (inst
.size_req
== 2)
11613 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11615 inst
.relax
= opcode
;
11619 /* Definitely a 32-bit variant. */
11621 /* Warning for Erratum 752419. */
11622 if (opcode
== T_MNEM_ldr
11623 && inst
.operands
[0].reg
== REG_SP
11624 && inst
.operands
[1].writeback
== 1
11625 && !inst
.operands
[1].immisreg
)
11627 if (no_cpu_selected ()
11628 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11629 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11630 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11631 as_warn (_("This instruction may be unpredictable "
11632 "if executed on M-profile cores "
11633 "with interrupts enabled."));
11636 /* Do some validations regarding addressing modes. */
11637 if (inst
.operands
[1].immisreg
)
11638 reject_bad_reg (inst
.operands
[1].imm
);
11640 constraint (inst
.operands
[1].writeback
== 1
11641 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11644 inst
.instruction
= THUMB_OP32 (opcode
);
11645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11646 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11647 check_ldr_r15_aligned ();
11651 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11653 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11655 /* Only [Rn,Rm] is acceptable. */
11656 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11657 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11658 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11659 || inst
.operands
[1].negative
,
11660 _("Thumb does not support this addressing mode"));
11661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11666 if (!inst
.operands
[1].isreg
)
11667 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11670 constraint (!inst
.operands
[1].preind
11671 || inst
.operands
[1].shifted
11672 || inst
.operands
[1].writeback
,
11673 _("Thumb does not support this addressing mode"));
11674 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11676 constraint (inst
.instruction
& 0x0600,
11677 _("byte or halfword not valid for base register"));
11678 constraint (inst
.operands
[1].reg
== REG_PC
11679 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11680 _("r15 based store not allowed"));
11681 constraint (inst
.operands
[1].immisreg
,
11682 _("invalid base register for register offset"));
11684 if (inst
.operands
[1].reg
== REG_PC
)
11685 inst
.instruction
= T_OPCODE_LDR_PC
;
11686 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11687 inst
.instruction
= T_OPCODE_LDR_SP
;
11689 inst
.instruction
= T_OPCODE_STR_SP
;
11691 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11692 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11696 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11697 if (!inst
.operands
[1].immisreg
)
11699 /* Immediate offset. */
11700 inst
.instruction
|= inst
.operands
[0].reg
;
11701 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11702 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11706 /* Register offset. */
11707 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11708 constraint (inst
.operands
[1].negative
,
11709 _("Thumb does not support this addressing mode"));
11712 switch (inst
.instruction
)
11714 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11715 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11716 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11717 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11718 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11719 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11720 case 0x5600 /* ldrsb */:
11721 case 0x5e00 /* ldrsh */: break;
11725 inst
.instruction
|= inst
.operands
[0].reg
;
11726 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11727 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11733 if (!inst
.operands
[1].present
)
11735 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11736 constraint (inst
.operands
[0].reg
== REG_LR
,
11737 _("r14 not allowed here"));
11738 constraint (inst
.operands
[0].reg
== REG_R12
,
11739 _("r12 not allowed here"));
11742 if (inst
.operands
[2].writeback
11743 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11744 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11745 as_warn (_("base register written back, and overlaps "
11746 "one of transfer registers"));
11748 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11749 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11750 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11756 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11757 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11763 unsigned Rd
, Rn
, Rm
, Ra
;
11765 Rd
= inst
.operands
[0].reg
;
11766 Rn
= inst
.operands
[1].reg
;
11767 Rm
= inst
.operands
[2].reg
;
11768 Ra
= inst
.operands
[3].reg
;
11770 reject_bad_reg (Rd
);
11771 reject_bad_reg (Rn
);
11772 reject_bad_reg (Rm
);
11773 reject_bad_reg (Ra
);
11775 inst
.instruction
|= Rd
<< 8;
11776 inst
.instruction
|= Rn
<< 16;
11777 inst
.instruction
|= Rm
;
11778 inst
.instruction
|= Ra
<< 12;
11784 unsigned RdLo
, RdHi
, Rn
, Rm
;
11786 RdLo
= inst
.operands
[0].reg
;
11787 RdHi
= inst
.operands
[1].reg
;
11788 Rn
= inst
.operands
[2].reg
;
11789 Rm
= inst
.operands
[3].reg
;
11791 reject_bad_reg (RdLo
);
11792 reject_bad_reg (RdHi
);
11793 reject_bad_reg (Rn
);
11794 reject_bad_reg (Rm
);
11796 inst
.instruction
|= RdLo
<< 12;
11797 inst
.instruction
|= RdHi
<< 8;
11798 inst
.instruction
|= Rn
<< 16;
11799 inst
.instruction
|= Rm
;
11803 do_t_mov_cmp (void)
11807 Rn
= inst
.operands
[0].reg
;
11808 Rm
= inst
.operands
[1].reg
;
11811 set_it_insn_type_last ();
11813 if (unified_syntax
)
11815 int r0off
= (inst
.instruction
== T_MNEM_mov
11816 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11817 unsigned long opcode
;
11818 bfd_boolean narrow
;
11819 bfd_boolean low_regs
;
11821 low_regs
= (Rn
<= 7 && Rm
<= 7);
11822 opcode
= inst
.instruction
;
11823 if (in_it_block ())
11824 narrow
= opcode
!= T_MNEM_movs
;
11826 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11827 if (inst
.size_req
== 4
11828 || inst
.operands
[1].shifted
)
11831 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11832 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11833 && !inst
.operands
[1].shifted
11837 inst
.instruction
= T2_SUBS_PC_LR
;
11841 if (opcode
== T_MNEM_cmp
)
11843 constraint (Rn
== REG_PC
, BAD_PC
);
11846 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11848 warn_deprecated_sp (Rm
);
11849 /* R15 was documented as a valid choice for Rm in ARMv6,
11850 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11851 tools reject R15, so we do too. */
11852 constraint (Rm
== REG_PC
, BAD_PC
);
11855 reject_bad_reg (Rm
);
11857 else if (opcode
== T_MNEM_mov
11858 || opcode
== T_MNEM_movs
)
11860 if (inst
.operands
[1].isreg
)
11862 if (opcode
== T_MNEM_movs
)
11864 reject_bad_reg (Rn
);
11865 reject_bad_reg (Rm
);
11869 /* This is mov.n. */
11870 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11871 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11873 as_tsktsk (_("Use of r%u as a source register is "
11874 "deprecated when r%u is the destination "
11875 "register."), Rm
, Rn
);
11880 /* This is mov.w. */
11881 constraint (Rn
== REG_PC
, BAD_PC
);
11882 constraint (Rm
== REG_PC
, BAD_PC
);
11883 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11887 reject_bad_reg (Rn
);
11890 if (!inst
.operands
[1].isreg
)
11892 /* Immediate operand. */
11893 if (!in_it_block () && opcode
== T_MNEM_mov
)
11895 if (low_regs
&& narrow
)
11897 inst
.instruction
= THUMB_OP16 (opcode
);
11898 inst
.instruction
|= Rn
<< 8;
11899 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11900 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11902 if (inst
.size_req
== 2)
11903 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11905 inst
.relax
= opcode
;
11910 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11911 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11912 THUMB1_RELOC_ONLY
);
11914 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11915 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11916 inst
.instruction
|= Rn
<< r0off
;
11917 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11920 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11921 && (inst
.instruction
== T_MNEM_mov
11922 || inst
.instruction
== T_MNEM_movs
))
11924 /* Register shifts are encoded as separate shift instructions. */
11925 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11927 if (in_it_block ())
11932 if (inst
.size_req
== 4)
11935 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11941 switch (inst
.operands
[1].shift_kind
)
11944 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11947 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11950 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11953 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11959 inst
.instruction
= opcode
;
11962 inst
.instruction
|= Rn
;
11963 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11968 inst
.instruction
|= CONDS_BIT
;
11970 inst
.instruction
|= Rn
<< 8;
11971 inst
.instruction
|= Rm
<< 16;
11972 inst
.instruction
|= inst
.operands
[1].imm
;
11977 /* Some mov with immediate shift have narrow variants.
11978 Register shifts are handled above. */
11979 if (low_regs
&& inst
.operands
[1].shifted
11980 && (inst
.instruction
== T_MNEM_mov
11981 || inst
.instruction
== T_MNEM_movs
))
11983 if (in_it_block ())
11984 narrow
= (inst
.instruction
== T_MNEM_mov
);
11986 narrow
= (inst
.instruction
== T_MNEM_movs
);
11991 switch (inst
.operands
[1].shift_kind
)
11993 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11994 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11995 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11996 default: narrow
= FALSE
; break;
12002 inst
.instruction
|= Rn
;
12003 inst
.instruction
|= Rm
<< 3;
12004 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12008 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12009 inst
.instruction
|= Rn
<< r0off
;
12010 encode_thumb32_shifted_operand (1);
12014 switch (inst
.instruction
)
12017 /* In v4t or v5t a move of two lowregs produces unpredictable
12018 results. Don't allow this. */
12021 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12022 "MOV Rd, Rs with two low registers is not "
12023 "permitted on this architecture");
12024 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12028 inst
.instruction
= T_OPCODE_MOV_HR
;
12029 inst
.instruction
|= (Rn
& 0x8) << 4;
12030 inst
.instruction
|= (Rn
& 0x7);
12031 inst
.instruction
|= Rm
<< 3;
12035 /* We know we have low registers at this point.
12036 Generate LSLS Rd, Rs, #0. */
12037 inst
.instruction
= T_OPCODE_LSL_I
;
12038 inst
.instruction
|= Rn
;
12039 inst
.instruction
|= Rm
<< 3;
12045 inst
.instruction
= T_OPCODE_CMP_LR
;
12046 inst
.instruction
|= Rn
;
12047 inst
.instruction
|= Rm
<< 3;
12051 inst
.instruction
= T_OPCODE_CMP_HR
;
12052 inst
.instruction
|= (Rn
& 0x8) << 4;
12053 inst
.instruction
|= (Rn
& 0x7);
12054 inst
.instruction
|= Rm
<< 3;
12061 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12063 /* PR 10443: Do not silently ignore shifted operands. */
12064 constraint (inst
.operands
[1].shifted
,
12065 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12067 if (inst
.operands
[1].isreg
)
12069 if (Rn
< 8 && Rm
< 8)
12071 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12072 since a MOV instruction produces unpredictable results. */
12073 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12074 inst
.instruction
= T_OPCODE_ADD_I3
;
12076 inst
.instruction
= T_OPCODE_CMP_LR
;
12078 inst
.instruction
|= Rn
;
12079 inst
.instruction
|= Rm
<< 3;
12083 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12084 inst
.instruction
= T_OPCODE_MOV_HR
;
12086 inst
.instruction
= T_OPCODE_CMP_HR
;
12092 constraint (Rn
> 7,
12093 _("only lo regs allowed with immediate"));
12094 inst
.instruction
|= Rn
<< 8;
12095 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12106 top
= (inst
.instruction
& 0x00800000) != 0;
12107 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12109 constraint (top
, _(":lower16: not allowed this instruction"));
12110 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12112 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12114 constraint (!top
, _(":upper16: not allowed this instruction"));
12115 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12118 Rd
= inst
.operands
[0].reg
;
12119 reject_bad_reg (Rd
);
12121 inst
.instruction
|= Rd
<< 8;
12122 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12124 imm
= inst
.reloc
.exp
.X_add_number
;
12125 inst
.instruction
|= (imm
& 0xf000) << 4;
12126 inst
.instruction
|= (imm
& 0x0800) << 15;
12127 inst
.instruction
|= (imm
& 0x0700) << 4;
12128 inst
.instruction
|= (imm
& 0x00ff);
12133 do_t_mvn_tst (void)
12137 Rn
= inst
.operands
[0].reg
;
12138 Rm
= inst
.operands
[1].reg
;
12140 if (inst
.instruction
== T_MNEM_cmp
12141 || inst
.instruction
== T_MNEM_cmn
)
12142 constraint (Rn
== REG_PC
, BAD_PC
);
12144 reject_bad_reg (Rn
);
12145 reject_bad_reg (Rm
);
12147 if (unified_syntax
)
12149 int r0off
= (inst
.instruction
== T_MNEM_mvn
12150 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12151 bfd_boolean narrow
;
12153 if (inst
.size_req
== 4
12154 || inst
.instruction
> 0xffff
12155 || inst
.operands
[1].shifted
12156 || Rn
> 7 || Rm
> 7)
12158 else if (inst
.instruction
== T_MNEM_cmn
12159 || inst
.instruction
== T_MNEM_tst
)
12161 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12162 narrow
= !in_it_block ();
12164 narrow
= in_it_block ();
12166 if (!inst
.operands
[1].isreg
)
12168 /* For an immediate, we always generate a 32-bit opcode;
12169 section relaxation will shrink it later if possible. */
12170 if (inst
.instruction
< 0xffff)
12171 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12172 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12173 inst
.instruction
|= Rn
<< r0off
;
12174 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12178 /* See if we can do this with a 16-bit instruction. */
12181 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12182 inst
.instruction
|= Rn
;
12183 inst
.instruction
|= Rm
<< 3;
12187 constraint (inst
.operands
[1].shifted
12188 && inst
.operands
[1].immisreg
,
12189 _("shift must be constant"));
12190 if (inst
.instruction
< 0xffff)
12191 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12192 inst
.instruction
|= Rn
<< r0off
;
12193 encode_thumb32_shifted_operand (1);
12199 constraint (inst
.instruction
> 0xffff
12200 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12201 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12202 _("unshifted register required"));
12203 constraint (Rn
> 7 || Rm
> 7,
12206 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12207 inst
.instruction
|= Rn
;
12208 inst
.instruction
|= Rm
<< 3;
12217 if (do_vfp_nsyn_mrs () == SUCCESS
)
12220 Rd
= inst
.operands
[0].reg
;
12221 reject_bad_reg (Rd
);
12222 inst
.instruction
|= Rd
<< 8;
12224 if (inst
.operands
[1].isreg
)
12226 unsigned br
= inst
.operands
[1].reg
;
12227 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12228 as_bad (_("bad register for mrs"));
12230 inst
.instruction
|= br
& (0xf << 16);
12231 inst
.instruction
|= (br
& 0x300) >> 4;
12232 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12236 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12238 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12240 /* PR gas/12698: The constraint is only applied for m_profile.
12241 If the user has specified -march=all, we want to ignore it as
12242 we are building for any CPU type, including non-m variants. */
12243 bfd_boolean m_profile
=
12244 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12245 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12246 "not support requested special purpose register"));
12249 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12251 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12252 _("'APSR', 'CPSR' or 'SPSR' expected"));
12254 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12255 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12256 inst
.instruction
|= 0xf0000;
12266 if (do_vfp_nsyn_msr () == SUCCESS
)
12269 constraint (!inst
.operands
[1].isreg
,
12270 _("Thumb encoding does not support an immediate here"));
12272 if (inst
.operands
[0].isreg
)
12273 flags
= (int)(inst
.operands
[0].reg
);
12275 flags
= inst
.operands
[0].imm
;
12277 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12279 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12281 /* PR gas/12698: The constraint is only applied for m_profile.
12282 If the user has specified -march=all, we want to ignore it as
12283 we are building for any CPU type, including non-m variants. */
12284 bfd_boolean m_profile
=
12285 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12286 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12287 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12288 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12289 && bits
!= PSR_f
)) && m_profile
,
12290 _("selected processor does not support requested special "
12291 "purpose register"));
12294 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12295 "requested special purpose register"));
12297 Rn
= inst
.operands
[1].reg
;
12298 reject_bad_reg (Rn
);
12300 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12301 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12302 inst
.instruction
|= (flags
& 0x300) >> 4;
12303 inst
.instruction
|= (flags
& 0xff);
12304 inst
.instruction
|= Rn
<< 16;
12310 bfd_boolean narrow
;
12311 unsigned Rd
, Rn
, Rm
;
12313 if (!inst
.operands
[2].present
)
12314 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12316 Rd
= inst
.operands
[0].reg
;
12317 Rn
= inst
.operands
[1].reg
;
12318 Rm
= inst
.operands
[2].reg
;
12320 if (unified_syntax
)
12322 if (inst
.size_req
== 4
12328 else if (inst
.instruction
== T_MNEM_muls
)
12329 narrow
= !in_it_block ();
12331 narrow
= in_it_block ();
12335 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12336 constraint (Rn
> 7 || Rm
> 7,
12343 /* 16-bit MULS/Conditional MUL. */
12344 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12345 inst
.instruction
|= Rd
;
12348 inst
.instruction
|= Rm
<< 3;
12350 inst
.instruction
|= Rn
<< 3;
12352 constraint (1, _("dest must overlap one source register"));
12356 constraint (inst
.instruction
!= T_MNEM_mul
,
12357 _("Thumb-2 MUL must not set flags"));
12359 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12360 inst
.instruction
|= Rd
<< 8;
12361 inst
.instruction
|= Rn
<< 16;
12362 inst
.instruction
|= Rm
<< 0;
12364 reject_bad_reg (Rd
);
12365 reject_bad_reg (Rn
);
12366 reject_bad_reg (Rm
);
12373 unsigned RdLo
, RdHi
, Rn
, Rm
;
12375 RdLo
= inst
.operands
[0].reg
;
12376 RdHi
= inst
.operands
[1].reg
;
12377 Rn
= inst
.operands
[2].reg
;
12378 Rm
= inst
.operands
[3].reg
;
12380 reject_bad_reg (RdLo
);
12381 reject_bad_reg (RdHi
);
12382 reject_bad_reg (Rn
);
12383 reject_bad_reg (Rm
);
12385 inst
.instruction
|= RdLo
<< 12;
12386 inst
.instruction
|= RdHi
<< 8;
12387 inst
.instruction
|= Rn
<< 16;
12388 inst
.instruction
|= Rm
;
12391 as_tsktsk (_("rdhi and rdlo must be different"));
12397 set_it_insn_type (NEUTRAL_IT_INSN
);
12399 if (unified_syntax
)
12401 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12403 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12404 inst
.instruction
|= inst
.operands
[0].imm
;
12408 /* PR9722: Check for Thumb2 availability before
12409 generating a thumb2 nop instruction. */
12410 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12412 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12413 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12416 inst
.instruction
= 0x46c0;
12421 constraint (inst
.operands
[0].present
,
12422 _("Thumb does not support NOP with hints"));
12423 inst
.instruction
= 0x46c0;
12430 if (unified_syntax
)
12432 bfd_boolean narrow
;
12434 if (THUMB_SETS_FLAGS (inst
.instruction
))
12435 narrow
= !in_it_block ();
12437 narrow
= in_it_block ();
12438 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12440 if (inst
.size_req
== 4)
12445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12446 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12447 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12451 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12452 inst
.instruction
|= inst
.operands
[0].reg
;
12453 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12458 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12460 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12462 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12463 inst
.instruction
|= inst
.operands
[0].reg
;
12464 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12473 Rd
= inst
.operands
[0].reg
;
12474 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12476 reject_bad_reg (Rd
);
12477 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12478 reject_bad_reg (Rn
);
12480 inst
.instruction
|= Rd
<< 8;
12481 inst
.instruction
|= Rn
<< 16;
12483 if (!inst
.operands
[2].isreg
)
12485 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12486 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12492 Rm
= inst
.operands
[2].reg
;
12493 reject_bad_reg (Rm
);
12495 constraint (inst
.operands
[2].shifted
12496 && inst
.operands
[2].immisreg
,
12497 _("shift must be constant"));
12498 encode_thumb32_shifted_operand (2);
12505 unsigned Rd
, Rn
, Rm
;
12507 Rd
= inst
.operands
[0].reg
;
12508 Rn
= inst
.operands
[1].reg
;
12509 Rm
= inst
.operands
[2].reg
;
12511 reject_bad_reg (Rd
);
12512 reject_bad_reg (Rn
);
12513 reject_bad_reg (Rm
);
12515 inst
.instruction
|= Rd
<< 8;
12516 inst
.instruction
|= Rn
<< 16;
12517 inst
.instruction
|= Rm
;
12518 if (inst
.operands
[3].present
)
12520 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12521 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12522 _("expression too complex"));
12523 inst
.instruction
|= (val
& 0x1c) << 10;
12524 inst
.instruction
|= (val
& 0x03) << 6;
12531 if (!inst
.operands
[3].present
)
12535 inst
.instruction
&= ~0x00000020;
12537 /* PR 10168. Swap the Rm and Rn registers. */
12538 Rtmp
= inst
.operands
[1].reg
;
12539 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12540 inst
.operands
[2].reg
= Rtmp
;
12548 if (inst
.operands
[0].immisreg
)
12549 reject_bad_reg (inst
.operands
[0].imm
);
12551 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12555 do_t_push_pop (void)
12559 constraint (inst
.operands
[0].writeback
,
12560 _("push/pop do not support {reglist}^"));
12561 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12562 _("expression too complex"));
12564 mask
= inst
.operands
[0].imm
;
12565 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12566 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12567 else if (inst
.size_req
!= 4
12568 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12569 ? REG_LR
: REG_PC
)))
12571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12572 inst
.instruction
|= THUMB_PP_PC_LR
;
12573 inst
.instruction
|= mask
& 0xff;
12575 else if (unified_syntax
)
12577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12578 encode_thumb2_ldmstm (13, mask
, TRUE
);
12582 inst
.error
= _("invalid register list to push/pop instruction");
12592 Rd
= inst
.operands
[0].reg
;
12593 Rm
= inst
.operands
[1].reg
;
12595 reject_bad_reg (Rd
);
12596 reject_bad_reg (Rm
);
12598 inst
.instruction
|= Rd
<< 8;
12599 inst
.instruction
|= Rm
<< 16;
12600 inst
.instruction
|= Rm
;
12608 Rd
= inst
.operands
[0].reg
;
12609 Rm
= inst
.operands
[1].reg
;
12611 reject_bad_reg (Rd
);
12612 reject_bad_reg (Rm
);
12614 if (Rd
<= 7 && Rm
<= 7
12615 && inst
.size_req
!= 4)
12617 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12618 inst
.instruction
|= Rd
;
12619 inst
.instruction
|= Rm
<< 3;
12621 else if (unified_syntax
)
12623 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12624 inst
.instruction
|= Rd
<< 8;
12625 inst
.instruction
|= Rm
<< 16;
12626 inst
.instruction
|= Rm
;
12629 inst
.error
= BAD_HIREG
;
12637 Rd
= inst
.operands
[0].reg
;
12638 Rm
= inst
.operands
[1].reg
;
12640 reject_bad_reg (Rd
);
12641 reject_bad_reg (Rm
);
12643 inst
.instruction
|= Rd
<< 8;
12644 inst
.instruction
|= Rm
;
12652 Rd
= inst
.operands
[0].reg
;
12653 Rs
= (inst
.operands
[1].present
12654 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12655 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12657 reject_bad_reg (Rd
);
12658 reject_bad_reg (Rs
);
12659 if (inst
.operands
[2].isreg
)
12660 reject_bad_reg (inst
.operands
[2].reg
);
12662 inst
.instruction
|= Rd
<< 8;
12663 inst
.instruction
|= Rs
<< 16;
12664 if (!inst
.operands
[2].isreg
)
12666 bfd_boolean narrow
;
12668 if ((inst
.instruction
& 0x00100000) != 0)
12669 narrow
= !in_it_block ();
12671 narrow
= in_it_block ();
12673 if (Rd
> 7 || Rs
> 7)
12676 if (inst
.size_req
== 4 || !unified_syntax
)
12679 if (inst
.reloc
.exp
.X_op
!= O_constant
12680 || inst
.reloc
.exp
.X_add_number
!= 0)
12683 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12684 relaxation, but it doesn't seem worth the hassle. */
12687 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12688 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12689 inst
.instruction
|= Rs
<< 3;
12690 inst
.instruction
|= Rd
;
12694 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12695 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12699 encode_thumb32_shifted_operand (2);
12705 if (warn_on_deprecated
12706 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12707 as_tsktsk (_("setend use is deprecated for ARMv8"));
12709 set_it_insn_type (OUTSIDE_IT_INSN
);
12710 if (inst
.operands
[0].imm
)
12711 inst
.instruction
|= 0x8;
12717 if (!inst
.operands
[1].present
)
12718 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12720 if (unified_syntax
)
12722 bfd_boolean narrow
;
12725 switch (inst
.instruction
)
12728 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12730 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12732 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12734 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12738 if (THUMB_SETS_FLAGS (inst
.instruction
))
12739 narrow
= !in_it_block ();
12741 narrow
= in_it_block ();
12742 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12744 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12746 if (inst
.operands
[2].isreg
12747 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12748 || inst
.operands
[2].reg
> 7))
12750 if (inst
.size_req
== 4)
12753 reject_bad_reg (inst
.operands
[0].reg
);
12754 reject_bad_reg (inst
.operands
[1].reg
);
12758 if (inst
.operands
[2].isreg
)
12760 reject_bad_reg (inst
.operands
[2].reg
);
12761 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12762 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12763 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12764 inst
.instruction
|= inst
.operands
[2].reg
;
12766 /* PR 12854: Error on extraneous shifts. */
12767 constraint (inst
.operands
[2].shifted
,
12768 _("extraneous shift as part of operand to shift insn"));
12772 inst
.operands
[1].shifted
= 1;
12773 inst
.operands
[1].shift_kind
= shift_kind
;
12774 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12775 ? T_MNEM_movs
: T_MNEM_mov
);
12776 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12777 encode_thumb32_shifted_operand (1);
12778 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12779 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12784 if (inst
.operands
[2].isreg
)
12786 switch (shift_kind
)
12788 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12789 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12790 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12791 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12795 inst
.instruction
|= inst
.operands
[0].reg
;
12796 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12798 /* PR 12854: Error on extraneous shifts. */
12799 constraint (inst
.operands
[2].shifted
,
12800 _("extraneous shift as part of operand to shift insn"));
12804 switch (shift_kind
)
12806 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12807 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12808 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12811 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12812 inst
.instruction
|= inst
.operands
[0].reg
;
12813 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12819 constraint (inst
.operands
[0].reg
> 7
12820 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12821 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12823 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12825 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12826 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12827 _("source1 and dest must be same register"));
12829 switch (inst
.instruction
)
12831 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12832 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12833 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12834 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12838 inst
.instruction
|= inst
.operands
[0].reg
;
12839 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12841 /* PR 12854: Error on extraneous shifts. */
12842 constraint (inst
.operands
[2].shifted
,
12843 _("extraneous shift as part of operand to shift insn"));
12847 switch (inst
.instruction
)
12849 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12850 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12851 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12852 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12855 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12856 inst
.instruction
|= inst
.operands
[0].reg
;
12857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12865 unsigned Rd
, Rn
, Rm
;
12867 Rd
= inst
.operands
[0].reg
;
12868 Rn
= inst
.operands
[1].reg
;
12869 Rm
= inst
.operands
[2].reg
;
12871 reject_bad_reg (Rd
);
12872 reject_bad_reg (Rn
);
12873 reject_bad_reg (Rm
);
12875 inst
.instruction
|= Rd
<< 8;
12876 inst
.instruction
|= Rn
<< 16;
12877 inst
.instruction
|= Rm
;
12883 unsigned Rd
, Rn
, Rm
;
12885 Rd
= inst
.operands
[0].reg
;
12886 Rm
= inst
.operands
[1].reg
;
12887 Rn
= inst
.operands
[2].reg
;
12889 reject_bad_reg (Rd
);
12890 reject_bad_reg (Rn
);
12891 reject_bad_reg (Rm
);
12893 inst
.instruction
|= Rd
<< 8;
12894 inst
.instruction
|= Rn
<< 16;
12895 inst
.instruction
|= Rm
;
12901 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12902 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12903 _("SMC is not permitted on this architecture"));
12904 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12905 _("expression too complex"));
12906 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12907 inst
.instruction
|= (value
& 0xf000) >> 12;
12908 inst
.instruction
|= (value
& 0x0ff0);
12909 inst
.instruction
|= (value
& 0x000f) << 16;
12910 /* PR gas/15623: SMC instructions must be last in an IT block. */
12911 set_it_insn_type_last ();
12917 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12919 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12920 inst
.instruction
|= (value
& 0x0fff);
12921 inst
.instruction
|= (value
& 0xf000) << 4;
12925 do_t_ssat_usat (int bias
)
12929 Rd
= inst
.operands
[0].reg
;
12930 Rn
= inst
.operands
[2].reg
;
12932 reject_bad_reg (Rd
);
12933 reject_bad_reg (Rn
);
12935 inst
.instruction
|= Rd
<< 8;
12936 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12937 inst
.instruction
|= Rn
<< 16;
12939 if (inst
.operands
[3].present
)
12941 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12943 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12945 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12946 _("expression too complex"));
12948 if (shift_amount
!= 0)
12950 constraint (shift_amount
> 31,
12951 _("shift expression is too large"));
12953 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12954 inst
.instruction
|= 0x00200000; /* sh bit. */
12956 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12957 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12965 do_t_ssat_usat (1);
12973 Rd
= inst
.operands
[0].reg
;
12974 Rn
= inst
.operands
[2].reg
;
12976 reject_bad_reg (Rd
);
12977 reject_bad_reg (Rn
);
12979 inst
.instruction
|= Rd
<< 8;
12980 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12981 inst
.instruction
|= Rn
<< 16;
12987 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12988 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12989 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12990 || inst
.operands
[2].negative
,
12993 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12995 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12996 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12997 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12998 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13004 if (!inst
.operands
[2].present
)
13005 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13007 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13008 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13009 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13012 inst
.instruction
|= inst
.operands
[0].reg
;
13013 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13014 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13015 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13021 unsigned Rd
, Rn
, Rm
;
13023 Rd
= inst
.operands
[0].reg
;
13024 Rn
= inst
.operands
[1].reg
;
13025 Rm
= inst
.operands
[2].reg
;
13027 reject_bad_reg (Rd
);
13028 reject_bad_reg (Rn
);
13029 reject_bad_reg (Rm
);
13031 inst
.instruction
|= Rd
<< 8;
13032 inst
.instruction
|= Rn
<< 16;
13033 inst
.instruction
|= Rm
;
13034 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13042 Rd
= inst
.operands
[0].reg
;
13043 Rm
= inst
.operands
[1].reg
;
13045 reject_bad_reg (Rd
);
13046 reject_bad_reg (Rm
);
13048 if (inst
.instruction
<= 0xffff
13049 && inst
.size_req
!= 4
13050 && Rd
<= 7 && Rm
<= 7
13051 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13053 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13054 inst
.instruction
|= Rd
;
13055 inst
.instruction
|= Rm
<< 3;
13057 else if (unified_syntax
)
13059 if (inst
.instruction
<= 0xffff)
13060 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13061 inst
.instruction
|= Rd
<< 8;
13062 inst
.instruction
|= Rm
;
13063 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13067 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13068 _("Thumb encoding does not support rotation"));
13069 constraint (1, BAD_HIREG
);
13076 /* We have to do the following check manually as ARM_EXT_OS only applies
13078 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13080 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13081 /* This only applies to the v6m howver, not later architectures. */
13082 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13083 as_bad (_("SVC is not permitted on this architecture"));
13084 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13087 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13096 half
= (inst
.instruction
& 0x10) != 0;
13097 set_it_insn_type_last ();
13098 constraint (inst
.operands
[0].immisreg
,
13099 _("instruction requires register index"));
13101 Rn
= inst
.operands
[0].reg
;
13102 Rm
= inst
.operands
[0].imm
;
13104 constraint (Rn
== REG_SP
, BAD_SP
);
13105 reject_bad_reg (Rm
);
13107 constraint (!half
&& inst
.operands
[0].shifted
,
13108 _("instruction does not allow shifted index"));
13109 inst
.instruction
|= (Rn
<< 16) | Rm
;
13115 if (!inst
.operands
[0].present
)
13116 inst
.operands
[0].imm
= 0;
13118 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13120 constraint (inst
.size_req
== 2,
13121 _("immediate value out of range"));
13122 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13123 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13124 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13128 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13129 inst
.instruction
|= inst
.operands
[0].imm
;
13132 set_it_insn_type (NEUTRAL_IT_INSN
);
13139 do_t_ssat_usat (0);
13147 Rd
= inst
.operands
[0].reg
;
13148 Rn
= inst
.operands
[2].reg
;
13150 reject_bad_reg (Rd
);
13151 reject_bad_reg (Rn
);
13153 inst
.instruction
|= Rd
<< 8;
13154 inst
.instruction
|= inst
.operands
[1].imm
;
13155 inst
.instruction
|= Rn
<< 16;
13158 /* Neon instruction encoder helpers. */
13160 /* Encodings for the different types for various Neon opcodes. */
13162 /* An "invalid" code for the following tables. */
13165 struct neon_tab_entry
13168 unsigned float_or_poly
;
13169 unsigned scalar_or_imm
;
13172 /* Map overloaded Neon opcodes to their respective encodings. */
13173 #define NEON_ENC_TAB \
13174 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13175 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13176 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13177 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13178 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13179 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13180 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13181 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13182 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13183 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13184 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13185 /* Register variants of the following two instructions are encoded as
13186 vcge / vcgt with the operands reversed. */ \
13187 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13188 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13189 X(vfma, N_INV, 0x0000c10, N_INV), \
13190 X(vfms, N_INV, 0x0200c10, N_INV), \
13191 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13192 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13193 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13194 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13195 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13196 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13197 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13198 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13199 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13200 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13201 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13202 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13203 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13204 X(vshl, 0x0000400, N_INV, 0x0800510), \
13205 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13206 X(vand, 0x0000110, N_INV, 0x0800030), \
13207 X(vbic, 0x0100110, N_INV, 0x0800030), \
13208 X(veor, 0x1000110, N_INV, N_INV), \
13209 X(vorn, 0x0300110, N_INV, 0x0800010), \
13210 X(vorr, 0x0200110, N_INV, 0x0800010), \
13211 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13212 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13213 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13214 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13215 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13216 X(vst1, 0x0000000, 0x0800000, N_INV), \
13217 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13218 X(vst2, 0x0000100, 0x0800100, N_INV), \
13219 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13220 X(vst3, 0x0000200, 0x0800200, N_INV), \
13221 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13222 X(vst4, 0x0000300, 0x0800300, N_INV), \
13223 X(vmovn, 0x1b20200, N_INV, N_INV), \
13224 X(vtrn, 0x1b20080, N_INV, N_INV), \
13225 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13226 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13227 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13228 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13229 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13230 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13231 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13232 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13233 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13234 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13235 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13236 X(vseleq, 0xe000a00, N_INV, N_INV), \
13237 X(vselvs, 0xe100a00, N_INV, N_INV), \
13238 X(vselge, 0xe200a00, N_INV, N_INV), \
13239 X(vselgt, 0xe300a00, N_INV, N_INV), \
13240 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13241 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13242 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13243 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13244 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13245 X(aes, 0x3b00300, N_INV, N_INV), \
13246 X(sha3op, 0x2000c00, N_INV, N_INV), \
13247 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13248 X(sha2op, 0x3ba0380, N_INV, N_INV)
13252 #define X(OPC,I,F,S) N_MNEM_##OPC
13257 static const struct neon_tab_entry neon_enc_tab
[] =
13259 #define X(OPC,I,F,S) { (I), (F), (S) }
13264 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13265 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13266 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13267 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13268 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13269 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13270 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13271 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13272 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13273 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13274 #define NEON_ENC_SINGLE_(X) \
13275 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13276 #define NEON_ENC_DOUBLE_(X) \
13277 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13278 #define NEON_ENC_FPV8_(X) \
13279 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13281 #define NEON_ENCODE(type, inst) \
13284 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13285 inst.is_neon = 1; \
13289 #define check_neon_suffixes \
13292 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13294 as_bad (_("invalid neon suffix for non neon instruction")); \
13300 /* Define shapes for instruction operands. The following mnemonic characters
13301 are used in this table:
13303 F - VFP S<n> register
13304 D - Neon D<n> register
13305 Q - Neon Q<n> register
13309 L - D<n> register list
13311 This table is used to generate various data:
13312 - enumerations of the form NS_DDR to be used as arguments to
13314 - a table classifying shapes into single, double, quad, mixed.
13315 - a table used to drive neon_select_shape. */
13317 #define NEON_SHAPE_DEF \
13318 X(3, (D, D, D), DOUBLE), \
13319 X(3, (Q, Q, Q), QUAD), \
13320 X(3, (D, D, I), DOUBLE), \
13321 X(3, (Q, Q, I), QUAD), \
13322 X(3, (D, D, S), DOUBLE), \
13323 X(3, (Q, Q, S), QUAD), \
13324 X(2, (D, D), DOUBLE), \
13325 X(2, (Q, Q), QUAD), \
13326 X(2, (D, S), DOUBLE), \
13327 X(2, (Q, S), QUAD), \
13328 X(2, (D, R), DOUBLE), \
13329 X(2, (Q, R), QUAD), \
13330 X(2, (D, I), DOUBLE), \
13331 X(2, (Q, I), QUAD), \
13332 X(3, (D, L, D), DOUBLE), \
13333 X(2, (D, Q), MIXED), \
13334 X(2, (Q, D), MIXED), \
13335 X(3, (D, Q, I), MIXED), \
13336 X(3, (Q, D, I), MIXED), \
13337 X(3, (Q, D, D), MIXED), \
13338 X(3, (D, Q, Q), MIXED), \
13339 X(3, (Q, Q, D), MIXED), \
13340 X(3, (Q, D, S), MIXED), \
13341 X(3, (D, Q, S), MIXED), \
13342 X(4, (D, D, D, I), DOUBLE), \
13343 X(4, (Q, Q, Q, I), QUAD), \
13344 X(2, (F, F), SINGLE), \
13345 X(3, (F, F, F), SINGLE), \
13346 X(2, (F, I), SINGLE), \
13347 X(2, (F, D), MIXED), \
13348 X(2, (D, F), MIXED), \
13349 X(3, (F, F, I), MIXED), \
13350 X(4, (R, R, F, F), SINGLE), \
13351 X(4, (F, F, R, R), SINGLE), \
13352 X(3, (D, R, R), DOUBLE), \
13353 X(3, (R, R, D), DOUBLE), \
13354 X(2, (S, R), SINGLE), \
13355 X(2, (R, S), SINGLE), \
13356 X(2, (F, R), SINGLE), \
13357 X(2, (R, F), SINGLE), \
13358 /* Half float shape supported so far. */\
13359 X (2, (H, D), MIXED), \
13360 X (2, (D, H), MIXED), \
13361 X (2, (H, F), MIXED), \
13362 X (2, (F, H), MIXED), \
13363 X (2, (H, H), HALF), \
13364 X (2, (H, R), HALF), \
13365 X (2, (R, H), HALF), \
13366 X (2, (H, I), HALF), \
13367 X (3, (H, H, H), HALF), \
13368 X (3, (H, F, I), MIXED), \
13369 X (3, (F, H, I), MIXED)
13371 #define S2(A,B) NS_##A##B
13372 #define S3(A,B,C) NS_##A##B##C
13373 #define S4(A,B,C,D) NS_##A##B##C##D
13375 #define X(N, L, C) S##N L
13388 enum neon_shape_class
13397 #define X(N, L, C) SC_##C
13399 static enum neon_shape_class neon_shape_class
[] =
13418 /* Register widths of above. */
13419 static unsigned neon_shape_el_size
[] =
13431 struct neon_shape_info
13434 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13437 #define S2(A,B) { SE_##A, SE_##B }
13438 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13439 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13441 #define X(N, L, C) { N, S##N L }
13443 static struct neon_shape_info neon_shape_tab
[] =
13453 /* Bit masks used in type checking given instructions.
13454 'N_EQK' means the type must be the same as (or based on in some way) the key
13455 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13456 set, various other bits can be set as well in order to modify the meaning of
13457 the type constraint. */
13459 enum neon_type_mask
13483 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13484 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13485 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13486 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13487 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13488 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13489 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13490 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13491 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13492 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13493 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13495 N_MAX_NONSPECIAL
= N_P64
13498 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13500 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13501 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13502 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13503 #define N_S_32 (N_S8 | N_S16 | N_S32)
13504 #define N_F_16_32 (N_F16 | N_F32)
13505 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13506 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13507 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13508 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13510 /* Pass this as the first type argument to neon_check_type to ignore types
13512 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13514 /* Select a "shape" for the current instruction (describing register types or
13515 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13516 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13517 function of operand parsing, so this function doesn't need to be called.
13518 Shapes should be listed in order of decreasing length. */
13520 static enum neon_shape
13521 neon_select_shape (enum neon_shape shape
, ...)
13524 enum neon_shape first_shape
= shape
;
13526 /* Fix missing optional operands. FIXME: we don't know at this point how
13527 many arguments we should have, so this makes the assumption that we have
13528 > 1. This is true of all current Neon opcodes, I think, but may not be
13529 true in the future. */
13530 if (!inst
.operands
[1].present
)
13531 inst
.operands
[1] = inst
.operands
[0];
13533 va_start (ap
, shape
);
13535 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13540 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13542 if (!inst
.operands
[j
].present
)
13548 switch (neon_shape_tab
[shape
].el
[j
])
13550 /* If a .f16, .16, .u16, .s16 type specifier is given over
13551 a VFP single precision register operand, it's essentially
13552 means only half of the register is used.
13554 If the type specifier is given after the mnemonics, the
13555 information is stored in inst.vectype. If the type specifier
13556 is given after register operand, the information is stored
13557 in inst.operands[].vectype.
13559 When there is only one type specifier, and all the register
13560 operands are the same type of hardware register, the type
13561 specifier applies to all register operands.
13563 If no type specifier is given, the shape is inferred from
13564 operand information.
13567 vadd.f16 s0, s1, s2: NS_HHH
13568 vabs.f16 s0, s1: NS_HH
13569 vmov.f16 s0, r1: NS_HR
13570 vmov.f16 r0, s1: NS_RH
13571 vcvt.f16 r0, s1: NS_RH
13572 vcvt.f16.s32 s2, s2, #29: NS_HFI
13573 vcvt.f16.s32 s2, s2: NS_HF
13576 if (!(inst
.operands
[j
].isreg
13577 && inst
.operands
[j
].isvec
13578 && inst
.operands
[j
].issingle
13579 && !inst
.operands
[j
].isquad
13580 && ((inst
.vectype
.elems
== 1
13581 && inst
.vectype
.el
[0].size
== 16)
13582 || (inst
.vectype
.elems
> 1
13583 && inst
.vectype
.el
[j
].size
== 16)
13584 || (inst
.vectype
.elems
== 0
13585 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13586 && inst
.operands
[j
].vectype
.size
== 16))))
13591 if (!(inst
.operands
[j
].isreg
13592 && inst
.operands
[j
].isvec
13593 && inst
.operands
[j
].issingle
13594 && !inst
.operands
[j
].isquad
13595 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13596 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13597 || (inst
.vectype
.elems
== 0
13598 && (inst
.operands
[j
].vectype
.size
== 32
13599 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13604 if (!(inst
.operands
[j
].isreg
13605 && inst
.operands
[j
].isvec
13606 && !inst
.operands
[j
].isquad
13607 && !inst
.operands
[j
].issingle
))
13612 if (!(inst
.operands
[j
].isreg
13613 && !inst
.operands
[j
].isvec
))
13618 if (!(inst
.operands
[j
].isreg
13619 && inst
.operands
[j
].isvec
13620 && inst
.operands
[j
].isquad
13621 && !inst
.operands
[j
].issingle
))
13626 if (!(!inst
.operands
[j
].isreg
13627 && !inst
.operands
[j
].isscalar
))
13632 if (!(!inst
.operands
[j
].isreg
13633 && inst
.operands
[j
].isscalar
))
13643 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13644 /* We've matched all the entries in the shape table, and we don't
13645 have any left over operands which have not been matched. */
13651 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13652 first_error (_("invalid instruction shape"));
13657 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13658 means the Q bit should be set). */
13661 neon_quad (enum neon_shape shape
)
13663 return neon_shape_class
[shape
] == SC_QUAD
;
13667 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13670 /* Allow modification to be made to types which are constrained to be
13671 based on the key element, based on bits set alongside N_EQK. */
13672 if ((typebits
& N_EQK
) != 0)
13674 if ((typebits
& N_HLF
) != 0)
13676 else if ((typebits
& N_DBL
) != 0)
13678 if ((typebits
& N_SGN
) != 0)
13679 *g_type
= NT_signed
;
13680 else if ((typebits
& N_UNS
) != 0)
13681 *g_type
= NT_unsigned
;
13682 else if ((typebits
& N_INT
) != 0)
13683 *g_type
= NT_integer
;
13684 else if ((typebits
& N_FLT
) != 0)
13685 *g_type
= NT_float
;
13686 else if ((typebits
& N_SIZ
) != 0)
13687 *g_type
= NT_untyped
;
13691 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13692 operand type, i.e. the single type specified in a Neon instruction when it
13693 is the only one given. */
13695 static struct neon_type_el
13696 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13698 struct neon_type_el dest
= *key
;
13700 gas_assert ((thisarg
& N_EQK
) != 0);
13702 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13707 /* Convert Neon type and size into compact bitmask representation. */
13709 static enum neon_type_mask
13710 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13717 case 8: return N_8
;
13718 case 16: return N_16
;
13719 case 32: return N_32
;
13720 case 64: return N_64
;
13728 case 8: return N_I8
;
13729 case 16: return N_I16
;
13730 case 32: return N_I32
;
13731 case 64: return N_I64
;
13739 case 16: return N_F16
;
13740 case 32: return N_F32
;
13741 case 64: return N_F64
;
13749 case 8: return N_P8
;
13750 case 16: return N_P16
;
13751 case 64: return N_P64
;
13759 case 8: return N_S8
;
13760 case 16: return N_S16
;
13761 case 32: return N_S32
;
13762 case 64: return N_S64
;
13770 case 8: return N_U8
;
13771 case 16: return N_U16
;
13772 case 32: return N_U32
;
13773 case 64: return N_U64
;
13784 /* Convert compact Neon bitmask type representation to a type and size. Only
13785 handles the case where a single bit is set in the mask. */
13788 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13789 enum neon_type_mask mask
)
13791 if ((mask
& N_EQK
) != 0)
13794 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13796 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13798 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13800 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13805 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13807 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13808 *type
= NT_unsigned
;
13809 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13810 *type
= NT_integer
;
13811 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13812 *type
= NT_untyped
;
13813 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13815 else if ((mask
& (N_F_ALL
)) != 0)
13823 /* Modify a bitmask of allowed types. This is only needed for type
13827 modify_types_allowed (unsigned allowed
, unsigned mods
)
13830 enum neon_el_type type
;
13836 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13838 if (el_type_of_type_chk (&type
, &size
,
13839 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13841 neon_modify_type_size (mods
, &type
, &size
);
13842 destmask
|= type_chk_of_el_type (type
, size
);
13849 /* Check type and return type classification.
13850 The manual states (paraphrase): If one datatype is given, it indicates the
13852 - the second operand, if there is one
13853 - the operand, if there is no second operand
13854 - the result, if there are no operands.
13855 This isn't quite good enough though, so we use a concept of a "key" datatype
13856 which is set on a per-instruction basis, which is the one which matters when
13857 only one data type is written.
13858 Note: this function has side-effects (e.g. filling in missing operands). All
13859 Neon instructions should call it before performing bit encoding. */
13861 static struct neon_type_el
13862 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13865 unsigned i
, pass
, key_el
= 0;
13866 unsigned types
[NEON_MAX_TYPE_ELS
];
13867 enum neon_el_type k_type
= NT_invtype
;
13868 unsigned k_size
= -1u;
13869 struct neon_type_el badtype
= {NT_invtype
, -1};
13870 unsigned key_allowed
= 0;
13872 /* Optional registers in Neon instructions are always (not) in operand 1.
13873 Fill in the missing operand here, if it was omitted. */
13874 if (els
> 1 && !inst
.operands
[1].present
)
13875 inst
.operands
[1] = inst
.operands
[0];
13877 /* Suck up all the varargs. */
13879 for (i
= 0; i
< els
; i
++)
13881 unsigned thisarg
= va_arg (ap
, unsigned);
13882 if (thisarg
== N_IGNORE_TYPE
)
13887 types
[i
] = thisarg
;
13888 if ((thisarg
& N_KEY
) != 0)
13893 if (inst
.vectype
.elems
> 0)
13894 for (i
= 0; i
< els
; i
++)
13895 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13897 first_error (_("types specified in both the mnemonic and operands"));
13901 /* Duplicate inst.vectype elements here as necessary.
13902 FIXME: No idea if this is exactly the same as the ARM assembler,
13903 particularly when an insn takes one register and one non-register
13905 if (inst
.vectype
.elems
== 1 && els
> 1)
13908 inst
.vectype
.elems
= els
;
13909 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13910 for (j
= 0; j
< els
; j
++)
13912 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13915 else if (inst
.vectype
.elems
== 0 && els
> 0)
13918 /* No types were given after the mnemonic, so look for types specified
13919 after each operand. We allow some flexibility here; as long as the
13920 "key" operand has a type, we can infer the others. */
13921 for (j
= 0; j
< els
; j
++)
13922 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13923 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13925 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13927 for (j
= 0; j
< els
; j
++)
13928 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13929 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13934 first_error (_("operand types can't be inferred"));
13938 else if (inst
.vectype
.elems
!= els
)
13940 first_error (_("type specifier has the wrong number of parts"));
13944 for (pass
= 0; pass
< 2; pass
++)
13946 for (i
= 0; i
< els
; i
++)
13948 unsigned thisarg
= types
[i
];
13949 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13950 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13951 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13952 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13954 /* Decay more-specific signed & unsigned types to sign-insensitive
13955 integer types if sign-specific variants are unavailable. */
13956 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13957 && (types_allowed
& N_SU_ALL
) == 0)
13958 g_type
= NT_integer
;
13960 /* If only untyped args are allowed, decay any more specific types to
13961 them. Some instructions only care about signs for some element
13962 sizes, so handle that properly. */
13963 if (((types_allowed
& N_UNT
) == 0)
13964 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13965 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13966 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13967 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13968 g_type
= NT_untyped
;
13972 if ((thisarg
& N_KEY
) != 0)
13976 key_allowed
= thisarg
& ~N_KEY
;
13978 /* Check architecture constraint on FP16 extension. */
13980 && k_type
== NT_float
13981 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13983 inst
.error
= _(BAD_FP16
);
13990 if ((thisarg
& N_VFP
) != 0)
13992 enum neon_shape_el regshape
;
13993 unsigned regwidth
, match
;
13995 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13998 first_error (_("invalid instruction shape"));
14001 regshape
= neon_shape_tab
[ns
].el
[i
];
14002 regwidth
= neon_shape_el_size
[regshape
];
14004 /* In VFP mode, operands must match register widths. If we
14005 have a key operand, use its width, else use the width of
14006 the current operand. */
14012 /* FP16 will use a single precision register. */
14013 if (regwidth
== 32 && match
== 16)
14015 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14019 inst
.error
= _(BAD_FP16
);
14024 if (regwidth
!= match
)
14026 first_error (_("operand size must match register width"));
14031 if ((thisarg
& N_EQK
) == 0)
14033 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14035 if ((given_type
& types_allowed
) == 0)
14037 first_error (_("bad type in Neon instruction"));
14043 enum neon_el_type mod_k_type
= k_type
;
14044 unsigned mod_k_size
= k_size
;
14045 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14046 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14048 first_error (_("inconsistent types in Neon instruction"));
14056 return inst
.vectype
.el
[key_el
];
14059 /* Neon-style VFP instruction forwarding. */
14061 /* Thumb VFP instructions have 0xE in the condition field. */
14064 do_vfp_cond_or_thumb (void)
14069 inst
.instruction
|= 0xe0000000;
14071 inst
.instruction
|= inst
.cond
<< 28;
14074 /* Look up and encode a simple mnemonic, for use as a helper function for the
14075 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14076 etc. It is assumed that operand parsing has already been done, and that the
14077 operands are in the form expected by the given opcode (this isn't necessarily
14078 the same as the form in which they were parsed, hence some massaging must
14079 take place before this function is called).
14080 Checks current arch version against that in the looked-up opcode. */
14083 do_vfp_nsyn_opcode (const char *opname
)
14085 const struct asm_opcode
*opcode
;
14087 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14093 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14100 inst
.instruction
= opcode
->tvalue
;
14101 opcode
->tencode ();
14105 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14106 opcode
->aencode ();
14111 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14113 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14115 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14118 do_vfp_nsyn_opcode ("fadds");
14120 do_vfp_nsyn_opcode ("fsubs");
14122 /* ARMv8.2 fp16 instruction. */
14124 do_scalar_fp16_v82_encode ();
14129 do_vfp_nsyn_opcode ("faddd");
14131 do_vfp_nsyn_opcode ("fsubd");
14135 /* Check operand types to see if this is a VFP instruction, and if so call
14139 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14141 enum neon_shape rs
;
14142 struct neon_type_el et
;
14147 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14148 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14152 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14153 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14154 N_F_ALL
| N_KEY
| N_VFP
);
14161 if (et
.type
!= NT_invtype
)
14172 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14174 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14176 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14179 do_vfp_nsyn_opcode ("fmacs");
14181 do_vfp_nsyn_opcode ("fnmacs");
14183 /* ARMv8.2 fp16 instruction. */
14185 do_scalar_fp16_v82_encode ();
14190 do_vfp_nsyn_opcode ("fmacd");
14192 do_vfp_nsyn_opcode ("fnmacd");
14197 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14199 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14201 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14204 do_vfp_nsyn_opcode ("ffmas");
14206 do_vfp_nsyn_opcode ("ffnmas");
14208 /* ARMv8.2 fp16 instruction. */
14210 do_scalar_fp16_v82_encode ();
14215 do_vfp_nsyn_opcode ("ffmad");
14217 do_vfp_nsyn_opcode ("ffnmad");
14222 do_vfp_nsyn_mul (enum neon_shape rs
)
14224 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14226 do_vfp_nsyn_opcode ("fmuls");
14228 /* ARMv8.2 fp16 instruction. */
14230 do_scalar_fp16_v82_encode ();
14233 do_vfp_nsyn_opcode ("fmuld");
14237 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14239 int is_neg
= (inst
.instruction
& 0x80) != 0;
14240 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14242 if (rs
== NS_FF
|| rs
== NS_HH
)
14245 do_vfp_nsyn_opcode ("fnegs");
14247 do_vfp_nsyn_opcode ("fabss");
14249 /* ARMv8.2 fp16 instruction. */
14251 do_scalar_fp16_v82_encode ();
14256 do_vfp_nsyn_opcode ("fnegd");
14258 do_vfp_nsyn_opcode ("fabsd");
14262 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14263 insns belong to Neon, and are handled elsewhere. */
14266 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14268 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14272 do_vfp_nsyn_opcode ("fldmdbs");
14274 do_vfp_nsyn_opcode ("fldmias");
14279 do_vfp_nsyn_opcode ("fstmdbs");
14281 do_vfp_nsyn_opcode ("fstmias");
14286 do_vfp_nsyn_sqrt (void)
14288 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14289 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14291 if (rs
== NS_FF
|| rs
== NS_HH
)
14293 do_vfp_nsyn_opcode ("fsqrts");
14295 /* ARMv8.2 fp16 instruction. */
14297 do_scalar_fp16_v82_encode ();
14300 do_vfp_nsyn_opcode ("fsqrtd");
14304 do_vfp_nsyn_div (void)
14306 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14307 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14308 N_F_ALL
| N_KEY
| N_VFP
);
14310 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14312 do_vfp_nsyn_opcode ("fdivs");
14314 /* ARMv8.2 fp16 instruction. */
14316 do_scalar_fp16_v82_encode ();
14319 do_vfp_nsyn_opcode ("fdivd");
14323 do_vfp_nsyn_nmul (void)
14325 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14326 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14327 N_F_ALL
| N_KEY
| N_VFP
);
14329 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14331 NEON_ENCODE (SINGLE
, inst
);
14332 do_vfp_sp_dyadic ();
14334 /* ARMv8.2 fp16 instruction. */
14336 do_scalar_fp16_v82_encode ();
14340 NEON_ENCODE (DOUBLE
, inst
);
14341 do_vfp_dp_rd_rn_rm ();
14343 do_vfp_cond_or_thumb ();
14348 do_vfp_nsyn_cmp (void)
14350 enum neon_shape rs
;
14351 if (inst
.operands
[1].isreg
)
14353 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14354 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14356 if (rs
== NS_FF
|| rs
== NS_HH
)
14358 NEON_ENCODE (SINGLE
, inst
);
14359 do_vfp_sp_monadic ();
14363 NEON_ENCODE (DOUBLE
, inst
);
14364 do_vfp_dp_rd_rm ();
14369 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14370 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14372 switch (inst
.instruction
& 0x0fffffff)
14375 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14378 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14384 if (rs
== NS_FI
|| rs
== NS_HI
)
14386 NEON_ENCODE (SINGLE
, inst
);
14387 do_vfp_sp_compare_z ();
14391 NEON_ENCODE (DOUBLE
, inst
);
14395 do_vfp_cond_or_thumb ();
14397 /* ARMv8.2 fp16 instruction. */
14398 if (rs
== NS_HI
|| rs
== NS_HH
)
14399 do_scalar_fp16_v82_encode ();
14403 nsyn_insert_sp (void)
14405 inst
.operands
[1] = inst
.operands
[0];
14406 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14407 inst
.operands
[0].reg
= REG_SP
;
14408 inst
.operands
[0].isreg
= 1;
14409 inst
.operands
[0].writeback
= 1;
14410 inst
.operands
[0].present
= 1;
14414 do_vfp_nsyn_push (void)
14418 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14419 _("register list must contain at least 1 and at most 16 "
14422 if (inst
.operands
[1].issingle
)
14423 do_vfp_nsyn_opcode ("fstmdbs");
14425 do_vfp_nsyn_opcode ("fstmdbd");
14429 do_vfp_nsyn_pop (void)
14433 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14434 _("register list must contain at least 1 and at most 16 "
14437 if (inst
.operands
[1].issingle
)
14438 do_vfp_nsyn_opcode ("fldmias");
14440 do_vfp_nsyn_opcode ("fldmiad");
14443 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14444 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14447 neon_dp_fixup (struct arm_it
* insn
)
14449 unsigned int i
= insn
->instruction
;
14454 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14465 insn
->instruction
= i
;
14468 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14472 neon_logbits (unsigned x
)
14474 return ffs (x
) - 4;
14477 #define LOW4(R) ((R) & 0xf)
14478 #define HI1(R) (((R) >> 4) & 1)
14480 /* Encode insns with bit pattern:
14482 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14483 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14485 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14486 different meaning for some instruction. */
14489 neon_three_same (int isquad
, int ubit
, int size
)
14491 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14492 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14493 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14494 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14495 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14496 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14497 inst
.instruction
|= (isquad
!= 0) << 6;
14498 inst
.instruction
|= (ubit
!= 0) << 24;
14500 inst
.instruction
|= neon_logbits (size
) << 20;
14502 neon_dp_fixup (&inst
);
14505 /* Encode instructions of the form:
14507 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14508 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14510 Don't write size if SIZE == -1. */
14513 neon_two_same (int qbit
, int ubit
, int size
)
14515 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14516 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14517 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14518 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14519 inst
.instruction
|= (qbit
!= 0) << 6;
14520 inst
.instruction
|= (ubit
!= 0) << 24;
14523 inst
.instruction
|= neon_logbits (size
) << 18;
14525 neon_dp_fixup (&inst
);
14528 /* Neon instruction encoders, in approximate order of appearance. */
14531 do_neon_dyadic_i_su (void)
14533 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14534 struct neon_type_el et
= neon_check_type (3, rs
,
14535 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14536 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14540 do_neon_dyadic_i64_su (void)
14542 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14543 struct neon_type_el et
= neon_check_type (3, rs
,
14544 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14545 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14549 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14552 unsigned size
= et
.size
>> 3;
14553 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14554 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14556 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14557 inst
.instruction
|= (isquad
!= 0) << 6;
14558 inst
.instruction
|= immbits
<< 16;
14559 inst
.instruction
|= (size
>> 3) << 7;
14560 inst
.instruction
|= (size
& 0x7) << 19;
14562 inst
.instruction
|= (uval
!= 0) << 24;
14564 neon_dp_fixup (&inst
);
14568 do_neon_shl_imm (void)
14570 if (!inst
.operands
[2].isreg
)
14572 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14573 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14574 int imm
= inst
.operands
[2].imm
;
14576 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14577 _("immediate out of range for shift"));
14578 NEON_ENCODE (IMMED
, inst
);
14579 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14583 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14584 struct neon_type_el et
= neon_check_type (3, rs
,
14585 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14588 /* VSHL/VQSHL 3-register variants have syntax such as:
14590 whereas other 3-register operations encoded by neon_three_same have
14593 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14595 tmp
= inst
.operands
[2].reg
;
14596 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14597 inst
.operands
[1].reg
= tmp
;
14598 NEON_ENCODE (INTEGER
, inst
);
14599 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14604 do_neon_qshl_imm (void)
14606 if (!inst
.operands
[2].isreg
)
14608 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14609 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14610 int imm
= inst
.operands
[2].imm
;
14612 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14613 _("immediate out of range for shift"));
14614 NEON_ENCODE (IMMED
, inst
);
14615 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14619 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14620 struct neon_type_el et
= neon_check_type (3, rs
,
14621 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14624 /* See note in do_neon_shl_imm. */
14625 tmp
= inst
.operands
[2].reg
;
14626 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14627 inst
.operands
[1].reg
= tmp
;
14628 NEON_ENCODE (INTEGER
, inst
);
14629 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14634 do_neon_rshl (void)
14636 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14637 struct neon_type_el et
= neon_check_type (3, rs
,
14638 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14641 tmp
= inst
.operands
[2].reg
;
14642 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14643 inst
.operands
[1].reg
= tmp
;
14644 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14648 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14650 /* Handle .I8 pseudo-instructions. */
14653 /* Unfortunately, this will make everything apart from zero out-of-range.
14654 FIXME is this the intended semantics? There doesn't seem much point in
14655 accepting .I8 if so. */
14656 immediate
|= immediate
<< 8;
14662 if (immediate
== (immediate
& 0x000000ff))
14664 *immbits
= immediate
;
14667 else if (immediate
== (immediate
& 0x0000ff00))
14669 *immbits
= immediate
>> 8;
14672 else if (immediate
== (immediate
& 0x00ff0000))
14674 *immbits
= immediate
>> 16;
14677 else if (immediate
== (immediate
& 0xff000000))
14679 *immbits
= immediate
>> 24;
14682 if ((immediate
& 0xffff) != (immediate
>> 16))
14683 goto bad_immediate
;
14684 immediate
&= 0xffff;
14687 if (immediate
== (immediate
& 0x000000ff))
14689 *immbits
= immediate
;
14692 else if (immediate
== (immediate
& 0x0000ff00))
14694 *immbits
= immediate
>> 8;
14699 first_error (_("immediate value out of range"));
14704 do_neon_logic (void)
14706 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14708 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14709 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14710 /* U bit and size field were set as part of the bitmask. */
14711 NEON_ENCODE (INTEGER
, inst
);
14712 neon_three_same (neon_quad (rs
), 0, -1);
14716 const int three_ops_form
= (inst
.operands
[2].present
14717 && !inst
.operands
[2].isreg
);
14718 const int immoperand
= (three_ops_form
? 2 : 1);
14719 enum neon_shape rs
= (three_ops_form
14720 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14721 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14722 struct neon_type_el et
= neon_check_type (2, rs
,
14723 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14724 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14728 if (et
.type
== NT_invtype
)
14731 if (three_ops_form
)
14732 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14733 _("first and second operands shall be the same register"));
14735 NEON_ENCODE (IMMED
, inst
);
14737 immbits
= inst
.operands
[immoperand
].imm
;
14740 /* .i64 is a pseudo-op, so the immediate must be a repeating
14742 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14743 inst
.operands
[immoperand
].reg
: 0))
14745 /* Set immbits to an invalid constant. */
14746 immbits
= 0xdeadbeef;
14753 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14757 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14761 /* Pseudo-instruction for VBIC. */
14762 neon_invert_size (&immbits
, 0, et
.size
);
14763 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14767 /* Pseudo-instruction for VORR. */
14768 neon_invert_size (&immbits
, 0, et
.size
);
14769 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14779 inst
.instruction
|= neon_quad (rs
) << 6;
14780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14782 inst
.instruction
|= cmode
<< 8;
14783 neon_write_immbits (immbits
);
14785 neon_dp_fixup (&inst
);
14790 do_neon_bitfield (void)
14792 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14793 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14794 neon_three_same (neon_quad (rs
), 0, -1);
14798 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14801 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14802 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14804 if (et
.type
== NT_float
)
14806 NEON_ENCODE (FLOAT
, inst
);
14807 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14811 NEON_ENCODE (INTEGER
, inst
);
14812 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14817 do_neon_dyadic_if_su (void)
14819 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14823 do_neon_dyadic_if_su_d (void)
14825 /* This version only allow D registers, but that constraint is enforced during
14826 operand parsing so we don't need to do anything extra here. */
14827 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14831 do_neon_dyadic_if_i_d (void)
14833 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14834 affected if we specify unsigned args. */
14835 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14838 enum vfp_or_neon_is_neon_bits
14841 NEON_CHECK_ARCH
= 2,
14842 NEON_CHECK_ARCH8
= 4
14845 /* Call this function if an instruction which may have belonged to the VFP or
14846 Neon instruction sets, but turned out to be a Neon instruction (due to the
14847 operand types involved, etc.). We have to check and/or fix-up a couple of
14850 - Make sure the user hasn't attempted to make a Neon instruction
14852 - Alter the value in the condition code field if necessary.
14853 - Make sure that the arch supports Neon instructions.
14855 Which of these operations take place depends on bits from enum
14856 vfp_or_neon_is_neon_bits.
14858 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14859 current instruction's condition is COND_ALWAYS, the condition field is
14860 changed to inst.uncond_value. This is necessary because instructions shared
14861 between VFP and Neon may be conditional for the VFP variants only, and the
14862 unconditional Neon version must have, e.g., 0xF in the condition field. */
14865 vfp_or_neon_is_neon (unsigned check
)
14867 /* Conditions are always legal in Thumb mode (IT blocks). */
14868 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14870 if (inst
.cond
!= COND_ALWAYS
)
14872 first_error (_(BAD_COND
));
14875 if (inst
.uncond_value
!= -1)
14876 inst
.instruction
|= inst
.uncond_value
<< 28;
14879 if ((check
& NEON_CHECK_ARCH
)
14880 && !mark_feature_used (&fpu_neon_ext_v1
))
14882 first_error (_(BAD_FPU
));
14886 if ((check
& NEON_CHECK_ARCH8
)
14887 && !mark_feature_used (&fpu_neon_ext_armv8
))
14889 first_error (_(BAD_FPU
));
14897 do_neon_addsub_if_i (void)
14899 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14902 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14905 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14906 affected if we specify unsigned args. */
14907 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14910 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14912 V<op> A,B (A is operand 0, B is operand 2)
14917 so handle that case specially. */
14920 neon_exchange_operands (void)
14922 if (inst
.operands
[1].present
)
14924 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14926 /* Swap operands[1] and operands[2]. */
14927 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14928 inst
.operands
[1] = inst
.operands
[2];
14929 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14934 inst
.operands
[1] = inst
.operands
[2];
14935 inst
.operands
[2] = inst
.operands
[0];
14940 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14942 if (inst
.operands
[2].isreg
)
14945 neon_exchange_operands ();
14946 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14950 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14951 struct neon_type_el et
= neon_check_type (2, rs
,
14952 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14954 NEON_ENCODE (IMMED
, inst
);
14955 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14956 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14957 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14958 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14959 inst
.instruction
|= neon_quad (rs
) << 6;
14960 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14961 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14963 neon_dp_fixup (&inst
);
14970 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14974 do_neon_cmp_inv (void)
14976 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14982 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14985 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14986 scalars, which are encoded in 5 bits, M : Rm.
14987 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14988 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14992 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14994 unsigned regno
= NEON_SCALAR_REG (scalar
);
14995 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15000 if (regno
> 7 || elno
> 3)
15002 return regno
| (elno
<< 3);
15005 if (regno
> 15 || elno
> 1)
15007 return regno
| (elno
<< 4);
15011 first_error (_("scalar out of range for multiply instruction"));
15017 /* Encode multiply / multiply-accumulate scalar instructions. */
15020 neon_mul_mac (struct neon_type_el et
, int ubit
)
15024 /* Give a more helpful error message if we have an invalid type. */
15025 if (et
.type
== NT_invtype
)
15028 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15030 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15033 inst
.instruction
|= LOW4 (scalar
);
15034 inst
.instruction
|= HI1 (scalar
) << 5;
15035 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15036 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15037 inst
.instruction
|= (ubit
!= 0) << 24;
15039 neon_dp_fixup (&inst
);
15043 do_neon_mac_maybe_scalar (void)
15045 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15048 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15051 if (inst
.operands
[2].isscalar
)
15053 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15054 struct neon_type_el et
= neon_check_type (3, rs
,
15055 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15056 NEON_ENCODE (SCALAR
, inst
);
15057 neon_mul_mac (et
, neon_quad (rs
));
15061 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15062 affected if we specify unsigned args. */
15063 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15068 do_neon_fmac (void)
15070 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15073 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15076 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15082 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15083 struct neon_type_el et
= neon_check_type (3, rs
,
15084 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15085 neon_three_same (neon_quad (rs
), 0, et
.size
);
15088 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15089 same types as the MAC equivalents. The polynomial type for this instruction
15090 is encoded the same as the integer type. */
15095 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15098 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15101 if (inst
.operands
[2].isscalar
)
15102 do_neon_mac_maybe_scalar ();
15104 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15108 do_neon_qdmulh (void)
15110 if (inst
.operands
[2].isscalar
)
15112 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15113 struct neon_type_el et
= neon_check_type (3, rs
,
15114 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15115 NEON_ENCODE (SCALAR
, inst
);
15116 neon_mul_mac (et
, neon_quad (rs
));
15120 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15121 struct neon_type_el et
= neon_check_type (3, rs
,
15122 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15123 NEON_ENCODE (INTEGER
, inst
);
15124 /* The U bit (rounding) comes from bit mask. */
15125 neon_three_same (neon_quad (rs
), 0, et
.size
);
15130 do_neon_qrdmlah (void)
15132 /* Check we're on the correct architecture. */
15133 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15135 _("instruction form not available on this architecture.");
15136 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15138 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15139 record_feature_use (&fpu_neon_ext_v8_1
);
15142 if (inst
.operands
[2].isscalar
)
15144 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15145 struct neon_type_el et
= neon_check_type (3, rs
,
15146 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15147 NEON_ENCODE (SCALAR
, inst
);
15148 neon_mul_mac (et
, neon_quad (rs
));
15152 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15153 struct neon_type_el et
= neon_check_type (3, rs
,
15154 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15155 NEON_ENCODE (INTEGER
, inst
);
15156 /* The U bit (rounding) comes from bit mask. */
15157 neon_three_same (neon_quad (rs
), 0, et
.size
);
15162 do_neon_fcmp_absolute (void)
15164 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15165 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15166 N_F_16_32
| N_KEY
);
15167 /* Size field comes from bit mask. */
15168 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15172 do_neon_fcmp_absolute_inv (void)
15174 neon_exchange_operands ();
15175 do_neon_fcmp_absolute ();
15179 do_neon_step (void)
15181 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15182 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15183 N_F_16_32
| N_KEY
);
15184 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15188 do_neon_abs_neg (void)
15190 enum neon_shape rs
;
15191 struct neon_type_el et
;
15193 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15196 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15199 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15200 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15202 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15203 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15204 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15205 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15206 inst
.instruction
|= neon_quad (rs
) << 6;
15207 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15208 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15210 neon_dp_fixup (&inst
);
15216 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15217 struct neon_type_el et
= neon_check_type (2, rs
,
15218 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15219 int imm
= inst
.operands
[2].imm
;
15220 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15221 _("immediate out of range for insert"));
15222 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15228 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15229 struct neon_type_el et
= neon_check_type (2, rs
,
15230 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15231 int imm
= inst
.operands
[2].imm
;
15232 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15233 _("immediate out of range for insert"));
15234 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15238 do_neon_qshlu_imm (void)
15240 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15241 struct neon_type_el et
= neon_check_type (2, rs
,
15242 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15243 int imm
= inst
.operands
[2].imm
;
15244 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15245 _("immediate out of range for shift"));
15246 /* Only encodes the 'U present' variant of the instruction.
15247 In this case, signed types have OP (bit 8) set to 0.
15248 Unsigned types have OP set to 1. */
15249 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15250 /* The rest of the bits are the same as other immediate shifts. */
15251 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15255 do_neon_qmovn (void)
15257 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15258 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15259 /* Saturating move where operands can be signed or unsigned, and the
15260 destination has the same signedness. */
15261 NEON_ENCODE (INTEGER
, inst
);
15262 if (et
.type
== NT_unsigned
)
15263 inst
.instruction
|= 0xc0;
15265 inst
.instruction
|= 0x80;
15266 neon_two_same (0, 1, et
.size
/ 2);
15270 do_neon_qmovun (void)
15272 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15273 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15274 /* Saturating move with unsigned results. Operands must be signed. */
15275 NEON_ENCODE (INTEGER
, inst
);
15276 neon_two_same (0, 1, et
.size
/ 2);
15280 do_neon_rshift_sat_narrow (void)
15282 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15283 or unsigned. If operands are unsigned, results must also be unsigned. */
15284 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15285 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15286 int imm
= inst
.operands
[2].imm
;
15287 /* This gets the bounds check, size encoding and immediate bits calculation
15291 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15292 VQMOVN.I<size> <Dd>, <Qm>. */
15295 inst
.operands
[2].present
= 0;
15296 inst
.instruction
= N_MNEM_vqmovn
;
15301 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15302 _("immediate out of range"));
15303 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15307 do_neon_rshift_sat_narrow_u (void)
15309 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15310 or unsigned. If operands are unsigned, results must also be unsigned. */
15311 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15312 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15313 int imm
= inst
.operands
[2].imm
;
15314 /* This gets the bounds check, size encoding and immediate bits calculation
15318 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15319 VQMOVUN.I<size> <Dd>, <Qm>. */
15322 inst
.operands
[2].present
= 0;
15323 inst
.instruction
= N_MNEM_vqmovun
;
15328 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15329 _("immediate out of range"));
15330 /* FIXME: The manual is kind of unclear about what value U should have in
15331 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15333 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15337 do_neon_movn (void)
15339 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15340 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15341 NEON_ENCODE (INTEGER
, inst
);
15342 neon_two_same (0, 1, et
.size
/ 2);
15346 do_neon_rshift_narrow (void)
15348 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15349 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15350 int imm
= inst
.operands
[2].imm
;
15351 /* This gets the bounds check, size encoding and immediate bits calculation
15355 /* If immediate is zero then we are a pseudo-instruction for
15356 VMOVN.I<size> <Dd>, <Qm> */
15359 inst
.operands
[2].present
= 0;
15360 inst
.instruction
= N_MNEM_vmovn
;
15365 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15366 _("immediate out of range for narrowing operation"));
15367 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15371 do_neon_shll (void)
15373 /* FIXME: Type checking when lengthening. */
15374 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15375 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15376 unsigned imm
= inst
.operands
[2].imm
;
15378 if (imm
== et
.size
)
15380 /* Maximum shift variant. */
15381 NEON_ENCODE (INTEGER
, inst
);
15382 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15385 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15386 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15388 neon_dp_fixup (&inst
);
15392 /* A more-specific type check for non-max versions. */
15393 et
= neon_check_type (2, NS_QDI
,
15394 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15395 NEON_ENCODE (IMMED
, inst
);
15396 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15400 /* Check the various types for the VCVT instruction, and return which version
15401 the current instruction is. */
15403 #define CVT_FLAVOUR_VAR \
15404 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15405 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15406 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15407 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15408 /* Half-precision conversions. */ \
15409 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15410 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15411 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15412 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15413 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15414 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15415 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15416 Compared with single/double precision variants, only the co-processor \
15417 field is different, so the encoding flow is reused here. */ \
15418 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15419 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15420 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15421 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15422 /* VFP instructions. */ \
15423 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15424 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15425 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15426 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15427 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15428 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15429 /* VFP instructions with bitshift. */ \
15430 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15431 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15432 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15433 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15434 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15435 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15436 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15437 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15439 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15440 neon_cvt_flavour_##C,
15442 /* The different types of conversions we can do. */
15443 enum neon_cvt_flavour
15446 neon_cvt_flavour_invalid
,
15447 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15452 static enum neon_cvt_flavour
15453 get_neon_cvt_flavour (enum neon_shape rs
)
15455 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15456 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15457 if (et.type != NT_invtype) \
15459 inst.error = NULL; \
15460 return (neon_cvt_flavour_##C); \
15463 struct neon_type_el et
;
15464 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15465 || rs
== NS_FF
) ? N_VFP
: 0;
15466 /* The instruction versions which take an immediate take one register
15467 argument, which is extended to the width of the full register. Thus the
15468 "source" and "destination" registers must have the same width. Hack that
15469 here by making the size equal to the key (wider, in this case) operand. */
15470 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15474 return neon_cvt_flavour_invalid
;
15489 /* Neon-syntax VFP conversions. */
15492 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15494 const char *opname
= 0;
15496 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15497 || rs
== NS_FHI
|| rs
== NS_HFI
)
15499 /* Conversions with immediate bitshift. */
15500 const char *enc
[] =
15502 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15508 if (flavour
< (int) ARRAY_SIZE (enc
))
15510 opname
= enc
[flavour
];
15511 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15512 _("operands 0 and 1 must be the same register"));
15513 inst
.operands
[1] = inst
.operands
[2];
15514 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15519 /* Conversions without bitshift. */
15520 const char *enc
[] =
15522 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15528 if (flavour
< (int) ARRAY_SIZE (enc
))
15529 opname
= enc
[flavour
];
15533 do_vfp_nsyn_opcode (opname
);
15535 /* ARMv8.2 fp16 VCVT instruction. */
15536 if (flavour
== neon_cvt_flavour_s32_f16
15537 || flavour
== neon_cvt_flavour_u32_f16
15538 || flavour
== neon_cvt_flavour_f16_u32
15539 || flavour
== neon_cvt_flavour_f16_s32
)
15540 do_scalar_fp16_v82_encode ();
15544 do_vfp_nsyn_cvtz (void)
15546 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15547 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15548 const char *enc
[] =
15550 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15556 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15557 do_vfp_nsyn_opcode (enc
[flavour
]);
15561 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15562 enum neon_cvt_mode mode
)
15567 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15568 D register operands. */
15569 if (flavour
== neon_cvt_flavour_s32_f64
15570 || flavour
== neon_cvt_flavour_u32_f64
)
15571 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15574 if (flavour
== neon_cvt_flavour_s32_f16
15575 || flavour
== neon_cvt_flavour_u32_f16
)
15576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15579 set_it_insn_type (OUTSIDE_IT_INSN
);
15583 case neon_cvt_flavour_s32_f64
:
15587 case neon_cvt_flavour_s32_f32
:
15591 case neon_cvt_flavour_s32_f16
:
15595 case neon_cvt_flavour_u32_f64
:
15599 case neon_cvt_flavour_u32_f32
:
15603 case neon_cvt_flavour_u32_f16
:
15608 first_error (_("invalid instruction shape"));
15614 case neon_cvt_mode_a
: rm
= 0; break;
15615 case neon_cvt_mode_n
: rm
= 1; break;
15616 case neon_cvt_mode_p
: rm
= 2; break;
15617 case neon_cvt_mode_m
: rm
= 3; break;
15618 default: first_error (_("invalid rounding mode")); return;
15621 NEON_ENCODE (FPV8
, inst
);
15622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15623 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15624 inst
.instruction
|= sz
<< 8;
15626 /* ARMv8.2 fp16 VCVT instruction. */
15627 if (flavour
== neon_cvt_flavour_s32_f16
15628 ||flavour
== neon_cvt_flavour_u32_f16
)
15629 do_scalar_fp16_v82_encode ();
15630 inst
.instruction
|= op
<< 7;
15631 inst
.instruction
|= rm
<< 16;
15632 inst
.instruction
|= 0xf0000000;
15633 inst
.is_neon
= TRUE
;
15637 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15639 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15640 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15641 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15643 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15645 if (flavour
== neon_cvt_flavour_invalid
)
15648 /* PR11109: Handle round-to-zero for VCVT conversions. */
15649 if (mode
== neon_cvt_mode_z
15650 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15651 && (flavour
== neon_cvt_flavour_s16_f16
15652 || flavour
== neon_cvt_flavour_u16_f16
15653 || flavour
== neon_cvt_flavour_s32_f32
15654 || flavour
== neon_cvt_flavour_u32_f32
15655 || flavour
== neon_cvt_flavour_s32_f64
15656 || flavour
== neon_cvt_flavour_u32_f64
)
15657 && (rs
== NS_FD
|| rs
== NS_FF
))
15659 do_vfp_nsyn_cvtz ();
15663 /* ARMv8.2 fp16 VCVT conversions. */
15664 if (mode
== neon_cvt_mode_z
15665 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15666 && (flavour
== neon_cvt_flavour_s32_f16
15667 || flavour
== neon_cvt_flavour_u32_f16
)
15670 do_vfp_nsyn_cvtz ();
15671 do_scalar_fp16_v82_encode ();
15675 /* VFP rather than Neon conversions. */
15676 if (flavour
>= neon_cvt_flavour_first_fp
)
15678 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15679 do_vfp_nsyn_cvt (rs
, flavour
);
15681 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15692 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15693 0x0000100, 0x1000100, 0x0, 0x1000000};
15695 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15698 /* Fixed-point conversion with #0 immediate is encoded as an
15699 integer conversion. */
15700 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15702 NEON_ENCODE (IMMED
, inst
);
15703 if (flavour
!= neon_cvt_flavour_invalid
)
15704 inst
.instruction
|= enctab
[flavour
];
15705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15707 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15708 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15709 inst
.instruction
|= neon_quad (rs
) << 6;
15710 inst
.instruction
|= 1 << 21;
15711 if (flavour
< neon_cvt_flavour_s16_f16
)
15713 inst
.instruction
|= 1 << 21;
15714 immbits
= 32 - inst
.operands
[2].imm
;
15715 inst
.instruction
|= immbits
<< 16;
15719 inst
.instruction
|= 3 << 20;
15720 immbits
= 16 - inst
.operands
[2].imm
;
15721 inst
.instruction
|= immbits
<< 16;
15722 inst
.instruction
&= ~(1 << 9);
15725 neon_dp_fixup (&inst
);
15731 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15733 NEON_ENCODE (FLOAT
, inst
);
15734 set_it_insn_type (OUTSIDE_IT_INSN
);
15736 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15739 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15740 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15741 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15742 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15743 inst
.instruction
|= neon_quad (rs
) << 6;
15744 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15745 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15746 inst
.instruction
|= mode
<< 8;
15747 if (flavour
== neon_cvt_flavour_u16_f16
15748 || flavour
== neon_cvt_flavour_s16_f16
)
15749 /* Mask off the original size bits and reencode them. */
15750 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15753 inst
.instruction
|= 0xfc000000;
15755 inst
.instruction
|= 0xf0000000;
15761 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15762 0x100, 0x180, 0x0, 0x080};
15764 NEON_ENCODE (INTEGER
, inst
);
15766 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15769 if (flavour
!= neon_cvt_flavour_invalid
)
15770 inst
.instruction
|= enctab
[flavour
];
15772 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15773 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15774 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15775 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15776 inst
.instruction
|= neon_quad (rs
) << 6;
15777 if (flavour
>= neon_cvt_flavour_s16_f16
15778 && flavour
<= neon_cvt_flavour_f16_u16
)
15779 /* Half precision. */
15780 inst
.instruction
|= 1 << 18;
15782 inst
.instruction
|= 2 << 18;
15784 neon_dp_fixup (&inst
);
15789 /* Half-precision conversions for Advanced SIMD -- neon. */
15794 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15796 as_bad (_("operand size must match register width"));
15801 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15803 as_bad (_("operand size must match register width"));
15808 inst
.instruction
= 0x3b60600;
15810 inst
.instruction
= 0x3b60700;
15812 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15813 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15814 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15815 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15816 neon_dp_fixup (&inst
);
15820 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15821 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15822 do_vfp_nsyn_cvt (rs
, flavour
);
15824 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15829 do_neon_cvtr (void)
15831 do_neon_cvt_1 (neon_cvt_mode_x
);
15837 do_neon_cvt_1 (neon_cvt_mode_z
);
15841 do_neon_cvta (void)
15843 do_neon_cvt_1 (neon_cvt_mode_a
);
15847 do_neon_cvtn (void)
15849 do_neon_cvt_1 (neon_cvt_mode_n
);
15853 do_neon_cvtp (void)
15855 do_neon_cvt_1 (neon_cvt_mode_p
);
15859 do_neon_cvtm (void)
15861 do_neon_cvt_1 (neon_cvt_mode_m
);
15865 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15868 mark_feature_used (&fpu_vfp_ext_armv8
);
15870 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15871 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15872 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15873 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15874 inst
.instruction
|= to
? 0x10000 : 0;
15875 inst
.instruction
|= t
? 0x80 : 0;
15876 inst
.instruction
|= is_double
? 0x100 : 0;
15877 do_vfp_cond_or_thumb ();
15881 do_neon_cvttb_1 (bfd_boolean t
)
15883 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15884 NS_DF
, NS_DH
, NS_NULL
);
15888 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15891 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15893 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15896 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15898 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15900 /* The VCVTB and VCVTT instructions with D-register operands
15901 don't work for SP only targets. */
15902 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15906 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15908 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15910 /* The VCVTB and VCVTT instructions with D-register operands
15911 don't work for SP only targets. */
15912 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15916 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15923 do_neon_cvtb (void)
15925 do_neon_cvttb_1 (FALSE
);
15930 do_neon_cvtt (void)
15932 do_neon_cvttb_1 (TRUE
);
15936 neon_move_immediate (void)
15938 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15939 struct neon_type_el et
= neon_check_type (2, rs
,
15940 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15941 unsigned immlo
, immhi
= 0, immbits
;
15942 int op
, cmode
, float_p
;
15944 constraint (et
.type
== NT_invtype
,
15945 _("operand size must be specified for immediate VMOV"));
15947 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15948 op
= (inst
.instruction
& (1 << 5)) != 0;
15950 immlo
= inst
.operands
[1].imm
;
15951 if (inst
.operands
[1].regisimm
)
15952 immhi
= inst
.operands
[1].reg
;
15954 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15955 _("immediate has bits set outside the operand size"));
15957 float_p
= inst
.operands
[1].immisfloat
;
15959 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15960 et
.size
, et
.type
)) == FAIL
)
15962 /* Invert relevant bits only. */
15963 neon_invert_size (&immlo
, &immhi
, et
.size
);
15964 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15965 with one or the other; those cases are caught by
15966 neon_cmode_for_move_imm. */
15968 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15969 &op
, et
.size
, et
.type
)) == FAIL
)
15971 first_error (_("immediate out of range"));
15976 inst
.instruction
&= ~(1 << 5);
15977 inst
.instruction
|= op
<< 5;
15979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15981 inst
.instruction
|= neon_quad (rs
) << 6;
15982 inst
.instruction
|= cmode
<< 8;
15984 neon_write_immbits (immbits
);
15990 if (inst
.operands
[1].isreg
)
15992 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15994 NEON_ENCODE (INTEGER
, inst
);
15995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15999 inst
.instruction
|= neon_quad (rs
) << 6;
16003 NEON_ENCODE (IMMED
, inst
);
16004 neon_move_immediate ();
16007 neon_dp_fixup (&inst
);
16010 /* Encode instructions of form:
16012 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16013 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16016 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16018 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16019 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16020 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16021 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16022 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16023 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16024 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16025 inst
.instruction
|= neon_logbits (size
) << 20;
16027 neon_dp_fixup (&inst
);
16031 do_neon_dyadic_long (void)
16033 /* FIXME: Type checking for lengthening op. */
16034 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16035 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16036 neon_mixed_length (et
, et
.size
);
16040 do_neon_abal (void)
16042 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16043 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16044 neon_mixed_length (et
, et
.size
);
16048 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16050 if (inst
.operands
[2].isscalar
)
16052 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16053 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16054 NEON_ENCODE (SCALAR
, inst
);
16055 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16059 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16060 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16061 NEON_ENCODE (INTEGER
, inst
);
16062 neon_mixed_length (et
, et
.size
);
16067 do_neon_mac_maybe_scalar_long (void)
16069 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16073 do_neon_dyadic_wide (void)
16075 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16076 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16077 neon_mixed_length (et
, et
.size
);
16081 do_neon_dyadic_narrow (void)
16083 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16084 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16085 /* Operand sign is unimportant, and the U bit is part of the opcode,
16086 so force the operand type to integer. */
16087 et
.type
= NT_integer
;
16088 neon_mixed_length (et
, et
.size
/ 2);
16092 do_neon_mul_sat_scalar_long (void)
16094 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16098 do_neon_vmull (void)
16100 if (inst
.operands
[2].isscalar
)
16101 do_neon_mac_maybe_scalar_long ();
16104 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16105 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16107 if (et
.type
== NT_poly
)
16108 NEON_ENCODE (POLY
, inst
);
16110 NEON_ENCODE (INTEGER
, inst
);
16112 /* For polynomial encoding the U bit must be zero, and the size must
16113 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16114 obviously, as 0b10). */
16117 /* Check we're on the correct architecture. */
16118 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16120 _("Instruction form not available on this architecture.");
16125 neon_mixed_length (et
, et
.size
);
16132 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16133 struct neon_type_el et
= neon_check_type (3, rs
,
16134 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16135 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16137 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16138 _("shift out of range"));
16139 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16140 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16141 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16142 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16143 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16144 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16145 inst
.instruction
|= neon_quad (rs
) << 6;
16146 inst
.instruction
|= imm
<< 8;
16148 neon_dp_fixup (&inst
);
16154 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16155 struct neon_type_el et
= neon_check_type (2, rs
,
16156 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16157 unsigned op
= (inst
.instruction
>> 7) & 3;
16158 /* N (width of reversed regions) is encoded as part of the bitmask. We
16159 extract it here to check the elements to be reversed are smaller.
16160 Otherwise we'd get a reserved instruction. */
16161 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16162 gas_assert (elsize
!= 0);
16163 constraint (et
.size
>= elsize
,
16164 _("elements must be smaller than reversal region"));
16165 neon_two_same (neon_quad (rs
), 1, et
.size
);
16171 if (inst
.operands
[1].isscalar
)
16173 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16174 struct neon_type_el et
= neon_check_type (2, rs
,
16175 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16176 unsigned sizebits
= et
.size
>> 3;
16177 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16178 int logsize
= neon_logbits (et
.size
);
16179 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16181 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16184 NEON_ENCODE (SCALAR
, inst
);
16185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16187 inst
.instruction
|= LOW4 (dm
);
16188 inst
.instruction
|= HI1 (dm
) << 5;
16189 inst
.instruction
|= neon_quad (rs
) << 6;
16190 inst
.instruction
|= x
<< 17;
16191 inst
.instruction
|= sizebits
<< 16;
16193 neon_dp_fixup (&inst
);
16197 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16198 struct neon_type_el et
= neon_check_type (2, rs
,
16199 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16200 /* Duplicate ARM register to lanes of vector. */
16201 NEON_ENCODE (ARMREG
, inst
);
16204 case 8: inst
.instruction
|= 0x400000; break;
16205 case 16: inst
.instruction
|= 0x000020; break;
16206 case 32: inst
.instruction
|= 0x000000; break;
16209 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16212 inst
.instruction
|= neon_quad (rs
) << 21;
16213 /* The encoding for this instruction is identical for the ARM and Thumb
16214 variants, except for the condition field. */
16215 do_vfp_cond_or_thumb ();
16219 /* VMOV has particularly many variations. It can be one of:
16220 0. VMOV<c><q> <Qd>, <Qm>
16221 1. VMOV<c><q> <Dd>, <Dm>
16222 (Register operations, which are VORR with Rm = Rn.)
16223 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16224 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16226 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16227 (ARM register to scalar.)
16228 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16229 (Two ARM registers to vector.)
16230 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16231 (Scalar to ARM register.)
16232 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16233 (Vector to two ARM registers.)
16234 8. VMOV.F32 <Sd>, <Sm>
16235 9. VMOV.F64 <Dd>, <Dm>
16236 (VFP register moves.)
16237 10. VMOV.F32 <Sd>, #imm
16238 11. VMOV.F64 <Dd>, #imm
16239 (VFP float immediate load.)
16240 12. VMOV <Rd>, <Sm>
16241 (VFP single to ARM reg.)
16242 13. VMOV <Sd>, <Rm>
16243 (ARM reg to VFP single.)
16244 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16245 (Two ARM regs to two VFP singles.)
16246 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16247 (Two VFP singles to two ARM regs.)
16249 These cases can be disambiguated using neon_select_shape, except cases 1/9
16250 and 3/11 which depend on the operand type too.
16252 All the encoded bits are hardcoded by this function.
16254 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16255 Cases 5, 7 may be used with VFPv2 and above.
16257 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16258 can specify a type where it doesn't make sense to, and is ignored). */
16263 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16264 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16265 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16266 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16267 struct neon_type_el et
;
16268 const char *ldconst
= 0;
16272 case NS_DD
: /* case 1/9. */
16273 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16274 /* It is not an error here if no type is given. */
16276 if (et
.type
== NT_float
&& et
.size
== 64)
16278 do_vfp_nsyn_opcode ("fcpyd");
16281 /* fall through. */
16283 case NS_QQ
: /* case 0/1. */
16285 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16287 /* The architecture manual I have doesn't explicitly state which
16288 value the U bit should have for register->register moves, but
16289 the equivalent VORR instruction has U = 0, so do that. */
16290 inst
.instruction
= 0x0200110;
16291 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16292 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16293 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16294 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16295 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16296 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16297 inst
.instruction
|= neon_quad (rs
) << 6;
16299 neon_dp_fixup (&inst
);
16303 case NS_DI
: /* case 3/11. */
16304 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16306 if (et
.type
== NT_float
&& et
.size
== 64)
16308 /* case 11 (fconstd). */
16309 ldconst
= "fconstd";
16310 goto encode_fconstd
;
16312 /* fall through. */
16314 case NS_QI
: /* case 2/3. */
16315 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16317 inst
.instruction
= 0x0800010;
16318 neon_move_immediate ();
16319 neon_dp_fixup (&inst
);
16322 case NS_SR
: /* case 4. */
16324 unsigned bcdebits
= 0;
16326 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16327 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16329 /* .<size> is optional here, defaulting to .32. */
16330 if (inst
.vectype
.elems
== 0
16331 && inst
.operands
[0].vectype
.type
== NT_invtype
16332 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16334 inst
.vectype
.el
[0].type
= NT_untyped
;
16335 inst
.vectype
.el
[0].size
= 32;
16336 inst
.vectype
.elems
= 1;
16339 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16340 logsize
= neon_logbits (et
.size
);
16342 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16345 && et
.size
!= 32, _(BAD_FPU
));
16346 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16347 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16351 case 8: bcdebits
= 0x8; break;
16352 case 16: bcdebits
= 0x1; break;
16353 case 32: bcdebits
= 0x0; break;
16357 bcdebits
|= x
<< logsize
;
16359 inst
.instruction
= 0xe000b10;
16360 do_vfp_cond_or_thumb ();
16361 inst
.instruction
|= LOW4 (dn
) << 16;
16362 inst
.instruction
|= HI1 (dn
) << 7;
16363 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16364 inst
.instruction
|= (bcdebits
& 3) << 5;
16365 inst
.instruction
|= (bcdebits
>> 2) << 21;
16369 case NS_DRR
: /* case 5 (fmdrr). */
16370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16373 inst
.instruction
= 0xc400b10;
16374 do_vfp_cond_or_thumb ();
16375 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16376 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16377 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16378 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16381 case NS_RS
: /* case 6. */
16384 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16385 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16386 unsigned abcdebits
= 0;
16388 /* .<dt> is optional here, defaulting to .32. */
16389 if (inst
.vectype
.elems
== 0
16390 && inst
.operands
[0].vectype
.type
== NT_invtype
16391 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16393 inst
.vectype
.el
[0].type
= NT_untyped
;
16394 inst
.vectype
.el
[0].size
= 32;
16395 inst
.vectype
.elems
= 1;
16398 et
= neon_check_type (2, NS_NULL
,
16399 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16400 logsize
= neon_logbits (et
.size
);
16402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16405 && et
.size
!= 32, _(BAD_FPU
));
16406 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16407 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16411 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16412 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16413 case 32: abcdebits
= 0x00; break;
16417 abcdebits
|= x
<< logsize
;
16418 inst
.instruction
= 0xe100b10;
16419 do_vfp_cond_or_thumb ();
16420 inst
.instruction
|= LOW4 (dn
) << 16;
16421 inst
.instruction
|= HI1 (dn
) << 7;
16422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16423 inst
.instruction
|= (abcdebits
& 3) << 5;
16424 inst
.instruction
|= (abcdebits
>> 2) << 21;
16428 case NS_RRD
: /* case 7 (fmrrd). */
16429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16432 inst
.instruction
= 0xc500b10;
16433 do_vfp_cond_or_thumb ();
16434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16435 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16436 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16437 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16440 case NS_FF
: /* case 8 (fcpys). */
16441 do_vfp_nsyn_opcode ("fcpys");
16445 case NS_FI
: /* case 10 (fconsts). */
16446 ldconst
= "fconsts";
16448 if (is_quarter_float (inst
.operands
[1].imm
))
16450 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16451 do_vfp_nsyn_opcode (ldconst
);
16453 /* ARMv8.2 fp16 vmov.f16 instruction. */
16455 do_scalar_fp16_v82_encode ();
16458 first_error (_("immediate out of range"));
16462 case NS_RF
: /* case 12 (fmrs). */
16463 do_vfp_nsyn_opcode ("fmrs");
16464 /* ARMv8.2 fp16 vmov.f16 instruction. */
16466 do_scalar_fp16_v82_encode ();
16470 case NS_FR
: /* case 13 (fmsr). */
16471 do_vfp_nsyn_opcode ("fmsr");
16472 /* ARMv8.2 fp16 vmov.f16 instruction. */
16474 do_scalar_fp16_v82_encode ();
16477 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16478 (one of which is a list), but we have parsed four. Do some fiddling to
16479 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16481 case NS_RRFF
: /* case 14 (fmrrs). */
16482 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16483 _("VFP registers must be adjacent"));
16484 inst
.operands
[2].imm
= 2;
16485 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16486 do_vfp_nsyn_opcode ("fmrrs");
16489 case NS_FFRR
: /* case 15 (fmsrr). */
16490 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16491 _("VFP registers must be adjacent"));
16492 inst
.operands
[1] = inst
.operands
[2];
16493 inst
.operands
[2] = inst
.operands
[3];
16494 inst
.operands
[0].imm
= 2;
16495 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16496 do_vfp_nsyn_opcode ("fmsrr");
16500 /* neon_select_shape has determined that the instruction
16501 shape is wrong and has already set the error message. */
16510 do_neon_rshift_round_imm (void)
16512 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16513 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16514 int imm
= inst
.operands
[2].imm
;
16516 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16519 inst
.operands
[2].present
= 0;
16524 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16525 _("immediate out of range for shift"));
16526 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16531 do_neon_movhf (void)
16533 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16534 constraint (rs
!= NS_HH
, _("invalid suffix"));
16536 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16539 do_vfp_sp_monadic ();
16542 inst
.instruction
|= 0xf0000000;
16546 do_neon_movl (void)
16548 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16549 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16550 unsigned sizebits
= et
.size
>> 3;
16551 inst
.instruction
|= sizebits
<< 19;
16552 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16558 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16559 struct neon_type_el et
= neon_check_type (2, rs
,
16560 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16561 NEON_ENCODE (INTEGER
, inst
);
16562 neon_two_same (neon_quad (rs
), 1, et
.size
);
16566 do_neon_zip_uzp (void)
16568 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16569 struct neon_type_el et
= neon_check_type (2, rs
,
16570 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16571 if (rs
== NS_DD
&& et
.size
== 32)
16573 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16574 inst
.instruction
= N_MNEM_vtrn
;
16578 neon_two_same (neon_quad (rs
), 1, et
.size
);
16582 do_neon_sat_abs_neg (void)
16584 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16585 struct neon_type_el et
= neon_check_type (2, rs
,
16586 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16587 neon_two_same (neon_quad (rs
), 1, et
.size
);
16591 do_neon_pair_long (void)
16593 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16594 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16595 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16596 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16597 neon_two_same (neon_quad (rs
), 1, et
.size
);
16601 do_neon_recip_est (void)
16603 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16604 struct neon_type_el et
= neon_check_type (2, rs
,
16605 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16606 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16607 neon_two_same (neon_quad (rs
), 1, et
.size
);
16613 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16614 struct neon_type_el et
= neon_check_type (2, rs
,
16615 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16616 neon_two_same (neon_quad (rs
), 1, et
.size
);
16622 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16623 struct neon_type_el et
= neon_check_type (2, rs
,
16624 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16625 neon_two_same (neon_quad (rs
), 1, et
.size
);
16631 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16632 struct neon_type_el et
= neon_check_type (2, rs
,
16633 N_EQK
| N_INT
, N_8
| N_KEY
);
16634 neon_two_same (neon_quad (rs
), 1, et
.size
);
16640 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16641 neon_two_same (neon_quad (rs
), 1, -1);
16645 do_neon_tbl_tbx (void)
16647 unsigned listlenbits
;
16648 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16650 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16652 first_error (_("bad list length for table lookup"));
16656 listlenbits
= inst
.operands
[1].imm
- 1;
16657 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16658 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16659 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16660 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16661 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16662 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16663 inst
.instruction
|= listlenbits
<< 8;
16665 neon_dp_fixup (&inst
);
16669 do_neon_ldm_stm (void)
16671 /* P, U and L bits are part of bitmask. */
16672 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16673 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16675 if (inst
.operands
[1].issingle
)
16677 do_vfp_nsyn_ldm_stm (is_dbmode
);
16681 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16682 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16684 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16685 _("register list must contain at least 1 and at most 16 "
16688 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16689 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16693 inst
.instruction
|= offsetbits
;
16695 do_vfp_cond_or_thumb ();
16699 do_neon_ldr_str (void)
16701 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16703 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16704 And is UNPREDICTABLE in thumb mode. */
16706 && inst
.operands
[1].reg
== REG_PC
16707 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16710 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16711 else if (warn_on_deprecated
)
16712 as_tsktsk (_("Use of PC here is deprecated"));
16715 if (inst
.operands
[0].issingle
)
16718 do_vfp_nsyn_opcode ("flds");
16720 do_vfp_nsyn_opcode ("fsts");
16722 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16723 if (inst
.vectype
.el
[0].size
== 16)
16724 do_scalar_fp16_v82_encode ();
16729 do_vfp_nsyn_opcode ("fldd");
16731 do_vfp_nsyn_opcode ("fstd");
16735 /* "interleave" version also handles non-interleaving register VLD1/VST1
16739 do_neon_ld_st_interleave (void)
16741 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16742 N_8
| N_16
| N_32
| N_64
);
16743 unsigned alignbits
= 0;
16745 /* The bits in this table go:
16746 0: register stride of one (0) or two (1)
16747 1,2: register list length, minus one (1, 2, 3, 4).
16748 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16749 We use -1 for invalid entries. */
16750 const int typetable
[] =
16752 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16753 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16754 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16755 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16759 if (et
.type
== NT_invtype
)
16762 if (inst
.operands
[1].immisalign
)
16763 switch (inst
.operands
[1].imm
>> 8)
16765 case 64: alignbits
= 1; break;
16767 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16768 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16769 goto bad_alignment
;
16773 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16774 goto bad_alignment
;
16779 first_error (_("bad alignment"));
16783 inst
.instruction
|= alignbits
<< 4;
16784 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16786 /* Bits [4:6] of the immediate in a list specifier encode register stride
16787 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16788 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16789 up the right value for "type" in a table based on this value and the given
16790 list style, then stick it back. */
16791 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16792 | (((inst
.instruction
>> 8) & 3) << 3);
16794 typebits
= typetable
[idx
];
16796 constraint (typebits
== -1, _("bad list type for instruction"));
16797 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16798 _("bad element type for instruction"));
16800 inst
.instruction
&= ~0xf00;
16801 inst
.instruction
|= typebits
<< 8;
16804 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16805 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16806 otherwise. The variable arguments are a list of pairs of legal (size, align)
16807 values, terminated with -1. */
16810 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16813 int result
= FAIL
, thissize
, thisalign
;
16815 if (!inst
.operands
[1].immisalign
)
16821 va_start (ap
, do_alignment
);
16825 thissize
= va_arg (ap
, int);
16826 if (thissize
== -1)
16828 thisalign
= va_arg (ap
, int);
16830 if (size
== thissize
&& align
== thisalign
)
16833 while (result
!= SUCCESS
);
16837 if (result
== SUCCESS
)
16840 first_error (_("unsupported alignment for instruction"));
16846 do_neon_ld_st_lane (void)
16848 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16849 int align_good
, do_alignment
= 0;
16850 int logsize
= neon_logbits (et
.size
);
16851 int align
= inst
.operands
[1].imm
>> 8;
16852 int n
= (inst
.instruction
>> 8) & 3;
16853 int max_el
= 64 / et
.size
;
16855 if (et
.type
== NT_invtype
)
16858 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16859 _("bad list length"));
16860 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16861 _("scalar index out of range"));
16862 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16864 _("stride of 2 unavailable when element size is 8"));
16868 case 0: /* VLD1 / VST1. */
16869 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16871 if (align_good
== FAIL
)
16875 unsigned alignbits
= 0;
16878 case 16: alignbits
= 0x1; break;
16879 case 32: alignbits
= 0x3; break;
16882 inst
.instruction
|= alignbits
<< 4;
16886 case 1: /* VLD2 / VST2. */
16887 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16888 16, 32, 32, 64, -1);
16889 if (align_good
== FAIL
)
16892 inst
.instruction
|= 1 << 4;
16895 case 2: /* VLD3 / VST3. */
16896 constraint (inst
.operands
[1].immisalign
,
16897 _("can't use alignment with this instruction"));
16900 case 3: /* VLD4 / VST4. */
16901 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16902 16, 64, 32, 64, 32, 128, -1);
16903 if (align_good
== FAIL
)
16907 unsigned alignbits
= 0;
16910 case 8: alignbits
= 0x1; break;
16911 case 16: alignbits
= 0x1; break;
16912 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16915 inst
.instruction
|= alignbits
<< 4;
16922 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16923 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16924 inst
.instruction
|= 1 << (4 + logsize
);
16926 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16927 inst
.instruction
|= logsize
<< 10;
16930 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16933 do_neon_ld_dup (void)
16935 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16936 int align_good
, do_alignment
= 0;
16938 if (et
.type
== NT_invtype
)
16941 switch ((inst
.instruction
>> 8) & 3)
16943 case 0: /* VLD1. */
16944 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16945 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16946 &do_alignment
, 16, 16, 32, 32, -1);
16947 if (align_good
== FAIL
)
16949 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16952 case 2: inst
.instruction
|= 1 << 5; break;
16953 default: first_error (_("bad list length")); return;
16955 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16958 case 1: /* VLD2. */
16959 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16960 &do_alignment
, 8, 16, 16, 32, 32, 64,
16962 if (align_good
== FAIL
)
16964 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16965 _("bad list length"));
16966 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16967 inst
.instruction
|= 1 << 5;
16968 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16971 case 2: /* VLD3. */
16972 constraint (inst
.operands
[1].immisalign
,
16973 _("can't use alignment with this instruction"));
16974 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16975 _("bad list length"));
16976 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16977 inst
.instruction
|= 1 << 5;
16978 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16981 case 3: /* VLD4. */
16983 int align
= inst
.operands
[1].imm
>> 8;
16984 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16985 16, 64, 32, 64, 32, 128, -1);
16986 if (align_good
== FAIL
)
16988 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16989 _("bad list length"));
16990 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16991 inst
.instruction
|= 1 << 5;
16992 if (et
.size
== 32 && align
== 128)
16993 inst
.instruction
|= 0x3 << 6;
16995 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17002 inst
.instruction
|= do_alignment
<< 4;
17005 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17006 apart from bits [11:4]. */
17009 do_neon_ldx_stx (void)
17011 if (inst
.operands
[1].isreg
)
17012 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17014 switch (NEON_LANE (inst
.operands
[0].imm
))
17016 case NEON_INTERLEAVE_LANES
:
17017 NEON_ENCODE (INTERLV
, inst
);
17018 do_neon_ld_st_interleave ();
17021 case NEON_ALL_LANES
:
17022 NEON_ENCODE (DUP
, inst
);
17023 if (inst
.instruction
== N_INV
)
17025 first_error ("only loads support such operands");
17032 NEON_ENCODE (LANE
, inst
);
17033 do_neon_ld_st_lane ();
17036 /* L bit comes from bit mask. */
17037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17041 if (inst
.operands
[1].postind
)
17043 int postreg
= inst
.operands
[1].imm
& 0xf;
17044 constraint (!inst
.operands
[1].immisreg
,
17045 _("post-index must be a register"));
17046 constraint (postreg
== 0xd || postreg
== 0xf,
17047 _("bad register for post-index"));
17048 inst
.instruction
|= postreg
;
17052 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17053 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17054 || inst
.reloc
.exp
.X_add_number
!= 0,
17057 if (inst
.operands
[1].writeback
)
17059 inst
.instruction
|= 0xd;
17062 inst
.instruction
|= 0xf;
17066 inst
.instruction
|= 0xf9000000;
17068 inst
.instruction
|= 0xf4000000;
17073 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17075 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17076 D register operands. */
17077 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17078 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17081 NEON_ENCODE (FPV8
, inst
);
17083 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17085 do_vfp_sp_dyadic ();
17087 /* ARMv8.2 fp16 instruction. */
17089 do_scalar_fp16_v82_encode ();
17092 do_vfp_dp_rd_rn_rm ();
17095 inst
.instruction
|= 0x100;
17097 inst
.instruction
|= 0xf0000000;
17103 set_it_insn_type (OUTSIDE_IT_INSN
);
17105 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17106 first_error (_("invalid instruction shape"));
17112 set_it_insn_type (OUTSIDE_IT_INSN
);
17114 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17117 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17120 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17124 do_vrint_1 (enum neon_cvt_mode mode
)
17126 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17127 struct neon_type_el et
;
17132 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17133 D register operands. */
17134 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17138 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17140 if (et
.type
!= NT_invtype
)
17142 /* VFP encodings. */
17143 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17144 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17145 set_it_insn_type (OUTSIDE_IT_INSN
);
17147 NEON_ENCODE (FPV8
, inst
);
17148 if (rs
== NS_FF
|| rs
== NS_HH
)
17149 do_vfp_sp_monadic ();
17151 do_vfp_dp_rd_rm ();
17155 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17156 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17157 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17158 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17159 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17160 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17161 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17165 inst
.instruction
|= (rs
== NS_DD
) << 8;
17166 do_vfp_cond_or_thumb ();
17168 /* ARMv8.2 fp16 vrint instruction. */
17170 do_scalar_fp16_v82_encode ();
17174 /* Neon encodings (or something broken...). */
17176 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17178 if (et
.type
== NT_invtype
)
17181 set_it_insn_type (OUTSIDE_IT_INSN
);
17182 NEON_ENCODE (FLOAT
, inst
);
17184 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17188 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17189 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17190 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17191 inst
.instruction
|= neon_quad (rs
) << 6;
17192 /* Mask off the original size bits and reencode them. */
17193 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17194 | neon_logbits (et
.size
) << 18);
17198 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17199 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17200 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17201 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17202 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17203 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17204 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17209 inst
.instruction
|= 0xfc000000;
17211 inst
.instruction
|= 0xf0000000;
17218 do_vrint_1 (neon_cvt_mode_x
);
17224 do_vrint_1 (neon_cvt_mode_z
);
17230 do_vrint_1 (neon_cvt_mode_r
);
17236 do_vrint_1 (neon_cvt_mode_a
);
17242 do_vrint_1 (neon_cvt_mode_n
);
17248 do_vrint_1 (neon_cvt_mode_p
);
17254 do_vrint_1 (neon_cvt_mode_m
);
17257 /* Crypto v1 instructions. */
17259 do_crypto_2op_1 (unsigned elttype
, int op
)
17261 set_it_insn_type (OUTSIDE_IT_INSN
);
17263 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17269 NEON_ENCODE (INTEGER
, inst
);
17270 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17271 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17272 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17273 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17275 inst
.instruction
|= op
<< 6;
17278 inst
.instruction
|= 0xfc000000;
17280 inst
.instruction
|= 0xf0000000;
17284 do_crypto_3op_1 (int u
, int op
)
17286 set_it_insn_type (OUTSIDE_IT_INSN
);
17288 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17289 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17294 NEON_ENCODE (INTEGER
, inst
);
17295 neon_three_same (1, u
, 8 << op
);
17301 do_crypto_2op_1 (N_8
, 0);
17307 do_crypto_2op_1 (N_8
, 1);
17313 do_crypto_2op_1 (N_8
, 2);
17319 do_crypto_2op_1 (N_8
, 3);
17325 do_crypto_3op_1 (0, 0);
17331 do_crypto_3op_1 (0, 1);
17337 do_crypto_3op_1 (0, 2);
17343 do_crypto_3op_1 (0, 3);
17349 do_crypto_3op_1 (1, 0);
17355 do_crypto_3op_1 (1, 1);
17359 do_sha256su1 (void)
17361 do_crypto_3op_1 (1, 2);
17367 do_crypto_2op_1 (N_32
, -1);
17373 do_crypto_2op_1 (N_32
, 0);
17377 do_sha256su0 (void)
17379 do_crypto_2op_1 (N_32
, 1);
17383 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17385 unsigned int Rd
= inst
.operands
[0].reg
;
17386 unsigned int Rn
= inst
.operands
[1].reg
;
17387 unsigned int Rm
= inst
.operands
[2].reg
;
17389 set_it_insn_type (OUTSIDE_IT_INSN
);
17390 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17391 inst
.instruction
|= LOW4 (Rn
) << 16;
17392 inst
.instruction
|= LOW4 (Rm
);
17393 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17394 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17396 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17397 as_warn (UNPRED_REG ("r15"));
17398 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17399 as_warn (UNPRED_REG ("r13"));
17439 /* Overall per-instruction processing. */
17441 /* We need to be able to fix up arbitrary expressions in some statements.
17442 This is so that we can handle symbols that are an arbitrary distance from
17443 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17444 which returns part of an address in a form which will be valid for
17445 a data instruction. We do this by pushing the expression into a symbol
17446 in the expr_section, and creating a fix for that. */
17449 fix_new_arm (fragS
* frag
,
17463 /* Create an absolute valued symbol, so we have something to
17464 refer to in the object file. Unfortunately for us, gas's
17465 generic expression parsing will already have folded out
17466 any use of .set foo/.type foo %function that may have
17467 been used to set type information of the target location,
17468 that's being specified symbolically. We have to presume
17469 the user knows what they are doing. */
17473 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17475 symbol
= symbol_find_or_make (name
);
17476 S_SET_SEGMENT (symbol
, absolute_section
);
17477 symbol_set_frag (symbol
, &zero_address_frag
);
17478 S_SET_VALUE (symbol
, exp
->X_add_number
);
17479 exp
->X_op
= O_symbol
;
17480 exp
->X_add_symbol
= symbol
;
17481 exp
->X_add_number
= 0;
17487 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17488 (enum bfd_reloc_code_real
) reloc
);
17492 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17493 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17497 /* Mark whether the fix is to a THUMB instruction, or an ARM
17499 new_fix
->tc_fix_data
= thumb_mode
;
17502 /* Create a frg for an instruction requiring relaxation. */
17504 output_relax_insn (void)
17510 /* The size of the instruction is unknown, so tie the debug info to the
17511 start of the instruction. */
17512 dwarf2_emit_insn (0);
17514 switch (inst
.reloc
.exp
.X_op
)
17517 sym
= inst
.reloc
.exp
.X_add_symbol
;
17518 offset
= inst
.reloc
.exp
.X_add_number
;
17522 offset
= inst
.reloc
.exp
.X_add_number
;
17525 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17529 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17530 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17531 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17534 /* Write a 32-bit thumb instruction to buf. */
17536 put_thumb32_insn (char * buf
, unsigned long insn
)
17538 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17539 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17543 output_inst (const char * str
)
17549 as_bad ("%s -- `%s'", inst
.error
, str
);
17554 output_relax_insn ();
17557 if (inst
.size
== 0)
17560 to
= frag_more (inst
.size
);
17561 /* PR 9814: Record the thumb mode into the current frag so that we know
17562 what type of NOP padding to use, if necessary. We override any previous
17563 setting so that if the mode has changed then the NOPS that we use will
17564 match the encoding of the last instruction in the frag. */
17565 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17567 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17569 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17570 put_thumb32_insn (to
, inst
.instruction
);
17572 else if (inst
.size
> INSN_SIZE
)
17574 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17575 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17576 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17579 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17581 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17582 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17583 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17586 dwarf2_emit_insn (inst
.size
);
17590 output_it_inst (int cond
, int mask
, char * to
)
17592 unsigned long instruction
= 0xbf00;
17595 instruction
|= mask
;
17596 instruction
|= cond
<< 4;
17600 to
= frag_more (2);
17602 dwarf2_emit_insn (2);
17606 md_number_to_chars (to
, instruction
, 2);
17611 /* Tag values used in struct asm_opcode's tag field. */
17614 OT_unconditional
, /* Instruction cannot be conditionalized.
17615 The ARM condition field is still 0xE. */
17616 OT_unconditionalF
, /* Instruction cannot be conditionalized
17617 and carries 0xF in its ARM condition field. */
17618 OT_csuffix
, /* Instruction takes a conditional suffix. */
17619 OT_csuffixF
, /* Some forms of the instruction take a conditional
17620 suffix, others place 0xF where the condition field
17622 OT_cinfix3
, /* Instruction takes a conditional infix,
17623 beginning at character index 3. (In
17624 unified mode, it becomes a suffix.) */
17625 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17626 tsts, cmps, cmns, and teqs. */
17627 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17628 character index 3, even in unified mode. Used for
17629 legacy instructions where suffix and infix forms
17630 may be ambiguous. */
17631 OT_csuf_or_in3
, /* Instruction takes either a conditional
17632 suffix or an infix at character index 3. */
17633 OT_odd_infix_unc
, /* This is the unconditional variant of an
17634 instruction that takes a conditional infix
17635 at an unusual position. In unified mode,
17636 this variant will accept a suffix. */
17637 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17638 are the conditional variants of instructions that
17639 take conditional infixes in unusual positions.
17640 The infix appears at character index
17641 (tag - OT_odd_infix_0). These are not accepted
17642 in unified mode. */
17645 /* Subroutine of md_assemble, responsible for looking up the primary
17646 opcode from the mnemonic the user wrote. STR points to the
17647 beginning of the mnemonic.
17649 This is not simply a hash table lookup, because of conditional
17650 variants. Most instructions have conditional variants, which are
17651 expressed with a _conditional affix_ to the mnemonic. If we were
17652 to encode each conditional variant as a literal string in the opcode
17653 table, it would have approximately 20,000 entries.
17655 Most mnemonics take this affix as a suffix, and in unified syntax,
17656 'most' is upgraded to 'all'. However, in the divided syntax, some
17657 instructions take the affix as an infix, notably the s-variants of
17658 the arithmetic instructions. Of those instructions, all but six
17659 have the infix appear after the third character of the mnemonic.
17661 Accordingly, the algorithm for looking up primary opcodes given
17664 1. Look up the identifier in the opcode table.
17665 If we find a match, go to step U.
17667 2. Look up the last two characters of the identifier in the
17668 conditions table. If we find a match, look up the first N-2
17669 characters of the identifier in the opcode table. If we
17670 find a match, go to step CE.
17672 3. Look up the fourth and fifth characters of the identifier in
17673 the conditions table. If we find a match, extract those
17674 characters from the identifier, and look up the remaining
17675 characters in the opcode table. If we find a match, go
17680 U. Examine the tag field of the opcode structure, in case this is
17681 one of the six instructions with its conditional infix in an
17682 unusual place. If it is, the tag tells us where to find the
17683 infix; look it up in the conditions table and set inst.cond
17684 accordingly. Otherwise, this is an unconditional instruction.
17685 Again set inst.cond accordingly. Return the opcode structure.
17687 CE. Examine the tag field to make sure this is an instruction that
17688 should receive a conditional suffix. If it is not, fail.
17689 Otherwise, set inst.cond from the suffix we already looked up,
17690 and return the opcode structure.
17692 CM. Examine the tag field to make sure this is an instruction that
17693 should receive a conditional infix after the third character.
17694 If it is not, fail. Otherwise, undo the edits to the current
17695 line of input and proceed as for case CE. */
17697 static const struct asm_opcode
*
17698 opcode_lookup (char **str
)
17702 const struct asm_opcode
*opcode
;
17703 const struct asm_cond
*cond
;
17706 /* Scan up to the end of the mnemonic, which must end in white space,
17707 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17708 for (base
= end
= *str
; *end
!= '\0'; end
++)
17709 if (*end
== ' ' || *end
== '.')
17715 /* Handle a possible width suffix and/or Neon type suffix. */
17720 /* The .w and .n suffixes are only valid if the unified syntax is in
17722 if (unified_syntax
&& end
[1] == 'w')
17724 else if (unified_syntax
&& end
[1] == 'n')
17729 inst
.vectype
.elems
= 0;
17731 *str
= end
+ offset
;
17733 if (end
[offset
] == '.')
17735 /* See if we have a Neon type suffix (possible in either unified or
17736 non-unified ARM syntax mode). */
17737 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17740 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17746 /* Look for unaffixed or special-case affixed mnemonic. */
17747 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17752 if (opcode
->tag
< OT_odd_infix_0
)
17754 inst
.cond
= COND_ALWAYS
;
17758 if (warn_on_deprecated
&& unified_syntax
)
17759 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17760 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17761 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17764 inst
.cond
= cond
->value
;
17768 /* Cannot have a conditional suffix on a mnemonic of less than two
17770 if (end
- base
< 3)
17773 /* Look for suffixed mnemonic. */
17775 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17776 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17778 if (opcode
&& cond
)
17781 switch (opcode
->tag
)
17783 case OT_cinfix3_legacy
:
17784 /* Ignore conditional suffixes matched on infix only mnemonics. */
17788 case OT_cinfix3_deprecated
:
17789 case OT_odd_infix_unc
:
17790 if (!unified_syntax
)
17792 /* Fall through. */
17796 case OT_csuf_or_in3
:
17797 inst
.cond
= cond
->value
;
17800 case OT_unconditional
:
17801 case OT_unconditionalF
:
17803 inst
.cond
= cond
->value
;
17806 /* Delayed diagnostic. */
17807 inst
.error
= BAD_COND
;
17808 inst
.cond
= COND_ALWAYS
;
17817 /* Cannot have a usual-position infix on a mnemonic of less than
17818 six characters (five would be a suffix). */
17819 if (end
- base
< 6)
17822 /* Look for infixed mnemonic in the usual position. */
17824 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17828 memcpy (save
, affix
, 2);
17829 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17830 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17832 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17833 memcpy (affix
, save
, 2);
17836 && (opcode
->tag
== OT_cinfix3
17837 || opcode
->tag
== OT_cinfix3_deprecated
17838 || opcode
->tag
== OT_csuf_or_in3
17839 || opcode
->tag
== OT_cinfix3_legacy
))
17842 if (warn_on_deprecated
&& unified_syntax
17843 && (opcode
->tag
== OT_cinfix3
17844 || opcode
->tag
== OT_cinfix3_deprecated
))
17845 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17847 inst
.cond
= cond
->value
;
17854 /* This function generates an initial IT instruction, leaving its block
17855 virtually open for the new instructions. Eventually,
17856 the mask will be updated by now_it_add_mask () each time
17857 a new instruction needs to be included in the IT block.
17858 Finally, the block is closed with close_automatic_it_block ().
17859 The block closure can be requested either from md_assemble (),
17860 a tencode (), or due to a label hook. */
17863 new_automatic_it_block (int cond
)
17865 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17866 now_it
.mask
= 0x18;
17868 now_it
.block_length
= 1;
17869 mapping_state (MAP_THUMB
);
17870 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17871 now_it
.warn_deprecated
= FALSE
;
17872 now_it
.insn_cond
= TRUE
;
17875 /* Close an automatic IT block.
17876 See comments in new_automatic_it_block (). */
17879 close_automatic_it_block (void)
17881 now_it
.mask
= 0x10;
17882 now_it
.block_length
= 0;
17885 /* Update the mask of the current automatically-generated IT
17886 instruction. See comments in new_automatic_it_block (). */
17889 now_it_add_mask (int cond
)
17891 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17892 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17893 | ((bitvalue) << (nbit)))
17894 const int resulting_bit
= (cond
& 1);
17896 now_it
.mask
&= 0xf;
17897 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17899 (5 - now_it
.block_length
));
17900 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17902 ((5 - now_it
.block_length
) - 1) );
17903 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17906 #undef SET_BIT_VALUE
17909 /* The IT blocks handling machinery is accessed through the these functions:
17910 it_fsm_pre_encode () from md_assemble ()
17911 set_it_insn_type () optional, from the tencode functions
17912 set_it_insn_type_last () ditto
17913 in_it_block () ditto
17914 it_fsm_post_encode () from md_assemble ()
17915 force_automatic_it_block_close () from label habdling functions
17918 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17919 initializing the IT insn type with a generic initial value depending
17920 on the inst.condition.
17921 2) During the tencode function, two things may happen:
17922 a) The tencode function overrides the IT insn type by
17923 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17924 b) The tencode function queries the IT block state by
17925 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17927 Both set_it_insn_type and in_it_block run the internal FSM state
17928 handling function (handle_it_state), because: a) setting the IT insn
17929 type may incur in an invalid state (exiting the function),
17930 and b) querying the state requires the FSM to be updated.
17931 Specifically we want to avoid creating an IT block for conditional
17932 branches, so it_fsm_pre_encode is actually a guess and we can't
17933 determine whether an IT block is required until the tencode () routine
17934 has decided what type of instruction this actually it.
17935 Because of this, if set_it_insn_type and in_it_block have to be used,
17936 set_it_insn_type has to be called first.
17938 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17939 determines the insn IT type depending on the inst.cond code.
17940 When a tencode () routine encodes an instruction that can be
17941 either outside an IT block, or, in the case of being inside, has to be
17942 the last one, set_it_insn_type_last () will determine the proper
17943 IT instruction type based on the inst.cond code. Otherwise,
17944 set_it_insn_type can be called for overriding that logic or
17945 for covering other cases.
17947 Calling handle_it_state () may not transition the IT block state to
17948 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17949 still queried. Instead, if the FSM determines that the state should
17950 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17951 after the tencode () function: that's what it_fsm_post_encode () does.
17953 Since in_it_block () calls the state handling function to get an
17954 updated state, an error may occur (due to invalid insns combination).
17955 In that case, inst.error is set.
17956 Therefore, inst.error has to be checked after the execution of
17957 the tencode () routine.
17959 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17960 any pending state change (if any) that didn't take place in
17961 handle_it_state () as explained above. */
17964 it_fsm_pre_encode (void)
17966 if (inst
.cond
!= COND_ALWAYS
)
17967 inst
.it_insn_type
= INSIDE_IT_INSN
;
17969 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17971 now_it
.state_handled
= 0;
17974 /* IT state FSM handling function. */
17977 handle_it_state (void)
17979 now_it
.state_handled
= 1;
17980 now_it
.insn_cond
= FALSE
;
17982 switch (now_it
.state
)
17984 case OUTSIDE_IT_BLOCK
:
17985 switch (inst
.it_insn_type
)
17987 case OUTSIDE_IT_INSN
:
17990 case INSIDE_IT_INSN
:
17991 case INSIDE_IT_LAST_INSN
:
17992 if (thumb_mode
== 0)
17995 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17996 as_tsktsk (_("Warning: conditional outside an IT block"\
18001 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18002 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18004 /* Automatically generate the IT instruction. */
18005 new_automatic_it_block (inst
.cond
);
18006 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18007 close_automatic_it_block ();
18011 inst
.error
= BAD_OUT_IT
;
18017 case IF_INSIDE_IT_LAST_INSN
:
18018 case NEUTRAL_IT_INSN
:
18022 now_it
.state
= MANUAL_IT_BLOCK
;
18023 now_it
.block_length
= 0;
18028 case AUTOMATIC_IT_BLOCK
:
18029 /* Three things may happen now:
18030 a) We should increment current it block size;
18031 b) We should close current it block (closing insn or 4 insns);
18032 c) We should close current it block and start a new one (due
18033 to incompatible conditions or
18034 4 insns-length block reached). */
18036 switch (inst
.it_insn_type
)
18038 case OUTSIDE_IT_INSN
:
18039 /* The closure of the block shall happen immediatelly,
18040 so any in_it_block () call reports the block as closed. */
18041 force_automatic_it_block_close ();
18044 case INSIDE_IT_INSN
:
18045 case INSIDE_IT_LAST_INSN
:
18046 case IF_INSIDE_IT_LAST_INSN
:
18047 now_it
.block_length
++;
18049 if (now_it
.block_length
> 4
18050 || !now_it_compatible (inst
.cond
))
18052 force_automatic_it_block_close ();
18053 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18054 new_automatic_it_block (inst
.cond
);
18058 now_it
.insn_cond
= TRUE
;
18059 now_it_add_mask (inst
.cond
);
18062 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18063 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18064 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18065 close_automatic_it_block ();
18068 case NEUTRAL_IT_INSN
:
18069 now_it
.block_length
++;
18070 now_it
.insn_cond
= TRUE
;
18072 if (now_it
.block_length
> 4)
18073 force_automatic_it_block_close ();
18075 now_it_add_mask (now_it
.cc
& 1);
18079 close_automatic_it_block ();
18080 now_it
.state
= MANUAL_IT_BLOCK
;
18085 case MANUAL_IT_BLOCK
:
18087 /* Check conditional suffixes. */
18088 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18091 now_it
.mask
&= 0x1f;
18092 is_last
= (now_it
.mask
== 0x10);
18093 now_it
.insn_cond
= TRUE
;
18095 switch (inst
.it_insn_type
)
18097 case OUTSIDE_IT_INSN
:
18098 inst
.error
= BAD_NOT_IT
;
18101 case INSIDE_IT_INSN
:
18102 if (cond
!= inst
.cond
)
18104 inst
.error
= BAD_IT_COND
;
18109 case INSIDE_IT_LAST_INSN
:
18110 case IF_INSIDE_IT_LAST_INSN
:
18111 if (cond
!= inst
.cond
)
18113 inst
.error
= BAD_IT_COND
;
18118 inst
.error
= BAD_BRANCH
;
18123 case NEUTRAL_IT_INSN
:
18124 /* The BKPT instruction is unconditional even in an IT block. */
18128 inst
.error
= BAD_IT_IT
;
18138 struct depr_insn_mask
18140 unsigned long pattern
;
18141 unsigned long mask
;
18142 const char* description
;
18145 /* List of 16-bit instruction patterns deprecated in an IT block in
18147 static const struct depr_insn_mask depr_it_insns
[] = {
18148 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18149 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18150 { 0xa000, 0xb800, N_("ADR") },
18151 { 0x4800, 0xf800, N_("Literal loads") },
18152 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18153 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18154 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18155 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18156 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18161 it_fsm_post_encode (void)
18165 if (!now_it
.state_handled
)
18166 handle_it_state ();
18168 if (now_it
.insn_cond
18169 && !now_it
.warn_deprecated
18170 && warn_on_deprecated
18171 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18173 if (inst
.instruction
>= 0x10000)
18175 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18176 "deprecated in ARMv8"));
18177 now_it
.warn_deprecated
= TRUE
;
18181 const struct depr_insn_mask
*p
= depr_it_insns
;
18183 while (p
->mask
!= 0)
18185 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18187 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18188 "of the following class are deprecated in ARMv8: "
18189 "%s"), p
->description
);
18190 now_it
.warn_deprecated
= TRUE
;
18198 if (now_it
.block_length
> 1)
18200 as_tsktsk (_("IT blocks containing more than one conditional "
18201 "instruction are deprecated in ARMv8"));
18202 now_it
.warn_deprecated
= TRUE
;
18206 is_last
= (now_it
.mask
== 0x10);
18209 now_it
.state
= OUTSIDE_IT_BLOCK
;
18215 force_automatic_it_block_close (void)
18217 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18219 close_automatic_it_block ();
18220 now_it
.state
= OUTSIDE_IT_BLOCK
;
18228 if (!now_it
.state_handled
)
18229 handle_it_state ();
18231 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18234 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18235 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18236 here, hence the "known" in the function name. */
18239 known_t32_only_insn (const struct asm_opcode
*opcode
)
18241 /* Original Thumb-1 wide instruction. */
18242 if (opcode
->tencode
== do_t_blx
18243 || opcode
->tencode
== do_t_branch23
18244 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18245 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18248 /* Wide-only instruction added to ARMv8-M Baseline. */
18249 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18250 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18251 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18252 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18258 /* Whether wide instruction variant can be used if available for a valid OPCODE
18262 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18264 if (known_t32_only_insn (opcode
))
18267 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18268 of variant T3 of B.W is checked in do_t_branch. */
18269 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18270 && opcode
->tencode
== do_t_branch
)
18273 /* Wide instruction variants of all instructions with narrow *and* wide
18274 variants become available with ARMv6t2. Other opcodes are either
18275 narrow-only or wide-only and are thus available if OPCODE is valid. */
18276 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18279 /* OPCODE with narrow only instruction variant or wide variant not
18285 md_assemble (char *str
)
18288 const struct asm_opcode
* opcode
;
18290 /* Align the previous label if needed. */
18291 if (last_label_seen
!= NULL
)
18293 symbol_set_frag (last_label_seen
, frag_now
);
18294 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18295 S_SET_SEGMENT (last_label_seen
, now_seg
);
18298 memset (&inst
, '\0', sizeof (inst
));
18299 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18301 opcode
= opcode_lookup (&p
);
18304 /* It wasn't an instruction, but it might be a register alias of
18305 the form alias .req reg, or a Neon .dn/.qn directive. */
18306 if (! create_register_alias (str
, p
)
18307 && ! create_neon_reg_alias (str
, p
))
18308 as_bad (_("bad instruction `%s'"), str
);
18313 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18314 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18316 /* The value which unconditional instructions should have in place of the
18317 condition field. */
18318 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18322 arm_feature_set variant
;
18324 variant
= cpu_variant
;
18325 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18326 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18327 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18328 /* Check that this instruction is supported for this CPU. */
18329 if (!opcode
->tvariant
18330 || (thumb_mode
== 1
18331 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18333 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18336 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18337 && opcode
->tencode
!= do_t_branch
)
18339 as_bad (_("Thumb does not support conditional execution"));
18343 /* Two things are addressed here:
18344 1) Implicit require narrow instructions on Thumb-1.
18345 This avoids relaxation accidentally introducing Thumb-2
18347 2) Reject wide instructions in non Thumb-2 cores.
18349 Only instructions with narrow and wide variants need to be handled
18350 but selecting all non wide-only instructions is easier. */
18351 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18352 && !t32_insn_ok (variant
, opcode
))
18354 if (inst
.size_req
== 0)
18356 else if (inst
.size_req
== 4)
18358 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18359 as_bad (_("selected processor does not support 32bit wide "
18360 "variant of instruction `%s'"), str
);
18362 as_bad (_("selected processor does not support `%s' in "
18363 "Thumb-2 mode"), str
);
18368 inst
.instruction
= opcode
->tvalue
;
18370 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18372 /* Prepare the it_insn_type for those encodings that don't set
18374 it_fsm_pre_encode ();
18376 opcode
->tencode ();
18378 it_fsm_post_encode ();
18381 if (!(inst
.error
|| inst
.relax
))
18383 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18384 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18385 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18387 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18392 /* Something has gone badly wrong if we try to relax a fixed size
18394 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18396 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18397 *opcode
->tvariant
);
18398 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18399 set those bits when Thumb-2 32-bit instructions are seen. The impact
18400 of relaxable instructions will be considered later after we finish all
18402 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18403 variant
= arm_arch_none
;
18405 variant
= cpu_variant
;
18406 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18407 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18410 check_neon_suffixes
;
18414 mapping_state (MAP_THUMB
);
18417 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18421 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18422 is_bx
= (opcode
->aencode
== do_bx
);
18424 /* Check that this instruction is supported for this CPU. */
18425 if (!(is_bx
&& fix_v4bx
)
18426 && !(opcode
->avariant
&&
18427 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18429 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18434 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18438 inst
.instruction
= opcode
->avalue
;
18439 if (opcode
->tag
== OT_unconditionalF
)
18440 inst
.instruction
|= 0xFU
<< 28;
18442 inst
.instruction
|= inst
.cond
<< 28;
18443 inst
.size
= INSN_SIZE
;
18444 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18446 it_fsm_pre_encode ();
18447 opcode
->aencode ();
18448 it_fsm_post_encode ();
18450 /* Arm mode bx is marked as both v4T and v5 because it's still required
18451 on a hypothetical non-thumb v5 core. */
18453 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18455 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18456 *opcode
->avariant
);
18458 check_neon_suffixes
;
18462 mapping_state (MAP_ARM
);
18467 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18475 check_it_blocks_finished (void)
18480 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18481 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18482 == MANUAL_IT_BLOCK
)
18484 as_warn (_("section '%s' finished with an open IT block."),
18488 if (now_it
.state
== MANUAL_IT_BLOCK
)
18489 as_warn (_("file finished with an open IT block."));
18493 /* Various frobbings of labels and their addresses. */
18496 arm_start_line_hook (void)
18498 last_label_seen
= NULL
;
18502 arm_frob_label (symbolS
* sym
)
18504 last_label_seen
= sym
;
18506 ARM_SET_THUMB (sym
, thumb_mode
);
18508 #if defined OBJ_COFF || defined OBJ_ELF
18509 ARM_SET_INTERWORK (sym
, support_interwork
);
18512 force_automatic_it_block_close ();
18514 /* Note - do not allow local symbols (.Lxxx) to be labelled
18515 as Thumb functions. This is because these labels, whilst
18516 they exist inside Thumb code, are not the entry points for
18517 possible ARM->Thumb calls. Also, these labels can be used
18518 as part of a computed goto or switch statement. eg gcc
18519 can generate code that looks like this:
18521 ldr r2, [pc, .Laaa]
18531 The first instruction loads the address of the jump table.
18532 The second instruction converts a table index into a byte offset.
18533 The third instruction gets the jump address out of the table.
18534 The fourth instruction performs the jump.
18536 If the address stored at .Laaa is that of a symbol which has the
18537 Thumb_Func bit set, then the linker will arrange for this address
18538 to have the bottom bit set, which in turn would mean that the
18539 address computation performed by the third instruction would end
18540 up with the bottom bit set. Since the ARM is capable of unaligned
18541 word loads, the instruction would then load the incorrect address
18542 out of the jump table, and chaos would ensue. */
18543 if (label_is_thumb_function_name
18544 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18545 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18547 /* When the address of a Thumb function is taken the bottom
18548 bit of that address should be set. This will allow
18549 interworking between Arm and Thumb functions to work
18552 THUMB_SET_FUNC (sym
, 1);
18554 label_is_thumb_function_name
= FALSE
;
18557 dwarf2_emit_label (sym
);
18561 arm_data_in_code (void)
18563 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18565 *input_line_pointer
= '/';
18566 input_line_pointer
+= 5;
18567 *input_line_pointer
= 0;
18575 arm_canonicalize_symbol_name (char * name
)
18579 if (thumb_mode
&& (len
= strlen (name
)) > 5
18580 && streq (name
+ len
- 5, "/data"))
18581 *(name
+ len
- 5) = 0;
18586 /* Table of all register names defined by default. The user can
18587 define additional names with .req. Note that all register names
18588 should appear in both upper and lowercase variants. Some registers
18589 also have mixed-case names. */
18591 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18592 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18593 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18594 #define REGSET(p,t) \
18595 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18596 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18597 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18598 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18599 #define REGSETH(p,t) \
18600 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18601 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18602 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18603 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18604 #define REGSET2(p,t) \
18605 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18606 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18607 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18608 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18609 #define SPLRBANK(base,bank,t) \
18610 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18611 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18612 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18613 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18614 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18615 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18617 static const struct reg_entry reg_names
[] =
18619 /* ARM integer registers. */
18620 REGSET(r
, RN
), REGSET(R
, RN
),
18622 /* ATPCS synonyms. */
18623 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18624 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18625 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18627 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18628 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18629 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18631 /* Well-known aliases. */
18632 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18633 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18635 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18636 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18638 /* Coprocessor numbers. */
18639 REGSET(p
, CP
), REGSET(P
, CP
),
18641 /* Coprocessor register numbers. The "cr" variants are for backward
18643 REGSET(c
, CN
), REGSET(C
, CN
),
18644 REGSET(cr
, CN
), REGSET(CR
, CN
),
18646 /* ARM banked registers. */
18647 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18648 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18649 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18650 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18651 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18652 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18653 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18655 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18656 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18657 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18658 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18659 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18660 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18661 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18662 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18664 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18665 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18666 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18667 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18668 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18669 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18670 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18671 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18672 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18674 /* FPA registers. */
18675 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18676 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18678 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18679 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18681 /* VFP SP registers. */
18682 REGSET(s
,VFS
), REGSET(S
,VFS
),
18683 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18685 /* VFP DP Registers. */
18686 REGSET(d
,VFD
), REGSET(D
,VFD
),
18687 /* Extra Neon DP registers. */
18688 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18690 /* Neon QP registers. */
18691 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18693 /* VFP control registers. */
18694 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18695 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18696 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18697 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18698 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18699 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18701 /* Maverick DSP coprocessor registers. */
18702 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18703 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18705 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18706 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18707 REGDEF(dspsc
,0,DSPSC
),
18709 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18710 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18711 REGDEF(DSPSC
,0,DSPSC
),
18713 /* iWMMXt data registers - p0, c0-15. */
18714 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18716 /* iWMMXt control registers - p1, c0-3. */
18717 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18718 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18719 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18720 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18722 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18723 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18724 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18725 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18726 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18728 /* XScale accumulator registers. */
18729 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18735 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18736 within psr_required_here. */
18737 static const struct asm_psr psrs
[] =
18739 /* Backward compatibility notation. Note that "all" is no longer
18740 truly all possible PSR bits. */
18741 {"all", PSR_c
| PSR_f
},
18745 /* Individual flags. */
18751 /* Combinations of flags. */
18752 {"fs", PSR_f
| PSR_s
},
18753 {"fx", PSR_f
| PSR_x
},
18754 {"fc", PSR_f
| PSR_c
},
18755 {"sf", PSR_s
| PSR_f
},
18756 {"sx", PSR_s
| PSR_x
},
18757 {"sc", PSR_s
| PSR_c
},
18758 {"xf", PSR_x
| PSR_f
},
18759 {"xs", PSR_x
| PSR_s
},
18760 {"xc", PSR_x
| PSR_c
},
18761 {"cf", PSR_c
| PSR_f
},
18762 {"cs", PSR_c
| PSR_s
},
18763 {"cx", PSR_c
| PSR_x
},
18764 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18765 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18766 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18767 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18768 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18769 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18770 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18771 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18772 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18773 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18774 {"scf", PSR_s
| PSR_c
| PSR_f
},
18775 {"scx", PSR_s
| PSR_c
| PSR_x
},
18776 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18777 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18778 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18779 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18780 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18781 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18782 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18783 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18784 {"csf", PSR_c
| PSR_s
| PSR_f
},
18785 {"csx", PSR_c
| PSR_s
| PSR_x
},
18786 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18787 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18788 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18789 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18790 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18791 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18792 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18793 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18794 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18795 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18796 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18797 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18798 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18799 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18800 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18801 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18802 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18803 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18804 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18805 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18806 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18807 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18808 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18809 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18810 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18811 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18814 /* Table of V7M psr names. */
18815 static const struct asm_psr v7m_psrs
[] =
18817 {"apsr", 0x0 }, {"APSR", 0x0 },
18818 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18819 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18820 {"psr", 0x3 }, {"PSR", 0x3 },
18821 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18822 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18823 {"epsr", 0x6 }, {"EPSR", 0x6 },
18824 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18825 {"msp", 0x8 }, {"MSP", 0x8 },
18826 {"psp", 0x9 }, {"PSP", 0x9 },
18827 {"msplim", 0xa }, {"MSPLIM", 0xa },
18828 {"psplim", 0xb }, {"PSPLIM", 0xb },
18829 {"primask", 0x10}, {"PRIMASK", 0x10},
18830 {"basepri", 0x11}, {"BASEPRI", 0x11},
18831 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18832 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18833 {"control", 0x14}, {"CONTROL", 0x14},
18834 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18835 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18836 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18837 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18838 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18839 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18840 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18841 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18842 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18845 /* Table of all shift-in-operand names. */
18846 static const struct asm_shift_name shift_names
[] =
18848 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18849 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18850 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18851 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18852 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18853 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18856 /* Table of all explicit relocation names. */
18858 static struct reloc_entry reloc_names
[] =
18860 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18861 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18862 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18863 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18864 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18865 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18866 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18867 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18868 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18869 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18870 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18871 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18872 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18873 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18874 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18875 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18876 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18877 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18881 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18882 static const struct asm_cond conds
[] =
18886 {"cs", 0x2}, {"hs", 0x2},
18887 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18901 #define UL_BARRIER(L,U,CODE,FEAT) \
18902 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18903 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18905 static struct asm_barrier_opt barrier_opt_names
[] =
18907 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18908 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18909 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18910 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18911 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18912 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18913 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18914 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18915 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18916 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18917 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18918 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18919 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18920 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18921 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18922 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18927 /* Table of ARM-format instructions. */
18929 /* Macros for gluing together operand strings. N.B. In all cases
18930 other than OPS0, the trailing OP_stop comes from default
18931 zero-initialization of the unspecified elements of the array. */
18932 #define OPS0() { OP_stop, }
18933 #define OPS1(a) { OP_##a, }
18934 #define OPS2(a,b) { OP_##a,OP_##b, }
18935 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18936 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18937 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18938 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18940 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18941 This is useful when mixing operands for ARM and THUMB, i.e. using the
18942 MIX_ARM_THUMB_OPERANDS macro.
18943 In order to use these macros, prefix the number of operands with _
18945 #define OPS_1(a) { a, }
18946 #define OPS_2(a,b) { a,b, }
18947 #define OPS_3(a,b,c) { a,b,c, }
18948 #define OPS_4(a,b,c,d) { a,b,c,d, }
18949 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18950 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18952 /* These macros abstract out the exact format of the mnemonic table and
18953 save some repeated characters. */
18955 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18956 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18957 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18958 THUMB_VARIANT, do_##ae, do_##te }
18960 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18961 a T_MNEM_xyz enumerator. */
18962 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18963 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18964 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18965 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18967 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18968 infix after the third character. */
18969 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18970 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18971 THUMB_VARIANT, do_##ae, do_##te }
18972 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18973 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18974 THUMB_VARIANT, do_##ae, do_##te }
18975 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18976 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18977 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18978 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18979 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18980 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18981 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18982 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18984 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18985 field is still 0xE. Many of the Thumb variants can be executed
18986 conditionally, so this is checked separately. */
18987 #define TUE(mnem, op, top, nops, ops, ae, te) \
18988 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18989 THUMB_VARIANT, do_##ae, do_##te }
18991 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18992 Used by mnemonics that have very minimal differences in the encoding for
18993 ARM and Thumb variants and can be handled in a common function. */
18994 #define TUEc(mnem, op, top, nops, ops, en) \
18995 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18996 THUMB_VARIANT, do_##en, do_##en }
18998 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18999 condition code field. */
19000 #define TUF(mnem, op, top, nops, ops, ae, te) \
19001 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19002 THUMB_VARIANT, do_##ae, do_##te }
19004 /* ARM-only variants of all the above. */
19005 #define CE(mnem, op, nops, ops, ae) \
19006 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19008 #define C3(mnem, op, nops, ops, ae) \
19009 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19011 /* Legacy mnemonics that always have conditional infix after the third
19013 #define CL(mnem, op, nops, ops, ae) \
19014 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19015 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19017 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19018 #define cCE(mnem, op, nops, ops, ae) \
19019 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19021 /* Legacy coprocessor instructions where conditional infix and conditional
19022 suffix are ambiguous. For consistency this includes all FPA instructions,
19023 not just the potentially ambiguous ones. */
19024 #define cCL(mnem, op, nops, ops, ae) \
19025 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19026 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19028 /* Coprocessor, takes either a suffix or a position-3 infix
19029 (for an FPA corner case). */
19030 #define C3E(mnem, op, nops, ops, ae) \
19031 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19032 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19034 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19035 { m1 #m2 m3, OPS##nops ops, \
19036 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19037 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19039 #define CM(m1, m2, op, nops, ops, ae) \
19040 xCM_ (m1, , m2, op, nops, ops, ae), \
19041 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19042 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19043 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19044 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19045 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19046 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19047 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19048 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19049 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19050 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19051 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19052 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19053 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19054 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19055 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19056 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19057 xCM_ (m1, le, m2, op, nops, ops, ae), \
19058 xCM_ (m1, al, m2, op, nops, ops, ae)
19060 #define UE(mnem, op, nops, ops, ae) \
19061 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19063 #define UF(mnem, op, nops, ops, ae) \
19064 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19066 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19067 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19068 use the same encoding function for each. */
19069 #define NUF(mnem, op, nops, ops, enc) \
19070 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19071 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19073 /* Neon data processing, version which indirects through neon_enc_tab for
19074 the various overloaded versions of opcodes. */
19075 #define nUF(mnem, op, nops, ops, enc) \
19076 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19077 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19079 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19081 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19082 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19083 THUMB_VARIANT, do_##enc, do_##enc }
19085 #define NCE(mnem, op, nops, ops, enc) \
19086 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19088 #define NCEF(mnem, op, nops, ops, enc) \
19089 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19091 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19092 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19093 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19094 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19096 #define nCE(mnem, op, nops, ops, enc) \
19097 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19099 #define nCEF(mnem, op, nops, ops, enc) \
19100 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19104 static const struct asm_opcode insns
[] =
19106 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19107 #define THUMB_VARIANT & arm_ext_v4t
19108 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19109 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19110 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19111 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19112 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19113 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19114 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19115 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19116 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19117 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19118 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19119 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19120 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19121 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19122 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19123 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19125 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19126 for setting PSR flag bits. They are obsolete in V6 and do not
19127 have Thumb equivalents. */
19128 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19129 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19130 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19131 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19132 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19133 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19134 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19135 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19136 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19138 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19139 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19140 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19141 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19143 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19144 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19145 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19147 OP_ADDRGLDR
),ldst
, t_ldst
),
19148 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19150 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19151 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19152 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19153 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19154 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19155 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19157 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19158 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19159 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19160 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19163 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19164 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19165 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19166 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19168 /* Thumb-compatibility pseudo ops. */
19169 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19170 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19171 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19172 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19173 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19174 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19175 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19176 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19177 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19178 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19179 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19180 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19182 /* These may simplify to neg. */
19183 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19184 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19186 #undef THUMB_VARIANT
19187 #define THUMB_VARIANT & arm_ext_v6
19189 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19191 /* V1 instructions with no Thumb analogue prior to V6T2. */
19192 #undef THUMB_VARIANT
19193 #define THUMB_VARIANT & arm_ext_v6t2
19195 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19196 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19197 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19199 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19200 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19201 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19202 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19204 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19205 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19207 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19208 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19210 /* V1 instructions with no Thumb analogue at all. */
19211 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19212 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19214 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19215 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19216 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19217 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19218 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19219 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19220 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19221 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19224 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19225 #undef THUMB_VARIANT
19226 #define THUMB_VARIANT & arm_ext_v4t
19228 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19229 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19231 #undef THUMB_VARIANT
19232 #define THUMB_VARIANT & arm_ext_v6t2
19234 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19235 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19237 /* Generic coprocessor instructions. */
19238 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19239 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19240 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19241 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19242 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19243 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19244 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19247 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19249 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19250 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19253 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19254 #undef THUMB_VARIANT
19255 #define THUMB_VARIANT & arm_ext_msr
19257 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19258 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19261 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19262 #undef THUMB_VARIANT
19263 #define THUMB_VARIANT & arm_ext_v6t2
19265 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19266 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19267 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19268 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19269 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19270 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19271 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19272 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19275 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19276 #undef THUMB_VARIANT
19277 #define THUMB_VARIANT & arm_ext_v4t
19279 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19280 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19281 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19282 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19283 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19284 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19287 #define ARM_VARIANT & arm_ext_v4t_5
19289 /* ARM Architecture 4T. */
19290 /* Note: bx (and blx) are required on V5, even if the processor does
19291 not support Thumb. */
19292 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19295 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19296 #undef THUMB_VARIANT
19297 #define THUMB_VARIANT & arm_ext_v5t
19299 /* Note: blx has 2 variants; the .value coded here is for
19300 BLX(2). Only this variant has conditional execution. */
19301 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19302 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19304 #undef THUMB_VARIANT
19305 #define THUMB_VARIANT & arm_ext_v6t2
19307 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19308 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19309 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19310 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19311 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19312 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19313 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19314 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19317 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19318 #undef THUMB_VARIANT
19319 #define THUMB_VARIANT & arm_ext_v5exp
19321 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19322 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19323 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19324 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19326 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19327 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19329 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19330 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19331 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19332 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19334 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19335 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19336 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19337 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19339 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19340 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19342 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19343 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19344 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19345 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19348 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19349 #undef THUMB_VARIANT
19350 #define THUMB_VARIANT & arm_ext_v6t2
19352 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19353 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19355 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19356 ADDRGLDRS
), ldrd
, t_ldstd
),
19358 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19359 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19362 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19364 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19367 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19368 #undef THUMB_VARIANT
19369 #define THUMB_VARIANT & arm_ext_v6
19371 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19372 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19373 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19374 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19375 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19376 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19377 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19378 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19379 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19380 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19382 #undef THUMB_VARIANT
19383 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19385 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19386 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19388 #undef THUMB_VARIANT
19389 #define THUMB_VARIANT & arm_ext_v6t2
19391 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19392 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19394 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19395 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19397 /* ARM V6 not included in V7M. */
19398 #undef THUMB_VARIANT
19399 #define THUMB_VARIANT & arm_ext_v6_notm
19400 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19401 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19402 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19403 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19404 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19405 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19406 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19407 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19408 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19409 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19410 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19411 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19412 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19413 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19414 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19415 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19416 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19417 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19418 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19420 /* ARM V6 not included in V7M (eg. integer SIMD). */
19421 #undef THUMB_VARIANT
19422 #define THUMB_VARIANT & arm_ext_v6_dsp
19423 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19424 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19425 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19426 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19427 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 /* Old name for QASX. */
19429 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19430 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19431 /* Old name for QSAX. */
19432 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19433 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19434 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19435 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19436 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19437 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19438 /* Old name for SASX. */
19439 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19440 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19441 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19442 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19443 /* Old name for SHASX. */
19444 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19445 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19446 /* Old name for SHSAX. */
19447 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19448 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19449 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19450 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19451 /* Old name for SSAX. */
19452 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19453 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19454 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19455 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19456 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19457 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19458 /* Old name for UASX. */
19459 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19460 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19461 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19462 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19463 /* Old name for UHASX. */
19464 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19465 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19466 /* Old name for UHSAX. */
19467 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19468 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19469 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19470 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19471 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19472 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19473 /* Old name for UQASX. */
19474 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19475 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19476 /* Old name for UQSAX. */
19477 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19478 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19479 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19480 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19481 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19482 /* Old name for USAX. */
19483 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19484 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19485 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19486 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19487 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19488 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19489 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19490 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19491 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19492 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19493 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19494 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19495 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19496 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19497 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19498 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19499 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19500 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19501 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19502 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19503 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19504 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19505 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19506 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19507 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19508 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19509 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19510 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19511 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19512 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19513 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19514 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19515 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19516 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19519 #define ARM_VARIANT & arm_ext_v6k
19520 #undef THUMB_VARIANT
19521 #define THUMB_VARIANT & arm_ext_v6k
19523 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19524 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19525 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19526 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19528 #undef THUMB_VARIANT
19529 #define THUMB_VARIANT & arm_ext_v6_notm
19530 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19532 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19533 RRnpcb
), strexd
, t_strexd
),
19535 #undef THUMB_VARIANT
19536 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19537 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19539 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19541 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19543 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19545 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19548 #define ARM_VARIANT & arm_ext_sec
19549 #undef THUMB_VARIANT
19550 #define THUMB_VARIANT & arm_ext_sec
19552 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19555 #define ARM_VARIANT & arm_ext_virt
19556 #undef THUMB_VARIANT
19557 #define THUMB_VARIANT & arm_ext_virt
19559 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19560 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19563 #define ARM_VARIANT & arm_ext_pan
19564 #undef THUMB_VARIANT
19565 #define THUMB_VARIANT & arm_ext_pan
19567 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19570 #define ARM_VARIANT & arm_ext_v6t2
19571 #undef THUMB_VARIANT
19572 #define THUMB_VARIANT & arm_ext_v6t2
19574 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19575 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19576 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19577 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19579 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19580 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19582 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19583 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19584 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19585 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19587 #undef THUMB_VARIANT
19588 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19589 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19590 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19592 /* Thumb-only instructions. */
19594 #define ARM_VARIANT NULL
19595 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19596 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19598 /* ARM does not really have an IT instruction, so always allow it.
19599 The opcode is copied from Thumb in order to allow warnings in
19600 -mimplicit-it=[never | arm] modes. */
19602 #define ARM_VARIANT & arm_ext_v1
19603 #undef THUMB_VARIANT
19604 #define THUMB_VARIANT & arm_ext_v6t2
19606 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19607 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19608 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19609 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19610 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19611 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19612 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19613 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19614 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19615 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19616 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19617 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19618 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19619 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19620 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19621 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19622 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19623 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19625 /* Thumb2 only instructions. */
19627 #define ARM_VARIANT NULL
19629 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19630 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19631 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19632 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19633 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19634 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19636 /* Hardware division instructions. */
19638 #define ARM_VARIANT & arm_ext_adiv
19639 #undef THUMB_VARIANT
19640 #define THUMB_VARIANT & arm_ext_div
19642 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19643 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19645 /* ARM V6M/V7 instructions. */
19647 #define ARM_VARIANT & arm_ext_barrier
19648 #undef THUMB_VARIANT
19649 #define THUMB_VARIANT & arm_ext_barrier
19651 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19652 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19653 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19655 /* ARM V7 instructions. */
19657 #define ARM_VARIANT & arm_ext_v7
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & arm_ext_v7
19661 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19662 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19665 #define ARM_VARIANT & arm_ext_mp
19666 #undef THUMB_VARIANT
19667 #define THUMB_VARIANT & arm_ext_mp
19669 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19671 /* AArchv8 instructions. */
19673 #define ARM_VARIANT & arm_ext_v8
19675 /* Instructions shared between armv8-a and armv8-m. */
19676 #undef THUMB_VARIANT
19677 #define THUMB_VARIANT & arm_ext_atomics
19679 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19680 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19681 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19682 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19683 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19684 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19685 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19686 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19687 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19688 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19690 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19692 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19694 #undef THUMB_VARIANT
19695 #define THUMB_VARIANT & arm_ext_v8
19697 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19698 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19699 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19701 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19703 /* ARMv8 T32 only. */
19705 #define ARM_VARIANT NULL
19706 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19707 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19708 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19710 /* FP for ARMv8. */
19712 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19713 #undef THUMB_VARIANT
19714 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19716 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19717 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19718 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19719 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19720 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19721 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19722 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19723 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19724 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19725 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19726 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19727 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19728 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19729 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19730 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19731 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19732 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19734 /* Crypto v1 extensions. */
19736 #define ARM_VARIANT & fpu_crypto_ext_armv8
19737 #undef THUMB_VARIANT
19738 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19740 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19741 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19742 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19743 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19744 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19745 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19746 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19747 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19748 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19749 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19750 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19751 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19752 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19753 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19756 #define ARM_VARIANT & crc_ext_armv8
19757 #undef THUMB_VARIANT
19758 #define THUMB_VARIANT & crc_ext_armv8
19759 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19760 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19761 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19762 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19763 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19764 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19766 /* ARMv8.2 RAS extension. */
19768 #define ARM_VARIANT & arm_ext_ras
19769 #undef THUMB_VARIANT
19770 #define THUMB_VARIANT & arm_ext_ras
19771 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19774 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19775 #undef THUMB_VARIANT
19776 #define THUMB_VARIANT NULL
19778 cCE("wfs", e200110
, 1, (RR
), rd
),
19779 cCE("rfs", e300110
, 1, (RR
), rd
),
19780 cCE("wfc", e400110
, 1, (RR
), rd
),
19781 cCE("rfc", e500110
, 1, (RR
), rd
),
19783 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19784 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19785 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19786 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19788 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19789 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19790 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19791 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19793 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20108 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20121 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20123 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20127 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20128 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20134 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20136 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20140 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20141 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20171 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20172 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20173 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20175 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20176 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20177 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20178 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20179 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20180 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20181 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20182 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20183 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20184 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20185 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20186 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20188 /* The implementation of the FIX instruction is broken on some
20189 assemblers, in that it accepts a precision specifier as well as a
20190 rounding specifier, despite the fact that this is meaningless.
20191 To be more compatible, we accept it as well, though of course it
20192 does not set any bits. */
20193 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20194 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20195 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20196 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20197 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20198 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20199 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20200 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20201 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20202 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20203 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20204 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20205 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20207 /* Instructions that were new with the real FPA, call them V2. */
20209 #define ARM_VARIANT & fpu_fpa_ext_v2
20211 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20212 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20213 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20214 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20215 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20216 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20219 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20221 /* Moves and type conversions. */
20222 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20223 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20224 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20225 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20226 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20227 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20228 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20229 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20230 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20231 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20232 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20233 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20234 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20235 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20237 /* Memory operations. */
20238 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20239 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20240 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20241 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20242 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20243 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20244 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20245 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20246 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20247 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20248 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20249 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20250 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20251 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20252 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20253 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20254 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20255 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20257 /* Monadic operations. */
20258 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20259 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20260 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20262 /* Dyadic operations. */
20263 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20264 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20265 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20266 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20267 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20268 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20269 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20270 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20271 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20274 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20275 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20276 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20277 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20279 /* Double precision load/store are still present on single precision
20280 implementations. */
20281 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20282 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20283 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20284 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20285 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20286 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20287 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20288 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20289 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20290 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20293 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20295 /* Moves and type conversions. */
20296 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20297 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20298 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20299 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20300 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20301 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20302 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20303 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20304 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20305 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20306 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20307 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20308 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20310 /* Monadic operations. */
20311 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20312 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20313 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20315 /* Dyadic operations. */
20316 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20317 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20318 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20319 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20320 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20321 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20322 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20323 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20324 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20327 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20328 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20329 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20330 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20333 #define ARM_VARIANT & fpu_vfp_ext_v2
20335 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20336 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20337 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20338 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20340 /* Instructions which may belong to either the Neon or VFP instruction sets.
20341 Individual encoder functions perform additional architecture checks. */
20343 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20344 #undef THUMB_VARIANT
20345 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20347 /* These mnemonics are unique to VFP. */
20348 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20349 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20350 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20351 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20352 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20353 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20354 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20355 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20356 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20357 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20359 /* Mnemonics shared by Neon and VFP. */
20360 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20361 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20362 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20364 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20365 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20367 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20368 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20370 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20371 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20372 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20373 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20374 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20375 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20376 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20377 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20379 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20380 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20381 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20382 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20385 /* NOTE: All VMOV encoding is special-cased! */
20386 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20387 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20390 #define ARM_VARIANT & arm_ext_fp16
20391 #undef THUMB_VARIANT
20392 #define THUMB_VARIANT & arm_ext_fp16
20393 /* New instructions added from v8.2, allowing the extraction and insertion of
20394 the upper 16 bits of a 32-bit vector register. */
20395 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20396 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20398 #undef THUMB_VARIANT
20399 #define THUMB_VARIANT & fpu_neon_ext_v1
20401 #define ARM_VARIANT & fpu_neon_ext_v1
20403 /* Data processing with three registers of the same length. */
20404 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20405 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20406 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20407 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20408 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20409 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20410 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20411 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20412 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20413 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20414 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20415 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20416 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20417 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20418 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20419 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20420 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20421 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20422 /* If not immediate, fall back to neon_dyadic_i64_su.
20423 shl_imm should accept I8 I16 I32 I64,
20424 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20425 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20426 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20427 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20428 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20429 /* Logic ops, types optional & ignored. */
20430 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20431 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20432 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20433 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20434 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20435 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20436 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20437 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20438 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20439 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20440 /* Bitfield ops, untyped. */
20441 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20442 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20443 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20444 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20445 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20446 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20447 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20448 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20449 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20450 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20451 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20452 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20453 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20454 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20455 back to neon_dyadic_if_su. */
20456 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20457 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20458 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20459 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20460 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20461 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20462 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20463 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20464 /* Comparison. Type I8 I16 I32 F32. */
20465 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20466 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20467 /* As above, D registers only. */
20468 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20469 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20470 /* Int and float variants, signedness unimportant. */
20471 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20472 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20473 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20474 /* Add/sub take types I8 I16 I32 I64 F32. */
20475 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20476 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20477 /* vtst takes sizes 8, 16, 32. */
20478 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20479 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20480 /* VMUL takes I8 I16 I32 F32 P8. */
20481 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20482 /* VQD{R}MULH takes S16 S32. */
20483 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20484 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20485 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20486 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20487 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20488 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20489 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20490 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20491 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20492 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20493 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20494 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20495 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20496 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20497 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20498 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20499 /* ARM v8.1 extension. */
20500 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20501 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20502 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20503 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20505 /* Two address, int/float. Types S8 S16 S32 F32. */
20506 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20507 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20509 /* Data processing with two registers and a shift amount. */
20510 /* Right shifts, and variants with rounding.
20511 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20512 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20513 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20514 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20515 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20516 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20517 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20518 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20519 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20520 /* Shift and insert. Sizes accepted 8 16 32 64. */
20521 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20522 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20523 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20524 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20525 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20526 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20527 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20528 /* Right shift immediate, saturating & narrowing, with rounding variants.
20529 Types accepted S16 S32 S64 U16 U32 U64. */
20530 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20531 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20532 /* As above, unsigned. Types accepted S16 S32 S64. */
20533 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20534 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20535 /* Right shift narrowing. Types accepted I16 I32 I64. */
20536 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20537 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20538 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20539 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20540 /* CVT with optional immediate for fixed-point variant. */
20541 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20543 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20544 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20546 /* Data processing, three registers of different lengths. */
20547 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20548 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20549 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20550 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20551 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20552 /* If not scalar, fall back to neon_dyadic_long.
20553 Vector types as above, scalar types S16 S32 U16 U32. */
20554 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20555 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20556 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20557 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20558 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20559 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20560 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20561 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20562 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20563 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20564 /* Saturating doubling multiplies. Types S16 S32. */
20565 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20566 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20567 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20568 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20569 S16 S32 U16 U32. */
20570 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20572 /* Extract. Size 8. */
20573 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20574 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20576 /* Two registers, miscellaneous. */
20577 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20578 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20579 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20580 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20581 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20582 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20583 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20584 /* Vector replicate. Sizes 8 16 32. */
20585 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20586 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20587 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20588 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20589 /* VMOVN. Types I16 I32 I64. */
20590 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20591 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20592 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20593 /* VQMOVUN. Types S16 S32 S64. */
20594 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20595 /* VZIP / VUZP. Sizes 8 16 32. */
20596 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20597 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20598 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20599 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20600 /* VQABS / VQNEG. Types S8 S16 S32. */
20601 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20602 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20603 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20604 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20605 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20606 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20607 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20608 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20609 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20610 /* Reciprocal estimates. Types U32 F16 F32. */
20611 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20612 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20613 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20614 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20615 /* VCLS. Types S8 S16 S32. */
20616 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20617 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20618 /* VCLZ. Types I8 I16 I32. */
20619 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20620 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20621 /* VCNT. Size 8. */
20622 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20623 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20624 /* Two address, untyped. */
20625 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20626 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20627 /* VTRN. Sizes 8 16 32. */
20628 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20629 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20631 /* Table lookup. Size 8. */
20632 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20633 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20635 #undef THUMB_VARIANT
20636 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20638 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20640 /* Neon element/structure load/store. */
20641 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20642 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20643 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20644 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20645 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20646 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20647 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20648 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20650 #undef THUMB_VARIANT
20651 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20653 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20654 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20655 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20656 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20657 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20658 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20659 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20660 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20661 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20662 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20664 #undef THUMB_VARIANT
20665 #define THUMB_VARIANT & fpu_vfp_ext_v3
20667 #define ARM_VARIANT & fpu_vfp_ext_v3
20669 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20670 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20671 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20672 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20673 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20674 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20675 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20676 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20677 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20680 #define ARM_VARIANT & fpu_vfp_ext_fma
20681 #undef THUMB_VARIANT
20682 #define THUMB_VARIANT & fpu_vfp_ext_fma
20683 /* Mnemonics shared by Neon and VFP. These are included in the
20684 VFP FMA variant; NEON and VFP FMA always includes the NEON
20685 FMA instructions. */
20686 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20687 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20688 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20689 the v form should always be used. */
20690 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20691 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20692 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20693 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20694 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20695 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20697 #undef THUMB_VARIANT
20699 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20701 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20702 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20703 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20704 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20705 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20706 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20707 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20708 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20711 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20713 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20714 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20715 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20716 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20717 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20718 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20719 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20720 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20721 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20722 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20723 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20724 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20725 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20726 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20727 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20728 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20729 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20730 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20731 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20732 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20733 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20734 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20735 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20736 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20737 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20738 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20739 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20740 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20741 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20742 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20743 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20744 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20745 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20746 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20747 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20748 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20749 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20750 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20760 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20765 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20766 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20767 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20776 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20777 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20780 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20781 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20782 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20783 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20787 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20789 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20790 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20791 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20799 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20800 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20802 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20804 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20809 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20810 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20811 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20812 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20813 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20814 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20815 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20816 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20817 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20818 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20819 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20824 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20825 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20826 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20827 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20828 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20829 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20830 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20831 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20832 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20833 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20834 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20835 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20836 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20837 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20838 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20839 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20840 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20841 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20842 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20843 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20844 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20845 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20846 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20856 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20857 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20858 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20859 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20860 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20861 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20865 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20866 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20867 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20868 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20869 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20870 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20877 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20879 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20880 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20881 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20882 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20883 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20884 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20885 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20891 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20900 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20924 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20926 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20928 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20929 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20940 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20941 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20942 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20943 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20944 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20945 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20946 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20947 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20948 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20949 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20950 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20951 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20952 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20953 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20954 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20955 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20956 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20957 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20958 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20959 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20960 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20961 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20962 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20963 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20964 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20965 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20966 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20967 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20968 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20969 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20970 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20971 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20972 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20973 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20974 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20975 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20976 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20977 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20978 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20979 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20980 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20981 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20982 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20983 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20984 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20985 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20986 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20987 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20988 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20989 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20990 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20991 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20992 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20993 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20994 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20995 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20996 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20997 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20998 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20999 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21000 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21001 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21002 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21003 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21004 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21005 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21006 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21007 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21008 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21009 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21010 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21011 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21012 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21013 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21014 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21015 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21017 /* ARMv8-M instructions. */
21019 #define ARM_VARIANT NULL
21020 #undef THUMB_VARIANT
21021 #define THUMB_VARIANT & arm_ext_v8m
21022 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21023 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21024 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21025 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21026 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21027 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21028 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21030 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21031 instructions behave as nop if no VFP is present. */
21032 #undef THUMB_VARIANT
21033 #define THUMB_VARIANT & arm_ext_v8m_main
21034 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21035 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21038 #undef THUMB_VARIANT
21064 /* MD interface: bits in the object file. */
21066 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21067 for use in the a.out file, and stores them in the array pointed to by buf.
21068 This knows about the endian-ness of the target machine and does
21069 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21070 2 (short) and 4 (long) Floating numbers are put out as a series of
21071 LITTLENUMS (shorts, here at least). */
21074 md_number_to_chars (char * buf
, valueT val
, int n
)
21076 if (target_big_endian
)
21077 number_to_chars_bigendian (buf
, val
, n
);
21079 number_to_chars_littleendian (buf
, val
, n
);
21083 md_chars_to_number (char * buf
, int n
)
21086 unsigned char * where
= (unsigned char *) buf
;
21088 if (target_big_endian
)
21093 result
|= (*where
++ & 255);
21101 result
|= (where
[n
] & 255);
21108 /* MD interface: Sections. */
21110 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21111 that an rs_machine_dependent frag may reach. */
21114 arm_frag_max_var (fragS
*fragp
)
21116 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21117 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21119 Note that we generate relaxable instructions even for cases that don't
21120 really need it, like an immediate that's a trivial constant. So we're
21121 overestimating the instruction size for some of those cases. Rather
21122 than putting more intelligence here, it would probably be better to
21123 avoid generating a relaxation frag in the first place when it can be
21124 determined up front that a short instruction will suffice. */
21126 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21130 /* Estimate the size of a frag before relaxing. Assume everything fits in
21134 md_estimate_size_before_relax (fragS
* fragp
,
21135 segT segtype ATTRIBUTE_UNUSED
)
21141 /* Convert a machine dependent frag. */
21144 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21146 unsigned long insn
;
21147 unsigned long old_op
;
21155 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21157 old_op
= bfd_get_16(abfd
, buf
);
21158 if (fragp
->fr_symbol
)
21160 exp
.X_op
= O_symbol
;
21161 exp
.X_add_symbol
= fragp
->fr_symbol
;
21165 exp
.X_op
= O_constant
;
21167 exp
.X_add_number
= fragp
->fr_offset
;
21168 opcode
= fragp
->fr_subtype
;
21171 case T_MNEM_ldr_pc
:
21172 case T_MNEM_ldr_pc2
:
21173 case T_MNEM_ldr_sp
:
21174 case T_MNEM_str_sp
:
21181 if (fragp
->fr_var
== 4)
21183 insn
= THUMB_OP32 (opcode
);
21184 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21186 insn
|= (old_op
& 0x700) << 4;
21190 insn
|= (old_op
& 7) << 12;
21191 insn
|= (old_op
& 0x38) << 13;
21193 insn
|= 0x00000c00;
21194 put_thumb32_insn (buf
, insn
);
21195 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21199 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21201 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21204 if (fragp
->fr_var
== 4)
21206 insn
= THUMB_OP32 (opcode
);
21207 insn
|= (old_op
& 0xf0) << 4;
21208 put_thumb32_insn (buf
, insn
);
21209 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21213 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21214 exp
.X_add_number
-= 4;
21222 if (fragp
->fr_var
== 4)
21224 int r0off
= (opcode
== T_MNEM_mov
21225 || opcode
== T_MNEM_movs
) ? 0 : 8;
21226 insn
= THUMB_OP32 (opcode
);
21227 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21228 insn
|= (old_op
& 0x700) << r0off
;
21229 put_thumb32_insn (buf
, insn
);
21230 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21234 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21239 if (fragp
->fr_var
== 4)
21241 insn
= THUMB_OP32(opcode
);
21242 put_thumb32_insn (buf
, insn
);
21243 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21246 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21250 if (fragp
->fr_var
== 4)
21252 insn
= THUMB_OP32(opcode
);
21253 insn
|= (old_op
& 0xf00) << 14;
21254 put_thumb32_insn (buf
, insn
);
21255 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21258 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21261 case T_MNEM_add_sp
:
21262 case T_MNEM_add_pc
:
21263 case T_MNEM_inc_sp
:
21264 case T_MNEM_dec_sp
:
21265 if (fragp
->fr_var
== 4)
21267 /* ??? Choose between add and addw. */
21268 insn
= THUMB_OP32 (opcode
);
21269 insn
|= (old_op
& 0xf0) << 4;
21270 put_thumb32_insn (buf
, insn
);
21271 if (opcode
== T_MNEM_add_pc
)
21272 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21274 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21277 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21285 if (fragp
->fr_var
== 4)
21287 insn
= THUMB_OP32 (opcode
);
21288 insn
|= (old_op
& 0xf0) << 4;
21289 insn
|= (old_op
& 0xf) << 16;
21290 put_thumb32_insn (buf
, insn
);
21291 if (insn
& (1 << 20))
21292 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21294 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21297 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21303 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21304 (enum bfd_reloc_code_real
) reloc_type
);
21305 fixp
->fx_file
= fragp
->fr_file
;
21306 fixp
->fx_line
= fragp
->fr_line
;
21307 fragp
->fr_fix
+= fragp
->fr_var
;
21309 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21310 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21311 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21312 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21315 /* Return the size of a relaxable immediate operand instruction.
21316 SHIFT and SIZE specify the form of the allowable immediate. */
21318 relax_immediate (fragS
*fragp
, int size
, int shift
)
21324 /* ??? Should be able to do better than this. */
21325 if (fragp
->fr_symbol
)
21328 low
= (1 << shift
) - 1;
21329 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21330 offset
= fragp
->fr_offset
;
21331 /* Force misaligned offsets to 32-bit variant. */
21334 if (offset
& ~mask
)
21339 /* Get the address of a symbol during relaxation. */
21341 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21347 sym
= fragp
->fr_symbol
;
21348 sym_frag
= symbol_get_frag (sym
);
21349 know (S_GET_SEGMENT (sym
) != absolute_section
21350 || sym_frag
== &zero_address_frag
);
21351 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21353 /* If frag has yet to be reached on this pass, assume it will
21354 move by STRETCH just as we did. If this is not so, it will
21355 be because some frag between grows, and that will force
21359 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21363 /* Adjust stretch for any alignment frag. Note that if have
21364 been expanding the earlier code, the symbol may be
21365 defined in what appears to be an earlier frag. FIXME:
21366 This doesn't handle the fr_subtype field, which specifies
21367 a maximum number of bytes to skip when doing an
21369 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21371 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21374 stretch
= - ((- stretch
)
21375 & ~ ((1 << (int) f
->fr_offset
) - 1));
21377 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21389 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21392 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21397 /* Assume worst case for symbols not known to be in the same section. */
21398 if (fragp
->fr_symbol
== NULL
21399 || !S_IS_DEFINED (fragp
->fr_symbol
)
21400 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21401 || S_IS_WEAK (fragp
->fr_symbol
))
21404 val
= relaxed_symbol_addr (fragp
, stretch
);
21405 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21406 addr
= (addr
+ 4) & ~3;
21407 /* Force misaligned targets to 32-bit variant. */
21411 if (val
< 0 || val
> 1020)
21416 /* Return the size of a relaxable add/sub immediate instruction. */
21418 relax_addsub (fragS
*fragp
, asection
*sec
)
21423 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21424 op
= bfd_get_16(sec
->owner
, buf
);
21425 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21426 return relax_immediate (fragp
, 8, 0);
21428 return relax_immediate (fragp
, 3, 0);
21431 /* Return TRUE iff the definition of symbol S could be pre-empted
21432 (overridden) at link or load time. */
21434 symbol_preemptible (symbolS
*s
)
21436 /* Weak symbols can always be pre-empted. */
21440 /* Non-global symbols cannot be pre-empted. */
21441 if (! S_IS_EXTERNAL (s
))
21445 /* In ELF, a global symbol can be marked protected, or private. In that
21446 case it can't be pre-empted (other definitions in the same link unit
21447 would violate the ODR). */
21448 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21452 /* Other global symbols might be pre-empted. */
21456 /* Return the size of a relaxable branch instruction. BITS is the
21457 size of the offset field in the narrow instruction. */
21460 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21466 /* Assume worst case for symbols not known to be in the same section. */
21467 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21468 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21469 || S_IS_WEAK (fragp
->fr_symbol
))
21473 /* A branch to a function in ARM state will require interworking. */
21474 if (S_IS_DEFINED (fragp
->fr_symbol
)
21475 && ARM_IS_FUNC (fragp
->fr_symbol
))
21479 if (symbol_preemptible (fragp
->fr_symbol
))
21482 val
= relaxed_symbol_addr (fragp
, stretch
);
21483 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21486 /* Offset is a signed value *2 */
21488 if (val
>= limit
|| val
< -limit
)
21494 /* Relax a machine dependent frag. This returns the amount by which
21495 the current size of the frag should change. */
21498 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21503 oldsize
= fragp
->fr_var
;
21504 switch (fragp
->fr_subtype
)
21506 case T_MNEM_ldr_pc2
:
21507 newsize
= relax_adr (fragp
, sec
, stretch
);
21509 case T_MNEM_ldr_pc
:
21510 case T_MNEM_ldr_sp
:
21511 case T_MNEM_str_sp
:
21512 newsize
= relax_immediate (fragp
, 8, 2);
21516 newsize
= relax_immediate (fragp
, 5, 2);
21520 newsize
= relax_immediate (fragp
, 5, 1);
21524 newsize
= relax_immediate (fragp
, 5, 0);
21527 newsize
= relax_adr (fragp
, sec
, stretch
);
21533 newsize
= relax_immediate (fragp
, 8, 0);
21536 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21539 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21541 case T_MNEM_add_sp
:
21542 case T_MNEM_add_pc
:
21543 newsize
= relax_immediate (fragp
, 8, 2);
21545 case T_MNEM_inc_sp
:
21546 case T_MNEM_dec_sp
:
21547 newsize
= relax_immediate (fragp
, 7, 2);
21553 newsize
= relax_addsub (fragp
, sec
);
21559 fragp
->fr_var
= newsize
;
21560 /* Freeze wide instructions that are at or before the same location as
21561 in the previous pass. This avoids infinite loops.
21562 Don't freeze them unconditionally because targets may be artificially
21563 misaligned by the expansion of preceding frags. */
21564 if (stretch
<= 0 && newsize
> 2)
21566 md_convert_frag (sec
->owner
, sec
, fragp
);
21570 return newsize
- oldsize
;
21573 /* Round up a section size to the appropriate boundary. */
21576 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21579 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21580 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21582 /* For a.out, force the section size to be aligned. If we don't do
21583 this, BFD will align it for us, but it will not write out the
21584 final bytes of the section. This may be a bug in BFD, but it is
21585 easier to fix it here since that is how the other a.out targets
21589 align
= bfd_get_section_alignment (stdoutput
, segment
);
21590 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21597 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21598 of an rs_align_code fragment. */
21601 arm_handle_align (fragS
* fragP
)
21603 static unsigned char const arm_noop
[2][2][4] =
21606 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21607 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21610 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21611 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21614 static unsigned char const thumb_noop
[2][2][2] =
21617 {0xc0, 0x46}, /* LE */
21618 {0x46, 0xc0}, /* BE */
21621 {0x00, 0xbf}, /* LE */
21622 {0xbf, 0x00} /* BE */
21625 static unsigned char const wide_thumb_noop
[2][4] =
21626 { /* Wide Thumb-2 */
21627 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21628 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21631 unsigned bytes
, fix
, noop_size
;
21633 const unsigned char * noop
;
21634 const unsigned char *narrow_noop
= NULL
;
21639 if (fragP
->fr_type
!= rs_align_code
)
21642 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21643 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21646 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21647 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21649 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21651 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21653 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21654 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21656 narrow_noop
= thumb_noop
[1][target_big_endian
];
21657 noop
= wide_thumb_noop
[target_big_endian
];
21660 noop
= thumb_noop
[0][target_big_endian
];
21668 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21669 ? selected_cpu
: arm_arch_none
,
21671 [target_big_endian
];
21678 fragP
->fr_var
= noop_size
;
21680 if (bytes
& (noop_size
- 1))
21682 fix
= bytes
& (noop_size
- 1);
21684 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21686 memset (p
, 0, fix
);
21693 if (bytes
& noop_size
)
21695 /* Insert a narrow noop. */
21696 memcpy (p
, narrow_noop
, noop_size
);
21698 bytes
-= noop_size
;
21702 /* Use wide noops for the remainder */
21706 while (bytes
>= noop_size
)
21708 memcpy (p
, noop
, noop_size
);
21710 bytes
-= noop_size
;
21714 fragP
->fr_fix
+= fix
;
21717 /* Called from md_do_align. Used to create an alignment
21718 frag in a code section. */
21721 arm_frag_align_code (int n
, int max
)
21725 /* We assume that there will never be a requirement
21726 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21727 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21732 _("alignments greater than %d bytes not supported in .text sections."),
21733 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21734 as_fatal ("%s", err_msg
);
21737 p
= frag_var (rs_align_code
,
21738 MAX_MEM_FOR_RS_ALIGN_CODE
,
21740 (relax_substateT
) max
,
21747 /* Perform target specific initialisation of a frag.
21748 Note - despite the name this initialisation is not done when the frag
21749 is created, but only when its type is assigned. A frag can be created
21750 and used a long time before its type is set, so beware of assuming that
21751 this initialisationis performed first. */
21755 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21757 /* Record whether this frag is in an ARM or a THUMB area. */
21758 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21761 #else /* OBJ_ELF is defined. */
21763 arm_init_frag (fragS
* fragP
, int max_chars
)
21765 int frag_thumb_mode
;
21767 /* If the current ARM vs THUMB mode has not already
21768 been recorded into this frag then do so now. */
21769 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21770 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21772 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21774 /* Record a mapping symbol for alignment frags. We will delete this
21775 later if the alignment ends up empty. */
21776 switch (fragP
->fr_type
)
21779 case rs_align_test
:
21781 mapping_state_2 (MAP_DATA
, max_chars
);
21783 case rs_align_code
:
21784 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21791 /* When we change sections we need to issue a new mapping symbol. */
21794 arm_elf_change_section (void)
21796 /* Link an unlinked unwind index table section to the .text section. */
21797 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21798 && elf_linked_to_section (now_seg
) == NULL
)
21799 elf_linked_to_section (now_seg
) = text_section
;
21803 arm_elf_section_type (const char * str
, size_t len
)
21805 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21806 return SHT_ARM_EXIDX
;
21811 /* Code to deal with unwinding tables. */
21813 static void add_unwind_adjustsp (offsetT
);
21815 /* Generate any deferred unwind frame offset. */
21818 flush_pending_unwind (void)
21822 offset
= unwind
.pending_offset
;
21823 unwind
.pending_offset
= 0;
21825 add_unwind_adjustsp (offset
);
21828 /* Add an opcode to this list for this function. Two-byte opcodes should
21829 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21833 add_unwind_opcode (valueT op
, int length
)
21835 /* Add any deferred stack adjustment. */
21836 if (unwind
.pending_offset
)
21837 flush_pending_unwind ();
21839 unwind
.sp_restored
= 0;
21841 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21843 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21844 if (unwind
.opcodes
)
21845 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21846 unwind
.opcode_alloc
);
21848 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21853 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21855 unwind
.opcode_count
++;
21859 /* Add unwind opcodes to adjust the stack pointer. */
21862 add_unwind_adjustsp (offsetT offset
)
21866 if (offset
> 0x200)
21868 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21873 /* Long form: 0xb2, uleb128. */
21874 /* This might not fit in a word so add the individual bytes,
21875 remembering the list is built in reverse order. */
21876 o
= (valueT
) ((offset
- 0x204) >> 2);
21878 add_unwind_opcode (0, 1);
21880 /* Calculate the uleb128 encoding of the offset. */
21884 bytes
[n
] = o
& 0x7f;
21890 /* Add the insn. */
21892 add_unwind_opcode (bytes
[n
- 1], 1);
21893 add_unwind_opcode (0xb2, 1);
21895 else if (offset
> 0x100)
21897 /* Two short opcodes. */
21898 add_unwind_opcode (0x3f, 1);
21899 op
= (offset
- 0x104) >> 2;
21900 add_unwind_opcode (op
, 1);
21902 else if (offset
> 0)
21904 /* Short opcode. */
21905 op
= (offset
- 4) >> 2;
21906 add_unwind_opcode (op
, 1);
21908 else if (offset
< 0)
21911 while (offset
> 0x100)
21913 add_unwind_opcode (0x7f, 1);
21916 op
= ((offset
- 4) >> 2) | 0x40;
21917 add_unwind_opcode (op
, 1);
21921 /* Finish the list of unwind opcodes for this function. */
21923 finish_unwind_opcodes (void)
21927 if (unwind
.fp_used
)
21929 /* Adjust sp as necessary. */
21930 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21931 flush_pending_unwind ();
21933 /* After restoring sp from the frame pointer. */
21934 op
= 0x90 | unwind
.fp_reg
;
21935 add_unwind_opcode (op
, 1);
21938 flush_pending_unwind ();
21942 /* Start an exception table entry. If idx is nonzero this is an index table
21946 start_unwind_section (const segT text_seg
, int idx
)
21948 const char * text_name
;
21949 const char * prefix
;
21950 const char * prefix_once
;
21951 const char * group_name
;
21959 prefix
= ELF_STRING_ARM_unwind
;
21960 prefix_once
= ELF_STRING_ARM_unwind_once
;
21961 type
= SHT_ARM_EXIDX
;
21965 prefix
= ELF_STRING_ARM_unwind_info
;
21966 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21967 type
= SHT_PROGBITS
;
21970 text_name
= segment_name (text_seg
);
21971 if (streq (text_name
, ".text"))
21974 if (strncmp (text_name
, ".gnu.linkonce.t.",
21975 strlen (".gnu.linkonce.t.")) == 0)
21977 prefix
= prefix_once
;
21978 text_name
+= strlen (".gnu.linkonce.t.");
21981 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
21987 /* Handle COMDAT group. */
21988 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21990 group_name
= elf_group_name (text_seg
);
21991 if (group_name
== NULL
)
21993 as_bad (_("Group section `%s' has no group signature"),
21994 segment_name (text_seg
));
21995 ignore_rest_of_line ();
21998 flags
|= SHF_GROUP
;
22002 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
22004 /* Set the section link for index tables. */
22006 elf_linked_to_section (now_seg
) = text_seg
;
22010 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22011 personality routine data. Returns zero, or the index table value for
22012 an inline entry. */
22015 create_unwind_entry (int have_data
)
22020 /* The current word of data. */
22022 /* The number of bytes left in this word. */
22025 finish_unwind_opcodes ();
22027 /* Remember the current text section. */
22028 unwind
.saved_seg
= now_seg
;
22029 unwind
.saved_subseg
= now_subseg
;
22031 start_unwind_section (now_seg
, 0);
22033 if (unwind
.personality_routine
== NULL
)
22035 if (unwind
.personality_index
== -2)
22038 as_bad (_("handlerdata in cantunwind frame"));
22039 return 1; /* EXIDX_CANTUNWIND. */
22042 /* Use a default personality routine if none is specified. */
22043 if (unwind
.personality_index
== -1)
22045 if (unwind
.opcode_count
> 3)
22046 unwind
.personality_index
= 1;
22048 unwind
.personality_index
= 0;
22051 /* Space for the personality routine entry. */
22052 if (unwind
.personality_index
== 0)
22054 if (unwind
.opcode_count
> 3)
22055 as_bad (_("too many unwind opcodes for personality routine 0"));
22059 /* All the data is inline in the index table. */
22062 while (unwind
.opcode_count
> 0)
22064 unwind
.opcode_count
--;
22065 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22069 /* Pad with "finish" opcodes. */
22071 data
= (data
<< 8) | 0xb0;
22078 /* We get two opcodes "free" in the first word. */
22079 size
= unwind
.opcode_count
- 2;
22083 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22084 if (unwind
.personality_index
!= -1)
22086 as_bad (_("attempt to recreate an unwind entry"));
22090 /* An extra byte is required for the opcode count. */
22091 size
= unwind
.opcode_count
+ 1;
22094 size
= (size
+ 3) >> 2;
22096 as_bad (_("too many unwind opcodes"));
22098 frag_align (2, 0, 0);
22099 record_alignment (now_seg
, 2);
22100 unwind
.table_entry
= expr_build_dot ();
22102 /* Allocate the table entry. */
22103 ptr
= frag_more ((size
<< 2) + 4);
22104 /* PR 13449: Zero the table entries in case some of them are not used. */
22105 memset (ptr
, 0, (size
<< 2) + 4);
22106 where
= frag_now_fix () - ((size
<< 2) + 4);
22108 switch (unwind
.personality_index
)
22111 /* ??? Should this be a PLT generating relocation? */
22112 /* Custom personality routine. */
22113 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22114 BFD_RELOC_ARM_PREL31
);
22119 /* Set the first byte to the number of additional words. */
22120 data
= size
> 0 ? size
- 1 : 0;
22124 /* ABI defined personality routines. */
22126 /* Three opcodes bytes are packed into the first word. */
22133 /* The size and first two opcode bytes go in the first word. */
22134 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22139 /* Should never happen. */
22143 /* Pack the opcodes into words (MSB first), reversing the list at the same
22145 while (unwind
.opcode_count
> 0)
22149 md_number_to_chars (ptr
, data
, 4);
22154 unwind
.opcode_count
--;
22156 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22159 /* Finish off the last word. */
22162 /* Pad with "finish" opcodes. */
22164 data
= (data
<< 8) | 0xb0;
22166 md_number_to_chars (ptr
, data
, 4);
22171 /* Add an empty descriptor if there is no user-specified data. */
22172 ptr
= frag_more (4);
22173 md_number_to_chars (ptr
, 0, 4);
22180 /* Initialize the DWARF-2 unwind information for this procedure. */
22183 tc_arm_frame_initial_instructions (void)
22185 cfi_add_CFA_def_cfa (REG_SP
, 0);
22187 #endif /* OBJ_ELF */
22189 /* Convert REGNAME to a DWARF-2 register number. */
22192 tc_arm_regname_to_dw2regnum (char *regname
)
22194 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22198 /* PR 16694: Allow VFP registers as well. */
22199 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22203 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22212 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22216 exp
.X_op
= O_secrel
;
22217 exp
.X_add_symbol
= symbol
;
22218 exp
.X_add_number
= 0;
22219 emit_expr (&exp
, size
);
22223 /* MD interface: Symbol and relocation handling. */
22225 /* Return the address within the segment that a PC-relative fixup is
22226 relative to. For ARM, PC-relative fixups applied to instructions
22227 are generally relative to the location of the fixup plus 8 bytes.
22228 Thumb branches are offset by 4, and Thumb loads relative to PC
22229 require special handling. */
22232 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22234 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22236 /* If this is pc-relative and we are going to emit a relocation
22237 then we just want to put out any pipeline compensation that the linker
22238 will need. Otherwise we want to use the calculated base.
22239 For WinCE we skip the bias for externals as well, since this
22240 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22242 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22243 || (arm_force_relocation (fixP
)
22245 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22251 switch (fixP
->fx_r_type
)
22253 /* PC relative addressing on the Thumb is slightly odd as the
22254 bottom two bits of the PC are forced to zero for the
22255 calculation. This happens *after* application of the
22256 pipeline offset. However, Thumb adrl already adjusts for
22257 this, so we need not do it again. */
22258 case BFD_RELOC_ARM_THUMB_ADD
:
22261 case BFD_RELOC_ARM_THUMB_OFFSET
:
22262 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22263 case BFD_RELOC_ARM_T32_ADD_PC12
:
22264 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22265 return (base
+ 4) & ~3;
22267 /* Thumb branches are simply offset by +4. */
22268 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22269 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22270 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22271 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22272 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22275 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22277 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22278 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22279 && ARM_IS_FUNC (fixP
->fx_addsy
)
22280 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22281 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22284 /* BLX is like branches above, but forces the low two bits of PC to
22286 case BFD_RELOC_THUMB_PCREL_BLX
:
22288 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22289 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22290 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22291 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22292 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22293 return (base
+ 4) & ~3;
22295 /* ARM mode branches are offset by +8. However, the Windows CE
22296 loader expects the relocation not to take this into account. */
22297 case BFD_RELOC_ARM_PCREL_BLX
:
22299 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22300 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22301 && ARM_IS_FUNC (fixP
->fx_addsy
)
22302 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22303 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22306 case BFD_RELOC_ARM_PCREL_CALL
:
22308 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22309 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22310 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22311 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22312 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22315 case BFD_RELOC_ARM_PCREL_BRANCH
:
22316 case BFD_RELOC_ARM_PCREL_JUMP
:
22317 case BFD_RELOC_ARM_PLT32
:
22319 /* When handling fixups immediately, because we have already
22320 discovered the value of a symbol, or the address of the frag involved
22321 we must account for the offset by +8, as the OS loader will never see the reloc.
22322 see fixup_segment() in write.c
22323 The S_IS_EXTERNAL test handles the case of global symbols.
22324 Those need the calculated base, not just the pipe compensation the linker will need. */
22326 && fixP
->fx_addsy
!= NULL
22327 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22328 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22336 /* ARM mode loads relative to PC are also offset by +8. Unlike
22337 branches, the Windows CE loader *does* expect the relocation
22338 to take this into account. */
22339 case BFD_RELOC_ARM_OFFSET_IMM
:
22340 case BFD_RELOC_ARM_OFFSET_IMM8
:
22341 case BFD_RELOC_ARM_HWLITERAL
:
22342 case BFD_RELOC_ARM_LITERAL
:
22343 case BFD_RELOC_ARM_CP_OFF_IMM
:
22347 /* Other PC-relative relocations are un-offset. */
22353 static bfd_boolean flag_warn_syms
= TRUE
;
22356 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22358 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22359 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22360 does mean that the resulting code might be very confusing to the reader.
22361 Also this warning can be triggered if the user omits an operand before
22362 an immediate address, eg:
22366 GAS treats this as an assignment of the value of the symbol foo to a
22367 symbol LDR, and so (without this code) it will not issue any kind of
22368 warning or error message.
22370 Note - ARM instructions are case-insensitive but the strings in the hash
22371 table are all stored in lower case, so we must first ensure that name is
22373 if (flag_warn_syms
&& arm_ops_hsh
)
22375 char * nbuf
= strdup (name
);
22378 for (p
= nbuf
; *p
; p
++)
22380 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22382 static struct hash_control
* already_warned
= NULL
;
22384 if (already_warned
== NULL
)
22385 already_warned
= hash_new ();
22386 /* Only warn about the symbol once. To keep the code
22387 simple we let hash_insert do the lookup for us. */
22388 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22389 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22398 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22399 Otherwise we have no need to default values of symbols. */
22402 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22405 if (name
[0] == '_' && name
[1] == 'G'
22406 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22410 if (symbol_find (name
))
22411 as_bad (_("GOT already in the symbol table"));
22413 GOT_symbol
= symbol_new (name
, undefined_section
,
22414 (valueT
) 0, & zero_address_frag
);
22424 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22425 computed as two separate immediate values, added together. We
22426 already know that this value cannot be computed by just one ARM
22429 static unsigned int
22430 validate_immediate_twopart (unsigned int val
,
22431 unsigned int * highpart
)
22436 for (i
= 0; i
< 32; i
+= 2)
22437 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22443 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22445 else if (a
& 0xff0000)
22447 if (a
& 0xff000000)
22449 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22453 gas_assert (a
& 0xff000000);
22454 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22457 return (a
& 0xff) | (i
<< 7);
22464 validate_offset_imm (unsigned int val
, int hwse
)
22466 if ((hwse
&& val
> 255) || val
> 4095)
22471 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22472 negative immediate constant by altering the instruction. A bit of
22477 by inverting the second operand, and
22480 by negating the second operand. */
22483 negate_data_op (unsigned long * instruction
,
22484 unsigned long value
)
22487 unsigned long negated
, inverted
;
22489 negated
= encode_arm_immediate (-value
);
22490 inverted
= encode_arm_immediate (~value
);
22492 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22495 /* First negates. */
22496 case OPCODE_SUB
: /* ADD <-> SUB */
22497 new_inst
= OPCODE_ADD
;
22502 new_inst
= OPCODE_SUB
;
22506 case OPCODE_CMP
: /* CMP <-> CMN */
22507 new_inst
= OPCODE_CMN
;
22512 new_inst
= OPCODE_CMP
;
22516 /* Now Inverted ops. */
22517 case OPCODE_MOV
: /* MOV <-> MVN */
22518 new_inst
= OPCODE_MVN
;
22523 new_inst
= OPCODE_MOV
;
22527 case OPCODE_AND
: /* AND <-> BIC */
22528 new_inst
= OPCODE_BIC
;
22533 new_inst
= OPCODE_AND
;
22537 case OPCODE_ADC
: /* ADC <-> SBC */
22538 new_inst
= OPCODE_SBC
;
22543 new_inst
= OPCODE_ADC
;
22547 /* We cannot do anything. */
22552 if (value
== (unsigned) FAIL
)
22555 *instruction
&= OPCODE_MASK
;
22556 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22560 /* Like negate_data_op, but for Thumb-2. */
22562 static unsigned int
22563 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22567 unsigned int negated
, inverted
;
22569 negated
= encode_thumb32_immediate (-value
);
22570 inverted
= encode_thumb32_immediate (~value
);
22572 rd
= (*instruction
>> 8) & 0xf;
22573 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22576 /* ADD <-> SUB. Includes CMP <-> CMN. */
22577 case T2_OPCODE_SUB
:
22578 new_inst
= T2_OPCODE_ADD
;
22582 case T2_OPCODE_ADD
:
22583 new_inst
= T2_OPCODE_SUB
;
22587 /* ORR <-> ORN. Includes MOV <-> MVN. */
22588 case T2_OPCODE_ORR
:
22589 new_inst
= T2_OPCODE_ORN
;
22593 case T2_OPCODE_ORN
:
22594 new_inst
= T2_OPCODE_ORR
;
22598 /* AND <-> BIC. TST has no inverted equivalent. */
22599 case T2_OPCODE_AND
:
22600 new_inst
= T2_OPCODE_BIC
;
22607 case T2_OPCODE_BIC
:
22608 new_inst
= T2_OPCODE_AND
;
22613 case T2_OPCODE_ADC
:
22614 new_inst
= T2_OPCODE_SBC
;
22618 case T2_OPCODE_SBC
:
22619 new_inst
= T2_OPCODE_ADC
;
22623 /* We cannot do anything. */
22628 if (value
== (unsigned int)FAIL
)
22631 *instruction
&= T2_OPCODE_MASK
;
22632 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22636 /* Read a 32-bit thumb instruction from buf. */
22637 static unsigned long
22638 get_thumb32_insn (char * buf
)
22640 unsigned long insn
;
22641 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22642 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22648 /* We usually want to set the low bit on the address of thumb function
22649 symbols. In particular .word foo - . should have the low bit set.
22650 Generic code tries to fold the difference of two symbols to
22651 a constant. Prevent this and force a relocation when the first symbols
22652 is a thumb function. */
22655 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22657 if (op
== O_subtract
22658 && l
->X_op
== O_symbol
22659 && r
->X_op
== O_symbol
22660 && THUMB_IS_FUNC (l
->X_add_symbol
))
22662 l
->X_op
= O_subtract
;
22663 l
->X_op_symbol
= r
->X_add_symbol
;
22664 l
->X_add_number
-= r
->X_add_number
;
22668 /* Process as normal. */
22672 /* Encode Thumb2 unconditional branches and calls. The encoding
22673 for the 2 are identical for the immediate values. */
22676 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22678 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22681 addressT S
, I1
, I2
, lo
, hi
;
22683 S
= (value
>> 24) & 0x01;
22684 I1
= (value
>> 23) & 0x01;
22685 I2
= (value
>> 22) & 0x01;
22686 hi
= (value
>> 12) & 0x3ff;
22687 lo
= (value
>> 1) & 0x7ff;
22688 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22689 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22690 newval
|= (S
<< 10) | hi
;
22691 newval2
&= ~T2I1I2MASK
;
22692 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22693 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22694 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22698 md_apply_fix (fixS
* fixP
,
22702 offsetT value
= * valP
;
22704 unsigned int newimm
;
22705 unsigned long temp
;
22707 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22709 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22711 /* Note whether this will delete the relocation. */
22713 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22716 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22717 consistency with the behaviour on 32-bit hosts. Remember value
22719 value
&= 0xffffffff;
22720 value
^= 0x80000000;
22721 value
-= 0x80000000;
22724 fixP
->fx_addnumber
= value
;
22726 /* Same treatment for fixP->fx_offset. */
22727 fixP
->fx_offset
&= 0xffffffff;
22728 fixP
->fx_offset
^= 0x80000000;
22729 fixP
->fx_offset
-= 0x80000000;
22731 switch (fixP
->fx_r_type
)
22733 case BFD_RELOC_NONE
:
22734 /* This will need to go in the object file. */
22738 case BFD_RELOC_ARM_IMMEDIATE
:
22739 /* We claim that this fixup has been processed here,
22740 even if in fact we generate an error because we do
22741 not have a reloc for it, so tc_gen_reloc will reject it. */
22744 if (fixP
->fx_addsy
)
22746 const char *msg
= 0;
22748 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22749 msg
= _("undefined symbol %s used as an immediate value");
22750 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22751 msg
= _("symbol %s is in a different section");
22752 else if (S_IS_WEAK (fixP
->fx_addsy
))
22753 msg
= _("symbol %s is weak and may be overridden later");
22757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22758 msg
, S_GET_NAME (fixP
->fx_addsy
));
22763 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22765 /* If the offset is negative, we should use encoding A2 for ADR. */
22766 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22767 newimm
= negate_data_op (&temp
, value
);
22770 newimm
= encode_arm_immediate (value
);
22772 /* If the instruction will fail, see if we can fix things up by
22773 changing the opcode. */
22774 if (newimm
== (unsigned int) FAIL
)
22775 newimm
= negate_data_op (&temp
, value
);
22778 if (newimm
== (unsigned int) FAIL
)
22780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22781 _("invalid constant (%lx) after fixup"),
22782 (unsigned long) value
);
22786 newimm
|= (temp
& 0xfffff000);
22787 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22790 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22792 unsigned int highpart
= 0;
22793 unsigned int newinsn
= 0xe1a00000; /* nop. */
22795 if (fixP
->fx_addsy
)
22797 const char *msg
= 0;
22799 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22800 msg
= _("undefined symbol %s used as an immediate value");
22801 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22802 msg
= _("symbol %s is in a different section");
22803 else if (S_IS_WEAK (fixP
->fx_addsy
))
22804 msg
= _("symbol %s is weak and may be overridden later");
22808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22809 msg
, S_GET_NAME (fixP
->fx_addsy
));
22814 newimm
= encode_arm_immediate (value
);
22815 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22817 /* If the instruction will fail, see if we can fix things up by
22818 changing the opcode. */
22819 if (newimm
== (unsigned int) FAIL
22820 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22822 /* No ? OK - try using two ADD instructions to generate
22824 newimm
= validate_immediate_twopart (value
, & highpart
);
22826 /* Yes - then make sure that the second instruction is
22828 if (newimm
!= (unsigned int) FAIL
)
22830 /* Still No ? Try using a negated value. */
22831 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22832 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22833 /* Otherwise - give up. */
22836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22837 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22842 /* Replace the first operand in the 2nd instruction (which
22843 is the PC) with the destination register. We have
22844 already added in the PC in the first instruction and we
22845 do not want to do it again. */
22846 newinsn
&= ~ 0xf0000;
22847 newinsn
|= ((newinsn
& 0x0f000) << 4);
22850 newimm
|= (temp
& 0xfffff000);
22851 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22853 highpart
|= (newinsn
& 0xfffff000);
22854 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22858 case BFD_RELOC_ARM_OFFSET_IMM
:
22859 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22861 /* Fall through. */
22863 case BFD_RELOC_ARM_LITERAL
:
22869 if (validate_offset_imm (value
, 0) == FAIL
)
22871 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22873 _("invalid literal constant: pool needs to be closer"));
22875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22876 _("bad immediate value for offset (%ld)"),
22881 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22883 newval
&= 0xfffff000;
22886 newval
&= 0xff7ff000;
22887 newval
|= value
| (sign
? INDEX_UP
: 0);
22889 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22892 case BFD_RELOC_ARM_OFFSET_IMM8
:
22893 case BFD_RELOC_ARM_HWLITERAL
:
22899 if (validate_offset_imm (value
, 1) == FAIL
)
22901 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22903 _("invalid literal constant: pool needs to be closer"));
22905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22906 _("bad immediate value for 8-bit offset (%ld)"),
22911 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22913 newval
&= 0xfffff0f0;
22916 newval
&= 0xff7ff0f0;
22917 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22919 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22922 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22923 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22925 _("bad immediate value for offset (%ld)"), (long) value
);
22928 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22930 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22933 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22934 /* This is a complicated relocation used for all varieties of Thumb32
22935 load/store instruction with immediate offset:
22937 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22938 *4, optional writeback(W)
22939 (doubleword load/store)
22941 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22942 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22943 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22944 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22945 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22947 Uppercase letters indicate bits that are already encoded at
22948 this point. Lowercase letters are our problem. For the
22949 second block of instructions, the secondary opcode nybble
22950 (bits 8..11) is present, and bit 23 is zero, even if this is
22951 a PC-relative operation. */
22952 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22954 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22956 if ((newval
& 0xf0000000) == 0xe0000000)
22958 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22960 newval
|= (1 << 23);
22963 if (value
% 4 != 0)
22965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22966 _("offset not a multiple of 4"));
22972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22973 _("offset out of range"));
22978 else if ((newval
& 0x000f0000) == 0x000f0000)
22980 /* PC-relative, 12-bit offset. */
22982 newval
|= (1 << 23);
22987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22988 _("offset out of range"));
22993 else if ((newval
& 0x00000100) == 0x00000100)
22995 /* Writeback: 8-bit, +/- offset. */
22997 newval
|= (1 << 9);
23002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23003 _("offset out of range"));
23008 else if ((newval
& 0x00000f00) == 0x00000e00)
23010 /* T-instruction: positive 8-bit offset. */
23011 if (value
< 0 || value
> 0xff)
23013 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23014 _("offset out of range"));
23022 /* Positive 12-bit or negative 8-bit offset. */
23026 newval
|= (1 << 23);
23036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23037 _("offset out of range"));
23044 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23045 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23048 case BFD_RELOC_ARM_SHIFT_IMM
:
23049 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23050 if (((unsigned long) value
) > 32
23052 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23055 _("shift expression is too large"));
23060 /* Shifts of zero must be done as lsl. */
23062 else if (value
== 32)
23064 newval
&= 0xfffff07f;
23065 newval
|= (value
& 0x1f) << 7;
23066 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23069 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23070 case BFD_RELOC_ARM_T32_ADD_IMM
:
23071 case BFD_RELOC_ARM_T32_IMM12
:
23072 case BFD_RELOC_ARM_T32_ADD_PC12
:
23073 /* We claim that this fixup has been processed here,
23074 even if in fact we generate an error because we do
23075 not have a reloc for it, so tc_gen_reloc will reject it. */
23079 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23082 _("undefined symbol %s used as an immediate value"),
23083 S_GET_NAME (fixP
->fx_addsy
));
23087 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23089 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23092 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23093 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23095 newimm
= encode_thumb32_immediate (value
);
23096 if (newimm
== (unsigned int) FAIL
)
23097 newimm
= thumb32_negate_data_op (&newval
, value
);
23099 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23100 && newimm
== (unsigned int) FAIL
)
23102 /* Turn add/sum into addw/subw. */
23103 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23104 newval
= (newval
& 0xfeffffff) | 0x02000000;
23105 /* No flat 12-bit imm encoding for addsw/subsw. */
23106 if ((newval
& 0x00100000) == 0)
23108 /* 12 bit immediate for addw/subw. */
23112 newval
^= 0x00a00000;
23115 newimm
= (unsigned int) FAIL
;
23121 if (newimm
== (unsigned int)FAIL
)
23123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23124 _("invalid constant (%lx) after fixup"),
23125 (unsigned long) value
);
23129 newval
|= (newimm
& 0x800) << 15;
23130 newval
|= (newimm
& 0x700) << 4;
23131 newval
|= (newimm
& 0x0ff);
23133 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23134 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23137 case BFD_RELOC_ARM_SMC
:
23138 if (((unsigned long) value
) > 0xffff)
23139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23140 _("invalid smc expression"));
23141 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23142 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23143 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23146 case BFD_RELOC_ARM_HVC
:
23147 if (((unsigned long) value
) > 0xffff)
23148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23149 _("invalid hvc expression"));
23150 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23151 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23152 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23155 case BFD_RELOC_ARM_SWI
:
23156 if (fixP
->tc_fix_data
!= 0)
23158 if (((unsigned long) value
) > 0xff)
23159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23160 _("invalid swi expression"));
23161 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23163 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23167 if (((unsigned long) value
) > 0x00ffffff)
23168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23169 _("invalid swi expression"));
23170 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23172 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23176 case BFD_RELOC_ARM_MULTI
:
23177 if (((unsigned long) value
) > 0xffff)
23178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23179 _("invalid expression in load/store multiple"));
23180 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23181 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23185 case BFD_RELOC_ARM_PCREL_CALL
:
23187 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23189 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23190 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23191 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23192 /* Flip the bl to blx. This is a simple flip
23193 bit here because we generate PCREL_CALL for
23194 unconditional bls. */
23196 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23197 newval
= newval
| 0x10000000;
23198 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23204 goto arm_branch_common
;
23206 case BFD_RELOC_ARM_PCREL_JUMP
:
23207 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23209 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23210 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23211 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23213 /* This would map to a bl<cond>, b<cond>,
23214 b<always> to a Thumb function. We
23215 need to force a relocation for this particular
23217 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23220 /* Fall through. */
23222 case BFD_RELOC_ARM_PLT32
:
23224 case BFD_RELOC_ARM_PCREL_BRANCH
:
23226 goto arm_branch_common
;
23228 case BFD_RELOC_ARM_PCREL_BLX
:
23231 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23233 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23234 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23235 && ARM_IS_FUNC (fixP
->fx_addsy
))
23237 /* Flip the blx to a bl and warn. */
23238 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23239 newval
= 0xeb000000;
23240 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23241 _("blx to '%s' an ARM ISA state function changed to bl"),
23243 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23249 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23250 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23254 /* We are going to store value (shifted right by two) in the
23255 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23256 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23257 also be be clear. */
23259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23260 _("misaligned branch destination"));
23261 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23262 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23265 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23267 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23268 newval
|= (value
>> 2) & 0x00ffffff;
23269 /* Set the H bit on BLX instructions. */
23273 newval
|= 0x01000000;
23275 newval
&= ~0x01000000;
23277 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23281 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23282 /* CBZ can only branch forward. */
23284 /* Attempts to use CBZ to branch to the next instruction
23285 (which, strictly speaking, are prohibited) will be turned into
23288 FIXME: It may be better to remove the instruction completely and
23289 perform relaxation. */
23292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23293 newval
= 0xbf00; /* NOP encoding T1 */
23294 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23301 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23303 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23304 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23305 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23310 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23311 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23314 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23316 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23317 newval
|= (value
& 0x1ff) >> 1;
23318 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23322 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23323 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23326 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23328 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23329 newval
|= (value
& 0xfff) >> 1;
23330 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23334 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23336 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23337 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23338 && ARM_IS_FUNC (fixP
->fx_addsy
)
23339 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23341 /* Force a relocation for a branch 20 bits wide. */
23344 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23346 _("conditional branch out of range"));
23348 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23351 addressT S
, J1
, J2
, lo
, hi
;
23353 S
= (value
& 0x00100000) >> 20;
23354 J2
= (value
& 0x00080000) >> 19;
23355 J1
= (value
& 0x00040000) >> 18;
23356 hi
= (value
& 0x0003f000) >> 12;
23357 lo
= (value
& 0x00000ffe) >> 1;
23359 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23360 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23361 newval
|= (S
<< 10) | hi
;
23362 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23363 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23364 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23368 case BFD_RELOC_THUMB_PCREL_BLX
:
23369 /* If there is a blx from a thumb state function to
23370 another thumb function flip this to a bl and warn
23374 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23375 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23376 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23378 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23379 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23380 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23382 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23383 newval
= newval
| 0x1000;
23384 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23385 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23390 goto thumb_bl_common
;
23392 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23393 /* A bl from Thumb state ISA to an internal ARM state function
23394 is converted to a blx. */
23396 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23397 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23398 && ARM_IS_FUNC (fixP
->fx_addsy
)
23399 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23401 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23402 newval
= newval
& ~0x1000;
23403 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23404 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23410 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23411 /* For a BLX instruction, make sure that the relocation is rounded up
23412 to a word boundary. This follows the semantics of the instruction
23413 which specifies that bit 1 of the target address will come from bit
23414 1 of the base address. */
23415 value
= (value
+ 3) & ~ 3;
23418 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23419 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23420 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23423 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23425 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23427 else if ((value
& ~0x1ffffff)
23428 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23430 _("Thumb2 branch out of range"));
23433 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23434 encode_thumb2_b_bl_offset (buf
, value
);
23438 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23439 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23442 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23443 encode_thumb2_b_bl_offset (buf
, value
);
23448 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23453 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23454 md_number_to_chars (buf
, value
, 2);
23458 case BFD_RELOC_ARM_TLS_CALL
:
23459 case BFD_RELOC_ARM_THM_TLS_CALL
:
23460 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23461 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23462 case BFD_RELOC_ARM_TLS_GOTDESC
:
23463 case BFD_RELOC_ARM_TLS_GD32
:
23464 case BFD_RELOC_ARM_TLS_LE32
:
23465 case BFD_RELOC_ARM_TLS_IE32
:
23466 case BFD_RELOC_ARM_TLS_LDM32
:
23467 case BFD_RELOC_ARM_TLS_LDO32
:
23468 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23471 case BFD_RELOC_ARM_GOT32
:
23472 case BFD_RELOC_ARM_GOTOFF
:
23475 case BFD_RELOC_ARM_GOT_PREL
:
23476 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23477 md_number_to_chars (buf
, value
, 4);
23480 case BFD_RELOC_ARM_TARGET2
:
23481 /* TARGET2 is not partial-inplace, so we need to write the
23482 addend here for REL targets, because it won't be written out
23483 during reloc processing later. */
23484 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23485 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23489 case BFD_RELOC_RVA
:
23491 case BFD_RELOC_ARM_TARGET1
:
23492 case BFD_RELOC_ARM_ROSEGREL32
:
23493 case BFD_RELOC_ARM_SBREL32
:
23494 case BFD_RELOC_32_PCREL
:
23496 case BFD_RELOC_32_SECREL
:
23498 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23500 /* For WinCE we only do this for pcrel fixups. */
23501 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23503 md_number_to_chars (buf
, value
, 4);
23507 case BFD_RELOC_ARM_PREL31
:
23508 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23510 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23511 if ((value
^ (value
>> 1)) & 0x40000000)
23513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23514 _("rel31 relocation overflow"));
23516 newval
|= value
& 0x7fffffff;
23517 md_number_to_chars (buf
, newval
, 4);
23522 case BFD_RELOC_ARM_CP_OFF_IMM
:
23523 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23524 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23525 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23527 newval
= get_thumb32_insn (buf
);
23528 if ((newval
& 0x0f200f00) == 0x0d000900)
23530 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23531 has permitted values that are multiples of 2, in the range 0
23533 if (value
< -510 || value
> 510 || (value
& 1))
23534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23535 _("co-processor offset out of range"));
23537 else if (value
< -1023 || value
> 1023 || (value
& 3))
23538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23539 _("co-processor offset out of range"));
23544 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23545 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23546 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23548 newval
= get_thumb32_insn (buf
);
23550 newval
&= 0xffffff00;
23553 newval
&= 0xff7fff00;
23554 if ((newval
& 0x0f200f00) == 0x0d000900)
23556 /* This is a fp16 vstr/vldr.
23558 It requires the immediate offset in the instruction is shifted
23559 left by 1 to be a half-word offset.
23561 Here, left shift by 1 first, and later right shift by 2
23562 should get the right offset. */
23565 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23567 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23568 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23569 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23571 put_thumb32_insn (buf
, newval
);
23574 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23575 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23576 if (value
< -255 || value
> 255)
23577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23578 _("co-processor offset out of range"));
23580 goto cp_off_common
;
23582 case BFD_RELOC_ARM_THUMB_OFFSET
:
23583 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23584 /* Exactly what ranges, and where the offset is inserted depends
23585 on the type of instruction, we can establish this from the
23587 switch (newval
>> 12)
23589 case 4: /* PC load. */
23590 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23591 forced to zero for these loads; md_pcrel_from has already
23592 compensated for this. */
23594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23595 _("invalid offset, target not word aligned (0x%08lX)"),
23596 (((unsigned long) fixP
->fx_frag
->fr_address
23597 + (unsigned long) fixP
->fx_where
) & ~3)
23598 + (unsigned long) value
);
23600 if (value
& ~0x3fc)
23601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23602 _("invalid offset, value too big (0x%08lX)"),
23605 newval
|= value
>> 2;
23608 case 9: /* SP load/store. */
23609 if (value
& ~0x3fc)
23610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23611 _("invalid offset, value too big (0x%08lX)"),
23613 newval
|= value
>> 2;
23616 case 6: /* Word load/store. */
23618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23619 _("invalid offset, value too big (0x%08lX)"),
23621 newval
|= value
<< 4; /* 6 - 2. */
23624 case 7: /* Byte load/store. */
23626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23627 _("invalid offset, value too big (0x%08lX)"),
23629 newval
|= value
<< 6;
23632 case 8: /* Halfword load/store. */
23634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23635 _("invalid offset, value too big (0x%08lX)"),
23637 newval
|= value
<< 5; /* 6 - 1. */
23641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23642 "Unable to process relocation for thumb opcode: %lx",
23643 (unsigned long) newval
);
23646 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23649 case BFD_RELOC_ARM_THUMB_ADD
:
23650 /* This is a complicated relocation, since we use it for all of
23651 the following immediate relocations:
23655 9bit ADD/SUB SP word-aligned
23656 10bit ADD PC/SP word-aligned
23658 The type of instruction being processed is encoded in the
23665 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23667 int rd
= (newval
>> 4) & 0xf;
23668 int rs
= newval
& 0xf;
23669 int subtract
= !!(newval
& 0x8000);
23671 /* Check for HI regs, only very restricted cases allowed:
23672 Adjusting SP, and using PC or SP to get an address. */
23673 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23674 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23676 _("invalid Hi register with immediate"));
23678 /* If value is negative, choose the opposite instruction. */
23682 subtract
= !subtract
;
23684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23685 _("immediate value out of range"));
23690 if (value
& ~0x1fc)
23691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23692 _("invalid immediate for stack address calculation"));
23693 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23694 newval
|= value
>> 2;
23696 else if (rs
== REG_PC
|| rs
== REG_SP
)
23698 /* PR gas/18541. If the addition is for a defined symbol
23699 within range of an ADR instruction then accept it. */
23702 && fixP
->fx_addsy
!= NULL
)
23706 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23707 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23708 || S_IS_WEAK (fixP
->fx_addsy
))
23710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23711 _("address calculation needs a strongly defined nearby symbol"));
23715 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23717 /* Round up to the next 4-byte boundary. */
23722 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23727 _("symbol too far away"));
23737 if (subtract
|| value
& ~0x3fc)
23738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23739 _("invalid immediate for address calculation (value = 0x%08lX)"),
23740 (unsigned long) (subtract
? - value
: value
));
23741 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23743 newval
|= value
>> 2;
23748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23749 _("immediate value out of range"));
23750 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23751 newval
|= (rd
<< 8) | value
;
23756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23757 _("immediate value out of range"));
23758 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23759 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23762 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23765 case BFD_RELOC_ARM_THUMB_IMM
:
23766 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23767 if (value
< 0 || value
> 255)
23768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23769 _("invalid immediate: %ld is out of range"),
23772 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23775 case BFD_RELOC_ARM_THUMB_SHIFT
:
23776 /* 5bit shift value (0..32). LSL cannot take 32. */
23777 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23778 temp
= newval
& 0xf800;
23779 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23781 _("invalid shift value: %ld"), (long) value
);
23782 /* Shifts of zero must be encoded as LSL. */
23784 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23785 /* Shifts of 32 are encoded as zero. */
23786 else if (value
== 32)
23788 newval
|= value
<< 6;
23789 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23792 case BFD_RELOC_VTABLE_INHERIT
:
23793 case BFD_RELOC_VTABLE_ENTRY
:
23797 case BFD_RELOC_ARM_MOVW
:
23798 case BFD_RELOC_ARM_MOVT
:
23799 case BFD_RELOC_ARM_THUMB_MOVW
:
23800 case BFD_RELOC_ARM_THUMB_MOVT
:
23801 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23803 /* REL format relocations are limited to a 16-bit addend. */
23804 if (!fixP
->fx_done
)
23806 if (value
< -0x8000 || value
> 0x7fff)
23807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23808 _("offset out of range"));
23810 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23811 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23816 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23817 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23819 newval
= get_thumb32_insn (buf
);
23820 newval
&= 0xfbf08f00;
23821 newval
|= (value
& 0xf000) << 4;
23822 newval
|= (value
& 0x0800) << 15;
23823 newval
|= (value
& 0x0700) << 4;
23824 newval
|= (value
& 0x00ff);
23825 put_thumb32_insn (buf
, newval
);
23829 newval
= md_chars_to_number (buf
, 4);
23830 newval
&= 0xfff0f000;
23831 newval
|= value
& 0x0fff;
23832 newval
|= (value
& 0xf000) << 4;
23833 md_number_to_chars (buf
, newval
, 4);
23838 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23839 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23840 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23841 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23842 gas_assert (!fixP
->fx_done
);
23845 bfd_boolean is_mov
;
23846 bfd_vma encoded_addend
= value
;
23848 /* Check that addend can be encoded in instruction. */
23849 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23851 _("the offset 0x%08lX is not representable"),
23852 (unsigned long) encoded_addend
);
23854 /* Extract the instruction. */
23855 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23856 is_mov
= (insn
& 0xf800) == 0x2000;
23861 if (!seg
->use_rela_p
)
23862 insn
|= encoded_addend
;
23868 /* Extract the instruction. */
23869 /* Encoding is the following
23874 /* The following conditions must be true :
23879 rd
= (insn
>> 4) & 0xf;
23881 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23883 _("Unable to process relocation for thumb opcode: %lx"),
23884 (unsigned long) insn
);
23886 /* Encode as ADD immediate8 thumb 1 code. */
23887 insn
= 0x3000 | (rd
<< 8);
23889 /* Place the encoded addend into the first 8 bits of the
23891 if (!seg
->use_rela_p
)
23892 insn
|= encoded_addend
;
23895 /* Update the instruction. */
23896 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23900 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23901 case BFD_RELOC_ARM_ALU_PC_G0
:
23902 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23903 case BFD_RELOC_ARM_ALU_PC_G1
:
23904 case BFD_RELOC_ARM_ALU_PC_G2
:
23905 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23906 case BFD_RELOC_ARM_ALU_SB_G0
:
23907 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23908 case BFD_RELOC_ARM_ALU_SB_G1
:
23909 case BFD_RELOC_ARM_ALU_SB_G2
:
23910 gas_assert (!fixP
->fx_done
);
23911 if (!seg
->use_rela_p
)
23914 bfd_vma encoded_addend
;
23915 bfd_vma addend_abs
= abs (value
);
23917 /* Check that the absolute value of the addend can be
23918 expressed as an 8-bit constant plus a rotation. */
23919 encoded_addend
= encode_arm_immediate (addend_abs
);
23920 if (encoded_addend
== (unsigned int) FAIL
)
23921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23922 _("the offset 0x%08lX is not representable"),
23923 (unsigned long) addend_abs
);
23925 /* Extract the instruction. */
23926 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23928 /* If the addend is positive, use an ADD instruction.
23929 Otherwise use a SUB. Take care not to destroy the S bit. */
23930 insn
&= 0xff1fffff;
23936 /* Place the encoded addend into the first 12 bits of the
23938 insn
&= 0xfffff000;
23939 insn
|= encoded_addend
;
23941 /* Update the instruction. */
23942 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23946 case BFD_RELOC_ARM_LDR_PC_G0
:
23947 case BFD_RELOC_ARM_LDR_PC_G1
:
23948 case BFD_RELOC_ARM_LDR_PC_G2
:
23949 case BFD_RELOC_ARM_LDR_SB_G0
:
23950 case BFD_RELOC_ARM_LDR_SB_G1
:
23951 case BFD_RELOC_ARM_LDR_SB_G2
:
23952 gas_assert (!fixP
->fx_done
);
23953 if (!seg
->use_rela_p
)
23956 bfd_vma addend_abs
= abs (value
);
23958 /* Check that the absolute value of the addend can be
23959 encoded in 12 bits. */
23960 if (addend_abs
>= 0x1000)
23961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23962 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23963 (unsigned long) addend_abs
);
23965 /* Extract the instruction. */
23966 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23968 /* If the addend is negative, clear bit 23 of the instruction.
23969 Otherwise set it. */
23971 insn
&= ~(1 << 23);
23975 /* Place the absolute value of the addend into the first 12 bits
23976 of the instruction. */
23977 insn
&= 0xfffff000;
23978 insn
|= addend_abs
;
23980 /* Update the instruction. */
23981 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23985 case BFD_RELOC_ARM_LDRS_PC_G0
:
23986 case BFD_RELOC_ARM_LDRS_PC_G1
:
23987 case BFD_RELOC_ARM_LDRS_PC_G2
:
23988 case BFD_RELOC_ARM_LDRS_SB_G0
:
23989 case BFD_RELOC_ARM_LDRS_SB_G1
:
23990 case BFD_RELOC_ARM_LDRS_SB_G2
:
23991 gas_assert (!fixP
->fx_done
);
23992 if (!seg
->use_rela_p
)
23995 bfd_vma addend_abs
= abs (value
);
23997 /* Check that the absolute value of the addend can be
23998 encoded in 8 bits. */
23999 if (addend_abs
>= 0x100)
24000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24001 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24002 (unsigned long) addend_abs
);
24004 /* Extract the instruction. */
24005 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24007 /* If the addend is negative, clear bit 23 of the instruction.
24008 Otherwise set it. */
24010 insn
&= ~(1 << 23);
24014 /* Place the first four bits of the absolute value of the addend
24015 into the first 4 bits of the instruction, and the remaining
24016 four into bits 8 .. 11. */
24017 insn
&= 0xfffff0f0;
24018 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24020 /* Update the instruction. */
24021 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24025 case BFD_RELOC_ARM_LDC_PC_G0
:
24026 case BFD_RELOC_ARM_LDC_PC_G1
:
24027 case BFD_RELOC_ARM_LDC_PC_G2
:
24028 case BFD_RELOC_ARM_LDC_SB_G0
:
24029 case BFD_RELOC_ARM_LDC_SB_G1
:
24030 case BFD_RELOC_ARM_LDC_SB_G2
:
24031 gas_assert (!fixP
->fx_done
);
24032 if (!seg
->use_rela_p
)
24035 bfd_vma addend_abs
= abs (value
);
24037 /* Check that the absolute value of the addend is a multiple of
24038 four and, when divided by four, fits in 8 bits. */
24039 if (addend_abs
& 0x3)
24040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24041 _("bad offset 0x%08lX (must be word-aligned)"),
24042 (unsigned long) addend_abs
);
24044 if ((addend_abs
>> 2) > 0xff)
24045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24046 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24047 (unsigned long) addend_abs
);
24049 /* Extract the instruction. */
24050 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24052 /* If the addend is negative, clear bit 23 of the instruction.
24053 Otherwise set it. */
24055 insn
&= ~(1 << 23);
24059 /* Place the addend (divided by four) into the first eight
24060 bits of the instruction. */
24061 insn
&= 0xfffffff0;
24062 insn
|= addend_abs
>> 2;
24064 /* Update the instruction. */
24065 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24069 case BFD_RELOC_ARM_V4BX
:
24070 /* This will need to go in the object file. */
24074 case BFD_RELOC_UNUSED
:
24076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24077 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24081 /* Translate internal representation of relocation info to BFD target
24085 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24088 bfd_reloc_code_real_type code
;
24090 reloc
= XNEW (arelent
);
24092 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24093 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24094 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24096 if (fixp
->fx_pcrel
)
24098 if (section
->use_rela_p
)
24099 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24101 fixp
->fx_offset
= reloc
->address
;
24103 reloc
->addend
= fixp
->fx_offset
;
24105 switch (fixp
->fx_r_type
)
24108 if (fixp
->fx_pcrel
)
24110 code
= BFD_RELOC_8_PCREL
;
24113 /* Fall through. */
24116 if (fixp
->fx_pcrel
)
24118 code
= BFD_RELOC_16_PCREL
;
24121 /* Fall through. */
24124 if (fixp
->fx_pcrel
)
24126 code
= BFD_RELOC_32_PCREL
;
24129 /* Fall through. */
24131 case BFD_RELOC_ARM_MOVW
:
24132 if (fixp
->fx_pcrel
)
24134 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24137 /* Fall through. */
24139 case BFD_RELOC_ARM_MOVT
:
24140 if (fixp
->fx_pcrel
)
24142 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24145 /* Fall through. */
24147 case BFD_RELOC_ARM_THUMB_MOVW
:
24148 if (fixp
->fx_pcrel
)
24150 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24153 /* Fall through. */
24155 case BFD_RELOC_ARM_THUMB_MOVT
:
24156 if (fixp
->fx_pcrel
)
24158 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24161 /* Fall through. */
24163 case BFD_RELOC_NONE
:
24164 case BFD_RELOC_ARM_PCREL_BRANCH
:
24165 case BFD_RELOC_ARM_PCREL_BLX
:
24166 case BFD_RELOC_RVA
:
24167 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24168 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24169 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24170 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24171 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24172 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24173 case BFD_RELOC_VTABLE_ENTRY
:
24174 case BFD_RELOC_VTABLE_INHERIT
:
24176 case BFD_RELOC_32_SECREL
:
24178 code
= fixp
->fx_r_type
;
24181 case BFD_RELOC_THUMB_PCREL_BLX
:
24183 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24184 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24187 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24190 case BFD_RELOC_ARM_LITERAL
:
24191 case BFD_RELOC_ARM_HWLITERAL
:
24192 /* If this is called then the a literal has
24193 been referenced across a section boundary. */
24194 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24195 _("literal referenced across section boundary"));
24199 case BFD_RELOC_ARM_TLS_CALL
:
24200 case BFD_RELOC_ARM_THM_TLS_CALL
:
24201 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24202 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24203 case BFD_RELOC_ARM_GOT32
:
24204 case BFD_RELOC_ARM_GOTOFF
:
24205 case BFD_RELOC_ARM_GOT_PREL
:
24206 case BFD_RELOC_ARM_PLT32
:
24207 case BFD_RELOC_ARM_TARGET1
:
24208 case BFD_RELOC_ARM_ROSEGREL32
:
24209 case BFD_RELOC_ARM_SBREL32
:
24210 case BFD_RELOC_ARM_PREL31
:
24211 case BFD_RELOC_ARM_TARGET2
:
24212 case BFD_RELOC_ARM_TLS_LDO32
:
24213 case BFD_RELOC_ARM_PCREL_CALL
:
24214 case BFD_RELOC_ARM_PCREL_JUMP
:
24215 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24216 case BFD_RELOC_ARM_ALU_PC_G0
:
24217 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24218 case BFD_RELOC_ARM_ALU_PC_G1
:
24219 case BFD_RELOC_ARM_ALU_PC_G2
:
24220 case BFD_RELOC_ARM_LDR_PC_G0
:
24221 case BFD_RELOC_ARM_LDR_PC_G1
:
24222 case BFD_RELOC_ARM_LDR_PC_G2
:
24223 case BFD_RELOC_ARM_LDRS_PC_G0
:
24224 case BFD_RELOC_ARM_LDRS_PC_G1
:
24225 case BFD_RELOC_ARM_LDRS_PC_G2
:
24226 case BFD_RELOC_ARM_LDC_PC_G0
:
24227 case BFD_RELOC_ARM_LDC_PC_G1
:
24228 case BFD_RELOC_ARM_LDC_PC_G2
:
24229 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24230 case BFD_RELOC_ARM_ALU_SB_G0
:
24231 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24232 case BFD_RELOC_ARM_ALU_SB_G1
:
24233 case BFD_RELOC_ARM_ALU_SB_G2
:
24234 case BFD_RELOC_ARM_LDR_SB_G0
:
24235 case BFD_RELOC_ARM_LDR_SB_G1
:
24236 case BFD_RELOC_ARM_LDR_SB_G2
:
24237 case BFD_RELOC_ARM_LDRS_SB_G0
:
24238 case BFD_RELOC_ARM_LDRS_SB_G1
:
24239 case BFD_RELOC_ARM_LDRS_SB_G2
:
24240 case BFD_RELOC_ARM_LDC_SB_G0
:
24241 case BFD_RELOC_ARM_LDC_SB_G1
:
24242 case BFD_RELOC_ARM_LDC_SB_G2
:
24243 case BFD_RELOC_ARM_V4BX
:
24244 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24245 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24246 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24247 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24248 code
= fixp
->fx_r_type
;
24251 case BFD_RELOC_ARM_TLS_GOTDESC
:
24252 case BFD_RELOC_ARM_TLS_GD32
:
24253 case BFD_RELOC_ARM_TLS_LE32
:
24254 case BFD_RELOC_ARM_TLS_IE32
:
24255 case BFD_RELOC_ARM_TLS_LDM32
:
24256 /* BFD will include the symbol's address in the addend.
24257 But we don't want that, so subtract it out again here. */
24258 if (!S_IS_COMMON (fixp
->fx_addsy
))
24259 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24260 code
= fixp
->fx_r_type
;
24264 case BFD_RELOC_ARM_IMMEDIATE
:
24265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24266 _("internal relocation (type: IMMEDIATE) not fixed up"));
24269 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24270 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24271 _("ADRL used for a symbol not defined in the same file"));
24274 case BFD_RELOC_ARM_OFFSET_IMM
:
24275 if (section
->use_rela_p
)
24277 code
= fixp
->fx_r_type
;
24281 if (fixp
->fx_addsy
!= NULL
24282 && !S_IS_DEFINED (fixp
->fx_addsy
)
24283 && S_IS_LOCAL (fixp
->fx_addsy
))
24285 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24286 _("undefined local label `%s'"),
24287 S_GET_NAME (fixp
->fx_addsy
));
24291 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24292 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24299 switch (fixp
->fx_r_type
)
24301 case BFD_RELOC_NONE
: type
= "NONE"; break;
24302 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24303 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24304 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24305 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24306 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24307 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24308 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24309 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24310 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24311 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24312 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24313 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24314 default: type
= _("<unknown>"); break;
24316 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24317 _("cannot represent %s relocation in this object file format"),
24324 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24326 && fixp
->fx_addsy
== GOT_symbol
)
24328 code
= BFD_RELOC_ARM_GOTPC
;
24329 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24333 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24335 if (reloc
->howto
== NULL
)
24337 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24338 _("cannot represent %s relocation in this object file format"),
24339 bfd_get_reloc_code_name (code
));
24343 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24344 vtable entry to be used in the relocation's section offset. */
24345 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24346 reloc
->address
= fixp
->fx_offset
;
24351 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24354 cons_fix_new_arm (fragS
* frag
,
24358 bfd_reloc_code_real_type reloc
)
24363 FIXME: @@ Should look at CPU word size. */
24367 reloc
= BFD_RELOC_8
;
24370 reloc
= BFD_RELOC_16
;
24374 reloc
= BFD_RELOC_32
;
24377 reloc
= BFD_RELOC_64
;
24382 if (exp
->X_op
== O_secrel
)
24384 exp
->X_op
= O_symbol
;
24385 reloc
= BFD_RELOC_32_SECREL
;
24389 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24392 #if defined (OBJ_COFF)
24394 arm_validate_fix (fixS
* fixP
)
24396 /* If the destination of the branch is a defined symbol which does not have
24397 the THUMB_FUNC attribute, then we must be calling a function which has
24398 the (interfacearm) attribute. We look for the Thumb entry point to that
24399 function and change the branch to refer to that function instead. */
24400 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24401 && fixP
->fx_addsy
!= NULL
24402 && S_IS_DEFINED (fixP
->fx_addsy
)
24403 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24405 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24412 arm_force_relocation (struct fix
* fixp
)
24414 #if defined (OBJ_COFF) && defined (TE_PE)
24415 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24419 /* In case we have a call or a branch to a function in ARM ISA mode from
24420 a thumb function or vice-versa force the relocation. These relocations
24421 are cleared off for some cores that might have blx and simple transformations
24425 switch (fixp
->fx_r_type
)
24427 case BFD_RELOC_ARM_PCREL_JUMP
:
24428 case BFD_RELOC_ARM_PCREL_CALL
:
24429 case BFD_RELOC_THUMB_PCREL_BLX
:
24430 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24434 case BFD_RELOC_ARM_PCREL_BLX
:
24435 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24436 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24437 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24438 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24447 /* Resolve these relocations even if the symbol is extern or weak.
24448 Technically this is probably wrong due to symbol preemption.
24449 In practice these relocations do not have enough range to be useful
24450 at dynamic link time, and some code (e.g. in the Linux kernel)
24451 expects these references to be resolved. */
24452 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24453 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24454 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24455 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24456 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24457 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24458 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24459 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24460 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24461 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24462 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24463 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24464 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24465 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24468 /* Always leave these relocations for the linker. */
24469 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24470 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24471 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24474 /* Always generate relocations against function symbols. */
24475 if (fixp
->fx_r_type
== BFD_RELOC_32
24477 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24480 return generic_force_reloc (fixp
);
24483 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24484 /* Relocations against function names must be left unadjusted,
24485 so that the linker can use this information to generate interworking
24486 stubs. The MIPS version of this function
24487 also prevents relocations that are mips-16 specific, but I do not
24488 know why it does this.
24491 There is one other problem that ought to be addressed here, but
24492 which currently is not: Taking the address of a label (rather
24493 than a function) and then later jumping to that address. Such
24494 addresses also ought to have their bottom bit set (assuming that
24495 they reside in Thumb code), but at the moment they will not. */
24498 arm_fix_adjustable (fixS
* fixP
)
24500 if (fixP
->fx_addsy
== NULL
)
24503 /* Preserve relocations against symbols with function type. */
24504 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24507 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24508 && fixP
->fx_subsy
== NULL
)
24511 /* We need the symbol name for the VTABLE entries. */
24512 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24513 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24516 /* Don't allow symbols to be discarded on GOT related relocs. */
24517 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24518 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24519 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24520 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24521 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24522 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24523 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24524 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24525 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24526 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24527 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24528 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24529 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24530 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24533 /* Similarly for group relocations. */
24534 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24535 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24536 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24539 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24540 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24541 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24542 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24543 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24544 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24545 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24546 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24547 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24550 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24551 offsets, so keep these symbols. */
24552 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24553 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24558 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24562 elf32_arm_target_format (void)
24565 return (target_big_endian
24566 ? "elf32-bigarm-symbian"
24567 : "elf32-littlearm-symbian");
24568 #elif defined (TE_VXWORKS)
24569 return (target_big_endian
24570 ? "elf32-bigarm-vxworks"
24571 : "elf32-littlearm-vxworks");
24572 #elif defined (TE_NACL)
24573 return (target_big_endian
24574 ? "elf32-bigarm-nacl"
24575 : "elf32-littlearm-nacl");
24577 if (target_big_endian
)
24578 return "elf32-bigarm";
24580 return "elf32-littlearm";
24585 armelf_frob_symbol (symbolS
* symp
,
24588 elf_frob_symbol (symp
, puntp
);
24592 /* MD interface: Finalization. */
24597 literal_pool
* pool
;
24599 /* Ensure that all the IT blocks are properly closed. */
24600 check_it_blocks_finished ();
24602 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24604 /* Put it at the end of the relevant section. */
24605 subseg_set (pool
->section
, pool
->sub_section
);
24607 arm_elf_change_section ();
24614 /* Remove any excess mapping symbols generated for alignment frags in
24615 SEC. We may have created a mapping symbol before a zero byte
24616 alignment; remove it if there's a mapping symbol after the
24619 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24620 void *dummy ATTRIBUTE_UNUSED
)
24622 segment_info_type
*seginfo
= seg_info (sec
);
24625 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24628 for (fragp
= seginfo
->frchainP
->frch_root
;
24630 fragp
= fragp
->fr_next
)
24632 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24633 fragS
*next
= fragp
->fr_next
;
24635 /* Variable-sized frags have been converted to fixed size by
24636 this point. But if this was variable-sized to start with,
24637 there will be a fixed-size frag after it. So don't handle
24639 if (sym
== NULL
|| next
== NULL
)
24642 if (S_GET_VALUE (sym
) < next
->fr_address
)
24643 /* Not at the end of this frag. */
24645 know (S_GET_VALUE (sym
) == next
->fr_address
);
24649 if (next
->tc_frag_data
.first_map
!= NULL
)
24651 /* Next frag starts with a mapping symbol. Discard this
24653 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24657 if (next
->fr_next
== NULL
)
24659 /* This mapping symbol is at the end of the section. Discard
24661 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24662 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24666 /* As long as we have empty frags without any mapping symbols,
24668 /* If the next frag is non-empty and does not start with a
24669 mapping symbol, then this mapping symbol is required. */
24670 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24673 next
= next
->fr_next
;
24675 while (next
!= NULL
);
24680 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24684 arm_adjust_symtab (void)
24689 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24691 if (ARM_IS_THUMB (sym
))
24693 if (THUMB_IS_FUNC (sym
))
24695 /* Mark the symbol as a Thumb function. */
24696 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24697 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24698 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24700 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24701 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24703 as_bad (_("%s: unexpected function type: %d"),
24704 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24706 else switch (S_GET_STORAGE_CLASS (sym
))
24709 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24712 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24715 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24723 if (ARM_IS_INTERWORK (sym
))
24724 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24731 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24733 if (ARM_IS_THUMB (sym
))
24735 elf_symbol_type
* elf_sym
;
24737 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24738 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24740 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24741 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24743 /* If it's a .thumb_func, declare it as so,
24744 otherwise tag label as .code 16. */
24745 if (THUMB_IS_FUNC (sym
))
24746 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24747 ST_BRANCH_TO_THUMB
);
24748 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24749 elf_sym
->internal_elf_sym
.st_info
=
24750 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24755 /* Remove any overlapping mapping symbols generated by alignment frags. */
24756 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24757 /* Now do generic ELF adjustments. */
24758 elf_adjust_symtab ();
24762 /* MD interface: Initialization. */
24765 set_constant_flonums (void)
24769 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24770 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24774 /* Auto-select Thumb mode if it's the only available instruction set for the
24775 given architecture. */
24778 autoselect_thumb_from_cpu_variant (void)
24780 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24781 opcode_select (16);
24790 if ( (arm_ops_hsh
= hash_new ()) == NULL
24791 || (arm_cond_hsh
= hash_new ()) == NULL
24792 || (arm_shift_hsh
= hash_new ()) == NULL
24793 || (arm_psr_hsh
= hash_new ()) == NULL
24794 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24795 || (arm_reg_hsh
= hash_new ()) == NULL
24796 || (arm_reloc_hsh
= hash_new ()) == NULL
24797 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24798 as_fatal (_("virtual memory exhausted"));
24800 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24801 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24802 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24803 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24804 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24805 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24806 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24807 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24808 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24809 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24810 (void *) (v7m_psrs
+ i
));
24811 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24812 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24814 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24816 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24817 (void *) (barrier_opt_names
+ i
));
24819 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24821 struct reloc_entry
* entry
= reloc_names
+ i
;
24823 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24824 /* This makes encode_branch() use the EABI versions of this relocation. */
24825 entry
->reloc
= BFD_RELOC_UNUSED
;
24827 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24831 set_constant_flonums ();
24833 /* Set the cpu variant based on the command-line options. We prefer
24834 -mcpu= over -march= if both are set (as for GCC); and we prefer
24835 -mfpu= over any other way of setting the floating point unit.
24836 Use of legacy options with new options are faulted. */
24839 if (mcpu_cpu_opt
|| march_cpu_opt
)
24840 as_bad (_("use of old and new-style options to set CPU type"));
24842 mcpu_cpu_opt
= legacy_cpu
;
24844 else if (!mcpu_cpu_opt
)
24845 mcpu_cpu_opt
= march_cpu_opt
;
24850 as_bad (_("use of old and new-style options to set FPU type"));
24852 mfpu_opt
= legacy_fpu
;
24854 else if (!mfpu_opt
)
24856 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24857 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24858 /* Some environments specify a default FPU. If they don't, infer it
24859 from the processor. */
24861 mfpu_opt
= mcpu_fpu_opt
;
24863 mfpu_opt
= march_fpu_opt
;
24865 mfpu_opt
= &fpu_default
;
24871 if (mcpu_cpu_opt
!= NULL
)
24872 mfpu_opt
= &fpu_default
;
24873 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24874 mfpu_opt
= &fpu_arch_vfp_v2
;
24876 mfpu_opt
= &fpu_arch_fpa
;
24882 mcpu_cpu_opt
= &cpu_default
;
24883 selected_cpu
= cpu_default
;
24885 else if (no_cpu_selected ())
24886 selected_cpu
= cpu_default
;
24889 selected_cpu
= *mcpu_cpu_opt
;
24891 mcpu_cpu_opt
= &arm_arch_any
;
24894 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24896 autoselect_thumb_from_cpu_variant ();
24898 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24900 #if defined OBJ_COFF || defined OBJ_ELF
24902 unsigned int flags
= 0;
24904 #if defined OBJ_ELF
24905 flags
= meabi_flags
;
24907 switch (meabi_flags
)
24909 case EF_ARM_EABI_UNKNOWN
:
24911 /* Set the flags in the private structure. */
24912 if (uses_apcs_26
) flags
|= F_APCS26
;
24913 if (support_interwork
) flags
|= F_INTERWORK
;
24914 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24915 if (pic_code
) flags
|= F_PIC
;
24916 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24917 flags
|= F_SOFT_FLOAT
;
24919 switch (mfloat_abi_opt
)
24921 case ARM_FLOAT_ABI_SOFT
:
24922 case ARM_FLOAT_ABI_SOFTFP
:
24923 flags
|= F_SOFT_FLOAT
;
24926 case ARM_FLOAT_ABI_HARD
:
24927 if (flags
& F_SOFT_FLOAT
)
24928 as_bad (_("hard-float conflicts with specified fpu"));
24932 /* Using pure-endian doubles (even if soft-float). */
24933 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24934 flags
|= F_VFP_FLOAT
;
24936 #if defined OBJ_ELF
24937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24938 flags
|= EF_ARM_MAVERICK_FLOAT
;
24941 case EF_ARM_EABI_VER4
:
24942 case EF_ARM_EABI_VER5
:
24943 /* No additional flags to set. */
24950 bfd_set_private_flags (stdoutput
, flags
);
24952 /* We have run out flags in the COFF header to encode the
24953 status of ATPCS support, so instead we create a dummy,
24954 empty, debug section called .arm.atpcs. */
24959 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24963 bfd_set_section_flags
24964 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24965 bfd_set_section_size (stdoutput
, sec
, 0);
24966 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24972 /* Record the CPU type as well. */
24973 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24974 mach
= bfd_mach_arm_iWMMXt2
;
24975 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24976 mach
= bfd_mach_arm_iWMMXt
;
24977 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24978 mach
= bfd_mach_arm_XScale
;
24979 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24980 mach
= bfd_mach_arm_ep9312
;
24981 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24982 mach
= bfd_mach_arm_5TE
;
24983 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24986 mach
= bfd_mach_arm_5T
;
24988 mach
= bfd_mach_arm_5
;
24990 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24993 mach
= bfd_mach_arm_4T
;
24995 mach
= bfd_mach_arm_4
;
24997 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24998 mach
= bfd_mach_arm_3M
;
24999 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25000 mach
= bfd_mach_arm_3
;
25001 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25002 mach
= bfd_mach_arm_2a
;
25003 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25004 mach
= bfd_mach_arm_2
;
25006 mach
= bfd_mach_arm_unknown
;
25008 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25011 /* Command line processing. */
25014 Invocation line includes a switch not recognized by the base assembler.
25015 See if it's a processor-specific option.
25017 This routine is somewhat complicated by the need for backwards
25018 compatibility (since older releases of gcc can't be changed).
25019 The new options try to make the interface as compatible as
25022 New options (supported) are:
25024 -mcpu=<cpu name> Assemble for selected processor
25025 -march=<architecture name> Assemble for selected architecture
25026 -mfpu=<fpu architecture> Assemble for selected FPU.
25027 -EB/-mbig-endian Big-endian
25028 -EL/-mlittle-endian Little-endian
25029 -k Generate PIC code
25030 -mthumb Start in Thumb mode
25031 -mthumb-interwork Code supports ARM/Thumb interworking
25033 -m[no-]warn-deprecated Warn about deprecated features
25034 -m[no-]warn-syms Warn when symbols match instructions
25036 For now we will also provide support for:
25038 -mapcs-32 32-bit Program counter
25039 -mapcs-26 26-bit Program counter
25040 -macps-float Floats passed in FP registers
25041 -mapcs-reentrant Reentrant code
25043 (sometime these will probably be replaced with -mapcs=<list of options>
25044 and -matpcs=<list of options>)
25046 The remaining options are only supported for back-wards compatibility.
25047 Cpu variants, the arm part is optional:
25048 -m[arm]1 Currently not supported.
25049 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25050 -m[arm]3 Arm 3 processor
25051 -m[arm]6[xx], Arm 6 processors
25052 -m[arm]7[xx][t][[d]m] Arm 7 processors
25053 -m[arm]8[10] Arm 8 processors
25054 -m[arm]9[20][tdmi] Arm 9 processors
25055 -mstrongarm[110[0]] StrongARM processors
25056 -mxscale XScale processors
25057 -m[arm]v[2345[t[e]]] Arm architectures
25058 -mall All (except the ARM1)
25060 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25061 -mfpe-old (No float load/store multiples)
25062 -mvfpxd VFP Single precision
25064 -mno-fpu Disable all floating point instructions
25066 The following CPU names are recognized:
25067 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25068 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25069 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25070 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25071 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25072 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25073 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25077 const char * md_shortopts
= "m:k";
25079 #ifdef ARM_BI_ENDIAN
25080 #define OPTION_EB (OPTION_MD_BASE + 0)
25081 #define OPTION_EL (OPTION_MD_BASE + 1)
25083 #if TARGET_BYTES_BIG_ENDIAN
25084 #define OPTION_EB (OPTION_MD_BASE + 0)
25086 #define OPTION_EL (OPTION_MD_BASE + 1)
25089 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25091 struct option md_longopts
[] =
25094 {"EB", no_argument
, NULL
, OPTION_EB
},
25097 {"EL", no_argument
, NULL
, OPTION_EL
},
25099 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25100 {NULL
, no_argument
, NULL
, 0}
25104 size_t md_longopts_size
= sizeof (md_longopts
);
25106 struct arm_option_table
25108 const char *option
; /* Option name to match. */
25109 const char *help
; /* Help information. */
25110 int *var
; /* Variable to change. */
25111 int value
; /* What to change it to. */
25112 const char *deprecated
; /* If non-null, print this message. */
25115 struct arm_option_table arm_opts
[] =
25117 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25118 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25119 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25120 &support_interwork
, 1, NULL
},
25121 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25122 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25123 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25125 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25126 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25127 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25128 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25131 /* These are recognized by the assembler, but have no affect on code. */
25132 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25133 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25135 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25136 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25137 &warn_on_deprecated
, 0, NULL
},
25138 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25139 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25140 {NULL
, NULL
, NULL
, 0, NULL
}
25143 struct arm_legacy_option_table
25145 const char *option
; /* Option name to match. */
25146 const arm_feature_set
**var
; /* Variable to change. */
25147 const arm_feature_set value
; /* What to change it to. */
25148 const char *deprecated
; /* If non-null, print this message. */
25151 const struct arm_legacy_option_table arm_legacy_opts
[] =
25153 /* DON'T add any new processors to this list -- we want the whole list
25154 to go away... Add them to the processors table instead. */
25155 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25156 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25157 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25158 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25159 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25160 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25161 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25162 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25163 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25164 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25165 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25166 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25167 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25168 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25169 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25170 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25171 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25172 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25173 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25174 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25175 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25176 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25177 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25178 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25179 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25180 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25181 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25182 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25183 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25184 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25185 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25186 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25187 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25188 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25189 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25190 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25191 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25192 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25193 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25194 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25195 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25196 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25197 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25198 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25199 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25200 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25201 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25202 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25203 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25204 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25205 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25206 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25207 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25208 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25209 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25210 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25211 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25212 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25213 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25214 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25215 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25216 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25217 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25218 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25219 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25220 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25221 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25222 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25223 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25224 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25225 N_("use -mcpu=strongarm110")},
25226 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25227 N_("use -mcpu=strongarm1100")},
25228 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25229 N_("use -mcpu=strongarm1110")},
25230 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25231 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25232 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25234 /* Architecture variants -- don't add any more to this list either. */
25235 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25236 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25237 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25238 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25239 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25240 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25241 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25242 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25243 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25244 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25245 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25246 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25247 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25248 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25249 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25250 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25251 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25252 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25254 /* Floating point variants -- don't add any more to this list either. */
25255 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25256 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25257 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25258 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25259 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25261 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25264 struct arm_cpu_option_table
25268 const arm_feature_set value
;
25269 /* For some CPUs we assume an FPU unless the user explicitly sets
25271 const arm_feature_set default_fpu
;
25272 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25274 const char *canonical_name
;
25277 /* This list should, at a minimum, contain all the cpu names
25278 recognized by GCC. */
25279 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25280 static const struct arm_cpu_option_table arm_cpus
[] =
25282 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25283 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25284 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25285 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25286 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25287 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25288 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25289 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25290 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25291 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25292 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25293 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25294 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25295 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25296 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25297 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25298 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25299 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25300 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25301 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25302 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25303 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25304 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25305 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25306 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25307 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25308 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25309 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25310 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25311 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25312 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25313 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25314 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25315 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25316 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25317 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25318 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25319 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25320 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25321 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25322 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25323 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25324 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25325 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25326 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25327 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25328 /* For V5 or later processors we default to using VFP; but the user
25329 should really set the FPU type explicitly. */
25330 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25331 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25332 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25333 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25334 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25335 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25336 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25337 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25338 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25339 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25340 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25341 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25342 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25343 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25344 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25345 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25346 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25347 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25348 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25349 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25351 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25352 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25353 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25354 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25355 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25356 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25357 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25358 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25359 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25361 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25362 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25363 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25364 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25365 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25366 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25367 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25368 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25369 FPU_NONE
, "Cortex-A5"),
25370 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25372 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25373 ARM_FEATURE_COPROC (FPU_VFP_V3
25374 | FPU_NEON_EXT_V1
),
25376 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25377 ARM_FEATURE_COPROC (FPU_VFP_V3
25378 | FPU_NEON_EXT_V1
),
25380 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25382 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25384 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25386 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25388 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25390 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25392 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25394 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25396 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25398 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25399 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25401 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25402 FPU_NONE
, "Cortex-R5"),
25403 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25404 FPU_ARCH_VFP_V3D16
,
25406 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25407 FPU_ARCH_VFP_V3D16
,
25409 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25410 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25411 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25412 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25413 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25414 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25415 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25418 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25422 /* ??? XSCALE is really an architecture. */
25423 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25424 /* ??? iwmmxt is not a processor. */
25425 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25426 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25427 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25429 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25430 FPU_ARCH_MAVERICK
, "ARM920T"),
25431 /* Marvell processors. */
25432 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25434 ARM_EXT2_V6T2_V8M
),
25435 FPU_ARCH_VFP_V3D16
, NULL
),
25436 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25438 ARM_EXT2_V6T2_V8M
),
25439 FPU_ARCH_NEON_VFP_V4
, NULL
),
25440 /* APM X-Gene family. */
25441 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25443 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25446 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25450 struct arm_arch_option_table
25454 const arm_feature_set value
;
25455 const arm_feature_set default_fpu
;
25458 /* This list should, at a minimum, contain all the architecture names
25459 recognized by GCC. */
25460 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25461 static const struct arm_arch_option_table arm_archs
[] =
25463 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25464 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25465 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25466 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25467 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25468 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25469 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25470 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25471 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25472 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25473 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25474 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25475 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25476 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25477 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25478 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25479 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25480 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25481 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25482 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25483 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25484 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25485 kept to preserve existing behaviour. */
25486 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25487 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25488 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25489 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25490 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25491 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25492 kept to preserve existing behaviour. */
25493 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25494 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25495 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25496 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25497 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25498 /* The official spelling of the ARMv7 profile variants is the dashed form.
25499 Accept the non-dashed form for compatibility with old toolchains. */
25500 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25501 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25502 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25503 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25504 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25505 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25506 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25507 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25508 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25509 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25510 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25511 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25512 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25513 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25514 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25515 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25516 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25518 #undef ARM_ARCH_OPT
25520 /* ISA extensions in the co-processor and main instruction set space. */
25521 struct arm_option_extension_value_table
25525 const arm_feature_set merge_value
;
25526 const arm_feature_set clear_value
;
25527 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25528 indicates that an extension is available for all architectures while
25529 ARM_ANY marks an empty entry. */
25530 const arm_feature_set allowed_archs
[2];
25533 /* The following table must be in alphabetical order with a NULL last entry.
25535 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25536 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25537 static const struct arm_option_extension_value_table arm_extensions
[] =
25539 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25540 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25541 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25542 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25543 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25544 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25545 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25546 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25547 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25548 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25549 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25550 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25552 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25553 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25554 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25555 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25556 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25557 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25558 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25559 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25560 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25561 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25562 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25563 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25564 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25565 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25566 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25567 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25568 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25569 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25570 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25571 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25572 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25573 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25574 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25575 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25576 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25577 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25578 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25579 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25580 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25581 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25582 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25583 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25584 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25585 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25587 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25588 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25589 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25590 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25591 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25595 /* ISA floating-point and Advanced SIMD extensions. */
25596 struct arm_option_fpu_value_table
25599 const arm_feature_set value
;
25602 /* This list should, at a minimum, contain all the fpu names
25603 recognized by GCC. */
25604 static const struct arm_option_fpu_value_table arm_fpus
[] =
25606 {"softfpa", FPU_NONE
},
25607 {"fpe", FPU_ARCH_FPE
},
25608 {"fpe2", FPU_ARCH_FPE
},
25609 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25610 {"fpa", FPU_ARCH_FPA
},
25611 {"fpa10", FPU_ARCH_FPA
},
25612 {"fpa11", FPU_ARCH_FPA
},
25613 {"arm7500fe", FPU_ARCH_FPA
},
25614 {"softvfp", FPU_ARCH_VFP
},
25615 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25616 {"vfp", FPU_ARCH_VFP_V2
},
25617 {"vfp9", FPU_ARCH_VFP_V2
},
25618 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25619 {"vfp10", FPU_ARCH_VFP_V2
},
25620 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25621 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25622 {"vfpv2", FPU_ARCH_VFP_V2
},
25623 {"vfpv3", FPU_ARCH_VFP_V3
},
25624 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25625 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25626 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25627 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25628 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25629 {"arm1020t", FPU_ARCH_VFP_V1
},
25630 {"arm1020e", FPU_ARCH_VFP_V2
},
25631 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25632 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25633 {"maverick", FPU_ARCH_MAVERICK
},
25634 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25635 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25636 {"vfpv4", FPU_ARCH_VFP_V4
},
25637 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25638 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25639 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25640 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25641 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25642 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25643 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25644 {"crypto-neon-fp-armv8",
25645 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25646 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25647 {"crypto-neon-fp-armv8.1",
25648 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25649 {NULL
, ARM_ARCH_NONE
}
25652 struct arm_option_value_table
25658 static const struct arm_option_value_table arm_float_abis
[] =
25660 {"hard", ARM_FLOAT_ABI_HARD
},
25661 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25662 {"soft", ARM_FLOAT_ABI_SOFT
},
25667 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25668 static const struct arm_option_value_table arm_eabis
[] =
25670 {"gnu", EF_ARM_EABI_UNKNOWN
},
25671 {"4", EF_ARM_EABI_VER4
},
25672 {"5", EF_ARM_EABI_VER5
},
25677 struct arm_long_option_table
25679 const char * option
; /* Substring to match. */
25680 const char * help
; /* Help information. */
25681 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25682 const char * deprecated
; /* If non-null, print this message. */
25686 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25688 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25690 /* We insist on extensions being specified in alphabetical order, and with
25691 extensions being added before being removed. We achieve this by having
25692 the global ARM_EXTENSIONS table in alphabetical order, and using the
25693 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25694 or removing it (0) and only allowing it to change in the order
25696 const struct arm_option_extension_value_table
* opt
= NULL
;
25697 const arm_feature_set arm_any
= ARM_ANY
;
25698 int adding_value
= -1;
25700 /* Copy the feature set, so that we can modify it. */
25701 *ext_set
= **opt_p
;
25704 while (str
!= NULL
&& *str
!= 0)
25711 as_bad (_("invalid architectural extension"));
25716 ext
= strchr (str
, '+');
25721 len
= strlen (str
);
25723 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25725 if (adding_value
!= 0)
25728 opt
= arm_extensions
;
25736 if (adding_value
== -1)
25739 opt
= arm_extensions
;
25741 else if (adding_value
!= 1)
25743 as_bad (_("must specify extensions to add before specifying "
25744 "those to remove"));
25751 as_bad (_("missing architectural extension"));
25755 gas_assert (adding_value
!= -1);
25756 gas_assert (opt
!= NULL
);
25758 /* Scan over the options table trying to find an exact match. */
25759 for (; opt
->name
!= NULL
; opt
++)
25760 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25762 int i
, nb_allowed_archs
=
25763 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25764 /* Check we can apply the extension to this architecture. */
25765 for (i
= 0; i
< nb_allowed_archs
; i
++)
25768 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25770 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25773 if (i
== nb_allowed_archs
)
25775 as_bad (_("extension does not apply to the base architecture"));
25779 /* Add or remove the extension. */
25781 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25783 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25788 if (opt
->name
== NULL
)
25790 /* Did we fail to find an extension because it wasn't specified in
25791 alphabetical order, or because it does not exist? */
25793 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25794 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25797 if (opt
->name
== NULL
)
25798 as_bad (_("unknown architectural extension `%s'"), str
);
25800 as_bad (_("architectural extensions must be specified in "
25801 "alphabetical order"));
25807 /* We should skip the extension we've just matched the next time
25819 arm_parse_cpu (const char *str
)
25821 const struct arm_cpu_option_table
*opt
;
25822 const char *ext
= strchr (str
, '+');
25828 len
= strlen (str
);
25832 as_bad (_("missing cpu name `%s'"), str
);
25836 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25837 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25839 mcpu_cpu_opt
= &opt
->value
;
25840 mcpu_fpu_opt
= &opt
->default_fpu
;
25841 if (opt
->canonical_name
)
25843 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25844 strcpy (selected_cpu_name
, opt
->canonical_name
);
25850 if (len
>= sizeof selected_cpu_name
)
25851 len
= (sizeof selected_cpu_name
) - 1;
25853 for (i
= 0; i
< len
; i
++)
25854 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25855 selected_cpu_name
[i
] = 0;
25859 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25864 as_bad (_("unknown cpu `%s'"), str
);
25869 arm_parse_arch (const char *str
)
25871 const struct arm_arch_option_table
*opt
;
25872 const char *ext
= strchr (str
, '+');
25878 len
= strlen (str
);
25882 as_bad (_("missing architecture name `%s'"), str
);
25886 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25887 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25889 march_cpu_opt
= &opt
->value
;
25890 march_fpu_opt
= &opt
->default_fpu
;
25891 strcpy (selected_cpu_name
, opt
->name
);
25894 return arm_parse_extension (ext
, &march_cpu_opt
);
25899 as_bad (_("unknown architecture `%s'\n"), str
);
25904 arm_parse_fpu (const char * str
)
25906 const struct arm_option_fpu_value_table
* opt
;
25908 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25909 if (streq (opt
->name
, str
))
25911 mfpu_opt
= &opt
->value
;
25915 as_bad (_("unknown floating point format `%s'\n"), str
);
25920 arm_parse_float_abi (const char * str
)
25922 const struct arm_option_value_table
* opt
;
25924 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25925 if (streq (opt
->name
, str
))
25927 mfloat_abi_opt
= opt
->value
;
25931 as_bad (_("unknown floating point abi `%s'\n"), str
);
25937 arm_parse_eabi (const char * str
)
25939 const struct arm_option_value_table
*opt
;
25941 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25942 if (streq (opt
->name
, str
))
25944 meabi_flags
= opt
->value
;
25947 as_bad (_("unknown EABI `%s'\n"), str
);
25953 arm_parse_it_mode (const char * str
)
25955 bfd_boolean ret
= TRUE
;
25957 if (streq ("arm", str
))
25958 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25959 else if (streq ("thumb", str
))
25960 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25961 else if (streq ("always", str
))
25962 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25963 else if (streq ("never", str
))
25964 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25967 as_bad (_("unknown implicit IT mode `%s', should be "\
25968 "arm, thumb, always, or never."), str
);
25976 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25978 codecomposer_syntax
= TRUE
;
25979 arm_comment_chars
[0] = ';';
25980 arm_line_separator_chars
[0] = 0;
25984 struct arm_long_option_table arm_long_opts
[] =
25986 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25987 arm_parse_cpu
, NULL
},
25988 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25989 arm_parse_arch
, NULL
},
25990 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25991 arm_parse_fpu
, NULL
},
25992 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25993 arm_parse_float_abi
, NULL
},
25995 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25996 arm_parse_eabi
, NULL
},
25998 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25999 arm_parse_it_mode
, NULL
},
26000 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26001 arm_ccs_mode
, NULL
},
26002 {NULL
, NULL
, 0, NULL
}
26006 md_parse_option (int c
, const char * arg
)
26008 struct arm_option_table
*opt
;
26009 const struct arm_legacy_option_table
*fopt
;
26010 struct arm_long_option_table
*lopt
;
26016 target_big_endian
= 1;
26022 target_big_endian
= 0;
26026 case OPTION_FIX_V4BX
:
26031 /* Listing option. Just ignore these, we don't support additional
26036 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26038 if (c
== opt
->option
[0]
26039 && ((arg
== NULL
&& opt
->option
[1] == 0)
26040 || streq (arg
, opt
->option
+ 1)))
26042 /* If the option is deprecated, tell the user. */
26043 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26044 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26045 arg
? arg
: "", _(opt
->deprecated
));
26047 if (opt
->var
!= NULL
)
26048 *opt
->var
= opt
->value
;
26054 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26056 if (c
== fopt
->option
[0]
26057 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26058 || streq (arg
, fopt
->option
+ 1)))
26060 /* If the option is deprecated, tell the user. */
26061 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26062 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26063 arg
? arg
: "", _(fopt
->deprecated
));
26065 if (fopt
->var
!= NULL
)
26066 *fopt
->var
= &fopt
->value
;
26072 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26074 /* These options are expected to have an argument. */
26075 if (c
== lopt
->option
[0]
26077 && strncmp (arg
, lopt
->option
+ 1,
26078 strlen (lopt
->option
+ 1)) == 0)
26080 /* If the option is deprecated, tell the user. */
26081 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26082 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26083 _(lopt
->deprecated
));
26085 /* Call the sup-option parser. */
26086 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26097 md_show_usage (FILE * fp
)
26099 struct arm_option_table
*opt
;
26100 struct arm_long_option_table
*lopt
;
26102 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26104 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26105 if (opt
->help
!= NULL
)
26106 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26108 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26109 if (lopt
->help
!= NULL
)
26110 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26114 -EB assemble code for a big-endian cpu\n"));
26119 -EL assemble code for a little-endian cpu\n"));
26123 --fix-v4bx Allow BX in ARMv4 code\n"));
26131 arm_feature_set flags
;
26132 } cpu_arch_ver_table
;
26134 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26135 must be sorted least features first but some reordering is needed, eg. for
26136 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26137 static const cpu_arch_ver_table cpu_arch_ver
[] =
26143 {4, ARM_ARCH_V5TE
},
26144 {5, ARM_ARCH_V5TEJ
},
26148 {11, ARM_ARCH_V6M
},
26149 {12, ARM_ARCH_V6SM
},
26150 {8, ARM_ARCH_V6T2
},
26151 {10, ARM_ARCH_V7VE
},
26152 {10, ARM_ARCH_V7R
},
26153 {10, ARM_ARCH_V7M
},
26154 {14, ARM_ARCH_V8A
},
26155 {16, ARM_ARCH_V8M_BASE
},
26156 {17, ARM_ARCH_V8M_MAIN
},
26160 /* Set an attribute if it has not already been set by the user. */
26162 aeabi_set_attribute_int (int tag
, int value
)
26165 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26166 || !attributes_set_explicitly
[tag
])
26167 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26171 aeabi_set_attribute_string (int tag
, const char *value
)
26174 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26175 || !attributes_set_explicitly
[tag
])
26176 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26179 /* Set the public EABI object attributes. */
26181 aeabi_set_public_attributes (void)
26186 int fp16_optional
= 0;
26187 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26188 arm_feature_set flags
;
26189 arm_feature_set tmp
;
26190 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26191 const cpu_arch_ver_table
*p
;
26193 /* Choose the architecture based on the capabilities of the requested cpu
26194 (if any) and/or the instructions actually used. */
26195 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26196 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26197 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26199 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26200 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26202 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26203 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26205 selected_cpu
= flags
;
26207 /* Allow the user to override the reported architecture. */
26210 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26211 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26214 /* We need to make sure that the attributes do not identify us as v6S-M
26215 when the only v6S-M feature in use is the Operating System Extensions. */
26216 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26217 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26218 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26222 for (p
= cpu_arch_ver
; p
->val
; p
++)
26224 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26227 arm_arch
= p
->flags
;
26228 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26232 /* The table lookup above finds the last architecture to contribute
26233 a new feature. Unfortunately, Tag13 is a subset of the union of
26234 v6T2 and v7-M, so it is never seen as contributing a new feature.
26235 We can not search for the last entry which is entirely used,
26236 because if no CPU is specified we build up only those flags
26237 actually used. Perhaps we should separate out the specified
26238 and implicit cases. Avoid taking this path for -march=all by
26239 checking for contradictory v7-A / v7-M features. */
26240 if (arch
== TAG_CPU_ARCH_V7
26241 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26242 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26243 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26245 arch
= TAG_CPU_ARCH_V7E_M
;
26246 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26249 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26250 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26252 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26253 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26256 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26257 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26258 ARMv8-M, -march=all must be detected as ARMv8-A. */
26259 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26260 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26262 arch
= TAG_CPU_ARCH_V8
;
26263 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26266 /* Tag_CPU_name. */
26267 if (selected_cpu_name
[0])
26271 q
= selected_cpu_name
;
26272 if (strncmp (q
, "armv", 4) == 0)
26277 for (i
= 0; q
[i
]; i
++)
26278 q
[i
] = TOUPPER (q
[i
]);
26280 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26283 /* Tag_CPU_arch. */
26284 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26286 /* Tag_CPU_arch_profile. */
26287 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26288 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26289 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26290 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26292 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26294 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26299 if (profile
!= '\0')
26300 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26302 /* Tag_DSP_extension. */
26303 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26305 arm_feature_set ext
;
26307 /* DSP instructions not in architecture. */
26308 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26309 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26310 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26313 /* Tag_ARM_ISA_use. */
26314 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26316 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26318 /* Tag_THUMB_ISA_use. */
26319 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26324 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26325 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26327 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26331 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26334 /* Tag_VFP_arch. */
26335 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26336 aeabi_set_attribute_int (Tag_VFP_arch
,
26337 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26339 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26340 aeabi_set_attribute_int (Tag_VFP_arch
,
26341 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26343 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26346 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26348 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26350 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26353 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26354 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26355 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26356 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26357 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26359 /* Tag_ABI_HardFP_use. */
26360 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26361 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26362 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26364 /* Tag_WMMX_arch. */
26365 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26366 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26367 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26368 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26370 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26371 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26372 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26373 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26374 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26375 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26377 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26379 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26383 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26388 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26389 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26390 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26394 We set Tag_DIV_use to two when integer divide instructions have been used
26395 in ARM state, or when Thumb integer divide instructions have been used,
26396 but we have no architecture profile set, nor have we any ARM instructions.
26398 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26399 by the base architecture.
26401 For new architectures we will have to check these tests. */
26402 gas_assert (arch
<= TAG_CPU_ARCH_V8
26403 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26404 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26405 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26406 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26407 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26408 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26409 || (profile
== '\0'
26410 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26411 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26412 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26414 /* Tag_MP_extension_use. */
26415 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26416 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26418 /* Tag Virtualization_use. */
26419 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26421 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26424 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26427 /* Add the default contents for the .ARM.attributes section. */
26431 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26434 aeabi_set_public_attributes ();
26436 #endif /* OBJ_ELF */
26439 /* Parse a .cpu directive. */
26442 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26444 const struct arm_cpu_option_table
*opt
;
26448 name
= input_line_pointer
;
26449 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26450 input_line_pointer
++;
26451 saved_char
= *input_line_pointer
;
26452 *input_line_pointer
= 0;
26454 /* Skip the first "all" entry. */
26455 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26456 if (streq (opt
->name
, name
))
26458 mcpu_cpu_opt
= &opt
->value
;
26459 selected_cpu
= opt
->value
;
26460 if (opt
->canonical_name
)
26461 strcpy (selected_cpu_name
, opt
->canonical_name
);
26465 for (i
= 0; opt
->name
[i
]; i
++)
26466 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26468 selected_cpu_name
[i
] = 0;
26470 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26471 *input_line_pointer
= saved_char
;
26472 demand_empty_rest_of_line ();
26475 as_bad (_("unknown cpu `%s'"), name
);
26476 *input_line_pointer
= saved_char
;
26477 ignore_rest_of_line ();
26481 /* Parse a .arch directive. */
26484 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26486 const struct arm_arch_option_table
*opt
;
26490 name
= input_line_pointer
;
26491 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26492 input_line_pointer
++;
26493 saved_char
= *input_line_pointer
;
26494 *input_line_pointer
= 0;
26496 /* Skip the first "all" entry. */
26497 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26498 if (streq (opt
->name
, name
))
26500 mcpu_cpu_opt
= &opt
->value
;
26501 selected_cpu
= opt
->value
;
26502 strcpy (selected_cpu_name
, opt
->name
);
26503 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26504 *input_line_pointer
= saved_char
;
26505 demand_empty_rest_of_line ();
26509 as_bad (_("unknown architecture `%s'\n"), name
);
26510 *input_line_pointer
= saved_char
;
26511 ignore_rest_of_line ();
26515 /* Parse a .object_arch directive. */
26518 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26520 const struct arm_arch_option_table
*opt
;
26524 name
= input_line_pointer
;
26525 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26526 input_line_pointer
++;
26527 saved_char
= *input_line_pointer
;
26528 *input_line_pointer
= 0;
26530 /* Skip the first "all" entry. */
26531 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26532 if (streq (opt
->name
, name
))
26534 object_arch
= &opt
->value
;
26535 *input_line_pointer
= saved_char
;
26536 demand_empty_rest_of_line ();
26540 as_bad (_("unknown architecture `%s'\n"), name
);
26541 *input_line_pointer
= saved_char
;
26542 ignore_rest_of_line ();
26545 /* Parse a .arch_extension directive. */
26548 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26550 const struct arm_option_extension_value_table
*opt
;
26551 const arm_feature_set arm_any
= ARM_ANY
;
26554 int adding_value
= 1;
26556 name
= input_line_pointer
;
26557 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26558 input_line_pointer
++;
26559 saved_char
= *input_line_pointer
;
26560 *input_line_pointer
= 0;
26562 if (strlen (name
) >= 2
26563 && strncmp (name
, "no", 2) == 0)
26569 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26570 if (streq (opt
->name
, name
))
26572 int i
, nb_allowed_archs
=
26573 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26574 for (i
= 0; i
< nb_allowed_archs
; i
++)
26577 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26579 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26583 if (i
== nb_allowed_archs
)
26585 as_bad (_("architectural extension `%s' is not allowed for the "
26586 "current base architecture"), name
);
26591 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26594 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26596 mcpu_cpu_opt
= &selected_cpu
;
26597 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26598 *input_line_pointer
= saved_char
;
26599 demand_empty_rest_of_line ();
26603 if (opt
->name
== NULL
)
26604 as_bad (_("unknown architecture extension `%s'\n"), name
);
26606 *input_line_pointer
= saved_char
;
26607 ignore_rest_of_line ();
26610 /* Parse a .fpu directive. */
26613 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26615 const struct arm_option_fpu_value_table
*opt
;
26619 name
= input_line_pointer
;
26620 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26621 input_line_pointer
++;
26622 saved_char
= *input_line_pointer
;
26623 *input_line_pointer
= 0;
26625 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26626 if (streq (opt
->name
, name
))
26628 mfpu_opt
= &opt
->value
;
26629 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26630 *input_line_pointer
= saved_char
;
26631 demand_empty_rest_of_line ();
26635 as_bad (_("unknown floating point format `%s'\n"), name
);
26636 *input_line_pointer
= saved_char
;
26637 ignore_rest_of_line ();
26640 /* Copy symbol information. */
26643 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26645 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26649 /* Given a symbolic attribute NAME, return the proper integer value.
26650 Returns -1 if the attribute is not known. */
26653 arm_convert_symbolic_attribute (const char *name
)
26655 static const struct
26660 attribute_table
[] =
26662 /* When you modify this table you should
26663 also modify the list in doc/c-arm.texi. */
26664 #define T(tag) {#tag, tag}
26665 T (Tag_CPU_raw_name
),
26668 T (Tag_CPU_arch_profile
),
26669 T (Tag_ARM_ISA_use
),
26670 T (Tag_THUMB_ISA_use
),
26674 T (Tag_Advanced_SIMD_arch
),
26675 T (Tag_PCS_config
),
26676 T (Tag_ABI_PCS_R9_use
),
26677 T (Tag_ABI_PCS_RW_data
),
26678 T (Tag_ABI_PCS_RO_data
),
26679 T (Tag_ABI_PCS_GOT_use
),
26680 T (Tag_ABI_PCS_wchar_t
),
26681 T (Tag_ABI_FP_rounding
),
26682 T (Tag_ABI_FP_denormal
),
26683 T (Tag_ABI_FP_exceptions
),
26684 T (Tag_ABI_FP_user_exceptions
),
26685 T (Tag_ABI_FP_number_model
),
26686 T (Tag_ABI_align_needed
),
26687 T (Tag_ABI_align8_needed
),
26688 T (Tag_ABI_align_preserved
),
26689 T (Tag_ABI_align8_preserved
),
26690 T (Tag_ABI_enum_size
),
26691 T (Tag_ABI_HardFP_use
),
26692 T (Tag_ABI_VFP_args
),
26693 T (Tag_ABI_WMMX_args
),
26694 T (Tag_ABI_optimization_goals
),
26695 T (Tag_ABI_FP_optimization_goals
),
26696 T (Tag_compatibility
),
26697 T (Tag_CPU_unaligned_access
),
26698 T (Tag_FP_HP_extension
),
26699 T (Tag_VFP_HP_extension
),
26700 T (Tag_ABI_FP_16bit_format
),
26701 T (Tag_MPextension_use
),
26703 T (Tag_nodefaults
),
26704 T (Tag_also_compatible_with
),
26705 T (Tag_conformance
),
26707 T (Tag_Virtualization_use
),
26708 T (Tag_DSP_extension
),
26709 /* We deliberately do not include Tag_MPextension_use_legacy. */
26717 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26718 if (streq (name
, attribute_table
[i
].name
))
26719 return attribute_table
[i
].tag
;
26725 /* Apply sym value for relocations only in the case that they are for
26726 local symbols in the same segment as the fixup and you have the
26727 respective architectural feature for blx and simple switches. */
26729 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26732 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26733 /* PR 17444: If the local symbol is in a different section then a reloc
26734 will always be generated for it, so applying the symbol value now
26735 will result in a double offset being stored in the relocation. */
26736 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26737 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26739 switch (fixP
->fx_r_type
)
26741 case BFD_RELOC_ARM_PCREL_BLX
:
26742 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26743 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26747 case BFD_RELOC_ARM_PCREL_CALL
:
26748 case BFD_RELOC_THUMB_PCREL_BLX
:
26749 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26760 #endif /* OBJ_ELF */