1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
*dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static arm_feature_set
*dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
*march_fpu_opt
= NULL
;
155 static const arm_feature_set
*mfpu_opt
= NULL
;
156 static const arm_feature_set
*object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_v8_3
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
241 static const arm_feature_set arm_arch_any
= ARM_ANY
;
243 static const arm_feature_set fpu_any
= FPU_ANY
;
245 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
246 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
247 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
249 static const arm_feature_set arm_cext_iwmmxt2
=
250 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
251 static const arm_feature_set arm_cext_iwmmxt
=
252 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
253 static const arm_feature_set arm_cext_xscale
=
254 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
255 static const arm_feature_set arm_cext_maverick
=
256 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
257 static const arm_feature_set fpu_fpa_ext_v1
=
258 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
259 static const arm_feature_set fpu_fpa_ext_v2
=
260 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
261 static const arm_feature_set fpu_vfp_ext_v1xd
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
263 static const arm_feature_set fpu_vfp_ext_v1
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
265 static const arm_feature_set fpu_vfp_ext_v2
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
267 static const arm_feature_set fpu_vfp_ext_v3xd
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
269 static const arm_feature_set fpu_vfp_ext_v3
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
271 static const arm_feature_set fpu_vfp_ext_d32
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
273 static const arm_feature_set fpu_neon_ext_v1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
275 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
276 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
278 static const arm_feature_set fpu_vfp_fp16
=
279 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
280 static const arm_feature_set fpu_neon_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
283 static const arm_feature_set fpu_vfp_ext_fma
=
284 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
285 static const arm_feature_set fpu_vfp_ext_armv8
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
287 static const arm_feature_set fpu_vfp_ext_armv8xd
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
289 static const arm_feature_set fpu_neon_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
291 static const arm_feature_set fpu_crypto_ext_armv8
=
292 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
293 static const arm_feature_set crc_ext_armv8
=
294 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
295 static const arm_feature_set fpu_neon_ext_v8_1
=
296 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
298 static int mfloat_abi_opt
= -1;
299 /* Record user cpu selection for object attributes. */
300 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
301 /* Must be long enough to hold any of the names in arm_cpus. */
302 static char selected_cpu_name
[20];
304 extern FLONUM_TYPE generic_floating_point_number
;
306 /* Return if no cpu was selected on command-line. */
308 no_cpu_selected (void)
310 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
315 static int meabi_flags
= EABI_DEFAULT
;
317 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
320 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
325 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
330 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
331 symbolS
* GOT_symbol
;
334 /* 0: assemble for ARM,
335 1: assemble for Thumb,
336 2: assemble for Thumb even though target CPU does not support thumb
338 static int thumb_mode
= 0;
339 /* A value distinct from the possible values for thumb_mode that we
340 can use to record whether thumb_mode has been copied into the
341 tc_frag_data field of a frag. */
342 #define MODE_RECORDED (1 << 4)
344 /* Specifies the intrinsic IT insn behavior mode. */
345 enum implicit_it_mode
347 IMPLICIT_IT_MODE_NEVER
= 0x00,
348 IMPLICIT_IT_MODE_ARM
= 0x01,
349 IMPLICIT_IT_MODE_THUMB
= 0x02,
350 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
352 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
354 /* If unified_syntax is true, we are processing the new unified
355 ARM/Thumb syntax. Important differences from the old ARM mode:
357 - Immediate operands do not require a # prefix.
358 - Conditional affixes always appear at the end of the
359 instruction. (For backward compatibility, those instructions
360 that formerly had them in the middle, continue to accept them
362 - The IT instruction may appear, and if it does is validated
363 against subsequent conditional affixes. It does not generate
366 Important differences from the old Thumb mode:
368 - Immediate operands do not require a # prefix.
369 - Most of the V6T2 instructions are only available in unified mode.
370 - The .N and .W suffixes are recognized and honored (it is an error
371 if they cannot be honored).
372 - All instructions set the flags if and only if they have an 's' affix.
373 - Conditional affixes may be used. They are validated against
374 preceding IT instructions. Unlike ARM mode, you cannot use a
375 conditional affix except in the scope of an IT instruction. */
377 static bfd_boolean unified_syntax
= FALSE
;
379 /* An immediate operand can start with #, and ld*, st*, pld operands
380 can contain [ and ]. We need to tell APP not to elide whitespace
381 before a [, which can appear as the first operand for pld.
382 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
383 const char arm_symbol_chars
[] = "#[]{}";
398 enum neon_el_type type
;
402 #define NEON_MAX_TYPE_ELS 4
406 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
410 enum it_instruction_type
415 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
416 if inside, should be the last one. */
417 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
418 i.e. BKPT and NOP. */
419 IT_INSN
/* The IT insn has been parsed. */
422 /* The maximum number of operands we need. */
423 #define ARM_IT_MAX_OPERANDS 6
428 unsigned long instruction
;
432 /* "uncond_value" is set to the value in place of the conditional field in
433 unconditional versions of the instruction, or -1 if nothing is
436 struct neon_type vectype
;
437 /* This does not indicate an actual NEON instruction, only that
438 the mnemonic accepts neon-style type suffixes. */
440 /* Set to the opcode if the instruction needs relaxation.
441 Zero if the instruction is not relaxed. */
445 bfd_reloc_code_real_type type
;
450 enum it_instruction_type it_insn_type
;
456 struct neon_type_el vectype
;
457 unsigned present
: 1; /* Operand present. */
458 unsigned isreg
: 1; /* Operand was a register. */
459 unsigned immisreg
: 1; /* .imm field is a second register. */
460 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
461 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
462 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
463 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
464 instructions. This allows us to disambiguate ARM <-> vector insns. */
465 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
466 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
467 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
468 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
469 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
470 unsigned writeback
: 1; /* Operand has trailing ! */
471 unsigned preind
: 1; /* Preindexed address. */
472 unsigned postind
: 1; /* Postindexed address. */
473 unsigned negative
: 1; /* Index register was negated. */
474 unsigned shifted
: 1; /* Shift applied to operation. */
475 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
476 } operands
[ARM_IT_MAX_OPERANDS
];
479 static struct arm_it inst
;
481 #define NUM_FLOAT_VALS 8
483 const char * fp_const
[] =
485 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
488 /* Number of littlenums required to hold an extended precision number. */
489 #define MAX_LITTLENUMS 6
491 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
501 #define CP_T_X 0x00008000
502 #define CP_T_Y 0x00400000
504 #define CONDS_BIT 0x00100000
505 #define LOAD_BIT 0x00100000
507 #define DOUBLE_LOAD_FLAG 0x00000001
511 const char * template_name
;
515 #define COND_ALWAYS 0xE
519 const char * template_name
;
523 struct asm_barrier_opt
525 const char * template_name
;
527 const arm_feature_set arch
;
530 /* The bit that distinguishes CPSR and SPSR. */
531 #define SPSR_BIT (1 << 22)
533 /* The individual PSR flag bits. */
534 #define PSR_c (1 << 16)
535 #define PSR_x (1 << 17)
536 #define PSR_s (1 << 18)
537 #define PSR_f (1 << 19)
542 bfd_reloc_code_real_type reloc
;
547 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
548 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
553 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
556 /* Bits for DEFINED field in neon_typed_alias. */
557 #define NTA_HASTYPE 1
558 #define NTA_HASINDEX 2
560 struct neon_typed_alias
562 unsigned char defined
;
564 struct neon_type_el eltype
;
567 /* ARM register categories. This includes coprocessor numbers and various
568 architecture extensions' registers. */
595 /* Structure for a hash table entry for a register.
596 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
597 information which states whether a vector type or index is specified (for a
598 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
604 unsigned char builtin
;
605 struct neon_typed_alias
* neon
;
608 /* Diagnostics used when we don't get a register of the expected type. */
609 const char * const reg_expected_msgs
[] =
611 N_("ARM register expected"),
612 N_("bad or missing co-processor number"),
613 N_("co-processor register expected"),
614 N_("FPA register expected"),
615 N_("VFP single precision register expected"),
616 N_("VFP/Neon double precision register expected"),
617 N_("Neon quad precision register expected"),
618 N_("VFP single or double precision register expected"),
619 N_("Neon double or quad precision register expected"),
620 N_("VFP single, double or Neon quad precision register expected"),
621 N_("VFP system register expected"),
622 N_("Maverick MVF register expected"),
623 N_("Maverick MVD register expected"),
624 N_("Maverick MVFX register expected"),
625 N_("Maverick MVDX register expected"),
626 N_("Maverick MVAX register expected"),
627 N_("Maverick DSPSC register expected"),
628 N_("iWMMXt data register expected"),
629 N_("iWMMXt control register expected"),
630 N_("iWMMXt scalar register expected"),
631 N_("XScale accumulator register expected"),
634 /* Some well known registers that we refer to directly elsewhere. */
640 /* ARM instructions take 4bytes in the object file, Thumb instructions
646 /* Basic string to match. */
647 const char * template_name
;
649 /* Parameters to instruction. */
650 unsigned int operands
[8];
652 /* Conditional tag - see opcode_lookup. */
653 unsigned int tag
: 4;
655 /* Basic instruction code. */
656 unsigned int avalue
: 28;
658 /* Thumb-format instruction code. */
661 /* Which architecture variant provides this instruction. */
662 const arm_feature_set
* avariant
;
663 const arm_feature_set
* tvariant
;
665 /* Function to call to encode instruction in ARM format. */
666 void (* aencode
) (void);
668 /* Function to call to encode instruction in Thumb format. */
669 void (* tencode
) (void);
672 /* Defines for various bits that we will want to toggle. */
673 #define INST_IMMEDIATE 0x02000000
674 #define OFFSET_REG 0x02000000
675 #define HWOFFSET_IMM 0x00400000
676 #define SHIFT_BY_REG 0x00000010
677 #define PRE_INDEX 0x01000000
678 #define INDEX_UP 0x00800000
679 #define WRITE_BACK 0x00200000
680 #define LDM_TYPE_2_OR_3 0x00400000
681 #define CPSI_MMOD 0x00020000
683 #define LITERAL_MASK 0xf000f000
684 #define OPCODE_MASK 0xfe1fffff
685 #define V4_STR_BIT 0x00000020
686 #define VLDR_VMOV_SAME 0x0040f000
688 #define T2_SUBS_PC_LR 0xf3de8f00
690 #define DATA_OP_SHIFT 21
691 #define SBIT_SHIFT 20
693 #define T2_OPCODE_MASK 0xfe1fffff
694 #define T2_DATA_OP_SHIFT 21
695 #define T2_SBIT_SHIFT 20
697 #define A_COND_MASK 0xf0000000
698 #define A_PUSH_POP_OP_MASK 0x0fff0000
700 /* Opcodes for pushing/poping registers to/from the stack. */
701 #define A1_OPCODE_PUSH 0x092d0000
702 #define A2_OPCODE_PUSH 0x052d0004
703 #define A2_OPCODE_POP 0x049d0004
705 /* Codes to distinguish the arithmetic instructions. */
716 #define OPCODE_CMP 10
717 #define OPCODE_CMN 11
718 #define OPCODE_ORR 12
719 #define OPCODE_MOV 13
720 #define OPCODE_BIC 14
721 #define OPCODE_MVN 15
723 #define T2_OPCODE_AND 0
724 #define T2_OPCODE_BIC 1
725 #define T2_OPCODE_ORR 2
726 #define T2_OPCODE_ORN 3
727 #define T2_OPCODE_EOR 4
728 #define T2_OPCODE_ADD 8
729 #define T2_OPCODE_ADC 10
730 #define T2_OPCODE_SBC 11
731 #define T2_OPCODE_SUB 13
732 #define T2_OPCODE_RSB 14
734 #define T_OPCODE_MUL 0x4340
735 #define T_OPCODE_TST 0x4200
736 #define T_OPCODE_CMN 0x42c0
737 #define T_OPCODE_NEG 0x4240
738 #define T_OPCODE_MVN 0x43c0
740 #define T_OPCODE_ADD_R3 0x1800
741 #define T_OPCODE_SUB_R3 0x1a00
742 #define T_OPCODE_ADD_HI 0x4400
743 #define T_OPCODE_ADD_ST 0xb000
744 #define T_OPCODE_SUB_ST 0xb080
745 #define T_OPCODE_ADD_SP 0xa800
746 #define T_OPCODE_ADD_PC 0xa000
747 #define T_OPCODE_ADD_I8 0x3000
748 #define T_OPCODE_SUB_I8 0x3800
749 #define T_OPCODE_ADD_I3 0x1c00
750 #define T_OPCODE_SUB_I3 0x1e00
752 #define T_OPCODE_ASR_R 0x4100
753 #define T_OPCODE_LSL_R 0x4080
754 #define T_OPCODE_LSR_R 0x40c0
755 #define T_OPCODE_ROR_R 0x41c0
756 #define T_OPCODE_ASR_I 0x1000
757 #define T_OPCODE_LSL_I 0x0000
758 #define T_OPCODE_LSR_I 0x0800
760 #define T_OPCODE_MOV_I8 0x2000
761 #define T_OPCODE_CMP_I8 0x2800
762 #define T_OPCODE_CMP_LR 0x4280
763 #define T_OPCODE_MOV_HR 0x4600
764 #define T_OPCODE_CMP_HR 0x4500
766 #define T_OPCODE_LDR_PC 0x4800
767 #define T_OPCODE_LDR_SP 0x9800
768 #define T_OPCODE_STR_SP 0x9000
769 #define T_OPCODE_LDR_IW 0x6800
770 #define T_OPCODE_STR_IW 0x6000
771 #define T_OPCODE_LDR_IH 0x8800
772 #define T_OPCODE_STR_IH 0x8000
773 #define T_OPCODE_LDR_IB 0x7800
774 #define T_OPCODE_STR_IB 0x7000
775 #define T_OPCODE_LDR_RW 0x5800
776 #define T_OPCODE_STR_RW 0x5000
777 #define T_OPCODE_LDR_RH 0x5a00
778 #define T_OPCODE_STR_RH 0x5200
779 #define T_OPCODE_LDR_RB 0x5c00
780 #define T_OPCODE_STR_RB 0x5400
782 #define T_OPCODE_PUSH 0xb400
783 #define T_OPCODE_POP 0xbc00
785 #define T_OPCODE_BRANCH 0xe000
787 #define THUMB_SIZE 2 /* Size of thumb instruction. */
788 #define THUMB_PP_PC_LR 0x0100
789 #define THUMB_LOAD_BIT 0x0800
790 #define THUMB2_LOAD_BIT 0x00100000
792 #define BAD_ARGS _("bad arguments to instruction")
793 #define BAD_SP _("r13 not allowed here")
794 #define BAD_PC _("r15 not allowed here")
795 #define BAD_COND _("instruction cannot be conditional")
796 #define BAD_OVERLAP _("registers may not be the same")
797 #define BAD_HIREG _("lo register required")
798 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
799 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
800 #define BAD_BRANCH _("branch must be last instruction in IT block")
801 #define BAD_NOT_IT _("instruction not allowed in IT block")
802 #define BAD_FPU _("selected FPU does not support instruction")
803 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
804 #define BAD_IT_COND _("incorrect condition in IT block")
805 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
806 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
807 #define BAD_PC_ADDRESSING \
808 _("cannot use register index with PC-relative addressing")
809 #define BAD_PC_WRITEBACK \
810 _("cannot use writeback with PC-relative addressing")
811 #define BAD_RANGE _("branch out of range")
812 #define BAD_FP16 _("selected processor does not support fp16 instruction")
813 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
814 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
816 static struct hash_control
* arm_ops_hsh
;
817 static struct hash_control
* arm_cond_hsh
;
818 static struct hash_control
* arm_shift_hsh
;
819 static struct hash_control
* arm_psr_hsh
;
820 static struct hash_control
* arm_v7m_psr_hsh
;
821 static struct hash_control
* arm_reg_hsh
;
822 static struct hash_control
* arm_reloc_hsh
;
823 static struct hash_control
* arm_barrier_opt_hsh
;
825 /* Stuff needed to resolve the label ambiguity
834 symbolS
* last_label_seen
;
835 static int label_is_thumb_function_name
= FALSE
;
837 /* Literal pool structure. Held on a per-section
838 and per-sub-section basis. */
840 #define MAX_LITERAL_POOL_SIZE 1024
841 typedef struct literal_pool
843 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
844 unsigned int next_free_entry
;
850 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
852 struct literal_pool
* next
;
853 unsigned int alignment
;
856 /* Pointer to a linked list of literal pools. */
857 literal_pool
* list_of_pools
= NULL
;
859 typedef enum asmfunc_states
862 WAITING_ASMFUNC_NAME
,
866 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
869 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
871 static struct current_it now_it
;
875 now_it_compatible (int cond
)
877 return (cond
& ~1) == (now_it
.cc
& ~1);
881 conditional_insn (void)
883 return inst
.cond
!= COND_ALWAYS
;
886 static int in_it_block (void);
888 static int handle_it_state (void);
890 static void force_automatic_it_block_close (void);
892 static void it_fsm_post_encode (void);
894 #define set_it_insn_type(type) \
897 inst.it_insn_type = type; \
898 if (handle_it_state () == FAIL) \
903 #define set_it_insn_type_nonvoid(type, failret) \
906 inst.it_insn_type = type; \
907 if (handle_it_state () == FAIL) \
912 #define set_it_insn_type_last() \
915 if (inst.cond == COND_ALWAYS) \
916 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
918 set_it_insn_type (INSIDE_IT_LAST_INSN); \
924 /* This array holds the chars that always start a comment. If the
925 pre-processor is disabled, these aren't very useful. */
926 char arm_comment_chars
[] = "@";
928 /* This array holds the chars that only start a comment at the beginning of
929 a line. If the line seems to have the form '# 123 filename'
930 .line and .file directives will appear in the pre-processed output. */
931 /* Note that input_file.c hand checks for '#' at the beginning of the
932 first line of the input file. This is because the compiler outputs
933 #NO_APP at the beginning of its output. */
934 /* Also note that comments like this one will always work. */
935 const char line_comment_chars
[] = "#";
937 char arm_line_separator_chars
[] = ";";
939 /* Chars that can be used to separate mant
940 from exp in floating point numbers. */
941 const char EXP_CHARS
[] = "eE";
943 /* Chars that mean this number is a floating point constant. */
947 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
949 /* Prefix characters that indicate the start of an immediate
951 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
953 /* Separator character handling. */
955 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
958 skip_past_char (char ** str
, char c
)
960 /* PR gas/14987: Allow for whitespace before the expected character. */
961 skip_whitespace (*str
);
972 #define skip_past_comma(str) skip_past_char (str, ',')
974 /* Arithmetic expressions (possibly involving symbols). */
976 /* Return TRUE if anything in the expression is a bignum. */
979 walk_no_bignums (symbolS
* sp
)
981 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
984 if (symbol_get_value_expression (sp
)->X_add_symbol
)
986 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
987 || (symbol_get_value_expression (sp
)->X_op_symbol
988 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
994 static int in_my_get_expression
= 0;
996 /* Third argument to my_get_expression. */
997 #define GE_NO_PREFIX 0
998 #define GE_IMM_PREFIX 1
999 #define GE_OPT_PREFIX 2
1000 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1001 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1002 #define GE_OPT_PREFIX_BIG 3
1005 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1010 /* In unified syntax, all prefixes are optional. */
1012 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1015 switch (prefix_mode
)
1017 case GE_NO_PREFIX
: break;
1019 if (!is_immediate_prefix (**str
))
1021 inst
.error
= _("immediate expression requires a # prefix");
1027 case GE_OPT_PREFIX_BIG
:
1028 if (is_immediate_prefix (**str
))
1034 memset (ep
, 0, sizeof (expressionS
));
1036 save_in
= input_line_pointer
;
1037 input_line_pointer
= *str
;
1038 in_my_get_expression
= 1;
1039 seg
= expression (ep
);
1040 in_my_get_expression
= 0;
1042 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1044 /* We found a bad or missing expression in md_operand(). */
1045 *str
= input_line_pointer
;
1046 input_line_pointer
= save_in
;
1047 if (inst
.error
== NULL
)
1048 inst
.error
= (ep
->X_op
== O_absent
1049 ? _("missing expression") :_("bad expression"));
1054 if (seg
!= absolute_section
1055 && seg
!= text_section
1056 && seg
!= data_section
1057 && seg
!= bss_section
1058 && seg
!= undefined_section
)
1060 inst
.error
= _("bad segment");
1061 *str
= input_line_pointer
;
1062 input_line_pointer
= save_in
;
1069 /* Get rid of any bignums now, so that we don't generate an error for which
1070 we can't establish a line number later on. Big numbers are never valid
1071 in instructions, which is where this routine is always called. */
1072 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1073 && (ep
->X_op
== O_big
1074 || (ep
->X_add_symbol
1075 && (walk_no_bignums (ep
->X_add_symbol
)
1077 && walk_no_bignums (ep
->X_op_symbol
))))))
1079 inst
.error
= _("invalid constant");
1080 *str
= input_line_pointer
;
1081 input_line_pointer
= save_in
;
1085 *str
= input_line_pointer
;
1086 input_line_pointer
= save_in
;
1090 /* Turn a string in input_line_pointer into a floating point constant
1091 of type TYPE, and store the appropriate bytes in *LITP. The number
1092 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1093 returned, or NULL on OK.
1095 Note that fp constants aren't represent in the normal way on the ARM.
1096 In big endian mode, things are as expected. However, in little endian
1097 mode fp constants are big-endian word-wise, and little-endian byte-wise
1098 within the words. For example, (double) 1.1 in big endian mode is
1099 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1100 the byte sequence 99 99 f1 3f 9a 99 99 99.
1102 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1105 md_atof (int type
, char * litP
, int * sizeP
)
1108 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1140 return _("Unrecognized or unsupported floating point constant");
1143 t
= atof_ieee (input_line_pointer
, type
, words
);
1145 input_line_pointer
= t
;
1146 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1148 if (target_big_endian
)
1150 for (i
= 0; i
< prec
; i
++)
1152 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1153 litP
+= sizeof (LITTLENUM_TYPE
);
1158 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1159 for (i
= prec
- 1; i
>= 0; i
--)
1161 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1162 litP
+= sizeof (LITTLENUM_TYPE
);
1165 /* For a 4 byte float the order of elements in `words' is 1 0.
1166 For an 8 byte float the order is 1 0 3 2. */
1167 for (i
= 0; i
< prec
; i
+= 2)
1169 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1170 sizeof (LITTLENUM_TYPE
));
1171 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1172 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1173 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1180 /* We handle all bad expressions here, so that we can report the faulty
1181 instruction in the error message. */
1183 md_operand (expressionS
* exp
)
1185 if (in_my_get_expression
)
1186 exp
->X_op
= O_illegal
;
1189 /* Immediate values. */
1191 /* Generic immediate-value read function for use in directives.
1192 Accepts anything that 'expression' can fold to a constant.
1193 *val receives the number. */
1196 immediate_for_directive (int *val
)
1199 exp
.X_op
= O_illegal
;
1201 if (is_immediate_prefix (*input_line_pointer
))
1203 input_line_pointer
++;
1207 if (exp
.X_op
!= O_constant
)
1209 as_bad (_("expected #constant"));
1210 ignore_rest_of_line ();
1213 *val
= exp
.X_add_number
;
1218 /* Register parsing. */
1220 /* Generic register parser. CCP points to what should be the
1221 beginning of a register name. If it is indeed a valid register
1222 name, advance CCP over it and return the reg_entry structure;
1223 otherwise return NULL. Does not issue diagnostics. */
1225 static struct reg_entry
*
1226 arm_reg_parse_multi (char **ccp
)
1230 struct reg_entry
*reg
;
1232 skip_whitespace (start
);
1234 #ifdef REGISTER_PREFIX
1235 if (*start
!= REGISTER_PREFIX
)
1239 #ifdef OPTIONAL_REGISTER_PREFIX
1240 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1245 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1250 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1252 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1262 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1263 enum arm_reg_type type
)
1265 /* Alternative syntaxes are accepted for a few register classes. */
1272 /* Generic coprocessor register names are allowed for these. */
1273 if (reg
&& reg
->type
== REG_TYPE_CN
)
1278 /* For backward compatibility, a bare number is valid here. */
1280 unsigned long processor
= strtoul (start
, ccp
, 10);
1281 if (*ccp
!= start
&& processor
<= 15)
1286 case REG_TYPE_MMXWC
:
1287 /* WC includes WCG. ??? I'm not sure this is true for all
1288 instructions that take WC registers. */
1289 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1300 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1301 return value is the register number or FAIL. */
1304 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1307 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1310 /* Do not allow a scalar (reg+index) to parse as a register. */
1311 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1314 if (reg
&& reg
->type
== type
)
1317 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1324 /* Parse a Neon type specifier. *STR should point at the leading '.'
1325 character. Does no verification at this stage that the type fits the opcode
1332 Can all be legally parsed by this function.
1334 Fills in neon_type struct pointer with parsed information, and updates STR
1335 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1336 type, FAIL if not. */
1339 parse_neon_type (struct neon_type
*type
, char **str
)
1346 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1348 enum neon_el_type thistype
= NT_untyped
;
1349 unsigned thissize
= -1u;
1356 /* Just a size without an explicit type. */
1360 switch (TOLOWER (*ptr
))
1362 case 'i': thistype
= NT_integer
; break;
1363 case 'f': thistype
= NT_float
; break;
1364 case 'p': thistype
= NT_poly
; break;
1365 case 's': thistype
= NT_signed
; break;
1366 case 'u': thistype
= NT_unsigned
; break;
1368 thistype
= NT_float
;
1373 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1379 /* .f is an abbreviation for .f32. */
1380 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1385 thissize
= strtoul (ptr
, &ptr
, 10);
1387 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1390 as_bad (_("bad size %d in type specifier"), thissize
);
1398 type
->el
[type
->elems
].type
= thistype
;
1399 type
->el
[type
->elems
].size
= thissize
;
1404 /* Empty/missing type is not a successful parse. */
1405 if (type
->elems
== 0)
1413 /* Errors may be set multiple times during parsing or bit encoding
1414 (particularly in the Neon bits), but usually the earliest error which is set
1415 will be the most meaningful. Avoid overwriting it with later (cascading)
1416 errors by calling this function. */
1419 first_error (const char *err
)
1425 /* Parse a single type, e.g. ".s32", leading period included. */
1427 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1430 struct neon_type optype
;
1434 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1436 if (optype
.elems
== 1)
1437 *vectype
= optype
.el
[0];
1440 first_error (_("only one type should be specified for operand"));
1446 first_error (_("vector type expected"));
1458 /* Special meanings for indices (which have a range of 0-7), which will fit into
1461 #define NEON_ALL_LANES 15
1462 #define NEON_INTERLEAVE_LANES 14
1464 /* Parse either a register or a scalar, with an optional type. Return the
1465 register number, and optionally fill in the actual type of the register
1466 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1467 type/index information in *TYPEINFO. */
1470 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1471 enum arm_reg_type
*rtype
,
1472 struct neon_typed_alias
*typeinfo
)
1475 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1476 struct neon_typed_alias atype
;
1477 struct neon_type_el parsetype
;
1481 atype
.eltype
.type
= NT_invtype
;
1482 atype
.eltype
.size
= -1;
1484 /* Try alternate syntax for some types of register. Note these are mutually
1485 exclusive with the Neon syntax extensions. */
1488 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1496 /* Undo polymorphism when a set of register types may be accepted. */
1497 if ((type
== REG_TYPE_NDQ
1498 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1499 || (type
== REG_TYPE_VFSD
1500 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1501 || (type
== REG_TYPE_NSDQ
1502 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1503 || reg
->type
== REG_TYPE_NQ
))
1504 || (type
== REG_TYPE_MMXWC
1505 && (reg
->type
== REG_TYPE_MMXWCG
)))
1506 type
= (enum arm_reg_type
) reg
->type
;
1508 if (type
!= reg
->type
)
1514 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1516 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1518 first_error (_("can't redefine type for operand"));
1521 atype
.defined
|= NTA_HASTYPE
;
1522 atype
.eltype
= parsetype
;
1525 if (skip_past_char (&str
, '[') == SUCCESS
)
1527 if (type
!= REG_TYPE_VFD
)
1529 first_error (_("only D registers may be indexed"));
1533 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1535 first_error (_("can't change index for operand"));
1539 atype
.defined
|= NTA_HASINDEX
;
1541 if (skip_past_char (&str
, ']') == SUCCESS
)
1542 atype
.index
= NEON_ALL_LANES
;
1547 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1549 if (exp
.X_op
!= O_constant
)
1551 first_error (_("constant expression required"));
1555 if (skip_past_char (&str
, ']') == FAIL
)
1558 atype
.index
= exp
.X_add_number
;
1573 /* Like arm_reg_parse, but allow allow the following extra features:
1574 - If RTYPE is non-zero, return the (possibly restricted) type of the
1575 register (e.g. Neon double or quad reg when either has been requested).
1576 - If this is a Neon vector type with additional type information, fill
1577 in the struct pointed to by VECTYPE (if non-NULL).
1578 This function will fault on encountering a scalar. */
1581 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1584 struct neon_typed_alias atype
;
1586 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1591 /* Do not allow regname(... to parse as a register. */
1595 /* Do not allow a scalar (reg+index) to parse as a register. */
1596 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1598 first_error (_("register operand expected, but got scalar"));
1603 *vectype
= atype
.eltype
;
1610 #define NEON_SCALAR_REG(X) ((X) >> 4)
1611 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1613 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1614 have enough information to be able to do a good job bounds-checking. So, we
1615 just do easy checks here, and do further checks later. */
1618 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1622 struct neon_typed_alias atype
;
1624 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1626 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1629 if (atype
.index
== NEON_ALL_LANES
)
1631 first_error (_("scalar must have an index"));
1634 else if (atype
.index
>= 64 / elsize
)
1636 first_error (_("scalar index out of range"));
1641 *type
= atype
.eltype
;
1645 return reg
* 16 + atype
.index
;
1648 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1651 parse_reg_list (char ** strp
)
1653 char * str
= * strp
;
1657 /* We come back here if we get ranges concatenated by '+' or '|'. */
1660 skip_whitespace (str
);
1674 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1676 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1686 first_error (_("bad range in register list"));
1690 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1692 if (range
& (1 << i
))
1694 (_("Warning: duplicated register (r%d) in register list"),
1702 if (range
& (1 << reg
))
1703 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1705 else if (reg
<= cur_reg
)
1706 as_tsktsk (_("Warning: register range not in ascending order"));
1711 while (skip_past_comma (&str
) != FAIL
1712 || (in_range
= 1, *str
++ == '-'));
1715 if (skip_past_char (&str
, '}') == FAIL
)
1717 first_error (_("missing `}'"));
1725 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1728 if (exp
.X_op
== O_constant
)
1730 if (exp
.X_add_number
1731 != (exp
.X_add_number
& 0x0000ffff))
1733 inst
.error
= _("invalid register mask");
1737 if ((range
& exp
.X_add_number
) != 0)
1739 int regno
= range
& exp
.X_add_number
;
1742 regno
= (1 << regno
) - 1;
1744 (_("Warning: duplicated register (r%d) in register list"),
1748 range
|= exp
.X_add_number
;
1752 if (inst
.reloc
.type
!= 0)
1754 inst
.error
= _("expression too complex");
1758 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1759 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1760 inst
.reloc
.pc_rel
= 0;
1764 if (*str
== '|' || *str
== '+')
1770 while (another_range
);
1776 /* Types of registers in a list. */
1785 /* Parse a VFP register list. If the string is invalid return FAIL.
1786 Otherwise return the number of registers, and set PBASE to the first
1787 register. Parses registers of type ETYPE.
1788 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1789 - Q registers can be used to specify pairs of D registers
1790 - { } can be omitted from around a singleton register list
1791 FIXME: This is not implemented, as it would require backtracking in
1794 This could be done (the meaning isn't really ambiguous), but doesn't
1795 fit in well with the current parsing framework.
1796 - 32 D registers may be used (also true for VFPv3).
1797 FIXME: Types are ignored in these register lists, which is probably a
1801 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1806 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1810 unsigned long mask
= 0;
1813 if (skip_past_char (&str
, '{') == FAIL
)
1815 inst
.error
= _("expecting {");
1822 regtype
= REG_TYPE_VFS
;
1827 regtype
= REG_TYPE_VFD
;
1830 case REGLIST_NEON_D
:
1831 regtype
= REG_TYPE_NDQ
;
1835 if (etype
!= REGLIST_VFP_S
)
1837 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1838 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1842 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1845 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1852 base_reg
= max_regs
;
1856 int setmask
= 1, addregs
= 1;
1858 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1860 if (new_base
== FAIL
)
1862 first_error (_(reg_expected_msgs
[regtype
]));
1866 if (new_base
>= max_regs
)
1868 first_error (_("register out of range in list"));
1872 /* Note: a value of 2 * n is returned for the register Q<n>. */
1873 if (regtype
== REG_TYPE_NQ
)
1879 if (new_base
< base_reg
)
1880 base_reg
= new_base
;
1882 if (mask
& (setmask
<< new_base
))
1884 first_error (_("invalid register list"));
1888 if ((mask
>> new_base
) != 0 && ! warned
)
1890 as_tsktsk (_("register list not in ascending order"));
1894 mask
|= setmask
<< new_base
;
1897 if (*str
== '-') /* We have the start of a range expression */
1903 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1906 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1910 if (high_range
>= max_regs
)
1912 first_error (_("register out of range in list"));
1916 if (regtype
== REG_TYPE_NQ
)
1917 high_range
= high_range
+ 1;
1919 if (high_range
<= new_base
)
1921 inst
.error
= _("register range not in ascending order");
1925 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1927 if (mask
& (setmask
<< new_base
))
1929 inst
.error
= _("invalid register list");
1933 mask
|= setmask
<< new_base
;
1938 while (skip_past_comma (&str
) != FAIL
);
1942 /* Sanity check -- should have raised a parse error above. */
1943 if (count
== 0 || count
> max_regs
)
1948 /* Final test -- the registers must be consecutive. */
1950 for (i
= 0; i
< count
; i
++)
1952 if ((mask
& (1u << i
)) == 0)
1954 inst
.error
= _("non-contiguous register range");
1964 /* True if two alias types are the same. */
1967 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1975 if (a
->defined
!= b
->defined
)
1978 if ((a
->defined
& NTA_HASTYPE
) != 0
1979 && (a
->eltype
.type
!= b
->eltype
.type
1980 || a
->eltype
.size
!= b
->eltype
.size
))
1983 if ((a
->defined
& NTA_HASINDEX
) != 0
1984 && (a
->index
!= b
->index
))
1990 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1991 The base register is put in *PBASE.
1992 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1994 The register stride (minus one) is put in bit 4 of the return value.
1995 Bits [6:5] encode the list length (minus one).
1996 The type of the list elements is put in *ELTYPE, if non-NULL. */
1998 #define NEON_LANE(X) ((X) & 0xf)
1999 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2000 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2003 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2004 struct neon_type_el
*eltype
)
2011 int leading_brace
= 0;
2012 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2013 const char *const incr_error
= _("register stride must be 1 or 2");
2014 const char *const type_error
= _("mismatched element/structure types in list");
2015 struct neon_typed_alias firsttype
;
2016 firsttype
.defined
= 0;
2017 firsttype
.eltype
.type
= NT_invtype
;
2018 firsttype
.eltype
.size
= -1;
2019 firsttype
.index
= -1;
2021 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2026 struct neon_typed_alias atype
;
2027 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2031 first_error (_(reg_expected_msgs
[rtype
]));
2038 if (rtype
== REG_TYPE_NQ
)
2044 else if (reg_incr
== -1)
2046 reg_incr
= getreg
- base_reg
;
2047 if (reg_incr
< 1 || reg_incr
> 2)
2049 first_error (_(incr_error
));
2053 else if (getreg
!= base_reg
+ reg_incr
* count
)
2055 first_error (_(incr_error
));
2059 if (! neon_alias_types_same (&atype
, &firsttype
))
2061 first_error (_(type_error
));
2065 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2069 struct neon_typed_alias htype
;
2070 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2072 lane
= NEON_INTERLEAVE_LANES
;
2073 else if (lane
!= NEON_INTERLEAVE_LANES
)
2075 first_error (_(type_error
));
2080 else if (reg_incr
!= 1)
2082 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2086 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2089 first_error (_(reg_expected_msgs
[rtype
]));
2092 if (! neon_alias_types_same (&htype
, &firsttype
))
2094 first_error (_(type_error
));
2097 count
+= hireg
+ dregs
- getreg
;
2101 /* If we're using Q registers, we can't use [] or [n] syntax. */
2102 if (rtype
== REG_TYPE_NQ
)
2108 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2112 else if (lane
!= atype
.index
)
2114 first_error (_(type_error
));
2118 else if (lane
== -1)
2119 lane
= NEON_INTERLEAVE_LANES
;
2120 else if (lane
!= NEON_INTERLEAVE_LANES
)
2122 first_error (_(type_error
));
2127 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2129 /* No lane set by [x]. We must be interleaving structures. */
2131 lane
= NEON_INTERLEAVE_LANES
;
2134 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2135 || (count
> 1 && reg_incr
== -1))
2137 first_error (_("error parsing element/structure list"));
2141 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2143 first_error (_("expected }"));
2151 *eltype
= firsttype
.eltype
;
2156 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2159 /* Parse an explicit relocation suffix on an expression. This is
2160 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2161 arm_reloc_hsh contains no entries, so this function can only
2162 succeed if there is no () after the word. Returns -1 on error,
2163 BFD_RELOC_UNUSED if there wasn't any suffix. */
2166 parse_reloc (char **str
)
2168 struct reloc_entry
*r
;
2172 return BFD_RELOC_UNUSED
;
2177 while (*q
&& *q
!= ')' && *q
!= ',')
2182 if ((r
= (struct reloc_entry
*)
2183 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2190 /* Directives: register aliases. */
2192 static struct reg_entry
*
2193 insert_reg_alias (char *str
, unsigned number
, int type
)
2195 struct reg_entry
*new_reg
;
2198 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2200 if (new_reg
->builtin
)
2201 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2203 /* Only warn about a redefinition if it's not defined as the
2205 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2206 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2211 name
= xstrdup (str
);
2212 new_reg
= XNEW (struct reg_entry
);
2214 new_reg
->name
= name
;
2215 new_reg
->number
= number
;
2216 new_reg
->type
= type
;
2217 new_reg
->builtin
= FALSE
;
2218 new_reg
->neon
= NULL
;
2220 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2227 insert_neon_reg_alias (char *str
, int number
, int type
,
2228 struct neon_typed_alias
*atype
)
2230 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2234 first_error (_("attempt to redefine typed alias"));
2240 reg
->neon
= XNEW (struct neon_typed_alias
);
2241 *reg
->neon
= *atype
;
2245 /* Look for the .req directive. This is of the form:
2247 new_register_name .req existing_register_name
2249 If we find one, or if it looks sufficiently like one that we want to
2250 handle any error here, return TRUE. Otherwise return FALSE. */
2253 create_register_alias (char * newname
, char *p
)
2255 struct reg_entry
*old
;
2256 char *oldname
, *nbuf
;
2259 /* The input scrubber ensures that whitespace after the mnemonic is
2260 collapsed to single spaces. */
2262 if (strncmp (oldname
, " .req ", 6) != 0)
2266 if (*oldname
== '\0')
2269 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2272 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2276 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2277 the desired alias name, and p points to its end. If not, then
2278 the desired alias name is in the global original_case_string. */
2279 #ifdef TC_CASE_SENSITIVE
2282 newname
= original_case_string
;
2283 nlen
= strlen (newname
);
2286 nbuf
= xmemdup0 (newname
, nlen
);
2288 /* Create aliases under the new name as stated; an all-lowercase
2289 version of the new name; and an all-uppercase version of the new
2291 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2293 for (p
= nbuf
; *p
; p
++)
2296 if (strncmp (nbuf
, newname
, nlen
))
2298 /* If this attempt to create an additional alias fails, do not bother
2299 trying to create the all-lower case alias. We will fail and issue
2300 a second, duplicate error message. This situation arises when the
2301 programmer does something like:
2304 The second .req creates the "Foo" alias but then fails to create
2305 the artificial FOO alias because it has already been created by the
2307 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2314 for (p
= nbuf
; *p
; p
++)
2317 if (strncmp (nbuf
, newname
, nlen
))
2318 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2325 /* Create a Neon typed/indexed register alias using directives, e.g.:
2330 These typed registers can be used instead of the types specified after the
2331 Neon mnemonic, so long as all operands given have types. Types can also be
2332 specified directly, e.g.:
2333 vadd d0.s32, d1.s32, d2.s32 */
2336 create_neon_reg_alias (char *newname
, char *p
)
2338 enum arm_reg_type basetype
;
2339 struct reg_entry
*basereg
;
2340 struct reg_entry mybasereg
;
2341 struct neon_type ntype
;
2342 struct neon_typed_alias typeinfo
;
2343 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2346 typeinfo
.defined
= 0;
2347 typeinfo
.eltype
.type
= NT_invtype
;
2348 typeinfo
.eltype
.size
= -1;
2349 typeinfo
.index
= -1;
2353 if (strncmp (p
, " .dn ", 5) == 0)
2354 basetype
= REG_TYPE_VFD
;
2355 else if (strncmp (p
, " .qn ", 5) == 0)
2356 basetype
= REG_TYPE_NQ
;
2365 basereg
= arm_reg_parse_multi (&p
);
2367 if (basereg
&& basereg
->type
!= basetype
)
2369 as_bad (_("bad type for register"));
2373 if (basereg
== NULL
)
2376 /* Try parsing as an integer. */
2377 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2378 if (exp
.X_op
!= O_constant
)
2380 as_bad (_("expression must be constant"));
2383 basereg
= &mybasereg
;
2384 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2390 typeinfo
= *basereg
->neon
;
2392 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2394 /* We got a type. */
2395 if (typeinfo
.defined
& NTA_HASTYPE
)
2397 as_bad (_("can't redefine the type of a register alias"));
2401 typeinfo
.defined
|= NTA_HASTYPE
;
2402 if (ntype
.elems
!= 1)
2404 as_bad (_("you must specify a single type only"));
2407 typeinfo
.eltype
= ntype
.el
[0];
2410 if (skip_past_char (&p
, '[') == SUCCESS
)
2413 /* We got a scalar index. */
2415 if (typeinfo
.defined
& NTA_HASINDEX
)
2417 as_bad (_("can't redefine the index of a scalar alias"));
2421 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2423 if (exp
.X_op
!= O_constant
)
2425 as_bad (_("scalar index must be constant"));
2429 typeinfo
.defined
|= NTA_HASINDEX
;
2430 typeinfo
.index
= exp
.X_add_number
;
2432 if (skip_past_char (&p
, ']') == FAIL
)
2434 as_bad (_("expecting ]"));
2439 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2440 the desired alias name, and p points to its end. If not, then
2441 the desired alias name is in the global original_case_string. */
2442 #ifdef TC_CASE_SENSITIVE
2443 namelen
= nameend
- newname
;
2445 newname
= original_case_string
;
2446 namelen
= strlen (newname
);
2449 namebuf
= xmemdup0 (newname
, namelen
);
2451 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2452 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2454 /* Insert name in all uppercase. */
2455 for (p
= namebuf
; *p
; p
++)
2458 if (strncmp (namebuf
, newname
, namelen
))
2459 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2460 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2462 /* Insert name in all lowercase. */
2463 for (p
= namebuf
; *p
; p
++)
2466 if (strncmp (namebuf
, newname
, namelen
))
2467 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2468 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2474 /* Should never be called, as .req goes between the alias and the
2475 register name, not at the beginning of the line. */
2478 s_req (int a ATTRIBUTE_UNUSED
)
2480 as_bad (_("invalid syntax for .req directive"));
2484 s_dn (int a ATTRIBUTE_UNUSED
)
2486 as_bad (_("invalid syntax for .dn directive"));
2490 s_qn (int a ATTRIBUTE_UNUSED
)
2492 as_bad (_("invalid syntax for .qn directive"));
2495 /* The .unreq directive deletes an alias which was previously defined
2496 by .req. For example:
2502 s_unreq (int a ATTRIBUTE_UNUSED
)
2507 name
= input_line_pointer
;
2509 while (*input_line_pointer
!= 0
2510 && *input_line_pointer
!= ' '
2511 && *input_line_pointer
!= '\n')
2512 ++input_line_pointer
;
2514 saved_char
= *input_line_pointer
;
2515 *input_line_pointer
= 0;
2518 as_bad (_("invalid syntax for .unreq directive"));
2521 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2525 as_bad (_("unknown register alias '%s'"), name
);
2526 else if (reg
->builtin
)
2527 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2534 hash_delete (arm_reg_hsh
, name
, FALSE
);
2535 free ((char *) reg
->name
);
2540 /* Also locate the all upper case and all lower case versions.
2541 Do not complain if we cannot find one or the other as it
2542 was probably deleted above. */
2544 nbuf
= strdup (name
);
2545 for (p
= nbuf
; *p
; p
++)
2547 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2550 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2551 free ((char *) reg
->name
);
2557 for (p
= nbuf
; *p
; p
++)
2559 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2562 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2563 free ((char *) reg
->name
);
2573 *input_line_pointer
= saved_char
;
2574 demand_empty_rest_of_line ();
2577 /* Directives: Instruction set selection. */
2580 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2581 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2582 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2583 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2585 /* Create a new mapping symbol for the transition to STATE. */
2588 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2591 const char * symname
;
2598 type
= BSF_NO_FLAGS
;
2602 type
= BSF_NO_FLAGS
;
2606 type
= BSF_NO_FLAGS
;
2612 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2613 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2618 THUMB_SET_FUNC (symbolP
, 0);
2619 ARM_SET_THUMB (symbolP
, 0);
2620 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2624 THUMB_SET_FUNC (symbolP
, 1);
2625 ARM_SET_THUMB (symbolP
, 1);
2626 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2634 /* Save the mapping symbols for future reference. Also check that
2635 we do not place two mapping symbols at the same offset within a
2636 frag. We'll handle overlap between frags in
2637 check_mapping_symbols.
2639 If .fill or other data filling directive generates zero sized data,
2640 the mapping symbol for the following code will have the same value
2641 as the one generated for the data filling directive. In this case,
2642 we replace the old symbol with the new one at the same address. */
2645 if (frag
->tc_frag_data
.first_map
!= NULL
)
2647 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2648 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2650 frag
->tc_frag_data
.first_map
= symbolP
;
2652 if (frag
->tc_frag_data
.last_map
!= NULL
)
2654 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2655 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2656 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2658 frag
->tc_frag_data
.last_map
= symbolP
;
2661 /* We must sometimes convert a region marked as code to data during
2662 code alignment, if an odd number of bytes have to be padded. The
2663 code mapping symbol is pushed to an aligned address. */
2666 insert_data_mapping_symbol (enum mstate state
,
2667 valueT value
, fragS
*frag
, offsetT bytes
)
2669 /* If there was already a mapping symbol, remove it. */
2670 if (frag
->tc_frag_data
.last_map
!= NULL
2671 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2673 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2677 know (frag
->tc_frag_data
.first_map
== symp
);
2678 frag
->tc_frag_data
.first_map
= NULL
;
2680 frag
->tc_frag_data
.last_map
= NULL
;
2681 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2684 make_mapping_symbol (MAP_DATA
, value
, frag
);
2685 make_mapping_symbol (state
, value
+ bytes
, frag
);
2688 static void mapping_state_2 (enum mstate state
, int max_chars
);
2690 /* Set the mapping state to STATE. Only call this when about to
2691 emit some STATE bytes to the file. */
2693 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2695 mapping_state (enum mstate state
)
2697 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2699 if (mapstate
== state
)
2700 /* The mapping symbol has already been emitted.
2701 There is nothing else to do. */
2704 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2706 All ARM instructions require 4-byte alignment.
2707 (Almost) all Thumb instructions require 2-byte alignment.
2709 When emitting instructions into any section, mark the section
2712 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2713 but themselves require 2-byte alignment; this applies to some
2714 PC- relative forms. However, these cases will involve implicit
2715 literal pool generation or an explicit .align >=2, both of
2716 which will cause the section to me marked with sufficient
2717 alignment. Thus, we don't handle those cases here. */
2718 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2720 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2721 /* This case will be evaluated later. */
2724 mapping_state_2 (state
, 0);
2727 /* Same as mapping_state, but MAX_CHARS bytes have already been
2728 allocated. Put the mapping symbol that far back. */
2731 mapping_state_2 (enum mstate state
, int max_chars
)
2733 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2735 if (!SEG_NORMAL (now_seg
))
2738 if (mapstate
== state
)
2739 /* The mapping symbol has already been emitted.
2740 There is nothing else to do. */
2743 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2744 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2746 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2747 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2750 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2753 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2754 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2758 #define mapping_state(x) ((void)0)
2759 #define mapping_state_2(x, y) ((void)0)
2762 /* Find the real, Thumb encoded start of a Thumb function. */
2766 find_real_start (symbolS
* symbolP
)
2769 const char * name
= S_GET_NAME (symbolP
);
2770 symbolS
* new_target
;
2772 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2773 #define STUB_NAME ".real_start_of"
2778 /* The compiler may generate BL instructions to local labels because
2779 it needs to perform a branch to a far away location. These labels
2780 do not have a corresponding ".real_start_of" label. We check
2781 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2782 the ".real_start_of" convention for nonlocal branches. */
2783 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2786 real_start
= concat (STUB_NAME
, name
, NULL
);
2787 new_target
= symbol_find (real_start
);
2790 if (new_target
== NULL
)
2792 as_warn (_("Failed to find real start of function: %s\n"), name
);
2793 new_target
= symbolP
;
2801 opcode_select (int width
)
2808 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2809 as_bad (_("selected processor does not support THUMB opcodes"));
2812 /* No need to force the alignment, since we will have been
2813 coming from ARM mode, which is word-aligned. */
2814 record_alignment (now_seg
, 1);
2821 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2822 as_bad (_("selected processor does not support ARM opcodes"));
2827 frag_align (2, 0, 0);
2829 record_alignment (now_seg
, 1);
2834 as_bad (_("invalid instruction size selected (%d)"), width
);
2839 s_arm (int ignore ATTRIBUTE_UNUSED
)
2842 demand_empty_rest_of_line ();
2846 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2849 demand_empty_rest_of_line ();
2853 s_code (int unused ATTRIBUTE_UNUSED
)
2857 temp
= get_absolute_expression ();
2862 opcode_select (temp
);
2866 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2871 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2873 /* If we are not already in thumb mode go into it, EVEN if
2874 the target processor does not support thumb instructions.
2875 This is used by gcc/config/arm/lib1funcs.asm for example
2876 to compile interworking support functions even if the
2877 target processor should not support interworking. */
2881 record_alignment (now_seg
, 1);
2884 demand_empty_rest_of_line ();
2888 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2892 /* The following label is the name/address of the start of a Thumb function.
2893 We need to know this for the interworking support. */
2894 label_is_thumb_function_name
= TRUE
;
2897 /* Perform a .set directive, but also mark the alias as
2898 being a thumb function. */
2901 s_thumb_set (int equiv
)
2903 /* XXX the following is a duplicate of the code for s_set() in read.c
2904 We cannot just call that code as we need to get at the symbol that
2911 /* Especial apologies for the random logic:
2912 This just grew, and could be parsed much more simply!
2914 delim
= get_symbol_name (& name
);
2915 end_name
= input_line_pointer
;
2916 (void) restore_line_pointer (delim
);
2918 if (*input_line_pointer
!= ',')
2921 as_bad (_("expected comma after name \"%s\""), name
);
2923 ignore_rest_of_line ();
2927 input_line_pointer
++;
2930 if (name
[0] == '.' && name
[1] == '\0')
2932 /* XXX - this should not happen to .thumb_set. */
2936 if ((symbolP
= symbol_find (name
)) == NULL
2937 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2940 /* When doing symbol listings, play games with dummy fragments living
2941 outside the normal fragment chain to record the file and line info
2943 if (listing
& LISTING_SYMBOLS
)
2945 extern struct list_info_struct
* listing_tail
;
2946 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2948 memset (dummy_frag
, 0, sizeof (fragS
));
2949 dummy_frag
->fr_type
= rs_fill
;
2950 dummy_frag
->line
= listing_tail
;
2951 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2952 dummy_frag
->fr_symbol
= symbolP
;
2956 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2959 /* "set" symbols are local unless otherwise specified. */
2960 SF_SET_LOCAL (symbolP
);
2961 #endif /* OBJ_COFF */
2962 } /* Make a new symbol. */
2964 symbol_table_insert (symbolP
);
2969 && S_IS_DEFINED (symbolP
)
2970 && S_GET_SEGMENT (symbolP
) != reg_section
)
2971 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2973 pseudo_set (symbolP
);
2975 demand_empty_rest_of_line ();
2977 /* XXX Now we come to the Thumb specific bit of code. */
2979 THUMB_SET_FUNC (symbolP
, 1);
2980 ARM_SET_THUMB (symbolP
, 1);
2981 #if defined OBJ_ELF || defined OBJ_COFF
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 /* Directives: Mode selection. */
2988 /* .syntax [unified|divided] - choose the new unified syntax
2989 (same for Arm and Thumb encoding, modulo slight differences in what
2990 can be represented) or the old divergent syntax for each mode. */
2992 s_syntax (int unused ATTRIBUTE_UNUSED
)
2996 delim
= get_symbol_name (& name
);
2998 if (!strcasecmp (name
, "unified"))
2999 unified_syntax
= TRUE
;
3000 else if (!strcasecmp (name
, "divided"))
3001 unified_syntax
= FALSE
;
3004 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3007 (void) restore_line_pointer (delim
);
3008 demand_empty_rest_of_line ();
3011 /* Directives: sectioning and alignment. */
3014 s_bss (int ignore ATTRIBUTE_UNUSED
)
3016 /* We don't support putting frags in the BSS segment, we fake it by
3017 marking in_bss, then looking at s_skip for clues. */
3018 subseg_set (bss_section
, 0);
3019 demand_empty_rest_of_line ();
3021 #ifdef md_elf_section_change_hook
3022 md_elf_section_change_hook ();
3027 s_even (int ignore ATTRIBUTE_UNUSED
)
3029 /* Never make frag if expect extra pass. */
3031 frag_align (1, 0, 0);
3033 record_alignment (now_seg
, 1);
3035 demand_empty_rest_of_line ();
3038 /* Directives: CodeComposer Studio. */
3040 /* .ref (for CodeComposer Studio syntax only). */
3042 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3044 if (codecomposer_syntax
)
3045 ignore_rest_of_line ();
3047 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3050 /* If name is not NULL, then it is used for marking the beginning of a
3051 function, whereas if it is NULL then it means the function end. */
3053 asmfunc_debug (const char * name
)
3055 static const char * last_name
= NULL
;
3059 gas_assert (last_name
== NULL
);
3062 if (debug_type
== DEBUG_STABS
)
3063 stabs_generate_asm_func (name
, name
);
3067 gas_assert (last_name
!= NULL
);
3069 if (debug_type
== DEBUG_STABS
)
3070 stabs_generate_asm_endfunc (last_name
, last_name
);
3077 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3079 if (codecomposer_syntax
)
3081 switch (asmfunc_state
)
3083 case OUTSIDE_ASMFUNC
:
3084 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3087 case WAITING_ASMFUNC_NAME
:
3088 as_bad (_(".asmfunc repeated."));
3091 case WAITING_ENDASMFUNC
:
3092 as_bad (_(".asmfunc without function."));
3095 demand_empty_rest_of_line ();
3098 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3102 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3104 if (codecomposer_syntax
)
3106 switch (asmfunc_state
)
3108 case OUTSIDE_ASMFUNC
:
3109 as_bad (_(".endasmfunc without a .asmfunc."));
3112 case WAITING_ASMFUNC_NAME
:
3113 as_bad (_(".endasmfunc without function."));
3116 case WAITING_ENDASMFUNC
:
3117 asmfunc_state
= OUTSIDE_ASMFUNC
;
3118 asmfunc_debug (NULL
);
3121 demand_empty_rest_of_line ();
3124 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3128 s_ccs_def (int name
)
3130 if (codecomposer_syntax
)
3133 as_bad (_(".def pseudo-op only available with -mccs flag."));
3136 /* Directives: Literal pools. */
3138 static literal_pool
*
3139 find_literal_pool (void)
3141 literal_pool
* pool
;
3143 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3145 if (pool
->section
== now_seg
3146 && pool
->sub_section
== now_subseg
)
3153 static literal_pool
*
3154 find_or_make_literal_pool (void)
3156 /* Next literal pool ID number. */
3157 static unsigned int latest_pool_num
= 1;
3158 literal_pool
* pool
;
3160 pool
= find_literal_pool ();
3164 /* Create a new pool. */
3165 pool
= XNEW (literal_pool
);
3169 pool
->next_free_entry
= 0;
3170 pool
->section
= now_seg
;
3171 pool
->sub_section
= now_subseg
;
3172 pool
->next
= list_of_pools
;
3173 pool
->symbol
= NULL
;
3174 pool
->alignment
= 2;
3176 /* Add it to the list. */
3177 list_of_pools
= pool
;
3180 /* New pools, and emptied pools, will have a NULL symbol. */
3181 if (pool
->symbol
== NULL
)
3183 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3184 (valueT
) 0, &zero_address_frag
);
3185 pool
->id
= latest_pool_num
++;
3192 /* Add the literal in the global 'inst'
3193 structure to the relevant literal pool. */
3196 add_to_lit_pool (unsigned int nbytes
)
3198 #define PADDING_SLOT 0x1
3199 #define LIT_ENTRY_SIZE_MASK 0xFF
3200 literal_pool
* pool
;
3201 unsigned int entry
, pool_size
= 0;
3202 bfd_boolean padding_slot_p
= FALSE
;
3208 imm1
= inst
.operands
[1].imm
;
3209 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3210 : inst
.reloc
.exp
.X_unsigned
? 0
3211 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3212 if (target_big_endian
)
3215 imm2
= inst
.operands
[1].imm
;
3219 pool
= find_or_make_literal_pool ();
3221 /* Check if this literal value is already in the pool. */
3222 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3226 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3227 && (inst
.reloc
.exp
.X_op
== O_constant
)
3228 && (pool
->literals
[entry
].X_add_number
3229 == inst
.reloc
.exp
.X_add_number
)
3230 && (pool
->literals
[entry
].X_md
== nbytes
)
3231 && (pool
->literals
[entry
].X_unsigned
3232 == inst
.reloc
.exp
.X_unsigned
))
3235 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3236 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3237 && (pool
->literals
[entry
].X_add_number
3238 == inst
.reloc
.exp
.X_add_number
)
3239 && (pool
->literals
[entry
].X_add_symbol
3240 == inst
.reloc
.exp
.X_add_symbol
)
3241 && (pool
->literals
[entry
].X_op_symbol
3242 == inst
.reloc
.exp
.X_op_symbol
)
3243 && (pool
->literals
[entry
].X_md
== nbytes
))
3246 else if ((nbytes
== 8)
3247 && !(pool_size
& 0x7)
3248 && ((entry
+ 1) != pool
->next_free_entry
)
3249 && (pool
->literals
[entry
].X_op
== O_constant
)
3250 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3251 && (pool
->literals
[entry
].X_unsigned
3252 == inst
.reloc
.exp
.X_unsigned
)
3253 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3254 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3255 && (pool
->literals
[entry
+ 1].X_unsigned
3256 == inst
.reloc
.exp
.X_unsigned
))
3259 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3260 if (padding_slot_p
&& (nbytes
== 4))
3266 /* Do we need to create a new entry? */
3267 if (entry
== pool
->next_free_entry
)
3269 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3271 inst
.error
= _("literal pool overflow");
3277 /* For 8-byte entries, we align to an 8-byte boundary,
3278 and split it into two 4-byte entries, because on 32-bit
3279 host, 8-byte constants are treated as big num, thus
3280 saved in "generic_bignum" which will be overwritten
3281 by later assignments.
3283 We also need to make sure there is enough space for
3286 We also check to make sure the literal operand is a
3288 if (!(inst
.reloc
.exp
.X_op
== O_constant
3289 || inst
.reloc
.exp
.X_op
== O_big
))
3291 inst
.error
= _("invalid type for literal pool");
3294 else if (pool_size
& 0x7)
3296 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3298 inst
.error
= _("literal pool overflow");
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_op
= O_constant
;
3304 pool
->literals
[entry
].X_add_number
= 0;
3305 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3306 pool
->next_free_entry
+= 1;
3309 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3311 inst
.error
= _("literal pool overflow");
3315 pool
->literals
[entry
] = inst
.reloc
.exp
;
3316 pool
->literals
[entry
].X_op
= O_constant
;
3317 pool
->literals
[entry
].X_add_number
= imm1
;
3318 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3319 pool
->literals
[entry
++].X_md
= 4;
3320 pool
->literals
[entry
] = inst
.reloc
.exp
;
3321 pool
->literals
[entry
].X_op
= O_constant
;
3322 pool
->literals
[entry
].X_add_number
= imm2
;
3323 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3324 pool
->literals
[entry
].X_md
= 4;
3325 pool
->alignment
= 3;
3326 pool
->next_free_entry
+= 1;
3330 pool
->literals
[entry
] = inst
.reloc
.exp
;
3331 pool
->literals
[entry
].X_md
= 4;
3335 /* PR ld/12974: Record the location of the first source line to reference
3336 this entry in the literal pool. If it turns out during linking that the
3337 symbol does not exist we will be able to give an accurate line number for
3338 the (first use of the) missing reference. */
3339 if (debug_type
== DEBUG_DWARF2
)
3340 dwarf2_where (pool
->locs
+ entry
);
3342 pool
->next_free_entry
+= 1;
3344 else if (padding_slot_p
)
3346 pool
->literals
[entry
] = inst
.reloc
.exp
;
3347 pool
->literals
[entry
].X_md
= nbytes
;
3350 inst
.reloc
.exp
.X_op
= O_symbol
;
3351 inst
.reloc
.exp
.X_add_number
= pool_size
;
3352 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3358 tc_start_label_without_colon (void)
3360 bfd_boolean ret
= TRUE
;
3362 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3364 const char *label
= input_line_pointer
;
3366 while (!is_end_of_line
[(int) label
[-1]])
3371 as_bad (_("Invalid label '%s'"), label
);
3375 asmfunc_debug (label
);
3377 asmfunc_state
= WAITING_ENDASMFUNC
;
3383 /* Can't use symbol_new here, so have to create a symbol and then at
3384 a later date assign it a value. That's what these functions do. */
3387 symbol_locate (symbolS
* symbolP
,
3388 const char * name
, /* It is copied, the caller can modify. */
3389 segT segment
, /* Segment identifier (SEG_<something>). */
3390 valueT valu
, /* Symbol value. */
3391 fragS
* frag
) /* Associated fragment. */
3394 char * preserved_copy_of_name
;
3396 name_length
= strlen (name
) + 1; /* +1 for \0. */
3397 obstack_grow (¬es
, name
, name_length
);
3398 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3400 #ifdef tc_canonicalize_symbol_name
3401 preserved_copy_of_name
=
3402 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3405 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3407 S_SET_SEGMENT (symbolP
, segment
);
3408 S_SET_VALUE (symbolP
, valu
);
3409 symbol_clear_list_pointers (symbolP
);
3411 symbol_set_frag (symbolP
, frag
);
3413 /* Link to end of symbol chain. */
3415 extern int symbol_table_frozen
;
3417 if (symbol_table_frozen
)
3421 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3423 obj_symbol_new_hook (symbolP
);
3425 #ifdef tc_symbol_new_hook
3426 tc_symbol_new_hook (symbolP
);
3430 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3431 #endif /* DEBUG_SYMS */
3435 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3438 literal_pool
* pool
;
3441 pool
= find_literal_pool ();
3443 || pool
->symbol
== NULL
3444 || pool
->next_free_entry
== 0)
3447 /* Align pool as you have word accesses.
3448 Only make a frag if we have to. */
3450 frag_align (pool
->alignment
, 0, 0);
3452 record_alignment (now_seg
, 2);
3455 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3456 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3458 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3460 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3461 (valueT
) frag_now_fix (), frag_now
);
3462 symbol_table_insert (pool
->symbol
);
3464 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3466 #if defined OBJ_COFF || defined OBJ_ELF
3467 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3470 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3473 if (debug_type
== DEBUG_DWARF2
)
3474 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3476 /* First output the expression in the instruction to the pool. */
3477 emit_expr (&(pool
->literals
[entry
]),
3478 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3481 /* Mark the pool as empty. */
3482 pool
->next_free_entry
= 0;
3483 pool
->symbol
= NULL
;
3487 /* Forward declarations for functions below, in the MD interface
3489 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3490 static valueT
create_unwind_entry (int);
3491 static void start_unwind_section (const segT
, int);
3492 static void add_unwind_opcode (valueT
, int);
3493 static void flush_pending_unwind (void);
3495 /* Directives: Data. */
3498 s_arm_elf_cons (int nbytes
)
3502 #ifdef md_flush_pending_output
3503 md_flush_pending_output ();
3506 if (is_it_end_of_statement ())
3508 demand_empty_rest_of_line ();
3512 #ifdef md_cons_align
3513 md_cons_align (nbytes
);
3516 mapping_state (MAP_DATA
);
3520 char *base
= input_line_pointer
;
3524 if (exp
.X_op
!= O_symbol
)
3525 emit_expr (&exp
, (unsigned int) nbytes
);
3528 char *before_reloc
= input_line_pointer
;
3529 reloc
= parse_reloc (&input_line_pointer
);
3532 as_bad (_("unrecognized relocation suffix"));
3533 ignore_rest_of_line ();
3536 else if (reloc
== BFD_RELOC_UNUSED
)
3537 emit_expr (&exp
, (unsigned int) nbytes
);
3540 reloc_howto_type
*howto
= (reloc_howto_type
*)
3541 bfd_reloc_type_lookup (stdoutput
,
3542 (bfd_reloc_code_real_type
) reloc
);
3543 int size
= bfd_get_reloc_size (howto
);
3545 if (reloc
== BFD_RELOC_ARM_PLT32
)
3547 as_bad (_("(plt) is only valid on branch targets"));
3548 reloc
= BFD_RELOC_UNUSED
;
3553 as_bad (_("%s relocations do not fit in %d bytes"),
3554 howto
->name
, nbytes
);
3557 /* We've parsed an expression stopping at O_symbol.
3558 But there may be more expression left now that we
3559 have parsed the relocation marker. Parse it again.
3560 XXX Surely there is a cleaner way to do this. */
3561 char *p
= input_line_pointer
;
3563 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3565 memcpy (save_buf
, base
, input_line_pointer
- base
);
3566 memmove (base
+ (input_line_pointer
- before_reloc
),
3567 base
, before_reloc
- base
);
3569 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3571 memcpy (base
, save_buf
, p
- base
);
3573 offset
= nbytes
- size
;
3574 p
= frag_more (nbytes
);
3575 memset (p
, 0, nbytes
);
3576 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3577 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3583 while (*input_line_pointer
++ == ',');
3585 /* Put terminator back into stream. */
3586 input_line_pointer
--;
3587 demand_empty_rest_of_line ();
3590 /* Emit an expression containing a 32-bit thumb instruction.
3591 Implementation based on put_thumb32_insn. */
3594 emit_thumb32_expr (expressionS
* exp
)
3596 expressionS exp_high
= *exp
;
3598 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3599 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3600 exp
->X_add_number
&= 0xffff;
3601 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3604 /* Guess the instruction size based on the opcode. */
3607 thumb_insn_size (int opcode
)
3609 if ((unsigned int) opcode
< 0xe800u
)
3611 else if ((unsigned int) opcode
>= 0xe8000000u
)
3618 emit_insn (expressionS
*exp
, int nbytes
)
3622 if (exp
->X_op
== O_constant
)
3627 size
= thumb_insn_size (exp
->X_add_number
);
3631 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3633 as_bad (_(".inst.n operand too big. "\
3634 "Use .inst.w instead"));
3639 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3640 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3642 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3644 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3645 emit_thumb32_expr (exp
);
3647 emit_expr (exp
, (unsigned int) size
);
3649 it_fsm_post_encode ();
3653 as_bad (_("cannot determine Thumb instruction size. " \
3654 "Use .inst.n/.inst.w instead"));
3657 as_bad (_("constant expression required"));
3662 /* Like s_arm_elf_cons but do not use md_cons_align and
3663 set the mapping state to MAP_ARM/MAP_THUMB. */
3666 s_arm_elf_inst (int nbytes
)
3668 if (is_it_end_of_statement ())
3670 demand_empty_rest_of_line ();
3674 /* Calling mapping_state () here will not change ARM/THUMB,
3675 but will ensure not to be in DATA state. */
3678 mapping_state (MAP_THUMB
);
3683 as_bad (_("width suffixes are invalid in ARM mode"));
3684 ignore_rest_of_line ();
3690 mapping_state (MAP_ARM
);
3699 if (! emit_insn (& exp
, nbytes
))
3701 ignore_rest_of_line ();
3705 while (*input_line_pointer
++ == ',');
3707 /* Put terminator back into stream. */
3708 input_line_pointer
--;
3709 demand_empty_rest_of_line ();
3712 /* Parse a .rel31 directive. */
3715 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3722 if (*input_line_pointer
== '1')
3723 highbit
= 0x80000000;
3724 else if (*input_line_pointer
!= '0')
3725 as_bad (_("expected 0 or 1"));
3727 input_line_pointer
++;
3728 if (*input_line_pointer
!= ',')
3729 as_bad (_("missing comma"));
3730 input_line_pointer
++;
3732 #ifdef md_flush_pending_output
3733 md_flush_pending_output ();
3736 #ifdef md_cons_align
3740 mapping_state (MAP_DATA
);
3745 md_number_to_chars (p
, highbit
, 4);
3746 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3747 BFD_RELOC_ARM_PREL31
);
3749 demand_empty_rest_of_line ();
3752 /* Directives: AEABI stack-unwind tables. */
3754 /* Parse an unwind_fnstart directive. Simply records the current location. */
3757 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3759 demand_empty_rest_of_line ();
3760 if (unwind
.proc_start
)
3762 as_bad (_("duplicate .fnstart directive"));
3766 /* Mark the start of the function. */
3767 unwind
.proc_start
= expr_build_dot ();
3769 /* Reset the rest of the unwind info. */
3770 unwind
.opcode_count
= 0;
3771 unwind
.table_entry
= NULL
;
3772 unwind
.personality_routine
= NULL
;
3773 unwind
.personality_index
= -1;
3774 unwind
.frame_size
= 0;
3775 unwind
.fp_offset
= 0;
3776 unwind
.fp_reg
= REG_SP
;
3778 unwind
.sp_restored
= 0;
3782 /* Parse a handlerdata directive. Creates the exception handling table entry
3783 for the function. */
3786 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3788 demand_empty_rest_of_line ();
3789 if (!unwind
.proc_start
)
3790 as_bad (MISSING_FNSTART
);
3792 if (unwind
.table_entry
)
3793 as_bad (_("duplicate .handlerdata directive"));
3795 create_unwind_entry (1);
3798 /* Parse an unwind_fnend directive. Generates the index table entry. */
3801 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3806 unsigned int marked_pr_dependency
;
3808 demand_empty_rest_of_line ();
3810 if (!unwind
.proc_start
)
3812 as_bad (_(".fnend directive without .fnstart"));
3816 /* Add eh table entry. */
3817 if (unwind
.table_entry
== NULL
)
3818 val
= create_unwind_entry (0);
3822 /* Add index table entry. This is two words. */
3823 start_unwind_section (unwind
.saved_seg
, 1);
3824 frag_align (2, 0, 0);
3825 record_alignment (now_seg
, 2);
3827 ptr
= frag_more (8);
3829 where
= frag_now_fix () - 8;
3831 /* Self relative offset of the function start. */
3832 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3833 BFD_RELOC_ARM_PREL31
);
3835 /* Indicate dependency on EHABI-defined personality routines to the
3836 linker, if it hasn't been done already. */
3837 marked_pr_dependency
3838 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3839 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3840 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3842 static const char *const name
[] =
3844 "__aeabi_unwind_cpp_pr0",
3845 "__aeabi_unwind_cpp_pr1",
3846 "__aeabi_unwind_cpp_pr2"
3848 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3849 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3850 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3851 |= 1 << unwind
.personality_index
;
3855 /* Inline exception table entry. */
3856 md_number_to_chars (ptr
+ 4, val
, 4);
3858 /* Self relative offset of the table entry. */
3859 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3860 BFD_RELOC_ARM_PREL31
);
3862 /* Restore the original section. */
3863 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3865 unwind
.proc_start
= NULL
;
3869 /* Parse an unwind_cantunwind directive. */
3872 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3874 demand_empty_rest_of_line ();
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("personality routine specified for cantunwind frame"));
3881 unwind
.personality_index
= -2;
3885 /* Parse a personalityindex directive. */
3888 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3892 if (!unwind
.proc_start
)
3893 as_bad (MISSING_FNSTART
);
3895 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3896 as_bad (_("duplicate .personalityindex directive"));
3900 if (exp
.X_op
!= O_constant
3901 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3903 as_bad (_("bad personality routine number"));
3904 ignore_rest_of_line ();
3908 unwind
.personality_index
= exp
.X_add_number
;
3910 demand_empty_rest_of_line ();
3914 /* Parse a personality directive. */
3917 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3921 if (!unwind
.proc_start
)
3922 as_bad (MISSING_FNSTART
);
3924 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3925 as_bad (_("duplicate .personality directive"));
3927 c
= get_symbol_name (& name
);
3928 p
= input_line_pointer
;
3930 ++ input_line_pointer
;
3931 unwind
.personality_routine
= symbol_find_or_make (name
);
3933 demand_empty_rest_of_line ();
3937 /* Parse a directive saving core registers. */
3940 s_arm_unwind_save_core (void)
3946 range
= parse_reg_list (&input_line_pointer
);
3949 as_bad (_("expected register list"));
3950 ignore_rest_of_line ();
3954 demand_empty_rest_of_line ();
3956 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3957 into .unwind_save {..., sp...}. We aren't bothered about the value of
3958 ip because it is clobbered by calls. */
3959 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3960 && (range
& 0x3000) == 0x1000)
3962 unwind
.opcode_count
--;
3963 unwind
.sp_restored
= 0;
3964 range
= (range
| 0x2000) & ~0x1000;
3965 unwind
.pending_offset
= 0;
3971 /* See if we can use the short opcodes. These pop a block of up to 8
3972 registers starting with r4, plus maybe r14. */
3973 for (n
= 0; n
< 8; n
++)
3975 /* Break at the first non-saved register. */
3976 if ((range
& (1 << (n
+ 4))) == 0)
3979 /* See if there are any other bits set. */
3980 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3982 /* Use the long form. */
3983 op
= 0x8000 | ((range
>> 4) & 0xfff);
3984 add_unwind_opcode (op
, 2);
3988 /* Use the short form. */
3990 op
= 0xa8; /* Pop r14. */
3992 op
= 0xa0; /* Do not pop r14. */
3994 add_unwind_opcode (op
, 1);
4001 op
= 0xb100 | (range
& 0xf);
4002 add_unwind_opcode (op
, 2);
4005 /* Record the number of bytes pushed. */
4006 for (n
= 0; n
< 16; n
++)
4008 if (range
& (1 << n
))
4009 unwind
.frame_size
+= 4;
4014 /* Parse a directive saving FPA registers. */
4017 s_arm_unwind_save_fpa (int reg
)
4023 /* Get Number of registers to transfer. */
4024 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4027 exp
.X_op
= O_illegal
;
4029 if (exp
.X_op
!= O_constant
)
4031 as_bad (_("expected , <constant>"));
4032 ignore_rest_of_line ();
4036 num_regs
= exp
.X_add_number
;
4038 if (num_regs
< 1 || num_regs
> 4)
4040 as_bad (_("number of registers must be in the range [1:4]"));
4041 ignore_rest_of_line ();
4045 demand_empty_rest_of_line ();
4050 op
= 0xb4 | (num_regs
- 1);
4051 add_unwind_opcode (op
, 1);
4056 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4057 add_unwind_opcode (op
, 2);
4059 unwind
.frame_size
+= num_regs
* 12;
4063 /* Parse a directive saving VFP registers for ARMv6 and above. */
4066 s_arm_unwind_save_vfp_armv6 (void)
4071 int num_vfpv3_regs
= 0;
4072 int num_regs_below_16
;
4074 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4077 as_bad (_("expected register list"));
4078 ignore_rest_of_line ();
4082 demand_empty_rest_of_line ();
4084 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4085 than FSTMX/FLDMX-style ones). */
4087 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4089 num_vfpv3_regs
= count
;
4090 else if (start
+ count
> 16)
4091 num_vfpv3_regs
= start
+ count
- 16;
4093 if (num_vfpv3_regs
> 0)
4095 int start_offset
= start
> 16 ? start
- 16 : 0;
4096 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4097 add_unwind_opcode (op
, 2);
4100 /* Generate opcode for registers numbered in the range 0 .. 15. */
4101 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4102 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4103 if (num_regs_below_16
> 0)
4105 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4106 add_unwind_opcode (op
, 2);
4109 unwind
.frame_size
+= count
* 8;
4113 /* Parse a directive saving VFP registers for pre-ARMv6. */
4116 s_arm_unwind_save_vfp (void)
4122 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4125 as_bad (_("expected register list"));
4126 ignore_rest_of_line ();
4130 demand_empty_rest_of_line ();
4135 op
= 0xb8 | (count
- 1);
4136 add_unwind_opcode (op
, 1);
4141 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4142 add_unwind_opcode (op
, 2);
4144 unwind
.frame_size
+= count
* 8 + 4;
4148 /* Parse a directive saving iWMMXt data registers. */
4151 s_arm_unwind_save_mmxwr (void)
4159 if (*input_line_pointer
== '{')
4160 input_line_pointer
++;
4164 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4168 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4173 as_tsktsk (_("register list not in ascending order"));
4176 if (*input_line_pointer
== '-')
4178 input_line_pointer
++;
4179 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4182 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4185 else if (reg
>= hi_reg
)
4187 as_bad (_("bad register range"));
4190 for (; reg
< hi_reg
; reg
++)
4194 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4196 skip_past_char (&input_line_pointer
, '}');
4198 demand_empty_rest_of_line ();
4200 /* Generate any deferred opcodes because we're going to be looking at
4202 flush_pending_unwind ();
4204 for (i
= 0; i
< 16; i
++)
4206 if (mask
& (1 << i
))
4207 unwind
.frame_size
+= 8;
4210 /* Attempt to combine with a previous opcode. We do this because gcc
4211 likes to output separate unwind directives for a single block of
4213 if (unwind
.opcode_count
> 0)
4215 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4216 if ((i
& 0xf8) == 0xc0)
4219 /* Only merge if the blocks are contiguous. */
4222 if ((mask
& 0xfe00) == (1 << 9))
4224 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4225 unwind
.opcode_count
--;
4228 else if (i
== 6 && unwind
.opcode_count
>= 2)
4230 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4234 op
= 0xffff << (reg
- 1);
4236 && ((mask
& op
) == (1u << (reg
- 1))))
4238 op
= (1 << (reg
+ i
+ 1)) - 1;
4239 op
&= ~((1 << reg
) - 1);
4241 unwind
.opcode_count
-= 2;
4248 /* We want to generate opcodes in the order the registers have been
4249 saved, ie. descending order. */
4250 for (reg
= 15; reg
>= -1; reg
--)
4252 /* Save registers in blocks. */
4254 || !(mask
& (1 << reg
)))
4256 /* We found an unsaved reg. Generate opcodes to save the
4263 op
= 0xc0 | (hi_reg
- 10);
4264 add_unwind_opcode (op
, 1);
4269 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4270 add_unwind_opcode (op
, 2);
4279 ignore_rest_of_line ();
4283 s_arm_unwind_save_mmxwcg (void)
4290 if (*input_line_pointer
== '{')
4291 input_line_pointer
++;
4293 skip_whitespace (input_line_pointer
);
4297 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4301 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4307 as_tsktsk (_("register list not in ascending order"));
4310 if (*input_line_pointer
== '-')
4312 input_line_pointer
++;
4313 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4316 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4319 else if (reg
>= hi_reg
)
4321 as_bad (_("bad register range"));
4324 for (; reg
< hi_reg
; reg
++)
4328 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4330 skip_past_char (&input_line_pointer
, '}');
4332 demand_empty_rest_of_line ();
4334 /* Generate any deferred opcodes because we're going to be looking at
4336 flush_pending_unwind ();
4338 for (reg
= 0; reg
< 16; reg
++)
4340 if (mask
& (1 << reg
))
4341 unwind
.frame_size
+= 4;
4344 add_unwind_opcode (op
, 2);
4347 ignore_rest_of_line ();
4351 /* Parse an unwind_save directive.
4352 If the argument is non-zero, this is a .vsave directive. */
4355 s_arm_unwind_save (int arch_v6
)
4358 struct reg_entry
*reg
;
4359 bfd_boolean had_brace
= FALSE
;
4361 if (!unwind
.proc_start
)
4362 as_bad (MISSING_FNSTART
);
4364 /* Figure out what sort of save we have. */
4365 peek
= input_line_pointer
;
4373 reg
= arm_reg_parse_multi (&peek
);
4377 as_bad (_("register expected"));
4378 ignore_rest_of_line ();
4387 as_bad (_("FPA .unwind_save does not take a register list"));
4388 ignore_rest_of_line ();
4391 input_line_pointer
= peek
;
4392 s_arm_unwind_save_fpa (reg
->number
);
4396 s_arm_unwind_save_core ();
4401 s_arm_unwind_save_vfp_armv6 ();
4403 s_arm_unwind_save_vfp ();
4406 case REG_TYPE_MMXWR
:
4407 s_arm_unwind_save_mmxwr ();
4410 case REG_TYPE_MMXWCG
:
4411 s_arm_unwind_save_mmxwcg ();
4415 as_bad (_(".unwind_save does not support this kind of register"));
4416 ignore_rest_of_line ();
4421 /* Parse an unwind_movsp directive. */
4424 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4430 if (!unwind
.proc_start
)
4431 as_bad (MISSING_FNSTART
);
4433 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4436 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4437 ignore_rest_of_line ();
4441 /* Optional constant. */
4442 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4444 if (immediate_for_directive (&offset
) == FAIL
)
4450 demand_empty_rest_of_line ();
4452 if (reg
== REG_SP
|| reg
== REG_PC
)
4454 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4458 if (unwind
.fp_reg
!= REG_SP
)
4459 as_bad (_("unexpected .unwind_movsp directive"));
4461 /* Generate opcode to restore the value. */
4463 add_unwind_opcode (op
, 1);
4465 /* Record the information for later. */
4466 unwind
.fp_reg
= reg
;
4467 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4468 unwind
.sp_restored
= 1;
4471 /* Parse an unwind_pad directive. */
4474 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4478 if (!unwind
.proc_start
)
4479 as_bad (MISSING_FNSTART
);
4481 if (immediate_for_directive (&offset
) == FAIL
)
4486 as_bad (_("stack increment must be multiple of 4"));
4487 ignore_rest_of_line ();
4491 /* Don't generate any opcodes, just record the details for later. */
4492 unwind
.frame_size
+= offset
;
4493 unwind
.pending_offset
+= offset
;
4495 demand_empty_rest_of_line ();
4498 /* Parse an unwind_setfp directive. */
4501 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4507 if (!unwind
.proc_start
)
4508 as_bad (MISSING_FNSTART
);
4510 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4511 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4514 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4516 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4518 as_bad (_("expected <reg>, <reg>"));
4519 ignore_rest_of_line ();
4523 /* Optional constant. */
4524 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4526 if (immediate_for_directive (&offset
) == FAIL
)
4532 demand_empty_rest_of_line ();
4534 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4536 as_bad (_("register must be either sp or set by a previous"
4537 "unwind_movsp directive"));
4541 /* Don't generate any opcodes, just record the information for later. */
4542 unwind
.fp_reg
= fp_reg
;
4544 if (sp_reg
== REG_SP
)
4545 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4547 unwind
.fp_offset
-= offset
;
4550 /* Parse an unwind_raw directive. */
4553 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4556 /* This is an arbitrary limit. */
4557 unsigned char op
[16];
4560 if (!unwind
.proc_start
)
4561 as_bad (MISSING_FNSTART
);
4564 if (exp
.X_op
== O_constant
4565 && skip_past_comma (&input_line_pointer
) != FAIL
)
4567 unwind
.frame_size
+= exp
.X_add_number
;
4571 exp
.X_op
= O_illegal
;
4573 if (exp
.X_op
!= O_constant
)
4575 as_bad (_("expected <offset>, <opcode>"));
4576 ignore_rest_of_line ();
4582 /* Parse the opcode. */
4587 as_bad (_("unwind opcode too long"));
4588 ignore_rest_of_line ();
4590 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4592 as_bad (_("invalid unwind opcode"));
4593 ignore_rest_of_line ();
4596 op
[count
++] = exp
.X_add_number
;
4598 /* Parse the next byte. */
4599 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4605 /* Add the opcode bytes in reverse order. */
4607 add_unwind_opcode (op
[count
], 1);
4609 demand_empty_rest_of_line ();
4613 /* Parse a .eabi_attribute directive. */
4616 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4618 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4620 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4621 attributes_set_explicitly
[tag
] = 1;
4624 /* Emit a tls fix for the symbol. */
4627 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4631 #ifdef md_flush_pending_output
4632 md_flush_pending_output ();
4635 #ifdef md_cons_align
4639 /* Since we're just labelling the code, there's no need to define a
4642 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4643 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4644 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4645 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4647 #endif /* OBJ_ELF */
4649 static void s_arm_arch (int);
4650 static void s_arm_object_arch (int);
4651 static void s_arm_cpu (int);
4652 static void s_arm_fpu (int);
4653 static void s_arm_arch_extension (int);
4658 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4665 if (exp
.X_op
== O_symbol
)
4666 exp
.X_op
= O_secrel
;
4668 emit_expr (&exp
, 4);
4670 while (*input_line_pointer
++ == ',');
4672 input_line_pointer
--;
4673 demand_empty_rest_of_line ();
4677 /* This table describes all the machine specific pseudo-ops the assembler
4678 has to support. The fields are:
4679 pseudo-op name without dot
4680 function to call to execute this pseudo-op
4681 Integer arg to pass to the function. */
4683 const pseudo_typeS md_pseudo_table
[] =
4685 /* Never called because '.req' does not start a line. */
4686 { "req", s_req
, 0 },
4687 /* Following two are likewise never called. */
4690 { "unreq", s_unreq
, 0 },
4691 { "bss", s_bss
, 0 },
4692 { "align", s_align_ptwo
, 2 },
4693 { "arm", s_arm
, 0 },
4694 { "thumb", s_thumb
, 0 },
4695 { "code", s_code
, 0 },
4696 { "force_thumb", s_force_thumb
, 0 },
4697 { "thumb_func", s_thumb_func
, 0 },
4698 { "thumb_set", s_thumb_set
, 0 },
4699 { "even", s_even
, 0 },
4700 { "ltorg", s_ltorg
, 0 },
4701 { "pool", s_ltorg
, 0 },
4702 { "syntax", s_syntax
, 0 },
4703 { "cpu", s_arm_cpu
, 0 },
4704 { "arch", s_arm_arch
, 0 },
4705 { "object_arch", s_arm_object_arch
, 0 },
4706 { "fpu", s_arm_fpu
, 0 },
4707 { "arch_extension", s_arm_arch_extension
, 0 },
4709 { "word", s_arm_elf_cons
, 4 },
4710 { "long", s_arm_elf_cons
, 4 },
4711 { "inst.n", s_arm_elf_inst
, 2 },
4712 { "inst.w", s_arm_elf_inst
, 4 },
4713 { "inst", s_arm_elf_inst
, 0 },
4714 { "rel31", s_arm_rel31
, 0 },
4715 { "fnstart", s_arm_unwind_fnstart
, 0 },
4716 { "fnend", s_arm_unwind_fnend
, 0 },
4717 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4718 { "personality", s_arm_unwind_personality
, 0 },
4719 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4720 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4721 { "save", s_arm_unwind_save
, 0 },
4722 { "vsave", s_arm_unwind_save
, 1 },
4723 { "movsp", s_arm_unwind_movsp
, 0 },
4724 { "pad", s_arm_unwind_pad
, 0 },
4725 { "setfp", s_arm_unwind_setfp
, 0 },
4726 { "unwind_raw", s_arm_unwind_raw
, 0 },
4727 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4728 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4732 /* These are used for dwarf. */
4736 /* These are used for dwarf2. */
4737 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4738 { "loc", dwarf2_directive_loc
, 0 },
4739 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4741 { "extend", float_cons
, 'x' },
4742 { "ldouble", float_cons
, 'x' },
4743 { "packed", float_cons
, 'p' },
4745 {"secrel32", pe_directive_secrel
, 0},
4748 /* These are for compatibility with CodeComposer Studio. */
4749 {"ref", s_ccs_ref
, 0},
4750 {"def", s_ccs_def
, 0},
4751 {"asmfunc", s_ccs_asmfunc
, 0},
4752 {"endasmfunc", s_ccs_endasmfunc
, 0},
4757 /* Parser functions used exclusively in instruction operands. */
4759 /* Generic immediate-value read function for use in insn parsing.
4760 STR points to the beginning of the immediate (the leading #);
4761 VAL receives the value; if the value is outside [MIN, MAX]
4762 issue an error. PREFIX_OPT is true if the immediate prefix is
4766 parse_immediate (char **str
, int *val
, int min
, int max
,
4767 bfd_boolean prefix_opt
)
4770 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4771 if (exp
.X_op
!= O_constant
)
4773 inst
.error
= _("constant expression required");
4777 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4779 inst
.error
= _("immediate value out of range");
4783 *val
= exp
.X_add_number
;
4787 /* Less-generic immediate-value read function with the possibility of loading a
4788 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4789 instructions. Puts the result directly in inst.operands[i]. */
4792 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4793 bfd_boolean allow_symbol_p
)
4796 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4799 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4801 if (exp_p
->X_op
== O_constant
)
4803 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4804 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4805 O_constant. We have to be careful not to break compilation for
4806 32-bit X_add_number, though. */
4807 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4809 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4810 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4812 inst
.operands
[i
].regisimm
= 1;
4815 else if (exp_p
->X_op
== O_big
4816 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4818 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4820 /* Bignums have their least significant bits in
4821 generic_bignum[0]. Make sure we put 32 bits in imm and
4822 32 bits in reg, in a (hopefully) portable way. */
4823 gas_assert (parts
!= 0);
4825 /* Make sure that the number is not too big.
4826 PR 11972: Bignums can now be sign-extended to the
4827 size of a .octa so check that the out of range bits
4828 are all zero or all one. */
4829 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4831 LITTLENUM_TYPE m
= -1;
4833 if (generic_bignum
[parts
* 2] != 0
4834 && generic_bignum
[parts
* 2] != m
)
4837 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4838 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4842 inst
.operands
[i
].imm
= 0;
4843 for (j
= 0; j
< parts
; j
++, idx
++)
4844 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4845 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4846 inst
.operands
[i
].reg
= 0;
4847 for (j
= 0; j
< parts
; j
++, idx
++)
4848 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4849 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4850 inst
.operands
[i
].regisimm
= 1;
4852 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4860 /* Returns the pseudo-register number of an FPA immediate constant,
4861 or FAIL if there isn't a valid constant here. */
4864 parse_fpa_immediate (char ** str
)
4866 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4872 /* First try and match exact strings, this is to guarantee
4873 that some formats will work even for cross assembly. */
4875 for (i
= 0; fp_const
[i
]; i
++)
4877 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4881 *str
+= strlen (fp_const
[i
]);
4882 if (is_end_of_line
[(unsigned char) **str
])
4888 /* Just because we didn't get a match doesn't mean that the constant
4889 isn't valid, just that it is in a format that we don't
4890 automatically recognize. Try parsing it with the standard
4891 expression routines. */
4893 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4895 /* Look for a raw floating point number. */
4896 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4897 && is_end_of_line
[(unsigned char) *save_in
])
4899 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4901 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4903 if (words
[j
] != fp_values
[i
][j
])
4907 if (j
== MAX_LITTLENUMS
)
4915 /* Try and parse a more complex expression, this will probably fail
4916 unless the code uses a floating point prefix (eg "0f"). */
4917 save_in
= input_line_pointer
;
4918 input_line_pointer
= *str
;
4919 if (expression (&exp
) == absolute_section
4920 && exp
.X_op
== O_big
4921 && exp
.X_add_number
< 0)
4923 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4925 #define X_PRECISION 5
4926 #define E_PRECISION 15L
4927 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4929 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4931 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4933 if (words
[j
] != fp_values
[i
][j
])
4937 if (j
== MAX_LITTLENUMS
)
4939 *str
= input_line_pointer
;
4940 input_line_pointer
= save_in
;
4947 *str
= input_line_pointer
;
4948 input_line_pointer
= save_in
;
4949 inst
.error
= _("invalid FPA immediate expression");
4953 /* Returns 1 if a number has "quarter-precision" float format
4954 0baBbbbbbc defgh000 00000000 00000000. */
4957 is_quarter_float (unsigned imm
)
4959 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4960 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4964 /* Detect the presence of a floating point or integer zero constant,
4968 parse_ifimm_zero (char **in
)
4972 if (!is_immediate_prefix (**in
))
4974 /* In unified syntax, all prefixes are optional. */
4975 if (!unified_syntax
)
4981 /* Accept #0x0 as a synonym for #0. */
4982 if (strncmp (*in
, "0x", 2) == 0)
4985 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4990 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4991 &generic_floating_point_number
);
4994 && generic_floating_point_number
.sign
== '+'
4995 && (generic_floating_point_number
.low
4996 > generic_floating_point_number
.leader
))
5002 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5003 0baBbbbbbc defgh000 00000000 00000000.
5004 The zero and minus-zero cases need special handling, since they can't be
5005 encoded in the "quarter-precision" float format, but can nonetheless be
5006 loaded as integer constants. */
5009 parse_qfloat_immediate (char **ccp
, int *immed
)
5013 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5014 int found_fpchar
= 0;
5016 skip_past_char (&str
, '#');
5018 /* We must not accidentally parse an integer as a floating-point number. Make
5019 sure that the value we parse is not an integer by checking for special
5020 characters '.' or 'e'.
5021 FIXME: This is a horrible hack, but doing better is tricky because type
5022 information isn't in a very usable state at parse time. */
5024 skip_whitespace (fpnum
);
5026 if (strncmp (fpnum
, "0x", 2) == 0)
5030 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5031 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5041 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5043 unsigned fpword
= 0;
5046 /* Our FP word must be 32 bits (single-precision FP). */
5047 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5049 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5053 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5066 /* Shift operands. */
5069 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5072 struct asm_shift_name
5075 enum shift_kind kind
;
5078 /* Third argument to parse_shift. */
5079 enum parse_shift_mode
5081 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5082 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5083 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5084 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5085 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5088 /* Parse a <shift> specifier on an ARM data processing instruction.
5089 This has three forms:
5091 (LSL|LSR|ASL|ASR|ROR) Rs
5092 (LSL|LSR|ASL|ASR|ROR) #imm
5095 Note that ASL is assimilated to LSL in the instruction encoding, and
5096 RRX to ROR #0 (which cannot be written as such). */
5099 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5101 const struct asm_shift_name
*shift_name
;
5102 enum shift_kind shift
;
5107 for (p
= *str
; ISALPHA (*p
); p
++)
5112 inst
.error
= _("shift expression expected");
5116 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5119 if (shift_name
== NULL
)
5121 inst
.error
= _("shift expression expected");
5125 shift
= shift_name
->kind
;
5129 case NO_SHIFT_RESTRICT
:
5130 case SHIFT_IMMEDIATE
: break;
5132 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5133 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5135 inst
.error
= _("'LSL' or 'ASR' required");
5140 case SHIFT_LSL_IMMEDIATE
:
5141 if (shift
!= SHIFT_LSL
)
5143 inst
.error
= _("'LSL' required");
5148 case SHIFT_ASR_IMMEDIATE
:
5149 if (shift
!= SHIFT_ASR
)
5151 inst
.error
= _("'ASR' required");
5159 if (shift
!= SHIFT_RRX
)
5161 /* Whitespace can appear here if the next thing is a bare digit. */
5162 skip_whitespace (p
);
5164 if (mode
== NO_SHIFT_RESTRICT
5165 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5167 inst
.operands
[i
].imm
= reg
;
5168 inst
.operands
[i
].immisreg
= 1;
5170 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5173 inst
.operands
[i
].shift_kind
= shift
;
5174 inst
.operands
[i
].shifted
= 1;
5179 /* Parse a <shifter_operand> for an ARM data processing instruction:
5182 #<immediate>, <rotate>
5186 where <shift> is defined by parse_shift above, and <rotate> is a
5187 multiple of 2 between 0 and 30. Validation of immediate operands
5188 is deferred to md_apply_fix. */
5191 parse_shifter_operand (char **str
, int i
)
5196 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5198 inst
.operands
[i
].reg
= value
;
5199 inst
.operands
[i
].isreg
= 1;
5201 /* parse_shift will override this if appropriate */
5202 inst
.reloc
.exp
.X_op
= O_constant
;
5203 inst
.reloc
.exp
.X_add_number
= 0;
5205 if (skip_past_comma (str
) == FAIL
)
5208 /* Shift operation on register. */
5209 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5212 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5215 if (skip_past_comma (str
) == SUCCESS
)
5217 /* #x, y -- ie explicit rotation by Y. */
5218 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5221 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5223 inst
.error
= _("constant expression expected");
5227 value
= exp
.X_add_number
;
5228 if (value
< 0 || value
> 30 || value
% 2 != 0)
5230 inst
.error
= _("invalid rotation");
5233 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5235 inst
.error
= _("invalid constant");
5239 /* Encode as specified. */
5240 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5244 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5245 inst
.reloc
.pc_rel
= 0;
5249 /* Group relocation information. Each entry in the table contains the
5250 textual name of the relocation as may appear in assembler source
5251 and must end with a colon.
5252 Along with this textual name are the relocation codes to be used if
5253 the corresponding instruction is an ALU instruction (ADD or SUB only),
5254 an LDR, an LDRS, or an LDC. */
5256 struct group_reloc_table_entry
5267 /* Varieties of non-ALU group relocation. */
5274 static struct group_reloc_table_entry group_reloc_table
[] =
5275 { /* Program counter relative: */
5277 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5282 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5283 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5284 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5285 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5287 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5292 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5293 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5297 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5298 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5299 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5300 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5301 /* Section base relative */
5303 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5308 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5309 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5310 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5311 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5313 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5318 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5319 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5320 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5321 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5323 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5324 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5325 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5326 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5327 /* Absolute thumb alu relocations. */
5329 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5334 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5339 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5344 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5349 /* Given the address of a pointer pointing to the textual name of a group
5350 relocation as may appear in assembler source, attempt to find its details
5351 in group_reloc_table. The pointer will be updated to the character after
5352 the trailing colon. On failure, FAIL will be returned; SUCCESS
5353 otherwise. On success, *entry will be updated to point at the relevant
5354 group_reloc_table entry. */
5357 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5360 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5362 int length
= strlen (group_reloc_table
[i
].name
);
5364 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5365 && (*str
)[length
] == ':')
5367 *out
= &group_reloc_table
[i
];
5368 *str
+= (length
+ 1);
5376 /* Parse a <shifter_operand> for an ARM data processing instruction
5377 (as for parse_shifter_operand) where group relocations are allowed:
5380 #<immediate>, <rotate>
5381 #:<group_reloc>:<expression>
5385 where <group_reloc> is one of the strings defined in group_reloc_table.
5386 The hashes are optional.
5388 Everything else is as for parse_shifter_operand. */
5390 static parse_operand_result
5391 parse_shifter_operand_group_reloc (char **str
, int i
)
5393 /* Determine if we have the sequence of characters #: or just :
5394 coming next. If we do, then we check for a group relocation.
5395 If we don't, punt the whole lot to parse_shifter_operand. */
5397 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5398 || (*str
)[0] == ':')
5400 struct group_reloc_table_entry
*entry
;
5402 if ((*str
)[0] == '#')
5407 /* Try to parse a group relocation. Anything else is an error. */
5408 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5410 inst
.error
= _("unknown group relocation");
5411 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5414 /* We now have the group relocation table entry corresponding to
5415 the name in the assembler source. Next, we parse the expression. */
5416 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5417 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5419 /* Record the relocation type (always the ALU variant here). */
5420 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5421 gas_assert (inst
.reloc
.type
!= 0);
5423 return PARSE_OPERAND_SUCCESS
;
5426 return parse_shifter_operand (str
, i
) == SUCCESS
5427 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5429 /* Never reached. */
5432 /* Parse a Neon alignment expression. Information is written to
5433 inst.operands[i]. We assume the initial ':' has been skipped.
5435 align .imm = align << 8, .immisalign=1, .preind=0 */
5436 static parse_operand_result
5437 parse_neon_alignment (char **str
, int i
)
5442 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5444 if (exp
.X_op
!= O_constant
)
5446 inst
.error
= _("alignment must be constant");
5447 return PARSE_OPERAND_FAIL
;
5450 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5451 inst
.operands
[i
].immisalign
= 1;
5452 /* Alignments are not pre-indexes. */
5453 inst
.operands
[i
].preind
= 0;
5456 return PARSE_OPERAND_SUCCESS
;
5459 /* Parse all forms of an ARM address expression. Information is written
5460 to inst.operands[i] and/or inst.reloc.
5462 Preindexed addressing (.preind=1):
5464 [Rn, #offset] .reg=Rn .reloc.exp=offset
5465 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5467 .shift_kind=shift .reloc.exp=shift_imm
5469 These three may have a trailing ! which causes .writeback to be set also.
5471 Postindexed addressing (.postind=1, .writeback=1):
5473 [Rn], #offset .reg=Rn .reloc.exp=offset
5474 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5475 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5476 .shift_kind=shift .reloc.exp=shift_imm
5478 Unindexed addressing (.preind=0, .postind=0):
5480 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5484 [Rn]{!} shorthand for [Rn,#0]{!}
5485 =immediate .isreg=0 .reloc.exp=immediate
5486 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5488 It is the caller's responsibility to check for addressing modes not
5489 supported by the instruction, and to set inst.reloc.type. */
5491 static parse_operand_result
5492 parse_address_main (char **str
, int i
, int group_relocations
,
5493 group_reloc_type group_type
)
5498 if (skip_past_char (&p
, '[') == FAIL
)
5500 if (skip_past_char (&p
, '=') == FAIL
)
5502 /* Bare address - translate to PC-relative offset. */
5503 inst
.reloc
.pc_rel
= 1;
5504 inst
.operands
[i
].reg
= REG_PC
;
5505 inst
.operands
[i
].isreg
= 1;
5506 inst
.operands
[i
].preind
= 1;
5508 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5509 return PARSE_OPERAND_FAIL
;
5511 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5512 /*allow_symbol_p=*/TRUE
))
5513 return PARSE_OPERAND_FAIL
;
5516 return PARSE_OPERAND_SUCCESS
;
5519 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5520 skip_whitespace (p
);
5522 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5524 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5525 return PARSE_OPERAND_FAIL
;
5527 inst
.operands
[i
].reg
= reg
;
5528 inst
.operands
[i
].isreg
= 1;
5530 if (skip_past_comma (&p
) == SUCCESS
)
5532 inst
.operands
[i
].preind
= 1;
5535 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5537 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5539 inst
.operands
[i
].imm
= reg
;
5540 inst
.operands
[i
].immisreg
= 1;
5542 if (skip_past_comma (&p
) == SUCCESS
)
5543 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5544 return PARSE_OPERAND_FAIL
;
5546 else if (skip_past_char (&p
, ':') == SUCCESS
)
5548 /* FIXME: '@' should be used here, but it's filtered out by generic
5549 code before we get to see it here. This may be subject to
5551 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5553 if (result
!= PARSE_OPERAND_SUCCESS
)
5558 if (inst
.operands
[i
].negative
)
5560 inst
.operands
[i
].negative
= 0;
5564 if (group_relocations
5565 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5567 struct group_reloc_table_entry
*entry
;
5569 /* Skip over the #: or : sequence. */
5575 /* Try to parse a group relocation. Anything else is an
5577 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5579 inst
.error
= _("unknown group relocation");
5580 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5583 /* We now have the group relocation table entry corresponding to
5584 the name in the assembler source. Next, we parse the
5586 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5587 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5589 /* Record the relocation type. */
5593 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5597 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5601 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5608 if (inst
.reloc
.type
== 0)
5610 inst
.error
= _("this group relocation is not allowed on this instruction");
5611 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5617 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5618 return PARSE_OPERAND_FAIL
;
5619 /* If the offset is 0, find out if it's a +0 or -0. */
5620 if (inst
.reloc
.exp
.X_op
== O_constant
5621 && inst
.reloc
.exp
.X_add_number
== 0)
5623 skip_whitespace (q
);
5627 skip_whitespace (q
);
5630 inst
.operands
[i
].negative
= 1;
5635 else if (skip_past_char (&p
, ':') == SUCCESS
)
5637 /* FIXME: '@' should be used here, but it's filtered out by generic code
5638 before we get to see it here. This may be subject to change. */
5639 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5641 if (result
!= PARSE_OPERAND_SUCCESS
)
5645 if (skip_past_char (&p
, ']') == FAIL
)
5647 inst
.error
= _("']' expected");
5648 return PARSE_OPERAND_FAIL
;
5651 if (skip_past_char (&p
, '!') == SUCCESS
)
5652 inst
.operands
[i
].writeback
= 1;
5654 else if (skip_past_comma (&p
) == SUCCESS
)
5656 if (skip_past_char (&p
, '{') == SUCCESS
)
5658 /* [Rn], {expr} - unindexed, with option */
5659 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5660 0, 255, TRUE
) == FAIL
)
5661 return PARSE_OPERAND_FAIL
;
5663 if (skip_past_char (&p
, '}') == FAIL
)
5665 inst
.error
= _("'}' expected at end of 'option' field");
5666 return PARSE_OPERAND_FAIL
;
5668 if (inst
.operands
[i
].preind
)
5670 inst
.error
= _("cannot combine index with option");
5671 return PARSE_OPERAND_FAIL
;
5674 return PARSE_OPERAND_SUCCESS
;
5678 inst
.operands
[i
].postind
= 1;
5679 inst
.operands
[i
].writeback
= 1;
5681 if (inst
.operands
[i
].preind
)
5683 inst
.error
= _("cannot combine pre- and post-indexing");
5684 return PARSE_OPERAND_FAIL
;
5688 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5690 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5692 /* We might be using the immediate for alignment already. If we
5693 are, OR the register number into the low-order bits. */
5694 if (inst
.operands
[i
].immisalign
)
5695 inst
.operands
[i
].imm
|= reg
;
5697 inst
.operands
[i
].imm
= reg
;
5698 inst
.operands
[i
].immisreg
= 1;
5700 if (skip_past_comma (&p
) == SUCCESS
)
5701 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5702 return PARSE_OPERAND_FAIL
;
5707 if (inst
.operands
[i
].negative
)
5709 inst
.operands
[i
].negative
= 0;
5712 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5713 return PARSE_OPERAND_FAIL
;
5714 /* If the offset is 0, find out if it's a +0 or -0. */
5715 if (inst
.reloc
.exp
.X_op
== O_constant
5716 && inst
.reloc
.exp
.X_add_number
== 0)
5718 skip_whitespace (q
);
5722 skip_whitespace (q
);
5725 inst
.operands
[i
].negative
= 1;
5731 /* If at this point neither .preind nor .postind is set, we have a
5732 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5733 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5735 inst
.operands
[i
].preind
= 1;
5736 inst
.reloc
.exp
.X_op
= O_constant
;
5737 inst
.reloc
.exp
.X_add_number
= 0;
5740 return PARSE_OPERAND_SUCCESS
;
5744 parse_address (char **str
, int i
)
5746 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5750 static parse_operand_result
5751 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5753 return parse_address_main (str
, i
, 1, type
);
5756 /* Parse an operand for a MOVW or MOVT instruction. */
5758 parse_half (char **str
)
5763 skip_past_char (&p
, '#');
5764 if (strncasecmp (p
, ":lower16:", 9) == 0)
5765 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5766 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5767 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5769 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5772 skip_whitespace (p
);
5775 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5778 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5780 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5782 inst
.error
= _("constant expression expected");
5785 if (inst
.reloc
.exp
.X_add_number
< 0
5786 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5788 inst
.error
= _("immediate value out of range");
5796 /* Miscellaneous. */
5798 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5799 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5801 parse_psr (char **str
, bfd_boolean lhs
)
5804 unsigned long psr_field
;
5805 const struct asm_psr
*psr
;
5807 bfd_boolean is_apsr
= FALSE
;
5808 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5810 /* PR gas/12698: If the user has specified -march=all then m_profile will
5811 be TRUE, but we want to ignore it in this case as we are building for any
5812 CPU type, including non-m variants. */
5813 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5816 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5817 feature for ease of use and backwards compatibility. */
5819 if (strncasecmp (p
, "SPSR", 4) == 0)
5822 goto unsupported_psr
;
5824 psr_field
= SPSR_BIT
;
5826 else if (strncasecmp (p
, "CPSR", 4) == 0)
5829 goto unsupported_psr
;
5833 else if (strncasecmp (p
, "APSR", 4) == 0)
5835 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5836 and ARMv7-R architecture CPUs. */
5845 while (ISALNUM (*p
) || *p
== '_');
5847 if (strncasecmp (start
, "iapsr", 5) == 0
5848 || strncasecmp (start
, "eapsr", 5) == 0
5849 || strncasecmp (start
, "xpsr", 4) == 0
5850 || strncasecmp (start
, "psr", 3) == 0)
5851 p
= start
+ strcspn (start
, "rR") + 1;
5853 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5859 /* If APSR is being written, a bitfield may be specified. Note that
5860 APSR itself is handled above. */
5861 if (psr
->field
<= 3)
5863 psr_field
= psr
->field
;
5869 /* M-profile MSR instructions have the mask field set to "10", except
5870 *PSR variants which modify APSR, which may use a different mask (and
5871 have been handled already). Do that by setting the PSR_f field
5873 return psr
->field
| (lhs
? PSR_f
: 0);
5876 goto unsupported_psr
;
5882 /* A suffix follows. */
5888 while (ISALNUM (*p
) || *p
== '_');
5892 /* APSR uses a notation for bits, rather than fields. */
5893 unsigned int nzcvq_bits
= 0;
5894 unsigned int g_bit
= 0;
5897 for (bit
= start
; bit
!= p
; bit
++)
5899 switch (TOLOWER (*bit
))
5902 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5906 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5910 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5914 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5918 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5922 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5926 inst
.error
= _("unexpected bit specified after APSR");
5931 if (nzcvq_bits
== 0x1f)
5936 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5938 inst
.error
= _("selected processor does not "
5939 "support DSP extension");
5946 if ((nzcvq_bits
& 0x20) != 0
5947 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5948 || (g_bit
& 0x2) != 0)
5950 inst
.error
= _("bad bitmask specified after APSR");
5956 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5961 psr_field
|= psr
->field
;
5967 goto error
; /* Garbage after "[CS]PSR". */
5969 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5970 is deprecated, but allow it anyway. */
5974 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5977 else if (!m_profile
)
5978 /* These bits are never right for M-profile devices: don't set them
5979 (only code paths which read/write APSR reach here). */
5980 psr_field
|= (PSR_c
| PSR_f
);
5986 inst
.error
= _("selected processor does not support requested special "
5987 "purpose register");
5991 inst
.error
= _("flag for {c}psr instruction expected");
5995 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5996 value suitable for splatting into the AIF field of the instruction. */
5999 parse_cps_flags (char **str
)
6008 case '\0': case ',':
6011 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6012 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6013 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6016 inst
.error
= _("unrecognized CPS flag");
6021 if (saw_a_flag
== 0)
6023 inst
.error
= _("missing CPS flags");
6031 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6032 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6035 parse_endian_specifier (char **str
)
6040 if (strncasecmp (s
, "BE", 2))
6042 else if (strncasecmp (s
, "LE", 2))
6046 inst
.error
= _("valid endian specifiers are be or le");
6050 if (ISALNUM (s
[2]) || s
[2] == '_')
6052 inst
.error
= _("valid endian specifiers are be or le");
6057 return little_endian
;
6060 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6061 value suitable for poking into the rotate field of an sxt or sxta
6062 instruction, or FAIL on error. */
6065 parse_ror (char **str
)
6070 if (strncasecmp (s
, "ROR", 3) == 0)
6074 inst
.error
= _("missing rotation field after comma");
6078 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6083 case 0: *str
= s
; return 0x0;
6084 case 8: *str
= s
; return 0x1;
6085 case 16: *str
= s
; return 0x2;
6086 case 24: *str
= s
; return 0x3;
6089 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6094 /* Parse a conditional code (from conds[] below). The value returned is in the
6095 range 0 .. 14, or FAIL. */
6097 parse_cond (char **str
)
6100 const struct asm_cond
*c
;
6102 /* Condition codes are always 2 characters, so matching up to
6103 3 characters is sufficient. */
6108 while (ISALPHA (*q
) && n
< 3)
6110 cond
[n
] = TOLOWER (*q
);
6115 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6118 inst
.error
= _("condition required");
6126 /* Record a use of the given feature. */
6128 record_feature_use (const arm_feature_set
*feature
)
6131 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6133 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6136 /* If the given feature available in the selected CPU, mark it as used.
6137 Returns TRUE iff feature is available. */
6139 mark_feature_used (const arm_feature_set
*feature
)
6141 /* Ensure the option is valid on the current architecture. */
6142 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6145 /* Add the appropriate architecture feature for the barrier option used.
6147 record_feature_use (feature
);
6152 /* Parse an option for a barrier instruction. Returns the encoding for the
6155 parse_barrier (char **str
)
6158 const struct asm_barrier_opt
*o
;
6161 while (ISALPHA (*q
))
6164 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6169 if (!mark_feature_used (&o
->arch
))
6176 /* Parse the operands of a table branch instruction. Similar to a memory
6179 parse_tb (char **str
)
6184 if (skip_past_char (&p
, '[') == FAIL
)
6186 inst
.error
= _("'[' expected");
6190 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6192 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6195 inst
.operands
[0].reg
= reg
;
6197 if (skip_past_comma (&p
) == FAIL
)
6199 inst
.error
= _("',' expected");
6203 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6205 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6208 inst
.operands
[0].imm
= reg
;
6210 if (skip_past_comma (&p
) == SUCCESS
)
6212 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6214 if (inst
.reloc
.exp
.X_add_number
!= 1)
6216 inst
.error
= _("invalid shift");
6219 inst
.operands
[0].shifted
= 1;
6222 if (skip_past_char (&p
, ']') == FAIL
)
6224 inst
.error
= _("']' expected");
6231 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6232 information on the types the operands can take and how they are encoded.
6233 Up to four operands may be read; this function handles setting the
6234 ".present" field for each read operand itself.
6235 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6236 else returns FAIL. */
6239 parse_neon_mov (char **str
, int *which_operand
)
6241 int i
= *which_operand
, val
;
6242 enum arm_reg_type rtype
;
6244 struct neon_type_el optype
;
6246 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6248 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6249 inst
.operands
[i
].reg
= val
;
6250 inst
.operands
[i
].isscalar
= 1;
6251 inst
.operands
[i
].vectype
= optype
;
6252 inst
.operands
[i
++].present
= 1;
6254 if (skip_past_comma (&ptr
) == FAIL
)
6257 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6260 inst
.operands
[i
].reg
= val
;
6261 inst
.operands
[i
].isreg
= 1;
6262 inst
.operands
[i
].present
= 1;
6264 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6267 /* Cases 0, 1, 2, 3, 5 (D only). */
6268 if (skip_past_comma (&ptr
) == FAIL
)
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isreg
= 1;
6273 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6274 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6275 inst
.operands
[i
].isvec
= 1;
6276 inst
.operands
[i
].vectype
= optype
;
6277 inst
.operands
[i
++].present
= 1;
6279 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6281 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6282 Case 13: VMOV <Sd>, <Rm> */
6283 inst
.operands
[i
].reg
= val
;
6284 inst
.operands
[i
].isreg
= 1;
6285 inst
.operands
[i
].present
= 1;
6287 if (rtype
== REG_TYPE_NQ
)
6289 first_error (_("can't use Neon quad register here"));
6292 else if (rtype
!= REG_TYPE_VFS
)
6295 if (skip_past_comma (&ptr
) == FAIL
)
6297 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6299 inst
.operands
[i
].reg
= val
;
6300 inst
.operands
[i
].isreg
= 1;
6301 inst
.operands
[i
].present
= 1;
6304 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6307 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6308 Case 1: VMOV<c><q> <Dd>, <Dm>
6309 Case 8: VMOV.F32 <Sd>, <Sm>
6310 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6312 inst
.operands
[i
].reg
= val
;
6313 inst
.operands
[i
].isreg
= 1;
6314 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6315 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6316 inst
.operands
[i
].isvec
= 1;
6317 inst
.operands
[i
].vectype
= optype
;
6318 inst
.operands
[i
].present
= 1;
6320 if (skip_past_comma (&ptr
) == SUCCESS
)
6325 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6328 inst
.operands
[i
].reg
= val
;
6329 inst
.operands
[i
].isreg
= 1;
6330 inst
.operands
[i
++].present
= 1;
6332 if (skip_past_comma (&ptr
) == FAIL
)
6335 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6338 inst
.operands
[i
].reg
= val
;
6339 inst
.operands
[i
].isreg
= 1;
6340 inst
.operands
[i
].present
= 1;
6343 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6344 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6345 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6346 Case 10: VMOV.F32 <Sd>, #<imm>
6347 Case 11: VMOV.F64 <Dd>, #<imm> */
6348 inst
.operands
[i
].immisfloat
= 1;
6349 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6351 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6352 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6356 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6360 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6363 inst
.operands
[i
].reg
= val
;
6364 inst
.operands
[i
].isreg
= 1;
6365 inst
.operands
[i
++].present
= 1;
6367 if (skip_past_comma (&ptr
) == FAIL
)
6370 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6372 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6373 inst
.operands
[i
].reg
= val
;
6374 inst
.operands
[i
].isscalar
= 1;
6375 inst
.operands
[i
].present
= 1;
6376 inst
.operands
[i
].vectype
= optype
;
6378 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6380 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6381 inst
.operands
[i
].reg
= val
;
6382 inst
.operands
[i
].isreg
= 1;
6383 inst
.operands
[i
++].present
= 1;
6385 if (skip_past_comma (&ptr
) == FAIL
)
6388 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6391 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6395 inst
.operands
[i
].reg
= val
;
6396 inst
.operands
[i
].isreg
= 1;
6397 inst
.operands
[i
].isvec
= 1;
6398 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6399 inst
.operands
[i
].vectype
= optype
;
6400 inst
.operands
[i
].present
= 1;
6402 if (rtype
== REG_TYPE_VFS
)
6406 if (skip_past_comma (&ptr
) == FAIL
)
6408 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6411 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6414 inst
.operands
[i
].reg
= val
;
6415 inst
.operands
[i
].isreg
= 1;
6416 inst
.operands
[i
].isvec
= 1;
6417 inst
.operands
[i
].issingle
= 1;
6418 inst
.operands
[i
].vectype
= optype
;
6419 inst
.operands
[i
].present
= 1;
6422 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6426 inst
.operands
[i
].reg
= val
;
6427 inst
.operands
[i
].isreg
= 1;
6428 inst
.operands
[i
].isvec
= 1;
6429 inst
.operands
[i
].issingle
= 1;
6430 inst
.operands
[i
].vectype
= optype
;
6431 inst
.operands
[i
].present
= 1;
6436 first_error (_("parse error"));
6440 /* Successfully parsed the operands. Update args. */
6446 first_error (_("expected comma"));
6450 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6454 /* Use this macro when the operand constraints are different
6455 for ARM and THUMB (e.g. ldrd). */
6456 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6457 ((arm_operand) | ((thumb_operand) << 16))
6459 /* Matcher codes for parse_operands. */
6460 enum operand_parse_code
6462 OP_stop
, /* end of line */
6464 OP_RR
, /* ARM register */
6465 OP_RRnpc
, /* ARM register, not r15 */
6466 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6467 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6468 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6469 optional trailing ! */
6470 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6471 OP_RCP
, /* Coprocessor number */
6472 OP_RCN
, /* Coprocessor register */
6473 OP_RF
, /* FPA register */
6474 OP_RVS
, /* VFP single precision register */
6475 OP_RVD
, /* VFP double precision register (0..15) */
6476 OP_RND
, /* Neon double precision register (0..31) */
6477 OP_RNQ
, /* Neon quad precision register */
6478 OP_RVSD
, /* VFP single or double precision register */
6479 OP_RNDQ
, /* Neon double or quad precision register */
6480 OP_RNSDQ
, /* Neon single, double or quad precision register */
6481 OP_RNSC
, /* Neon scalar D[X] */
6482 OP_RVC
, /* VFP control register */
6483 OP_RMF
, /* Maverick F register */
6484 OP_RMD
, /* Maverick D register */
6485 OP_RMFX
, /* Maverick FX register */
6486 OP_RMDX
, /* Maverick DX register */
6487 OP_RMAX
, /* Maverick AX register */
6488 OP_RMDS
, /* Maverick DSPSC register */
6489 OP_RIWR
, /* iWMMXt wR register */
6490 OP_RIWC
, /* iWMMXt wC register */
6491 OP_RIWG
, /* iWMMXt wCG register */
6492 OP_RXA
, /* XScale accumulator register */
6494 OP_REGLST
, /* ARM register list */
6495 OP_VRSLST
, /* VFP single-precision register list */
6496 OP_VRDLST
, /* VFP double-precision register list */
6497 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6498 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6499 OP_NSTRLST
, /* Neon element/structure list */
6501 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6502 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6503 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6504 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6505 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6506 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6507 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6508 OP_VMOV
, /* Neon VMOV operands. */
6509 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6510 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6511 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6513 OP_I0
, /* immediate zero */
6514 OP_I7
, /* immediate value 0 .. 7 */
6515 OP_I15
, /* 0 .. 15 */
6516 OP_I16
, /* 1 .. 16 */
6517 OP_I16z
, /* 0 .. 16 */
6518 OP_I31
, /* 0 .. 31 */
6519 OP_I31w
, /* 0 .. 31, optional trailing ! */
6520 OP_I32
, /* 1 .. 32 */
6521 OP_I32z
, /* 0 .. 32 */
6522 OP_I63
, /* 0 .. 63 */
6523 OP_I63s
, /* -64 .. 63 */
6524 OP_I64
, /* 1 .. 64 */
6525 OP_I64z
, /* 0 .. 64 */
6526 OP_I255
, /* 0 .. 255 */
6528 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6529 OP_I7b
, /* 0 .. 7 */
6530 OP_I15b
, /* 0 .. 15 */
6531 OP_I31b
, /* 0 .. 31 */
6533 OP_SH
, /* shifter operand */
6534 OP_SHG
, /* shifter operand with possible group relocation */
6535 OP_ADDR
, /* Memory address expression (any mode) */
6536 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6537 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6538 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6539 OP_EXP
, /* arbitrary expression */
6540 OP_EXPi
, /* same, with optional immediate prefix */
6541 OP_EXPr
, /* same, with optional relocation suffix */
6542 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6543 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6544 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6546 OP_CPSF
, /* CPS flags */
6547 OP_ENDI
, /* Endianness specifier */
6548 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6549 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6550 OP_COND
, /* conditional code */
6551 OP_TB
, /* Table branch. */
6553 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6555 OP_RRnpc_I0
, /* ARM register or literal 0 */
6556 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6557 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6558 OP_RF_IF
, /* FPA register or immediate */
6559 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6560 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6562 /* Optional operands. */
6563 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6564 OP_oI31b
, /* 0 .. 31 */
6565 OP_oI32b
, /* 1 .. 32 */
6566 OP_oI32z
, /* 0 .. 32 */
6567 OP_oIffffb
, /* 0 .. 65535 */
6568 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6570 OP_oRR
, /* ARM register */
6571 OP_oRRnpc
, /* ARM register, not the PC */
6572 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6573 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6574 OP_oRND
, /* Optional Neon double precision register */
6575 OP_oRNQ
, /* Optional Neon quad precision register */
6576 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6577 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6578 OP_oSHll
, /* LSL immediate */
6579 OP_oSHar
, /* ASR immediate */
6580 OP_oSHllar
, /* LSL or ASR immediate */
6581 OP_oROR
, /* ROR 0/8/16/24 */
6582 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6584 /* Some pre-defined mixed (ARM/THUMB) operands. */
6585 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6586 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6587 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6589 OP_FIRST_OPTIONAL
= OP_oI7b
6592 /* Generic instruction operand parser. This does no encoding and no
6593 semantic validation; it merely squirrels values away in the inst
6594 structure. Returns SUCCESS or FAIL depending on whether the
6595 specified grammar matched. */
6597 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6599 unsigned const int *upat
= pattern
;
6600 char *backtrack_pos
= 0;
6601 const char *backtrack_error
= 0;
6602 int i
, val
= 0, backtrack_index
= 0;
6603 enum arm_reg_type rtype
;
6604 parse_operand_result result
;
6605 unsigned int op_parse_code
;
6607 #define po_char_or_fail(chr) \
6610 if (skip_past_char (&str, chr) == FAIL) \
6615 #define po_reg_or_fail(regtype) \
6618 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6619 & inst.operands[i].vectype); \
6622 first_error (_(reg_expected_msgs[regtype])); \
6625 inst.operands[i].reg = val; \
6626 inst.operands[i].isreg = 1; \
6627 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6628 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6629 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6630 || rtype == REG_TYPE_VFD \
6631 || rtype == REG_TYPE_NQ); \
6635 #define po_reg_or_goto(regtype, label) \
6638 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6639 & inst.operands[i].vectype); \
6643 inst.operands[i].reg = val; \
6644 inst.operands[i].isreg = 1; \
6645 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6646 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6647 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6648 || rtype == REG_TYPE_VFD \
6649 || rtype == REG_TYPE_NQ); \
6653 #define po_imm_or_fail(min, max, popt) \
6656 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6658 inst.operands[i].imm = val; \
6662 #define po_scalar_or_goto(elsz, label) \
6665 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6668 inst.operands[i].reg = val; \
6669 inst.operands[i].isscalar = 1; \
6673 #define po_misc_or_fail(expr) \
6681 #define po_misc_or_fail_no_backtrack(expr) \
6685 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6686 backtrack_pos = 0; \
6687 if (result != PARSE_OPERAND_SUCCESS) \
6692 #define po_barrier_or_imm(str) \
6695 val = parse_barrier (&str); \
6696 if (val == FAIL && ! ISALPHA (*str)) \
6699 /* ISB can only take SY as an option. */ \
6700 || ((inst.instruction & 0xf0) == 0x60 \
6703 inst.error = _("invalid barrier type"); \
6704 backtrack_pos = 0; \
6710 skip_whitespace (str
);
6712 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6714 op_parse_code
= upat
[i
];
6715 if (op_parse_code
>= 1<<16)
6716 op_parse_code
= thumb
? (op_parse_code
>> 16)
6717 : (op_parse_code
& ((1<<16)-1));
6719 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6721 /* Remember where we are in case we need to backtrack. */
6722 gas_assert (!backtrack_pos
);
6723 backtrack_pos
= str
;
6724 backtrack_error
= inst
.error
;
6725 backtrack_index
= i
;
6728 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6729 po_char_or_fail (',');
6731 switch (op_parse_code
)
6739 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6740 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6741 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6742 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6743 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6744 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6746 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6748 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6750 /* Also accept generic coprocessor regs for unknown registers. */
6752 po_reg_or_fail (REG_TYPE_CN
);
6754 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6755 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6756 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6757 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6758 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6759 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6760 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6761 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6762 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6763 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6765 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6767 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6768 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6770 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6772 /* Neon scalar. Using an element size of 8 means that some invalid
6773 scalars are accepted here, so deal with those in later code. */
6774 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6778 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6781 po_imm_or_fail (0, 0, TRUE
);
6786 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6791 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6794 if (parse_ifimm_zero (&str
))
6795 inst
.operands
[i
].imm
= 0;
6799 = _("only floating point zero is allowed as immediate value");
6807 po_scalar_or_goto (8, try_rr
);
6810 po_reg_or_fail (REG_TYPE_RN
);
6816 po_scalar_or_goto (8, try_nsdq
);
6819 po_reg_or_fail (REG_TYPE_NSDQ
);
6825 po_scalar_or_goto (8, try_ndq
);
6828 po_reg_or_fail (REG_TYPE_NDQ
);
6834 po_scalar_or_goto (8, try_vfd
);
6837 po_reg_or_fail (REG_TYPE_VFD
);
6842 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6843 not careful then bad things might happen. */
6844 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6849 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6852 /* There's a possibility of getting a 64-bit immediate here, so
6853 we need special handling. */
6854 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6857 inst
.error
= _("immediate value is out of range");
6865 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6868 po_imm_or_fail (0, 63, TRUE
);
6873 po_char_or_fail ('[');
6874 po_reg_or_fail (REG_TYPE_RN
);
6875 po_char_or_fail (']');
6881 po_reg_or_fail (REG_TYPE_RN
);
6882 if (skip_past_char (&str
, '!') == SUCCESS
)
6883 inst
.operands
[i
].writeback
= 1;
6887 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6888 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6889 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6890 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6891 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6892 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6893 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6894 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6895 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6896 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6897 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6898 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6900 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6902 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6903 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6905 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6906 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6907 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6908 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6910 /* Immediate variants */
6912 po_char_or_fail ('{');
6913 po_imm_or_fail (0, 255, TRUE
);
6914 po_char_or_fail ('}');
6918 /* The expression parser chokes on a trailing !, so we have
6919 to find it first and zap it. */
6922 while (*s
&& *s
!= ',')
6927 inst
.operands
[i
].writeback
= 1;
6929 po_imm_or_fail (0, 31, TRUE
);
6937 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6942 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6947 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6949 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6951 val
= parse_reloc (&str
);
6954 inst
.error
= _("unrecognized relocation suffix");
6957 else if (val
!= BFD_RELOC_UNUSED
)
6959 inst
.operands
[i
].imm
= val
;
6960 inst
.operands
[i
].hasreloc
= 1;
6965 /* Operand for MOVW or MOVT. */
6967 po_misc_or_fail (parse_half (&str
));
6970 /* Register or expression. */
6971 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6972 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6974 /* Register or immediate. */
6975 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6976 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6978 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6980 if (!is_immediate_prefix (*str
))
6983 val
= parse_fpa_immediate (&str
);
6986 /* FPA immediates are encoded as registers 8-15.
6987 parse_fpa_immediate has already applied the offset. */
6988 inst
.operands
[i
].reg
= val
;
6989 inst
.operands
[i
].isreg
= 1;
6992 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6993 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6995 /* Two kinds of register. */
6998 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7000 || (rege
->type
!= REG_TYPE_MMXWR
7001 && rege
->type
!= REG_TYPE_MMXWC
7002 && rege
->type
!= REG_TYPE_MMXWCG
))
7004 inst
.error
= _("iWMMXt data or control register expected");
7007 inst
.operands
[i
].reg
= rege
->number
;
7008 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7014 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7016 || (rege
->type
!= REG_TYPE_MMXWC
7017 && rege
->type
!= REG_TYPE_MMXWCG
))
7019 inst
.error
= _("iWMMXt control register expected");
7022 inst
.operands
[i
].reg
= rege
->number
;
7023 inst
.operands
[i
].isreg
= 1;
7028 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7029 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7030 case OP_oROR
: val
= parse_ror (&str
); break;
7031 case OP_COND
: val
= parse_cond (&str
); break;
7032 case OP_oBARRIER_I15
:
7033 po_barrier_or_imm (str
); break;
7035 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7041 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7042 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7044 inst
.error
= _("Banked registers are not available with this "
7050 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7054 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7057 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7059 if (strncasecmp (str
, "APSR_", 5) == 0)
7066 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7067 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7068 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7069 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7070 default: found
= 16;
7074 inst
.operands
[i
].isvec
= 1;
7075 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7076 inst
.operands
[i
].reg
= REG_PC
;
7083 po_misc_or_fail (parse_tb (&str
));
7086 /* Register lists. */
7088 val
= parse_reg_list (&str
);
7091 inst
.operands
[i
].writeback
= 1;
7097 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7101 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7105 /* Allow Q registers too. */
7106 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7111 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7113 inst
.operands
[i
].issingle
= 1;
7118 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7123 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7124 &inst
.operands
[i
].vectype
);
7127 /* Addressing modes */
7129 po_misc_or_fail (parse_address (&str
, i
));
7133 po_misc_or_fail_no_backtrack (
7134 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7138 po_misc_or_fail_no_backtrack (
7139 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7143 po_misc_or_fail_no_backtrack (
7144 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7148 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7152 po_misc_or_fail_no_backtrack (
7153 parse_shifter_operand_group_reloc (&str
, i
));
7157 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7161 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7165 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7169 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7172 /* Various value-based sanity checks and shared operations. We
7173 do not signal immediate failures for the register constraints;
7174 this allows a syntax error to take precedence. */
7175 switch (op_parse_code
)
7183 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7184 inst
.error
= BAD_PC
;
7189 if (inst
.operands
[i
].isreg
)
7191 if (inst
.operands
[i
].reg
== REG_PC
)
7192 inst
.error
= BAD_PC
;
7193 else if (inst
.operands
[i
].reg
== REG_SP
7194 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7195 relaxed since ARMv8-A. */
7196 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7199 inst
.error
= BAD_SP
;
7205 if (inst
.operands
[i
].isreg
7206 && inst
.operands
[i
].reg
== REG_PC
7207 && (inst
.operands
[i
].writeback
|| thumb
))
7208 inst
.error
= BAD_PC
;
7217 case OP_oBARRIER_I15
:
7226 inst
.operands
[i
].imm
= val
;
7233 /* If we get here, this operand was successfully parsed. */
7234 inst
.operands
[i
].present
= 1;
7238 inst
.error
= BAD_ARGS
;
7243 /* The parse routine should already have set inst.error, but set a
7244 default here just in case. */
7246 inst
.error
= _("syntax error");
7250 /* Do not backtrack over a trailing optional argument that
7251 absorbed some text. We will only fail again, with the
7252 'garbage following instruction' error message, which is
7253 probably less helpful than the current one. */
7254 if (backtrack_index
== i
&& backtrack_pos
!= str
7255 && upat
[i
+1] == OP_stop
)
7258 inst
.error
= _("syntax error");
7262 /* Try again, skipping the optional argument at backtrack_pos. */
7263 str
= backtrack_pos
;
7264 inst
.error
= backtrack_error
;
7265 inst
.operands
[backtrack_index
].present
= 0;
7266 i
= backtrack_index
;
7270 /* Check that we have parsed all the arguments. */
7271 if (*str
!= '\0' && !inst
.error
)
7272 inst
.error
= _("garbage following instruction");
7274 return inst
.error
? FAIL
: SUCCESS
;
7277 #undef po_char_or_fail
7278 #undef po_reg_or_fail
7279 #undef po_reg_or_goto
7280 #undef po_imm_or_fail
7281 #undef po_scalar_or_fail
7282 #undef po_barrier_or_imm
7284 /* Shorthand macro for instruction encoding functions issuing errors. */
7285 #define constraint(expr, err) \
7296 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7297 instructions are unpredictable if these registers are used. This
7298 is the BadReg predicate in ARM's Thumb-2 documentation.
7300 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7301 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7302 #define reject_bad_reg(reg) \
7304 if (reg == REG_PC) \
7306 inst.error = BAD_PC; \
7309 else if (reg == REG_SP \
7310 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7312 inst.error = BAD_SP; \
7317 /* If REG is R13 (the stack pointer), warn that its use is
7319 #define warn_deprecated_sp(reg) \
7321 if (warn_on_deprecated && reg == REG_SP) \
7322 as_tsktsk (_("use of r13 is deprecated")); \
7325 /* Functions for operand encoding. ARM, then Thumb. */
7327 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7329 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7331 The only binary encoding difference is the Coprocessor number. Coprocessor
7332 9 is used for half-precision calculations or conversions. The format of the
7333 instruction is the same as the equivalent Coprocessor 10 instruction that
7334 exists for Single-Precision operation. */
7337 do_scalar_fp16_v82_encode (void)
7339 if (inst
.cond
!= COND_ALWAYS
)
7340 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7341 " the behaviour is UNPREDICTABLE"));
7342 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7345 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7346 mark_feature_used (&arm_ext_fp16
);
7349 /* If VAL can be encoded in the immediate field of an ARM instruction,
7350 return the encoded form. Otherwise, return FAIL. */
7353 encode_arm_immediate (unsigned int val
)
7360 for (i
= 2; i
< 32; i
+= 2)
7361 if ((a
= rotate_left (val
, i
)) <= 0xff)
7362 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7367 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7368 return the encoded form. Otherwise, return FAIL. */
7370 encode_thumb32_immediate (unsigned int val
)
7377 for (i
= 1; i
<= 24; i
++)
7380 if ((val
& ~(0xff << i
)) == 0)
7381 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7385 if (val
== ((a
<< 16) | a
))
7387 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7391 if (val
== ((a
<< 16) | a
))
7392 return 0x200 | (a
>> 8);
7396 /* Encode a VFP SP or DP register number into inst.instruction. */
7399 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7401 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7407 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7410 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7415 first_error (_("D register out of range for selected VFP version"));
7423 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7427 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7431 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7435 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7439 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7443 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7451 /* Encode a <shift> in an ARM-format instruction. The immediate,
7452 if any, is handled by md_apply_fix. */
7454 encode_arm_shift (int i
)
7456 /* register-shifted register. */
7457 if (inst
.operands
[i
].immisreg
)
7460 for (op_index
= 0; op_index
<= i
; ++op_index
)
7462 /* Check the operand only when it's presented. In pre-UAL syntax,
7463 if the destination register is the same as the first operand, two
7464 register form of the instruction can be used. */
7465 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7466 && inst
.operands
[op_index
].reg
== REG_PC
)
7467 as_warn (UNPRED_REG ("r15"));
7470 if (inst
.operands
[i
].imm
== REG_PC
)
7471 as_warn (UNPRED_REG ("r15"));
7474 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7475 inst
.instruction
|= SHIFT_ROR
<< 5;
7478 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7479 if (inst
.operands
[i
].immisreg
)
7481 inst
.instruction
|= SHIFT_BY_REG
;
7482 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7485 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7490 encode_arm_shifter_operand (int i
)
7492 if (inst
.operands
[i
].isreg
)
7494 inst
.instruction
|= inst
.operands
[i
].reg
;
7495 encode_arm_shift (i
);
7499 inst
.instruction
|= INST_IMMEDIATE
;
7500 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7501 inst
.instruction
|= inst
.operands
[i
].imm
;
7505 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7507 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7510 Generate an error if the operand is not a register. */
7511 constraint (!inst
.operands
[i
].isreg
,
7512 _("Instruction does not support =N addresses"));
7514 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7516 if (inst
.operands
[i
].preind
)
7520 inst
.error
= _("instruction does not accept preindexed addressing");
7523 inst
.instruction
|= PRE_INDEX
;
7524 if (inst
.operands
[i
].writeback
)
7525 inst
.instruction
|= WRITE_BACK
;
7528 else if (inst
.operands
[i
].postind
)
7530 gas_assert (inst
.operands
[i
].writeback
);
7532 inst
.instruction
|= WRITE_BACK
;
7534 else /* unindexed - only for coprocessor */
7536 inst
.error
= _("instruction does not accept unindexed addressing");
7540 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7541 && (((inst
.instruction
& 0x000f0000) >> 16)
7542 == ((inst
.instruction
& 0x0000f000) >> 12)))
7543 as_warn ((inst
.instruction
& LOAD_BIT
)
7544 ? _("destination register same as write-back base")
7545 : _("source register same as write-back base"));
7548 /* inst.operands[i] was set up by parse_address. Encode it into an
7549 ARM-format mode 2 load or store instruction. If is_t is true,
7550 reject forms that cannot be used with a T instruction (i.e. not
7553 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7555 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7557 encode_arm_addr_mode_common (i
, is_t
);
7559 if (inst
.operands
[i
].immisreg
)
7561 constraint ((inst
.operands
[i
].imm
== REG_PC
7562 || (is_pc
&& inst
.operands
[i
].writeback
)),
7564 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7565 inst
.instruction
|= inst
.operands
[i
].imm
;
7566 if (!inst
.operands
[i
].negative
)
7567 inst
.instruction
|= INDEX_UP
;
7568 if (inst
.operands
[i
].shifted
)
7570 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7571 inst
.instruction
|= SHIFT_ROR
<< 5;
7574 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7575 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7579 else /* immediate offset in inst.reloc */
7581 if (is_pc
&& !inst
.reloc
.pc_rel
)
7583 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7585 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7586 cannot use PC in addressing.
7587 PC cannot be used in writeback addressing, either. */
7588 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7591 /* Use of PC in str is deprecated for ARMv7. */
7592 if (warn_on_deprecated
7594 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7595 as_tsktsk (_("use of PC in this instruction is deprecated"));
7598 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7600 /* Prefer + for zero encoded value. */
7601 if (!inst
.operands
[i
].negative
)
7602 inst
.instruction
|= INDEX_UP
;
7603 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7608 /* inst.operands[i] was set up by parse_address. Encode it into an
7609 ARM-format mode 3 load or store instruction. Reject forms that
7610 cannot be used with such instructions. If is_t is true, reject
7611 forms that cannot be used with a T instruction (i.e. not
7614 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7616 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7618 inst
.error
= _("instruction does not accept scaled register index");
7622 encode_arm_addr_mode_common (i
, is_t
);
7624 if (inst
.operands
[i
].immisreg
)
7626 constraint ((inst
.operands
[i
].imm
== REG_PC
7627 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7629 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7631 inst
.instruction
|= inst
.operands
[i
].imm
;
7632 if (!inst
.operands
[i
].negative
)
7633 inst
.instruction
|= INDEX_UP
;
7635 else /* immediate offset in inst.reloc */
7637 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7638 && inst
.operands
[i
].writeback
),
7640 inst
.instruction
|= HWOFFSET_IMM
;
7641 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7643 /* Prefer + for zero encoded value. */
7644 if (!inst
.operands
[i
].negative
)
7645 inst
.instruction
|= INDEX_UP
;
7647 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7652 /* Write immediate bits [7:0] to the following locations:
7654 |28/24|23 19|18 16|15 4|3 0|
7655 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7657 This function is used by VMOV/VMVN/VORR/VBIC. */
7660 neon_write_immbits (unsigned immbits
)
7662 inst
.instruction
|= immbits
& 0xf;
7663 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7664 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7667 /* Invert low-order SIZE bits of XHI:XLO. */
7670 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7672 unsigned immlo
= xlo
? *xlo
: 0;
7673 unsigned immhi
= xhi
? *xhi
: 0;
7678 immlo
= (~immlo
) & 0xff;
7682 immlo
= (~immlo
) & 0xffff;
7686 immhi
= (~immhi
) & 0xffffffff;
7690 immlo
= (~immlo
) & 0xffffffff;
7704 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7708 neon_bits_same_in_bytes (unsigned imm
)
7710 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7711 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7712 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7713 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7716 /* For immediate of above form, return 0bABCD. */
7719 neon_squash_bits (unsigned imm
)
7721 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7722 | ((imm
& 0x01000000) >> 21);
7725 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7728 neon_qfloat_bits (unsigned imm
)
7730 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7733 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7734 the instruction. *OP is passed as the initial value of the op field, and
7735 may be set to a different value depending on the constant (i.e.
7736 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7737 MVN). If the immediate looks like a repeated pattern then also
7738 try smaller element sizes. */
7741 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7742 unsigned *immbits
, int *op
, int size
,
7743 enum neon_el_type type
)
7745 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7747 if (type
== NT_float
&& !float_p
)
7750 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7752 if (size
!= 32 || *op
== 1)
7754 *immbits
= neon_qfloat_bits (immlo
);
7760 if (neon_bits_same_in_bytes (immhi
)
7761 && neon_bits_same_in_bytes (immlo
))
7765 *immbits
= (neon_squash_bits (immhi
) << 4)
7766 | neon_squash_bits (immlo
);
7777 if (immlo
== (immlo
& 0x000000ff))
7782 else if (immlo
== (immlo
& 0x0000ff00))
7784 *immbits
= immlo
>> 8;
7787 else if (immlo
== (immlo
& 0x00ff0000))
7789 *immbits
= immlo
>> 16;
7792 else if (immlo
== (immlo
& 0xff000000))
7794 *immbits
= immlo
>> 24;
7797 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7799 *immbits
= (immlo
>> 8) & 0xff;
7802 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7804 *immbits
= (immlo
>> 16) & 0xff;
7808 if ((immlo
& 0xffff) != (immlo
>> 16))
7815 if (immlo
== (immlo
& 0x000000ff))
7820 else if (immlo
== (immlo
& 0x0000ff00))
7822 *immbits
= immlo
>> 8;
7826 if ((immlo
& 0xff) != (immlo
>> 8))
7831 if (immlo
== (immlo
& 0x000000ff))
7833 /* Don't allow MVN with 8-bit immediate. */
7843 #if defined BFD_HOST_64_BIT
7844 /* Returns TRUE if double precision value V may be cast
7845 to single precision without loss of accuracy. */
7848 is_double_a_single (bfd_int64_t v
)
7850 int exp
= (int)((v
>> 52) & 0x7FF);
7851 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7853 return (exp
== 0 || exp
== 0x7FF
7854 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7855 && (mantissa
& 0x1FFFFFFFl
) == 0;
7858 /* Returns a double precision value casted to single precision
7859 (ignoring the least significant bits in exponent and mantissa). */
7862 double_to_single (bfd_int64_t v
)
7864 int sign
= (int) ((v
>> 63) & 1l);
7865 int exp
= (int) ((v
>> 52) & 0x7FF);
7866 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7872 exp
= exp
- 1023 + 127;
7881 /* No denormalized numbers. */
7887 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7889 #endif /* BFD_HOST_64_BIT */
7898 static void do_vfp_nsyn_opcode (const char *);
7900 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7901 Determine whether it can be performed with a move instruction; if
7902 it can, convert inst.instruction to that move instruction and
7903 return TRUE; if it can't, convert inst.instruction to a literal-pool
7904 load and return FALSE. If this is not a valid thing to do in the
7905 current context, set inst.error and return TRUE.
7907 inst.operands[i] describes the destination register. */
7910 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7913 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7914 bfd_boolean arm_p
= (t
== CONST_ARM
);
7917 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7921 if ((inst
.instruction
& tbit
) == 0)
7923 inst
.error
= _("invalid pseudo operation");
7927 if (inst
.reloc
.exp
.X_op
!= O_constant
7928 && inst
.reloc
.exp
.X_op
!= O_symbol
7929 && inst
.reloc
.exp
.X_op
!= O_big
)
7931 inst
.error
= _("constant expression expected");
7935 if (inst
.reloc
.exp
.X_op
== O_constant
7936 || inst
.reloc
.exp
.X_op
== O_big
)
7938 #if defined BFD_HOST_64_BIT
7943 if (inst
.reloc
.exp
.X_op
== O_big
)
7945 LITTLENUM_TYPE w
[X_PRECISION
];
7948 if (inst
.reloc
.exp
.X_add_number
== -1)
7950 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7952 /* FIXME: Should we check words w[2..5] ? */
7957 #if defined BFD_HOST_64_BIT
7959 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7960 << LITTLENUM_NUMBER_OF_BITS
)
7961 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7962 << LITTLENUM_NUMBER_OF_BITS
)
7963 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7964 << LITTLENUM_NUMBER_OF_BITS
)
7965 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7967 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7968 | (l
[0] & LITTLENUM_MASK
);
7972 v
= inst
.reloc
.exp
.X_add_number
;
7974 if (!inst
.operands
[i
].issingle
)
7978 /* LDR should not use lead in a flag-setting instruction being
7979 chosen so we do not check whether movs can be used. */
7981 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7982 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7983 && inst
.operands
[i
].reg
!= 13
7984 && inst
.operands
[i
].reg
!= 15)
7986 /* Check if on thumb2 it can be done with a mov.w, mvn or
7987 movw instruction. */
7988 unsigned int newimm
;
7989 bfd_boolean isNegated
;
7991 newimm
= encode_thumb32_immediate (v
);
7992 if (newimm
!= (unsigned int) FAIL
)
7996 newimm
= encode_thumb32_immediate (~v
);
7997 if (newimm
!= (unsigned int) FAIL
)
8001 /* The number can be loaded with a mov.w or mvn
8003 if (newimm
!= (unsigned int) FAIL
8004 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8006 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8007 | (inst
.operands
[i
].reg
<< 8));
8008 /* Change to MOVN. */
8009 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8010 inst
.instruction
|= (newimm
& 0x800) << 15;
8011 inst
.instruction
|= (newimm
& 0x700) << 4;
8012 inst
.instruction
|= (newimm
& 0x0ff);
8015 /* The number can be loaded with a movw instruction. */
8016 else if ((v
& ~0xFFFF) == 0
8017 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8019 int imm
= v
& 0xFFFF;
8021 inst
.instruction
= 0xf2400000; /* MOVW. */
8022 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8023 inst
.instruction
|= (imm
& 0xf000) << 4;
8024 inst
.instruction
|= (imm
& 0x0800) << 15;
8025 inst
.instruction
|= (imm
& 0x0700) << 4;
8026 inst
.instruction
|= (imm
& 0x00ff);
8033 int value
= encode_arm_immediate (v
);
8037 /* This can be done with a mov instruction. */
8038 inst
.instruction
&= LITERAL_MASK
;
8039 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8040 inst
.instruction
|= value
& 0xfff;
8044 value
= encode_arm_immediate (~ v
);
8047 /* This can be done with a mvn instruction. */
8048 inst
.instruction
&= LITERAL_MASK
;
8049 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8050 inst
.instruction
|= value
& 0xfff;
8054 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8057 unsigned immbits
= 0;
8058 unsigned immlo
= inst
.operands
[1].imm
;
8059 unsigned immhi
= inst
.operands
[1].regisimm
8060 ? inst
.operands
[1].reg
8061 : inst
.reloc
.exp
.X_unsigned
8063 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8064 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8065 &op
, 64, NT_invtype
);
8069 neon_invert_size (&immlo
, &immhi
, 64);
8071 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8072 &op
, 64, NT_invtype
);
8077 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8083 /* Fill other bits in vmov encoding for both thumb and arm. */
8085 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8087 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8088 neon_write_immbits (immbits
);
8096 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8097 if (inst
.operands
[i
].issingle
8098 && is_quarter_float (inst
.operands
[1].imm
)
8099 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8101 inst
.operands
[1].imm
=
8102 neon_qfloat_bits (v
);
8103 do_vfp_nsyn_opcode ("fconsts");
8107 /* If our host does not support a 64-bit type then we cannot perform
8108 the following optimization. This mean that there will be a
8109 discrepancy between the output produced by an assembler built for
8110 a 32-bit-only host and the output produced from a 64-bit host, but
8111 this cannot be helped. */
8112 #if defined BFD_HOST_64_BIT
8113 else if (!inst
.operands
[1].issingle
8114 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8116 if (is_double_a_single (v
)
8117 && is_quarter_float (double_to_single (v
)))
8119 inst
.operands
[1].imm
=
8120 neon_qfloat_bits (double_to_single (v
));
8121 do_vfp_nsyn_opcode ("fconstd");
8129 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8130 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8133 inst
.operands
[1].reg
= REG_PC
;
8134 inst
.operands
[1].isreg
= 1;
8135 inst
.operands
[1].preind
= 1;
8136 inst
.reloc
.pc_rel
= 1;
8137 inst
.reloc
.type
= (thumb_p
8138 ? BFD_RELOC_ARM_THUMB_OFFSET
8140 ? BFD_RELOC_ARM_HWLITERAL
8141 : BFD_RELOC_ARM_LITERAL
));
8145 /* inst.operands[i] was set up by parse_address. Encode it into an
8146 ARM-format instruction. Reject all forms which cannot be encoded
8147 into a coprocessor load/store instruction. If wb_ok is false,
8148 reject use of writeback; if unind_ok is false, reject use of
8149 unindexed addressing. If reloc_override is not 0, use it instead
8150 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8151 (in which case it is preserved). */
8154 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8156 if (!inst
.operands
[i
].isreg
)
8159 if (! inst
.operands
[0].isvec
)
8161 inst
.error
= _("invalid co-processor operand");
8164 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8168 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8170 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8172 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8174 gas_assert (!inst
.operands
[i
].writeback
);
8177 inst
.error
= _("instruction does not support unindexed addressing");
8180 inst
.instruction
|= inst
.operands
[i
].imm
;
8181 inst
.instruction
|= INDEX_UP
;
8185 if (inst
.operands
[i
].preind
)
8186 inst
.instruction
|= PRE_INDEX
;
8188 if (inst
.operands
[i
].writeback
)
8190 if (inst
.operands
[i
].reg
== REG_PC
)
8192 inst
.error
= _("pc may not be used with write-back");
8197 inst
.error
= _("instruction does not support writeback");
8200 inst
.instruction
|= WRITE_BACK
;
8204 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8205 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8206 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8207 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8210 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8212 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8215 /* Prefer + for zero encoded value. */
8216 if (!inst
.operands
[i
].negative
)
8217 inst
.instruction
|= INDEX_UP
;
8222 /* Functions for instruction encoding, sorted by sub-architecture.
8223 First some generics; their names are taken from the conventional
8224 bit positions for register arguments in ARM format instructions. */
8234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8240 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8247 inst
.instruction
|= inst
.operands
[1].reg
;
8253 inst
.instruction
|= inst
.operands
[0].reg
;
8254 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8260 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8261 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8267 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8268 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8274 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8275 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8279 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8281 if (ARM_CPU_IS_ANY (cpu_variant
))
8283 as_tsktsk ("%s", msg
);
8286 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8298 unsigned Rn
= inst
.operands
[2].reg
;
8299 /* Enforce restrictions on SWP instruction. */
8300 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8302 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8303 _("Rn must not overlap other operands"));
8305 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8307 if (!check_obsolete (&arm_ext_v8
,
8308 _("swp{b} use is obsoleted for ARMv8 and later"))
8309 && warn_on_deprecated
8310 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8311 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8315 inst
.instruction
|= inst
.operands
[1].reg
;
8316 inst
.instruction
|= Rn
<< 16;
8322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8323 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8324 inst
.instruction
|= inst
.operands
[2].reg
;
8330 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8331 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8332 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8333 || inst
.reloc
.exp
.X_add_number
!= 0),
8335 inst
.instruction
|= inst
.operands
[0].reg
;
8336 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8337 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8343 inst
.instruction
|= inst
.operands
[0].imm
;
8349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8350 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8353 /* ARM instructions, in alphabetical order by function name (except
8354 that wrapper functions appear immediately after the function they
8357 /* This is a pseudo-op of the form "adr rd, label" to be converted
8358 into a relative address of the form "add rd, pc, #label-.-8". */
8363 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8365 /* Frag hacking will turn this into a sub instruction if the offset turns
8366 out to be negative. */
8367 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8368 inst
.reloc
.pc_rel
= 1;
8369 inst
.reloc
.exp
.X_add_number
-= 8;
8371 if (inst
.reloc
.exp
.X_op
== O_symbol
8372 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8373 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8374 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8375 inst
.reloc
.exp
.X_add_number
+= 1;
8378 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8379 into a relative address of the form:
8380 add rd, pc, #low(label-.-8)"
8381 add rd, rd, #high(label-.-8)" */
8386 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8388 /* Frag hacking will turn this into a sub instruction if the offset turns
8389 out to be negative. */
8390 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8391 inst
.reloc
.pc_rel
= 1;
8392 inst
.size
= INSN_SIZE
* 2;
8393 inst
.reloc
.exp
.X_add_number
-= 8;
8395 if (inst
.reloc
.exp
.X_op
== O_symbol
8396 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8397 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8398 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8399 inst
.reloc
.exp
.X_add_number
+= 1;
8405 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8406 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8408 if (!inst
.operands
[1].present
)
8409 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8411 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8412 encode_arm_shifter_operand (2);
8418 if (inst
.operands
[0].present
)
8419 inst
.instruction
|= inst
.operands
[0].imm
;
8421 inst
.instruction
|= 0xf;
8427 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8428 constraint (msb
> 32, _("bit-field extends past end of register"));
8429 /* The instruction encoding stores the LSB and MSB,
8430 not the LSB and width. */
8431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8432 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8433 inst
.instruction
|= (msb
- 1) << 16;
8441 /* #0 in second position is alternative syntax for bfc, which is
8442 the same instruction but with REG_PC in the Rm field. */
8443 if (!inst
.operands
[1].isreg
)
8444 inst
.operands
[1].reg
= REG_PC
;
8446 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8447 constraint (msb
> 32, _("bit-field extends past end of register"));
8448 /* The instruction encoding stores the LSB and MSB,
8449 not the LSB and width. */
8450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8451 inst
.instruction
|= inst
.operands
[1].reg
;
8452 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8453 inst
.instruction
|= (msb
- 1) << 16;
8459 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8460 _("bit-field extends past end of register"));
8461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[1].reg
;
8463 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8464 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8467 /* ARM V5 breakpoint instruction (argument parse)
8468 BKPT <16 bit unsigned immediate>
8469 Instruction is not conditional.
8470 The bit pattern given in insns[] has the COND_ALWAYS condition,
8471 and it is an error if the caller tried to override that. */
8476 /* Top 12 of 16 bits to bits 19:8. */
8477 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8479 /* Bottom 4 of 16 bits to bits 3:0. */
8480 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8484 encode_branch (int default_reloc
)
8486 if (inst
.operands
[0].hasreloc
)
8488 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8489 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8490 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8491 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8492 ? BFD_RELOC_ARM_PLT32
8493 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8496 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8497 inst
.reloc
.pc_rel
= 1;
8504 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8505 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8508 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8515 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8517 if (inst
.cond
== COND_ALWAYS
)
8518 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8520 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8524 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8527 /* ARM V5 branch-link-exchange instruction (argument parse)
8528 BLX <target_addr> ie BLX(1)
8529 BLX{<condition>} <Rm> ie BLX(2)
8530 Unfortunately, there are two different opcodes for this mnemonic.
8531 So, the insns[].value is not used, and the code here zaps values
8532 into inst.instruction.
8533 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8538 if (inst
.operands
[0].isreg
)
8540 /* Arg is a register; the opcode provided by insns[] is correct.
8541 It is not illegal to do "blx pc", just useless. */
8542 if (inst
.operands
[0].reg
== REG_PC
)
8543 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8545 inst
.instruction
|= inst
.operands
[0].reg
;
8549 /* Arg is an address; this instruction cannot be executed
8550 conditionally, and the opcode must be adjusted.
8551 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8552 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8553 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8554 inst
.instruction
= 0xfa000000;
8555 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8562 bfd_boolean want_reloc
;
8564 if (inst
.operands
[0].reg
== REG_PC
)
8565 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8567 inst
.instruction
|= inst
.operands
[0].reg
;
8568 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8569 it is for ARMv4t or earlier. */
8570 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8571 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8575 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8580 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8584 /* ARM v5TEJ. Jump to Jazelle code. */
8589 if (inst
.operands
[0].reg
== REG_PC
)
8590 as_tsktsk (_("use of r15 in bxj is not really useful"));
8592 inst
.instruction
|= inst
.operands
[0].reg
;
8595 /* Co-processor data operation:
8596 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8597 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8601 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8602 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8603 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8604 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8605 inst
.instruction
|= inst
.operands
[4].reg
;
8606 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8612 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8613 encode_arm_shifter_operand (1);
8616 /* Transfer between coprocessor and ARM registers.
8617 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8622 No special properties. */
8624 struct deprecated_coproc_regs_s
8631 arm_feature_set deprecated
;
8632 arm_feature_set obsoleted
;
8633 const char *dep_msg
;
8634 const char *obs_msg
;
8637 #define DEPR_ACCESS_V8 \
8638 N_("This coprocessor register access is deprecated in ARMv8")
8640 /* Table of all deprecated coprocessor registers. */
8641 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8643 {15, 0, 7, 10, 5, /* CP15DMB. */
8644 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8645 DEPR_ACCESS_V8
, NULL
},
8646 {15, 0, 7, 10, 4, /* CP15DSB. */
8647 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8648 DEPR_ACCESS_V8
, NULL
},
8649 {15, 0, 7, 5, 4, /* CP15ISB. */
8650 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8651 DEPR_ACCESS_V8
, NULL
},
8652 {14, 6, 1, 0, 0, /* TEEHBR. */
8653 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8654 DEPR_ACCESS_V8
, NULL
},
8655 {14, 6, 0, 0, 0, /* TEECR. */
8656 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8657 DEPR_ACCESS_V8
, NULL
},
8660 #undef DEPR_ACCESS_V8
8662 static const size_t deprecated_coproc_reg_count
=
8663 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8671 Rd
= inst
.operands
[2].reg
;
8674 if (inst
.instruction
== 0xee000010
8675 || inst
.instruction
== 0xfe000010)
8677 reject_bad_reg (Rd
);
8678 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8680 constraint (Rd
== REG_SP
, BAD_SP
);
8685 if (inst
.instruction
== 0xe000010)
8686 constraint (Rd
== REG_PC
, BAD_PC
);
8689 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8691 const struct deprecated_coproc_regs_s
*r
=
8692 deprecated_coproc_regs
+ i
;
8694 if (inst
.operands
[0].reg
== r
->cp
8695 && inst
.operands
[1].imm
== r
->opc1
8696 && inst
.operands
[3].reg
== r
->crn
8697 && inst
.operands
[4].reg
== r
->crm
8698 && inst
.operands
[5].imm
== r
->opc2
)
8700 if (! ARM_CPU_IS_ANY (cpu_variant
)
8701 && warn_on_deprecated
8702 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8703 as_tsktsk ("%s", r
->dep_msg
);
8707 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8708 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8709 inst
.instruction
|= Rd
<< 12;
8710 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8711 inst
.instruction
|= inst
.operands
[4].reg
;
8712 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8715 /* Transfer between coprocessor register and pair of ARM registers.
8716 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8721 Two XScale instructions are special cases of these:
8723 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8724 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8726 Result unpredictable if Rd or Rn is R15. */
8733 Rd
= inst
.operands
[2].reg
;
8734 Rn
= inst
.operands
[3].reg
;
8738 reject_bad_reg (Rd
);
8739 reject_bad_reg (Rn
);
8743 constraint (Rd
== REG_PC
, BAD_PC
);
8744 constraint (Rn
== REG_PC
, BAD_PC
);
8747 /* Only check the MRRC{2} variants. */
8748 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8750 /* If Rd == Rn, error that the operation is
8751 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8752 constraint (Rd
== Rn
, BAD_OVERLAP
);
8755 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8756 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8757 inst
.instruction
|= Rd
<< 12;
8758 inst
.instruction
|= Rn
<< 16;
8759 inst
.instruction
|= inst
.operands
[4].reg
;
8765 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8766 if (inst
.operands
[1].present
)
8768 inst
.instruction
|= CPSI_MMOD
;
8769 inst
.instruction
|= inst
.operands
[1].imm
;
8776 inst
.instruction
|= inst
.operands
[0].imm
;
8782 unsigned Rd
, Rn
, Rm
;
8784 Rd
= inst
.operands
[0].reg
;
8785 Rn
= (inst
.operands
[1].present
8786 ? inst
.operands
[1].reg
: Rd
);
8787 Rm
= inst
.operands
[2].reg
;
8789 constraint ((Rd
== REG_PC
), BAD_PC
);
8790 constraint ((Rn
== REG_PC
), BAD_PC
);
8791 constraint ((Rm
== REG_PC
), BAD_PC
);
8793 inst
.instruction
|= Rd
<< 16;
8794 inst
.instruction
|= Rn
<< 0;
8795 inst
.instruction
|= Rm
<< 8;
8801 /* There is no IT instruction in ARM mode. We
8802 process it to do the validation as if in
8803 thumb mode, just in case the code gets
8804 assembled for thumb using the unified syntax. */
8809 set_it_insn_type (IT_INSN
);
8810 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8811 now_it
.cc
= inst
.operands
[0].imm
;
8815 /* If there is only one register in the register list,
8816 then return its register number. Otherwise return -1. */
8818 only_one_reg_in_list (int range
)
8820 int i
= ffs (range
) - 1;
8821 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8825 encode_ldmstm(int from_push_pop_mnem
)
8827 int base_reg
= inst
.operands
[0].reg
;
8828 int range
= inst
.operands
[1].imm
;
8831 inst
.instruction
|= base_reg
<< 16;
8832 inst
.instruction
|= range
;
8834 if (inst
.operands
[1].writeback
)
8835 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8837 if (inst
.operands
[0].writeback
)
8839 inst
.instruction
|= WRITE_BACK
;
8840 /* Check for unpredictable uses of writeback. */
8841 if (inst
.instruction
& LOAD_BIT
)
8843 /* Not allowed in LDM type 2. */
8844 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8845 && ((range
& (1 << REG_PC
)) == 0))
8846 as_warn (_("writeback of base register is UNPREDICTABLE"));
8847 /* Only allowed if base reg not in list for other types. */
8848 else if (range
& (1 << base_reg
))
8849 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8853 /* Not allowed for type 2. */
8854 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8855 as_warn (_("writeback of base register is UNPREDICTABLE"));
8856 /* Only allowed if base reg not in list, or first in list. */
8857 else if ((range
& (1 << base_reg
))
8858 && (range
& ((1 << base_reg
) - 1)))
8859 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8863 /* If PUSH/POP has only one register, then use the A2 encoding. */
8864 one_reg
= only_one_reg_in_list (range
);
8865 if (from_push_pop_mnem
&& one_reg
>= 0)
8867 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8869 inst
.instruction
&= A_COND_MASK
;
8870 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8871 inst
.instruction
|= one_reg
<< 12;
8878 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8881 /* ARMv5TE load-consecutive (argument parse)
8890 constraint (inst
.operands
[0].reg
% 2 != 0,
8891 _("first transfer register must be even"));
8892 constraint (inst
.operands
[1].present
8893 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8894 _("can only transfer two consecutive registers"));
8895 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8896 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8898 if (!inst
.operands
[1].present
)
8899 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8901 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8902 register and the first register written; we have to diagnose
8903 overlap between the base and the second register written here. */
8905 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8906 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8907 as_warn (_("base register written back, and overlaps "
8908 "second transfer register"));
8910 if (!(inst
.instruction
& V4_STR_BIT
))
8912 /* For an index-register load, the index register must not overlap the
8913 destination (even if not write-back). */
8914 if (inst
.operands
[2].immisreg
8915 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8916 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8917 as_warn (_("index register overlaps transfer register"));
8919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8920 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8926 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8927 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8928 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8929 || inst
.operands
[1].negative
8930 /* This can arise if the programmer has written
8932 or if they have mistakenly used a register name as the last
8935 It is very difficult to distinguish between these two cases
8936 because "rX" might actually be a label. ie the register
8937 name has been occluded by a symbol of the same name. So we
8938 just generate a general 'bad addressing mode' type error
8939 message and leave it up to the programmer to discover the
8940 true cause and fix their mistake. */
8941 || (inst
.operands
[1].reg
== REG_PC
),
8944 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8945 || inst
.reloc
.exp
.X_add_number
!= 0,
8946 _("offset must be zero in ARM encoding"));
8948 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8952 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8958 constraint (inst
.operands
[0].reg
% 2 != 0,
8959 _("even register required"));
8960 constraint (inst
.operands
[1].present
8961 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8962 _("can only load two consecutive registers"));
8963 /* If op 1 were present and equal to PC, this function wouldn't
8964 have been called in the first place. */
8965 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8968 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8971 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8972 which is not a multiple of four is UNPREDICTABLE. */
8974 check_ldr_r15_aligned (void)
8976 constraint (!(inst
.operands
[1].immisreg
)
8977 && (inst
.operands
[0].reg
== REG_PC
8978 && inst
.operands
[1].reg
== REG_PC
8979 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8980 _("ldr to register 15 must be 4-byte alligned"));
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 if (!inst
.operands
[1].isreg
)
8988 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8990 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8991 check_ldr_r15_aligned ();
8997 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8999 if (inst
.operands
[1].preind
)
9001 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9002 || inst
.reloc
.exp
.X_add_number
!= 0,
9003 _("this instruction requires a post-indexed address"));
9005 inst
.operands
[1].preind
= 0;
9006 inst
.operands
[1].postind
= 1;
9007 inst
.operands
[1].writeback
= 1;
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9010 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9013 /* Halfword and signed-byte load/store operations. */
9018 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9020 if (!inst
.operands
[1].isreg
)
9021 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9023 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9029 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9031 if (inst
.operands
[1].preind
)
9033 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9034 || inst
.reloc
.exp
.X_add_number
!= 0,
9035 _("this instruction requires a post-indexed address"));
9037 inst
.operands
[1].preind
= 0;
9038 inst
.operands
[1].postind
= 1;
9039 inst
.operands
[1].writeback
= 1;
9041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9042 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9045 /* Co-processor register load/store.
9046 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9050 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9051 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9052 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9058 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9059 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9060 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9061 && !(inst
.instruction
& 0x00400000))
9062 as_tsktsk (_("Rd and Rm should be different in mla"));
9064 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9065 inst
.instruction
|= inst
.operands
[1].reg
;
9066 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9067 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9073 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9074 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9077 encode_arm_shifter_operand (1);
9080 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9087 top
= (inst
.instruction
& 0x00400000) != 0;
9088 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9089 _(":lower16: not allowed in this instruction"));
9090 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9091 _(":upper16: not allowed in this instruction"));
9092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9093 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9095 imm
= inst
.reloc
.exp
.X_add_number
;
9096 /* The value is in two pieces: 0:11, 16:19. */
9097 inst
.instruction
|= (imm
& 0x00000fff);
9098 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9103 do_vfp_nsyn_mrs (void)
9105 if (inst
.operands
[0].isvec
)
9107 if (inst
.operands
[1].reg
!= 1)
9108 first_error (_("operand 1 must be FPSCR"));
9109 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9110 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9111 do_vfp_nsyn_opcode ("fmstat");
9113 else if (inst
.operands
[1].isvec
)
9114 do_vfp_nsyn_opcode ("fmrx");
9122 do_vfp_nsyn_msr (void)
9124 if (inst
.operands
[0].isvec
)
9125 do_vfp_nsyn_opcode ("fmxr");
9135 unsigned Rt
= inst
.operands
[0].reg
;
9137 if (thumb_mode
&& Rt
== REG_SP
)
9139 inst
.error
= BAD_SP
;
9143 /* APSR_ sets isvec. All other refs to PC are illegal. */
9144 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9146 inst
.error
= BAD_PC
;
9150 /* If we get through parsing the register name, we just insert the number
9151 generated into the instruction without further validation. */
9152 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9153 inst
.instruction
|= (Rt
<< 12);
9159 unsigned Rt
= inst
.operands
[1].reg
;
9162 reject_bad_reg (Rt
);
9163 else if (Rt
== REG_PC
)
9165 inst
.error
= BAD_PC
;
9169 /* If we get through parsing the register name, we just insert the number
9170 generated into the instruction without further validation. */
9171 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9172 inst
.instruction
|= (Rt
<< 12);
9180 if (do_vfp_nsyn_mrs () == SUCCESS
)
9183 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9186 if (inst
.operands
[1].isreg
)
9188 br
= inst
.operands
[1].reg
;
9189 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9190 as_bad (_("bad register for mrs"));
9194 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9195 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9197 _("'APSR', 'CPSR' or 'SPSR' expected"));
9198 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9201 inst
.instruction
|= br
;
9204 /* Two possible forms:
9205 "{C|S}PSR_<field>, Rm",
9206 "{C|S}PSR_f, #expression". */
9211 if (do_vfp_nsyn_msr () == SUCCESS
)
9214 inst
.instruction
|= inst
.operands
[0].imm
;
9215 if (inst
.operands
[1].isreg
)
9216 inst
.instruction
|= inst
.operands
[1].reg
;
9219 inst
.instruction
|= INST_IMMEDIATE
;
9220 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9221 inst
.reloc
.pc_rel
= 0;
9228 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9230 if (!inst
.operands
[2].present
)
9231 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9232 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9233 inst
.instruction
|= inst
.operands
[1].reg
;
9234 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9236 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9237 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9238 as_tsktsk (_("Rd and Rm should be different in mul"));
9241 /* Long Multiply Parser
9242 UMULL RdLo, RdHi, Rm, Rs
9243 SMULL RdLo, RdHi, Rm, Rs
9244 UMLAL RdLo, RdHi, Rm, Rs
9245 SMLAL RdLo, RdHi, Rm, Rs. */
9250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9252 inst
.instruction
|= inst
.operands
[2].reg
;
9253 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9255 /* rdhi and rdlo must be different. */
9256 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9257 as_tsktsk (_("rdhi and rdlo must be different"));
9259 /* rdhi, rdlo and rm must all be different before armv6. */
9260 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9261 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9262 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9263 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9269 if (inst
.operands
[0].present
9270 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9272 /* Architectural NOP hints are CPSR sets with no bits selected. */
9273 inst
.instruction
&= 0xf0000000;
9274 inst
.instruction
|= 0x0320f000;
9275 if (inst
.operands
[0].present
)
9276 inst
.instruction
|= inst
.operands
[0].imm
;
9280 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9281 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9282 Condition defaults to COND_ALWAYS.
9283 Error if Rd, Rn or Rm are R15. */
9288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9289 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9290 inst
.instruction
|= inst
.operands
[2].reg
;
9291 if (inst
.operands
[3].present
)
9292 encode_arm_shift (3);
9295 /* ARM V6 PKHTB (Argument Parse). */
9300 if (!inst
.operands
[3].present
)
9302 /* If the shift specifier is omitted, turn the instruction
9303 into pkhbt rd, rm, rn. */
9304 inst
.instruction
&= 0xfff00010;
9305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9306 inst
.instruction
|= inst
.operands
[1].reg
;
9307 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9313 inst
.instruction
|= inst
.operands
[2].reg
;
9314 encode_arm_shift (3);
9318 /* ARMv5TE: Preload-Cache
9319 MP Extensions: Preload for write
9323 Syntactically, like LDR with B=1, W=0, L=1. */
9328 constraint (!inst
.operands
[0].isreg
,
9329 _("'[' expected after PLD mnemonic"));
9330 constraint (inst
.operands
[0].postind
,
9331 _("post-indexed expression used in preload instruction"));
9332 constraint (inst
.operands
[0].writeback
,
9333 _("writeback used in preload instruction"));
9334 constraint (!inst
.operands
[0].preind
,
9335 _("unindexed addressing used in preload instruction"));
9336 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9339 /* ARMv7: PLI <addr_mode> */
9343 constraint (!inst
.operands
[0].isreg
,
9344 _("'[' expected after PLI mnemonic"));
9345 constraint (inst
.operands
[0].postind
,
9346 _("post-indexed expression used in preload instruction"));
9347 constraint (inst
.operands
[0].writeback
,
9348 _("writeback used in preload instruction"));
9349 constraint (!inst
.operands
[0].preind
,
9350 _("unindexed addressing used in preload instruction"));
9351 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9352 inst
.instruction
&= ~PRE_INDEX
;
9358 constraint (inst
.operands
[0].writeback
,
9359 _("push/pop do not support {reglist}^"));
9360 inst
.operands
[1] = inst
.operands
[0];
9361 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9362 inst
.operands
[0].isreg
= 1;
9363 inst
.operands
[0].writeback
= 1;
9364 inst
.operands
[0].reg
= REG_SP
;
9365 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9368 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9369 word at the specified address and the following word
9371 Unconditionally executed.
9372 Error if Rn is R15. */
9377 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9378 if (inst
.operands
[0].writeback
)
9379 inst
.instruction
|= WRITE_BACK
;
9382 /* ARM V6 ssat (argument parse). */
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9388 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9389 inst
.instruction
|= inst
.operands
[2].reg
;
9391 if (inst
.operands
[3].present
)
9392 encode_arm_shift (3);
9395 /* ARM V6 usat (argument parse). */
9400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9401 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9402 inst
.instruction
|= inst
.operands
[2].reg
;
9404 if (inst
.operands
[3].present
)
9405 encode_arm_shift (3);
9408 /* ARM V6 ssat16 (argument parse). */
9413 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9414 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9415 inst
.instruction
|= inst
.operands
[2].reg
;
9421 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9422 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9423 inst
.instruction
|= inst
.operands
[2].reg
;
9426 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9427 preserving the other bits.
9429 setend <endian_specifier>, where <endian_specifier> is either
9435 if (warn_on_deprecated
9436 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9437 as_tsktsk (_("setend use is deprecated for ARMv8"));
9439 if (inst
.operands
[0].imm
)
9440 inst
.instruction
|= 0x200;
9446 unsigned int Rm
= (inst
.operands
[1].present
9447 ? inst
.operands
[1].reg
9448 : inst
.operands
[0].reg
);
9450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9451 inst
.instruction
|= Rm
;
9452 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9454 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9455 inst
.instruction
|= SHIFT_BY_REG
;
9456 /* PR 12854: Error on extraneous shifts. */
9457 constraint (inst
.operands
[2].shifted
,
9458 _("extraneous shift as part of operand to shift insn"));
9461 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9467 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9468 inst
.reloc
.pc_rel
= 0;
9474 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9475 inst
.reloc
.pc_rel
= 0;
9481 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9482 inst
.reloc
.pc_rel
= 0;
9488 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9489 _("selected processor does not support SETPAN instruction"));
9491 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9498 _("selected processor does not support SETPAN instruction"));
9500 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9503 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9504 SMLAxy{cond} Rd,Rm,Rs,Rn
9505 SMLAWy{cond} Rd,Rm,Rs,Rn
9506 Error if any register is R15. */
9511 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9512 inst
.instruction
|= inst
.operands
[1].reg
;
9513 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9514 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9517 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9518 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9519 Error if any register is R15.
9520 Warning if Rdlo == Rdhi. */
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9527 inst
.instruction
|= inst
.operands
[2].reg
;
9528 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9530 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9531 as_tsktsk (_("rdhi and rdlo must be different"));
9534 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9535 SMULxy{cond} Rd,Rm,Rs
9536 Error if any register is R15. */
9541 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9542 inst
.instruction
|= inst
.operands
[1].reg
;
9543 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9546 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9547 the same for both ARM and Thumb-2. */
9554 if (inst
.operands
[0].present
)
9556 reg
= inst
.operands
[0].reg
;
9557 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9562 inst
.instruction
|= reg
<< 16;
9563 inst
.instruction
|= inst
.operands
[1].imm
;
9564 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9565 inst
.instruction
|= WRITE_BACK
;
9568 /* ARM V6 strex (argument parse). */
9573 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9574 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9575 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9576 || inst
.operands
[2].negative
9577 /* See comment in do_ldrex(). */
9578 || (inst
.operands
[2].reg
== REG_PC
),
9581 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9582 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9584 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9585 || inst
.reloc
.exp
.X_add_number
!= 0,
9586 _("offset must be zero in ARM encoding"));
9588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9589 inst
.instruction
|= inst
.operands
[1].reg
;
9590 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9591 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9597 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9598 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9599 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9600 || inst
.operands
[2].negative
,
9603 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9604 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9612 constraint (inst
.operands
[1].reg
% 2 != 0,
9613 _("even register required"));
9614 constraint (inst
.operands
[2].present
9615 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9616 _("can only store two consecutive registers"));
9617 /* If op 2 were present and equal to PC, this function wouldn't
9618 have been called in the first place. */
9619 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9621 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9622 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9623 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9627 inst
.instruction
|= inst
.operands
[1].reg
;
9628 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9635 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9636 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9644 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9645 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9650 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9651 extends it to 32-bits, and adds the result to a value in another
9652 register. You can specify a rotation by 0, 8, 16, or 24 bits
9653 before extracting the 16-bit value.
9654 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9655 Condition defaults to COND_ALWAYS.
9656 Error if any register uses R15. */
9661 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9662 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9663 inst
.instruction
|= inst
.operands
[2].reg
;
9664 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9669 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9670 Condition defaults to COND_ALWAYS.
9671 Error if any register uses R15. */
9676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9677 inst
.instruction
|= inst
.operands
[1].reg
;
9678 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9681 /* VFP instructions. In a logical order: SP variant first, monad
9682 before dyad, arithmetic then move then load/store. */
9685 do_vfp_sp_monadic (void)
9687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9692 do_vfp_sp_dyadic (void)
9694 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9695 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9696 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9700 do_vfp_sp_compare_z (void)
9702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9706 do_vfp_dp_sp_cvt (void)
9708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9709 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9713 do_vfp_sp_dp_cvt (void)
9715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9716 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9720 do_vfp_reg_from_sp (void)
9722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9723 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9727 do_vfp_reg2_from_sp2 (void)
9729 constraint (inst
.operands
[2].imm
!= 2,
9730 _("only two consecutive VFP SP registers allowed here"));
9731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9732 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9733 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9737 do_vfp_sp_from_reg (void)
9739 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9740 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9744 do_vfp_sp2_from_reg2 (void)
9746 constraint (inst
.operands
[0].imm
!= 2,
9747 _("only two consecutive VFP SP registers allowed here"));
9748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9749 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9750 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9754 do_vfp_sp_ldst (void)
9756 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9757 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9761 do_vfp_dp_ldst (void)
9763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9764 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9769 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9771 if (inst
.operands
[0].writeback
)
9772 inst
.instruction
|= WRITE_BACK
;
9774 constraint (ldstm_type
!= VFP_LDSTMIA
,
9775 _("this addressing mode requires base-register writeback"));
9776 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9777 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9778 inst
.instruction
|= inst
.operands
[1].imm
;
9782 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9786 if (inst
.operands
[0].writeback
)
9787 inst
.instruction
|= WRITE_BACK
;
9789 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9790 _("this addressing mode requires base-register writeback"));
9792 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9793 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9795 count
= inst
.operands
[1].imm
<< 1;
9796 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9799 inst
.instruction
|= count
;
9803 do_vfp_sp_ldstmia (void)
9805 vfp_sp_ldstm (VFP_LDSTMIA
);
9809 do_vfp_sp_ldstmdb (void)
9811 vfp_sp_ldstm (VFP_LDSTMDB
);
9815 do_vfp_dp_ldstmia (void)
9817 vfp_dp_ldstm (VFP_LDSTMIA
);
9821 do_vfp_dp_ldstmdb (void)
9823 vfp_dp_ldstm (VFP_LDSTMDB
);
9827 do_vfp_xp_ldstmia (void)
9829 vfp_dp_ldstm (VFP_LDSTMIAX
);
9833 do_vfp_xp_ldstmdb (void)
9835 vfp_dp_ldstm (VFP_LDSTMDBX
);
9839 do_vfp_dp_rd_rm (void)
9841 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9842 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9846 do_vfp_dp_rn_rd (void)
9848 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9849 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9853 do_vfp_dp_rd_rn (void)
9855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9856 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9860 do_vfp_dp_rd_rn_rm (void)
9862 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9863 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9864 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9870 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9874 do_vfp_dp_rm_rd_rn (void)
9876 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9877 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9878 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9881 /* VFPv3 instructions. */
9883 do_vfp_sp_const (void)
9885 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9886 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9887 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9891 do_vfp_dp_const (void)
9893 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9894 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9895 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9899 vfp_conv (int srcsize
)
9901 int immbits
= srcsize
- inst
.operands
[1].imm
;
9903 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9905 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9906 i.e. immbits must be in range 0 - 16. */
9907 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9910 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9912 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9913 i.e. immbits must be in range 0 - 31. */
9914 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9918 inst
.instruction
|= (immbits
& 1) << 5;
9919 inst
.instruction
|= (immbits
>> 1);
9923 do_vfp_sp_conv_16 (void)
9925 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9930 do_vfp_dp_conv_16 (void)
9932 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9937 do_vfp_sp_conv_32 (void)
9939 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9944 do_vfp_dp_conv_32 (void)
9946 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9950 /* FPA instructions. Also in a logical order. */
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9956 inst
.instruction
|= inst
.operands
[1].reg
;
9960 do_fpa_ldmstm (void)
9962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9963 switch (inst
.operands
[1].imm
)
9965 case 1: inst
.instruction
|= CP_T_X
; break;
9966 case 2: inst
.instruction
|= CP_T_Y
; break;
9967 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9972 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9974 /* The instruction specified "ea" or "fd", so we can only accept
9975 [Rn]{!}. The instruction does not really support stacking or
9976 unstacking, so we have to emulate these by setting appropriate
9977 bits and offsets. */
9978 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9979 || inst
.reloc
.exp
.X_add_number
!= 0,
9980 _("this instruction does not support indexing"));
9982 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9983 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9985 if (!(inst
.instruction
& INDEX_UP
))
9986 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9988 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9990 inst
.operands
[2].preind
= 0;
9991 inst
.operands
[2].postind
= 1;
9995 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9998 /* iWMMXt instructions: strictly in alphabetical order. */
10001 do_iwmmxt_tandorc (void)
10003 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10007 do_iwmmxt_textrc (void)
10009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10010 inst
.instruction
|= inst
.operands
[1].imm
;
10014 do_iwmmxt_textrm (void)
10016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10017 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10018 inst
.instruction
|= inst
.operands
[2].imm
;
10022 do_iwmmxt_tinsr (void)
10024 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10025 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10026 inst
.instruction
|= inst
.operands
[2].imm
;
10030 do_iwmmxt_tmia (void)
10032 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10033 inst
.instruction
|= inst
.operands
[1].reg
;
10034 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10038 do_iwmmxt_waligni (void)
10040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10041 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10042 inst
.instruction
|= inst
.operands
[2].reg
;
10043 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10047 do_iwmmxt_wmerge (void)
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10051 inst
.instruction
|= inst
.operands
[2].reg
;
10052 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10056 do_iwmmxt_wmov (void)
10058 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10060 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10061 inst
.instruction
|= inst
.operands
[1].reg
;
10065 do_iwmmxt_wldstbh (void)
10068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10070 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10072 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10073 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10077 do_iwmmxt_wldstw (void)
10079 /* RIWR_RIWC clears .isreg for a control register. */
10080 if (!inst
.operands
[0].isreg
)
10082 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10083 inst
.instruction
|= 0xf0000000;
10086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10087 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10091 do_iwmmxt_wldstd (void)
10093 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10094 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10095 && inst
.operands
[1].immisreg
)
10097 inst
.instruction
&= ~0x1a000ff;
10098 inst
.instruction
|= (0xfU
<< 28);
10099 if (inst
.operands
[1].preind
)
10100 inst
.instruction
|= PRE_INDEX
;
10101 if (!inst
.operands
[1].negative
)
10102 inst
.instruction
|= INDEX_UP
;
10103 if (inst
.operands
[1].writeback
)
10104 inst
.instruction
|= WRITE_BACK
;
10105 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10106 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10107 inst
.instruction
|= inst
.operands
[1].imm
;
10110 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10114 do_iwmmxt_wshufh (void)
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10118 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10119 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10123 do_iwmmxt_wzero (void)
10125 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10126 inst
.instruction
|= inst
.operands
[0].reg
;
10127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10132 do_iwmmxt_wrwrwr_or_imm5 (void)
10134 if (inst
.operands
[2].isreg
)
10137 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10138 _("immediate operand requires iWMMXt2"));
10140 if (inst
.operands
[2].imm
== 0)
10142 switch ((inst
.instruction
>> 20) & 0xf)
10148 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10149 inst
.operands
[2].imm
= 16;
10150 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10156 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10157 inst
.operands
[2].imm
= 32;
10158 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10165 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10167 wrn
= (inst
.instruction
>> 16) & 0xf;
10168 inst
.instruction
&= 0xff0fff0f;
10169 inst
.instruction
|= wrn
;
10170 /* Bail out here; the instruction is now assembled. */
10175 /* Map 32 -> 0, etc. */
10176 inst
.operands
[2].imm
&= 0x1f;
10177 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10181 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10182 operations first, then control, shift, and load/store. */
10184 /* Insns like "foo X,Y,Z". */
10187 do_mav_triple (void)
10189 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10190 inst
.instruction
|= inst
.operands
[1].reg
;
10191 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10194 /* Insns like "foo W,X,Y,Z".
10195 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10200 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10201 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10202 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10203 inst
.instruction
|= inst
.operands
[3].reg
;
10206 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10208 do_mav_dspsc (void)
10210 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10213 /* Maverick shift immediate instructions.
10214 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10215 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10218 do_mav_shift (void)
10220 int imm
= inst
.operands
[2].imm
;
10222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10223 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10225 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10226 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10227 Bit 4 should be 0. */
10228 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10230 inst
.instruction
|= imm
;
10233 /* XScale instructions. Also sorted arithmetic before move. */
10235 /* Xscale multiply-accumulate (argument parse)
10238 MIAxycc acc0,Rm,Rs. */
10243 inst
.instruction
|= inst
.operands
[1].reg
;
10244 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10247 /* Xscale move-accumulator-register (argument parse)
10249 MARcc acc0,RdLo,RdHi. */
10254 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10255 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10258 /* Xscale move-register-accumulator (argument parse)
10260 MRAcc RdLo,RdHi,acc0. */
10265 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10267 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10270 /* Encoding functions relevant only to Thumb. */
10272 /* inst.operands[i] is a shifted-register operand; encode
10273 it into inst.instruction in the format used by Thumb32. */
10276 encode_thumb32_shifted_operand (int i
)
10278 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10279 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10281 constraint (inst
.operands
[i
].immisreg
,
10282 _("shift by register not allowed in thumb mode"));
10283 inst
.instruction
|= inst
.operands
[i
].reg
;
10284 if (shift
== SHIFT_RRX
)
10285 inst
.instruction
|= SHIFT_ROR
<< 4;
10288 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10289 _("expression too complex"));
10291 constraint (value
> 32
10292 || (value
== 32 && (shift
== SHIFT_LSL
10293 || shift
== SHIFT_ROR
)),
10294 _("shift expression is too large"));
10298 else if (value
== 32)
10301 inst
.instruction
|= shift
<< 4;
10302 inst
.instruction
|= (value
& 0x1c) << 10;
10303 inst
.instruction
|= (value
& 0x03) << 6;
10308 /* inst.operands[i] was set up by parse_address. Encode it into a
10309 Thumb32 format load or store instruction. Reject forms that cannot
10310 be used with such instructions. If is_t is true, reject forms that
10311 cannot be used with a T instruction; if is_d is true, reject forms
10312 that cannot be used with a D instruction. If it is a store insn,
10313 reject PC in Rn. */
10316 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10318 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10320 constraint (!inst
.operands
[i
].isreg
,
10321 _("Instruction does not support =N addresses"));
10323 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10324 if (inst
.operands
[i
].immisreg
)
10326 constraint (is_pc
, BAD_PC_ADDRESSING
);
10327 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10328 constraint (inst
.operands
[i
].negative
,
10329 _("Thumb does not support negative register indexing"));
10330 constraint (inst
.operands
[i
].postind
,
10331 _("Thumb does not support register post-indexing"));
10332 constraint (inst
.operands
[i
].writeback
,
10333 _("Thumb does not support register indexing with writeback"));
10334 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10335 _("Thumb supports only LSL in shifted register indexing"));
10337 inst
.instruction
|= inst
.operands
[i
].imm
;
10338 if (inst
.operands
[i
].shifted
)
10340 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10341 _("expression too complex"));
10342 constraint (inst
.reloc
.exp
.X_add_number
< 0
10343 || inst
.reloc
.exp
.X_add_number
> 3,
10344 _("shift out of range"));
10345 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10347 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10349 else if (inst
.operands
[i
].preind
)
10351 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10352 constraint (is_t
&& inst
.operands
[i
].writeback
,
10353 _("cannot use writeback with this instruction"));
10354 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10355 BAD_PC_ADDRESSING
);
10359 inst
.instruction
|= 0x01000000;
10360 if (inst
.operands
[i
].writeback
)
10361 inst
.instruction
|= 0x00200000;
10365 inst
.instruction
|= 0x00000c00;
10366 if (inst
.operands
[i
].writeback
)
10367 inst
.instruction
|= 0x00000100;
10369 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10371 else if (inst
.operands
[i
].postind
)
10373 gas_assert (inst
.operands
[i
].writeback
);
10374 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10375 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10378 inst
.instruction
|= 0x00200000;
10380 inst
.instruction
|= 0x00000900;
10381 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10383 else /* unindexed - only for coprocessor */
10384 inst
.error
= _("instruction does not accept unindexed addressing");
10387 /* Table of Thumb instructions which exist in both 16- and 32-bit
10388 encodings (the latter only in post-V6T2 cores). The index is the
10389 value used in the insns table below. When there is more than one
10390 possible 16-bit encoding for the instruction, this table always
10392 Also contains several pseudo-instructions used during relaxation. */
10393 #define T16_32_TAB \
10394 X(_adc, 4140, eb400000), \
10395 X(_adcs, 4140, eb500000), \
10396 X(_add, 1c00, eb000000), \
10397 X(_adds, 1c00, eb100000), \
10398 X(_addi, 0000, f1000000), \
10399 X(_addis, 0000, f1100000), \
10400 X(_add_pc,000f, f20f0000), \
10401 X(_add_sp,000d, f10d0000), \
10402 X(_adr, 000f, f20f0000), \
10403 X(_and, 4000, ea000000), \
10404 X(_ands, 4000, ea100000), \
10405 X(_asr, 1000, fa40f000), \
10406 X(_asrs, 1000, fa50f000), \
10407 X(_b, e000, f000b000), \
10408 X(_bcond, d000, f0008000), \
10409 X(_bic, 4380, ea200000), \
10410 X(_bics, 4380, ea300000), \
10411 X(_cmn, 42c0, eb100f00), \
10412 X(_cmp, 2800, ebb00f00), \
10413 X(_cpsie, b660, f3af8400), \
10414 X(_cpsid, b670, f3af8600), \
10415 X(_cpy, 4600, ea4f0000), \
10416 X(_dec_sp,80dd, f1ad0d00), \
10417 X(_eor, 4040, ea800000), \
10418 X(_eors, 4040, ea900000), \
10419 X(_inc_sp,00dd, f10d0d00), \
10420 X(_ldmia, c800, e8900000), \
10421 X(_ldr, 6800, f8500000), \
10422 X(_ldrb, 7800, f8100000), \
10423 X(_ldrh, 8800, f8300000), \
10424 X(_ldrsb, 5600, f9100000), \
10425 X(_ldrsh, 5e00, f9300000), \
10426 X(_ldr_pc,4800, f85f0000), \
10427 X(_ldr_pc2,4800, f85f0000), \
10428 X(_ldr_sp,9800, f85d0000), \
10429 X(_lsl, 0000, fa00f000), \
10430 X(_lsls, 0000, fa10f000), \
10431 X(_lsr, 0800, fa20f000), \
10432 X(_lsrs, 0800, fa30f000), \
10433 X(_mov, 2000, ea4f0000), \
10434 X(_movs, 2000, ea5f0000), \
10435 X(_mul, 4340, fb00f000), \
10436 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10437 X(_mvn, 43c0, ea6f0000), \
10438 X(_mvns, 43c0, ea7f0000), \
10439 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10440 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10441 X(_orr, 4300, ea400000), \
10442 X(_orrs, 4300, ea500000), \
10443 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10444 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10445 X(_rev, ba00, fa90f080), \
10446 X(_rev16, ba40, fa90f090), \
10447 X(_revsh, bac0, fa90f0b0), \
10448 X(_ror, 41c0, fa60f000), \
10449 X(_rors, 41c0, fa70f000), \
10450 X(_sbc, 4180, eb600000), \
10451 X(_sbcs, 4180, eb700000), \
10452 X(_stmia, c000, e8800000), \
10453 X(_str, 6000, f8400000), \
10454 X(_strb, 7000, f8000000), \
10455 X(_strh, 8000, f8200000), \
10456 X(_str_sp,9000, f84d0000), \
10457 X(_sub, 1e00, eba00000), \
10458 X(_subs, 1e00, ebb00000), \
10459 X(_subi, 8000, f1a00000), \
10460 X(_subis, 8000, f1b00000), \
10461 X(_sxtb, b240, fa4ff080), \
10462 X(_sxth, b200, fa0ff080), \
10463 X(_tst, 4200, ea100f00), \
10464 X(_uxtb, b2c0, fa5ff080), \
10465 X(_uxth, b280, fa1ff080), \
10466 X(_nop, bf00, f3af8000), \
10467 X(_yield, bf10, f3af8001), \
10468 X(_wfe, bf20, f3af8002), \
10469 X(_wfi, bf30, f3af8003), \
10470 X(_sev, bf40, f3af8004), \
10471 X(_sevl, bf50, f3af8005), \
10472 X(_udf, de00, f7f0a000)
10474 /* To catch errors in encoding functions, the codes are all offset by
10475 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10476 as 16-bit instructions. */
10477 #define X(a,b,c) T_MNEM##a
10478 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10481 #define X(a,b,c) 0x##b
10482 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10483 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10486 #define X(a,b,c) 0x##c
10487 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10488 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10489 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10493 /* Thumb instruction encoders, in alphabetical order. */
10495 /* ADDW or SUBW. */
10498 do_t_add_sub_w (void)
10502 Rd
= inst
.operands
[0].reg
;
10503 Rn
= inst
.operands
[1].reg
;
10505 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10506 is the SP-{plus,minus}-immediate form of the instruction. */
10508 constraint (Rd
== REG_PC
, BAD_PC
);
10510 reject_bad_reg (Rd
);
10512 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10513 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10516 /* Parse an add or subtract instruction. We get here with inst.instruction
10517 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10520 do_t_add_sub (void)
10524 Rd
= inst
.operands
[0].reg
;
10525 Rs
= (inst
.operands
[1].present
10526 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10527 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10530 set_it_insn_type_last ();
10532 if (unified_syntax
)
10535 bfd_boolean narrow
;
10538 flags
= (inst
.instruction
== T_MNEM_adds
10539 || inst
.instruction
== T_MNEM_subs
);
10541 narrow
= !in_it_block ();
10543 narrow
= in_it_block ();
10544 if (!inst
.operands
[2].isreg
)
10548 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10549 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10551 add
= (inst
.instruction
== T_MNEM_add
10552 || inst
.instruction
== T_MNEM_adds
);
10554 if (inst
.size_req
!= 4)
10556 /* Attempt to use a narrow opcode, with relaxation if
10558 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10559 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10560 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10561 opcode
= T_MNEM_add_sp
;
10562 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10563 opcode
= T_MNEM_add_pc
;
10564 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10567 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10569 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10573 inst
.instruction
= THUMB_OP16(opcode
);
10574 inst
.instruction
|= (Rd
<< 4) | Rs
;
10575 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10576 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10578 if (inst
.size_req
== 2)
10579 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10581 inst
.relax
= opcode
;
10585 constraint (inst
.size_req
== 2, BAD_HIREG
);
10587 if (inst
.size_req
== 4
10588 || (inst
.size_req
!= 2 && !opcode
))
10590 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10591 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10592 THUMB1_RELOC_ONLY
);
10595 constraint (add
, BAD_PC
);
10596 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10597 _("only SUBS PC, LR, #const allowed"));
10598 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10599 _("expression too complex"));
10600 constraint (inst
.reloc
.exp
.X_add_number
< 0
10601 || inst
.reloc
.exp
.X_add_number
> 0xff,
10602 _("immediate value out of range"));
10603 inst
.instruction
= T2_SUBS_PC_LR
10604 | inst
.reloc
.exp
.X_add_number
;
10605 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10608 else if (Rs
== REG_PC
)
10610 /* Always use addw/subw. */
10611 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10612 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10616 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10617 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10620 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10622 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10624 inst
.instruction
|= Rd
<< 8;
10625 inst
.instruction
|= Rs
<< 16;
10630 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10631 unsigned int shift
= inst
.operands
[2].shift_kind
;
10633 Rn
= inst
.operands
[2].reg
;
10634 /* See if we can do this with a 16-bit instruction. */
10635 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10637 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10642 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10643 || inst
.instruction
== T_MNEM_add
)
10645 : T_OPCODE_SUB_R3
);
10646 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10650 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10652 /* Thumb-1 cores (except v6-M) require at least one high
10653 register in a narrow non flag setting add. */
10654 if (Rd
> 7 || Rn
> 7
10655 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10656 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10663 inst
.instruction
= T_OPCODE_ADD_HI
;
10664 inst
.instruction
|= (Rd
& 8) << 4;
10665 inst
.instruction
|= (Rd
& 7);
10666 inst
.instruction
|= Rn
<< 3;
10672 constraint (Rd
== REG_PC
, BAD_PC
);
10673 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10674 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10675 constraint (Rs
== REG_PC
, BAD_PC
);
10676 reject_bad_reg (Rn
);
10678 /* If we get here, it can't be done in 16 bits. */
10679 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10680 _("shift must be constant"));
10681 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10682 inst
.instruction
|= Rd
<< 8;
10683 inst
.instruction
|= Rs
<< 16;
10684 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10685 _("shift value over 3 not allowed in thumb mode"));
10686 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10687 _("only LSL shift allowed in thumb mode"));
10688 encode_thumb32_shifted_operand (2);
10693 constraint (inst
.instruction
== T_MNEM_adds
10694 || inst
.instruction
== T_MNEM_subs
,
10697 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10699 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10700 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10703 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10704 ? 0x0000 : 0x8000);
10705 inst
.instruction
|= (Rd
<< 4) | Rs
;
10706 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10710 Rn
= inst
.operands
[2].reg
;
10711 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10713 /* We now have Rd, Rs, and Rn set to registers. */
10714 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10716 /* Can't do this for SUB. */
10717 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10718 inst
.instruction
= T_OPCODE_ADD_HI
;
10719 inst
.instruction
|= (Rd
& 8) << 4;
10720 inst
.instruction
|= (Rd
& 7);
10722 inst
.instruction
|= Rn
<< 3;
10724 inst
.instruction
|= Rs
<< 3;
10726 constraint (1, _("dest must overlap one source register"));
10730 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10731 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10732 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10742 Rd
= inst
.operands
[0].reg
;
10743 reject_bad_reg (Rd
);
10745 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10747 /* Defer to section relaxation. */
10748 inst
.relax
= inst
.instruction
;
10749 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10750 inst
.instruction
|= Rd
<< 4;
10752 else if (unified_syntax
&& inst
.size_req
!= 2)
10754 /* Generate a 32-bit opcode. */
10755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10756 inst
.instruction
|= Rd
<< 8;
10757 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10758 inst
.reloc
.pc_rel
= 1;
10762 /* Generate a 16-bit opcode. */
10763 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10764 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10765 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10766 inst
.reloc
.pc_rel
= 1;
10767 inst
.instruction
|= Rd
<< 4;
10770 if (inst
.reloc
.exp
.X_op
== O_symbol
10771 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10772 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10773 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10774 inst
.reloc
.exp
.X_add_number
+= 1;
10777 /* Arithmetic instructions for which there is just one 16-bit
10778 instruction encoding, and it allows only two low registers.
10779 For maximal compatibility with ARM syntax, we allow three register
10780 operands even when Thumb-32 instructions are not available, as long
10781 as the first two are identical. For instance, both "sbc r0,r1" and
10782 "sbc r0,r0,r1" are allowed. */
10788 Rd
= inst
.operands
[0].reg
;
10789 Rs
= (inst
.operands
[1].present
10790 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10791 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10792 Rn
= inst
.operands
[2].reg
;
10794 reject_bad_reg (Rd
);
10795 reject_bad_reg (Rs
);
10796 if (inst
.operands
[2].isreg
)
10797 reject_bad_reg (Rn
);
10799 if (unified_syntax
)
10801 if (!inst
.operands
[2].isreg
)
10803 /* For an immediate, we always generate a 32-bit opcode;
10804 section relaxation will shrink it later if possible. */
10805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10806 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10807 inst
.instruction
|= Rd
<< 8;
10808 inst
.instruction
|= Rs
<< 16;
10809 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10813 bfd_boolean narrow
;
10815 /* See if we can do this with a 16-bit instruction. */
10816 if (THUMB_SETS_FLAGS (inst
.instruction
))
10817 narrow
= !in_it_block ();
10819 narrow
= in_it_block ();
10821 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10823 if (inst
.operands
[2].shifted
)
10825 if (inst
.size_req
== 4)
10831 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10832 inst
.instruction
|= Rd
;
10833 inst
.instruction
|= Rn
<< 3;
10837 /* If we get here, it can't be done in 16 bits. */
10838 constraint (inst
.operands
[2].shifted
10839 && inst
.operands
[2].immisreg
,
10840 _("shift must be constant"));
10841 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10842 inst
.instruction
|= Rd
<< 8;
10843 inst
.instruction
|= Rs
<< 16;
10844 encode_thumb32_shifted_operand (2);
10849 /* On its face this is a lie - the instruction does set the
10850 flags. However, the only supported mnemonic in this mode
10851 says it doesn't. */
10852 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10854 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10855 _("unshifted register required"));
10856 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10857 constraint (Rd
!= Rs
,
10858 _("dest and source1 must be the same register"));
10860 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10861 inst
.instruction
|= Rd
;
10862 inst
.instruction
|= Rn
<< 3;
10866 /* Similarly, but for instructions where the arithmetic operation is
10867 commutative, so we can allow either of them to be different from
10868 the destination operand in a 16-bit instruction. For instance, all
10869 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10876 Rd
= inst
.operands
[0].reg
;
10877 Rs
= (inst
.operands
[1].present
10878 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10879 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10880 Rn
= inst
.operands
[2].reg
;
10882 reject_bad_reg (Rd
);
10883 reject_bad_reg (Rs
);
10884 if (inst
.operands
[2].isreg
)
10885 reject_bad_reg (Rn
);
10887 if (unified_syntax
)
10889 if (!inst
.operands
[2].isreg
)
10891 /* For an immediate, we always generate a 32-bit opcode;
10892 section relaxation will shrink it later if possible. */
10893 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10894 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10895 inst
.instruction
|= Rd
<< 8;
10896 inst
.instruction
|= Rs
<< 16;
10897 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10901 bfd_boolean narrow
;
10903 /* See if we can do this with a 16-bit instruction. */
10904 if (THUMB_SETS_FLAGS (inst
.instruction
))
10905 narrow
= !in_it_block ();
10907 narrow
= in_it_block ();
10909 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10911 if (inst
.operands
[2].shifted
)
10913 if (inst
.size_req
== 4)
10920 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10921 inst
.instruction
|= Rd
;
10922 inst
.instruction
|= Rn
<< 3;
10927 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10928 inst
.instruction
|= Rd
;
10929 inst
.instruction
|= Rs
<< 3;
10934 /* If we get here, it can't be done in 16 bits. */
10935 constraint (inst
.operands
[2].shifted
10936 && inst
.operands
[2].immisreg
,
10937 _("shift must be constant"));
10938 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10939 inst
.instruction
|= Rd
<< 8;
10940 inst
.instruction
|= Rs
<< 16;
10941 encode_thumb32_shifted_operand (2);
10946 /* On its face this is a lie - the instruction does set the
10947 flags. However, the only supported mnemonic in this mode
10948 says it doesn't. */
10949 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10951 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10952 _("unshifted register required"));
10953 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10955 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10956 inst
.instruction
|= Rd
;
10959 inst
.instruction
|= Rn
<< 3;
10961 inst
.instruction
|= Rs
<< 3;
10963 constraint (1, _("dest must overlap one source register"));
10971 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10972 constraint (msb
> 32, _("bit-field extends past end of register"));
10973 /* The instruction encoding stores the LSB and MSB,
10974 not the LSB and width. */
10975 Rd
= inst
.operands
[0].reg
;
10976 reject_bad_reg (Rd
);
10977 inst
.instruction
|= Rd
<< 8;
10978 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10979 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10980 inst
.instruction
|= msb
- 1;
10989 Rd
= inst
.operands
[0].reg
;
10990 reject_bad_reg (Rd
);
10992 /* #0 in second position is alternative syntax for bfc, which is
10993 the same instruction but with REG_PC in the Rm field. */
10994 if (!inst
.operands
[1].isreg
)
10998 Rn
= inst
.operands
[1].reg
;
10999 reject_bad_reg (Rn
);
11002 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11003 constraint (msb
> 32, _("bit-field extends past end of register"));
11004 /* The instruction encoding stores the LSB and MSB,
11005 not the LSB and width. */
11006 inst
.instruction
|= Rd
<< 8;
11007 inst
.instruction
|= Rn
<< 16;
11008 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11009 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11010 inst
.instruction
|= msb
- 1;
11018 Rd
= inst
.operands
[0].reg
;
11019 Rn
= inst
.operands
[1].reg
;
11021 reject_bad_reg (Rd
);
11022 reject_bad_reg (Rn
);
11024 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11025 _("bit-field extends past end of register"));
11026 inst
.instruction
|= Rd
<< 8;
11027 inst
.instruction
|= Rn
<< 16;
11028 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11029 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11030 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11033 /* ARM V5 Thumb BLX (argument parse)
11034 BLX <target_addr> which is BLX(1)
11035 BLX <Rm> which is BLX(2)
11036 Unfortunately, there are two different opcodes for this mnemonic.
11037 So, the insns[].value is not used, and the code here zaps values
11038 into inst.instruction.
11040 ??? How to take advantage of the additional two bits of displacement
11041 available in Thumb32 mode? Need new relocation? */
11046 set_it_insn_type_last ();
11048 if (inst
.operands
[0].isreg
)
11050 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11051 /* We have a register, so this is BLX(2). */
11052 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11056 /* No register. This must be BLX(1). */
11057 inst
.instruction
= 0xf000e800;
11058 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11067 bfd_reloc_code_real_type reloc
;
11070 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11072 if (in_it_block ())
11074 /* Conditional branches inside IT blocks are encoded as unconditional
11076 cond
= COND_ALWAYS
;
11081 if (cond
!= COND_ALWAYS
)
11082 opcode
= T_MNEM_bcond
;
11084 opcode
= inst
.instruction
;
11087 && (inst
.size_req
== 4
11088 || (inst
.size_req
!= 2
11089 && (inst
.operands
[0].hasreloc
11090 || inst
.reloc
.exp
.X_op
== O_constant
))))
11092 inst
.instruction
= THUMB_OP32(opcode
);
11093 if (cond
== COND_ALWAYS
)
11094 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11098 _("selected architecture does not support "
11099 "wide conditional branch instruction"));
11101 gas_assert (cond
!= 0xF);
11102 inst
.instruction
|= cond
<< 22;
11103 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11108 inst
.instruction
= THUMB_OP16(opcode
);
11109 if (cond
== COND_ALWAYS
)
11110 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11113 inst
.instruction
|= cond
<< 8;
11114 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11116 /* Allow section relaxation. */
11117 if (unified_syntax
&& inst
.size_req
!= 2)
11118 inst
.relax
= opcode
;
11120 inst
.reloc
.type
= reloc
;
11121 inst
.reloc
.pc_rel
= 1;
11124 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11125 between the two is the maximum immediate allowed - which is passed in
11128 do_t_bkpt_hlt1 (int range
)
11130 constraint (inst
.cond
!= COND_ALWAYS
,
11131 _("instruction is always unconditional"));
11132 if (inst
.operands
[0].present
)
11134 constraint (inst
.operands
[0].imm
> range
,
11135 _("immediate value out of range"));
11136 inst
.instruction
|= inst
.operands
[0].imm
;
11139 set_it_insn_type (NEUTRAL_IT_INSN
);
11145 do_t_bkpt_hlt1 (63);
11151 do_t_bkpt_hlt1 (255);
11155 do_t_branch23 (void)
11157 set_it_insn_type_last ();
11158 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11160 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11161 this file. We used to simply ignore the PLT reloc type here --
11162 the branch encoding is now needed to deal with TLSCALL relocs.
11163 So if we see a PLT reloc now, put it back to how it used to be to
11164 keep the preexisting behaviour. */
11165 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11166 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11168 #if defined(OBJ_COFF)
11169 /* If the destination of the branch is a defined symbol which does not have
11170 the THUMB_FUNC attribute, then we must be calling a function which has
11171 the (interfacearm) attribute. We look for the Thumb entry point to that
11172 function and change the branch to refer to that function instead. */
11173 if ( inst
.reloc
.exp
.X_op
== O_symbol
11174 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11175 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11176 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11177 inst
.reloc
.exp
.X_add_symbol
=
11178 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11185 set_it_insn_type_last ();
11186 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11187 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11188 should cause the alignment to be checked once it is known. This is
11189 because BX PC only works if the instruction is word aligned. */
11197 set_it_insn_type_last ();
11198 Rm
= inst
.operands
[0].reg
;
11199 reject_bad_reg (Rm
);
11200 inst
.instruction
|= Rm
<< 16;
11209 Rd
= inst
.operands
[0].reg
;
11210 Rm
= inst
.operands
[1].reg
;
11212 reject_bad_reg (Rd
);
11213 reject_bad_reg (Rm
);
11215 inst
.instruction
|= Rd
<< 8;
11216 inst
.instruction
|= Rm
<< 16;
11217 inst
.instruction
|= Rm
;
11223 set_it_insn_type (OUTSIDE_IT_INSN
);
11224 inst
.instruction
|= inst
.operands
[0].imm
;
11230 set_it_insn_type (OUTSIDE_IT_INSN
);
11232 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11233 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11235 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11236 inst
.instruction
= 0xf3af8000;
11237 inst
.instruction
|= imod
<< 9;
11238 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11239 if (inst
.operands
[1].present
)
11240 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11244 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11245 && (inst
.operands
[0].imm
& 4),
11246 _("selected processor does not support 'A' form "
11247 "of this instruction"));
11248 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11249 _("Thumb does not support the 2-argument "
11250 "form of this instruction"));
11251 inst
.instruction
|= inst
.operands
[0].imm
;
11255 /* THUMB CPY instruction (argument parse). */
11260 if (inst
.size_req
== 4)
11262 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11263 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11264 inst
.instruction
|= inst
.operands
[1].reg
;
11268 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11269 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11270 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11277 set_it_insn_type (OUTSIDE_IT_INSN
);
11278 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11279 inst
.instruction
|= inst
.operands
[0].reg
;
11280 inst
.reloc
.pc_rel
= 1;
11281 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11287 inst
.instruction
|= inst
.operands
[0].imm
;
11293 unsigned Rd
, Rn
, Rm
;
11295 Rd
= inst
.operands
[0].reg
;
11296 Rn
= (inst
.operands
[1].present
11297 ? inst
.operands
[1].reg
: Rd
);
11298 Rm
= inst
.operands
[2].reg
;
11300 reject_bad_reg (Rd
);
11301 reject_bad_reg (Rn
);
11302 reject_bad_reg (Rm
);
11304 inst
.instruction
|= Rd
<< 8;
11305 inst
.instruction
|= Rn
<< 16;
11306 inst
.instruction
|= Rm
;
11312 if (unified_syntax
&& inst
.size_req
== 4)
11313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11315 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11321 unsigned int cond
= inst
.operands
[0].imm
;
11323 set_it_insn_type (IT_INSN
);
11324 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11326 now_it
.warn_deprecated
= FALSE
;
11328 /* If the condition is a negative condition, invert the mask. */
11329 if ((cond
& 0x1) == 0x0)
11331 unsigned int mask
= inst
.instruction
& 0x000f;
11333 if ((mask
& 0x7) == 0)
11335 /* No conversion needed. */
11336 now_it
.block_length
= 1;
11338 else if ((mask
& 0x3) == 0)
11341 now_it
.block_length
= 2;
11343 else if ((mask
& 0x1) == 0)
11346 now_it
.block_length
= 3;
11351 now_it
.block_length
= 4;
11354 inst
.instruction
&= 0xfff0;
11355 inst
.instruction
|= mask
;
11358 inst
.instruction
|= cond
<< 4;
11361 /* Helper function used for both push/pop and ldm/stm. */
11363 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11367 load
= (inst
.instruction
& (1 << 20)) != 0;
11369 if (mask
& (1 << 13))
11370 inst
.error
= _("SP not allowed in register list");
11372 if ((mask
& (1 << base
)) != 0
11374 inst
.error
= _("having the base register in the register list when "
11375 "using write back is UNPREDICTABLE");
11379 if (mask
& (1 << 15))
11381 if (mask
& (1 << 14))
11382 inst
.error
= _("LR and PC should not both be in register list");
11384 set_it_insn_type_last ();
11389 if (mask
& (1 << 15))
11390 inst
.error
= _("PC not allowed in register list");
11393 if ((mask
& (mask
- 1)) == 0)
11395 /* Single register transfers implemented as str/ldr. */
11398 if (inst
.instruction
& (1 << 23))
11399 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11401 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11405 if (inst
.instruction
& (1 << 23))
11406 inst
.instruction
= 0x00800000; /* ia -> [base] */
11408 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11411 inst
.instruction
|= 0xf8400000;
11413 inst
.instruction
|= 0x00100000;
11415 mask
= ffs (mask
) - 1;
11418 else if (writeback
)
11419 inst
.instruction
|= WRITE_BACK
;
11421 inst
.instruction
|= mask
;
11422 inst
.instruction
|= base
<< 16;
11428 /* This really doesn't seem worth it. */
11429 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11430 _("expression too complex"));
11431 constraint (inst
.operands
[1].writeback
,
11432 _("Thumb load/store multiple does not support {reglist}^"));
11434 if (unified_syntax
)
11436 bfd_boolean narrow
;
11440 /* See if we can use a 16-bit instruction. */
11441 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11442 && inst
.size_req
!= 4
11443 && !(inst
.operands
[1].imm
& ~0xff))
11445 mask
= 1 << inst
.operands
[0].reg
;
11447 if (inst
.operands
[0].reg
<= 7)
11449 if (inst
.instruction
== T_MNEM_stmia
11450 ? inst
.operands
[0].writeback
11451 : (inst
.operands
[0].writeback
11452 == !(inst
.operands
[1].imm
& mask
)))
11454 if (inst
.instruction
== T_MNEM_stmia
11455 && (inst
.operands
[1].imm
& mask
)
11456 && (inst
.operands
[1].imm
& (mask
- 1)))
11457 as_warn (_("value stored for r%d is UNKNOWN"),
11458 inst
.operands
[0].reg
);
11460 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11461 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11462 inst
.instruction
|= inst
.operands
[1].imm
;
11465 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11467 /* This means 1 register in reg list one of 3 situations:
11468 1. Instruction is stmia, but without writeback.
11469 2. lmdia without writeback, but with Rn not in
11471 3. ldmia with writeback, but with Rn in reglist.
11472 Case 3 is UNPREDICTABLE behaviour, so we handle
11473 case 1 and 2 which can be converted into a 16-bit
11474 str or ldr. The SP cases are handled below. */
11475 unsigned long opcode
;
11476 /* First, record an error for Case 3. */
11477 if (inst
.operands
[1].imm
& mask
11478 && inst
.operands
[0].writeback
)
11480 _("having the base register in the register list when "
11481 "using write back is UNPREDICTABLE");
11483 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11485 inst
.instruction
= THUMB_OP16 (opcode
);
11486 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11487 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11491 else if (inst
.operands
[0] .reg
== REG_SP
)
11493 if (inst
.operands
[0].writeback
)
11496 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11497 ? T_MNEM_push
: T_MNEM_pop
);
11498 inst
.instruction
|= inst
.operands
[1].imm
;
11501 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11504 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11505 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11506 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11514 if (inst
.instruction
< 0xffff)
11515 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11517 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11518 inst
.operands
[0].writeback
);
11523 constraint (inst
.operands
[0].reg
> 7
11524 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11525 constraint (inst
.instruction
!= T_MNEM_ldmia
11526 && inst
.instruction
!= T_MNEM_stmia
,
11527 _("Thumb-2 instruction only valid in unified syntax"));
11528 if (inst
.instruction
== T_MNEM_stmia
)
11530 if (!inst
.operands
[0].writeback
)
11531 as_warn (_("this instruction will write back the base register"));
11532 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11533 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11534 as_warn (_("value stored for r%d is UNKNOWN"),
11535 inst
.operands
[0].reg
);
11539 if (!inst
.operands
[0].writeback
11540 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11541 as_warn (_("this instruction will write back the base register"));
11542 else if (inst
.operands
[0].writeback
11543 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11544 as_warn (_("this instruction will not write back the base register"));
11547 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11549 inst
.instruction
|= inst
.operands
[1].imm
;
11556 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11557 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11558 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11559 || inst
.operands
[1].negative
,
11562 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11565 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11566 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11572 if (!inst
.operands
[1].present
)
11574 constraint (inst
.operands
[0].reg
== REG_LR
,
11575 _("r14 not allowed as first register "
11576 "when second register is omitted"));
11577 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11579 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11583 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11584 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11590 unsigned long opcode
;
11593 if (inst
.operands
[0].isreg
11594 && !inst
.operands
[0].preind
11595 && inst
.operands
[0].reg
== REG_PC
)
11596 set_it_insn_type_last ();
11598 opcode
= inst
.instruction
;
11599 if (unified_syntax
)
11601 if (!inst
.operands
[1].isreg
)
11603 if (opcode
<= 0xffff)
11604 inst
.instruction
= THUMB_OP32 (opcode
);
11605 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11608 if (inst
.operands
[1].isreg
11609 && !inst
.operands
[1].writeback
11610 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11611 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11612 && opcode
<= 0xffff
11613 && inst
.size_req
!= 4)
11615 /* Insn may have a 16-bit form. */
11616 Rn
= inst
.operands
[1].reg
;
11617 if (inst
.operands
[1].immisreg
)
11619 inst
.instruction
= THUMB_OP16 (opcode
);
11621 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11623 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11624 reject_bad_reg (inst
.operands
[1].imm
);
11626 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11627 && opcode
!= T_MNEM_ldrsb
)
11628 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11629 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11636 if (inst
.reloc
.pc_rel
)
11637 opcode
= T_MNEM_ldr_pc2
;
11639 opcode
= T_MNEM_ldr_pc
;
11643 if (opcode
== T_MNEM_ldr
)
11644 opcode
= T_MNEM_ldr_sp
;
11646 opcode
= T_MNEM_str_sp
;
11648 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11652 inst
.instruction
= inst
.operands
[0].reg
;
11653 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11655 inst
.instruction
|= THUMB_OP16 (opcode
);
11656 if (inst
.size_req
== 2)
11657 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11659 inst
.relax
= opcode
;
11663 /* Definitely a 32-bit variant. */
11665 /* Warning for Erratum 752419. */
11666 if (opcode
== T_MNEM_ldr
11667 && inst
.operands
[0].reg
== REG_SP
11668 && inst
.operands
[1].writeback
== 1
11669 && !inst
.operands
[1].immisreg
)
11671 if (no_cpu_selected ()
11672 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11673 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11674 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11675 as_warn (_("This instruction may be unpredictable "
11676 "if executed on M-profile cores "
11677 "with interrupts enabled."));
11680 /* Do some validations regarding addressing modes. */
11681 if (inst
.operands
[1].immisreg
)
11682 reject_bad_reg (inst
.operands
[1].imm
);
11684 constraint (inst
.operands
[1].writeback
== 1
11685 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11688 inst
.instruction
= THUMB_OP32 (opcode
);
11689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11690 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11691 check_ldr_r15_aligned ();
11695 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11697 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11699 /* Only [Rn,Rm] is acceptable. */
11700 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11701 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11702 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11703 || inst
.operands
[1].negative
,
11704 _("Thumb does not support this addressing mode"));
11705 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11709 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11710 if (!inst
.operands
[1].isreg
)
11711 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11714 constraint (!inst
.operands
[1].preind
11715 || inst
.operands
[1].shifted
11716 || inst
.operands
[1].writeback
,
11717 _("Thumb does not support this addressing mode"));
11718 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11720 constraint (inst
.instruction
& 0x0600,
11721 _("byte or halfword not valid for base register"));
11722 constraint (inst
.operands
[1].reg
== REG_PC
11723 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11724 _("r15 based store not allowed"));
11725 constraint (inst
.operands
[1].immisreg
,
11726 _("invalid base register for register offset"));
11728 if (inst
.operands
[1].reg
== REG_PC
)
11729 inst
.instruction
= T_OPCODE_LDR_PC
;
11730 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11731 inst
.instruction
= T_OPCODE_LDR_SP
;
11733 inst
.instruction
= T_OPCODE_STR_SP
;
11735 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11736 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11740 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11741 if (!inst
.operands
[1].immisreg
)
11743 /* Immediate offset. */
11744 inst
.instruction
|= inst
.operands
[0].reg
;
11745 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11746 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11750 /* Register offset. */
11751 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11752 constraint (inst
.operands
[1].negative
,
11753 _("Thumb does not support this addressing mode"));
11756 switch (inst
.instruction
)
11758 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11759 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11760 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11761 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11762 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11763 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11764 case 0x5600 /* ldrsb */:
11765 case 0x5e00 /* ldrsh */: break;
11769 inst
.instruction
|= inst
.operands
[0].reg
;
11770 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11771 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11777 if (!inst
.operands
[1].present
)
11779 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11780 constraint (inst
.operands
[0].reg
== REG_LR
,
11781 _("r14 not allowed here"));
11782 constraint (inst
.operands
[0].reg
== REG_R12
,
11783 _("r12 not allowed here"));
11786 if (inst
.operands
[2].writeback
11787 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11788 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11789 as_warn (_("base register written back, and overlaps "
11790 "one of transfer registers"));
11792 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11793 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11794 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11801 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11807 unsigned Rd
, Rn
, Rm
, Ra
;
11809 Rd
= inst
.operands
[0].reg
;
11810 Rn
= inst
.operands
[1].reg
;
11811 Rm
= inst
.operands
[2].reg
;
11812 Ra
= inst
.operands
[3].reg
;
11814 reject_bad_reg (Rd
);
11815 reject_bad_reg (Rn
);
11816 reject_bad_reg (Rm
);
11817 reject_bad_reg (Ra
);
11819 inst
.instruction
|= Rd
<< 8;
11820 inst
.instruction
|= Rn
<< 16;
11821 inst
.instruction
|= Rm
;
11822 inst
.instruction
|= Ra
<< 12;
11828 unsigned RdLo
, RdHi
, Rn
, Rm
;
11830 RdLo
= inst
.operands
[0].reg
;
11831 RdHi
= inst
.operands
[1].reg
;
11832 Rn
= inst
.operands
[2].reg
;
11833 Rm
= inst
.operands
[3].reg
;
11835 reject_bad_reg (RdLo
);
11836 reject_bad_reg (RdHi
);
11837 reject_bad_reg (Rn
);
11838 reject_bad_reg (Rm
);
11840 inst
.instruction
|= RdLo
<< 12;
11841 inst
.instruction
|= RdHi
<< 8;
11842 inst
.instruction
|= Rn
<< 16;
11843 inst
.instruction
|= Rm
;
11847 do_t_mov_cmp (void)
11851 Rn
= inst
.operands
[0].reg
;
11852 Rm
= inst
.operands
[1].reg
;
11855 set_it_insn_type_last ();
11857 if (unified_syntax
)
11859 int r0off
= (inst
.instruction
== T_MNEM_mov
11860 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11861 unsigned long opcode
;
11862 bfd_boolean narrow
;
11863 bfd_boolean low_regs
;
11865 low_regs
= (Rn
<= 7 && Rm
<= 7);
11866 opcode
= inst
.instruction
;
11867 if (in_it_block ())
11868 narrow
= opcode
!= T_MNEM_movs
;
11870 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11871 if (inst
.size_req
== 4
11872 || inst
.operands
[1].shifted
)
11875 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11876 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11877 && !inst
.operands
[1].shifted
11881 inst
.instruction
= T2_SUBS_PC_LR
;
11885 if (opcode
== T_MNEM_cmp
)
11887 constraint (Rn
== REG_PC
, BAD_PC
);
11890 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11892 warn_deprecated_sp (Rm
);
11893 /* R15 was documented as a valid choice for Rm in ARMv6,
11894 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11895 tools reject R15, so we do too. */
11896 constraint (Rm
== REG_PC
, BAD_PC
);
11899 reject_bad_reg (Rm
);
11901 else if (opcode
== T_MNEM_mov
11902 || opcode
== T_MNEM_movs
)
11904 if (inst
.operands
[1].isreg
)
11906 if (opcode
== T_MNEM_movs
)
11908 reject_bad_reg (Rn
);
11909 reject_bad_reg (Rm
);
11913 /* This is mov.n. */
11914 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11915 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11917 as_tsktsk (_("Use of r%u as a source register is "
11918 "deprecated when r%u is the destination "
11919 "register."), Rm
, Rn
);
11924 /* This is mov.w. */
11925 constraint (Rn
== REG_PC
, BAD_PC
);
11926 constraint (Rm
== REG_PC
, BAD_PC
);
11927 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11928 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11932 reject_bad_reg (Rn
);
11935 if (!inst
.operands
[1].isreg
)
11937 /* Immediate operand. */
11938 if (!in_it_block () && opcode
== T_MNEM_mov
)
11940 if (low_regs
&& narrow
)
11942 inst
.instruction
= THUMB_OP16 (opcode
);
11943 inst
.instruction
|= Rn
<< 8;
11944 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11945 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11947 if (inst
.size_req
== 2)
11948 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11950 inst
.relax
= opcode
;
11955 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11956 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11957 THUMB1_RELOC_ONLY
);
11959 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11960 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11961 inst
.instruction
|= Rn
<< r0off
;
11962 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11965 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11966 && (inst
.instruction
== T_MNEM_mov
11967 || inst
.instruction
== T_MNEM_movs
))
11969 /* Register shifts are encoded as separate shift instructions. */
11970 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11972 if (in_it_block ())
11977 if (inst
.size_req
== 4)
11980 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11986 switch (inst
.operands
[1].shift_kind
)
11989 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11992 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11995 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11998 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12004 inst
.instruction
= opcode
;
12007 inst
.instruction
|= Rn
;
12008 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12013 inst
.instruction
|= CONDS_BIT
;
12015 inst
.instruction
|= Rn
<< 8;
12016 inst
.instruction
|= Rm
<< 16;
12017 inst
.instruction
|= inst
.operands
[1].imm
;
12022 /* Some mov with immediate shift have narrow variants.
12023 Register shifts are handled above. */
12024 if (low_regs
&& inst
.operands
[1].shifted
12025 && (inst
.instruction
== T_MNEM_mov
12026 || inst
.instruction
== T_MNEM_movs
))
12028 if (in_it_block ())
12029 narrow
= (inst
.instruction
== T_MNEM_mov
);
12031 narrow
= (inst
.instruction
== T_MNEM_movs
);
12036 switch (inst
.operands
[1].shift_kind
)
12038 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12039 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12040 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12041 default: narrow
= FALSE
; break;
12047 inst
.instruction
|= Rn
;
12048 inst
.instruction
|= Rm
<< 3;
12049 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12054 inst
.instruction
|= Rn
<< r0off
;
12055 encode_thumb32_shifted_operand (1);
12059 switch (inst
.instruction
)
12062 /* In v4t or v5t a move of two lowregs produces unpredictable
12063 results. Don't allow this. */
12066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12067 "MOV Rd, Rs with two low registers is not "
12068 "permitted on this architecture");
12069 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12073 inst
.instruction
= T_OPCODE_MOV_HR
;
12074 inst
.instruction
|= (Rn
& 0x8) << 4;
12075 inst
.instruction
|= (Rn
& 0x7);
12076 inst
.instruction
|= Rm
<< 3;
12080 /* We know we have low registers at this point.
12081 Generate LSLS Rd, Rs, #0. */
12082 inst
.instruction
= T_OPCODE_LSL_I
;
12083 inst
.instruction
|= Rn
;
12084 inst
.instruction
|= Rm
<< 3;
12090 inst
.instruction
= T_OPCODE_CMP_LR
;
12091 inst
.instruction
|= Rn
;
12092 inst
.instruction
|= Rm
<< 3;
12096 inst
.instruction
= T_OPCODE_CMP_HR
;
12097 inst
.instruction
|= (Rn
& 0x8) << 4;
12098 inst
.instruction
|= (Rn
& 0x7);
12099 inst
.instruction
|= Rm
<< 3;
12106 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12108 /* PR 10443: Do not silently ignore shifted operands. */
12109 constraint (inst
.operands
[1].shifted
,
12110 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12112 if (inst
.operands
[1].isreg
)
12114 if (Rn
< 8 && Rm
< 8)
12116 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12117 since a MOV instruction produces unpredictable results. */
12118 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12119 inst
.instruction
= T_OPCODE_ADD_I3
;
12121 inst
.instruction
= T_OPCODE_CMP_LR
;
12123 inst
.instruction
|= Rn
;
12124 inst
.instruction
|= Rm
<< 3;
12128 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12129 inst
.instruction
= T_OPCODE_MOV_HR
;
12131 inst
.instruction
= T_OPCODE_CMP_HR
;
12137 constraint (Rn
> 7,
12138 _("only lo regs allowed with immediate"));
12139 inst
.instruction
|= Rn
<< 8;
12140 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12151 top
= (inst
.instruction
& 0x00800000) != 0;
12152 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12154 constraint (top
, _(":lower16: not allowed in this instruction"));
12155 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12157 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12159 constraint (!top
, _(":upper16: not allowed in this instruction"));
12160 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12163 Rd
= inst
.operands
[0].reg
;
12164 reject_bad_reg (Rd
);
12166 inst
.instruction
|= Rd
<< 8;
12167 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12169 imm
= inst
.reloc
.exp
.X_add_number
;
12170 inst
.instruction
|= (imm
& 0xf000) << 4;
12171 inst
.instruction
|= (imm
& 0x0800) << 15;
12172 inst
.instruction
|= (imm
& 0x0700) << 4;
12173 inst
.instruction
|= (imm
& 0x00ff);
12178 do_t_mvn_tst (void)
12182 Rn
= inst
.operands
[0].reg
;
12183 Rm
= inst
.operands
[1].reg
;
12185 if (inst
.instruction
== T_MNEM_cmp
12186 || inst
.instruction
== T_MNEM_cmn
)
12187 constraint (Rn
== REG_PC
, BAD_PC
);
12189 reject_bad_reg (Rn
);
12190 reject_bad_reg (Rm
);
12192 if (unified_syntax
)
12194 int r0off
= (inst
.instruction
== T_MNEM_mvn
12195 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12196 bfd_boolean narrow
;
12198 if (inst
.size_req
== 4
12199 || inst
.instruction
> 0xffff
12200 || inst
.operands
[1].shifted
12201 || Rn
> 7 || Rm
> 7)
12203 else if (inst
.instruction
== T_MNEM_cmn
12204 || inst
.instruction
== T_MNEM_tst
)
12206 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12207 narrow
= !in_it_block ();
12209 narrow
= in_it_block ();
12211 if (!inst
.operands
[1].isreg
)
12213 /* For an immediate, we always generate a 32-bit opcode;
12214 section relaxation will shrink it later if possible. */
12215 if (inst
.instruction
< 0xffff)
12216 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12217 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12218 inst
.instruction
|= Rn
<< r0off
;
12219 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12223 /* See if we can do this with a 16-bit instruction. */
12226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12227 inst
.instruction
|= Rn
;
12228 inst
.instruction
|= Rm
<< 3;
12232 constraint (inst
.operands
[1].shifted
12233 && inst
.operands
[1].immisreg
,
12234 _("shift must be constant"));
12235 if (inst
.instruction
< 0xffff)
12236 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12237 inst
.instruction
|= Rn
<< r0off
;
12238 encode_thumb32_shifted_operand (1);
12244 constraint (inst
.instruction
> 0xffff
12245 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12246 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12247 _("unshifted register required"));
12248 constraint (Rn
> 7 || Rm
> 7,
12251 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12252 inst
.instruction
|= Rn
;
12253 inst
.instruction
|= Rm
<< 3;
12262 if (do_vfp_nsyn_mrs () == SUCCESS
)
12265 Rd
= inst
.operands
[0].reg
;
12266 reject_bad_reg (Rd
);
12267 inst
.instruction
|= Rd
<< 8;
12269 if (inst
.operands
[1].isreg
)
12271 unsigned br
= inst
.operands
[1].reg
;
12272 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12273 as_bad (_("bad register for mrs"));
12275 inst
.instruction
|= br
& (0xf << 16);
12276 inst
.instruction
|= (br
& 0x300) >> 4;
12277 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12281 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12283 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12285 /* PR gas/12698: The constraint is only applied for m_profile.
12286 If the user has specified -march=all, we want to ignore it as
12287 we are building for any CPU type, including non-m variants. */
12288 bfd_boolean m_profile
=
12289 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12290 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12291 "not support requested special purpose register"));
12294 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12296 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12297 _("'APSR', 'CPSR' or 'SPSR' expected"));
12299 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12300 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12301 inst
.instruction
|= 0xf0000;
12311 if (do_vfp_nsyn_msr () == SUCCESS
)
12314 constraint (!inst
.operands
[1].isreg
,
12315 _("Thumb encoding does not support an immediate here"));
12317 if (inst
.operands
[0].isreg
)
12318 flags
= (int)(inst
.operands
[0].reg
);
12320 flags
= inst
.operands
[0].imm
;
12322 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12324 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12326 /* PR gas/12698: The constraint is only applied for m_profile.
12327 If the user has specified -march=all, we want to ignore it as
12328 we are building for any CPU type, including non-m variants. */
12329 bfd_boolean m_profile
=
12330 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12331 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12332 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12333 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12334 && bits
!= PSR_f
)) && m_profile
,
12335 _("selected processor does not support requested special "
12336 "purpose register"));
12339 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12340 "requested special purpose register"));
12342 Rn
= inst
.operands
[1].reg
;
12343 reject_bad_reg (Rn
);
12345 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12346 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12347 inst
.instruction
|= (flags
& 0x300) >> 4;
12348 inst
.instruction
|= (flags
& 0xff);
12349 inst
.instruction
|= Rn
<< 16;
12355 bfd_boolean narrow
;
12356 unsigned Rd
, Rn
, Rm
;
12358 if (!inst
.operands
[2].present
)
12359 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12361 Rd
= inst
.operands
[0].reg
;
12362 Rn
= inst
.operands
[1].reg
;
12363 Rm
= inst
.operands
[2].reg
;
12365 if (unified_syntax
)
12367 if (inst
.size_req
== 4
12373 else if (inst
.instruction
== T_MNEM_muls
)
12374 narrow
= !in_it_block ();
12376 narrow
= in_it_block ();
12380 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12381 constraint (Rn
> 7 || Rm
> 7,
12388 /* 16-bit MULS/Conditional MUL. */
12389 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12390 inst
.instruction
|= Rd
;
12393 inst
.instruction
|= Rm
<< 3;
12395 inst
.instruction
|= Rn
<< 3;
12397 constraint (1, _("dest must overlap one source register"));
12401 constraint (inst
.instruction
!= T_MNEM_mul
,
12402 _("Thumb-2 MUL must not set flags"));
12404 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12405 inst
.instruction
|= Rd
<< 8;
12406 inst
.instruction
|= Rn
<< 16;
12407 inst
.instruction
|= Rm
<< 0;
12409 reject_bad_reg (Rd
);
12410 reject_bad_reg (Rn
);
12411 reject_bad_reg (Rm
);
12418 unsigned RdLo
, RdHi
, Rn
, Rm
;
12420 RdLo
= inst
.operands
[0].reg
;
12421 RdHi
= inst
.operands
[1].reg
;
12422 Rn
= inst
.operands
[2].reg
;
12423 Rm
= inst
.operands
[3].reg
;
12425 reject_bad_reg (RdLo
);
12426 reject_bad_reg (RdHi
);
12427 reject_bad_reg (Rn
);
12428 reject_bad_reg (Rm
);
12430 inst
.instruction
|= RdLo
<< 12;
12431 inst
.instruction
|= RdHi
<< 8;
12432 inst
.instruction
|= Rn
<< 16;
12433 inst
.instruction
|= Rm
;
12436 as_tsktsk (_("rdhi and rdlo must be different"));
12442 set_it_insn_type (NEUTRAL_IT_INSN
);
12444 if (unified_syntax
)
12446 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12448 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12449 inst
.instruction
|= inst
.operands
[0].imm
;
12453 /* PR9722: Check for Thumb2 availability before
12454 generating a thumb2 nop instruction. */
12455 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12457 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12458 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12461 inst
.instruction
= 0x46c0;
12466 constraint (inst
.operands
[0].present
,
12467 _("Thumb does not support NOP with hints"));
12468 inst
.instruction
= 0x46c0;
12475 if (unified_syntax
)
12477 bfd_boolean narrow
;
12479 if (THUMB_SETS_FLAGS (inst
.instruction
))
12480 narrow
= !in_it_block ();
12482 narrow
= in_it_block ();
12483 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12485 if (inst
.size_req
== 4)
12490 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12491 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12492 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12496 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12497 inst
.instruction
|= inst
.operands
[0].reg
;
12498 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12503 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12505 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12507 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12508 inst
.instruction
|= inst
.operands
[0].reg
;
12509 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12518 Rd
= inst
.operands
[0].reg
;
12519 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12521 reject_bad_reg (Rd
);
12522 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12523 reject_bad_reg (Rn
);
12525 inst
.instruction
|= Rd
<< 8;
12526 inst
.instruction
|= Rn
<< 16;
12528 if (!inst
.operands
[2].isreg
)
12530 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12531 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12537 Rm
= inst
.operands
[2].reg
;
12538 reject_bad_reg (Rm
);
12540 constraint (inst
.operands
[2].shifted
12541 && inst
.operands
[2].immisreg
,
12542 _("shift must be constant"));
12543 encode_thumb32_shifted_operand (2);
12550 unsigned Rd
, Rn
, Rm
;
12552 Rd
= inst
.operands
[0].reg
;
12553 Rn
= inst
.operands
[1].reg
;
12554 Rm
= inst
.operands
[2].reg
;
12556 reject_bad_reg (Rd
);
12557 reject_bad_reg (Rn
);
12558 reject_bad_reg (Rm
);
12560 inst
.instruction
|= Rd
<< 8;
12561 inst
.instruction
|= Rn
<< 16;
12562 inst
.instruction
|= Rm
;
12563 if (inst
.operands
[3].present
)
12565 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12566 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12567 _("expression too complex"));
12568 inst
.instruction
|= (val
& 0x1c) << 10;
12569 inst
.instruction
|= (val
& 0x03) << 6;
12576 if (!inst
.operands
[3].present
)
12580 inst
.instruction
&= ~0x00000020;
12582 /* PR 10168. Swap the Rm and Rn registers. */
12583 Rtmp
= inst
.operands
[1].reg
;
12584 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12585 inst
.operands
[2].reg
= Rtmp
;
12593 if (inst
.operands
[0].immisreg
)
12594 reject_bad_reg (inst
.operands
[0].imm
);
12596 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12600 do_t_push_pop (void)
12604 constraint (inst
.operands
[0].writeback
,
12605 _("push/pop do not support {reglist}^"));
12606 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12607 _("expression too complex"));
12609 mask
= inst
.operands
[0].imm
;
12610 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12611 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12612 else if (inst
.size_req
!= 4
12613 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12614 ? REG_LR
: REG_PC
)))
12616 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12617 inst
.instruction
|= THUMB_PP_PC_LR
;
12618 inst
.instruction
|= mask
& 0xff;
12620 else if (unified_syntax
)
12622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12623 encode_thumb2_ldmstm (13, mask
, TRUE
);
12627 inst
.error
= _("invalid register list to push/pop instruction");
12637 Rd
= inst
.operands
[0].reg
;
12638 Rm
= inst
.operands
[1].reg
;
12640 reject_bad_reg (Rd
);
12641 reject_bad_reg (Rm
);
12643 inst
.instruction
|= Rd
<< 8;
12644 inst
.instruction
|= Rm
<< 16;
12645 inst
.instruction
|= Rm
;
12653 Rd
= inst
.operands
[0].reg
;
12654 Rm
= inst
.operands
[1].reg
;
12656 reject_bad_reg (Rd
);
12657 reject_bad_reg (Rm
);
12659 if (Rd
<= 7 && Rm
<= 7
12660 && inst
.size_req
!= 4)
12662 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12663 inst
.instruction
|= Rd
;
12664 inst
.instruction
|= Rm
<< 3;
12666 else if (unified_syntax
)
12668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12669 inst
.instruction
|= Rd
<< 8;
12670 inst
.instruction
|= Rm
<< 16;
12671 inst
.instruction
|= Rm
;
12674 inst
.error
= BAD_HIREG
;
12682 Rd
= inst
.operands
[0].reg
;
12683 Rm
= inst
.operands
[1].reg
;
12685 reject_bad_reg (Rd
);
12686 reject_bad_reg (Rm
);
12688 inst
.instruction
|= Rd
<< 8;
12689 inst
.instruction
|= Rm
;
12697 Rd
= inst
.operands
[0].reg
;
12698 Rs
= (inst
.operands
[1].present
12699 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12700 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12702 reject_bad_reg (Rd
);
12703 reject_bad_reg (Rs
);
12704 if (inst
.operands
[2].isreg
)
12705 reject_bad_reg (inst
.operands
[2].reg
);
12707 inst
.instruction
|= Rd
<< 8;
12708 inst
.instruction
|= Rs
<< 16;
12709 if (!inst
.operands
[2].isreg
)
12711 bfd_boolean narrow
;
12713 if ((inst
.instruction
& 0x00100000) != 0)
12714 narrow
= !in_it_block ();
12716 narrow
= in_it_block ();
12718 if (Rd
> 7 || Rs
> 7)
12721 if (inst
.size_req
== 4 || !unified_syntax
)
12724 if (inst
.reloc
.exp
.X_op
!= O_constant
12725 || inst
.reloc
.exp
.X_add_number
!= 0)
12728 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12729 relaxation, but it doesn't seem worth the hassle. */
12732 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12733 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12734 inst
.instruction
|= Rs
<< 3;
12735 inst
.instruction
|= Rd
;
12739 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12740 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12744 encode_thumb32_shifted_operand (2);
12750 if (warn_on_deprecated
12751 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12752 as_tsktsk (_("setend use is deprecated for ARMv8"));
12754 set_it_insn_type (OUTSIDE_IT_INSN
);
12755 if (inst
.operands
[0].imm
)
12756 inst
.instruction
|= 0x8;
12762 if (!inst
.operands
[1].present
)
12763 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12765 if (unified_syntax
)
12767 bfd_boolean narrow
;
12770 switch (inst
.instruction
)
12773 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12775 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12777 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12779 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12783 if (THUMB_SETS_FLAGS (inst
.instruction
))
12784 narrow
= !in_it_block ();
12786 narrow
= in_it_block ();
12787 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12789 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12791 if (inst
.operands
[2].isreg
12792 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12793 || inst
.operands
[2].reg
> 7))
12795 if (inst
.size_req
== 4)
12798 reject_bad_reg (inst
.operands
[0].reg
);
12799 reject_bad_reg (inst
.operands
[1].reg
);
12803 if (inst
.operands
[2].isreg
)
12805 reject_bad_reg (inst
.operands
[2].reg
);
12806 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12807 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12808 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12809 inst
.instruction
|= inst
.operands
[2].reg
;
12811 /* PR 12854: Error on extraneous shifts. */
12812 constraint (inst
.operands
[2].shifted
,
12813 _("extraneous shift as part of operand to shift insn"));
12817 inst
.operands
[1].shifted
= 1;
12818 inst
.operands
[1].shift_kind
= shift_kind
;
12819 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12820 ? T_MNEM_movs
: T_MNEM_mov
);
12821 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12822 encode_thumb32_shifted_operand (1);
12823 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12824 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12829 if (inst
.operands
[2].isreg
)
12831 switch (shift_kind
)
12833 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12834 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12835 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12836 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12840 inst
.instruction
|= inst
.operands
[0].reg
;
12841 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12843 /* PR 12854: Error on extraneous shifts. */
12844 constraint (inst
.operands
[2].shifted
,
12845 _("extraneous shift as part of operand to shift insn"));
12849 switch (shift_kind
)
12851 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12852 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12853 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12856 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12857 inst
.instruction
|= inst
.operands
[0].reg
;
12858 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12864 constraint (inst
.operands
[0].reg
> 7
12865 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12866 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12868 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12870 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12871 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12872 _("source1 and dest must be same register"));
12874 switch (inst
.instruction
)
12876 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12877 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12878 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12879 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12883 inst
.instruction
|= inst
.operands
[0].reg
;
12884 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12886 /* PR 12854: Error on extraneous shifts. */
12887 constraint (inst
.operands
[2].shifted
,
12888 _("extraneous shift as part of operand to shift insn"));
12892 switch (inst
.instruction
)
12894 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12895 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12896 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12897 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12900 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12901 inst
.instruction
|= inst
.operands
[0].reg
;
12902 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12910 unsigned Rd
, Rn
, Rm
;
12912 Rd
= inst
.operands
[0].reg
;
12913 Rn
= inst
.operands
[1].reg
;
12914 Rm
= inst
.operands
[2].reg
;
12916 reject_bad_reg (Rd
);
12917 reject_bad_reg (Rn
);
12918 reject_bad_reg (Rm
);
12920 inst
.instruction
|= Rd
<< 8;
12921 inst
.instruction
|= Rn
<< 16;
12922 inst
.instruction
|= Rm
;
12928 unsigned Rd
, Rn
, Rm
;
12930 Rd
= inst
.operands
[0].reg
;
12931 Rm
= inst
.operands
[1].reg
;
12932 Rn
= inst
.operands
[2].reg
;
12934 reject_bad_reg (Rd
);
12935 reject_bad_reg (Rn
);
12936 reject_bad_reg (Rm
);
12938 inst
.instruction
|= Rd
<< 8;
12939 inst
.instruction
|= Rn
<< 16;
12940 inst
.instruction
|= Rm
;
12946 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12948 _("SMC is not permitted on this architecture"));
12949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12950 _("expression too complex"));
12951 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12952 inst
.instruction
|= (value
& 0xf000) >> 12;
12953 inst
.instruction
|= (value
& 0x0ff0);
12954 inst
.instruction
|= (value
& 0x000f) << 16;
12955 /* PR gas/15623: SMC instructions must be last in an IT block. */
12956 set_it_insn_type_last ();
12962 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12964 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12965 inst
.instruction
|= (value
& 0x0fff);
12966 inst
.instruction
|= (value
& 0xf000) << 4;
12970 do_t_ssat_usat (int bias
)
12974 Rd
= inst
.operands
[0].reg
;
12975 Rn
= inst
.operands
[2].reg
;
12977 reject_bad_reg (Rd
);
12978 reject_bad_reg (Rn
);
12980 inst
.instruction
|= Rd
<< 8;
12981 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12982 inst
.instruction
|= Rn
<< 16;
12984 if (inst
.operands
[3].present
)
12986 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12988 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12990 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12991 _("expression too complex"));
12993 if (shift_amount
!= 0)
12995 constraint (shift_amount
> 31,
12996 _("shift expression is too large"));
12998 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12999 inst
.instruction
|= 0x00200000; /* sh bit. */
13001 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13002 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13010 do_t_ssat_usat (1);
13018 Rd
= inst
.operands
[0].reg
;
13019 Rn
= inst
.operands
[2].reg
;
13021 reject_bad_reg (Rd
);
13022 reject_bad_reg (Rn
);
13024 inst
.instruction
|= Rd
<< 8;
13025 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13026 inst
.instruction
|= Rn
<< 16;
13032 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13033 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13034 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13035 || inst
.operands
[2].negative
,
13038 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13040 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13041 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13042 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13043 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13049 if (!inst
.operands
[2].present
)
13050 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13052 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13053 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13054 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13057 inst
.instruction
|= inst
.operands
[0].reg
;
13058 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13059 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13060 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13066 unsigned Rd
, Rn
, Rm
;
13068 Rd
= inst
.operands
[0].reg
;
13069 Rn
= inst
.operands
[1].reg
;
13070 Rm
= inst
.operands
[2].reg
;
13072 reject_bad_reg (Rd
);
13073 reject_bad_reg (Rn
);
13074 reject_bad_reg (Rm
);
13076 inst
.instruction
|= Rd
<< 8;
13077 inst
.instruction
|= Rn
<< 16;
13078 inst
.instruction
|= Rm
;
13079 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13087 Rd
= inst
.operands
[0].reg
;
13088 Rm
= inst
.operands
[1].reg
;
13090 reject_bad_reg (Rd
);
13091 reject_bad_reg (Rm
);
13093 if (inst
.instruction
<= 0xffff
13094 && inst
.size_req
!= 4
13095 && Rd
<= 7 && Rm
<= 7
13096 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13098 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13099 inst
.instruction
|= Rd
;
13100 inst
.instruction
|= Rm
<< 3;
13102 else if (unified_syntax
)
13104 if (inst
.instruction
<= 0xffff)
13105 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13106 inst
.instruction
|= Rd
<< 8;
13107 inst
.instruction
|= Rm
;
13108 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13112 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13113 _("Thumb encoding does not support rotation"));
13114 constraint (1, BAD_HIREG
);
13121 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13130 half
= (inst
.instruction
& 0x10) != 0;
13131 set_it_insn_type_last ();
13132 constraint (inst
.operands
[0].immisreg
,
13133 _("instruction requires register index"));
13135 Rn
= inst
.operands
[0].reg
;
13136 Rm
= inst
.operands
[0].imm
;
13138 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13139 constraint (Rn
== REG_SP
, BAD_SP
);
13140 reject_bad_reg (Rm
);
13142 constraint (!half
&& inst
.operands
[0].shifted
,
13143 _("instruction does not allow shifted index"));
13144 inst
.instruction
|= (Rn
<< 16) | Rm
;
13150 if (!inst
.operands
[0].present
)
13151 inst
.operands
[0].imm
= 0;
13153 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13155 constraint (inst
.size_req
== 2,
13156 _("immediate value out of range"));
13157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13158 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13159 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13163 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13164 inst
.instruction
|= inst
.operands
[0].imm
;
13167 set_it_insn_type (NEUTRAL_IT_INSN
);
13174 do_t_ssat_usat (0);
13182 Rd
= inst
.operands
[0].reg
;
13183 Rn
= inst
.operands
[2].reg
;
13185 reject_bad_reg (Rd
);
13186 reject_bad_reg (Rn
);
13188 inst
.instruction
|= Rd
<< 8;
13189 inst
.instruction
|= inst
.operands
[1].imm
;
13190 inst
.instruction
|= Rn
<< 16;
13193 /* Neon instruction encoder helpers. */
13195 /* Encodings for the different types for various Neon opcodes. */
13197 /* An "invalid" code for the following tables. */
13200 struct neon_tab_entry
13203 unsigned float_or_poly
;
13204 unsigned scalar_or_imm
;
13207 /* Map overloaded Neon opcodes to their respective encodings. */
13208 #define NEON_ENC_TAB \
13209 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13210 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13211 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13212 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13213 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13214 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13215 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13216 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13217 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13218 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13219 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13220 /* Register variants of the following two instructions are encoded as
13221 vcge / vcgt with the operands reversed. */ \
13222 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13223 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13224 X(vfma, N_INV, 0x0000c10, N_INV), \
13225 X(vfms, N_INV, 0x0200c10, N_INV), \
13226 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13227 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13228 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13229 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13230 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13231 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13232 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13233 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13234 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13235 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13236 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13237 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13238 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13239 X(vshl, 0x0000400, N_INV, 0x0800510), \
13240 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13241 X(vand, 0x0000110, N_INV, 0x0800030), \
13242 X(vbic, 0x0100110, N_INV, 0x0800030), \
13243 X(veor, 0x1000110, N_INV, N_INV), \
13244 X(vorn, 0x0300110, N_INV, 0x0800010), \
13245 X(vorr, 0x0200110, N_INV, 0x0800010), \
13246 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13247 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13248 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13249 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13250 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13251 X(vst1, 0x0000000, 0x0800000, N_INV), \
13252 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13253 X(vst2, 0x0000100, 0x0800100, N_INV), \
13254 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13255 X(vst3, 0x0000200, 0x0800200, N_INV), \
13256 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13257 X(vst4, 0x0000300, 0x0800300, N_INV), \
13258 X(vmovn, 0x1b20200, N_INV, N_INV), \
13259 X(vtrn, 0x1b20080, N_INV, N_INV), \
13260 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13261 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13262 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13263 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13264 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13265 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13266 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13267 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13268 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13269 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13270 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13271 X(vseleq, 0xe000a00, N_INV, N_INV), \
13272 X(vselvs, 0xe100a00, N_INV, N_INV), \
13273 X(vselge, 0xe200a00, N_INV, N_INV), \
13274 X(vselgt, 0xe300a00, N_INV, N_INV), \
13275 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13276 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13277 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13278 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13279 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13280 X(aes, 0x3b00300, N_INV, N_INV), \
13281 X(sha3op, 0x2000c00, N_INV, N_INV), \
13282 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13283 X(sha2op, 0x3ba0380, N_INV, N_INV)
13287 #define X(OPC,I,F,S) N_MNEM_##OPC
13292 static const struct neon_tab_entry neon_enc_tab
[] =
13294 #define X(OPC,I,F,S) { (I), (F), (S) }
13299 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13300 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13301 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13302 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13303 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13304 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13305 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13306 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13307 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13308 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13309 #define NEON_ENC_SINGLE_(X) \
13310 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13311 #define NEON_ENC_DOUBLE_(X) \
13312 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13313 #define NEON_ENC_FPV8_(X) \
13314 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13316 #define NEON_ENCODE(type, inst) \
13319 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13320 inst.is_neon = 1; \
13324 #define check_neon_suffixes \
13327 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13329 as_bad (_("invalid neon suffix for non neon instruction")); \
13335 /* Define shapes for instruction operands. The following mnemonic characters
13336 are used in this table:
13338 F - VFP S<n> register
13339 D - Neon D<n> register
13340 Q - Neon Q<n> register
13344 L - D<n> register list
13346 This table is used to generate various data:
13347 - enumerations of the form NS_DDR to be used as arguments to
13349 - a table classifying shapes into single, double, quad, mixed.
13350 - a table used to drive neon_select_shape. */
13352 #define NEON_SHAPE_DEF \
13353 X(3, (D, D, D), DOUBLE), \
13354 X(3, (Q, Q, Q), QUAD), \
13355 X(3, (D, D, I), DOUBLE), \
13356 X(3, (Q, Q, I), QUAD), \
13357 X(3, (D, D, S), DOUBLE), \
13358 X(3, (Q, Q, S), QUAD), \
13359 X(2, (D, D), DOUBLE), \
13360 X(2, (Q, Q), QUAD), \
13361 X(2, (D, S), DOUBLE), \
13362 X(2, (Q, S), QUAD), \
13363 X(2, (D, R), DOUBLE), \
13364 X(2, (Q, R), QUAD), \
13365 X(2, (D, I), DOUBLE), \
13366 X(2, (Q, I), QUAD), \
13367 X(3, (D, L, D), DOUBLE), \
13368 X(2, (D, Q), MIXED), \
13369 X(2, (Q, D), MIXED), \
13370 X(3, (D, Q, I), MIXED), \
13371 X(3, (Q, D, I), MIXED), \
13372 X(3, (Q, D, D), MIXED), \
13373 X(3, (D, Q, Q), MIXED), \
13374 X(3, (Q, Q, D), MIXED), \
13375 X(3, (Q, D, S), MIXED), \
13376 X(3, (D, Q, S), MIXED), \
13377 X(4, (D, D, D, I), DOUBLE), \
13378 X(4, (Q, Q, Q, I), QUAD), \
13379 X(4, (D, D, S, I), DOUBLE), \
13380 X(4, (Q, Q, S, I), QUAD), \
13381 X(2, (F, F), SINGLE), \
13382 X(3, (F, F, F), SINGLE), \
13383 X(2, (F, I), SINGLE), \
13384 X(2, (F, D), MIXED), \
13385 X(2, (D, F), MIXED), \
13386 X(3, (F, F, I), MIXED), \
13387 X(4, (R, R, F, F), SINGLE), \
13388 X(4, (F, F, R, R), SINGLE), \
13389 X(3, (D, R, R), DOUBLE), \
13390 X(3, (R, R, D), DOUBLE), \
13391 X(2, (S, R), SINGLE), \
13392 X(2, (R, S), SINGLE), \
13393 X(2, (F, R), SINGLE), \
13394 X(2, (R, F), SINGLE), \
13395 /* Half float shape supported so far. */\
13396 X (2, (H, D), MIXED), \
13397 X (2, (D, H), MIXED), \
13398 X (2, (H, F), MIXED), \
13399 X (2, (F, H), MIXED), \
13400 X (2, (H, H), HALF), \
13401 X (2, (H, R), HALF), \
13402 X (2, (R, H), HALF), \
13403 X (2, (H, I), HALF), \
13404 X (3, (H, H, H), HALF), \
13405 X (3, (H, F, I), MIXED), \
13406 X (3, (F, H, I), MIXED)
13408 #define S2(A,B) NS_##A##B
13409 #define S3(A,B,C) NS_##A##B##C
13410 #define S4(A,B,C,D) NS_##A##B##C##D
13412 #define X(N, L, C) S##N L
13425 enum neon_shape_class
13434 #define X(N, L, C) SC_##C
13436 static enum neon_shape_class neon_shape_class
[] =
13455 /* Register widths of above. */
13456 static unsigned neon_shape_el_size
[] =
13468 struct neon_shape_info
13471 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13474 #define S2(A,B) { SE_##A, SE_##B }
13475 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13476 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13478 #define X(N, L, C) { N, S##N L }
13480 static struct neon_shape_info neon_shape_tab
[] =
13490 /* Bit masks used in type checking given instructions.
13491 'N_EQK' means the type must be the same as (or based on in some way) the key
13492 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13493 set, various other bits can be set as well in order to modify the meaning of
13494 the type constraint. */
13496 enum neon_type_mask
13520 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13521 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13522 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13523 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13524 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13525 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13526 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13527 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13528 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13529 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13530 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13532 N_MAX_NONSPECIAL
= N_P64
13535 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13537 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13538 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13539 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13540 #define N_S_32 (N_S8 | N_S16 | N_S32)
13541 #define N_F_16_32 (N_F16 | N_F32)
13542 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13543 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13544 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13545 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13547 /* Pass this as the first type argument to neon_check_type to ignore types
13549 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13551 /* Select a "shape" for the current instruction (describing register types or
13552 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13553 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13554 function of operand parsing, so this function doesn't need to be called.
13555 Shapes should be listed in order of decreasing length. */
13557 static enum neon_shape
13558 neon_select_shape (enum neon_shape shape
, ...)
13561 enum neon_shape first_shape
= shape
;
13563 /* Fix missing optional operands. FIXME: we don't know at this point how
13564 many arguments we should have, so this makes the assumption that we have
13565 > 1. This is true of all current Neon opcodes, I think, but may not be
13566 true in the future. */
13567 if (!inst
.operands
[1].present
)
13568 inst
.operands
[1] = inst
.operands
[0];
13570 va_start (ap
, shape
);
13572 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13577 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13579 if (!inst
.operands
[j
].present
)
13585 switch (neon_shape_tab
[shape
].el
[j
])
13587 /* If a .f16, .16, .u16, .s16 type specifier is given over
13588 a VFP single precision register operand, it's essentially
13589 means only half of the register is used.
13591 If the type specifier is given after the mnemonics, the
13592 information is stored in inst.vectype. If the type specifier
13593 is given after register operand, the information is stored
13594 in inst.operands[].vectype.
13596 When there is only one type specifier, and all the register
13597 operands are the same type of hardware register, the type
13598 specifier applies to all register operands.
13600 If no type specifier is given, the shape is inferred from
13601 operand information.
13604 vadd.f16 s0, s1, s2: NS_HHH
13605 vabs.f16 s0, s1: NS_HH
13606 vmov.f16 s0, r1: NS_HR
13607 vmov.f16 r0, s1: NS_RH
13608 vcvt.f16 r0, s1: NS_RH
13609 vcvt.f16.s32 s2, s2, #29: NS_HFI
13610 vcvt.f16.s32 s2, s2: NS_HF
13613 if (!(inst
.operands
[j
].isreg
13614 && inst
.operands
[j
].isvec
13615 && inst
.operands
[j
].issingle
13616 && !inst
.operands
[j
].isquad
13617 && ((inst
.vectype
.elems
== 1
13618 && inst
.vectype
.el
[0].size
== 16)
13619 || (inst
.vectype
.elems
> 1
13620 && inst
.vectype
.el
[j
].size
== 16)
13621 || (inst
.vectype
.elems
== 0
13622 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13623 && inst
.operands
[j
].vectype
.size
== 16))))
13628 if (!(inst
.operands
[j
].isreg
13629 && inst
.operands
[j
].isvec
13630 && inst
.operands
[j
].issingle
13631 && !inst
.operands
[j
].isquad
13632 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13633 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13634 || (inst
.vectype
.elems
== 0
13635 && (inst
.operands
[j
].vectype
.size
== 32
13636 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13641 if (!(inst
.operands
[j
].isreg
13642 && inst
.operands
[j
].isvec
13643 && !inst
.operands
[j
].isquad
13644 && !inst
.operands
[j
].issingle
))
13649 if (!(inst
.operands
[j
].isreg
13650 && !inst
.operands
[j
].isvec
))
13655 if (!(inst
.operands
[j
].isreg
13656 && inst
.operands
[j
].isvec
13657 && inst
.operands
[j
].isquad
13658 && !inst
.operands
[j
].issingle
))
13663 if (!(!inst
.operands
[j
].isreg
13664 && !inst
.operands
[j
].isscalar
))
13669 if (!(!inst
.operands
[j
].isreg
13670 && inst
.operands
[j
].isscalar
))
13680 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13681 /* We've matched all the entries in the shape table, and we don't
13682 have any left over operands which have not been matched. */
13688 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13689 first_error (_("invalid instruction shape"));
13694 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13695 means the Q bit should be set). */
13698 neon_quad (enum neon_shape shape
)
13700 return neon_shape_class
[shape
] == SC_QUAD
;
13704 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13707 /* Allow modification to be made to types which are constrained to be
13708 based on the key element, based on bits set alongside N_EQK. */
13709 if ((typebits
& N_EQK
) != 0)
13711 if ((typebits
& N_HLF
) != 0)
13713 else if ((typebits
& N_DBL
) != 0)
13715 if ((typebits
& N_SGN
) != 0)
13716 *g_type
= NT_signed
;
13717 else if ((typebits
& N_UNS
) != 0)
13718 *g_type
= NT_unsigned
;
13719 else if ((typebits
& N_INT
) != 0)
13720 *g_type
= NT_integer
;
13721 else if ((typebits
& N_FLT
) != 0)
13722 *g_type
= NT_float
;
13723 else if ((typebits
& N_SIZ
) != 0)
13724 *g_type
= NT_untyped
;
13728 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13729 operand type, i.e. the single type specified in a Neon instruction when it
13730 is the only one given. */
13732 static struct neon_type_el
13733 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13735 struct neon_type_el dest
= *key
;
13737 gas_assert ((thisarg
& N_EQK
) != 0);
13739 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13744 /* Convert Neon type and size into compact bitmask representation. */
13746 static enum neon_type_mask
13747 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13754 case 8: return N_8
;
13755 case 16: return N_16
;
13756 case 32: return N_32
;
13757 case 64: return N_64
;
13765 case 8: return N_I8
;
13766 case 16: return N_I16
;
13767 case 32: return N_I32
;
13768 case 64: return N_I64
;
13776 case 16: return N_F16
;
13777 case 32: return N_F32
;
13778 case 64: return N_F64
;
13786 case 8: return N_P8
;
13787 case 16: return N_P16
;
13788 case 64: return N_P64
;
13796 case 8: return N_S8
;
13797 case 16: return N_S16
;
13798 case 32: return N_S32
;
13799 case 64: return N_S64
;
13807 case 8: return N_U8
;
13808 case 16: return N_U16
;
13809 case 32: return N_U32
;
13810 case 64: return N_U64
;
13821 /* Convert compact Neon bitmask type representation to a type and size. Only
13822 handles the case where a single bit is set in the mask. */
13825 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13826 enum neon_type_mask mask
)
13828 if ((mask
& N_EQK
) != 0)
13831 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13833 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13835 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13837 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13842 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13844 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13845 *type
= NT_unsigned
;
13846 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13847 *type
= NT_integer
;
13848 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13849 *type
= NT_untyped
;
13850 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13852 else if ((mask
& (N_F_ALL
)) != 0)
13860 /* Modify a bitmask of allowed types. This is only needed for type
13864 modify_types_allowed (unsigned allowed
, unsigned mods
)
13867 enum neon_el_type type
;
13873 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13875 if (el_type_of_type_chk (&type
, &size
,
13876 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13878 neon_modify_type_size (mods
, &type
, &size
);
13879 destmask
|= type_chk_of_el_type (type
, size
);
13886 /* Check type and return type classification.
13887 The manual states (paraphrase): If one datatype is given, it indicates the
13889 - the second operand, if there is one
13890 - the operand, if there is no second operand
13891 - the result, if there are no operands.
13892 This isn't quite good enough though, so we use a concept of a "key" datatype
13893 which is set on a per-instruction basis, which is the one which matters when
13894 only one data type is written.
13895 Note: this function has side-effects (e.g. filling in missing operands). All
13896 Neon instructions should call it before performing bit encoding. */
13898 static struct neon_type_el
13899 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13902 unsigned i
, pass
, key_el
= 0;
13903 unsigned types
[NEON_MAX_TYPE_ELS
];
13904 enum neon_el_type k_type
= NT_invtype
;
13905 unsigned k_size
= -1u;
13906 struct neon_type_el badtype
= {NT_invtype
, -1};
13907 unsigned key_allowed
= 0;
13909 /* Optional registers in Neon instructions are always (not) in operand 1.
13910 Fill in the missing operand here, if it was omitted. */
13911 if (els
> 1 && !inst
.operands
[1].present
)
13912 inst
.operands
[1] = inst
.operands
[0];
13914 /* Suck up all the varargs. */
13916 for (i
= 0; i
< els
; i
++)
13918 unsigned thisarg
= va_arg (ap
, unsigned);
13919 if (thisarg
== N_IGNORE_TYPE
)
13924 types
[i
] = thisarg
;
13925 if ((thisarg
& N_KEY
) != 0)
13930 if (inst
.vectype
.elems
> 0)
13931 for (i
= 0; i
< els
; i
++)
13932 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13934 first_error (_("types specified in both the mnemonic and operands"));
13938 /* Duplicate inst.vectype elements here as necessary.
13939 FIXME: No idea if this is exactly the same as the ARM assembler,
13940 particularly when an insn takes one register and one non-register
13942 if (inst
.vectype
.elems
== 1 && els
> 1)
13945 inst
.vectype
.elems
= els
;
13946 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13947 for (j
= 0; j
< els
; j
++)
13949 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13952 else if (inst
.vectype
.elems
== 0 && els
> 0)
13955 /* No types were given after the mnemonic, so look for types specified
13956 after each operand. We allow some flexibility here; as long as the
13957 "key" operand has a type, we can infer the others. */
13958 for (j
= 0; j
< els
; j
++)
13959 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13960 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13962 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13964 for (j
= 0; j
< els
; j
++)
13965 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13966 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13971 first_error (_("operand types can't be inferred"));
13975 else if (inst
.vectype
.elems
!= els
)
13977 first_error (_("type specifier has the wrong number of parts"));
13981 for (pass
= 0; pass
< 2; pass
++)
13983 for (i
= 0; i
< els
; i
++)
13985 unsigned thisarg
= types
[i
];
13986 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13987 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13988 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13989 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13991 /* Decay more-specific signed & unsigned types to sign-insensitive
13992 integer types if sign-specific variants are unavailable. */
13993 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13994 && (types_allowed
& N_SU_ALL
) == 0)
13995 g_type
= NT_integer
;
13997 /* If only untyped args are allowed, decay any more specific types to
13998 them. Some instructions only care about signs for some element
13999 sizes, so handle that properly. */
14000 if (((types_allowed
& N_UNT
) == 0)
14001 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14002 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14003 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14004 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14005 g_type
= NT_untyped
;
14009 if ((thisarg
& N_KEY
) != 0)
14013 key_allowed
= thisarg
& ~N_KEY
;
14015 /* Check architecture constraint on FP16 extension. */
14017 && k_type
== NT_float
14018 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14020 inst
.error
= _(BAD_FP16
);
14027 if ((thisarg
& N_VFP
) != 0)
14029 enum neon_shape_el regshape
;
14030 unsigned regwidth
, match
;
14032 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14035 first_error (_("invalid instruction shape"));
14038 regshape
= neon_shape_tab
[ns
].el
[i
];
14039 regwidth
= neon_shape_el_size
[regshape
];
14041 /* In VFP mode, operands must match register widths. If we
14042 have a key operand, use its width, else use the width of
14043 the current operand. */
14049 /* FP16 will use a single precision register. */
14050 if (regwidth
== 32 && match
== 16)
14052 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14056 inst
.error
= _(BAD_FP16
);
14061 if (regwidth
!= match
)
14063 first_error (_("operand size must match register width"));
14068 if ((thisarg
& N_EQK
) == 0)
14070 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14072 if ((given_type
& types_allowed
) == 0)
14074 first_error (_("bad type in Neon instruction"));
14080 enum neon_el_type mod_k_type
= k_type
;
14081 unsigned mod_k_size
= k_size
;
14082 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14083 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14085 first_error (_("inconsistent types in Neon instruction"));
14093 return inst
.vectype
.el
[key_el
];
14096 /* Neon-style VFP instruction forwarding. */
14098 /* Thumb VFP instructions have 0xE in the condition field. */
14101 do_vfp_cond_or_thumb (void)
14106 inst
.instruction
|= 0xe0000000;
14108 inst
.instruction
|= inst
.cond
<< 28;
14111 /* Look up and encode a simple mnemonic, for use as a helper function for the
14112 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14113 etc. It is assumed that operand parsing has already been done, and that the
14114 operands are in the form expected by the given opcode (this isn't necessarily
14115 the same as the form in which they were parsed, hence some massaging must
14116 take place before this function is called).
14117 Checks current arch version against that in the looked-up opcode. */
14120 do_vfp_nsyn_opcode (const char *opname
)
14122 const struct asm_opcode
*opcode
;
14124 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14129 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14130 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14137 inst
.instruction
= opcode
->tvalue
;
14138 opcode
->tencode ();
14142 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14143 opcode
->aencode ();
14148 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14150 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14152 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14155 do_vfp_nsyn_opcode ("fadds");
14157 do_vfp_nsyn_opcode ("fsubs");
14159 /* ARMv8.2 fp16 instruction. */
14161 do_scalar_fp16_v82_encode ();
14166 do_vfp_nsyn_opcode ("faddd");
14168 do_vfp_nsyn_opcode ("fsubd");
14172 /* Check operand types to see if this is a VFP instruction, and if so call
14176 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14178 enum neon_shape rs
;
14179 struct neon_type_el et
;
14184 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14185 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14189 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14190 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14191 N_F_ALL
| N_KEY
| N_VFP
);
14198 if (et
.type
!= NT_invtype
)
14209 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14211 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14213 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14216 do_vfp_nsyn_opcode ("fmacs");
14218 do_vfp_nsyn_opcode ("fnmacs");
14220 /* ARMv8.2 fp16 instruction. */
14222 do_scalar_fp16_v82_encode ();
14227 do_vfp_nsyn_opcode ("fmacd");
14229 do_vfp_nsyn_opcode ("fnmacd");
14234 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14236 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14238 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14241 do_vfp_nsyn_opcode ("ffmas");
14243 do_vfp_nsyn_opcode ("ffnmas");
14245 /* ARMv8.2 fp16 instruction. */
14247 do_scalar_fp16_v82_encode ();
14252 do_vfp_nsyn_opcode ("ffmad");
14254 do_vfp_nsyn_opcode ("ffnmad");
14259 do_vfp_nsyn_mul (enum neon_shape rs
)
14261 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14263 do_vfp_nsyn_opcode ("fmuls");
14265 /* ARMv8.2 fp16 instruction. */
14267 do_scalar_fp16_v82_encode ();
14270 do_vfp_nsyn_opcode ("fmuld");
14274 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14276 int is_neg
= (inst
.instruction
& 0x80) != 0;
14277 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14279 if (rs
== NS_FF
|| rs
== NS_HH
)
14282 do_vfp_nsyn_opcode ("fnegs");
14284 do_vfp_nsyn_opcode ("fabss");
14286 /* ARMv8.2 fp16 instruction. */
14288 do_scalar_fp16_v82_encode ();
14293 do_vfp_nsyn_opcode ("fnegd");
14295 do_vfp_nsyn_opcode ("fabsd");
14299 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14300 insns belong to Neon, and are handled elsewhere. */
14303 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14305 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14309 do_vfp_nsyn_opcode ("fldmdbs");
14311 do_vfp_nsyn_opcode ("fldmias");
14316 do_vfp_nsyn_opcode ("fstmdbs");
14318 do_vfp_nsyn_opcode ("fstmias");
14323 do_vfp_nsyn_sqrt (void)
14325 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14326 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14328 if (rs
== NS_FF
|| rs
== NS_HH
)
14330 do_vfp_nsyn_opcode ("fsqrts");
14332 /* ARMv8.2 fp16 instruction. */
14334 do_scalar_fp16_v82_encode ();
14337 do_vfp_nsyn_opcode ("fsqrtd");
14341 do_vfp_nsyn_div (void)
14343 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14344 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14345 N_F_ALL
| N_KEY
| N_VFP
);
14347 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14349 do_vfp_nsyn_opcode ("fdivs");
14351 /* ARMv8.2 fp16 instruction. */
14353 do_scalar_fp16_v82_encode ();
14356 do_vfp_nsyn_opcode ("fdivd");
14360 do_vfp_nsyn_nmul (void)
14362 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14363 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14364 N_F_ALL
| N_KEY
| N_VFP
);
14366 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14368 NEON_ENCODE (SINGLE
, inst
);
14369 do_vfp_sp_dyadic ();
14371 /* ARMv8.2 fp16 instruction. */
14373 do_scalar_fp16_v82_encode ();
14377 NEON_ENCODE (DOUBLE
, inst
);
14378 do_vfp_dp_rd_rn_rm ();
14380 do_vfp_cond_or_thumb ();
14385 do_vfp_nsyn_cmp (void)
14387 enum neon_shape rs
;
14388 if (inst
.operands
[1].isreg
)
14390 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14391 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14393 if (rs
== NS_FF
|| rs
== NS_HH
)
14395 NEON_ENCODE (SINGLE
, inst
);
14396 do_vfp_sp_monadic ();
14400 NEON_ENCODE (DOUBLE
, inst
);
14401 do_vfp_dp_rd_rm ();
14406 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14407 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14409 switch (inst
.instruction
& 0x0fffffff)
14412 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14415 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14421 if (rs
== NS_FI
|| rs
== NS_HI
)
14423 NEON_ENCODE (SINGLE
, inst
);
14424 do_vfp_sp_compare_z ();
14428 NEON_ENCODE (DOUBLE
, inst
);
14432 do_vfp_cond_or_thumb ();
14434 /* ARMv8.2 fp16 instruction. */
14435 if (rs
== NS_HI
|| rs
== NS_HH
)
14436 do_scalar_fp16_v82_encode ();
14440 nsyn_insert_sp (void)
14442 inst
.operands
[1] = inst
.operands
[0];
14443 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14444 inst
.operands
[0].reg
= REG_SP
;
14445 inst
.operands
[0].isreg
= 1;
14446 inst
.operands
[0].writeback
= 1;
14447 inst
.operands
[0].present
= 1;
14451 do_vfp_nsyn_push (void)
14455 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14456 _("register list must contain at least 1 and at most 16 "
14459 if (inst
.operands
[1].issingle
)
14460 do_vfp_nsyn_opcode ("fstmdbs");
14462 do_vfp_nsyn_opcode ("fstmdbd");
14466 do_vfp_nsyn_pop (void)
14470 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14471 _("register list must contain at least 1 and at most 16 "
14474 if (inst
.operands
[1].issingle
)
14475 do_vfp_nsyn_opcode ("fldmias");
14477 do_vfp_nsyn_opcode ("fldmiad");
14480 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14481 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14484 neon_dp_fixup (struct arm_it
* insn
)
14486 unsigned int i
= insn
->instruction
;
14491 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14502 insn
->instruction
= i
;
14505 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14509 neon_logbits (unsigned x
)
14511 return ffs (x
) - 4;
14514 #define LOW4(R) ((R) & 0xf)
14515 #define HI1(R) (((R) >> 4) & 1)
14517 /* Encode insns with bit pattern:
14519 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14520 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14522 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14523 different meaning for some instruction. */
14526 neon_three_same (int isquad
, int ubit
, int size
)
14528 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14529 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14530 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14531 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14532 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14533 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14534 inst
.instruction
|= (isquad
!= 0) << 6;
14535 inst
.instruction
|= (ubit
!= 0) << 24;
14537 inst
.instruction
|= neon_logbits (size
) << 20;
14539 neon_dp_fixup (&inst
);
14542 /* Encode instructions of the form:
14544 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14545 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14547 Don't write size if SIZE == -1. */
14550 neon_two_same (int qbit
, int ubit
, int size
)
14552 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14553 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14554 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14555 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14556 inst
.instruction
|= (qbit
!= 0) << 6;
14557 inst
.instruction
|= (ubit
!= 0) << 24;
14560 inst
.instruction
|= neon_logbits (size
) << 18;
14562 neon_dp_fixup (&inst
);
14565 /* Neon instruction encoders, in approximate order of appearance. */
14568 do_neon_dyadic_i_su (void)
14570 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14571 struct neon_type_el et
= neon_check_type (3, rs
,
14572 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14573 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14577 do_neon_dyadic_i64_su (void)
14579 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14580 struct neon_type_el et
= neon_check_type (3, rs
,
14581 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14582 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14586 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14589 unsigned size
= et
.size
>> 3;
14590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14594 inst
.instruction
|= (isquad
!= 0) << 6;
14595 inst
.instruction
|= immbits
<< 16;
14596 inst
.instruction
|= (size
>> 3) << 7;
14597 inst
.instruction
|= (size
& 0x7) << 19;
14599 inst
.instruction
|= (uval
!= 0) << 24;
14601 neon_dp_fixup (&inst
);
14605 do_neon_shl_imm (void)
14607 if (!inst
.operands
[2].isreg
)
14609 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14610 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14611 int imm
= inst
.operands
[2].imm
;
14613 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14614 _("immediate out of range for shift"));
14615 NEON_ENCODE (IMMED
, inst
);
14616 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14620 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14621 struct neon_type_el et
= neon_check_type (3, rs
,
14622 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14625 /* VSHL/VQSHL 3-register variants have syntax such as:
14627 whereas other 3-register operations encoded by neon_three_same have
14630 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14632 tmp
= inst
.operands
[2].reg
;
14633 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14634 inst
.operands
[1].reg
= tmp
;
14635 NEON_ENCODE (INTEGER
, inst
);
14636 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14641 do_neon_qshl_imm (void)
14643 if (!inst
.operands
[2].isreg
)
14645 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14646 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14647 int imm
= inst
.operands
[2].imm
;
14649 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14650 _("immediate out of range for shift"));
14651 NEON_ENCODE (IMMED
, inst
);
14652 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14656 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14657 struct neon_type_el et
= neon_check_type (3, rs
,
14658 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14661 /* See note in do_neon_shl_imm. */
14662 tmp
= inst
.operands
[2].reg
;
14663 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14664 inst
.operands
[1].reg
= tmp
;
14665 NEON_ENCODE (INTEGER
, inst
);
14666 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14671 do_neon_rshl (void)
14673 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14674 struct neon_type_el et
= neon_check_type (3, rs
,
14675 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14678 tmp
= inst
.operands
[2].reg
;
14679 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14680 inst
.operands
[1].reg
= tmp
;
14681 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14685 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14687 /* Handle .I8 pseudo-instructions. */
14690 /* Unfortunately, this will make everything apart from zero out-of-range.
14691 FIXME is this the intended semantics? There doesn't seem much point in
14692 accepting .I8 if so. */
14693 immediate
|= immediate
<< 8;
14699 if (immediate
== (immediate
& 0x000000ff))
14701 *immbits
= immediate
;
14704 else if (immediate
== (immediate
& 0x0000ff00))
14706 *immbits
= immediate
>> 8;
14709 else if (immediate
== (immediate
& 0x00ff0000))
14711 *immbits
= immediate
>> 16;
14714 else if (immediate
== (immediate
& 0xff000000))
14716 *immbits
= immediate
>> 24;
14719 if ((immediate
& 0xffff) != (immediate
>> 16))
14720 goto bad_immediate
;
14721 immediate
&= 0xffff;
14724 if (immediate
== (immediate
& 0x000000ff))
14726 *immbits
= immediate
;
14729 else if (immediate
== (immediate
& 0x0000ff00))
14731 *immbits
= immediate
>> 8;
14736 first_error (_("immediate value out of range"));
14741 do_neon_logic (void)
14743 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14745 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14746 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14747 /* U bit and size field were set as part of the bitmask. */
14748 NEON_ENCODE (INTEGER
, inst
);
14749 neon_three_same (neon_quad (rs
), 0, -1);
14753 const int three_ops_form
= (inst
.operands
[2].present
14754 && !inst
.operands
[2].isreg
);
14755 const int immoperand
= (three_ops_form
? 2 : 1);
14756 enum neon_shape rs
= (three_ops_form
14757 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14758 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14759 struct neon_type_el et
= neon_check_type (2, rs
,
14760 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14761 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14765 if (et
.type
== NT_invtype
)
14768 if (three_ops_form
)
14769 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14770 _("first and second operands shall be the same register"));
14772 NEON_ENCODE (IMMED
, inst
);
14774 immbits
= inst
.operands
[immoperand
].imm
;
14777 /* .i64 is a pseudo-op, so the immediate must be a repeating
14779 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14780 inst
.operands
[immoperand
].reg
: 0))
14782 /* Set immbits to an invalid constant. */
14783 immbits
= 0xdeadbeef;
14790 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14794 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14798 /* Pseudo-instruction for VBIC. */
14799 neon_invert_size (&immbits
, 0, et
.size
);
14800 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14804 /* Pseudo-instruction for VORR. */
14805 neon_invert_size (&immbits
, 0, et
.size
);
14806 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14816 inst
.instruction
|= neon_quad (rs
) << 6;
14817 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14818 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14819 inst
.instruction
|= cmode
<< 8;
14820 neon_write_immbits (immbits
);
14822 neon_dp_fixup (&inst
);
14827 do_neon_bitfield (void)
14829 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14830 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14831 neon_three_same (neon_quad (rs
), 0, -1);
14835 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14838 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14839 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14841 if (et
.type
== NT_float
)
14843 NEON_ENCODE (FLOAT
, inst
);
14844 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14848 NEON_ENCODE (INTEGER
, inst
);
14849 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14854 do_neon_dyadic_if_su (void)
14856 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14860 do_neon_dyadic_if_su_d (void)
14862 /* This version only allow D registers, but that constraint is enforced during
14863 operand parsing so we don't need to do anything extra here. */
14864 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14868 do_neon_dyadic_if_i_d (void)
14870 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14871 affected if we specify unsigned args. */
14872 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14875 enum vfp_or_neon_is_neon_bits
14878 NEON_CHECK_ARCH
= 2,
14879 NEON_CHECK_ARCH8
= 4
14882 /* Call this function if an instruction which may have belonged to the VFP or
14883 Neon instruction sets, but turned out to be a Neon instruction (due to the
14884 operand types involved, etc.). We have to check and/or fix-up a couple of
14887 - Make sure the user hasn't attempted to make a Neon instruction
14889 - Alter the value in the condition code field if necessary.
14890 - Make sure that the arch supports Neon instructions.
14892 Which of these operations take place depends on bits from enum
14893 vfp_or_neon_is_neon_bits.
14895 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14896 current instruction's condition is COND_ALWAYS, the condition field is
14897 changed to inst.uncond_value. This is necessary because instructions shared
14898 between VFP and Neon may be conditional for the VFP variants only, and the
14899 unconditional Neon version must have, e.g., 0xF in the condition field. */
14902 vfp_or_neon_is_neon (unsigned check
)
14904 /* Conditions are always legal in Thumb mode (IT blocks). */
14905 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14907 if (inst
.cond
!= COND_ALWAYS
)
14909 first_error (_(BAD_COND
));
14912 if (inst
.uncond_value
!= -1)
14913 inst
.instruction
|= inst
.uncond_value
<< 28;
14916 if ((check
& NEON_CHECK_ARCH
)
14917 && !mark_feature_used (&fpu_neon_ext_v1
))
14919 first_error (_(BAD_FPU
));
14923 if ((check
& NEON_CHECK_ARCH8
)
14924 && !mark_feature_used (&fpu_neon_ext_armv8
))
14926 first_error (_(BAD_FPU
));
14934 do_neon_addsub_if_i (void)
14936 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14939 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14942 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14943 affected if we specify unsigned args. */
14944 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14947 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14949 V<op> A,B (A is operand 0, B is operand 2)
14954 so handle that case specially. */
14957 neon_exchange_operands (void)
14959 if (inst
.operands
[1].present
)
14961 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14963 /* Swap operands[1] and operands[2]. */
14964 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14965 inst
.operands
[1] = inst
.operands
[2];
14966 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14971 inst
.operands
[1] = inst
.operands
[2];
14972 inst
.operands
[2] = inst
.operands
[0];
14977 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14979 if (inst
.operands
[2].isreg
)
14982 neon_exchange_operands ();
14983 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14987 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14988 struct neon_type_el et
= neon_check_type (2, rs
,
14989 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14991 NEON_ENCODE (IMMED
, inst
);
14992 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14993 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14994 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14995 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14996 inst
.instruction
|= neon_quad (rs
) << 6;
14997 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14998 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15000 neon_dp_fixup (&inst
);
15007 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15011 do_neon_cmp_inv (void)
15013 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15019 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15022 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15023 scalars, which are encoded in 5 bits, M : Rm.
15024 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15025 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15029 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15031 unsigned regno
= NEON_SCALAR_REG (scalar
);
15032 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15037 if (regno
> 7 || elno
> 3)
15039 return regno
| (elno
<< 3);
15042 if (regno
> 15 || elno
> 1)
15044 return regno
| (elno
<< 4);
15048 first_error (_("scalar out of range for multiply instruction"));
15054 /* Encode multiply / multiply-accumulate scalar instructions. */
15057 neon_mul_mac (struct neon_type_el et
, int ubit
)
15061 /* Give a more helpful error message if we have an invalid type. */
15062 if (et
.type
== NT_invtype
)
15065 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15066 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15067 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15068 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15069 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15070 inst
.instruction
|= LOW4 (scalar
);
15071 inst
.instruction
|= HI1 (scalar
) << 5;
15072 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15073 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15074 inst
.instruction
|= (ubit
!= 0) << 24;
15076 neon_dp_fixup (&inst
);
15080 do_neon_mac_maybe_scalar (void)
15082 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15085 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15088 if (inst
.operands
[2].isscalar
)
15090 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15091 struct neon_type_el et
= neon_check_type (3, rs
,
15092 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15093 NEON_ENCODE (SCALAR
, inst
);
15094 neon_mul_mac (et
, neon_quad (rs
));
15098 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15099 affected if we specify unsigned args. */
15100 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15105 do_neon_fmac (void)
15107 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15110 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15113 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15119 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15120 struct neon_type_el et
= neon_check_type (3, rs
,
15121 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15122 neon_three_same (neon_quad (rs
), 0, et
.size
);
15125 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15126 same types as the MAC equivalents. The polynomial type for this instruction
15127 is encoded the same as the integer type. */
15132 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15135 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15138 if (inst
.operands
[2].isscalar
)
15139 do_neon_mac_maybe_scalar ();
15141 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15145 do_neon_qdmulh (void)
15147 if (inst
.operands
[2].isscalar
)
15149 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15150 struct neon_type_el et
= neon_check_type (3, rs
,
15151 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15152 NEON_ENCODE (SCALAR
, inst
);
15153 neon_mul_mac (et
, neon_quad (rs
));
15157 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15158 struct neon_type_el et
= neon_check_type (3, rs
,
15159 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15160 NEON_ENCODE (INTEGER
, inst
);
15161 /* The U bit (rounding) comes from bit mask. */
15162 neon_three_same (neon_quad (rs
), 0, et
.size
);
15167 do_neon_qrdmlah (void)
15169 /* Check we're on the correct architecture. */
15170 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15172 _("instruction form not available on this architecture.");
15173 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15175 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15176 record_feature_use (&fpu_neon_ext_v8_1
);
15179 if (inst
.operands
[2].isscalar
)
15181 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15182 struct neon_type_el et
= neon_check_type (3, rs
,
15183 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15184 NEON_ENCODE (SCALAR
, inst
);
15185 neon_mul_mac (et
, neon_quad (rs
));
15189 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15190 struct neon_type_el et
= neon_check_type (3, rs
,
15191 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15192 NEON_ENCODE (INTEGER
, inst
);
15193 /* The U bit (rounding) comes from bit mask. */
15194 neon_three_same (neon_quad (rs
), 0, et
.size
);
15199 do_neon_fcmp_absolute (void)
15201 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15202 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15203 N_F_16_32
| N_KEY
);
15204 /* Size field comes from bit mask. */
15205 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15209 do_neon_fcmp_absolute_inv (void)
15211 neon_exchange_operands ();
15212 do_neon_fcmp_absolute ();
15216 do_neon_step (void)
15218 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15219 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15220 N_F_16_32
| N_KEY
);
15221 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15225 do_neon_abs_neg (void)
15227 enum neon_shape rs
;
15228 struct neon_type_el et
;
15230 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15233 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15236 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15237 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15242 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15243 inst
.instruction
|= neon_quad (rs
) << 6;
15244 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15245 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15247 neon_dp_fixup (&inst
);
15253 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15254 struct neon_type_el et
= neon_check_type (2, rs
,
15255 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15256 int imm
= inst
.operands
[2].imm
;
15257 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15258 _("immediate out of range for insert"));
15259 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15265 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15266 struct neon_type_el et
= neon_check_type (2, rs
,
15267 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15268 int imm
= inst
.operands
[2].imm
;
15269 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15270 _("immediate out of range for insert"));
15271 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15275 do_neon_qshlu_imm (void)
15277 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15278 struct neon_type_el et
= neon_check_type (2, rs
,
15279 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15280 int imm
= inst
.operands
[2].imm
;
15281 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15282 _("immediate out of range for shift"));
15283 /* Only encodes the 'U present' variant of the instruction.
15284 In this case, signed types have OP (bit 8) set to 0.
15285 Unsigned types have OP set to 1. */
15286 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15287 /* The rest of the bits are the same as other immediate shifts. */
15288 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15292 do_neon_qmovn (void)
15294 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15295 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15296 /* Saturating move where operands can be signed or unsigned, and the
15297 destination has the same signedness. */
15298 NEON_ENCODE (INTEGER
, inst
);
15299 if (et
.type
== NT_unsigned
)
15300 inst
.instruction
|= 0xc0;
15302 inst
.instruction
|= 0x80;
15303 neon_two_same (0, 1, et
.size
/ 2);
15307 do_neon_qmovun (void)
15309 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15310 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15311 /* Saturating move with unsigned results. Operands must be signed. */
15312 NEON_ENCODE (INTEGER
, inst
);
15313 neon_two_same (0, 1, et
.size
/ 2);
15317 do_neon_rshift_sat_narrow (void)
15319 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15320 or unsigned. If operands are unsigned, results must also be unsigned. */
15321 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15322 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15323 int imm
= inst
.operands
[2].imm
;
15324 /* This gets the bounds check, size encoding and immediate bits calculation
15328 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15329 VQMOVN.I<size> <Dd>, <Qm>. */
15332 inst
.operands
[2].present
= 0;
15333 inst
.instruction
= N_MNEM_vqmovn
;
15338 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15339 _("immediate out of range"));
15340 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15344 do_neon_rshift_sat_narrow_u (void)
15346 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15347 or unsigned. If operands are unsigned, results must also be unsigned. */
15348 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15349 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15350 int imm
= inst
.operands
[2].imm
;
15351 /* This gets the bounds check, size encoding and immediate bits calculation
15355 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15356 VQMOVUN.I<size> <Dd>, <Qm>. */
15359 inst
.operands
[2].present
= 0;
15360 inst
.instruction
= N_MNEM_vqmovun
;
15365 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15366 _("immediate out of range"));
15367 /* FIXME: The manual is kind of unclear about what value U should have in
15368 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15370 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15374 do_neon_movn (void)
15376 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15377 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15378 NEON_ENCODE (INTEGER
, inst
);
15379 neon_two_same (0, 1, et
.size
/ 2);
15383 do_neon_rshift_narrow (void)
15385 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15386 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15387 int imm
= inst
.operands
[2].imm
;
15388 /* This gets the bounds check, size encoding and immediate bits calculation
15392 /* If immediate is zero then we are a pseudo-instruction for
15393 VMOVN.I<size> <Dd>, <Qm> */
15396 inst
.operands
[2].present
= 0;
15397 inst
.instruction
= N_MNEM_vmovn
;
15402 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15403 _("immediate out of range for narrowing operation"));
15404 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15408 do_neon_shll (void)
15410 /* FIXME: Type checking when lengthening. */
15411 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15412 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15413 unsigned imm
= inst
.operands
[2].imm
;
15415 if (imm
== et
.size
)
15417 /* Maximum shift variant. */
15418 NEON_ENCODE (INTEGER
, inst
);
15419 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15420 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15421 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15423 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15425 neon_dp_fixup (&inst
);
15429 /* A more-specific type check for non-max versions. */
15430 et
= neon_check_type (2, NS_QDI
,
15431 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15432 NEON_ENCODE (IMMED
, inst
);
15433 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15437 /* Check the various types for the VCVT instruction, and return which version
15438 the current instruction is. */
15440 #define CVT_FLAVOUR_VAR \
15441 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15442 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15443 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15444 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15445 /* Half-precision conversions. */ \
15446 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15447 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15448 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15449 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15450 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15451 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15452 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15453 Compared with single/double precision variants, only the co-processor \
15454 field is different, so the encoding flow is reused here. */ \
15455 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15456 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15457 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15458 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15459 /* VFP instructions. */ \
15460 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15461 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15462 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15463 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15464 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15465 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15466 /* VFP instructions with bitshift. */ \
15467 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15468 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15469 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15470 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15471 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15472 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15473 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15474 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15476 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15477 neon_cvt_flavour_##C,
15479 /* The different types of conversions we can do. */
15480 enum neon_cvt_flavour
15483 neon_cvt_flavour_invalid
,
15484 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15489 static enum neon_cvt_flavour
15490 get_neon_cvt_flavour (enum neon_shape rs
)
15492 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15493 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15494 if (et.type != NT_invtype) \
15496 inst.error = NULL; \
15497 return (neon_cvt_flavour_##C); \
15500 struct neon_type_el et
;
15501 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15502 || rs
== NS_FF
) ? N_VFP
: 0;
15503 /* The instruction versions which take an immediate take one register
15504 argument, which is extended to the width of the full register. Thus the
15505 "source" and "destination" registers must have the same width. Hack that
15506 here by making the size equal to the key (wider, in this case) operand. */
15507 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15511 return neon_cvt_flavour_invalid
;
15526 /* Neon-syntax VFP conversions. */
15529 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15531 const char *opname
= 0;
15533 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15534 || rs
== NS_FHI
|| rs
== NS_HFI
)
15536 /* Conversions with immediate bitshift. */
15537 const char *enc
[] =
15539 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15545 if (flavour
< (int) ARRAY_SIZE (enc
))
15547 opname
= enc
[flavour
];
15548 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15549 _("operands 0 and 1 must be the same register"));
15550 inst
.operands
[1] = inst
.operands
[2];
15551 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15556 /* Conversions without bitshift. */
15557 const char *enc
[] =
15559 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15565 if (flavour
< (int) ARRAY_SIZE (enc
))
15566 opname
= enc
[flavour
];
15570 do_vfp_nsyn_opcode (opname
);
15572 /* ARMv8.2 fp16 VCVT instruction. */
15573 if (flavour
== neon_cvt_flavour_s32_f16
15574 || flavour
== neon_cvt_flavour_u32_f16
15575 || flavour
== neon_cvt_flavour_f16_u32
15576 || flavour
== neon_cvt_flavour_f16_s32
)
15577 do_scalar_fp16_v82_encode ();
15581 do_vfp_nsyn_cvtz (void)
15583 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15584 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15585 const char *enc
[] =
15587 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15593 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15594 do_vfp_nsyn_opcode (enc
[flavour
]);
15598 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15599 enum neon_cvt_mode mode
)
15604 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15605 D register operands. */
15606 if (flavour
== neon_cvt_flavour_s32_f64
15607 || flavour
== neon_cvt_flavour_u32_f64
)
15608 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15611 if (flavour
== neon_cvt_flavour_s32_f16
15612 || flavour
== neon_cvt_flavour_u32_f16
)
15613 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15616 set_it_insn_type (OUTSIDE_IT_INSN
);
15620 case neon_cvt_flavour_s32_f64
:
15624 case neon_cvt_flavour_s32_f32
:
15628 case neon_cvt_flavour_s32_f16
:
15632 case neon_cvt_flavour_u32_f64
:
15636 case neon_cvt_flavour_u32_f32
:
15640 case neon_cvt_flavour_u32_f16
:
15645 first_error (_("invalid instruction shape"));
15651 case neon_cvt_mode_a
: rm
= 0; break;
15652 case neon_cvt_mode_n
: rm
= 1; break;
15653 case neon_cvt_mode_p
: rm
= 2; break;
15654 case neon_cvt_mode_m
: rm
= 3; break;
15655 default: first_error (_("invalid rounding mode")); return;
15658 NEON_ENCODE (FPV8
, inst
);
15659 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15660 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15661 inst
.instruction
|= sz
<< 8;
15663 /* ARMv8.2 fp16 VCVT instruction. */
15664 if (flavour
== neon_cvt_flavour_s32_f16
15665 ||flavour
== neon_cvt_flavour_u32_f16
)
15666 do_scalar_fp16_v82_encode ();
15667 inst
.instruction
|= op
<< 7;
15668 inst
.instruction
|= rm
<< 16;
15669 inst
.instruction
|= 0xf0000000;
15670 inst
.is_neon
= TRUE
;
15674 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15676 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15677 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15678 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15680 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15682 if (flavour
== neon_cvt_flavour_invalid
)
15685 /* PR11109: Handle round-to-zero for VCVT conversions. */
15686 if (mode
== neon_cvt_mode_z
15687 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15688 && (flavour
== neon_cvt_flavour_s16_f16
15689 || flavour
== neon_cvt_flavour_u16_f16
15690 || flavour
== neon_cvt_flavour_s32_f32
15691 || flavour
== neon_cvt_flavour_u32_f32
15692 || flavour
== neon_cvt_flavour_s32_f64
15693 || flavour
== neon_cvt_flavour_u32_f64
)
15694 && (rs
== NS_FD
|| rs
== NS_FF
))
15696 do_vfp_nsyn_cvtz ();
15700 /* ARMv8.2 fp16 VCVT conversions. */
15701 if (mode
== neon_cvt_mode_z
15702 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15703 && (flavour
== neon_cvt_flavour_s32_f16
15704 || flavour
== neon_cvt_flavour_u32_f16
)
15707 do_vfp_nsyn_cvtz ();
15708 do_scalar_fp16_v82_encode ();
15712 /* VFP rather than Neon conversions. */
15713 if (flavour
>= neon_cvt_flavour_first_fp
)
15715 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15716 do_vfp_nsyn_cvt (rs
, flavour
);
15718 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15729 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15730 0x0000100, 0x1000100, 0x0, 0x1000000};
15732 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15735 /* Fixed-point conversion with #0 immediate is encoded as an
15736 integer conversion. */
15737 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15739 NEON_ENCODE (IMMED
, inst
);
15740 if (flavour
!= neon_cvt_flavour_invalid
)
15741 inst
.instruction
|= enctab
[flavour
];
15742 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15743 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15744 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15745 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15746 inst
.instruction
|= neon_quad (rs
) << 6;
15747 inst
.instruction
|= 1 << 21;
15748 if (flavour
< neon_cvt_flavour_s16_f16
)
15750 inst
.instruction
|= 1 << 21;
15751 immbits
= 32 - inst
.operands
[2].imm
;
15752 inst
.instruction
|= immbits
<< 16;
15756 inst
.instruction
|= 3 << 20;
15757 immbits
= 16 - inst
.operands
[2].imm
;
15758 inst
.instruction
|= immbits
<< 16;
15759 inst
.instruction
&= ~(1 << 9);
15762 neon_dp_fixup (&inst
);
15768 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15770 NEON_ENCODE (FLOAT
, inst
);
15771 set_it_insn_type (OUTSIDE_IT_INSN
);
15773 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15776 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15777 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15778 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15779 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15780 inst
.instruction
|= neon_quad (rs
) << 6;
15781 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15782 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15783 inst
.instruction
|= mode
<< 8;
15784 if (flavour
== neon_cvt_flavour_u16_f16
15785 || flavour
== neon_cvt_flavour_s16_f16
)
15786 /* Mask off the original size bits and reencode them. */
15787 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15790 inst
.instruction
|= 0xfc000000;
15792 inst
.instruction
|= 0xf0000000;
15798 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15799 0x100, 0x180, 0x0, 0x080};
15801 NEON_ENCODE (INTEGER
, inst
);
15803 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15806 if (flavour
!= neon_cvt_flavour_invalid
)
15807 inst
.instruction
|= enctab
[flavour
];
15809 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15810 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15811 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15812 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15813 inst
.instruction
|= neon_quad (rs
) << 6;
15814 if (flavour
>= neon_cvt_flavour_s16_f16
15815 && flavour
<= neon_cvt_flavour_f16_u16
)
15816 /* Half precision. */
15817 inst
.instruction
|= 1 << 18;
15819 inst
.instruction
|= 2 << 18;
15821 neon_dp_fixup (&inst
);
15826 /* Half-precision conversions for Advanced SIMD -- neon. */
15831 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15833 as_bad (_("operand size must match register width"));
15838 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15840 as_bad (_("operand size must match register width"));
15845 inst
.instruction
= 0x3b60600;
15847 inst
.instruction
= 0x3b60700;
15849 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15850 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15851 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15852 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15853 neon_dp_fixup (&inst
);
15857 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15858 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15859 do_vfp_nsyn_cvt (rs
, flavour
);
15861 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15866 do_neon_cvtr (void)
15868 do_neon_cvt_1 (neon_cvt_mode_x
);
15874 do_neon_cvt_1 (neon_cvt_mode_z
);
15878 do_neon_cvta (void)
15880 do_neon_cvt_1 (neon_cvt_mode_a
);
15884 do_neon_cvtn (void)
15886 do_neon_cvt_1 (neon_cvt_mode_n
);
15890 do_neon_cvtp (void)
15892 do_neon_cvt_1 (neon_cvt_mode_p
);
15896 do_neon_cvtm (void)
15898 do_neon_cvt_1 (neon_cvt_mode_m
);
15902 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15905 mark_feature_used (&fpu_vfp_ext_armv8
);
15907 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15908 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15909 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15910 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15911 inst
.instruction
|= to
? 0x10000 : 0;
15912 inst
.instruction
|= t
? 0x80 : 0;
15913 inst
.instruction
|= is_double
? 0x100 : 0;
15914 do_vfp_cond_or_thumb ();
15918 do_neon_cvttb_1 (bfd_boolean t
)
15920 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15921 NS_DF
, NS_DH
, NS_NULL
);
15925 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15928 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15930 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15933 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15935 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15937 /* The VCVTB and VCVTT instructions with D-register operands
15938 don't work for SP only targets. */
15939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15943 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15945 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15947 /* The VCVTB and VCVTT instructions with D-register operands
15948 don't work for SP only targets. */
15949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15953 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15960 do_neon_cvtb (void)
15962 do_neon_cvttb_1 (FALSE
);
15967 do_neon_cvtt (void)
15969 do_neon_cvttb_1 (TRUE
);
15973 neon_move_immediate (void)
15975 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15976 struct neon_type_el et
= neon_check_type (2, rs
,
15977 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15978 unsigned immlo
, immhi
= 0, immbits
;
15979 int op
, cmode
, float_p
;
15981 constraint (et
.type
== NT_invtype
,
15982 _("operand size must be specified for immediate VMOV"));
15984 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15985 op
= (inst
.instruction
& (1 << 5)) != 0;
15987 immlo
= inst
.operands
[1].imm
;
15988 if (inst
.operands
[1].regisimm
)
15989 immhi
= inst
.operands
[1].reg
;
15991 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15992 _("immediate has bits set outside the operand size"));
15994 float_p
= inst
.operands
[1].immisfloat
;
15996 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15997 et
.size
, et
.type
)) == FAIL
)
15999 /* Invert relevant bits only. */
16000 neon_invert_size (&immlo
, &immhi
, et
.size
);
16001 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16002 with one or the other; those cases are caught by
16003 neon_cmode_for_move_imm. */
16005 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16006 &op
, et
.size
, et
.type
)) == FAIL
)
16008 first_error (_("immediate out of range"));
16013 inst
.instruction
&= ~(1 << 5);
16014 inst
.instruction
|= op
<< 5;
16016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16018 inst
.instruction
|= neon_quad (rs
) << 6;
16019 inst
.instruction
|= cmode
<< 8;
16021 neon_write_immbits (immbits
);
16027 if (inst
.operands
[1].isreg
)
16029 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16031 NEON_ENCODE (INTEGER
, inst
);
16032 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16034 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16035 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16036 inst
.instruction
|= neon_quad (rs
) << 6;
16040 NEON_ENCODE (IMMED
, inst
);
16041 neon_move_immediate ();
16044 neon_dp_fixup (&inst
);
16047 /* Encode instructions of form:
16049 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16050 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16053 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16055 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16056 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16057 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16058 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16059 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16060 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16061 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16062 inst
.instruction
|= neon_logbits (size
) << 20;
16064 neon_dp_fixup (&inst
);
16068 do_neon_dyadic_long (void)
16070 /* FIXME: Type checking for lengthening op. */
16071 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16072 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16073 neon_mixed_length (et
, et
.size
);
16077 do_neon_abal (void)
16079 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16080 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16081 neon_mixed_length (et
, et
.size
);
16085 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16087 if (inst
.operands
[2].isscalar
)
16089 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16090 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16091 NEON_ENCODE (SCALAR
, inst
);
16092 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16096 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16097 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16098 NEON_ENCODE (INTEGER
, inst
);
16099 neon_mixed_length (et
, et
.size
);
16104 do_neon_mac_maybe_scalar_long (void)
16106 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16110 do_neon_dyadic_wide (void)
16112 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16113 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16114 neon_mixed_length (et
, et
.size
);
16118 do_neon_dyadic_narrow (void)
16120 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16121 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16122 /* Operand sign is unimportant, and the U bit is part of the opcode,
16123 so force the operand type to integer. */
16124 et
.type
= NT_integer
;
16125 neon_mixed_length (et
, et
.size
/ 2);
16129 do_neon_mul_sat_scalar_long (void)
16131 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16135 do_neon_vmull (void)
16137 if (inst
.operands
[2].isscalar
)
16138 do_neon_mac_maybe_scalar_long ();
16141 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16142 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16144 if (et
.type
== NT_poly
)
16145 NEON_ENCODE (POLY
, inst
);
16147 NEON_ENCODE (INTEGER
, inst
);
16149 /* For polynomial encoding the U bit must be zero, and the size must
16150 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16151 obviously, as 0b10). */
16154 /* Check we're on the correct architecture. */
16155 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16157 _("Instruction form not available on this architecture.");
16162 neon_mixed_length (et
, et
.size
);
16169 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16170 struct neon_type_el et
= neon_check_type (3, rs
,
16171 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16172 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16174 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16175 _("shift out of range"));
16176 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16177 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16178 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16179 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16180 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16181 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16182 inst
.instruction
|= neon_quad (rs
) << 6;
16183 inst
.instruction
|= imm
<< 8;
16185 neon_dp_fixup (&inst
);
16191 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16192 struct neon_type_el et
= neon_check_type (2, rs
,
16193 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16194 unsigned op
= (inst
.instruction
>> 7) & 3;
16195 /* N (width of reversed regions) is encoded as part of the bitmask. We
16196 extract it here to check the elements to be reversed are smaller.
16197 Otherwise we'd get a reserved instruction. */
16198 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16199 gas_assert (elsize
!= 0);
16200 constraint (et
.size
>= elsize
,
16201 _("elements must be smaller than reversal region"));
16202 neon_two_same (neon_quad (rs
), 1, et
.size
);
16208 if (inst
.operands
[1].isscalar
)
16210 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16211 struct neon_type_el et
= neon_check_type (2, rs
,
16212 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16213 unsigned sizebits
= et
.size
>> 3;
16214 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16215 int logsize
= neon_logbits (et
.size
);
16216 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16218 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16221 NEON_ENCODE (SCALAR
, inst
);
16222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16223 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16224 inst
.instruction
|= LOW4 (dm
);
16225 inst
.instruction
|= HI1 (dm
) << 5;
16226 inst
.instruction
|= neon_quad (rs
) << 6;
16227 inst
.instruction
|= x
<< 17;
16228 inst
.instruction
|= sizebits
<< 16;
16230 neon_dp_fixup (&inst
);
16234 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16235 struct neon_type_el et
= neon_check_type (2, rs
,
16236 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16237 /* Duplicate ARM register to lanes of vector. */
16238 NEON_ENCODE (ARMREG
, inst
);
16241 case 8: inst
.instruction
|= 0x400000; break;
16242 case 16: inst
.instruction
|= 0x000020; break;
16243 case 32: inst
.instruction
|= 0x000000; break;
16246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16249 inst
.instruction
|= neon_quad (rs
) << 21;
16250 /* The encoding for this instruction is identical for the ARM and Thumb
16251 variants, except for the condition field. */
16252 do_vfp_cond_or_thumb ();
16256 /* VMOV has particularly many variations. It can be one of:
16257 0. VMOV<c><q> <Qd>, <Qm>
16258 1. VMOV<c><q> <Dd>, <Dm>
16259 (Register operations, which are VORR with Rm = Rn.)
16260 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16261 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16263 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16264 (ARM register to scalar.)
16265 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16266 (Two ARM registers to vector.)
16267 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16268 (Scalar to ARM register.)
16269 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16270 (Vector to two ARM registers.)
16271 8. VMOV.F32 <Sd>, <Sm>
16272 9. VMOV.F64 <Dd>, <Dm>
16273 (VFP register moves.)
16274 10. VMOV.F32 <Sd>, #imm
16275 11. VMOV.F64 <Dd>, #imm
16276 (VFP float immediate load.)
16277 12. VMOV <Rd>, <Sm>
16278 (VFP single to ARM reg.)
16279 13. VMOV <Sd>, <Rm>
16280 (ARM reg to VFP single.)
16281 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16282 (Two ARM regs to two VFP singles.)
16283 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16284 (Two VFP singles to two ARM regs.)
16286 These cases can be disambiguated using neon_select_shape, except cases 1/9
16287 and 3/11 which depend on the operand type too.
16289 All the encoded bits are hardcoded by this function.
16291 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16292 Cases 5, 7 may be used with VFPv2 and above.
16294 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16295 can specify a type where it doesn't make sense to, and is ignored). */
16300 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16301 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16302 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16303 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16304 struct neon_type_el et
;
16305 const char *ldconst
= 0;
16309 case NS_DD
: /* case 1/9. */
16310 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16311 /* It is not an error here if no type is given. */
16313 if (et
.type
== NT_float
&& et
.size
== 64)
16315 do_vfp_nsyn_opcode ("fcpyd");
16318 /* fall through. */
16320 case NS_QQ
: /* case 0/1. */
16322 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16324 /* The architecture manual I have doesn't explicitly state which
16325 value the U bit should have for register->register moves, but
16326 the equivalent VORR instruction has U = 0, so do that. */
16327 inst
.instruction
= 0x0200110;
16328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16332 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16333 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16334 inst
.instruction
|= neon_quad (rs
) << 6;
16336 neon_dp_fixup (&inst
);
16340 case NS_DI
: /* case 3/11. */
16341 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16343 if (et
.type
== NT_float
&& et
.size
== 64)
16345 /* case 11 (fconstd). */
16346 ldconst
= "fconstd";
16347 goto encode_fconstd
;
16349 /* fall through. */
16351 case NS_QI
: /* case 2/3. */
16352 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16354 inst
.instruction
= 0x0800010;
16355 neon_move_immediate ();
16356 neon_dp_fixup (&inst
);
16359 case NS_SR
: /* case 4. */
16361 unsigned bcdebits
= 0;
16363 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16364 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16366 /* .<size> is optional here, defaulting to .32. */
16367 if (inst
.vectype
.elems
== 0
16368 && inst
.operands
[0].vectype
.type
== NT_invtype
16369 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16371 inst
.vectype
.el
[0].type
= NT_untyped
;
16372 inst
.vectype
.el
[0].size
= 32;
16373 inst
.vectype
.elems
= 1;
16376 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16377 logsize
= neon_logbits (et
.size
);
16379 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16381 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16382 && et
.size
!= 32, _(BAD_FPU
));
16383 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16384 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16388 case 8: bcdebits
= 0x8; break;
16389 case 16: bcdebits
= 0x1; break;
16390 case 32: bcdebits
= 0x0; break;
16394 bcdebits
|= x
<< logsize
;
16396 inst
.instruction
= 0xe000b10;
16397 do_vfp_cond_or_thumb ();
16398 inst
.instruction
|= LOW4 (dn
) << 16;
16399 inst
.instruction
|= HI1 (dn
) << 7;
16400 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16401 inst
.instruction
|= (bcdebits
& 3) << 5;
16402 inst
.instruction
|= (bcdebits
>> 2) << 21;
16406 case NS_DRR
: /* case 5 (fmdrr). */
16407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16410 inst
.instruction
= 0xc400b10;
16411 do_vfp_cond_or_thumb ();
16412 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16414 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16415 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16418 case NS_RS
: /* case 6. */
16421 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16422 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16423 unsigned abcdebits
= 0;
16425 /* .<dt> is optional here, defaulting to .32. */
16426 if (inst
.vectype
.elems
== 0
16427 && inst
.operands
[0].vectype
.type
== NT_invtype
16428 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16430 inst
.vectype
.el
[0].type
= NT_untyped
;
16431 inst
.vectype
.el
[0].size
= 32;
16432 inst
.vectype
.elems
= 1;
16435 et
= neon_check_type (2, NS_NULL
,
16436 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16437 logsize
= neon_logbits (et
.size
);
16439 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16441 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16442 && et
.size
!= 32, _(BAD_FPU
));
16443 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16444 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16448 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16449 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16450 case 32: abcdebits
= 0x00; break;
16454 abcdebits
|= x
<< logsize
;
16455 inst
.instruction
= 0xe100b10;
16456 do_vfp_cond_or_thumb ();
16457 inst
.instruction
|= LOW4 (dn
) << 16;
16458 inst
.instruction
|= HI1 (dn
) << 7;
16459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16460 inst
.instruction
|= (abcdebits
& 3) << 5;
16461 inst
.instruction
|= (abcdebits
>> 2) << 21;
16465 case NS_RRD
: /* case 7 (fmrrd). */
16466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16469 inst
.instruction
= 0xc500b10;
16470 do_vfp_cond_or_thumb ();
16471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16472 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16473 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16474 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16477 case NS_FF
: /* case 8 (fcpys). */
16478 do_vfp_nsyn_opcode ("fcpys");
16482 case NS_FI
: /* case 10 (fconsts). */
16483 ldconst
= "fconsts";
16485 if (is_quarter_float (inst
.operands
[1].imm
))
16487 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16488 do_vfp_nsyn_opcode (ldconst
);
16490 /* ARMv8.2 fp16 vmov.f16 instruction. */
16492 do_scalar_fp16_v82_encode ();
16495 first_error (_("immediate out of range"));
16499 case NS_RF
: /* case 12 (fmrs). */
16500 do_vfp_nsyn_opcode ("fmrs");
16501 /* ARMv8.2 fp16 vmov.f16 instruction. */
16503 do_scalar_fp16_v82_encode ();
16507 case NS_FR
: /* case 13 (fmsr). */
16508 do_vfp_nsyn_opcode ("fmsr");
16509 /* ARMv8.2 fp16 vmov.f16 instruction. */
16511 do_scalar_fp16_v82_encode ();
16514 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16515 (one of which is a list), but we have parsed four. Do some fiddling to
16516 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16518 case NS_RRFF
: /* case 14 (fmrrs). */
16519 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16520 _("VFP registers must be adjacent"));
16521 inst
.operands
[2].imm
= 2;
16522 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16523 do_vfp_nsyn_opcode ("fmrrs");
16526 case NS_FFRR
: /* case 15 (fmsrr). */
16527 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16528 _("VFP registers must be adjacent"));
16529 inst
.operands
[1] = inst
.operands
[2];
16530 inst
.operands
[2] = inst
.operands
[3];
16531 inst
.operands
[0].imm
= 2;
16532 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16533 do_vfp_nsyn_opcode ("fmsrr");
16537 /* neon_select_shape has determined that the instruction
16538 shape is wrong and has already set the error message. */
16547 do_neon_rshift_round_imm (void)
16549 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16550 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16551 int imm
= inst
.operands
[2].imm
;
16553 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16556 inst
.operands
[2].present
= 0;
16561 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16562 _("immediate out of range for shift"));
16563 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16568 do_neon_movhf (void)
16570 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16571 constraint (rs
!= NS_HH
, _("invalid suffix"));
16573 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16576 do_vfp_sp_monadic ();
16579 inst
.instruction
|= 0xf0000000;
16583 do_neon_movl (void)
16585 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16586 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16587 unsigned sizebits
= et
.size
>> 3;
16588 inst
.instruction
|= sizebits
<< 19;
16589 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16595 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16596 struct neon_type_el et
= neon_check_type (2, rs
,
16597 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16598 NEON_ENCODE (INTEGER
, inst
);
16599 neon_two_same (neon_quad (rs
), 1, et
.size
);
16603 do_neon_zip_uzp (void)
16605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16606 struct neon_type_el et
= neon_check_type (2, rs
,
16607 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16608 if (rs
== NS_DD
&& et
.size
== 32)
16610 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16611 inst
.instruction
= N_MNEM_vtrn
;
16615 neon_two_same (neon_quad (rs
), 1, et
.size
);
16619 do_neon_sat_abs_neg (void)
16621 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16622 struct neon_type_el et
= neon_check_type (2, rs
,
16623 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16624 neon_two_same (neon_quad (rs
), 1, et
.size
);
16628 do_neon_pair_long (void)
16630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16631 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16632 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16633 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16634 neon_two_same (neon_quad (rs
), 1, et
.size
);
16638 do_neon_recip_est (void)
16640 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16641 struct neon_type_el et
= neon_check_type (2, rs
,
16642 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16643 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16644 neon_two_same (neon_quad (rs
), 1, et
.size
);
16650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16651 struct neon_type_el et
= neon_check_type (2, rs
,
16652 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16653 neon_two_same (neon_quad (rs
), 1, et
.size
);
16659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16660 struct neon_type_el et
= neon_check_type (2, rs
,
16661 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16662 neon_two_same (neon_quad (rs
), 1, et
.size
);
16668 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16669 struct neon_type_el et
= neon_check_type (2, rs
,
16670 N_EQK
| N_INT
, N_8
| N_KEY
);
16671 neon_two_same (neon_quad (rs
), 1, et
.size
);
16677 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16678 neon_two_same (neon_quad (rs
), 1, -1);
16682 do_neon_tbl_tbx (void)
16684 unsigned listlenbits
;
16685 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16687 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16689 first_error (_("bad list length for table lookup"));
16693 listlenbits
= inst
.operands
[1].imm
- 1;
16694 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16695 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16696 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16697 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16698 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16699 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16700 inst
.instruction
|= listlenbits
<< 8;
16702 neon_dp_fixup (&inst
);
16706 do_neon_ldm_stm (void)
16708 /* P, U and L bits are part of bitmask. */
16709 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16710 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16712 if (inst
.operands
[1].issingle
)
16714 do_vfp_nsyn_ldm_stm (is_dbmode
);
16718 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16719 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16721 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16722 _("register list must contain at least 1 and at most 16 "
16725 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16726 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16727 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16728 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16730 inst
.instruction
|= offsetbits
;
16732 do_vfp_cond_or_thumb ();
16736 do_neon_ldr_str (void)
16738 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16740 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16741 And is UNPREDICTABLE in thumb mode. */
16743 && inst
.operands
[1].reg
== REG_PC
16744 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16747 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16748 else if (warn_on_deprecated
)
16749 as_tsktsk (_("Use of PC here is deprecated"));
16752 if (inst
.operands
[0].issingle
)
16755 do_vfp_nsyn_opcode ("flds");
16757 do_vfp_nsyn_opcode ("fsts");
16759 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16760 if (inst
.vectype
.el
[0].size
== 16)
16761 do_scalar_fp16_v82_encode ();
16766 do_vfp_nsyn_opcode ("fldd");
16768 do_vfp_nsyn_opcode ("fstd");
16772 /* "interleave" version also handles non-interleaving register VLD1/VST1
16776 do_neon_ld_st_interleave (void)
16778 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16779 N_8
| N_16
| N_32
| N_64
);
16780 unsigned alignbits
= 0;
16782 /* The bits in this table go:
16783 0: register stride of one (0) or two (1)
16784 1,2: register list length, minus one (1, 2, 3, 4).
16785 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16786 We use -1 for invalid entries. */
16787 const int typetable
[] =
16789 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16790 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16791 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16792 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16796 if (et
.type
== NT_invtype
)
16799 if (inst
.operands
[1].immisalign
)
16800 switch (inst
.operands
[1].imm
>> 8)
16802 case 64: alignbits
= 1; break;
16804 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16805 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16806 goto bad_alignment
;
16810 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16811 goto bad_alignment
;
16816 first_error (_("bad alignment"));
16820 inst
.instruction
|= alignbits
<< 4;
16821 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16823 /* Bits [4:6] of the immediate in a list specifier encode register stride
16824 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16825 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16826 up the right value for "type" in a table based on this value and the given
16827 list style, then stick it back. */
16828 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16829 | (((inst
.instruction
>> 8) & 3) << 3);
16831 typebits
= typetable
[idx
];
16833 constraint (typebits
== -1, _("bad list type for instruction"));
16834 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16835 _("bad element type for instruction"));
16837 inst
.instruction
&= ~0xf00;
16838 inst
.instruction
|= typebits
<< 8;
16841 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16842 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16843 otherwise. The variable arguments are a list of pairs of legal (size, align)
16844 values, terminated with -1. */
16847 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16850 int result
= FAIL
, thissize
, thisalign
;
16852 if (!inst
.operands
[1].immisalign
)
16858 va_start (ap
, do_alignment
);
16862 thissize
= va_arg (ap
, int);
16863 if (thissize
== -1)
16865 thisalign
= va_arg (ap
, int);
16867 if (size
== thissize
&& align
== thisalign
)
16870 while (result
!= SUCCESS
);
16874 if (result
== SUCCESS
)
16877 first_error (_("unsupported alignment for instruction"));
16883 do_neon_ld_st_lane (void)
16885 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16886 int align_good
, do_alignment
= 0;
16887 int logsize
= neon_logbits (et
.size
);
16888 int align
= inst
.operands
[1].imm
>> 8;
16889 int n
= (inst
.instruction
>> 8) & 3;
16890 int max_el
= 64 / et
.size
;
16892 if (et
.type
== NT_invtype
)
16895 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16896 _("bad list length"));
16897 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16898 _("scalar index out of range"));
16899 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16901 _("stride of 2 unavailable when element size is 8"));
16905 case 0: /* VLD1 / VST1. */
16906 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16908 if (align_good
== FAIL
)
16912 unsigned alignbits
= 0;
16915 case 16: alignbits
= 0x1; break;
16916 case 32: alignbits
= 0x3; break;
16919 inst
.instruction
|= alignbits
<< 4;
16923 case 1: /* VLD2 / VST2. */
16924 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16925 16, 32, 32, 64, -1);
16926 if (align_good
== FAIL
)
16929 inst
.instruction
|= 1 << 4;
16932 case 2: /* VLD3 / VST3. */
16933 constraint (inst
.operands
[1].immisalign
,
16934 _("can't use alignment with this instruction"));
16937 case 3: /* VLD4 / VST4. */
16938 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16939 16, 64, 32, 64, 32, 128, -1);
16940 if (align_good
== FAIL
)
16944 unsigned alignbits
= 0;
16947 case 8: alignbits
= 0x1; break;
16948 case 16: alignbits
= 0x1; break;
16949 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16952 inst
.instruction
|= alignbits
<< 4;
16959 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16960 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16961 inst
.instruction
|= 1 << (4 + logsize
);
16963 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16964 inst
.instruction
|= logsize
<< 10;
16967 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16970 do_neon_ld_dup (void)
16972 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16973 int align_good
, do_alignment
= 0;
16975 if (et
.type
== NT_invtype
)
16978 switch ((inst
.instruction
>> 8) & 3)
16980 case 0: /* VLD1. */
16981 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16982 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16983 &do_alignment
, 16, 16, 32, 32, -1);
16984 if (align_good
== FAIL
)
16986 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16989 case 2: inst
.instruction
|= 1 << 5; break;
16990 default: first_error (_("bad list length")); return;
16992 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16995 case 1: /* VLD2. */
16996 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16997 &do_alignment
, 8, 16, 16, 32, 32, 64,
16999 if (align_good
== FAIL
)
17001 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17002 _("bad list length"));
17003 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17004 inst
.instruction
|= 1 << 5;
17005 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17008 case 2: /* VLD3. */
17009 constraint (inst
.operands
[1].immisalign
,
17010 _("can't use alignment with this instruction"));
17011 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17012 _("bad list length"));
17013 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17014 inst
.instruction
|= 1 << 5;
17015 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17018 case 3: /* VLD4. */
17020 int align
= inst
.operands
[1].imm
>> 8;
17021 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17022 16, 64, 32, 64, 32, 128, -1);
17023 if (align_good
== FAIL
)
17025 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17026 _("bad list length"));
17027 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17028 inst
.instruction
|= 1 << 5;
17029 if (et
.size
== 32 && align
== 128)
17030 inst
.instruction
|= 0x3 << 6;
17032 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17039 inst
.instruction
|= do_alignment
<< 4;
17042 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17043 apart from bits [11:4]. */
17046 do_neon_ldx_stx (void)
17048 if (inst
.operands
[1].isreg
)
17049 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17051 switch (NEON_LANE (inst
.operands
[0].imm
))
17053 case NEON_INTERLEAVE_LANES
:
17054 NEON_ENCODE (INTERLV
, inst
);
17055 do_neon_ld_st_interleave ();
17058 case NEON_ALL_LANES
:
17059 NEON_ENCODE (DUP
, inst
);
17060 if (inst
.instruction
== N_INV
)
17062 first_error ("only loads support such operands");
17069 NEON_ENCODE (LANE
, inst
);
17070 do_neon_ld_st_lane ();
17073 /* L bit comes from bit mask. */
17074 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17075 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17078 if (inst
.operands
[1].postind
)
17080 int postreg
= inst
.operands
[1].imm
& 0xf;
17081 constraint (!inst
.operands
[1].immisreg
,
17082 _("post-index must be a register"));
17083 constraint (postreg
== 0xd || postreg
== 0xf,
17084 _("bad register for post-index"));
17085 inst
.instruction
|= postreg
;
17089 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17090 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17091 || inst
.reloc
.exp
.X_add_number
!= 0,
17094 if (inst
.operands
[1].writeback
)
17096 inst
.instruction
|= 0xd;
17099 inst
.instruction
|= 0xf;
17103 inst
.instruction
|= 0xf9000000;
17105 inst
.instruction
|= 0xf4000000;
17110 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17112 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17113 D register operands. */
17114 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17118 NEON_ENCODE (FPV8
, inst
);
17120 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17122 do_vfp_sp_dyadic ();
17124 /* ARMv8.2 fp16 instruction. */
17126 do_scalar_fp16_v82_encode ();
17129 do_vfp_dp_rd_rn_rm ();
17132 inst
.instruction
|= 0x100;
17134 inst
.instruction
|= 0xf0000000;
17140 set_it_insn_type (OUTSIDE_IT_INSN
);
17142 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17143 first_error (_("invalid instruction shape"));
17149 set_it_insn_type (OUTSIDE_IT_INSN
);
17151 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17154 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17157 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17161 do_vrint_1 (enum neon_cvt_mode mode
)
17163 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17164 struct neon_type_el et
;
17169 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17170 D register operands. */
17171 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17175 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17177 if (et
.type
!= NT_invtype
)
17179 /* VFP encodings. */
17180 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17181 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17182 set_it_insn_type (OUTSIDE_IT_INSN
);
17184 NEON_ENCODE (FPV8
, inst
);
17185 if (rs
== NS_FF
|| rs
== NS_HH
)
17186 do_vfp_sp_monadic ();
17188 do_vfp_dp_rd_rm ();
17192 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17193 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17194 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17195 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17196 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17197 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17198 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17202 inst
.instruction
|= (rs
== NS_DD
) << 8;
17203 do_vfp_cond_or_thumb ();
17205 /* ARMv8.2 fp16 vrint instruction. */
17207 do_scalar_fp16_v82_encode ();
17211 /* Neon encodings (or something broken...). */
17213 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17215 if (et
.type
== NT_invtype
)
17218 set_it_insn_type (OUTSIDE_IT_INSN
);
17219 NEON_ENCODE (FLOAT
, inst
);
17221 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17224 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17225 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17226 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17227 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17228 inst
.instruction
|= neon_quad (rs
) << 6;
17229 /* Mask off the original size bits and reencode them. */
17230 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17231 | neon_logbits (et
.size
) << 18);
17235 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17236 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17237 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17238 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17239 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17240 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17241 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17246 inst
.instruction
|= 0xfc000000;
17248 inst
.instruction
|= 0xf0000000;
17255 do_vrint_1 (neon_cvt_mode_x
);
17261 do_vrint_1 (neon_cvt_mode_z
);
17267 do_vrint_1 (neon_cvt_mode_r
);
17273 do_vrint_1 (neon_cvt_mode_a
);
17279 do_vrint_1 (neon_cvt_mode_n
);
17285 do_vrint_1 (neon_cvt_mode_p
);
17291 do_vrint_1 (neon_cvt_mode_m
);
17295 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17297 unsigned regno
= NEON_SCALAR_REG (opnd
);
17298 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17300 if (elsize
== 16 && elno
< 2 && regno
< 16)
17301 return regno
| (elno
<< 4);
17302 else if (elsize
== 32 && elno
== 0)
17305 first_error (_("scalar out of range"));
17312 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17314 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17315 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17316 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17317 _("immediate out of range"));
17319 if (inst
.operands
[2].isscalar
)
17321 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17322 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17323 N_KEY
| N_F16
| N_F32
).size
;
17324 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17326 inst
.instruction
= 0xfe000800;
17327 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17328 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17329 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17330 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17331 inst
.instruction
|= LOW4 (m
);
17332 inst
.instruction
|= HI1 (m
) << 5;
17333 inst
.instruction
|= neon_quad (rs
) << 6;
17334 inst
.instruction
|= rot
<< 20;
17335 inst
.instruction
|= (size
== 32) << 23;
17339 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17340 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17341 N_KEY
| N_F16
| N_F32
).size
;
17342 neon_three_same (neon_quad (rs
), 0, -1);
17343 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17344 inst
.instruction
|= 0xfc200800;
17345 inst
.instruction
|= rot
<< 23;
17346 inst
.instruction
|= (size
== 32) << 20;
17353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17355 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17356 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17357 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17358 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17359 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17360 N_KEY
| N_F16
| N_F32
).size
;
17361 neon_three_same (neon_quad (rs
), 0, -1);
17362 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17363 inst
.instruction
|= 0xfc800800;
17364 inst
.instruction
|= (rot
== 270) << 24;
17365 inst
.instruction
|= (size
== 32) << 20;
17368 /* Crypto v1 instructions. */
17370 do_crypto_2op_1 (unsigned elttype
, int op
)
17372 set_it_insn_type (OUTSIDE_IT_INSN
);
17374 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17380 NEON_ENCODE (INTEGER
, inst
);
17381 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17382 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17384 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17386 inst
.instruction
|= op
<< 6;
17389 inst
.instruction
|= 0xfc000000;
17391 inst
.instruction
|= 0xf0000000;
17395 do_crypto_3op_1 (int u
, int op
)
17397 set_it_insn_type (OUTSIDE_IT_INSN
);
17399 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17400 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17405 NEON_ENCODE (INTEGER
, inst
);
17406 neon_three_same (1, u
, 8 << op
);
17412 do_crypto_2op_1 (N_8
, 0);
17418 do_crypto_2op_1 (N_8
, 1);
17424 do_crypto_2op_1 (N_8
, 2);
17430 do_crypto_2op_1 (N_8
, 3);
17436 do_crypto_3op_1 (0, 0);
17442 do_crypto_3op_1 (0, 1);
17448 do_crypto_3op_1 (0, 2);
17454 do_crypto_3op_1 (0, 3);
17460 do_crypto_3op_1 (1, 0);
17466 do_crypto_3op_1 (1, 1);
17470 do_sha256su1 (void)
17472 do_crypto_3op_1 (1, 2);
17478 do_crypto_2op_1 (N_32
, -1);
17484 do_crypto_2op_1 (N_32
, 0);
17488 do_sha256su0 (void)
17490 do_crypto_2op_1 (N_32
, 1);
17494 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17496 unsigned int Rd
= inst
.operands
[0].reg
;
17497 unsigned int Rn
= inst
.operands
[1].reg
;
17498 unsigned int Rm
= inst
.operands
[2].reg
;
17500 set_it_insn_type (OUTSIDE_IT_INSN
);
17501 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17502 inst
.instruction
|= LOW4 (Rn
) << 16;
17503 inst
.instruction
|= LOW4 (Rm
);
17504 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17505 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17507 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17508 as_warn (UNPRED_REG ("r15"));
17509 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17510 as_warn (UNPRED_REG ("r13"));
17552 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17554 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17555 do_vfp_sp_dp_cvt ();
17556 do_vfp_cond_or_thumb ();
17560 /* Overall per-instruction processing. */
17562 /* We need to be able to fix up arbitrary expressions in some statements.
17563 This is so that we can handle symbols that are an arbitrary distance from
17564 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17565 which returns part of an address in a form which will be valid for
17566 a data instruction. We do this by pushing the expression into a symbol
17567 in the expr_section, and creating a fix for that. */
17570 fix_new_arm (fragS
* frag
,
17584 /* Create an absolute valued symbol, so we have something to
17585 refer to in the object file. Unfortunately for us, gas's
17586 generic expression parsing will already have folded out
17587 any use of .set foo/.type foo %function that may have
17588 been used to set type information of the target location,
17589 that's being specified symbolically. We have to presume
17590 the user knows what they are doing. */
17594 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17596 symbol
= symbol_find_or_make (name
);
17597 S_SET_SEGMENT (symbol
, absolute_section
);
17598 symbol_set_frag (symbol
, &zero_address_frag
);
17599 S_SET_VALUE (symbol
, exp
->X_add_number
);
17600 exp
->X_op
= O_symbol
;
17601 exp
->X_add_symbol
= symbol
;
17602 exp
->X_add_number
= 0;
17608 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17609 (enum bfd_reloc_code_real
) reloc
);
17613 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17614 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17618 /* Mark whether the fix is to a THUMB instruction, or an ARM
17620 new_fix
->tc_fix_data
= thumb_mode
;
17623 /* Create a frg for an instruction requiring relaxation. */
17625 output_relax_insn (void)
17631 /* The size of the instruction is unknown, so tie the debug info to the
17632 start of the instruction. */
17633 dwarf2_emit_insn (0);
17635 switch (inst
.reloc
.exp
.X_op
)
17638 sym
= inst
.reloc
.exp
.X_add_symbol
;
17639 offset
= inst
.reloc
.exp
.X_add_number
;
17643 offset
= inst
.reloc
.exp
.X_add_number
;
17646 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17650 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17651 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17652 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17655 /* Write a 32-bit thumb instruction to buf. */
17657 put_thumb32_insn (char * buf
, unsigned long insn
)
17659 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17660 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17664 output_inst (const char * str
)
17670 as_bad ("%s -- `%s'", inst
.error
, str
);
17675 output_relax_insn ();
17678 if (inst
.size
== 0)
17681 to
= frag_more (inst
.size
);
17682 /* PR 9814: Record the thumb mode into the current frag so that we know
17683 what type of NOP padding to use, if necessary. We override any previous
17684 setting so that if the mode has changed then the NOPS that we use will
17685 match the encoding of the last instruction in the frag. */
17686 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17688 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17690 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17691 put_thumb32_insn (to
, inst
.instruction
);
17693 else if (inst
.size
> INSN_SIZE
)
17695 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17696 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17697 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17700 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17702 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17703 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17704 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17707 dwarf2_emit_insn (inst
.size
);
17711 output_it_inst (int cond
, int mask
, char * to
)
17713 unsigned long instruction
= 0xbf00;
17716 instruction
|= mask
;
17717 instruction
|= cond
<< 4;
17721 to
= frag_more (2);
17723 dwarf2_emit_insn (2);
17727 md_number_to_chars (to
, instruction
, 2);
17732 /* Tag values used in struct asm_opcode's tag field. */
17735 OT_unconditional
, /* Instruction cannot be conditionalized.
17736 The ARM condition field is still 0xE. */
17737 OT_unconditionalF
, /* Instruction cannot be conditionalized
17738 and carries 0xF in its ARM condition field. */
17739 OT_csuffix
, /* Instruction takes a conditional suffix. */
17740 OT_csuffixF
, /* Some forms of the instruction take a conditional
17741 suffix, others place 0xF where the condition field
17743 OT_cinfix3
, /* Instruction takes a conditional infix,
17744 beginning at character index 3. (In
17745 unified mode, it becomes a suffix.) */
17746 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17747 tsts, cmps, cmns, and teqs. */
17748 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17749 character index 3, even in unified mode. Used for
17750 legacy instructions where suffix and infix forms
17751 may be ambiguous. */
17752 OT_csuf_or_in3
, /* Instruction takes either a conditional
17753 suffix or an infix at character index 3. */
17754 OT_odd_infix_unc
, /* This is the unconditional variant of an
17755 instruction that takes a conditional infix
17756 at an unusual position. In unified mode,
17757 this variant will accept a suffix. */
17758 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17759 are the conditional variants of instructions that
17760 take conditional infixes in unusual positions.
17761 The infix appears at character index
17762 (tag - OT_odd_infix_0). These are not accepted
17763 in unified mode. */
17766 /* Subroutine of md_assemble, responsible for looking up the primary
17767 opcode from the mnemonic the user wrote. STR points to the
17768 beginning of the mnemonic.
17770 This is not simply a hash table lookup, because of conditional
17771 variants. Most instructions have conditional variants, which are
17772 expressed with a _conditional affix_ to the mnemonic. If we were
17773 to encode each conditional variant as a literal string in the opcode
17774 table, it would have approximately 20,000 entries.
17776 Most mnemonics take this affix as a suffix, and in unified syntax,
17777 'most' is upgraded to 'all'. However, in the divided syntax, some
17778 instructions take the affix as an infix, notably the s-variants of
17779 the arithmetic instructions. Of those instructions, all but six
17780 have the infix appear after the third character of the mnemonic.
17782 Accordingly, the algorithm for looking up primary opcodes given
17785 1. Look up the identifier in the opcode table.
17786 If we find a match, go to step U.
17788 2. Look up the last two characters of the identifier in the
17789 conditions table. If we find a match, look up the first N-2
17790 characters of the identifier in the opcode table. If we
17791 find a match, go to step CE.
17793 3. Look up the fourth and fifth characters of the identifier in
17794 the conditions table. If we find a match, extract those
17795 characters from the identifier, and look up the remaining
17796 characters in the opcode table. If we find a match, go
17801 U. Examine the tag field of the opcode structure, in case this is
17802 one of the six instructions with its conditional infix in an
17803 unusual place. If it is, the tag tells us where to find the
17804 infix; look it up in the conditions table and set inst.cond
17805 accordingly. Otherwise, this is an unconditional instruction.
17806 Again set inst.cond accordingly. Return the opcode structure.
17808 CE. Examine the tag field to make sure this is an instruction that
17809 should receive a conditional suffix. If it is not, fail.
17810 Otherwise, set inst.cond from the suffix we already looked up,
17811 and return the opcode structure.
17813 CM. Examine the tag field to make sure this is an instruction that
17814 should receive a conditional infix after the third character.
17815 If it is not, fail. Otherwise, undo the edits to the current
17816 line of input and proceed as for case CE. */
17818 static const struct asm_opcode
*
17819 opcode_lookup (char **str
)
17823 const struct asm_opcode
*opcode
;
17824 const struct asm_cond
*cond
;
17827 /* Scan up to the end of the mnemonic, which must end in white space,
17828 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17829 for (base
= end
= *str
; *end
!= '\0'; end
++)
17830 if (*end
== ' ' || *end
== '.')
17836 /* Handle a possible width suffix and/or Neon type suffix. */
17841 /* The .w and .n suffixes are only valid if the unified syntax is in
17843 if (unified_syntax
&& end
[1] == 'w')
17845 else if (unified_syntax
&& end
[1] == 'n')
17850 inst
.vectype
.elems
= 0;
17852 *str
= end
+ offset
;
17854 if (end
[offset
] == '.')
17856 /* See if we have a Neon type suffix (possible in either unified or
17857 non-unified ARM syntax mode). */
17858 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17861 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17867 /* Look for unaffixed or special-case affixed mnemonic. */
17868 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17873 if (opcode
->tag
< OT_odd_infix_0
)
17875 inst
.cond
= COND_ALWAYS
;
17879 if (warn_on_deprecated
&& unified_syntax
)
17880 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17881 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17882 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17885 inst
.cond
= cond
->value
;
17889 /* Cannot have a conditional suffix on a mnemonic of less than two
17891 if (end
- base
< 3)
17894 /* Look for suffixed mnemonic. */
17896 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17897 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17899 if (opcode
&& cond
)
17902 switch (opcode
->tag
)
17904 case OT_cinfix3_legacy
:
17905 /* Ignore conditional suffixes matched on infix only mnemonics. */
17909 case OT_cinfix3_deprecated
:
17910 case OT_odd_infix_unc
:
17911 if (!unified_syntax
)
17913 /* Fall through. */
17917 case OT_csuf_or_in3
:
17918 inst
.cond
= cond
->value
;
17921 case OT_unconditional
:
17922 case OT_unconditionalF
:
17924 inst
.cond
= cond
->value
;
17927 /* Delayed diagnostic. */
17928 inst
.error
= BAD_COND
;
17929 inst
.cond
= COND_ALWAYS
;
17938 /* Cannot have a usual-position infix on a mnemonic of less than
17939 six characters (five would be a suffix). */
17940 if (end
- base
< 6)
17943 /* Look for infixed mnemonic in the usual position. */
17945 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17949 memcpy (save
, affix
, 2);
17950 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17951 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17953 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17954 memcpy (affix
, save
, 2);
17957 && (opcode
->tag
== OT_cinfix3
17958 || opcode
->tag
== OT_cinfix3_deprecated
17959 || opcode
->tag
== OT_csuf_or_in3
17960 || opcode
->tag
== OT_cinfix3_legacy
))
17963 if (warn_on_deprecated
&& unified_syntax
17964 && (opcode
->tag
== OT_cinfix3
17965 || opcode
->tag
== OT_cinfix3_deprecated
))
17966 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17968 inst
.cond
= cond
->value
;
17975 /* This function generates an initial IT instruction, leaving its block
17976 virtually open for the new instructions. Eventually,
17977 the mask will be updated by now_it_add_mask () each time
17978 a new instruction needs to be included in the IT block.
17979 Finally, the block is closed with close_automatic_it_block ().
17980 The block closure can be requested either from md_assemble (),
17981 a tencode (), or due to a label hook. */
17984 new_automatic_it_block (int cond
)
17986 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17987 now_it
.mask
= 0x18;
17989 now_it
.block_length
= 1;
17990 mapping_state (MAP_THUMB
);
17991 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17992 now_it
.warn_deprecated
= FALSE
;
17993 now_it
.insn_cond
= TRUE
;
17996 /* Close an automatic IT block.
17997 See comments in new_automatic_it_block (). */
18000 close_automatic_it_block (void)
18002 now_it
.mask
= 0x10;
18003 now_it
.block_length
= 0;
18006 /* Update the mask of the current automatically-generated IT
18007 instruction. See comments in new_automatic_it_block (). */
18010 now_it_add_mask (int cond
)
18012 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18013 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18014 | ((bitvalue) << (nbit)))
18015 const int resulting_bit
= (cond
& 1);
18017 now_it
.mask
&= 0xf;
18018 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18020 (5 - now_it
.block_length
));
18021 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18023 ((5 - now_it
.block_length
) - 1) );
18024 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18027 #undef SET_BIT_VALUE
18030 /* The IT blocks handling machinery is accessed through the these functions:
18031 it_fsm_pre_encode () from md_assemble ()
18032 set_it_insn_type () optional, from the tencode functions
18033 set_it_insn_type_last () ditto
18034 in_it_block () ditto
18035 it_fsm_post_encode () from md_assemble ()
18036 force_automatic_it_block_close () from label handling functions
18039 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18040 initializing the IT insn type with a generic initial value depending
18041 on the inst.condition.
18042 2) During the tencode function, two things may happen:
18043 a) The tencode function overrides the IT insn type by
18044 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18045 b) The tencode function queries the IT block state by
18046 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18048 Both set_it_insn_type and in_it_block run the internal FSM state
18049 handling function (handle_it_state), because: a) setting the IT insn
18050 type may incur in an invalid state (exiting the function),
18051 and b) querying the state requires the FSM to be updated.
18052 Specifically we want to avoid creating an IT block for conditional
18053 branches, so it_fsm_pre_encode is actually a guess and we can't
18054 determine whether an IT block is required until the tencode () routine
18055 has decided what type of instruction this actually it.
18056 Because of this, if set_it_insn_type and in_it_block have to be used,
18057 set_it_insn_type has to be called first.
18059 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18060 determines the insn IT type depending on the inst.cond code.
18061 When a tencode () routine encodes an instruction that can be
18062 either outside an IT block, or, in the case of being inside, has to be
18063 the last one, set_it_insn_type_last () will determine the proper
18064 IT instruction type based on the inst.cond code. Otherwise,
18065 set_it_insn_type can be called for overriding that logic or
18066 for covering other cases.
18068 Calling handle_it_state () may not transition the IT block state to
18069 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18070 still queried. Instead, if the FSM determines that the state should
18071 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18072 after the tencode () function: that's what it_fsm_post_encode () does.
18074 Since in_it_block () calls the state handling function to get an
18075 updated state, an error may occur (due to invalid insns combination).
18076 In that case, inst.error is set.
18077 Therefore, inst.error has to be checked after the execution of
18078 the tencode () routine.
18080 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18081 any pending state change (if any) that didn't take place in
18082 handle_it_state () as explained above. */
18085 it_fsm_pre_encode (void)
18087 if (inst
.cond
!= COND_ALWAYS
)
18088 inst
.it_insn_type
= INSIDE_IT_INSN
;
18090 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18092 now_it
.state_handled
= 0;
18095 /* IT state FSM handling function. */
18098 handle_it_state (void)
18100 now_it
.state_handled
= 1;
18101 now_it
.insn_cond
= FALSE
;
18103 switch (now_it
.state
)
18105 case OUTSIDE_IT_BLOCK
:
18106 switch (inst
.it_insn_type
)
18108 case OUTSIDE_IT_INSN
:
18111 case INSIDE_IT_INSN
:
18112 case INSIDE_IT_LAST_INSN
:
18113 if (thumb_mode
== 0)
18116 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18117 as_tsktsk (_("Warning: conditional outside an IT block"\
18122 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18123 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18125 /* Automatically generate the IT instruction. */
18126 new_automatic_it_block (inst
.cond
);
18127 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18128 close_automatic_it_block ();
18132 inst
.error
= BAD_OUT_IT
;
18138 case IF_INSIDE_IT_LAST_INSN
:
18139 case NEUTRAL_IT_INSN
:
18143 now_it
.state
= MANUAL_IT_BLOCK
;
18144 now_it
.block_length
= 0;
18149 case AUTOMATIC_IT_BLOCK
:
18150 /* Three things may happen now:
18151 a) We should increment current it block size;
18152 b) We should close current it block (closing insn or 4 insns);
18153 c) We should close current it block and start a new one (due
18154 to incompatible conditions or
18155 4 insns-length block reached). */
18157 switch (inst
.it_insn_type
)
18159 case OUTSIDE_IT_INSN
:
18160 /* The closure of the block shall happen immediately,
18161 so any in_it_block () call reports the block as closed. */
18162 force_automatic_it_block_close ();
18165 case INSIDE_IT_INSN
:
18166 case INSIDE_IT_LAST_INSN
:
18167 case IF_INSIDE_IT_LAST_INSN
:
18168 now_it
.block_length
++;
18170 if (now_it
.block_length
> 4
18171 || !now_it_compatible (inst
.cond
))
18173 force_automatic_it_block_close ();
18174 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18175 new_automatic_it_block (inst
.cond
);
18179 now_it
.insn_cond
= TRUE
;
18180 now_it_add_mask (inst
.cond
);
18183 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18184 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18185 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18186 close_automatic_it_block ();
18189 case NEUTRAL_IT_INSN
:
18190 now_it
.block_length
++;
18191 now_it
.insn_cond
= TRUE
;
18193 if (now_it
.block_length
> 4)
18194 force_automatic_it_block_close ();
18196 now_it_add_mask (now_it
.cc
& 1);
18200 close_automatic_it_block ();
18201 now_it
.state
= MANUAL_IT_BLOCK
;
18206 case MANUAL_IT_BLOCK
:
18208 /* Check conditional suffixes. */
18209 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18212 now_it
.mask
&= 0x1f;
18213 is_last
= (now_it
.mask
== 0x10);
18214 now_it
.insn_cond
= TRUE
;
18216 switch (inst
.it_insn_type
)
18218 case OUTSIDE_IT_INSN
:
18219 inst
.error
= BAD_NOT_IT
;
18222 case INSIDE_IT_INSN
:
18223 if (cond
!= inst
.cond
)
18225 inst
.error
= BAD_IT_COND
;
18230 case INSIDE_IT_LAST_INSN
:
18231 case IF_INSIDE_IT_LAST_INSN
:
18232 if (cond
!= inst
.cond
)
18234 inst
.error
= BAD_IT_COND
;
18239 inst
.error
= BAD_BRANCH
;
18244 case NEUTRAL_IT_INSN
:
18245 /* The BKPT instruction is unconditional even in an IT block. */
18249 inst
.error
= BAD_IT_IT
;
18259 struct depr_insn_mask
18261 unsigned long pattern
;
18262 unsigned long mask
;
18263 const char* description
;
18266 /* List of 16-bit instruction patterns deprecated in an IT block in
18268 static const struct depr_insn_mask depr_it_insns
[] = {
18269 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18270 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18271 { 0xa000, 0xb800, N_("ADR") },
18272 { 0x4800, 0xf800, N_("Literal loads") },
18273 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18274 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18275 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18276 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18277 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18282 it_fsm_post_encode (void)
18286 if (!now_it
.state_handled
)
18287 handle_it_state ();
18289 if (now_it
.insn_cond
18290 && !now_it
.warn_deprecated
18291 && warn_on_deprecated
18292 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18294 if (inst
.instruction
>= 0x10000)
18296 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18297 "deprecated in ARMv8"));
18298 now_it
.warn_deprecated
= TRUE
;
18302 const struct depr_insn_mask
*p
= depr_it_insns
;
18304 while (p
->mask
!= 0)
18306 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18308 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18309 "of the following class are deprecated in ARMv8: "
18310 "%s"), p
->description
);
18311 now_it
.warn_deprecated
= TRUE
;
18319 if (now_it
.block_length
> 1)
18321 as_tsktsk (_("IT blocks containing more than one conditional "
18322 "instruction are deprecated in ARMv8"));
18323 now_it
.warn_deprecated
= TRUE
;
18327 is_last
= (now_it
.mask
== 0x10);
18330 now_it
.state
= OUTSIDE_IT_BLOCK
;
18336 force_automatic_it_block_close (void)
18338 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18340 close_automatic_it_block ();
18341 now_it
.state
= OUTSIDE_IT_BLOCK
;
18349 if (!now_it
.state_handled
)
18350 handle_it_state ();
18352 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18355 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18356 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18357 here, hence the "known" in the function name. */
18360 known_t32_only_insn (const struct asm_opcode
*opcode
)
18362 /* Original Thumb-1 wide instruction. */
18363 if (opcode
->tencode
== do_t_blx
18364 || opcode
->tencode
== do_t_branch23
18365 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18366 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18369 /* Wide-only instruction added to ARMv8-M Baseline. */
18370 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18371 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18372 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18373 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18379 /* Whether wide instruction variant can be used if available for a valid OPCODE
18383 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18385 if (known_t32_only_insn (opcode
))
18388 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18389 of variant T3 of B.W is checked in do_t_branch. */
18390 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18391 && opcode
->tencode
== do_t_branch
)
18394 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18395 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18396 && opcode
->tencode
== do_t_mov_cmp
18397 /* Make sure CMP instruction is not affected. */
18398 && opcode
->aencode
== do_mov
)
18401 /* Wide instruction variants of all instructions with narrow *and* wide
18402 variants become available with ARMv6t2. Other opcodes are either
18403 narrow-only or wide-only and are thus available if OPCODE is valid. */
18404 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18407 /* OPCODE with narrow only instruction variant or wide variant not
18413 md_assemble (char *str
)
18416 const struct asm_opcode
* opcode
;
18418 /* Align the previous label if needed. */
18419 if (last_label_seen
!= NULL
)
18421 symbol_set_frag (last_label_seen
, frag_now
);
18422 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18423 S_SET_SEGMENT (last_label_seen
, now_seg
);
18426 memset (&inst
, '\0', sizeof (inst
));
18427 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18429 opcode
= opcode_lookup (&p
);
18432 /* It wasn't an instruction, but it might be a register alias of
18433 the form alias .req reg, or a Neon .dn/.qn directive. */
18434 if (! create_register_alias (str
, p
)
18435 && ! create_neon_reg_alias (str
, p
))
18436 as_bad (_("bad instruction `%s'"), str
);
18441 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18442 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18444 /* The value which unconditional instructions should have in place of the
18445 condition field. */
18446 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18450 arm_feature_set variant
;
18452 variant
= cpu_variant
;
18453 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18454 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18455 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18456 /* Check that this instruction is supported for this CPU. */
18457 if (!opcode
->tvariant
18458 || (thumb_mode
== 1
18459 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18461 if (opcode
->tencode
== do_t_swi
)
18462 as_bad (_("SVC is not permitted on this architecture"));
18464 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18467 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18468 && opcode
->tencode
!= do_t_branch
)
18470 as_bad (_("Thumb does not support conditional execution"));
18474 /* Two things are addressed here:
18475 1) Implicit require narrow instructions on Thumb-1.
18476 This avoids relaxation accidentally introducing Thumb-2
18478 2) Reject wide instructions in non Thumb-2 cores.
18480 Only instructions with narrow and wide variants need to be handled
18481 but selecting all non wide-only instructions is easier. */
18482 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18483 && !t32_insn_ok (variant
, opcode
))
18485 if (inst
.size_req
== 0)
18487 else if (inst
.size_req
== 4)
18489 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18490 as_bad (_("selected processor does not support 32bit wide "
18491 "variant of instruction `%s'"), str
);
18493 as_bad (_("selected processor does not support `%s' in "
18494 "Thumb-2 mode"), str
);
18499 inst
.instruction
= opcode
->tvalue
;
18501 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18503 /* Prepare the it_insn_type for those encodings that don't set
18505 it_fsm_pre_encode ();
18507 opcode
->tencode ();
18509 it_fsm_post_encode ();
18512 if (!(inst
.error
|| inst
.relax
))
18514 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18515 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18516 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18518 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18523 /* Something has gone badly wrong if we try to relax a fixed size
18525 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18527 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18528 *opcode
->tvariant
);
18529 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18530 set those bits when Thumb-2 32-bit instructions are seen. The impact
18531 of relaxable instructions will be considered later after we finish all
18533 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18534 variant
= arm_arch_none
;
18536 variant
= cpu_variant
;
18537 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18538 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18541 check_neon_suffixes
;
18545 mapping_state (MAP_THUMB
);
18548 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18552 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18553 is_bx
= (opcode
->aencode
== do_bx
);
18555 /* Check that this instruction is supported for this CPU. */
18556 if (!(is_bx
&& fix_v4bx
)
18557 && !(opcode
->avariant
&&
18558 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18560 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18565 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18569 inst
.instruction
= opcode
->avalue
;
18570 if (opcode
->tag
== OT_unconditionalF
)
18571 inst
.instruction
|= 0xFU
<< 28;
18573 inst
.instruction
|= inst
.cond
<< 28;
18574 inst
.size
= INSN_SIZE
;
18575 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18577 it_fsm_pre_encode ();
18578 opcode
->aencode ();
18579 it_fsm_post_encode ();
18581 /* Arm mode bx is marked as both v4T and v5 because it's still required
18582 on a hypothetical non-thumb v5 core. */
18584 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18586 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18587 *opcode
->avariant
);
18589 check_neon_suffixes
;
18593 mapping_state (MAP_ARM
);
18598 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18606 check_it_blocks_finished (void)
18611 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18612 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18613 == MANUAL_IT_BLOCK
)
18615 as_warn (_("section '%s' finished with an open IT block."),
18619 if (now_it
.state
== MANUAL_IT_BLOCK
)
18620 as_warn (_("file finished with an open IT block."));
18624 /* Various frobbings of labels and their addresses. */
18627 arm_start_line_hook (void)
18629 last_label_seen
= NULL
;
18633 arm_frob_label (symbolS
* sym
)
18635 last_label_seen
= sym
;
18637 ARM_SET_THUMB (sym
, thumb_mode
);
18639 #if defined OBJ_COFF || defined OBJ_ELF
18640 ARM_SET_INTERWORK (sym
, support_interwork
);
18643 force_automatic_it_block_close ();
18645 /* Note - do not allow local symbols (.Lxxx) to be labelled
18646 as Thumb functions. This is because these labels, whilst
18647 they exist inside Thumb code, are not the entry points for
18648 possible ARM->Thumb calls. Also, these labels can be used
18649 as part of a computed goto or switch statement. eg gcc
18650 can generate code that looks like this:
18652 ldr r2, [pc, .Laaa]
18662 The first instruction loads the address of the jump table.
18663 The second instruction converts a table index into a byte offset.
18664 The third instruction gets the jump address out of the table.
18665 The fourth instruction performs the jump.
18667 If the address stored at .Laaa is that of a symbol which has the
18668 Thumb_Func bit set, then the linker will arrange for this address
18669 to have the bottom bit set, which in turn would mean that the
18670 address computation performed by the third instruction would end
18671 up with the bottom bit set. Since the ARM is capable of unaligned
18672 word loads, the instruction would then load the incorrect address
18673 out of the jump table, and chaos would ensue. */
18674 if (label_is_thumb_function_name
18675 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18676 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18678 /* When the address of a Thumb function is taken the bottom
18679 bit of that address should be set. This will allow
18680 interworking between Arm and Thumb functions to work
18683 THUMB_SET_FUNC (sym
, 1);
18685 label_is_thumb_function_name
= FALSE
;
18688 dwarf2_emit_label (sym
);
18692 arm_data_in_code (void)
18694 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18696 *input_line_pointer
= '/';
18697 input_line_pointer
+= 5;
18698 *input_line_pointer
= 0;
18706 arm_canonicalize_symbol_name (char * name
)
18710 if (thumb_mode
&& (len
= strlen (name
)) > 5
18711 && streq (name
+ len
- 5, "/data"))
18712 *(name
+ len
- 5) = 0;
18717 /* Table of all register names defined by default. The user can
18718 define additional names with .req. Note that all register names
18719 should appear in both upper and lowercase variants. Some registers
18720 also have mixed-case names. */
18722 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18723 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18724 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18725 #define REGSET(p,t) \
18726 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18727 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18728 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18729 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18730 #define REGSETH(p,t) \
18731 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18732 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18733 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18734 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18735 #define REGSET2(p,t) \
18736 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18737 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18738 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18739 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18740 #define SPLRBANK(base,bank,t) \
18741 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18742 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18743 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18744 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18745 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18746 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18748 static const struct reg_entry reg_names
[] =
18750 /* ARM integer registers. */
18751 REGSET(r
, RN
), REGSET(R
, RN
),
18753 /* ATPCS synonyms. */
18754 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18755 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18756 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18758 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18759 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18760 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18762 /* Well-known aliases. */
18763 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18764 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18766 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18767 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18769 /* Coprocessor numbers. */
18770 REGSET(p
, CP
), REGSET(P
, CP
),
18772 /* Coprocessor register numbers. The "cr" variants are for backward
18774 REGSET(c
, CN
), REGSET(C
, CN
),
18775 REGSET(cr
, CN
), REGSET(CR
, CN
),
18777 /* ARM banked registers. */
18778 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18779 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18780 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18781 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18782 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18783 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18784 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18786 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18787 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18788 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18789 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18790 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18791 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18792 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18793 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18795 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18796 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18797 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18798 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18799 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18800 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18801 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18802 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18803 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18805 /* FPA registers. */
18806 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18807 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18809 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18810 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18812 /* VFP SP registers. */
18813 REGSET(s
,VFS
), REGSET(S
,VFS
),
18814 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18816 /* VFP DP Registers. */
18817 REGSET(d
,VFD
), REGSET(D
,VFD
),
18818 /* Extra Neon DP registers. */
18819 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18821 /* Neon QP registers. */
18822 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18824 /* VFP control registers. */
18825 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18826 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18827 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18828 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18829 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18830 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18832 /* Maverick DSP coprocessor registers. */
18833 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18834 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18836 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18837 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18838 REGDEF(dspsc
,0,DSPSC
),
18840 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18841 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18842 REGDEF(DSPSC
,0,DSPSC
),
18844 /* iWMMXt data registers - p0, c0-15. */
18845 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18847 /* iWMMXt control registers - p1, c0-3. */
18848 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18849 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18850 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18851 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18853 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18854 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18855 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18856 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18857 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18859 /* XScale accumulator registers. */
18860 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18866 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18867 within psr_required_here. */
18868 static const struct asm_psr psrs
[] =
18870 /* Backward compatibility notation. Note that "all" is no longer
18871 truly all possible PSR bits. */
18872 {"all", PSR_c
| PSR_f
},
18876 /* Individual flags. */
18882 /* Combinations of flags. */
18883 {"fs", PSR_f
| PSR_s
},
18884 {"fx", PSR_f
| PSR_x
},
18885 {"fc", PSR_f
| PSR_c
},
18886 {"sf", PSR_s
| PSR_f
},
18887 {"sx", PSR_s
| PSR_x
},
18888 {"sc", PSR_s
| PSR_c
},
18889 {"xf", PSR_x
| PSR_f
},
18890 {"xs", PSR_x
| PSR_s
},
18891 {"xc", PSR_x
| PSR_c
},
18892 {"cf", PSR_c
| PSR_f
},
18893 {"cs", PSR_c
| PSR_s
},
18894 {"cx", PSR_c
| PSR_x
},
18895 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18896 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18897 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18898 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18899 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18900 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18901 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18902 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18903 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18904 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18905 {"scf", PSR_s
| PSR_c
| PSR_f
},
18906 {"scx", PSR_s
| PSR_c
| PSR_x
},
18907 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18908 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18909 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18910 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18911 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18912 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18913 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18914 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18915 {"csf", PSR_c
| PSR_s
| PSR_f
},
18916 {"csx", PSR_c
| PSR_s
| PSR_x
},
18917 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18918 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18919 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18920 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18921 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18922 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18923 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18924 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18925 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18926 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18927 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18928 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18929 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18930 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18931 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18932 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18933 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18934 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18935 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18936 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18937 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18938 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18939 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18940 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18941 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18942 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18945 /* Table of V7M psr names. */
18946 static const struct asm_psr v7m_psrs
[] =
18948 {"apsr", 0x0 }, {"APSR", 0x0 },
18949 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18950 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18951 {"psr", 0x3 }, {"PSR", 0x3 },
18952 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18953 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18954 {"epsr", 0x6 }, {"EPSR", 0x6 },
18955 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18956 {"msp", 0x8 }, {"MSP", 0x8 },
18957 {"psp", 0x9 }, {"PSP", 0x9 },
18958 {"msplim", 0xa }, {"MSPLIM", 0xa },
18959 {"psplim", 0xb }, {"PSPLIM", 0xb },
18960 {"primask", 0x10}, {"PRIMASK", 0x10},
18961 {"basepri", 0x11}, {"BASEPRI", 0x11},
18962 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18963 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18964 {"control", 0x14}, {"CONTROL", 0x14},
18965 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18966 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18967 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18968 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18969 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18970 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18971 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18972 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18973 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18976 /* Table of all shift-in-operand names. */
18977 static const struct asm_shift_name shift_names
[] =
18979 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18980 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18981 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18982 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18983 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18984 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18987 /* Table of all explicit relocation names. */
18989 static struct reloc_entry reloc_names
[] =
18991 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18992 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18993 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18994 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18995 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18996 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18997 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18998 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18999 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19000 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19001 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19002 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19003 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19004 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19005 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19006 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19007 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19008 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19012 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19013 static const struct asm_cond conds
[] =
19017 {"cs", 0x2}, {"hs", 0x2},
19018 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19032 #define UL_BARRIER(L,U,CODE,FEAT) \
19033 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19034 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19036 static struct asm_barrier_opt barrier_opt_names
[] =
19038 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19039 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19040 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19041 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19042 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19043 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19044 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19045 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19046 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19047 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19048 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19049 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19050 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19051 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19052 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19053 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19058 /* Table of ARM-format instructions. */
19060 /* Macros for gluing together operand strings. N.B. In all cases
19061 other than OPS0, the trailing OP_stop comes from default
19062 zero-initialization of the unspecified elements of the array. */
19063 #define OPS0() { OP_stop, }
19064 #define OPS1(a) { OP_##a, }
19065 #define OPS2(a,b) { OP_##a,OP_##b, }
19066 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19067 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19068 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19069 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19071 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19072 This is useful when mixing operands for ARM and THUMB, i.e. using the
19073 MIX_ARM_THUMB_OPERANDS macro.
19074 In order to use these macros, prefix the number of operands with _
19076 #define OPS_1(a) { a, }
19077 #define OPS_2(a,b) { a,b, }
19078 #define OPS_3(a,b,c) { a,b,c, }
19079 #define OPS_4(a,b,c,d) { a,b,c,d, }
19080 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19081 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19083 /* These macros abstract out the exact format of the mnemonic table and
19084 save some repeated characters. */
19086 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19087 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19088 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19089 THUMB_VARIANT, do_##ae, do_##te }
19091 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19092 a T_MNEM_xyz enumerator. */
19093 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19094 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19095 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19096 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19098 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19099 infix after the third character. */
19100 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19101 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19102 THUMB_VARIANT, do_##ae, do_##te }
19103 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19104 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19105 THUMB_VARIANT, do_##ae, do_##te }
19106 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19107 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19108 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19109 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19110 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19111 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19112 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19113 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19115 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19116 field is still 0xE. Many of the Thumb variants can be executed
19117 conditionally, so this is checked separately. */
19118 #define TUE(mnem, op, top, nops, ops, ae, te) \
19119 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19120 THUMB_VARIANT, do_##ae, do_##te }
19122 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19123 Used by mnemonics that have very minimal differences in the encoding for
19124 ARM and Thumb variants and can be handled in a common function. */
19125 #define TUEc(mnem, op, top, nops, ops, en) \
19126 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19127 THUMB_VARIANT, do_##en, do_##en }
19129 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19130 condition code field. */
19131 #define TUF(mnem, op, top, nops, ops, ae, te) \
19132 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19133 THUMB_VARIANT, do_##ae, do_##te }
19135 /* ARM-only variants of all the above. */
19136 #define CE(mnem, op, nops, ops, ae) \
19137 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19139 #define C3(mnem, op, nops, ops, ae) \
19140 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19142 /* Legacy mnemonics that always have conditional infix after the third
19144 #define CL(mnem, op, nops, ops, ae) \
19145 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19146 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19148 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19149 #define cCE(mnem, op, nops, ops, ae) \
19150 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19152 /* Legacy coprocessor instructions where conditional infix and conditional
19153 suffix are ambiguous. For consistency this includes all FPA instructions,
19154 not just the potentially ambiguous ones. */
19155 #define cCL(mnem, op, nops, ops, ae) \
19156 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19157 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19159 /* Coprocessor, takes either a suffix or a position-3 infix
19160 (for an FPA corner case). */
19161 #define C3E(mnem, op, nops, ops, ae) \
19162 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19163 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19165 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19166 { m1 #m2 m3, OPS##nops ops, \
19167 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19168 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19170 #define CM(m1, m2, op, nops, ops, ae) \
19171 xCM_ (m1, , m2, op, nops, ops, ae), \
19172 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19173 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19174 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19175 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19176 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19177 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19178 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19179 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19180 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19181 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19182 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19183 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19184 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19185 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19186 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19187 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19188 xCM_ (m1, le, m2, op, nops, ops, ae), \
19189 xCM_ (m1, al, m2, op, nops, ops, ae)
19191 #define UE(mnem, op, nops, ops, ae) \
19192 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19194 #define UF(mnem, op, nops, ops, ae) \
19195 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19197 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19198 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19199 use the same encoding function for each. */
19200 #define NUF(mnem, op, nops, ops, enc) \
19201 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19202 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19204 /* Neon data processing, version which indirects through neon_enc_tab for
19205 the various overloaded versions of opcodes. */
19206 #define nUF(mnem, op, nops, ops, enc) \
19207 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19208 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19210 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19212 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19213 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19214 THUMB_VARIANT, do_##enc, do_##enc }
19216 #define NCE(mnem, op, nops, ops, enc) \
19217 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19219 #define NCEF(mnem, op, nops, ops, enc) \
19220 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19222 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19223 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19224 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19225 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19227 #define nCE(mnem, op, nops, ops, enc) \
19228 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19230 #define nCEF(mnem, op, nops, ops, enc) \
19231 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19235 static const struct asm_opcode insns
[] =
19237 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19238 #define THUMB_VARIANT & arm_ext_v4t
19239 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19240 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19241 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19242 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19243 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19244 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19245 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19246 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19247 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19248 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19249 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19250 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19251 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19252 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19253 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19254 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19256 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19257 for setting PSR flag bits. They are obsolete in V6 and do not
19258 have Thumb equivalents. */
19259 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19260 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19261 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19262 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19263 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19264 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19265 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19266 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19267 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19269 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19270 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19271 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19272 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19274 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19275 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19276 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19278 OP_ADDRGLDR
),ldst
, t_ldst
),
19279 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19281 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19282 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19283 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19284 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19285 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19286 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19288 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19289 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19292 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19293 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19294 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19295 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19297 /* Thumb-compatibility pseudo ops. */
19298 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19299 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19300 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19301 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19302 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19303 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19304 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19305 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19306 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19307 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19308 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19309 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19311 /* These may simplify to neg. */
19312 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19313 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19315 #undef THUMB_VARIANT
19316 #define THUMB_VARIANT & arm_ext_os
19318 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19319 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19321 #undef THUMB_VARIANT
19322 #define THUMB_VARIANT & arm_ext_v6
19324 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19326 /* V1 instructions with no Thumb analogue prior to V6T2. */
19327 #undef THUMB_VARIANT
19328 #define THUMB_VARIANT & arm_ext_v6t2
19330 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19331 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19332 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19334 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19335 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19336 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19337 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19339 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19340 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19342 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19343 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19345 /* V1 instructions with no Thumb analogue at all. */
19346 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19347 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19349 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19350 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19351 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19352 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19353 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19354 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19355 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19356 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19359 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19360 #undef THUMB_VARIANT
19361 #define THUMB_VARIANT & arm_ext_v4t
19363 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19364 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19366 #undef THUMB_VARIANT
19367 #define THUMB_VARIANT & arm_ext_v6t2
19369 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19370 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19372 /* Generic coprocessor instructions. */
19373 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19374 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19375 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19376 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19377 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19378 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19379 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19382 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19384 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19385 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19388 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19389 #undef THUMB_VARIANT
19390 #define THUMB_VARIANT & arm_ext_msr
19392 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19393 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19396 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19397 #undef THUMB_VARIANT
19398 #define THUMB_VARIANT & arm_ext_v6t2
19400 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19401 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19402 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19403 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19404 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19405 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19406 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19407 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19410 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19411 #undef THUMB_VARIANT
19412 #define THUMB_VARIANT & arm_ext_v4t
19414 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19415 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19416 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19417 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19418 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19419 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19422 #define ARM_VARIANT & arm_ext_v4t_5
19424 /* ARM Architecture 4T. */
19425 /* Note: bx (and blx) are required on V5, even if the processor does
19426 not support Thumb. */
19427 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19430 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19431 #undef THUMB_VARIANT
19432 #define THUMB_VARIANT & arm_ext_v5t
19434 /* Note: blx has 2 variants; the .value coded here is for
19435 BLX(2). Only this variant has conditional execution. */
19436 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19437 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19439 #undef THUMB_VARIANT
19440 #define THUMB_VARIANT & arm_ext_v6t2
19442 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19443 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19444 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19445 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19446 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19447 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19448 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19449 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19452 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19453 #undef THUMB_VARIANT
19454 #define THUMB_VARIANT & arm_ext_v5exp
19456 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19457 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19458 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19459 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19461 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19462 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19464 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19465 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19466 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19467 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19469 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19470 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19471 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19472 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19474 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19475 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19477 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19478 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19479 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19480 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19483 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19484 #undef THUMB_VARIANT
19485 #define THUMB_VARIANT & arm_ext_v6t2
19487 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19488 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19490 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19491 ADDRGLDRS
), ldrd
, t_ldstd
),
19493 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19494 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19497 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19499 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19502 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19503 #undef THUMB_VARIANT
19504 #define THUMB_VARIANT & arm_ext_v6
19506 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19507 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19508 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19509 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19510 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19511 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19512 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19513 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19514 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19515 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19517 #undef THUMB_VARIANT
19518 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19520 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19521 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19523 #undef THUMB_VARIANT
19524 #define THUMB_VARIANT & arm_ext_v6t2
19526 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19527 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19529 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19530 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19532 /* ARM V6 not included in V7M. */
19533 #undef THUMB_VARIANT
19534 #define THUMB_VARIANT & arm_ext_v6_notm
19535 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19536 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19537 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19538 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19539 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19540 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19541 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19542 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19543 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19544 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19545 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19546 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19547 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19548 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19549 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19550 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19551 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19552 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19553 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19555 /* ARM V6 not included in V7M (eg. integer SIMD). */
19556 #undef THUMB_VARIANT
19557 #define THUMB_VARIANT & arm_ext_v6_dsp
19558 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19559 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19560 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19561 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19562 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19563 /* Old name for QASX. */
19564 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19565 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19566 /* Old name for QSAX. */
19567 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19569 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19570 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19571 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19572 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19573 /* Old name for SASX. */
19574 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19576 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19577 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19578 /* Old name for SHASX. */
19579 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19580 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 /* Old name for SHSAX. */
19582 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19583 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19585 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19586 /* Old name for SSAX. */
19587 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19588 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19589 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19590 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19591 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19592 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19593 /* Old name for UASX. */
19594 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19595 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19596 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19597 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19598 /* Old name for UHASX. */
19599 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19600 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19601 /* Old name for UHSAX. */
19602 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19603 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19604 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19605 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19606 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19607 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19608 /* Old name for UQASX. */
19609 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19610 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19611 /* Old name for UQSAX. */
19612 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19613 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19614 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19615 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19616 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19617 /* Old name for USAX. */
19618 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19619 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19620 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19621 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19622 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19623 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19624 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19625 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19626 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19627 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19628 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19629 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19630 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19631 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19632 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19633 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19634 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19635 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19636 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19637 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19638 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19639 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19640 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19641 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19642 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19643 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19644 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19645 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19646 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19647 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19648 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19649 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19650 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19651 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19654 #define ARM_VARIANT & arm_ext_v6k
19655 #undef THUMB_VARIANT
19656 #define THUMB_VARIANT & arm_ext_v6k
19658 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19659 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19660 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19661 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19663 #undef THUMB_VARIANT
19664 #define THUMB_VARIANT & arm_ext_v6_notm
19665 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19667 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19668 RRnpcb
), strexd
, t_strexd
),
19670 #undef THUMB_VARIANT
19671 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19672 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19674 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19676 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19678 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19680 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19683 #define ARM_VARIANT & arm_ext_sec
19684 #undef THUMB_VARIANT
19685 #define THUMB_VARIANT & arm_ext_sec
19687 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19690 #define ARM_VARIANT & arm_ext_virt
19691 #undef THUMB_VARIANT
19692 #define THUMB_VARIANT & arm_ext_virt
19694 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19695 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19698 #define ARM_VARIANT & arm_ext_pan
19699 #undef THUMB_VARIANT
19700 #define THUMB_VARIANT & arm_ext_pan
19702 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19705 #define ARM_VARIANT & arm_ext_v6t2
19706 #undef THUMB_VARIANT
19707 #define THUMB_VARIANT & arm_ext_v6t2
19709 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19710 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19711 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19712 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19714 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19715 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19717 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19718 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19719 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19720 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19722 #undef THUMB_VARIANT
19723 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19724 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19725 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19727 /* Thumb-only instructions. */
19729 #define ARM_VARIANT NULL
19730 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19731 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19733 /* ARM does not really have an IT instruction, so always allow it.
19734 The opcode is copied from Thumb in order to allow warnings in
19735 -mimplicit-it=[never | arm] modes. */
19737 #define ARM_VARIANT & arm_ext_v1
19738 #undef THUMB_VARIANT
19739 #define THUMB_VARIANT & arm_ext_v6t2
19741 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19742 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19743 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19744 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19745 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19746 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19747 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19748 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19749 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19750 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19751 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19752 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19753 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19754 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19755 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19756 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19757 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19758 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19760 /* Thumb2 only instructions. */
19762 #define ARM_VARIANT NULL
19764 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19765 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19766 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19767 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19768 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19769 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19771 /* Hardware division instructions. */
19773 #define ARM_VARIANT & arm_ext_adiv
19774 #undef THUMB_VARIANT
19775 #define THUMB_VARIANT & arm_ext_div
19777 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19778 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19780 /* ARM V6M/V7 instructions. */
19782 #define ARM_VARIANT & arm_ext_barrier
19783 #undef THUMB_VARIANT
19784 #define THUMB_VARIANT & arm_ext_barrier
19786 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19787 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19788 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19790 /* ARM V7 instructions. */
19792 #define ARM_VARIANT & arm_ext_v7
19793 #undef THUMB_VARIANT
19794 #define THUMB_VARIANT & arm_ext_v7
19796 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19797 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19800 #define ARM_VARIANT & arm_ext_mp
19801 #undef THUMB_VARIANT
19802 #define THUMB_VARIANT & arm_ext_mp
19804 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19806 /* AArchv8 instructions. */
19808 #define ARM_VARIANT & arm_ext_v8
19810 /* Instructions shared between armv8-a and armv8-m. */
19811 #undef THUMB_VARIANT
19812 #define THUMB_VARIANT & arm_ext_atomics
19814 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19815 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19816 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19817 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19818 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19819 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19820 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19821 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19822 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19823 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19825 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19827 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19829 #undef THUMB_VARIANT
19830 #define THUMB_VARIANT & arm_ext_v8
19832 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19833 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19834 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19836 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19838 /* ARMv8 T32 only. */
19840 #define ARM_VARIANT NULL
19841 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19842 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19843 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19845 /* FP for ARMv8. */
19847 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19848 #undef THUMB_VARIANT
19849 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19851 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19852 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19853 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19854 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19855 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19856 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19857 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19858 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19859 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19860 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19861 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19862 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19863 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19864 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19865 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19866 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19867 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19869 /* Crypto v1 extensions. */
19871 #define ARM_VARIANT & fpu_crypto_ext_armv8
19872 #undef THUMB_VARIANT
19873 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19875 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19876 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19877 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19878 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19879 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19880 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19881 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19882 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19883 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19884 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19885 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19886 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19887 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19888 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19891 #define ARM_VARIANT & crc_ext_armv8
19892 #undef THUMB_VARIANT
19893 #define THUMB_VARIANT & crc_ext_armv8
19894 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19895 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19896 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19897 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19898 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19899 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19901 /* ARMv8.2 RAS extension. */
19903 #define ARM_VARIANT & arm_ext_ras
19904 #undef THUMB_VARIANT
19905 #define THUMB_VARIANT & arm_ext_ras
19906 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19909 #define ARM_VARIANT & arm_ext_v8_3
19910 #undef THUMB_VARIANT
19911 #define THUMB_VARIANT & arm_ext_v8_3
19912 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19913 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19914 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19917 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19918 #undef THUMB_VARIANT
19919 #define THUMB_VARIANT NULL
19921 cCE("wfs", e200110
, 1, (RR
), rd
),
19922 cCE("rfs", e300110
, 1, (RR
), rd
),
19923 cCE("wfc", e400110
, 1, (RR
), rd
),
19924 cCE("rfc", e500110
, 1, (RR
), rd
),
19926 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19927 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19928 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19929 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19931 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19932 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19933 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19934 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19936 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20010 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20023 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20036 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20114 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20115 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20120 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20126 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20127 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20128 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20129 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20131 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20132 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20133 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20134 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20135 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20136 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20137 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20138 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20139 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20140 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20141 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20142 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20144 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20179 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20192 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20201 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20205 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20206 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20211 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20214 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20218 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20219 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20224 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20227 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20231 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20232 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20244 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20283 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20284 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20289 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20295 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20296 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20297 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20298 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20300 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20301 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20302 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20303 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20304 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20305 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20306 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20307 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20308 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20309 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20310 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20311 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20313 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20314 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20315 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20316 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20318 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20319 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20320 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20321 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20322 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20323 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20324 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20325 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20326 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20327 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20328 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20329 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20331 /* The implementation of the FIX instruction is broken on some
20332 assemblers, in that it accepts a precision specifier as well as a
20333 rounding specifier, despite the fact that this is meaningless.
20334 To be more compatible, we accept it as well, though of course it
20335 does not set any bits. */
20336 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20337 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20338 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20339 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20340 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20341 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20342 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20343 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20344 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20345 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20346 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20347 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20348 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20350 /* Instructions that were new with the real FPA, call them V2. */
20352 #define ARM_VARIANT & fpu_fpa_ext_v2
20354 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20355 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20356 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20357 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20358 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20359 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20362 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20364 /* Moves and type conversions. */
20365 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20366 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20367 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20368 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20369 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20370 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20371 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20372 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20373 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20374 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20375 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20376 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20377 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20378 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20380 /* Memory operations. */
20381 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20382 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20383 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20384 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20385 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20386 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20387 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20388 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20389 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20390 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20391 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20392 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20393 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20394 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20395 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20396 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20397 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20398 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20400 /* Monadic operations. */
20401 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20402 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20403 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20405 /* Dyadic operations. */
20406 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20407 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20408 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20409 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20410 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20411 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20412 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20413 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20414 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20417 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20418 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20419 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20420 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20422 /* Double precision load/store are still present on single precision
20423 implementations. */
20424 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20425 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20426 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20427 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20428 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20429 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20430 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20431 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20432 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20433 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20436 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20438 /* Moves and type conversions. */
20439 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20440 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20441 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20442 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20443 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20444 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20445 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20446 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20447 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20448 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20449 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20450 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20451 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20453 /* Monadic operations. */
20454 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20455 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20456 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20458 /* Dyadic operations. */
20459 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20460 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20461 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20462 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20463 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20464 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20465 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20466 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20467 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20470 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20471 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20472 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20473 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20476 #define ARM_VARIANT & fpu_vfp_ext_v2
20478 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20479 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20480 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20481 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20483 /* Instructions which may belong to either the Neon or VFP instruction sets.
20484 Individual encoder functions perform additional architecture checks. */
20486 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20487 #undef THUMB_VARIANT
20488 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20490 /* These mnemonics are unique to VFP. */
20491 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20492 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20493 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20494 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20495 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20496 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20497 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20498 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20499 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20500 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20502 /* Mnemonics shared by Neon and VFP. */
20503 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20504 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20505 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20507 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20508 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20510 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20511 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20513 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20514 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20515 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20516 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20517 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20518 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20519 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20520 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20522 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20523 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20524 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20525 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20528 /* NOTE: All VMOV encoding is special-cased! */
20529 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20530 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20533 #define ARM_VARIANT & arm_ext_fp16
20534 #undef THUMB_VARIANT
20535 #define THUMB_VARIANT & arm_ext_fp16
20536 /* New instructions added from v8.2, allowing the extraction and insertion of
20537 the upper 16 bits of a 32-bit vector register. */
20538 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20539 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20541 #undef THUMB_VARIANT
20542 #define THUMB_VARIANT & fpu_neon_ext_v1
20544 #define ARM_VARIANT & fpu_neon_ext_v1
20546 /* Data processing with three registers of the same length. */
20547 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20548 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20549 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20550 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20551 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20552 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20553 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20554 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20555 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20556 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20557 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20558 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20559 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20560 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20561 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20562 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20563 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20564 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20565 /* If not immediate, fall back to neon_dyadic_i64_su.
20566 shl_imm should accept I8 I16 I32 I64,
20567 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20568 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20569 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20570 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20571 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20572 /* Logic ops, types optional & ignored. */
20573 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20574 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20575 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20576 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20577 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20578 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20579 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20580 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20581 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20582 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20583 /* Bitfield ops, untyped. */
20584 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20585 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20586 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20587 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20588 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20589 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20590 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20591 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20592 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20593 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20594 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20595 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20596 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20597 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20598 back to neon_dyadic_if_su. */
20599 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20600 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20601 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20602 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20603 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20604 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20605 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20606 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20607 /* Comparison. Type I8 I16 I32 F32. */
20608 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20609 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20610 /* As above, D registers only. */
20611 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20612 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20613 /* Int and float variants, signedness unimportant. */
20614 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20615 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20616 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20617 /* Add/sub take types I8 I16 I32 I64 F32. */
20618 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20619 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20620 /* vtst takes sizes 8, 16, 32. */
20621 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20622 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20623 /* VMUL takes I8 I16 I32 F32 P8. */
20624 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20625 /* VQD{R}MULH takes S16 S32. */
20626 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20627 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20628 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20629 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20630 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20631 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20632 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20633 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20634 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20635 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20636 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20637 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20638 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20639 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20640 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20641 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20642 /* ARM v8.1 extension. */
20643 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20644 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20645 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20646 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20648 /* Two address, int/float. Types S8 S16 S32 F32. */
20649 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20650 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20652 /* Data processing with two registers and a shift amount. */
20653 /* Right shifts, and variants with rounding.
20654 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20655 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20656 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20657 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20658 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20659 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20660 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20661 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20662 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20663 /* Shift and insert. Sizes accepted 8 16 32 64. */
20664 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20665 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20666 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20667 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20668 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20669 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20670 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20671 /* Right shift immediate, saturating & narrowing, with rounding variants.
20672 Types accepted S16 S32 S64 U16 U32 U64. */
20673 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20674 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20675 /* As above, unsigned. Types accepted S16 S32 S64. */
20676 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20677 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20678 /* Right shift narrowing. Types accepted I16 I32 I64. */
20679 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20680 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20681 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20682 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20683 /* CVT with optional immediate for fixed-point variant. */
20684 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20686 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20687 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20689 /* Data processing, three registers of different lengths. */
20690 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20691 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20692 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20693 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20694 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20695 /* If not scalar, fall back to neon_dyadic_long.
20696 Vector types as above, scalar types S16 S32 U16 U32. */
20697 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20698 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20699 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20700 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20701 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20702 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20703 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20704 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20705 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20706 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20707 /* Saturating doubling multiplies. Types S16 S32. */
20708 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20709 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20710 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20711 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20712 S16 S32 U16 U32. */
20713 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20715 /* Extract. Size 8. */
20716 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20717 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20719 /* Two registers, miscellaneous. */
20720 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20721 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20722 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20723 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20724 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20725 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20726 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20727 /* Vector replicate. Sizes 8 16 32. */
20728 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20729 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20730 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20731 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20732 /* VMOVN. Types I16 I32 I64. */
20733 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20734 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20735 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20736 /* VQMOVUN. Types S16 S32 S64. */
20737 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20738 /* VZIP / VUZP. Sizes 8 16 32. */
20739 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20740 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20741 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20742 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20743 /* VQABS / VQNEG. Types S8 S16 S32. */
20744 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20745 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20746 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20747 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20748 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20749 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20750 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20751 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20752 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20753 /* Reciprocal estimates. Types U32 F16 F32. */
20754 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20755 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20756 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20757 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20758 /* VCLS. Types S8 S16 S32. */
20759 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20760 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20761 /* VCLZ. Types I8 I16 I32. */
20762 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20763 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20764 /* VCNT. Size 8. */
20765 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20766 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20767 /* Two address, untyped. */
20768 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20769 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20770 /* VTRN. Sizes 8 16 32. */
20771 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20772 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20774 /* Table lookup. Size 8. */
20775 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20776 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20778 #undef THUMB_VARIANT
20779 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20781 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20783 /* Neon element/structure load/store. */
20784 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20785 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20786 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20787 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20788 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20789 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20790 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20791 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20793 #undef THUMB_VARIANT
20794 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20796 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20797 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20798 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20799 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20800 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20801 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20802 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20803 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20804 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20805 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20807 #undef THUMB_VARIANT
20808 #define THUMB_VARIANT & fpu_vfp_ext_v3
20810 #define ARM_VARIANT & fpu_vfp_ext_v3
20812 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20813 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20814 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20815 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20816 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20817 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20818 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20819 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20820 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20823 #define ARM_VARIANT & fpu_vfp_ext_fma
20824 #undef THUMB_VARIANT
20825 #define THUMB_VARIANT & fpu_vfp_ext_fma
20826 /* Mnemonics shared by Neon and VFP. These are included in the
20827 VFP FMA variant; NEON and VFP FMA always includes the NEON
20828 FMA instructions. */
20829 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20830 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20831 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20832 the v form should always be used. */
20833 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20834 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20835 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20836 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20837 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20838 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20840 #undef THUMB_VARIANT
20842 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20844 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20845 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20846 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20847 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20848 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20849 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20850 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20851 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20854 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20856 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20857 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20858 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20859 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20860 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20861 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20862 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20863 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20864 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20865 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20866 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20867 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20868 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20869 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20870 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20871 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20872 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20873 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20874 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20875 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20876 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20877 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20878 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20879 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20880 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20881 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20882 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20883 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20884 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20885 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20886 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20887 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20888 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20889 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20890 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20891 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20892 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20893 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20903 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20923 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20924 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20925 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20926 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20928 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20929 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20939 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20940 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20941 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20942 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20943 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20944 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20945 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20946 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20947 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20948 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20949 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20950 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20951 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20952 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20953 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20954 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20955 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20956 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20957 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20958 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20959 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20960 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20961 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20962 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20963 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20964 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20965 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20966 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20967 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20968 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20969 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20970 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20971 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20972 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20973 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20974 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20975 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20976 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20977 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20978 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20979 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20980 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20981 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20982 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20983 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20984 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20985 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20986 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20987 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20988 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20989 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20990 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20991 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20992 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20993 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20994 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20995 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20997 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20999 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21000 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21001 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21002 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21003 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21004 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21006 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21007 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21008 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21009 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21010 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21011 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21012 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21013 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21014 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21020 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21022 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21023 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21024 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21025 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21026 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21027 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21028 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21043 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21046 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21050 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21051 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21056 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21057 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21058 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21059 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21060 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21061 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21062 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21063 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21064 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21065 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21066 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21067 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21068 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21069 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21070 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21071 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21072 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21073 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21074 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21075 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21076 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21077 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21078 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21081 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21083 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21084 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21085 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21086 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21087 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21088 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21089 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21090 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21091 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21092 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21093 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21094 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21095 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21096 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21097 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21098 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21099 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21100 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21101 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21102 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21103 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21104 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21105 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21106 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21107 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21108 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21109 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21110 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21111 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21112 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21113 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21114 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21115 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21116 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21117 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21118 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21119 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21120 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21121 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21122 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21123 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21124 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21125 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21126 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21127 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21128 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21129 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21130 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21131 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21132 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21133 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21134 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21135 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21136 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21137 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21138 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21139 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21140 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21141 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21142 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21143 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21144 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21145 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21146 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21147 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21148 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21149 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21150 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21151 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21152 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21153 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21154 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21155 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21156 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21157 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21158 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21160 /* ARMv8-M instructions. */
21162 #define ARM_VARIANT NULL
21163 #undef THUMB_VARIANT
21164 #define THUMB_VARIANT & arm_ext_v8m
21165 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21166 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21167 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21168 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21169 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21170 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21171 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21173 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21174 instructions behave as nop if no VFP is present. */
21175 #undef THUMB_VARIANT
21176 #define THUMB_VARIANT & arm_ext_v8m_main
21177 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21178 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21181 #undef THUMB_VARIANT
21207 /* MD interface: bits in the object file. */
21209 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21210 for use in the a.out file, and stores them in the array pointed to by buf.
21211 This knows about the endian-ness of the target machine and does
21212 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21213 2 (short) and 4 (long) Floating numbers are put out as a series of
21214 LITTLENUMS (shorts, here at least). */
21217 md_number_to_chars (char * buf
, valueT val
, int n
)
21219 if (target_big_endian
)
21220 number_to_chars_bigendian (buf
, val
, n
);
21222 number_to_chars_littleendian (buf
, val
, n
);
21226 md_chars_to_number (char * buf
, int n
)
21229 unsigned char * where
= (unsigned char *) buf
;
21231 if (target_big_endian
)
21236 result
|= (*where
++ & 255);
21244 result
|= (where
[n
] & 255);
21251 /* MD interface: Sections. */
21253 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21254 that an rs_machine_dependent frag may reach. */
21257 arm_frag_max_var (fragS
*fragp
)
21259 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21260 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21262 Note that we generate relaxable instructions even for cases that don't
21263 really need it, like an immediate that's a trivial constant. So we're
21264 overestimating the instruction size for some of those cases. Rather
21265 than putting more intelligence here, it would probably be better to
21266 avoid generating a relaxation frag in the first place when it can be
21267 determined up front that a short instruction will suffice. */
21269 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21273 /* Estimate the size of a frag before relaxing. Assume everything fits in
21277 md_estimate_size_before_relax (fragS
* fragp
,
21278 segT segtype ATTRIBUTE_UNUSED
)
21284 /* Convert a machine dependent frag. */
21287 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21289 unsigned long insn
;
21290 unsigned long old_op
;
21298 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21300 old_op
= bfd_get_16(abfd
, buf
);
21301 if (fragp
->fr_symbol
)
21303 exp
.X_op
= O_symbol
;
21304 exp
.X_add_symbol
= fragp
->fr_symbol
;
21308 exp
.X_op
= O_constant
;
21310 exp
.X_add_number
= fragp
->fr_offset
;
21311 opcode
= fragp
->fr_subtype
;
21314 case T_MNEM_ldr_pc
:
21315 case T_MNEM_ldr_pc2
:
21316 case T_MNEM_ldr_sp
:
21317 case T_MNEM_str_sp
:
21324 if (fragp
->fr_var
== 4)
21326 insn
= THUMB_OP32 (opcode
);
21327 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21329 insn
|= (old_op
& 0x700) << 4;
21333 insn
|= (old_op
& 7) << 12;
21334 insn
|= (old_op
& 0x38) << 13;
21336 insn
|= 0x00000c00;
21337 put_thumb32_insn (buf
, insn
);
21338 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21342 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21344 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21347 if (fragp
->fr_var
== 4)
21349 insn
= THUMB_OP32 (opcode
);
21350 insn
|= (old_op
& 0xf0) << 4;
21351 put_thumb32_insn (buf
, insn
);
21352 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21356 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21357 exp
.X_add_number
-= 4;
21365 if (fragp
->fr_var
== 4)
21367 int r0off
= (opcode
== T_MNEM_mov
21368 || opcode
== T_MNEM_movs
) ? 0 : 8;
21369 insn
= THUMB_OP32 (opcode
);
21370 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21371 insn
|= (old_op
& 0x700) << r0off
;
21372 put_thumb32_insn (buf
, insn
);
21373 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21377 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21382 if (fragp
->fr_var
== 4)
21384 insn
= THUMB_OP32(opcode
);
21385 put_thumb32_insn (buf
, insn
);
21386 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21389 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21393 if (fragp
->fr_var
== 4)
21395 insn
= THUMB_OP32(opcode
);
21396 insn
|= (old_op
& 0xf00) << 14;
21397 put_thumb32_insn (buf
, insn
);
21398 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21401 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21404 case T_MNEM_add_sp
:
21405 case T_MNEM_add_pc
:
21406 case T_MNEM_inc_sp
:
21407 case T_MNEM_dec_sp
:
21408 if (fragp
->fr_var
== 4)
21410 /* ??? Choose between add and addw. */
21411 insn
= THUMB_OP32 (opcode
);
21412 insn
|= (old_op
& 0xf0) << 4;
21413 put_thumb32_insn (buf
, insn
);
21414 if (opcode
== T_MNEM_add_pc
)
21415 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21417 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21420 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21428 if (fragp
->fr_var
== 4)
21430 insn
= THUMB_OP32 (opcode
);
21431 insn
|= (old_op
& 0xf0) << 4;
21432 insn
|= (old_op
& 0xf) << 16;
21433 put_thumb32_insn (buf
, insn
);
21434 if (insn
& (1 << 20))
21435 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21437 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21440 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21446 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21447 (enum bfd_reloc_code_real
) reloc_type
);
21448 fixp
->fx_file
= fragp
->fr_file
;
21449 fixp
->fx_line
= fragp
->fr_line
;
21450 fragp
->fr_fix
+= fragp
->fr_var
;
21452 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21453 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21454 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21455 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21458 /* Return the size of a relaxable immediate operand instruction.
21459 SHIFT and SIZE specify the form of the allowable immediate. */
21461 relax_immediate (fragS
*fragp
, int size
, int shift
)
21467 /* ??? Should be able to do better than this. */
21468 if (fragp
->fr_symbol
)
21471 low
= (1 << shift
) - 1;
21472 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21473 offset
= fragp
->fr_offset
;
21474 /* Force misaligned offsets to 32-bit variant. */
21477 if (offset
& ~mask
)
21482 /* Get the address of a symbol during relaxation. */
21484 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21490 sym
= fragp
->fr_symbol
;
21491 sym_frag
= symbol_get_frag (sym
);
21492 know (S_GET_SEGMENT (sym
) != absolute_section
21493 || sym_frag
== &zero_address_frag
);
21494 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21496 /* If frag has yet to be reached on this pass, assume it will
21497 move by STRETCH just as we did. If this is not so, it will
21498 be because some frag between grows, and that will force
21502 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21506 /* Adjust stretch for any alignment frag. Note that if have
21507 been expanding the earlier code, the symbol may be
21508 defined in what appears to be an earlier frag. FIXME:
21509 This doesn't handle the fr_subtype field, which specifies
21510 a maximum number of bytes to skip when doing an
21512 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21514 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21517 stretch
= - ((- stretch
)
21518 & ~ ((1 << (int) f
->fr_offset
) - 1));
21520 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21532 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21535 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21540 /* Assume worst case for symbols not known to be in the same section. */
21541 if (fragp
->fr_symbol
== NULL
21542 || !S_IS_DEFINED (fragp
->fr_symbol
)
21543 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21544 || S_IS_WEAK (fragp
->fr_symbol
))
21547 val
= relaxed_symbol_addr (fragp
, stretch
);
21548 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21549 addr
= (addr
+ 4) & ~3;
21550 /* Force misaligned targets to 32-bit variant. */
21554 if (val
< 0 || val
> 1020)
21559 /* Return the size of a relaxable add/sub immediate instruction. */
21561 relax_addsub (fragS
*fragp
, asection
*sec
)
21566 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21567 op
= bfd_get_16(sec
->owner
, buf
);
21568 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21569 return relax_immediate (fragp
, 8, 0);
21571 return relax_immediate (fragp
, 3, 0);
21574 /* Return TRUE iff the definition of symbol S could be pre-empted
21575 (overridden) at link or load time. */
21577 symbol_preemptible (symbolS
*s
)
21579 /* Weak symbols can always be pre-empted. */
21583 /* Non-global symbols cannot be pre-empted. */
21584 if (! S_IS_EXTERNAL (s
))
21588 /* In ELF, a global symbol can be marked protected, or private. In that
21589 case it can't be pre-empted (other definitions in the same link unit
21590 would violate the ODR). */
21591 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21595 /* Other global symbols might be pre-empted. */
21599 /* Return the size of a relaxable branch instruction. BITS is the
21600 size of the offset field in the narrow instruction. */
21603 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21609 /* Assume worst case for symbols not known to be in the same section. */
21610 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21611 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21612 || S_IS_WEAK (fragp
->fr_symbol
))
21616 /* A branch to a function in ARM state will require interworking. */
21617 if (S_IS_DEFINED (fragp
->fr_symbol
)
21618 && ARM_IS_FUNC (fragp
->fr_symbol
))
21622 if (symbol_preemptible (fragp
->fr_symbol
))
21625 val
= relaxed_symbol_addr (fragp
, stretch
);
21626 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21629 /* Offset is a signed value *2 */
21631 if (val
>= limit
|| val
< -limit
)
21637 /* Relax a machine dependent frag. This returns the amount by which
21638 the current size of the frag should change. */
21641 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21646 oldsize
= fragp
->fr_var
;
21647 switch (fragp
->fr_subtype
)
21649 case T_MNEM_ldr_pc2
:
21650 newsize
= relax_adr (fragp
, sec
, stretch
);
21652 case T_MNEM_ldr_pc
:
21653 case T_MNEM_ldr_sp
:
21654 case T_MNEM_str_sp
:
21655 newsize
= relax_immediate (fragp
, 8, 2);
21659 newsize
= relax_immediate (fragp
, 5, 2);
21663 newsize
= relax_immediate (fragp
, 5, 1);
21667 newsize
= relax_immediate (fragp
, 5, 0);
21670 newsize
= relax_adr (fragp
, sec
, stretch
);
21676 newsize
= relax_immediate (fragp
, 8, 0);
21679 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21682 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21684 case T_MNEM_add_sp
:
21685 case T_MNEM_add_pc
:
21686 newsize
= relax_immediate (fragp
, 8, 2);
21688 case T_MNEM_inc_sp
:
21689 case T_MNEM_dec_sp
:
21690 newsize
= relax_immediate (fragp
, 7, 2);
21696 newsize
= relax_addsub (fragp
, sec
);
21702 fragp
->fr_var
= newsize
;
21703 /* Freeze wide instructions that are at or before the same location as
21704 in the previous pass. This avoids infinite loops.
21705 Don't freeze them unconditionally because targets may be artificially
21706 misaligned by the expansion of preceding frags. */
21707 if (stretch
<= 0 && newsize
> 2)
21709 md_convert_frag (sec
->owner
, sec
, fragp
);
21713 return newsize
- oldsize
;
21716 /* Round up a section size to the appropriate boundary. */
21719 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21722 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21723 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21725 /* For a.out, force the section size to be aligned. If we don't do
21726 this, BFD will align it for us, but it will not write out the
21727 final bytes of the section. This may be a bug in BFD, but it is
21728 easier to fix it here since that is how the other a.out targets
21732 align
= bfd_get_section_alignment (stdoutput
, segment
);
21733 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21740 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21741 of an rs_align_code fragment. */
21744 arm_handle_align (fragS
* fragP
)
21746 static unsigned char const arm_noop
[2][2][4] =
21749 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21750 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21753 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21754 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21757 static unsigned char const thumb_noop
[2][2][2] =
21760 {0xc0, 0x46}, /* LE */
21761 {0x46, 0xc0}, /* BE */
21764 {0x00, 0xbf}, /* LE */
21765 {0xbf, 0x00} /* BE */
21768 static unsigned char const wide_thumb_noop
[2][4] =
21769 { /* Wide Thumb-2 */
21770 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21771 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21774 unsigned bytes
, fix
, noop_size
;
21776 const unsigned char * noop
;
21777 const unsigned char *narrow_noop
= NULL
;
21782 if (fragP
->fr_type
!= rs_align_code
)
21785 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21786 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21789 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21790 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21792 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21794 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21796 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21797 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21799 narrow_noop
= thumb_noop
[1][target_big_endian
];
21800 noop
= wide_thumb_noop
[target_big_endian
];
21803 noop
= thumb_noop
[0][target_big_endian
];
21811 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21812 ? selected_cpu
: arm_arch_none
,
21814 [target_big_endian
];
21821 fragP
->fr_var
= noop_size
;
21823 if (bytes
& (noop_size
- 1))
21825 fix
= bytes
& (noop_size
- 1);
21827 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21829 memset (p
, 0, fix
);
21836 if (bytes
& noop_size
)
21838 /* Insert a narrow noop. */
21839 memcpy (p
, narrow_noop
, noop_size
);
21841 bytes
-= noop_size
;
21845 /* Use wide noops for the remainder */
21849 while (bytes
>= noop_size
)
21851 memcpy (p
, noop
, noop_size
);
21853 bytes
-= noop_size
;
21857 fragP
->fr_fix
+= fix
;
21860 /* Called from md_do_align. Used to create an alignment
21861 frag in a code section. */
21864 arm_frag_align_code (int n
, int max
)
21868 /* We assume that there will never be a requirement
21869 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21870 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21875 _("alignments greater than %d bytes not supported in .text sections."),
21876 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21877 as_fatal ("%s", err_msg
);
21880 p
= frag_var (rs_align_code
,
21881 MAX_MEM_FOR_RS_ALIGN_CODE
,
21883 (relax_substateT
) max
,
21890 /* Perform target specific initialisation of a frag.
21891 Note - despite the name this initialisation is not done when the frag
21892 is created, but only when its type is assigned. A frag can be created
21893 and used a long time before its type is set, so beware of assuming that
21894 this initialisation is performed first. */
21898 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21900 /* Record whether this frag is in an ARM or a THUMB area. */
21901 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21904 #else /* OBJ_ELF is defined. */
21906 arm_init_frag (fragS
* fragP
, int max_chars
)
21908 int frag_thumb_mode
;
21910 /* If the current ARM vs THUMB mode has not already
21911 been recorded into this frag then do so now. */
21912 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21913 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21915 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21917 /* Record a mapping symbol for alignment frags. We will delete this
21918 later if the alignment ends up empty. */
21919 switch (fragP
->fr_type
)
21922 case rs_align_test
:
21924 mapping_state_2 (MAP_DATA
, max_chars
);
21926 case rs_align_code
:
21927 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21934 /* When we change sections we need to issue a new mapping symbol. */
21937 arm_elf_change_section (void)
21939 /* Link an unlinked unwind index table section to the .text section. */
21940 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21941 && elf_linked_to_section (now_seg
) == NULL
)
21942 elf_linked_to_section (now_seg
) = text_section
;
21946 arm_elf_section_type (const char * str
, size_t len
)
21948 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21949 return SHT_ARM_EXIDX
;
21954 /* Code to deal with unwinding tables. */
21956 static void add_unwind_adjustsp (offsetT
);
21958 /* Generate any deferred unwind frame offset. */
21961 flush_pending_unwind (void)
21965 offset
= unwind
.pending_offset
;
21966 unwind
.pending_offset
= 0;
21968 add_unwind_adjustsp (offset
);
21971 /* Add an opcode to this list for this function. Two-byte opcodes should
21972 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21976 add_unwind_opcode (valueT op
, int length
)
21978 /* Add any deferred stack adjustment. */
21979 if (unwind
.pending_offset
)
21980 flush_pending_unwind ();
21982 unwind
.sp_restored
= 0;
21984 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21986 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21987 if (unwind
.opcodes
)
21988 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21989 unwind
.opcode_alloc
);
21991 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21996 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21998 unwind
.opcode_count
++;
22002 /* Add unwind opcodes to adjust the stack pointer. */
22005 add_unwind_adjustsp (offsetT offset
)
22009 if (offset
> 0x200)
22011 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22016 /* Long form: 0xb2, uleb128. */
22017 /* This might not fit in a word so add the individual bytes,
22018 remembering the list is built in reverse order. */
22019 o
= (valueT
) ((offset
- 0x204) >> 2);
22021 add_unwind_opcode (0, 1);
22023 /* Calculate the uleb128 encoding of the offset. */
22027 bytes
[n
] = o
& 0x7f;
22033 /* Add the insn. */
22035 add_unwind_opcode (bytes
[n
- 1], 1);
22036 add_unwind_opcode (0xb2, 1);
22038 else if (offset
> 0x100)
22040 /* Two short opcodes. */
22041 add_unwind_opcode (0x3f, 1);
22042 op
= (offset
- 0x104) >> 2;
22043 add_unwind_opcode (op
, 1);
22045 else if (offset
> 0)
22047 /* Short opcode. */
22048 op
= (offset
- 4) >> 2;
22049 add_unwind_opcode (op
, 1);
22051 else if (offset
< 0)
22054 while (offset
> 0x100)
22056 add_unwind_opcode (0x7f, 1);
22059 op
= ((offset
- 4) >> 2) | 0x40;
22060 add_unwind_opcode (op
, 1);
22064 /* Finish the list of unwind opcodes for this function. */
22066 finish_unwind_opcodes (void)
22070 if (unwind
.fp_used
)
22072 /* Adjust sp as necessary. */
22073 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22074 flush_pending_unwind ();
22076 /* After restoring sp from the frame pointer. */
22077 op
= 0x90 | unwind
.fp_reg
;
22078 add_unwind_opcode (op
, 1);
22081 flush_pending_unwind ();
22085 /* Start an exception table entry. If idx is nonzero this is an index table
22089 start_unwind_section (const segT text_seg
, int idx
)
22091 const char * text_name
;
22092 const char * prefix
;
22093 const char * prefix_once
;
22094 const char * group_name
;
22102 prefix
= ELF_STRING_ARM_unwind
;
22103 prefix_once
= ELF_STRING_ARM_unwind_once
;
22104 type
= SHT_ARM_EXIDX
;
22108 prefix
= ELF_STRING_ARM_unwind_info
;
22109 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22110 type
= SHT_PROGBITS
;
22113 text_name
= segment_name (text_seg
);
22114 if (streq (text_name
, ".text"))
22117 if (strncmp (text_name
, ".gnu.linkonce.t.",
22118 strlen (".gnu.linkonce.t.")) == 0)
22120 prefix
= prefix_once
;
22121 text_name
+= strlen (".gnu.linkonce.t.");
22124 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22130 /* Handle COMDAT group. */
22131 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22133 group_name
= elf_group_name (text_seg
);
22134 if (group_name
== NULL
)
22136 as_bad (_("Group section `%s' has no group signature"),
22137 segment_name (text_seg
));
22138 ignore_rest_of_line ();
22141 flags
|= SHF_GROUP
;
22145 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22148 /* Set the section link for index tables. */
22150 elf_linked_to_section (now_seg
) = text_seg
;
22154 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22155 personality routine data. Returns zero, or the index table value for
22156 an inline entry. */
22159 create_unwind_entry (int have_data
)
22164 /* The current word of data. */
22166 /* The number of bytes left in this word. */
22169 finish_unwind_opcodes ();
22171 /* Remember the current text section. */
22172 unwind
.saved_seg
= now_seg
;
22173 unwind
.saved_subseg
= now_subseg
;
22175 start_unwind_section (now_seg
, 0);
22177 if (unwind
.personality_routine
== NULL
)
22179 if (unwind
.personality_index
== -2)
22182 as_bad (_("handlerdata in cantunwind frame"));
22183 return 1; /* EXIDX_CANTUNWIND. */
22186 /* Use a default personality routine if none is specified. */
22187 if (unwind
.personality_index
== -1)
22189 if (unwind
.opcode_count
> 3)
22190 unwind
.personality_index
= 1;
22192 unwind
.personality_index
= 0;
22195 /* Space for the personality routine entry. */
22196 if (unwind
.personality_index
== 0)
22198 if (unwind
.opcode_count
> 3)
22199 as_bad (_("too many unwind opcodes for personality routine 0"));
22203 /* All the data is inline in the index table. */
22206 while (unwind
.opcode_count
> 0)
22208 unwind
.opcode_count
--;
22209 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22213 /* Pad with "finish" opcodes. */
22215 data
= (data
<< 8) | 0xb0;
22222 /* We get two opcodes "free" in the first word. */
22223 size
= unwind
.opcode_count
- 2;
22227 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22228 if (unwind
.personality_index
!= -1)
22230 as_bad (_("attempt to recreate an unwind entry"));
22234 /* An extra byte is required for the opcode count. */
22235 size
= unwind
.opcode_count
+ 1;
22238 size
= (size
+ 3) >> 2;
22240 as_bad (_("too many unwind opcodes"));
22242 frag_align (2, 0, 0);
22243 record_alignment (now_seg
, 2);
22244 unwind
.table_entry
= expr_build_dot ();
22246 /* Allocate the table entry. */
22247 ptr
= frag_more ((size
<< 2) + 4);
22248 /* PR 13449: Zero the table entries in case some of them are not used. */
22249 memset (ptr
, 0, (size
<< 2) + 4);
22250 where
= frag_now_fix () - ((size
<< 2) + 4);
22252 switch (unwind
.personality_index
)
22255 /* ??? Should this be a PLT generating relocation? */
22256 /* Custom personality routine. */
22257 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22258 BFD_RELOC_ARM_PREL31
);
22263 /* Set the first byte to the number of additional words. */
22264 data
= size
> 0 ? size
- 1 : 0;
22268 /* ABI defined personality routines. */
22270 /* Three opcodes bytes are packed into the first word. */
22277 /* The size and first two opcode bytes go in the first word. */
22278 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22283 /* Should never happen. */
22287 /* Pack the opcodes into words (MSB first), reversing the list at the same
22289 while (unwind
.opcode_count
> 0)
22293 md_number_to_chars (ptr
, data
, 4);
22298 unwind
.opcode_count
--;
22300 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22303 /* Finish off the last word. */
22306 /* Pad with "finish" opcodes. */
22308 data
= (data
<< 8) | 0xb0;
22310 md_number_to_chars (ptr
, data
, 4);
22315 /* Add an empty descriptor if there is no user-specified data. */
22316 ptr
= frag_more (4);
22317 md_number_to_chars (ptr
, 0, 4);
22324 /* Initialize the DWARF-2 unwind information for this procedure. */
22327 tc_arm_frame_initial_instructions (void)
22329 cfi_add_CFA_def_cfa (REG_SP
, 0);
22331 #endif /* OBJ_ELF */
22333 /* Convert REGNAME to a DWARF-2 register number. */
22336 tc_arm_regname_to_dw2regnum (char *regname
)
22338 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22342 /* PR 16694: Allow VFP registers as well. */
22343 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22347 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22356 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22360 exp
.X_op
= O_secrel
;
22361 exp
.X_add_symbol
= symbol
;
22362 exp
.X_add_number
= 0;
22363 emit_expr (&exp
, size
);
22367 /* MD interface: Symbol and relocation handling. */
22369 /* Return the address within the segment that a PC-relative fixup is
22370 relative to. For ARM, PC-relative fixups applied to instructions
22371 are generally relative to the location of the fixup plus 8 bytes.
22372 Thumb branches are offset by 4, and Thumb loads relative to PC
22373 require special handling. */
22376 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22378 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22380 /* If this is pc-relative and we are going to emit a relocation
22381 then we just want to put out any pipeline compensation that the linker
22382 will need. Otherwise we want to use the calculated base.
22383 For WinCE we skip the bias for externals as well, since this
22384 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22386 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22387 || (arm_force_relocation (fixP
)
22389 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22395 switch (fixP
->fx_r_type
)
22397 /* PC relative addressing on the Thumb is slightly odd as the
22398 bottom two bits of the PC are forced to zero for the
22399 calculation. This happens *after* application of the
22400 pipeline offset. However, Thumb adrl already adjusts for
22401 this, so we need not do it again. */
22402 case BFD_RELOC_ARM_THUMB_ADD
:
22405 case BFD_RELOC_ARM_THUMB_OFFSET
:
22406 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22407 case BFD_RELOC_ARM_T32_ADD_PC12
:
22408 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22409 return (base
+ 4) & ~3;
22411 /* Thumb branches are simply offset by +4. */
22412 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22413 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22414 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22415 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22416 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22419 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22421 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22422 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22423 && ARM_IS_FUNC (fixP
->fx_addsy
)
22424 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22425 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22428 /* BLX is like branches above, but forces the low two bits of PC to
22430 case BFD_RELOC_THUMB_PCREL_BLX
:
22432 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22433 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22434 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22435 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22436 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22437 return (base
+ 4) & ~3;
22439 /* ARM mode branches are offset by +8. However, the Windows CE
22440 loader expects the relocation not to take this into account. */
22441 case BFD_RELOC_ARM_PCREL_BLX
:
22443 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22444 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22445 && ARM_IS_FUNC (fixP
->fx_addsy
)
22446 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22447 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22450 case BFD_RELOC_ARM_PCREL_CALL
:
22452 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22453 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22454 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22455 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22456 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22459 case BFD_RELOC_ARM_PCREL_BRANCH
:
22460 case BFD_RELOC_ARM_PCREL_JUMP
:
22461 case BFD_RELOC_ARM_PLT32
:
22463 /* When handling fixups immediately, because we have already
22464 discovered the value of a symbol, or the address of the frag involved
22465 we must account for the offset by +8, as the OS loader will never see the reloc.
22466 see fixup_segment() in write.c
22467 The S_IS_EXTERNAL test handles the case of global symbols.
22468 Those need the calculated base, not just the pipe compensation the linker will need. */
22470 && fixP
->fx_addsy
!= NULL
22471 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22472 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22480 /* ARM mode loads relative to PC are also offset by +8. Unlike
22481 branches, the Windows CE loader *does* expect the relocation
22482 to take this into account. */
22483 case BFD_RELOC_ARM_OFFSET_IMM
:
22484 case BFD_RELOC_ARM_OFFSET_IMM8
:
22485 case BFD_RELOC_ARM_HWLITERAL
:
22486 case BFD_RELOC_ARM_LITERAL
:
22487 case BFD_RELOC_ARM_CP_OFF_IMM
:
22491 /* Other PC-relative relocations are un-offset. */
22497 static bfd_boolean flag_warn_syms
= TRUE
;
22500 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22502 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22503 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22504 does mean that the resulting code might be very confusing to the reader.
22505 Also this warning can be triggered if the user omits an operand before
22506 an immediate address, eg:
22510 GAS treats this as an assignment of the value of the symbol foo to a
22511 symbol LDR, and so (without this code) it will not issue any kind of
22512 warning or error message.
22514 Note - ARM instructions are case-insensitive but the strings in the hash
22515 table are all stored in lower case, so we must first ensure that name is
22517 if (flag_warn_syms
&& arm_ops_hsh
)
22519 char * nbuf
= strdup (name
);
22522 for (p
= nbuf
; *p
; p
++)
22524 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22526 static struct hash_control
* already_warned
= NULL
;
22528 if (already_warned
== NULL
)
22529 already_warned
= hash_new ();
22530 /* Only warn about the symbol once. To keep the code
22531 simple we let hash_insert do the lookup for us. */
22532 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22533 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22542 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22543 Otherwise we have no need to default values of symbols. */
22546 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22549 if (name
[0] == '_' && name
[1] == 'G'
22550 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22554 if (symbol_find (name
))
22555 as_bad (_("GOT already in the symbol table"));
22557 GOT_symbol
= symbol_new (name
, undefined_section
,
22558 (valueT
) 0, & zero_address_frag
);
22568 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22569 computed as two separate immediate values, added together. We
22570 already know that this value cannot be computed by just one ARM
22573 static unsigned int
22574 validate_immediate_twopart (unsigned int val
,
22575 unsigned int * highpart
)
22580 for (i
= 0; i
< 32; i
+= 2)
22581 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22587 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22589 else if (a
& 0xff0000)
22591 if (a
& 0xff000000)
22593 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22597 gas_assert (a
& 0xff000000);
22598 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22601 return (a
& 0xff) | (i
<< 7);
22608 validate_offset_imm (unsigned int val
, int hwse
)
22610 if ((hwse
&& val
> 255) || val
> 4095)
22615 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22616 negative immediate constant by altering the instruction. A bit of
22621 by inverting the second operand, and
22624 by negating the second operand. */
22627 negate_data_op (unsigned long * instruction
,
22628 unsigned long value
)
22631 unsigned long negated
, inverted
;
22633 negated
= encode_arm_immediate (-value
);
22634 inverted
= encode_arm_immediate (~value
);
22636 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22639 /* First negates. */
22640 case OPCODE_SUB
: /* ADD <-> SUB */
22641 new_inst
= OPCODE_ADD
;
22646 new_inst
= OPCODE_SUB
;
22650 case OPCODE_CMP
: /* CMP <-> CMN */
22651 new_inst
= OPCODE_CMN
;
22656 new_inst
= OPCODE_CMP
;
22660 /* Now Inverted ops. */
22661 case OPCODE_MOV
: /* MOV <-> MVN */
22662 new_inst
= OPCODE_MVN
;
22667 new_inst
= OPCODE_MOV
;
22671 case OPCODE_AND
: /* AND <-> BIC */
22672 new_inst
= OPCODE_BIC
;
22677 new_inst
= OPCODE_AND
;
22681 case OPCODE_ADC
: /* ADC <-> SBC */
22682 new_inst
= OPCODE_SBC
;
22687 new_inst
= OPCODE_ADC
;
22691 /* We cannot do anything. */
22696 if (value
== (unsigned) FAIL
)
22699 *instruction
&= OPCODE_MASK
;
22700 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22704 /* Like negate_data_op, but for Thumb-2. */
22706 static unsigned int
22707 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22711 unsigned int negated
, inverted
;
22713 negated
= encode_thumb32_immediate (-value
);
22714 inverted
= encode_thumb32_immediate (~value
);
22716 rd
= (*instruction
>> 8) & 0xf;
22717 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22720 /* ADD <-> SUB. Includes CMP <-> CMN. */
22721 case T2_OPCODE_SUB
:
22722 new_inst
= T2_OPCODE_ADD
;
22726 case T2_OPCODE_ADD
:
22727 new_inst
= T2_OPCODE_SUB
;
22731 /* ORR <-> ORN. Includes MOV <-> MVN. */
22732 case T2_OPCODE_ORR
:
22733 new_inst
= T2_OPCODE_ORN
;
22737 case T2_OPCODE_ORN
:
22738 new_inst
= T2_OPCODE_ORR
;
22742 /* AND <-> BIC. TST has no inverted equivalent. */
22743 case T2_OPCODE_AND
:
22744 new_inst
= T2_OPCODE_BIC
;
22751 case T2_OPCODE_BIC
:
22752 new_inst
= T2_OPCODE_AND
;
22757 case T2_OPCODE_ADC
:
22758 new_inst
= T2_OPCODE_SBC
;
22762 case T2_OPCODE_SBC
:
22763 new_inst
= T2_OPCODE_ADC
;
22767 /* We cannot do anything. */
22772 if (value
== (unsigned int)FAIL
)
22775 *instruction
&= T2_OPCODE_MASK
;
22776 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22780 /* Read a 32-bit thumb instruction from buf. */
22781 static unsigned long
22782 get_thumb32_insn (char * buf
)
22784 unsigned long insn
;
22785 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22786 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22792 /* We usually want to set the low bit on the address of thumb function
22793 symbols. In particular .word foo - . should have the low bit set.
22794 Generic code tries to fold the difference of two symbols to
22795 a constant. Prevent this and force a relocation when the first symbols
22796 is a thumb function. */
22799 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22801 if (op
== O_subtract
22802 && l
->X_op
== O_symbol
22803 && r
->X_op
== O_symbol
22804 && THUMB_IS_FUNC (l
->X_add_symbol
))
22806 l
->X_op
= O_subtract
;
22807 l
->X_op_symbol
= r
->X_add_symbol
;
22808 l
->X_add_number
-= r
->X_add_number
;
22812 /* Process as normal. */
22816 /* Encode Thumb2 unconditional branches and calls. The encoding
22817 for the 2 are identical for the immediate values. */
22820 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22822 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22825 addressT S
, I1
, I2
, lo
, hi
;
22827 S
= (value
>> 24) & 0x01;
22828 I1
= (value
>> 23) & 0x01;
22829 I2
= (value
>> 22) & 0x01;
22830 hi
= (value
>> 12) & 0x3ff;
22831 lo
= (value
>> 1) & 0x7ff;
22832 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22833 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22834 newval
|= (S
<< 10) | hi
;
22835 newval2
&= ~T2I1I2MASK
;
22836 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22838 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22842 md_apply_fix (fixS
* fixP
,
22846 offsetT value
= * valP
;
22848 unsigned int newimm
;
22849 unsigned long temp
;
22851 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22853 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22855 /* Note whether this will delete the relocation. */
22857 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22860 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22861 consistency with the behaviour on 32-bit hosts. Remember value
22863 value
&= 0xffffffff;
22864 value
^= 0x80000000;
22865 value
-= 0x80000000;
22868 fixP
->fx_addnumber
= value
;
22870 /* Same treatment for fixP->fx_offset. */
22871 fixP
->fx_offset
&= 0xffffffff;
22872 fixP
->fx_offset
^= 0x80000000;
22873 fixP
->fx_offset
-= 0x80000000;
22875 switch (fixP
->fx_r_type
)
22877 case BFD_RELOC_NONE
:
22878 /* This will need to go in the object file. */
22882 case BFD_RELOC_ARM_IMMEDIATE
:
22883 /* We claim that this fixup has been processed here,
22884 even if in fact we generate an error because we do
22885 not have a reloc for it, so tc_gen_reloc will reject it. */
22888 if (fixP
->fx_addsy
)
22890 const char *msg
= 0;
22892 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22893 msg
= _("undefined symbol %s used as an immediate value");
22894 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22895 msg
= _("symbol %s is in a different section");
22896 else if (S_IS_WEAK (fixP
->fx_addsy
))
22897 msg
= _("symbol %s is weak and may be overridden later");
22901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22902 msg
, S_GET_NAME (fixP
->fx_addsy
));
22907 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22909 /* If the offset is negative, we should use encoding A2 for ADR. */
22910 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22911 newimm
= negate_data_op (&temp
, value
);
22914 newimm
= encode_arm_immediate (value
);
22916 /* If the instruction will fail, see if we can fix things up by
22917 changing the opcode. */
22918 if (newimm
== (unsigned int) FAIL
)
22919 newimm
= negate_data_op (&temp
, value
);
22920 /* MOV accepts both ARM modified immediate (A1 encoding) and
22921 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22922 When disassembling, MOV is preferred when there is no encoding
22924 if (newimm
== (unsigned int) FAIL
22925 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22926 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22927 && !((temp
>> SBIT_SHIFT
) & 0x1)
22928 && value
>= 0 && value
<= 0xffff)
22930 /* Clear bits[23:20] to change encoding from A1 to A2. */
22931 temp
&= 0xff0fffff;
22932 /* Encoding high 4bits imm. Code below will encode the remaining
22934 temp
|= (value
& 0x0000f000) << 4;
22935 newimm
= value
& 0x00000fff;
22939 if (newimm
== (unsigned int) FAIL
)
22941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22942 _("invalid constant (%lx) after fixup"),
22943 (unsigned long) value
);
22947 newimm
|= (temp
& 0xfffff000);
22948 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22951 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22953 unsigned int highpart
= 0;
22954 unsigned int newinsn
= 0xe1a00000; /* nop. */
22956 if (fixP
->fx_addsy
)
22958 const char *msg
= 0;
22960 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22961 msg
= _("undefined symbol %s used as an immediate value");
22962 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22963 msg
= _("symbol %s is in a different section");
22964 else if (S_IS_WEAK (fixP
->fx_addsy
))
22965 msg
= _("symbol %s is weak and may be overridden later");
22969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22970 msg
, S_GET_NAME (fixP
->fx_addsy
));
22975 newimm
= encode_arm_immediate (value
);
22976 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22978 /* If the instruction will fail, see if we can fix things up by
22979 changing the opcode. */
22980 if (newimm
== (unsigned int) FAIL
22981 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22983 /* No ? OK - try using two ADD instructions to generate
22985 newimm
= validate_immediate_twopart (value
, & highpart
);
22987 /* Yes - then make sure that the second instruction is
22989 if (newimm
!= (unsigned int) FAIL
)
22991 /* Still No ? Try using a negated value. */
22992 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22993 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22994 /* Otherwise - give up. */
22997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22998 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23003 /* Replace the first operand in the 2nd instruction (which
23004 is the PC) with the destination register. We have
23005 already added in the PC in the first instruction and we
23006 do not want to do it again. */
23007 newinsn
&= ~ 0xf0000;
23008 newinsn
|= ((newinsn
& 0x0f000) << 4);
23011 newimm
|= (temp
& 0xfffff000);
23012 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23014 highpart
|= (newinsn
& 0xfffff000);
23015 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23019 case BFD_RELOC_ARM_OFFSET_IMM
:
23020 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23022 /* Fall through. */
23024 case BFD_RELOC_ARM_LITERAL
:
23030 if (validate_offset_imm (value
, 0) == FAIL
)
23032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23034 _("invalid literal constant: pool needs to be closer"));
23036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23037 _("bad immediate value for offset (%ld)"),
23042 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23044 newval
&= 0xfffff000;
23047 newval
&= 0xff7ff000;
23048 newval
|= value
| (sign
? INDEX_UP
: 0);
23050 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23053 case BFD_RELOC_ARM_OFFSET_IMM8
:
23054 case BFD_RELOC_ARM_HWLITERAL
:
23060 if (validate_offset_imm (value
, 1) == FAIL
)
23062 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23064 _("invalid literal constant: pool needs to be closer"));
23066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23067 _("bad immediate value for 8-bit offset (%ld)"),
23072 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23074 newval
&= 0xfffff0f0;
23077 newval
&= 0xff7ff0f0;
23078 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23080 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23083 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23084 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23086 _("bad immediate value for offset (%ld)"), (long) value
);
23089 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23091 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23094 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23095 /* This is a complicated relocation used for all varieties of Thumb32
23096 load/store instruction with immediate offset:
23098 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23099 *4, optional writeback(W)
23100 (doubleword load/store)
23102 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23103 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23104 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23105 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23106 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23108 Uppercase letters indicate bits that are already encoded at
23109 this point. Lowercase letters are our problem. For the
23110 second block of instructions, the secondary opcode nybble
23111 (bits 8..11) is present, and bit 23 is zero, even if this is
23112 a PC-relative operation. */
23113 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23115 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23117 if ((newval
& 0xf0000000) == 0xe0000000)
23119 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23121 newval
|= (1 << 23);
23124 if (value
% 4 != 0)
23126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23127 _("offset not a multiple of 4"));
23133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23134 _("offset out of range"));
23139 else if ((newval
& 0x000f0000) == 0x000f0000)
23141 /* PC-relative, 12-bit offset. */
23143 newval
|= (1 << 23);
23148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23149 _("offset out of range"));
23154 else if ((newval
& 0x00000100) == 0x00000100)
23156 /* Writeback: 8-bit, +/- offset. */
23158 newval
|= (1 << 9);
23163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23164 _("offset out of range"));
23169 else if ((newval
& 0x00000f00) == 0x00000e00)
23171 /* T-instruction: positive 8-bit offset. */
23172 if (value
< 0 || value
> 0xff)
23174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23175 _("offset out of range"));
23183 /* Positive 12-bit or negative 8-bit offset. */
23187 newval
|= (1 << 23);
23197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23198 _("offset out of range"));
23205 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23206 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23209 case BFD_RELOC_ARM_SHIFT_IMM
:
23210 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23211 if (((unsigned long) value
) > 32
23213 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23216 _("shift expression is too large"));
23221 /* Shifts of zero must be done as lsl. */
23223 else if (value
== 32)
23225 newval
&= 0xfffff07f;
23226 newval
|= (value
& 0x1f) << 7;
23227 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23230 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23231 case BFD_RELOC_ARM_T32_ADD_IMM
:
23232 case BFD_RELOC_ARM_T32_IMM12
:
23233 case BFD_RELOC_ARM_T32_ADD_PC12
:
23234 /* We claim that this fixup has been processed here,
23235 even if in fact we generate an error because we do
23236 not have a reloc for it, so tc_gen_reloc will reject it. */
23240 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23243 _("undefined symbol %s used as an immediate value"),
23244 S_GET_NAME (fixP
->fx_addsy
));
23248 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23250 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23253 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23254 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23255 Thumb2 modified immediate encoding (T2). */
23256 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23257 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23259 newimm
= encode_thumb32_immediate (value
);
23260 if (newimm
== (unsigned int) FAIL
)
23261 newimm
= thumb32_negate_data_op (&newval
, value
);
23263 if (newimm
== (unsigned int) FAIL
)
23265 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23267 /* Turn add/sum into addw/subw. */
23268 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23269 newval
= (newval
& 0xfeffffff) | 0x02000000;
23270 /* No flat 12-bit imm encoding for addsw/subsw. */
23271 if ((newval
& 0x00100000) == 0)
23273 /* 12 bit immediate for addw/subw. */
23277 newval
^= 0x00a00000;
23280 newimm
= (unsigned int) FAIL
;
23287 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23288 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23289 disassembling, MOV is preferred when there is no encoding
23291 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23292 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23293 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23294 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23295 && value
>= 0 && value
<=0xffff)
23297 /* Toggle bit[25] to change encoding from T2 to T3. */
23299 /* Clear bits[19:16]. */
23300 newval
&= 0xfff0ffff;
23301 /* Encoding high 4bits imm. Code below will encode the
23302 remaining low 12bits. */
23303 newval
|= (value
& 0x0000f000) << 4;
23304 newimm
= value
& 0x00000fff;
23309 if (newimm
== (unsigned int)FAIL
)
23311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23312 _("invalid constant (%lx) after fixup"),
23313 (unsigned long) value
);
23317 newval
|= (newimm
& 0x800) << 15;
23318 newval
|= (newimm
& 0x700) << 4;
23319 newval
|= (newimm
& 0x0ff);
23321 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23322 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23325 case BFD_RELOC_ARM_SMC
:
23326 if (((unsigned long) value
) > 0xffff)
23327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23328 _("invalid smc expression"));
23329 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23330 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23331 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23334 case BFD_RELOC_ARM_HVC
:
23335 if (((unsigned long) value
) > 0xffff)
23336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23337 _("invalid hvc expression"));
23338 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23339 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23340 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23343 case BFD_RELOC_ARM_SWI
:
23344 if (fixP
->tc_fix_data
!= 0)
23346 if (((unsigned long) value
) > 0xff)
23347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23348 _("invalid swi expression"));
23349 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23351 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23355 if (((unsigned long) value
) > 0x00ffffff)
23356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23357 _("invalid swi expression"));
23358 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23360 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23364 case BFD_RELOC_ARM_MULTI
:
23365 if (((unsigned long) value
) > 0xffff)
23366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23367 _("invalid expression in load/store multiple"));
23368 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23369 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23373 case BFD_RELOC_ARM_PCREL_CALL
:
23375 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23377 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23378 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23379 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23380 /* Flip the bl to blx. This is a simple flip
23381 bit here because we generate PCREL_CALL for
23382 unconditional bls. */
23384 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23385 newval
= newval
| 0x10000000;
23386 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23392 goto arm_branch_common
;
23394 case BFD_RELOC_ARM_PCREL_JUMP
:
23395 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23397 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23398 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23399 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23401 /* This would map to a bl<cond>, b<cond>,
23402 b<always> to a Thumb function. We
23403 need to force a relocation for this particular
23405 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23408 /* Fall through. */
23410 case BFD_RELOC_ARM_PLT32
:
23412 case BFD_RELOC_ARM_PCREL_BRANCH
:
23414 goto arm_branch_common
;
23416 case BFD_RELOC_ARM_PCREL_BLX
:
23419 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23421 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23422 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23423 && ARM_IS_FUNC (fixP
->fx_addsy
))
23425 /* Flip the blx to a bl and warn. */
23426 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23427 newval
= 0xeb000000;
23428 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23429 _("blx to '%s' an ARM ISA state function changed to bl"),
23431 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23437 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23438 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23442 /* We are going to store value (shifted right by two) in the
23443 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23444 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23445 also be be clear. */
23447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23448 _("misaligned branch destination"));
23449 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23450 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23453 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23455 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23456 newval
|= (value
>> 2) & 0x00ffffff;
23457 /* Set the H bit on BLX instructions. */
23461 newval
|= 0x01000000;
23463 newval
&= ~0x01000000;
23465 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23469 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23470 /* CBZ can only branch forward. */
23472 /* Attempts to use CBZ to branch to the next instruction
23473 (which, strictly speaking, are prohibited) will be turned into
23476 FIXME: It may be better to remove the instruction completely and
23477 perform relaxation. */
23480 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23481 newval
= 0xbf00; /* NOP encoding T1 */
23482 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23489 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23491 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23492 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23493 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23498 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23499 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23502 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23504 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23505 newval
|= (value
& 0x1ff) >> 1;
23506 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23510 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23511 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23516 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23517 newval
|= (value
& 0xfff) >> 1;
23518 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23522 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23524 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23525 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23526 && ARM_IS_FUNC (fixP
->fx_addsy
)
23527 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23529 /* Force a relocation for a branch 20 bits wide. */
23532 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("conditional branch out of range"));
23536 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23539 addressT S
, J1
, J2
, lo
, hi
;
23541 S
= (value
& 0x00100000) >> 20;
23542 J2
= (value
& 0x00080000) >> 19;
23543 J1
= (value
& 0x00040000) >> 18;
23544 hi
= (value
& 0x0003f000) >> 12;
23545 lo
= (value
& 0x00000ffe) >> 1;
23547 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23548 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23549 newval
|= (S
<< 10) | hi
;
23550 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23551 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23552 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23556 case BFD_RELOC_THUMB_PCREL_BLX
:
23557 /* If there is a blx from a thumb state function to
23558 another thumb function flip this to a bl and warn
23562 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23563 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23564 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23566 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23567 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23568 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23570 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23571 newval
= newval
| 0x1000;
23572 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23573 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23578 goto thumb_bl_common
;
23580 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23581 /* A bl from Thumb state ISA to an internal ARM state function
23582 is converted to a blx. */
23584 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23585 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23586 && ARM_IS_FUNC (fixP
->fx_addsy
)
23587 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23589 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23590 newval
= newval
& ~0x1000;
23591 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23592 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23598 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23599 /* For a BLX instruction, make sure that the relocation is rounded up
23600 to a word boundary. This follows the semantics of the instruction
23601 which specifies that bit 1 of the target address will come from bit
23602 1 of the base address. */
23603 value
= (value
+ 3) & ~ 3;
23606 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23607 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23608 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23611 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23613 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23615 else if ((value
& ~0x1ffffff)
23616 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23618 _("Thumb2 branch out of range"));
23621 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23622 encode_thumb2_b_bl_offset (buf
, value
);
23626 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23627 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23630 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23631 encode_thumb2_b_bl_offset (buf
, value
);
23636 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23641 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23642 md_number_to_chars (buf
, value
, 2);
23646 case BFD_RELOC_ARM_TLS_CALL
:
23647 case BFD_RELOC_ARM_THM_TLS_CALL
:
23648 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23649 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23650 case BFD_RELOC_ARM_TLS_GOTDESC
:
23651 case BFD_RELOC_ARM_TLS_GD32
:
23652 case BFD_RELOC_ARM_TLS_LE32
:
23653 case BFD_RELOC_ARM_TLS_IE32
:
23654 case BFD_RELOC_ARM_TLS_LDM32
:
23655 case BFD_RELOC_ARM_TLS_LDO32
:
23656 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23659 case BFD_RELOC_ARM_GOT32
:
23660 case BFD_RELOC_ARM_GOTOFF
:
23663 case BFD_RELOC_ARM_GOT_PREL
:
23664 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23665 md_number_to_chars (buf
, value
, 4);
23668 case BFD_RELOC_ARM_TARGET2
:
23669 /* TARGET2 is not partial-inplace, so we need to write the
23670 addend here for REL targets, because it won't be written out
23671 during reloc processing later. */
23672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23673 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23677 case BFD_RELOC_RVA
:
23679 case BFD_RELOC_ARM_TARGET1
:
23680 case BFD_RELOC_ARM_ROSEGREL32
:
23681 case BFD_RELOC_ARM_SBREL32
:
23682 case BFD_RELOC_32_PCREL
:
23684 case BFD_RELOC_32_SECREL
:
23686 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23688 /* For WinCE we only do this for pcrel fixups. */
23689 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23691 md_number_to_chars (buf
, value
, 4);
23695 case BFD_RELOC_ARM_PREL31
:
23696 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23698 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23699 if ((value
^ (value
>> 1)) & 0x40000000)
23701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23702 _("rel31 relocation overflow"));
23704 newval
|= value
& 0x7fffffff;
23705 md_number_to_chars (buf
, newval
, 4);
23710 case BFD_RELOC_ARM_CP_OFF_IMM
:
23711 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23712 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23713 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23715 newval
= get_thumb32_insn (buf
);
23716 if ((newval
& 0x0f200f00) == 0x0d000900)
23718 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23719 has permitted values that are multiples of 2, in the range 0
23721 if (value
< -510 || value
> 510 || (value
& 1))
23722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23723 _("co-processor offset out of range"));
23725 else if (value
< -1023 || value
> 1023 || (value
& 3))
23726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23727 _("co-processor offset out of range"));
23732 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23733 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23734 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23736 newval
= get_thumb32_insn (buf
);
23738 newval
&= 0xffffff00;
23741 newval
&= 0xff7fff00;
23742 if ((newval
& 0x0f200f00) == 0x0d000900)
23744 /* This is a fp16 vstr/vldr.
23746 It requires the immediate offset in the instruction is shifted
23747 left by 1 to be a half-word offset.
23749 Here, left shift by 1 first, and later right shift by 2
23750 should get the right offset. */
23753 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23755 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23756 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23757 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23759 put_thumb32_insn (buf
, newval
);
23762 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23763 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23764 if (value
< -255 || value
> 255)
23765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23766 _("co-processor offset out of range"));
23768 goto cp_off_common
;
23770 case BFD_RELOC_ARM_THUMB_OFFSET
:
23771 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23772 /* Exactly what ranges, and where the offset is inserted depends
23773 on the type of instruction, we can establish this from the
23775 switch (newval
>> 12)
23777 case 4: /* PC load. */
23778 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23779 forced to zero for these loads; md_pcrel_from has already
23780 compensated for this. */
23782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23783 _("invalid offset, target not word aligned (0x%08lX)"),
23784 (((unsigned long) fixP
->fx_frag
->fr_address
23785 + (unsigned long) fixP
->fx_where
) & ~3)
23786 + (unsigned long) value
);
23788 if (value
& ~0x3fc)
23789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23790 _("invalid offset, value too big (0x%08lX)"),
23793 newval
|= value
>> 2;
23796 case 9: /* SP load/store. */
23797 if (value
& ~0x3fc)
23798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23799 _("invalid offset, value too big (0x%08lX)"),
23801 newval
|= value
>> 2;
23804 case 6: /* Word load/store. */
23806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23807 _("invalid offset, value too big (0x%08lX)"),
23809 newval
|= value
<< 4; /* 6 - 2. */
23812 case 7: /* Byte load/store. */
23814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23815 _("invalid offset, value too big (0x%08lX)"),
23817 newval
|= value
<< 6;
23820 case 8: /* Halfword load/store. */
23822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23823 _("invalid offset, value too big (0x%08lX)"),
23825 newval
|= value
<< 5; /* 6 - 1. */
23829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23830 "Unable to process relocation for thumb opcode: %lx",
23831 (unsigned long) newval
);
23834 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23837 case BFD_RELOC_ARM_THUMB_ADD
:
23838 /* This is a complicated relocation, since we use it for all of
23839 the following immediate relocations:
23843 9bit ADD/SUB SP word-aligned
23844 10bit ADD PC/SP word-aligned
23846 The type of instruction being processed is encoded in the
23853 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23855 int rd
= (newval
>> 4) & 0xf;
23856 int rs
= newval
& 0xf;
23857 int subtract
= !!(newval
& 0x8000);
23859 /* Check for HI regs, only very restricted cases allowed:
23860 Adjusting SP, and using PC or SP to get an address. */
23861 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23862 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23864 _("invalid Hi register with immediate"));
23866 /* If value is negative, choose the opposite instruction. */
23870 subtract
= !subtract
;
23872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23873 _("immediate value out of range"));
23878 if (value
& ~0x1fc)
23879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23880 _("invalid immediate for stack address calculation"));
23881 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23882 newval
|= value
>> 2;
23884 else if (rs
== REG_PC
|| rs
== REG_SP
)
23886 /* PR gas/18541. If the addition is for a defined symbol
23887 within range of an ADR instruction then accept it. */
23890 && fixP
->fx_addsy
!= NULL
)
23894 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23895 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23896 || S_IS_WEAK (fixP
->fx_addsy
))
23898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23899 _("address calculation needs a strongly defined nearby symbol"));
23903 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23905 /* Round up to the next 4-byte boundary. */
23910 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23915 _("symbol too far away"));
23925 if (subtract
|| value
& ~0x3fc)
23926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23927 _("invalid immediate for address calculation (value = 0x%08lX)"),
23928 (unsigned long) (subtract
? - value
: value
));
23929 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23931 newval
|= value
>> 2;
23936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23937 _("immediate value out of range"));
23938 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23939 newval
|= (rd
<< 8) | value
;
23944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23945 _("immediate value out of range"));
23946 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23947 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23950 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23953 case BFD_RELOC_ARM_THUMB_IMM
:
23954 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23955 if (value
< 0 || value
> 255)
23956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23957 _("invalid immediate: %ld is out of range"),
23960 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23963 case BFD_RELOC_ARM_THUMB_SHIFT
:
23964 /* 5bit shift value (0..32). LSL cannot take 32. */
23965 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23966 temp
= newval
& 0xf800;
23967 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23969 _("invalid shift value: %ld"), (long) value
);
23970 /* Shifts of zero must be encoded as LSL. */
23972 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23973 /* Shifts of 32 are encoded as zero. */
23974 else if (value
== 32)
23976 newval
|= value
<< 6;
23977 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23980 case BFD_RELOC_VTABLE_INHERIT
:
23981 case BFD_RELOC_VTABLE_ENTRY
:
23985 case BFD_RELOC_ARM_MOVW
:
23986 case BFD_RELOC_ARM_MOVT
:
23987 case BFD_RELOC_ARM_THUMB_MOVW
:
23988 case BFD_RELOC_ARM_THUMB_MOVT
:
23989 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23991 /* REL format relocations are limited to a 16-bit addend. */
23992 if (!fixP
->fx_done
)
23994 if (value
< -0x8000 || value
> 0x7fff)
23995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23996 _("offset out of range"));
23998 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23999 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24004 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24005 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24007 newval
= get_thumb32_insn (buf
);
24008 newval
&= 0xfbf08f00;
24009 newval
|= (value
& 0xf000) << 4;
24010 newval
|= (value
& 0x0800) << 15;
24011 newval
|= (value
& 0x0700) << 4;
24012 newval
|= (value
& 0x00ff);
24013 put_thumb32_insn (buf
, newval
);
24017 newval
= md_chars_to_number (buf
, 4);
24018 newval
&= 0xfff0f000;
24019 newval
|= value
& 0x0fff;
24020 newval
|= (value
& 0xf000) << 4;
24021 md_number_to_chars (buf
, newval
, 4);
24026 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24027 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24028 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24029 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24030 gas_assert (!fixP
->fx_done
);
24033 bfd_boolean is_mov
;
24034 bfd_vma encoded_addend
= value
;
24036 /* Check that addend can be encoded in instruction. */
24037 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24039 _("the offset 0x%08lX is not representable"),
24040 (unsigned long) encoded_addend
);
24042 /* Extract the instruction. */
24043 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24044 is_mov
= (insn
& 0xf800) == 0x2000;
24049 if (!seg
->use_rela_p
)
24050 insn
|= encoded_addend
;
24056 /* Extract the instruction. */
24057 /* Encoding is the following
24062 /* The following conditions must be true :
24067 rd
= (insn
>> 4) & 0xf;
24069 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24071 _("Unable to process relocation for thumb opcode: %lx"),
24072 (unsigned long) insn
);
24074 /* Encode as ADD immediate8 thumb 1 code. */
24075 insn
= 0x3000 | (rd
<< 8);
24077 /* Place the encoded addend into the first 8 bits of the
24079 if (!seg
->use_rela_p
)
24080 insn
|= encoded_addend
;
24083 /* Update the instruction. */
24084 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24088 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24089 case BFD_RELOC_ARM_ALU_PC_G0
:
24090 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24091 case BFD_RELOC_ARM_ALU_PC_G1
:
24092 case BFD_RELOC_ARM_ALU_PC_G2
:
24093 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24094 case BFD_RELOC_ARM_ALU_SB_G0
:
24095 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24096 case BFD_RELOC_ARM_ALU_SB_G1
:
24097 case BFD_RELOC_ARM_ALU_SB_G2
:
24098 gas_assert (!fixP
->fx_done
);
24099 if (!seg
->use_rela_p
)
24102 bfd_vma encoded_addend
;
24103 bfd_vma addend_abs
= abs (value
);
24105 /* Check that the absolute value of the addend can be
24106 expressed as an 8-bit constant plus a rotation. */
24107 encoded_addend
= encode_arm_immediate (addend_abs
);
24108 if (encoded_addend
== (unsigned int) FAIL
)
24109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24110 _("the offset 0x%08lX is not representable"),
24111 (unsigned long) addend_abs
);
24113 /* Extract the instruction. */
24114 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24116 /* If the addend is positive, use an ADD instruction.
24117 Otherwise use a SUB. Take care not to destroy the S bit. */
24118 insn
&= 0xff1fffff;
24124 /* Place the encoded addend into the first 12 bits of the
24126 insn
&= 0xfffff000;
24127 insn
|= encoded_addend
;
24129 /* Update the instruction. */
24130 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24134 case BFD_RELOC_ARM_LDR_PC_G0
:
24135 case BFD_RELOC_ARM_LDR_PC_G1
:
24136 case BFD_RELOC_ARM_LDR_PC_G2
:
24137 case BFD_RELOC_ARM_LDR_SB_G0
:
24138 case BFD_RELOC_ARM_LDR_SB_G1
:
24139 case BFD_RELOC_ARM_LDR_SB_G2
:
24140 gas_assert (!fixP
->fx_done
);
24141 if (!seg
->use_rela_p
)
24144 bfd_vma addend_abs
= abs (value
);
24146 /* Check that the absolute value of the addend can be
24147 encoded in 12 bits. */
24148 if (addend_abs
>= 0x1000)
24149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24150 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24151 (unsigned long) addend_abs
);
24153 /* Extract the instruction. */
24154 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24156 /* If the addend is negative, clear bit 23 of the instruction.
24157 Otherwise set it. */
24159 insn
&= ~(1 << 23);
24163 /* Place the absolute value of the addend into the first 12 bits
24164 of the instruction. */
24165 insn
&= 0xfffff000;
24166 insn
|= addend_abs
;
24168 /* Update the instruction. */
24169 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24173 case BFD_RELOC_ARM_LDRS_PC_G0
:
24174 case BFD_RELOC_ARM_LDRS_PC_G1
:
24175 case BFD_RELOC_ARM_LDRS_PC_G2
:
24176 case BFD_RELOC_ARM_LDRS_SB_G0
:
24177 case BFD_RELOC_ARM_LDRS_SB_G1
:
24178 case BFD_RELOC_ARM_LDRS_SB_G2
:
24179 gas_assert (!fixP
->fx_done
);
24180 if (!seg
->use_rela_p
)
24183 bfd_vma addend_abs
= abs (value
);
24185 /* Check that the absolute value of the addend can be
24186 encoded in 8 bits. */
24187 if (addend_abs
>= 0x100)
24188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24189 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24190 (unsigned long) addend_abs
);
24192 /* Extract the instruction. */
24193 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24195 /* If the addend is negative, clear bit 23 of the instruction.
24196 Otherwise set it. */
24198 insn
&= ~(1 << 23);
24202 /* Place the first four bits of the absolute value of the addend
24203 into the first 4 bits of the instruction, and the remaining
24204 four into bits 8 .. 11. */
24205 insn
&= 0xfffff0f0;
24206 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24208 /* Update the instruction. */
24209 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24213 case BFD_RELOC_ARM_LDC_PC_G0
:
24214 case BFD_RELOC_ARM_LDC_PC_G1
:
24215 case BFD_RELOC_ARM_LDC_PC_G2
:
24216 case BFD_RELOC_ARM_LDC_SB_G0
:
24217 case BFD_RELOC_ARM_LDC_SB_G1
:
24218 case BFD_RELOC_ARM_LDC_SB_G2
:
24219 gas_assert (!fixP
->fx_done
);
24220 if (!seg
->use_rela_p
)
24223 bfd_vma addend_abs
= abs (value
);
24225 /* Check that the absolute value of the addend is a multiple of
24226 four and, when divided by four, fits in 8 bits. */
24227 if (addend_abs
& 0x3)
24228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24229 _("bad offset 0x%08lX (must be word-aligned)"),
24230 (unsigned long) addend_abs
);
24232 if ((addend_abs
>> 2) > 0xff)
24233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24234 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24235 (unsigned long) addend_abs
);
24237 /* Extract the instruction. */
24238 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24240 /* If the addend is negative, clear bit 23 of the instruction.
24241 Otherwise set it. */
24243 insn
&= ~(1 << 23);
24247 /* Place the addend (divided by four) into the first eight
24248 bits of the instruction. */
24249 insn
&= 0xfffffff0;
24250 insn
|= addend_abs
>> 2;
24252 /* Update the instruction. */
24253 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24257 case BFD_RELOC_ARM_V4BX
:
24258 /* This will need to go in the object file. */
24262 case BFD_RELOC_UNUSED
:
24264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24265 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24269 /* Translate internal representation of relocation info to BFD target
24273 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24276 bfd_reloc_code_real_type code
;
24278 reloc
= XNEW (arelent
);
24280 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24281 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24282 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24284 if (fixp
->fx_pcrel
)
24286 if (section
->use_rela_p
)
24287 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24289 fixp
->fx_offset
= reloc
->address
;
24291 reloc
->addend
= fixp
->fx_offset
;
24293 switch (fixp
->fx_r_type
)
24296 if (fixp
->fx_pcrel
)
24298 code
= BFD_RELOC_8_PCREL
;
24301 /* Fall through. */
24304 if (fixp
->fx_pcrel
)
24306 code
= BFD_RELOC_16_PCREL
;
24309 /* Fall through. */
24312 if (fixp
->fx_pcrel
)
24314 code
= BFD_RELOC_32_PCREL
;
24317 /* Fall through. */
24319 case BFD_RELOC_ARM_MOVW
:
24320 if (fixp
->fx_pcrel
)
24322 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24325 /* Fall through. */
24327 case BFD_RELOC_ARM_MOVT
:
24328 if (fixp
->fx_pcrel
)
24330 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24333 /* Fall through. */
24335 case BFD_RELOC_ARM_THUMB_MOVW
:
24336 if (fixp
->fx_pcrel
)
24338 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24341 /* Fall through. */
24343 case BFD_RELOC_ARM_THUMB_MOVT
:
24344 if (fixp
->fx_pcrel
)
24346 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24349 /* Fall through. */
24351 case BFD_RELOC_NONE
:
24352 case BFD_RELOC_ARM_PCREL_BRANCH
:
24353 case BFD_RELOC_ARM_PCREL_BLX
:
24354 case BFD_RELOC_RVA
:
24355 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24356 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24357 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24358 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24359 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24360 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24361 case BFD_RELOC_VTABLE_ENTRY
:
24362 case BFD_RELOC_VTABLE_INHERIT
:
24364 case BFD_RELOC_32_SECREL
:
24366 code
= fixp
->fx_r_type
;
24369 case BFD_RELOC_THUMB_PCREL_BLX
:
24371 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24372 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24375 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24378 case BFD_RELOC_ARM_LITERAL
:
24379 case BFD_RELOC_ARM_HWLITERAL
:
24380 /* If this is called then the a literal has
24381 been referenced across a section boundary. */
24382 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24383 _("literal referenced across section boundary"));
24387 case BFD_RELOC_ARM_TLS_CALL
:
24388 case BFD_RELOC_ARM_THM_TLS_CALL
:
24389 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24390 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24391 case BFD_RELOC_ARM_GOT32
:
24392 case BFD_RELOC_ARM_GOTOFF
:
24393 case BFD_RELOC_ARM_GOT_PREL
:
24394 case BFD_RELOC_ARM_PLT32
:
24395 case BFD_RELOC_ARM_TARGET1
:
24396 case BFD_RELOC_ARM_ROSEGREL32
:
24397 case BFD_RELOC_ARM_SBREL32
:
24398 case BFD_RELOC_ARM_PREL31
:
24399 case BFD_RELOC_ARM_TARGET2
:
24400 case BFD_RELOC_ARM_TLS_LDO32
:
24401 case BFD_RELOC_ARM_PCREL_CALL
:
24402 case BFD_RELOC_ARM_PCREL_JUMP
:
24403 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24404 case BFD_RELOC_ARM_ALU_PC_G0
:
24405 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24406 case BFD_RELOC_ARM_ALU_PC_G1
:
24407 case BFD_RELOC_ARM_ALU_PC_G2
:
24408 case BFD_RELOC_ARM_LDR_PC_G0
:
24409 case BFD_RELOC_ARM_LDR_PC_G1
:
24410 case BFD_RELOC_ARM_LDR_PC_G2
:
24411 case BFD_RELOC_ARM_LDRS_PC_G0
:
24412 case BFD_RELOC_ARM_LDRS_PC_G1
:
24413 case BFD_RELOC_ARM_LDRS_PC_G2
:
24414 case BFD_RELOC_ARM_LDC_PC_G0
:
24415 case BFD_RELOC_ARM_LDC_PC_G1
:
24416 case BFD_RELOC_ARM_LDC_PC_G2
:
24417 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24418 case BFD_RELOC_ARM_ALU_SB_G0
:
24419 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24420 case BFD_RELOC_ARM_ALU_SB_G1
:
24421 case BFD_RELOC_ARM_ALU_SB_G2
:
24422 case BFD_RELOC_ARM_LDR_SB_G0
:
24423 case BFD_RELOC_ARM_LDR_SB_G1
:
24424 case BFD_RELOC_ARM_LDR_SB_G2
:
24425 case BFD_RELOC_ARM_LDRS_SB_G0
:
24426 case BFD_RELOC_ARM_LDRS_SB_G1
:
24427 case BFD_RELOC_ARM_LDRS_SB_G2
:
24428 case BFD_RELOC_ARM_LDC_SB_G0
:
24429 case BFD_RELOC_ARM_LDC_SB_G1
:
24430 case BFD_RELOC_ARM_LDC_SB_G2
:
24431 case BFD_RELOC_ARM_V4BX
:
24432 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24433 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24434 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24435 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24436 code
= fixp
->fx_r_type
;
24439 case BFD_RELOC_ARM_TLS_GOTDESC
:
24440 case BFD_RELOC_ARM_TLS_GD32
:
24441 case BFD_RELOC_ARM_TLS_LE32
:
24442 case BFD_RELOC_ARM_TLS_IE32
:
24443 case BFD_RELOC_ARM_TLS_LDM32
:
24444 /* BFD will include the symbol's address in the addend.
24445 But we don't want that, so subtract it out again here. */
24446 if (!S_IS_COMMON (fixp
->fx_addsy
))
24447 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24448 code
= fixp
->fx_r_type
;
24452 case BFD_RELOC_ARM_IMMEDIATE
:
24453 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24454 _("internal relocation (type: IMMEDIATE) not fixed up"));
24457 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24458 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24459 _("ADRL used for a symbol not defined in the same file"));
24462 case BFD_RELOC_ARM_OFFSET_IMM
:
24463 if (section
->use_rela_p
)
24465 code
= fixp
->fx_r_type
;
24469 if (fixp
->fx_addsy
!= NULL
24470 && !S_IS_DEFINED (fixp
->fx_addsy
)
24471 && S_IS_LOCAL (fixp
->fx_addsy
))
24473 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24474 _("undefined local label `%s'"),
24475 S_GET_NAME (fixp
->fx_addsy
));
24479 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24480 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24487 switch (fixp
->fx_r_type
)
24489 case BFD_RELOC_NONE
: type
= "NONE"; break;
24490 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24491 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24492 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24493 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24494 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24495 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24496 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24497 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24498 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24499 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24500 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24501 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24502 default: type
= _("<unknown>"); break;
24504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24505 _("cannot represent %s relocation in this object file format"),
24512 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24514 && fixp
->fx_addsy
== GOT_symbol
)
24516 code
= BFD_RELOC_ARM_GOTPC
;
24517 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24521 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24523 if (reloc
->howto
== NULL
)
24525 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24526 _("cannot represent %s relocation in this object file format"),
24527 bfd_get_reloc_code_name (code
));
24531 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24532 vtable entry to be used in the relocation's section offset. */
24533 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24534 reloc
->address
= fixp
->fx_offset
;
24539 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24542 cons_fix_new_arm (fragS
* frag
,
24546 bfd_reloc_code_real_type reloc
)
24551 FIXME: @@ Should look at CPU word size. */
24555 reloc
= BFD_RELOC_8
;
24558 reloc
= BFD_RELOC_16
;
24562 reloc
= BFD_RELOC_32
;
24565 reloc
= BFD_RELOC_64
;
24570 if (exp
->X_op
== O_secrel
)
24572 exp
->X_op
= O_symbol
;
24573 reloc
= BFD_RELOC_32_SECREL
;
24577 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24580 #if defined (OBJ_COFF)
24582 arm_validate_fix (fixS
* fixP
)
24584 /* If the destination of the branch is a defined symbol which does not have
24585 the THUMB_FUNC attribute, then we must be calling a function which has
24586 the (interfacearm) attribute. We look for the Thumb entry point to that
24587 function and change the branch to refer to that function instead. */
24588 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24589 && fixP
->fx_addsy
!= NULL
24590 && S_IS_DEFINED (fixP
->fx_addsy
)
24591 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24593 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24600 arm_force_relocation (struct fix
* fixp
)
24602 #if defined (OBJ_COFF) && defined (TE_PE)
24603 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24607 /* In case we have a call or a branch to a function in ARM ISA mode from
24608 a thumb function or vice-versa force the relocation. These relocations
24609 are cleared off for some cores that might have blx and simple transformations
24613 switch (fixp
->fx_r_type
)
24615 case BFD_RELOC_ARM_PCREL_JUMP
:
24616 case BFD_RELOC_ARM_PCREL_CALL
:
24617 case BFD_RELOC_THUMB_PCREL_BLX
:
24618 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24622 case BFD_RELOC_ARM_PCREL_BLX
:
24623 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24624 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24625 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24626 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24635 /* Resolve these relocations even if the symbol is extern or weak.
24636 Technically this is probably wrong due to symbol preemption.
24637 In practice these relocations do not have enough range to be useful
24638 at dynamic link time, and some code (e.g. in the Linux kernel)
24639 expects these references to be resolved. */
24640 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24641 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24642 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24643 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24644 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24645 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24646 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24647 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24648 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24649 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24650 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24651 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24652 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24653 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24656 /* Always leave these relocations for the linker. */
24657 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24658 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24659 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24662 /* Always generate relocations against function symbols. */
24663 if (fixp
->fx_r_type
== BFD_RELOC_32
24665 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24668 return generic_force_reloc (fixp
);
24671 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24672 /* Relocations against function names must be left unadjusted,
24673 so that the linker can use this information to generate interworking
24674 stubs. The MIPS version of this function
24675 also prevents relocations that are mips-16 specific, but I do not
24676 know why it does this.
24679 There is one other problem that ought to be addressed here, but
24680 which currently is not: Taking the address of a label (rather
24681 than a function) and then later jumping to that address. Such
24682 addresses also ought to have their bottom bit set (assuming that
24683 they reside in Thumb code), but at the moment they will not. */
24686 arm_fix_adjustable (fixS
* fixP
)
24688 if (fixP
->fx_addsy
== NULL
)
24691 /* Preserve relocations against symbols with function type. */
24692 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24695 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24696 && fixP
->fx_subsy
== NULL
)
24699 /* We need the symbol name for the VTABLE entries. */
24700 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24701 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24704 /* Don't allow symbols to be discarded on GOT related relocs. */
24705 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24706 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24707 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24708 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24709 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24710 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24711 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24712 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24713 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24714 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24715 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24716 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24717 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24718 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24721 /* Similarly for group relocations. */
24722 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24723 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24724 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24727 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24728 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24729 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24730 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24731 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24732 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24733 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24734 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24735 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24738 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24739 offsets, so keep these symbols. */
24740 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24741 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24746 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24750 elf32_arm_target_format (void)
24753 return (target_big_endian
24754 ? "elf32-bigarm-symbian"
24755 : "elf32-littlearm-symbian");
24756 #elif defined (TE_VXWORKS)
24757 return (target_big_endian
24758 ? "elf32-bigarm-vxworks"
24759 : "elf32-littlearm-vxworks");
24760 #elif defined (TE_NACL)
24761 return (target_big_endian
24762 ? "elf32-bigarm-nacl"
24763 : "elf32-littlearm-nacl");
24765 if (target_big_endian
)
24766 return "elf32-bigarm";
24768 return "elf32-littlearm";
24773 armelf_frob_symbol (symbolS
* symp
,
24776 elf_frob_symbol (symp
, puntp
);
24780 /* MD interface: Finalization. */
24785 literal_pool
* pool
;
24787 /* Ensure that all the IT blocks are properly closed. */
24788 check_it_blocks_finished ();
24790 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24792 /* Put it at the end of the relevant section. */
24793 subseg_set (pool
->section
, pool
->sub_section
);
24795 arm_elf_change_section ();
24802 /* Remove any excess mapping symbols generated for alignment frags in
24803 SEC. We may have created a mapping symbol before a zero byte
24804 alignment; remove it if there's a mapping symbol after the
24807 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24808 void *dummy ATTRIBUTE_UNUSED
)
24810 segment_info_type
*seginfo
= seg_info (sec
);
24813 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24816 for (fragp
= seginfo
->frchainP
->frch_root
;
24818 fragp
= fragp
->fr_next
)
24820 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24821 fragS
*next
= fragp
->fr_next
;
24823 /* Variable-sized frags have been converted to fixed size by
24824 this point. But if this was variable-sized to start with,
24825 there will be a fixed-size frag after it. So don't handle
24827 if (sym
== NULL
|| next
== NULL
)
24830 if (S_GET_VALUE (sym
) < next
->fr_address
)
24831 /* Not at the end of this frag. */
24833 know (S_GET_VALUE (sym
) == next
->fr_address
);
24837 if (next
->tc_frag_data
.first_map
!= NULL
)
24839 /* Next frag starts with a mapping symbol. Discard this
24841 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24845 if (next
->fr_next
== NULL
)
24847 /* This mapping symbol is at the end of the section. Discard
24849 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24850 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24854 /* As long as we have empty frags without any mapping symbols,
24856 /* If the next frag is non-empty and does not start with a
24857 mapping symbol, then this mapping symbol is required. */
24858 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24861 next
= next
->fr_next
;
24863 while (next
!= NULL
);
24868 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24872 arm_adjust_symtab (void)
24877 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24879 if (ARM_IS_THUMB (sym
))
24881 if (THUMB_IS_FUNC (sym
))
24883 /* Mark the symbol as a Thumb function. */
24884 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24885 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24886 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24888 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24889 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24891 as_bad (_("%s: unexpected function type: %d"),
24892 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24894 else switch (S_GET_STORAGE_CLASS (sym
))
24897 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24900 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24903 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24911 if (ARM_IS_INTERWORK (sym
))
24912 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24919 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24921 if (ARM_IS_THUMB (sym
))
24923 elf_symbol_type
* elf_sym
;
24925 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24926 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24928 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24929 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24931 /* If it's a .thumb_func, declare it as so,
24932 otherwise tag label as .code 16. */
24933 if (THUMB_IS_FUNC (sym
))
24934 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24935 ST_BRANCH_TO_THUMB
);
24936 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24937 elf_sym
->internal_elf_sym
.st_info
=
24938 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24943 /* Remove any overlapping mapping symbols generated by alignment frags. */
24944 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24945 /* Now do generic ELF adjustments. */
24946 elf_adjust_symtab ();
24950 /* MD interface: Initialization. */
24953 set_constant_flonums (void)
24957 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24958 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24962 /* Auto-select Thumb mode if it's the only available instruction set for the
24963 given architecture. */
24966 autoselect_thumb_from_cpu_variant (void)
24968 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24969 opcode_select (16);
24978 if ( (arm_ops_hsh
= hash_new ()) == NULL
24979 || (arm_cond_hsh
= hash_new ()) == NULL
24980 || (arm_shift_hsh
= hash_new ()) == NULL
24981 || (arm_psr_hsh
= hash_new ()) == NULL
24982 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24983 || (arm_reg_hsh
= hash_new ()) == NULL
24984 || (arm_reloc_hsh
= hash_new ()) == NULL
24985 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24986 as_fatal (_("virtual memory exhausted"));
24988 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24989 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24990 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24991 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24992 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24993 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24994 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24995 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24996 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24997 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24998 (void *) (v7m_psrs
+ i
));
24999 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25000 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25002 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25004 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25005 (void *) (barrier_opt_names
+ i
));
25007 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25009 struct reloc_entry
* entry
= reloc_names
+ i
;
25011 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25012 /* This makes encode_branch() use the EABI versions of this relocation. */
25013 entry
->reloc
= BFD_RELOC_UNUSED
;
25015 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25019 set_constant_flonums ();
25021 /* Set the cpu variant based on the command-line options. We prefer
25022 -mcpu= over -march= if both are set (as for GCC); and we prefer
25023 -mfpu= over any other way of setting the floating point unit.
25024 Use of legacy options with new options are faulted. */
25027 if (mcpu_cpu_opt
|| march_cpu_opt
)
25028 as_bad (_("use of old and new-style options to set CPU type"));
25030 mcpu_cpu_opt
= legacy_cpu
;
25032 else if (!mcpu_cpu_opt
)
25034 mcpu_cpu_opt
= march_cpu_opt
;
25035 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25036 /* Avoid double free in arm_md_end. */
25037 dyn_march_ext_opt
= NULL
;
25043 as_bad (_("use of old and new-style options to set FPU type"));
25045 mfpu_opt
= legacy_fpu
;
25047 else if (!mfpu_opt
)
25049 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25050 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25051 /* Some environments specify a default FPU. If they don't, infer it
25052 from the processor. */
25054 mfpu_opt
= mcpu_fpu_opt
;
25056 mfpu_opt
= march_fpu_opt
;
25058 mfpu_opt
= &fpu_default
;
25064 if (mcpu_cpu_opt
!= NULL
)
25065 mfpu_opt
= &fpu_default
;
25066 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25067 mfpu_opt
= &fpu_arch_vfp_v2
;
25069 mfpu_opt
= &fpu_arch_fpa
;
25075 mcpu_cpu_opt
= &cpu_default
;
25076 selected_cpu
= cpu_default
;
25078 else if (dyn_mcpu_ext_opt
)
25079 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25081 selected_cpu
= *mcpu_cpu_opt
;
25083 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25084 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25085 else if (mcpu_cpu_opt
)
25086 selected_cpu
= *mcpu_cpu_opt
;
25088 mcpu_cpu_opt
= &arm_arch_any
;
25091 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25092 if (dyn_mcpu_ext_opt
)
25093 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25095 autoselect_thumb_from_cpu_variant ();
25097 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25099 #if defined OBJ_COFF || defined OBJ_ELF
25101 unsigned int flags
= 0;
25103 #if defined OBJ_ELF
25104 flags
= meabi_flags
;
25106 switch (meabi_flags
)
25108 case EF_ARM_EABI_UNKNOWN
:
25110 /* Set the flags in the private structure. */
25111 if (uses_apcs_26
) flags
|= F_APCS26
;
25112 if (support_interwork
) flags
|= F_INTERWORK
;
25113 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25114 if (pic_code
) flags
|= F_PIC
;
25115 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25116 flags
|= F_SOFT_FLOAT
;
25118 switch (mfloat_abi_opt
)
25120 case ARM_FLOAT_ABI_SOFT
:
25121 case ARM_FLOAT_ABI_SOFTFP
:
25122 flags
|= F_SOFT_FLOAT
;
25125 case ARM_FLOAT_ABI_HARD
:
25126 if (flags
& F_SOFT_FLOAT
)
25127 as_bad (_("hard-float conflicts with specified fpu"));
25131 /* Using pure-endian doubles (even if soft-float). */
25132 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25133 flags
|= F_VFP_FLOAT
;
25135 #if defined OBJ_ELF
25136 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25137 flags
|= EF_ARM_MAVERICK_FLOAT
;
25140 case EF_ARM_EABI_VER4
:
25141 case EF_ARM_EABI_VER5
:
25142 /* No additional flags to set. */
25149 bfd_set_private_flags (stdoutput
, flags
);
25151 /* We have run out flags in the COFF header to encode the
25152 status of ATPCS support, so instead we create a dummy,
25153 empty, debug section called .arm.atpcs. */
25158 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25162 bfd_set_section_flags
25163 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25164 bfd_set_section_size (stdoutput
, sec
, 0);
25165 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25171 /* Record the CPU type as well. */
25172 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25173 mach
= bfd_mach_arm_iWMMXt2
;
25174 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25175 mach
= bfd_mach_arm_iWMMXt
;
25176 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25177 mach
= bfd_mach_arm_XScale
;
25178 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25179 mach
= bfd_mach_arm_ep9312
;
25180 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25181 mach
= bfd_mach_arm_5TE
;
25182 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25184 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25185 mach
= bfd_mach_arm_5T
;
25187 mach
= bfd_mach_arm_5
;
25189 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25191 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25192 mach
= bfd_mach_arm_4T
;
25194 mach
= bfd_mach_arm_4
;
25196 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25197 mach
= bfd_mach_arm_3M
;
25198 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25199 mach
= bfd_mach_arm_3
;
25200 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25201 mach
= bfd_mach_arm_2a
;
25202 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25203 mach
= bfd_mach_arm_2
;
25205 mach
= bfd_mach_arm_unknown
;
25207 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25210 /* Command line processing. */
25213 Invocation line includes a switch not recognized by the base assembler.
25214 See if it's a processor-specific option.
25216 This routine is somewhat complicated by the need for backwards
25217 compatibility (since older releases of gcc can't be changed).
25218 The new options try to make the interface as compatible as
25221 New options (supported) are:
25223 -mcpu=<cpu name> Assemble for selected processor
25224 -march=<architecture name> Assemble for selected architecture
25225 -mfpu=<fpu architecture> Assemble for selected FPU.
25226 -EB/-mbig-endian Big-endian
25227 -EL/-mlittle-endian Little-endian
25228 -k Generate PIC code
25229 -mthumb Start in Thumb mode
25230 -mthumb-interwork Code supports ARM/Thumb interworking
25232 -m[no-]warn-deprecated Warn about deprecated features
25233 -m[no-]warn-syms Warn when symbols match instructions
25235 For now we will also provide support for:
25237 -mapcs-32 32-bit Program counter
25238 -mapcs-26 26-bit Program counter
25239 -macps-float Floats passed in FP registers
25240 -mapcs-reentrant Reentrant code
25242 (sometime these will probably be replaced with -mapcs=<list of options>
25243 and -matpcs=<list of options>)
25245 The remaining options are only supported for back-wards compatibility.
25246 Cpu variants, the arm part is optional:
25247 -m[arm]1 Currently not supported.
25248 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25249 -m[arm]3 Arm 3 processor
25250 -m[arm]6[xx], Arm 6 processors
25251 -m[arm]7[xx][t][[d]m] Arm 7 processors
25252 -m[arm]8[10] Arm 8 processors
25253 -m[arm]9[20][tdmi] Arm 9 processors
25254 -mstrongarm[110[0]] StrongARM processors
25255 -mxscale XScale processors
25256 -m[arm]v[2345[t[e]]] Arm architectures
25257 -mall All (except the ARM1)
25259 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25260 -mfpe-old (No float load/store multiples)
25261 -mvfpxd VFP Single precision
25263 -mno-fpu Disable all floating point instructions
25265 The following CPU names are recognized:
25266 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25267 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25268 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25269 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25270 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25271 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25272 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25276 const char * md_shortopts
= "m:k";
25278 #ifdef ARM_BI_ENDIAN
25279 #define OPTION_EB (OPTION_MD_BASE + 0)
25280 #define OPTION_EL (OPTION_MD_BASE + 1)
25282 #if TARGET_BYTES_BIG_ENDIAN
25283 #define OPTION_EB (OPTION_MD_BASE + 0)
25285 #define OPTION_EL (OPTION_MD_BASE + 1)
25288 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25290 struct option md_longopts
[] =
25293 {"EB", no_argument
, NULL
, OPTION_EB
},
25296 {"EL", no_argument
, NULL
, OPTION_EL
},
25298 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25299 {NULL
, no_argument
, NULL
, 0}
25303 size_t md_longopts_size
= sizeof (md_longopts
);
25305 struct arm_option_table
25307 const char *option
; /* Option name to match. */
25308 const char *help
; /* Help information. */
25309 int *var
; /* Variable to change. */
25310 int value
; /* What to change it to. */
25311 const char *deprecated
; /* If non-null, print this message. */
25314 struct arm_option_table arm_opts
[] =
25316 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25317 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25318 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25319 &support_interwork
, 1, NULL
},
25320 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25321 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25322 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25324 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25325 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25326 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25327 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25330 /* These are recognized by the assembler, but have no affect on code. */
25331 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25332 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25334 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25335 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25336 &warn_on_deprecated
, 0, NULL
},
25337 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25338 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25339 {NULL
, NULL
, NULL
, 0, NULL
}
25342 struct arm_legacy_option_table
25344 const char *option
; /* Option name to match. */
25345 const arm_feature_set
**var
; /* Variable to change. */
25346 const arm_feature_set value
; /* What to change it to. */
25347 const char *deprecated
; /* If non-null, print this message. */
25350 const struct arm_legacy_option_table arm_legacy_opts
[] =
25352 /* DON'T add any new processors to this list -- we want the whole list
25353 to go away... Add them to the processors table instead. */
25354 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25355 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25356 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25357 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25358 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25359 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25360 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25361 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25362 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25363 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25364 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25365 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25366 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25367 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25368 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25369 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25370 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25371 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25372 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25373 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25374 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25375 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25376 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25377 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25378 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25379 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25380 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25381 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25382 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25383 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25384 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25385 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25386 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25387 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25388 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25389 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25390 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25391 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25392 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25393 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25394 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25395 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25396 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25397 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25398 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25399 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25400 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25401 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25402 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25403 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25404 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25405 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25406 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25407 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25408 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25409 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25410 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25411 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25412 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25413 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25414 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25415 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25416 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25417 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25418 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25419 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25420 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25421 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25422 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25423 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25424 N_("use -mcpu=strongarm110")},
25425 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25426 N_("use -mcpu=strongarm1100")},
25427 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25428 N_("use -mcpu=strongarm1110")},
25429 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25430 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25431 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25433 /* Architecture variants -- don't add any more to this list either. */
25434 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25435 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25436 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25437 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25438 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25439 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25440 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25441 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25442 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25443 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25444 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25445 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25446 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25447 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25448 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25449 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25450 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25451 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25453 /* Floating point variants -- don't add any more to this list either. */
25454 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25455 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25456 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25457 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25458 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25460 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25463 struct arm_cpu_option_table
25467 const arm_feature_set value
;
25468 const arm_feature_set ext
;
25469 /* For some CPUs we assume an FPU unless the user explicitly sets
25471 const arm_feature_set default_fpu
;
25472 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25474 const char *canonical_name
;
25477 /* This list should, at a minimum, contain all the cpu names
25478 recognized by GCC. */
25479 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25480 static const struct arm_cpu_option_table arm_cpus
[] =
25482 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25485 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25488 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25491 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25494 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25497 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25500 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25503 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25506 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25509 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25512 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25515 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25518 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25521 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25524 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25527 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25530 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25533 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25536 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25539 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25542 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25545 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25548 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25551 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25554 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25557 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25560 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25563 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25566 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25569 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25572 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25575 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25578 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25581 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25584 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25587 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25590 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25593 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25596 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25599 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25602 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25605 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25608 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25611 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25614 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25617 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25621 /* For V5 or later processors we default to using VFP; but the user
25622 should really set the FPU type explicitly. */
25623 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25626 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25629 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25632 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25635 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25638 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25641 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25644 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25647 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25650 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25653 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25656 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25659 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25662 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25665 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25668 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25671 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25674 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25677 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25680 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25683 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25686 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25689 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25692 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25695 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25698 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25701 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25704 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25707 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25710 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25713 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25716 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25719 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25722 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25725 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
25728 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
25731 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
25732 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25734 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
25736 FPU_ARCH_NEON_VFP_V4
),
25737 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
25738 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25739 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25740 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
25741 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25742 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25743 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
25745 FPU_ARCH_NEON_VFP_V4
),
25746 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
25748 FPU_ARCH_NEON_VFP_V4
),
25749 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
25751 FPU_ARCH_NEON_VFP_V4
),
25752 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
25753 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25754 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25755 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
25756 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25757 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25758 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
25759 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25760 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25761 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
25762 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25763 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25764 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
25765 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25766 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25767 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
25768 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25769 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25770 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
25773 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
25775 FPU_ARCH_VFP_V3D16
),
25776 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
25777 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25779 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
25780 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25781 FPU_ARCH_VFP_V3D16
),
25782 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
25783 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25784 FPU_ARCH_VFP_V3D16
),
25785 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
25786 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25787 FPU_ARCH_NEON_VFP_ARMV8
),
25788 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
25789 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25791 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
25794 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
25797 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
25800 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
25803 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
25806 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
25809 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
25812 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
25813 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25814 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25816 /* ??? XSCALE is really an architecture. */
25817 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
25821 /* ??? iwmmxt is not a processor. */
25822 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
25825 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
25828 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
25833 ARM_CPU_OPT ("ep9312", "ARM920T",
25834 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25835 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
25837 /* Marvell processors. */
25838 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
25839 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25840 FPU_ARCH_VFP_V3D16
),
25841 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
25842 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25843 FPU_ARCH_NEON_VFP_V4
),
25845 /* APM X-Gene family. */
25846 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
25848 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25849 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
25850 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25851 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25853 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25857 struct arm_arch_option_table
25861 const arm_feature_set value
;
25862 const arm_feature_set default_fpu
;
25865 /* This list should, at a minimum, contain all the architecture names
25866 recognized by GCC. */
25867 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25868 static const struct arm_arch_option_table arm_archs
[] =
25870 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25871 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25872 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25873 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25874 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25875 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25876 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25877 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25878 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25879 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25880 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25881 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25882 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25883 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25884 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25885 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25886 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25887 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25888 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25889 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25890 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25891 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25892 kept to preserve existing behaviour. */
25893 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25894 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25895 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25896 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25897 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25898 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25899 kept to preserve existing behaviour. */
25900 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25901 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25902 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25903 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25904 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25905 /* The official spelling of the ARMv7 profile variants is the dashed form.
25906 Accept the non-dashed form for compatibility with old toolchains. */
25907 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25908 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25909 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25910 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25911 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25912 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25913 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25914 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25915 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25916 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25917 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25918 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25919 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25920 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25921 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
25922 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25923 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25924 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25925 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25927 #undef ARM_ARCH_OPT
25929 /* ISA extensions in the co-processor and main instruction set space. */
25930 struct arm_option_extension_value_table
25934 const arm_feature_set merge_value
;
25935 const arm_feature_set clear_value
;
25936 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25937 indicates that an extension is available for all architectures while
25938 ARM_ANY marks an empty entry. */
25939 const arm_feature_set allowed_archs
[2];
25942 /* The following table must be in alphabetical order with a NULL last entry.
25944 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25945 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25946 static const struct arm_option_extension_value_table arm_extensions
[] =
25948 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25949 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25950 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25951 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25952 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25953 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25954 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25955 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25956 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25957 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25958 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25959 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25961 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25962 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25963 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25964 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25965 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
25966 Thumb divide instruction. Due to this having the same name as the
25967 previous entry, this will be ignored when doing command-line parsing and
25968 only considered by build attribute selection code. */
25969 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
25970 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
25971 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
25972 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25973 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25974 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25975 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25976 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25977 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25978 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25979 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25980 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25981 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25982 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25983 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25984 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25985 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25986 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25987 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25988 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25989 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25990 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25991 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25992 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25993 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25994 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25995 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25996 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25997 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25998 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25999 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26000 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26001 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26003 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26004 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26005 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26006 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26007 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26011 /* ISA floating-point and Advanced SIMD extensions. */
26012 struct arm_option_fpu_value_table
26015 const arm_feature_set value
;
26018 /* This list should, at a minimum, contain all the fpu names
26019 recognized by GCC. */
26020 static const struct arm_option_fpu_value_table arm_fpus
[] =
26022 {"softfpa", FPU_NONE
},
26023 {"fpe", FPU_ARCH_FPE
},
26024 {"fpe2", FPU_ARCH_FPE
},
26025 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26026 {"fpa", FPU_ARCH_FPA
},
26027 {"fpa10", FPU_ARCH_FPA
},
26028 {"fpa11", FPU_ARCH_FPA
},
26029 {"arm7500fe", FPU_ARCH_FPA
},
26030 {"softvfp", FPU_ARCH_VFP
},
26031 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26032 {"vfp", FPU_ARCH_VFP_V2
},
26033 {"vfp9", FPU_ARCH_VFP_V2
},
26034 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26035 {"vfp10", FPU_ARCH_VFP_V2
},
26036 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26037 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26038 {"vfpv2", FPU_ARCH_VFP_V2
},
26039 {"vfpv3", FPU_ARCH_VFP_V3
},
26040 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26041 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26042 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26043 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26044 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26045 {"arm1020t", FPU_ARCH_VFP_V1
},
26046 {"arm1020e", FPU_ARCH_VFP_V2
},
26047 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26048 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26049 {"maverick", FPU_ARCH_MAVERICK
},
26050 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26051 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26052 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26053 {"vfpv4", FPU_ARCH_VFP_V4
},
26054 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26055 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26056 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26057 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26058 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26059 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26060 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26061 {"crypto-neon-fp-armv8",
26062 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26063 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26064 {"crypto-neon-fp-armv8.1",
26065 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26066 {NULL
, ARM_ARCH_NONE
}
26069 struct arm_option_value_table
26075 static const struct arm_option_value_table arm_float_abis
[] =
26077 {"hard", ARM_FLOAT_ABI_HARD
},
26078 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26079 {"soft", ARM_FLOAT_ABI_SOFT
},
26084 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26085 static const struct arm_option_value_table arm_eabis
[] =
26087 {"gnu", EF_ARM_EABI_UNKNOWN
},
26088 {"4", EF_ARM_EABI_VER4
},
26089 {"5", EF_ARM_EABI_VER5
},
26094 struct arm_long_option_table
26096 const char * option
; /* Substring to match. */
26097 const char * help
; /* Help information. */
26098 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26099 const char * deprecated
; /* If non-null, print this message. */
26103 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26104 arm_feature_set
**ext_set_p
)
26106 /* We insist on extensions being specified in alphabetical order, and with
26107 extensions being added before being removed. We achieve this by having
26108 the global ARM_EXTENSIONS table in alphabetical order, and using the
26109 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26110 or removing it (0) and only allowing it to change in the order
26112 const struct arm_option_extension_value_table
* opt
= NULL
;
26113 const arm_feature_set arm_any
= ARM_ANY
;
26114 int adding_value
= -1;
26118 *ext_set_p
= XNEW (arm_feature_set
);
26119 **ext_set_p
= arm_arch_none
;
26122 while (str
!= NULL
&& *str
!= 0)
26129 as_bad (_("invalid architectural extension"));
26134 ext
= strchr (str
, '+');
26139 len
= strlen (str
);
26141 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26143 if (adding_value
!= 0)
26146 opt
= arm_extensions
;
26154 if (adding_value
== -1)
26157 opt
= arm_extensions
;
26159 else if (adding_value
!= 1)
26161 as_bad (_("must specify extensions to add before specifying "
26162 "those to remove"));
26169 as_bad (_("missing architectural extension"));
26173 gas_assert (adding_value
!= -1);
26174 gas_assert (opt
!= NULL
);
26176 /* Scan over the options table trying to find an exact match. */
26177 for (; opt
->name
!= NULL
; opt
++)
26178 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26180 int i
, nb_allowed_archs
=
26181 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26182 /* Check we can apply the extension to this architecture. */
26183 for (i
= 0; i
< nb_allowed_archs
; i
++)
26186 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26188 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26191 if (i
== nb_allowed_archs
)
26193 as_bad (_("extension does not apply to the base architecture"));
26197 /* Add or remove the extension. */
26199 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26202 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26204 /* Allowing Thumb division instructions for ARMv7 in autodetection
26205 rely on this break so that duplicate extensions (extensions
26206 with the same name as a previous extension in the list) are not
26207 considered for command-line parsing. */
26211 if (opt
->name
== NULL
)
26213 /* Did we fail to find an extension because it wasn't specified in
26214 alphabetical order, or because it does not exist? */
26216 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26217 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26220 if (opt
->name
== NULL
)
26221 as_bad (_("unknown architectural extension `%s'"), str
);
26223 as_bad (_("architectural extensions must be specified in "
26224 "alphabetical order"));
26230 /* We should skip the extension we've just matched the next time
26242 arm_parse_cpu (const char *str
)
26244 const struct arm_cpu_option_table
*opt
;
26245 const char *ext
= strchr (str
, '+');
26251 len
= strlen (str
);
26255 as_bad (_("missing cpu name `%s'"), str
);
26259 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26260 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26262 mcpu_cpu_opt
= &opt
->value
;
26263 if (!dyn_mcpu_ext_opt
)
26264 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26265 *dyn_mcpu_ext_opt
= opt
->ext
;
26266 mcpu_fpu_opt
= &opt
->default_fpu
;
26267 if (opt
->canonical_name
)
26269 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26270 strcpy (selected_cpu_name
, opt
->canonical_name
);
26276 if (len
>= sizeof selected_cpu_name
)
26277 len
= (sizeof selected_cpu_name
) - 1;
26279 for (i
= 0; i
< len
; i
++)
26280 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26281 selected_cpu_name
[i
] = 0;
26285 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26290 as_bad (_("unknown cpu `%s'"), str
);
26295 arm_parse_arch (const char *str
)
26297 const struct arm_arch_option_table
*opt
;
26298 const char *ext
= strchr (str
, '+');
26304 len
= strlen (str
);
26308 as_bad (_("missing architecture name `%s'"), str
);
26312 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26313 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26315 march_cpu_opt
= &opt
->value
;
26316 march_fpu_opt
= &opt
->default_fpu
;
26317 strcpy (selected_cpu_name
, opt
->name
);
26320 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26325 as_bad (_("unknown architecture `%s'\n"), str
);
26330 arm_parse_fpu (const char * str
)
26332 const struct arm_option_fpu_value_table
* opt
;
26334 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26335 if (streq (opt
->name
, str
))
26337 mfpu_opt
= &opt
->value
;
26341 as_bad (_("unknown floating point format `%s'\n"), str
);
26346 arm_parse_float_abi (const char * str
)
26348 const struct arm_option_value_table
* opt
;
26350 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26351 if (streq (opt
->name
, str
))
26353 mfloat_abi_opt
= opt
->value
;
26357 as_bad (_("unknown floating point abi `%s'\n"), str
);
26363 arm_parse_eabi (const char * str
)
26365 const struct arm_option_value_table
*opt
;
26367 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26368 if (streq (opt
->name
, str
))
26370 meabi_flags
= opt
->value
;
26373 as_bad (_("unknown EABI `%s'\n"), str
);
26379 arm_parse_it_mode (const char * str
)
26381 bfd_boolean ret
= TRUE
;
26383 if (streq ("arm", str
))
26384 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26385 else if (streq ("thumb", str
))
26386 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26387 else if (streq ("always", str
))
26388 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26389 else if (streq ("never", str
))
26390 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26393 as_bad (_("unknown implicit IT mode `%s', should be "\
26394 "arm, thumb, always, or never."), str
);
26402 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26404 codecomposer_syntax
= TRUE
;
26405 arm_comment_chars
[0] = ';';
26406 arm_line_separator_chars
[0] = 0;
26410 struct arm_long_option_table arm_long_opts
[] =
26412 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26413 arm_parse_cpu
, NULL
},
26414 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26415 arm_parse_arch
, NULL
},
26416 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26417 arm_parse_fpu
, NULL
},
26418 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26419 arm_parse_float_abi
, NULL
},
26421 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26422 arm_parse_eabi
, NULL
},
26424 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26425 arm_parse_it_mode
, NULL
},
26426 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26427 arm_ccs_mode
, NULL
},
26428 {NULL
, NULL
, 0, NULL
}
26432 md_parse_option (int c
, const char * arg
)
26434 struct arm_option_table
*opt
;
26435 const struct arm_legacy_option_table
*fopt
;
26436 struct arm_long_option_table
*lopt
;
26442 target_big_endian
= 1;
26448 target_big_endian
= 0;
26452 case OPTION_FIX_V4BX
:
26457 /* Listing option. Just ignore these, we don't support additional
26462 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26464 if (c
== opt
->option
[0]
26465 && ((arg
== NULL
&& opt
->option
[1] == 0)
26466 || streq (arg
, opt
->option
+ 1)))
26468 /* If the option is deprecated, tell the user. */
26469 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26470 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26471 arg
? arg
: "", _(opt
->deprecated
));
26473 if (opt
->var
!= NULL
)
26474 *opt
->var
= opt
->value
;
26480 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26482 if (c
== fopt
->option
[0]
26483 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26484 || streq (arg
, fopt
->option
+ 1)))
26486 /* If the option is deprecated, tell the user. */
26487 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26488 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26489 arg
? arg
: "", _(fopt
->deprecated
));
26491 if (fopt
->var
!= NULL
)
26492 *fopt
->var
= &fopt
->value
;
26498 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26500 /* These options are expected to have an argument. */
26501 if (c
== lopt
->option
[0]
26503 && strncmp (arg
, lopt
->option
+ 1,
26504 strlen (lopt
->option
+ 1)) == 0)
26506 /* If the option is deprecated, tell the user. */
26507 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26508 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26509 _(lopt
->deprecated
));
26511 /* Call the sup-option parser. */
26512 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26523 md_show_usage (FILE * fp
)
26525 struct arm_option_table
*opt
;
26526 struct arm_long_option_table
*lopt
;
26528 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26530 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26531 if (opt
->help
!= NULL
)
26532 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26534 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26535 if (lopt
->help
!= NULL
)
26536 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26540 -EB assemble code for a big-endian cpu\n"));
26545 -EL assemble code for a little-endian cpu\n"));
26549 --fix-v4bx Allow BX in ARMv4 code\n"));
26557 arm_feature_set flags
;
26558 } cpu_arch_ver_table
;
26560 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26561 chronologically for architectures, with an exception for ARMv6-M and
26562 ARMv6S-M due to legacy reasons. No new architecture should have a
26563 special case. This allows for build attribute selection results to be
26564 stable when new architectures are added. */
26565 static const cpu_arch_ver_table cpu_arch_ver
[] =
26572 {1, ARM_ARCH_V4xM
},
26574 {2, ARM_ARCH_V4TxM
},
26576 {3, ARM_ARCH_V5xM
},
26578 {3, ARM_ARCH_V5TxM
},
26580 {4, ARM_ARCH_V5TExP
},
26581 {4, ARM_ARCH_V5TE
},
26582 {5, ARM_ARCH_V5TEJ
},
26585 {7, ARM_ARCH_V6KZ
},
26587 {8, ARM_ARCH_V6T2
},
26588 {8, ARM_ARCH_V6KT2
},
26589 {8, ARM_ARCH_V6ZT2
},
26590 {8, ARM_ARCH_V6KZT2
},
26592 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26593 always selected build attributes to match those of ARMv6-M
26594 (resp. ARMv6S-M). However, due to these architectures being a strict
26595 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26596 would be selected when fully respecting chronology of architectures.
26597 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26598 move them before ARMv7 architectures. */
26599 {11, ARM_ARCH_V6M
},
26600 {12, ARM_ARCH_V6SM
},
26603 {10, ARM_ARCH_V7A
},
26604 {10, ARM_ARCH_V7R
},
26605 {10, ARM_ARCH_V7M
},
26606 {10, ARM_ARCH_V7VE
},
26607 {13, ARM_ARCH_V7EM
},
26608 {14, ARM_ARCH_V8A
},
26609 {14, ARM_ARCH_V8_1A
},
26610 {14, ARM_ARCH_V8_2A
},
26611 {14, ARM_ARCH_V8_3A
},
26612 {16, ARM_ARCH_V8M_BASE
},
26613 {17, ARM_ARCH_V8M_MAIN
},
26614 {15, ARM_ARCH_V8R
},
26615 {-1, ARM_ARCH_NONE
}
26618 /* Set an attribute if it has not already been set by the user. */
26620 aeabi_set_attribute_int (int tag
, int value
)
26623 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26624 || !attributes_set_explicitly
[tag
])
26625 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26629 aeabi_set_attribute_string (int tag
, const char *value
)
26632 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26633 || !attributes_set_explicitly
[tag
])
26634 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26637 /* Return whether features in the *NEEDED feature set are available via
26638 extensions for the architecture whose feature set is *ARCH_FSET. */
26640 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26641 const arm_feature_set
*needed
)
26643 int i
, nb_allowed_archs
;
26644 arm_feature_set ext_fset
;
26645 const struct arm_option_extension_value_table
*opt
;
26647 ext_fset
= arm_arch_none
;
26648 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26650 /* Extension does not provide any feature we need. */
26651 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26655 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26656 for (i
= 0; i
< nb_allowed_archs
; i
++)
26659 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26662 /* Extension is available, add it. */
26663 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26664 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26668 /* Can we enable all features in *needed? */
26669 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26672 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26673 a given architecture feature set *ARCH_EXT_FSET including extension feature
26674 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26675 - if true, check for an exact match of the architecture modulo extensions;
26676 - otherwise, select build attribute value of the first superset
26677 architecture released so that results remains stable when new architectures
26679 For -march/-mcpu=all the build attribute value of the most featureful
26680 architecture is returned. Tag_CPU_arch_profile result is returned in
26683 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26684 const arm_feature_set
*ext_fset
,
26685 char *profile
, int exact_match
)
26687 arm_feature_set arch_fset
;
26688 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26690 /* Select most featureful architecture with all its extensions if building
26691 for -march=all as the feature sets used to set build attributes. */
26692 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26694 /* Force revisiting of decision for each new architecture. */
26695 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26697 return TAG_CPU_ARCH_V8
;
26700 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
26702 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
26704 arm_feature_set known_arch_fset
;
26706 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
26709 /* Base architecture match user-specified architecture and
26710 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
26711 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
26716 /* Base architecture match user-specified architecture only
26717 (eg. ARMv6-M in the same case as above). Record it in case we
26718 find a match with above condition. */
26719 else if (p_ver_ret
== NULL
26720 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
26726 /* Architecture has all features wanted. */
26727 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
26729 arm_feature_set added_fset
;
26731 /* Compute features added by this architecture over the one
26732 recorded in p_ver_ret. */
26733 if (p_ver_ret
!= NULL
)
26734 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
26736 /* First architecture that match incl. with extensions, or the
26737 only difference in features over the recorded match is
26738 features that were optional and are now mandatory. */
26739 if (p_ver_ret
== NULL
26740 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
26746 else if (p_ver_ret
== NULL
)
26748 arm_feature_set needed_ext_fset
;
26750 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
26752 /* Architecture has all features needed when using some
26753 extensions. Record it and continue searching in case there
26754 exist an architecture providing all needed features without
26755 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
26757 if (have_ext_for_needed_feat_p (&known_arch_fset
,
26764 if (p_ver_ret
== NULL
)
26768 /* Tag_CPU_arch_profile. */
26769 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
26770 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
26771 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
26772 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
26774 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
26776 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
26780 return p_ver_ret
->val
;
26783 /* Set the public EABI object attributes. */
26785 aeabi_set_public_attributes (void)
26790 int fp16_optional
= 0;
26791 int skip_exact_match
= 0;
26792 arm_feature_set flags
, flags_arch
, flags_ext
;
26794 /* Autodetection mode, choose the architecture based the instructions
26796 if (no_cpu_selected ())
26798 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26800 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26801 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26803 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26804 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26806 /* Code run during relaxation relies on selected_cpu being set. */
26807 selected_cpu
= flags
;
26809 /* Otherwise, choose the architecture based on the capabilities of the
26812 flags
= selected_cpu
;
26813 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26815 /* Allow the user to override the reported architecture. */
26818 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
26819 flags_ext
= arm_arch_none
;
26823 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26824 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
26825 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
26828 /* When this function is run again after relaxation has happened there is no
26829 way to determine whether an architecture or CPU was specified by the user:
26830 - selected_cpu is set above for relaxation to work;
26831 - march_cpu_opt is not set if only -mcpu or .cpu is used;
26832 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
26833 Therefore, if not in -march=all case we first try an exact match and fall
26834 back to autodetection. */
26835 if (!skip_exact_match
)
26836 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
26838 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
26840 as_bad (_("no architecture contains all the instructions used\n"));
26842 /* Tag_CPU_name. */
26843 if (selected_cpu_name
[0])
26847 q
= selected_cpu_name
;
26848 if (strncmp (q
, "armv", 4) == 0)
26853 for (i
= 0; q
[i
]; i
++)
26854 q
[i
] = TOUPPER (q
[i
]);
26856 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26859 /* Tag_CPU_arch. */
26860 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26862 /* Tag_CPU_arch_profile. */
26863 if (profile
!= '\0')
26864 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26866 /* Tag_DSP_extension. */
26867 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
26868 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26870 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26871 /* Tag_ARM_ISA_use. */
26872 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26873 || ARM_FEATURE_ZERO (flags_arch
))
26874 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26876 /* Tag_THUMB_ISA_use. */
26877 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26878 || ARM_FEATURE_ZERO (flags_arch
))
26882 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26883 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26885 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26889 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26892 /* Tag_VFP_arch. */
26893 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26894 aeabi_set_attribute_int (Tag_VFP_arch
,
26895 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26897 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26898 aeabi_set_attribute_int (Tag_VFP_arch
,
26899 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26901 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26904 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26906 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26908 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26911 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26912 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26913 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26914 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26915 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26917 /* Tag_ABI_HardFP_use. */
26918 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26919 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26920 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26922 /* Tag_WMMX_arch. */
26923 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26924 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26925 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26926 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26928 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26929 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26930 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26931 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26932 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26933 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26935 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26937 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26941 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26946 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26947 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26948 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26952 We set Tag_DIV_use to two when integer divide instructions have been used
26953 in ARM state, or when Thumb integer divide instructions have been used,
26954 but we have no architecture profile set, nor have we any ARM instructions.
26956 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26957 by the base architecture.
26959 For new architectures we will have to check these tests. */
26960 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
26961 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26962 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26963 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26964 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26965 || (profile
== '\0'
26966 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26967 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26968 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26970 /* Tag_MP_extension_use. */
26971 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26972 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26974 /* Tag Virtualization_use. */
26975 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26977 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26980 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26983 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
26984 finished and free extension feature bits which will not be used anymore. */
26986 arm_md_post_relax (void)
26988 aeabi_set_public_attributes ();
26989 XDELETE (dyn_mcpu_ext_opt
);
26990 dyn_mcpu_ext_opt
= NULL
;
26991 XDELETE (dyn_march_ext_opt
);
26992 dyn_march_ext_opt
= NULL
;
26995 /* Add the default contents for the .ARM.attributes section. */
26999 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27002 aeabi_set_public_attributes ();
27004 #endif /* OBJ_ELF */
27007 /* Parse a .cpu directive. */
27010 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27012 const struct arm_cpu_option_table
*opt
;
27016 name
= input_line_pointer
;
27017 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27018 input_line_pointer
++;
27019 saved_char
= *input_line_pointer
;
27020 *input_line_pointer
= 0;
27022 /* Skip the first "all" entry. */
27023 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27024 if (streq (opt
->name
, name
))
27026 mcpu_cpu_opt
= &opt
->value
;
27027 if (!dyn_mcpu_ext_opt
)
27028 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27029 *dyn_mcpu_ext_opt
= opt
->ext
;
27030 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27031 if (opt
->canonical_name
)
27032 strcpy (selected_cpu_name
, opt
->canonical_name
);
27036 for (i
= 0; opt
->name
[i
]; i
++)
27037 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27039 selected_cpu_name
[i
] = 0;
27041 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27042 if (dyn_mcpu_ext_opt
)
27043 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27044 *input_line_pointer
= saved_char
;
27045 demand_empty_rest_of_line ();
27048 as_bad (_("unknown cpu `%s'"), name
);
27049 *input_line_pointer
= saved_char
;
27050 ignore_rest_of_line ();
27054 /* Parse a .arch directive. */
27057 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27059 const struct arm_arch_option_table
*opt
;
27063 name
= input_line_pointer
;
27064 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27065 input_line_pointer
++;
27066 saved_char
= *input_line_pointer
;
27067 *input_line_pointer
= 0;
27069 /* Skip the first "all" entry. */
27070 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27071 if (streq (opt
->name
, name
))
27073 mcpu_cpu_opt
= &opt
->value
;
27074 XDELETE (dyn_mcpu_ext_opt
);
27075 dyn_mcpu_ext_opt
= NULL
;
27076 selected_cpu
= *mcpu_cpu_opt
;
27077 strcpy (selected_cpu_name
, opt
->name
);
27078 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27079 *input_line_pointer
= saved_char
;
27080 demand_empty_rest_of_line ();
27084 as_bad (_("unknown architecture `%s'\n"), name
);
27085 *input_line_pointer
= saved_char
;
27086 ignore_rest_of_line ();
27090 /* Parse a .object_arch directive. */
27093 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27095 const struct arm_arch_option_table
*opt
;
27099 name
= input_line_pointer
;
27100 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27101 input_line_pointer
++;
27102 saved_char
= *input_line_pointer
;
27103 *input_line_pointer
= 0;
27105 /* Skip the first "all" entry. */
27106 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27107 if (streq (opt
->name
, name
))
27109 object_arch
= &opt
->value
;
27110 *input_line_pointer
= saved_char
;
27111 demand_empty_rest_of_line ();
27115 as_bad (_("unknown architecture `%s'\n"), name
);
27116 *input_line_pointer
= saved_char
;
27117 ignore_rest_of_line ();
27120 /* Parse a .arch_extension directive. */
27123 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27125 const struct arm_option_extension_value_table
*opt
;
27126 const arm_feature_set arm_any
= ARM_ANY
;
27129 int adding_value
= 1;
27131 name
= input_line_pointer
;
27132 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27133 input_line_pointer
++;
27134 saved_char
= *input_line_pointer
;
27135 *input_line_pointer
= 0;
27137 if (strlen (name
) >= 2
27138 && strncmp (name
, "no", 2) == 0)
27144 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27145 if (streq (opt
->name
, name
))
27147 int i
, nb_allowed_archs
=
27148 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27149 for (i
= 0; i
< nb_allowed_archs
; i
++)
27152 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27154 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27158 if (i
== nb_allowed_archs
)
27160 as_bad (_("architectural extension `%s' is not allowed for the "
27161 "current base architecture"), name
);
27165 if (!dyn_mcpu_ext_opt
)
27167 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27168 *dyn_mcpu_ext_opt
= arm_arch_none
;
27171 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27174 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27177 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27178 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27179 *input_line_pointer
= saved_char
;
27180 demand_empty_rest_of_line ();
27181 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27182 on this return so that duplicate extensions (extensions with the
27183 same name as a previous extension in the list) are not considered
27184 for command-line parsing. */
27188 if (opt
->name
== NULL
)
27189 as_bad (_("unknown architecture extension `%s'\n"), name
);
27191 *input_line_pointer
= saved_char
;
27192 ignore_rest_of_line ();
27195 /* Parse a .fpu directive. */
27198 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27200 const struct arm_option_fpu_value_table
*opt
;
27204 name
= input_line_pointer
;
27205 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27206 input_line_pointer
++;
27207 saved_char
= *input_line_pointer
;
27208 *input_line_pointer
= 0;
27210 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27211 if (streq (opt
->name
, name
))
27213 mfpu_opt
= &opt
->value
;
27214 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27215 if (dyn_mcpu_ext_opt
)
27216 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27217 *input_line_pointer
= saved_char
;
27218 demand_empty_rest_of_line ();
27222 as_bad (_("unknown floating point format `%s'\n"), name
);
27223 *input_line_pointer
= saved_char
;
27224 ignore_rest_of_line ();
27227 /* Copy symbol information. */
27230 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27232 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27236 /* Given a symbolic attribute NAME, return the proper integer value.
27237 Returns -1 if the attribute is not known. */
27240 arm_convert_symbolic_attribute (const char *name
)
27242 static const struct
27247 attribute_table
[] =
27249 /* When you modify this table you should
27250 also modify the list in doc/c-arm.texi. */
27251 #define T(tag) {#tag, tag}
27252 T (Tag_CPU_raw_name
),
27255 T (Tag_CPU_arch_profile
),
27256 T (Tag_ARM_ISA_use
),
27257 T (Tag_THUMB_ISA_use
),
27261 T (Tag_Advanced_SIMD_arch
),
27262 T (Tag_PCS_config
),
27263 T (Tag_ABI_PCS_R9_use
),
27264 T (Tag_ABI_PCS_RW_data
),
27265 T (Tag_ABI_PCS_RO_data
),
27266 T (Tag_ABI_PCS_GOT_use
),
27267 T (Tag_ABI_PCS_wchar_t
),
27268 T (Tag_ABI_FP_rounding
),
27269 T (Tag_ABI_FP_denormal
),
27270 T (Tag_ABI_FP_exceptions
),
27271 T (Tag_ABI_FP_user_exceptions
),
27272 T (Tag_ABI_FP_number_model
),
27273 T (Tag_ABI_align_needed
),
27274 T (Tag_ABI_align8_needed
),
27275 T (Tag_ABI_align_preserved
),
27276 T (Tag_ABI_align8_preserved
),
27277 T (Tag_ABI_enum_size
),
27278 T (Tag_ABI_HardFP_use
),
27279 T (Tag_ABI_VFP_args
),
27280 T (Tag_ABI_WMMX_args
),
27281 T (Tag_ABI_optimization_goals
),
27282 T (Tag_ABI_FP_optimization_goals
),
27283 T (Tag_compatibility
),
27284 T (Tag_CPU_unaligned_access
),
27285 T (Tag_FP_HP_extension
),
27286 T (Tag_VFP_HP_extension
),
27287 T (Tag_ABI_FP_16bit_format
),
27288 T (Tag_MPextension_use
),
27290 T (Tag_nodefaults
),
27291 T (Tag_also_compatible_with
),
27292 T (Tag_conformance
),
27294 T (Tag_Virtualization_use
),
27295 T (Tag_DSP_extension
),
27296 /* We deliberately do not include Tag_MPextension_use_legacy. */
27304 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27305 if (streq (name
, attribute_table
[i
].name
))
27306 return attribute_table
[i
].tag
;
27312 /* Apply sym value for relocations only in the case that they are for
27313 local symbols in the same segment as the fixup and you have the
27314 respective architectural feature for blx and simple switches. */
27316 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27319 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27320 /* PR 17444: If the local symbol is in a different section then a reloc
27321 will always be generated for it, so applying the symbol value now
27322 will result in a double offset being stored in the relocation. */
27323 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27324 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27326 switch (fixP
->fx_r_type
)
27328 case BFD_RELOC_ARM_PCREL_BLX
:
27329 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27330 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27334 case BFD_RELOC_ARM_PCREL_CALL
:
27335 case BFD_RELOC_THUMB_PCREL_BLX
:
27336 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27347 #endif /* OBJ_ELF */