1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
306 static const arm_feature_set fpu_vfp_fp16
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
308 static const arm_feature_set fpu_neon_ext_fma
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_fma
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
313 static const arm_feature_set fpu_vfp_ext_armv8
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
315 static const arm_feature_set fpu_vfp_ext_armv8xd
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
317 static const arm_feature_set fpu_neon_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
319 static const arm_feature_set fpu_crypto_ext_armv8
=
320 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
321 static const arm_feature_set crc_ext_armv8
=
322 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
323 static const arm_feature_set fpu_neon_ext_v8_1
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
325 static const arm_feature_set fpu_neon_ext_dotprod
=
326 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
328 static int mfloat_abi_opt
= -1;
329 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
331 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
332 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
334 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
335 /* Feature bits selected by the last -mcpu/-march or by the combination of the
336 last .cpu/.arch directive .arch_extension directives since that
338 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
339 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
340 static arm_feature_set selected_fpu
= FPU_NONE
;
341 /* Feature bits selected by the last .object_arch directive. */
342 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
343 /* Must be long enough to hold any of the names in arm_cpus. */
344 static char selected_cpu_name
[20];
346 extern FLONUM_TYPE generic_floating_point_number
;
348 /* Return if no cpu was selected on command-line. */
350 no_cpu_selected (void)
352 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
357 static int meabi_flags
= EABI_DEFAULT
;
359 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
362 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
367 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
372 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
373 symbolS
* GOT_symbol
;
376 /* 0: assemble for ARM,
377 1: assemble for Thumb,
378 2: assemble for Thumb even though target CPU does not support thumb
380 static int thumb_mode
= 0;
381 /* A value distinct from the possible values for thumb_mode that we
382 can use to record whether thumb_mode has been copied into the
383 tc_frag_data field of a frag. */
384 #define MODE_RECORDED (1 << 4)
386 /* Specifies the intrinsic IT insn behavior mode. */
387 enum implicit_it_mode
389 IMPLICIT_IT_MODE_NEVER
= 0x00,
390 IMPLICIT_IT_MODE_ARM
= 0x01,
391 IMPLICIT_IT_MODE_THUMB
= 0x02,
392 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
394 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
396 /* If unified_syntax is true, we are processing the new unified
397 ARM/Thumb syntax. Important differences from the old ARM mode:
399 - Immediate operands do not require a # prefix.
400 - Conditional affixes always appear at the end of the
401 instruction. (For backward compatibility, those instructions
402 that formerly had them in the middle, continue to accept them
404 - The IT instruction may appear, and if it does is validated
405 against subsequent conditional affixes. It does not generate
408 Important differences from the old Thumb mode:
410 - Immediate operands do not require a # prefix.
411 - Most of the V6T2 instructions are only available in unified mode.
412 - The .N and .W suffixes are recognized and honored (it is an error
413 if they cannot be honored).
414 - All instructions set the flags if and only if they have an 's' affix.
415 - Conditional affixes may be used. They are validated against
416 preceding IT instructions. Unlike ARM mode, you cannot use a
417 conditional affix except in the scope of an IT instruction. */
419 static bfd_boolean unified_syntax
= FALSE
;
421 /* An immediate operand can start with #, and ld*, st*, pld operands
422 can contain [ and ]. We need to tell APP not to elide whitespace
423 before a [, which can appear as the first operand for pld.
424 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
425 const char arm_symbol_chars
[] = "#[]{}";
440 enum neon_el_type type
;
444 #define NEON_MAX_TYPE_ELS 4
448 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
452 enum it_instruction_type
457 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
458 if inside, should be the last one. */
459 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
460 i.e. BKPT and NOP. */
461 IT_INSN
/* The IT insn has been parsed. */
464 /* The maximum number of operands we need. */
465 #define ARM_IT_MAX_OPERANDS 6
466 #define ARM_IT_MAX_RELOCS 3
471 unsigned long instruction
;
475 /* "uncond_value" is set to the value in place of the conditional field in
476 unconditional versions of the instruction, or -1 if nothing is
479 struct neon_type vectype
;
480 /* This does not indicate an actual NEON instruction, only that
481 the mnemonic accepts neon-style type suffixes. */
483 /* Set to the opcode if the instruction needs relaxation.
484 Zero if the instruction is not relaxed. */
488 bfd_reloc_code_real_type type
;
491 } relocs
[ARM_IT_MAX_RELOCS
];
493 enum it_instruction_type it_insn_type
;
499 struct neon_type_el vectype
;
500 unsigned present
: 1; /* Operand present. */
501 unsigned isreg
: 1; /* Operand was a register. */
502 unsigned immisreg
: 1; /* .imm field is a second register. */
503 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
504 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
505 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
506 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
507 instructions. This allows us to disambiguate ARM <-> vector insns. */
508 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
509 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
510 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
511 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
512 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
513 unsigned writeback
: 1; /* Operand has trailing ! */
514 unsigned preind
: 1; /* Preindexed address. */
515 unsigned postind
: 1; /* Postindexed address. */
516 unsigned negative
: 1; /* Index register was negated. */
517 unsigned shifted
: 1; /* Shift applied to operation. */
518 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
519 } operands
[ARM_IT_MAX_OPERANDS
];
522 static struct arm_it inst
;
524 #define NUM_FLOAT_VALS 8
526 const char * fp_const
[] =
528 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
531 /* Number of littlenums required to hold an extended precision number. */
532 #define MAX_LITTLENUMS 6
534 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
544 #define CP_T_X 0x00008000
545 #define CP_T_Y 0x00400000
547 #define CONDS_BIT 0x00100000
548 #define LOAD_BIT 0x00100000
550 #define DOUBLE_LOAD_FLAG 0x00000001
554 const char * template_name
;
558 #define COND_ALWAYS 0xE
562 const char * template_name
;
566 struct asm_barrier_opt
568 const char * template_name
;
570 const arm_feature_set arch
;
573 /* The bit that distinguishes CPSR and SPSR. */
574 #define SPSR_BIT (1 << 22)
576 /* The individual PSR flag bits. */
577 #define PSR_c (1 << 16)
578 #define PSR_x (1 << 17)
579 #define PSR_s (1 << 18)
580 #define PSR_f (1 << 19)
585 bfd_reloc_code_real_type reloc
;
590 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
591 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
596 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
599 /* Bits for DEFINED field in neon_typed_alias. */
600 #define NTA_HASTYPE 1
601 #define NTA_HASINDEX 2
603 struct neon_typed_alias
605 unsigned char defined
;
607 struct neon_type_el eltype
;
610 /* ARM register categories. This includes coprocessor numbers and various
611 architecture extensions' registers. Each entry should have an error message
612 in reg_expected_msgs below. */
640 /* Structure for a hash table entry for a register.
641 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
642 information which states whether a vector type or index is specified (for a
643 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
649 unsigned char builtin
;
650 struct neon_typed_alias
* neon
;
653 /* Diagnostics used when we don't get a register of the expected type. */
654 const char * const reg_expected_msgs
[] =
656 [REG_TYPE_RN
] = N_("ARM register expected"),
657 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
658 [REG_TYPE_CN
] = N_("co-processor register expected"),
659 [REG_TYPE_FN
] = N_("FPA register expected"),
660 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
661 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
662 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
663 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
664 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
665 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
666 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
668 [REG_TYPE_VFC
] = N_("VFP system register expected"),
669 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
670 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
671 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
672 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
673 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
674 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
675 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
676 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
677 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
678 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
679 [REG_TYPE_RNB
] = N_("")
682 /* Some well known registers that we refer to directly elsewhere. */
688 /* ARM instructions take 4bytes in the object file, Thumb instructions
694 /* Basic string to match. */
695 const char * template_name
;
697 /* Parameters to instruction. */
698 unsigned int operands
[8];
700 /* Conditional tag - see opcode_lookup. */
701 unsigned int tag
: 4;
703 /* Basic instruction code. */
704 unsigned int avalue
: 28;
706 /* Thumb-format instruction code. */
709 /* Which architecture variant provides this instruction. */
710 const arm_feature_set
* avariant
;
711 const arm_feature_set
* tvariant
;
713 /* Function to call to encode instruction in ARM format. */
714 void (* aencode
) (void);
716 /* Function to call to encode instruction in Thumb format. */
717 void (* tencode
) (void);
720 /* Defines for various bits that we will want to toggle. */
721 #define INST_IMMEDIATE 0x02000000
722 #define OFFSET_REG 0x02000000
723 #define HWOFFSET_IMM 0x00400000
724 #define SHIFT_BY_REG 0x00000010
725 #define PRE_INDEX 0x01000000
726 #define INDEX_UP 0x00800000
727 #define WRITE_BACK 0x00200000
728 #define LDM_TYPE_2_OR_3 0x00400000
729 #define CPSI_MMOD 0x00020000
731 #define LITERAL_MASK 0xf000f000
732 #define OPCODE_MASK 0xfe1fffff
733 #define V4_STR_BIT 0x00000020
734 #define VLDR_VMOV_SAME 0x0040f000
736 #define T2_SUBS_PC_LR 0xf3de8f00
738 #define DATA_OP_SHIFT 21
739 #define SBIT_SHIFT 20
741 #define T2_OPCODE_MASK 0xfe1fffff
742 #define T2_DATA_OP_SHIFT 21
743 #define T2_SBIT_SHIFT 20
745 #define A_COND_MASK 0xf0000000
746 #define A_PUSH_POP_OP_MASK 0x0fff0000
748 /* Opcodes for pushing/poping registers to/from the stack. */
749 #define A1_OPCODE_PUSH 0x092d0000
750 #define A2_OPCODE_PUSH 0x052d0004
751 #define A2_OPCODE_POP 0x049d0004
753 /* Codes to distinguish the arithmetic instructions. */
764 #define OPCODE_CMP 10
765 #define OPCODE_CMN 11
766 #define OPCODE_ORR 12
767 #define OPCODE_MOV 13
768 #define OPCODE_BIC 14
769 #define OPCODE_MVN 15
771 #define T2_OPCODE_AND 0
772 #define T2_OPCODE_BIC 1
773 #define T2_OPCODE_ORR 2
774 #define T2_OPCODE_ORN 3
775 #define T2_OPCODE_EOR 4
776 #define T2_OPCODE_ADD 8
777 #define T2_OPCODE_ADC 10
778 #define T2_OPCODE_SBC 11
779 #define T2_OPCODE_SUB 13
780 #define T2_OPCODE_RSB 14
782 #define T_OPCODE_MUL 0x4340
783 #define T_OPCODE_TST 0x4200
784 #define T_OPCODE_CMN 0x42c0
785 #define T_OPCODE_NEG 0x4240
786 #define T_OPCODE_MVN 0x43c0
788 #define T_OPCODE_ADD_R3 0x1800
789 #define T_OPCODE_SUB_R3 0x1a00
790 #define T_OPCODE_ADD_HI 0x4400
791 #define T_OPCODE_ADD_ST 0xb000
792 #define T_OPCODE_SUB_ST 0xb080
793 #define T_OPCODE_ADD_SP 0xa800
794 #define T_OPCODE_ADD_PC 0xa000
795 #define T_OPCODE_ADD_I8 0x3000
796 #define T_OPCODE_SUB_I8 0x3800
797 #define T_OPCODE_ADD_I3 0x1c00
798 #define T_OPCODE_SUB_I3 0x1e00
800 #define T_OPCODE_ASR_R 0x4100
801 #define T_OPCODE_LSL_R 0x4080
802 #define T_OPCODE_LSR_R 0x40c0
803 #define T_OPCODE_ROR_R 0x41c0
804 #define T_OPCODE_ASR_I 0x1000
805 #define T_OPCODE_LSL_I 0x0000
806 #define T_OPCODE_LSR_I 0x0800
808 #define T_OPCODE_MOV_I8 0x2000
809 #define T_OPCODE_CMP_I8 0x2800
810 #define T_OPCODE_CMP_LR 0x4280
811 #define T_OPCODE_MOV_HR 0x4600
812 #define T_OPCODE_CMP_HR 0x4500
814 #define T_OPCODE_LDR_PC 0x4800
815 #define T_OPCODE_LDR_SP 0x9800
816 #define T_OPCODE_STR_SP 0x9000
817 #define T_OPCODE_LDR_IW 0x6800
818 #define T_OPCODE_STR_IW 0x6000
819 #define T_OPCODE_LDR_IH 0x8800
820 #define T_OPCODE_STR_IH 0x8000
821 #define T_OPCODE_LDR_IB 0x7800
822 #define T_OPCODE_STR_IB 0x7000
823 #define T_OPCODE_LDR_RW 0x5800
824 #define T_OPCODE_STR_RW 0x5000
825 #define T_OPCODE_LDR_RH 0x5a00
826 #define T_OPCODE_STR_RH 0x5200
827 #define T_OPCODE_LDR_RB 0x5c00
828 #define T_OPCODE_STR_RB 0x5400
830 #define T_OPCODE_PUSH 0xb400
831 #define T_OPCODE_POP 0xbc00
833 #define T_OPCODE_BRANCH 0xe000
835 #define THUMB_SIZE 2 /* Size of thumb instruction. */
836 #define THUMB_PP_PC_LR 0x0100
837 #define THUMB_LOAD_BIT 0x0800
838 #define THUMB2_LOAD_BIT 0x00100000
840 #define BAD_ARGS _("bad arguments to instruction")
841 #define BAD_SP _("r13 not allowed here")
842 #define BAD_PC _("r15 not allowed here")
843 #define BAD_COND _("instruction cannot be conditional")
844 #define BAD_OVERLAP _("registers may not be the same")
845 #define BAD_HIREG _("lo register required")
846 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
847 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
848 #define BAD_BRANCH _("branch must be last instruction in IT block")
849 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
850 #define BAD_NOT_IT _("instruction not allowed in IT block")
851 #define BAD_FPU _("selected FPU does not support instruction")
852 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
853 #define BAD_IT_COND _("incorrect condition in IT block")
854 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
855 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
856 #define BAD_PC_ADDRESSING \
857 _("cannot use register index with PC-relative addressing")
858 #define BAD_PC_WRITEBACK \
859 _("cannot use writeback with PC-relative addressing")
860 #define BAD_RANGE _("branch out of range")
861 #define BAD_FP16 _("selected processor does not support fp16 instruction")
862 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
863 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
865 static struct hash_control
* arm_ops_hsh
;
866 static struct hash_control
* arm_cond_hsh
;
867 static struct hash_control
* arm_shift_hsh
;
868 static struct hash_control
* arm_psr_hsh
;
869 static struct hash_control
* arm_v7m_psr_hsh
;
870 static struct hash_control
* arm_reg_hsh
;
871 static struct hash_control
* arm_reloc_hsh
;
872 static struct hash_control
* arm_barrier_opt_hsh
;
874 /* Stuff needed to resolve the label ambiguity
883 symbolS
* last_label_seen
;
884 static int label_is_thumb_function_name
= FALSE
;
886 /* Literal pool structure. Held on a per-section
887 and per-sub-section basis. */
889 #define MAX_LITERAL_POOL_SIZE 1024
890 typedef struct literal_pool
892 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
893 unsigned int next_free_entry
;
899 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
901 struct literal_pool
* next
;
902 unsigned int alignment
;
905 /* Pointer to a linked list of literal pools. */
906 literal_pool
* list_of_pools
= NULL
;
908 typedef enum asmfunc_states
911 WAITING_ASMFUNC_NAME
,
915 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
918 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
920 static struct current_it now_it
;
924 now_it_compatible (int cond
)
926 return (cond
& ~1) == (now_it
.cc
& ~1);
930 conditional_insn (void)
932 return inst
.cond
!= COND_ALWAYS
;
935 static int in_it_block (void);
937 static int handle_it_state (void);
939 static void force_automatic_it_block_close (void);
941 static void it_fsm_post_encode (void);
943 #define set_it_insn_type(type) \
946 inst.it_insn_type = type; \
947 if (handle_it_state () == FAIL) \
952 #define set_it_insn_type_nonvoid(type, failret) \
955 inst.it_insn_type = type; \
956 if (handle_it_state () == FAIL) \
961 #define set_it_insn_type_last() \
964 if (inst.cond == COND_ALWAYS) \
965 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
967 set_it_insn_type (INSIDE_IT_LAST_INSN); \
973 /* This array holds the chars that always start a comment. If the
974 pre-processor is disabled, these aren't very useful. */
975 char arm_comment_chars
[] = "@";
977 /* This array holds the chars that only start a comment at the beginning of
978 a line. If the line seems to have the form '# 123 filename'
979 .line and .file directives will appear in the pre-processed output. */
980 /* Note that input_file.c hand checks for '#' at the beginning of the
981 first line of the input file. This is because the compiler outputs
982 #NO_APP at the beginning of its output. */
983 /* Also note that comments like this one will always work. */
984 const char line_comment_chars
[] = "#";
986 char arm_line_separator_chars
[] = ";";
988 /* Chars that can be used to separate mant
989 from exp in floating point numbers. */
990 const char EXP_CHARS
[] = "eE";
992 /* Chars that mean this number is a floating point constant. */
996 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
998 /* Prefix characters that indicate the start of an immediate
1000 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1002 /* Separator character handling. */
1004 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1007 skip_past_char (char ** str
, char c
)
1009 /* PR gas/14987: Allow for whitespace before the expected character. */
1010 skip_whitespace (*str
);
1021 #define skip_past_comma(str) skip_past_char (str, ',')
1023 /* Arithmetic expressions (possibly involving symbols). */
1025 /* Return TRUE if anything in the expression is a bignum. */
1028 walk_no_bignums (symbolS
* sp
)
1030 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1033 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1035 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1036 || (symbol_get_value_expression (sp
)->X_op_symbol
1037 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1043 static bfd_boolean in_my_get_expression
= FALSE
;
1045 /* Third argument to my_get_expression. */
1046 #define GE_NO_PREFIX 0
1047 #define GE_IMM_PREFIX 1
1048 #define GE_OPT_PREFIX 2
1049 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1050 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1051 #define GE_OPT_PREFIX_BIG 3
1054 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1058 /* In unified syntax, all prefixes are optional. */
1060 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1063 switch (prefix_mode
)
1065 case GE_NO_PREFIX
: break;
1067 if (!is_immediate_prefix (**str
))
1069 inst
.error
= _("immediate expression requires a # prefix");
1075 case GE_OPT_PREFIX_BIG
:
1076 if (is_immediate_prefix (**str
))
1083 memset (ep
, 0, sizeof (expressionS
));
1085 save_in
= input_line_pointer
;
1086 input_line_pointer
= *str
;
1087 in_my_get_expression
= TRUE
;
1089 in_my_get_expression
= FALSE
;
1091 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1093 /* We found a bad or missing expression in md_operand(). */
1094 *str
= input_line_pointer
;
1095 input_line_pointer
= save_in
;
1096 if (inst
.error
== NULL
)
1097 inst
.error
= (ep
->X_op
== O_absent
1098 ? _("missing expression") :_("bad expression"));
1102 /* Get rid of any bignums now, so that we don't generate an error for which
1103 we can't establish a line number later on. Big numbers are never valid
1104 in instructions, which is where this routine is always called. */
1105 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1106 && (ep
->X_op
== O_big
1107 || (ep
->X_add_symbol
1108 && (walk_no_bignums (ep
->X_add_symbol
)
1110 && walk_no_bignums (ep
->X_op_symbol
))))))
1112 inst
.error
= _("invalid constant");
1113 *str
= input_line_pointer
;
1114 input_line_pointer
= save_in
;
1118 *str
= input_line_pointer
;
1119 input_line_pointer
= save_in
;
1123 /* Turn a string in input_line_pointer into a floating point constant
1124 of type TYPE, and store the appropriate bytes in *LITP. The number
1125 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1126 returned, or NULL on OK.
1128 Note that fp constants aren't represent in the normal way on the ARM.
1129 In big endian mode, things are as expected. However, in little endian
1130 mode fp constants are big-endian word-wise, and little-endian byte-wise
1131 within the words. For example, (double) 1.1 in big endian mode is
1132 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1133 the byte sequence 99 99 f1 3f 9a 99 99 99.
1135 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1138 md_atof (int type
, char * litP
, int * sizeP
)
1141 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1173 return _("Unrecognized or unsupported floating point constant");
1176 t
= atof_ieee (input_line_pointer
, type
, words
);
1178 input_line_pointer
= t
;
1179 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1181 if (target_big_endian
)
1183 for (i
= 0; i
< prec
; i
++)
1185 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1186 litP
+= sizeof (LITTLENUM_TYPE
);
1191 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1192 for (i
= prec
- 1; i
>= 0; i
--)
1194 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= sizeof (LITTLENUM_TYPE
);
1198 /* For a 4 byte float the order of elements in `words' is 1 0.
1199 For an 8 byte float the order is 1 0 3 2. */
1200 for (i
= 0; i
< prec
; i
+= 2)
1202 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1203 sizeof (LITTLENUM_TYPE
));
1204 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1205 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1206 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1213 /* We handle all bad expressions here, so that we can report the faulty
1214 instruction in the error message. */
1217 md_operand (expressionS
* exp
)
1219 if (in_my_get_expression
)
1220 exp
->X_op
= O_illegal
;
1223 /* Immediate values. */
1226 /* Generic immediate-value read function for use in directives.
1227 Accepts anything that 'expression' can fold to a constant.
1228 *val receives the number. */
1231 immediate_for_directive (int *val
)
1234 exp
.X_op
= O_illegal
;
1236 if (is_immediate_prefix (*input_line_pointer
))
1238 input_line_pointer
++;
1242 if (exp
.X_op
!= O_constant
)
1244 as_bad (_("expected #constant"));
1245 ignore_rest_of_line ();
1248 *val
= exp
.X_add_number
;
1253 /* Register parsing. */
1255 /* Generic register parser. CCP points to what should be the
1256 beginning of a register name. If it is indeed a valid register
1257 name, advance CCP over it and return the reg_entry structure;
1258 otherwise return NULL. Does not issue diagnostics. */
1260 static struct reg_entry
*
1261 arm_reg_parse_multi (char **ccp
)
1265 struct reg_entry
*reg
;
1267 skip_whitespace (start
);
1269 #ifdef REGISTER_PREFIX
1270 if (*start
!= REGISTER_PREFIX
)
1274 #ifdef OPTIONAL_REGISTER_PREFIX
1275 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1280 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1285 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1287 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1297 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1298 enum arm_reg_type type
)
1300 /* Alternative syntaxes are accepted for a few register classes. */
1307 /* Generic coprocessor register names are allowed for these. */
1308 if (reg
&& reg
->type
== REG_TYPE_CN
)
1313 /* For backward compatibility, a bare number is valid here. */
1315 unsigned long processor
= strtoul (start
, ccp
, 10);
1316 if (*ccp
!= start
&& processor
<= 15)
1321 case REG_TYPE_MMXWC
:
1322 /* WC includes WCG. ??? I'm not sure this is true for all
1323 instructions that take WC registers. */
1324 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1335 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1336 return value is the register number or FAIL. */
1339 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1345 /* Do not allow a scalar (reg+index) to parse as a register. */
1346 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1349 if (reg
&& reg
->type
== type
)
1352 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1359 /* Parse a Neon type specifier. *STR should point at the leading '.'
1360 character. Does no verification at this stage that the type fits the opcode
1367 Can all be legally parsed by this function.
1369 Fills in neon_type struct pointer with parsed information, and updates STR
1370 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1371 type, FAIL if not. */
1374 parse_neon_type (struct neon_type
*type
, char **str
)
1381 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1383 enum neon_el_type thistype
= NT_untyped
;
1384 unsigned thissize
= -1u;
1391 /* Just a size without an explicit type. */
1395 switch (TOLOWER (*ptr
))
1397 case 'i': thistype
= NT_integer
; break;
1398 case 'f': thistype
= NT_float
; break;
1399 case 'p': thistype
= NT_poly
; break;
1400 case 's': thistype
= NT_signed
; break;
1401 case 'u': thistype
= NT_unsigned
; break;
1403 thistype
= NT_float
;
1408 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1414 /* .f is an abbreviation for .f32. */
1415 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1420 thissize
= strtoul (ptr
, &ptr
, 10);
1422 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1425 as_bad (_("bad size %d in type specifier"), thissize
);
1433 type
->el
[type
->elems
].type
= thistype
;
1434 type
->el
[type
->elems
].size
= thissize
;
1439 /* Empty/missing type is not a successful parse. */
1440 if (type
->elems
== 0)
1448 /* Errors may be set multiple times during parsing or bit encoding
1449 (particularly in the Neon bits), but usually the earliest error which is set
1450 will be the most meaningful. Avoid overwriting it with later (cascading)
1451 errors by calling this function. */
1454 first_error (const char *err
)
1460 /* Parse a single type, e.g. ".s32", leading period included. */
1462 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1465 struct neon_type optype
;
1469 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1471 if (optype
.elems
== 1)
1472 *vectype
= optype
.el
[0];
1475 first_error (_("only one type should be specified for operand"));
1481 first_error (_("vector type expected"));
1493 /* Special meanings for indices (which have a range of 0-7), which will fit into
1496 #define NEON_ALL_LANES 15
1497 #define NEON_INTERLEAVE_LANES 14
1499 /* Parse either a register or a scalar, with an optional type. Return the
1500 register number, and optionally fill in the actual type of the register
1501 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1502 type/index information in *TYPEINFO. */
1505 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1506 enum arm_reg_type
*rtype
,
1507 struct neon_typed_alias
*typeinfo
)
1510 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1511 struct neon_typed_alias atype
;
1512 struct neon_type_el parsetype
;
1516 atype
.eltype
.type
= NT_invtype
;
1517 atype
.eltype
.size
= -1;
1519 /* Try alternate syntax for some types of register. Note these are mutually
1520 exclusive with the Neon syntax extensions. */
1523 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1531 /* Undo polymorphism when a set of register types may be accepted. */
1532 if ((type
== REG_TYPE_NDQ
1533 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1534 || (type
== REG_TYPE_VFSD
1535 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1536 || (type
== REG_TYPE_NSDQ
1537 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1538 || reg
->type
== REG_TYPE_NQ
))
1539 || (type
== REG_TYPE_NSD
1540 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1541 || (type
== REG_TYPE_MMXWC
1542 && (reg
->type
== REG_TYPE_MMXWCG
)))
1543 type
= (enum arm_reg_type
) reg
->type
;
1545 if (type
!= reg
->type
)
1551 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1553 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1555 first_error (_("can't redefine type for operand"));
1558 atype
.defined
|= NTA_HASTYPE
;
1559 atype
.eltype
= parsetype
;
1562 if (skip_past_char (&str
, '[') == SUCCESS
)
1564 if (type
!= REG_TYPE_VFD
1565 && !(type
== REG_TYPE_VFS
1566 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1568 first_error (_("only D registers may be indexed"));
1572 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1574 first_error (_("can't change index for operand"));
1578 atype
.defined
|= NTA_HASINDEX
;
1580 if (skip_past_char (&str
, ']') == SUCCESS
)
1581 atype
.index
= NEON_ALL_LANES
;
1586 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1588 if (exp
.X_op
!= O_constant
)
1590 first_error (_("constant expression required"));
1594 if (skip_past_char (&str
, ']') == FAIL
)
1597 atype
.index
= exp
.X_add_number
;
1612 /* Like arm_reg_parse, but allow allow the following extra features:
1613 - If RTYPE is non-zero, return the (possibly restricted) type of the
1614 register (e.g. Neon double or quad reg when either has been requested).
1615 - If this is a Neon vector type with additional type information, fill
1616 in the struct pointed to by VECTYPE (if non-NULL).
1617 This function will fault on encountering a scalar. */
1620 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1621 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1623 struct neon_typed_alias atype
;
1625 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1630 /* Do not allow regname(... to parse as a register. */
1634 /* Do not allow a scalar (reg+index) to parse as a register. */
1635 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1637 first_error (_("register operand expected, but got scalar"));
1642 *vectype
= atype
.eltype
;
1649 #define NEON_SCALAR_REG(X) ((X) >> 4)
1650 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1652 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1653 have enough information to be able to do a good job bounds-checking. So, we
1654 just do easy checks here, and do further checks later. */
1657 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1661 struct neon_typed_alias atype
;
1662 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1665 reg_type
= REG_TYPE_VFS
;
1667 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1669 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1672 if (atype
.index
== NEON_ALL_LANES
)
1674 first_error (_("scalar must have an index"));
1677 else if (atype
.index
>= 64 / elsize
)
1679 first_error (_("scalar index out of range"));
1684 *type
= atype
.eltype
;
1688 return reg
* 16 + atype
.index
;
1691 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1694 parse_reg_list (char ** strp
)
1696 char * str
= * strp
;
1700 /* We come back here if we get ranges concatenated by '+' or '|'. */
1703 skip_whitespace (str
);
1717 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1719 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1729 first_error (_("bad range in register list"));
1733 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1735 if (range
& (1 << i
))
1737 (_("Warning: duplicated register (r%d) in register list"),
1745 if (range
& (1 << reg
))
1746 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1748 else if (reg
<= cur_reg
)
1749 as_tsktsk (_("Warning: register range not in ascending order"));
1754 while (skip_past_comma (&str
) != FAIL
1755 || (in_range
= 1, *str
++ == '-'));
1758 if (skip_past_char (&str
, '}') == FAIL
)
1760 first_error (_("missing `}'"));
1768 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1771 if (exp
.X_op
== O_constant
)
1773 if (exp
.X_add_number
1774 != (exp
.X_add_number
& 0x0000ffff))
1776 inst
.error
= _("invalid register mask");
1780 if ((range
& exp
.X_add_number
) != 0)
1782 int regno
= range
& exp
.X_add_number
;
1785 regno
= (1 << regno
) - 1;
1787 (_("Warning: duplicated register (r%d) in register list"),
1791 range
|= exp
.X_add_number
;
1795 if (inst
.relocs
[0].type
!= 0)
1797 inst
.error
= _("expression too complex");
1801 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1802 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1803 inst
.relocs
[0].pc_rel
= 0;
1807 if (*str
== '|' || *str
== '+')
1813 while (another_range
);
1819 /* Types of registers in a list. */
1828 /* Parse a VFP register list. If the string is invalid return FAIL.
1829 Otherwise return the number of registers, and set PBASE to the first
1830 register. Parses registers of type ETYPE.
1831 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1832 - Q registers can be used to specify pairs of D registers
1833 - { } can be omitted from around a singleton register list
1834 FIXME: This is not implemented, as it would require backtracking in
1837 This could be done (the meaning isn't really ambiguous), but doesn't
1838 fit in well with the current parsing framework.
1839 - 32 D registers may be used (also true for VFPv3).
1840 FIXME: Types are ignored in these register lists, which is probably a
1844 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1849 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1853 unsigned long mask
= 0;
1856 if (skip_past_char (&str
, '{') == FAIL
)
1858 inst
.error
= _("expecting {");
1865 regtype
= REG_TYPE_VFS
;
1870 regtype
= REG_TYPE_VFD
;
1873 case REGLIST_NEON_D
:
1874 regtype
= REG_TYPE_NDQ
;
1878 if (etype
!= REGLIST_VFP_S
)
1880 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1885 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1888 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1895 base_reg
= max_regs
;
1899 int setmask
= 1, addregs
= 1;
1901 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1903 if (new_base
== FAIL
)
1905 first_error (_(reg_expected_msgs
[regtype
]));
1909 if (new_base
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 /* Note: a value of 2 * n is returned for the register Q<n>. */
1916 if (regtype
== REG_TYPE_NQ
)
1922 if (new_base
< base_reg
)
1923 base_reg
= new_base
;
1925 if (mask
& (setmask
<< new_base
))
1927 first_error (_("invalid register list"));
1931 if ((mask
>> new_base
) != 0 && ! warned
)
1933 as_tsktsk (_("register list not in ascending order"));
1937 mask
|= setmask
<< new_base
;
1940 if (*str
== '-') /* We have the start of a range expression */
1946 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1949 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1953 if (high_range
>= max_regs
)
1955 first_error (_("register out of range in list"));
1959 if (regtype
== REG_TYPE_NQ
)
1960 high_range
= high_range
+ 1;
1962 if (high_range
<= new_base
)
1964 inst
.error
= _("register range not in ascending order");
1968 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1970 if (mask
& (setmask
<< new_base
))
1972 inst
.error
= _("invalid register list");
1976 mask
|= setmask
<< new_base
;
1981 while (skip_past_comma (&str
) != FAIL
);
1985 /* Sanity check -- should have raised a parse error above. */
1986 if (count
== 0 || count
> max_regs
)
1991 /* Final test -- the registers must be consecutive. */
1993 for (i
= 0; i
< count
; i
++)
1995 if ((mask
& (1u << i
)) == 0)
1997 inst
.error
= _("non-contiguous register range");
2007 /* True if two alias types are the same. */
2010 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2018 if (a
->defined
!= b
->defined
)
2021 if ((a
->defined
& NTA_HASTYPE
) != 0
2022 && (a
->eltype
.type
!= b
->eltype
.type
2023 || a
->eltype
.size
!= b
->eltype
.size
))
2026 if ((a
->defined
& NTA_HASINDEX
) != 0
2027 && (a
->index
!= b
->index
))
2033 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2034 The base register is put in *PBASE.
2035 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2037 The register stride (minus one) is put in bit 4 of the return value.
2038 Bits [6:5] encode the list length (minus one).
2039 The type of the list elements is put in *ELTYPE, if non-NULL. */
2041 #define NEON_LANE(X) ((X) & 0xf)
2042 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2043 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2046 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2047 struct neon_type_el
*eltype
)
2054 int leading_brace
= 0;
2055 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2056 const char *const incr_error
= _("register stride must be 1 or 2");
2057 const char *const type_error
= _("mismatched element/structure types in list");
2058 struct neon_typed_alias firsttype
;
2059 firsttype
.defined
= 0;
2060 firsttype
.eltype
.type
= NT_invtype
;
2061 firsttype
.eltype
.size
= -1;
2062 firsttype
.index
= -1;
2064 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2069 struct neon_typed_alias atype
;
2070 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2074 first_error (_(reg_expected_msgs
[rtype
]));
2081 if (rtype
== REG_TYPE_NQ
)
2087 else if (reg_incr
== -1)
2089 reg_incr
= getreg
- base_reg
;
2090 if (reg_incr
< 1 || reg_incr
> 2)
2092 first_error (_(incr_error
));
2096 else if (getreg
!= base_reg
+ reg_incr
* count
)
2098 first_error (_(incr_error
));
2102 if (! neon_alias_types_same (&atype
, &firsttype
))
2104 first_error (_(type_error
));
2108 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2112 struct neon_typed_alias htype
;
2113 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2115 lane
= NEON_INTERLEAVE_LANES
;
2116 else if (lane
!= NEON_INTERLEAVE_LANES
)
2118 first_error (_(type_error
));
2123 else if (reg_incr
!= 1)
2125 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2129 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2132 first_error (_(reg_expected_msgs
[rtype
]));
2135 if (! neon_alias_types_same (&htype
, &firsttype
))
2137 first_error (_(type_error
));
2140 count
+= hireg
+ dregs
- getreg
;
2144 /* If we're using Q registers, we can't use [] or [n] syntax. */
2145 if (rtype
== REG_TYPE_NQ
)
2151 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2155 else if (lane
!= atype
.index
)
2157 first_error (_(type_error
));
2161 else if (lane
== -1)
2162 lane
= NEON_INTERLEAVE_LANES
;
2163 else if (lane
!= NEON_INTERLEAVE_LANES
)
2165 first_error (_(type_error
));
2170 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2172 /* No lane set by [x]. We must be interleaving structures. */
2174 lane
= NEON_INTERLEAVE_LANES
;
2177 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2178 || (count
> 1 && reg_incr
== -1))
2180 first_error (_("error parsing element/structure list"));
2184 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2186 first_error (_("expected }"));
2194 *eltype
= firsttype
.eltype
;
2199 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2202 /* Parse an explicit relocation suffix on an expression. This is
2203 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2204 arm_reloc_hsh contains no entries, so this function can only
2205 succeed if there is no () after the word. Returns -1 on error,
2206 BFD_RELOC_UNUSED if there wasn't any suffix. */
2209 parse_reloc (char **str
)
2211 struct reloc_entry
*r
;
2215 return BFD_RELOC_UNUSED
;
2220 while (*q
&& *q
!= ')' && *q
!= ',')
2225 if ((r
= (struct reloc_entry
*)
2226 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2233 /* Directives: register aliases. */
2235 static struct reg_entry
*
2236 insert_reg_alias (char *str
, unsigned number
, int type
)
2238 struct reg_entry
*new_reg
;
2241 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2243 if (new_reg
->builtin
)
2244 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2246 /* Only warn about a redefinition if it's not defined as the
2248 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2249 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2254 name
= xstrdup (str
);
2255 new_reg
= XNEW (struct reg_entry
);
2257 new_reg
->name
= name
;
2258 new_reg
->number
= number
;
2259 new_reg
->type
= type
;
2260 new_reg
->builtin
= FALSE
;
2261 new_reg
->neon
= NULL
;
2263 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2270 insert_neon_reg_alias (char *str
, int number
, int type
,
2271 struct neon_typed_alias
*atype
)
2273 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2277 first_error (_("attempt to redefine typed alias"));
2283 reg
->neon
= XNEW (struct neon_typed_alias
);
2284 *reg
->neon
= *atype
;
2288 /* Look for the .req directive. This is of the form:
2290 new_register_name .req existing_register_name
2292 If we find one, or if it looks sufficiently like one that we want to
2293 handle any error here, return TRUE. Otherwise return FALSE. */
2296 create_register_alias (char * newname
, char *p
)
2298 struct reg_entry
*old
;
2299 char *oldname
, *nbuf
;
2302 /* The input scrubber ensures that whitespace after the mnemonic is
2303 collapsed to single spaces. */
2305 if (strncmp (oldname
, " .req ", 6) != 0)
2309 if (*oldname
== '\0')
2312 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2315 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2319 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2320 the desired alias name, and p points to its end. If not, then
2321 the desired alias name is in the global original_case_string. */
2322 #ifdef TC_CASE_SENSITIVE
2325 newname
= original_case_string
;
2326 nlen
= strlen (newname
);
2329 nbuf
= xmemdup0 (newname
, nlen
);
2331 /* Create aliases under the new name as stated; an all-lowercase
2332 version of the new name; and an all-uppercase version of the new
2334 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2336 for (p
= nbuf
; *p
; p
++)
2339 if (strncmp (nbuf
, newname
, nlen
))
2341 /* If this attempt to create an additional alias fails, do not bother
2342 trying to create the all-lower case alias. We will fail and issue
2343 a second, duplicate error message. This situation arises when the
2344 programmer does something like:
2347 The second .req creates the "Foo" alias but then fails to create
2348 the artificial FOO alias because it has already been created by the
2350 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2357 for (p
= nbuf
; *p
; p
++)
2360 if (strncmp (nbuf
, newname
, nlen
))
2361 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2368 /* Create a Neon typed/indexed register alias using directives, e.g.:
2373 These typed registers can be used instead of the types specified after the
2374 Neon mnemonic, so long as all operands given have types. Types can also be
2375 specified directly, e.g.:
2376 vadd d0.s32, d1.s32, d2.s32 */
2379 create_neon_reg_alias (char *newname
, char *p
)
2381 enum arm_reg_type basetype
;
2382 struct reg_entry
*basereg
;
2383 struct reg_entry mybasereg
;
2384 struct neon_type ntype
;
2385 struct neon_typed_alias typeinfo
;
2386 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2389 typeinfo
.defined
= 0;
2390 typeinfo
.eltype
.type
= NT_invtype
;
2391 typeinfo
.eltype
.size
= -1;
2392 typeinfo
.index
= -1;
2396 if (strncmp (p
, " .dn ", 5) == 0)
2397 basetype
= REG_TYPE_VFD
;
2398 else if (strncmp (p
, " .qn ", 5) == 0)
2399 basetype
= REG_TYPE_NQ
;
2408 basereg
= arm_reg_parse_multi (&p
);
2410 if (basereg
&& basereg
->type
!= basetype
)
2412 as_bad (_("bad type for register"));
2416 if (basereg
== NULL
)
2419 /* Try parsing as an integer. */
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2421 if (exp
.X_op
!= O_constant
)
2423 as_bad (_("expression must be constant"));
2426 basereg
= &mybasereg
;
2427 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2433 typeinfo
= *basereg
->neon
;
2435 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2437 /* We got a type. */
2438 if (typeinfo
.defined
& NTA_HASTYPE
)
2440 as_bad (_("can't redefine the type of a register alias"));
2444 typeinfo
.defined
|= NTA_HASTYPE
;
2445 if (ntype
.elems
!= 1)
2447 as_bad (_("you must specify a single type only"));
2450 typeinfo
.eltype
= ntype
.el
[0];
2453 if (skip_past_char (&p
, '[') == SUCCESS
)
2456 /* We got a scalar index. */
2458 if (typeinfo
.defined
& NTA_HASINDEX
)
2460 as_bad (_("can't redefine the index of a scalar alias"));
2464 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2466 if (exp
.X_op
!= O_constant
)
2468 as_bad (_("scalar index must be constant"));
2472 typeinfo
.defined
|= NTA_HASINDEX
;
2473 typeinfo
.index
= exp
.X_add_number
;
2475 if (skip_past_char (&p
, ']') == FAIL
)
2477 as_bad (_("expecting ]"));
2482 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2483 the desired alias name, and p points to its end. If not, then
2484 the desired alias name is in the global original_case_string. */
2485 #ifdef TC_CASE_SENSITIVE
2486 namelen
= nameend
- newname
;
2488 newname
= original_case_string
;
2489 namelen
= strlen (newname
);
2492 namebuf
= xmemdup0 (newname
, namelen
);
2494 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2495 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2497 /* Insert name in all uppercase. */
2498 for (p
= namebuf
; *p
; p
++)
2501 if (strncmp (namebuf
, newname
, namelen
))
2502 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2503 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2505 /* Insert name in all lowercase. */
2506 for (p
= namebuf
; *p
; p
++)
2509 if (strncmp (namebuf
, newname
, namelen
))
2510 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2511 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2517 /* Should never be called, as .req goes between the alias and the
2518 register name, not at the beginning of the line. */
2521 s_req (int a ATTRIBUTE_UNUSED
)
2523 as_bad (_("invalid syntax for .req directive"));
2527 s_dn (int a ATTRIBUTE_UNUSED
)
2529 as_bad (_("invalid syntax for .dn directive"));
2533 s_qn (int a ATTRIBUTE_UNUSED
)
2535 as_bad (_("invalid syntax for .qn directive"));
2538 /* The .unreq directive deletes an alias which was previously defined
2539 by .req. For example:
2545 s_unreq (int a ATTRIBUTE_UNUSED
)
2550 name
= input_line_pointer
;
2552 while (*input_line_pointer
!= 0
2553 && *input_line_pointer
!= ' '
2554 && *input_line_pointer
!= '\n')
2555 ++input_line_pointer
;
2557 saved_char
= *input_line_pointer
;
2558 *input_line_pointer
= 0;
2561 as_bad (_("invalid syntax for .unreq directive"));
2564 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2568 as_bad (_("unknown register alias '%s'"), name
);
2569 else if (reg
->builtin
)
2570 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2577 hash_delete (arm_reg_hsh
, name
, FALSE
);
2578 free ((char *) reg
->name
);
2583 /* Also locate the all upper case and all lower case versions.
2584 Do not complain if we cannot find one or the other as it
2585 was probably deleted above. */
2587 nbuf
= strdup (name
);
2588 for (p
= nbuf
; *p
; p
++)
2590 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2593 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2594 free ((char *) reg
->name
);
2600 for (p
= nbuf
; *p
; p
++)
2602 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2605 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2606 free ((char *) reg
->name
);
2616 *input_line_pointer
= saved_char
;
2617 demand_empty_rest_of_line ();
2620 /* Directives: Instruction set selection. */
2623 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2624 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2625 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2626 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2628 /* Create a new mapping symbol for the transition to STATE. */
2631 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2634 const char * symname
;
2641 type
= BSF_NO_FLAGS
;
2645 type
= BSF_NO_FLAGS
;
2649 type
= BSF_NO_FLAGS
;
2655 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2656 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2661 THUMB_SET_FUNC (symbolP
, 0);
2662 ARM_SET_THUMB (symbolP
, 0);
2663 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2667 THUMB_SET_FUNC (symbolP
, 1);
2668 ARM_SET_THUMB (symbolP
, 1);
2669 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2677 /* Save the mapping symbols for future reference. Also check that
2678 we do not place two mapping symbols at the same offset within a
2679 frag. We'll handle overlap between frags in
2680 check_mapping_symbols.
2682 If .fill or other data filling directive generates zero sized data,
2683 the mapping symbol for the following code will have the same value
2684 as the one generated for the data filling directive. In this case,
2685 we replace the old symbol with the new one at the same address. */
2688 if (frag
->tc_frag_data
.first_map
!= NULL
)
2690 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2691 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2693 frag
->tc_frag_data
.first_map
= symbolP
;
2695 if (frag
->tc_frag_data
.last_map
!= NULL
)
2697 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2698 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2699 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2701 frag
->tc_frag_data
.last_map
= symbolP
;
2704 /* We must sometimes convert a region marked as code to data during
2705 code alignment, if an odd number of bytes have to be padded. The
2706 code mapping symbol is pushed to an aligned address. */
2709 insert_data_mapping_symbol (enum mstate state
,
2710 valueT value
, fragS
*frag
, offsetT bytes
)
2712 /* If there was already a mapping symbol, remove it. */
2713 if (frag
->tc_frag_data
.last_map
!= NULL
2714 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2716 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2720 know (frag
->tc_frag_data
.first_map
== symp
);
2721 frag
->tc_frag_data
.first_map
= NULL
;
2723 frag
->tc_frag_data
.last_map
= NULL
;
2724 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2727 make_mapping_symbol (MAP_DATA
, value
, frag
);
2728 make_mapping_symbol (state
, value
+ bytes
, frag
);
2731 static void mapping_state_2 (enum mstate state
, int max_chars
);
2733 /* Set the mapping state to STATE. Only call this when about to
2734 emit some STATE bytes to the file. */
2736 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2738 mapping_state (enum mstate state
)
2740 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2742 if (mapstate
== state
)
2743 /* The mapping symbol has already been emitted.
2744 There is nothing else to do. */
2747 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2749 All ARM instructions require 4-byte alignment.
2750 (Almost) all Thumb instructions require 2-byte alignment.
2752 When emitting instructions into any section, mark the section
2755 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2756 but themselves require 2-byte alignment; this applies to some
2757 PC- relative forms. However, these cases will involve implicit
2758 literal pool generation or an explicit .align >=2, both of
2759 which will cause the section to me marked with sufficient
2760 alignment. Thus, we don't handle those cases here. */
2761 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2763 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2764 /* This case will be evaluated later. */
2767 mapping_state_2 (state
, 0);
2770 /* Same as mapping_state, but MAX_CHARS bytes have already been
2771 allocated. Put the mapping symbol that far back. */
2774 mapping_state_2 (enum mstate state
, int max_chars
)
2776 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2778 if (!SEG_NORMAL (now_seg
))
2781 if (mapstate
== state
)
2782 /* The mapping symbol has already been emitted.
2783 There is nothing else to do. */
2786 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2787 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2789 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2790 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2793 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2796 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2797 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2801 #define mapping_state(x) ((void)0)
2802 #define mapping_state_2(x, y) ((void)0)
2805 /* Find the real, Thumb encoded start of a Thumb function. */
2809 find_real_start (symbolS
* symbolP
)
2812 const char * name
= S_GET_NAME (symbolP
);
2813 symbolS
* new_target
;
2815 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2816 #define STUB_NAME ".real_start_of"
2821 /* The compiler may generate BL instructions to local labels because
2822 it needs to perform a branch to a far away location. These labels
2823 do not have a corresponding ".real_start_of" label. We check
2824 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2825 the ".real_start_of" convention for nonlocal branches. */
2826 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2829 real_start
= concat (STUB_NAME
, name
, NULL
);
2830 new_target
= symbol_find (real_start
);
2833 if (new_target
== NULL
)
2835 as_warn (_("Failed to find real start of function: %s\n"), name
);
2836 new_target
= symbolP
;
2844 opcode_select (int width
)
2851 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2852 as_bad (_("selected processor does not support THUMB opcodes"));
2855 /* No need to force the alignment, since we will have been
2856 coming from ARM mode, which is word-aligned. */
2857 record_alignment (now_seg
, 1);
2864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2865 as_bad (_("selected processor does not support ARM opcodes"));
2870 frag_align (2, 0, 0);
2872 record_alignment (now_seg
, 1);
2877 as_bad (_("invalid instruction size selected (%d)"), width
);
2882 s_arm (int ignore ATTRIBUTE_UNUSED
)
2885 demand_empty_rest_of_line ();
2889 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2892 demand_empty_rest_of_line ();
2896 s_code (int unused ATTRIBUTE_UNUSED
)
2900 temp
= get_absolute_expression ();
2905 opcode_select (temp
);
2909 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2914 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2916 /* If we are not already in thumb mode go into it, EVEN if
2917 the target processor does not support thumb instructions.
2918 This is used by gcc/config/arm/lib1funcs.asm for example
2919 to compile interworking support functions even if the
2920 target processor should not support interworking. */
2924 record_alignment (now_seg
, 1);
2927 demand_empty_rest_of_line ();
2931 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2935 /* The following label is the name/address of the start of a Thumb function.
2936 We need to know this for the interworking support. */
2937 label_is_thumb_function_name
= TRUE
;
2940 /* Perform a .set directive, but also mark the alias as
2941 being a thumb function. */
2944 s_thumb_set (int equiv
)
2946 /* XXX the following is a duplicate of the code for s_set() in read.c
2947 We cannot just call that code as we need to get at the symbol that
2954 /* Especial apologies for the random logic:
2955 This just grew, and could be parsed much more simply!
2957 delim
= get_symbol_name (& name
);
2958 end_name
= input_line_pointer
;
2959 (void) restore_line_pointer (delim
);
2961 if (*input_line_pointer
!= ',')
2964 as_bad (_("expected comma after name \"%s\""), name
);
2966 ignore_rest_of_line ();
2970 input_line_pointer
++;
2973 if (name
[0] == '.' && name
[1] == '\0')
2975 /* XXX - this should not happen to .thumb_set. */
2979 if ((symbolP
= symbol_find (name
)) == NULL
2980 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2983 /* When doing symbol listings, play games with dummy fragments living
2984 outside the normal fragment chain to record the file and line info
2986 if (listing
& LISTING_SYMBOLS
)
2988 extern struct list_info_struct
* listing_tail
;
2989 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2991 memset (dummy_frag
, 0, sizeof (fragS
));
2992 dummy_frag
->fr_type
= rs_fill
;
2993 dummy_frag
->line
= listing_tail
;
2994 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2995 dummy_frag
->fr_symbol
= symbolP
;
2999 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3002 /* "set" symbols are local unless otherwise specified. */
3003 SF_SET_LOCAL (symbolP
);
3004 #endif /* OBJ_COFF */
3005 } /* Make a new symbol. */
3007 symbol_table_insert (symbolP
);
3012 && S_IS_DEFINED (symbolP
)
3013 && S_GET_SEGMENT (symbolP
) != reg_section
)
3014 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3016 pseudo_set (symbolP
);
3018 demand_empty_rest_of_line ();
3020 /* XXX Now we come to the Thumb specific bit of code. */
3022 THUMB_SET_FUNC (symbolP
, 1);
3023 ARM_SET_THUMB (symbolP
, 1);
3024 #if defined OBJ_ELF || defined OBJ_COFF
3025 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3029 /* Directives: Mode selection. */
3031 /* .syntax [unified|divided] - choose the new unified syntax
3032 (same for Arm and Thumb encoding, modulo slight differences in what
3033 can be represented) or the old divergent syntax for each mode. */
3035 s_syntax (int unused ATTRIBUTE_UNUSED
)
3039 delim
= get_symbol_name (& name
);
3041 if (!strcasecmp (name
, "unified"))
3042 unified_syntax
= TRUE
;
3043 else if (!strcasecmp (name
, "divided"))
3044 unified_syntax
= FALSE
;
3047 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3050 (void) restore_line_pointer (delim
);
3051 demand_empty_rest_of_line ();
3054 /* Directives: sectioning and alignment. */
3057 s_bss (int ignore ATTRIBUTE_UNUSED
)
3059 /* We don't support putting frags in the BSS segment, we fake it by
3060 marking in_bss, then looking at s_skip for clues. */
3061 subseg_set (bss_section
, 0);
3062 demand_empty_rest_of_line ();
3064 #ifdef md_elf_section_change_hook
3065 md_elf_section_change_hook ();
3070 s_even (int ignore ATTRIBUTE_UNUSED
)
3072 /* Never make frag if expect extra pass. */
3074 frag_align (1, 0, 0);
3076 record_alignment (now_seg
, 1);
3078 demand_empty_rest_of_line ();
3081 /* Directives: CodeComposer Studio. */
3083 /* .ref (for CodeComposer Studio syntax only). */
3085 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3087 if (codecomposer_syntax
)
3088 ignore_rest_of_line ();
3090 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3093 /* If name is not NULL, then it is used for marking the beginning of a
3094 function, whereas if it is NULL then it means the function end. */
3096 asmfunc_debug (const char * name
)
3098 static const char * last_name
= NULL
;
3102 gas_assert (last_name
== NULL
);
3105 if (debug_type
== DEBUG_STABS
)
3106 stabs_generate_asm_func (name
, name
);
3110 gas_assert (last_name
!= NULL
);
3112 if (debug_type
== DEBUG_STABS
)
3113 stabs_generate_asm_endfunc (last_name
, last_name
);
3120 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3122 if (codecomposer_syntax
)
3124 switch (asmfunc_state
)
3126 case OUTSIDE_ASMFUNC
:
3127 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3130 case WAITING_ASMFUNC_NAME
:
3131 as_bad (_(".asmfunc repeated."));
3134 case WAITING_ENDASMFUNC
:
3135 as_bad (_(".asmfunc without function."));
3138 demand_empty_rest_of_line ();
3141 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3145 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3147 if (codecomposer_syntax
)
3149 switch (asmfunc_state
)
3151 case OUTSIDE_ASMFUNC
:
3152 as_bad (_(".endasmfunc without a .asmfunc."));
3155 case WAITING_ASMFUNC_NAME
:
3156 as_bad (_(".endasmfunc without function."));
3159 case WAITING_ENDASMFUNC
:
3160 asmfunc_state
= OUTSIDE_ASMFUNC
;
3161 asmfunc_debug (NULL
);
3164 demand_empty_rest_of_line ();
3167 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3171 s_ccs_def (int name
)
3173 if (codecomposer_syntax
)
3176 as_bad (_(".def pseudo-op only available with -mccs flag."));
3179 /* Directives: Literal pools. */
3181 static literal_pool
*
3182 find_literal_pool (void)
3184 literal_pool
* pool
;
3186 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3188 if (pool
->section
== now_seg
3189 && pool
->sub_section
== now_subseg
)
3196 static literal_pool
*
3197 find_or_make_literal_pool (void)
3199 /* Next literal pool ID number. */
3200 static unsigned int latest_pool_num
= 1;
3201 literal_pool
* pool
;
3203 pool
= find_literal_pool ();
3207 /* Create a new pool. */
3208 pool
= XNEW (literal_pool
);
3212 pool
->next_free_entry
= 0;
3213 pool
->section
= now_seg
;
3214 pool
->sub_section
= now_subseg
;
3215 pool
->next
= list_of_pools
;
3216 pool
->symbol
= NULL
;
3217 pool
->alignment
= 2;
3219 /* Add it to the list. */
3220 list_of_pools
= pool
;
3223 /* New pools, and emptied pools, will have a NULL symbol. */
3224 if (pool
->symbol
== NULL
)
3226 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3227 (valueT
) 0, &zero_address_frag
);
3228 pool
->id
= latest_pool_num
++;
3235 /* Add the literal in the global 'inst'
3236 structure to the relevant literal pool. */
3239 add_to_lit_pool (unsigned int nbytes
)
3241 #define PADDING_SLOT 0x1
3242 #define LIT_ENTRY_SIZE_MASK 0xFF
3243 literal_pool
* pool
;
3244 unsigned int entry
, pool_size
= 0;
3245 bfd_boolean padding_slot_p
= FALSE
;
3251 imm1
= inst
.operands
[1].imm
;
3252 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3253 : inst
.relocs
[0].exp
.X_unsigned
? 0
3254 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3255 if (target_big_endian
)
3258 imm2
= inst
.operands
[1].imm
;
3262 pool
= find_or_make_literal_pool ();
3264 /* Check if this literal value is already in the pool. */
3265 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3269 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3270 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3271 && (pool
->literals
[entry
].X_add_number
3272 == inst
.relocs
[0].exp
.X_add_number
)
3273 && (pool
->literals
[entry
].X_md
== nbytes
)
3274 && (pool
->literals
[entry
].X_unsigned
3275 == inst
.relocs
[0].exp
.X_unsigned
))
3278 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3279 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3280 && (pool
->literals
[entry
].X_add_number
3281 == inst
.relocs
[0].exp
.X_add_number
)
3282 && (pool
->literals
[entry
].X_add_symbol
3283 == inst
.relocs
[0].exp
.X_add_symbol
)
3284 && (pool
->literals
[entry
].X_op_symbol
3285 == inst
.relocs
[0].exp
.X_op_symbol
)
3286 && (pool
->literals
[entry
].X_md
== nbytes
))
3289 else if ((nbytes
== 8)
3290 && !(pool_size
& 0x7)
3291 && ((entry
+ 1) != pool
->next_free_entry
)
3292 && (pool
->literals
[entry
].X_op
== O_constant
)
3293 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3294 && (pool
->literals
[entry
].X_unsigned
3295 == inst
.relocs
[0].exp
.X_unsigned
)
3296 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3297 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3298 && (pool
->literals
[entry
+ 1].X_unsigned
3299 == inst
.relocs
[0].exp
.X_unsigned
))
3302 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3303 if (padding_slot_p
&& (nbytes
== 4))
3309 /* Do we need to create a new entry? */
3310 if (entry
== pool
->next_free_entry
)
3312 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3314 inst
.error
= _("literal pool overflow");
3320 /* For 8-byte entries, we align to an 8-byte boundary,
3321 and split it into two 4-byte entries, because on 32-bit
3322 host, 8-byte constants are treated as big num, thus
3323 saved in "generic_bignum" which will be overwritten
3324 by later assignments.
3326 We also need to make sure there is enough space for
3329 We also check to make sure the literal operand is a
3331 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3332 || inst
.relocs
[0].exp
.X_op
== O_big
))
3334 inst
.error
= _("invalid type for literal pool");
3337 else if (pool_size
& 0x7)
3339 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3341 inst
.error
= _("literal pool overflow");
3345 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3346 pool
->literals
[entry
].X_op
= O_constant
;
3347 pool
->literals
[entry
].X_add_number
= 0;
3348 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3349 pool
->next_free_entry
+= 1;
3352 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3354 inst
.error
= _("literal pool overflow");
3358 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3359 pool
->literals
[entry
].X_op
= O_constant
;
3360 pool
->literals
[entry
].X_add_number
= imm1
;
3361 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3362 pool
->literals
[entry
++].X_md
= 4;
3363 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3364 pool
->literals
[entry
].X_op
= O_constant
;
3365 pool
->literals
[entry
].X_add_number
= imm2
;
3366 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3367 pool
->literals
[entry
].X_md
= 4;
3368 pool
->alignment
= 3;
3369 pool
->next_free_entry
+= 1;
3373 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3374 pool
->literals
[entry
].X_md
= 4;
3378 /* PR ld/12974: Record the location of the first source line to reference
3379 this entry in the literal pool. If it turns out during linking that the
3380 symbol does not exist we will be able to give an accurate line number for
3381 the (first use of the) missing reference. */
3382 if (debug_type
== DEBUG_DWARF2
)
3383 dwarf2_where (pool
->locs
+ entry
);
3385 pool
->next_free_entry
+= 1;
3387 else if (padding_slot_p
)
3389 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3390 pool
->literals
[entry
].X_md
= nbytes
;
3393 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3394 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3395 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3401 tc_start_label_without_colon (void)
3403 bfd_boolean ret
= TRUE
;
3405 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3407 const char *label
= input_line_pointer
;
3409 while (!is_end_of_line
[(int) label
[-1]])
3414 as_bad (_("Invalid label '%s'"), label
);
3418 asmfunc_debug (label
);
3420 asmfunc_state
= WAITING_ENDASMFUNC
;
3426 /* Can't use symbol_new here, so have to create a symbol and then at
3427 a later date assign it a value. That's what these functions do. */
3430 symbol_locate (symbolS
* symbolP
,
3431 const char * name
, /* It is copied, the caller can modify. */
3432 segT segment
, /* Segment identifier (SEG_<something>). */
3433 valueT valu
, /* Symbol value. */
3434 fragS
* frag
) /* Associated fragment. */
3437 char * preserved_copy_of_name
;
3439 name_length
= strlen (name
) + 1; /* +1 for \0. */
3440 obstack_grow (¬es
, name
, name_length
);
3441 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3443 #ifdef tc_canonicalize_symbol_name
3444 preserved_copy_of_name
=
3445 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3448 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3450 S_SET_SEGMENT (symbolP
, segment
);
3451 S_SET_VALUE (symbolP
, valu
);
3452 symbol_clear_list_pointers (symbolP
);
3454 symbol_set_frag (symbolP
, frag
);
3456 /* Link to end of symbol chain. */
3458 extern int symbol_table_frozen
;
3460 if (symbol_table_frozen
)
3464 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3466 obj_symbol_new_hook (symbolP
);
3468 #ifdef tc_symbol_new_hook
3469 tc_symbol_new_hook (symbolP
);
3473 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3474 #endif /* DEBUG_SYMS */
3478 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3481 literal_pool
* pool
;
3484 pool
= find_literal_pool ();
3486 || pool
->symbol
== NULL
3487 || pool
->next_free_entry
== 0)
3490 /* Align pool as you have word accesses.
3491 Only make a frag if we have to. */
3493 frag_align (pool
->alignment
, 0, 0);
3495 record_alignment (now_seg
, 2);
3498 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3499 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3501 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3503 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3504 (valueT
) frag_now_fix (), frag_now
);
3505 symbol_table_insert (pool
->symbol
);
3507 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3509 #if defined OBJ_COFF || defined OBJ_ELF
3510 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3513 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3516 if (debug_type
== DEBUG_DWARF2
)
3517 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3519 /* First output the expression in the instruction to the pool. */
3520 emit_expr (&(pool
->literals
[entry
]),
3521 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3524 /* Mark the pool as empty. */
3525 pool
->next_free_entry
= 0;
3526 pool
->symbol
= NULL
;
3530 /* Forward declarations for functions below, in the MD interface
3532 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3533 static valueT
create_unwind_entry (int);
3534 static void start_unwind_section (const segT
, int);
3535 static void add_unwind_opcode (valueT
, int);
3536 static void flush_pending_unwind (void);
3538 /* Directives: Data. */
3541 s_arm_elf_cons (int nbytes
)
3545 #ifdef md_flush_pending_output
3546 md_flush_pending_output ();
3549 if (is_it_end_of_statement ())
3551 demand_empty_rest_of_line ();
3555 #ifdef md_cons_align
3556 md_cons_align (nbytes
);
3559 mapping_state (MAP_DATA
);
3563 char *base
= input_line_pointer
;
3567 if (exp
.X_op
!= O_symbol
)
3568 emit_expr (&exp
, (unsigned int) nbytes
);
3571 char *before_reloc
= input_line_pointer
;
3572 reloc
= parse_reloc (&input_line_pointer
);
3575 as_bad (_("unrecognized relocation suffix"));
3576 ignore_rest_of_line ();
3579 else if (reloc
== BFD_RELOC_UNUSED
)
3580 emit_expr (&exp
, (unsigned int) nbytes
);
3583 reloc_howto_type
*howto
= (reloc_howto_type
*)
3584 bfd_reloc_type_lookup (stdoutput
,
3585 (bfd_reloc_code_real_type
) reloc
);
3586 int size
= bfd_get_reloc_size (howto
);
3588 if (reloc
== BFD_RELOC_ARM_PLT32
)
3590 as_bad (_("(plt) is only valid on branch targets"));
3591 reloc
= BFD_RELOC_UNUSED
;
3596 as_bad (ngettext ("%s relocations do not fit in %d byte",
3597 "%s relocations do not fit in %d bytes",
3599 howto
->name
, nbytes
);
3602 /* We've parsed an expression stopping at O_symbol.
3603 But there may be more expression left now that we
3604 have parsed the relocation marker. Parse it again.
3605 XXX Surely there is a cleaner way to do this. */
3606 char *p
= input_line_pointer
;
3608 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3610 memcpy (save_buf
, base
, input_line_pointer
- base
);
3611 memmove (base
+ (input_line_pointer
- before_reloc
),
3612 base
, before_reloc
- base
);
3614 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3616 memcpy (base
, save_buf
, p
- base
);
3618 offset
= nbytes
- size
;
3619 p
= frag_more (nbytes
);
3620 memset (p
, 0, nbytes
);
3621 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3622 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3628 while (*input_line_pointer
++ == ',');
3630 /* Put terminator back into stream. */
3631 input_line_pointer
--;
3632 demand_empty_rest_of_line ();
3635 /* Emit an expression containing a 32-bit thumb instruction.
3636 Implementation based on put_thumb32_insn. */
3639 emit_thumb32_expr (expressionS
* exp
)
3641 expressionS exp_high
= *exp
;
3643 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3644 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3645 exp
->X_add_number
&= 0xffff;
3646 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3649 /* Guess the instruction size based on the opcode. */
3652 thumb_insn_size (int opcode
)
3654 if ((unsigned int) opcode
< 0xe800u
)
3656 else if ((unsigned int) opcode
>= 0xe8000000u
)
3663 emit_insn (expressionS
*exp
, int nbytes
)
3667 if (exp
->X_op
== O_constant
)
3672 size
= thumb_insn_size (exp
->X_add_number
);
3676 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3678 as_bad (_(".inst.n operand too big. "\
3679 "Use .inst.w instead"));
3684 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3685 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3687 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3689 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3690 emit_thumb32_expr (exp
);
3692 emit_expr (exp
, (unsigned int) size
);
3694 it_fsm_post_encode ();
3698 as_bad (_("cannot determine Thumb instruction size. " \
3699 "Use .inst.n/.inst.w instead"));
3702 as_bad (_("constant expression required"));
3707 /* Like s_arm_elf_cons but do not use md_cons_align and
3708 set the mapping state to MAP_ARM/MAP_THUMB. */
3711 s_arm_elf_inst (int nbytes
)
3713 if (is_it_end_of_statement ())
3715 demand_empty_rest_of_line ();
3719 /* Calling mapping_state () here will not change ARM/THUMB,
3720 but will ensure not to be in DATA state. */
3723 mapping_state (MAP_THUMB
);
3728 as_bad (_("width suffixes are invalid in ARM mode"));
3729 ignore_rest_of_line ();
3735 mapping_state (MAP_ARM
);
3744 if (! emit_insn (& exp
, nbytes
))
3746 ignore_rest_of_line ();
3750 while (*input_line_pointer
++ == ',');
3752 /* Put terminator back into stream. */
3753 input_line_pointer
--;
3754 demand_empty_rest_of_line ();
3757 /* Parse a .rel31 directive. */
3760 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3767 if (*input_line_pointer
== '1')
3768 highbit
= 0x80000000;
3769 else if (*input_line_pointer
!= '0')
3770 as_bad (_("expected 0 or 1"));
3772 input_line_pointer
++;
3773 if (*input_line_pointer
!= ',')
3774 as_bad (_("missing comma"));
3775 input_line_pointer
++;
3777 #ifdef md_flush_pending_output
3778 md_flush_pending_output ();
3781 #ifdef md_cons_align
3785 mapping_state (MAP_DATA
);
3790 md_number_to_chars (p
, highbit
, 4);
3791 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3792 BFD_RELOC_ARM_PREL31
);
3794 demand_empty_rest_of_line ();
3797 /* Directives: AEABI stack-unwind tables. */
3799 /* Parse an unwind_fnstart directive. Simply records the current location. */
3802 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3804 demand_empty_rest_of_line ();
3805 if (unwind
.proc_start
)
3807 as_bad (_("duplicate .fnstart directive"));
3811 /* Mark the start of the function. */
3812 unwind
.proc_start
= expr_build_dot ();
3814 /* Reset the rest of the unwind info. */
3815 unwind
.opcode_count
= 0;
3816 unwind
.table_entry
= NULL
;
3817 unwind
.personality_routine
= NULL
;
3818 unwind
.personality_index
= -1;
3819 unwind
.frame_size
= 0;
3820 unwind
.fp_offset
= 0;
3821 unwind
.fp_reg
= REG_SP
;
3823 unwind
.sp_restored
= 0;
3827 /* Parse a handlerdata directive. Creates the exception handling table entry
3828 for the function. */
3831 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3833 demand_empty_rest_of_line ();
3834 if (!unwind
.proc_start
)
3835 as_bad (MISSING_FNSTART
);
3837 if (unwind
.table_entry
)
3838 as_bad (_("duplicate .handlerdata directive"));
3840 create_unwind_entry (1);
3843 /* Parse an unwind_fnend directive. Generates the index table entry. */
3846 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3851 unsigned int marked_pr_dependency
;
3853 demand_empty_rest_of_line ();
3855 if (!unwind
.proc_start
)
3857 as_bad (_(".fnend directive without .fnstart"));
3861 /* Add eh table entry. */
3862 if (unwind
.table_entry
== NULL
)
3863 val
= create_unwind_entry (0);
3867 /* Add index table entry. This is two words. */
3868 start_unwind_section (unwind
.saved_seg
, 1);
3869 frag_align (2, 0, 0);
3870 record_alignment (now_seg
, 2);
3872 ptr
= frag_more (8);
3874 where
= frag_now_fix () - 8;
3876 /* Self relative offset of the function start. */
3877 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3878 BFD_RELOC_ARM_PREL31
);
3880 /* Indicate dependency on EHABI-defined personality routines to the
3881 linker, if it hasn't been done already. */
3882 marked_pr_dependency
3883 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3884 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3885 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3887 static const char *const name
[] =
3889 "__aeabi_unwind_cpp_pr0",
3890 "__aeabi_unwind_cpp_pr1",
3891 "__aeabi_unwind_cpp_pr2"
3893 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3894 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3895 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3896 |= 1 << unwind
.personality_index
;
3900 /* Inline exception table entry. */
3901 md_number_to_chars (ptr
+ 4, val
, 4);
3903 /* Self relative offset of the table entry. */
3904 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3905 BFD_RELOC_ARM_PREL31
);
3907 /* Restore the original section. */
3908 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3910 unwind
.proc_start
= NULL
;
3914 /* Parse an unwind_cantunwind directive. */
3917 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3919 demand_empty_rest_of_line ();
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("personality routine specified for cantunwind frame"));
3926 unwind
.personality_index
= -2;
3930 /* Parse a personalityindex directive. */
3933 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3937 if (!unwind
.proc_start
)
3938 as_bad (MISSING_FNSTART
);
3940 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3941 as_bad (_("duplicate .personalityindex directive"));
3945 if (exp
.X_op
!= O_constant
3946 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3948 as_bad (_("bad personality routine number"));
3949 ignore_rest_of_line ();
3953 unwind
.personality_index
= exp
.X_add_number
;
3955 demand_empty_rest_of_line ();
3959 /* Parse a personality directive. */
3962 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3966 if (!unwind
.proc_start
)
3967 as_bad (MISSING_FNSTART
);
3969 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3970 as_bad (_("duplicate .personality directive"));
3972 c
= get_symbol_name (& name
);
3973 p
= input_line_pointer
;
3975 ++ input_line_pointer
;
3976 unwind
.personality_routine
= symbol_find_or_make (name
);
3978 demand_empty_rest_of_line ();
3982 /* Parse a directive saving core registers. */
3985 s_arm_unwind_save_core (void)
3991 range
= parse_reg_list (&input_line_pointer
);
3994 as_bad (_("expected register list"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4001 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4002 into .unwind_save {..., sp...}. We aren't bothered about the value of
4003 ip because it is clobbered by calls. */
4004 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4005 && (range
& 0x3000) == 0x1000)
4007 unwind
.opcode_count
--;
4008 unwind
.sp_restored
= 0;
4009 range
= (range
| 0x2000) & ~0x1000;
4010 unwind
.pending_offset
= 0;
4016 /* See if we can use the short opcodes. These pop a block of up to 8
4017 registers starting with r4, plus maybe r14. */
4018 for (n
= 0; n
< 8; n
++)
4020 /* Break at the first non-saved register. */
4021 if ((range
& (1 << (n
+ 4))) == 0)
4024 /* See if there are any other bits set. */
4025 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4027 /* Use the long form. */
4028 op
= 0x8000 | ((range
>> 4) & 0xfff);
4029 add_unwind_opcode (op
, 2);
4033 /* Use the short form. */
4035 op
= 0xa8; /* Pop r14. */
4037 op
= 0xa0; /* Do not pop r14. */
4039 add_unwind_opcode (op
, 1);
4046 op
= 0xb100 | (range
& 0xf);
4047 add_unwind_opcode (op
, 2);
4050 /* Record the number of bytes pushed. */
4051 for (n
= 0; n
< 16; n
++)
4053 if (range
& (1 << n
))
4054 unwind
.frame_size
+= 4;
4059 /* Parse a directive saving FPA registers. */
4062 s_arm_unwind_save_fpa (int reg
)
4068 /* Get Number of registers to transfer. */
4069 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4072 exp
.X_op
= O_illegal
;
4074 if (exp
.X_op
!= O_constant
)
4076 as_bad (_("expected , <constant>"));
4077 ignore_rest_of_line ();
4081 num_regs
= exp
.X_add_number
;
4083 if (num_regs
< 1 || num_regs
> 4)
4085 as_bad (_("number of registers must be in the range [1:4]"));
4086 ignore_rest_of_line ();
4090 demand_empty_rest_of_line ();
4095 op
= 0xb4 | (num_regs
- 1);
4096 add_unwind_opcode (op
, 1);
4101 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4102 add_unwind_opcode (op
, 2);
4104 unwind
.frame_size
+= num_regs
* 12;
4108 /* Parse a directive saving VFP registers for ARMv6 and above. */
4111 s_arm_unwind_save_vfp_armv6 (void)
4116 int num_vfpv3_regs
= 0;
4117 int num_regs_below_16
;
4119 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4122 as_bad (_("expected register list"));
4123 ignore_rest_of_line ();
4127 demand_empty_rest_of_line ();
4129 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4130 than FSTMX/FLDMX-style ones). */
4132 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4134 num_vfpv3_regs
= count
;
4135 else if (start
+ count
> 16)
4136 num_vfpv3_regs
= start
+ count
- 16;
4138 if (num_vfpv3_regs
> 0)
4140 int start_offset
= start
> 16 ? start
- 16 : 0;
4141 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4142 add_unwind_opcode (op
, 2);
4145 /* Generate opcode for registers numbered in the range 0 .. 15. */
4146 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4147 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4148 if (num_regs_below_16
> 0)
4150 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4151 add_unwind_opcode (op
, 2);
4154 unwind
.frame_size
+= count
* 8;
4158 /* Parse a directive saving VFP registers for pre-ARMv6. */
4161 s_arm_unwind_save_vfp (void)
4167 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4170 as_bad (_("expected register list"));
4171 ignore_rest_of_line ();
4175 demand_empty_rest_of_line ();
4180 op
= 0xb8 | (count
- 1);
4181 add_unwind_opcode (op
, 1);
4186 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4187 add_unwind_opcode (op
, 2);
4189 unwind
.frame_size
+= count
* 8 + 4;
4193 /* Parse a directive saving iWMMXt data registers. */
4196 s_arm_unwind_save_mmxwr (void)
4204 if (*input_line_pointer
== '{')
4205 input_line_pointer
++;
4209 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4213 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4218 as_tsktsk (_("register list not in ascending order"));
4221 if (*input_line_pointer
== '-')
4223 input_line_pointer
++;
4224 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4227 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4230 else if (reg
>= hi_reg
)
4232 as_bad (_("bad register range"));
4235 for (; reg
< hi_reg
; reg
++)
4239 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4241 skip_past_char (&input_line_pointer
, '}');
4243 demand_empty_rest_of_line ();
4245 /* Generate any deferred opcodes because we're going to be looking at
4247 flush_pending_unwind ();
4249 for (i
= 0; i
< 16; i
++)
4251 if (mask
& (1 << i
))
4252 unwind
.frame_size
+= 8;
4255 /* Attempt to combine with a previous opcode. We do this because gcc
4256 likes to output separate unwind directives for a single block of
4258 if (unwind
.opcode_count
> 0)
4260 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4261 if ((i
& 0xf8) == 0xc0)
4264 /* Only merge if the blocks are contiguous. */
4267 if ((mask
& 0xfe00) == (1 << 9))
4269 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4270 unwind
.opcode_count
--;
4273 else if (i
== 6 && unwind
.opcode_count
>= 2)
4275 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4279 op
= 0xffff << (reg
- 1);
4281 && ((mask
& op
) == (1u << (reg
- 1))))
4283 op
= (1 << (reg
+ i
+ 1)) - 1;
4284 op
&= ~((1 << reg
) - 1);
4286 unwind
.opcode_count
-= 2;
4293 /* We want to generate opcodes in the order the registers have been
4294 saved, ie. descending order. */
4295 for (reg
= 15; reg
>= -1; reg
--)
4297 /* Save registers in blocks. */
4299 || !(mask
& (1 << reg
)))
4301 /* We found an unsaved reg. Generate opcodes to save the
4308 op
= 0xc0 | (hi_reg
- 10);
4309 add_unwind_opcode (op
, 1);
4314 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4315 add_unwind_opcode (op
, 2);
4324 ignore_rest_of_line ();
4328 s_arm_unwind_save_mmxwcg (void)
4335 if (*input_line_pointer
== '{')
4336 input_line_pointer
++;
4338 skip_whitespace (input_line_pointer
);
4342 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4346 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4352 as_tsktsk (_("register list not in ascending order"));
4355 if (*input_line_pointer
== '-')
4357 input_line_pointer
++;
4358 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4361 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4364 else if (reg
>= hi_reg
)
4366 as_bad (_("bad register range"));
4369 for (; reg
< hi_reg
; reg
++)
4373 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4375 skip_past_char (&input_line_pointer
, '}');
4377 demand_empty_rest_of_line ();
4379 /* Generate any deferred opcodes because we're going to be looking at
4381 flush_pending_unwind ();
4383 for (reg
= 0; reg
< 16; reg
++)
4385 if (mask
& (1 << reg
))
4386 unwind
.frame_size
+= 4;
4389 add_unwind_opcode (op
, 2);
4392 ignore_rest_of_line ();
4396 /* Parse an unwind_save directive.
4397 If the argument is non-zero, this is a .vsave directive. */
4400 s_arm_unwind_save (int arch_v6
)
4403 struct reg_entry
*reg
;
4404 bfd_boolean had_brace
= FALSE
;
4406 if (!unwind
.proc_start
)
4407 as_bad (MISSING_FNSTART
);
4409 /* Figure out what sort of save we have. */
4410 peek
= input_line_pointer
;
4418 reg
= arm_reg_parse_multi (&peek
);
4422 as_bad (_("register expected"));
4423 ignore_rest_of_line ();
4432 as_bad (_("FPA .unwind_save does not take a register list"));
4433 ignore_rest_of_line ();
4436 input_line_pointer
= peek
;
4437 s_arm_unwind_save_fpa (reg
->number
);
4441 s_arm_unwind_save_core ();
4446 s_arm_unwind_save_vfp_armv6 ();
4448 s_arm_unwind_save_vfp ();
4451 case REG_TYPE_MMXWR
:
4452 s_arm_unwind_save_mmxwr ();
4455 case REG_TYPE_MMXWCG
:
4456 s_arm_unwind_save_mmxwcg ();
4460 as_bad (_(".unwind_save does not support this kind of register"));
4461 ignore_rest_of_line ();
4466 /* Parse an unwind_movsp directive. */
4469 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4475 if (!unwind
.proc_start
)
4476 as_bad (MISSING_FNSTART
);
4478 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4481 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4482 ignore_rest_of_line ();
4486 /* Optional constant. */
4487 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4489 if (immediate_for_directive (&offset
) == FAIL
)
4495 demand_empty_rest_of_line ();
4497 if (reg
== REG_SP
|| reg
== REG_PC
)
4499 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4503 if (unwind
.fp_reg
!= REG_SP
)
4504 as_bad (_("unexpected .unwind_movsp directive"));
4506 /* Generate opcode to restore the value. */
4508 add_unwind_opcode (op
, 1);
4510 /* Record the information for later. */
4511 unwind
.fp_reg
= reg
;
4512 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4513 unwind
.sp_restored
= 1;
4516 /* Parse an unwind_pad directive. */
4519 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4523 if (!unwind
.proc_start
)
4524 as_bad (MISSING_FNSTART
);
4526 if (immediate_for_directive (&offset
) == FAIL
)
4531 as_bad (_("stack increment must be multiple of 4"));
4532 ignore_rest_of_line ();
4536 /* Don't generate any opcodes, just record the details for later. */
4537 unwind
.frame_size
+= offset
;
4538 unwind
.pending_offset
+= offset
;
4540 demand_empty_rest_of_line ();
4543 /* Parse an unwind_setfp directive. */
4546 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4552 if (!unwind
.proc_start
)
4553 as_bad (MISSING_FNSTART
);
4555 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4556 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4561 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4563 as_bad (_("expected <reg>, <reg>"));
4564 ignore_rest_of_line ();
4568 /* Optional constant. */
4569 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4571 if (immediate_for_directive (&offset
) == FAIL
)
4577 demand_empty_rest_of_line ();
4579 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4581 as_bad (_("register must be either sp or set by a previous"
4582 "unwind_movsp directive"));
4586 /* Don't generate any opcodes, just record the information for later. */
4587 unwind
.fp_reg
= fp_reg
;
4589 if (sp_reg
== REG_SP
)
4590 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4592 unwind
.fp_offset
-= offset
;
4595 /* Parse an unwind_raw directive. */
4598 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4601 /* This is an arbitrary limit. */
4602 unsigned char op
[16];
4605 if (!unwind
.proc_start
)
4606 as_bad (MISSING_FNSTART
);
4609 if (exp
.X_op
== O_constant
4610 && skip_past_comma (&input_line_pointer
) != FAIL
)
4612 unwind
.frame_size
+= exp
.X_add_number
;
4616 exp
.X_op
= O_illegal
;
4618 if (exp
.X_op
!= O_constant
)
4620 as_bad (_("expected <offset>, <opcode>"));
4621 ignore_rest_of_line ();
4627 /* Parse the opcode. */
4632 as_bad (_("unwind opcode too long"));
4633 ignore_rest_of_line ();
4635 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4637 as_bad (_("invalid unwind opcode"));
4638 ignore_rest_of_line ();
4641 op
[count
++] = exp
.X_add_number
;
4643 /* Parse the next byte. */
4644 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4650 /* Add the opcode bytes in reverse order. */
4652 add_unwind_opcode (op
[count
], 1);
4654 demand_empty_rest_of_line ();
4658 /* Parse a .eabi_attribute directive. */
4661 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4663 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4665 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4666 attributes_set_explicitly
[tag
] = 1;
4669 /* Emit a tls fix for the symbol. */
4672 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4676 #ifdef md_flush_pending_output
4677 md_flush_pending_output ();
4680 #ifdef md_cons_align
4684 /* Since we're just labelling the code, there's no need to define a
4687 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4688 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4689 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4690 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4692 #endif /* OBJ_ELF */
4694 static void s_arm_arch (int);
4695 static void s_arm_object_arch (int);
4696 static void s_arm_cpu (int);
4697 static void s_arm_fpu (int);
4698 static void s_arm_arch_extension (int);
4703 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4710 if (exp
.X_op
== O_symbol
)
4711 exp
.X_op
= O_secrel
;
4713 emit_expr (&exp
, 4);
4715 while (*input_line_pointer
++ == ',');
4717 input_line_pointer
--;
4718 demand_empty_rest_of_line ();
4722 /* This table describes all the machine specific pseudo-ops the assembler
4723 has to support. The fields are:
4724 pseudo-op name without dot
4725 function to call to execute this pseudo-op
4726 Integer arg to pass to the function. */
4728 const pseudo_typeS md_pseudo_table
[] =
4730 /* Never called because '.req' does not start a line. */
4731 { "req", s_req
, 0 },
4732 /* Following two are likewise never called. */
4735 { "unreq", s_unreq
, 0 },
4736 { "bss", s_bss
, 0 },
4737 { "align", s_align_ptwo
, 2 },
4738 { "arm", s_arm
, 0 },
4739 { "thumb", s_thumb
, 0 },
4740 { "code", s_code
, 0 },
4741 { "force_thumb", s_force_thumb
, 0 },
4742 { "thumb_func", s_thumb_func
, 0 },
4743 { "thumb_set", s_thumb_set
, 0 },
4744 { "even", s_even
, 0 },
4745 { "ltorg", s_ltorg
, 0 },
4746 { "pool", s_ltorg
, 0 },
4747 { "syntax", s_syntax
, 0 },
4748 { "cpu", s_arm_cpu
, 0 },
4749 { "arch", s_arm_arch
, 0 },
4750 { "object_arch", s_arm_object_arch
, 0 },
4751 { "fpu", s_arm_fpu
, 0 },
4752 { "arch_extension", s_arm_arch_extension
, 0 },
4754 { "word", s_arm_elf_cons
, 4 },
4755 { "long", s_arm_elf_cons
, 4 },
4756 { "inst.n", s_arm_elf_inst
, 2 },
4757 { "inst.w", s_arm_elf_inst
, 4 },
4758 { "inst", s_arm_elf_inst
, 0 },
4759 { "rel31", s_arm_rel31
, 0 },
4760 { "fnstart", s_arm_unwind_fnstart
, 0 },
4761 { "fnend", s_arm_unwind_fnend
, 0 },
4762 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4763 { "personality", s_arm_unwind_personality
, 0 },
4764 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4765 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4766 { "save", s_arm_unwind_save
, 0 },
4767 { "vsave", s_arm_unwind_save
, 1 },
4768 { "movsp", s_arm_unwind_movsp
, 0 },
4769 { "pad", s_arm_unwind_pad
, 0 },
4770 { "setfp", s_arm_unwind_setfp
, 0 },
4771 { "unwind_raw", s_arm_unwind_raw
, 0 },
4772 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4773 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4777 /* These are used for dwarf. */
4781 /* These are used for dwarf2. */
4782 { "file", dwarf2_directive_file
, 0 },
4783 { "loc", dwarf2_directive_loc
, 0 },
4784 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4786 { "extend", float_cons
, 'x' },
4787 { "ldouble", float_cons
, 'x' },
4788 { "packed", float_cons
, 'p' },
4790 {"secrel32", pe_directive_secrel
, 0},
4793 /* These are for compatibility with CodeComposer Studio. */
4794 {"ref", s_ccs_ref
, 0},
4795 {"def", s_ccs_def
, 0},
4796 {"asmfunc", s_ccs_asmfunc
, 0},
4797 {"endasmfunc", s_ccs_endasmfunc
, 0},
4802 /* Parser functions used exclusively in instruction operands. */
4804 /* Generic immediate-value read function for use in insn parsing.
4805 STR points to the beginning of the immediate (the leading #);
4806 VAL receives the value; if the value is outside [MIN, MAX]
4807 issue an error. PREFIX_OPT is true if the immediate prefix is
4811 parse_immediate (char **str
, int *val
, int min
, int max
,
4812 bfd_boolean prefix_opt
)
4816 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4817 if (exp
.X_op
!= O_constant
)
4819 inst
.error
= _("constant expression required");
4823 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4825 inst
.error
= _("immediate value out of range");
4829 *val
= exp
.X_add_number
;
4833 /* Less-generic immediate-value read function with the possibility of loading a
4834 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4835 instructions. Puts the result directly in inst.operands[i]. */
4838 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4839 bfd_boolean allow_symbol_p
)
4842 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4845 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4847 if (exp_p
->X_op
== O_constant
)
4849 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4850 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4851 O_constant. We have to be careful not to break compilation for
4852 32-bit X_add_number, though. */
4853 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4855 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4856 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4858 inst
.operands
[i
].regisimm
= 1;
4861 else if (exp_p
->X_op
== O_big
4862 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4864 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4866 /* Bignums have their least significant bits in
4867 generic_bignum[0]. Make sure we put 32 bits in imm and
4868 32 bits in reg, in a (hopefully) portable way. */
4869 gas_assert (parts
!= 0);
4871 /* Make sure that the number is not too big.
4872 PR 11972: Bignums can now be sign-extended to the
4873 size of a .octa so check that the out of range bits
4874 are all zero or all one. */
4875 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4877 LITTLENUM_TYPE m
= -1;
4879 if (generic_bignum
[parts
* 2] != 0
4880 && generic_bignum
[parts
* 2] != m
)
4883 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4884 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4888 inst
.operands
[i
].imm
= 0;
4889 for (j
= 0; j
< parts
; j
++, idx
++)
4890 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4891 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4892 inst
.operands
[i
].reg
= 0;
4893 for (j
= 0; j
< parts
; j
++, idx
++)
4894 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4895 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4896 inst
.operands
[i
].regisimm
= 1;
4898 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4906 /* Returns the pseudo-register number of an FPA immediate constant,
4907 or FAIL if there isn't a valid constant here. */
4910 parse_fpa_immediate (char ** str
)
4912 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4918 /* First try and match exact strings, this is to guarantee
4919 that some formats will work even for cross assembly. */
4921 for (i
= 0; fp_const
[i
]; i
++)
4923 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4927 *str
+= strlen (fp_const
[i
]);
4928 if (is_end_of_line
[(unsigned char) **str
])
4934 /* Just because we didn't get a match doesn't mean that the constant
4935 isn't valid, just that it is in a format that we don't
4936 automatically recognize. Try parsing it with the standard
4937 expression routines. */
4939 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4941 /* Look for a raw floating point number. */
4942 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4943 && is_end_of_line
[(unsigned char) *save_in
])
4945 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4947 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4949 if (words
[j
] != fp_values
[i
][j
])
4953 if (j
== MAX_LITTLENUMS
)
4961 /* Try and parse a more complex expression, this will probably fail
4962 unless the code uses a floating point prefix (eg "0f"). */
4963 save_in
= input_line_pointer
;
4964 input_line_pointer
= *str
;
4965 if (expression (&exp
) == absolute_section
4966 && exp
.X_op
== O_big
4967 && exp
.X_add_number
< 0)
4969 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4971 #define X_PRECISION 5
4972 #define E_PRECISION 15L
4973 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4975 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4977 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4979 if (words
[j
] != fp_values
[i
][j
])
4983 if (j
== MAX_LITTLENUMS
)
4985 *str
= input_line_pointer
;
4986 input_line_pointer
= save_in
;
4993 *str
= input_line_pointer
;
4994 input_line_pointer
= save_in
;
4995 inst
.error
= _("invalid FPA immediate expression");
4999 /* Returns 1 if a number has "quarter-precision" float format
5000 0baBbbbbbc defgh000 00000000 00000000. */
5003 is_quarter_float (unsigned imm
)
5005 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5006 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5010 /* Detect the presence of a floating point or integer zero constant,
5014 parse_ifimm_zero (char **in
)
5018 if (!is_immediate_prefix (**in
))
5020 /* In unified syntax, all prefixes are optional. */
5021 if (!unified_syntax
)
5027 /* Accept #0x0 as a synonym for #0. */
5028 if (strncmp (*in
, "0x", 2) == 0)
5031 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5036 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5037 &generic_floating_point_number
);
5040 && generic_floating_point_number
.sign
== '+'
5041 && (generic_floating_point_number
.low
5042 > generic_floating_point_number
.leader
))
5048 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5049 0baBbbbbbc defgh000 00000000 00000000.
5050 The zero and minus-zero cases need special handling, since they can't be
5051 encoded in the "quarter-precision" float format, but can nonetheless be
5052 loaded as integer constants. */
5055 parse_qfloat_immediate (char **ccp
, int *immed
)
5059 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5060 int found_fpchar
= 0;
5062 skip_past_char (&str
, '#');
5064 /* We must not accidentally parse an integer as a floating-point number. Make
5065 sure that the value we parse is not an integer by checking for special
5066 characters '.' or 'e'.
5067 FIXME: This is a horrible hack, but doing better is tricky because type
5068 information isn't in a very usable state at parse time. */
5070 skip_whitespace (fpnum
);
5072 if (strncmp (fpnum
, "0x", 2) == 0)
5076 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5077 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5087 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5089 unsigned fpword
= 0;
5092 /* Our FP word must be 32 bits (single-precision FP). */
5093 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5095 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5099 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5112 /* Shift operands. */
5115 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5118 struct asm_shift_name
5121 enum shift_kind kind
;
5124 /* Third argument to parse_shift. */
5125 enum parse_shift_mode
5127 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5128 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5129 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5130 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5131 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5134 /* Parse a <shift> specifier on an ARM data processing instruction.
5135 This has three forms:
5137 (LSL|LSR|ASL|ASR|ROR) Rs
5138 (LSL|LSR|ASL|ASR|ROR) #imm
5141 Note that ASL is assimilated to LSL in the instruction encoding, and
5142 RRX to ROR #0 (which cannot be written as such). */
5145 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5147 const struct asm_shift_name
*shift_name
;
5148 enum shift_kind shift
;
5153 for (p
= *str
; ISALPHA (*p
); p
++)
5158 inst
.error
= _("shift expression expected");
5162 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5165 if (shift_name
== NULL
)
5167 inst
.error
= _("shift expression expected");
5171 shift
= shift_name
->kind
;
5175 case NO_SHIFT_RESTRICT
:
5176 case SHIFT_IMMEDIATE
: break;
5178 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5179 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5181 inst
.error
= _("'LSL' or 'ASR' required");
5186 case SHIFT_LSL_IMMEDIATE
:
5187 if (shift
!= SHIFT_LSL
)
5189 inst
.error
= _("'LSL' required");
5194 case SHIFT_ASR_IMMEDIATE
:
5195 if (shift
!= SHIFT_ASR
)
5197 inst
.error
= _("'ASR' required");
5205 if (shift
!= SHIFT_RRX
)
5207 /* Whitespace can appear here if the next thing is a bare digit. */
5208 skip_whitespace (p
);
5210 if (mode
== NO_SHIFT_RESTRICT
5211 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5213 inst
.operands
[i
].imm
= reg
;
5214 inst
.operands
[i
].immisreg
= 1;
5216 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5219 inst
.operands
[i
].shift_kind
= shift
;
5220 inst
.operands
[i
].shifted
= 1;
5225 /* Parse a <shifter_operand> for an ARM data processing instruction:
5228 #<immediate>, <rotate>
5232 where <shift> is defined by parse_shift above, and <rotate> is a
5233 multiple of 2 between 0 and 30. Validation of immediate operands
5234 is deferred to md_apply_fix. */
5237 parse_shifter_operand (char **str
, int i
)
5242 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5244 inst
.operands
[i
].reg
= value
;
5245 inst
.operands
[i
].isreg
= 1;
5247 /* parse_shift will override this if appropriate */
5248 inst
.relocs
[0].exp
.X_op
= O_constant
;
5249 inst
.relocs
[0].exp
.X_add_number
= 0;
5251 if (skip_past_comma (str
) == FAIL
)
5254 /* Shift operation on register. */
5255 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5258 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5261 if (skip_past_comma (str
) == SUCCESS
)
5263 /* #x, y -- ie explicit rotation by Y. */
5264 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5267 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5269 inst
.error
= _("constant expression expected");
5273 value
= exp
.X_add_number
;
5274 if (value
< 0 || value
> 30 || value
% 2 != 0)
5276 inst
.error
= _("invalid rotation");
5279 if (inst
.relocs
[0].exp
.X_add_number
< 0
5280 || inst
.relocs
[0].exp
.X_add_number
> 255)
5282 inst
.error
= _("invalid constant");
5286 /* Encode as specified. */
5287 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5291 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5292 inst
.relocs
[0].pc_rel
= 0;
5296 /* Group relocation information. Each entry in the table contains the
5297 textual name of the relocation as may appear in assembler source
5298 and must end with a colon.
5299 Along with this textual name are the relocation codes to be used if
5300 the corresponding instruction is an ALU instruction (ADD or SUB only),
5301 an LDR, an LDRS, or an LDC. */
5303 struct group_reloc_table_entry
5314 /* Varieties of non-ALU group relocation. */
5321 static struct group_reloc_table_entry group_reloc_table
[] =
5322 { /* Program counter relative: */
5324 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5329 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5330 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5331 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5332 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5334 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5339 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5340 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5341 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5342 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5344 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5345 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5346 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5347 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5348 /* Section base relative */
5350 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5355 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5356 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5357 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5358 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5360 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5365 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5366 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5367 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5368 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5370 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5371 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5372 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5373 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5374 /* Absolute thumb alu relocations. */
5376 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5381 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5386 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5391 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5396 /* Given the address of a pointer pointing to the textual name of a group
5397 relocation as may appear in assembler source, attempt to find its details
5398 in group_reloc_table. The pointer will be updated to the character after
5399 the trailing colon. On failure, FAIL will be returned; SUCCESS
5400 otherwise. On success, *entry will be updated to point at the relevant
5401 group_reloc_table entry. */
5404 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5407 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5409 int length
= strlen (group_reloc_table
[i
].name
);
5411 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5412 && (*str
)[length
] == ':')
5414 *out
= &group_reloc_table
[i
];
5415 *str
+= (length
+ 1);
5423 /* Parse a <shifter_operand> for an ARM data processing instruction
5424 (as for parse_shifter_operand) where group relocations are allowed:
5427 #<immediate>, <rotate>
5428 #:<group_reloc>:<expression>
5432 where <group_reloc> is one of the strings defined in group_reloc_table.
5433 The hashes are optional.
5435 Everything else is as for parse_shifter_operand. */
5437 static parse_operand_result
5438 parse_shifter_operand_group_reloc (char **str
, int i
)
5440 /* Determine if we have the sequence of characters #: or just :
5441 coming next. If we do, then we check for a group relocation.
5442 If we don't, punt the whole lot to parse_shifter_operand. */
5444 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5445 || (*str
)[0] == ':')
5447 struct group_reloc_table_entry
*entry
;
5449 if ((*str
)[0] == '#')
5454 /* Try to parse a group relocation. Anything else is an error. */
5455 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5457 inst
.error
= _("unknown group relocation");
5458 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5461 /* We now have the group relocation table entry corresponding to
5462 the name in the assembler source. Next, we parse the expression. */
5463 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5464 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5466 /* Record the relocation type (always the ALU variant here). */
5467 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5468 gas_assert (inst
.relocs
[0].type
!= 0);
5470 return PARSE_OPERAND_SUCCESS
;
5473 return parse_shifter_operand (str
, i
) == SUCCESS
5474 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5476 /* Never reached. */
5479 /* Parse a Neon alignment expression. Information is written to
5480 inst.operands[i]. We assume the initial ':' has been skipped.
5482 align .imm = align << 8, .immisalign=1, .preind=0 */
5483 static parse_operand_result
5484 parse_neon_alignment (char **str
, int i
)
5489 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5491 if (exp
.X_op
!= O_constant
)
5493 inst
.error
= _("alignment must be constant");
5494 return PARSE_OPERAND_FAIL
;
5497 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5498 inst
.operands
[i
].immisalign
= 1;
5499 /* Alignments are not pre-indexes. */
5500 inst
.operands
[i
].preind
= 0;
5503 return PARSE_OPERAND_SUCCESS
;
5506 /* Parse all forms of an ARM address expression. Information is written
5507 to inst.operands[i] and/or inst.relocs[0].
5509 Preindexed addressing (.preind=1):
5511 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5512 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5513 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5514 .shift_kind=shift .relocs[0].exp=shift_imm
5516 These three may have a trailing ! which causes .writeback to be set also.
5518 Postindexed addressing (.postind=1, .writeback=1):
5520 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5521 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5522 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5523 .shift_kind=shift .relocs[0].exp=shift_imm
5525 Unindexed addressing (.preind=0, .postind=0):
5527 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5531 [Rn]{!} shorthand for [Rn,#0]{!}
5532 =immediate .isreg=0 .relocs[0].exp=immediate
5533 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5535 It is the caller's responsibility to check for addressing modes not
5536 supported by the instruction, and to set inst.relocs[0].type. */
5538 static parse_operand_result
5539 parse_address_main (char **str
, int i
, int group_relocations
,
5540 group_reloc_type group_type
)
5545 if (skip_past_char (&p
, '[') == FAIL
)
5547 if (skip_past_char (&p
, '=') == FAIL
)
5549 /* Bare address - translate to PC-relative offset. */
5550 inst
.relocs
[0].pc_rel
= 1;
5551 inst
.operands
[i
].reg
= REG_PC
;
5552 inst
.operands
[i
].isreg
= 1;
5553 inst
.operands
[i
].preind
= 1;
5555 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5556 return PARSE_OPERAND_FAIL
;
5558 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5559 /*allow_symbol_p=*/TRUE
))
5560 return PARSE_OPERAND_FAIL
;
5563 return PARSE_OPERAND_SUCCESS
;
5566 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5567 skip_whitespace (p
);
5569 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5571 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5572 return PARSE_OPERAND_FAIL
;
5574 inst
.operands
[i
].reg
= reg
;
5575 inst
.operands
[i
].isreg
= 1;
5577 if (skip_past_comma (&p
) == SUCCESS
)
5579 inst
.operands
[i
].preind
= 1;
5582 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5584 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5586 inst
.operands
[i
].imm
= reg
;
5587 inst
.operands
[i
].immisreg
= 1;
5589 if (skip_past_comma (&p
) == SUCCESS
)
5590 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5591 return PARSE_OPERAND_FAIL
;
5593 else if (skip_past_char (&p
, ':') == SUCCESS
)
5595 /* FIXME: '@' should be used here, but it's filtered out by generic
5596 code before we get to see it here. This may be subject to
5598 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5600 if (result
!= PARSE_OPERAND_SUCCESS
)
5605 if (inst
.operands
[i
].negative
)
5607 inst
.operands
[i
].negative
= 0;
5611 if (group_relocations
5612 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5614 struct group_reloc_table_entry
*entry
;
5616 /* Skip over the #: or : sequence. */
5622 /* Try to parse a group relocation. Anything else is an
5624 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5626 inst
.error
= _("unknown group relocation");
5627 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5630 /* We now have the group relocation table entry corresponding to
5631 the name in the assembler source. Next, we parse the
5633 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5634 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5636 /* Record the relocation type. */
5641 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5646 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5651 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5658 if (inst
.relocs
[0].type
== 0)
5660 inst
.error
= _("this group relocation is not allowed on this instruction");
5661 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5668 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5669 return PARSE_OPERAND_FAIL
;
5670 /* If the offset is 0, find out if it's a +0 or -0. */
5671 if (inst
.relocs
[0].exp
.X_op
== O_constant
5672 && inst
.relocs
[0].exp
.X_add_number
== 0)
5674 skip_whitespace (q
);
5678 skip_whitespace (q
);
5681 inst
.operands
[i
].negative
= 1;
5686 else if (skip_past_char (&p
, ':') == SUCCESS
)
5688 /* FIXME: '@' should be used here, but it's filtered out by generic code
5689 before we get to see it here. This may be subject to change. */
5690 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5692 if (result
!= PARSE_OPERAND_SUCCESS
)
5696 if (skip_past_char (&p
, ']') == FAIL
)
5698 inst
.error
= _("']' expected");
5699 return PARSE_OPERAND_FAIL
;
5702 if (skip_past_char (&p
, '!') == SUCCESS
)
5703 inst
.operands
[i
].writeback
= 1;
5705 else if (skip_past_comma (&p
) == SUCCESS
)
5707 if (skip_past_char (&p
, '{') == SUCCESS
)
5709 /* [Rn], {expr} - unindexed, with option */
5710 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5711 0, 255, TRUE
) == FAIL
)
5712 return PARSE_OPERAND_FAIL
;
5714 if (skip_past_char (&p
, '}') == FAIL
)
5716 inst
.error
= _("'}' expected at end of 'option' field");
5717 return PARSE_OPERAND_FAIL
;
5719 if (inst
.operands
[i
].preind
)
5721 inst
.error
= _("cannot combine index with option");
5722 return PARSE_OPERAND_FAIL
;
5725 return PARSE_OPERAND_SUCCESS
;
5729 inst
.operands
[i
].postind
= 1;
5730 inst
.operands
[i
].writeback
= 1;
5732 if (inst
.operands
[i
].preind
)
5734 inst
.error
= _("cannot combine pre- and post-indexing");
5735 return PARSE_OPERAND_FAIL
;
5739 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5741 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5743 /* We might be using the immediate for alignment already. If we
5744 are, OR the register number into the low-order bits. */
5745 if (inst
.operands
[i
].immisalign
)
5746 inst
.operands
[i
].imm
|= reg
;
5748 inst
.operands
[i
].imm
= reg
;
5749 inst
.operands
[i
].immisreg
= 1;
5751 if (skip_past_comma (&p
) == SUCCESS
)
5752 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5753 return PARSE_OPERAND_FAIL
;
5759 if (inst
.operands
[i
].negative
)
5761 inst
.operands
[i
].negative
= 0;
5764 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5765 return PARSE_OPERAND_FAIL
;
5766 /* If the offset is 0, find out if it's a +0 or -0. */
5767 if (inst
.relocs
[0].exp
.X_op
== O_constant
5768 && inst
.relocs
[0].exp
.X_add_number
== 0)
5770 skip_whitespace (q
);
5774 skip_whitespace (q
);
5777 inst
.operands
[i
].negative
= 1;
5783 /* If at this point neither .preind nor .postind is set, we have a
5784 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5785 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5787 inst
.operands
[i
].preind
= 1;
5788 inst
.relocs
[0].exp
.X_op
= O_constant
;
5789 inst
.relocs
[0].exp
.X_add_number
= 0;
5792 return PARSE_OPERAND_SUCCESS
;
5796 parse_address (char **str
, int i
)
5798 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5802 static parse_operand_result
5803 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5805 return parse_address_main (str
, i
, 1, type
);
5808 /* Parse an operand for a MOVW or MOVT instruction. */
5810 parse_half (char **str
)
5815 skip_past_char (&p
, '#');
5816 if (strncasecmp (p
, ":lower16:", 9) == 0)
5817 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
5818 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5819 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
5821 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
5824 skip_whitespace (p
);
5827 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5830 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
5832 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
5834 inst
.error
= _("constant expression expected");
5837 if (inst
.relocs
[0].exp
.X_add_number
< 0
5838 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
5840 inst
.error
= _("immediate value out of range");
5848 /* Miscellaneous. */
5850 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5851 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5853 parse_psr (char **str
, bfd_boolean lhs
)
5856 unsigned long psr_field
;
5857 const struct asm_psr
*psr
;
5859 bfd_boolean is_apsr
= FALSE
;
5860 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5862 /* PR gas/12698: If the user has specified -march=all then m_profile will
5863 be TRUE, but we want to ignore it in this case as we are building for any
5864 CPU type, including non-m variants. */
5865 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5868 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5869 feature for ease of use and backwards compatibility. */
5871 if (strncasecmp (p
, "SPSR", 4) == 0)
5874 goto unsupported_psr
;
5876 psr_field
= SPSR_BIT
;
5878 else if (strncasecmp (p
, "CPSR", 4) == 0)
5881 goto unsupported_psr
;
5885 else if (strncasecmp (p
, "APSR", 4) == 0)
5887 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5888 and ARMv7-R architecture CPUs. */
5897 while (ISALNUM (*p
) || *p
== '_');
5899 if (strncasecmp (start
, "iapsr", 5) == 0
5900 || strncasecmp (start
, "eapsr", 5) == 0
5901 || strncasecmp (start
, "xpsr", 4) == 0
5902 || strncasecmp (start
, "psr", 3) == 0)
5903 p
= start
+ strcspn (start
, "rR") + 1;
5905 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5911 /* If APSR is being written, a bitfield may be specified. Note that
5912 APSR itself is handled above. */
5913 if (psr
->field
<= 3)
5915 psr_field
= psr
->field
;
5921 /* M-profile MSR instructions have the mask field set to "10", except
5922 *PSR variants which modify APSR, which may use a different mask (and
5923 have been handled already). Do that by setting the PSR_f field
5925 return psr
->field
| (lhs
? PSR_f
: 0);
5928 goto unsupported_psr
;
5934 /* A suffix follows. */
5940 while (ISALNUM (*p
) || *p
== '_');
5944 /* APSR uses a notation for bits, rather than fields. */
5945 unsigned int nzcvq_bits
= 0;
5946 unsigned int g_bit
= 0;
5949 for (bit
= start
; bit
!= p
; bit
++)
5951 switch (TOLOWER (*bit
))
5954 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5958 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5962 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5966 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5970 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5974 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5978 inst
.error
= _("unexpected bit specified after APSR");
5983 if (nzcvq_bits
== 0x1f)
5988 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5990 inst
.error
= _("selected processor does not "
5991 "support DSP extension");
5998 if ((nzcvq_bits
& 0x20) != 0
5999 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6000 || (g_bit
& 0x2) != 0)
6002 inst
.error
= _("bad bitmask specified after APSR");
6008 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6013 psr_field
|= psr
->field
;
6019 goto error
; /* Garbage after "[CS]PSR". */
6021 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6022 is deprecated, but allow it anyway. */
6026 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6029 else if (!m_profile
)
6030 /* These bits are never right for M-profile devices: don't set them
6031 (only code paths which read/write APSR reach here). */
6032 psr_field
|= (PSR_c
| PSR_f
);
6038 inst
.error
= _("selected processor does not support requested special "
6039 "purpose register");
6043 inst
.error
= _("flag for {c}psr instruction expected");
6047 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6048 value suitable for splatting into the AIF field of the instruction. */
6051 parse_cps_flags (char **str
)
6060 case '\0': case ',':
6063 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6064 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6065 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6068 inst
.error
= _("unrecognized CPS flag");
6073 if (saw_a_flag
== 0)
6075 inst
.error
= _("missing CPS flags");
6083 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6084 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6087 parse_endian_specifier (char **str
)
6092 if (strncasecmp (s
, "BE", 2))
6094 else if (strncasecmp (s
, "LE", 2))
6098 inst
.error
= _("valid endian specifiers are be or le");
6102 if (ISALNUM (s
[2]) || s
[2] == '_')
6104 inst
.error
= _("valid endian specifiers are be or le");
6109 return little_endian
;
6112 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6113 value suitable for poking into the rotate field of an sxt or sxta
6114 instruction, or FAIL on error. */
6117 parse_ror (char **str
)
6122 if (strncasecmp (s
, "ROR", 3) == 0)
6126 inst
.error
= _("missing rotation field after comma");
6130 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6135 case 0: *str
= s
; return 0x0;
6136 case 8: *str
= s
; return 0x1;
6137 case 16: *str
= s
; return 0x2;
6138 case 24: *str
= s
; return 0x3;
6141 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6146 /* Parse a conditional code (from conds[] below). The value returned is in the
6147 range 0 .. 14, or FAIL. */
6149 parse_cond (char **str
)
6152 const struct asm_cond
*c
;
6154 /* Condition codes are always 2 characters, so matching up to
6155 3 characters is sufficient. */
6160 while (ISALPHA (*q
) && n
< 3)
6162 cond
[n
] = TOLOWER (*q
);
6167 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6170 inst
.error
= _("condition required");
6178 /* Record a use of the given feature. */
6180 record_feature_use (const arm_feature_set
*feature
)
6183 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6185 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6188 /* If the given feature is currently allowed, mark it as used and return TRUE.
6189 Return FALSE otherwise. */
6191 mark_feature_used (const arm_feature_set
*feature
)
6193 /* Ensure the option is currently allowed. */
6194 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6197 /* Add the appropriate architecture feature for the barrier option used. */
6198 record_feature_use (feature
);
6203 /* Parse an option for a barrier instruction. Returns the encoding for the
6206 parse_barrier (char **str
)
6209 const struct asm_barrier_opt
*o
;
6212 while (ISALPHA (*q
))
6215 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6220 if (!mark_feature_used (&o
->arch
))
6227 /* Parse the operands of a table branch instruction. Similar to a memory
6230 parse_tb (char **str
)
6235 if (skip_past_char (&p
, '[') == FAIL
)
6237 inst
.error
= _("'[' expected");
6241 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6243 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6246 inst
.operands
[0].reg
= reg
;
6248 if (skip_past_comma (&p
) == FAIL
)
6250 inst
.error
= _("',' expected");
6254 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6256 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6259 inst
.operands
[0].imm
= reg
;
6261 if (skip_past_comma (&p
) == SUCCESS
)
6263 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6265 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6267 inst
.error
= _("invalid shift");
6270 inst
.operands
[0].shifted
= 1;
6273 if (skip_past_char (&p
, ']') == FAIL
)
6275 inst
.error
= _("']' expected");
6282 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6283 information on the types the operands can take and how they are encoded.
6284 Up to four operands may be read; this function handles setting the
6285 ".present" field for each read operand itself.
6286 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6287 else returns FAIL. */
6290 parse_neon_mov (char **str
, int *which_operand
)
6292 int i
= *which_operand
, val
;
6293 enum arm_reg_type rtype
;
6295 struct neon_type_el optype
;
6297 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6299 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6300 inst
.operands
[i
].reg
= val
;
6301 inst
.operands
[i
].isscalar
= 1;
6302 inst
.operands
[i
].vectype
= optype
;
6303 inst
.operands
[i
++].present
= 1;
6305 if (skip_past_comma (&ptr
) == FAIL
)
6308 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].present
= 1;
6315 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6318 /* Cases 0, 1, 2, 3, 5 (D only). */
6319 if (skip_past_comma (&ptr
) == FAIL
)
6322 inst
.operands
[i
].reg
= val
;
6323 inst
.operands
[i
].isreg
= 1;
6324 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6325 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6326 inst
.operands
[i
].isvec
= 1;
6327 inst
.operands
[i
].vectype
= optype
;
6328 inst
.operands
[i
++].present
= 1;
6330 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6332 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6333 Case 13: VMOV <Sd>, <Rm> */
6334 inst
.operands
[i
].reg
= val
;
6335 inst
.operands
[i
].isreg
= 1;
6336 inst
.operands
[i
].present
= 1;
6338 if (rtype
== REG_TYPE_NQ
)
6340 first_error (_("can't use Neon quad register here"));
6343 else if (rtype
!= REG_TYPE_VFS
)
6346 if (skip_past_comma (&ptr
) == FAIL
)
6348 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6350 inst
.operands
[i
].reg
= val
;
6351 inst
.operands
[i
].isreg
= 1;
6352 inst
.operands
[i
].present
= 1;
6355 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6358 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6359 Case 1: VMOV<c><q> <Dd>, <Dm>
6360 Case 8: VMOV.F32 <Sd>, <Sm>
6361 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6363 inst
.operands
[i
].reg
= val
;
6364 inst
.operands
[i
].isreg
= 1;
6365 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6366 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].vectype
= optype
;
6369 inst
.operands
[i
].present
= 1;
6371 if (skip_past_comma (&ptr
) == SUCCESS
)
6376 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6379 inst
.operands
[i
].reg
= val
;
6380 inst
.operands
[i
].isreg
= 1;
6381 inst
.operands
[i
++].present
= 1;
6383 if (skip_past_comma (&ptr
) == FAIL
)
6386 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6389 inst
.operands
[i
].reg
= val
;
6390 inst
.operands
[i
].isreg
= 1;
6391 inst
.operands
[i
].present
= 1;
6394 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6395 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6396 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6397 Case 10: VMOV.F32 <Sd>, #<imm>
6398 Case 11: VMOV.F64 <Dd>, #<imm> */
6399 inst
.operands
[i
].immisfloat
= 1;
6400 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6402 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6403 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6407 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6411 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6414 inst
.operands
[i
].reg
= val
;
6415 inst
.operands
[i
].isreg
= 1;
6416 inst
.operands
[i
++].present
= 1;
6418 if (skip_past_comma (&ptr
) == FAIL
)
6421 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6423 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6424 inst
.operands
[i
].reg
= val
;
6425 inst
.operands
[i
].isscalar
= 1;
6426 inst
.operands
[i
].present
= 1;
6427 inst
.operands
[i
].vectype
= optype
;
6429 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6431 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6432 inst
.operands
[i
].reg
= val
;
6433 inst
.operands
[i
].isreg
= 1;
6434 inst
.operands
[i
++].present
= 1;
6436 if (skip_past_comma (&ptr
) == FAIL
)
6439 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6442 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6446 inst
.operands
[i
].reg
= val
;
6447 inst
.operands
[i
].isreg
= 1;
6448 inst
.operands
[i
].isvec
= 1;
6449 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6450 inst
.operands
[i
].vectype
= optype
;
6451 inst
.operands
[i
].present
= 1;
6453 if (rtype
== REG_TYPE_VFS
)
6457 if (skip_past_comma (&ptr
) == FAIL
)
6459 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6462 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6465 inst
.operands
[i
].reg
= val
;
6466 inst
.operands
[i
].isreg
= 1;
6467 inst
.operands
[i
].isvec
= 1;
6468 inst
.operands
[i
].issingle
= 1;
6469 inst
.operands
[i
].vectype
= optype
;
6470 inst
.operands
[i
].present
= 1;
6473 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6477 inst
.operands
[i
].reg
= val
;
6478 inst
.operands
[i
].isreg
= 1;
6479 inst
.operands
[i
].isvec
= 1;
6480 inst
.operands
[i
].issingle
= 1;
6481 inst
.operands
[i
].vectype
= optype
;
6482 inst
.operands
[i
].present
= 1;
6487 first_error (_("parse error"));
6491 /* Successfully parsed the operands. Update args. */
6497 first_error (_("expected comma"));
6501 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6505 /* Use this macro when the operand constraints are different
6506 for ARM and THUMB (e.g. ldrd). */
6507 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6508 ((arm_operand) | ((thumb_operand) << 16))
6510 /* Matcher codes for parse_operands. */
6511 enum operand_parse_code
6513 OP_stop
, /* end of line */
6515 OP_RR
, /* ARM register */
6516 OP_RRnpc
, /* ARM register, not r15 */
6517 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6518 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6519 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6520 optional trailing ! */
6521 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6522 OP_RCP
, /* Coprocessor number */
6523 OP_RCN
, /* Coprocessor register */
6524 OP_RF
, /* FPA register */
6525 OP_RVS
, /* VFP single precision register */
6526 OP_RVD
, /* VFP double precision register (0..15) */
6527 OP_RND
, /* Neon double precision register (0..31) */
6528 OP_RNQ
, /* Neon quad precision register */
6529 OP_RVSD
, /* VFP single or double precision register */
6530 OP_RNSD
, /* Neon single or double precision register */
6531 OP_RNDQ
, /* Neon double or quad precision register */
6532 OP_RNSDQ
, /* Neon single, double or quad precision register */
6533 OP_RNSC
, /* Neon scalar D[X] */
6534 OP_RVC
, /* VFP control register */
6535 OP_RMF
, /* Maverick F register */
6536 OP_RMD
, /* Maverick D register */
6537 OP_RMFX
, /* Maverick FX register */
6538 OP_RMDX
, /* Maverick DX register */
6539 OP_RMAX
, /* Maverick AX register */
6540 OP_RMDS
, /* Maverick DSPSC register */
6541 OP_RIWR
, /* iWMMXt wR register */
6542 OP_RIWC
, /* iWMMXt wC register */
6543 OP_RIWG
, /* iWMMXt wCG register */
6544 OP_RXA
, /* XScale accumulator register */
6546 /* New operands for Armv8.1-M Mainline. */
6547 OP_LR
, /* ARM LR register */
6548 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6550 OP_REGLST
, /* ARM register list */
6551 OP_VRSLST
, /* VFP single-precision register list */
6552 OP_VRDLST
, /* VFP double-precision register list */
6553 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6554 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6555 OP_NSTRLST
, /* Neon element/structure list */
6557 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6558 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6559 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6560 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6561 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6562 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6563 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6564 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6565 OP_VMOV
, /* Neon VMOV operands. */
6566 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6567 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6568 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6570 OP_I0
, /* immediate zero */
6571 OP_I7
, /* immediate value 0 .. 7 */
6572 OP_I15
, /* 0 .. 15 */
6573 OP_I16
, /* 1 .. 16 */
6574 OP_I16z
, /* 0 .. 16 */
6575 OP_I31
, /* 0 .. 31 */
6576 OP_I31w
, /* 0 .. 31, optional trailing ! */
6577 OP_I32
, /* 1 .. 32 */
6578 OP_I32z
, /* 0 .. 32 */
6579 OP_I63
, /* 0 .. 63 */
6580 OP_I63s
, /* -64 .. 63 */
6581 OP_I64
, /* 1 .. 64 */
6582 OP_I64z
, /* 0 .. 64 */
6583 OP_I255
, /* 0 .. 255 */
6585 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6586 OP_I7b
, /* 0 .. 7 */
6587 OP_I15b
, /* 0 .. 15 */
6588 OP_I31b
, /* 0 .. 31 */
6590 OP_SH
, /* shifter operand */
6591 OP_SHG
, /* shifter operand with possible group relocation */
6592 OP_ADDR
, /* Memory address expression (any mode) */
6593 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6594 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6595 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6596 OP_EXP
, /* arbitrary expression */
6597 OP_EXPi
, /* same, with optional immediate prefix */
6598 OP_EXPr
, /* same, with optional relocation suffix */
6599 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6600 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6601 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6602 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6604 OP_CPSF
, /* CPS flags */
6605 OP_ENDI
, /* Endianness specifier */
6606 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6607 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6608 OP_COND
, /* conditional code */
6609 OP_TB
, /* Table branch. */
6611 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6613 OP_RRnpc_I0
, /* ARM register or literal 0 */
6614 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6615 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6616 OP_RF_IF
, /* FPA register or immediate */
6617 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6618 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6620 /* Optional operands. */
6621 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6622 OP_oI31b
, /* 0 .. 31 */
6623 OP_oI32b
, /* 1 .. 32 */
6624 OP_oI32z
, /* 0 .. 32 */
6625 OP_oIffffb
, /* 0 .. 65535 */
6626 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6628 OP_oRR
, /* ARM register */
6629 OP_oLR
, /* ARM LR register */
6630 OP_oRRnpc
, /* ARM register, not the PC */
6631 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6632 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6633 OP_oRND
, /* Optional Neon double precision register */
6634 OP_oRNQ
, /* Optional Neon quad precision register */
6635 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6636 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6637 OP_oSHll
, /* LSL immediate */
6638 OP_oSHar
, /* ASR immediate */
6639 OP_oSHllar
, /* LSL or ASR immediate */
6640 OP_oROR
, /* ROR 0/8/16/24 */
6641 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6643 /* Some pre-defined mixed (ARM/THUMB) operands. */
6644 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6645 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6646 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6648 OP_FIRST_OPTIONAL
= OP_oI7b
6651 /* Generic instruction operand parser. This does no encoding and no
6652 semantic validation; it merely squirrels values away in the inst
6653 structure. Returns SUCCESS or FAIL depending on whether the
6654 specified grammar matched. */
6656 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6658 unsigned const int *upat
= pattern
;
6659 char *backtrack_pos
= 0;
6660 const char *backtrack_error
= 0;
6661 int i
, val
= 0, backtrack_index
= 0;
6662 enum arm_reg_type rtype
;
6663 parse_operand_result result
;
6664 unsigned int op_parse_code
;
6666 #define po_char_or_fail(chr) \
6669 if (skip_past_char (&str, chr) == FAIL) \
6674 #define po_reg_or_fail(regtype) \
6677 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6678 & inst.operands[i].vectype); \
6681 first_error (_(reg_expected_msgs[regtype])); \
6684 inst.operands[i].reg = val; \
6685 inst.operands[i].isreg = 1; \
6686 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6687 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6688 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6689 || rtype == REG_TYPE_VFD \
6690 || rtype == REG_TYPE_NQ); \
6694 #define po_reg_or_goto(regtype, label) \
6697 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6698 & inst.operands[i].vectype); \
6702 inst.operands[i].reg = val; \
6703 inst.operands[i].isreg = 1; \
6704 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6705 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6706 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6707 || rtype == REG_TYPE_VFD \
6708 || rtype == REG_TYPE_NQ); \
6712 #define po_imm_or_fail(min, max, popt) \
6715 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6717 inst.operands[i].imm = val; \
6721 #define po_scalar_or_goto(elsz, label) \
6724 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6727 inst.operands[i].reg = val; \
6728 inst.operands[i].isscalar = 1; \
6732 #define po_misc_or_fail(expr) \
6740 #define po_misc_or_fail_no_backtrack(expr) \
6744 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6745 backtrack_pos = 0; \
6746 if (result != PARSE_OPERAND_SUCCESS) \
6751 #define po_barrier_or_imm(str) \
6754 val = parse_barrier (&str); \
6755 if (val == FAIL && ! ISALPHA (*str)) \
6758 /* ISB can only take SY as an option. */ \
6759 || ((inst.instruction & 0xf0) == 0x60 \
6762 inst.error = _("invalid barrier type"); \
6763 backtrack_pos = 0; \
6769 skip_whitespace (str
);
6771 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6773 op_parse_code
= upat
[i
];
6774 if (op_parse_code
>= 1<<16)
6775 op_parse_code
= thumb
? (op_parse_code
>> 16)
6776 : (op_parse_code
& ((1<<16)-1));
6778 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6780 /* Remember where we are in case we need to backtrack. */
6781 gas_assert (!backtrack_pos
);
6782 backtrack_pos
= str
;
6783 backtrack_error
= inst
.error
;
6784 backtrack_index
= i
;
6787 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6788 po_char_or_fail (',');
6790 switch (op_parse_code
)
6800 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6801 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6802 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6803 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6804 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6805 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6807 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6809 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6811 /* Also accept generic coprocessor regs for unknown registers. */
6813 po_reg_or_fail (REG_TYPE_CN
);
6815 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6816 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6817 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6818 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6819 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6820 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6821 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6822 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6823 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6824 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6826 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6827 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6829 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6830 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6832 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6834 /* Neon scalar. Using an element size of 8 means that some invalid
6835 scalars are accepted here, so deal with those in later code. */
6836 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6840 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6843 po_imm_or_fail (0, 0, TRUE
);
6848 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6853 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6856 if (parse_ifimm_zero (&str
))
6857 inst
.operands
[i
].imm
= 0;
6861 = _("only floating point zero is allowed as immediate value");
6869 po_scalar_or_goto (8, try_rr
);
6872 po_reg_or_fail (REG_TYPE_RN
);
6878 po_scalar_or_goto (8, try_nsdq
);
6881 po_reg_or_fail (REG_TYPE_NSDQ
);
6887 po_scalar_or_goto (8, try_s_scalar
);
6890 po_scalar_or_goto (4, try_nsd
);
6893 po_reg_or_fail (REG_TYPE_NSD
);
6899 po_scalar_or_goto (8, try_ndq
);
6902 po_reg_or_fail (REG_TYPE_NDQ
);
6908 po_scalar_or_goto (8, try_vfd
);
6911 po_reg_or_fail (REG_TYPE_VFD
);
6916 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6917 not careful then bad things might happen. */
6918 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6923 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6926 /* There's a possibility of getting a 64-bit immediate here, so
6927 we need special handling. */
6928 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6931 inst
.error
= _("immediate value is out of range");
6939 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6942 po_imm_or_fail (0, 63, TRUE
);
6947 po_char_or_fail ('[');
6948 po_reg_or_fail (REG_TYPE_RN
);
6949 po_char_or_fail (']');
6955 po_reg_or_fail (REG_TYPE_RN
);
6956 if (skip_past_char (&str
, '!') == SUCCESS
)
6957 inst
.operands
[i
].writeback
= 1;
6961 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6962 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6963 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6964 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6965 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6966 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6967 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6968 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6969 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6970 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6971 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6972 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6974 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6976 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6977 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6979 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6980 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6981 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6982 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6984 /* Immediate variants */
6986 po_char_or_fail ('{');
6987 po_imm_or_fail (0, 255, TRUE
);
6988 po_char_or_fail ('}');
6992 /* The expression parser chokes on a trailing !, so we have
6993 to find it first and zap it. */
6996 while (*s
&& *s
!= ',')
7001 inst
.operands
[i
].writeback
= 1;
7003 po_imm_or_fail (0, 31, TRUE
);
7011 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7016 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7021 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7023 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7025 val
= parse_reloc (&str
);
7028 inst
.error
= _("unrecognized relocation suffix");
7031 else if (val
!= BFD_RELOC_UNUSED
)
7033 inst
.operands
[i
].imm
= val
;
7034 inst
.operands
[i
].hasreloc
= 1;
7040 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7042 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7044 inst
.operands
[i
].hasreloc
= 1;
7046 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7048 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7049 inst
.operands
[i
].hasreloc
= 0;
7053 /* Operand for MOVW or MOVT. */
7055 po_misc_or_fail (parse_half (&str
));
7058 /* Register or expression. */
7059 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7060 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7062 /* Register or immediate. */
7063 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7064 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7066 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7068 if (!is_immediate_prefix (*str
))
7071 val
= parse_fpa_immediate (&str
);
7074 /* FPA immediates are encoded as registers 8-15.
7075 parse_fpa_immediate has already applied the offset. */
7076 inst
.operands
[i
].reg
= val
;
7077 inst
.operands
[i
].isreg
= 1;
7080 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7081 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7083 /* Two kinds of register. */
7086 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7088 || (rege
->type
!= REG_TYPE_MMXWR
7089 && rege
->type
!= REG_TYPE_MMXWC
7090 && rege
->type
!= REG_TYPE_MMXWCG
))
7092 inst
.error
= _("iWMMXt data or control register expected");
7095 inst
.operands
[i
].reg
= rege
->number
;
7096 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7102 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7104 || (rege
->type
!= REG_TYPE_MMXWC
7105 && rege
->type
!= REG_TYPE_MMXWCG
))
7107 inst
.error
= _("iWMMXt control register expected");
7110 inst
.operands
[i
].reg
= rege
->number
;
7111 inst
.operands
[i
].isreg
= 1;
7116 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7117 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7118 case OP_oROR
: val
= parse_ror (&str
); break;
7119 case OP_COND
: val
= parse_cond (&str
); break;
7120 case OP_oBARRIER_I15
:
7121 po_barrier_or_imm (str
); break;
7123 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7129 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7130 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7132 inst
.error
= _("Banked registers are not available with this "
7138 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7142 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7145 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7147 if (strncasecmp (str
, "APSR_", 5) == 0)
7154 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7155 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7156 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7157 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7158 default: found
= 16;
7162 inst
.operands
[i
].isvec
= 1;
7163 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7164 inst
.operands
[i
].reg
= REG_PC
;
7171 po_misc_or_fail (parse_tb (&str
));
7174 /* Register lists. */
7176 val
= parse_reg_list (&str
);
7179 inst
.operands
[i
].writeback
= 1;
7185 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7189 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7193 /* Allow Q registers too. */
7194 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7199 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7201 inst
.operands
[i
].issingle
= 1;
7206 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7211 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7212 &inst
.operands
[i
].vectype
);
7215 /* Addressing modes */
7217 po_misc_or_fail (parse_address (&str
, i
));
7221 po_misc_or_fail_no_backtrack (
7222 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7226 po_misc_or_fail_no_backtrack (
7227 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7231 po_misc_or_fail_no_backtrack (
7232 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7236 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7240 po_misc_or_fail_no_backtrack (
7241 parse_shifter_operand_group_reloc (&str
, i
));
7245 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7249 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7253 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7257 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7260 /* Various value-based sanity checks and shared operations. We
7261 do not signal immediate failures for the register constraints;
7262 this allows a syntax error to take precedence. */
7263 switch (op_parse_code
)
7271 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7272 inst
.error
= BAD_PC
;
7277 if (inst
.operands
[i
].isreg
)
7279 if (inst
.operands
[i
].reg
== REG_PC
)
7280 inst
.error
= BAD_PC
;
7281 else if (inst
.operands
[i
].reg
== REG_SP
7282 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7283 relaxed since ARMv8-A. */
7284 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7287 inst
.error
= BAD_SP
;
7293 if (inst
.operands
[i
].isreg
7294 && inst
.operands
[i
].reg
== REG_PC
7295 && (inst
.operands
[i
].writeback
|| thumb
))
7296 inst
.error
= BAD_PC
;
7305 case OP_oBARRIER_I15
:
7314 inst
.operands
[i
].imm
= val
;
7319 if (inst
.operands
[i
].reg
!= REG_LR
)
7320 inst
.error
= _("operand must be LR register");
7327 /* If we get here, this operand was successfully parsed. */
7328 inst
.operands
[i
].present
= 1;
7332 inst
.error
= BAD_ARGS
;
7337 /* The parse routine should already have set inst.error, but set a
7338 default here just in case. */
7340 inst
.error
= _("syntax error");
7344 /* Do not backtrack over a trailing optional argument that
7345 absorbed some text. We will only fail again, with the
7346 'garbage following instruction' error message, which is
7347 probably less helpful than the current one. */
7348 if (backtrack_index
== i
&& backtrack_pos
!= str
7349 && upat
[i
+1] == OP_stop
)
7352 inst
.error
= _("syntax error");
7356 /* Try again, skipping the optional argument at backtrack_pos. */
7357 str
= backtrack_pos
;
7358 inst
.error
= backtrack_error
;
7359 inst
.operands
[backtrack_index
].present
= 0;
7360 i
= backtrack_index
;
7364 /* Check that we have parsed all the arguments. */
7365 if (*str
!= '\0' && !inst
.error
)
7366 inst
.error
= _("garbage following instruction");
7368 return inst
.error
? FAIL
: SUCCESS
;
7371 #undef po_char_or_fail
7372 #undef po_reg_or_fail
7373 #undef po_reg_or_goto
7374 #undef po_imm_or_fail
7375 #undef po_scalar_or_fail
7376 #undef po_barrier_or_imm
7378 /* Shorthand macro for instruction encoding functions issuing errors. */
7379 #define constraint(expr, err) \
7390 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7391 instructions are unpredictable if these registers are used. This
7392 is the BadReg predicate in ARM's Thumb-2 documentation.
7394 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7395 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7396 #define reject_bad_reg(reg) \
7398 if (reg == REG_PC) \
7400 inst.error = BAD_PC; \
7403 else if (reg == REG_SP \
7404 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7406 inst.error = BAD_SP; \
7411 /* If REG is R13 (the stack pointer), warn that its use is
7413 #define warn_deprecated_sp(reg) \
7415 if (warn_on_deprecated && reg == REG_SP) \
7416 as_tsktsk (_("use of r13 is deprecated")); \
7419 /* Functions for operand encoding. ARM, then Thumb. */
7421 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7423 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7425 The only binary encoding difference is the Coprocessor number. Coprocessor
7426 9 is used for half-precision calculations or conversions. The format of the
7427 instruction is the same as the equivalent Coprocessor 10 instruction that
7428 exists for Single-Precision operation. */
7431 do_scalar_fp16_v82_encode (void)
7433 if (inst
.cond
!= COND_ALWAYS
)
7434 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7435 " the behaviour is UNPREDICTABLE"));
7436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7439 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7440 mark_feature_used (&arm_ext_fp16
);
7443 /* If VAL can be encoded in the immediate field of an ARM instruction,
7444 return the encoded form. Otherwise, return FAIL. */
7447 encode_arm_immediate (unsigned int val
)
7454 for (i
= 2; i
< 32; i
+= 2)
7455 if ((a
= rotate_left (val
, i
)) <= 0xff)
7456 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7461 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7462 return the encoded form. Otherwise, return FAIL. */
7464 encode_thumb32_immediate (unsigned int val
)
7471 for (i
= 1; i
<= 24; i
++)
7474 if ((val
& ~(0xff << i
)) == 0)
7475 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7479 if (val
== ((a
<< 16) | a
))
7481 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7485 if (val
== ((a
<< 16) | a
))
7486 return 0x200 | (a
>> 8);
7490 /* Encode a VFP SP or DP register number into inst.instruction. */
7493 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7495 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7498 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7501 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7504 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7509 first_error (_("D register out of range for selected VFP version"));
7517 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7521 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7525 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7529 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7533 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7537 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7545 /* Encode a <shift> in an ARM-format instruction. The immediate,
7546 if any, is handled by md_apply_fix. */
7548 encode_arm_shift (int i
)
7550 /* register-shifted register. */
7551 if (inst
.operands
[i
].immisreg
)
7554 for (op_index
= 0; op_index
<= i
; ++op_index
)
7556 /* Check the operand only when it's presented. In pre-UAL syntax,
7557 if the destination register is the same as the first operand, two
7558 register form of the instruction can be used. */
7559 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7560 && inst
.operands
[op_index
].reg
== REG_PC
)
7561 as_warn (UNPRED_REG ("r15"));
7564 if (inst
.operands
[i
].imm
== REG_PC
)
7565 as_warn (UNPRED_REG ("r15"));
7568 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7569 inst
.instruction
|= SHIFT_ROR
<< 5;
7572 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7573 if (inst
.operands
[i
].immisreg
)
7575 inst
.instruction
|= SHIFT_BY_REG
;
7576 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7579 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7584 encode_arm_shifter_operand (int i
)
7586 if (inst
.operands
[i
].isreg
)
7588 inst
.instruction
|= inst
.operands
[i
].reg
;
7589 encode_arm_shift (i
);
7593 inst
.instruction
|= INST_IMMEDIATE
;
7594 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
7595 inst
.instruction
|= inst
.operands
[i
].imm
;
7599 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7601 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7604 Generate an error if the operand is not a register. */
7605 constraint (!inst
.operands
[i
].isreg
,
7606 _("Instruction does not support =N addresses"));
7608 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7610 if (inst
.operands
[i
].preind
)
7614 inst
.error
= _("instruction does not accept preindexed addressing");
7617 inst
.instruction
|= PRE_INDEX
;
7618 if (inst
.operands
[i
].writeback
)
7619 inst
.instruction
|= WRITE_BACK
;
7622 else if (inst
.operands
[i
].postind
)
7624 gas_assert (inst
.operands
[i
].writeback
);
7626 inst
.instruction
|= WRITE_BACK
;
7628 else /* unindexed - only for coprocessor */
7630 inst
.error
= _("instruction does not accept unindexed addressing");
7634 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7635 && (((inst
.instruction
& 0x000f0000) >> 16)
7636 == ((inst
.instruction
& 0x0000f000) >> 12)))
7637 as_warn ((inst
.instruction
& LOAD_BIT
)
7638 ? _("destination register same as write-back base")
7639 : _("source register same as write-back base"));
7642 /* inst.operands[i] was set up by parse_address. Encode it into an
7643 ARM-format mode 2 load or store instruction. If is_t is true,
7644 reject forms that cannot be used with a T instruction (i.e. not
7647 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7649 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7651 encode_arm_addr_mode_common (i
, is_t
);
7653 if (inst
.operands
[i
].immisreg
)
7655 constraint ((inst
.operands
[i
].imm
== REG_PC
7656 || (is_pc
&& inst
.operands
[i
].writeback
)),
7658 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7659 inst
.instruction
|= inst
.operands
[i
].imm
;
7660 if (!inst
.operands
[i
].negative
)
7661 inst
.instruction
|= INDEX_UP
;
7662 if (inst
.operands
[i
].shifted
)
7664 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7665 inst
.instruction
|= SHIFT_ROR
<< 5;
7668 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7669 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7673 else /* immediate offset in inst.relocs[0] */
7675 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
7677 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7679 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7680 cannot use PC in addressing.
7681 PC cannot be used in writeback addressing, either. */
7682 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7685 /* Use of PC in str is deprecated for ARMv7. */
7686 if (warn_on_deprecated
7688 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7689 as_tsktsk (_("use of PC in this instruction is deprecated"));
7692 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7694 /* Prefer + for zero encoded value. */
7695 if (!inst
.operands
[i
].negative
)
7696 inst
.instruction
|= INDEX_UP
;
7697 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
7702 /* inst.operands[i] was set up by parse_address. Encode it into an
7703 ARM-format mode 3 load or store instruction. Reject forms that
7704 cannot be used with such instructions. If is_t is true, reject
7705 forms that cannot be used with a T instruction (i.e. not
7708 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7710 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7712 inst
.error
= _("instruction does not accept scaled register index");
7716 encode_arm_addr_mode_common (i
, is_t
);
7718 if (inst
.operands
[i
].immisreg
)
7720 constraint ((inst
.operands
[i
].imm
== REG_PC
7721 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7723 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7725 inst
.instruction
|= inst
.operands
[i
].imm
;
7726 if (!inst
.operands
[i
].negative
)
7727 inst
.instruction
|= INDEX_UP
;
7729 else /* immediate offset in inst.relocs[0] */
7731 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
7732 && inst
.operands
[i
].writeback
),
7734 inst
.instruction
|= HWOFFSET_IMM
;
7735 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7737 /* Prefer + for zero encoded value. */
7738 if (!inst
.operands
[i
].negative
)
7739 inst
.instruction
|= INDEX_UP
;
7741 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7746 /* Write immediate bits [7:0] to the following locations:
7748 |28/24|23 19|18 16|15 4|3 0|
7749 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7751 This function is used by VMOV/VMVN/VORR/VBIC. */
7754 neon_write_immbits (unsigned immbits
)
7756 inst
.instruction
|= immbits
& 0xf;
7757 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7758 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7761 /* Invert low-order SIZE bits of XHI:XLO. */
7764 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7766 unsigned immlo
= xlo
? *xlo
: 0;
7767 unsigned immhi
= xhi
? *xhi
: 0;
7772 immlo
= (~immlo
) & 0xff;
7776 immlo
= (~immlo
) & 0xffff;
7780 immhi
= (~immhi
) & 0xffffffff;
7784 immlo
= (~immlo
) & 0xffffffff;
7798 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7802 neon_bits_same_in_bytes (unsigned imm
)
7804 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7805 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7806 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7807 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7810 /* For immediate of above form, return 0bABCD. */
7813 neon_squash_bits (unsigned imm
)
7815 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7816 | ((imm
& 0x01000000) >> 21);
7819 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7822 neon_qfloat_bits (unsigned imm
)
7824 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7827 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7828 the instruction. *OP is passed as the initial value of the op field, and
7829 may be set to a different value depending on the constant (i.e.
7830 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7831 MVN). If the immediate looks like a repeated pattern then also
7832 try smaller element sizes. */
7835 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7836 unsigned *immbits
, int *op
, int size
,
7837 enum neon_el_type type
)
7839 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7841 if (type
== NT_float
&& !float_p
)
7844 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7846 if (size
!= 32 || *op
== 1)
7848 *immbits
= neon_qfloat_bits (immlo
);
7854 if (neon_bits_same_in_bytes (immhi
)
7855 && neon_bits_same_in_bytes (immlo
))
7859 *immbits
= (neon_squash_bits (immhi
) << 4)
7860 | neon_squash_bits (immlo
);
7871 if (immlo
== (immlo
& 0x000000ff))
7876 else if (immlo
== (immlo
& 0x0000ff00))
7878 *immbits
= immlo
>> 8;
7881 else if (immlo
== (immlo
& 0x00ff0000))
7883 *immbits
= immlo
>> 16;
7886 else if (immlo
== (immlo
& 0xff000000))
7888 *immbits
= immlo
>> 24;
7891 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7893 *immbits
= (immlo
>> 8) & 0xff;
7896 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7898 *immbits
= (immlo
>> 16) & 0xff;
7902 if ((immlo
& 0xffff) != (immlo
>> 16))
7909 if (immlo
== (immlo
& 0x000000ff))
7914 else if (immlo
== (immlo
& 0x0000ff00))
7916 *immbits
= immlo
>> 8;
7920 if ((immlo
& 0xff) != (immlo
>> 8))
7925 if (immlo
== (immlo
& 0x000000ff))
7927 /* Don't allow MVN with 8-bit immediate. */
7937 #if defined BFD_HOST_64_BIT
7938 /* Returns TRUE if double precision value V may be cast
7939 to single precision without loss of accuracy. */
7942 is_double_a_single (bfd_int64_t v
)
7944 int exp
= (int)((v
>> 52) & 0x7FF);
7945 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7947 return (exp
== 0 || exp
== 0x7FF
7948 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7949 && (mantissa
& 0x1FFFFFFFl
) == 0;
7952 /* Returns a double precision value casted to single precision
7953 (ignoring the least significant bits in exponent and mantissa). */
7956 double_to_single (bfd_int64_t v
)
7958 int sign
= (int) ((v
>> 63) & 1l);
7959 int exp
= (int) ((v
>> 52) & 0x7FF);
7960 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7966 exp
= exp
- 1023 + 127;
7975 /* No denormalized numbers. */
7981 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7983 #endif /* BFD_HOST_64_BIT */
7992 static void do_vfp_nsyn_opcode (const char *);
7994 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
7995 Determine whether it can be performed with a move instruction; if
7996 it can, convert inst.instruction to that move instruction and
7997 return TRUE; if it can't, convert inst.instruction to a literal-pool
7998 load and return FALSE. If this is not a valid thing to do in the
7999 current context, set inst.error and return TRUE.
8001 inst.operands[i] describes the destination register. */
8004 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8007 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8008 bfd_boolean arm_p
= (t
== CONST_ARM
);
8011 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8015 if ((inst
.instruction
& tbit
) == 0)
8017 inst
.error
= _("invalid pseudo operation");
8021 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8022 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8023 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8025 inst
.error
= _("constant expression expected");
8029 if (inst
.relocs
[0].exp
.X_op
== O_constant
8030 || inst
.relocs
[0].exp
.X_op
== O_big
)
8032 #if defined BFD_HOST_64_BIT
8037 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8039 LITTLENUM_TYPE w
[X_PRECISION
];
8042 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8044 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8046 /* FIXME: Should we check words w[2..5] ? */
8051 #if defined BFD_HOST_64_BIT
8053 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8054 << LITTLENUM_NUMBER_OF_BITS
)
8055 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8056 << LITTLENUM_NUMBER_OF_BITS
)
8057 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8058 << LITTLENUM_NUMBER_OF_BITS
)
8059 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8061 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8062 | (l
[0] & LITTLENUM_MASK
);
8066 v
= inst
.relocs
[0].exp
.X_add_number
;
8068 if (!inst
.operands
[i
].issingle
)
8072 /* LDR should not use lead in a flag-setting instruction being
8073 chosen so we do not check whether movs can be used. */
8075 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8076 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8077 && inst
.operands
[i
].reg
!= 13
8078 && inst
.operands
[i
].reg
!= 15)
8080 /* Check if on thumb2 it can be done with a mov.w, mvn or
8081 movw instruction. */
8082 unsigned int newimm
;
8083 bfd_boolean isNegated
;
8085 newimm
= encode_thumb32_immediate (v
);
8086 if (newimm
!= (unsigned int) FAIL
)
8090 newimm
= encode_thumb32_immediate (~v
);
8091 if (newimm
!= (unsigned int) FAIL
)
8095 /* The number can be loaded with a mov.w or mvn
8097 if (newimm
!= (unsigned int) FAIL
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8100 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8101 | (inst
.operands
[i
].reg
<< 8));
8102 /* Change to MOVN. */
8103 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8104 inst
.instruction
|= (newimm
& 0x800) << 15;
8105 inst
.instruction
|= (newimm
& 0x700) << 4;
8106 inst
.instruction
|= (newimm
& 0x0ff);
8109 /* The number can be loaded with a movw instruction. */
8110 else if ((v
& ~0xFFFF) == 0
8111 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8113 int imm
= v
& 0xFFFF;
8115 inst
.instruction
= 0xf2400000; /* MOVW. */
8116 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8117 inst
.instruction
|= (imm
& 0xf000) << 4;
8118 inst
.instruction
|= (imm
& 0x0800) << 15;
8119 inst
.instruction
|= (imm
& 0x0700) << 4;
8120 inst
.instruction
|= (imm
& 0x00ff);
8127 int value
= encode_arm_immediate (v
);
8131 /* This can be done with a mov instruction. */
8132 inst
.instruction
&= LITERAL_MASK
;
8133 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8134 inst
.instruction
|= value
& 0xfff;
8138 value
= encode_arm_immediate (~ v
);
8141 /* This can be done with a mvn instruction. */
8142 inst
.instruction
&= LITERAL_MASK
;
8143 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8144 inst
.instruction
|= value
& 0xfff;
8148 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8151 unsigned immbits
= 0;
8152 unsigned immlo
= inst
.operands
[1].imm
;
8153 unsigned immhi
= inst
.operands
[1].regisimm
8154 ? inst
.operands
[1].reg
8155 : inst
.relocs
[0].exp
.X_unsigned
8157 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8158 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8159 &op
, 64, NT_invtype
);
8163 neon_invert_size (&immlo
, &immhi
, 64);
8165 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8166 &op
, 64, NT_invtype
);
8171 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8177 /* Fill other bits in vmov encoding for both thumb and arm. */
8179 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8181 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8182 neon_write_immbits (immbits
);
8190 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8191 if (inst
.operands
[i
].issingle
8192 && is_quarter_float (inst
.operands
[1].imm
)
8193 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8195 inst
.operands
[1].imm
=
8196 neon_qfloat_bits (v
);
8197 do_vfp_nsyn_opcode ("fconsts");
8201 /* If our host does not support a 64-bit type then we cannot perform
8202 the following optimization. This mean that there will be a
8203 discrepancy between the output produced by an assembler built for
8204 a 32-bit-only host and the output produced from a 64-bit host, but
8205 this cannot be helped. */
8206 #if defined BFD_HOST_64_BIT
8207 else if (!inst
.operands
[1].issingle
8208 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8210 if (is_double_a_single (v
)
8211 && is_quarter_float (double_to_single (v
)))
8213 inst
.operands
[1].imm
=
8214 neon_qfloat_bits (double_to_single (v
));
8215 do_vfp_nsyn_opcode ("fconstd");
8223 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8224 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8227 inst
.operands
[1].reg
= REG_PC
;
8228 inst
.operands
[1].isreg
= 1;
8229 inst
.operands
[1].preind
= 1;
8230 inst
.relocs
[0].pc_rel
= 1;
8231 inst
.relocs
[0].type
= (thumb_p
8232 ? BFD_RELOC_ARM_THUMB_OFFSET
8234 ? BFD_RELOC_ARM_HWLITERAL
8235 : BFD_RELOC_ARM_LITERAL
));
8239 /* inst.operands[i] was set up by parse_address. Encode it into an
8240 ARM-format instruction. Reject all forms which cannot be encoded
8241 into a coprocessor load/store instruction. If wb_ok is false,
8242 reject use of writeback; if unind_ok is false, reject use of
8243 unindexed addressing. If reloc_override is not 0, use it instead
8244 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8245 (in which case it is preserved). */
8248 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8250 if (!inst
.operands
[i
].isreg
)
8253 if (! inst
.operands
[0].isvec
)
8255 inst
.error
= _("invalid co-processor operand");
8258 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8262 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8264 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8266 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8268 gas_assert (!inst
.operands
[i
].writeback
);
8271 inst
.error
= _("instruction does not support unindexed addressing");
8274 inst
.instruction
|= inst
.operands
[i
].imm
;
8275 inst
.instruction
|= INDEX_UP
;
8279 if (inst
.operands
[i
].preind
)
8280 inst
.instruction
|= PRE_INDEX
;
8282 if (inst
.operands
[i
].writeback
)
8284 if (inst
.operands
[i
].reg
== REG_PC
)
8286 inst
.error
= _("pc may not be used with write-back");
8291 inst
.error
= _("instruction does not support writeback");
8294 inst
.instruction
|= WRITE_BACK
;
8298 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8299 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8300 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8301 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8304 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8306 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8309 /* Prefer + for zero encoded value. */
8310 if (!inst
.operands
[i
].negative
)
8311 inst
.instruction
|= INDEX_UP
;
8316 /* Functions for instruction encoding, sorted by sub-architecture.
8317 First some generics; their names are taken from the conventional
8318 bit positions for register arguments in ARM format instructions. */
8328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8334 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8341 inst
.instruction
|= inst
.operands
[1].reg
;
8347 inst
.instruction
|= inst
.operands
[0].reg
;
8348 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8355 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8361 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8362 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8368 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8369 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8373 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8375 if (ARM_CPU_IS_ANY (cpu_variant
))
8377 as_tsktsk ("%s", msg
);
8380 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8392 unsigned Rn
= inst
.operands
[2].reg
;
8393 /* Enforce restrictions on SWP instruction. */
8394 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8396 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8397 _("Rn must not overlap other operands"));
8399 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8401 if (!check_obsolete (&arm_ext_v8
,
8402 _("swp{b} use is obsoleted for ARMv8 and later"))
8403 && warn_on_deprecated
8404 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8405 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8409 inst
.instruction
|= inst
.operands
[1].reg
;
8410 inst
.instruction
|= Rn
<< 16;
8416 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8417 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8418 inst
.instruction
|= inst
.operands
[2].reg
;
8424 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8425 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8426 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8427 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8429 inst
.instruction
|= inst
.operands
[0].reg
;
8430 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8431 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8437 inst
.instruction
|= inst
.operands
[0].imm
;
8443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8444 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8447 /* ARM instructions, in alphabetical order by function name (except
8448 that wrapper functions appear immediately after the function they
8451 /* This is a pseudo-op of the form "adr rd, label" to be converted
8452 into a relative address of the form "add rd, pc, #label-.-8". */
8457 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8459 /* Frag hacking will turn this into a sub instruction if the offset turns
8460 out to be negative. */
8461 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8462 inst
.relocs
[0].pc_rel
= 1;
8463 inst
.relocs
[0].exp
.X_add_number
-= 8;
8465 if (support_interwork
8466 && inst
.relocs
[0].exp
.X_op
== O_symbol
8467 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8468 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8469 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8470 inst
.relocs
[0].exp
.X_add_number
|= 1;
8473 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8474 into a relative address of the form:
8475 add rd, pc, #low(label-.-8)"
8476 add rd, rd, #high(label-.-8)" */
8481 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8483 /* Frag hacking will turn this into a sub instruction if the offset turns
8484 out to be negative. */
8485 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8486 inst
.relocs
[0].pc_rel
= 1;
8487 inst
.size
= INSN_SIZE
* 2;
8488 inst
.relocs
[0].exp
.X_add_number
-= 8;
8490 if (support_interwork
8491 && inst
.relocs
[0].exp
.X_op
== O_symbol
8492 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8493 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8494 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8495 inst
.relocs
[0].exp
.X_add_number
|= 1;
8501 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8502 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8504 if (!inst
.operands
[1].present
)
8505 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8506 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8507 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8508 encode_arm_shifter_operand (2);
8514 if (inst
.operands
[0].present
)
8515 inst
.instruction
|= inst
.operands
[0].imm
;
8517 inst
.instruction
|= 0xf;
8523 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8524 constraint (msb
> 32, _("bit-field extends past end of register"));
8525 /* The instruction encoding stores the LSB and MSB,
8526 not the LSB and width. */
8527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8528 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8529 inst
.instruction
|= (msb
- 1) << 16;
8537 /* #0 in second position is alternative syntax for bfc, which is
8538 the same instruction but with REG_PC in the Rm field. */
8539 if (!inst
.operands
[1].isreg
)
8540 inst
.operands
[1].reg
= REG_PC
;
8542 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8543 constraint (msb
> 32, _("bit-field extends past end of register"));
8544 /* The instruction encoding stores the LSB and MSB,
8545 not the LSB and width. */
8546 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8547 inst
.instruction
|= inst
.operands
[1].reg
;
8548 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8549 inst
.instruction
|= (msb
- 1) << 16;
8555 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8556 _("bit-field extends past end of register"));
8557 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8558 inst
.instruction
|= inst
.operands
[1].reg
;
8559 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8560 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8563 /* ARM V5 breakpoint instruction (argument parse)
8564 BKPT <16 bit unsigned immediate>
8565 Instruction is not conditional.
8566 The bit pattern given in insns[] has the COND_ALWAYS condition,
8567 and it is an error if the caller tried to override that. */
8572 /* Top 12 of 16 bits to bits 19:8. */
8573 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8575 /* Bottom 4 of 16 bits to bits 3:0. */
8576 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8580 encode_branch (int default_reloc
)
8582 if (inst
.operands
[0].hasreloc
)
8584 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8585 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8586 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8587 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8588 ? BFD_RELOC_ARM_PLT32
8589 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8592 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
8593 inst
.relocs
[0].pc_rel
= 1;
8600 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8601 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8604 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8611 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8613 if (inst
.cond
== COND_ALWAYS
)
8614 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8616 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8620 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8623 /* ARM V5 branch-link-exchange instruction (argument parse)
8624 BLX <target_addr> ie BLX(1)
8625 BLX{<condition>} <Rm> ie BLX(2)
8626 Unfortunately, there are two different opcodes for this mnemonic.
8627 So, the insns[].value is not used, and the code here zaps values
8628 into inst.instruction.
8629 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8634 if (inst
.operands
[0].isreg
)
8636 /* Arg is a register; the opcode provided by insns[] is correct.
8637 It is not illegal to do "blx pc", just useless. */
8638 if (inst
.operands
[0].reg
== REG_PC
)
8639 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8641 inst
.instruction
|= inst
.operands
[0].reg
;
8645 /* Arg is an address; this instruction cannot be executed
8646 conditionally, and the opcode must be adjusted.
8647 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8648 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8649 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8650 inst
.instruction
= 0xfa000000;
8651 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8658 bfd_boolean want_reloc
;
8660 if (inst
.operands
[0].reg
== REG_PC
)
8661 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8663 inst
.instruction
|= inst
.operands
[0].reg
;
8664 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8665 it is for ARMv4t or earlier. */
8666 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8667 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8668 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8672 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8677 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
8681 /* ARM v5TEJ. Jump to Jazelle code. */
8686 if (inst
.operands
[0].reg
== REG_PC
)
8687 as_tsktsk (_("use of r15 in bxj is not really useful"));
8689 inst
.instruction
|= inst
.operands
[0].reg
;
8692 /* Co-processor data operation:
8693 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8694 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8698 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8699 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8700 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8701 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8702 inst
.instruction
|= inst
.operands
[4].reg
;
8703 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8709 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8710 encode_arm_shifter_operand (1);
8713 /* Transfer between coprocessor and ARM registers.
8714 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8719 No special properties. */
8721 struct deprecated_coproc_regs_s
8728 arm_feature_set deprecated
;
8729 arm_feature_set obsoleted
;
8730 const char *dep_msg
;
8731 const char *obs_msg
;
8734 #define DEPR_ACCESS_V8 \
8735 N_("This coprocessor register access is deprecated in ARMv8")
8737 /* Table of all deprecated coprocessor registers. */
8738 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8740 {15, 0, 7, 10, 5, /* CP15DMB. */
8741 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8742 DEPR_ACCESS_V8
, NULL
},
8743 {15, 0, 7, 10, 4, /* CP15DSB. */
8744 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8745 DEPR_ACCESS_V8
, NULL
},
8746 {15, 0, 7, 5, 4, /* CP15ISB. */
8747 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8748 DEPR_ACCESS_V8
, NULL
},
8749 {14, 6, 1, 0, 0, /* TEEHBR. */
8750 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8751 DEPR_ACCESS_V8
, NULL
},
8752 {14, 6, 0, 0, 0, /* TEECR. */
8753 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8754 DEPR_ACCESS_V8
, NULL
},
8757 #undef DEPR_ACCESS_V8
8759 static const size_t deprecated_coproc_reg_count
=
8760 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8768 Rd
= inst
.operands
[2].reg
;
8771 if (inst
.instruction
== 0xee000010
8772 || inst
.instruction
== 0xfe000010)
8774 reject_bad_reg (Rd
);
8775 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8777 constraint (Rd
== REG_SP
, BAD_SP
);
8782 if (inst
.instruction
== 0xe000010)
8783 constraint (Rd
== REG_PC
, BAD_PC
);
8786 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8788 const struct deprecated_coproc_regs_s
*r
=
8789 deprecated_coproc_regs
+ i
;
8791 if (inst
.operands
[0].reg
== r
->cp
8792 && inst
.operands
[1].imm
== r
->opc1
8793 && inst
.operands
[3].reg
== r
->crn
8794 && inst
.operands
[4].reg
== r
->crm
8795 && inst
.operands
[5].imm
== r
->opc2
)
8797 if (! ARM_CPU_IS_ANY (cpu_variant
)
8798 && warn_on_deprecated
8799 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8800 as_tsktsk ("%s", r
->dep_msg
);
8804 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8805 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8806 inst
.instruction
|= Rd
<< 12;
8807 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8808 inst
.instruction
|= inst
.operands
[4].reg
;
8809 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8812 /* Transfer between coprocessor register and pair of ARM registers.
8813 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8818 Two XScale instructions are special cases of these:
8820 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8821 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8823 Result unpredictable if Rd or Rn is R15. */
8830 Rd
= inst
.operands
[2].reg
;
8831 Rn
= inst
.operands
[3].reg
;
8835 reject_bad_reg (Rd
);
8836 reject_bad_reg (Rn
);
8840 constraint (Rd
== REG_PC
, BAD_PC
);
8841 constraint (Rn
== REG_PC
, BAD_PC
);
8844 /* Only check the MRRC{2} variants. */
8845 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8847 /* If Rd == Rn, error that the operation is
8848 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8849 constraint (Rd
== Rn
, BAD_OVERLAP
);
8852 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8853 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8854 inst
.instruction
|= Rd
<< 12;
8855 inst
.instruction
|= Rn
<< 16;
8856 inst
.instruction
|= inst
.operands
[4].reg
;
8862 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8863 if (inst
.operands
[1].present
)
8865 inst
.instruction
|= CPSI_MMOD
;
8866 inst
.instruction
|= inst
.operands
[1].imm
;
8873 inst
.instruction
|= inst
.operands
[0].imm
;
8879 unsigned Rd
, Rn
, Rm
;
8881 Rd
= inst
.operands
[0].reg
;
8882 Rn
= (inst
.operands
[1].present
8883 ? inst
.operands
[1].reg
: Rd
);
8884 Rm
= inst
.operands
[2].reg
;
8886 constraint ((Rd
== REG_PC
), BAD_PC
);
8887 constraint ((Rn
== REG_PC
), BAD_PC
);
8888 constraint ((Rm
== REG_PC
), BAD_PC
);
8890 inst
.instruction
|= Rd
<< 16;
8891 inst
.instruction
|= Rn
<< 0;
8892 inst
.instruction
|= Rm
<< 8;
8898 /* There is no IT instruction in ARM mode. We
8899 process it to do the validation as if in
8900 thumb mode, just in case the code gets
8901 assembled for thumb using the unified syntax. */
8906 set_it_insn_type (IT_INSN
);
8907 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8908 now_it
.cc
= inst
.operands
[0].imm
;
8912 /* If there is only one register in the register list,
8913 then return its register number. Otherwise return -1. */
8915 only_one_reg_in_list (int range
)
8917 int i
= ffs (range
) - 1;
8918 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8922 encode_ldmstm(int from_push_pop_mnem
)
8924 int base_reg
= inst
.operands
[0].reg
;
8925 int range
= inst
.operands
[1].imm
;
8928 inst
.instruction
|= base_reg
<< 16;
8929 inst
.instruction
|= range
;
8931 if (inst
.operands
[1].writeback
)
8932 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8934 if (inst
.operands
[0].writeback
)
8936 inst
.instruction
|= WRITE_BACK
;
8937 /* Check for unpredictable uses of writeback. */
8938 if (inst
.instruction
& LOAD_BIT
)
8940 /* Not allowed in LDM type 2. */
8941 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8942 && ((range
& (1 << REG_PC
)) == 0))
8943 as_warn (_("writeback of base register is UNPREDICTABLE"));
8944 /* Only allowed if base reg not in list for other types. */
8945 else if (range
& (1 << base_reg
))
8946 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8950 /* Not allowed for type 2. */
8951 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8952 as_warn (_("writeback of base register is UNPREDICTABLE"));
8953 /* Only allowed if base reg not in list, or first in list. */
8954 else if ((range
& (1 << base_reg
))
8955 && (range
& ((1 << base_reg
) - 1)))
8956 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8960 /* If PUSH/POP has only one register, then use the A2 encoding. */
8961 one_reg
= only_one_reg_in_list (range
);
8962 if (from_push_pop_mnem
&& one_reg
>= 0)
8964 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8966 if (is_push
&& one_reg
== 13 /* SP */)
8967 /* PR 22483: The A2 encoding cannot be used when
8968 pushing the stack pointer as this is UNPREDICTABLE. */
8971 inst
.instruction
&= A_COND_MASK
;
8972 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8973 inst
.instruction
|= one_reg
<< 12;
8980 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8983 /* ARMv5TE load-consecutive (argument parse)
8992 constraint (inst
.operands
[0].reg
% 2 != 0,
8993 _("first transfer register must be even"));
8994 constraint (inst
.operands
[1].present
8995 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8996 _("can only transfer two consecutive registers"));
8997 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8998 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9000 if (!inst
.operands
[1].present
)
9001 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9003 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9004 register and the first register written; we have to diagnose
9005 overlap between the base and the second register written here. */
9007 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9008 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9009 as_warn (_("base register written back, and overlaps "
9010 "second transfer register"));
9012 if (!(inst
.instruction
& V4_STR_BIT
))
9014 /* For an index-register load, the index register must not overlap the
9015 destination (even if not write-back). */
9016 if (inst
.operands
[2].immisreg
9017 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9018 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9019 as_warn (_("index register overlaps transfer register"));
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9028 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9029 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9030 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9031 || inst
.operands
[1].negative
9032 /* This can arise if the programmer has written
9034 or if they have mistakenly used a register name as the last
9037 It is very difficult to distinguish between these two cases
9038 because "rX" might actually be a label. ie the register
9039 name has been occluded by a symbol of the same name. So we
9040 just generate a general 'bad addressing mode' type error
9041 message and leave it up to the programmer to discover the
9042 true cause and fix their mistake. */
9043 || (inst
.operands
[1].reg
== REG_PC
),
9046 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9047 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9048 _("offset must be zero in ARM encoding"));
9050 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9053 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9054 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9060 constraint (inst
.operands
[0].reg
% 2 != 0,
9061 _("even register required"));
9062 constraint (inst
.operands
[1].present
9063 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9064 _("can only load two consecutive registers"));
9065 /* If op 1 were present and equal to PC, this function wouldn't
9066 have been called in the first place. */
9067 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9070 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9073 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9074 which is not a multiple of four is UNPREDICTABLE. */
9076 check_ldr_r15_aligned (void)
9078 constraint (!(inst
.operands
[1].immisreg
)
9079 && (inst
.operands
[0].reg
== REG_PC
9080 && inst
.operands
[1].reg
== REG_PC
9081 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9082 _("ldr to register 15 must be 4-byte aligned"));
9088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9089 if (!inst
.operands
[1].isreg
)
9090 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9092 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9093 check_ldr_r15_aligned ();
9099 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9101 if (inst
.operands
[1].preind
)
9103 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9104 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9105 _("this instruction requires a post-indexed address"));
9107 inst
.operands
[1].preind
= 0;
9108 inst
.operands
[1].postind
= 1;
9109 inst
.operands
[1].writeback
= 1;
9111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9112 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9115 /* Halfword and signed-byte load/store operations. */
9120 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9122 if (!inst
.operands
[1].isreg
)
9123 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9125 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9131 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9133 if (inst
.operands
[1].preind
)
9135 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9136 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9137 _("this instruction requires a post-indexed address"));
9139 inst
.operands
[1].preind
= 0;
9140 inst
.operands
[1].postind
= 1;
9141 inst
.operands
[1].writeback
= 1;
9143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9144 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9147 /* Co-processor register load/store.
9148 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9152 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9153 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9154 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9160 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9161 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9162 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9163 && !(inst
.instruction
& 0x00400000))
9164 as_tsktsk (_("Rd and Rm should be different in mla"));
9166 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9167 inst
.instruction
|= inst
.operands
[1].reg
;
9168 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9169 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9175 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9176 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9178 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9179 encode_arm_shifter_operand (1);
9182 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9189 top
= (inst
.instruction
& 0x00400000) != 0;
9190 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9191 _(":lower16: not allowed in this instruction"));
9192 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9193 _(":upper16: not allowed in this instruction"));
9194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9195 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9197 imm
= inst
.relocs
[0].exp
.X_add_number
;
9198 /* The value is in two pieces: 0:11, 16:19. */
9199 inst
.instruction
|= (imm
& 0x00000fff);
9200 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9205 do_vfp_nsyn_mrs (void)
9207 if (inst
.operands
[0].isvec
)
9209 if (inst
.operands
[1].reg
!= 1)
9210 first_error (_("operand 1 must be FPSCR"));
9211 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9212 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9213 do_vfp_nsyn_opcode ("fmstat");
9215 else if (inst
.operands
[1].isvec
)
9216 do_vfp_nsyn_opcode ("fmrx");
9224 do_vfp_nsyn_msr (void)
9226 if (inst
.operands
[0].isvec
)
9227 do_vfp_nsyn_opcode ("fmxr");
9237 unsigned Rt
= inst
.operands
[0].reg
;
9239 if (thumb_mode
&& Rt
== REG_SP
)
9241 inst
.error
= BAD_SP
;
9245 /* MVFR2 is only valid at ARMv8-A. */
9246 if (inst
.operands
[1].reg
== 5)
9247 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9250 /* APSR_ sets isvec. All other refs to PC are illegal. */
9251 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9253 inst
.error
= BAD_PC
;
9257 /* If we get through parsing the register name, we just insert the number
9258 generated into the instruction without further validation. */
9259 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9260 inst
.instruction
|= (Rt
<< 12);
9266 unsigned Rt
= inst
.operands
[1].reg
;
9269 reject_bad_reg (Rt
);
9270 else if (Rt
== REG_PC
)
9272 inst
.error
= BAD_PC
;
9276 /* MVFR2 is only valid for ARMv8-A. */
9277 if (inst
.operands
[0].reg
== 5)
9278 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9281 /* If we get through parsing the register name, we just insert the number
9282 generated into the instruction without further validation. */
9283 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9284 inst
.instruction
|= (Rt
<< 12);
9292 if (do_vfp_nsyn_mrs () == SUCCESS
)
9295 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9298 if (inst
.operands
[1].isreg
)
9300 br
= inst
.operands
[1].reg
;
9301 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9302 as_bad (_("bad register for mrs"));
9306 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9307 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9309 _("'APSR', 'CPSR' or 'SPSR' expected"));
9310 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9313 inst
.instruction
|= br
;
9316 /* Two possible forms:
9317 "{C|S}PSR_<field>, Rm",
9318 "{C|S}PSR_f, #expression". */
9323 if (do_vfp_nsyn_msr () == SUCCESS
)
9326 inst
.instruction
|= inst
.operands
[0].imm
;
9327 if (inst
.operands
[1].isreg
)
9328 inst
.instruction
|= inst
.operands
[1].reg
;
9331 inst
.instruction
|= INST_IMMEDIATE
;
9332 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9333 inst
.relocs
[0].pc_rel
= 0;
9340 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9342 if (!inst
.operands
[2].present
)
9343 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9344 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9345 inst
.instruction
|= inst
.operands
[1].reg
;
9346 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9348 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9349 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9350 as_tsktsk (_("Rd and Rm should be different in mul"));
9353 /* Long Multiply Parser
9354 UMULL RdLo, RdHi, Rm, Rs
9355 SMULL RdLo, RdHi, Rm, Rs
9356 UMLAL RdLo, RdHi, Rm, Rs
9357 SMLAL RdLo, RdHi, Rm, Rs. */
9362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9363 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9364 inst
.instruction
|= inst
.operands
[2].reg
;
9365 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9367 /* rdhi and rdlo must be different. */
9368 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9369 as_tsktsk (_("rdhi and rdlo must be different"));
9371 /* rdhi, rdlo and rm must all be different before armv6. */
9372 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9373 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9374 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9375 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9381 if (inst
.operands
[0].present
9382 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9384 /* Architectural NOP hints are CPSR sets with no bits selected. */
9385 inst
.instruction
&= 0xf0000000;
9386 inst
.instruction
|= 0x0320f000;
9387 if (inst
.operands
[0].present
)
9388 inst
.instruction
|= inst
.operands
[0].imm
;
9392 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9393 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9394 Condition defaults to COND_ALWAYS.
9395 Error if Rd, Rn or Rm are R15. */
9400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9401 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9402 inst
.instruction
|= inst
.operands
[2].reg
;
9403 if (inst
.operands
[3].present
)
9404 encode_arm_shift (3);
9407 /* ARM V6 PKHTB (Argument Parse). */
9412 if (!inst
.operands
[3].present
)
9414 /* If the shift specifier is omitted, turn the instruction
9415 into pkhbt rd, rm, rn. */
9416 inst
.instruction
&= 0xfff00010;
9417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9418 inst
.instruction
|= inst
.operands
[1].reg
;
9419 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9424 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9425 inst
.instruction
|= inst
.operands
[2].reg
;
9426 encode_arm_shift (3);
9430 /* ARMv5TE: Preload-Cache
9431 MP Extensions: Preload for write
9435 Syntactically, like LDR with B=1, W=0, L=1. */
9440 constraint (!inst
.operands
[0].isreg
,
9441 _("'[' expected after PLD mnemonic"));
9442 constraint (inst
.operands
[0].postind
,
9443 _("post-indexed expression used in preload instruction"));
9444 constraint (inst
.operands
[0].writeback
,
9445 _("writeback used in preload instruction"));
9446 constraint (!inst
.operands
[0].preind
,
9447 _("unindexed addressing used in preload instruction"));
9448 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9451 /* ARMv7: PLI <addr_mode> */
9455 constraint (!inst
.operands
[0].isreg
,
9456 _("'[' expected after PLI mnemonic"));
9457 constraint (inst
.operands
[0].postind
,
9458 _("post-indexed expression used in preload instruction"));
9459 constraint (inst
.operands
[0].writeback
,
9460 _("writeback used in preload instruction"));
9461 constraint (!inst
.operands
[0].preind
,
9462 _("unindexed addressing used in preload instruction"));
9463 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9464 inst
.instruction
&= ~PRE_INDEX
;
9470 constraint (inst
.operands
[0].writeback
,
9471 _("push/pop do not support {reglist}^"));
9472 inst
.operands
[1] = inst
.operands
[0];
9473 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9474 inst
.operands
[0].isreg
= 1;
9475 inst
.operands
[0].writeback
= 1;
9476 inst
.operands
[0].reg
= REG_SP
;
9477 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9480 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9481 word at the specified address and the following word
9483 Unconditionally executed.
9484 Error if Rn is R15. */
9489 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9490 if (inst
.operands
[0].writeback
)
9491 inst
.instruction
|= WRITE_BACK
;
9494 /* ARM V6 ssat (argument parse). */
9499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9500 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9501 inst
.instruction
|= inst
.operands
[2].reg
;
9503 if (inst
.operands
[3].present
)
9504 encode_arm_shift (3);
9507 /* ARM V6 usat (argument parse). */
9512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9513 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9514 inst
.instruction
|= inst
.operands
[2].reg
;
9516 if (inst
.operands
[3].present
)
9517 encode_arm_shift (3);
9520 /* ARM V6 ssat16 (argument parse). */
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9526 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9527 inst
.instruction
|= inst
.operands
[2].reg
;
9533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9534 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9535 inst
.instruction
|= inst
.operands
[2].reg
;
9538 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9539 preserving the other bits.
9541 setend <endian_specifier>, where <endian_specifier> is either
9547 if (warn_on_deprecated
9548 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9549 as_tsktsk (_("setend use is deprecated for ARMv8"));
9551 if (inst
.operands
[0].imm
)
9552 inst
.instruction
|= 0x200;
9558 unsigned int Rm
= (inst
.operands
[1].present
9559 ? inst
.operands
[1].reg
9560 : inst
.operands
[0].reg
);
9562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9563 inst
.instruction
|= Rm
;
9564 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9566 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9567 inst
.instruction
|= SHIFT_BY_REG
;
9568 /* PR 12854: Error on extraneous shifts. */
9569 constraint (inst
.operands
[2].shifted
,
9570 _("extraneous shift as part of operand to shift insn"));
9573 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
9579 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
9580 inst
.relocs
[0].pc_rel
= 0;
9586 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
9587 inst
.relocs
[0].pc_rel
= 0;
9593 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
9594 inst
.relocs
[0].pc_rel
= 0;
9600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9601 _("selected processor does not support SETPAN instruction"));
9603 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9609 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9610 _("selected processor does not support SETPAN instruction"));
9612 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9615 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9616 SMLAxy{cond} Rd,Rm,Rs,Rn
9617 SMLAWy{cond} Rd,Rm,Rs,Rn
9618 Error if any register is R15. */
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9624 inst
.instruction
|= inst
.operands
[1].reg
;
9625 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9626 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9629 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9630 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9631 Error if any register is R15.
9632 Warning if Rdlo == Rdhi. */
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9639 inst
.instruction
|= inst
.operands
[2].reg
;
9640 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9642 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9643 as_tsktsk (_("rdhi and rdlo must be different"));
9646 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9647 SMULxy{cond} Rd,Rm,Rs
9648 Error if any register is R15. */
9653 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9654 inst
.instruction
|= inst
.operands
[1].reg
;
9655 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9658 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9659 the same for both ARM and Thumb-2. */
9666 if (inst
.operands
[0].present
)
9668 reg
= inst
.operands
[0].reg
;
9669 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9674 inst
.instruction
|= reg
<< 16;
9675 inst
.instruction
|= inst
.operands
[1].imm
;
9676 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9677 inst
.instruction
|= WRITE_BACK
;
9680 /* ARM V6 strex (argument parse). */
9685 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9686 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9687 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9688 || inst
.operands
[2].negative
9689 /* See comment in do_ldrex(). */
9690 || (inst
.operands
[2].reg
== REG_PC
),
9693 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9694 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9696 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9697 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9698 _("offset must be zero in ARM encoding"));
9700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9701 inst
.instruction
|= inst
.operands
[1].reg
;
9702 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9703 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9709 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9710 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9711 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9712 || inst
.operands
[2].negative
,
9715 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9716 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9724 constraint (inst
.operands
[1].reg
% 2 != 0,
9725 _("even register required"));
9726 constraint (inst
.operands
[2].present
9727 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9728 _("can only store two consecutive registers"));
9729 /* If op 2 were present and equal to PC, this function wouldn't
9730 have been called in the first place. */
9731 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9733 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9734 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9735 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9739 inst
.instruction
|= inst
.operands
[1].reg
;
9740 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9747 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9748 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9756 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9757 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9762 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9763 extends it to 32-bits, and adds the result to a value in another
9764 register. You can specify a rotation by 0, 8, 16, or 24 bits
9765 before extracting the 16-bit value.
9766 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9767 Condition defaults to COND_ALWAYS.
9768 Error if any register uses R15. */
9773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9774 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9775 inst
.instruction
|= inst
.operands
[2].reg
;
9776 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9781 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9782 Condition defaults to COND_ALWAYS.
9783 Error if any register uses R15. */
9788 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9789 inst
.instruction
|= inst
.operands
[1].reg
;
9790 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9793 /* VFP instructions. In a logical order: SP variant first, monad
9794 before dyad, arithmetic then move then load/store. */
9797 do_vfp_sp_monadic (void)
9799 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9800 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9804 do_vfp_sp_dyadic (void)
9806 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9807 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9808 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9812 do_vfp_sp_compare_z (void)
9814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9818 do_vfp_dp_sp_cvt (void)
9820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9821 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9825 do_vfp_sp_dp_cvt (void)
9827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9828 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9832 do_vfp_reg_from_sp (void)
9834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9835 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9839 do_vfp_reg2_from_sp2 (void)
9841 constraint (inst
.operands
[2].imm
!= 2,
9842 _("only two consecutive VFP SP registers allowed here"));
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9844 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9845 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9849 do_vfp_sp_from_reg (void)
9851 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9852 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9856 do_vfp_sp2_from_reg2 (void)
9858 constraint (inst
.operands
[0].imm
!= 2,
9859 _("only two consecutive VFP SP registers allowed here"));
9860 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9861 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9862 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9866 do_vfp_sp_ldst (void)
9868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9869 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9873 do_vfp_dp_ldst (void)
9875 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9876 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9881 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9883 if (inst
.operands
[0].writeback
)
9884 inst
.instruction
|= WRITE_BACK
;
9886 constraint (ldstm_type
!= VFP_LDSTMIA
,
9887 _("this addressing mode requires base-register writeback"));
9888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9889 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9890 inst
.instruction
|= inst
.operands
[1].imm
;
9894 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9898 if (inst
.operands
[0].writeback
)
9899 inst
.instruction
|= WRITE_BACK
;
9901 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9902 _("this addressing mode requires base-register writeback"));
9904 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9905 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9907 count
= inst
.operands
[1].imm
<< 1;
9908 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9911 inst
.instruction
|= count
;
9915 do_vfp_sp_ldstmia (void)
9917 vfp_sp_ldstm (VFP_LDSTMIA
);
9921 do_vfp_sp_ldstmdb (void)
9923 vfp_sp_ldstm (VFP_LDSTMDB
);
9927 do_vfp_dp_ldstmia (void)
9929 vfp_dp_ldstm (VFP_LDSTMIA
);
9933 do_vfp_dp_ldstmdb (void)
9935 vfp_dp_ldstm (VFP_LDSTMDB
);
9939 do_vfp_xp_ldstmia (void)
9941 vfp_dp_ldstm (VFP_LDSTMIAX
);
9945 do_vfp_xp_ldstmdb (void)
9947 vfp_dp_ldstm (VFP_LDSTMDBX
);
9951 do_vfp_dp_rd_rm (void)
9953 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9954 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9958 do_vfp_dp_rn_rd (void)
9960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9961 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9965 do_vfp_dp_rd_rn (void)
9967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9968 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9972 do_vfp_dp_rd_rn_rm (void)
9974 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9975 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9976 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9982 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9986 do_vfp_dp_rm_rd_rn (void)
9988 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9989 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9990 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9993 /* VFPv3 instructions. */
9995 do_vfp_sp_const (void)
9997 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9998 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9999 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10003 do_vfp_dp_const (void)
10005 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10006 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10007 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10011 vfp_conv (int srcsize
)
10013 int immbits
= srcsize
- inst
.operands
[1].imm
;
10015 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10017 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10018 i.e. immbits must be in range 0 - 16. */
10019 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10022 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10024 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10025 i.e. immbits must be in range 0 - 31. */
10026 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10030 inst
.instruction
|= (immbits
& 1) << 5;
10031 inst
.instruction
|= (immbits
>> 1);
10035 do_vfp_sp_conv_16 (void)
10037 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10042 do_vfp_dp_conv_16 (void)
10044 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10049 do_vfp_sp_conv_32 (void)
10051 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10056 do_vfp_dp_conv_32 (void)
10058 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10062 /* FPA instructions. Also in a logical order. */
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10068 inst
.instruction
|= inst
.operands
[1].reg
;
10072 do_fpa_ldmstm (void)
10074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10075 switch (inst
.operands
[1].imm
)
10077 case 1: inst
.instruction
|= CP_T_X
; break;
10078 case 2: inst
.instruction
|= CP_T_Y
; break;
10079 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10084 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10086 /* The instruction specified "ea" or "fd", so we can only accept
10087 [Rn]{!}. The instruction does not really support stacking or
10088 unstacking, so we have to emulate these by setting appropriate
10089 bits and offsets. */
10090 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10091 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10092 _("this instruction does not support indexing"));
10094 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10095 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10097 if (!(inst
.instruction
& INDEX_UP
))
10098 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10100 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10102 inst
.operands
[2].preind
= 0;
10103 inst
.operands
[2].postind
= 1;
10107 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10110 /* iWMMXt instructions: strictly in alphabetical order. */
10113 do_iwmmxt_tandorc (void)
10115 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10119 do_iwmmxt_textrc (void)
10121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10122 inst
.instruction
|= inst
.operands
[1].imm
;
10126 do_iwmmxt_textrm (void)
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10130 inst
.instruction
|= inst
.operands
[2].imm
;
10134 do_iwmmxt_tinsr (void)
10136 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10137 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10138 inst
.instruction
|= inst
.operands
[2].imm
;
10142 do_iwmmxt_tmia (void)
10144 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10145 inst
.instruction
|= inst
.operands
[1].reg
;
10146 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10150 do_iwmmxt_waligni (void)
10152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10153 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10154 inst
.instruction
|= inst
.operands
[2].reg
;
10155 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10159 do_iwmmxt_wmerge (void)
10161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10163 inst
.instruction
|= inst
.operands
[2].reg
;
10164 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10168 do_iwmmxt_wmov (void)
10170 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10173 inst
.instruction
|= inst
.operands
[1].reg
;
10177 do_iwmmxt_wldstbh (void)
10180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10182 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10184 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10185 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10189 do_iwmmxt_wldstw (void)
10191 /* RIWR_RIWC clears .isreg for a control register. */
10192 if (!inst
.operands
[0].isreg
)
10194 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10195 inst
.instruction
|= 0xf0000000;
10198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10199 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10203 do_iwmmxt_wldstd (void)
10205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10206 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10207 && inst
.operands
[1].immisreg
)
10209 inst
.instruction
&= ~0x1a000ff;
10210 inst
.instruction
|= (0xfU
<< 28);
10211 if (inst
.operands
[1].preind
)
10212 inst
.instruction
|= PRE_INDEX
;
10213 if (!inst
.operands
[1].negative
)
10214 inst
.instruction
|= INDEX_UP
;
10215 if (inst
.operands
[1].writeback
)
10216 inst
.instruction
|= WRITE_BACK
;
10217 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10218 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10219 inst
.instruction
|= inst
.operands
[1].imm
;
10222 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10226 do_iwmmxt_wshufh (void)
10228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10230 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10231 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10235 do_iwmmxt_wzero (void)
10237 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10238 inst
.instruction
|= inst
.operands
[0].reg
;
10239 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10240 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10244 do_iwmmxt_wrwrwr_or_imm5 (void)
10246 if (inst
.operands
[2].isreg
)
10249 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10250 _("immediate operand requires iWMMXt2"));
10252 if (inst
.operands
[2].imm
== 0)
10254 switch ((inst
.instruction
>> 20) & 0xf)
10260 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10261 inst
.operands
[2].imm
= 16;
10262 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10268 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10269 inst
.operands
[2].imm
= 32;
10270 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10277 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10279 wrn
= (inst
.instruction
>> 16) & 0xf;
10280 inst
.instruction
&= 0xff0fff0f;
10281 inst
.instruction
|= wrn
;
10282 /* Bail out here; the instruction is now assembled. */
10287 /* Map 32 -> 0, etc. */
10288 inst
.operands
[2].imm
&= 0x1f;
10289 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10293 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10294 operations first, then control, shift, and load/store. */
10296 /* Insns like "foo X,Y,Z". */
10299 do_mav_triple (void)
10301 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10302 inst
.instruction
|= inst
.operands
[1].reg
;
10303 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10306 /* Insns like "foo W,X,Y,Z".
10307 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10312 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10313 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10314 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10315 inst
.instruction
|= inst
.operands
[3].reg
;
10318 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10320 do_mav_dspsc (void)
10322 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10325 /* Maverick shift immediate instructions.
10326 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10327 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10330 do_mav_shift (void)
10332 int imm
= inst
.operands
[2].imm
;
10334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10335 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10337 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10338 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10339 Bit 4 should be 0. */
10340 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10342 inst
.instruction
|= imm
;
10345 /* XScale instructions. Also sorted arithmetic before move. */
10347 /* Xscale multiply-accumulate (argument parse)
10350 MIAxycc acc0,Rm,Rs. */
10355 inst
.instruction
|= inst
.operands
[1].reg
;
10356 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10359 /* Xscale move-accumulator-register (argument parse)
10361 MARcc acc0,RdLo,RdHi. */
10366 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10367 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10370 /* Xscale move-register-accumulator (argument parse)
10372 MRAcc RdLo,RdHi,acc0. */
10377 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10379 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10382 /* Encoding functions relevant only to Thumb. */
10384 /* inst.operands[i] is a shifted-register operand; encode
10385 it into inst.instruction in the format used by Thumb32. */
10388 encode_thumb32_shifted_operand (int i
)
10390 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10391 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10393 constraint (inst
.operands
[i
].immisreg
,
10394 _("shift by register not allowed in thumb mode"));
10395 inst
.instruction
|= inst
.operands
[i
].reg
;
10396 if (shift
== SHIFT_RRX
)
10397 inst
.instruction
|= SHIFT_ROR
<< 4;
10400 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10401 _("expression too complex"));
10403 constraint (value
> 32
10404 || (value
== 32 && (shift
== SHIFT_LSL
10405 || shift
== SHIFT_ROR
)),
10406 _("shift expression is too large"));
10410 else if (value
== 32)
10413 inst
.instruction
|= shift
<< 4;
10414 inst
.instruction
|= (value
& 0x1c) << 10;
10415 inst
.instruction
|= (value
& 0x03) << 6;
10420 /* inst.operands[i] was set up by parse_address. Encode it into a
10421 Thumb32 format load or store instruction. Reject forms that cannot
10422 be used with such instructions. If is_t is true, reject forms that
10423 cannot be used with a T instruction; if is_d is true, reject forms
10424 that cannot be used with a D instruction. If it is a store insn,
10425 reject PC in Rn. */
10428 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10430 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10432 constraint (!inst
.operands
[i
].isreg
,
10433 _("Instruction does not support =N addresses"));
10435 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10436 if (inst
.operands
[i
].immisreg
)
10438 constraint (is_pc
, BAD_PC_ADDRESSING
);
10439 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10440 constraint (inst
.operands
[i
].negative
,
10441 _("Thumb does not support negative register indexing"));
10442 constraint (inst
.operands
[i
].postind
,
10443 _("Thumb does not support register post-indexing"));
10444 constraint (inst
.operands
[i
].writeback
,
10445 _("Thumb does not support register indexing with writeback"));
10446 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10447 _("Thumb supports only LSL in shifted register indexing"));
10449 inst
.instruction
|= inst
.operands
[i
].imm
;
10450 if (inst
.operands
[i
].shifted
)
10452 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10453 _("expression too complex"));
10454 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10455 || inst
.relocs
[0].exp
.X_add_number
> 3,
10456 _("shift out of range"));
10457 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10459 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10461 else if (inst
.operands
[i
].preind
)
10463 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10464 constraint (is_t
&& inst
.operands
[i
].writeback
,
10465 _("cannot use writeback with this instruction"));
10466 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10467 BAD_PC_ADDRESSING
);
10471 inst
.instruction
|= 0x01000000;
10472 if (inst
.operands
[i
].writeback
)
10473 inst
.instruction
|= 0x00200000;
10477 inst
.instruction
|= 0x00000c00;
10478 if (inst
.operands
[i
].writeback
)
10479 inst
.instruction
|= 0x00000100;
10481 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10483 else if (inst
.operands
[i
].postind
)
10485 gas_assert (inst
.operands
[i
].writeback
);
10486 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10487 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10490 inst
.instruction
|= 0x00200000;
10492 inst
.instruction
|= 0x00000900;
10493 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10495 else /* unindexed - only for coprocessor */
10496 inst
.error
= _("instruction does not accept unindexed addressing");
10499 /* Table of Thumb instructions which exist in both 16- and 32-bit
10500 encodings (the latter only in post-V6T2 cores). The index is the
10501 value used in the insns table below. When there is more than one
10502 possible 16-bit encoding for the instruction, this table always
10504 Also contains several pseudo-instructions used during relaxation. */
10505 #define T16_32_TAB \
10506 X(_adc, 4140, eb400000), \
10507 X(_adcs, 4140, eb500000), \
10508 X(_add, 1c00, eb000000), \
10509 X(_adds, 1c00, eb100000), \
10510 X(_addi, 0000, f1000000), \
10511 X(_addis, 0000, f1100000), \
10512 X(_add_pc,000f, f20f0000), \
10513 X(_add_sp,000d, f10d0000), \
10514 X(_adr, 000f, f20f0000), \
10515 X(_and, 4000, ea000000), \
10516 X(_ands, 4000, ea100000), \
10517 X(_asr, 1000, fa40f000), \
10518 X(_asrs, 1000, fa50f000), \
10519 X(_b, e000, f000b000), \
10520 X(_bcond, d000, f0008000), \
10521 X(_bf, 0000, f040e001), \
10522 X(_bfcsel,0000, f000e001), \
10523 X(_bfx, 0000, f060e001), \
10524 X(_bfl, 0000, f000c001), \
10525 X(_bflx, 0000, f070e001), \
10526 X(_bic, 4380, ea200000), \
10527 X(_bics, 4380, ea300000), \
10528 X(_cmn, 42c0, eb100f00), \
10529 X(_cmp, 2800, ebb00f00), \
10530 X(_cpsie, b660, f3af8400), \
10531 X(_cpsid, b670, f3af8600), \
10532 X(_cpy, 4600, ea4f0000), \
10533 X(_dec_sp,80dd, f1ad0d00), \
10534 X(_dls, 0000, f040e001), \
10535 X(_eor, 4040, ea800000), \
10536 X(_eors, 4040, ea900000), \
10537 X(_inc_sp,00dd, f10d0d00), \
10538 X(_ldmia, c800, e8900000), \
10539 X(_ldr, 6800, f8500000), \
10540 X(_ldrb, 7800, f8100000), \
10541 X(_ldrh, 8800, f8300000), \
10542 X(_ldrsb, 5600, f9100000), \
10543 X(_ldrsh, 5e00, f9300000), \
10544 X(_ldr_pc,4800, f85f0000), \
10545 X(_ldr_pc2,4800, f85f0000), \
10546 X(_ldr_sp,9800, f85d0000), \
10547 X(_le, 0000, f00fc001), \
10548 X(_lsl, 0000, fa00f000), \
10549 X(_lsls, 0000, fa10f000), \
10550 X(_lsr, 0800, fa20f000), \
10551 X(_lsrs, 0800, fa30f000), \
10552 X(_mov, 2000, ea4f0000), \
10553 X(_movs, 2000, ea5f0000), \
10554 X(_mul, 4340, fb00f000), \
10555 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10556 X(_mvn, 43c0, ea6f0000), \
10557 X(_mvns, 43c0, ea7f0000), \
10558 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10559 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10560 X(_orr, 4300, ea400000), \
10561 X(_orrs, 4300, ea500000), \
10562 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10563 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10564 X(_rev, ba00, fa90f080), \
10565 X(_rev16, ba40, fa90f090), \
10566 X(_revsh, bac0, fa90f0b0), \
10567 X(_ror, 41c0, fa60f000), \
10568 X(_rors, 41c0, fa70f000), \
10569 X(_sbc, 4180, eb600000), \
10570 X(_sbcs, 4180, eb700000), \
10571 X(_stmia, c000, e8800000), \
10572 X(_str, 6000, f8400000), \
10573 X(_strb, 7000, f8000000), \
10574 X(_strh, 8000, f8200000), \
10575 X(_str_sp,9000, f84d0000), \
10576 X(_sub, 1e00, eba00000), \
10577 X(_subs, 1e00, ebb00000), \
10578 X(_subi, 8000, f1a00000), \
10579 X(_subis, 8000, f1b00000), \
10580 X(_sxtb, b240, fa4ff080), \
10581 X(_sxth, b200, fa0ff080), \
10582 X(_tst, 4200, ea100f00), \
10583 X(_uxtb, b2c0, fa5ff080), \
10584 X(_uxth, b280, fa1ff080), \
10585 X(_nop, bf00, f3af8000), \
10586 X(_yield, bf10, f3af8001), \
10587 X(_wfe, bf20, f3af8002), \
10588 X(_wfi, bf30, f3af8003), \
10589 X(_wls, 0000, f040c001), \
10590 X(_sev, bf40, f3af8004), \
10591 X(_sevl, bf50, f3af8005), \
10592 X(_udf, de00, f7f0a000)
10594 /* To catch errors in encoding functions, the codes are all offset by
10595 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10596 as 16-bit instructions. */
10597 #define X(a,b,c) T_MNEM##a
10598 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10601 #define X(a,b,c) 0x##b
10602 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10603 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10606 #define X(a,b,c) 0x##c
10607 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10608 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10609 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10613 /* Thumb instruction encoders, in alphabetical order. */
10615 /* ADDW or SUBW. */
10618 do_t_add_sub_w (void)
10622 Rd
= inst
.operands
[0].reg
;
10623 Rn
= inst
.operands
[1].reg
;
10625 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10626 is the SP-{plus,minus}-immediate form of the instruction. */
10628 constraint (Rd
== REG_PC
, BAD_PC
);
10630 reject_bad_reg (Rd
);
10632 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10633 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10636 /* Parse an add or subtract instruction. We get here with inst.instruction
10637 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10640 do_t_add_sub (void)
10644 Rd
= inst
.operands
[0].reg
;
10645 Rs
= (inst
.operands
[1].present
10646 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10647 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10650 set_it_insn_type_last ();
10652 if (unified_syntax
)
10655 bfd_boolean narrow
;
10658 flags
= (inst
.instruction
== T_MNEM_adds
10659 || inst
.instruction
== T_MNEM_subs
);
10661 narrow
= !in_it_block ();
10663 narrow
= in_it_block ();
10664 if (!inst
.operands
[2].isreg
)
10668 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10669 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10671 add
= (inst
.instruction
== T_MNEM_add
10672 || inst
.instruction
== T_MNEM_adds
);
10674 if (inst
.size_req
!= 4)
10676 /* Attempt to use a narrow opcode, with relaxation if
10678 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10679 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10680 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10681 opcode
= T_MNEM_add_sp
;
10682 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10683 opcode
= T_MNEM_add_pc
;
10684 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10687 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10689 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10693 inst
.instruction
= THUMB_OP16(opcode
);
10694 inst
.instruction
|= (Rd
<< 4) | Rs
;
10695 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10696 || (inst
.relocs
[0].type
10697 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
10699 if (inst
.size_req
== 2)
10700 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10702 inst
.relax
= opcode
;
10706 constraint (inst
.size_req
== 2, BAD_HIREG
);
10708 if (inst
.size_req
== 4
10709 || (inst
.size_req
!= 2 && !opcode
))
10711 constraint ((inst
.relocs
[0].type
10712 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
10713 && (inst
.relocs
[0].type
10714 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
10715 THUMB1_RELOC_ONLY
);
10718 constraint (add
, BAD_PC
);
10719 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10720 _("only SUBS PC, LR, #const allowed"));
10721 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10722 _("expression too complex"));
10723 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10724 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
10725 _("immediate value out of range"));
10726 inst
.instruction
= T2_SUBS_PC_LR
10727 | inst
.relocs
[0].exp
.X_add_number
;
10728 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10731 else if (Rs
== REG_PC
)
10733 /* Always use addw/subw. */
10734 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10735 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10739 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10740 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10743 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10745 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10747 inst
.instruction
|= Rd
<< 8;
10748 inst
.instruction
|= Rs
<< 16;
10753 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10754 unsigned int shift
= inst
.operands
[2].shift_kind
;
10756 Rn
= inst
.operands
[2].reg
;
10757 /* See if we can do this with a 16-bit instruction. */
10758 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10760 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10765 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10766 || inst
.instruction
== T_MNEM_add
)
10768 : T_OPCODE_SUB_R3
);
10769 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10773 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10775 /* Thumb-1 cores (except v6-M) require at least one high
10776 register in a narrow non flag setting add. */
10777 if (Rd
> 7 || Rn
> 7
10778 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10779 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10786 inst
.instruction
= T_OPCODE_ADD_HI
;
10787 inst
.instruction
|= (Rd
& 8) << 4;
10788 inst
.instruction
|= (Rd
& 7);
10789 inst
.instruction
|= Rn
<< 3;
10795 constraint (Rd
== REG_PC
, BAD_PC
);
10796 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10797 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10798 constraint (Rs
== REG_PC
, BAD_PC
);
10799 reject_bad_reg (Rn
);
10801 /* If we get here, it can't be done in 16 bits. */
10802 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10803 _("shift must be constant"));
10804 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10805 inst
.instruction
|= Rd
<< 8;
10806 inst
.instruction
|= Rs
<< 16;
10807 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10808 _("shift value over 3 not allowed in thumb mode"));
10809 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10810 _("only LSL shift allowed in thumb mode"));
10811 encode_thumb32_shifted_operand (2);
10816 constraint (inst
.instruction
== T_MNEM_adds
10817 || inst
.instruction
== T_MNEM_subs
,
10820 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10822 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10823 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10826 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10827 ? 0x0000 : 0x8000);
10828 inst
.instruction
|= (Rd
<< 4) | Rs
;
10829 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10833 Rn
= inst
.operands
[2].reg
;
10834 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10836 /* We now have Rd, Rs, and Rn set to registers. */
10837 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10839 /* Can't do this for SUB. */
10840 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10841 inst
.instruction
= T_OPCODE_ADD_HI
;
10842 inst
.instruction
|= (Rd
& 8) << 4;
10843 inst
.instruction
|= (Rd
& 7);
10845 inst
.instruction
|= Rn
<< 3;
10847 inst
.instruction
|= Rs
<< 3;
10849 constraint (1, _("dest must overlap one source register"));
10853 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10854 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10855 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10865 Rd
= inst
.operands
[0].reg
;
10866 reject_bad_reg (Rd
);
10868 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10870 /* Defer to section relaxation. */
10871 inst
.relax
= inst
.instruction
;
10872 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10873 inst
.instruction
|= Rd
<< 4;
10875 else if (unified_syntax
&& inst
.size_req
!= 2)
10877 /* Generate a 32-bit opcode. */
10878 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10879 inst
.instruction
|= Rd
<< 8;
10880 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10881 inst
.relocs
[0].pc_rel
= 1;
10885 /* Generate a 16-bit opcode. */
10886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10887 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10888 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
10889 inst
.relocs
[0].pc_rel
= 1;
10890 inst
.instruction
|= Rd
<< 4;
10893 if (inst
.relocs
[0].exp
.X_op
== O_symbol
10894 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
10895 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
10896 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
10897 inst
.relocs
[0].exp
.X_add_number
+= 1;
10900 /* Arithmetic instructions for which there is just one 16-bit
10901 instruction encoding, and it allows only two low registers.
10902 For maximal compatibility with ARM syntax, we allow three register
10903 operands even when Thumb-32 instructions are not available, as long
10904 as the first two are identical. For instance, both "sbc r0,r1" and
10905 "sbc r0,r0,r1" are allowed. */
10911 Rd
= inst
.operands
[0].reg
;
10912 Rs
= (inst
.operands
[1].present
10913 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10914 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10915 Rn
= inst
.operands
[2].reg
;
10917 reject_bad_reg (Rd
);
10918 reject_bad_reg (Rs
);
10919 if (inst
.operands
[2].isreg
)
10920 reject_bad_reg (Rn
);
10922 if (unified_syntax
)
10924 if (!inst
.operands
[2].isreg
)
10926 /* For an immediate, we always generate a 32-bit opcode;
10927 section relaxation will shrink it later if possible. */
10928 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10929 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10930 inst
.instruction
|= Rd
<< 8;
10931 inst
.instruction
|= Rs
<< 16;
10932 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10936 bfd_boolean narrow
;
10938 /* See if we can do this with a 16-bit instruction. */
10939 if (THUMB_SETS_FLAGS (inst
.instruction
))
10940 narrow
= !in_it_block ();
10942 narrow
= in_it_block ();
10944 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10946 if (inst
.operands
[2].shifted
)
10948 if (inst
.size_req
== 4)
10954 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10955 inst
.instruction
|= Rd
;
10956 inst
.instruction
|= Rn
<< 3;
10960 /* If we get here, it can't be done in 16 bits. */
10961 constraint (inst
.operands
[2].shifted
10962 && inst
.operands
[2].immisreg
,
10963 _("shift must be constant"));
10964 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10965 inst
.instruction
|= Rd
<< 8;
10966 inst
.instruction
|= Rs
<< 16;
10967 encode_thumb32_shifted_operand (2);
10972 /* On its face this is a lie - the instruction does set the
10973 flags. However, the only supported mnemonic in this mode
10974 says it doesn't. */
10975 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10977 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10978 _("unshifted register required"));
10979 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10980 constraint (Rd
!= Rs
,
10981 _("dest and source1 must be the same register"));
10983 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10984 inst
.instruction
|= Rd
;
10985 inst
.instruction
|= Rn
<< 3;
10989 /* Similarly, but for instructions where the arithmetic operation is
10990 commutative, so we can allow either of them to be different from
10991 the destination operand in a 16-bit instruction. For instance, all
10992 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10999 Rd
= inst
.operands
[0].reg
;
11000 Rs
= (inst
.operands
[1].present
11001 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11002 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11003 Rn
= inst
.operands
[2].reg
;
11005 reject_bad_reg (Rd
);
11006 reject_bad_reg (Rs
);
11007 if (inst
.operands
[2].isreg
)
11008 reject_bad_reg (Rn
);
11010 if (unified_syntax
)
11012 if (!inst
.operands
[2].isreg
)
11014 /* For an immediate, we always generate a 32-bit opcode;
11015 section relaxation will shrink it later if possible. */
11016 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11017 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11018 inst
.instruction
|= Rd
<< 8;
11019 inst
.instruction
|= Rs
<< 16;
11020 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11024 bfd_boolean narrow
;
11026 /* See if we can do this with a 16-bit instruction. */
11027 if (THUMB_SETS_FLAGS (inst
.instruction
))
11028 narrow
= !in_it_block ();
11030 narrow
= in_it_block ();
11032 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11034 if (inst
.operands
[2].shifted
)
11036 if (inst
.size_req
== 4)
11043 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11044 inst
.instruction
|= Rd
;
11045 inst
.instruction
|= Rn
<< 3;
11050 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11051 inst
.instruction
|= Rd
;
11052 inst
.instruction
|= Rs
<< 3;
11057 /* If we get here, it can't be done in 16 bits. */
11058 constraint (inst
.operands
[2].shifted
11059 && inst
.operands
[2].immisreg
,
11060 _("shift must be constant"));
11061 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11062 inst
.instruction
|= Rd
<< 8;
11063 inst
.instruction
|= Rs
<< 16;
11064 encode_thumb32_shifted_operand (2);
11069 /* On its face this is a lie - the instruction does set the
11070 flags. However, the only supported mnemonic in this mode
11071 says it doesn't. */
11072 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11074 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11075 _("unshifted register required"));
11076 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11078 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11079 inst
.instruction
|= Rd
;
11082 inst
.instruction
|= Rn
<< 3;
11084 inst
.instruction
|= Rs
<< 3;
11086 constraint (1, _("dest must overlap one source register"));
11094 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11095 constraint (msb
> 32, _("bit-field extends past end of register"));
11096 /* The instruction encoding stores the LSB and MSB,
11097 not the LSB and width. */
11098 Rd
= inst
.operands
[0].reg
;
11099 reject_bad_reg (Rd
);
11100 inst
.instruction
|= Rd
<< 8;
11101 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11102 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11103 inst
.instruction
|= msb
- 1;
11112 Rd
= inst
.operands
[0].reg
;
11113 reject_bad_reg (Rd
);
11115 /* #0 in second position is alternative syntax for bfc, which is
11116 the same instruction but with REG_PC in the Rm field. */
11117 if (!inst
.operands
[1].isreg
)
11121 Rn
= inst
.operands
[1].reg
;
11122 reject_bad_reg (Rn
);
11125 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11126 constraint (msb
> 32, _("bit-field extends past end of register"));
11127 /* The instruction encoding stores the LSB and MSB,
11128 not the LSB and width. */
11129 inst
.instruction
|= Rd
<< 8;
11130 inst
.instruction
|= Rn
<< 16;
11131 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11132 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11133 inst
.instruction
|= msb
- 1;
11141 Rd
= inst
.operands
[0].reg
;
11142 Rn
= inst
.operands
[1].reg
;
11144 reject_bad_reg (Rd
);
11145 reject_bad_reg (Rn
);
11147 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11148 _("bit-field extends past end of register"));
11149 inst
.instruction
|= Rd
<< 8;
11150 inst
.instruction
|= Rn
<< 16;
11151 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11152 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11153 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11156 /* ARM V5 Thumb BLX (argument parse)
11157 BLX <target_addr> which is BLX(1)
11158 BLX <Rm> which is BLX(2)
11159 Unfortunately, there are two different opcodes for this mnemonic.
11160 So, the insns[].value is not used, and the code here zaps values
11161 into inst.instruction.
11163 ??? How to take advantage of the additional two bits of displacement
11164 available in Thumb32 mode? Need new relocation? */
11169 set_it_insn_type_last ();
11171 if (inst
.operands
[0].isreg
)
11173 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11174 /* We have a register, so this is BLX(2). */
11175 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11179 /* No register. This must be BLX(1). */
11180 inst
.instruction
= 0xf000e800;
11181 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11190 bfd_reloc_code_real_type reloc
;
11193 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11195 if (in_it_block ())
11197 /* Conditional branches inside IT blocks are encoded as unconditional
11199 cond
= COND_ALWAYS
;
11204 if (cond
!= COND_ALWAYS
)
11205 opcode
= T_MNEM_bcond
;
11207 opcode
= inst
.instruction
;
11210 && (inst
.size_req
== 4
11211 || (inst
.size_req
!= 2
11212 && (inst
.operands
[0].hasreloc
11213 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11215 inst
.instruction
= THUMB_OP32(opcode
);
11216 if (cond
== COND_ALWAYS
)
11217 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11220 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11221 _("selected architecture does not support "
11222 "wide conditional branch instruction"));
11224 gas_assert (cond
!= 0xF);
11225 inst
.instruction
|= cond
<< 22;
11226 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11231 inst
.instruction
= THUMB_OP16(opcode
);
11232 if (cond
== COND_ALWAYS
)
11233 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11236 inst
.instruction
|= cond
<< 8;
11237 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11239 /* Allow section relaxation. */
11240 if (unified_syntax
&& inst
.size_req
!= 2)
11241 inst
.relax
= opcode
;
11243 inst
.relocs
[0].type
= reloc
;
11244 inst
.relocs
[0].pc_rel
= 1;
11247 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11248 between the two is the maximum immediate allowed - which is passed in
11251 do_t_bkpt_hlt1 (int range
)
11253 constraint (inst
.cond
!= COND_ALWAYS
,
11254 _("instruction is always unconditional"));
11255 if (inst
.operands
[0].present
)
11257 constraint (inst
.operands
[0].imm
> range
,
11258 _("immediate value out of range"));
11259 inst
.instruction
|= inst
.operands
[0].imm
;
11262 set_it_insn_type (NEUTRAL_IT_INSN
);
11268 do_t_bkpt_hlt1 (63);
11274 do_t_bkpt_hlt1 (255);
11278 do_t_branch23 (void)
11280 set_it_insn_type_last ();
11281 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11283 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11284 this file. We used to simply ignore the PLT reloc type here --
11285 the branch encoding is now needed to deal with TLSCALL relocs.
11286 So if we see a PLT reloc now, put it back to how it used to be to
11287 keep the preexisting behaviour. */
11288 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11289 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11291 #if defined(OBJ_COFF)
11292 /* If the destination of the branch is a defined symbol which does not have
11293 the THUMB_FUNC attribute, then we must be calling a function which has
11294 the (interfacearm) attribute. We look for the Thumb entry point to that
11295 function and change the branch to refer to that function instead. */
11296 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11297 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11298 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11299 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11300 inst
.relocs
[0].exp
.X_add_symbol
11301 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11308 set_it_insn_type_last ();
11309 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11310 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11311 should cause the alignment to be checked once it is known. This is
11312 because BX PC only works if the instruction is word aligned. */
11320 set_it_insn_type_last ();
11321 Rm
= inst
.operands
[0].reg
;
11322 reject_bad_reg (Rm
);
11323 inst
.instruction
|= Rm
<< 16;
11332 Rd
= inst
.operands
[0].reg
;
11333 Rm
= inst
.operands
[1].reg
;
11335 reject_bad_reg (Rd
);
11336 reject_bad_reg (Rm
);
11338 inst
.instruction
|= Rd
<< 8;
11339 inst
.instruction
|= Rm
<< 16;
11340 inst
.instruction
|= Rm
;
11346 set_it_insn_type (OUTSIDE_IT_INSN
);
11352 set_it_insn_type (OUTSIDE_IT_INSN
);
11353 inst
.instruction
|= inst
.operands
[0].imm
;
11359 set_it_insn_type (OUTSIDE_IT_INSN
);
11361 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11362 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11364 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11365 inst
.instruction
= 0xf3af8000;
11366 inst
.instruction
|= imod
<< 9;
11367 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11368 if (inst
.operands
[1].present
)
11369 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11374 && (inst
.operands
[0].imm
& 4),
11375 _("selected processor does not support 'A' form "
11376 "of this instruction"));
11377 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11378 _("Thumb does not support the 2-argument "
11379 "form of this instruction"));
11380 inst
.instruction
|= inst
.operands
[0].imm
;
11384 /* THUMB CPY instruction (argument parse). */
11389 if (inst
.size_req
== 4)
11391 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11392 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11393 inst
.instruction
|= inst
.operands
[1].reg
;
11397 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11398 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11399 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11406 set_it_insn_type (OUTSIDE_IT_INSN
);
11407 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11408 inst
.instruction
|= inst
.operands
[0].reg
;
11409 inst
.relocs
[0].pc_rel
= 1;
11410 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11416 inst
.instruction
|= inst
.operands
[0].imm
;
11422 unsigned Rd
, Rn
, Rm
;
11424 Rd
= inst
.operands
[0].reg
;
11425 Rn
= (inst
.operands
[1].present
11426 ? inst
.operands
[1].reg
: Rd
);
11427 Rm
= inst
.operands
[2].reg
;
11429 reject_bad_reg (Rd
);
11430 reject_bad_reg (Rn
);
11431 reject_bad_reg (Rm
);
11433 inst
.instruction
|= Rd
<< 8;
11434 inst
.instruction
|= Rn
<< 16;
11435 inst
.instruction
|= Rm
;
11441 if (unified_syntax
&& inst
.size_req
== 4)
11442 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11450 unsigned int cond
= inst
.operands
[0].imm
;
11452 set_it_insn_type (IT_INSN
);
11453 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11455 now_it
.warn_deprecated
= FALSE
;
11457 /* If the condition is a negative condition, invert the mask. */
11458 if ((cond
& 0x1) == 0x0)
11460 unsigned int mask
= inst
.instruction
& 0x000f;
11462 if ((mask
& 0x7) == 0)
11464 /* No conversion needed. */
11465 now_it
.block_length
= 1;
11467 else if ((mask
& 0x3) == 0)
11470 now_it
.block_length
= 2;
11472 else if ((mask
& 0x1) == 0)
11475 now_it
.block_length
= 3;
11480 now_it
.block_length
= 4;
11483 inst
.instruction
&= 0xfff0;
11484 inst
.instruction
|= mask
;
11487 inst
.instruction
|= cond
<< 4;
11490 /* Helper function used for both push/pop and ldm/stm. */
11492 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11496 load
= (inst
.instruction
& (1 << 20)) != 0;
11498 if (mask
& (1 << 13))
11499 inst
.error
= _("SP not allowed in register list");
11501 if ((mask
& (1 << base
)) != 0
11503 inst
.error
= _("having the base register in the register list when "
11504 "using write back is UNPREDICTABLE");
11508 if (mask
& (1 << 15))
11510 if (mask
& (1 << 14))
11511 inst
.error
= _("LR and PC should not both be in register list");
11513 set_it_insn_type_last ();
11518 if (mask
& (1 << 15))
11519 inst
.error
= _("PC not allowed in register list");
11522 if ((mask
& (mask
- 1)) == 0)
11524 /* Single register transfers implemented as str/ldr. */
11527 if (inst
.instruction
& (1 << 23))
11528 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11530 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11534 if (inst
.instruction
& (1 << 23))
11535 inst
.instruction
= 0x00800000; /* ia -> [base] */
11537 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11540 inst
.instruction
|= 0xf8400000;
11542 inst
.instruction
|= 0x00100000;
11544 mask
= ffs (mask
) - 1;
11547 else if (writeback
)
11548 inst
.instruction
|= WRITE_BACK
;
11550 inst
.instruction
|= mask
;
11551 inst
.instruction
|= base
<< 16;
11557 /* This really doesn't seem worth it. */
11558 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
11559 _("expression too complex"));
11560 constraint (inst
.operands
[1].writeback
,
11561 _("Thumb load/store multiple does not support {reglist}^"));
11563 if (unified_syntax
)
11565 bfd_boolean narrow
;
11569 /* See if we can use a 16-bit instruction. */
11570 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11571 && inst
.size_req
!= 4
11572 && !(inst
.operands
[1].imm
& ~0xff))
11574 mask
= 1 << inst
.operands
[0].reg
;
11576 if (inst
.operands
[0].reg
<= 7)
11578 if (inst
.instruction
== T_MNEM_stmia
11579 ? inst
.operands
[0].writeback
11580 : (inst
.operands
[0].writeback
11581 == !(inst
.operands
[1].imm
& mask
)))
11583 if (inst
.instruction
== T_MNEM_stmia
11584 && (inst
.operands
[1].imm
& mask
)
11585 && (inst
.operands
[1].imm
& (mask
- 1)))
11586 as_warn (_("value stored for r%d is UNKNOWN"),
11587 inst
.operands
[0].reg
);
11589 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11590 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11591 inst
.instruction
|= inst
.operands
[1].imm
;
11594 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11596 /* This means 1 register in reg list one of 3 situations:
11597 1. Instruction is stmia, but without writeback.
11598 2. lmdia without writeback, but with Rn not in
11600 3. ldmia with writeback, but with Rn in reglist.
11601 Case 3 is UNPREDICTABLE behaviour, so we handle
11602 case 1 and 2 which can be converted into a 16-bit
11603 str or ldr. The SP cases are handled below. */
11604 unsigned long opcode
;
11605 /* First, record an error for Case 3. */
11606 if (inst
.operands
[1].imm
& mask
11607 && inst
.operands
[0].writeback
)
11609 _("having the base register in the register list when "
11610 "using write back is UNPREDICTABLE");
11612 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11614 inst
.instruction
= THUMB_OP16 (opcode
);
11615 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11616 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11620 else if (inst
.operands
[0] .reg
== REG_SP
)
11622 if (inst
.operands
[0].writeback
)
11625 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11626 ? T_MNEM_push
: T_MNEM_pop
);
11627 inst
.instruction
|= inst
.operands
[1].imm
;
11630 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11633 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11634 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11635 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11643 if (inst
.instruction
< 0xffff)
11644 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11646 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11647 inst
.operands
[0].writeback
);
11652 constraint (inst
.operands
[0].reg
> 7
11653 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11654 constraint (inst
.instruction
!= T_MNEM_ldmia
11655 && inst
.instruction
!= T_MNEM_stmia
,
11656 _("Thumb-2 instruction only valid in unified syntax"));
11657 if (inst
.instruction
== T_MNEM_stmia
)
11659 if (!inst
.operands
[0].writeback
)
11660 as_warn (_("this instruction will write back the base register"));
11661 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11662 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11663 as_warn (_("value stored for r%d is UNKNOWN"),
11664 inst
.operands
[0].reg
);
11668 if (!inst
.operands
[0].writeback
11669 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11670 as_warn (_("this instruction will write back the base register"));
11671 else if (inst
.operands
[0].writeback
11672 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11673 as_warn (_("this instruction will not write back the base register"));
11676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11677 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11678 inst
.instruction
|= inst
.operands
[1].imm
;
11685 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11686 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11687 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11688 || inst
.operands
[1].negative
,
11691 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11694 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11695 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11701 if (!inst
.operands
[1].present
)
11703 constraint (inst
.operands
[0].reg
== REG_LR
,
11704 _("r14 not allowed as first register "
11705 "when second register is omitted"));
11706 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11708 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11711 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11712 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11713 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11719 unsigned long opcode
;
11722 if (inst
.operands
[0].isreg
11723 && !inst
.operands
[0].preind
11724 && inst
.operands
[0].reg
== REG_PC
)
11725 set_it_insn_type_last ();
11727 opcode
= inst
.instruction
;
11728 if (unified_syntax
)
11730 if (!inst
.operands
[1].isreg
)
11732 if (opcode
<= 0xffff)
11733 inst
.instruction
= THUMB_OP32 (opcode
);
11734 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11737 if (inst
.operands
[1].isreg
11738 && !inst
.operands
[1].writeback
11739 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11740 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11741 && opcode
<= 0xffff
11742 && inst
.size_req
!= 4)
11744 /* Insn may have a 16-bit form. */
11745 Rn
= inst
.operands
[1].reg
;
11746 if (inst
.operands
[1].immisreg
)
11748 inst
.instruction
= THUMB_OP16 (opcode
);
11750 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11752 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11753 reject_bad_reg (inst
.operands
[1].imm
);
11755 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11756 && opcode
!= T_MNEM_ldrsb
)
11757 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11758 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11765 if (inst
.relocs
[0].pc_rel
)
11766 opcode
= T_MNEM_ldr_pc2
;
11768 opcode
= T_MNEM_ldr_pc
;
11772 if (opcode
== T_MNEM_ldr
)
11773 opcode
= T_MNEM_ldr_sp
;
11775 opcode
= T_MNEM_str_sp
;
11777 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11781 inst
.instruction
= inst
.operands
[0].reg
;
11782 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11784 inst
.instruction
|= THUMB_OP16 (opcode
);
11785 if (inst
.size_req
== 2)
11786 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11788 inst
.relax
= opcode
;
11792 /* Definitely a 32-bit variant. */
11794 /* Warning for Erratum 752419. */
11795 if (opcode
== T_MNEM_ldr
11796 && inst
.operands
[0].reg
== REG_SP
11797 && inst
.operands
[1].writeback
== 1
11798 && !inst
.operands
[1].immisreg
)
11800 if (no_cpu_selected ()
11801 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11802 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11803 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11804 as_warn (_("This instruction may be unpredictable "
11805 "if executed on M-profile cores "
11806 "with interrupts enabled."));
11809 /* Do some validations regarding addressing modes. */
11810 if (inst
.operands
[1].immisreg
)
11811 reject_bad_reg (inst
.operands
[1].imm
);
11813 constraint (inst
.operands
[1].writeback
== 1
11814 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11817 inst
.instruction
= THUMB_OP32 (opcode
);
11818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11819 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11820 check_ldr_r15_aligned ();
11824 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11826 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11828 /* Only [Rn,Rm] is acceptable. */
11829 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11830 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11831 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11832 || inst
.operands
[1].negative
,
11833 _("Thumb does not support this addressing mode"));
11834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11838 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11839 if (!inst
.operands
[1].isreg
)
11840 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11843 constraint (!inst
.operands
[1].preind
11844 || inst
.operands
[1].shifted
11845 || inst
.operands
[1].writeback
,
11846 _("Thumb does not support this addressing mode"));
11847 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11849 constraint (inst
.instruction
& 0x0600,
11850 _("byte or halfword not valid for base register"));
11851 constraint (inst
.operands
[1].reg
== REG_PC
11852 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11853 _("r15 based store not allowed"));
11854 constraint (inst
.operands
[1].immisreg
,
11855 _("invalid base register for register offset"));
11857 if (inst
.operands
[1].reg
== REG_PC
)
11858 inst
.instruction
= T_OPCODE_LDR_PC
;
11859 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11860 inst
.instruction
= T_OPCODE_LDR_SP
;
11862 inst
.instruction
= T_OPCODE_STR_SP
;
11864 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11865 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11869 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11870 if (!inst
.operands
[1].immisreg
)
11872 /* Immediate offset. */
11873 inst
.instruction
|= inst
.operands
[0].reg
;
11874 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11875 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11879 /* Register offset. */
11880 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11881 constraint (inst
.operands
[1].negative
,
11882 _("Thumb does not support this addressing mode"));
11885 switch (inst
.instruction
)
11887 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11888 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11889 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11890 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11891 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11892 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11893 case 0x5600 /* ldrsb */:
11894 case 0x5e00 /* ldrsh */: break;
11898 inst
.instruction
|= inst
.operands
[0].reg
;
11899 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11900 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11906 if (!inst
.operands
[1].present
)
11908 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11909 constraint (inst
.operands
[0].reg
== REG_LR
,
11910 _("r14 not allowed here"));
11911 constraint (inst
.operands
[0].reg
== REG_R12
,
11912 _("r12 not allowed here"));
11915 if (inst
.operands
[2].writeback
11916 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11917 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11918 as_warn (_("base register written back, and overlaps "
11919 "one of transfer registers"));
11921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11922 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11923 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11930 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11936 unsigned Rd
, Rn
, Rm
, Ra
;
11938 Rd
= inst
.operands
[0].reg
;
11939 Rn
= inst
.operands
[1].reg
;
11940 Rm
= inst
.operands
[2].reg
;
11941 Ra
= inst
.operands
[3].reg
;
11943 reject_bad_reg (Rd
);
11944 reject_bad_reg (Rn
);
11945 reject_bad_reg (Rm
);
11946 reject_bad_reg (Ra
);
11948 inst
.instruction
|= Rd
<< 8;
11949 inst
.instruction
|= Rn
<< 16;
11950 inst
.instruction
|= Rm
;
11951 inst
.instruction
|= Ra
<< 12;
11957 unsigned RdLo
, RdHi
, Rn
, Rm
;
11959 RdLo
= inst
.operands
[0].reg
;
11960 RdHi
= inst
.operands
[1].reg
;
11961 Rn
= inst
.operands
[2].reg
;
11962 Rm
= inst
.operands
[3].reg
;
11964 reject_bad_reg (RdLo
);
11965 reject_bad_reg (RdHi
);
11966 reject_bad_reg (Rn
);
11967 reject_bad_reg (Rm
);
11969 inst
.instruction
|= RdLo
<< 12;
11970 inst
.instruction
|= RdHi
<< 8;
11971 inst
.instruction
|= Rn
<< 16;
11972 inst
.instruction
|= Rm
;
11976 do_t_mov_cmp (void)
11980 Rn
= inst
.operands
[0].reg
;
11981 Rm
= inst
.operands
[1].reg
;
11984 set_it_insn_type_last ();
11986 if (unified_syntax
)
11988 int r0off
= (inst
.instruction
== T_MNEM_mov
11989 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11990 unsigned long opcode
;
11991 bfd_boolean narrow
;
11992 bfd_boolean low_regs
;
11994 low_regs
= (Rn
<= 7 && Rm
<= 7);
11995 opcode
= inst
.instruction
;
11996 if (in_it_block ())
11997 narrow
= opcode
!= T_MNEM_movs
;
11999 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12000 if (inst
.size_req
== 4
12001 || inst
.operands
[1].shifted
)
12004 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12005 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12006 && !inst
.operands
[1].shifted
12010 inst
.instruction
= T2_SUBS_PC_LR
;
12014 if (opcode
== T_MNEM_cmp
)
12016 constraint (Rn
== REG_PC
, BAD_PC
);
12019 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12021 warn_deprecated_sp (Rm
);
12022 /* R15 was documented as a valid choice for Rm in ARMv6,
12023 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12024 tools reject R15, so we do too. */
12025 constraint (Rm
== REG_PC
, BAD_PC
);
12028 reject_bad_reg (Rm
);
12030 else if (opcode
== T_MNEM_mov
12031 || opcode
== T_MNEM_movs
)
12033 if (inst
.operands
[1].isreg
)
12035 if (opcode
== T_MNEM_movs
)
12037 reject_bad_reg (Rn
);
12038 reject_bad_reg (Rm
);
12042 /* This is mov.n. */
12043 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12044 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12046 as_tsktsk (_("Use of r%u as a source register is "
12047 "deprecated when r%u is the destination "
12048 "register."), Rm
, Rn
);
12053 /* This is mov.w. */
12054 constraint (Rn
== REG_PC
, BAD_PC
);
12055 constraint (Rm
== REG_PC
, BAD_PC
);
12056 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12057 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12061 reject_bad_reg (Rn
);
12064 if (!inst
.operands
[1].isreg
)
12066 /* Immediate operand. */
12067 if (!in_it_block () && opcode
== T_MNEM_mov
)
12069 if (low_regs
&& narrow
)
12071 inst
.instruction
= THUMB_OP16 (opcode
);
12072 inst
.instruction
|= Rn
<< 8;
12073 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12074 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12076 if (inst
.size_req
== 2)
12077 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12079 inst
.relax
= opcode
;
12084 constraint ((inst
.relocs
[0].type
12085 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12086 && (inst
.relocs
[0].type
12087 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12088 THUMB1_RELOC_ONLY
);
12090 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12091 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12092 inst
.instruction
|= Rn
<< r0off
;
12093 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12096 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12097 && (inst
.instruction
== T_MNEM_mov
12098 || inst
.instruction
== T_MNEM_movs
))
12100 /* Register shifts are encoded as separate shift instructions. */
12101 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12103 if (in_it_block ())
12108 if (inst
.size_req
== 4)
12111 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12117 switch (inst
.operands
[1].shift_kind
)
12120 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12123 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12126 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12129 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12135 inst
.instruction
= opcode
;
12138 inst
.instruction
|= Rn
;
12139 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12144 inst
.instruction
|= CONDS_BIT
;
12146 inst
.instruction
|= Rn
<< 8;
12147 inst
.instruction
|= Rm
<< 16;
12148 inst
.instruction
|= inst
.operands
[1].imm
;
12153 /* Some mov with immediate shift have narrow variants.
12154 Register shifts are handled above. */
12155 if (low_regs
&& inst
.operands
[1].shifted
12156 && (inst
.instruction
== T_MNEM_mov
12157 || inst
.instruction
== T_MNEM_movs
))
12159 if (in_it_block ())
12160 narrow
= (inst
.instruction
== T_MNEM_mov
);
12162 narrow
= (inst
.instruction
== T_MNEM_movs
);
12167 switch (inst
.operands
[1].shift_kind
)
12169 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12170 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12171 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12172 default: narrow
= FALSE
; break;
12178 inst
.instruction
|= Rn
;
12179 inst
.instruction
|= Rm
<< 3;
12180 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12184 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12185 inst
.instruction
|= Rn
<< r0off
;
12186 encode_thumb32_shifted_operand (1);
12190 switch (inst
.instruction
)
12193 /* In v4t or v5t a move of two lowregs produces unpredictable
12194 results. Don't allow this. */
12197 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12198 "MOV Rd, Rs with two low registers is not "
12199 "permitted on this architecture");
12200 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12204 inst
.instruction
= T_OPCODE_MOV_HR
;
12205 inst
.instruction
|= (Rn
& 0x8) << 4;
12206 inst
.instruction
|= (Rn
& 0x7);
12207 inst
.instruction
|= Rm
<< 3;
12211 /* We know we have low registers at this point.
12212 Generate LSLS Rd, Rs, #0. */
12213 inst
.instruction
= T_OPCODE_LSL_I
;
12214 inst
.instruction
|= Rn
;
12215 inst
.instruction
|= Rm
<< 3;
12221 inst
.instruction
= T_OPCODE_CMP_LR
;
12222 inst
.instruction
|= Rn
;
12223 inst
.instruction
|= Rm
<< 3;
12227 inst
.instruction
= T_OPCODE_CMP_HR
;
12228 inst
.instruction
|= (Rn
& 0x8) << 4;
12229 inst
.instruction
|= (Rn
& 0x7);
12230 inst
.instruction
|= Rm
<< 3;
12237 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12239 /* PR 10443: Do not silently ignore shifted operands. */
12240 constraint (inst
.operands
[1].shifted
,
12241 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12243 if (inst
.operands
[1].isreg
)
12245 if (Rn
< 8 && Rm
< 8)
12247 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12248 since a MOV instruction produces unpredictable results. */
12249 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12250 inst
.instruction
= T_OPCODE_ADD_I3
;
12252 inst
.instruction
= T_OPCODE_CMP_LR
;
12254 inst
.instruction
|= Rn
;
12255 inst
.instruction
|= Rm
<< 3;
12259 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12260 inst
.instruction
= T_OPCODE_MOV_HR
;
12262 inst
.instruction
= T_OPCODE_CMP_HR
;
12268 constraint (Rn
> 7,
12269 _("only lo regs allowed with immediate"));
12270 inst
.instruction
|= Rn
<< 8;
12271 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12282 top
= (inst
.instruction
& 0x00800000) != 0;
12283 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12285 constraint (top
, _(":lower16: not allowed in this instruction"));
12286 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12288 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12290 constraint (!top
, _(":upper16: not allowed in this instruction"));
12291 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12294 Rd
= inst
.operands
[0].reg
;
12295 reject_bad_reg (Rd
);
12297 inst
.instruction
|= Rd
<< 8;
12298 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12300 imm
= inst
.relocs
[0].exp
.X_add_number
;
12301 inst
.instruction
|= (imm
& 0xf000) << 4;
12302 inst
.instruction
|= (imm
& 0x0800) << 15;
12303 inst
.instruction
|= (imm
& 0x0700) << 4;
12304 inst
.instruction
|= (imm
& 0x00ff);
12309 do_t_mvn_tst (void)
12313 Rn
= inst
.operands
[0].reg
;
12314 Rm
= inst
.operands
[1].reg
;
12316 if (inst
.instruction
== T_MNEM_cmp
12317 || inst
.instruction
== T_MNEM_cmn
)
12318 constraint (Rn
== REG_PC
, BAD_PC
);
12320 reject_bad_reg (Rn
);
12321 reject_bad_reg (Rm
);
12323 if (unified_syntax
)
12325 int r0off
= (inst
.instruction
== T_MNEM_mvn
12326 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12327 bfd_boolean narrow
;
12329 if (inst
.size_req
== 4
12330 || inst
.instruction
> 0xffff
12331 || inst
.operands
[1].shifted
12332 || Rn
> 7 || Rm
> 7)
12334 else if (inst
.instruction
== T_MNEM_cmn
12335 || inst
.instruction
== T_MNEM_tst
)
12337 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12338 narrow
= !in_it_block ();
12340 narrow
= in_it_block ();
12342 if (!inst
.operands
[1].isreg
)
12344 /* For an immediate, we always generate a 32-bit opcode;
12345 section relaxation will shrink it later if possible. */
12346 if (inst
.instruction
< 0xffff)
12347 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12348 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12349 inst
.instruction
|= Rn
<< r0off
;
12350 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12354 /* See if we can do this with a 16-bit instruction. */
12357 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12358 inst
.instruction
|= Rn
;
12359 inst
.instruction
|= Rm
<< 3;
12363 constraint (inst
.operands
[1].shifted
12364 && inst
.operands
[1].immisreg
,
12365 _("shift must be constant"));
12366 if (inst
.instruction
< 0xffff)
12367 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12368 inst
.instruction
|= Rn
<< r0off
;
12369 encode_thumb32_shifted_operand (1);
12375 constraint (inst
.instruction
> 0xffff
12376 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12377 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12378 _("unshifted register required"));
12379 constraint (Rn
> 7 || Rm
> 7,
12382 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12383 inst
.instruction
|= Rn
;
12384 inst
.instruction
|= Rm
<< 3;
12393 if (do_vfp_nsyn_mrs () == SUCCESS
)
12396 Rd
= inst
.operands
[0].reg
;
12397 reject_bad_reg (Rd
);
12398 inst
.instruction
|= Rd
<< 8;
12400 if (inst
.operands
[1].isreg
)
12402 unsigned br
= inst
.operands
[1].reg
;
12403 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12404 as_bad (_("bad register for mrs"));
12406 inst
.instruction
|= br
& (0xf << 16);
12407 inst
.instruction
|= (br
& 0x300) >> 4;
12408 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12412 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12414 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12416 /* PR gas/12698: The constraint is only applied for m_profile.
12417 If the user has specified -march=all, we want to ignore it as
12418 we are building for any CPU type, including non-m variants. */
12419 bfd_boolean m_profile
=
12420 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12421 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12422 "not support requested special purpose register"));
12425 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12427 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12428 _("'APSR', 'CPSR' or 'SPSR' expected"));
12430 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12431 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12432 inst
.instruction
|= 0xf0000;
12442 if (do_vfp_nsyn_msr () == SUCCESS
)
12445 constraint (!inst
.operands
[1].isreg
,
12446 _("Thumb encoding does not support an immediate here"));
12448 if (inst
.operands
[0].isreg
)
12449 flags
= (int)(inst
.operands
[0].reg
);
12451 flags
= inst
.operands
[0].imm
;
12453 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12455 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12457 /* PR gas/12698: The constraint is only applied for m_profile.
12458 If the user has specified -march=all, we want to ignore it as
12459 we are building for any CPU type, including non-m variants. */
12460 bfd_boolean m_profile
=
12461 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12462 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12463 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12464 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12465 && bits
!= PSR_f
)) && m_profile
,
12466 _("selected processor does not support requested special "
12467 "purpose register"));
12470 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12471 "requested special purpose register"));
12473 Rn
= inst
.operands
[1].reg
;
12474 reject_bad_reg (Rn
);
12476 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12477 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12478 inst
.instruction
|= (flags
& 0x300) >> 4;
12479 inst
.instruction
|= (flags
& 0xff);
12480 inst
.instruction
|= Rn
<< 16;
12486 bfd_boolean narrow
;
12487 unsigned Rd
, Rn
, Rm
;
12489 if (!inst
.operands
[2].present
)
12490 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12492 Rd
= inst
.operands
[0].reg
;
12493 Rn
= inst
.operands
[1].reg
;
12494 Rm
= inst
.operands
[2].reg
;
12496 if (unified_syntax
)
12498 if (inst
.size_req
== 4
12504 else if (inst
.instruction
== T_MNEM_muls
)
12505 narrow
= !in_it_block ();
12507 narrow
= in_it_block ();
12511 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12512 constraint (Rn
> 7 || Rm
> 7,
12519 /* 16-bit MULS/Conditional MUL. */
12520 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12521 inst
.instruction
|= Rd
;
12524 inst
.instruction
|= Rm
<< 3;
12526 inst
.instruction
|= Rn
<< 3;
12528 constraint (1, _("dest must overlap one source register"));
12532 constraint (inst
.instruction
!= T_MNEM_mul
,
12533 _("Thumb-2 MUL must not set flags"));
12535 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12536 inst
.instruction
|= Rd
<< 8;
12537 inst
.instruction
|= Rn
<< 16;
12538 inst
.instruction
|= Rm
<< 0;
12540 reject_bad_reg (Rd
);
12541 reject_bad_reg (Rn
);
12542 reject_bad_reg (Rm
);
12549 unsigned RdLo
, RdHi
, Rn
, Rm
;
12551 RdLo
= inst
.operands
[0].reg
;
12552 RdHi
= inst
.operands
[1].reg
;
12553 Rn
= inst
.operands
[2].reg
;
12554 Rm
= inst
.operands
[3].reg
;
12556 reject_bad_reg (RdLo
);
12557 reject_bad_reg (RdHi
);
12558 reject_bad_reg (Rn
);
12559 reject_bad_reg (Rm
);
12561 inst
.instruction
|= RdLo
<< 12;
12562 inst
.instruction
|= RdHi
<< 8;
12563 inst
.instruction
|= Rn
<< 16;
12564 inst
.instruction
|= Rm
;
12567 as_tsktsk (_("rdhi and rdlo must be different"));
12573 set_it_insn_type (NEUTRAL_IT_INSN
);
12575 if (unified_syntax
)
12577 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12579 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12580 inst
.instruction
|= inst
.operands
[0].imm
;
12584 /* PR9722: Check for Thumb2 availability before
12585 generating a thumb2 nop instruction. */
12586 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12588 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12589 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12592 inst
.instruction
= 0x46c0;
12597 constraint (inst
.operands
[0].present
,
12598 _("Thumb does not support NOP with hints"));
12599 inst
.instruction
= 0x46c0;
12606 if (unified_syntax
)
12608 bfd_boolean narrow
;
12610 if (THUMB_SETS_FLAGS (inst
.instruction
))
12611 narrow
= !in_it_block ();
12613 narrow
= in_it_block ();
12614 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12616 if (inst
.size_req
== 4)
12621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12622 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12623 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12627 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12628 inst
.instruction
|= inst
.operands
[0].reg
;
12629 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12634 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12636 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12638 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12639 inst
.instruction
|= inst
.operands
[0].reg
;
12640 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12649 Rd
= inst
.operands
[0].reg
;
12650 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12652 reject_bad_reg (Rd
);
12653 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12654 reject_bad_reg (Rn
);
12656 inst
.instruction
|= Rd
<< 8;
12657 inst
.instruction
|= Rn
<< 16;
12659 if (!inst
.operands
[2].isreg
)
12661 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12662 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12668 Rm
= inst
.operands
[2].reg
;
12669 reject_bad_reg (Rm
);
12671 constraint (inst
.operands
[2].shifted
12672 && inst
.operands
[2].immisreg
,
12673 _("shift must be constant"));
12674 encode_thumb32_shifted_operand (2);
12681 unsigned Rd
, Rn
, Rm
;
12683 Rd
= inst
.operands
[0].reg
;
12684 Rn
= inst
.operands
[1].reg
;
12685 Rm
= inst
.operands
[2].reg
;
12687 reject_bad_reg (Rd
);
12688 reject_bad_reg (Rn
);
12689 reject_bad_reg (Rm
);
12691 inst
.instruction
|= Rd
<< 8;
12692 inst
.instruction
|= Rn
<< 16;
12693 inst
.instruction
|= Rm
;
12694 if (inst
.operands
[3].present
)
12696 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
12697 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
12698 _("expression too complex"));
12699 inst
.instruction
|= (val
& 0x1c) << 10;
12700 inst
.instruction
|= (val
& 0x03) << 6;
12707 if (!inst
.operands
[3].present
)
12711 inst
.instruction
&= ~0x00000020;
12713 /* PR 10168. Swap the Rm and Rn registers. */
12714 Rtmp
= inst
.operands
[1].reg
;
12715 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12716 inst
.operands
[2].reg
= Rtmp
;
12724 if (inst
.operands
[0].immisreg
)
12725 reject_bad_reg (inst
.operands
[0].imm
);
12727 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12731 do_t_push_pop (void)
12735 constraint (inst
.operands
[0].writeback
,
12736 _("push/pop do not support {reglist}^"));
12737 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12738 _("expression too complex"));
12740 mask
= inst
.operands
[0].imm
;
12741 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12742 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12743 else if (inst
.size_req
!= 4
12744 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12745 ? REG_LR
: REG_PC
)))
12747 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12748 inst
.instruction
|= THUMB_PP_PC_LR
;
12749 inst
.instruction
|= mask
& 0xff;
12751 else if (unified_syntax
)
12753 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12754 encode_thumb2_ldmstm (13, mask
, TRUE
);
12758 inst
.error
= _("invalid register list to push/pop instruction");
12768 Rd
= inst
.operands
[0].reg
;
12769 Rm
= inst
.operands
[1].reg
;
12771 reject_bad_reg (Rd
);
12772 reject_bad_reg (Rm
);
12774 inst
.instruction
|= Rd
<< 8;
12775 inst
.instruction
|= Rm
<< 16;
12776 inst
.instruction
|= Rm
;
12784 Rd
= inst
.operands
[0].reg
;
12785 Rm
= inst
.operands
[1].reg
;
12787 reject_bad_reg (Rd
);
12788 reject_bad_reg (Rm
);
12790 if (Rd
<= 7 && Rm
<= 7
12791 && inst
.size_req
!= 4)
12793 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12794 inst
.instruction
|= Rd
;
12795 inst
.instruction
|= Rm
<< 3;
12797 else if (unified_syntax
)
12799 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12800 inst
.instruction
|= Rd
<< 8;
12801 inst
.instruction
|= Rm
<< 16;
12802 inst
.instruction
|= Rm
;
12805 inst
.error
= BAD_HIREG
;
12813 Rd
= inst
.operands
[0].reg
;
12814 Rm
= inst
.operands
[1].reg
;
12816 reject_bad_reg (Rd
);
12817 reject_bad_reg (Rm
);
12819 inst
.instruction
|= Rd
<< 8;
12820 inst
.instruction
|= Rm
;
12828 Rd
= inst
.operands
[0].reg
;
12829 Rs
= (inst
.operands
[1].present
12830 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12831 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12833 reject_bad_reg (Rd
);
12834 reject_bad_reg (Rs
);
12835 if (inst
.operands
[2].isreg
)
12836 reject_bad_reg (inst
.operands
[2].reg
);
12838 inst
.instruction
|= Rd
<< 8;
12839 inst
.instruction
|= Rs
<< 16;
12840 if (!inst
.operands
[2].isreg
)
12842 bfd_boolean narrow
;
12844 if ((inst
.instruction
& 0x00100000) != 0)
12845 narrow
= !in_it_block ();
12847 narrow
= in_it_block ();
12849 if (Rd
> 7 || Rs
> 7)
12852 if (inst
.size_req
== 4 || !unified_syntax
)
12855 if (inst
.relocs
[0].exp
.X_op
!= O_constant
12856 || inst
.relocs
[0].exp
.X_add_number
!= 0)
12859 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12860 relaxation, but it doesn't seem worth the hassle. */
12863 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12864 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12865 inst
.instruction
|= Rs
<< 3;
12866 inst
.instruction
|= Rd
;
12870 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12871 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12875 encode_thumb32_shifted_operand (2);
12881 if (warn_on_deprecated
12882 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12883 as_tsktsk (_("setend use is deprecated for ARMv8"));
12885 set_it_insn_type (OUTSIDE_IT_INSN
);
12886 if (inst
.operands
[0].imm
)
12887 inst
.instruction
|= 0x8;
12893 if (!inst
.operands
[1].present
)
12894 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12896 if (unified_syntax
)
12898 bfd_boolean narrow
;
12901 switch (inst
.instruction
)
12904 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12906 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12908 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12910 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12914 if (THUMB_SETS_FLAGS (inst
.instruction
))
12915 narrow
= !in_it_block ();
12917 narrow
= in_it_block ();
12918 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12920 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12922 if (inst
.operands
[2].isreg
12923 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12924 || inst
.operands
[2].reg
> 7))
12926 if (inst
.size_req
== 4)
12929 reject_bad_reg (inst
.operands
[0].reg
);
12930 reject_bad_reg (inst
.operands
[1].reg
);
12934 if (inst
.operands
[2].isreg
)
12936 reject_bad_reg (inst
.operands
[2].reg
);
12937 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12938 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12940 inst
.instruction
|= inst
.operands
[2].reg
;
12942 /* PR 12854: Error on extraneous shifts. */
12943 constraint (inst
.operands
[2].shifted
,
12944 _("extraneous shift as part of operand to shift insn"));
12948 inst
.operands
[1].shifted
= 1;
12949 inst
.operands
[1].shift_kind
= shift_kind
;
12950 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12951 ? T_MNEM_movs
: T_MNEM_mov
);
12952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12953 encode_thumb32_shifted_operand (1);
12954 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12955 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12960 if (inst
.operands
[2].isreg
)
12962 switch (shift_kind
)
12964 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12965 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12966 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12967 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12971 inst
.instruction
|= inst
.operands
[0].reg
;
12972 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12974 /* PR 12854: Error on extraneous shifts. */
12975 constraint (inst
.operands
[2].shifted
,
12976 _("extraneous shift as part of operand to shift insn"));
12980 switch (shift_kind
)
12982 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12983 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12984 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12987 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12988 inst
.instruction
|= inst
.operands
[0].reg
;
12989 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12995 constraint (inst
.operands
[0].reg
> 7
12996 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12997 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12999 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13001 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13002 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13003 _("source1 and dest must be same register"));
13005 switch (inst
.instruction
)
13007 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13008 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13009 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13010 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13014 inst
.instruction
|= inst
.operands
[0].reg
;
13015 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13017 /* PR 12854: Error on extraneous shifts. */
13018 constraint (inst
.operands
[2].shifted
,
13019 _("extraneous shift as part of operand to shift insn"));
13023 switch (inst
.instruction
)
13025 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13026 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13027 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13028 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13031 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13032 inst
.instruction
|= inst
.operands
[0].reg
;
13033 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13041 unsigned Rd
, Rn
, Rm
;
13043 Rd
= inst
.operands
[0].reg
;
13044 Rn
= inst
.operands
[1].reg
;
13045 Rm
= inst
.operands
[2].reg
;
13047 reject_bad_reg (Rd
);
13048 reject_bad_reg (Rn
);
13049 reject_bad_reg (Rm
);
13051 inst
.instruction
|= Rd
<< 8;
13052 inst
.instruction
|= Rn
<< 16;
13053 inst
.instruction
|= Rm
;
13059 unsigned Rd
, Rn
, Rm
;
13061 Rd
= inst
.operands
[0].reg
;
13062 Rm
= inst
.operands
[1].reg
;
13063 Rn
= inst
.operands
[2].reg
;
13065 reject_bad_reg (Rd
);
13066 reject_bad_reg (Rn
);
13067 reject_bad_reg (Rm
);
13069 inst
.instruction
|= Rd
<< 8;
13070 inst
.instruction
|= Rn
<< 16;
13071 inst
.instruction
|= Rm
;
13077 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13078 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13079 _("SMC is not permitted on this architecture"));
13080 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13081 _("expression too complex"));
13082 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13083 inst
.instruction
|= (value
& 0xf000) >> 12;
13084 inst
.instruction
|= (value
& 0x0ff0);
13085 inst
.instruction
|= (value
& 0x000f) << 16;
13086 /* PR gas/15623: SMC instructions must be last in an IT block. */
13087 set_it_insn_type_last ();
13093 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13095 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13096 inst
.instruction
|= (value
& 0x0fff);
13097 inst
.instruction
|= (value
& 0xf000) << 4;
13101 do_t_ssat_usat (int bias
)
13105 Rd
= inst
.operands
[0].reg
;
13106 Rn
= inst
.operands
[2].reg
;
13108 reject_bad_reg (Rd
);
13109 reject_bad_reg (Rn
);
13111 inst
.instruction
|= Rd
<< 8;
13112 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13113 inst
.instruction
|= Rn
<< 16;
13115 if (inst
.operands
[3].present
)
13117 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13119 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13121 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13122 _("expression too complex"));
13124 if (shift_amount
!= 0)
13126 constraint (shift_amount
> 31,
13127 _("shift expression is too large"));
13129 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13130 inst
.instruction
|= 0x00200000; /* sh bit. */
13132 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13133 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13141 do_t_ssat_usat (1);
13149 Rd
= inst
.operands
[0].reg
;
13150 Rn
= inst
.operands
[2].reg
;
13152 reject_bad_reg (Rd
);
13153 reject_bad_reg (Rn
);
13155 inst
.instruction
|= Rd
<< 8;
13156 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13157 inst
.instruction
|= Rn
<< 16;
13163 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13164 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13165 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13166 || inst
.operands
[2].negative
,
13169 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13171 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13172 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13173 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13174 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13180 if (!inst
.operands
[2].present
)
13181 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13183 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13184 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13185 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13188 inst
.instruction
|= inst
.operands
[0].reg
;
13189 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13190 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13191 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13197 unsigned Rd
, Rn
, Rm
;
13199 Rd
= inst
.operands
[0].reg
;
13200 Rn
= inst
.operands
[1].reg
;
13201 Rm
= inst
.operands
[2].reg
;
13203 reject_bad_reg (Rd
);
13204 reject_bad_reg (Rn
);
13205 reject_bad_reg (Rm
);
13207 inst
.instruction
|= Rd
<< 8;
13208 inst
.instruction
|= Rn
<< 16;
13209 inst
.instruction
|= Rm
;
13210 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13218 Rd
= inst
.operands
[0].reg
;
13219 Rm
= inst
.operands
[1].reg
;
13221 reject_bad_reg (Rd
);
13222 reject_bad_reg (Rm
);
13224 if (inst
.instruction
<= 0xffff
13225 && inst
.size_req
!= 4
13226 && Rd
<= 7 && Rm
<= 7
13227 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13229 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13230 inst
.instruction
|= Rd
;
13231 inst
.instruction
|= Rm
<< 3;
13233 else if (unified_syntax
)
13235 if (inst
.instruction
<= 0xffff)
13236 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13237 inst
.instruction
|= Rd
<< 8;
13238 inst
.instruction
|= Rm
;
13239 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13243 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13244 _("Thumb encoding does not support rotation"));
13245 constraint (1, BAD_HIREG
);
13252 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13261 half
= (inst
.instruction
& 0x10) != 0;
13262 set_it_insn_type_last ();
13263 constraint (inst
.operands
[0].immisreg
,
13264 _("instruction requires register index"));
13266 Rn
= inst
.operands
[0].reg
;
13267 Rm
= inst
.operands
[0].imm
;
13269 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13270 constraint (Rn
== REG_SP
, BAD_SP
);
13271 reject_bad_reg (Rm
);
13273 constraint (!half
&& inst
.operands
[0].shifted
,
13274 _("instruction does not allow shifted index"));
13275 inst
.instruction
|= (Rn
<< 16) | Rm
;
13281 if (!inst
.operands
[0].present
)
13282 inst
.operands
[0].imm
= 0;
13284 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13286 constraint (inst
.size_req
== 2,
13287 _("immediate value out of range"));
13288 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13289 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13290 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13294 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13295 inst
.instruction
|= inst
.operands
[0].imm
;
13298 set_it_insn_type (NEUTRAL_IT_INSN
);
13305 do_t_ssat_usat (0);
13313 Rd
= inst
.operands
[0].reg
;
13314 Rn
= inst
.operands
[2].reg
;
13316 reject_bad_reg (Rd
);
13317 reject_bad_reg (Rn
);
13319 inst
.instruction
|= Rd
<< 8;
13320 inst
.instruction
|= inst
.operands
[1].imm
;
13321 inst
.instruction
|= Rn
<< 16;
13324 /* Checking the range of the branch offset (VAL) with NBITS bits
13325 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13327 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13329 gas_assert (nbits
> 0 && nbits
<= 32);
13332 int cmp
= (1 << (nbits
- 1));
13333 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13338 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13344 /* For branches in Armv8.1-M Mainline. */
13346 do_t_branch_future (void)
13348 unsigned long insn
= inst
.instruction
;
13350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13351 if (inst
.operands
[0].hasreloc
== 0)
13353 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13354 as_bad (BAD_BRANCH_OFF
);
13356 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13360 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13361 inst
.relocs
[0].pc_rel
= 1;
13367 if (inst
.operands
[1].hasreloc
== 0)
13369 int val
= inst
.operands
[1].imm
;
13370 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13371 as_bad (BAD_BRANCH_OFF
);
13373 int immA
= (val
& 0x0001f000) >> 12;
13374 int immB
= (val
& 0x00000ffc) >> 2;
13375 int immC
= (val
& 0x00000002) >> 1;
13376 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13380 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13381 inst
.relocs
[1].pc_rel
= 1;
13386 if (inst
.operands
[1].hasreloc
== 0)
13388 int val
= inst
.operands
[1].imm
;
13389 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13390 as_bad (BAD_BRANCH_OFF
);
13392 int immA
= (val
& 0x0007f000) >> 12;
13393 int immB
= (val
& 0x00000ffc) >> 2;
13394 int immC
= (val
& 0x00000002) >> 1;
13395 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13399 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13400 inst
.relocs
[1].pc_rel
= 1;
13404 case T_MNEM_bfcsel
:
13406 if (inst
.operands
[1].hasreloc
== 0)
13408 int val
= inst
.operands
[1].imm
;
13409 int immA
= (val
& 0x00001000) >> 12;
13410 int immB
= (val
& 0x00000ffc) >> 2;
13411 int immC
= (val
& 0x00000002) >> 1;
13412 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13416 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
13417 inst
.relocs
[1].pc_rel
= 1;
13421 if (inst
.operands
[2].hasreloc
== 0)
13423 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
13424 int val2
= inst
.operands
[2].imm
;
13425 int val0
= inst
.operands
[0].imm
& 0x1f;
13426 int diff
= val2
- val0
;
13428 inst
.instruction
|= 1 << 17; /* T bit. */
13429 else if (diff
!= 2)
13430 as_bad (_("out of range label-relative fixup value"));
13434 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
13435 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
13436 inst
.relocs
[2].pc_rel
= 1;
13440 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
13441 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
13446 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13453 /* Helper function for do_t_loloop to handle relocations. */
13455 v8_1_loop_reloc (int is_le
)
13457 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
13459 int value
= inst
.relocs
[0].exp
.X_add_number
;
13460 value
= (is_le
) ? -value
: value
;
13462 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
13463 as_bad (BAD_BRANCH_OFF
);
13467 immh
= (value
& 0x00000ffc) >> 2;
13468 imml
= (value
& 0x00000002) >> 1;
13470 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
13474 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
13475 inst
.relocs
[0].pc_rel
= 1;
13479 /* To handle the Scalar Low Overhead Loop instructions
13480 in Armv8.1-M Mainline. */
13484 unsigned long insn
= inst
.instruction
;
13486 set_it_insn_type (OUTSIDE_IT_INSN
);
13487 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13493 if (!inst
.operands
[0].present
)
13494 inst
.instruction
|= 1 << 21;
13496 v8_1_loop_reloc (TRUE
);
13500 v8_1_loop_reloc (FALSE
);
13501 /* Fall through. */
13503 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
13504 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
13511 /* Neon instruction encoder helpers. */
13513 /* Encodings for the different types for various Neon opcodes. */
13515 /* An "invalid" code for the following tables. */
13518 struct neon_tab_entry
13521 unsigned float_or_poly
;
13522 unsigned scalar_or_imm
;
13525 /* Map overloaded Neon opcodes to their respective encodings. */
13526 #define NEON_ENC_TAB \
13527 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13528 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13529 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13530 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13531 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13532 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13533 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13534 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13535 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13536 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13537 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13538 /* Register variants of the following two instructions are encoded as
13539 vcge / vcgt with the operands reversed. */ \
13540 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13541 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13542 X(vfma, N_INV, 0x0000c10, N_INV), \
13543 X(vfms, N_INV, 0x0200c10, N_INV), \
13544 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13545 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13546 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13547 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13548 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13549 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13550 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13551 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13552 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13553 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13554 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13555 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13556 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13557 X(vshl, 0x0000400, N_INV, 0x0800510), \
13558 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13559 X(vand, 0x0000110, N_INV, 0x0800030), \
13560 X(vbic, 0x0100110, N_INV, 0x0800030), \
13561 X(veor, 0x1000110, N_INV, N_INV), \
13562 X(vorn, 0x0300110, N_INV, 0x0800010), \
13563 X(vorr, 0x0200110, N_INV, 0x0800010), \
13564 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13565 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13566 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13567 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13568 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13569 X(vst1, 0x0000000, 0x0800000, N_INV), \
13570 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13571 X(vst2, 0x0000100, 0x0800100, N_INV), \
13572 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13573 X(vst3, 0x0000200, 0x0800200, N_INV), \
13574 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13575 X(vst4, 0x0000300, 0x0800300, N_INV), \
13576 X(vmovn, 0x1b20200, N_INV, N_INV), \
13577 X(vtrn, 0x1b20080, N_INV, N_INV), \
13578 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13579 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13580 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13581 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13582 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13583 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13584 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13585 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13586 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13587 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13588 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13589 X(vseleq, 0xe000a00, N_INV, N_INV), \
13590 X(vselvs, 0xe100a00, N_INV, N_INV), \
13591 X(vselge, 0xe200a00, N_INV, N_INV), \
13592 X(vselgt, 0xe300a00, N_INV, N_INV), \
13593 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13594 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13595 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13596 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13597 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13598 X(aes, 0x3b00300, N_INV, N_INV), \
13599 X(sha3op, 0x2000c00, N_INV, N_INV), \
13600 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13601 X(sha2op, 0x3ba0380, N_INV, N_INV)
13605 #define X(OPC,I,F,S) N_MNEM_##OPC
13610 static const struct neon_tab_entry neon_enc_tab
[] =
13612 #define X(OPC,I,F,S) { (I), (F), (S) }
13617 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13618 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13619 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13620 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13621 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13622 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13623 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13624 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13625 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13626 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13627 #define NEON_ENC_SINGLE_(X) \
13628 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13629 #define NEON_ENC_DOUBLE_(X) \
13630 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13631 #define NEON_ENC_FPV8_(X) \
13632 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13634 #define NEON_ENCODE(type, inst) \
13637 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13638 inst.is_neon = 1; \
13642 #define check_neon_suffixes \
13645 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13647 as_bad (_("invalid neon suffix for non neon instruction")); \
13653 /* Define shapes for instruction operands. The following mnemonic characters
13654 are used in this table:
13656 F - VFP S<n> register
13657 D - Neon D<n> register
13658 Q - Neon Q<n> register
13662 L - D<n> register list
13664 This table is used to generate various data:
13665 - enumerations of the form NS_DDR to be used as arguments to
13667 - a table classifying shapes into single, double, quad, mixed.
13668 - a table used to drive neon_select_shape. */
13670 #define NEON_SHAPE_DEF \
13671 X(3, (D, D, D), DOUBLE), \
13672 X(3, (Q, Q, Q), QUAD), \
13673 X(3, (D, D, I), DOUBLE), \
13674 X(3, (Q, Q, I), QUAD), \
13675 X(3, (D, D, S), DOUBLE), \
13676 X(3, (Q, Q, S), QUAD), \
13677 X(2, (D, D), DOUBLE), \
13678 X(2, (Q, Q), QUAD), \
13679 X(2, (D, S), DOUBLE), \
13680 X(2, (Q, S), QUAD), \
13681 X(2, (D, R), DOUBLE), \
13682 X(2, (Q, R), QUAD), \
13683 X(2, (D, I), DOUBLE), \
13684 X(2, (Q, I), QUAD), \
13685 X(3, (D, L, D), DOUBLE), \
13686 X(2, (D, Q), MIXED), \
13687 X(2, (Q, D), MIXED), \
13688 X(3, (D, Q, I), MIXED), \
13689 X(3, (Q, D, I), MIXED), \
13690 X(3, (Q, D, D), MIXED), \
13691 X(3, (D, Q, Q), MIXED), \
13692 X(3, (Q, Q, D), MIXED), \
13693 X(3, (Q, D, S), MIXED), \
13694 X(3, (D, Q, S), MIXED), \
13695 X(4, (D, D, D, I), DOUBLE), \
13696 X(4, (Q, Q, Q, I), QUAD), \
13697 X(4, (D, D, S, I), DOUBLE), \
13698 X(4, (Q, Q, S, I), QUAD), \
13699 X(2, (F, F), SINGLE), \
13700 X(3, (F, F, F), SINGLE), \
13701 X(2, (F, I), SINGLE), \
13702 X(2, (F, D), MIXED), \
13703 X(2, (D, F), MIXED), \
13704 X(3, (F, F, I), MIXED), \
13705 X(4, (R, R, F, F), SINGLE), \
13706 X(4, (F, F, R, R), SINGLE), \
13707 X(3, (D, R, R), DOUBLE), \
13708 X(3, (R, R, D), DOUBLE), \
13709 X(2, (S, R), SINGLE), \
13710 X(2, (R, S), SINGLE), \
13711 X(2, (F, R), SINGLE), \
13712 X(2, (R, F), SINGLE), \
13713 /* Half float shape supported so far. */\
13714 X (2, (H, D), MIXED), \
13715 X (2, (D, H), MIXED), \
13716 X (2, (H, F), MIXED), \
13717 X (2, (F, H), MIXED), \
13718 X (2, (H, H), HALF), \
13719 X (2, (H, R), HALF), \
13720 X (2, (R, H), HALF), \
13721 X (2, (H, I), HALF), \
13722 X (3, (H, H, H), HALF), \
13723 X (3, (H, F, I), MIXED), \
13724 X (3, (F, H, I), MIXED), \
13725 X (3, (D, H, H), MIXED), \
13726 X (3, (D, H, S), MIXED)
13728 #define S2(A,B) NS_##A##B
13729 #define S3(A,B,C) NS_##A##B##C
13730 #define S4(A,B,C,D) NS_##A##B##C##D
13732 #define X(N, L, C) S##N L
13745 enum neon_shape_class
13754 #define X(N, L, C) SC_##C
13756 static enum neon_shape_class neon_shape_class
[] =
13775 /* Register widths of above. */
13776 static unsigned neon_shape_el_size
[] =
13788 struct neon_shape_info
13791 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13794 #define S2(A,B) { SE_##A, SE_##B }
13795 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13796 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13798 #define X(N, L, C) { N, S##N L }
13800 static struct neon_shape_info neon_shape_tab
[] =
13810 /* Bit masks used in type checking given instructions.
13811 'N_EQK' means the type must be the same as (or based on in some way) the key
13812 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13813 set, various other bits can be set as well in order to modify the meaning of
13814 the type constraint. */
13816 enum neon_type_mask
13840 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13841 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13842 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13843 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13844 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13845 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13846 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13847 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13848 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13849 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13850 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13852 N_MAX_NONSPECIAL
= N_P64
13855 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13857 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13858 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13859 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13860 #define N_S_32 (N_S8 | N_S16 | N_S32)
13861 #define N_F_16_32 (N_F16 | N_F32)
13862 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13863 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13864 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13865 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13867 /* Pass this as the first type argument to neon_check_type to ignore types
13869 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13871 /* Select a "shape" for the current instruction (describing register types or
13872 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13873 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13874 function of operand parsing, so this function doesn't need to be called.
13875 Shapes should be listed in order of decreasing length. */
13877 static enum neon_shape
13878 neon_select_shape (enum neon_shape shape
, ...)
13881 enum neon_shape first_shape
= shape
;
13883 /* Fix missing optional operands. FIXME: we don't know at this point how
13884 many arguments we should have, so this makes the assumption that we have
13885 > 1. This is true of all current Neon opcodes, I think, but may not be
13886 true in the future. */
13887 if (!inst
.operands
[1].present
)
13888 inst
.operands
[1] = inst
.operands
[0];
13890 va_start (ap
, shape
);
13892 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13897 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13899 if (!inst
.operands
[j
].present
)
13905 switch (neon_shape_tab
[shape
].el
[j
])
13907 /* If a .f16, .16, .u16, .s16 type specifier is given over
13908 a VFP single precision register operand, it's essentially
13909 means only half of the register is used.
13911 If the type specifier is given after the mnemonics, the
13912 information is stored in inst.vectype. If the type specifier
13913 is given after register operand, the information is stored
13914 in inst.operands[].vectype.
13916 When there is only one type specifier, and all the register
13917 operands are the same type of hardware register, the type
13918 specifier applies to all register operands.
13920 If no type specifier is given, the shape is inferred from
13921 operand information.
13924 vadd.f16 s0, s1, s2: NS_HHH
13925 vabs.f16 s0, s1: NS_HH
13926 vmov.f16 s0, r1: NS_HR
13927 vmov.f16 r0, s1: NS_RH
13928 vcvt.f16 r0, s1: NS_RH
13929 vcvt.f16.s32 s2, s2, #29: NS_HFI
13930 vcvt.f16.s32 s2, s2: NS_HF
13933 if (!(inst
.operands
[j
].isreg
13934 && inst
.operands
[j
].isvec
13935 && inst
.operands
[j
].issingle
13936 && !inst
.operands
[j
].isquad
13937 && ((inst
.vectype
.elems
== 1
13938 && inst
.vectype
.el
[0].size
== 16)
13939 || (inst
.vectype
.elems
> 1
13940 && inst
.vectype
.el
[j
].size
== 16)
13941 || (inst
.vectype
.elems
== 0
13942 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13943 && inst
.operands
[j
].vectype
.size
== 16))))
13948 if (!(inst
.operands
[j
].isreg
13949 && inst
.operands
[j
].isvec
13950 && inst
.operands
[j
].issingle
13951 && !inst
.operands
[j
].isquad
13952 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13953 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13954 || (inst
.vectype
.elems
== 0
13955 && (inst
.operands
[j
].vectype
.size
== 32
13956 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13961 if (!(inst
.operands
[j
].isreg
13962 && inst
.operands
[j
].isvec
13963 && !inst
.operands
[j
].isquad
13964 && !inst
.operands
[j
].issingle
))
13969 if (!(inst
.operands
[j
].isreg
13970 && !inst
.operands
[j
].isvec
))
13975 if (!(inst
.operands
[j
].isreg
13976 && inst
.operands
[j
].isvec
13977 && inst
.operands
[j
].isquad
13978 && !inst
.operands
[j
].issingle
))
13983 if (!(!inst
.operands
[j
].isreg
13984 && !inst
.operands
[j
].isscalar
))
13989 if (!(!inst
.operands
[j
].isreg
13990 && inst
.operands
[j
].isscalar
))
14000 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14001 /* We've matched all the entries in the shape table, and we don't
14002 have any left over operands which have not been matched. */
14008 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14009 first_error (_("invalid instruction shape"));
14014 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14015 means the Q bit should be set). */
14018 neon_quad (enum neon_shape shape
)
14020 return neon_shape_class
[shape
] == SC_QUAD
;
14024 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14027 /* Allow modification to be made to types which are constrained to be
14028 based on the key element, based on bits set alongside N_EQK. */
14029 if ((typebits
& N_EQK
) != 0)
14031 if ((typebits
& N_HLF
) != 0)
14033 else if ((typebits
& N_DBL
) != 0)
14035 if ((typebits
& N_SGN
) != 0)
14036 *g_type
= NT_signed
;
14037 else if ((typebits
& N_UNS
) != 0)
14038 *g_type
= NT_unsigned
;
14039 else if ((typebits
& N_INT
) != 0)
14040 *g_type
= NT_integer
;
14041 else if ((typebits
& N_FLT
) != 0)
14042 *g_type
= NT_float
;
14043 else if ((typebits
& N_SIZ
) != 0)
14044 *g_type
= NT_untyped
;
14048 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14049 operand type, i.e. the single type specified in a Neon instruction when it
14050 is the only one given. */
14052 static struct neon_type_el
14053 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14055 struct neon_type_el dest
= *key
;
14057 gas_assert ((thisarg
& N_EQK
) != 0);
14059 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14064 /* Convert Neon type and size into compact bitmask representation. */
14066 static enum neon_type_mask
14067 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14074 case 8: return N_8
;
14075 case 16: return N_16
;
14076 case 32: return N_32
;
14077 case 64: return N_64
;
14085 case 8: return N_I8
;
14086 case 16: return N_I16
;
14087 case 32: return N_I32
;
14088 case 64: return N_I64
;
14096 case 16: return N_F16
;
14097 case 32: return N_F32
;
14098 case 64: return N_F64
;
14106 case 8: return N_P8
;
14107 case 16: return N_P16
;
14108 case 64: return N_P64
;
14116 case 8: return N_S8
;
14117 case 16: return N_S16
;
14118 case 32: return N_S32
;
14119 case 64: return N_S64
;
14127 case 8: return N_U8
;
14128 case 16: return N_U16
;
14129 case 32: return N_U32
;
14130 case 64: return N_U64
;
14141 /* Convert compact Neon bitmask type representation to a type and size. Only
14142 handles the case where a single bit is set in the mask. */
14145 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14146 enum neon_type_mask mask
)
14148 if ((mask
& N_EQK
) != 0)
14151 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14153 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14155 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14157 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14162 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14164 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14165 *type
= NT_unsigned
;
14166 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14167 *type
= NT_integer
;
14168 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14169 *type
= NT_untyped
;
14170 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14172 else if ((mask
& (N_F_ALL
)) != 0)
14180 /* Modify a bitmask of allowed types. This is only needed for type
14184 modify_types_allowed (unsigned allowed
, unsigned mods
)
14187 enum neon_el_type type
;
14193 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14195 if (el_type_of_type_chk (&type
, &size
,
14196 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14198 neon_modify_type_size (mods
, &type
, &size
);
14199 destmask
|= type_chk_of_el_type (type
, size
);
14206 /* Check type and return type classification.
14207 The manual states (paraphrase): If one datatype is given, it indicates the
14209 - the second operand, if there is one
14210 - the operand, if there is no second operand
14211 - the result, if there are no operands.
14212 This isn't quite good enough though, so we use a concept of a "key" datatype
14213 which is set on a per-instruction basis, which is the one which matters when
14214 only one data type is written.
14215 Note: this function has side-effects (e.g. filling in missing operands). All
14216 Neon instructions should call it before performing bit encoding. */
14218 static struct neon_type_el
14219 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14222 unsigned i
, pass
, key_el
= 0;
14223 unsigned types
[NEON_MAX_TYPE_ELS
];
14224 enum neon_el_type k_type
= NT_invtype
;
14225 unsigned k_size
= -1u;
14226 struct neon_type_el badtype
= {NT_invtype
, -1};
14227 unsigned key_allowed
= 0;
14229 /* Optional registers in Neon instructions are always (not) in operand 1.
14230 Fill in the missing operand here, if it was omitted. */
14231 if (els
> 1 && !inst
.operands
[1].present
)
14232 inst
.operands
[1] = inst
.operands
[0];
14234 /* Suck up all the varargs. */
14236 for (i
= 0; i
< els
; i
++)
14238 unsigned thisarg
= va_arg (ap
, unsigned);
14239 if (thisarg
== N_IGNORE_TYPE
)
14244 types
[i
] = thisarg
;
14245 if ((thisarg
& N_KEY
) != 0)
14250 if (inst
.vectype
.elems
> 0)
14251 for (i
= 0; i
< els
; i
++)
14252 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14254 first_error (_("types specified in both the mnemonic and operands"));
14258 /* Duplicate inst.vectype elements here as necessary.
14259 FIXME: No idea if this is exactly the same as the ARM assembler,
14260 particularly when an insn takes one register and one non-register
14262 if (inst
.vectype
.elems
== 1 && els
> 1)
14265 inst
.vectype
.elems
= els
;
14266 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14267 for (j
= 0; j
< els
; j
++)
14269 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14272 else if (inst
.vectype
.elems
== 0 && els
> 0)
14275 /* No types were given after the mnemonic, so look for types specified
14276 after each operand. We allow some flexibility here; as long as the
14277 "key" operand has a type, we can infer the others. */
14278 for (j
= 0; j
< els
; j
++)
14279 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14280 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14282 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14284 for (j
= 0; j
< els
; j
++)
14285 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14286 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14291 first_error (_("operand types can't be inferred"));
14295 else if (inst
.vectype
.elems
!= els
)
14297 first_error (_("type specifier has the wrong number of parts"));
14301 for (pass
= 0; pass
< 2; pass
++)
14303 for (i
= 0; i
< els
; i
++)
14305 unsigned thisarg
= types
[i
];
14306 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14307 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14308 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14309 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14311 /* Decay more-specific signed & unsigned types to sign-insensitive
14312 integer types if sign-specific variants are unavailable. */
14313 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14314 && (types_allowed
& N_SU_ALL
) == 0)
14315 g_type
= NT_integer
;
14317 /* If only untyped args are allowed, decay any more specific types to
14318 them. Some instructions only care about signs for some element
14319 sizes, so handle that properly. */
14320 if (((types_allowed
& N_UNT
) == 0)
14321 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14322 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14323 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14324 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14325 g_type
= NT_untyped
;
14329 if ((thisarg
& N_KEY
) != 0)
14333 key_allowed
= thisarg
& ~N_KEY
;
14335 /* Check architecture constraint on FP16 extension. */
14337 && k_type
== NT_float
14338 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14340 inst
.error
= _(BAD_FP16
);
14347 if ((thisarg
& N_VFP
) != 0)
14349 enum neon_shape_el regshape
;
14350 unsigned regwidth
, match
;
14352 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14355 first_error (_("invalid instruction shape"));
14358 regshape
= neon_shape_tab
[ns
].el
[i
];
14359 regwidth
= neon_shape_el_size
[regshape
];
14361 /* In VFP mode, operands must match register widths. If we
14362 have a key operand, use its width, else use the width of
14363 the current operand. */
14369 /* FP16 will use a single precision register. */
14370 if (regwidth
== 32 && match
== 16)
14372 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14376 inst
.error
= _(BAD_FP16
);
14381 if (regwidth
!= match
)
14383 first_error (_("operand size must match register width"));
14388 if ((thisarg
& N_EQK
) == 0)
14390 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14392 if ((given_type
& types_allowed
) == 0)
14394 first_error (_("bad type in Neon instruction"));
14400 enum neon_el_type mod_k_type
= k_type
;
14401 unsigned mod_k_size
= k_size
;
14402 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14403 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14405 first_error (_("inconsistent types in Neon instruction"));
14413 return inst
.vectype
.el
[key_el
];
14416 /* Neon-style VFP instruction forwarding. */
14418 /* Thumb VFP instructions have 0xE in the condition field. */
14421 do_vfp_cond_or_thumb (void)
14426 inst
.instruction
|= 0xe0000000;
14428 inst
.instruction
|= inst
.cond
<< 28;
14431 /* Look up and encode a simple mnemonic, for use as a helper function for the
14432 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14433 etc. It is assumed that operand parsing has already been done, and that the
14434 operands are in the form expected by the given opcode (this isn't necessarily
14435 the same as the form in which they were parsed, hence some massaging must
14436 take place before this function is called).
14437 Checks current arch version against that in the looked-up opcode. */
14440 do_vfp_nsyn_opcode (const char *opname
)
14442 const struct asm_opcode
*opcode
;
14444 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14449 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14450 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14457 inst
.instruction
= opcode
->tvalue
;
14458 opcode
->tencode ();
14462 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14463 opcode
->aencode ();
14468 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14470 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14472 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14475 do_vfp_nsyn_opcode ("fadds");
14477 do_vfp_nsyn_opcode ("fsubs");
14479 /* ARMv8.2 fp16 instruction. */
14481 do_scalar_fp16_v82_encode ();
14486 do_vfp_nsyn_opcode ("faddd");
14488 do_vfp_nsyn_opcode ("fsubd");
14492 /* Check operand types to see if this is a VFP instruction, and if so call
14496 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14498 enum neon_shape rs
;
14499 struct neon_type_el et
;
14504 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14505 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14509 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14510 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14511 N_F_ALL
| N_KEY
| N_VFP
);
14518 if (et
.type
!= NT_invtype
)
14529 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14531 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14533 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14536 do_vfp_nsyn_opcode ("fmacs");
14538 do_vfp_nsyn_opcode ("fnmacs");
14540 /* ARMv8.2 fp16 instruction. */
14542 do_scalar_fp16_v82_encode ();
14547 do_vfp_nsyn_opcode ("fmacd");
14549 do_vfp_nsyn_opcode ("fnmacd");
14554 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14556 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14558 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14561 do_vfp_nsyn_opcode ("ffmas");
14563 do_vfp_nsyn_opcode ("ffnmas");
14565 /* ARMv8.2 fp16 instruction. */
14567 do_scalar_fp16_v82_encode ();
14572 do_vfp_nsyn_opcode ("ffmad");
14574 do_vfp_nsyn_opcode ("ffnmad");
14579 do_vfp_nsyn_mul (enum neon_shape rs
)
14581 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14583 do_vfp_nsyn_opcode ("fmuls");
14585 /* ARMv8.2 fp16 instruction. */
14587 do_scalar_fp16_v82_encode ();
14590 do_vfp_nsyn_opcode ("fmuld");
14594 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14596 int is_neg
= (inst
.instruction
& 0x80) != 0;
14597 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14599 if (rs
== NS_FF
|| rs
== NS_HH
)
14602 do_vfp_nsyn_opcode ("fnegs");
14604 do_vfp_nsyn_opcode ("fabss");
14606 /* ARMv8.2 fp16 instruction. */
14608 do_scalar_fp16_v82_encode ();
14613 do_vfp_nsyn_opcode ("fnegd");
14615 do_vfp_nsyn_opcode ("fabsd");
14619 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14620 insns belong to Neon, and are handled elsewhere. */
14623 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14625 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14629 do_vfp_nsyn_opcode ("fldmdbs");
14631 do_vfp_nsyn_opcode ("fldmias");
14636 do_vfp_nsyn_opcode ("fstmdbs");
14638 do_vfp_nsyn_opcode ("fstmias");
14643 do_vfp_nsyn_sqrt (void)
14645 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14646 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14648 if (rs
== NS_FF
|| rs
== NS_HH
)
14650 do_vfp_nsyn_opcode ("fsqrts");
14652 /* ARMv8.2 fp16 instruction. */
14654 do_scalar_fp16_v82_encode ();
14657 do_vfp_nsyn_opcode ("fsqrtd");
14661 do_vfp_nsyn_div (void)
14663 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14664 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14665 N_F_ALL
| N_KEY
| N_VFP
);
14667 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14669 do_vfp_nsyn_opcode ("fdivs");
14671 /* ARMv8.2 fp16 instruction. */
14673 do_scalar_fp16_v82_encode ();
14676 do_vfp_nsyn_opcode ("fdivd");
14680 do_vfp_nsyn_nmul (void)
14682 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14683 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14684 N_F_ALL
| N_KEY
| N_VFP
);
14686 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14688 NEON_ENCODE (SINGLE
, inst
);
14689 do_vfp_sp_dyadic ();
14691 /* ARMv8.2 fp16 instruction. */
14693 do_scalar_fp16_v82_encode ();
14697 NEON_ENCODE (DOUBLE
, inst
);
14698 do_vfp_dp_rd_rn_rm ();
14700 do_vfp_cond_or_thumb ();
14705 do_vfp_nsyn_cmp (void)
14707 enum neon_shape rs
;
14708 if (inst
.operands
[1].isreg
)
14710 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14711 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14713 if (rs
== NS_FF
|| rs
== NS_HH
)
14715 NEON_ENCODE (SINGLE
, inst
);
14716 do_vfp_sp_monadic ();
14720 NEON_ENCODE (DOUBLE
, inst
);
14721 do_vfp_dp_rd_rm ();
14726 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14727 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14729 switch (inst
.instruction
& 0x0fffffff)
14732 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14735 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14741 if (rs
== NS_FI
|| rs
== NS_HI
)
14743 NEON_ENCODE (SINGLE
, inst
);
14744 do_vfp_sp_compare_z ();
14748 NEON_ENCODE (DOUBLE
, inst
);
14752 do_vfp_cond_or_thumb ();
14754 /* ARMv8.2 fp16 instruction. */
14755 if (rs
== NS_HI
|| rs
== NS_HH
)
14756 do_scalar_fp16_v82_encode ();
14760 nsyn_insert_sp (void)
14762 inst
.operands
[1] = inst
.operands
[0];
14763 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14764 inst
.operands
[0].reg
= REG_SP
;
14765 inst
.operands
[0].isreg
= 1;
14766 inst
.operands
[0].writeback
= 1;
14767 inst
.operands
[0].present
= 1;
14771 do_vfp_nsyn_push (void)
14775 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14776 _("register list must contain at least 1 and at most 16 "
14779 if (inst
.operands
[1].issingle
)
14780 do_vfp_nsyn_opcode ("fstmdbs");
14782 do_vfp_nsyn_opcode ("fstmdbd");
14786 do_vfp_nsyn_pop (void)
14790 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14791 _("register list must contain at least 1 and at most 16 "
14794 if (inst
.operands
[1].issingle
)
14795 do_vfp_nsyn_opcode ("fldmias");
14797 do_vfp_nsyn_opcode ("fldmiad");
14800 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14801 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14804 neon_dp_fixup (struct arm_it
* insn
)
14806 unsigned int i
= insn
->instruction
;
14811 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14822 insn
->instruction
= i
;
14825 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14829 neon_logbits (unsigned x
)
14831 return ffs (x
) - 4;
14834 #define LOW4(R) ((R) & 0xf)
14835 #define HI1(R) (((R) >> 4) & 1)
14837 /* Encode insns with bit pattern:
14839 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14840 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14842 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14843 different meaning for some instruction. */
14846 neon_three_same (int isquad
, int ubit
, int size
)
14848 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14849 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14850 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14851 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14852 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14853 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14854 inst
.instruction
|= (isquad
!= 0) << 6;
14855 inst
.instruction
|= (ubit
!= 0) << 24;
14857 inst
.instruction
|= neon_logbits (size
) << 20;
14859 neon_dp_fixup (&inst
);
14862 /* Encode instructions of the form:
14864 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14865 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14867 Don't write size if SIZE == -1. */
14870 neon_two_same (int qbit
, int ubit
, int size
)
14872 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14873 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14874 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14875 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14876 inst
.instruction
|= (qbit
!= 0) << 6;
14877 inst
.instruction
|= (ubit
!= 0) << 24;
14880 inst
.instruction
|= neon_logbits (size
) << 18;
14882 neon_dp_fixup (&inst
);
14885 /* Neon instruction encoders, in approximate order of appearance. */
14888 do_neon_dyadic_i_su (void)
14890 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14891 struct neon_type_el et
= neon_check_type (3, rs
,
14892 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14893 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14897 do_neon_dyadic_i64_su (void)
14899 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14900 struct neon_type_el et
= neon_check_type (3, rs
,
14901 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14902 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14906 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14909 unsigned size
= et
.size
>> 3;
14910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14913 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14914 inst
.instruction
|= (isquad
!= 0) << 6;
14915 inst
.instruction
|= immbits
<< 16;
14916 inst
.instruction
|= (size
>> 3) << 7;
14917 inst
.instruction
|= (size
& 0x7) << 19;
14919 inst
.instruction
|= (uval
!= 0) << 24;
14921 neon_dp_fixup (&inst
);
14925 do_neon_shl_imm (void)
14927 if (!inst
.operands
[2].isreg
)
14929 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14930 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14931 int imm
= inst
.operands
[2].imm
;
14933 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14934 _("immediate out of range for shift"));
14935 NEON_ENCODE (IMMED
, inst
);
14936 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14940 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14941 struct neon_type_el et
= neon_check_type (3, rs
,
14942 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14945 /* VSHL/VQSHL 3-register variants have syntax such as:
14947 whereas other 3-register operations encoded by neon_three_same have
14950 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14952 tmp
= inst
.operands
[2].reg
;
14953 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14954 inst
.operands
[1].reg
= tmp
;
14955 NEON_ENCODE (INTEGER
, inst
);
14956 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14961 do_neon_qshl_imm (void)
14963 if (!inst
.operands
[2].isreg
)
14965 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14966 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14967 int imm
= inst
.operands
[2].imm
;
14969 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14970 _("immediate out of range for shift"));
14971 NEON_ENCODE (IMMED
, inst
);
14972 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14976 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14977 struct neon_type_el et
= neon_check_type (3, rs
,
14978 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14981 /* See note in do_neon_shl_imm. */
14982 tmp
= inst
.operands
[2].reg
;
14983 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14984 inst
.operands
[1].reg
= tmp
;
14985 NEON_ENCODE (INTEGER
, inst
);
14986 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14991 do_neon_rshl (void)
14993 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14994 struct neon_type_el et
= neon_check_type (3, rs
,
14995 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14998 tmp
= inst
.operands
[2].reg
;
14999 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15000 inst
.operands
[1].reg
= tmp
;
15001 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15005 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15007 /* Handle .I8 pseudo-instructions. */
15010 /* Unfortunately, this will make everything apart from zero out-of-range.
15011 FIXME is this the intended semantics? There doesn't seem much point in
15012 accepting .I8 if so. */
15013 immediate
|= immediate
<< 8;
15019 if (immediate
== (immediate
& 0x000000ff))
15021 *immbits
= immediate
;
15024 else if (immediate
== (immediate
& 0x0000ff00))
15026 *immbits
= immediate
>> 8;
15029 else if (immediate
== (immediate
& 0x00ff0000))
15031 *immbits
= immediate
>> 16;
15034 else if (immediate
== (immediate
& 0xff000000))
15036 *immbits
= immediate
>> 24;
15039 if ((immediate
& 0xffff) != (immediate
>> 16))
15040 goto bad_immediate
;
15041 immediate
&= 0xffff;
15044 if (immediate
== (immediate
& 0x000000ff))
15046 *immbits
= immediate
;
15049 else if (immediate
== (immediate
& 0x0000ff00))
15051 *immbits
= immediate
>> 8;
15056 first_error (_("immediate value out of range"));
15061 do_neon_logic (void)
15063 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
15065 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15066 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15067 /* U bit and size field were set as part of the bitmask. */
15068 NEON_ENCODE (INTEGER
, inst
);
15069 neon_three_same (neon_quad (rs
), 0, -1);
15073 const int three_ops_form
= (inst
.operands
[2].present
15074 && !inst
.operands
[2].isreg
);
15075 const int immoperand
= (three_ops_form
? 2 : 1);
15076 enum neon_shape rs
= (three_ops_form
15077 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
15078 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
15079 struct neon_type_el et
= neon_check_type (2, rs
,
15080 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15081 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
15085 if (et
.type
== NT_invtype
)
15088 if (three_ops_form
)
15089 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15090 _("first and second operands shall be the same register"));
15092 NEON_ENCODE (IMMED
, inst
);
15094 immbits
= inst
.operands
[immoperand
].imm
;
15097 /* .i64 is a pseudo-op, so the immediate must be a repeating
15099 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
15100 inst
.operands
[immoperand
].reg
: 0))
15102 /* Set immbits to an invalid constant. */
15103 immbits
= 0xdeadbeef;
15110 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15114 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15118 /* Pseudo-instruction for VBIC. */
15119 neon_invert_size (&immbits
, 0, et
.size
);
15120 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15124 /* Pseudo-instruction for VORR. */
15125 neon_invert_size (&immbits
, 0, et
.size
);
15126 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15136 inst
.instruction
|= neon_quad (rs
) << 6;
15137 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15138 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15139 inst
.instruction
|= cmode
<< 8;
15140 neon_write_immbits (immbits
);
15142 neon_dp_fixup (&inst
);
15147 do_neon_bitfield (void)
15149 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15150 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15151 neon_three_same (neon_quad (rs
), 0, -1);
15155 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15158 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15159 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15161 if (et
.type
== NT_float
)
15163 NEON_ENCODE (FLOAT
, inst
);
15164 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15168 NEON_ENCODE (INTEGER
, inst
);
15169 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15174 do_neon_dyadic_if_su (void)
15176 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15180 do_neon_dyadic_if_su_d (void)
15182 /* This version only allow D registers, but that constraint is enforced during
15183 operand parsing so we don't need to do anything extra here. */
15184 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15188 do_neon_dyadic_if_i_d (void)
15190 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15191 affected if we specify unsigned args. */
15192 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15195 enum vfp_or_neon_is_neon_bits
15198 NEON_CHECK_ARCH
= 2,
15199 NEON_CHECK_ARCH8
= 4
15202 /* Call this function if an instruction which may have belonged to the VFP or
15203 Neon instruction sets, but turned out to be a Neon instruction (due to the
15204 operand types involved, etc.). We have to check and/or fix-up a couple of
15207 - Make sure the user hasn't attempted to make a Neon instruction
15209 - Alter the value in the condition code field if necessary.
15210 - Make sure that the arch supports Neon instructions.
15212 Which of these operations take place depends on bits from enum
15213 vfp_or_neon_is_neon_bits.
15215 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15216 current instruction's condition is COND_ALWAYS, the condition field is
15217 changed to inst.uncond_value. This is necessary because instructions shared
15218 between VFP and Neon may be conditional for the VFP variants only, and the
15219 unconditional Neon version must have, e.g., 0xF in the condition field. */
15222 vfp_or_neon_is_neon (unsigned check
)
15224 /* Conditions are always legal in Thumb mode (IT blocks). */
15225 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15227 if (inst
.cond
!= COND_ALWAYS
)
15229 first_error (_(BAD_COND
));
15232 if (inst
.uncond_value
!= -1)
15233 inst
.instruction
|= inst
.uncond_value
<< 28;
15236 if ((check
& NEON_CHECK_ARCH
)
15237 && !mark_feature_used (&fpu_neon_ext_v1
))
15239 first_error (_(BAD_FPU
));
15243 if ((check
& NEON_CHECK_ARCH8
)
15244 && !mark_feature_used (&fpu_neon_ext_armv8
))
15246 first_error (_(BAD_FPU
));
15254 do_neon_addsub_if_i (void)
15256 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15259 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15262 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15263 affected if we specify unsigned args. */
15264 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15267 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15269 V<op> A,B (A is operand 0, B is operand 2)
15274 so handle that case specially. */
15277 neon_exchange_operands (void)
15279 if (inst
.operands
[1].present
)
15281 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15283 /* Swap operands[1] and operands[2]. */
15284 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15285 inst
.operands
[1] = inst
.operands
[2];
15286 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15291 inst
.operands
[1] = inst
.operands
[2];
15292 inst
.operands
[2] = inst
.operands
[0];
15297 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15299 if (inst
.operands
[2].isreg
)
15302 neon_exchange_operands ();
15303 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15307 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15308 struct neon_type_el et
= neon_check_type (2, rs
,
15309 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15311 NEON_ENCODE (IMMED
, inst
);
15312 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15313 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15314 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15315 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15316 inst
.instruction
|= neon_quad (rs
) << 6;
15317 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15318 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15320 neon_dp_fixup (&inst
);
15327 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15331 do_neon_cmp_inv (void)
15333 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15339 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15342 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15343 scalars, which are encoded in 5 bits, M : Rm.
15344 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15345 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15348 Dot Product instructions are similar to multiply instructions except elsize
15349 should always be 32.
15351 This function translates SCALAR, which is GAS's internal encoding of indexed
15352 scalar register, to raw encoding. There is also register and index range
15353 check based on ELSIZE. */
15356 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15358 unsigned regno
= NEON_SCALAR_REG (scalar
);
15359 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15364 if (regno
> 7 || elno
> 3)
15366 return regno
| (elno
<< 3);
15369 if (regno
> 15 || elno
> 1)
15371 return regno
| (elno
<< 4);
15375 first_error (_("scalar out of range for multiply instruction"));
15381 /* Encode multiply / multiply-accumulate scalar instructions. */
15384 neon_mul_mac (struct neon_type_el et
, int ubit
)
15388 /* Give a more helpful error message if we have an invalid type. */
15389 if (et
.type
== NT_invtype
)
15392 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15395 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15396 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15397 inst
.instruction
|= LOW4 (scalar
);
15398 inst
.instruction
|= HI1 (scalar
) << 5;
15399 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15400 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15401 inst
.instruction
|= (ubit
!= 0) << 24;
15403 neon_dp_fixup (&inst
);
15407 do_neon_mac_maybe_scalar (void)
15409 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15412 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15415 if (inst
.operands
[2].isscalar
)
15417 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15418 struct neon_type_el et
= neon_check_type (3, rs
,
15419 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15420 NEON_ENCODE (SCALAR
, inst
);
15421 neon_mul_mac (et
, neon_quad (rs
));
15425 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15426 affected if we specify unsigned args. */
15427 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15432 do_neon_fmac (void)
15434 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15437 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15440 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15446 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15447 struct neon_type_el et
= neon_check_type (3, rs
,
15448 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15449 neon_three_same (neon_quad (rs
), 0, et
.size
);
15452 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15453 same types as the MAC equivalents. The polynomial type for this instruction
15454 is encoded the same as the integer type. */
15459 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15462 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15465 if (inst
.operands
[2].isscalar
)
15466 do_neon_mac_maybe_scalar ();
15468 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15472 do_neon_qdmulh (void)
15474 if (inst
.operands
[2].isscalar
)
15476 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15477 struct neon_type_el et
= neon_check_type (3, rs
,
15478 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15479 NEON_ENCODE (SCALAR
, inst
);
15480 neon_mul_mac (et
, neon_quad (rs
));
15484 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15485 struct neon_type_el et
= neon_check_type (3, rs
,
15486 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15487 NEON_ENCODE (INTEGER
, inst
);
15488 /* The U bit (rounding) comes from bit mask. */
15489 neon_three_same (neon_quad (rs
), 0, et
.size
);
15494 do_neon_qrdmlah (void)
15496 /* Check we're on the correct architecture. */
15497 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15499 _("instruction form not available on this architecture.");
15500 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15502 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15503 record_feature_use (&fpu_neon_ext_v8_1
);
15506 if (inst
.operands
[2].isscalar
)
15508 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15509 struct neon_type_el et
= neon_check_type (3, rs
,
15510 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15511 NEON_ENCODE (SCALAR
, inst
);
15512 neon_mul_mac (et
, neon_quad (rs
));
15516 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15517 struct neon_type_el et
= neon_check_type (3, rs
,
15518 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15519 NEON_ENCODE (INTEGER
, inst
);
15520 /* The U bit (rounding) comes from bit mask. */
15521 neon_three_same (neon_quad (rs
), 0, et
.size
);
15526 do_neon_fcmp_absolute (void)
15528 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15529 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15530 N_F_16_32
| N_KEY
);
15531 /* Size field comes from bit mask. */
15532 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15536 do_neon_fcmp_absolute_inv (void)
15538 neon_exchange_operands ();
15539 do_neon_fcmp_absolute ();
15543 do_neon_step (void)
15545 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15546 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15547 N_F_16_32
| N_KEY
);
15548 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15552 do_neon_abs_neg (void)
15554 enum neon_shape rs
;
15555 struct neon_type_el et
;
15557 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15560 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15563 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15564 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15566 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15567 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15568 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15569 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15570 inst
.instruction
|= neon_quad (rs
) << 6;
15571 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15572 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15574 neon_dp_fixup (&inst
);
15580 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15581 struct neon_type_el et
= neon_check_type (2, rs
,
15582 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15583 int imm
= inst
.operands
[2].imm
;
15584 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15585 _("immediate out of range for insert"));
15586 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15592 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15593 struct neon_type_el et
= neon_check_type (2, rs
,
15594 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15595 int imm
= inst
.operands
[2].imm
;
15596 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15597 _("immediate out of range for insert"));
15598 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15602 do_neon_qshlu_imm (void)
15604 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15605 struct neon_type_el et
= neon_check_type (2, rs
,
15606 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15607 int imm
= inst
.operands
[2].imm
;
15608 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15609 _("immediate out of range for shift"));
15610 /* Only encodes the 'U present' variant of the instruction.
15611 In this case, signed types have OP (bit 8) set to 0.
15612 Unsigned types have OP set to 1. */
15613 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15614 /* The rest of the bits are the same as other immediate shifts. */
15615 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15619 do_neon_qmovn (void)
15621 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15622 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15623 /* Saturating move where operands can be signed or unsigned, and the
15624 destination has the same signedness. */
15625 NEON_ENCODE (INTEGER
, inst
);
15626 if (et
.type
== NT_unsigned
)
15627 inst
.instruction
|= 0xc0;
15629 inst
.instruction
|= 0x80;
15630 neon_two_same (0, 1, et
.size
/ 2);
15634 do_neon_qmovun (void)
15636 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15637 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15638 /* Saturating move with unsigned results. Operands must be signed. */
15639 NEON_ENCODE (INTEGER
, inst
);
15640 neon_two_same (0, 1, et
.size
/ 2);
15644 do_neon_rshift_sat_narrow (void)
15646 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15647 or unsigned. If operands are unsigned, results must also be unsigned. */
15648 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15649 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15650 int imm
= inst
.operands
[2].imm
;
15651 /* This gets the bounds check, size encoding and immediate bits calculation
15655 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15656 VQMOVN.I<size> <Dd>, <Qm>. */
15659 inst
.operands
[2].present
= 0;
15660 inst
.instruction
= N_MNEM_vqmovn
;
15665 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15666 _("immediate out of range"));
15667 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15671 do_neon_rshift_sat_narrow_u (void)
15673 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15674 or unsigned. If operands are unsigned, results must also be unsigned. */
15675 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15676 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15677 int imm
= inst
.operands
[2].imm
;
15678 /* This gets the bounds check, size encoding and immediate bits calculation
15682 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15683 VQMOVUN.I<size> <Dd>, <Qm>. */
15686 inst
.operands
[2].present
= 0;
15687 inst
.instruction
= N_MNEM_vqmovun
;
15692 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15693 _("immediate out of range"));
15694 /* FIXME: The manual is kind of unclear about what value U should have in
15695 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15697 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15701 do_neon_movn (void)
15703 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15704 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15705 NEON_ENCODE (INTEGER
, inst
);
15706 neon_two_same (0, 1, et
.size
/ 2);
15710 do_neon_rshift_narrow (void)
15712 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15713 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15714 int imm
= inst
.operands
[2].imm
;
15715 /* This gets the bounds check, size encoding and immediate bits calculation
15719 /* If immediate is zero then we are a pseudo-instruction for
15720 VMOVN.I<size> <Dd>, <Qm> */
15723 inst
.operands
[2].present
= 0;
15724 inst
.instruction
= N_MNEM_vmovn
;
15729 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15730 _("immediate out of range for narrowing operation"));
15731 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15735 do_neon_shll (void)
15737 /* FIXME: Type checking when lengthening. */
15738 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15739 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15740 unsigned imm
= inst
.operands
[2].imm
;
15742 if (imm
== et
.size
)
15744 /* Maximum shift variant. */
15745 NEON_ENCODE (INTEGER
, inst
);
15746 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15750 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15752 neon_dp_fixup (&inst
);
15756 /* A more-specific type check for non-max versions. */
15757 et
= neon_check_type (2, NS_QDI
,
15758 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15759 NEON_ENCODE (IMMED
, inst
);
15760 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15764 /* Check the various types for the VCVT instruction, and return which version
15765 the current instruction is. */
15767 #define CVT_FLAVOUR_VAR \
15768 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15769 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15770 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15771 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15772 /* Half-precision conversions. */ \
15773 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15774 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15775 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15776 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15777 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15778 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15779 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15780 Compared with single/double precision variants, only the co-processor \
15781 field is different, so the encoding flow is reused here. */ \
15782 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15783 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15784 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15785 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15786 /* VFP instructions. */ \
15787 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15788 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15789 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15790 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15791 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15792 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15793 /* VFP instructions with bitshift. */ \
15794 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15795 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15796 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15797 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15798 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15799 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15800 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15801 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15803 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15804 neon_cvt_flavour_##C,
15806 /* The different types of conversions we can do. */
15807 enum neon_cvt_flavour
15810 neon_cvt_flavour_invalid
,
15811 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15816 static enum neon_cvt_flavour
15817 get_neon_cvt_flavour (enum neon_shape rs
)
15819 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15820 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15821 if (et.type != NT_invtype) \
15823 inst.error = NULL; \
15824 return (neon_cvt_flavour_##C); \
15827 struct neon_type_el et
;
15828 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15829 || rs
== NS_FF
) ? N_VFP
: 0;
15830 /* The instruction versions which take an immediate take one register
15831 argument, which is extended to the width of the full register. Thus the
15832 "source" and "destination" registers must have the same width. Hack that
15833 here by making the size equal to the key (wider, in this case) operand. */
15834 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15838 return neon_cvt_flavour_invalid
;
15853 /* Neon-syntax VFP conversions. */
15856 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15858 const char *opname
= 0;
15860 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15861 || rs
== NS_FHI
|| rs
== NS_HFI
)
15863 /* Conversions with immediate bitshift. */
15864 const char *enc
[] =
15866 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15872 if (flavour
< (int) ARRAY_SIZE (enc
))
15874 opname
= enc
[flavour
];
15875 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15876 _("operands 0 and 1 must be the same register"));
15877 inst
.operands
[1] = inst
.operands
[2];
15878 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15883 /* Conversions without bitshift. */
15884 const char *enc
[] =
15886 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15892 if (flavour
< (int) ARRAY_SIZE (enc
))
15893 opname
= enc
[flavour
];
15897 do_vfp_nsyn_opcode (opname
);
15899 /* ARMv8.2 fp16 VCVT instruction. */
15900 if (flavour
== neon_cvt_flavour_s32_f16
15901 || flavour
== neon_cvt_flavour_u32_f16
15902 || flavour
== neon_cvt_flavour_f16_u32
15903 || flavour
== neon_cvt_flavour_f16_s32
)
15904 do_scalar_fp16_v82_encode ();
15908 do_vfp_nsyn_cvtz (void)
15910 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15911 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15912 const char *enc
[] =
15914 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15920 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15921 do_vfp_nsyn_opcode (enc
[flavour
]);
15925 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15926 enum neon_cvt_mode mode
)
15931 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15932 D register operands. */
15933 if (flavour
== neon_cvt_flavour_s32_f64
15934 || flavour
== neon_cvt_flavour_u32_f64
)
15935 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15938 if (flavour
== neon_cvt_flavour_s32_f16
15939 || flavour
== neon_cvt_flavour_u32_f16
)
15940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15943 set_it_insn_type (OUTSIDE_IT_INSN
);
15947 case neon_cvt_flavour_s32_f64
:
15951 case neon_cvt_flavour_s32_f32
:
15955 case neon_cvt_flavour_s32_f16
:
15959 case neon_cvt_flavour_u32_f64
:
15963 case neon_cvt_flavour_u32_f32
:
15967 case neon_cvt_flavour_u32_f16
:
15972 first_error (_("invalid instruction shape"));
15978 case neon_cvt_mode_a
: rm
= 0; break;
15979 case neon_cvt_mode_n
: rm
= 1; break;
15980 case neon_cvt_mode_p
: rm
= 2; break;
15981 case neon_cvt_mode_m
: rm
= 3; break;
15982 default: first_error (_("invalid rounding mode")); return;
15985 NEON_ENCODE (FPV8
, inst
);
15986 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15987 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15988 inst
.instruction
|= sz
<< 8;
15990 /* ARMv8.2 fp16 VCVT instruction. */
15991 if (flavour
== neon_cvt_flavour_s32_f16
15992 ||flavour
== neon_cvt_flavour_u32_f16
)
15993 do_scalar_fp16_v82_encode ();
15994 inst
.instruction
|= op
<< 7;
15995 inst
.instruction
|= rm
<< 16;
15996 inst
.instruction
|= 0xf0000000;
15997 inst
.is_neon
= TRUE
;
16001 do_neon_cvt_1 (enum neon_cvt_mode mode
)
16003 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
16004 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
16005 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
16007 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
16009 if (flavour
== neon_cvt_flavour_invalid
)
16012 /* PR11109: Handle round-to-zero for VCVT conversions. */
16013 if (mode
== neon_cvt_mode_z
16014 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
16015 && (flavour
== neon_cvt_flavour_s16_f16
16016 || flavour
== neon_cvt_flavour_u16_f16
16017 || flavour
== neon_cvt_flavour_s32_f32
16018 || flavour
== neon_cvt_flavour_u32_f32
16019 || flavour
== neon_cvt_flavour_s32_f64
16020 || flavour
== neon_cvt_flavour_u32_f64
)
16021 && (rs
== NS_FD
|| rs
== NS_FF
))
16023 do_vfp_nsyn_cvtz ();
16027 /* ARMv8.2 fp16 VCVT conversions. */
16028 if (mode
== neon_cvt_mode_z
16029 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
16030 && (flavour
== neon_cvt_flavour_s32_f16
16031 || flavour
== neon_cvt_flavour_u32_f16
)
16034 do_vfp_nsyn_cvtz ();
16035 do_scalar_fp16_v82_encode ();
16039 /* VFP rather than Neon conversions. */
16040 if (flavour
>= neon_cvt_flavour_first_fp
)
16042 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16043 do_vfp_nsyn_cvt (rs
, flavour
);
16045 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16056 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
16057 0x0000100, 0x1000100, 0x0, 0x1000000};
16059 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16062 /* Fixed-point conversion with #0 immediate is encoded as an
16063 integer conversion. */
16064 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
16066 NEON_ENCODE (IMMED
, inst
);
16067 if (flavour
!= neon_cvt_flavour_invalid
)
16068 inst
.instruction
|= enctab
[flavour
];
16069 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16073 inst
.instruction
|= neon_quad (rs
) << 6;
16074 inst
.instruction
|= 1 << 21;
16075 if (flavour
< neon_cvt_flavour_s16_f16
)
16077 inst
.instruction
|= 1 << 21;
16078 immbits
= 32 - inst
.operands
[2].imm
;
16079 inst
.instruction
|= immbits
<< 16;
16083 inst
.instruction
|= 3 << 20;
16084 immbits
= 16 - inst
.operands
[2].imm
;
16085 inst
.instruction
|= immbits
<< 16;
16086 inst
.instruction
&= ~(1 << 9);
16089 neon_dp_fixup (&inst
);
16095 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
16097 NEON_ENCODE (FLOAT
, inst
);
16098 set_it_insn_type (OUTSIDE_IT_INSN
);
16100 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16103 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16104 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16105 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16106 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16107 inst
.instruction
|= neon_quad (rs
) << 6;
16108 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
16109 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
16110 inst
.instruction
|= mode
<< 8;
16111 if (flavour
== neon_cvt_flavour_u16_f16
16112 || flavour
== neon_cvt_flavour_s16_f16
)
16113 /* Mask off the original size bits and reencode them. */
16114 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
16117 inst
.instruction
|= 0xfc000000;
16119 inst
.instruction
|= 0xf0000000;
16125 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
16126 0x100, 0x180, 0x0, 0x080};
16128 NEON_ENCODE (INTEGER
, inst
);
16130 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16133 if (flavour
!= neon_cvt_flavour_invalid
)
16134 inst
.instruction
|= enctab
[flavour
];
16136 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16137 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16138 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16139 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16140 inst
.instruction
|= neon_quad (rs
) << 6;
16141 if (flavour
>= neon_cvt_flavour_s16_f16
16142 && flavour
<= neon_cvt_flavour_f16_u16
)
16143 /* Half precision. */
16144 inst
.instruction
|= 1 << 18;
16146 inst
.instruction
|= 2 << 18;
16148 neon_dp_fixup (&inst
);
16153 /* Half-precision conversions for Advanced SIMD -- neon. */
16156 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16160 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
16162 as_bad (_("operand size must match register width"));
16167 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
16169 as_bad (_("operand size must match register width"));
16174 inst
.instruction
= 0x3b60600;
16176 inst
.instruction
= 0x3b60700;
16178 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16179 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16180 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16181 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16182 neon_dp_fixup (&inst
);
16186 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
16187 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16188 do_vfp_nsyn_cvt (rs
, flavour
);
16190 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16195 do_neon_cvtr (void)
16197 do_neon_cvt_1 (neon_cvt_mode_x
);
16203 do_neon_cvt_1 (neon_cvt_mode_z
);
16207 do_neon_cvta (void)
16209 do_neon_cvt_1 (neon_cvt_mode_a
);
16213 do_neon_cvtn (void)
16215 do_neon_cvt_1 (neon_cvt_mode_n
);
16219 do_neon_cvtp (void)
16221 do_neon_cvt_1 (neon_cvt_mode_p
);
16225 do_neon_cvtm (void)
16227 do_neon_cvt_1 (neon_cvt_mode_m
);
16231 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16234 mark_feature_used (&fpu_vfp_ext_armv8
);
16236 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16237 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16238 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16239 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16240 inst
.instruction
|= to
? 0x10000 : 0;
16241 inst
.instruction
|= t
? 0x80 : 0;
16242 inst
.instruction
|= is_double
? 0x100 : 0;
16243 do_vfp_cond_or_thumb ();
16247 do_neon_cvttb_1 (bfd_boolean t
)
16249 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16250 NS_DF
, NS_DH
, NS_NULL
);
16254 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16257 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16259 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16262 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16264 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16266 /* The VCVTB and VCVTT instructions with D-register operands
16267 don't work for SP only targets. */
16268 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16272 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16274 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16276 /* The VCVTB and VCVTT instructions with D-register operands
16277 don't work for SP only targets. */
16278 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16282 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16289 do_neon_cvtb (void)
16291 do_neon_cvttb_1 (FALSE
);
16296 do_neon_cvtt (void)
16298 do_neon_cvttb_1 (TRUE
);
16302 neon_move_immediate (void)
16304 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16305 struct neon_type_el et
= neon_check_type (2, rs
,
16306 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16307 unsigned immlo
, immhi
= 0, immbits
;
16308 int op
, cmode
, float_p
;
16310 constraint (et
.type
== NT_invtype
,
16311 _("operand size must be specified for immediate VMOV"));
16313 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16314 op
= (inst
.instruction
& (1 << 5)) != 0;
16316 immlo
= inst
.operands
[1].imm
;
16317 if (inst
.operands
[1].regisimm
)
16318 immhi
= inst
.operands
[1].reg
;
16320 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16321 _("immediate has bits set outside the operand size"));
16323 float_p
= inst
.operands
[1].immisfloat
;
16325 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16326 et
.size
, et
.type
)) == FAIL
)
16328 /* Invert relevant bits only. */
16329 neon_invert_size (&immlo
, &immhi
, et
.size
);
16330 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16331 with one or the other; those cases are caught by
16332 neon_cmode_for_move_imm. */
16334 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16335 &op
, et
.size
, et
.type
)) == FAIL
)
16337 first_error (_("immediate out of range"));
16342 inst
.instruction
&= ~(1 << 5);
16343 inst
.instruction
|= op
<< 5;
16345 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16346 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16347 inst
.instruction
|= neon_quad (rs
) << 6;
16348 inst
.instruction
|= cmode
<< 8;
16350 neon_write_immbits (immbits
);
16356 if (inst
.operands
[1].isreg
)
16358 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16360 NEON_ENCODE (INTEGER
, inst
);
16361 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16362 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16363 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16364 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16365 inst
.instruction
|= neon_quad (rs
) << 6;
16369 NEON_ENCODE (IMMED
, inst
);
16370 neon_move_immediate ();
16373 neon_dp_fixup (&inst
);
16376 /* Encode instructions of form:
16378 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16379 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16382 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16384 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16385 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16386 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16387 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16388 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16389 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16390 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16391 inst
.instruction
|= neon_logbits (size
) << 20;
16393 neon_dp_fixup (&inst
);
16397 do_neon_dyadic_long (void)
16399 /* FIXME: Type checking for lengthening op. */
16400 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16401 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16402 neon_mixed_length (et
, et
.size
);
16406 do_neon_abal (void)
16408 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16409 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16410 neon_mixed_length (et
, et
.size
);
16414 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16416 if (inst
.operands
[2].isscalar
)
16418 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16419 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16420 NEON_ENCODE (SCALAR
, inst
);
16421 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16425 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16426 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16427 NEON_ENCODE (INTEGER
, inst
);
16428 neon_mixed_length (et
, et
.size
);
16433 do_neon_mac_maybe_scalar_long (void)
16435 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16438 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16439 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16442 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16444 unsigned regno
= NEON_SCALAR_REG (scalar
);
16445 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16449 if (regno
> 7 || elno
> 3)
16452 return ((regno
& 0x7)
16453 | ((elno
& 0x1) << 3)
16454 | (((elno
>> 1) & 0x1) << 5));
16458 if (regno
> 15 || elno
> 1)
16461 return (((regno
& 0x1) << 5)
16462 | ((regno
>> 1) & 0x7)
16463 | ((elno
& 0x1) << 3));
16467 first_error (_("scalar out of range for multiply instruction"));
16472 do_neon_fmac_maybe_scalar_long (int subtype
)
16474 enum neon_shape rs
;
16476 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16477 field (bits[21:20]) has different meaning. For scalar index variant, it's
16478 used to differentiate add and subtract, otherwise it's with fixed value
16482 if (inst
.cond
!= COND_ALWAYS
)
16483 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16484 "behaviour is UNPREDICTABLE"));
16486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16489 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16492 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16493 be a scalar index register. */
16494 if (inst
.operands
[2].isscalar
)
16496 high8
= 0xfe000000;
16499 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16503 high8
= 0xfc000000;
16506 inst
.instruction
|= (0x1 << 23);
16507 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16510 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16512 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16513 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16514 so we simply pass -1 as size. */
16515 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16516 neon_three_same (quad_p
, 0, size
);
16518 /* Undo neon_dp_fixup. Redo the high eight bits. */
16519 inst
.instruction
&= 0x00ffffff;
16520 inst
.instruction
|= high8
;
16522 #define LOW1(R) ((R) & 0x1)
16523 #define HI4(R) (((R) >> 1) & 0xf)
16524 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16525 whether the instruction is in Q form and whether Vm is a scalar indexed
16527 if (inst
.operands
[2].isscalar
)
16530 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16531 inst
.instruction
&= 0xffffffd0;
16532 inst
.instruction
|= rm
;
16536 /* Redo Rn as well. */
16537 inst
.instruction
&= 0xfff0ff7f;
16538 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16539 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16544 /* Redo Rn and Rm. */
16545 inst
.instruction
&= 0xfff0ff50;
16546 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16547 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16548 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16549 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16554 do_neon_vfmal (void)
16556 return do_neon_fmac_maybe_scalar_long (0);
16560 do_neon_vfmsl (void)
16562 return do_neon_fmac_maybe_scalar_long (1);
16566 do_neon_dyadic_wide (void)
16568 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16569 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16570 neon_mixed_length (et
, et
.size
);
16574 do_neon_dyadic_narrow (void)
16576 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16577 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16578 /* Operand sign is unimportant, and the U bit is part of the opcode,
16579 so force the operand type to integer. */
16580 et
.type
= NT_integer
;
16581 neon_mixed_length (et
, et
.size
/ 2);
16585 do_neon_mul_sat_scalar_long (void)
16587 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16591 do_neon_vmull (void)
16593 if (inst
.operands
[2].isscalar
)
16594 do_neon_mac_maybe_scalar_long ();
16597 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16598 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16600 if (et
.type
== NT_poly
)
16601 NEON_ENCODE (POLY
, inst
);
16603 NEON_ENCODE (INTEGER
, inst
);
16605 /* For polynomial encoding the U bit must be zero, and the size must
16606 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16607 obviously, as 0b10). */
16610 /* Check we're on the correct architecture. */
16611 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16613 _("Instruction form not available on this architecture.");
16618 neon_mixed_length (et
, et
.size
);
16625 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16626 struct neon_type_el et
= neon_check_type (3, rs
,
16627 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16628 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16630 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16631 _("shift out of range"));
16632 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16633 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16634 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16635 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16636 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16637 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16638 inst
.instruction
|= neon_quad (rs
) << 6;
16639 inst
.instruction
|= imm
<< 8;
16641 neon_dp_fixup (&inst
);
16647 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16648 struct neon_type_el et
= neon_check_type (2, rs
,
16649 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16650 unsigned op
= (inst
.instruction
>> 7) & 3;
16651 /* N (width of reversed regions) is encoded as part of the bitmask. We
16652 extract it here to check the elements to be reversed are smaller.
16653 Otherwise we'd get a reserved instruction. */
16654 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16655 gas_assert (elsize
!= 0);
16656 constraint (et
.size
>= elsize
,
16657 _("elements must be smaller than reversal region"));
16658 neon_two_same (neon_quad (rs
), 1, et
.size
);
16664 if (inst
.operands
[1].isscalar
)
16666 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16667 struct neon_type_el et
= neon_check_type (2, rs
,
16668 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16669 unsigned sizebits
= et
.size
>> 3;
16670 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16671 int logsize
= neon_logbits (et
.size
);
16672 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16674 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16677 NEON_ENCODE (SCALAR
, inst
);
16678 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16679 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16680 inst
.instruction
|= LOW4 (dm
);
16681 inst
.instruction
|= HI1 (dm
) << 5;
16682 inst
.instruction
|= neon_quad (rs
) << 6;
16683 inst
.instruction
|= x
<< 17;
16684 inst
.instruction
|= sizebits
<< 16;
16686 neon_dp_fixup (&inst
);
16690 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16691 struct neon_type_el et
= neon_check_type (2, rs
,
16692 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16693 /* Duplicate ARM register to lanes of vector. */
16694 NEON_ENCODE (ARMREG
, inst
);
16697 case 8: inst
.instruction
|= 0x400000; break;
16698 case 16: inst
.instruction
|= 0x000020; break;
16699 case 32: inst
.instruction
|= 0x000000; break;
16702 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16705 inst
.instruction
|= neon_quad (rs
) << 21;
16706 /* The encoding for this instruction is identical for the ARM and Thumb
16707 variants, except for the condition field. */
16708 do_vfp_cond_or_thumb ();
16712 /* VMOV has particularly many variations. It can be one of:
16713 0. VMOV<c><q> <Qd>, <Qm>
16714 1. VMOV<c><q> <Dd>, <Dm>
16715 (Register operations, which are VORR with Rm = Rn.)
16716 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16717 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16719 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16720 (ARM register to scalar.)
16721 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16722 (Two ARM registers to vector.)
16723 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16724 (Scalar to ARM register.)
16725 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16726 (Vector to two ARM registers.)
16727 8. VMOV.F32 <Sd>, <Sm>
16728 9. VMOV.F64 <Dd>, <Dm>
16729 (VFP register moves.)
16730 10. VMOV.F32 <Sd>, #imm
16731 11. VMOV.F64 <Dd>, #imm
16732 (VFP float immediate load.)
16733 12. VMOV <Rd>, <Sm>
16734 (VFP single to ARM reg.)
16735 13. VMOV <Sd>, <Rm>
16736 (ARM reg to VFP single.)
16737 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16738 (Two ARM regs to two VFP singles.)
16739 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16740 (Two VFP singles to two ARM regs.)
16742 These cases can be disambiguated using neon_select_shape, except cases 1/9
16743 and 3/11 which depend on the operand type too.
16745 All the encoded bits are hardcoded by this function.
16747 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16748 Cases 5, 7 may be used with VFPv2 and above.
16750 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16751 can specify a type where it doesn't make sense to, and is ignored). */
16756 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16757 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16758 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16759 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16760 struct neon_type_el et
;
16761 const char *ldconst
= 0;
16765 case NS_DD
: /* case 1/9. */
16766 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16767 /* It is not an error here if no type is given. */
16769 if (et
.type
== NT_float
&& et
.size
== 64)
16771 do_vfp_nsyn_opcode ("fcpyd");
16774 /* fall through. */
16776 case NS_QQ
: /* case 0/1. */
16778 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16780 /* The architecture manual I have doesn't explicitly state which
16781 value the U bit should have for register->register moves, but
16782 the equivalent VORR instruction has U = 0, so do that. */
16783 inst
.instruction
= 0x0200110;
16784 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16785 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16786 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16787 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16790 inst
.instruction
|= neon_quad (rs
) << 6;
16792 neon_dp_fixup (&inst
);
16796 case NS_DI
: /* case 3/11. */
16797 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16799 if (et
.type
== NT_float
&& et
.size
== 64)
16801 /* case 11 (fconstd). */
16802 ldconst
= "fconstd";
16803 goto encode_fconstd
;
16805 /* fall through. */
16807 case NS_QI
: /* case 2/3. */
16808 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16810 inst
.instruction
= 0x0800010;
16811 neon_move_immediate ();
16812 neon_dp_fixup (&inst
);
16815 case NS_SR
: /* case 4. */
16817 unsigned bcdebits
= 0;
16819 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16820 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16822 /* .<size> is optional here, defaulting to .32. */
16823 if (inst
.vectype
.elems
== 0
16824 && inst
.operands
[0].vectype
.type
== NT_invtype
16825 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16827 inst
.vectype
.el
[0].type
= NT_untyped
;
16828 inst
.vectype
.el
[0].size
= 32;
16829 inst
.vectype
.elems
= 1;
16832 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16833 logsize
= neon_logbits (et
.size
);
16835 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16837 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16838 && et
.size
!= 32, _(BAD_FPU
));
16839 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16840 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16844 case 8: bcdebits
= 0x8; break;
16845 case 16: bcdebits
= 0x1; break;
16846 case 32: bcdebits
= 0x0; break;
16850 bcdebits
|= x
<< logsize
;
16852 inst
.instruction
= 0xe000b10;
16853 do_vfp_cond_or_thumb ();
16854 inst
.instruction
|= LOW4 (dn
) << 16;
16855 inst
.instruction
|= HI1 (dn
) << 7;
16856 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16857 inst
.instruction
|= (bcdebits
& 3) << 5;
16858 inst
.instruction
|= (bcdebits
>> 2) << 21;
16862 case NS_DRR
: /* case 5 (fmdrr). */
16863 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16866 inst
.instruction
= 0xc400b10;
16867 do_vfp_cond_or_thumb ();
16868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16870 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16871 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16874 case NS_RS
: /* case 6. */
16877 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16878 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16879 unsigned abcdebits
= 0;
16881 /* .<dt> is optional here, defaulting to .32. */
16882 if (inst
.vectype
.elems
== 0
16883 && inst
.operands
[0].vectype
.type
== NT_invtype
16884 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16886 inst
.vectype
.el
[0].type
= NT_untyped
;
16887 inst
.vectype
.el
[0].size
= 32;
16888 inst
.vectype
.elems
= 1;
16891 et
= neon_check_type (2, NS_NULL
,
16892 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16893 logsize
= neon_logbits (et
.size
);
16895 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16898 && et
.size
!= 32, _(BAD_FPU
));
16899 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16900 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16904 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16905 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16906 case 32: abcdebits
= 0x00; break;
16910 abcdebits
|= x
<< logsize
;
16911 inst
.instruction
= 0xe100b10;
16912 do_vfp_cond_or_thumb ();
16913 inst
.instruction
|= LOW4 (dn
) << 16;
16914 inst
.instruction
|= HI1 (dn
) << 7;
16915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16916 inst
.instruction
|= (abcdebits
& 3) << 5;
16917 inst
.instruction
|= (abcdebits
>> 2) << 21;
16921 case NS_RRD
: /* case 7 (fmrrd). */
16922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16925 inst
.instruction
= 0xc500b10;
16926 do_vfp_cond_or_thumb ();
16927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16929 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16930 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16933 case NS_FF
: /* case 8 (fcpys). */
16934 do_vfp_nsyn_opcode ("fcpys");
16938 case NS_FI
: /* case 10 (fconsts). */
16939 ldconst
= "fconsts";
16941 if (!inst
.operands
[1].immisfloat
)
16944 /* Immediate has to fit in 8 bits so float is enough. */
16945 float imm
= (float) inst
.operands
[1].imm
;
16946 memcpy (&new_imm
, &imm
, sizeof (float));
16947 /* But the assembly may have been written to provide an integer
16948 bit pattern that equates to a float, so check that the
16949 conversion has worked. */
16950 if (is_quarter_float (new_imm
))
16952 if (is_quarter_float (inst
.operands
[1].imm
))
16953 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16955 inst
.operands
[1].imm
= new_imm
;
16956 inst
.operands
[1].immisfloat
= 1;
16960 if (is_quarter_float (inst
.operands
[1].imm
))
16962 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16963 do_vfp_nsyn_opcode (ldconst
);
16965 /* ARMv8.2 fp16 vmov.f16 instruction. */
16967 do_scalar_fp16_v82_encode ();
16970 first_error (_("immediate out of range"));
16974 case NS_RF
: /* case 12 (fmrs). */
16975 do_vfp_nsyn_opcode ("fmrs");
16976 /* ARMv8.2 fp16 vmov.f16 instruction. */
16978 do_scalar_fp16_v82_encode ();
16982 case NS_FR
: /* case 13 (fmsr). */
16983 do_vfp_nsyn_opcode ("fmsr");
16984 /* ARMv8.2 fp16 vmov.f16 instruction. */
16986 do_scalar_fp16_v82_encode ();
16989 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16990 (one of which is a list), but we have parsed four. Do some fiddling to
16991 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16993 case NS_RRFF
: /* case 14 (fmrrs). */
16994 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16995 _("VFP registers must be adjacent"));
16996 inst
.operands
[2].imm
= 2;
16997 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16998 do_vfp_nsyn_opcode ("fmrrs");
17001 case NS_FFRR
: /* case 15 (fmsrr). */
17002 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
17003 _("VFP registers must be adjacent"));
17004 inst
.operands
[1] = inst
.operands
[2];
17005 inst
.operands
[2] = inst
.operands
[3];
17006 inst
.operands
[0].imm
= 2;
17007 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
17008 do_vfp_nsyn_opcode ("fmsrr");
17012 /* neon_select_shape has determined that the instruction
17013 shape is wrong and has already set the error message. */
17022 do_neon_rshift_round_imm (void)
17024 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17025 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17026 int imm
= inst
.operands
[2].imm
;
17028 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
17031 inst
.operands
[2].present
= 0;
17036 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17037 _("immediate out of range for shift"));
17038 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
17043 do_neon_movhf (void)
17045 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
17046 constraint (rs
!= NS_HH
, _("invalid suffix"));
17048 if (inst
.cond
!= COND_ALWAYS
)
17052 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
17053 " the behaviour is UNPREDICTABLE"));
17057 inst
.error
= BAD_COND
;
17062 do_vfp_sp_monadic ();
17065 inst
.instruction
|= 0xf0000000;
17069 do_neon_movl (void)
17071 struct neon_type_el et
= neon_check_type (2, NS_QD
,
17072 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17073 unsigned sizebits
= et
.size
>> 3;
17074 inst
.instruction
|= sizebits
<< 19;
17075 neon_two_same (0, et
.type
== NT_unsigned
, -1);
17081 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17082 struct neon_type_el et
= neon_check_type (2, rs
,
17083 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17084 NEON_ENCODE (INTEGER
, inst
);
17085 neon_two_same (neon_quad (rs
), 1, et
.size
);
17089 do_neon_zip_uzp (void)
17091 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17092 struct neon_type_el et
= neon_check_type (2, rs
,
17093 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17094 if (rs
== NS_DD
&& et
.size
== 32)
17096 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
17097 inst
.instruction
= N_MNEM_vtrn
;
17101 neon_two_same (neon_quad (rs
), 1, et
.size
);
17105 do_neon_sat_abs_neg (void)
17107 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17108 struct neon_type_el et
= neon_check_type (2, rs
,
17109 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17110 neon_two_same (neon_quad (rs
), 1, et
.size
);
17114 do_neon_pair_long (void)
17116 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17117 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17118 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
17119 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
17120 neon_two_same (neon_quad (rs
), 1, et
.size
);
17124 do_neon_recip_est (void)
17126 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17127 struct neon_type_el et
= neon_check_type (2, rs
,
17128 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
17129 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17130 neon_two_same (neon_quad (rs
), 1, et
.size
);
17136 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17137 struct neon_type_el et
= neon_check_type (2, rs
,
17138 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17139 neon_two_same (neon_quad (rs
), 1, et
.size
);
17145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17146 struct neon_type_el et
= neon_check_type (2, rs
,
17147 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
17148 neon_two_same (neon_quad (rs
), 1, et
.size
);
17154 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17155 struct neon_type_el et
= neon_check_type (2, rs
,
17156 N_EQK
| N_INT
, N_8
| N_KEY
);
17157 neon_two_same (neon_quad (rs
), 1, et
.size
);
17163 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17164 neon_two_same (neon_quad (rs
), 1, -1);
17168 do_neon_tbl_tbx (void)
17170 unsigned listlenbits
;
17171 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
17173 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
17175 first_error (_("bad list length for table lookup"));
17179 listlenbits
= inst
.operands
[1].imm
- 1;
17180 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17181 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17182 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17183 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17184 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17185 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17186 inst
.instruction
|= listlenbits
<< 8;
17188 neon_dp_fixup (&inst
);
17192 do_neon_ldm_stm (void)
17194 /* P, U and L bits are part of bitmask. */
17195 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
17196 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
17198 if (inst
.operands
[1].issingle
)
17200 do_vfp_nsyn_ldm_stm (is_dbmode
);
17204 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
17205 _("writeback (!) must be used for VLDMDB and VSTMDB"));
17207 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
17208 _("register list must contain at least 1 and at most 16 "
17211 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
17212 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17213 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17214 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17216 inst
.instruction
|= offsetbits
;
17218 do_vfp_cond_or_thumb ();
17222 do_neon_ldr_str (void)
17224 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17226 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17227 And is UNPREDICTABLE in thumb mode. */
17229 && inst
.operands
[1].reg
== REG_PC
17230 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17233 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17234 else if (warn_on_deprecated
)
17235 as_tsktsk (_("Use of PC here is deprecated"));
17238 if (inst
.operands
[0].issingle
)
17241 do_vfp_nsyn_opcode ("flds");
17243 do_vfp_nsyn_opcode ("fsts");
17245 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17246 if (inst
.vectype
.el
[0].size
== 16)
17247 do_scalar_fp16_v82_encode ();
17252 do_vfp_nsyn_opcode ("fldd");
17254 do_vfp_nsyn_opcode ("fstd");
17258 /* "interleave" version also handles non-interleaving register VLD1/VST1
17262 do_neon_ld_st_interleave (void)
17264 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17265 N_8
| N_16
| N_32
| N_64
);
17266 unsigned alignbits
= 0;
17268 /* The bits in this table go:
17269 0: register stride of one (0) or two (1)
17270 1,2: register list length, minus one (1, 2, 3, 4).
17271 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17272 We use -1 for invalid entries. */
17273 const int typetable
[] =
17275 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17276 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17277 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17278 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17282 if (et
.type
== NT_invtype
)
17285 if (inst
.operands
[1].immisalign
)
17286 switch (inst
.operands
[1].imm
>> 8)
17288 case 64: alignbits
= 1; break;
17290 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17291 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17292 goto bad_alignment
;
17296 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17297 goto bad_alignment
;
17302 first_error (_("bad alignment"));
17306 inst
.instruction
|= alignbits
<< 4;
17307 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17309 /* Bits [4:6] of the immediate in a list specifier encode register stride
17310 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17311 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17312 up the right value for "type" in a table based on this value and the given
17313 list style, then stick it back. */
17314 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17315 | (((inst
.instruction
>> 8) & 3) << 3);
17317 typebits
= typetable
[idx
];
17319 constraint (typebits
== -1, _("bad list type for instruction"));
17320 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17321 _("bad element type for instruction"));
17323 inst
.instruction
&= ~0xf00;
17324 inst
.instruction
|= typebits
<< 8;
17327 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17328 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17329 otherwise. The variable arguments are a list of pairs of legal (size, align)
17330 values, terminated with -1. */
17333 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17336 int result
= FAIL
, thissize
, thisalign
;
17338 if (!inst
.operands
[1].immisalign
)
17344 va_start (ap
, do_alignment
);
17348 thissize
= va_arg (ap
, int);
17349 if (thissize
== -1)
17351 thisalign
= va_arg (ap
, int);
17353 if (size
== thissize
&& align
== thisalign
)
17356 while (result
!= SUCCESS
);
17360 if (result
== SUCCESS
)
17363 first_error (_("unsupported alignment for instruction"));
17369 do_neon_ld_st_lane (void)
17371 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17372 int align_good
, do_alignment
= 0;
17373 int logsize
= neon_logbits (et
.size
);
17374 int align
= inst
.operands
[1].imm
>> 8;
17375 int n
= (inst
.instruction
>> 8) & 3;
17376 int max_el
= 64 / et
.size
;
17378 if (et
.type
== NT_invtype
)
17381 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17382 _("bad list length"));
17383 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17384 _("scalar index out of range"));
17385 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17387 _("stride of 2 unavailable when element size is 8"));
17391 case 0: /* VLD1 / VST1. */
17392 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17394 if (align_good
== FAIL
)
17398 unsigned alignbits
= 0;
17401 case 16: alignbits
= 0x1; break;
17402 case 32: alignbits
= 0x3; break;
17405 inst
.instruction
|= alignbits
<< 4;
17409 case 1: /* VLD2 / VST2. */
17410 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17411 16, 32, 32, 64, -1);
17412 if (align_good
== FAIL
)
17415 inst
.instruction
|= 1 << 4;
17418 case 2: /* VLD3 / VST3. */
17419 constraint (inst
.operands
[1].immisalign
,
17420 _("can't use alignment with this instruction"));
17423 case 3: /* VLD4 / VST4. */
17424 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17425 16, 64, 32, 64, 32, 128, -1);
17426 if (align_good
== FAIL
)
17430 unsigned alignbits
= 0;
17433 case 8: alignbits
= 0x1; break;
17434 case 16: alignbits
= 0x1; break;
17435 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17438 inst
.instruction
|= alignbits
<< 4;
17445 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17446 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17447 inst
.instruction
|= 1 << (4 + logsize
);
17449 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17450 inst
.instruction
|= logsize
<< 10;
17453 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17456 do_neon_ld_dup (void)
17458 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17459 int align_good
, do_alignment
= 0;
17461 if (et
.type
== NT_invtype
)
17464 switch ((inst
.instruction
>> 8) & 3)
17466 case 0: /* VLD1. */
17467 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17468 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17469 &do_alignment
, 16, 16, 32, 32, -1);
17470 if (align_good
== FAIL
)
17472 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17475 case 2: inst
.instruction
|= 1 << 5; break;
17476 default: first_error (_("bad list length")); return;
17478 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17481 case 1: /* VLD2. */
17482 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17483 &do_alignment
, 8, 16, 16, 32, 32, 64,
17485 if (align_good
== FAIL
)
17487 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17488 _("bad list length"));
17489 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17490 inst
.instruction
|= 1 << 5;
17491 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17494 case 2: /* VLD3. */
17495 constraint (inst
.operands
[1].immisalign
,
17496 _("can't use alignment with this instruction"));
17497 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17498 _("bad list length"));
17499 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17500 inst
.instruction
|= 1 << 5;
17501 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17504 case 3: /* VLD4. */
17506 int align
= inst
.operands
[1].imm
>> 8;
17507 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17508 16, 64, 32, 64, 32, 128, -1);
17509 if (align_good
== FAIL
)
17511 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17512 _("bad list length"));
17513 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17514 inst
.instruction
|= 1 << 5;
17515 if (et
.size
== 32 && align
== 128)
17516 inst
.instruction
|= 0x3 << 6;
17518 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17525 inst
.instruction
|= do_alignment
<< 4;
17528 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17529 apart from bits [11:4]. */
17532 do_neon_ldx_stx (void)
17534 if (inst
.operands
[1].isreg
)
17535 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17537 switch (NEON_LANE (inst
.operands
[0].imm
))
17539 case NEON_INTERLEAVE_LANES
:
17540 NEON_ENCODE (INTERLV
, inst
);
17541 do_neon_ld_st_interleave ();
17544 case NEON_ALL_LANES
:
17545 NEON_ENCODE (DUP
, inst
);
17546 if (inst
.instruction
== N_INV
)
17548 first_error ("only loads support such operands");
17555 NEON_ENCODE (LANE
, inst
);
17556 do_neon_ld_st_lane ();
17559 /* L bit comes from bit mask. */
17560 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17561 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17562 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17564 if (inst
.operands
[1].postind
)
17566 int postreg
= inst
.operands
[1].imm
& 0xf;
17567 constraint (!inst
.operands
[1].immisreg
,
17568 _("post-index must be a register"));
17569 constraint (postreg
== 0xd || postreg
== 0xf,
17570 _("bad register for post-index"));
17571 inst
.instruction
|= postreg
;
17575 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17576 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
17577 || inst
.relocs
[0].exp
.X_add_number
!= 0,
17580 if (inst
.operands
[1].writeback
)
17582 inst
.instruction
|= 0xd;
17585 inst
.instruction
|= 0xf;
17589 inst
.instruction
|= 0xf9000000;
17591 inst
.instruction
|= 0xf4000000;
17596 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17598 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17599 D register operands. */
17600 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17601 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17604 NEON_ENCODE (FPV8
, inst
);
17606 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17608 do_vfp_sp_dyadic ();
17610 /* ARMv8.2 fp16 instruction. */
17612 do_scalar_fp16_v82_encode ();
17615 do_vfp_dp_rd_rn_rm ();
17618 inst
.instruction
|= 0x100;
17620 inst
.instruction
|= 0xf0000000;
17626 set_it_insn_type (OUTSIDE_IT_INSN
);
17628 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17629 first_error (_("invalid instruction shape"));
17635 set_it_insn_type (OUTSIDE_IT_INSN
);
17637 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17640 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17643 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17647 do_vrint_1 (enum neon_cvt_mode mode
)
17649 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17650 struct neon_type_el et
;
17655 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17656 D register operands. */
17657 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17658 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17661 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17663 if (et
.type
!= NT_invtype
)
17665 /* VFP encodings. */
17666 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17667 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17668 set_it_insn_type (OUTSIDE_IT_INSN
);
17670 NEON_ENCODE (FPV8
, inst
);
17671 if (rs
== NS_FF
|| rs
== NS_HH
)
17672 do_vfp_sp_monadic ();
17674 do_vfp_dp_rd_rm ();
17678 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17679 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17680 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17681 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17682 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17683 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17684 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17688 inst
.instruction
|= (rs
== NS_DD
) << 8;
17689 do_vfp_cond_or_thumb ();
17691 /* ARMv8.2 fp16 vrint instruction. */
17693 do_scalar_fp16_v82_encode ();
17697 /* Neon encodings (or something broken...). */
17699 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17701 if (et
.type
== NT_invtype
)
17704 set_it_insn_type (OUTSIDE_IT_INSN
);
17705 NEON_ENCODE (FLOAT
, inst
);
17707 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17714 inst
.instruction
|= neon_quad (rs
) << 6;
17715 /* Mask off the original size bits and reencode them. */
17716 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17717 | neon_logbits (et
.size
) << 18);
17721 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17722 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17723 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17724 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17725 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17726 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17727 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17732 inst
.instruction
|= 0xfc000000;
17734 inst
.instruction
|= 0xf0000000;
17741 do_vrint_1 (neon_cvt_mode_x
);
17747 do_vrint_1 (neon_cvt_mode_z
);
17753 do_vrint_1 (neon_cvt_mode_r
);
17759 do_vrint_1 (neon_cvt_mode_a
);
17765 do_vrint_1 (neon_cvt_mode_n
);
17771 do_vrint_1 (neon_cvt_mode_p
);
17777 do_vrint_1 (neon_cvt_mode_m
);
17781 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17783 unsigned regno
= NEON_SCALAR_REG (opnd
);
17784 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17786 if (elsize
== 16 && elno
< 2 && regno
< 16)
17787 return regno
| (elno
<< 4);
17788 else if (elsize
== 32 && elno
== 0)
17791 first_error (_("scalar out of range"));
17798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17800 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17801 _("expression too complex"));
17802 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17803 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17804 _("immediate out of range"));
17806 if (inst
.operands
[2].isscalar
)
17808 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17809 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17810 N_KEY
| N_F16
| N_F32
).size
;
17811 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17813 inst
.instruction
= 0xfe000800;
17814 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17815 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17816 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17817 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17818 inst
.instruction
|= LOW4 (m
);
17819 inst
.instruction
|= HI1 (m
) << 5;
17820 inst
.instruction
|= neon_quad (rs
) << 6;
17821 inst
.instruction
|= rot
<< 20;
17822 inst
.instruction
|= (size
== 32) << 23;
17826 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17827 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17828 N_KEY
| N_F16
| N_F32
).size
;
17829 neon_three_same (neon_quad (rs
), 0, -1);
17830 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17831 inst
.instruction
|= 0xfc200800;
17832 inst
.instruction
|= rot
<< 23;
17833 inst
.instruction
|= (size
== 32) << 20;
17840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17842 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17843 _("expression too complex"));
17844 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17845 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17846 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17847 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17848 N_KEY
| N_F16
| N_F32
).size
;
17849 neon_three_same (neon_quad (rs
), 0, -1);
17850 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17851 inst
.instruction
|= 0xfc800800;
17852 inst
.instruction
|= (rot
== 270) << 24;
17853 inst
.instruction
|= (size
== 32) << 20;
17856 /* Dot Product instructions encoding support. */
17859 do_neon_dotproduct (int unsigned_p
)
17861 enum neon_shape rs
;
17862 unsigned scalar_oprd2
= 0;
17865 if (inst
.cond
!= COND_ALWAYS
)
17866 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17867 "is UNPREDICTABLE"));
17869 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17872 /* Dot Product instructions are in three-same D/Q register format or the third
17873 operand can be a scalar index register. */
17874 if (inst
.operands
[2].isscalar
)
17876 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17877 high8
= 0xfe000000;
17878 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17882 high8
= 0xfc000000;
17883 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17887 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17889 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17891 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17892 Product instruction, so we pass 0 as the "ubit" parameter. And the
17893 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17894 neon_three_same (neon_quad (rs
), 0, 32);
17896 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17897 different NEON three-same encoding. */
17898 inst
.instruction
&= 0x00ffffff;
17899 inst
.instruction
|= high8
;
17900 /* Encode 'U' bit which indicates signedness. */
17901 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17902 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17903 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17904 the instruction encoding. */
17905 if (inst
.operands
[2].isscalar
)
17907 inst
.instruction
&= 0xffffffd0;
17908 inst
.instruction
|= LOW4 (scalar_oprd2
);
17909 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17913 /* Dot Product instructions for signed integer. */
17916 do_neon_dotproduct_s (void)
17918 return do_neon_dotproduct (0);
17921 /* Dot Product instructions for unsigned integer. */
17924 do_neon_dotproduct_u (void)
17926 return do_neon_dotproduct (1);
17929 /* Crypto v1 instructions. */
17931 do_crypto_2op_1 (unsigned elttype
, int op
)
17933 set_it_insn_type (OUTSIDE_IT_INSN
);
17935 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17941 NEON_ENCODE (INTEGER
, inst
);
17942 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17943 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17944 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17945 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17947 inst
.instruction
|= op
<< 6;
17950 inst
.instruction
|= 0xfc000000;
17952 inst
.instruction
|= 0xf0000000;
17956 do_crypto_3op_1 (int u
, int op
)
17958 set_it_insn_type (OUTSIDE_IT_INSN
);
17960 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17961 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17966 NEON_ENCODE (INTEGER
, inst
);
17967 neon_three_same (1, u
, 8 << op
);
17973 do_crypto_2op_1 (N_8
, 0);
17979 do_crypto_2op_1 (N_8
, 1);
17985 do_crypto_2op_1 (N_8
, 2);
17991 do_crypto_2op_1 (N_8
, 3);
17997 do_crypto_3op_1 (0, 0);
18003 do_crypto_3op_1 (0, 1);
18009 do_crypto_3op_1 (0, 2);
18015 do_crypto_3op_1 (0, 3);
18021 do_crypto_3op_1 (1, 0);
18027 do_crypto_3op_1 (1, 1);
18031 do_sha256su1 (void)
18033 do_crypto_3op_1 (1, 2);
18039 do_crypto_2op_1 (N_32
, -1);
18045 do_crypto_2op_1 (N_32
, 0);
18049 do_sha256su0 (void)
18051 do_crypto_2op_1 (N_32
, 1);
18055 do_crc32_1 (unsigned int poly
, unsigned int sz
)
18057 unsigned int Rd
= inst
.operands
[0].reg
;
18058 unsigned int Rn
= inst
.operands
[1].reg
;
18059 unsigned int Rm
= inst
.operands
[2].reg
;
18061 set_it_insn_type (OUTSIDE_IT_INSN
);
18062 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
18063 inst
.instruction
|= LOW4 (Rn
) << 16;
18064 inst
.instruction
|= LOW4 (Rm
);
18065 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
18066 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
18068 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
18069 as_warn (UNPRED_REG ("r15"));
18111 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18113 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
18114 do_vfp_sp_dp_cvt ();
18115 do_vfp_cond_or_thumb ();
18119 /* Overall per-instruction processing. */
18121 /* We need to be able to fix up arbitrary expressions in some statements.
18122 This is so that we can handle symbols that are an arbitrary distance from
18123 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
18124 which returns part of an address in a form which will be valid for
18125 a data instruction. We do this by pushing the expression into a symbol
18126 in the expr_section, and creating a fix for that. */
18129 fix_new_arm (fragS
* frag
,
18143 /* Create an absolute valued symbol, so we have something to
18144 refer to in the object file. Unfortunately for us, gas's
18145 generic expression parsing will already have folded out
18146 any use of .set foo/.type foo %function that may have
18147 been used to set type information of the target location,
18148 that's being specified symbolically. We have to presume
18149 the user knows what they are doing. */
18153 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
18155 symbol
= symbol_find_or_make (name
);
18156 S_SET_SEGMENT (symbol
, absolute_section
);
18157 symbol_set_frag (symbol
, &zero_address_frag
);
18158 S_SET_VALUE (symbol
, exp
->X_add_number
);
18159 exp
->X_op
= O_symbol
;
18160 exp
->X_add_symbol
= symbol
;
18161 exp
->X_add_number
= 0;
18167 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
18168 (enum bfd_reloc_code_real
) reloc
);
18172 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
18173 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
18177 /* Mark whether the fix is to a THUMB instruction, or an ARM
18179 new_fix
->tc_fix_data
= thumb_mode
;
18182 /* Create a frg for an instruction requiring relaxation. */
18184 output_relax_insn (void)
18190 /* The size of the instruction is unknown, so tie the debug info to the
18191 start of the instruction. */
18192 dwarf2_emit_insn (0);
18194 switch (inst
.relocs
[0].exp
.X_op
)
18197 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
18198 offset
= inst
.relocs
[0].exp
.X_add_number
;
18202 offset
= inst
.relocs
[0].exp
.X_add_number
;
18205 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
18209 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
18210 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
18211 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
18214 /* Write a 32-bit thumb instruction to buf. */
18216 put_thumb32_insn (char * buf
, unsigned long insn
)
18218 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18219 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18223 output_inst (const char * str
)
18229 as_bad ("%s -- `%s'", inst
.error
, str
);
18234 output_relax_insn ();
18237 if (inst
.size
== 0)
18240 to
= frag_more (inst
.size
);
18241 /* PR 9814: Record the thumb mode into the current frag so that we know
18242 what type of NOP padding to use, if necessary. We override any previous
18243 setting so that if the mode has changed then the NOPS that we use will
18244 match the encoding of the last instruction in the frag. */
18245 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18247 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18249 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18250 put_thumb32_insn (to
, inst
.instruction
);
18252 else if (inst
.size
> INSN_SIZE
)
18254 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18255 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18256 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18259 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18262 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18264 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
18265 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18266 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
18267 inst
.relocs
[r
].type
);
18270 dwarf2_emit_insn (inst
.size
);
18274 output_it_inst (int cond
, int mask
, char * to
)
18276 unsigned long instruction
= 0xbf00;
18279 instruction
|= mask
;
18280 instruction
|= cond
<< 4;
18284 to
= frag_more (2);
18286 dwarf2_emit_insn (2);
18290 md_number_to_chars (to
, instruction
, 2);
18295 /* Tag values used in struct asm_opcode's tag field. */
18298 OT_unconditional
, /* Instruction cannot be conditionalized.
18299 The ARM condition field is still 0xE. */
18300 OT_unconditionalF
, /* Instruction cannot be conditionalized
18301 and carries 0xF in its ARM condition field. */
18302 OT_csuffix
, /* Instruction takes a conditional suffix. */
18303 OT_csuffixF
, /* Some forms of the instruction take a conditional
18304 suffix, others place 0xF where the condition field
18306 OT_cinfix3
, /* Instruction takes a conditional infix,
18307 beginning at character index 3. (In
18308 unified mode, it becomes a suffix.) */
18309 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18310 tsts, cmps, cmns, and teqs. */
18311 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18312 character index 3, even in unified mode. Used for
18313 legacy instructions where suffix and infix forms
18314 may be ambiguous. */
18315 OT_csuf_or_in3
, /* Instruction takes either a conditional
18316 suffix or an infix at character index 3. */
18317 OT_odd_infix_unc
, /* This is the unconditional variant of an
18318 instruction that takes a conditional infix
18319 at an unusual position. In unified mode,
18320 this variant will accept a suffix. */
18321 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18322 are the conditional variants of instructions that
18323 take conditional infixes in unusual positions.
18324 The infix appears at character index
18325 (tag - OT_odd_infix_0). These are not accepted
18326 in unified mode. */
18329 /* Subroutine of md_assemble, responsible for looking up the primary
18330 opcode from the mnemonic the user wrote. STR points to the
18331 beginning of the mnemonic.
18333 This is not simply a hash table lookup, because of conditional
18334 variants. Most instructions have conditional variants, which are
18335 expressed with a _conditional affix_ to the mnemonic. If we were
18336 to encode each conditional variant as a literal string in the opcode
18337 table, it would have approximately 20,000 entries.
18339 Most mnemonics take this affix as a suffix, and in unified syntax,
18340 'most' is upgraded to 'all'. However, in the divided syntax, some
18341 instructions take the affix as an infix, notably the s-variants of
18342 the arithmetic instructions. Of those instructions, all but six
18343 have the infix appear after the third character of the mnemonic.
18345 Accordingly, the algorithm for looking up primary opcodes given
18348 1. Look up the identifier in the opcode table.
18349 If we find a match, go to step U.
18351 2. Look up the last two characters of the identifier in the
18352 conditions table. If we find a match, look up the first N-2
18353 characters of the identifier in the opcode table. If we
18354 find a match, go to step CE.
18356 3. Look up the fourth and fifth characters of the identifier in
18357 the conditions table. If we find a match, extract those
18358 characters from the identifier, and look up the remaining
18359 characters in the opcode table. If we find a match, go
18364 U. Examine the tag field of the opcode structure, in case this is
18365 one of the six instructions with its conditional infix in an
18366 unusual place. If it is, the tag tells us where to find the
18367 infix; look it up in the conditions table and set inst.cond
18368 accordingly. Otherwise, this is an unconditional instruction.
18369 Again set inst.cond accordingly. Return the opcode structure.
18371 CE. Examine the tag field to make sure this is an instruction that
18372 should receive a conditional suffix. If it is not, fail.
18373 Otherwise, set inst.cond from the suffix we already looked up,
18374 and return the opcode structure.
18376 CM. Examine the tag field to make sure this is an instruction that
18377 should receive a conditional infix after the third character.
18378 If it is not, fail. Otherwise, undo the edits to the current
18379 line of input and proceed as for case CE. */
18381 static const struct asm_opcode
*
18382 opcode_lookup (char **str
)
18386 const struct asm_opcode
*opcode
;
18387 const struct asm_cond
*cond
;
18390 /* Scan up to the end of the mnemonic, which must end in white space,
18391 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18392 for (base
= end
= *str
; *end
!= '\0'; end
++)
18393 if (*end
== ' ' || *end
== '.')
18399 /* Handle a possible width suffix and/or Neon type suffix. */
18404 /* The .w and .n suffixes are only valid if the unified syntax is in
18406 if (unified_syntax
&& end
[1] == 'w')
18408 else if (unified_syntax
&& end
[1] == 'n')
18413 inst
.vectype
.elems
= 0;
18415 *str
= end
+ offset
;
18417 if (end
[offset
] == '.')
18419 /* See if we have a Neon type suffix (possible in either unified or
18420 non-unified ARM syntax mode). */
18421 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18424 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18430 /* Look for unaffixed or special-case affixed mnemonic. */
18431 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18436 if (opcode
->tag
< OT_odd_infix_0
)
18438 inst
.cond
= COND_ALWAYS
;
18442 if (warn_on_deprecated
&& unified_syntax
)
18443 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18444 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18445 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18448 inst
.cond
= cond
->value
;
18452 /* Cannot have a conditional suffix on a mnemonic of less than two
18454 if (end
- base
< 3)
18457 /* Look for suffixed mnemonic. */
18459 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18460 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18462 if (opcode
&& cond
)
18465 switch (opcode
->tag
)
18467 case OT_cinfix3_legacy
:
18468 /* Ignore conditional suffixes matched on infix only mnemonics. */
18472 case OT_cinfix3_deprecated
:
18473 case OT_odd_infix_unc
:
18474 if (!unified_syntax
)
18476 /* Fall through. */
18480 case OT_csuf_or_in3
:
18481 inst
.cond
= cond
->value
;
18484 case OT_unconditional
:
18485 case OT_unconditionalF
:
18487 inst
.cond
= cond
->value
;
18490 /* Delayed diagnostic. */
18491 inst
.error
= BAD_COND
;
18492 inst
.cond
= COND_ALWAYS
;
18501 /* Cannot have a usual-position infix on a mnemonic of less than
18502 six characters (five would be a suffix). */
18503 if (end
- base
< 6)
18506 /* Look for infixed mnemonic in the usual position. */
18508 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18512 memcpy (save
, affix
, 2);
18513 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18514 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18516 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18517 memcpy (affix
, save
, 2);
18520 && (opcode
->tag
== OT_cinfix3
18521 || opcode
->tag
== OT_cinfix3_deprecated
18522 || opcode
->tag
== OT_csuf_or_in3
18523 || opcode
->tag
== OT_cinfix3_legacy
))
18526 if (warn_on_deprecated
&& unified_syntax
18527 && (opcode
->tag
== OT_cinfix3
18528 || opcode
->tag
== OT_cinfix3_deprecated
))
18529 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18531 inst
.cond
= cond
->value
;
18538 /* This function generates an initial IT instruction, leaving its block
18539 virtually open for the new instructions. Eventually,
18540 the mask will be updated by now_it_add_mask () each time
18541 a new instruction needs to be included in the IT block.
18542 Finally, the block is closed with close_automatic_it_block ().
18543 The block closure can be requested either from md_assemble (),
18544 a tencode (), or due to a label hook. */
18547 new_automatic_it_block (int cond
)
18549 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18550 now_it
.mask
= 0x18;
18552 now_it
.block_length
= 1;
18553 mapping_state (MAP_THUMB
);
18554 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18555 now_it
.warn_deprecated
= FALSE
;
18556 now_it
.insn_cond
= TRUE
;
18559 /* Close an automatic IT block.
18560 See comments in new_automatic_it_block (). */
18563 close_automatic_it_block (void)
18565 now_it
.mask
= 0x10;
18566 now_it
.block_length
= 0;
18569 /* Update the mask of the current automatically-generated IT
18570 instruction. See comments in new_automatic_it_block (). */
18573 now_it_add_mask (int cond
)
18575 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18576 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18577 | ((bitvalue) << (nbit)))
18578 const int resulting_bit
= (cond
& 1);
18580 now_it
.mask
&= 0xf;
18581 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18583 (5 - now_it
.block_length
));
18584 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18586 ((5 - now_it
.block_length
) - 1) );
18587 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18590 #undef SET_BIT_VALUE
18593 /* The IT blocks handling machinery is accessed through the these functions:
18594 it_fsm_pre_encode () from md_assemble ()
18595 set_it_insn_type () optional, from the tencode functions
18596 set_it_insn_type_last () ditto
18597 in_it_block () ditto
18598 it_fsm_post_encode () from md_assemble ()
18599 force_automatic_it_block_close () from label handling functions
18602 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18603 initializing the IT insn type with a generic initial value depending
18604 on the inst.condition.
18605 2) During the tencode function, two things may happen:
18606 a) The tencode function overrides the IT insn type by
18607 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18608 b) The tencode function queries the IT block state by
18609 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18611 Both set_it_insn_type and in_it_block run the internal FSM state
18612 handling function (handle_it_state), because: a) setting the IT insn
18613 type may incur in an invalid state (exiting the function),
18614 and b) querying the state requires the FSM to be updated.
18615 Specifically we want to avoid creating an IT block for conditional
18616 branches, so it_fsm_pre_encode is actually a guess and we can't
18617 determine whether an IT block is required until the tencode () routine
18618 has decided what type of instruction this actually it.
18619 Because of this, if set_it_insn_type and in_it_block have to be used,
18620 set_it_insn_type has to be called first.
18622 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18623 determines the insn IT type depending on the inst.cond code.
18624 When a tencode () routine encodes an instruction that can be
18625 either outside an IT block, or, in the case of being inside, has to be
18626 the last one, set_it_insn_type_last () will determine the proper
18627 IT instruction type based on the inst.cond code. Otherwise,
18628 set_it_insn_type can be called for overriding that logic or
18629 for covering other cases.
18631 Calling handle_it_state () may not transition the IT block state to
18632 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18633 still queried. Instead, if the FSM determines that the state should
18634 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18635 after the tencode () function: that's what it_fsm_post_encode () does.
18637 Since in_it_block () calls the state handling function to get an
18638 updated state, an error may occur (due to invalid insns combination).
18639 In that case, inst.error is set.
18640 Therefore, inst.error has to be checked after the execution of
18641 the tencode () routine.
18643 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18644 any pending state change (if any) that didn't take place in
18645 handle_it_state () as explained above. */
18648 it_fsm_pre_encode (void)
18650 if (inst
.cond
!= COND_ALWAYS
)
18651 inst
.it_insn_type
= INSIDE_IT_INSN
;
18653 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18655 now_it
.state_handled
= 0;
18658 /* IT state FSM handling function. */
18661 handle_it_state (void)
18663 now_it
.state_handled
= 1;
18664 now_it
.insn_cond
= FALSE
;
18666 switch (now_it
.state
)
18668 case OUTSIDE_IT_BLOCK
:
18669 switch (inst
.it_insn_type
)
18671 case OUTSIDE_IT_INSN
:
18674 case INSIDE_IT_INSN
:
18675 case INSIDE_IT_LAST_INSN
:
18676 if (thumb_mode
== 0)
18679 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18680 as_tsktsk (_("Warning: conditional outside an IT block"\
18685 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18686 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18688 /* Automatically generate the IT instruction. */
18689 new_automatic_it_block (inst
.cond
);
18690 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18691 close_automatic_it_block ();
18695 inst
.error
= BAD_OUT_IT
;
18701 case IF_INSIDE_IT_LAST_INSN
:
18702 case NEUTRAL_IT_INSN
:
18706 now_it
.state
= MANUAL_IT_BLOCK
;
18707 now_it
.block_length
= 0;
18712 case AUTOMATIC_IT_BLOCK
:
18713 /* Three things may happen now:
18714 a) We should increment current it block size;
18715 b) We should close current it block (closing insn or 4 insns);
18716 c) We should close current it block and start a new one (due
18717 to incompatible conditions or
18718 4 insns-length block reached). */
18720 switch (inst
.it_insn_type
)
18722 case OUTSIDE_IT_INSN
:
18723 /* The closure of the block shall happen immediately,
18724 so any in_it_block () call reports the block as closed. */
18725 force_automatic_it_block_close ();
18728 case INSIDE_IT_INSN
:
18729 case INSIDE_IT_LAST_INSN
:
18730 case IF_INSIDE_IT_LAST_INSN
:
18731 now_it
.block_length
++;
18733 if (now_it
.block_length
> 4
18734 || !now_it_compatible (inst
.cond
))
18736 force_automatic_it_block_close ();
18737 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18738 new_automatic_it_block (inst
.cond
);
18742 now_it
.insn_cond
= TRUE
;
18743 now_it_add_mask (inst
.cond
);
18746 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18747 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18748 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18749 close_automatic_it_block ();
18752 case NEUTRAL_IT_INSN
:
18753 now_it
.block_length
++;
18754 now_it
.insn_cond
= TRUE
;
18756 if (now_it
.block_length
> 4)
18757 force_automatic_it_block_close ();
18759 now_it_add_mask (now_it
.cc
& 1);
18763 close_automatic_it_block ();
18764 now_it
.state
= MANUAL_IT_BLOCK
;
18769 case MANUAL_IT_BLOCK
:
18771 /* Check conditional suffixes. */
18772 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18775 now_it
.mask
&= 0x1f;
18776 is_last
= (now_it
.mask
== 0x10);
18777 now_it
.insn_cond
= TRUE
;
18779 switch (inst
.it_insn_type
)
18781 case OUTSIDE_IT_INSN
:
18782 inst
.error
= BAD_NOT_IT
;
18785 case INSIDE_IT_INSN
:
18786 if (cond
!= inst
.cond
)
18788 inst
.error
= BAD_IT_COND
;
18793 case INSIDE_IT_LAST_INSN
:
18794 case IF_INSIDE_IT_LAST_INSN
:
18795 if (cond
!= inst
.cond
)
18797 inst
.error
= BAD_IT_COND
;
18802 inst
.error
= BAD_BRANCH
;
18807 case NEUTRAL_IT_INSN
:
18808 /* The BKPT instruction is unconditional even in an IT block. */
18812 inst
.error
= BAD_IT_IT
;
18822 struct depr_insn_mask
18824 unsigned long pattern
;
18825 unsigned long mask
;
18826 const char* description
;
18829 /* List of 16-bit instruction patterns deprecated in an IT block in
18831 static const struct depr_insn_mask depr_it_insns
[] = {
18832 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18833 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18834 { 0xa000, 0xb800, N_("ADR") },
18835 { 0x4800, 0xf800, N_("Literal loads") },
18836 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18837 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18838 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18839 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18840 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18845 it_fsm_post_encode (void)
18849 if (!now_it
.state_handled
)
18850 handle_it_state ();
18852 if (now_it
.insn_cond
18853 && !now_it
.warn_deprecated
18854 && warn_on_deprecated
18855 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18856 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18858 if (inst
.instruction
>= 0x10000)
18860 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18861 "performance deprecated in ARMv8-A and ARMv8-R"));
18862 now_it
.warn_deprecated
= TRUE
;
18866 const struct depr_insn_mask
*p
= depr_it_insns
;
18868 while (p
->mask
!= 0)
18870 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18872 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18873 "instructions of the following class are "
18874 "performance deprecated in ARMv8-A and "
18875 "ARMv8-R: %s"), p
->description
);
18876 now_it
.warn_deprecated
= TRUE
;
18884 if (now_it
.block_length
> 1)
18886 as_tsktsk (_("IT blocks containing more than one conditional "
18887 "instruction are performance deprecated in ARMv8-A and "
18889 now_it
.warn_deprecated
= TRUE
;
18893 is_last
= (now_it
.mask
== 0x10);
18896 now_it
.state
= OUTSIDE_IT_BLOCK
;
18902 force_automatic_it_block_close (void)
18904 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18906 close_automatic_it_block ();
18907 now_it
.state
= OUTSIDE_IT_BLOCK
;
18915 if (!now_it
.state_handled
)
18916 handle_it_state ();
18918 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18921 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18922 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18923 here, hence the "known" in the function name. */
18926 known_t32_only_insn (const struct asm_opcode
*opcode
)
18928 /* Original Thumb-1 wide instruction. */
18929 if (opcode
->tencode
== do_t_blx
18930 || opcode
->tencode
== do_t_branch23
18931 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18932 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18935 /* Wide-only instruction added to ARMv8-M Baseline. */
18936 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18937 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18938 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18939 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18945 /* Whether wide instruction variant can be used if available for a valid OPCODE
18949 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18951 if (known_t32_only_insn (opcode
))
18954 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18955 of variant T3 of B.W is checked in do_t_branch. */
18956 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18957 && opcode
->tencode
== do_t_branch
)
18960 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18961 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18962 && opcode
->tencode
== do_t_mov_cmp
18963 /* Make sure CMP instruction is not affected. */
18964 && opcode
->aencode
== do_mov
)
18967 /* Wide instruction variants of all instructions with narrow *and* wide
18968 variants become available with ARMv6t2. Other opcodes are either
18969 narrow-only or wide-only and are thus available if OPCODE is valid. */
18970 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18973 /* OPCODE with narrow only instruction variant or wide variant not
18979 md_assemble (char *str
)
18982 const struct asm_opcode
* opcode
;
18984 /* Align the previous label if needed. */
18985 if (last_label_seen
!= NULL
)
18987 symbol_set_frag (last_label_seen
, frag_now
);
18988 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18989 S_SET_SEGMENT (last_label_seen
, now_seg
);
18992 memset (&inst
, '\0', sizeof (inst
));
18994 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18995 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
18997 opcode
= opcode_lookup (&p
);
19000 /* It wasn't an instruction, but it might be a register alias of
19001 the form alias .req reg, or a Neon .dn/.qn directive. */
19002 if (! create_register_alias (str
, p
)
19003 && ! create_neon_reg_alias (str
, p
))
19004 as_bad (_("bad instruction `%s'"), str
);
19009 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
19010 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
19012 /* The value which unconditional instructions should have in place of the
19013 condition field. */
19014 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
19018 arm_feature_set variant
;
19020 variant
= cpu_variant
;
19021 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
19022 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
19023 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
19024 /* Check that this instruction is supported for this CPU. */
19025 if (!opcode
->tvariant
19026 || (thumb_mode
== 1
19027 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
19029 if (opcode
->tencode
== do_t_swi
)
19030 as_bad (_("SVC is not permitted on this architecture"));
19032 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
19035 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
19036 && opcode
->tencode
!= do_t_branch
)
19038 as_bad (_("Thumb does not support conditional execution"));
19042 /* Two things are addressed here:
19043 1) Implicit require narrow instructions on Thumb-1.
19044 This avoids relaxation accidentally introducing Thumb-2
19046 2) Reject wide instructions in non Thumb-2 cores.
19048 Only instructions with narrow and wide variants need to be handled
19049 but selecting all non wide-only instructions is easier. */
19050 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
19051 && !t32_insn_ok (variant
, opcode
))
19053 if (inst
.size_req
== 0)
19055 else if (inst
.size_req
== 4)
19057 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
19058 as_bad (_("selected processor does not support 32bit wide "
19059 "variant of instruction `%s'"), str
);
19061 as_bad (_("selected processor does not support `%s' in "
19062 "Thumb-2 mode"), str
);
19067 inst
.instruction
= opcode
->tvalue
;
19069 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
19071 /* Prepare the it_insn_type for those encodings that don't set
19073 it_fsm_pre_encode ();
19075 opcode
->tencode ();
19077 it_fsm_post_encode ();
19080 if (!(inst
.error
|| inst
.relax
))
19082 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
19083 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
19084 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
19086 as_bad (_("cannot honor width suffix -- `%s'"), str
);
19091 /* Something has gone badly wrong if we try to relax a fixed size
19093 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
19095 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19096 *opcode
->tvariant
);
19097 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
19098 set those bits when Thumb-2 32-bit instructions are seen. The impact
19099 of relaxable instructions will be considered later after we finish all
19101 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
19102 variant
= arm_arch_none
;
19104 variant
= cpu_variant
;
19105 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
19106 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19109 check_neon_suffixes
;
19113 mapping_state (MAP_THUMB
);
19116 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19120 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
19121 is_bx
= (opcode
->aencode
== do_bx
);
19123 /* Check that this instruction is supported for this CPU. */
19124 if (!(is_bx
&& fix_v4bx
)
19125 && !(opcode
->avariant
&&
19126 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
19128 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
19133 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
19137 inst
.instruction
= opcode
->avalue
;
19138 if (opcode
->tag
== OT_unconditionalF
)
19139 inst
.instruction
|= 0xFU
<< 28;
19141 inst
.instruction
|= inst
.cond
<< 28;
19142 inst
.size
= INSN_SIZE
;
19143 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
19145 it_fsm_pre_encode ();
19146 opcode
->aencode ();
19147 it_fsm_post_encode ();
19149 /* Arm mode bx is marked as both v4T and v5 because it's still required
19150 on a hypothetical non-thumb v5 core. */
19152 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
19154 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
19155 *opcode
->avariant
);
19157 check_neon_suffixes
;
19161 mapping_state (MAP_ARM
);
19166 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
19174 check_it_blocks_finished (void)
19179 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
19180 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
19181 == MANUAL_IT_BLOCK
)
19183 as_warn (_("section '%s' finished with an open IT block."),
19187 if (now_it
.state
== MANUAL_IT_BLOCK
)
19188 as_warn (_("file finished with an open IT block."));
19192 /* Various frobbings of labels and their addresses. */
19195 arm_start_line_hook (void)
19197 last_label_seen
= NULL
;
19201 arm_frob_label (symbolS
* sym
)
19203 last_label_seen
= sym
;
19205 ARM_SET_THUMB (sym
, thumb_mode
);
19207 #if defined OBJ_COFF || defined OBJ_ELF
19208 ARM_SET_INTERWORK (sym
, support_interwork
);
19211 force_automatic_it_block_close ();
19213 /* Note - do not allow local symbols (.Lxxx) to be labelled
19214 as Thumb functions. This is because these labels, whilst
19215 they exist inside Thumb code, are not the entry points for
19216 possible ARM->Thumb calls. Also, these labels can be used
19217 as part of a computed goto or switch statement. eg gcc
19218 can generate code that looks like this:
19220 ldr r2, [pc, .Laaa]
19230 The first instruction loads the address of the jump table.
19231 The second instruction converts a table index into a byte offset.
19232 The third instruction gets the jump address out of the table.
19233 The fourth instruction performs the jump.
19235 If the address stored at .Laaa is that of a symbol which has the
19236 Thumb_Func bit set, then the linker will arrange for this address
19237 to have the bottom bit set, which in turn would mean that the
19238 address computation performed by the third instruction would end
19239 up with the bottom bit set. Since the ARM is capable of unaligned
19240 word loads, the instruction would then load the incorrect address
19241 out of the jump table, and chaos would ensue. */
19242 if (label_is_thumb_function_name
19243 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19244 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19246 /* When the address of a Thumb function is taken the bottom
19247 bit of that address should be set. This will allow
19248 interworking between Arm and Thumb functions to work
19251 THUMB_SET_FUNC (sym
, 1);
19253 label_is_thumb_function_name
= FALSE
;
19256 dwarf2_emit_label (sym
);
19260 arm_data_in_code (void)
19262 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19264 *input_line_pointer
= '/';
19265 input_line_pointer
+= 5;
19266 *input_line_pointer
= 0;
19274 arm_canonicalize_symbol_name (char * name
)
19278 if (thumb_mode
&& (len
= strlen (name
)) > 5
19279 && streq (name
+ len
- 5, "/data"))
19280 *(name
+ len
- 5) = 0;
19285 /* Table of all register names defined by default. The user can
19286 define additional names with .req. Note that all register names
19287 should appear in both upper and lowercase variants. Some registers
19288 also have mixed-case names. */
19290 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19291 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19292 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19293 #define REGSET(p,t) \
19294 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19295 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19296 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19297 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19298 #define REGSETH(p,t) \
19299 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19300 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19301 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19302 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19303 #define REGSET2(p,t) \
19304 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19305 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19306 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19307 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19308 #define SPLRBANK(base,bank,t) \
19309 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19310 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19311 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19312 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19313 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19314 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19316 static const struct reg_entry reg_names
[] =
19318 /* ARM integer registers. */
19319 REGSET(r
, RN
), REGSET(R
, RN
),
19321 /* ATPCS synonyms. */
19322 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19323 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19324 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19326 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19327 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19328 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19330 /* Well-known aliases. */
19331 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19332 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19334 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19335 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19337 /* Coprocessor numbers. */
19338 REGSET(p
, CP
), REGSET(P
, CP
),
19340 /* Coprocessor register numbers. The "cr" variants are for backward
19342 REGSET(c
, CN
), REGSET(C
, CN
),
19343 REGSET(cr
, CN
), REGSET(CR
, CN
),
19345 /* ARM banked registers. */
19346 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19347 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19348 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19349 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19350 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19351 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19352 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19354 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19355 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19356 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19357 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19358 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19359 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19360 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19361 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19363 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19364 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19365 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19366 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19367 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19368 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19369 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19370 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19371 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19373 /* FPA registers. */
19374 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19375 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19377 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19378 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19380 /* VFP SP registers. */
19381 REGSET(s
,VFS
), REGSET(S
,VFS
),
19382 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19384 /* VFP DP Registers. */
19385 REGSET(d
,VFD
), REGSET(D
,VFD
),
19386 /* Extra Neon DP registers. */
19387 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19389 /* Neon QP registers. */
19390 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19392 /* VFP control registers. */
19393 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19394 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19395 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19396 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19397 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19398 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19399 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19401 /* Maverick DSP coprocessor registers. */
19402 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19403 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19405 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19406 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19407 REGDEF(dspsc
,0,DSPSC
),
19409 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19410 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19411 REGDEF(DSPSC
,0,DSPSC
),
19413 /* iWMMXt data registers - p0, c0-15. */
19414 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19416 /* iWMMXt control registers - p1, c0-3. */
19417 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19418 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19419 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19420 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19422 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19423 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19424 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19425 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19426 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19428 /* XScale accumulator registers. */
19429 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19435 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19436 within psr_required_here. */
19437 static const struct asm_psr psrs
[] =
19439 /* Backward compatibility notation. Note that "all" is no longer
19440 truly all possible PSR bits. */
19441 {"all", PSR_c
| PSR_f
},
19445 /* Individual flags. */
19451 /* Combinations of flags. */
19452 {"fs", PSR_f
| PSR_s
},
19453 {"fx", PSR_f
| PSR_x
},
19454 {"fc", PSR_f
| PSR_c
},
19455 {"sf", PSR_s
| PSR_f
},
19456 {"sx", PSR_s
| PSR_x
},
19457 {"sc", PSR_s
| PSR_c
},
19458 {"xf", PSR_x
| PSR_f
},
19459 {"xs", PSR_x
| PSR_s
},
19460 {"xc", PSR_x
| PSR_c
},
19461 {"cf", PSR_c
| PSR_f
},
19462 {"cs", PSR_c
| PSR_s
},
19463 {"cx", PSR_c
| PSR_x
},
19464 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19465 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19466 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19467 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19468 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19469 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19470 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19471 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19472 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19473 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19474 {"scf", PSR_s
| PSR_c
| PSR_f
},
19475 {"scx", PSR_s
| PSR_c
| PSR_x
},
19476 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19477 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19478 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19479 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19480 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19481 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19482 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19483 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19484 {"csf", PSR_c
| PSR_s
| PSR_f
},
19485 {"csx", PSR_c
| PSR_s
| PSR_x
},
19486 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19487 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19488 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19489 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19490 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19491 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19492 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19493 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19494 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19495 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19496 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19497 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19498 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19499 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19500 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19501 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19502 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19503 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19504 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19505 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19506 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19507 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19508 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19509 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19510 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19511 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19514 /* Table of V7M psr names. */
19515 static const struct asm_psr v7m_psrs
[] =
19517 {"apsr", 0x0 }, {"APSR", 0x0 },
19518 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19519 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19520 {"psr", 0x3 }, {"PSR", 0x3 },
19521 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19522 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19523 {"epsr", 0x6 }, {"EPSR", 0x6 },
19524 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19525 {"msp", 0x8 }, {"MSP", 0x8 },
19526 {"psp", 0x9 }, {"PSP", 0x9 },
19527 {"msplim", 0xa }, {"MSPLIM", 0xa },
19528 {"psplim", 0xb }, {"PSPLIM", 0xb },
19529 {"primask", 0x10}, {"PRIMASK", 0x10},
19530 {"basepri", 0x11}, {"BASEPRI", 0x11},
19531 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19532 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19533 {"control", 0x14}, {"CONTROL", 0x14},
19534 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19535 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19536 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19537 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19538 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19539 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19540 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19541 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19542 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19545 /* Table of all shift-in-operand names. */
19546 static const struct asm_shift_name shift_names
[] =
19548 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19549 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19550 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19551 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19552 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19553 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19556 /* Table of all explicit relocation names. */
19558 static struct reloc_entry reloc_names
[] =
19560 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19561 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19562 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19563 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19564 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19565 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19566 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19567 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19568 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19569 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19570 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19571 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19572 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19573 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19574 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19575 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19576 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19577 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19578 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19579 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19580 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19581 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19582 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19583 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19584 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19585 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19586 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19590 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19591 static const struct asm_cond conds
[] =
19595 {"cs", 0x2}, {"hs", 0x2},
19596 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19610 #define UL_BARRIER(L,U,CODE,FEAT) \
19611 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19612 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19614 static struct asm_barrier_opt barrier_opt_names
[] =
19616 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19617 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19618 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19619 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19620 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19621 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19622 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19623 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19624 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19625 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19626 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19627 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19628 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19629 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19630 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19631 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19636 /* Table of ARM-format instructions. */
19638 /* Macros for gluing together operand strings. N.B. In all cases
19639 other than OPS0, the trailing OP_stop comes from default
19640 zero-initialization of the unspecified elements of the array. */
19641 #define OPS0() { OP_stop, }
19642 #define OPS1(a) { OP_##a, }
19643 #define OPS2(a,b) { OP_##a,OP_##b, }
19644 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19645 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19646 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19647 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19649 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19650 This is useful when mixing operands for ARM and THUMB, i.e. using the
19651 MIX_ARM_THUMB_OPERANDS macro.
19652 In order to use these macros, prefix the number of operands with _
19654 #define OPS_1(a) { a, }
19655 #define OPS_2(a,b) { a,b, }
19656 #define OPS_3(a,b,c) { a,b,c, }
19657 #define OPS_4(a,b,c,d) { a,b,c,d, }
19658 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19659 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19661 /* These macros abstract out the exact format of the mnemonic table and
19662 save some repeated characters. */
19664 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19665 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19666 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19667 THUMB_VARIANT, do_##ae, do_##te }
19669 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19670 a T_MNEM_xyz enumerator. */
19671 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19672 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19673 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19674 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19676 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19677 infix after the third character. */
19678 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19679 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19680 THUMB_VARIANT, do_##ae, do_##te }
19681 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19682 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19683 THUMB_VARIANT, do_##ae, do_##te }
19684 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19685 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19686 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19687 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19688 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19689 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19690 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19691 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19693 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19694 field is still 0xE. Many of the Thumb variants can be executed
19695 conditionally, so this is checked separately. */
19696 #define TUE(mnem, op, top, nops, ops, ae, te) \
19697 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19698 THUMB_VARIANT, do_##ae, do_##te }
19700 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19701 Used by mnemonics that have very minimal differences in the encoding for
19702 ARM and Thumb variants and can be handled in a common function. */
19703 #define TUEc(mnem, op, top, nops, ops, en) \
19704 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19705 THUMB_VARIANT, do_##en, do_##en }
19707 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19708 condition code field. */
19709 #define TUF(mnem, op, top, nops, ops, ae, te) \
19710 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19711 THUMB_VARIANT, do_##ae, do_##te }
19713 /* ARM-only variants of all the above. */
19714 #define CE(mnem, op, nops, ops, ae) \
19715 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19717 #define C3(mnem, op, nops, ops, ae) \
19718 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19720 /* Thumb-only variants of TCE and TUE. */
19721 #define ToC(mnem, top, nops, ops, te) \
19722 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19725 #define ToU(mnem, top, nops, ops, te) \
19726 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19729 /* T_MNEM_xyz enumerator variants of ToC. */
19730 #define toC(mnem, top, nops, ops, te) \
19731 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
19734 /* T_MNEM_xyz enumerator variants of ToU. */
19735 #define toU(mnem, top, nops, ops, te) \
19736 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
19739 /* Legacy mnemonics that always have conditional infix after the third
19741 #define CL(mnem, op, nops, ops, ae) \
19742 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19743 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19745 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19746 #define cCE(mnem, op, nops, ops, ae) \
19747 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19749 /* Legacy coprocessor instructions where conditional infix and conditional
19750 suffix are ambiguous. For consistency this includes all FPA instructions,
19751 not just the potentially ambiguous ones. */
19752 #define cCL(mnem, op, nops, ops, ae) \
19753 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19754 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19756 /* Coprocessor, takes either a suffix or a position-3 infix
19757 (for an FPA corner case). */
19758 #define C3E(mnem, op, nops, ops, ae) \
19759 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19760 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19762 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19763 { m1 #m2 m3, OPS##nops ops, \
19764 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19765 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19767 #define CM(m1, m2, op, nops, ops, ae) \
19768 xCM_ (m1, , m2, op, nops, ops, ae), \
19769 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19770 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19771 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19772 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19773 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19774 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19775 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19776 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19777 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19778 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19779 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19780 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19781 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19782 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19783 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19784 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19785 xCM_ (m1, le, m2, op, nops, ops, ae), \
19786 xCM_ (m1, al, m2, op, nops, ops, ae)
19788 #define UE(mnem, op, nops, ops, ae) \
19789 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19791 #define UF(mnem, op, nops, ops, ae) \
19792 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19794 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19795 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19796 use the same encoding function for each. */
19797 #define NUF(mnem, op, nops, ops, enc) \
19798 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19799 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19801 /* Neon data processing, version which indirects through neon_enc_tab for
19802 the various overloaded versions of opcodes. */
19803 #define nUF(mnem, op, nops, ops, enc) \
19804 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19805 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19807 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19809 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19810 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19811 THUMB_VARIANT, do_##enc, do_##enc }
19813 #define NCE(mnem, op, nops, ops, enc) \
19814 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19816 #define NCEF(mnem, op, nops, ops, enc) \
19817 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19819 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19820 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19821 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19822 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19824 #define nCE(mnem, op, nops, ops, enc) \
19825 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19827 #define nCEF(mnem, op, nops, ops, enc) \
19828 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19832 static const struct asm_opcode insns
[] =
19834 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19835 #define THUMB_VARIANT & arm_ext_v4t
19836 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19837 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19838 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19839 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19840 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19841 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19842 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19843 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19844 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19845 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19846 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19847 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19848 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19849 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19850 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19851 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19853 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19854 for setting PSR flag bits. They are obsolete in V6 and do not
19855 have Thumb equivalents. */
19856 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19857 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19858 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19859 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19860 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19861 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19862 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19863 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19864 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19866 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19867 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19868 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19869 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19871 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19872 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19873 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19875 OP_ADDRGLDR
),ldst
, t_ldst
),
19876 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19878 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19879 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19880 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19881 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19882 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19883 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19885 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19886 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19889 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19890 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19891 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19892 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19894 /* Thumb-compatibility pseudo ops. */
19895 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19896 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19897 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19898 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19899 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19900 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19901 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19902 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19903 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19904 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19905 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19906 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19908 /* These may simplify to neg. */
19909 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19910 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19912 #undef THUMB_VARIANT
19913 #define THUMB_VARIANT & arm_ext_os
19915 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19916 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19918 #undef THUMB_VARIANT
19919 #define THUMB_VARIANT & arm_ext_v6
19921 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19923 /* V1 instructions with no Thumb analogue prior to V6T2. */
19924 #undef THUMB_VARIANT
19925 #define THUMB_VARIANT & arm_ext_v6t2
19927 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19928 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19929 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19931 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19932 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19933 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19934 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19936 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19937 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19939 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19940 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19942 /* V1 instructions with no Thumb analogue at all. */
19943 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19944 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19946 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19947 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19948 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19949 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19950 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19951 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19952 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19953 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19956 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19957 #undef THUMB_VARIANT
19958 #define THUMB_VARIANT & arm_ext_v4t
19960 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19961 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19963 #undef THUMB_VARIANT
19964 #define THUMB_VARIANT & arm_ext_v6t2
19966 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19967 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19969 /* Generic coprocessor instructions. */
19970 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19971 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19972 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19973 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19974 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19975 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19976 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19979 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19981 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19982 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19985 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19986 #undef THUMB_VARIANT
19987 #define THUMB_VARIANT & arm_ext_msr
19989 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19990 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19993 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19994 #undef THUMB_VARIANT
19995 #define THUMB_VARIANT & arm_ext_v6t2
19997 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19998 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19999 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20000 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20001 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20002 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20003 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20004 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20007 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
20008 #undef THUMB_VARIANT
20009 #define THUMB_VARIANT & arm_ext_v4t
20011 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20012 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20013 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20014 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20015 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20016 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20019 #define ARM_VARIANT & arm_ext_v4t_5
20021 /* ARM Architecture 4T. */
20022 /* Note: bx (and blx) are required on V5, even if the processor does
20023 not support Thumb. */
20024 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
20027 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
20028 #undef THUMB_VARIANT
20029 #define THUMB_VARIANT & arm_ext_v5t
20031 /* Note: blx has 2 variants; the .value coded here is for
20032 BLX(2). Only this variant has conditional execution. */
20033 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
20034 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
20036 #undef THUMB_VARIANT
20037 #define THUMB_VARIANT & arm_ext_v6t2
20039 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
20040 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20041 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20042 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20043 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20044 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
20045 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20046 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20049 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
20050 #undef THUMB_VARIANT
20051 #define THUMB_VARIANT & arm_ext_v5exp
20053 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20054 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20055 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20056 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20058 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20059 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20061 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20062 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20063 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20064 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20066 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20067 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20068 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20069 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20071 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20072 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20074 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20075 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20076 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20077 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20080 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
20081 #undef THUMB_VARIANT
20082 #define THUMB_VARIANT & arm_ext_v6t2
20084 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
20085 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
20087 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
20088 ADDRGLDRS
), ldrd
, t_ldstd
),
20090 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20091 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20094 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
20096 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
20099 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
20100 #undef THUMB_VARIANT
20101 #define THUMB_VARIANT & arm_ext_v6
20103 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20104 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20105 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20106 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20107 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20108 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20109 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20110 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20111 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20112 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
20114 #undef THUMB_VARIANT
20115 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20117 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
20118 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20120 #undef THUMB_VARIANT
20121 #define THUMB_VARIANT & arm_ext_v6t2
20123 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20124 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20126 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
20127 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
20129 /* ARM V6 not included in V7M. */
20130 #undef THUMB_VARIANT
20131 #define THUMB_VARIANT & arm_ext_v6_notm
20132 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20133 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20134 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
20135 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
20136 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20137 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20138 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
20139 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20140 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
20141 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20142 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20143 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20144 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20145 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20146 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
20147 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
20148 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20149 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20150 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
20152 /* ARM V6 not included in V7M (eg. integer SIMD). */
20153 #undef THUMB_VARIANT
20154 #define THUMB_VARIANT & arm_ext_v6_dsp
20155 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
20156 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
20157 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20158 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20159 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20160 /* Old name for QASX. */
20161 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20162 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20163 /* Old name for QSAX. */
20164 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20165 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20166 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20167 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20168 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20169 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20170 /* Old name for SASX. */
20171 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20172 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20173 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20174 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20175 /* Old name for SHASX. */
20176 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20177 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20178 /* Old name for SHSAX. */
20179 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20180 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20181 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20182 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20183 /* Old name for SSAX. */
20184 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20185 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20186 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20187 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20188 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20189 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20190 /* Old name for UASX. */
20191 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20192 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20193 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20194 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20195 /* Old name for UHASX. */
20196 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20197 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20198 /* Old name for UHSAX. */
20199 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20200 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20201 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20202 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20203 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20204 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20205 /* Old name for UQASX. */
20206 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20207 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20208 /* Old name for UQSAX. */
20209 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20210 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20211 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20212 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20213 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20214 /* Old name for USAX. */
20215 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20216 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20217 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20218 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20219 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20220 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20221 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20222 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20223 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20224 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20225 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20226 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20227 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20228 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20229 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20230 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20231 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20232 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20233 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20234 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20235 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20236 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20237 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20238 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20239 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20240 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20241 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20242 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20243 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20244 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
20245 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
20246 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20247 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20248 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20251 #define ARM_VARIANT & arm_ext_v6k_v6t2
20252 #undef THUMB_VARIANT
20253 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20255 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20256 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20257 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20258 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20260 #undef THUMB_VARIANT
20261 #define THUMB_VARIANT & arm_ext_v6_notm
20262 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20264 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20265 RRnpcb
), strexd
, t_strexd
),
20267 #undef THUMB_VARIANT
20268 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20269 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20271 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20273 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20275 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20277 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20280 #define ARM_VARIANT & arm_ext_sec
20281 #undef THUMB_VARIANT
20282 #define THUMB_VARIANT & arm_ext_sec
20284 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20287 #define ARM_VARIANT & arm_ext_virt
20288 #undef THUMB_VARIANT
20289 #define THUMB_VARIANT & arm_ext_virt
20291 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20292 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20295 #define ARM_VARIANT & arm_ext_pan
20296 #undef THUMB_VARIANT
20297 #define THUMB_VARIANT & arm_ext_pan
20299 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20302 #define ARM_VARIANT & arm_ext_v6t2
20303 #undef THUMB_VARIANT
20304 #define THUMB_VARIANT & arm_ext_v6t2
20306 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20307 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20308 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20309 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20311 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20312 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20314 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20315 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20316 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20317 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20320 #define ARM_VARIANT & arm_ext_v3
20321 #undef THUMB_VARIANT
20322 #define THUMB_VARIANT & arm_ext_v6t2
20324 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20325 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20326 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20329 #define ARM_VARIANT & arm_ext_v6t2
20330 #undef THUMB_VARIANT
20331 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20332 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20333 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20335 /* Thumb-only instructions. */
20337 #define ARM_VARIANT NULL
20338 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20339 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20341 /* ARM does not really have an IT instruction, so always allow it.
20342 The opcode is copied from Thumb in order to allow warnings in
20343 -mimplicit-it=[never | arm] modes. */
20345 #define ARM_VARIANT & arm_ext_v1
20346 #undef THUMB_VARIANT
20347 #define THUMB_VARIANT & arm_ext_v6t2
20349 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20350 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20351 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20352 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20353 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20354 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20355 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20356 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20357 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20358 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20359 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20360 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20361 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20362 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20363 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20364 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20365 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20366 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20368 /* Thumb2 only instructions. */
20370 #define ARM_VARIANT NULL
20372 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20373 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20374 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20375 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20376 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20377 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20379 /* Hardware division instructions. */
20381 #define ARM_VARIANT & arm_ext_adiv
20382 #undef THUMB_VARIANT
20383 #define THUMB_VARIANT & arm_ext_div
20385 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20386 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20388 /* ARM V6M/V7 instructions. */
20390 #define ARM_VARIANT & arm_ext_barrier
20391 #undef THUMB_VARIANT
20392 #define THUMB_VARIANT & arm_ext_barrier
20394 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20395 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20396 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20398 /* ARM V7 instructions. */
20400 #define ARM_VARIANT & arm_ext_v7
20401 #undef THUMB_VARIANT
20402 #define THUMB_VARIANT & arm_ext_v7
20404 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20405 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20408 #define ARM_VARIANT & arm_ext_mp
20409 #undef THUMB_VARIANT
20410 #define THUMB_VARIANT & arm_ext_mp
20412 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20414 /* AArchv8 instructions. */
20416 #define ARM_VARIANT & arm_ext_v8
20418 /* Instructions shared between armv8-a and armv8-m. */
20419 #undef THUMB_VARIANT
20420 #define THUMB_VARIANT & arm_ext_atomics
20422 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20423 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20424 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20425 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20426 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20427 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20428 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20429 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20430 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20431 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20433 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20435 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20437 #undef THUMB_VARIANT
20438 #define THUMB_VARIANT & arm_ext_v8
20440 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20441 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20443 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20446 /* Defined in V8 but is in undefined encoding space for earlier
20447 architectures. However earlier architectures are required to treat
20448 this instuction as a semihosting trap as well. Hence while not explicitly
20449 defined as such, it is in fact correct to define the instruction for all
20451 #undef THUMB_VARIANT
20452 #define THUMB_VARIANT & arm_ext_v1
20454 #define ARM_VARIANT & arm_ext_v1
20455 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20457 /* ARMv8 T32 only. */
20459 #define ARM_VARIANT NULL
20460 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20461 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20462 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20464 /* FP for ARMv8. */
20466 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20467 #undef THUMB_VARIANT
20468 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20470 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20471 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20472 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20473 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20474 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20475 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20476 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20477 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20478 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20479 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20480 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20481 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20482 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20483 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20484 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20485 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20486 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20488 /* Crypto v1 extensions. */
20490 #define ARM_VARIANT & fpu_crypto_ext_armv8
20491 #undef THUMB_VARIANT
20492 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20494 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20495 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20496 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20497 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20498 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20499 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20500 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20501 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20502 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20503 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20504 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20505 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20506 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20507 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20510 #define ARM_VARIANT & crc_ext_armv8
20511 #undef THUMB_VARIANT
20512 #define THUMB_VARIANT & crc_ext_armv8
20513 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20514 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20515 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20516 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20517 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20518 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20520 /* ARMv8.2 RAS extension. */
20522 #define ARM_VARIANT & arm_ext_ras
20523 #undef THUMB_VARIANT
20524 #define THUMB_VARIANT & arm_ext_ras
20525 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20528 #define ARM_VARIANT & arm_ext_v8_3
20529 #undef THUMB_VARIANT
20530 #define THUMB_VARIANT & arm_ext_v8_3
20531 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20532 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20533 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20536 #define ARM_VARIANT & fpu_neon_ext_dotprod
20537 #undef THUMB_VARIANT
20538 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20539 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20540 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20543 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20544 #undef THUMB_VARIANT
20545 #define THUMB_VARIANT NULL
20547 cCE("wfs", e200110
, 1, (RR
), rd
),
20548 cCE("rfs", e300110
, 1, (RR
), rd
),
20549 cCE("wfc", e400110
, 1, (RR
), rd
),
20550 cCE("rfc", e500110
, 1, (RR
), rd
),
20552 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20553 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20554 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20555 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20557 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20558 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20559 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20560 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20562 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20563 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20564 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20565 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20566 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20567 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20568 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20569 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20570 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20571 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20572 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20573 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20575 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20576 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20577 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20578 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20579 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20580 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20581 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20582 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20583 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20584 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20585 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20586 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20588 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20589 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20590 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20591 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20592 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20593 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20594 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20595 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20596 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20597 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20598 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20599 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20601 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20602 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20603 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20604 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20605 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20606 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20607 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20608 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20609 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20610 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20611 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20612 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20614 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20615 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20616 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20617 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20618 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20619 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20620 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20621 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20622 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20623 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20624 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20625 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20627 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20628 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20629 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20630 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20631 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20632 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20633 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20634 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20635 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20636 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20637 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20638 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20640 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20641 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20642 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20643 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20644 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20645 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20646 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20647 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20648 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20649 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20650 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20651 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20653 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20654 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20655 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20656 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20657 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20658 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20659 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20660 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20661 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20662 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20663 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20664 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20666 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20667 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20668 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20669 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20670 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20671 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20672 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20673 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20674 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20675 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20676 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20677 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20679 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20680 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20681 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20682 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20683 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20684 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20685 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20686 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20687 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20688 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20689 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20690 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20692 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20693 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20694 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20695 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20696 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20697 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20698 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20699 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20700 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20701 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20702 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20703 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20705 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20706 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20707 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20708 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20709 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20710 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20711 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20712 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20713 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20714 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20715 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20716 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20718 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20719 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20720 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20721 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20722 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20723 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20724 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20725 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20726 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20727 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20728 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20729 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20731 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20732 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20733 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20734 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20735 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20736 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20737 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20738 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20739 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20740 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20741 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20742 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20744 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20745 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20746 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20747 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20748 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20749 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20750 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20751 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20752 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20753 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20754 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20755 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20757 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20758 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20759 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20760 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20761 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20762 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20763 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20764 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20765 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20766 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20767 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20768 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20770 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20771 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20772 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20773 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20774 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20775 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20776 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20777 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20778 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20779 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20780 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20781 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20783 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20784 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20785 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20786 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20787 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20788 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20789 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20790 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20791 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20792 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20793 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20794 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20796 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20797 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20798 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20799 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20800 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20801 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20802 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20803 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20804 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20805 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20806 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20807 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20809 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20810 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20811 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20812 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20813 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20814 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20815 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20816 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20817 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20818 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20819 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20820 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20822 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20823 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20824 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20825 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20826 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20827 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20828 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20829 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20830 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20831 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20832 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20833 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20835 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20836 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20837 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20838 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20839 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20840 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20841 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20842 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20843 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20844 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20845 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20846 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20848 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20849 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20850 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20851 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20852 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20853 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20854 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20855 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20856 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20857 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20858 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20859 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20861 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20862 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20863 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20864 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20865 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20866 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20867 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20868 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20869 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20870 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20871 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20872 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20874 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20875 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20876 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20877 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20878 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20879 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20880 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20881 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20882 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20883 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20884 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20885 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20887 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20888 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20889 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20890 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20891 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20892 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20893 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20894 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20895 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20896 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20897 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20898 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20900 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20901 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20902 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20903 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20904 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20905 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20906 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20907 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20908 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20909 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20910 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20911 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20913 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20914 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20915 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20916 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20917 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20918 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20919 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20920 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20921 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20922 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20923 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20924 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20926 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20927 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20928 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20929 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20930 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20931 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20932 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20933 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20934 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20935 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20936 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20937 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20939 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20940 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20941 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20942 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20944 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20945 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20946 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20947 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20948 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20949 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20950 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20951 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20952 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20953 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20954 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20955 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20957 /* The implementation of the FIX instruction is broken on some
20958 assemblers, in that it accepts a precision specifier as well as a
20959 rounding specifier, despite the fact that this is meaningless.
20960 To be more compatible, we accept it as well, though of course it
20961 does not set any bits. */
20962 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20963 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20964 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20965 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20966 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20967 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20968 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20969 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20970 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20971 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20972 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20973 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20974 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20976 /* Instructions that were new with the real FPA, call them V2. */
20978 #define ARM_VARIANT & fpu_fpa_ext_v2
20980 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20981 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20982 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20983 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20984 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20985 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20988 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20990 /* Moves and type conversions. */
20991 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20992 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20993 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20994 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20995 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20996 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20997 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20998 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20999 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21000 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21001 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21002 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21003 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
21004 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
21006 /* Memory operations. */
21007 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21008 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21009 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21010 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21011 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21012 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21013 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21014 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21015 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21016 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21017 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21018 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21019 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21020 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21021 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21022 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21023 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21024 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21026 /* Monadic operations. */
21027 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21028 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21029 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21031 /* Dyadic operations. */
21032 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21033 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21034 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21035 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21036 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21037 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21038 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21039 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21040 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21043 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21044 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
21045 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21046 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
21048 /* Double precision load/store are still present on single precision
21049 implementations. */
21050 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21051 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21052 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21053 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21054 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21055 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21056 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21057 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21058 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21059 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21062 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
21064 /* Moves and type conversions. */
21065 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21066 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21067 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21068 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21069 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21070 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21071 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21072 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21073 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21074 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21075 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21076 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21077 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21079 /* Monadic operations. */
21080 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21081 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21082 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21084 /* Dyadic operations. */
21085 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21086 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21087 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21088 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21089 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21090 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21091 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21092 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21093 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21096 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21097 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
21098 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21099 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
21102 #define ARM_VARIANT & fpu_vfp_ext_v2
21104 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
21105 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
21106 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
21107 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
21109 /* Instructions which may belong to either the Neon or VFP instruction sets.
21110 Individual encoder functions perform additional architecture checks. */
21112 #define ARM_VARIANT & fpu_vfp_ext_v1xd
21113 #undef THUMB_VARIANT
21114 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
21116 /* These mnemonics are unique to VFP. */
21117 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
21118 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
21119 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21120 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21121 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21122 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21123 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21124 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
21125 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
21126 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
21128 /* Mnemonics shared by Neon and VFP. */
21129 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
21130 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21131 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21133 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21134 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21136 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21137 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21139 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21140 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21141 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21142 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21143 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21144 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21145 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21146 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21148 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
21149 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
21150 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
21151 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
21154 /* NOTE: All VMOV encoding is special-cased! */
21155 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
21156 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
21159 #define ARM_VARIANT & arm_ext_fp16
21160 #undef THUMB_VARIANT
21161 #define THUMB_VARIANT & arm_ext_fp16
21162 /* New instructions added from v8.2, allowing the extraction and insertion of
21163 the upper 16 bits of a 32-bit vector register. */
21164 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
21165 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
21167 /* New backported fma/fms instructions optional in v8.2. */
21168 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
21169 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
21171 #undef THUMB_VARIANT
21172 #define THUMB_VARIANT & fpu_neon_ext_v1
21174 #define ARM_VARIANT & fpu_neon_ext_v1
21176 /* Data processing with three registers of the same length. */
21177 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
21178 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
21179 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
21180 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21181 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21182 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21183 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21184 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21185 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21186 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
21187 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21188 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21189 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21190 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21191 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21192 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21193 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21194 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21195 /* If not immediate, fall back to neon_dyadic_i64_su.
21196 shl_imm should accept I8 I16 I32 I64,
21197 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21198 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
21199 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
21200 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
21201 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
21202 /* Logic ops, types optional & ignored. */
21203 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21204 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21205 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21206 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21207 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21208 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21209 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21210 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21211 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
21212 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
21213 /* Bitfield ops, untyped. */
21214 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21215 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21216 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21217 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21218 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21219 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21220 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21221 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21222 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21223 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21224 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21225 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21226 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21227 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
21228 back to neon_dyadic_if_su. */
21229 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21230 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21231 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21232 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21233 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21234 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21235 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21236 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21237 /* Comparison. Type I8 I16 I32 F32. */
21238 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
21239 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
21240 /* As above, D registers only. */
21241 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21242 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21243 /* Int and float variants, signedness unimportant. */
21244 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21245 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21246 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
21247 /* Add/sub take types I8 I16 I32 I64 F32. */
21248 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21249 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21250 /* vtst takes sizes 8, 16, 32. */
21251 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21252 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21253 /* VMUL takes I8 I16 I32 F32 P8. */
21254 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21255 /* VQD{R}MULH takes S16 S32. */
21256 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21257 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21258 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21259 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21260 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21261 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21262 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21263 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21264 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21265 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21266 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21267 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21268 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21269 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21270 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21271 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21272 /* ARM v8.1 extension. */
21273 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21274 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21275 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21276 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21278 /* Two address, int/float. Types S8 S16 S32 F32. */
21279 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21280 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21282 /* Data processing with two registers and a shift amount. */
21283 /* Right shifts, and variants with rounding.
21284 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21285 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21286 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21287 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21288 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21289 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21290 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21291 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21292 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21293 /* Shift and insert. Sizes accepted 8 16 32 64. */
21294 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21295 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21296 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21297 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21298 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21299 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21300 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21301 /* Right shift immediate, saturating & narrowing, with rounding variants.
21302 Types accepted S16 S32 S64 U16 U32 U64. */
21303 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21304 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21305 /* As above, unsigned. Types accepted S16 S32 S64. */
21306 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21307 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21308 /* Right shift narrowing. Types accepted I16 I32 I64. */
21309 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21310 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21311 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21312 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21313 /* CVT with optional immediate for fixed-point variant. */
21314 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21316 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21317 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21319 /* Data processing, three registers of different lengths. */
21320 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21321 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21322 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21323 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21324 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21325 /* If not scalar, fall back to neon_dyadic_long.
21326 Vector types as above, scalar types S16 S32 U16 U32. */
21327 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21328 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21329 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21330 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21331 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21332 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21333 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21334 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21335 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21336 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21337 /* Saturating doubling multiplies. Types S16 S32. */
21338 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21339 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21340 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21341 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21342 S16 S32 U16 U32. */
21343 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21345 /* Extract. Size 8. */
21346 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21347 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21349 /* Two registers, miscellaneous. */
21350 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21351 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21352 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21353 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21354 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21355 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21356 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21357 /* Vector replicate. Sizes 8 16 32. */
21358 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21359 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21360 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21361 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21362 /* VMOVN. Types I16 I32 I64. */
21363 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21364 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21365 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21366 /* VQMOVUN. Types S16 S32 S64. */
21367 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21368 /* VZIP / VUZP. Sizes 8 16 32. */
21369 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21370 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21371 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21372 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21373 /* VQABS / VQNEG. Types S8 S16 S32. */
21374 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21375 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21376 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21377 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21378 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21379 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21380 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21381 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21382 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21383 /* Reciprocal estimates. Types U32 F16 F32. */
21384 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21385 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21386 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21387 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21388 /* VCLS. Types S8 S16 S32. */
21389 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21390 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21391 /* VCLZ. Types I8 I16 I32. */
21392 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21393 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21394 /* VCNT. Size 8. */
21395 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21396 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21397 /* Two address, untyped. */
21398 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21399 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21400 /* VTRN. Sizes 8 16 32. */
21401 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21402 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21404 /* Table lookup. Size 8. */
21405 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21406 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21408 #undef THUMB_VARIANT
21409 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21411 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21413 /* Neon element/structure load/store. */
21414 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21415 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21416 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21417 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21418 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21419 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21420 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21421 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21423 #undef THUMB_VARIANT
21424 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21426 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21427 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21428 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21429 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21430 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21431 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21432 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21433 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21434 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21435 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21437 #undef THUMB_VARIANT
21438 #define THUMB_VARIANT & fpu_vfp_ext_v3
21440 #define ARM_VARIANT & fpu_vfp_ext_v3
21442 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21443 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21444 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21445 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21446 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21447 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21448 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21449 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21450 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21453 #define ARM_VARIANT & fpu_vfp_ext_fma
21454 #undef THUMB_VARIANT
21455 #define THUMB_VARIANT & fpu_vfp_ext_fma
21456 /* Mnemonics shared by Neon and VFP. These are included in the
21457 VFP FMA variant; NEON and VFP FMA always includes the NEON
21458 FMA instructions. */
21459 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21460 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21461 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21462 the v form should always be used. */
21463 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21464 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21465 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21466 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21467 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21468 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21470 #undef THUMB_VARIANT
21472 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21474 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21475 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21476 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21477 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21478 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21479 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21480 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21481 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21484 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21486 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21487 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21488 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21489 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21490 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21491 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21492 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21493 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21494 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21495 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21496 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21497 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21498 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21499 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21500 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21501 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21502 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21503 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21504 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21505 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21506 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21507 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21508 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21509 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21510 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21511 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21512 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21513 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21514 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21515 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21516 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21517 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21518 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21519 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21520 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21521 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21522 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21523 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21524 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21525 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21526 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21527 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21528 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21529 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21530 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21531 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21532 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21533 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21534 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21535 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21536 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21537 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21538 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21539 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21540 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21541 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21542 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21543 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21544 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21545 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21546 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21547 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21548 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21549 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21550 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21551 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21552 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21553 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21554 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21555 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21556 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21557 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21558 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21559 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21560 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21561 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21562 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21563 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21564 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21565 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21566 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21567 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21568 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21569 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21570 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21571 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21572 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21573 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21574 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21575 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21576 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21577 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21578 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21579 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21580 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21581 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21582 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21583 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21584 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21585 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21586 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21587 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21588 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21589 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21590 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21591 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21592 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21593 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21594 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21595 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21596 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21597 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21598 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21599 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21600 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21601 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21602 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21603 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21604 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21605 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21606 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21607 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21608 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21609 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21610 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21611 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21612 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21613 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21614 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21615 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21616 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21617 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21618 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21619 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21620 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21621 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21622 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21623 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21624 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21625 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21626 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21627 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21628 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21629 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21630 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21631 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21632 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21633 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21634 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21635 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21636 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21637 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21638 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21639 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21640 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21641 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21642 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21643 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21644 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21645 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21646 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21647 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21650 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21652 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21653 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21654 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21655 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21656 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21657 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21658 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21659 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21660 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21661 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21662 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21663 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21664 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21665 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21666 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21667 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21668 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21669 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21670 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21671 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21672 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21673 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21674 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21675 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21676 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21677 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21678 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21679 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21680 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21681 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21682 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21683 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21684 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21685 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21686 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21687 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21688 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21689 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21690 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21691 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21692 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21693 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21694 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21695 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21696 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21697 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21698 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21699 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21700 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21701 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21702 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21703 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21704 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21705 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21706 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21707 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21708 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21711 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21713 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21714 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21715 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21716 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21717 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21718 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21719 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21720 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21721 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21722 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21723 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21724 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21725 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21726 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21727 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21728 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21729 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21730 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21731 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21732 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21733 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21734 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21735 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21736 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21737 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21738 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21739 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21740 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21741 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21742 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21743 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21744 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21745 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21746 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21747 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21748 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21749 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21750 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21751 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21752 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21753 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21754 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21755 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21756 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21757 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21758 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21759 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21760 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21761 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21762 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21763 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21764 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21765 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21766 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21767 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21768 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21769 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21770 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21771 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21772 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21773 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21774 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21775 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21776 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21777 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21778 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21779 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21780 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21781 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21782 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21783 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21784 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21785 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21786 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21787 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21788 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21790 /* ARMv8.5-A instructions. */
21792 #define ARM_VARIANT & arm_ext_sb
21793 #undef THUMB_VARIANT
21794 #define THUMB_VARIANT & arm_ext_sb
21795 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21798 #define ARM_VARIANT & arm_ext_predres
21799 #undef THUMB_VARIANT
21800 #define THUMB_VARIANT & arm_ext_predres
21801 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21802 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21803 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21805 /* ARMv8-M instructions. */
21807 #define ARM_VARIANT NULL
21808 #undef THUMB_VARIANT
21809 #define THUMB_VARIANT & arm_ext_v8m
21810 ToU("sg", e97fe97f
, 0, (), noargs
),
21811 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21812 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21813 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21814 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21815 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21816 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21818 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21819 instructions behave as nop if no VFP is present. */
21820 #undef THUMB_VARIANT
21821 #define THUMB_VARIANT & arm_ext_v8m_main
21822 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21823 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21825 /* Armv8.1-M Mainline instructions. */
21826 #undef THUMB_VARIANT
21827 #define THUMB_VARIANT & arm_ext_v8_1m_main
21828 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
21829 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
21830 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21831 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
21832 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21834 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
21835 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
21836 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
21839 #undef THUMB_VARIANT
21871 /* MD interface: bits in the object file. */
21873 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21874 for use in the a.out file, and stores them in the array pointed to by buf.
21875 This knows about the endian-ness of the target machine and does
21876 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21877 2 (short) and 4 (long) Floating numbers are put out as a series of
21878 LITTLENUMS (shorts, here at least). */
21881 md_number_to_chars (char * buf
, valueT val
, int n
)
21883 if (target_big_endian
)
21884 number_to_chars_bigendian (buf
, val
, n
);
21886 number_to_chars_littleendian (buf
, val
, n
);
21890 md_chars_to_number (char * buf
, int n
)
21893 unsigned char * where
= (unsigned char *) buf
;
21895 if (target_big_endian
)
21900 result
|= (*where
++ & 255);
21908 result
|= (where
[n
] & 255);
21915 /* MD interface: Sections. */
21917 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21918 that an rs_machine_dependent frag may reach. */
21921 arm_frag_max_var (fragS
*fragp
)
21923 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21924 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21926 Note that we generate relaxable instructions even for cases that don't
21927 really need it, like an immediate that's a trivial constant. So we're
21928 overestimating the instruction size for some of those cases. Rather
21929 than putting more intelligence here, it would probably be better to
21930 avoid generating a relaxation frag in the first place when it can be
21931 determined up front that a short instruction will suffice. */
21933 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21937 /* Estimate the size of a frag before relaxing. Assume everything fits in
21941 md_estimate_size_before_relax (fragS
* fragp
,
21942 segT segtype ATTRIBUTE_UNUSED
)
21948 /* Convert a machine dependent frag. */
21951 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21953 unsigned long insn
;
21954 unsigned long old_op
;
21962 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21964 old_op
= bfd_get_16(abfd
, buf
);
21965 if (fragp
->fr_symbol
)
21967 exp
.X_op
= O_symbol
;
21968 exp
.X_add_symbol
= fragp
->fr_symbol
;
21972 exp
.X_op
= O_constant
;
21974 exp
.X_add_number
= fragp
->fr_offset
;
21975 opcode
= fragp
->fr_subtype
;
21978 case T_MNEM_ldr_pc
:
21979 case T_MNEM_ldr_pc2
:
21980 case T_MNEM_ldr_sp
:
21981 case T_MNEM_str_sp
:
21988 if (fragp
->fr_var
== 4)
21990 insn
= THUMB_OP32 (opcode
);
21991 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21993 insn
|= (old_op
& 0x700) << 4;
21997 insn
|= (old_op
& 7) << 12;
21998 insn
|= (old_op
& 0x38) << 13;
22000 insn
|= 0x00000c00;
22001 put_thumb32_insn (buf
, insn
);
22002 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
22006 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
22008 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
22011 if (fragp
->fr_var
== 4)
22013 insn
= THUMB_OP32 (opcode
);
22014 insn
|= (old_op
& 0xf0) << 4;
22015 put_thumb32_insn (buf
, insn
);
22016 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
22020 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22021 exp
.X_add_number
-= 4;
22029 if (fragp
->fr_var
== 4)
22031 int r0off
= (opcode
== T_MNEM_mov
22032 || opcode
== T_MNEM_movs
) ? 0 : 8;
22033 insn
= THUMB_OP32 (opcode
);
22034 insn
= (insn
& 0xe1ffffff) | 0x10000000;
22035 insn
|= (old_op
& 0x700) << r0off
;
22036 put_thumb32_insn (buf
, insn
);
22037 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22041 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
22046 if (fragp
->fr_var
== 4)
22048 insn
= THUMB_OP32(opcode
);
22049 put_thumb32_insn (buf
, insn
);
22050 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
22053 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
22057 if (fragp
->fr_var
== 4)
22059 insn
= THUMB_OP32(opcode
);
22060 insn
|= (old_op
& 0xf00) << 14;
22061 put_thumb32_insn (buf
, insn
);
22062 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
22065 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
22068 case T_MNEM_add_sp
:
22069 case T_MNEM_add_pc
:
22070 case T_MNEM_inc_sp
:
22071 case T_MNEM_dec_sp
:
22072 if (fragp
->fr_var
== 4)
22074 /* ??? Choose between add and addw. */
22075 insn
= THUMB_OP32 (opcode
);
22076 insn
|= (old_op
& 0xf0) << 4;
22077 put_thumb32_insn (buf
, insn
);
22078 if (opcode
== T_MNEM_add_pc
)
22079 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
22081 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22084 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22092 if (fragp
->fr_var
== 4)
22094 insn
= THUMB_OP32 (opcode
);
22095 insn
|= (old_op
& 0xf0) << 4;
22096 insn
|= (old_op
& 0xf) << 16;
22097 put_thumb32_insn (buf
, insn
);
22098 if (insn
& (1 << 20))
22099 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22101 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22104 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22110 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
22111 (enum bfd_reloc_code_real
) reloc_type
);
22112 fixp
->fx_file
= fragp
->fr_file
;
22113 fixp
->fx_line
= fragp
->fr_line
;
22114 fragp
->fr_fix
+= fragp
->fr_var
;
22116 /* Set whether we use thumb-2 ISA based on final relaxation results. */
22117 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
22118 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
22119 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
22122 /* Return the size of a relaxable immediate operand instruction.
22123 SHIFT and SIZE specify the form of the allowable immediate. */
22125 relax_immediate (fragS
*fragp
, int size
, int shift
)
22131 /* ??? Should be able to do better than this. */
22132 if (fragp
->fr_symbol
)
22135 low
= (1 << shift
) - 1;
22136 mask
= (1 << (shift
+ size
)) - (1 << shift
);
22137 offset
= fragp
->fr_offset
;
22138 /* Force misaligned offsets to 32-bit variant. */
22141 if (offset
& ~mask
)
22146 /* Get the address of a symbol during relaxation. */
22148 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
22154 sym
= fragp
->fr_symbol
;
22155 sym_frag
= symbol_get_frag (sym
);
22156 know (S_GET_SEGMENT (sym
) != absolute_section
22157 || sym_frag
== &zero_address_frag
);
22158 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
22160 /* If frag has yet to be reached on this pass, assume it will
22161 move by STRETCH just as we did. If this is not so, it will
22162 be because some frag between grows, and that will force
22166 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
22170 /* Adjust stretch for any alignment frag. Note that if have
22171 been expanding the earlier code, the symbol may be
22172 defined in what appears to be an earlier frag. FIXME:
22173 This doesn't handle the fr_subtype field, which specifies
22174 a maximum number of bytes to skip when doing an
22176 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
22178 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
22181 stretch
= - ((- stretch
)
22182 & ~ ((1 << (int) f
->fr_offset
) - 1));
22184 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
22196 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
22199 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
22204 /* Assume worst case for symbols not known to be in the same section. */
22205 if (fragp
->fr_symbol
== NULL
22206 || !S_IS_DEFINED (fragp
->fr_symbol
)
22207 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22208 || S_IS_WEAK (fragp
->fr_symbol
))
22211 val
= relaxed_symbol_addr (fragp
, stretch
);
22212 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
22213 addr
= (addr
+ 4) & ~3;
22214 /* Force misaligned targets to 32-bit variant. */
22218 if (val
< 0 || val
> 1020)
22223 /* Return the size of a relaxable add/sub immediate instruction. */
22225 relax_addsub (fragS
*fragp
, asection
*sec
)
22230 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22231 op
= bfd_get_16(sec
->owner
, buf
);
22232 if ((op
& 0xf) == ((op
>> 4) & 0xf))
22233 return relax_immediate (fragp
, 8, 0);
22235 return relax_immediate (fragp
, 3, 0);
22238 /* Return TRUE iff the definition of symbol S could be pre-empted
22239 (overridden) at link or load time. */
22241 symbol_preemptible (symbolS
*s
)
22243 /* Weak symbols can always be pre-empted. */
22247 /* Non-global symbols cannot be pre-empted. */
22248 if (! S_IS_EXTERNAL (s
))
22252 /* In ELF, a global symbol can be marked protected, or private. In that
22253 case it can't be pre-empted (other definitions in the same link unit
22254 would violate the ODR). */
22255 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
22259 /* Other global symbols might be pre-empted. */
22263 /* Return the size of a relaxable branch instruction. BITS is the
22264 size of the offset field in the narrow instruction. */
22267 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22273 /* Assume worst case for symbols not known to be in the same section. */
22274 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22275 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22276 || S_IS_WEAK (fragp
->fr_symbol
))
22280 /* A branch to a function in ARM state will require interworking. */
22281 if (S_IS_DEFINED (fragp
->fr_symbol
)
22282 && ARM_IS_FUNC (fragp
->fr_symbol
))
22286 if (symbol_preemptible (fragp
->fr_symbol
))
22289 val
= relaxed_symbol_addr (fragp
, stretch
);
22290 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22293 /* Offset is a signed value *2 */
22295 if (val
>= limit
|| val
< -limit
)
22301 /* Relax a machine dependent frag. This returns the amount by which
22302 the current size of the frag should change. */
22305 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22310 oldsize
= fragp
->fr_var
;
22311 switch (fragp
->fr_subtype
)
22313 case T_MNEM_ldr_pc2
:
22314 newsize
= relax_adr (fragp
, sec
, stretch
);
22316 case T_MNEM_ldr_pc
:
22317 case T_MNEM_ldr_sp
:
22318 case T_MNEM_str_sp
:
22319 newsize
= relax_immediate (fragp
, 8, 2);
22323 newsize
= relax_immediate (fragp
, 5, 2);
22327 newsize
= relax_immediate (fragp
, 5, 1);
22331 newsize
= relax_immediate (fragp
, 5, 0);
22334 newsize
= relax_adr (fragp
, sec
, stretch
);
22340 newsize
= relax_immediate (fragp
, 8, 0);
22343 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22346 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22348 case T_MNEM_add_sp
:
22349 case T_MNEM_add_pc
:
22350 newsize
= relax_immediate (fragp
, 8, 2);
22352 case T_MNEM_inc_sp
:
22353 case T_MNEM_dec_sp
:
22354 newsize
= relax_immediate (fragp
, 7, 2);
22360 newsize
= relax_addsub (fragp
, sec
);
22366 fragp
->fr_var
= newsize
;
22367 /* Freeze wide instructions that are at or before the same location as
22368 in the previous pass. This avoids infinite loops.
22369 Don't freeze them unconditionally because targets may be artificially
22370 misaligned by the expansion of preceding frags. */
22371 if (stretch
<= 0 && newsize
> 2)
22373 md_convert_frag (sec
->owner
, sec
, fragp
);
22377 return newsize
- oldsize
;
22380 /* Round up a section size to the appropriate boundary. */
22383 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22389 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22390 of an rs_align_code fragment. */
22393 arm_handle_align (fragS
* fragP
)
22395 static unsigned char const arm_noop
[2][2][4] =
22398 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22399 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22402 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22403 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22406 static unsigned char const thumb_noop
[2][2][2] =
22409 {0xc0, 0x46}, /* LE */
22410 {0x46, 0xc0}, /* BE */
22413 {0x00, 0xbf}, /* LE */
22414 {0xbf, 0x00} /* BE */
22417 static unsigned char const wide_thumb_noop
[2][4] =
22418 { /* Wide Thumb-2 */
22419 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22420 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22423 unsigned bytes
, fix
, noop_size
;
22425 const unsigned char * noop
;
22426 const unsigned char *narrow_noop
= NULL
;
22431 if (fragP
->fr_type
!= rs_align_code
)
22434 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22435 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22438 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22439 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22441 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22443 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22445 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22446 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22448 narrow_noop
= thumb_noop
[1][target_big_endian
];
22449 noop
= wide_thumb_noop
[target_big_endian
];
22452 noop
= thumb_noop
[0][target_big_endian
];
22460 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22461 ? selected_cpu
: arm_arch_none
,
22463 [target_big_endian
];
22470 fragP
->fr_var
= noop_size
;
22472 if (bytes
& (noop_size
- 1))
22474 fix
= bytes
& (noop_size
- 1);
22476 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22478 memset (p
, 0, fix
);
22485 if (bytes
& noop_size
)
22487 /* Insert a narrow noop. */
22488 memcpy (p
, narrow_noop
, noop_size
);
22490 bytes
-= noop_size
;
22494 /* Use wide noops for the remainder */
22498 while (bytes
>= noop_size
)
22500 memcpy (p
, noop
, noop_size
);
22502 bytes
-= noop_size
;
22506 fragP
->fr_fix
+= fix
;
22509 /* Called from md_do_align. Used to create an alignment
22510 frag in a code section. */
22513 arm_frag_align_code (int n
, int max
)
22517 /* We assume that there will never be a requirement
22518 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22519 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22524 _("alignments greater than %d bytes not supported in .text sections."),
22525 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22526 as_fatal ("%s", err_msg
);
22529 p
= frag_var (rs_align_code
,
22530 MAX_MEM_FOR_RS_ALIGN_CODE
,
22532 (relax_substateT
) max
,
22539 /* Perform target specific initialisation of a frag.
22540 Note - despite the name this initialisation is not done when the frag
22541 is created, but only when its type is assigned. A frag can be created
22542 and used a long time before its type is set, so beware of assuming that
22543 this initialisation is performed first. */
22547 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22549 /* Record whether this frag is in an ARM or a THUMB area. */
22550 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22553 #else /* OBJ_ELF is defined. */
22555 arm_init_frag (fragS
* fragP
, int max_chars
)
22557 bfd_boolean frag_thumb_mode
;
22559 /* If the current ARM vs THUMB mode has not already
22560 been recorded into this frag then do so now. */
22561 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22562 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22564 /* PR 21809: Do not set a mapping state for debug sections
22565 - it just confuses other tools. */
22566 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22569 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22571 /* Record a mapping symbol for alignment frags. We will delete this
22572 later if the alignment ends up empty. */
22573 switch (fragP
->fr_type
)
22576 case rs_align_test
:
22578 mapping_state_2 (MAP_DATA
, max_chars
);
22580 case rs_align_code
:
22581 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22588 /* When we change sections we need to issue a new mapping symbol. */
22591 arm_elf_change_section (void)
22593 /* Link an unlinked unwind index table section to the .text section. */
22594 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22595 && elf_linked_to_section (now_seg
) == NULL
)
22596 elf_linked_to_section (now_seg
) = text_section
;
22600 arm_elf_section_type (const char * str
, size_t len
)
22602 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22603 return SHT_ARM_EXIDX
;
22608 /* Code to deal with unwinding tables. */
22610 static void add_unwind_adjustsp (offsetT
);
22612 /* Generate any deferred unwind frame offset. */
22615 flush_pending_unwind (void)
22619 offset
= unwind
.pending_offset
;
22620 unwind
.pending_offset
= 0;
22622 add_unwind_adjustsp (offset
);
22625 /* Add an opcode to this list for this function. Two-byte opcodes should
22626 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22630 add_unwind_opcode (valueT op
, int length
)
22632 /* Add any deferred stack adjustment. */
22633 if (unwind
.pending_offset
)
22634 flush_pending_unwind ();
22636 unwind
.sp_restored
= 0;
22638 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22640 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22641 if (unwind
.opcodes
)
22642 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22643 unwind
.opcode_alloc
);
22645 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22650 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22652 unwind
.opcode_count
++;
22656 /* Add unwind opcodes to adjust the stack pointer. */
22659 add_unwind_adjustsp (offsetT offset
)
22663 if (offset
> 0x200)
22665 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22670 /* Long form: 0xb2, uleb128. */
22671 /* This might not fit in a word so add the individual bytes,
22672 remembering the list is built in reverse order. */
22673 o
= (valueT
) ((offset
- 0x204) >> 2);
22675 add_unwind_opcode (0, 1);
22677 /* Calculate the uleb128 encoding of the offset. */
22681 bytes
[n
] = o
& 0x7f;
22687 /* Add the insn. */
22689 add_unwind_opcode (bytes
[n
- 1], 1);
22690 add_unwind_opcode (0xb2, 1);
22692 else if (offset
> 0x100)
22694 /* Two short opcodes. */
22695 add_unwind_opcode (0x3f, 1);
22696 op
= (offset
- 0x104) >> 2;
22697 add_unwind_opcode (op
, 1);
22699 else if (offset
> 0)
22701 /* Short opcode. */
22702 op
= (offset
- 4) >> 2;
22703 add_unwind_opcode (op
, 1);
22705 else if (offset
< 0)
22708 while (offset
> 0x100)
22710 add_unwind_opcode (0x7f, 1);
22713 op
= ((offset
- 4) >> 2) | 0x40;
22714 add_unwind_opcode (op
, 1);
22718 /* Finish the list of unwind opcodes for this function. */
22721 finish_unwind_opcodes (void)
22725 if (unwind
.fp_used
)
22727 /* Adjust sp as necessary. */
22728 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22729 flush_pending_unwind ();
22731 /* After restoring sp from the frame pointer. */
22732 op
= 0x90 | unwind
.fp_reg
;
22733 add_unwind_opcode (op
, 1);
22736 flush_pending_unwind ();
22740 /* Start an exception table entry. If idx is nonzero this is an index table
22744 start_unwind_section (const segT text_seg
, int idx
)
22746 const char * text_name
;
22747 const char * prefix
;
22748 const char * prefix_once
;
22749 const char * group_name
;
22757 prefix
= ELF_STRING_ARM_unwind
;
22758 prefix_once
= ELF_STRING_ARM_unwind_once
;
22759 type
= SHT_ARM_EXIDX
;
22763 prefix
= ELF_STRING_ARM_unwind_info
;
22764 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22765 type
= SHT_PROGBITS
;
22768 text_name
= segment_name (text_seg
);
22769 if (streq (text_name
, ".text"))
22772 if (strncmp (text_name
, ".gnu.linkonce.t.",
22773 strlen (".gnu.linkonce.t.")) == 0)
22775 prefix
= prefix_once
;
22776 text_name
+= strlen (".gnu.linkonce.t.");
22779 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22785 /* Handle COMDAT group. */
22786 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22788 group_name
= elf_group_name (text_seg
);
22789 if (group_name
== NULL
)
22791 as_bad (_("Group section `%s' has no group signature"),
22792 segment_name (text_seg
));
22793 ignore_rest_of_line ();
22796 flags
|= SHF_GROUP
;
22800 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22803 /* Set the section link for index tables. */
22805 elf_linked_to_section (now_seg
) = text_seg
;
22809 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22810 personality routine data. Returns zero, or the index table value for
22811 an inline entry. */
22814 create_unwind_entry (int have_data
)
22819 /* The current word of data. */
22821 /* The number of bytes left in this word. */
22824 finish_unwind_opcodes ();
22826 /* Remember the current text section. */
22827 unwind
.saved_seg
= now_seg
;
22828 unwind
.saved_subseg
= now_subseg
;
22830 start_unwind_section (now_seg
, 0);
22832 if (unwind
.personality_routine
== NULL
)
22834 if (unwind
.personality_index
== -2)
22837 as_bad (_("handlerdata in cantunwind frame"));
22838 return 1; /* EXIDX_CANTUNWIND. */
22841 /* Use a default personality routine if none is specified. */
22842 if (unwind
.personality_index
== -1)
22844 if (unwind
.opcode_count
> 3)
22845 unwind
.personality_index
= 1;
22847 unwind
.personality_index
= 0;
22850 /* Space for the personality routine entry. */
22851 if (unwind
.personality_index
== 0)
22853 if (unwind
.opcode_count
> 3)
22854 as_bad (_("too many unwind opcodes for personality routine 0"));
22858 /* All the data is inline in the index table. */
22861 while (unwind
.opcode_count
> 0)
22863 unwind
.opcode_count
--;
22864 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22868 /* Pad with "finish" opcodes. */
22870 data
= (data
<< 8) | 0xb0;
22877 /* We get two opcodes "free" in the first word. */
22878 size
= unwind
.opcode_count
- 2;
22882 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22883 if (unwind
.personality_index
!= -1)
22885 as_bad (_("attempt to recreate an unwind entry"));
22889 /* An extra byte is required for the opcode count. */
22890 size
= unwind
.opcode_count
+ 1;
22893 size
= (size
+ 3) >> 2;
22895 as_bad (_("too many unwind opcodes"));
22897 frag_align (2, 0, 0);
22898 record_alignment (now_seg
, 2);
22899 unwind
.table_entry
= expr_build_dot ();
22901 /* Allocate the table entry. */
22902 ptr
= frag_more ((size
<< 2) + 4);
22903 /* PR 13449: Zero the table entries in case some of them are not used. */
22904 memset (ptr
, 0, (size
<< 2) + 4);
22905 where
= frag_now_fix () - ((size
<< 2) + 4);
22907 switch (unwind
.personality_index
)
22910 /* ??? Should this be a PLT generating relocation? */
22911 /* Custom personality routine. */
22912 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22913 BFD_RELOC_ARM_PREL31
);
22918 /* Set the first byte to the number of additional words. */
22919 data
= size
> 0 ? size
- 1 : 0;
22923 /* ABI defined personality routines. */
22925 /* Three opcodes bytes are packed into the first word. */
22932 /* The size and first two opcode bytes go in the first word. */
22933 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22938 /* Should never happen. */
22942 /* Pack the opcodes into words (MSB first), reversing the list at the same
22944 while (unwind
.opcode_count
> 0)
22948 md_number_to_chars (ptr
, data
, 4);
22953 unwind
.opcode_count
--;
22955 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22958 /* Finish off the last word. */
22961 /* Pad with "finish" opcodes. */
22963 data
= (data
<< 8) | 0xb0;
22965 md_number_to_chars (ptr
, data
, 4);
22970 /* Add an empty descriptor if there is no user-specified data. */
22971 ptr
= frag_more (4);
22972 md_number_to_chars (ptr
, 0, 4);
22979 /* Initialize the DWARF-2 unwind information for this procedure. */
22982 tc_arm_frame_initial_instructions (void)
22984 cfi_add_CFA_def_cfa (REG_SP
, 0);
22986 #endif /* OBJ_ELF */
22988 /* Convert REGNAME to a DWARF-2 register number. */
22991 tc_arm_regname_to_dw2regnum (char *regname
)
22993 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22997 /* PR 16694: Allow VFP registers as well. */
22998 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
23002 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
23011 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
23015 exp
.X_op
= O_secrel
;
23016 exp
.X_add_symbol
= symbol
;
23017 exp
.X_add_number
= 0;
23018 emit_expr (&exp
, size
);
23022 /* MD interface: Symbol and relocation handling. */
23024 /* Return the address within the segment that a PC-relative fixup is
23025 relative to. For ARM, PC-relative fixups applied to instructions
23026 are generally relative to the location of the fixup plus 8 bytes.
23027 Thumb branches are offset by 4, and Thumb loads relative to PC
23028 require special handling. */
23031 md_pcrel_from_section (fixS
* fixP
, segT seg
)
23033 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23035 /* If this is pc-relative and we are going to emit a relocation
23036 then we just want to put out any pipeline compensation that the linker
23037 will need. Otherwise we want to use the calculated base.
23038 For WinCE we skip the bias for externals as well, since this
23039 is how the MS ARM-CE assembler behaves and we want to be compatible. */
23041 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23042 || (arm_force_relocation (fixP
)
23044 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
23050 switch (fixP
->fx_r_type
)
23052 /* PC relative addressing on the Thumb is slightly odd as the
23053 bottom two bits of the PC are forced to zero for the
23054 calculation. This happens *after* application of the
23055 pipeline offset. However, Thumb adrl already adjusts for
23056 this, so we need not do it again. */
23057 case BFD_RELOC_ARM_THUMB_ADD
:
23060 case BFD_RELOC_ARM_THUMB_OFFSET
:
23061 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23062 case BFD_RELOC_ARM_T32_ADD_PC12
:
23063 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23064 return (base
+ 4) & ~3;
23066 /* Thumb branches are simply offset by +4. */
23067 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
23068 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23069 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23070 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23071 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23072 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23073 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
23074 case BFD_RELOC_ARM_THUMB_BF17
:
23075 case BFD_RELOC_ARM_THUMB_BF19
:
23076 case BFD_RELOC_ARM_THUMB_BF13
:
23077 case BFD_RELOC_ARM_THUMB_LOOP12
:
23080 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23082 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23083 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23084 && ARM_IS_FUNC (fixP
->fx_addsy
)
23085 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23086 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23089 /* BLX is like branches above, but forces the low two bits of PC to
23091 case BFD_RELOC_THUMB_PCREL_BLX
:
23093 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23094 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23095 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23096 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23097 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23098 return (base
+ 4) & ~3;
23100 /* ARM mode branches are offset by +8. However, the Windows CE
23101 loader expects the relocation not to take this into account. */
23102 case BFD_RELOC_ARM_PCREL_BLX
:
23104 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23105 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23106 && ARM_IS_FUNC (fixP
->fx_addsy
)
23107 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23108 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23111 case BFD_RELOC_ARM_PCREL_CALL
:
23113 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23114 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23115 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23116 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23117 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23120 case BFD_RELOC_ARM_PCREL_BRANCH
:
23121 case BFD_RELOC_ARM_PCREL_JUMP
:
23122 case BFD_RELOC_ARM_PLT32
:
23124 /* When handling fixups immediately, because we have already
23125 discovered the value of a symbol, or the address of the frag involved
23126 we must account for the offset by +8, as the OS loader will never see the reloc.
23127 see fixup_segment() in write.c
23128 The S_IS_EXTERNAL test handles the case of global symbols.
23129 Those need the calculated base, not just the pipe compensation the linker will need. */
23131 && fixP
->fx_addsy
!= NULL
23132 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23133 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
23141 /* ARM mode loads relative to PC are also offset by +8. Unlike
23142 branches, the Windows CE loader *does* expect the relocation
23143 to take this into account. */
23144 case BFD_RELOC_ARM_OFFSET_IMM
:
23145 case BFD_RELOC_ARM_OFFSET_IMM8
:
23146 case BFD_RELOC_ARM_HWLITERAL
:
23147 case BFD_RELOC_ARM_LITERAL
:
23148 case BFD_RELOC_ARM_CP_OFF_IMM
:
23152 /* Other PC-relative relocations are un-offset. */
23158 static bfd_boolean flag_warn_syms
= TRUE
;
23161 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
23163 /* PR 18347 - Warn if the user attempts to create a symbol with the same
23164 name as an ARM instruction. Whilst strictly speaking it is allowed, it
23165 does mean that the resulting code might be very confusing to the reader.
23166 Also this warning can be triggered if the user omits an operand before
23167 an immediate address, eg:
23171 GAS treats this as an assignment of the value of the symbol foo to a
23172 symbol LDR, and so (without this code) it will not issue any kind of
23173 warning or error message.
23175 Note - ARM instructions are case-insensitive but the strings in the hash
23176 table are all stored in lower case, so we must first ensure that name is
23178 if (flag_warn_syms
&& arm_ops_hsh
)
23180 char * nbuf
= strdup (name
);
23183 for (p
= nbuf
; *p
; p
++)
23185 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
23187 static struct hash_control
* already_warned
= NULL
;
23189 if (already_warned
== NULL
)
23190 already_warned
= hash_new ();
23191 /* Only warn about the symbol once. To keep the code
23192 simple we let hash_insert do the lookup for us. */
23193 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
23194 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
23203 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
23204 Otherwise we have no need to default values of symbols. */
23207 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
23210 if (name
[0] == '_' && name
[1] == 'G'
23211 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
23215 if (symbol_find (name
))
23216 as_bad (_("GOT already in the symbol table"));
23218 GOT_symbol
= symbol_new (name
, undefined_section
,
23219 (valueT
) 0, & zero_address_frag
);
23229 /* Subroutine of md_apply_fix. Check to see if an immediate can be
23230 computed as two separate immediate values, added together. We
23231 already know that this value cannot be computed by just one ARM
23234 static unsigned int
23235 validate_immediate_twopart (unsigned int val
,
23236 unsigned int * highpart
)
23241 for (i
= 0; i
< 32; i
+= 2)
23242 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
23248 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
23250 else if (a
& 0xff0000)
23252 if (a
& 0xff000000)
23254 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
23258 gas_assert (a
& 0xff000000);
23259 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
23262 return (a
& 0xff) | (i
<< 7);
23269 validate_offset_imm (unsigned int val
, int hwse
)
23271 if ((hwse
&& val
> 255) || val
> 4095)
23276 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23277 negative immediate constant by altering the instruction. A bit of
23282 by inverting the second operand, and
23285 by negating the second operand. */
23288 negate_data_op (unsigned long * instruction
,
23289 unsigned long value
)
23292 unsigned long negated
, inverted
;
23294 negated
= encode_arm_immediate (-value
);
23295 inverted
= encode_arm_immediate (~value
);
23297 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23300 /* First negates. */
23301 case OPCODE_SUB
: /* ADD <-> SUB */
23302 new_inst
= OPCODE_ADD
;
23307 new_inst
= OPCODE_SUB
;
23311 case OPCODE_CMP
: /* CMP <-> CMN */
23312 new_inst
= OPCODE_CMN
;
23317 new_inst
= OPCODE_CMP
;
23321 /* Now Inverted ops. */
23322 case OPCODE_MOV
: /* MOV <-> MVN */
23323 new_inst
= OPCODE_MVN
;
23328 new_inst
= OPCODE_MOV
;
23332 case OPCODE_AND
: /* AND <-> BIC */
23333 new_inst
= OPCODE_BIC
;
23338 new_inst
= OPCODE_AND
;
23342 case OPCODE_ADC
: /* ADC <-> SBC */
23343 new_inst
= OPCODE_SBC
;
23348 new_inst
= OPCODE_ADC
;
23352 /* We cannot do anything. */
23357 if (value
== (unsigned) FAIL
)
23360 *instruction
&= OPCODE_MASK
;
23361 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23365 /* Like negate_data_op, but for Thumb-2. */
23367 static unsigned int
23368 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23372 unsigned int negated
, inverted
;
23374 negated
= encode_thumb32_immediate (-value
);
23375 inverted
= encode_thumb32_immediate (~value
);
23377 rd
= (*instruction
>> 8) & 0xf;
23378 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23381 /* ADD <-> SUB. Includes CMP <-> CMN. */
23382 case T2_OPCODE_SUB
:
23383 new_inst
= T2_OPCODE_ADD
;
23387 case T2_OPCODE_ADD
:
23388 new_inst
= T2_OPCODE_SUB
;
23392 /* ORR <-> ORN. Includes MOV <-> MVN. */
23393 case T2_OPCODE_ORR
:
23394 new_inst
= T2_OPCODE_ORN
;
23398 case T2_OPCODE_ORN
:
23399 new_inst
= T2_OPCODE_ORR
;
23403 /* AND <-> BIC. TST has no inverted equivalent. */
23404 case T2_OPCODE_AND
:
23405 new_inst
= T2_OPCODE_BIC
;
23412 case T2_OPCODE_BIC
:
23413 new_inst
= T2_OPCODE_AND
;
23418 case T2_OPCODE_ADC
:
23419 new_inst
= T2_OPCODE_SBC
;
23423 case T2_OPCODE_SBC
:
23424 new_inst
= T2_OPCODE_ADC
;
23428 /* We cannot do anything. */
23433 if (value
== (unsigned int)FAIL
)
23436 *instruction
&= T2_OPCODE_MASK
;
23437 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23441 /* Read a 32-bit thumb instruction from buf. */
23443 static unsigned long
23444 get_thumb32_insn (char * buf
)
23446 unsigned long insn
;
23447 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23448 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23453 /* We usually want to set the low bit on the address of thumb function
23454 symbols. In particular .word foo - . should have the low bit set.
23455 Generic code tries to fold the difference of two symbols to
23456 a constant. Prevent this and force a relocation when the first symbols
23457 is a thumb function. */
23460 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23462 if (op
== O_subtract
23463 && l
->X_op
== O_symbol
23464 && r
->X_op
== O_symbol
23465 && THUMB_IS_FUNC (l
->X_add_symbol
))
23467 l
->X_op
= O_subtract
;
23468 l
->X_op_symbol
= r
->X_add_symbol
;
23469 l
->X_add_number
-= r
->X_add_number
;
23473 /* Process as normal. */
23477 /* Encode Thumb2 unconditional branches and calls. The encoding
23478 for the 2 are identical for the immediate values. */
23481 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23483 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23486 addressT S
, I1
, I2
, lo
, hi
;
23488 S
= (value
>> 24) & 0x01;
23489 I1
= (value
>> 23) & 0x01;
23490 I2
= (value
>> 22) & 0x01;
23491 hi
= (value
>> 12) & 0x3ff;
23492 lo
= (value
>> 1) & 0x7ff;
23493 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23494 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23495 newval
|= (S
<< 10) | hi
;
23496 newval2
&= ~T2I1I2MASK
;
23497 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23498 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23499 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23503 md_apply_fix (fixS
* fixP
,
23507 offsetT value
= * valP
;
23509 unsigned int newimm
;
23510 unsigned long temp
;
23512 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23514 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23516 /* Note whether this will delete the relocation. */
23518 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23521 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23522 consistency with the behaviour on 32-bit hosts. Remember value
23524 value
&= 0xffffffff;
23525 value
^= 0x80000000;
23526 value
-= 0x80000000;
23529 fixP
->fx_addnumber
= value
;
23531 /* Same treatment for fixP->fx_offset. */
23532 fixP
->fx_offset
&= 0xffffffff;
23533 fixP
->fx_offset
^= 0x80000000;
23534 fixP
->fx_offset
-= 0x80000000;
23536 switch (fixP
->fx_r_type
)
23538 case BFD_RELOC_NONE
:
23539 /* This will need to go in the object file. */
23543 case BFD_RELOC_ARM_IMMEDIATE
:
23544 /* We claim that this fixup has been processed here,
23545 even if in fact we generate an error because we do
23546 not have a reloc for it, so tc_gen_reloc will reject it. */
23549 if (fixP
->fx_addsy
)
23551 const char *msg
= 0;
23553 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23554 msg
= _("undefined symbol %s used as an immediate value");
23555 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23556 msg
= _("symbol %s is in a different section");
23557 else if (S_IS_WEAK (fixP
->fx_addsy
))
23558 msg
= _("symbol %s is weak and may be overridden later");
23562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23563 msg
, S_GET_NAME (fixP
->fx_addsy
));
23568 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23570 /* If the offset is negative, we should use encoding A2 for ADR. */
23571 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23572 newimm
= negate_data_op (&temp
, value
);
23575 newimm
= encode_arm_immediate (value
);
23577 /* If the instruction will fail, see if we can fix things up by
23578 changing the opcode. */
23579 if (newimm
== (unsigned int) FAIL
)
23580 newimm
= negate_data_op (&temp
, value
);
23581 /* MOV accepts both ARM modified immediate (A1 encoding) and
23582 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23583 When disassembling, MOV is preferred when there is no encoding
23585 if (newimm
== (unsigned int) FAIL
23586 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23587 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23588 && !((temp
>> SBIT_SHIFT
) & 0x1)
23589 && value
>= 0 && value
<= 0xffff)
23591 /* Clear bits[23:20] to change encoding from A1 to A2. */
23592 temp
&= 0xff0fffff;
23593 /* Encoding high 4bits imm. Code below will encode the remaining
23595 temp
|= (value
& 0x0000f000) << 4;
23596 newimm
= value
& 0x00000fff;
23600 if (newimm
== (unsigned int) FAIL
)
23602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23603 _("invalid constant (%lx) after fixup"),
23604 (unsigned long) value
);
23608 newimm
|= (temp
& 0xfffff000);
23609 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23612 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23614 unsigned int highpart
= 0;
23615 unsigned int newinsn
= 0xe1a00000; /* nop. */
23617 if (fixP
->fx_addsy
)
23619 const char *msg
= 0;
23621 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23622 msg
= _("undefined symbol %s used as an immediate value");
23623 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23624 msg
= _("symbol %s is in a different section");
23625 else if (S_IS_WEAK (fixP
->fx_addsy
))
23626 msg
= _("symbol %s is weak and may be overridden later");
23630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23631 msg
, S_GET_NAME (fixP
->fx_addsy
));
23636 newimm
= encode_arm_immediate (value
);
23637 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23639 /* If the instruction will fail, see if we can fix things up by
23640 changing the opcode. */
23641 if (newimm
== (unsigned int) FAIL
23642 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23644 /* No ? OK - try using two ADD instructions to generate
23646 newimm
= validate_immediate_twopart (value
, & highpart
);
23648 /* Yes - then make sure that the second instruction is
23650 if (newimm
!= (unsigned int) FAIL
)
23652 /* Still No ? Try using a negated value. */
23653 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23654 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23655 /* Otherwise - give up. */
23658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23659 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23664 /* Replace the first operand in the 2nd instruction (which
23665 is the PC) with the destination register. We have
23666 already added in the PC in the first instruction and we
23667 do not want to do it again. */
23668 newinsn
&= ~ 0xf0000;
23669 newinsn
|= ((newinsn
& 0x0f000) << 4);
23672 newimm
|= (temp
& 0xfffff000);
23673 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23675 highpart
|= (newinsn
& 0xfffff000);
23676 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23680 case BFD_RELOC_ARM_OFFSET_IMM
:
23681 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23683 /* Fall through. */
23685 case BFD_RELOC_ARM_LITERAL
:
23691 if (validate_offset_imm (value
, 0) == FAIL
)
23693 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23695 _("invalid literal constant: pool needs to be closer"));
23697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23698 _("bad immediate value for offset (%ld)"),
23703 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23705 newval
&= 0xfffff000;
23708 newval
&= 0xff7ff000;
23709 newval
|= value
| (sign
? INDEX_UP
: 0);
23711 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23714 case BFD_RELOC_ARM_OFFSET_IMM8
:
23715 case BFD_RELOC_ARM_HWLITERAL
:
23721 if (validate_offset_imm (value
, 1) == FAIL
)
23723 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23725 _("invalid literal constant: pool needs to be closer"));
23727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23728 _("bad immediate value for 8-bit offset (%ld)"),
23733 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23735 newval
&= 0xfffff0f0;
23738 newval
&= 0xff7ff0f0;
23739 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23741 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23744 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23745 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23747 _("bad immediate value for offset (%ld)"), (long) value
);
23750 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23752 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23755 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23756 /* This is a complicated relocation used for all varieties of Thumb32
23757 load/store instruction with immediate offset:
23759 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23760 *4, optional writeback(W)
23761 (doubleword load/store)
23763 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23764 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23765 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23766 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23767 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23769 Uppercase letters indicate bits that are already encoded at
23770 this point. Lowercase letters are our problem. For the
23771 second block of instructions, the secondary opcode nybble
23772 (bits 8..11) is present, and bit 23 is zero, even if this is
23773 a PC-relative operation. */
23774 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23776 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23778 if ((newval
& 0xf0000000) == 0xe0000000)
23780 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23782 newval
|= (1 << 23);
23785 if (value
% 4 != 0)
23787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23788 _("offset not a multiple of 4"));
23794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23795 _("offset out of range"));
23800 else if ((newval
& 0x000f0000) == 0x000f0000)
23802 /* PC-relative, 12-bit offset. */
23804 newval
|= (1 << 23);
23809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23810 _("offset out of range"));
23815 else if ((newval
& 0x00000100) == 0x00000100)
23817 /* Writeback: 8-bit, +/- offset. */
23819 newval
|= (1 << 9);
23824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23825 _("offset out of range"));
23830 else if ((newval
& 0x00000f00) == 0x00000e00)
23832 /* T-instruction: positive 8-bit offset. */
23833 if (value
< 0 || value
> 0xff)
23835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23836 _("offset out of range"));
23844 /* Positive 12-bit or negative 8-bit offset. */
23848 newval
|= (1 << 23);
23858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23859 _("offset out of range"));
23866 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23867 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23870 case BFD_RELOC_ARM_SHIFT_IMM
:
23871 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23872 if (((unsigned long) value
) > 32
23874 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23877 _("shift expression is too large"));
23882 /* Shifts of zero must be done as lsl. */
23884 else if (value
== 32)
23886 newval
&= 0xfffff07f;
23887 newval
|= (value
& 0x1f) << 7;
23888 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23891 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23892 case BFD_RELOC_ARM_T32_ADD_IMM
:
23893 case BFD_RELOC_ARM_T32_IMM12
:
23894 case BFD_RELOC_ARM_T32_ADD_PC12
:
23895 /* We claim that this fixup has been processed here,
23896 even if in fact we generate an error because we do
23897 not have a reloc for it, so tc_gen_reloc will reject it. */
23901 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23904 _("undefined symbol %s used as an immediate value"),
23905 S_GET_NAME (fixP
->fx_addsy
));
23909 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23911 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23914 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23915 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23916 Thumb2 modified immediate encoding (T2). */
23917 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23918 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23920 newimm
= encode_thumb32_immediate (value
);
23921 if (newimm
== (unsigned int) FAIL
)
23922 newimm
= thumb32_negate_data_op (&newval
, value
);
23924 if (newimm
== (unsigned int) FAIL
)
23926 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23928 /* Turn add/sum into addw/subw. */
23929 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23930 newval
= (newval
& 0xfeffffff) | 0x02000000;
23931 /* No flat 12-bit imm encoding for addsw/subsw. */
23932 if ((newval
& 0x00100000) == 0)
23934 /* 12 bit immediate for addw/subw. */
23938 newval
^= 0x00a00000;
23941 newimm
= (unsigned int) FAIL
;
23948 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23949 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23950 disassembling, MOV is preferred when there is no encoding
23952 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23953 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23954 but with the Rn field [19:16] set to 1111. */
23955 && (((newval
>> 16) & 0xf) == 0xf)
23956 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23957 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23958 && value
>= 0 && value
<= 0xffff)
23960 /* Toggle bit[25] to change encoding from T2 to T3. */
23962 /* Clear bits[19:16]. */
23963 newval
&= 0xfff0ffff;
23964 /* Encoding high 4bits imm. Code below will encode the
23965 remaining low 12bits. */
23966 newval
|= (value
& 0x0000f000) << 4;
23967 newimm
= value
& 0x00000fff;
23972 if (newimm
== (unsigned int)FAIL
)
23974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23975 _("invalid constant (%lx) after fixup"),
23976 (unsigned long) value
);
23980 newval
|= (newimm
& 0x800) << 15;
23981 newval
|= (newimm
& 0x700) << 4;
23982 newval
|= (newimm
& 0x0ff);
23984 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23985 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23988 case BFD_RELOC_ARM_SMC
:
23989 if (((unsigned long) value
) > 0xffff)
23990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23991 _("invalid smc expression"));
23992 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23993 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23994 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23997 case BFD_RELOC_ARM_HVC
:
23998 if (((unsigned long) value
) > 0xffff)
23999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24000 _("invalid hvc expression"));
24001 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24002 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
24003 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24006 case BFD_RELOC_ARM_SWI
:
24007 if (fixP
->tc_fix_data
!= 0)
24009 if (((unsigned long) value
) > 0xff)
24010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24011 _("invalid swi expression"));
24012 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24014 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24018 if (((unsigned long) value
) > 0x00ffffff)
24019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24020 _("invalid swi expression"));
24021 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24023 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24027 case BFD_RELOC_ARM_MULTI
:
24028 if (((unsigned long) value
) > 0xffff)
24029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24030 _("invalid expression in load/store multiple"));
24031 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
24032 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24036 case BFD_RELOC_ARM_PCREL_CALL
:
24038 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24040 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24041 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24042 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24043 /* Flip the bl to blx. This is a simple flip
24044 bit here because we generate PCREL_CALL for
24045 unconditional bls. */
24047 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24048 newval
= newval
| 0x10000000;
24049 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24055 goto arm_branch_common
;
24057 case BFD_RELOC_ARM_PCREL_JUMP
:
24058 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24060 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24061 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24062 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24064 /* This would map to a bl<cond>, b<cond>,
24065 b<always> to a Thumb function. We
24066 need to force a relocation for this particular
24068 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24071 /* Fall through. */
24073 case BFD_RELOC_ARM_PLT32
:
24075 case BFD_RELOC_ARM_PCREL_BRANCH
:
24077 goto arm_branch_common
;
24079 case BFD_RELOC_ARM_PCREL_BLX
:
24082 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24084 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24085 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24086 && ARM_IS_FUNC (fixP
->fx_addsy
))
24088 /* Flip the blx to a bl and warn. */
24089 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24090 newval
= 0xeb000000;
24091 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24092 _("blx to '%s' an ARM ISA state function changed to bl"),
24094 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24100 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24101 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
24105 /* We are going to store value (shifted right by two) in the
24106 instruction, in a 24 bit, signed field. Bits 26 through 32 either
24107 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
24110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24111 _("misaligned branch destination"));
24112 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
24113 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
24114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24116 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24118 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24119 newval
|= (value
>> 2) & 0x00ffffff;
24120 /* Set the H bit on BLX instructions. */
24124 newval
|= 0x01000000;
24126 newval
&= ~0x01000000;
24128 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24132 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
24133 /* CBZ can only branch forward. */
24135 /* Attempts to use CBZ to branch to the next instruction
24136 (which, strictly speaking, are prohibited) will be turned into
24139 FIXME: It may be better to remove the instruction completely and
24140 perform relaxation. */
24143 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24144 newval
= 0xbf00; /* NOP encoding T1 */
24145 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24150 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24152 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24154 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24155 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
24156 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24161 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
24162 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
24163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24167 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24168 newval
|= (value
& 0x1ff) >> 1;
24169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24173 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
24174 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
24175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24177 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24179 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24180 newval
|= (value
& 0xfff) >> 1;
24181 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24185 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24187 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24188 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24189 && ARM_IS_FUNC (fixP
->fx_addsy
)
24190 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24192 /* Force a relocation for a branch 20 bits wide. */
24195 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
24196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24197 _("conditional branch out of range"));
24199 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24202 addressT S
, J1
, J2
, lo
, hi
;
24204 S
= (value
& 0x00100000) >> 20;
24205 J2
= (value
& 0x00080000) >> 19;
24206 J1
= (value
& 0x00040000) >> 18;
24207 hi
= (value
& 0x0003f000) >> 12;
24208 lo
= (value
& 0x00000ffe) >> 1;
24210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24211 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24212 newval
|= (S
<< 10) | hi
;
24213 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
24214 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24215 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24219 case BFD_RELOC_THUMB_PCREL_BLX
:
24220 /* If there is a blx from a thumb state function to
24221 another thumb function flip this to a bl and warn
24225 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24226 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24227 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24229 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24230 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24231 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
24233 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24234 newval
= newval
| 0x1000;
24235 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24236 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24241 goto thumb_bl_common
;
24243 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24244 /* A bl from Thumb state ISA to an internal ARM state function
24245 is converted to a blx. */
24247 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24248 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24249 && ARM_IS_FUNC (fixP
->fx_addsy
)
24250 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24252 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24253 newval
= newval
& ~0x1000;
24254 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24255 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
24261 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24262 /* For a BLX instruction, make sure that the relocation is rounded up
24263 to a word boundary. This follows the semantics of the instruction
24264 which specifies that bit 1 of the target address will come from bit
24265 1 of the base address. */
24266 value
= (value
+ 3) & ~ 3;
24269 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
24270 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24271 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24274 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24276 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24278 else if ((value
& ~0x1ffffff)
24279 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24281 _("Thumb2 branch out of range"));
24284 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24285 encode_thumb2_b_bl_offset (buf
, value
);
24289 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24290 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24293 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24294 encode_thumb2_b_bl_offset (buf
, value
);
24299 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24304 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24305 md_number_to_chars (buf
, value
, 2);
24309 case BFD_RELOC_ARM_TLS_CALL
:
24310 case BFD_RELOC_ARM_THM_TLS_CALL
:
24311 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24312 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24313 case BFD_RELOC_ARM_TLS_GOTDESC
:
24314 case BFD_RELOC_ARM_TLS_GD32
:
24315 case BFD_RELOC_ARM_TLS_LE32
:
24316 case BFD_RELOC_ARM_TLS_IE32
:
24317 case BFD_RELOC_ARM_TLS_LDM32
:
24318 case BFD_RELOC_ARM_TLS_LDO32
:
24319 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24322 /* Same handling as above, but with the arm_fdpic guard. */
24323 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24324 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24325 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24328 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24333 _("Relocation supported only in FDPIC mode"));
24337 case BFD_RELOC_ARM_GOT32
:
24338 case BFD_RELOC_ARM_GOTOFF
:
24341 case BFD_RELOC_ARM_GOT_PREL
:
24342 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24343 md_number_to_chars (buf
, value
, 4);
24346 case BFD_RELOC_ARM_TARGET2
:
24347 /* TARGET2 is not partial-inplace, so we need to write the
24348 addend here for REL targets, because it won't be written out
24349 during reloc processing later. */
24350 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24351 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24354 /* Relocations for FDPIC. */
24355 case BFD_RELOC_ARM_GOTFUNCDESC
:
24356 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24357 case BFD_RELOC_ARM_FUNCDESC
:
24360 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24361 md_number_to_chars (buf
, 0, 4);
24365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24366 _("Relocation supported only in FDPIC mode"));
24371 case BFD_RELOC_RVA
:
24373 case BFD_RELOC_ARM_TARGET1
:
24374 case BFD_RELOC_ARM_ROSEGREL32
:
24375 case BFD_RELOC_ARM_SBREL32
:
24376 case BFD_RELOC_32_PCREL
:
24378 case BFD_RELOC_32_SECREL
:
24380 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24382 /* For WinCE we only do this for pcrel fixups. */
24383 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24385 md_number_to_chars (buf
, value
, 4);
24389 case BFD_RELOC_ARM_PREL31
:
24390 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24392 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24393 if ((value
^ (value
>> 1)) & 0x40000000)
24395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24396 _("rel31 relocation overflow"));
24398 newval
|= value
& 0x7fffffff;
24399 md_number_to_chars (buf
, newval
, 4);
24404 case BFD_RELOC_ARM_CP_OFF_IMM
:
24405 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24406 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24407 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24409 newval
= get_thumb32_insn (buf
);
24410 if ((newval
& 0x0f200f00) == 0x0d000900)
24412 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24413 has permitted values that are multiples of 2, in the range 0
24415 if (value
< -510 || value
> 510 || (value
& 1))
24416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24417 _("co-processor offset out of range"));
24419 else if (value
< -1023 || value
> 1023 || (value
& 3))
24420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24421 _("co-processor offset out of range"));
24426 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24427 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24428 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24430 newval
= get_thumb32_insn (buf
);
24432 newval
&= 0xffffff00;
24435 newval
&= 0xff7fff00;
24436 if ((newval
& 0x0f200f00) == 0x0d000900)
24438 /* This is a fp16 vstr/vldr.
24440 It requires the immediate offset in the instruction is shifted
24441 left by 1 to be a half-word offset.
24443 Here, left shift by 1 first, and later right shift by 2
24444 should get the right offset. */
24447 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24449 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24450 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24451 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24453 put_thumb32_insn (buf
, newval
);
24456 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24457 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24458 if (value
< -255 || value
> 255)
24459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24460 _("co-processor offset out of range"));
24462 goto cp_off_common
;
24464 case BFD_RELOC_ARM_THUMB_OFFSET
:
24465 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24466 /* Exactly what ranges, and where the offset is inserted depends
24467 on the type of instruction, we can establish this from the
24469 switch (newval
>> 12)
24471 case 4: /* PC load. */
24472 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24473 forced to zero for these loads; md_pcrel_from has already
24474 compensated for this. */
24476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24477 _("invalid offset, target not word aligned (0x%08lX)"),
24478 (((unsigned long) fixP
->fx_frag
->fr_address
24479 + (unsigned long) fixP
->fx_where
) & ~3)
24480 + (unsigned long) value
);
24482 if (value
& ~0x3fc)
24483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24484 _("invalid offset, value too big (0x%08lX)"),
24487 newval
|= value
>> 2;
24490 case 9: /* SP load/store. */
24491 if (value
& ~0x3fc)
24492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24493 _("invalid offset, value too big (0x%08lX)"),
24495 newval
|= value
>> 2;
24498 case 6: /* Word load/store. */
24500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24501 _("invalid offset, value too big (0x%08lX)"),
24503 newval
|= value
<< 4; /* 6 - 2. */
24506 case 7: /* Byte load/store. */
24508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24509 _("invalid offset, value too big (0x%08lX)"),
24511 newval
|= value
<< 6;
24514 case 8: /* Halfword load/store. */
24516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24517 _("invalid offset, value too big (0x%08lX)"),
24519 newval
|= value
<< 5; /* 6 - 1. */
24523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24524 "Unable to process relocation for thumb opcode: %lx",
24525 (unsigned long) newval
);
24528 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24531 case BFD_RELOC_ARM_THUMB_ADD
:
24532 /* This is a complicated relocation, since we use it for all of
24533 the following immediate relocations:
24537 9bit ADD/SUB SP word-aligned
24538 10bit ADD PC/SP word-aligned
24540 The type of instruction being processed is encoded in the
24547 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24549 int rd
= (newval
>> 4) & 0xf;
24550 int rs
= newval
& 0xf;
24551 int subtract
= !!(newval
& 0x8000);
24553 /* Check for HI regs, only very restricted cases allowed:
24554 Adjusting SP, and using PC or SP to get an address. */
24555 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24556 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24558 _("invalid Hi register with immediate"));
24560 /* If value is negative, choose the opposite instruction. */
24564 subtract
= !subtract
;
24566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24567 _("immediate value out of range"));
24572 if (value
& ~0x1fc)
24573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24574 _("invalid immediate for stack address calculation"));
24575 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24576 newval
|= value
>> 2;
24578 else if (rs
== REG_PC
|| rs
== REG_SP
)
24580 /* PR gas/18541. If the addition is for a defined symbol
24581 within range of an ADR instruction then accept it. */
24584 && fixP
->fx_addsy
!= NULL
)
24588 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24589 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24590 || S_IS_WEAK (fixP
->fx_addsy
))
24592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24593 _("address calculation needs a strongly defined nearby symbol"));
24597 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24599 /* Round up to the next 4-byte boundary. */
24604 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24609 _("symbol too far away"));
24619 if (subtract
|| value
& ~0x3fc)
24620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24621 _("invalid immediate for address calculation (value = 0x%08lX)"),
24622 (unsigned long) (subtract
? - value
: value
));
24623 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24625 newval
|= value
>> 2;
24630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24631 _("immediate value out of range"));
24632 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24633 newval
|= (rd
<< 8) | value
;
24638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24639 _("immediate value out of range"));
24640 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24641 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24644 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24647 case BFD_RELOC_ARM_THUMB_IMM
:
24648 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24649 if (value
< 0 || value
> 255)
24650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24651 _("invalid immediate: %ld is out of range"),
24654 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24657 case BFD_RELOC_ARM_THUMB_SHIFT
:
24658 /* 5bit shift value (0..32). LSL cannot take 32. */
24659 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24660 temp
= newval
& 0xf800;
24661 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24663 _("invalid shift value: %ld"), (long) value
);
24664 /* Shifts of zero must be encoded as LSL. */
24666 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24667 /* Shifts of 32 are encoded as zero. */
24668 else if (value
== 32)
24670 newval
|= value
<< 6;
24671 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24674 case BFD_RELOC_VTABLE_INHERIT
:
24675 case BFD_RELOC_VTABLE_ENTRY
:
24679 case BFD_RELOC_ARM_MOVW
:
24680 case BFD_RELOC_ARM_MOVT
:
24681 case BFD_RELOC_ARM_THUMB_MOVW
:
24682 case BFD_RELOC_ARM_THUMB_MOVT
:
24683 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24685 /* REL format relocations are limited to a 16-bit addend. */
24686 if (!fixP
->fx_done
)
24688 if (value
< -0x8000 || value
> 0x7fff)
24689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24690 _("offset out of range"));
24692 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24693 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24698 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24699 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24701 newval
= get_thumb32_insn (buf
);
24702 newval
&= 0xfbf08f00;
24703 newval
|= (value
& 0xf000) << 4;
24704 newval
|= (value
& 0x0800) << 15;
24705 newval
|= (value
& 0x0700) << 4;
24706 newval
|= (value
& 0x00ff);
24707 put_thumb32_insn (buf
, newval
);
24711 newval
= md_chars_to_number (buf
, 4);
24712 newval
&= 0xfff0f000;
24713 newval
|= value
& 0x0fff;
24714 newval
|= (value
& 0xf000) << 4;
24715 md_number_to_chars (buf
, newval
, 4);
24720 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24721 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24722 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24723 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24724 gas_assert (!fixP
->fx_done
);
24727 bfd_boolean is_mov
;
24728 bfd_vma encoded_addend
= value
;
24730 /* Check that addend can be encoded in instruction. */
24731 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24733 _("the offset 0x%08lX is not representable"),
24734 (unsigned long) encoded_addend
);
24736 /* Extract the instruction. */
24737 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24738 is_mov
= (insn
& 0xf800) == 0x2000;
24743 if (!seg
->use_rela_p
)
24744 insn
|= encoded_addend
;
24750 /* Extract the instruction. */
24751 /* Encoding is the following
24756 /* The following conditions must be true :
24761 rd
= (insn
>> 4) & 0xf;
24763 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24765 _("Unable to process relocation for thumb opcode: %lx"),
24766 (unsigned long) insn
);
24768 /* Encode as ADD immediate8 thumb 1 code. */
24769 insn
= 0x3000 | (rd
<< 8);
24771 /* Place the encoded addend into the first 8 bits of the
24773 if (!seg
->use_rela_p
)
24774 insn
|= encoded_addend
;
24777 /* Update the instruction. */
24778 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24782 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24783 case BFD_RELOC_ARM_ALU_PC_G0
:
24784 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24785 case BFD_RELOC_ARM_ALU_PC_G1
:
24786 case BFD_RELOC_ARM_ALU_PC_G2
:
24787 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24788 case BFD_RELOC_ARM_ALU_SB_G0
:
24789 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24790 case BFD_RELOC_ARM_ALU_SB_G1
:
24791 case BFD_RELOC_ARM_ALU_SB_G2
:
24792 gas_assert (!fixP
->fx_done
);
24793 if (!seg
->use_rela_p
)
24796 bfd_vma encoded_addend
;
24797 bfd_vma addend_abs
= llabs (value
);
24799 /* Check that the absolute value of the addend can be
24800 expressed as an 8-bit constant plus a rotation. */
24801 encoded_addend
= encode_arm_immediate (addend_abs
);
24802 if (encoded_addend
== (unsigned int) FAIL
)
24803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24804 _("the offset 0x%08lX is not representable"),
24805 (unsigned long) addend_abs
);
24807 /* Extract the instruction. */
24808 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24810 /* If the addend is positive, use an ADD instruction.
24811 Otherwise use a SUB. Take care not to destroy the S bit. */
24812 insn
&= 0xff1fffff;
24818 /* Place the encoded addend into the first 12 bits of the
24820 insn
&= 0xfffff000;
24821 insn
|= encoded_addend
;
24823 /* Update the instruction. */
24824 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24828 case BFD_RELOC_ARM_LDR_PC_G0
:
24829 case BFD_RELOC_ARM_LDR_PC_G1
:
24830 case BFD_RELOC_ARM_LDR_PC_G2
:
24831 case BFD_RELOC_ARM_LDR_SB_G0
:
24832 case BFD_RELOC_ARM_LDR_SB_G1
:
24833 case BFD_RELOC_ARM_LDR_SB_G2
:
24834 gas_assert (!fixP
->fx_done
);
24835 if (!seg
->use_rela_p
)
24838 bfd_vma addend_abs
= llabs (value
);
24840 /* Check that the absolute value of the addend can be
24841 encoded in 12 bits. */
24842 if (addend_abs
>= 0x1000)
24843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24844 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24845 (unsigned long) addend_abs
);
24847 /* Extract the instruction. */
24848 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24850 /* If the addend is negative, clear bit 23 of the instruction.
24851 Otherwise set it. */
24853 insn
&= ~(1 << 23);
24857 /* Place the absolute value of the addend into the first 12 bits
24858 of the instruction. */
24859 insn
&= 0xfffff000;
24860 insn
|= addend_abs
;
24862 /* Update the instruction. */
24863 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24867 case BFD_RELOC_ARM_LDRS_PC_G0
:
24868 case BFD_RELOC_ARM_LDRS_PC_G1
:
24869 case BFD_RELOC_ARM_LDRS_PC_G2
:
24870 case BFD_RELOC_ARM_LDRS_SB_G0
:
24871 case BFD_RELOC_ARM_LDRS_SB_G1
:
24872 case BFD_RELOC_ARM_LDRS_SB_G2
:
24873 gas_assert (!fixP
->fx_done
);
24874 if (!seg
->use_rela_p
)
24877 bfd_vma addend_abs
= llabs (value
);
24879 /* Check that the absolute value of the addend can be
24880 encoded in 8 bits. */
24881 if (addend_abs
>= 0x100)
24882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24883 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24884 (unsigned long) addend_abs
);
24886 /* Extract the instruction. */
24887 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24889 /* If the addend is negative, clear bit 23 of the instruction.
24890 Otherwise set it. */
24892 insn
&= ~(1 << 23);
24896 /* Place the first four bits of the absolute value of the addend
24897 into the first 4 bits of the instruction, and the remaining
24898 four into bits 8 .. 11. */
24899 insn
&= 0xfffff0f0;
24900 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24902 /* Update the instruction. */
24903 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24907 case BFD_RELOC_ARM_LDC_PC_G0
:
24908 case BFD_RELOC_ARM_LDC_PC_G1
:
24909 case BFD_RELOC_ARM_LDC_PC_G2
:
24910 case BFD_RELOC_ARM_LDC_SB_G0
:
24911 case BFD_RELOC_ARM_LDC_SB_G1
:
24912 case BFD_RELOC_ARM_LDC_SB_G2
:
24913 gas_assert (!fixP
->fx_done
);
24914 if (!seg
->use_rela_p
)
24917 bfd_vma addend_abs
= llabs (value
);
24919 /* Check that the absolute value of the addend is a multiple of
24920 four and, when divided by four, fits in 8 bits. */
24921 if (addend_abs
& 0x3)
24922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24923 _("bad offset 0x%08lX (must be word-aligned)"),
24924 (unsigned long) addend_abs
);
24926 if ((addend_abs
>> 2) > 0xff)
24927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24928 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24929 (unsigned long) addend_abs
);
24931 /* Extract the instruction. */
24932 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24934 /* If the addend is negative, clear bit 23 of the instruction.
24935 Otherwise set it. */
24937 insn
&= ~(1 << 23);
24941 /* Place the addend (divided by four) into the first eight
24942 bits of the instruction. */
24943 insn
&= 0xfffffff0;
24944 insn
|= addend_abs
>> 2;
24946 /* Update the instruction. */
24947 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24951 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24953 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24954 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24955 && ARM_IS_FUNC (fixP
->fx_addsy
)
24956 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24958 /* Force a relocation for a branch 5 bits wide. */
24961 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
24962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24965 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24967 addressT boff
= value
>> 1;
24969 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24970 newval
|= (boff
<< 7);
24971 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24975 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
24977 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24978 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24979 && ARM_IS_FUNC (fixP
->fx_addsy
)
24980 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24984 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
24985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24986 _("branch out of range"));
24988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24990 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24992 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
24993 addressT diff
= value
- boff
;
24997 newval
|= 1 << 1; /* T bit. */
24999 else if (diff
!= 2)
25001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25002 _("out of range label-relative fixup value"));
25004 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25008 case BFD_RELOC_ARM_THUMB_BF17
:
25010 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25011 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25012 && ARM_IS_FUNC (fixP
->fx_addsy
)
25013 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25015 /* Force a relocation for a branch 17 bits wide. */
25019 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
25020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25026 addressT immA
, immB
, immC
;
25028 immA
= (value
& 0x0001f000) >> 12;
25029 immB
= (value
& 0x00000ffc) >> 2;
25030 immC
= (value
& 0x00000002) >> 1;
25032 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25033 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25035 newval2
|= (immC
<< 11) | (immB
<< 1);
25036 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25037 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25041 case BFD_RELOC_ARM_THUMB_BF19
:
25043 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25044 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25045 && ARM_IS_FUNC (fixP
->fx_addsy
)
25046 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25048 /* Force a relocation for a branch 19 bits wide. */
25052 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
25053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25056 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25059 addressT immA
, immB
, immC
;
25061 immA
= (value
& 0x0007f000) >> 12;
25062 immB
= (value
& 0x00000ffc) >> 2;
25063 immC
= (value
& 0x00000002) >> 1;
25065 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25066 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25068 newval2
|= (immC
<< 11) | (immB
<< 1);
25069 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25070 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25074 case BFD_RELOC_ARM_THUMB_BF13
:
25076 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25077 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25078 && ARM_IS_FUNC (fixP
->fx_addsy
)
25079 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25081 /* Force a relocation for a branch 13 bits wide. */
25085 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
25086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25089 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25092 addressT immA
, immB
, immC
;
25094 immA
= (value
& 0x00001000) >> 12;
25095 immB
= (value
& 0x00000ffc) >> 2;
25096 immC
= (value
& 0x00000002) >> 1;
25098 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25099 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25101 newval2
|= (immC
<< 11) | (immB
<< 1);
25102 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25103 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25107 case BFD_RELOC_ARM_THUMB_LOOP12
:
25109 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25110 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25111 && ARM_IS_FUNC (fixP
->fx_addsy
)
25112 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25114 /* Force a relocation for a branch 12 bits wide. */
25118 bfd_vma insn
= get_thumb32_insn (buf
);
25119 /* le lr, <label> or le <label> */
25120 if (((insn
& 0xffffffff) == 0xf00fc001)
25121 || ((insn
& 0xffffffff) == 0xf02fc001))
25124 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
25125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25127 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25129 addressT imml
, immh
;
25131 immh
= (value
& 0x00000ffc) >> 2;
25132 imml
= (value
& 0x00000002) >> 1;
25134 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25135 newval
|= (imml
<< 11) | (immh
<< 1);
25136 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
25140 case BFD_RELOC_ARM_V4BX
:
25141 /* This will need to go in the object file. */
25145 case BFD_RELOC_UNUSED
:
25147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25148 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
25152 /* Translate internal representation of relocation info to BFD target
25156 tc_gen_reloc (asection
*section
, fixS
*fixp
)
25159 bfd_reloc_code_real_type code
;
25161 reloc
= XNEW (arelent
);
25163 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
25164 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
25165 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
25167 if (fixp
->fx_pcrel
)
25169 if (section
->use_rela_p
)
25170 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
25172 fixp
->fx_offset
= reloc
->address
;
25174 reloc
->addend
= fixp
->fx_offset
;
25176 switch (fixp
->fx_r_type
)
25179 if (fixp
->fx_pcrel
)
25181 code
= BFD_RELOC_8_PCREL
;
25184 /* Fall through. */
25187 if (fixp
->fx_pcrel
)
25189 code
= BFD_RELOC_16_PCREL
;
25192 /* Fall through. */
25195 if (fixp
->fx_pcrel
)
25197 code
= BFD_RELOC_32_PCREL
;
25200 /* Fall through. */
25202 case BFD_RELOC_ARM_MOVW
:
25203 if (fixp
->fx_pcrel
)
25205 code
= BFD_RELOC_ARM_MOVW_PCREL
;
25208 /* Fall through. */
25210 case BFD_RELOC_ARM_MOVT
:
25211 if (fixp
->fx_pcrel
)
25213 code
= BFD_RELOC_ARM_MOVT_PCREL
;
25216 /* Fall through. */
25218 case BFD_RELOC_ARM_THUMB_MOVW
:
25219 if (fixp
->fx_pcrel
)
25221 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
25224 /* Fall through. */
25226 case BFD_RELOC_ARM_THUMB_MOVT
:
25227 if (fixp
->fx_pcrel
)
25229 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
25232 /* Fall through. */
25234 case BFD_RELOC_NONE
:
25235 case BFD_RELOC_ARM_PCREL_BRANCH
:
25236 case BFD_RELOC_ARM_PCREL_BLX
:
25237 case BFD_RELOC_RVA
:
25238 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25239 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25240 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25241 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25242 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25243 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25244 case BFD_RELOC_VTABLE_ENTRY
:
25245 case BFD_RELOC_VTABLE_INHERIT
:
25247 case BFD_RELOC_32_SECREL
:
25249 code
= fixp
->fx_r_type
;
25252 case BFD_RELOC_THUMB_PCREL_BLX
:
25254 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
25255 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25258 code
= BFD_RELOC_THUMB_PCREL_BLX
;
25261 case BFD_RELOC_ARM_LITERAL
:
25262 case BFD_RELOC_ARM_HWLITERAL
:
25263 /* If this is called then the a literal has
25264 been referenced across a section boundary. */
25265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25266 _("literal referenced across section boundary"));
25270 case BFD_RELOC_ARM_TLS_CALL
:
25271 case BFD_RELOC_ARM_THM_TLS_CALL
:
25272 case BFD_RELOC_ARM_TLS_DESCSEQ
:
25273 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
25274 case BFD_RELOC_ARM_GOT32
:
25275 case BFD_RELOC_ARM_GOTOFF
:
25276 case BFD_RELOC_ARM_GOT_PREL
:
25277 case BFD_RELOC_ARM_PLT32
:
25278 case BFD_RELOC_ARM_TARGET1
:
25279 case BFD_RELOC_ARM_ROSEGREL32
:
25280 case BFD_RELOC_ARM_SBREL32
:
25281 case BFD_RELOC_ARM_PREL31
:
25282 case BFD_RELOC_ARM_TARGET2
:
25283 case BFD_RELOC_ARM_TLS_LDO32
:
25284 case BFD_RELOC_ARM_PCREL_CALL
:
25285 case BFD_RELOC_ARM_PCREL_JUMP
:
25286 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
25287 case BFD_RELOC_ARM_ALU_PC_G0
:
25288 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
25289 case BFD_RELOC_ARM_ALU_PC_G1
:
25290 case BFD_RELOC_ARM_ALU_PC_G2
:
25291 case BFD_RELOC_ARM_LDR_PC_G0
:
25292 case BFD_RELOC_ARM_LDR_PC_G1
:
25293 case BFD_RELOC_ARM_LDR_PC_G2
:
25294 case BFD_RELOC_ARM_LDRS_PC_G0
:
25295 case BFD_RELOC_ARM_LDRS_PC_G1
:
25296 case BFD_RELOC_ARM_LDRS_PC_G2
:
25297 case BFD_RELOC_ARM_LDC_PC_G0
:
25298 case BFD_RELOC_ARM_LDC_PC_G1
:
25299 case BFD_RELOC_ARM_LDC_PC_G2
:
25300 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
25301 case BFD_RELOC_ARM_ALU_SB_G0
:
25302 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
25303 case BFD_RELOC_ARM_ALU_SB_G1
:
25304 case BFD_RELOC_ARM_ALU_SB_G2
:
25305 case BFD_RELOC_ARM_LDR_SB_G0
:
25306 case BFD_RELOC_ARM_LDR_SB_G1
:
25307 case BFD_RELOC_ARM_LDR_SB_G2
:
25308 case BFD_RELOC_ARM_LDRS_SB_G0
:
25309 case BFD_RELOC_ARM_LDRS_SB_G1
:
25310 case BFD_RELOC_ARM_LDRS_SB_G2
:
25311 case BFD_RELOC_ARM_LDC_SB_G0
:
25312 case BFD_RELOC_ARM_LDC_SB_G1
:
25313 case BFD_RELOC_ARM_LDC_SB_G2
:
25314 case BFD_RELOC_ARM_V4BX
:
25315 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
25316 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
25317 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
25318 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
25319 case BFD_RELOC_ARM_GOTFUNCDESC
:
25320 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
25321 case BFD_RELOC_ARM_FUNCDESC
:
25322 case BFD_RELOC_ARM_THUMB_BF17
:
25323 case BFD_RELOC_ARM_THUMB_BF19
:
25324 case BFD_RELOC_ARM_THUMB_BF13
:
25325 code
= fixp
->fx_r_type
;
25328 case BFD_RELOC_ARM_TLS_GOTDESC
:
25329 case BFD_RELOC_ARM_TLS_GD32
:
25330 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
25331 case BFD_RELOC_ARM_TLS_LE32
:
25332 case BFD_RELOC_ARM_TLS_IE32
:
25333 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
25334 case BFD_RELOC_ARM_TLS_LDM32
:
25335 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
25336 /* BFD will include the symbol's address in the addend.
25337 But we don't want that, so subtract it out again here. */
25338 if (!S_IS_COMMON (fixp
->fx_addsy
))
25339 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
25340 code
= fixp
->fx_r_type
;
25344 case BFD_RELOC_ARM_IMMEDIATE
:
25345 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25346 _("internal relocation (type: IMMEDIATE) not fixed up"));
25349 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25350 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25351 _("ADRL used for a symbol not defined in the same file"));
25354 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25355 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25356 case BFD_RELOC_ARM_THUMB_LOOP12
:
25357 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25358 _("%s used for a symbol not defined in the same file"),
25359 bfd_get_reloc_code_name (fixp
->fx_r_type
));
25362 case BFD_RELOC_ARM_OFFSET_IMM
:
25363 if (section
->use_rela_p
)
25365 code
= fixp
->fx_r_type
;
25369 if (fixp
->fx_addsy
!= NULL
25370 && !S_IS_DEFINED (fixp
->fx_addsy
)
25371 && S_IS_LOCAL (fixp
->fx_addsy
))
25373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25374 _("undefined local label `%s'"),
25375 S_GET_NAME (fixp
->fx_addsy
));
25379 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25380 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
25387 switch (fixp
->fx_r_type
)
25389 case BFD_RELOC_NONE
: type
= "NONE"; break;
25390 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
25391 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
25392 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
25393 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
25394 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
25395 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
25396 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
25397 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
25398 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
25399 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
25400 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
25401 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
25402 default: type
= _("<unknown>"); break;
25404 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25405 _("cannot represent %s relocation in this object file format"),
25412 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
25414 && fixp
->fx_addsy
== GOT_symbol
)
25416 code
= BFD_RELOC_ARM_GOTPC
;
25417 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
25421 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
25423 if (reloc
->howto
== NULL
)
25425 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25426 _("cannot represent %s relocation in this object file format"),
25427 bfd_get_reloc_code_name (code
));
25431 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
25432 vtable entry to be used in the relocation's section offset. */
25433 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25434 reloc
->address
= fixp
->fx_offset
;
25439 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
25442 cons_fix_new_arm (fragS
* frag
,
25446 bfd_reloc_code_real_type reloc
)
25451 FIXME: @@ Should look at CPU word size. */
25455 reloc
= BFD_RELOC_8
;
25458 reloc
= BFD_RELOC_16
;
25462 reloc
= BFD_RELOC_32
;
25465 reloc
= BFD_RELOC_64
;
25470 if (exp
->X_op
== O_secrel
)
25472 exp
->X_op
= O_symbol
;
25473 reloc
= BFD_RELOC_32_SECREL
;
25477 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25480 #if defined (OBJ_COFF)
25482 arm_validate_fix (fixS
* fixP
)
25484 /* If the destination of the branch is a defined symbol which does not have
25485 the THUMB_FUNC attribute, then we must be calling a function which has
25486 the (interfacearm) attribute. We look for the Thumb entry point to that
25487 function and change the branch to refer to that function instead. */
25488 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25489 && fixP
->fx_addsy
!= NULL
25490 && S_IS_DEFINED (fixP
->fx_addsy
)
25491 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25493 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25500 arm_force_relocation (struct fix
* fixp
)
25502 #if defined (OBJ_COFF) && defined (TE_PE)
25503 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25507 /* In case we have a call or a branch to a function in ARM ISA mode from
25508 a thumb function or vice-versa force the relocation. These relocations
25509 are cleared off for some cores that might have blx and simple transformations
25513 switch (fixp
->fx_r_type
)
25515 case BFD_RELOC_ARM_PCREL_JUMP
:
25516 case BFD_RELOC_ARM_PCREL_CALL
:
25517 case BFD_RELOC_THUMB_PCREL_BLX
:
25518 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25522 case BFD_RELOC_ARM_PCREL_BLX
:
25523 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25524 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25525 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25526 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25535 /* Resolve these relocations even if the symbol is extern or weak.
25536 Technically this is probably wrong due to symbol preemption.
25537 In practice these relocations do not have enough range to be useful
25538 at dynamic link time, and some code (e.g. in the Linux kernel)
25539 expects these references to be resolved. */
25540 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25541 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25542 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25543 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25544 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25545 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25546 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25547 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25548 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25549 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25550 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25551 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25552 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25553 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25556 /* Always leave these relocations for the linker. */
25557 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25558 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25559 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25562 /* Always generate relocations against function symbols. */
25563 if (fixp
->fx_r_type
== BFD_RELOC_32
25565 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25568 return generic_force_reloc (fixp
);
25571 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25572 /* Relocations against function names must be left unadjusted,
25573 so that the linker can use this information to generate interworking
25574 stubs. The MIPS version of this function
25575 also prevents relocations that are mips-16 specific, but I do not
25576 know why it does this.
25579 There is one other problem that ought to be addressed here, but
25580 which currently is not: Taking the address of a label (rather
25581 than a function) and then later jumping to that address. Such
25582 addresses also ought to have their bottom bit set (assuming that
25583 they reside in Thumb code), but at the moment they will not. */
25586 arm_fix_adjustable (fixS
* fixP
)
25588 if (fixP
->fx_addsy
== NULL
)
25591 /* Preserve relocations against symbols with function type. */
25592 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25595 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25596 && fixP
->fx_subsy
== NULL
)
25599 /* We need the symbol name for the VTABLE entries. */
25600 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25601 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25604 /* Don't allow symbols to be discarded on GOT related relocs. */
25605 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25606 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25607 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25608 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25609 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25610 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25611 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25612 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25613 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25614 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25615 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25616 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25617 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25618 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25619 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25620 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25621 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25624 /* Similarly for group relocations. */
25625 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25626 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25627 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25630 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25631 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25632 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25633 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25634 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25635 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25636 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25637 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25638 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25641 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25642 offsets, so keep these symbols. */
25643 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25644 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25649 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25653 elf32_arm_target_format (void)
25656 return (target_big_endian
25657 ? "elf32-bigarm-symbian"
25658 : "elf32-littlearm-symbian");
25659 #elif defined (TE_VXWORKS)
25660 return (target_big_endian
25661 ? "elf32-bigarm-vxworks"
25662 : "elf32-littlearm-vxworks");
25663 #elif defined (TE_NACL)
25664 return (target_big_endian
25665 ? "elf32-bigarm-nacl"
25666 : "elf32-littlearm-nacl");
25670 if (target_big_endian
)
25671 return "elf32-bigarm-fdpic";
25673 return "elf32-littlearm-fdpic";
25677 if (target_big_endian
)
25678 return "elf32-bigarm";
25680 return "elf32-littlearm";
25686 armelf_frob_symbol (symbolS
* symp
,
25689 elf_frob_symbol (symp
, puntp
);
25693 /* MD interface: Finalization. */
25698 literal_pool
* pool
;
25700 /* Ensure that all the IT blocks are properly closed. */
25701 check_it_blocks_finished ();
25703 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25705 /* Put it at the end of the relevant section. */
25706 subseg_set (pool
->section
, pool
->sub_section
);
25708 arm_elf_change_section ();
25715 /* Remove any excess mapping symbols generated for alignment frags in
25716 SEC. We may have created a mapping symbol before a zero byte
25717 alignment; remove it if there's a mapping symbol after the
25720 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25721 void *dummy ATTRIBUTE_UNUSED
)
25723 segment_info_type
*seginfo
= seg_info (sec
);
25726 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25729 for (fragp
= seginfo
->frchainP
->frch_root
;
25731 fragp
= fragp
->fr_next
)
25733 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25734 fragS
*next
= fragp
->fr_next
;
25736 /* Variable-sized frags have been converted to fixed size by
25737 this point. But if this was variable-sized to start with,
25738 there will be a fixed-size frag after it. So don't handle
25740 if (sym
== NULL
|| next
== NULL
)
25743 if (S_GET_VALUE (sym
) < next
->fr_address
)
25744 /* Not at the end of this frag. */
25746 know (S_GET_VALUE (sym
) == next
->fr_address
);
25750 if (next
->tc_frag_data
.first_map
!= NULL
)
25752 /* Next frag starts with a mapping symbol. Discard this
25754 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25758 if (next
->fr_next
== NULL
)
25760 /* This mapping symbol is at the end of the section. Discard
25762 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25763 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25767 /* As long as we have empty frags without any mapping symbols,
25769 /* If the next frag is non-empty and does not start with a
25770 mapping symbol, then this mapping symbol is required. */
25771 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25774 next
= next
->fr_next
;
25776 while (next
!= NULL
);
25781 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25785 arm_adjust_symtab (void)
25790 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25792 if (ARM_IS_THUMB (sym
))
25794 if (THUMB_IS_FUNC (sym
))
25796 /* Mark the symbol as a Thumb function. */
25797 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25798 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25799 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25801 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25802 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25804 as_bad (_("%s: unexpected function type: %d"),
25805 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25807 else switch (S_GET_STORAGE_CLASS (sym
))
25810 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25813 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25816 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25824 if (ARM_IS_INTERWORK (sym
))
25825 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25832 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25834 if (ARM_IS_THUMB (sym
))
25836 elf_symbol_type
* elf_sym
;
25838 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25839 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25841 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25842 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25844 /* If it's a .thumb_func, declare it as so,
25845 otherwise tag label as .code 16. */
25846 if (THUMB_IS_FUNC (sym
))
25847 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25848 ST_BRANCH_TO_THUMB
);
25849 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25850 elf_sym
->internal_elf_sym
.st_info
=
25851 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25856 /* Remove any overlapping mapping symbols generated by alignment frags. */
25857 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25858 /* Now do generic ELF adjustments. */
25859 elf_adjust_symtab ();
25863 /* MD interface: Initialization. */
25866 set_constant_flonums (void)
25870 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25871 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25875 /* Auto-select Thumb mode if it's the only available instruction set for the
25876 given architecture. */
25879 autoselect_thumb_from_cpu_variant (void)
25881 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25882 opcode_select (16);
25891 if ( (arm_ops_hsh
= hash_new ()) == NULL
25892 || (arm_cond_hsh
= hash_new ()) == NULL
25893 || (arm_shift_hsh
= hash_new ()) == NULL
25894 || (arm_psr_hsh
= hash_new ()) == NULL
25895 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25896 || (arm_reg_hsh
= hash_new ()) == NULL
25897 || (arm_reloc_hsh
= hash_new ()) == NULL
25898 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25899 as_fatal (_("virtual memory exhausted"));
25901 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25902 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25903 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25904 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25905 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25906 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25907 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25908 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25909 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25910 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25911 (void *) (v7m_psrs
+ i
));
25912 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25913 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25915 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25917 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25918 (void *) (barrier_opt_names
+ i
));
25920 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25922 struct reloc_entry
* entry
= reloc_names
+ i
;
25924 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25925 /* This makes encode_branch() use the EABI versions of this relocation. */
25926 entry
->reloc
= BFD_RELOC_UNUSED
;
25928 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25932 set_constant_flonums ();
25934 /* Set the cpu variant based on the command-line options. We prefer
25935 -mcpu= over -march= if both are set (as for GCC); and we prefer
25936 -mfpu= over any other way of setting the floating point unit.
25937 Use of legacy options with new options are faulted. */
25940 if (mcpu_cpu_opt
|| march_cpu_opt
)
25941 as_bad (_("use of old and new-style options to set CPU type"));
25943 selected_arch
= *legacy_cpu
;
25945 else if (mcpu_cpu_opt
)
25947 selected_arch
= *mcpu_cpu_opt
;
25948 selected_ext
= *mcpu_ext_opt
;
25950 else if (march_cpu_opt
)
25952 selected_arch
= *march_cpu_opt
;
25953 selected_ext
= *march_ext_opt
;
25955 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25960 as_bad (_("use of old and new-style options to set FPU type"));
25962 selected_fpu
= *legacy_fpu
;
25965 selected_fpu
= *mfpu_opt
;
25968 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25969 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25970 /* Some environments specify a default FPU. If they don't, infer it
25971 from the processor. */
25973 selected_fpu
= *mcpu_fpu_opt
;
25974 else if (march_fpu_opt
)
25975 selected_fpu
= *march_fpu_opt
;
25977 selected_fpu
= fpu_default
;
25981 if (ARM_FEATURE_ZERO (selected_fpu
))
25983 if (!no_cpu_selected ())
25984 selected_fpu
= fpu_default
;
25986 selected_fpu
= fpu_arch_fpa
;
25990 if (ARM_FEATURE_ZERO (selected_arch
))
25992 selected_arch
= cpu_default
;
25993 selected_cpu
= selected_arch
;
25995 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25997 /* Autodection of feature mode: allow all features in cpu_variant but leave
25998 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25999 after all instruction have been processed and we can decide what CPU
26000 should be selected. */
26001 if (ARM_FEATURE_ZERO (selected_arch
))
26002 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
26004 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
26007 autoselect_thumb_from_cpu_variant ();
26009 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
26011 #if defined OBJ_COFF || defined OBJ_ELF
26013 unsigned int flags
= 0;
26015 #if defined OBJ_ELF
26016 flags
= meabi_flags
;
26018 switch (meabi_flags
)
26020 case EF_ARM_EABI_UNKNOWN
:
26022 /* Set the flags in the private structure. */
26023 if (uses_apcs_26
) flags
|= F_APCS26
;
26024 if (support_interwork
) flags
|= F_INTERWORK
;
26025 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
26026 if (pic_code
) flags
|= F_PIC
;
26027 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
26028 flags
|= F_SOFT_FLOAT
;
26030 switch (mfloat_abi_opt
)
26032 case ARM_FLOAT_ABI_SOFT
:
26033 case ARM_FLOAT_ABI_SOFTFP
:
26034 flags
|= F_SOFT_FLOAT
;
26037 case ARM_FLOAT_ABI_HARD
:
26038 if (flags
& F_SOFT_FLOAT
)
26039 as_bad (_("hard-float conflicts with specified fpu"));
26043 /* Using pure-endian doubles (even if soft-float). */
26044 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
26045 flags
|= F_VFP_FLOAT
;
26047 #if defined OBJ_ELF
26048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
26049 flags
|= EF_ARM_MAVERICK_FLOAT
;
26052 case EF_ARM_EABI_VER4
:
26053 case EF_ARM_EABI_VER5
:
26054 /* No additional flags to set. */
26061 bfd_set_private_flags (stdoutput
, flags
);
26063 /* We have run out flags in the COFF header to encode the
26064 status of ATPCS support, so instead we create a dummy,
26065 empty, debug section called .arm.atpcs. */
26070 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
26074 bfd_set_section_flags
26075 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
26076 bfd_set_section_size (stdoutput
, sec
, 0);
26077 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
26083 /* Record the CPU type as well. */
26084 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
26085 mach
= bfd_mach_arm_iWMMXt2
;
26086 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
26087 mach
= bfd_mach_arm_iWMMXt
;
26088 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
26089 mach
= bfd_mach_arm_XScale
;
26090 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
26091 mach
= bfd_mach_arm_ep9312
;
26092 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
26093 mach
= bfd_mach_arm_5TE
;
26094 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
26096 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26097 mach
= bfd_mach_arm_5T
;
26099 mach
= bfd_mach_arm_5
;
26101 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
26103 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26104 mach
= bfd_mach_arm_4T
;
26106 mach
= bfd_mach_arm_4
;
26108 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
26109 mach
= bfd_mach_arm_3M
;
26110 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
26111 mach
= bfd_mach_arm_3
;
26112 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
26113 mach
= bfd_mach_arm_2a
;
26114 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
26115 mach
= bfd_mach_arm_2
;
26117 mach
= bfd_mach_arm_unknown
;
26119 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
26122 /* Command line processing. */
26125 Invocation line includes a switch not recognized by the base assembler.
26126 See if it's a processor-specific option.
26128 This routine is somewhat complicated by the need for backwards
26129 compatibility (since older releases of gcc can't be changed).
26130 The new options try to make the interface as compatible as
26133 New options (supported) are:
26135 -mcpu=<cpu name> Assemble for selected processor
26136 -march=<architecture name> Assemble for selected architecture
26137 -mfpu=<fpu architecture> Assemble for selected FPU.
26138 -EB/-mbig-endian Big-endian
26139 -EL/-mlittle-endian Little-endian
26140 -k Generate PIC code
26141 -mthumb Start in Thumb mode
26142 -mthumb-interwork Code supports ARM/Thumb interworking
26144 -m[no-]warn-deprecated Warn about deprecated features
26145 -m[no-]warn-syms Warn when symbols match instructions
26147 For now we will also provide support for:
26149 -mapcs-32 32-bit Program counter
26150 -mapcs-26 26-bit Program counter
26151 -macps-float Floats passed in FP registers
26152 -mapcs-reentrant Reentrant code
26154 (sometime these will probably be replaced with -mapcs=<list of options>
26155 and -matpcs=<list of options>)
26157 The remaining options are only supported for back-wards compatibility.
26158 Cpu variants, the arm part is optional:
26159 -m[arm]1 Currently not supported.
26160 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
26161 -m[arm]3 Arm 3 processor
26162 -m[arm]6[xx], Arm 6 processors
26163 -m[arm]7[xx][t][[d]m] Arm 7 processors
26164 -m[arm]8[10] Arm 8 processors
26165 -m[arm]9[20][tdmi] Arm 9 processors
26166 -mstrongarm[110[0]] StrongARM processors
26167 -mxscale XScale processors
26168 -m[arm]v[2345[t[e]]] Arm architectures
26169 -mall All (except the ARM1)
26171 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
26172 -mfpe-old (No float load/store multiples)
26173 -mvfpxd VFP Single precision
26175 -mno-fpu Disable all floating point instructions
26177 The following CPU names are recognized:
26178 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
26179 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
26180 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
26181 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
26182 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
26183 arm10t arm10e, arm1020t, arm1020e, arm10200e,
26184 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
26188 const char * md_shortopts
= "m:k";
26190 #ifdef ARM_BI_ENDIAN
26191 #define OPTION_EB (OPTION_MD_BASE + 0)
26192 #define OPTION_EL (OPTION_MD_BASE + 1)
26194 #if TARGET_BYTES_BIG_ENDIAN
26195 #define OPTION_EB (OPTION_MD_BASE + 0)
26197 #define OPTION_EL (OPTION_MD_BASE + 1)
26200 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
26201 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
26203 struct option md_longopts
[] =
26206 {"EB", no_argument
, NULL
, OPTION_EB
},
26209 {"EL", no_argument
, NULL
, OPTION_EL
},
26211 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
26213 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
26215 {NULL
, no_argument
, NULL
, 0}
26218 size_t md_longopts_size
= sizeof (md_longopts
);
26220 struct arm_option_table
26222 const char * option
; /* Option name to match. */
26223 const char * help
; /* Help information. */
26224 int * var
; /* Variable to change. */
26225 int value
; /* What to change it to. */
26226 const char * deprecated
; /* If non-null, print this message. */
26229 struct arm_option_table arm_opts
[] =
26231 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
26232 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
26233 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
26234 &support_interwork
, 1, NULL
},
26235 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
26236 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
26237 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
26239 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
26240 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
26241 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
26242 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
26245 /* These are recognized by the assembler, but have no affect on code. */
26246 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
26247 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
26249 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
26250 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
26251 &warn_on_deprecated
, 0, NULL
},
26252 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
26253 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
26254 {NULL
, NULL
, NULL
, 0, NULL
}
26257 struct arm_legacy_option_table
26259 const char * option
; /* Option name to match. */
26260 const arm_feature_set
** var
; /* Variable to change. */
26261 const arm_feature_set value
; /* What to change it to. */
26262 const char * deprecated
; /* If non-null, print this message. */
26265 const struct arm_legacy_option_table arm_legacy_opts
[] =
26267 /* DON'T add any new processors to this list -- we want the whole list
26268 to go away... Add them to the processors table instead. */
26269 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26270 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26271 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26272 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26273 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26274 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26275 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26276 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26277 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26278 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26279 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26280 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26281 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26282 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26283 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26284 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26285 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26286 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26287 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26288 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26289 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26290 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26291 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26292 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26293 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26294 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26295 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26296 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26297 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26298 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26299 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26300 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26301 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26302 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26303 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26304 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26305 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26306 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26307 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26308 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26309 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26310 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26311 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26312 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26313 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26314 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26315 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26316 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26317 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26318 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26319 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26320 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26321 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26322 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26323 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26324 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26325 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26326 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26327 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26328 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26329 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26330 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26331 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26332 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26333 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26334 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26335 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26336 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26337 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
26338 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
26339 N_("use -mcpu=strongarm110")},
26340 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
26341 N_("use -mcpu=strongarm1100")},
26342 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
26343 N_("use -mcpu=strongarm1110")},
26344 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
26345 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
26346 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
26348 /* Architecture variants -- don't add any more to this list either. */
26349 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26350 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26351 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26352 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26353 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26354 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26355 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26356 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26357 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26358 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26359 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26360 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26361 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26362 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26363 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26364 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26365 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26366 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26368 /* Floating point variants -- don't add any more to this list either. */
26369 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
26370 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
26371 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
26372 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
26373 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
26375 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
26378 struct arm_cpu_option_table
26382 const arm_feature_set value
;
26383 const arm_feature_set ext
;
26384 /* For some CPUs we assume an FPU unless the user explicitly sets
26386 const arm_feature_set default_fpu
;
26387 /* The canonical name of the CPU, or NULL to use NAME converted to upper
26389 const char * canonical_name
;
26392 /* This list should, at a minimum, contain all the cpu names
26393 recognized by GCC. */
26394 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
26396 static const struct arm_cpu_option_table arm_cpus
[] =
26398 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
26401 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
26404 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
26407 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
26410 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
26413 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
26416 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
26419 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
26422 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
26425 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
26428 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
26431 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
26434 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
26437 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
26440 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
26443 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
26446 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
26449 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
26452 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
26455 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
26458 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
26461 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
26464 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
26467 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
26470 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
26473 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26476 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26479 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26482 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26485 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26488 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26491 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26494 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26497 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26500 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26503 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26506 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26509 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26512 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26515 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26518 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26521 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26524 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26527 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26530 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26533 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26537 /* For V5 or later processors we default to using VFP; but the user
26538 should really set the FPU type explicitly. */
26539 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26542 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26545 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26548 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26551 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26554 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26557 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26560 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26563 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26566 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26569 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26572 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26575 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26578 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26581 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26584 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26587 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26590 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26593 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26596 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26599 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26602 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26605 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26608 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26611 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26614 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26617 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26620 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26623 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26626 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26629 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26632 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26635 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26638 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26641 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26644 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26647 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26648 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26650 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26652 FPU_ARCH_NEON_VFP_V4
),
26653 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26654 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26655 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26656 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26657 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26658 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26659 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26661 FPU_ARCH_NEON_VFP_V4
),
26662 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26664 FPU_ARCH_NEON_VFP_V4
),
26665 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26667 FPU_ARCH_NEON_VFP_V4
),
26668 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26669 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26670 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26671 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26672 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26673 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26674 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26675 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26676 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26677 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26678 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26679 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26680 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26681 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26682 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26683 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26684 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26685 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26686 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26687 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26688 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26689 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26690 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26691 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26692 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26693 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26694 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26695 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26696 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26697 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26698 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26701 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26703 FPU_ARCH_VFP_V3D16
),
26704 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26705 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26707 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26708 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26709 FPU_ARCH_VFP_V3D16
),
26710 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26711 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26712 FPU_ARCH_VFP_V3D16
),
26713 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26714 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26715 FPU_ARCH_NEON_VFP_ARMV8
),
26716 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26717 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26719 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26722 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26725 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26728 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26731 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26734 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26737 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26740 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26741 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26742 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26743 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26744 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26745 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26746 /* ??? XSCALE is really an architecture. */
26747 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26751 /* ??? iwmmxt is not a processor. */
26752 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26755 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26758 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26763 ARM_CPU_OPT ("ep9312", "ARM920T",
26764 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26765 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26767 /* Marvell processors. */
26768 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26769 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26770 FPU_ARCH_VFP_V3D16
),
26771 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26772 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26773 FPU_ARCH_NEON_VFP_V4
),
26775 /* APM X-Gene family. */
26776 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26778 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26779 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26780 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26781 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26783 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26787 struct arm_ext_table
26791 const arm_feature_set merge
;
26792 const arm_feature_set clear
;
26795 struct arm_arch_option_table
26799 const arm_feature_set value
;
26800 const arm_feature_set default_fpu
;
26801 const struct arm_ext_table
* ext_table
;
26804 /* Used to add support for +E and +noE extension. */
26805 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26806 /* Used to add support for a +E extension. */
26807 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26808 /* Used to add support for a +noE extension. */
26809 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26811 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26812 ~0 & ~FPU_ENDIAN_PURE)
26814 static const struct arm_ext_table armv5te_ext_table
[] =
26816 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26817 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26820 static const struct arm_ext_table armv7_ext_table
[] =
26822 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26823 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26826 static const struct arm_ext_table armv7ve_ext_table
[] =
26828 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26829 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26830 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26831 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26832 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26833 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26834 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26836 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26837 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26839 /* Aliases for +simd. */
26840 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26842 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26843 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26844 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26846 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26849 static const struct arm_ext_table armv7a_ext_table
[] =
26851 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26852 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26853 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26854 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26855 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26856 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
26857 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26859 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
26860 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26862 /* Aliases for +simd. */
26863 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26864 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26866 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26867 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26869 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
26870 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
26871 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26874 static const struct arm_ext_table armv7r_ext_table
[] =
26876 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
26877 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
26878 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26879 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26880 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
26881 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26882 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26883 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
26884 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26887 static const struct arm_ext_table armv7em_ext_table
[] =
26889 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
26890 /* Alias for +fp, used to be known as fpv4-sp-d16. */
26891 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
26892 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
26893 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26894 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
26895 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26898 static const struct arm_ext_table armv8a_ext_table
[] =
26900 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26901 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26902 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26903 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26905 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26906 should use the +simd option to turn on FP. */
26907 ARM_REMOVE ("fp", ALL_FP
),
26908 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26909 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26910 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26914 static const struct arm_ext_table armv81a_ext_table
[] =
26916 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26917 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26918 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26920 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26921 should use the +simd option to turn on FP. */
26922 ARM_REMOVE ("fp", ALL_FP
),
26923 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26924 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26925 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26928 static const struct arm_ext_table armv82a_ext_table
[] =
26930 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26931 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
26932 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
26933 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26934 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26935 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26937 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26938 should use the +simd option to turn on FP. */
26939 ARM_REMOVE ("fp", ALL_FP
),
26940 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26941 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26942 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26945 static const struct arm_ext_table armv84a_ext_table
[] =
26947 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26948 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26949 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26950 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26952 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26953 should use the +simd option to turn on FP. */
26954 ARM_REMOVE ("fp", ALL_FP
),
26955 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26956 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26957 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26960 static const struct arm_ext_table armv85a_ext_table
[] =
26962 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26963 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26964 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26965 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26967 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26968 should use the +simd option to turn on FP. */
26969 ARM_REMOVE ("fp", ALL_FP
),
26970 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26973 static const struct arm_ext_table armv8m_main_ext_table
[] =
26975 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26976 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26977 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
26978 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26979 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26982 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
26984 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26985 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26987 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26988 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
26991 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26992 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
26993 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26996 static const struct arm_ext_table armv8r_ext_table
[] =
26998 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26999 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
27000 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27001 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27002 ARM_REMOVE ("fp", ALL_FP
),
27003 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
27004 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27007 /* This list should, at a minimum, contain all the architecture names
27008 recognized by GCC. */
27009 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
27010 #define ARM_ARCH_OPT2(N, V, DF, ext) \
27011 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
27013 static const struct arm_arch_option_table arm_archs
[] =
27015 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
27016 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
27017 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
27018 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27019 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27020 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
27021 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
27022 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
27023 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
27024 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
27025 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
27026 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
27027 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
27028 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
27029 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
27030 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
27031 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
27032 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27033 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27034 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
27035 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
27036 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
27037 kept to preserve existing behaviour. */
27038 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27039 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27040 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
27041 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
27042 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
27043 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
27044 kept to preserve existing behaviour. */
27045 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27046 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27047 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
27048 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
27049 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
27050 /* The official spelling of the ARMv7 profile variants is the dashed form.
27051 Accept the non-dashed form for compatibility with old toolchains. */
27052 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27053 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
27054 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27055 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27056 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27057 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27058 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27059 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
27060 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
27061 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
27063 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
27065 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
27066 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
27067 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
27068 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
27069 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
27070 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
27071 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
27072 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
27073 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
27074 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
27075 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
27077 #undef ARM_ARCH_OPT
27079 /* ISA extensions in the co-processor and main instruction set space. */
27081 struct arm_option_extension_value_table
27085 const arm_feature_set merge_value
;
27086 const arm_feature_set clear_value
;
27087 /* List of architectures for which an extension is available. ARM_ARCH_NONE
27088 indicates that an extension is available for all architectures while
27089 ARM_ANY marks an empty entry. */
27090 const arm_feature_set allowed_archs
[2];
27093 /* The following table must be in alphabetical order with a NULL last entry. */
27095 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
27096 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
27098 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
27099 use the context sensitive approach using arm_ext_table's. */
27100 static const struct arm_option_extension_value_table arm_extensions
[] =
27102 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27103 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27104 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27105 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
27106 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27107 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
27108 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
27110 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27111 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27112 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
27113 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
27114 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27115 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27116 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27118 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27119 | ARM_EXT2_FP16_FML
),
27120 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27121 | ARM_EXT2_FP16_FML
),
27123 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27124 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27125 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27126 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27127 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
27128 Thumb divide instruction. Due to this having the same name as the
27129 previous entry, this will be ignored when doing command-line parsing and
27130 only considered by build attribute selection code. */
27131 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27132 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27133 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
27134 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
27135 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
27136 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
27137 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
27138 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
27139 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
27140 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27141 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27142 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27143 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27144 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27145 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27146 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
27147 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
27148 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
27149 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27150 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27151 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27153 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
27154 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
27155 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27156 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
27157 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
27158 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27159 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27160 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27162 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27163 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27164 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
27165 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27166 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
27167 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
27168 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27169 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
27171 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
27172 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27173 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
27174 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
27175 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
27179 /* ISA floating-point and Advanced SIMD extensions. */
27180 struct arm_option_fpu_value_table
27183 const arm_feature_set value
;
27186 /* This list should, at a minimum, contain all the fpu names
27187 recognized by GCC. */
27188 static const struct arm_option_fpu_value_table arm_fpus
[] =
27190 {"softfpa", FPU_NONE
},
27191 {"fpe", FPU_ARCH_FPE
},
27192 {"fpe2", FPU_ARCH_FPE
},
27193 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
27194 {"fpa", FPU_ARCH_FPA
},
27195 {"fpa10", FPU_ARCH_FPA
},
27196 {"fpa11", FPU_ARCH_FPA
},
27197 {"arm7500fe", FPU_ARCH_FPA
},
27198 {"softvfp", FPU_ARCH_VFP
},
27199 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
27200 {"vfp", FPU_ARCH_VFP_V2
},
27201 {"vfp9", FPU_ARCH_VFP_V2
},
27202 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
27203 {"vfp10", FPU_ARCH_VFP_V2
},
27204 {"vfp10-r0", FPU_ARCH_VFP_V1
},
27205 {"vfpxd", FPU_ARCH_VFP_V1xD
},
27206 {"vfpv2", FPU_ARCH_VFP_V2
},
27207 {"vfpv3", FPU_ARCH_VFP_V3
},
27208 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
27209 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
27210 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
27211 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
27212 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
27213 {"arm1020t", FPU_ARCH_VFP_V1
},
27214 {"arm1020e", FPU_ARCH_VFP_V2
},
27215 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
27216 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
27217 {"maverick", FPU_ARCH_MAVERICK
},
27218 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27219 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27220 {"neon-fp16", FPU_ARCH_NEON_FP16
},
27221 {"vfpv4", FPU_ARCH_VFP_V4
},
27222 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
27223 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
27224 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
27225 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
27226 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
27227 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
27228 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
27229 {"crypto-neon-fp-armv8",
27230 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
27231 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
27232 {"crypto-neon-fp-armv8.1",
27233 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
27234 {NULL
, ARM_ARCH_NONE
}
27237 struct arm_option_value_table
27243 static const struct arm_option_value_table arm_float_abis
[] =
27245 {"hard", ARM_FLOAT_ABI_HARD
},
27246 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
27247 {"soft", ARM_FLOAT_ABI_SOFT
},
27252 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
27253 static const struct arm_option_value_table arm_eabis
[] =
27255 {"gnu", EF_ARM_EABI_UNKNOWN
},
27256 {"4", EF_ARM_EABI_VER4
},
27257 {"5", EF_ARM_EABI_VER5
},
27262 struct arm_long_option_table
27264 const char * option
; /* Substring to match. */
27265 const char * help
; /* Help information. */
27266 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
27267 const char * deprecated
; /* If non-null, print this message. */
27271 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
27272 arm_feature_set
*ext_set
,
27273 const struct arm_ext_table
*ext_table
)
27275 /* We insist on extensions being specified in alphabetical order, and with
27276 extensions being added before being removed. We achieve this by having
27277 the global ARM_EXTENSIONS table in alphabetical order, and using the
27278 ADDING_VALUE variable to indicate whether we are adding an extension (1)
27279 or removing it (0) and only allowing it to change in the order
27281 const struct arm_option_extension_value_table
* opt
= NULL
;
27282 const arm_feature_set arm_any
= ARM_ANY
;
27283 int adding_value
= -1;
27285 while (str
!= NULL
&& *str
!= 0)
27292 as_bad (_("invalid architectural extension"));
27297 ext
= strchr (str
, '+');
27302 len
= strlen (str
);
27304 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
27306 if (adding_value
!= 0)
27309 opt
= arm_extensions
;
27317 if (adding_value
== -1)
27320 opt
= arm_extensions
;
27322 else if (adding_value
!= 1)
27324 as_bad (_("must specify extensions to add before specifying "
27325 "those to remove"));
27332 as_bad (_("missing architectural extension"));
27336 gas_assert (adding_value
!= -1);
27337 gas_assert (opt
!= NULL
);
27339 if (ext_table
!= NULL
)
27341 const struct arm_ext_table
* ext_opt
= ext_table
;
27342 bfd_boolean found
= FALSE
;
27343 for (; ext_opt
->name
!= NULL
; ext_opt
++)
27344 if (ext_opt
->name_len
== len
27345 && strncmp (ext_opt
->name
, str
, len
) == 0)
27349 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
27350 /* TODO: Option not supported. When we remove the
27351 legacy table this case should error out. */
27354 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
27358 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
27359 /* TODO: Option not supported. When we remove the
27360 legacy table this case should error out. */
27362 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
27374 /* Scan over the options table trying to find an exact match. */
27375 for (; opt
->name
!= NULL
; opt
++)
27376 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27378 int i
, nb_allowed_archs
=
27379 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27380 /* Check we can apply the extension to this architecture. */
27381 for (i
= 0; i
< nb_allowed_archs
; i
++)
27384 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27386 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
27389 if (i
== nb_allowed_archs
)
27391 as_bad (_("extension does not apply to the base architecture"));
27395 /* Add or remove the extension. */
27397 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
27399 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
27401 /* Allowing Thumb division instructions for ARMv7 in autodetection
27402 rely on this break so that duplicate extensions (extensions
27403 with the same name as a previous extension in the list) are not
27404 considered for command-line parsing. */
27408 if (opt
->name
== NULL
)
27410 /* Did we fail to find an extension because it wasn't specified in
27411 alphabetical order, or because it does not exist? */
27413 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27414 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27417 if (opt
->name
== NULL
)
27418 as_bad (_("unknown architectural extension `%s'"), str
);
27420 as_bad (_("architectural extensions must be specified in "
27421 "alphabetical order"));
27427 /* We should skip the extension we've just matched the next time
27439 arm_parse_cpu (const char *str
)
27441 const struct arm_cpu_option_table
*opt
;
27442 const char *ext
= strchr (str
, '+');
27448 len
= strlen (str
);
27452 as_bad (_("missing cpu name `%s'"), str
);
27456 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
27457 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27459 mcpu_cpu_opt
= &opt
->value
;
27460 if (mcpu_ext_opt
== NULL
)
27461 mcpu_ext_opt
= XNEW (arm_feature_set
);
27462 *mcpu_ext_opt
= opt
->ext
;
27463 mcpu_fpu_opt
= &opt
->default_fpu
;
27464 if (opt
->canonical_name
)
27466 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
27467 strcpy (selected_cpu_name
, opt
->canonical_name
);
27473 if (len
>= sizeof selected_cpu_name
)
27474 len
= (sizeof selected_cpu_name
) - 1;
27476 for (i
= 0; i
< len
; i
++)
27477 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27478 selected_cpu_name
[i
] = 0;
27482 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
27487 as_bad (_("unknown cpu `%s'"), str
);
27492 arm_parse_arch (const char *str
)
27494 const struct arm_arch_option_table
*opt
;
27495 const char *ext
= strchr (str
, '+');
27501 len
= strlen (str
);
27505 as_bad (_("missing architecture name `%s'"), str
);
27509 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27510 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27512 march_cpu_opt
= &opt
->value
;
27513 if (march_ext_opt
== NULL
)
27514 march_ext_opt
= XNEW (arm_feature_set
);
27515 *march_ext_opt
= arm_arch_none
;
27516 march_fpu_opt
= &opt
->default_fpu
;
27517 strcpy (selected_cpu_name
, opt
->name
);
27520 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27526 as_bad (_("unknown architecture `%s'\n"), str
);
27531 arm_parse_fpu (const char * str
)
27533 const struct arm_option_fpu_value_table
* opt
;
27535 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27536 if (streq (opt
->name
, str
))
27538 mfpu_opt
= &opt
->value
;
27542 as_bad (_("unknown floating point format `%s'\n"), str
);
27547 arm_parse_float_abi (const char * str
)
27549 const struct arm_option_value_table
* opt
;
27551 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27552 if (streq (opt
->name
, str
))
27554 mfloat_abi_opt
= opt
->value
;
27558 as_bad (_("unknown floating point abi `%s'\n"), str
);
27564 arm_parse_eabi (const char * str
)
27566 const struct arm_option_value_table
*opt
;
27568 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27569 if (streq (opt
->name
, str
))
27571 meabi_flags
= opt
->value
;
27574 as_bad (_("unknown EABI `%s'\n"), str
);
27580 arm_parse_it_mode (const char * str
)
27582 bfd_boolean ret
= TRUE
;
27584 if (streq ("arm", str
))
27585 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27586 else if (streq ("thumb", str
))
27587 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27588 else if (streq ("always", str
))
27589 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27590 else if (streq ("never", str
))
27591 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27594 as_bad (_("unknown implicit IT mode `%s', should be "\
27595 "arm, thumb, always, or never."), str
);
27603 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27605 codecomposer_syntax
= TRUE
;
27606 arm_comment_chars
[0] = ';';
27607 arm_line_separator_chars
[0] = 0;
27611 struct arm_long_option_table arm_long_opts
[] =
27613 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27614 arm_parse_cpu
, NULL
},
27615 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27616 arm_parse_arch
, NULL
},
27617 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27618 arm_parse_fpu
, NULL
},
27619 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27620 arm_parse_float_abi
, NULL
},
27622 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27623 arm_parse_eabi
, NULL
},
27625 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27626 arm_parse_it_mode
, NULL
},
27627 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27628 arm_ccs_mode
, NULL
},
27629 {NULL
, NULL
, 0, NULL
}
27633 md_parse_option (int c
, const char * arg
)
27635 struct arm_option_table
*opt
;
27636 const struct arm_legacy_option_table
*fopt
;
27637 struct arm_long_option_table
*lopt
;
27643 target_big_endian
= 1;
27649 target_big_endian
= 0;
27653 case OPTION_FIX_V4BX
:
27661 #endif /* OBJ_ELF */
27664 /* Listing option. Just ignore these, we don't support additional
27669 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27671 if (c
== opt
->option
[0]
27672 && ((arg
== NULL
&& opt
->option
[1] == 0)
27673 || streq (arg
, opt
->option
+ 1)))
27675 /* If the option is deprecated, tell the user. */
27676 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27677 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27678 arg
? arg
: "", _(opt
->deprecated
));
27680 if (opt
->var
!= NULL
)
27681 *opt
->var
= opt
->value
;
27687 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27689 if (c
== fopt
->option
[0]
27690 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27691 || streq (arg
, fopt
->option
+ 1)))
27693 /* If the option is deprecated, tell the user. */
27694 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27695 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27696 arg
? arg
: "", _(fopt
->deprecated
));
27698 if (fopt
->var
!= NULL
)
27699 *fopt
->var
= &fopt
->value
;
27705 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27707 /* These options are expected to have an argument. */
27708 if (c
== lopt
->option
[0]
27710 && strncmp (arg
, lopt
->option
+ 1,
27711 strlen (lopt
->option
+ 1)) == 0)
27713 /* If the option is deprecated, tell the user. */
27714 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27715 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27716 _(lopt
->deprecated
));
27718 /* Call the sup-option parser. */
27719 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27730 md_show_usage (FILE * fp
)
27732 struct arm_option_table
*opt
;
27733 struct arm_long_option_table
*lopt
;
27735 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27737 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27738 if (opt
->help
!= NULL
)
27739 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27741 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27742 if (lopt
->help
!= NULL
)
27743 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27747 -EB assemble code for a big-endian cpu\n"));
27752 -EL assemble code for a little-endian cpu\n"));
27756 --fix-v4bx Allow BX in ARMv4 code\n"));
27760 --fdpic generate an FDPIC object file\n"));
27761 #endif /* OBJ_ELF */
27769 arm_feature_set flags
;
27770 } cpu_arch_ver_table
;
27772 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27773 chronologically for architectures, with an exception for ARMv6-M and
27774 ARMv6S-M due to legacy reasons. No new architecture should have a
27775 special case. This allows for build attribute selection results to be
27776 stable when new architectures are added. */
27777 static const cpu_arch_ver_table cpu_arch_ver
[] =
27779 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27780 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27781 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27782 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27783 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27784 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27785 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27786 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27787 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27788 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27789 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27790 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27791 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27792 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27793 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27794 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27795 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27796 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27797 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27798 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27799 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27800 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27801 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27802 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27804 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27805 always selected build attributes to match those of ARMv6-M
27806 (resp. ARMv6S-M). However, due to these architectures being a strict
27807 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27808 would be selected when fully respecting chronology of architectures.
27809 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27810 move them before ARMv7 architectures. */
27811 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27812 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27814 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27815 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27816 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27817 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27818 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27819 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27820 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27821 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27822 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27823 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27824 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27825 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27826 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27827 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27828 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27829 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27830 {-1, ARM_ARCH_NONE
}
27833 /* Set an attribute if it has not already been set by the user. */
27836 aeabi_set_attribute_int (int tag
, int value
)
27839 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27840 || !attributes_set_explicitly
[tag
])
27841 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27845 aeabi_set_attribute_string (int tag
, const char *value
)
27848 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27849 || !attributes_set_explicitly
[tag
])
27850 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27853 /* Return whether features in the *NEEDED feature set are available via
27854 extensions for the architecture whose feature set is *ARCH_FSET. */
27857 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27858 const arm_feature_set
*needed
)
27860 int i
, nb_allowed_archs
;
27861 arm_feature_set ext_fset
;
27862 const struct arm_option_extension_value_table
*opt
;
27864 ext_fset
= arm_arch_none
;
27865 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27867 /* Extension does not provide any feature we need. */
27868 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27872 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27873 for (i
= 0; i
< nb_allowed_archs
; i
++)
27876 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27879 /* Extension is available, add it. */
27880 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27881 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27885 /* Can we enable all features in *needed? */
27886 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27889 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27890 a given architecture feature set *ARCH_EXT_FSET including extension feature
27891 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27892 - if true, check for an exact match of the architecture modulo extensions;
27893 - otherwise, select build attribute value of the first superset
27894 architecture released so that results remains stable when new architectures
27896 For -march/-mcpu=all the build attribute value of the most featureful
27897 architecture is returned. Tag_CPU_arch_profile result is returned in
27901 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27902 const arm_feature_set
*ext_fset
,
27903 char *profile
, int exact_match
)
27905 arm_feature_set arch_fset
;
27906 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27908 /* Select most featureful architecture with all its extensions if building
27909 for -march=all as the feature sets used to set build attributes. */
27910 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27912 /* Force revisiting of decision for each new architecture. */
27913 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27915 return TAG_CPU_ARCH_V8
;
27918 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27920 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27922 arm_feature_set known_arch_fset
;
27924 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27927 /* Base architecture match user-specified architecture and
27928 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27929 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27934 /* Base architecture match user-specified architecture only
27935 (eg. ARMv6-M in the same case as above). Record it in case we
27936 find a match with above condition. */
27937 else if (p_ver_ret
== NULL
27938 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27944 /* Architecture has all features wanted. */
27945 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27947 arm_feature_set added_fset
;
27949 /* Compute features added by this architecture over the one
27950 recorded in p_ver_ret. */
27951 if (p_ver_ret
!= NULL
)
27952 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27954 /* First architecture that match incl. with extensions, or the
27955 only difference in features over the recorded match is
27956 features that were optional and are now mandatory. */
27957 if (p_ver_ret
== NULL
27958 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27964 else if (p_ver_ret
== NULL
)
27966 arm_feature_set needed_ext_fset
;
27968 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27970 /* Architecture has all features needed when using some
27971 extensions. Record it and continue searching in case there
27972 exist an architecture providing all needed features without
27973 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27975 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27982 if (p_ver_ret
== NULL
)
27986 /* Tag_CPU_arch_profile. */
27987 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27988 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27989 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27990 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27992 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27994 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27998 return p_ver_ret
->val
;
28001 /* Set the public EABI object attributes. */
28004 aeabi_set_public_attributes (void)
28006 char profile
= '\0';
28009 int fp16_optional
= 0;
28010 int skip_exact_match
= 0;
28011 arm_feature_set flags
, flags_arch
, flags_ext
;
28013 /* Autodetection mode, choose the architecture based the instructions
28015 if (no_cpu_selected ())
28017 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
28019 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
28020 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
28022 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
28023 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
28025 /* Code run during relaxation relies on selected_cpu being set. */
28026 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28027 flags_ext
= arm_arch_none
;
28028 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
28029 selected_ext
= flags_ext
;
28030 selected_cpu
= flags
;
28032 /* Otherwise, choose the architecture based on the capabilities of the
28036 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
28037 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
28038 flags_ext
= selected_ext
;
28039 flags
= selected_cpu
;
28041 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
28043 /* Allow the user to override the reported architecture. */
28044 if (!ARM_FEATURE_ZERO (selected_object_arch
))
28046 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
28047 flags_ext
= arm_arch_none
;
28050 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
28052 /* When this function is run again after relaxation has happened there is no
28053 way to determine whether an architecture or CPU was specified by the user:
28054 - selected_cpu is set above for relaxation to work;
28055 - march_cpu_opt is not set if only -mcpu or .cpu is used;
28056 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
28057 Therefore, if not in -march=all case we first try an exact match and fall
28058 back to autodetection. */
28059 if (!skip_exact_match
)
28060 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
28062 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
28064 as_bad (_("no architecture contains all the instructions used\n"));
28066 /* Tag_CPU_name. */
28067 if (selected_cpu_name
[0])
28071 q
= selected_cpu_name
;
28072 if (strncmp (q
, "armv", 4) == 0)
28077 for (i
= 0; q
[i
]; i
++)
28078 q
[i
] = TOUPPER (q
[i
]);
28080 aeabi_set_attribute_string (Tag_CPU_name
, q
);
28083 /* Tag_CPU_arch. */
28084 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
28086 /* Tag_CPU_arch_profile. */
28087 if (profile
!= '\0')
28088 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
28090 /* Tag_DSP_extension. */
28091 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
28092 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
28094 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28095 /* Tag_ARM_ISA_use. */
28096 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
28097 || ARM_FEATURE_ZERO (flags_arch
))
28098 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
28100 /* Tag_THUMB_ISA_use. */
28101 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
28102 || ARM_FEATURE_ZERO (flags_arch
))
28106 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28107 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
28109 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
28113 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
28116 /* Tag_VFP_arch. */
28117 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
28118 aeabi_set_attribute_int (Tag_VFP_arch
,
28119 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28121 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
28122 aeabi_set_attribute_int (Tag_VFP_arch
,
28123 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28125 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
28128 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
28130 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
28132 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
28135 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
28136 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
28137 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
28138 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
28139 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
28141 /* Tag_ABI_HardFP_use. */
28142 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
28143 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
28144 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
28146 /* Tag_WMMX_arch. */
28147 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
28148 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
28149 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
28150 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
28152 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
28153 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
28154 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
28155 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
28156 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
28157 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
28159 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
28161 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
28165 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
28170 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
28171 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
28172 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
28176 We set Tag_DIV_use to two when integer divide instructions have been used
28177 in ARM state, or when Thumb integer divide instructions have been used,
28178 but we have no architecture profile set, nor have we any ARM instructions.
28180 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
28181 by the base architecture.
28183 For new architectures we will have to check these tests. */
28184 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
28185 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28186 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
28187 aeabi_set_attribute_int (Tag_DIV_use
, 0);
28188 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
28189 || (profile
== '\0'
28190 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
28191 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
28192 aeabi_set_attribute_int (Tag_DIV_use
, 2);
28194 /* Tag_MP_extension_use. */
28195 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
28196 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
28198 /* Tag Virtualization_use. */
28199 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
28201 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
28204 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
28207 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
28208 finished and free extension feature bits which will not be used anymore. */
28211 arm_md_post_relax (void)
28213 aeabi_set_public_attributes ();
28214 XDELETE (mcpu_ext_opt
);
28215 mcpu_ext_opt
= NULL
;
28216 XDELETE (march_ext_opt
);
28217 march_ext_opt
= NULL
;
28220 /* Add the default contents for the .ARM.attributes section. */
28225 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28228 aeabi_set_public_attributes ();
28230 #endif /* OBJ_ELF */
28232 /* Parse a .cpu directive. */
28235 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
28237 const struct arm_cpu_option_table
*opt
;
28241 name
= input_line_pointer
;
28242 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28243 input_line_pointer
++;
28244 saved_char
= *input_line_pointer
;
28245 *input_line_pointer
= 0;
28247 /* Skip the first "all" entry. */
28248 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
28249 if (streq (opt
->name
, name
))
28251 selected_arch
= opt
->value
;
28252 selected_ext
= opt
->ext
;
28253 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28254 if (opt
->canonical_name
)
28255 strcpy (selected_cpu_name
, opt
->canonical_name
);
28259 for (i
= 0; opt
->name
[i
]; i
++)
28260 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
28262 selected_cpu_name
[i
] = 0;
28264 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28266 *input_line_pointer
= saved_char
;
28267 demand_empty_rest_of_line ();
28270 as_bad (_("unknown cpu `%s'"), name
);
28271 *input_line_pointer
= saved_char
;
28272 ignore_rest_of_line ();
28275 /* Parse a .arch directive. */
28278 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
28280 const struct arm_arch_option_table
*opt
;
28284 name
= input_line_pointer
;
28285 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28286 input_line_pointer
++;
28287 saved_char
= *input_line_pointer
;
28288 *input_line_pointer
= 0;
28290 /* Skip the first "all" entry. */
28291 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28292 if (streq (opt
->name
, name
))
28294 selected_arch
= opt
->value
;
28295 selected_ext
= arm_arch_none
;
28296 selected_cpu
= selected_arch
;
28297 strcpy (selected_cpu_name
, opt
->name
);
28298 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28299 *input_line_pointer
= saved_char
;
28300 demand_empty_rest_of_line ();
28304 as_bad (_("unknown architecture `%s'\n"), name
);
28305 *input_line_pointer
= saved_char
;
28306 ignore_rest_of_line ();
28309 /* Parse a .object_arch directive. */
28312 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
28314 const struct arm_arch_option_table
*opt
;
28318 name
= input_line_pointer
;
28319 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28320 input_line_pointer
++;
28321 saved_char
= *input_line_pointer
;
28322 *input_line_pointer
= 0;
28324 /* Skip the first "all" entry. */
28325 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28326 if (streq (opt
->name
, name
))
28328 selected_object_arch
= opt
->value
;
28329 *input_line_pointer
= saved_char
;
28330 demand_empty_rest_of_line ();
28334 as_bad (_("unknown architecture `%s'\n"), name
);
28335 *input_line_pointer
= saved_char
;
28336 ignore_rest_of_line ();
28339 /* Parse a .arch_extension directive. */
28342 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
28344 const struct arm_option_extension_value_table
*opt
;
28347 int adding_value
= 1;
28349 name
= input_line_pointer
;
28350 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28351 input_line_pointer
++;
28352 saved_char
= *input_line_pointer
;
28353 *input_line_pointer
= 0;
28355 if (strlen (name
) >= 2
28356 && strncmp (name
, "no", 2) == 0)
28362 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28363 if (streq (opt
->name
, name
))
28365 int i
, nb_allowed_archs
=
28366 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
28367 for (i
= 0; i
< nb_allowed_archs
; i
++)
28370 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
28372 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
28376 if (i
== nb_allowed_archs
)
28378 as_bad (_("architectural extension `%s' is not allowed for the "
28379 "current base architecture"), name
);
28384 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
28387 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
28389 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28390 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28391 *input_line_pointer
= saved_char
;
28392 demand_empty_rest_of_line ();
28393 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
28394 on this return so that duplicate extensions (extensions with the
28395 same name as a previous extension in the list) are not considered
28396 for command-line parsing. */
28400 if (opt
->name
== NULL
)
28401 as_bad (_("unknown architecture extension `%s'\n"), name
);
28403 *input_line_pointer
= saved_char
;
28404 ignore_rest_of_line ();
28407 /* Parse a .fpu directive. */
28410 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
28412 const struct arm_option_fpu_value_table
*opt
;
28416 name
= input_line_pointer
;
28417 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28418 input_line_pointer
++;
28419 saved_char
= *input_line_pointer
;
28420 *input_line_pointer
= 0;
28422 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
28423 if (streq (opt
->name
, name
))
28425 selected_fpu
= opt
->value
;
28426 #ifndef CPU_DEFAULT
28427 if (no_cpu_selected ())
28428 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28431 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28432 *input_line_pointer
= saved_char
;
28433 demand_empty_rest_of_line ();
28437 as_bad (_("unknown floating point format `%s'\n"), name
);
28438 *input_line_pointer
= saved_char
;
28439 ignore_rest_of_line ();
28442 /* Copy symbol information. */
28445 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
28447 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
28451 /* Given a symbolic attribute NAME, return the proper integer value.
28452 Returns -1 if the attribute is not known. */
28455 arm_convert_symbolic_attribute (const char *name
)
28457 static const struct
28462 attribute_table
[] =
28464 /* When you modify this table you should
28465 also modify the list in doc/c-arm.texi. */
28466 #define T(tag) {#tag, tag}
28467 T (Tag_CPU_raw_name
),
28470 T (Tag_CPU_arch_profile
),
28471 T (Tag_ARM_ISA_use
),
28472 T (Tag_THUMB_ISA_use
),
28476 T (Tag_Advanced_SIMD_arch
),
28477 T (Tag_PCS_config
),
28478 T (Tag_ABI_PCS_R9_use
),
28479 T (Tag_ABI_PCS_RW_data
),
28480 T (Tag_ABI_PCS_RO_data
),
28481 T (Tag_ABI_PCS_GOT_use
),
28482 T (Tag_ABI_PCS_wchar_t
),
28483 T (Tag_ABI_FP_rounding
),
28484 T (Tag_ABI_FP_denormal
),
28485 T (Tag_ABI_FP_exceptions
),
28486 T (Tag_ABI_FP_user_exceptions
),
28487 T (Tag_ABI_FP_number_model
),
28488 T (Tag_ABI_align_needed
),
28489 T (Tag_ABI_align8_needed
),
28490 T (Tag_ABI_align_preserved
),
28491 T (Tag_ABI_align8_preserved
),
28492 T (Tag_ABI_enum_size
),
28493 T (Tag_ABI_HardFP_use
),
28494 T (Tag_ABI_VFP_args
),
28495 T (Tag_ABI_WMMX_args
),
28496 T (Tag_ABI_optimization_goals
),
28497 T (Tag_ABI_FP_optimization_goals
),
28498 T (Tag_compatibility
),
28499 T (Tag_CPU_unaligned_access
),
28500 T (Tag_FP_HP_extension
),
28501 T (Tag_VFP_HP_extension
),
28502 T (Tag_ABI_FP_16bit_format
),
28503 T (Tag_MPextension_use
),
28505 T (Tag_nodefaults
),
28506 T (Tag_also_compatible_with
),
28507 T (Tag_conformance
),
28509 T (Tag_Virtualization_use
),
28510 T (Tag_DSP_extension
),
28511 /* We deliberately do not include Tag_MPextension_use_legacy. */
28519 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28520 if (streq (name
, attribute_table
[i
].name
))
28521 return attribute_table
[i
].tag
;
28526 /* Apply sym value for relocations only in the case that they are for
28527 local symbols in the same segment as the fixup and you have the
28528 respective architectural feature for blx and simple switches. */
28531 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28534 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28535 /* PR 17444: If the local symbol is in a different section then a reloc
28536 will always be generated for it, so applying the symbol value now
28537 will result in a double offset being stored in the relocation. */
28538 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28539 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28541 switch (fixP
->fx_r_type
)
28543 case BFD_RELOC_ARM_PCREL_BLX
:
28544 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28545 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28549 case BFD_RELOC_ARM_PCREL_CALL
:
28550 case BFD_RELOC_THUMB_PCREL_BLX
:
28551 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28562 #endif /* OBJ_ELF */