1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
237 static const arm_feature_set arm_ext_v8_3
=
238 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
240 static const arm_feature_set arm_arch_any
= ARM_ANY
;
241 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
242 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
243 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
245 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
248 static const arm_feature_set arm_cext_iwmmxt2
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
250 static const arm_feature_set arm_cext_iwmmxt
=
251 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
252 static const arm_feature_set arm_cext_xscale
=
253 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
254 static const arm_feature_set arm_cext_maverick
=
255 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
256 static const arm_feature_set fpu_fpa_ext_v1
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
258 static const arm_feature_set fpu_fpa_ext_v2
=
259 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
260 static const arm_feature_set fpu_vfp_ext_v1xd
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
262 static const arm_feature_set fpu_vfp_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
264 static const arm_feature_set fpu_vfp_ext_v2
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
266 static const arm_feature_set fpu_vfp_ext_v3xd
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
268 static const arm_feature_set fpu_vfp_ext_v3
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
270 static const arm_feature_set fpu_vfp_ext_d32
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
272 static const arm_feature_set fpu_neon_ext_v1
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
274 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
275 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
277 static const arm_feature_set fpu_vfp_fp16
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
279 static const arm_feature_set fpu_neon_ext_fma
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
284 static const arm_feature_set fpu_vfp_ext_armv8
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
286 static const arm_feature_set fpu_vfp_ext_armv8xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
288 static const arm_feature_set fpu_neon_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
290 static const arm_feature_set fpu_crypto_ext_armv8
=
291 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
292 static const arm_feature_set crc_ext_armv8
=
293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
294 static const arm_feature_set fpu_neon_ext_v8_1
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static int mfloat_abi_opt
= -1;
298 /* Record user cpu selection for object attributes. */
299 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
300 /* Must be long enough to hold any of the names in arm_cpus. */
301 static char selected_cpu_name
[20];
303 extern FLONUM_TYPE generic_floating_point_number
;
305 /* Return if no cpu was selected on command-line. */
307 no_cpu_selected (void)
309 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
314 static int meabi_flags
= EABI_DEFAULT
;
316 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
319 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
324 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
330 symbolS
* GOT_symbol
;
333 /* 0: assemble for ARM,
334 1: assemble for Thumb,
335 2: assemble for Thumb even though target CPU does not support thumb
337 static int thumb_mode
= 0;
338 /* A value distinct from the possible values for thumb_mode that we
339 can use to record whether thumb_mode has been copied into the
340 tc_frag_data field of a frag. */
341 #define MODE_RECORDED (1 << 4)
343 /* Specifies the intrinsic IT insn behavior mode. */
344 enum implicit_it_mode
346 IMPLICIT_IT_MODE_NEVER
= 0x00,
347 IMPLICIT_IT_MODE_ARM
= 0x01,
348 IMPLICIT_IT_MODE_THUMB
= 0x02,
349 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
351 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
353 /* If unified_syntax is true, we are processing the new unified
354 ARM/Thumb syntax. Important differences from the old ARM mode:
356 - Immediate operands do not require a # prefix.
357 - Conditional affixes always appear at the end of the
358 instruction. (For backward compatibility, those instructions
359 that formerly had them in the middle, continue to accept them
361 - The IT instruction may appear, and if it does is validated
362 against subsequent conditional affixes. It does not generate
365 Important differences from the old Thumb mode:
367 - Immediate operands do not require a # prefix.
368 - Most of the V6T2 instructions are only available in unified mode.
369 - The .N and .W suffixes are recognized and honored (it is an error
370 if they cannot be honored).
371 - All instructions set the flags if and only if they have an 's' affix.
372 - Conditional affixes may be used. They are validated against
373 preceding IT instructions. Unlike ARM mode, you cannot use a
374 conditional affix except in the scope of an IT instruction. */
376 static bfd_boolean unified_syntax
= FALSE
;
378 /* An immediate operand can start with #, and ld*, st*, pld operands
379 can contain [ and ]. We need to tell APP not to elide whitespace
380 before a [, which can appear as the first operand for pld.
381 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
382 const char arm_symbol_chars
[] = "#[]{}";
397 enum neon_el_type type
;
401 #define NEON_MAX_TYPE_ELS 4
405 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
409 enum it_instruction_type
414 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
415 if inside, should be the last one. */
416 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
417 i.e. BKPT and NOP. */
418 IT_INSN
/* The IT insn has been parsed. */
421 /* The maximum number of operands we need. */
422 #define ARM_IT_MAX_OPERANDS 6
427 unsigned long instruction
;
431 /* "uncond_value" is set to the value in place of the conditional field in
432 unconditional versions of the instruction, or -1 if nothing is
435 struct neon_type vectype
;
436 /* This does not indicate an actual NEON instruction, only that
437 the mnemonic accepts neon-style type suffixes. */
439 /* Set to the opcode if the instruction needs relaxation.
440 Zero if the instruction is not relaxed. */
444 bfd_reloc_code_real_type type
;
449 enum it_instruction_type it_insn_type
;
455 struct neon_type_el vectype
;
456 unsigned present
: 1; /* Operand present. */
457 unsigned isreg
: 1; /* Operand was a register. */
458 unsigned immisreg
: 1; /* .imm field is a second register. */
459 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
460 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
461 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
462 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 instructions. This allows us to disambiguate ARM <-> vector insns. */
464 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
465 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
466 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
467 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
468 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
469 unsigned writeback
: 1; /* Operand has trailing ! */
470 unsigned preind
: 1; /* Preindexed address. */
471 unsigned postind
: 1; /* Postindexed address. */
472 unsigned negative
: 1; /* Index register was negated. */
473 unsigned shifted
: 1; /* Shift applied to operation. */
474 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
475 } operands
[ARM_IT_MAX_OPERANDS
];
478 static struct arm_it inst
;
480 #define NUM_FLOAT_VALS 8
482 const char * fp_const
[] =
484 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
487 /* Number of littlenums required to hold an extended precision number. */
488 #define MAX_LITTLENUMS 6
490 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
500 #define CP_T_X 0x00008000
501 #define CP_T_Y 0x00400000
503 #define CONDS_BIT 0x00100000
504 #define LOAD_BIT 0x00100000
506 #define DOUBLE_LOAD_FLAG 0x00000001
510 const char * template_name
;
514 #define COND_ALWAYS 0xE
518 const char * template_name
;
522 struct asm_barrier_opt
524 const char * template_name
;
526 const arm_feature_set arch
;
529 /* The bit that distinguishes CPSR and SPSR. */
530 #define SPSR_BIT (1 << 22)
532 /* The individual PSR flag bits. */
533 #define PSR_c (1 << 16)
534 #define PSR_x (1 << 17)
535 #define PSR_s (1 << 18)
536 #define PSR_f (1 << 19)
541 bfd_reloc_code_real_type reloc
;
546 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
547 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
552 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
555 /* Bits for DEFINED field in neon_typed_alias. */
556 #define NTA_HASTYPE 1
557 #define NTA_HASINDEX 2
559 struct neon_typed_alias
561 unsigned char defined
;
563 struct neon_type_el eltype
;
566 /* ARM register categories. This includes coprocessor numbers and various
567 architecture extensions' registers. */
594 /* Structure for a hash table entry for a register.
595 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
596 information which states whether a vector type or index is specified (for a
597 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
603 unsigned char builtin
;
604 struct neon_typed_alias
* neon
;
607 /* Diagnostics used when we don't get a register of the expected type. */
608 const char * const reg_expected_msgs
[] =
610 N_("ARM register expected"),
611 N_("bad or missing co-processor number"),
612 N_("co-processor register expected"),
613 N_("FPA register expected"),
614 N_("VFP single precision register expected"),
615 N_("VFP/Neon double precision register expected"),
616 N_("Neon quad precision register expected"),
617 N_("VFP single or double precision register expected"),
618 N_("Neon double or quad precision register expected"),
619 N_("VFP single, double or Neon quad precision register expected"),
620 N_("VFP system register expected"),
621 N_("Maverick MVF register expected"),
622 N_("Maverick MVD register expected"),
623 N_("Maverick MVFX register expected"),
624 N_("Maverick MVDX register expected"),
625 N_("Maverick MVAX register expected"),
626 N_("Maverick DSPSC register expected"),
627 N_("iWMMXt data register expected"),
628 N_("iWMMXt control register expected"),
629 N_("iWMMXt scalar register expected"),
630 N_("XScale accumulator register expected"),
633 /* Some well known registers that we refer to directly elsewhere. */
639 /* ARM instructions take 4bytes in the object file, Thumb instructions
645 /* Basic string to match. */
646 const char * template_name
;
648 /* Parameters to instruction. */
649 unsigned int operands
[8];
651 /* Conditional tag - see opcode_lookup. */
652 unsigned int tag
: 4;
654 /* Basic instruction code. */
655 unsigned int avalue
: 28;
657 /* Thumb-format instruction code. */
660 /* Which architecture variant provides this instruction. */
661 const arm_feature_set
* avariant
;
662 const arm_feature_set
* tvariant
;
664 /* Function to call to encode instruction in ARM format. */
665 void (* aencode
) (void);
667 /* Function to call to encode instruction in Thumb format. */
668 void (* tencode
) (void);
671 /* Defines for various bits that we will want to toggle. */
672 #define INST_IMMEDIATE 0x02000000
673 #define OFFSET_REG 0x02000000
674 #define HWOFFSET_IMM 0x00400000
675 #define SHIFT_BY_REG 0x00000010
676 #define PRE_INDEX 0x01000000
677 #define INDEX_UP 0x00800000
678 #define WRITE_BACK 0x00200000
679 #define LDM_TYPE_2_OR_3 0x00400000
680 #define CPSI_MMOD 0x00020000
682 #define LITERAL_MASK 0xf000f000
683 #define OPCODE_MASK 0xfe1fffff
684 #define V4_STR_BIT 0x00000020
685 #define VLDR_VMOV_SAME 0x0040f000
687 #define T2_SUBS_PC_LR 0xf3de8f00
689 #define DATA_OP_SHIFT 21
690 #define SBIT_SHIFT 20
692 #define T2_OPCODE_MASK 0xfe1fffff
693 #define T2_DATA_OP_SHIFT 21
694 #define T2_SBIT_SHIFT 20
696 #define A_COND_MASK 0xf0000000
697 #define A_PUSH_POP_OP_MASK 0x0fff0000
699 /* Opcodes for pushing/poping registers to/from the stack. */
700 #define A1_OPCODE_PUSH 0x092d0000
701 #define A2_OPCODE_PUSH 0x052d0004
702 #define A2_OPCODE_POP 0x049d0004
704 /* Codes to distinguish the arithmetic instructions. */
715 #define OPCODE_CMP 10
716 #define OPCODE_CMN 11
717 #define OPCODE_ORR 12
718 #define OPCODE_MOV 13
719 #define OPCODE_BIC 14
720 #define OPCODE_MVN 15
722 #define T2_OPCODE_AND 0
723 #define T2_OPCODE_BIC 1
724 #define T2_OPCODE_ORR 2
725 #define T2_OPCODE_ORN 3
726 #define T2_OPCODE_EOR 4
727 #define T2_OPCODE_ADD 8
728 #define T2_OPCODE_ADC 10
729 #define T2_OPCODE_SBC 11
730 #define T2_OPCODE_SUB 13
731 #define T2_OPCODE_RSB 14
733 #define T_OPCODE_MUL 0x4340
734 #define T_OPCODE_TST 0x4200
735 #define T_OPCODE_CMN 0x42c0
736 #define T_OPCODE_NEG 0x4240
737 #define T_OPCODE_MVN 0x43c0
739 #define T_OPCODE_ADD_R3 0x1800
740 #define T_OPCODE_SUB_R3 0x1a00
741 #define T_OPCODE_ADD_HI 0x4400
742 #define T_OPCODE_ADD_ST 0xb000
743 #define T_OPCODE_SUB_ST 0xb080
744 #define T_OPCODE_ADD_SP 0xa800
745 #define T_OPCODE_ADD_PC 0xa000
746 #define T_OPCODE_ADD_I8 0x3000
747 #define T_OPCODE_SUB_I8 0x3800
748 #define T_OPCODE_ADD_I3 0x1c00
749 #define T_OPCODE_SUB_I3 0x1e00
751 #define T_OPCODE_ASR_R 0x4100
752 #define T_OPCODE_LSL_R 0x4080
753 #define T_OPCODE_LSR_R 0x40c0
754 #define T_OPCODE_ROR_R 0x41c0
755 #define T_OPCODE_ASR_I 0x1000
756 #define T_OPCODE_LSL_I 0x0000
757 #define T_OPCODE_LSR_I 0x0800
759 #define T_OPCODE_MOV_I8 0x2000
760 #define T_OPCODE_CMP_I8 0x2800
761 #define T_OPCODE_CMP_LR 0x4280
762 #define T_OPCODE_MOV_HR 0x4600
763 #define T_OPCODE_CMP_HR 0x4500
765 #define T_OPCODE_LDR_PC 0x4800
766 #define T_OPCODE_LDR_SP 0x9800
767 #define T_OPCODE_STR_SP 0x9000
768 #define T_OPCODE_LDR_IW 0x6800
769 #define T_OPCODE_STR_IW 0x6000
770 #define T_OPCODE_LDR_IH 0x8800
771 #define T_OPCODE_STR_IH 0x8000
772 #define T_OPCODE_LDR_IB 0x7800
773 #define T_OPCODE_STR_IB 0x7000
774 #define T_OPCODE_LDR_RW 0x5800
775 #define T_OPCODE_STR_RW 0x5000
776 #define T_OPCODE_LDR_RH 0x5a00
777 #define T_OPCODE_STR_RH 0x5200
778 #define T_OPCODE_LDR_RB 0x5c00
779 #define T_OPCODE_STR_RB 0x5400
781 #define T_OPCODE_PUSH 0xb400
782 #define T_OPCODE_POP 0xbc00
784 #define T_OPCODE_BRANCH 0xe000
786 #define THUMB_SIZE 2 /* Size of thumb instruction. */
787 #define THUMB_PP_PC_LR 0x0100
788 #define THUMB_LOAD_BIT 0x0800
789 #define THUMB2_LOAD_BIT 0x00100000
791 #define BAD_ARGS _("bad arguments to instruction")
792 #define BAD_SP _("r13 not allowed here")
793 #define BAD_PC _("r15 not allowed here")
794 #define BAD_COND _("instruction cannot be conditional")
795 #define BAD_OVERLAP _("registers may not be the same")
796 #define BAD_HIREG _("lo register required")
797 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
798 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
799 #define BAD_BRANCH _("branch must be last instruction in IT block")
800 #define BAD_NOT_IT _("instruction not allowed in IT block")
801 #define BAD_FPU _("selected FPU does not support instruction")
802 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
803 #define BAD_IT_COND _("incorrect condition in IT block")
804 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
805 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
806 #define BAD_PC_ADDRESSING \
807 _("cannot use register index with PC-relative addressing")
808 #define BAD_PC_WRITEBACK \
809 _("cannot use writeback with PC-relative addressing")
810 #define BAD_RANGE _("branch out of range")
811 #define BAD_FP16 _("selected processor does not support fp16 instruction")
812 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
813 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
815 static struct hash_control
* arm_ops_hsh
;
816 static struct hash_control
* arm_cond_hsh
;
817 static struct hash_control
* arm_shift_hsh
;
818 static struct hash_control
* arm_psr_hsh
;
819 static struct hash_control
* arm_v7m_psr_hsh
;
820 static struct hash_control
* arm_reg_hsh
;
821 static struct hash_control
* arm_reloc_hsh
;
822 static struct hash_control
* arm_barrier_opt_hsh
;
824 /* Stuff needed to resolve the label ambiguity
833 symbolS
* last_label_seen
;
834 static int label_is_thumb_function_name
= FALSE
;
836 /* Literal pool structure. Held on a per-section
837 and per-sub-section basis. */
839 #define MAX_LITERAL_POOL_SIZE 1024
840 typedef struct literal_pool
842 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
843 unsigned int next_free_entry
;
849 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
851 struct literal_pool
* next
;
852 unsigned int alignment
;
855 /* Pointer to a linked list of literal pools. */
856 literal_pool
* list_of_pools
= NULL
;
858 typedef enum asmfunc_states
861 WAITING_ASMFUNC_NAME
,
865 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
868 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
870 static struct current_it now_it
;
874 now_it_compatible (int cond
)
876 return (cond
& ~1) == (now_it
.cc
& ~1);
880 conditional_insn (void)
882 return inst
.cond
!= COND_ALWAYS
;
885 static int in_it_block (void);
887 static int handle_it_state (void);
889 static void force_automatic_it_block_close (void);
891 static void it_fsm_post_encode (void);
893 #define set_it_insn_type(type) \
896 inst.it_insn_type = type; \
897 if (handle_it_state () == FAIL) \
902 #define set_it_insn_type_nonvoid(type, failret) \
905 inst.it_insn_type = type; \
906 if (handle_it_state () == FAIL) \
911 #define set_it_insn_type_last() \
914 if (inst.cond == COND_ALWAYS) \
915 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
917 set_it_insn_type (INSIDE_IT_LAST_INSN); \
923 /* This array holds the chars that always start a comment. If the
924 pre-processor is disabled, these aren't very useful. */
925 char arm_comment_chars
[] = "@";
927 /* This array holds the chars that only start a comment at the beginning of
928 a line. If the line seems to have the form '# 123 filename'
929 .line and .file directives will appear in the pre-processed output. */
930 /* Note that input_file.c hand checks for '#' at the beginning of the
931 first line of the input file. This is because the compiler outputs
932 #NO_APP at the beginning of its output. */
933 /* Also note that comments like this one will always work. */
934 const char line_comment_chars
[] = "#";
936 char arm_line_separator_chars
[] = ";";
938 /* Chars that can be used to separate mant
939 from exp in floating point numbers. */
940 const char EXP_CHARS
[] = "eE";
942 /* Chars that mean this number is a floating point constant. */
946 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
948 /* Prefix characters that indicate the start of an immediate
950 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
952 /* Separator character handling. */
954 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
957 skip_past_char (char ** str
, char c
)
959 /* PR gas/14987: Allow for whitespace before the expected character. */
960 skip_whitespace (*str
);
971 #define skip_past_comma(str) skip_past_char (str, ',')
973 /* Arithmetic expressions (possibly involving symbols). */
975 /* Return TRUE if anything in the expression is a bignum. */
978 walk_no_bignums (symbolS
* sp
)
980 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
983 if (symbol_get_value_expression (sp
)->X_add_symbol
)
985 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
986 || (symbol_get_value_expression (sp
)->X_op_symbol
987 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
993 static int in_my_get_expression
= 0;
995 /* Third argument to my_get_expression. */
996 #define GE_NO_PREFIX 0
997 #define GE_IMM_PREFIX 1
998 #define GE_OPT_PREFIX 2
999 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1000 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1001 #define GE_OPT_PREFIX_BIG 3
1004 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1009 /* In unified syntax, all prefixes are optional. */
1011 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1014 switch (prefix_mode
)
1016 case GE_NO_PREFIX
: break;
1018 if (!is_immediate_prefix (**str
))
1020 inst
.error
= _("immediate expression requires a # prefix");
1026 case GE_OPT_PREFIX_BIG
:
1027 if (is_immediate_prefix (**str
))
1033 memset (ep
, 0, sizeof (expressionS
));
1035 save_in
= input_line_pointer
;
1036 input_line_pointer
= *str
;
1037 in_my_get_expression
= 1;
1038 seg
= expression (ep
);
1039 in_my_get_expression
= 0;
1041 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1043 /* We found a bad or missing expression in md_operand(). */
1044 *str
= input_line_pointer
;
1045 input_line_pointer
= save_in
;
1046 if (inst
.error
== NULL
)
1047 inst
.error
= (ep
->X_op
== O_absent
1048 ? _("missing expression") :_("bad expression"));
1053 if (seg
!= absolute_section
1054 && seg
!= text_section
1055 && seg
!= data_section
1056 && seg
!= bss_section
1057 && seg
!= undefined_section
)
1059 inst
.error
= _("bad segment");
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1068 /* Get rid of any bignums now, so that we don't generate an error for which
1069 we can't establish a line number later on. Big numbers are never valid
1070 in instructions, which is where this routine is always called. */
1071 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1072 && (ep
->X_op
== O_big
1073 || (ep
->X_add_symbol
1074 && (walk_no_bignums (ep
->X_add_symbol
)
1076 && walk_no_bignums (ep
->X_op_symbol
))))))
1078 inst
.error
= _("invalid constant");
1079 *str
= input_line_pointer
;
1080 input_line_pointer
= save_in
;
1084 *str
= input_line_pointer
;
1085 input_line_pointer
= save_in
;
1089 /* Turn a string in input_line_pointer into a floating point constant
1090 of type TYPE, and store the appropriate bytes in *LITP. The number
1091 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1092 returned, or NULL on OK.
1094 Note that fp constants aren't represent in the normal way on the ARM.
1095 In big endian mode, things are as expected. However, in little endian
1096 mode fp constants are big-endian word-wise, and little-endian byte-wise
1097 within the words. For example, (double) 1.1 in big endian mode is
1098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1099 the byte sequence 99 99 f1 3f 9a 99 99 99.
1101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1104 md_atof (int type
, char * litP
, int * sizeP
)
1107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1139 return _("Unrecognized or unsupported floating point constant");
1142 t
= atof_ieee (input_line_pointer
, type
, words
);
1144 input_line_pointer
= t
;
1145 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1147 if (target_big_endian
)
1149 for (i
= 0; i
< prec
; i
++)
1151 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1152 litP
+= sizeof (LITTLENUM_TYPE
);
1157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1158 for (i
= prec
- 1; i
>= 0; i
--)
1160 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1161 litP
+= sizeof (LITTLENUM_TYPE
);
1164 /* For a 4 byte float the order of elements in `words' is 1 0.
1165 For an 8 byte float the order is 1 0 3 2. */
1166 for (i
= 0; i
< prec
; i
+= 2)
1168 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1169 sizeof (LITTLENUM_TYPE
));
1170 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1171 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1172 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1179 /* We handle all bad expressions here, so that we can report the faulty
1180 instruction in the error message. */
1182 md_operand (expressionS
* exp
)
1184 if (in_my_get_expression
)
1185 exp
->X_op
= O_illegal
;
1188 /* Immediate values. */
1190 /* Generic immediate-value read function for use in directives.
1191 Accepts anything that 'expression' can fold to a constant.
1192 *val receives the number. */
1195 immediate_for_directive (int *val
)
1198 exp
.X_op
= O_illegal
;
1200 if (is_immediate_prefix (*input_line_pointer
))
1202 input_line_pointer
++;
1206 if (exp
.X_op
!= O_constant
)
1208 as_bad (_("expected #constant"));
1209 ignore_rest_of_line ();
1212 *val
= exp
.X_add_number
;
1217 /* Register parsing. */
1219 /* Generic register parser. CCP points to what should be the
1220 beginning of a register name. If it is indeed a valid register
1221 name, advance CCP over it and return the reg_entry structure;
1222 otherwise return NULL. Does not issue diagnostics. */
1224 static struct reg_entry
*
1225 arm_reg_parse_multi (char **ccp
)
1229 struct reg_entry
*reg
;
1231 skip_whitespace (start
);
1233 #ifdef REGISTER_PREFIX
1234 if (*start
!= REGISTER_PREFIX
)
1238 #ifdef OPTIONAL_REGISTER_PREFIX
1239 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1244 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1249 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1251 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1261 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1262 enum arm_reg_type type
)
1264 /* Alternative syntaxes are accepted for a few register classes. */
1271 /* Generic coprocessor register names are allowed for these. */
1272 if (reg
&& reg
->type
== REG_TYPE_CN
)
1277 /* For backward compatibility, a bare number is valid here. */
1279 unsigned long processor
= strtoul (start
, ccp
, 10);
1280 if (*ccp
!= start
&& processor
<= 15)
1285 case REG_TYPE_MMXWC
:
1286 /* WC includes WCG. ??? I'm not sure this is true for all
1287 instructions that take WC registers. */
1288 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1299 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1300 return value is the register number or FAIL. */
1303 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1306 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1309 /* Do not allow a scalar (reg+index) to parse as a register. */
1310 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1313 if (reg
&& reg
->type
== type
)
1316 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1323 /* Parse a Neon type specifier. *STR should point at the leading '.'
1324 character. Does no verification at this stage that the type fits the opcode
1331 Can all be legally parsed by this function.
1333 Fills in neon_type struct pointer with parsed information, and updates STR
1334 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1335 type, FAIL if not. */
1338 parse_neon_type (struct neon_type
*type
, char **str
)
1345 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1347 enum neon_el_type thistype
= NT_untyped
;
1348 unsigned thissize
= -1u;
1355 /* Just a size without an explicit type. */
1359 switch (TOLOWER (*ptr
))
1361 case 'i': thistype
= NT_integer
; break;
1362 case 'f': thistype
= NT_float
; break;
1363 case 'p': thistype
= NT_poly
; break;
1364 case 's': thistype
= NT_signed
; break;
1365 case 'u': thistype
= NT_unsigned
; break;
1367 thistype
= NT_float
;
1372 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1378 /* .f is an abbreviation for .f32. */
1379 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1384 thissize
= strtoul (ptr
, &ptr
, 10);
1386 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1389 as_bad (_("bad size %d in type specifier"), thissize
);
1397 type
->el
[type
->elems
].type
= thistype
;
1398 type
->el
[type
->elems
].size
= thissize
;
1403 /* Empty/missing type is not a successful parse. */
1404 if (type
->elems
== 0)
1412 /* Errors may be set multiple times during parsing or bit encoding
1413 (particularly in the Neon bits), but usually the earliest error which is set
1414 will be the most meaningful. Avoid overwriting it with later (cascading)
1415 errors by calling this function. */
1418 first_error (const char *err
)
1424 /* Parse a single type, e.g. ".s32", leading period included. */
1426 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1429 struct neon_type optype
;
1433 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1435 if (optype
.elems
== 1)
1436 *vectype
= optype
.el
[0];
1439 first_error (_("only one type should be specified for operand"));
1445 first_error (_("vector type expected"));
1457 /* Special meanings for indices (which have a range of 0-7), which will fit into
1460 #define NEON_ALL_LANES 15
1461 #define NEON_INTERLEAVE_LANES 14
1463 /* Parse either a register or a scalar, with an optional type. Return the
1464 register number, and optionally fill in the actual type of the register
1465 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1466 type/index information in *TYPEINFO. */
1469 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1470 enum arm_reg_type
*rtype
,
1471 struct neon_typed_alias
*typeinfo
)
1474 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1475 struct neon_typed_alias atype
;
1476 struct neon_type_el parsetype
;
1480 atype
.eltype
.type
= NT_invtype
;
1481 atype
.eltype
.size
= -1;
1483 /* Try alternate syntax for some types of register. Note these are mutually
1484 exclusive with the Neon syntax extensions. */
1487 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1495 /* Undo polymorphism when a set of register types may be accepted. */
1496 if ((type
== REG_TYPE_NDQ
1497 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1498 || (type
== REG_TYPE_VFSD
1499 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1500 || (type
== REG_TYPE_NSDQ
1501 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1502 || reg
->type
== REG_TYPE_NQ
))
1503 || (type
== REG_TYPE_MMXWC
1504 && (reg
->type
== REG_TYPE_MMXWCG
)))
1505 type
= (enum arm_reg_type
) reg
->type
;
1507 if (type
!= reg
->type
)
1513 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1515 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1517 first_error (_("can't redefine type for operand"));
1520 atype
.defined
|= NTA_HASTYPE
;
1521 atype
.eltype
= parsetype
;
1524 if (skip_past_char (&str
, '[') == SUCCESS
)
1526 if (type
!= REG_TYPE_VFD
)
1528 first_error (_("only D registers may be indexed"));
1532 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1534 first_error (_("can't change index for operand"));
1538 atype
.defined
|= NTA_HASINDEX
;
1540 if (skip_past_char (&str
, ']') == SUCCESS
)
1541 atype
.index
= NEON_ALL_LANES
;
1546 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1548 if (exp
.X_op
!= O_constant
)
1550 first_error (_("constant expression required"));
1554 if (skip_past_char (&str
, ']') == FAIL
)
1557 atype
.index
= exp
.X_add_number
;
1572 /* Like arm_reg_parse, but allow allow the following extra features:
1573 - If RTYPE is non-zero, return the (possibly restricted) type of the
1574 register (e.g. Neon double or quad reg when either has been requested).
1575 - If this is a Neon vector type with additional type information, fill
1576 in the struct pointed to by VECTYPE (if non-NULL).
1577 This function will fault on encountering a scalar. */
1580 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1581 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1583 struct neon_typed_alias atype
;
1585 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1590 /* Do not allow regname(... to parse as a register. */
1594 /* Do not allow a scalar (reg+index) to parse as a register. */
1595 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1597 first_error (_("register operand expected, but got scalar"));
1602 *vectype
= atype
.eltype
;
1609 #define NEON_SCALAR_REG(X) ((X) >> 4)
1610 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1612 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1613 have enough information to be able to do a good job bounds-checking. So, we
1614 just do easy checks here, and do further checks later. */
1617 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1621 struct neon_typed_alias atype
;
1623 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1625 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1628 if (atype
.index
== NEON_ALL_LANES
)
1630 first_error (_("scalar must have an index"));
1633 else if (atype
.index
>= 64 / elsize
)
1635 first_error (_("scalar index out of range"));
1640 *type
= atype
.eltype
;
1644 return reg
* 16 + atype
.index
;
1647 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1650 parse_reg_list (char ** strp
)
1652 char * str
= * strp
;
1656 /* We come back here if we get ranges concatenated by '+' or '|'. */
1659 skip_whitespace (str
);
1673 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1675 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1685 first_error (_("bad range in register list"));
1689 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1691 if (range
& (1 << i
))
1693 (_("Warning: duplicated register (r%d) in register list"),
1701 if (range
& (1 << reg
))
1702 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1704 else if (reg
<= cur_reg
)
1705 as_tsktsk (_("Warning: register range not in ascending order"));
1710 while (skip_past_comma (&str
) != FAIL
1711 || (in_range
= 1, *str
++ == '-'));
1714 if (skip_past_char (&str
, '}') == FAIL
)
1716 first_error (_("missing `}'"));
1724 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1727 if (exp
.X_op
== O_constant
)
1729 if (exp
.X_add_number
1730 != (exp
.X_add_number
& 0x0000ffff))
1732 inst
.error
= _("invalid register mask");
1736 if ((range
& exp
.X_add_number
) != 0)
1738 int regno
= range
& exp
.X_add_number
;
1741 regno
= (1 << regno
) - 1;
1743 (_("Warning: duplicated register (r%d) in register list"),
1747 range
|= exp
.X_add_number
;
1751 if (inst
.reloc
.type
!= 0)
1753 inst
.error
= _("expression too complex");
1757 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1758 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1759 inst
.reloc
.pc_rel
= 0;
1763 if (*str
== '|' || *str
== '+')
1769 while (another_range
);
1775 /* Types of registers in a list. */
1784 /* Parse a VFP register list. If the string is invalid return FAIL.
1785 Otherwise return the number of registers, and set PBASE to the first
1786 register. Parses registers of type ETYPE.
1787 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1788 - Q registers can be used to specify pairs of D registers
1789 - { } can be omitted from around a singleton register list
1790 FIXME: This is not implemented, as it would require backtracking in
1793 This could be done (the meaning isn't really ambiguous), but doesn't
1794 fit in well with the current parsing framework.
1795 - 32 D registers may be used (also true for VFPv3).
1796 FIXME: Types are ignored in these register lists, which is probably a
1800 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1805 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1809 unsigned long mask
= 0;
1812 if (skip_past_char (&str
, '{') == FAIL
)
1814 inst
.error
= _("expecting {");
1821 regtype
= REG_TYPE_VFS
;
1826 regtype
= REG_TYPE_VFD
;
1829 case REGLIST_NEON_D
:
1830 regtype
= REG_TYPE_NDQ
;
1834 if (etype
!= REGLIST_VFP_S
)
1836 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1841 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1844 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1851 base_reg
= max_regs
;
1855 int setmask
= 1, addregs
= 1;
1857 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1859 if (new_base
== FAIL
)
1861 first_error (_(reg_expected_msgs
[regtype
]));
1865 if (new_base
>= max_regs
)
1867 first_error (_("register out of range in list"));
1871 /* Note: a value of 2 * n is returned for the register Q<n>. */
1872 if (regtype
== REG_TYPE_NQ
)
1878 if (new_base
< base_reg
)
1879 base_reg
= new_base
;
1881 if (mask
& (setmask
<< new_base
))
1883 first_error (_("invalid register list"));
1887 if ((mask
>> new_base
) != 0 && ! warned
)
1889 as_tsktsk (_("register list not in ascending order"));
1893 mask
|= setmask
<< new_base
;
1896 if (*str
== '-') /* We have the start of a range expression */
1902 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1905 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1909 if (high_range
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 if (regtype
== REG_TYPE_NQ
)
1916 high_range
= high_range
+ 1;
1918 if (high_range
<= new_base
)
1920 inst
.error
= _("register range not in ascending order");
1924 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1926 if (mask
& (setmask
<< new_base
))
1928 inst
.error
= _("invalid register list");
1932 mask
|= setmask
<< new_base
;
1937 while (skip_past_comma (&str
) != FAIL
);
1941 /* Sanity check -- should have raised a parse error above. */
1942 if (count
== 0 || count
> max_regs
)
1947 /* Final test -- the registers must be consecutive. */
1949 for (i
= 0; i
< count
; i
++)
1951 if ((mask
& (1u << i
)) == 0)
1953 inst
.error
= _("non-contiguous register range");
1963 /* True if two alias types are the same. */
1966 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1974 if (a
->defined
!= b
->defined
)
1977 if ((a
->defined
& NTA_HASTYPE
) != 0
1978 && (a
->eltype
.type
!= b
->eltype
.type
1979 || a
->eltype
.size
!= b
->eltype
.size
))
1982 if ((a
->defined
& NTA_HASINDEX
) != 0
1983 && (a
->index
!= b
->index
))
1989 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1990 The base register is put in *PBASE.
1991 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1993 The register stride (minus one) is put in bit 4 of the return value.
1994 Bits [6:5] encode the list length (minus one).
1995 The type of the list elements is put in *ELTYPE, if non-NULL. */
1997 #define NEON_LANE(X) ((X) & 0xf)
1998 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1999 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2002 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2003 struct neon_type_el
*eltype
)
2010 int leading_brace
= 0;
2011 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2012 const char *const incr_error
= _("register stride must be 1 or 2");
2013 const char *const type_error
= _("mismatched element/structure types in list");
2014 struct neon_typed_alias firsttype
;
2015 firsttype
.defined
= 0;
2016 firsttype
.eltype
.type
= NT_invtype
;
2017 firsttype
.eltype
.size
= -1;
2018 firsttype
.index
= -1;
2020 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2025 struct neon_typed_alias atype
;
2026 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2030 first_error (_(reg_expected_msgs
[rtype
]));
2037 if (rtype
== REG_TYPE_NQ
)
2043 else if (reg_incr
== -1)
2045 reg_incr
= getreg
- base_reg
;
2046 if (reg_incr
< 1 || reg_incr
> 2)
2048 first_error (_(incr_error
));
2052 else if (getreg
!= base_reg
+ reg_incr
* count
)
2054 first_error (_(incr_error
));
2058 if (! neon_alias_types_same (&atype
, &firsttype
))
2060 first_error (_(type_error
));
2064 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2068 struct neon_typed_alias htype
;
2069 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2071 lane
= NEON_INTERLEAVE_LANES
;
2072 else if (lane
!= NEON_INTERLEAVE_LANES
)
2074 first_error (_(type_error
));
2079 else if (reg_incr
!= 1)
2081 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2085 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2088 first_error (_(reg_expected_msgs
[rtype
]));
2091 if (! neon_alias_types_same (&htype
, &firsttype
))
2093 first_error (_(type_error
));
2096 count
+= hireg
+ dregs
- getreg
;
2100 /* If we're using Q registers, we can't use [] or [n] syntax. */
2101 if (rtype
== REG_TYPE_NQ
)
2107 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2111 else if (lane
!= atype
.index
)
2113 first_error (_(type_error
));
2117 else if (lane
== -1)
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2128 /* No lane set by [x]. We must be interleaving structures. */
2130 lane
= NEON_INTERLEAVE_LANES
;
2133 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2134 || (count
> 1 && reg_incr
== -1))
2136 first_error (_("error parsing element/structure list"));
2140 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2142 first_error (_("expected }"));
2150 *eltype
= firsttype
.eltype
;
2155 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2158 /* Parse an explicit relocation suffix on an expression. This is
2159 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2160 arm_reloc_hsh contains no entries, so this function can only
2161 succeed if there is no () after the word. Returns -1 on error,
2162 BFD_RELOC_UNUSED if there wasn't any suffix. */
2165 parse_reloc (char **str
)
2167 struct reloc_entry
*r
;
2171 return BFD_RELOC_UNUSED
;
2176 while (*q
&& *q
!= ')' && *q
!= ',')
2181 if ((r
= (struct reloc_entry
*)
2182 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2189 /* Directives: register aliases. */
2191 static struct reg_entry
*
2192 insert_reg_alias (char *str
, unsigned number
, int type
)
2194 struct reg_entry
*new_reg
;
2197 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2199 if (new_reg
->builtin
)
2200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2202 /* Only warn about a redefinition if it's not defined as the
2204 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2205 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2210 name
= xstrdup (str
);
2211 new_reg
= XNEW (struct reg_entry
);
2213 new_reg
->name
= name
;
2214 new_reg
->number
= number
;
2215 new_reg
->type
= type
;
2216 new_reg
->builtin
= FALSE
;
2217 new_reg
->neon
= NULL
;
2219 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2226 insert_neon_reg_alias (char *str
, int number
, int type
,
2227 struct neon_typed_alias
*atype
)
2229 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2233 first_error (_("attempt to redefine typed alias"));
2239 reg
->neon
= XNEW (struct neon_typed_alias
);
2240 *reg
->neon
= *atype
;
2244 /* Look for the .req directive. This is of the form:
2246 new_register_name .req existing_register_name
2248 If we find one, or if it looks sufficiently like one that we want to
2249 handle any error here, return TRUE. Otherwise return FALSE. */
2252 create_register_alias (char * newname
, char *p
)
2254 struct reg_entry
*old
;
2255 char *oldname
, *nbuf
;
2258 /* The input scrubber ensures that whitespace after the mnemonic is
2259 collapsed to single spaces. */
2261 if (strncmp (oldname
, " .req ", 6) != 0)
2265 if (*oldname
== '\0')
2268 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2271 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2275 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2276 the desired alias name, and p points to its end. If not, then
2277 the desired alias name is in the global original_case_string. */
2278 #ifdef TC_CASE_SENSITIVE
2281 newname
= original_case_string
;
2282 nlen
= strlen (newname
);
2285 nbuf
= xmemdup0 (newname
, nlen
);
2287 /* Create aliases under the new name as stated; an all-lowercase
2288 version of the new name; and an all-uppercase version of the new
2290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2292 for (p
= nbuf
; *p
; p
++)
2295 if (strncmp (nbuf
, newname
, nlen
))
2297 /* If this attempt to create an additional alias fails, do not bother
2298 trying to create the all-lower case alias. We will fail and issue
2299 a second, duplicate error message. This situation arises when the
2300 programmer does something like:
2303 The second .req creates the "Foo" alias but then fails to create
2304 the artificial FOO alias because it has already been created by the
2306 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2313 for (p
= nbuf
; *p
; p
++)
2316 if (strncmp (nbuf
, newname
, nlen
))
2317 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2324 /* Create a Neon typed/indexed register alias using directives, e.g.:
2329 These typed registers can be used instead of the types specified after the
2330 Neon mnemonic, so long as all operands given have types. Types can also be
2331 specified directly, e.g.:
2332 vadd d0.s32, d1.s32, d2.s32 */
2335 create_neon_reg_alias (char *newname
, char *p
)
2337 enum arm_reg_type basetype
;
2338 struct reg_entry
*basereg
;
2339 struct reg_entry mybasereg
;
2340 struct neon_type ntype
;
2341 struct neon_typed_alias typeinfo
;
2342 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2345 typeinfo
.defined
= 0;
2346 typeinfo
.eltype
.type
= NT_invtype
;
2347 typeinfo
.eltype
.size
= -1;
2348 typeinfo
.index
= -1;
2352 if (strncmp (p
, " .dn ", 5) == 0)
2353 basetype
= REG_TYPE_VFD
;
2354 else if (strncmp (p
, " .qn ", 5) == 0)
2355 basetype
= REG_TYPE_NQ
;
2364 basereg
= arm_reg_parse_multi (&p
);
2366 if (basereg
&& basereg
->type
!= basetype
)
2368 as_bad (_("bad type for register"));
2372 if (basereg
== NULL
)
2375 /* Try parsing as an integer. */
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2377 if (exp
.X_op
!= O_constant
)
2379 as_bad (_("expression must be constant"));
2382 basereg
= &mybasereg
;
2383 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2389 typeinfo
= *basereg
->neon
;
2391 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2393 /* We got a type. */
2394 if (typeinfo
.defined
& NTA_HASTYPE
)
2396 as_bad (_("can't redefine the type of a register alias"));
2400 typeinfo
.defined
|= NTA_HASTYPE
;
2401 if (ntype
.elems
!= 1)
2403 as_bad (_("you must specify a single type only"));
2406 typeinfo
.eltype
= ntype
.el
[0];
2409 if (skip_past_char (&p
, '[') == SUCCESS
)
2412 /* We got a scalar index. */
2414 if (typeinfo
.defined
& NTA_HASINDEX
)
2416 as_bad (_("can't redefine the index of a scalar alias"));
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2422 if (exp
.X_op
!= O_constant
)
2424 as_bad (_("scalar index must be constant"));
2428 typeinfo
.defined
|= NTA_HASINDEX
;
2429 typeinfo
.index
= exp
.X_add_number
;
2431 if (skip_past_char (&p
, ']') == FAIL
)
2433 as_bad (_("expecting ]"));
2438 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2439 the desired alias name, and p points to its end. If not, then
2440 the desired alias name is in the global original_case_string. */
2441 #ifdef TC_CASE_SENSITIVE
2442 namelen
= nameend
- newname
;
2444 newname
= original_case_string
;
2445 namelen
= strlen (newname
);
2448 namebuf
= xmemdup0 (newname
, namelen
);
2450 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2451 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Insert name in all uppercase. */
2454 for (p
= namebuf
; *p
; p
++)
2457 if (strncmp (namebuf
, newname
, namelen
))
2458 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2459 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2461 /* Insert name in all lowercase. */
2462 for (p
= namebuf
; *p
; p
++)
2465 if (strncmp (namebuf
, newname
, namelen
))
2466 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2467 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2473 /* Should never be called, as .req goes between the alias and the
2474 register name, not at the beginning of the line. */
2477 s_req (int a ATTRIBUTE_UNUSED
)
2479 as_bad (_("invalid syntax for .req directive"));
2483 s_dn (int a ATTRIBUTE_UNUSED
)
2485 as_bad (_("invalid syntax for .dn directive"));
2489 s_qn (int a ATTRIBUTE_UNUSED
)
2491 as_bad (_("invalid syntax for .qn directive"));
2494 /* The .unreq directive deletes an alias which was previously defined
2495 by .req. For example:
2501 s_unreq (int a ATTRIBUTE_UNUSED
)
2506 name
= input_line_pointer
;
2508 while (*input_line_pointer
!= 0
2509 && *input_line_pointer
!= ' '
2510 && *input_line_pointer
!= '\n')
2511 ++input_line_pointer
;
2513 saved_char
= *input_line_pointer
;
2514 *input_line_pointer
= 0;
2517 as_bad (_("invalid syntax for .unreq directive"));
2520 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2524 as_bad (_("unknown register alias '%s'"), name
);
2525 else if (reg
->builtin
)
2526 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2533 hash_delete (arm_reg_hsh
, name
, FALSE
);
2534 free ((char *) reg
->name
);
2539 /* Also locate the all upper case and all lower case versions.
2540 Do not complain if we cannot find one or the other as it
2541 was probably deleted above. */
2543 nbuf
= strdup (name
);
2544 for (p
= nbuf
; *p
; p
++)
2546 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2549 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2550 free ((char *) reg
->name
);
2556 for (p
= nbuf
; *p
; p
++)
2558 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2561 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2562 free ((char *) reg
->name
);
2572 *input_line_pointer
= saved_char
;
2573 demand_empty_rest_of_line ();
2576 /* Directives: Instruction set selection. */
2579 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2580 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2581 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2582 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2584 /* Create a new mapping symbol for the transition to STATE. */
2587 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2590 const char * symname
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2605 type
= BSF_NO_FLAGS
;
2611 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2612 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2617 THUMB_SET_FUNC (symbolP
, 0);
2618 ARM_SET_THUMB (symbolP
, 0);
2619 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2623 THUMB_SET_FUNC (symbolP
, 1);
2624 ARM_SET_THUMB (symbolP
, 1);
2625 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2633 /* Save the mapping symbols for future reference. Also check that
2634 we do not place two mapping symbols at the same offset within a
2635 frag. We'll handle overlap between frags in
2636 check_mapping_symbols.
2638 If .fill or other data filling directive generates zero sized data,
2639 the mapping symbol for the following code will have the same value
2640 as the one generated for the data filling directive. In this case,
2641 we replace the old symbol with the new one at the same address. */
2644 if (frag
->tc_frag_data
.first_map
!= NULL
)
2646 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2647 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2649 frag
->tc_frag_data
.first_map
= symbolP
;
2651 if (frag
->tc_frag_data
.last_map
!= NULL
)
2653 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2654 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2655 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2657 frag
->tc_frag_data
.last_map
= symbolP
;
2660 /* We must sometimes convert a region marked as code to data during
2661 code alignment, if an odd number of bytes have to be padded. The
2662 code mapping symbol is pushed to an aligned address. */
2665 insert_data_mapping_symbol (enum mstate state
,
2666 valueT value
, fragS
*frag
, offsetT bytes
)
2668 /* If there was already a mapping symbol, remove it. */
2669 if (frag
->tc_frag_data
.last_map
!= NULL
2670 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2672 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2676 know (frag
->tc_frag_data
.first_map
== symp
);
2677 frag
->tc_frag_data
.first_map
= NULL
;
2679 frag
->tc_frag_data
.last_map
= NULL
;
2680 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2683 make_mapping_symbol (MAP_DATA
, value
, frag
);
2684 make_mapping_symbol (state
, value
+ bytes
, frag
);
2687 static void mapping_state_2 (enum mstate state
, int max_chars
);
2689 /* Set the mapping state to STATE. Only call this when about to
2690 emit some STATE bytes to the file. */
2692 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2694 mapping_state (enum mstate state
)
2696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2698 if (mapstate
== state
)
2699 /* The mapping symbol has already been emitted.
2700 There is nothing else to do. */
2703 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2705 All ARM instructions require 4-byte alignment.
2706 (Almost) all Thumb instructions require 2-byte alignment.
2708 When emitting instructions into any section, mark the section
2711 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2712 but themselves require 2-byte alignment; this applies to some
2713 PC- relative forms. However, these cases will involve implicit
2714 literal pool generation or an explicit .align >=2, both of
2715 which will cause the section to me marked with sufficient
2716 alignment. Thus, we don't handle those cases here. */
2717 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2719 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2720 /* This case will be evaluated later. */
2723 mapping_state_2 (state
, 0);
2726 /* Same as mapping_state, but MAX_CHARS bytes have already been
2727 allocated. Put the mapping symbol that far back. */
2730 mapping_state_2 (enum mstate state
, int max_chars
)
2732 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2734 if (!SEG_NORMAL (now_seg
))
2737 if (mapstate
== state
)
2738 /* The mapping symbol has already been emitted.
2739 There is nothing else to do. */
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2743 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2745 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2746 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2749 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2752 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2753 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2757 #define mapping_state(x) ((void)0)
2758 #define mapping_state_2(x, y) ((void)0)
2761 /* Find the real, Thumb encoded start of a Thumb function. */
2765 find_real_start (symbolS
* symbolP
)
2768 const char * name
= S_GET_NAME (symbolP
);
2769 symbolS
* new_target
;
2771 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2772 #define STUB_NAME ".real_start_of"
2777 /* The compiler may generate BL instructions to local labels because
2778 it needs to perform a branch to a far away location. These labels
2779 do not have a corresponding ".real_start_of" label. We check
2780 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2781 the ".real_start_of" convention for nonlocal branches. */
2782 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2785 real_start
= concat (STUB_NAME
, name
, NULL
);
2786 new_target
= symbol_find (real_start
);
2789 if (new_target
== NULL
)
2791 as_warn (_("Failed to find real start of function: %s\n"), name
);
2792 new_target
= symbolP
;
2800 opcode_select (int width
)
2807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2808 as_bad (_("selected processor does not support THUMB opcodes"));
2811 /* No need to force the alignment, since we will have been
2812 coming from ARM mode, which is word-aligned. */
2813 record_alignment (now_seg
, 1);
2820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2821 as_bad (_("selected processor does not support ARM opcodes"));
2826 frag_align (2, 0, 0);
2828 record_alignment (now_seg
, 1);
2833 as_bad (_("invalid instruction size selected (%d)"), width
);
2838 s_arm (int ignore ATTRIBUTE_UNUSED
)
2841 demand_empty_rest_of_line ();
2845 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 demand_empty_rest_of_line ();
2852 s_code (int unused ATTRIBUTE_UNUSED
)
2856 temp
= get_absolute_expression ();
2861 opcode_select (temp
);
2865 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2870 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2872 /* If we are not already in thumb mode go into it, EVEN if
2873 the target processor does not support thumb instructions.
2874 This is used by gcc/config/arm/lib1funcs.asm for example
2875 to compile interworking support functions even if the
2876 target processor should not support interworking. */
2880 record_alignment (now_seg
, 1);
2883 demand_empty_rest_of_line ();
2887 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2891 /* The following label is the name/address of the start of a Thumb function.
2892 We need to know this for the interworking support. */
2893 label_is_thumb_function_name
= TRUE
;
2896 /* Perform a .set directive, but also mark the alias as
2897 being a thumb function. */
2900 s_thumb_set (int equiv
)
2902 /* XXX the following is a duplicate of the code for s_set() in read.c
2903 We cannot just call that code as we need to get at the symbol that
2910 /* Especial apologies for the random logic:
2911 This just grew, and could be parsed much more simply!
2913 delim
= get_symbol_name (& name
);
2914 end_name
= input_line_pointer
;
2915 (void) restore_line_pointer (delim
);
2917 if (*input_line_pointer
!= ',')
2920 as_bad (_("expected comma after name \"%s\""), name
);
2922 ignore_rest_of_line ();
2926 input_line_pointer
++;
2929 if (name
[0] == '.' && name
[1] == '\0')
2931 /* XXX - this should not happen to .thumb_set. */
2935 if ((symbolP
= symbol_find (name
)) == NULL
2936 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2939 /* When doing symbol listings, play games with dummy fragments living
2940 outside the normal fragment chain to record the file and line info
2942 if (listing
& LISTING_SYMBOLS
)
2944 extern struct list_info_struct
* listing_tail
;
2945 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2947 memset (dummy_frag
, 0, sizeof (fragS
));
2948 dummy_frag
->fr_type
= rs_fill
;
2949 dummy_frag
->line
= listing_tail
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2951 dummy_frag
->fr_symbol
= symbolP
;
2955 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2958 /* "set" symbols are local unless otherwise specified. */
2959 SF_SET_LOCAL (symbolP
);
2960 #endif /* OBJ_COFF */
2961 } /* Make a new symbol. */
2963 symbol_table_insert (symbolP
);
2968 && S_IS_DEFINED (symbolP
)
2969 && S_GET_SEGMENT (symbolP
) != reg_section
)
2970 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2972 pseudo_set (symbolP
);
2974 demand_empty_rest_of_line ();
2976 /* XXX Now we come to the Thumb specific bit of code. */
2978 THUMB_SET_FUNC (symbolP
, 1);
2979 ARM_SET_THUMB (symbolP
, 1);
2980 #if defined OBJ_ELF || defined OBJ_COFF
2981 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2985 /* Directives: Mode selection. */
2987 /* .syntax [unified|divided] - choose the new unified syntax
2988 (same for Arm and Thumb encoding, modulo slight differences in what
2989 can be represented) or the old divergent syntax for each mode. */
2991 s_syntax (int unused ATTRIBUTE_UNUSED
)
2995 delim
= get_symbol_name (& name
);
2997 if (!strcasecmp (name
, "unified"))
2998 unified_syntax
= TRUE
;
2999 else if (!strcasecmp (name
, "divided"))
3000 unified_syntax
= FALSE
;
3003 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3006 (void) restore_line_pointer (delim
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: sectioning and alignment. */
3013 s_bss (int ignore ATTRIBUTE_UNUSED
)
3015 /* We don't support putting frags in the BSS segment, we fake it by
3016 marking in_bss, then looking at s_skip for clues. */
3017 subseg_set (bss_section
, 0);
3018 demand_empty_rest_of_line ();
3020 #ifdef md_elf_section_change_hook
3021 md_elf_section_change_hook ();
3026 s_even (int ignore ATTRIBUTE_UNUSED
)
3028 /* Never make frag if expect extra pass. */
3030 frag_align (1, 0, 0);
3032 record_alignment (now_seg
, 1);
3034 demand_empty_rest_of_line ();
3037 /* Directives: CodeComposer Studio. */
3039 /* .ref (for CodeComposer Studio syntax only). */
3041 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3043 if (codecomposer_syntax
)
3044 ignore_rest_of_line ();
3046 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3049 /* If name is not NULL, then it is used for marking the beginning of a
3050 function, whereas if it is NULL then it means the function end. */
3052 asmfunc_debug (const char * name
)
3054 static const char * last_name
= NULL
;
3058 gas_assert (last_name
== NULL
);
3061 if (debug_type
== DEBUG_STABS
)
3062 stabs_generate_asm_func (name
, name
);
3066 gas_assert (last_name
!= NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_endfunc (last_name
, last_name
);
3076 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3078 if (codecomposer_syntax
)
3080 switch (asmfunc_state
)
3082 case OUTSIDE_ASMFUNC
:
3083 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3086 case WAITING_ASMFUNC_NAME
:
3087 as_bad (_(".asmfunc repeated."));
3090 case WAITING_ENDASMFUNC
:
3091 as_bad (_(".asmfunc without function."));
3094 demand_empty_rest_of_line ();
3097 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3101 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3103 if (codecomposer_syntax
)
3105 switch (asmfunc_state
)
3107 case OUTSIDE_ASMFUNC
:
3108 as_bad (_(".endasmfunc without a .asmfunc."));
3111 case WAITING_ASMFUNC_NAME
:
3112 as_bad (_(".endasmfunc without function."));
3115 case WAITING_ENDASMFUNC
:
3116 asmfunc_state
= OUTSIDE_ASMFUNC
;
3117 asmfunc_debug (NULL
);
3120 demand_empty_rest_of_line ();
3123 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3127 s_ccs_def (int name
)
3129 if (codecomposer_syntax
)
3132 as_bad (_(".def pseudo-op only available with -mccs flag."));
3135 /* Directives: Literal pools. */
3137 static literal_pool
*
3138 find_literal_pool (void)
3140 literal_pool
* pool
;
3142 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3144 if (pool
->section
== now_seg
3145 && pool
->sub_section
== now_subseg
)
3152 static literal_pool
*
3153 find_or_make_literal_pool (void)
3155 /* Next literal pool ID number. */
3156 static unsigned int latest_pool_num
= 1;
3157 literal_pool
* pool
;
3159 pool
= find_literal_pool ();
3163 /* Create a new pool. */
3164 pool
= XNEW (literal_pool
);
3168 pool
->next_free_entry
= 0;
3169 pool
->section
= now_seg
;
3170 pool
->sub_section
= now_subseg
;
3171 pool
->next
= list_of_pools
;
3172 pool
->symbol
= NULL
;
3173 pool
->alignment
= 2;
3175 /* Add it to the list. */
3176 list_of_pools
= pool
;
3179 /* New pools, and emptied pools, will have a NULL symbol. */
3180 if (pool
->symbol
== NULL
)
3182 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3183 (valueT
) 0, &zero_address_frag
);
3184 pool
->id
= latest_pool_num
++;
3191 /* Add the literal in the global 'inst'
3192 structure to the relevant literal pool. */
3195 add_to_lit_pool (unsigned int nbytes
)
3197 #define PADDING_SLOT 0x1
3198 #define LIT_ENTRY_SIZE_MASK 0xFF
3199 literal_pool
* pool
;
3200 unsigned int entry
, pool_size
= 0;
3201 bfd_boolean padding_slot_p
= FALSE
;
3207 imm1
= inst
.operands
[1].imm
;
3208 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3209 : inst
.reloc
.exp
.X_unsigned
? 0
3210 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3211 if (target_big_endian
)
3214 imm2
= inst
.operands
[1].imm
;
3218 pool
= find_or_make_literal_pool ();
3220 /* Check if this literal value is already in the pool. */
3221 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_constant
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_md
== nbytes
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3235 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3236 && (pool
->literals
[entry
].X_add_number
3237 == inst
.reloc
.exp
.X_add_number
)
3238 && (pool
->literals
[entry
].X_add_symbol
3239 == inst
.reloc
.exp
.X_add_symbol
)
3240 && (pool
->literals
[entry
].X_op_symbol
3241 == inst
.reloc
.exp
.X_op_symbol
)
3242 && (pool
->literals
[entry
].X_md
== nbytes
))
3245 else if ((nbytes
== 8)
3246 && !(pool_size
& 0x7)
3247 && ((entry
+ 1) != pool
->next_free_entry
)
3248 && (pool
->literals
[entry
].X_op
== O_constant
)
3249 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3250 && (pool
->literals
[entry
].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
)
3252 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3253 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3254 && (pool
->literals
[entry
+ 1].X_unsigned
3255 == inst
.reloc
.exp
.X_unsigned
))
3258 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3259 if (padding_slot_p
&& (nbytes
== 4))
3265 /* Do we need to create a new entry? */
3266 if (entry
== pool
->next_free_entry
)
3268 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3270 inst
.error
= _("literal pool overflow");
3276 /* For 8-byte entries, we align to an 8-byte boundary,
3277 and split it into two 4-byte entries, because on 32-bit
3278 host, 8-byte constants are treated as big num, thus
3279 saved in "generic_bignum" which will be overwritten
3280 by later assignments.
3282 We also need to make sure there is enough space for
3285 We also check to make sure the literal operand is a
3287 if (!(inst
.reloc
.exp
.X_op
== O_constant
3288 || inst
.reloc
.exp
.X_op
== O_big
))
3290 inst
.error
= _("invalid type for literal pool");
3293 else if (pool_size
& 0x7)
3295 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3297 inst
.error
= _("literal pool overflow");
3301 pool
->literals
[entry
] = inst
.reloc
.exp
;
3302 pool
->literals
[entry
].X_op
= O_constant
;
3303 pool
->literals
[entry
].X_add_number
= 0;
3304 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3305 pool
->next_free_entry
+= 1;
3308 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm1
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
++].X_md
= 4;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= imm2
;
3322 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3323 pool
->literals
[entry
].X_md
= 4;
3324 pool
->alignment
= 3;
3325 pool
->next_free_entry
+= 1;
3329 pool
->literals
[entry
] = inst
.reloc
.exp
;
3330 pool
->literals
[entry
].X_md
= 4;
3334 /* PR ld/12974: Record the location of the first source line to reference
3335 this entry in the literal pool. If it turns out during linking that the
3336 symbol does not exist we will be able to give an accurate line number for
3337 the (first use of the) missing reference. */
3338 if (debug_type
== DEBUG_DWARF2
)
3339 dwarf2_where (pool
->locs
+ entry
);
3341 pool
->next_free_entry
+= 1;
3343 else if (padding_slot_p
)
3345 pool
->literals
[entry
] = inst
.reloc
.exp
;
3346 pool
->literals
[entry
].X_md
= nbytes
;
3349 inst
.reloc
.exp
.X_op
= O_symbol
;
3350 inst
.reloc
.exp
.X_add_number
= pool_size
;
3351 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3357 tc_start_label_without_colon (void)
3359 bfd_boolean ret
= TRUE
;
3361 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3363 const char *label
= input_line_pointer
;
3365 while (!is_end_of_line
[(int) label
[-1]])
3370 as_bad (_("Invalid label '%s'"), label
);
3374 asmfunc_debug (label
);
3376 asmfunc_state
= WAITING_ENDASMFUNC
;
3382 /* Can't use symbol_new here, so have to create a symbol and then at
3383 a later date assign it a value. That's what these functions do. */
3386 symbol_locate (symbolS
* symbolP
,
3387 const char * name
, /* It is copied, the caller can modify. */
3388 segT segment
, /* Segment identifier (SEG_<something>). */
3389 valueT valu
, /* Symbol value. */
3390 fragS
* frag
) /* Associated fragment. */
3393 char * preserved_copy_of_name
;
3395 name_length
= strlen (name
) + 1; /* +1 for \0. */
3396 obstack_grow (¬es
, name
, name_length
);
3397 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3399 #ifdef tc_canonicalize_symbol_name
3400 preserved_copy_of_name
=
3401 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3404 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3406 S_SET_SEGMENT (symbolP
, segment
);
3407 S_SET_VALUE (symbolP
, valu
);
3408 symbol_clear_list_pointers (symbolP
);
3410 symbol_set_frag (symbolP
, frag
);
3412 /* Link to end of symbol chain. */
3414 extern int symbol_table_frozen
;
3416 if (symbol_table_frozen
)
3420 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3422 obj_symbol_new_hook (symbolP
);
3424 #ifdef tc_symbol_new_hook
3425 tc_symbol_new_hook (symbolP
);
3429 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3430 #endif /* DEBUG_SYMS */
3434 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3437 literal_pool
* pool
;
3440 pool
= find_literal_pool ();
3442 || pool
->symbol
== NULL
3443 || pool
->next_free_entry
== 0)
3446 /* Align pool as you have word accesses.
3447 Only make a frag if we have to. */
3449 frag_align (pool
->alignment
, 0, 0);
3451 record_alignment (now_seg
, 2);
3454 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3455 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3457 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3459 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3460 (valueT
) frag_now_fix (), frag_now
);
3461 symbol_table_insert (pool
->symbol
);
3463 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3465 #if defined OBJ_COFF || defined OBJ_ELF
3466 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3469 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3472 if (debug_type
== DEBUG_DWARF2
)
3473 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3475 /* First output the expression in the instruction to the pool. */
3476 emit_expr (&(pool
->literals
[entry
]),
3477 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3480 /* Mark the pool as empty. */
3481 pool
->next_free_entry
= 0;
3482 pool
->symbol
= NULL
;
3486 /* Forward declarations for functions below, in the MD interface
3488 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3489 static valueT
create_unwind_entry (int);
3490 static void start_unwind_section (const segT
, int);
3491 static void add_unwind_opcode (valueT
, int);
3492 static void flush_pending_unwind (void);
3494 /* Directives: Data. */
3497 s_arm_elf_cons (int nbytes
)
3501 #ifdef md_flush_pending_output
3502 md_flush_pending_output ();
3505 if (is_it_end_of_statement ())
3507 demand_empty_rest_of_line ();
3511 #ifdef md_cons_align
3512 md_cons_align (nbytes
);
3515 mapping_state (MAP_DATA
);
3519 char *base
= input_line_pointer
;
3523 if (exp
.X_op
!= O_symbol
)
3524 emit_expr (&exp
, (unsigned int) nbytes
);
3527 char *before_reloc
= input_line_pointer
;
3528 reloc
= parse_reloc (&input_line_pointer
);
3531 as_bad (_("unrecognized relocation suffix"));
3532 ignore_rest_of_line ();
3535 else if (reloc
== BFD_RELOC_UNUSED
)
3536 emit_expr (&exp
, (unsigned int) nbytes
);
3539 reloc_howto_type
*howto
= (reloc_howto_type
*)
3540 bfd_reloc_type_lookup (stdoutput
,
3541 (bfd_reloc_code_real_type
) reloc
);
3542 int size
= bfd_get_reloc_size (howto
);
3544 if (reloc
== BFD_RELOC_ARM_PLT32
)
3546 as_bad (_("(plt) is only valid on branch targets"));
3547 reloc
= BFD_RELOC_UNUSED
;
3552 as_bad (_("%s relocations do not fit in %d bytes"),
3553 howto
->name
, nbytes
);
3556 /* We've parsed an expression stopping at O_symbol.
3557 But there may be more expression left now that we
3558 have parsed the relocation marker. Parse it again.
3559 XXX Surely there is a cleaner way to do this. */
3560 char *p
= input_line_pointer
;
3562 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3564 memcpy (save_buf
, base
, input_line_pointer
- base
);
3565 memmove (base
+ (input_line_pointer
- before_reloc
),
3566 base
, before_reloc
- base
);
3568 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3570 memcpy (base
, save_buf
, p
- base
);
3572 offset
= nbytes
- size
;
3573 p
= frag_more (nbytes
);
3574 memset (p
, 0, nbytes
);
3575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3576 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3582 while (*input_line_pointer
++ == ',');
3584 /* Put terminator back into stream. */
3585 input_line_pointer
--;
3586 demand_empty_rest_of_line ();
3589 /* Emit an expression containing a 32-bit thumb instruction.
3590 Implementation based on put_thumb32_insn. */
3593 emit_thumb32_expr (expressionS
* exp
)
3595 expressionS exp_high
= *exp
;
3597 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3598 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3599 exp
->X_add_number
&= 0xffff;
3600 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3603 /* Guess the instruction size based on the opcode. */
3606 thumb_insn_size (int opcode
)
3608 if ((unsigned int) opcode
< 0xe800u
)
3610 else if ((unsigned int) opcode
>= 0xe8000000u
)
3617 emit_insn (expressionS
*exp
, int nbytes
)
3621 if (exp
->X_op
== O_constant
)
3626 size
= thumb_insn_size (exp
->X_add_number
);
3630 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3632 as_bad (_(".inst.n operand too big. "\
3633 "Use .inst.w instead"));
3638 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3639 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3641 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3643 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3644 emit_thumb32_expr (exp
);
3646 emit_expr (exp
, (unsigned int) size
);
3648 it_fsm_post_encode ();
3652 as_bad (_("cannot determine Thumb instruction size. " \
3653 "Use .inst.n/.inst.w instead"));
3656 as_bad (_("constant expression required"));
3661 /* Like s_arm_elf_cons but do not use md_cons_align and
3662 set the mapping state to MAP_ARM/MAP_THUMB. */
3665 s_arm_elf_inst (int nbytes
)
3667 if (is_it_end_of_statement ())
3669 demand_empty_rest_of_line ();
3673 /* Calling mapping_state () here will not change ARM/THUMB,
3674 but will ensure not to be in DATA state. */
3677 mapping_state (MAP_THUMB
);
3682 as_bad (_("width suffixes are invalid in ARM mode"));
3683 ignore_rest_of_line ();
3689 mapping_state (MAP_ARM
);
3698 if (! emit_insn (& exp
, nbytes
))
3700 ignore_rest_of_line ();
3704 while (*input_line_pointer
++ == ',');
3706 /* Put terminator back into stream. */
3707 input_line_pointer
--;
3708 demand_empty_rest_of_line ();
3711 /* Parse a .rel31 directive. */
3714 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3721 if (*input_line_pointer
== '1')
3722 highbit
= 0x80000000;
3723 else if (*input_line_pointer
!= '0')
3724 as_bad (_("expected 0 or 1"));
3726 input_line_pointer
++;
3727 if (*input_line_pointer
!= ',')
3728 as_bad (_("missing comma"));
3729 input_line_pointer
++;
3731 #ifdef md_flush_pending_output
3732 md_flush_pending_output ();
3735 #ifdef md_cons_align
3739 mapping_state (MAP_DATA
);
3744 md_number_to_chars (p
, highbit
, 4);
3745 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3746 BFD_RELOC_ARM_PREL31
);
3748 demand_empty_rest_of_line ();
3751 /* Directives: AEABI stack-unwind tables. */
3753 /* Parse an unwind_fnstart directive. Simply records the current location. */
3756 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3758 demand_empty_rest_of_line ();
3759 if (unwind
.proc_start
)
3761 as_bad (_("duplicate .fnstart directive"));
3765 /* Mark the start of the function. */
3766 unwind
.proc_start
= expr_build_dot ();
3768 /* Reset the rest of the unwind info. */
3769 unwind
.opcode_count
= 0;
3770 unwind
.table_entry
= NULL
;
3771 unwind
.personality_routine
= NULL
;
3772 unwind
.personality_index
= -1;
3773 unwind
.frame_size
= 0;
3774 unwind
.fp_offset
= 0;
3775 unwind
.fp_reg
= REG_SP
;
3777 unwind
.sp_restored
= 0;
3781 /* Parse a handlerdata directive. Creates the exception handling table entry
3782 for the function. */
3785 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3787 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3789 as_bad (MISSING_FNSTART
);
3791 if (unwind
.table_entry
)
3792 as_bad (_("duplicate .handlerdata directive"));
3794 create_unwind_entry (1);
3797 /* Parse an unwind_fnend directive. Generates the index table entry. */
3800 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3805 unsigned int marked_pr_dependency
;
3807 demand_empty_rest_of_line ();
3809 if (!unwind
.proc_start
)
3811 as_bad (_(".fnend directive without .fnstart"));
3815 /* Add eh table entry. */
3816 if (unwind
.table_entry
== NULL
)
3817 val
= create_unwind_entry (0);
3821 /* Add index table entry. This is two words. */
3822 start_unwind_section (unwind
.saved_seg
, 1);
3823 frag_align (2, 0, 0);
3824 record_alignment (now_seg
, 2);
3826 ptr
= frag_more (8);
3828 where
= frag_now_fix () - 8;
3830 /* Self relative offset of the function start. */
3831 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3832 BFD_RELOC_ARM_PREL31
);
3834 /* Indicate dependency on EHABI-defined personality routines to the
3835 linker, if it hasn't been done already. */
3836 marked_pr_dependency
3837 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3838 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3839 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3841 static const char *const name
[] =
3843 "__aeabi_unwind_cpp_pr0",
3844 "__aeabi_unwind_cpp_pr1",
3845 "__aeabi_unwind_cpp_pr2"
3847 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3848 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3849 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3850 |= 1 << unwind
.personality_index
;
3854 /* Inline exception table entry. */
3855 md_number_to_chars (ptr
+ 4, val
, 4);
3857 /* Self relative offset of the table entry. */
3858 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3859 BFD_RELOC_ARM_PREL31
);
3861 /* Restore the original section. */
3862 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3864 unwind
.proc_start
= NULL
;
3868 /* Parse an unwind_cantunwind directive. */
3871 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3873 demand_empty_rest_of_line ();
3874 if (!unwind
.proc_start
)
3875 as_bad (MISSING_FNSTART
);
3877 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3878 as_bad (_("personality routine specified for cantunwind frame"));
3880 unwind
.personality_index
= -2;
3884 /* Parse a personalityindex directive. */
3887 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3895 as_bad (_("duplicate .personalityindex directive"));
3899 if (exp
.X_op
!= O_constant
3900 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3902 as_bad (_("bad personality routine number"));
3903 ignore_rest_of_line ();
3907 unwind
.personality_index
= exp
.X_add_number
;
3909 demand_empty_rest_of_line ();
3913 /* Parse a personality directive. */
3916 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("duplicate .personality directive"));
3926 c
= get_symbol_name (& name
);
3927 p
= input_line_pointer
;
3929 ++ input_line_pointer
;
3930 unwind
.personality_routine
= symbol_find_or_make (name
);
3932 demand_empty_rest_of_line ();
3936 /* Parse a directive saving core registers. */
3939 s_arm_unwind_save_core (void)
3945 range
= parse_reg_list (&input_line_pointer
);
3948 as_bad (_("expected register list"));
3949 ignore_rest_of_line ();
3953 demand_empty_rest_of_line ();
3955 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3956 into .unwind_save {..., sp...}. We aren't bothered about the value of
3957 ip because it is clobbered by calls. */
3958 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3959 && (range
& 0x3000) == 0x1000)
3961 unwind
.opcode_count
--;
3962 unwind
.sp_restored
= 0;
3963 range
= (range
| 0x2000) & ~0x1000;
3964 unwind
.pending_offset
= 0;
3970 /* See if we can use the short opcodes. These pop a block of up to 8
3971 registers starting with r4, plus maybe r14. */
3972 for (n
= 0; n
< 8; n
++)
3974 /* Break at the first non-saved register. */
3975 if ((range
& (1 << (n
+ 4))) == 0)
3978 /* See if there are any other bits set. */
3979 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3981 /* Use the long form. */
3982 op
= 0x8000 | ((range
>> 4) & 0xfff);
3983 add_unwind_opcode (op
, 2);
3987 /* Use the short form. */
3989 op
= 0xa8; /* Pop r14. */
3991 op
= 0xa0; /* Do not pop r14. */
3993 add_unwind_opcode (op
, 1);
4000 op
= 0xb100 | (range
& 0xf);
4001 add_unwind_opcode (op
, 2);
4004 /* Record the number of bytes pushed. */
4005 for (n
= 0; n
< 16; n
++)
4007 if (range
& (1 << n
))
4008 unwind
.frame_size
+= 4;
4013 /* Parse a directive saving FPA registers. */
4016 s_arm_unwind_save_fpa (int reg
)
4022 /* Get Number of registers to transfer. */
4023 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4026 exp
.X_op
= O_illegal
;
4028 if (exp
.X_op
!= O_constant
)
4030 as_bad (_("expected , <constant>"));
4031 ignore_rest_of_line ();
4035 num_regs
= exp
.X_add_number
;
4037 if (num_regs
< 1 || num_regs
> 4)
4039 as_bad (_("number of registers must be in the range [1:4]"));
4040 ignore_rest_of_line ();
4044 demand_empty_rest_of_line ();
4049 op
= 0xb4 | (num_regs
- 1);
4050 add_unwind_opcode (op
, 1);
4055 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4056 add_unwind_opcode (op
, 2);
4058 unwind
.frame_size
+= num_regs
* 12;
4062 /* Parse a directive saving VFP registers for ARMv6 and above. */
4065 s_arm_unwind_save_vfp_armv6 (void)
4070 int num_vfpv3_regs
= 0;
4071 int num_regs_below_16
;
4073 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4076 as_bad (_("expected register list"));
4077 ignore_rest_of_line ();
4081 demand_empty_rest_of_line ();
4083 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4084 than FSTMX/FLDMX-style ones). */
4086 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4088 num_vfpv3_regs
= count
;
4089 else if (start
+ count
> 16)
4090 num_vfpv3_regs
= start
+ count
- 16;
4092 if (num_vfpv3_regs
> 0)
4094 int start_offset
= start
> 16 ? start
- 16 : 0;
4095 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4096 add_unwind_opcode (op
, 2);
4099 /* Generate opcode for registers numbered in the range 0 .. 15. */
4100 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4101 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4102 if (num_regs_below_16
> 0)
4104 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4105 add_unwind_opcode (op
, 2);
4108 unwind
.frame_size
+= count
* 8;
4112 /* Parse a directive saving VFP registers for pre-ARMv6. */
4115 s_arm_unwind_save_vfp (void)
4121 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4124 as_bad (_("expected register list"));
4125 ignore_rest_of_line ();
4129 demand_empty_rest_of_line ();
4134 op
= 0xb8 | (count
- 1);
4135 add_unwind_opcode (op
, 1);
4140 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4141 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8 + 4;
4147 /* Parse a directive saving iWMMXt data registers. */
4150 s_arm_unwind_save_mmxwr (void)
4158 if (*input_line_pointer
== '{')
4159 input_line_pointer
++;
4163 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4167 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4172 as_tsktsk (_("register list not in ascending order"));
4175 if (*input_line_pointer
== '-')
4177 input_line_pointer
++;
4178 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4181 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4184 else if (reg
>= hi_reg
)
4186 as_bad (_("bad register range"));
4189 for (; reg
< hi_reg
; reg
++)
4193 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4195 skip_past_char (&input_line_pointer
, '}');
4197 demand_empty_rest_of_line ();
4199 /* Generate any deferred opcodes because we're going to be looking at
4201 flush_pending_unwind ();
4203 for (i
= 0; i
< 16; i
++)
4205 if (mask
& (1 << i
))
4206 unwind
.frame_size
+= 8;
4209 /* Attempt to combine with a previous opcode. We do this because gcc
4210 likes to output separate unwind directives for a single block of
4212 if (unwind
.opcode_count
> 0)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4215 if ((i
& 0xf8) == 0xc0)
4218 /* Only merge if the blocks are contiguous. */
4221 if ((mask
& 0xfe00) == (1 << 9))
4223 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4224 unwind
.opcode_count
--;
4227 else if (i
== 6 && unwind
.opcode_count
>= 2)
4229 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4233 op
= 0xffff << (reg
- 1);
4235 && ((mask
& op
) == (1u << (reg
- 1))))
4237 op
= (1 << (reg
+ i
+ 1)) - 1;
4238 op
&= ~((1 << reg
) - 1);
4240 unwind
.opcode_count
-= 2;
4247 /* We want to generate opcodes in the order the registers have been
4248 saved, ie. descending order. */
4249 for (reg
= 15; reg
>= -1; reg
--)
4251 /* Save registers in blocks. */
4253 || !(mask
& (1 << reg
)))
4255 /* We found an unsaved reg. Generate opcodes to save the
4262 op
= 0xc0 | (hi_reg
- 10);
4263 add_unwind_opcode (op
, 1);
4268 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4269 add_unwind_opcode (op
, 2);
4278 ignore_rest_of_line ();
4282 s_arm_unwind_save_mmxwcg (void)
4289 if (*input_line_pointer
== '{')
4290 input_line_pointer
++;
4292 skip_whitespace (input_line_pointer
);
4296 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4306 as_tsktsk (_("register list not in ascending order"));
4309 if (*input_line_pointer
== '-')
4311 input_line_pointer
++;
4312 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4318 else if (reg
>= hi_reg
)
4320 as_bad (_("bad register range"));
4323 for (; reg
< hi_reg
; reg
++)
4327 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4329 skip_past_char (&input_line_pointer
, '}');
4331 demand_empty_rest_of_line ();
4333 /* Generate any deferred opcodes because we're going to be looking at
4335 flush_pending_unwind ();
4337 for (reg
= 0; reg
< 16; reg
++)
4339 if (mask
& (1 << reg
))
4340 unwind
.frame_size
+= 4;
4343 add_unwind_opcode (op
, 2);
4346 ignore_rest_of_line ();
4350 /* Parse an unwind_save directive.
4351 If the argument is non-zero, this is a .vsave directive. */
4354 s_arm_unwind_save (int arch_v6
)
4357 struct reg_entry
*reg
;
4358 bfd_boolean had_brace
= FALSE
;
4360 if (!unwind
.proc_start
)
4361 as_bad (MISSING_FNSTART
);
4363 /* Figure out what sort of save we have. */
4364 peek
= input_line_pointer
;
4372 reg
= arm_reg_parse_multi (&peek
);
4376 as_bad (_("register expected"));
4377 ignore_rest_of_line ();
4386 as_bad (_("FPA .unwind_save does not take a register list"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
= peek
;
4391 s_arm_unwind_save_fpa (reg
->number
);
4395 s_arm_unwind_save_core ();
4400 s_arm_unwind_save_vfp_armv6 ();
4402 s_arm_unwind_save_vfp ();
4405 case REG_TYPE_MMXWR
:
4406 s_arm_unwind_save_mmxwr ();
4409 case REG_TYPE_MMXWCG
:
4410 s_arm_unwind_save_mmxwcg ();
4414 as_bad (_(".unwind_save does not support this kind of register"));
4415 ignore_rest_of_line ();
4420 /* Parse an unwind_movsp directive. */
4423 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4429 if (!unwind
.proc_start
)
4430 as_bad (MISSING_FNSTART
);
4432 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4435 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4436 ignore_rest_of_line ();
4440 /* Optional constant. */
4441 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4443 if (immediate_for_directive (&offset
) == FAIL
)
4449 demand_empty_rest_of_line ();
4451 if (reg
== REG_SP
|| reg
== REG_PC
)
4453 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4457 if (unwind
.fp_reg
!= REG_SP
)
4458 as_bad (_("unexpected .unwind_movsp directive"));
4460 /* Generate opcode to restore the value. */
4462 add_unwind_opcode (op
, 1);
4464 /* Record the information for later. */
4465 unwind
.fp_reg
= reg
;
4466 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4467 unwind
.sp_restored
= 1;
4470 /* Parse an unwind_pad directive. */
4473 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4477 if (!unwind
.proc_start
)
4478 as_bad (MISSING_FNSTART
);
4480 if (immediate_for_directive (&offset
) == FAIL
)
4485 as_bad (_("stack increment must be multiple of 4"));
4486 ignore_rest_of_line ();
4490 /* Don't generate any opcodes, just record the details for later. */
4491 unwind
.frame_size
+= offset
;
4492 unwind
.pending_offset
+= offset
;
4494 demand_empty_rest_of_line ();
4497 /* Parse an unwind_setfp directive. */
4500 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4506 if (!unwind
.proc_start
)
4507 as_bad (MISSING_FNSTART
);
4509 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4513 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4517 as_bad (_("expected <reg>, <reg>"));
4518 ignore_rest_of_line ();
4522 /* Optional constant. */
4523 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4525 if (immediate_for_directive (&offset
) == FAIL
)
4531 demand_empty_rest_of_line ();
4533 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4535 as_bad (_("register must be either sp or set by a previous"
4536 "unwind_movsp directive"));
4540 /* Don't generate any opcodes, just record the information for later. */
4541 unwind
.fp_reg
= fp_reg
;
4543 if (sp_reg
== REG_SP
)
4544 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4546 unwind
.fp_offset
-= offset
;
4549 /* Parse an unwind_raw directive. */
4552 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4555 /* This is an arbitrary limit. */
4556 unsigned char op
[16];
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4563 if (exp
.X_op
== O_constant
4564 && skip_past_comma (&input_line_pointer
) != FAIL
)
4566 unwind
.frame_size
+= exp
.X_add_number
;
4570 exp
.X_op
= O_illegal
;
4572 if (exp
.X_op
!= O_constant
)
4574 as_bad (_("expected <offset>, <opcode>"));
4575 ignore_rest_of_line ();
4581 /* Parse the opcode. */
4586 as_bad (_("unwind opcode too long"));
4587 ignore_rest_of_line ();
4589 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4591 as_bad (_("invalid unwind opcode"));
4592 ignore_rest_of_line ();
4595 op
[count
++] = exp
.X_add_number
;
4597 /* Parse the next byte. */
4598 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4604 /* Add the opcode bytes in reverse order. */
4606 add_unwind_opcode (op
[count
], 1);
4608 demand_empty_rest_of_line ();
4612 /* Parse a .eabi_attribute directive. */
4615 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4617 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4619 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4620 attributes_set_explicitly
[tag
] = 1;
4623 /* Emit a tls fix for the symbol. */
4626 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4630 #ifdef md_flush_pending_output
4631 md_flush_pending_output ();
4634 #ifdef md_cons_align
4638 /* Since we're just labelling the code, there's no need to define a
4641 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4642 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4643 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4644 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4646 #endif /* OBJ_ELF */
4648 static void s_arm_arch (int);
4649 static void s_arm_object_arch (int);
4650 static void s_arm_cpu (int);
4651 static void s_arm_fpu (int);
4652 static void s_arm_arch_extension (int);
4657 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4664 if (exp
.X_op
== O_symbol
)
4665 exp
.X_op
= O_secrel
;
4667 emit_expr (&exp
, 4);
4669 while (*input_line_pointer
++ == ',');
4671 input_line_pointer
--;
4672 demand_empty_rest_of_line ();
4676 /* This table describes all the machine specific pseudo-ops the assembler
4677 has to support. The fields are:
4678 pseudo-op name without dot
4679 function to call to execute this pseudo-op
4680 Integer arg to pass to the function. */
4682 const pseudo_typeS md_pseudo_table
[] =
4684 /* Never called because '.req' does not start a line. */
4685 { "req", s_req
, 0 },
4686 /* Following two are likewise never called. */
4689 { "unreq", s_unreq
, 0 },
4690 { "bss", s_bss
, 0 },
4691 { "align", s_align_ptwo
, 2 },
4692 { "arm", s_arm
, 0 },
4693 { "thumb", s_thumb
, 0 },
4694 { "code", s_code
, 0 },
4695 { "force_thumb", s_force_thumb
, 0 },
4696 { "thumb_func", s_thumb_func
, 0 },
4697 { "thumb_set", s_thumb_set
, 0 },
4698 { "even", s_even
, 0 },
4699 { "ltorg", s_ltorg
, 0 },
4700 { "pool", s_ltorg
, 0 },
4701 { "syntax", s_syntax
, 0 },
4702 { "cpu", s_arm_cpu
, 0 },
4703 { "arch", s_arm_arch
, 0 },
4704 { "object_arch", s_arm_object_arch
, 0 },
4705 { "fpu", s_arm_fpu
, 0 },
4706 { "arch_extension", s_arm_arch_extension
, 0 },
4708 { "word", s_arm_elf_cons
, 4 },
4709 { "long", s_arm_elf_cons
, 4 },
4710 { "inst.n", s_arm_elf_inst
, 2 },
4711 { "inst.w", s_arm_elf_inst
, 4 },
4712 { "inst", s_arm_elf_inst
, 0 },
4713 { "rel31", s_arm_rel31
, 0 },
4714 { "fnstart", s_arm_unwind_fnstart
, 0 },
4715 { "fnend", s_arm_unwind_fnend
, 0 },
4716 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4717 { "personality", s_arm_unwind_personality
, 0 },
4718 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4719 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4720 { "save", s_arm_unwind_save
, 0 },
4721 { "vsave", s_arm_unwind_save
, 1 },
4722 { "movsp", s_arm_unwind_movsp
, 0 },
4723 { "pad", s_arm_unwind_pad
, 0 },
4724 { "setfp", s_arm_unwind_setfp
, 0 },
4725 { "unwind_raw", s_arm_unwind_raw
, 0 },
4726 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4727 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4731 /* These are used for dwarf. */
4735 /* These are used for dwarf2. */
4736 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4737 { "loc", dwarf2_directive_loc
, 0 },
4738 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4740 { "extend", float_cons
, 'x' },
4741 { "ldouble", float_cons
, 'x' },
4742 { "packed", float_cons
, 'p' },
4744 {"secrel32", pe_directive_secrel
, 0},
4747 /* These are for compatibility with CodeComposer Studio. */
4748 {"ref", s_ccs_ref
, 0},
4749 {"def", s_ccs_def
, 0},
4750 {"asmfunc", s_ccs_asmfunc
, 0},
4751 {"endasmfunc", s_ccs_endasmfunc
, 0},
4756 /* Parser functions used exclusively in instruction operands. */
4758 /* Generic immediate-value read function for use in insn parsing.
4759 STR points to the beginning of the immediate (the leading #);
4760 VAL receives the value; if the value is outside [MIN, MAX]
4761 issue an error. PREFIX_OPT is true if the immediate prefix is
4765 parse_immediate (char **str
, int *val
, int min
, int max
,
4766 bfd_boolean prefix_opt
)
4769 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4770 if (exp
.X_op
!= O_constant
)
4772 inst
.error
= _("constant expression required");
4776 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4778 inst
.error
= _("immediate value out of range");
4782 *val
= exp
.X_add_number
;
4786 /* Less-generic immediate-value read function with the possibility of loading a
4787 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4788 instructions. Puts the result directly in inst.operands[i]. */
4791 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4792 bfd_boolean allow_symbol_p
)
4795 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4798 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4800 if (exp_p
->X_op
== O_constant
)
4802 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4803 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4804 O_constant. We have to be careful not to break compilation for
4805 32-bit X_add_number, though. */
4806 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4808 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4809 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4811 inst
.operands
[i
].regisimm
= 1;
4814 else if (exp_p
->X_op
== O_big
4815 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4817 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4819 /* Bignums have their least significant bits in
4820 generic_bignum[0]. Make sure we put 32 bits in imm and
4821 32 bits in reg, in a (hopefully) portable way. */
4822 gas_assert (parts
!= 0);
4824 /* Make sure that the number is not too big.
4825 PR 11972: Bignums can now be sign-extended to the
4826 size of a .octa so check that the out of range bits
4827 are all zero or all one. */
4828 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4830 LITTLENUM_TYPE m
= -1;
4832 if (generic_bignum
[parts
* 2] != 0
4833 && generic_bignum
[parts
* 2] != m
)
4836 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4837 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4841 inst
.operands
[i
].imm
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].reg
= 0;
4846 for (j
= 0; j
< parts
; j
++, idx
++)
4847 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4848 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4849 inst
.operands
[i
].regisimm
= 1;
4851 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4859 /* Returns the pseudo-register number of an FPA immediate constant,
4860 or FAIL if there isn't a valid constant here. */
4863 parse_fpa_immediate (char ** str
)
4865 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4871 /* First try and match exact strings, this is to guarantee
4872 that some formats will work even for cross assembly. */
4874 for (i
= 0; fp_const
[i
]; i
++)
4876 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4880 *str
+= strlen (fp_const
[i
]);
4881 if (is_end_of_line
[(unsigned char) **str
])
4887 /* Just because we didn't get a match doesn't mean that the constant
4888 isn't valid, just that it is in a format that we don't
4889 automatically recognize. Try parsing it with the standard
4890 expression routines. */
4892 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4894 /* Look for a raw floating point number. */
4895 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4896 && is_end_of_line
[(unsigned char) *save_in
])
4898 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4900 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4902 if (words
[j
] != fp_values
[i
][j
])
4906 if (j
== MAX_LITTLENUMS
)
4914 /* Try and parse a more complex expression, this will probably fail
4915 unless the code uses a floating point prefix (eg "0f"). */
4916 save_in
= input_line_pointer
;
4917 input_line_pointer
= *str
;
4918 if (expression (&exp
) == absolute_section
4919 && exp
.X_op
== O_big
4920 && exp
.X_add_number
< 0)
4922 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4924 #define X_PRECISION 5
4925 #define E_PRECISION 15L
4926 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4930 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4932 if (words
[j
] != fp_values
[i
][j
])
4936 if (j
== MAX_LITTLENUMS
)
4938 *str
= input_line_pointer
;
4939 input_line_pointer
= save_in
;
4946 *str
= input_line_pointer
;
4947 input_line_pointer
= save_in
;
4948 inst
.error
= _("invalid FPA immediate expression");
4952 /* Returns 1 if a number has "quarter-precision" float format
4953 0baBbbbbbc defgh000 00000000 00000000. */
4956 is_quarter_float (unsigned imm
)
4958 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4959 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4963 /* Detect the presence of a floating point or integer zero constant,
4967 parse_ifimm_zero (char **in
)
4971 if (!is_immediate_prefix (**in
))
4973 /* In unified syntax, all prefixes are optional. */
4974 if (!unified_syntax
)
4980 /* Accept #0x0 as a synonym for #0. */
4981 if (strncmp (*in
, "0x", 2) == 0)
4984 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4989 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4990 &generic_floating_point_number
);
4993 && generic_floating_point_number
.sign
== '+'
4994 && (generic_floating_point_number
.low
4995 > generic_floating_point_number
.leader
))
5001 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5002 0baBbbbbbc defgh000 00000000 00000000.
5003 The zero and minus-zero cases need special handling, since they can't be
5004 encoded in the "quarter-precision" float format, but can nonetheless be
5005 loaded as integer constants. */
5008 parse_qfloat_immediate (char **ccp
, int *immed
)
5012 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5013 int found_fpchar
= 0;
5015 skip_past_char (&str
, '#');
5017 /* We must not accidentally parse an integer as a floating-point number. Make
5018 sure that the value we parse is not an integer by checking for special
5019 characters '.' or 'e'.
5020 FIXME: This is a horrible hack, but doing better is tricky because type
5021 information isn't in a very usable state at parse time. */
5023 skip_whitespace (fpnum
);
5025 if (strncmp (fpnum
, "0x", 2) == 0)
5029 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5030 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5040 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5042 unsigned fpword
= 0;
5045 /* Our FP word must be 32 bits (single-precision FP). */
5046 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5048 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5052 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5065 /* Shift operands. */
5068 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5071 struct asm_shift_name
5074 enum shift_kind kind
;
5077 /* Third argument to parse_shift. */
5078 enum parse_shift_mode
5080 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5081 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5082 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5083 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5084 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5087 /* Parse a <shift> specifier on an ARM data processing instruction.
5088 This has three forms:
5090 (LSL|LSR|ASL|ASR|ROR) Rs
5091 (LSL|LSR|ASL|ASR|ROR) #imm
5094 Note that ASL is assimilated to LSL in the instruction encoding, and
5095 RRX to ROR #0 (which cannot be written as such). */
5098 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5100 const struct asm_shift_name
*shift_name
;
5101 enum shift_kind shift
;
5106 for (p
= *str
; ISALPHA (*p
); p
++)
5111 inst
.error
= _("shift expression expected");
5115 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5118 if (shift_name
== NULL
)
5120 inst
.error
= _("shift expression expected");
5124 shift
= shift_name
->kind
;
5128 case NO_SHIFT_RESTRICT
:
5129 case SHIFT_IMMEDIATE
: break;
5131 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5132 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5134 inst
.error
= _("'LSL' or 'ASR' required");
5139 case SHIFT_LSL_IMMEDIATE
:
5140 if (shift
!= SHIFT_LSL
)
5142 inst
.error
= _("'LSL' required");
5147 case SHIFT_ASR_IMMEDIATE
:
5148 if (shift
!= SHIFT_ASR
)
5150 inst
.error
= _("'ASR' required");
5158 if (shift
!= SHIFT_RRX
)
5160 /* Whitespace can appear here if the next thing is a bare digit. */
5161 skip_whitespace (p
);
5163 if (mode
== NO_SHIFT_RESTRICT
5164 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5166 inst
.operands
[i
].imm
= reg
;
5167 inst
.operands
[i
].immisreg
= 1;
5169 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5172 inst
.operands
[i
].shift_kind
= shift
;
5173 inst
.operands
[i
].shifted
= 1;
5178 /* Parse a <shifter_operand> for an ARM data processing instruction:
5181 #<immediate>, <rotate>
5185 where <shift> is defined by parse_shift above, and <rotate> is a
5186 multiple of 2 between 0 and 30. Validation of immediate operands
5187 is deferred to md_apply_fix. */
5190 parse_shifter_operand (char **str
, int i
)
5195 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5197 inst
.operands
[i
].reg
= value
;
5198 inst
.operands
[i
].isreg
= 1;
5200 /* parse_shift will override this if appropriate */
5201 inst
.reloc
.exp
.X_op
= O_constant
;
5202 inst
.reloc
.exp
.X_add_number
= 0;
5204 if (skip_past_comma (str
) == FAIL
)
5207 /* Shift operation on register. */
5208 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5211 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5214 if (skip_past_comma (str
) == SUCCESS
)
5216 /* #x, y -- ie explicit rotation by Y. */
5217 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5220 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5222 inst
.error
= _("constant expression expected");
5226 value
= exp
.X_add_number
;
5227 if (value
< 0 || value
> 30 || value
% 2 != 0)
5229 inst
.error
= _("invalid rotation");
5232 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5234 inst
.error
= _("invalid constant");
5238 /* Encode as specified. */
5239 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5243 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5244 inst
.reloc
.pc_rel
= 0;
5248 /* Group relocation information. Each entry in the table contains the
5249 textual name of the relocation as may appear in assembler source
5250 and must end with a colon.
5251 Along with this textual name are the relocation codes to be used if
5252 the corresponding instruction is an ALU instruction (ADD or SUB only),
5253 an LDR, an LDRS, or an LDC. */
5255 struct group_reloc_table_entry
5266 /* Varieties of non-ALU group relocation. */
5273 static struct group_reloc_table_entry group_reloc_table
[] =
5274 { /* Program counter relative: */
5276 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5281 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5282 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5286 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5291 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5292 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5293 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5294 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5296 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5297 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5298 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5299 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5300 /* Section base relative */
5302 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5307 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5308 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5312 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5318 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5323 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5326 /* Absolute thumb alu relocations. */
5328 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5333 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5338 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5343 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5348 /* Given the address of a pointer pointing to the textual name of a group
5349 relocation as may appear in assembler source, attempt to find its details
5350 in group_reloc_table. The pointer will be updated to the character after
5351 the trailing colon. On failure, FAIL will be returned; SUCCESS
5352 otherwise. On success, *entry will be updated to point at the relevant
5353 group_reloc_table entry. */
5356 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5359 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5361 int length
= strlen (group_reloc_table
[i
].name
);
5363 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5364 && (*str
)[length
] == ':')
5366 *out
= &group_reloc_table
[i
];
5367 *str
+= (length
+ 1);
5375 /* Parse a <shifter_operand> for an ARM data processing instruction
5376 (as for parse_shifter_operand) where group relocations are allowed:
5379 #<immediate>, <rotate>
5380 #:<group_reloc>:<expression>
5384 where <group_reloc> is one of the strings defined in group_reloc_table.
5385 The hashes are optional.
5387 Everything else is as for parse_shifter_operand. */
5389 static parse_operand_result
5390 parse_shifter_operand_group_reloc (char **str
, int i
)
5392 /* Determine if we have the sequence of characters #: or just :
5393 coming next. If we do, then we check for a group relocation.
5394 If we don't, punt the whole lot to parse_shifter_operand. */
5396 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5397 || (*str
)[0] == ':')
5399 struct group_reloc_table_entry
*entry
;
5401 if ((*str
)[0] == '#')
5406 /* Try to parse a group relocation. Anything else is an error. */
5407 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5409 inst
.error
= _("unknown group relocation");
5410 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5413 /* We now have the group relocation table entry corresponding to
5414 the name in the assembler source. Next, we parse the expression. */
5415 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5416 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5418 /* Record the relocation type (always the ALU variant here). */
5419 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5420 gas_assert (inst
.reloc
.type
!= 0);
5422 return PARSE_OPERAND_SUCCESS
;
5425 return parse_shifter_operand (str
, i
) == SUCCESS
5426 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5428 /* Never reached. */
5431 /* Parse a Neon alignment expression. Information is written to
5432 inst.operands[i]. We assume the initial ':' has been skipped.
5434 align .imm = align << 8, .immisalign=1, .preind=0 */
5435 static parse_operand_result
5436 parse_neon_alignment (char **str
, int i
)
5441 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5443 if (exp
.X_op
!= O_constant
)
5445 inst
.error
= _("alignment must be constant");
5446 return PARSE_OPERAND_FAIL
;
5449 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5450 inst
.operands
[i
].immisalign
= 1;
5451 /* Alignments are not pre-indexes. */
5452 inst
.operands
[i
].preind
= 0;
5455 return PARSE_OPERAND_SUCCESS
;
5458 /* Parse all forms of an ARM address expression. Information is written
5459 to inst.operands[i] and/or inst.reloc.
5461 Preindexed addressing (.preind=1):
5463 [Rn, #offset] .reg=Rn .reloc.exp=offset
5464 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5465 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 .shift_kind=shift .reloc.exp=shift_imm
5468 These three may have a trailing ! which causes .writeback to be set also.
5470 Postindexed addressing (.postind=1, .writeback=1):
5472 [Rn], #offset .reg=Rn .reloc.exp=offset
5473 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5474 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5475 .shift_kind=shift .reloc.exp=shift_imm
5477 Unindexed addressing (.preind=0, .postind=0):
5479 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5483 [Rn]{!} shorthand for [Rn,#0]{!}
5484 =immediate .isreg=0 .reloc.exp=immediate
5485 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5487 It is the caller's responsibility to check for addressing modes not
5488 supported by the instruction, and to set inst.reloc.type. */
5490 static parse_operand_result
5491 parse_address_main (char **str
, int i
, int group_relocations
,
5492 group_reloc_type group_type
)
5497 if (skip_past_char (&p
, '[') == FAIL
)
5499 if (skip_past_char (&p
, '=') == FAIL
)
5501 /* Bare address - translate to PC-relative offset. */
5502 inst
.reloc
.pc_rel
= 1;
5503 inst
.operands
[i
].reg
= REG_PC
;
5504 inst
.operands
[i
].isreg
= 1;
5505 inst
.operands
[i
].preind
= 1;
5507 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5508 return PARSE_OPERAND_FAIL
;
5510 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5511 /*allow_symbol_p=*/TRUE
))
5512 return PARSE_OPERAND_FAIL
;
5515 return PARSE_OPERAND_SUCCESS
;
5518 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5519 skip_whitespace (p
);
5521 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5523 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5524 return PARSE_OPERAND_FAIL
;
5526 inst
.operands
[i
].reg
= reg
;
5527 inst
.operands
[i
].isreg
= 1;
5529 if (skip_past_comma (&p
) == SUCCESS
)
5531 inst
.operands
[i
].preind
= 1;
5534 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5536 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5538 inst
.operands
[i
].imm
= reg
;
5539 inst
.operands
[i
].immisreg
= 1;
5541 if (skip_past_comma (&p
) == SUCCESS
)
5542 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5543 return PARSE_OPERAND_FAIL
;
5545 else if (skip_past_char (&p
, ':') == SUCCESS
)
5547 /* FIXME: '@' should be used here, but it's filtered out by generic
5548 code before we get to see it here. This may be subject to
5550 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5552 if (result
!= PARSE_OPERAND_SUCCESS
)
5557 if (inst
.operands
[i
].negative
)
5559 inst
.operands
[i
].negative
= 0;
5563 if (group_relocations
5564 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5566 struct group_reloc_table_entry
*entry
;
5568 /* Skip over the #: or : sequence. */
5574 /* Try to parse a group relocation. Anything else is an
5576 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5578 inst
.error
= _("unknown group relocation");
5579 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5582 /* We now have the group relocation table entry corresponding to
5583 the name in the assembler source. Next, we parse the
5585 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5586 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5588 /* Record the relocation type. */
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5596 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5600 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5607 if (inst
.reloc
.type
== 0)
5609 inst
.error
= _("this group relocation is not allowed on this instruction");
5610 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5616 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5617 return PARSE_OPERAND_FAIL
;
5618 /* If the offset is 0, find out if it's a +0 or -0. */
5619 if (inst
.reloc
.exp
.X_op
== O_constant
5620 && inst
.reloc
.exp
.X_add_number
== 0)
5622 skip_whitespace (q
);
5626 skip_whitespace (q
);
5629 inst
.operands
[i
].negative
= 1;
5634 else if (skip_past_char (&p
, ':') == SUCCESS
)
5636 /* FIXME: '@' should be used here, but it's filtered out by generic code
5637 before we get to see it here. This may be subject to change. */
5638 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5640 if (result
!= PARSE_OPERAND_SUCCESS
)
5644 if (skip_past_char (&p
, ']') == FAIL
)
5646 inst
.error
= _("']' expected");
5647 return PARSE_OPERAND_FAIL
;
5650 if (skip_past_char (&p
, '!') == SUCCESS
)
5651 inst
.operands
[i
].writeback
= 1;
5653 else if (skip_past_comma (&p
) == SUCCESS
)
5655 if (skip_past_char (&p
, '{') == SUCCESS
)
5657 /* [Rn], {expr} - unindexed, with option */
5658 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5659 0, 255, TRUE
) == FAIL
)
5660 return PARSE_OPERAND_FAIL
;
5662 if (skip_past_char (&p
, '}') == FAIL
)
5664 inst
.error
= _("'}' expected at end of 'option' field");
5665 return PARSE_OPERAND_FAIL
;
5667 if (inst
.operands
[i
].preind
)
5669 inst
.error
= _("cannot combine index with option");
5670 return PARSE_OPERAND_FAIL
;
5673 return PARSE_OPERAND_SUCCESS
;
5677 inst
.operands
[i
].postind
= 1;
5678 inst
.operands
[i
].writeback
= 1;
5680 if (inst
.operands
[i
].preind
)
5682 inst
.error
= _("cannot combine pre- and post-indexing");
5683 return PARSE_OPERAND_FAIL
;
5687 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5689 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5691 /* We might be using the immediate for alignment already. If we
5692 are, OR the register number into the low-order bits. */
5693 if (inst
.operands
[i
].immisalign
)
5694 inst
.operands
[i
].imm
|= reg
;
5696 inst
.operands
[i
].imm
= reg
;
5697 inst
.operands
[i
].immisreg
= 1;
5699 if (skip_past_comma (&p
) == SUCCESS
)
5700 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5701 return PARSE_OPERAND_FAIL
;
5706 if (inst
.operands
[i
].negative
)
5708 inst
.operands
[i
].negative
= 0;
5711 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5712 return PARSE_OPERAND_FAIL
;
5713 /* If the offset is 0, find out if it's a +0 or -0. */
5714 if (inst
.reloc
.exp
.X_op
== O_constant
5715 && inst
.reloc
.exp
.X_add_number
== 0)
5717 skip_whitespace (q
);
5721 skip_whitespace (q
);
5724 inst
.operands
[i
].negative
= 1;
5730 /* If at this point neither .preind nor .postind is set, we have a
5731 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5732 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5734 inst
.operands
[i
].preind
= 1;
5735 inst
.reloc
.exp
.X_op
= O_constant
;
5736 inst
.reloc
.exp
.X_add_number
= 0;
5739 return PARSE_OPERAND_SUCCESS
;
5743 parse_address (char **str
, int i
)
5745 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5749 static parse_operand_result
5750 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5752 return parse_address_main (str
, i
, 1, type
);
5755 /* Parse an operand for a MOVW or MOVT instruction. */
5757 parse_half (char **str
)
5762 skip_past_char (&p
, '#');
5763 if (strncasecmp (p
, ":lower16:", 9) == 0)
5764 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5765 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5766 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5768 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5771 skip_whitespace (p
);
5774 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5777 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5779 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5781 inst
.error
= _("constant expression expected");
5784 if (inst
.reloc
.exp
.X_add_number
< 0
5785 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5787 inst
.error
= _("immediate value out of range");
5795 /* Miscellaneous. */
5797 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5798 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5800 parse_psr (char **str
, bfd_boolean lhs
)
5803 unsigned long psr_field
;
5804 const struct asm_psr
*psr
;
5806 bfd_boolean is_apsr
= FALSE
;
5807 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5809 /* PR gas/12698: If the user has specified -march=all then m_profile will
5810 be TRUE, but we want to ignore it in this case as we are building for any
5811 CPU type, including non-m variants. */
5812 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5815 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5816 feature for ease of use and backwards compatibility. */
5818 if (strncasecmp (p
, "SPSR", 4) == 0)
5821 goto unsupported_psr
;
5823 psr_field
= SPSR_BIT
;
5825 else if (strncasecmp (p
, "CPSR", 4) == 0)
5828 goto unsupported_psr
;
5832 else if (strncasecmp (p
, "APSR", 4) == 0)
5834 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5835 and ARMv7-R architecture CPUs. */
5844 while (ISALNUM (*p
) || *p
== '_');
5846 if (strncasecmp (start
, "iapsr", 5) == 0
5847 || strncasecmp (start
, "eapsr", 5) == 0
5848 || strncasecmp (start
, "xpsr", 4) == 0
5849 || strncasecmp (start
, "psr", 3) == 0)
5850 p
= start
+ strcspn (start
, "rR") + 1;
5852 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5858 /* If APSR is being written, a bitfield may be specified. Note that
5859 APSR itself is handled above. */
5860 if (psr
->field
<= 3)
5862 psr_field
= psr
->field
;
5868 /* M-profile MSR instructions have the mask field set to "10", except
5869 *PSR variants which modify APSR, which may use a different mask (and
5870 have been handled already). Do that by setting the PSR_f field
5872 return psr
->field
| (lhs
? PSR_f
: 0);
5875 goto unsupported_psr
;
5881 /* A suffix follows. */
5887 while (ISALNUM (*p
) || *p
== '_');
5891 /* APSR uses a notation for bits, rather than fields. */
5892 unsigned int nzcvq_bits
= 0;
5893 unsigned int g_bit
= 0;
5896 for (bit
= start
; bit
!= p
; bit
++)
5898 switch (TOLOWER (*bit
))
5901 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5913 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5917 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5921 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5925 inst
.error
= _("unexpected bit specified after APSR");
5930 if (nzcvq_bits
== 0x1f)
5935 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5937 inst
.error
= _("selected processor does not "
5938 "support DSP extension");
5945 if ((nzcvq_bits
& 0x20) != 0
5946 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5947 || (g_bit
& 0x2) != 0)
5949 inst
.error
= _("bad bitmask specified after APSR");
5955 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5960 psr_field
|= psr
->field
;
5966 goto error
; /* Garbage after "[CS]PSR". */
5968 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5969 is deprecated, but allow it anyway. */
5973 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5976 else if (!m_profile
)
5977 /* These bits are never right for M-profile devices: don't set them
5978 (only code paths which read/write APSR reach here). */
5979 psr_field
|= (PSR_c
| PSR_f
);
5985 inst
.error
= _("selected processor does not support requested special "
5986 "purpose register");
5990 inst
.error
= _("flag for {c}psr instruction expected");
5994 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5995 value suitable for splatting into the AIF field of the instruction. */
5998 parse_cps_flags (char **str
)
6007 case '\0': case ',':
6010 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6011 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6012 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6015 inst
.error
= _("unrecognized CPS flag");
6020 if (saw_a_flag
== 0)
6022 inst
.error
= _("missing CPS flags");
6030 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6031 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6034 parse_endian_specifier (char **str
)
6039 if (strncasecmp (s
, "BE", 2))
6041 else if (strncasecmp (s
, "LE", 2))
6045 inst
.error
= _("valid endian specifiers are be or le");
6049 if (ISALNUM (s
[2]) || s
[2] == '_')
6051 inst
.error
= _("valid endian specifiers are be or le");
6056 return little_endian
;
6059 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6060 value suitable for poking into the rotate field of an sxt or sxta
6061 instruction, or FAIL on error. */
6064 parse_ror (char **str
)
6069 if (strncasecmp (s
, "ROR", 3) == 0)
6073 inst
.error
= _("missing rotation field after comma");
6077 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6082 case 0: *str
= s
; return 0x0;
6083 case 8: *str
= s
; return 0x1;
6084 case 16: *str
= s
; return 0x2;
6085 case 24: *str
= s
; return 0x3;
6088 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6093 /* Parse a conditional code (from conds[] below). The value returned is in the
6094 range 0 .. 14, or FAIL. */
6096 parse_cond (char **str
)
6099 const struct asm_cond
*c
;
6101 /* Condition codes are always 2 characters, so matching up to
6102 3 characters is sufficient. */
6107 while (ISALPHA (*q
) && n
< 3)
6109 cond
[n
] = TOLOWER (*q
);
6114 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6117 inst
.error
= _("condition required");
6125 /* Record a use of the given feature. */
6127 record_feature_use (const arm_feature_set
*feature
)
6130 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6132 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6135 /* If the given feature available in the selected CPU, mark it as used.
6136 Returns TRUE iff feature is available. */
6138 mark_feature_used (const arm_feature_set
*feature
)
6140 /* Ensure the option is valid on the current architecture. */
6141 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6144 /* Add the appropriate architecture feature for the barrier option used.
6146 record_feature_use (feature
);
6151 /* Parse an option for a barrier instruction. Returns the encoding for the
6154 parse_barrier (char **str
)
6157 const struct asm_barrier_opt
*o
;
6160 while (ISALPHA (*q
))
6163 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6168 if (!mark_feature_used (&o
->arch
))
6175 /* Parse the operands of a table branch instruction. Similar to a memory
6178 parse_tb (char **str
)
6183 if (skip_past_char (&p
, '[') == FAIL
)
6185 inst
.error
= _("'[' expected");
6189 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6191 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6194 inst
.operands
[0].reg
= reg
;
6196 if (skip_past_comma (&p
) == FAIL
)
6198 inst
.error
= _("',' expected");
6202 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6204 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6207 inst
.operands
[0].imm
= reg
;
6209 if (skip_past_comma (&p
) == SUCCESS
)
6211 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6213 if (inst
.reloc
.exp
.X_add_number
!= 1)
6215 inst
.error
= _("invalid shift");
6218 inst
.operands
[0].shifted
= 1;
6221 if (skip_past_char (&p
, ']') == FAIL
)
6223 inst
.error
= _("']' expected");
6230 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6231 information on the types the operands can take and how they are encoded.
6232 Up to four operands may be read; this function handles setting the
6233 ".present" field for each read operand itself.
6234 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6235 else returns FAIL. */
6238 parse_neon_mov (char **str
, int *which_operand
)
6240 int i
= *which_operand
, val
;
6241 enum arm_reg_type rtype
;
6243 struct neon_type_el optype
;
6245 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6247 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6248 inst
.operands
[i
].reg
= val
;
6249 inst
.operands
[i
].isscalar
= 1;
6250 inst
.operands
[i
].vectype
= optype
;
6251 inst
.operands
[i
++].present
= 1;
6253 if (skip_past_comma (&ptr
) == FAIL
)
6256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6259 inst
.operands
[i
].reg
= val
;
6260 inst
.operands
[i
].isreg
= 1;
6261 inst
.operands
[i
].present
= 1;
6263 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6266 /* Cases 0, 1, 2, 3, 5 (D only). */
6267 if (skip_past_comma (&ptr
) == FAIL
)
6270 inst
.operands
[i
].reg
= val
;
6271 inst
.operands
[i
].isreg
= 1;
6272 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6273 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6274 inst
.operands
[i
].isvec
= 1;
6275 inst
.operands
[i
].vectype
= optype
;
6276 inst
.operands
[i
++].present
= 1;
6278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6280 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6281 Case 13: VMOV <Sd>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].present
= 1;
6286 if (rtype
== REG_TYPE_NQ
)
6288 first_error (_("can't use Neon quad register here"));
6291 else if (rtype
!= REG_TYPE_VFS
)
6294 if (skip_past_comma (&ptr
) == FAIL
)
6296 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
].present
= 1;
6303 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6306 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6307 Case 1: VMOV<c><q> <Dd>, <Dm>
6308 Case 8: VMOV.F32 <Sd>, <Sm>
6309 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6314 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6315 inst
.operands
[i
].isvec
= 1;
6316 inst
.operands
[i
].vectype
= optype
;
6317 inst
.operands
[i
].present
= 1;
6319 if (skip_past_comma (&ptr
) == SUCCESS
)
6324 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6327 inst
.operands
[i
].reg
= val
;
6328 inst
.operands
[i
].isreg
= 1;
6329 inst
.operands
[i
++].present
= 1;
6331 if (skip_past_comma (&ptr
) == FAIL
)
6334 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6337 inst
.operands
[i
].reg
= val
;
6338 inst
.operands
[i
].isreg
= 1;
6339 inst
.operands
[i
].present
= 1;
6342 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6343 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6344 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6345 Case 10: VMOV.F32 <Sd>, #<imm>
6346 Case 11: VMOV.F64 <Dd>, #<imm> */
6347 inst
.operands
[i
].immisfloat
= 1;
6348 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6350 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6351 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6355 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6359 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6362 inst
.operands
[i
].reg
= val
;
6363 inst
.operands
[i
].isreg
= 1;
6364 inst
.operands
[i
++].present
= 1;
6366 if (skip_past_comma (&ptr
) == FAIL
)
6369 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6371 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isscalar
= 1;
6374 inst
.operands
[i
].present
= 1;
6375 inst
.operands
[i
].vectype
= optype
;
6377 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6379 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6380 inst
.operands
[i
].reg
= val
;
6381 inst
.operands
[i
].isreg
= 1;
6382 inst
.operands
[i
++].present
= 1;
6384 if (skip_past_comma (&ptr
) == FAIL
)
6387 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6390 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6394 inst
.operands
[i
].reg
= val
;
6395 inst
.operands
[i
].isreg
= 1;
6396 inst
.operands
[i
].isvec
= 1;
6397 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6398 inst
.operands
[i
].vectype
= optype
;
6399 inst
.operands
[i
].present
= 1;
6401 if (rtype
== REG_TYPE_VFS
)
6405 if (skip_past_comma (&ptr
) == FAIL
)
6407 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6410 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6413 inst
.operands
[i
].reg
= val
;
6414 inst
.operands
[i
].isreg
= 1;
6415 inst
.operands
[i
].isvec
= 1;
6416 inst
.operands
[i
].issingle
= 1;
6417 inst
.operands
[i
].vectype
= optype
;
6418 inst
.operands
[i
].present
= 1;
6421 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6425 inst
.operands
[i
].reg
= val
;
6426 inst
.operands
[i
].isreg
= 1;
6427 inst
.operands
[i
].isvec
= 1;
6428 inst
.operands
[i
].issingle
= 1;
6429 inst
.operands
[i
].vectype
= optype
;
6430 inst
.operands
[i
].present
= 1;
6435 first_error (_("parse error"));
6439 /* Successfully parsed the operands. Update args. */
6445 first_error (_("expected comma"));
6449 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6453 /* Use this macro when the operand constraints are different
6454 for ARM and THUMB (e.g. ldrd). */
6455 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6456 ((arm_operand) | ((thumb_operand) << 16))
6458 /* Matcher codes for parse_operands. */
6459 enum operand_parse_code
6461 OP_stop
, /* end of line */
6463 OP_RR
, /* ARM register */
6464 OP_RRnpc
, /* ARM register, not r15 */
6465 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6466 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6467 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6468 optional trailing ! */
6469 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6470 OP_RCP
, /* Coprocessor number */
6471 OP_RCN
, /* Coprocessor register */
6472 OP_RF
, /* FPA register */
6473 OP_RVS
, /* VFP single precision register */
6474 OP_RVD
, /* VFP double precision register (0..15) */
6475 OP_RND
, /* Neon double precision register (0..31) */
6476 OP_RNQ
, /* Neon quad precision register */
6477 OP_RVSD
, /* VFP single or double precision register */
6478 OP_RNDQ
, /* Neon double or quad precision register */
6479 OP_RNSDQ
, /* Neon single, double or quad precision register */
6480 OP_RNSC
, /* Neon scalar D[X] */
6481 OP_RVC
, /* VFP control register */
6482 OP_RMF
, /* Maverick F register */
6483 OP_RMD
, /* Maverick D register */
6484 OP_RMFX
, /* Maverick FX register */
6485 OP_RMDX
, /* Maverick DX register */
6486 OP_RMAX
, /* Maverick AX register */
6487 OP_RMDS
, /* Maverick DSPSC register */
6488 OP_RIWR
, /* iWMMXt wR register */
6489 OP_RIWC
, /* iWMMXt wC register */
6490 OP_RIWG
, /* iWMMXt wCG register */
6491 OP_RXA
, /* XScale accumulator register */
6493 OP_REGLST
, /* ARM register list */
6494 OP_VRSLST
, /* VFP single-precision register list */
6495 OP_VRDLST
, /* VFP double-precision register list */
6496 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6497 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6498 OP_NSTRLST
, /* Neon element/structure list */
6500 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6501 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6502 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6503 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6504 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6505 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6506 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6507 OP_VMOV
, /* Neon VMOV operands. */
6508 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6509 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6510 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6512 OP_I0
, /* immediate zero */
6513 OP_I7
, /* immediate value 0 .. 7 */
6514 OP_I15
, /* 0 .. 15 */
6515 OP_I16
, /* 1 .. 16 */
6516 OP_I16z
, /* 0 .. 16 */
6517 OP_I31
, /* 0 .. 31 */
6518 OP_I31w
, /* 0 .. 31, optional trailing ! */
6519 OP_I32
, /* 1 .. 32 */
6520 OP_I32z
, /* 0 .. 32 */
6521 OP_I63
, /* 0 .. 63 */
6522 OP_I63s
, /* -64 .. 63 */
6523 OP_I64
, /* 1 .. 64 */
6524 OP_I64z
, /* 0 .. 64 */
6525 OP_I255
, /* 0 .. 255 */
6527 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6528 OP_I7b
, /* 0 .. 7 */
6529 OP_I15b
, /* 0 .. 15 */
6530 OP_I31b
, /* 0 .. 31 */
6532 OP_SH
, /* shifter operand */
6533 OP_SHG
, /* shifter operand with possible group relocation */
6534 OP_ADDR
, /* Memory address expression (any mode) */
6535 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6536 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6537 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6538 OP_EXP
, /* arbitrary expression */
6539 OP_EXPi
, /* same, with optional immediate prefix */
6540 OP_EXPr
, /* same, with optional relocation suffix */
6541 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6542 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6543 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6545 OP_CPSF
, /* CPS flags */
6546 OP_ENDI
, /* Endianness specifier */
6547 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6548 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6549 OP_COND
, /* conditional code */
6550 OP_TB
, /* Table branch. */
6552 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6554 OP_RRnpc_I0
, /* ARM register or literal 0 */
6555 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6556 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6557 OP_RF_IF
, /* FPA register or immediate */
6558 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6559 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6561 /* Optional operands. */
6562 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6563 OP_oI31b
, /* 0 .. 31 */
6564 OP_oI32b
, /* 1 .. 32 */
6565 OP_oI32z
, /* 0 .. 32 */
6566 OP_oIffffb
, /* 0 .. 65535 */
6567 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6569 OP_oRR
, /* ARM register */
6570 OP_oRRnpc
, /* ARM register, not the PC */
6571 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6572 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6573 OP_oRND
, /* Optional Neon double precision register */
6574 OP_oRNQ
, /* Optional Neon quad precision register */
6575 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6576 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6577 OP_oSHll
, /* LSL immediate */
6578 OP_oSHar
, /* ASR immediate */
6579 OP_oSHllar
, /* LSL or ASR immediate */
6580 OP_oROR
, /* ROR 0/8/16/24 */
6581 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6583 /* Some pre-defined mixed (ARM/THUMB) operands. */
6584 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6585 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6586 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6588 OP_FIRST_OPTIONAL
= OP_oI7b
6591 /* Generic instruction operand parser. This does no encoding and no
6592 semantic validation; it merely squirrels values away in the inst
6593 structure. Returns SUCCESS or FAIL depending on whether the
6594 specified grammar matched. */
6596 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6598 unsigned const int *upat
= pattern
;
6599 char *backtrack_pos
= 0;
6600 const char *backtrack_error
= 0;
6601 int i
, val
= 0, backtrack_index
= 0;
6602 enum arm_reg_type rtype
;
6603 parse_operand_result result
;
6604 unsigned int op_parse_code
;
6606 #define po_char_or_fail(chr) \
6609 if (skip_past_char (&str, chr) == FAIL) \
6614 #define po_reg_or_fail(regtype) \
6617 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6618 & inst.operands[i].vectype); \
6621 first_error (_(reg_expected_msgs[regtype])); \
6624 inst.operands[i].reg = val; \
6625 inst.operands[i].isreg = 1; \
6626 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6627 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6628 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6629 || rtype == REG_TYPE_VFD \
6630 || rtype == REG_TYPE_NQ); \
6634 #define po_reg_or_goto(regtype, label) \
6637 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6638 & inst.operands[i].vectype); \
6642 inst.operands[i].reg = val; \
6643 inst.operands[i].isreg = 1; \
6644 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6645 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6646 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6647 || rtype == REG_TYPE_VFD \
6648 || rtype == REG_TYPE_NQ); \
6652 #define po_imm_or_fail(min, max, popt) \
6655 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6657 inst.operands[i].imm = val; \
6661 #define po_scalar_or_goto(elsz, label) \
6664 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6667 inst.operands[i].reg = val; \
6668 inst.operands[i].isscalar = 1; \
6672 #define po_misc_or_fail(expr) \
6680 #define po_misc_or_fail_no_backtrack(expr) \
6684 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6685 backtrack_pos = 0; \
6686 if (result != PARSE_OPERAND_SUCCESS) \
6691 #define po_barrier_or_imm(str) \
6694 val = parse_barrier (&str); \
6695 if (val == FAIL && ! ISALPHA (*str)) \
6698 /* ISB can only take SY as an option. */ \
6699 || ((inst.instruction & 0xf0) == 0x60 \
6702 inst.error = _("invalid barrier type"); \
6703 backtrack_pos = 0; \
6709 skip_whitespace (str
);
6711 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6713 op_parse_code
= upat
[i
];
6714 if (op_parse_code
>= 1<<16)
6715 op_parse_code
= thumb
? (op_parse_code
>> 16)
6716 : (op_parse_code
& ((1<<16)-1));
6718 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6720 /* Remember where we are in case we need to backtrack. */
6721 gas_assert (!backtrack_pos
);
6722 backtrack_pos
= str
;
6723 backtrack_error
= inst
.error
;
6724 backtrack_index
= i
;
6727 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6728 po_char_or_fail (',');
6730 switch (op_parse_code
)
6738 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6739 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6740 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6741 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6742 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6743 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6745 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6747 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6749 /* Also accept generic coprocessor regs for unknown registers. */
6751 po_reg_or_fail (REG_TYPE_CN
);
6753 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6754 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6755 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6756 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6757 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6758 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6759 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6760 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6761 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6762 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6764 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6766 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6767 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6769 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6771 /* Neon scalar. Using an element size of 8 means that some invalid
6772 scalars are accepted here, so deal with those in later code. */
6773 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6777 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6780 po_imm_or_fail (0, 0, TRUE
);
6785 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6790 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6793 if (parse_ifimm_zero (&str
))
6794 inst
.operands
[i
].imm
= 0;
6798 = _("only floating point zero is allowed as immediate value");
6806 po_scalar_or_goto (8, try_rr
);
6809 po_reg_or_fail (REG_TYPE_RN
);
6815 po_scalar_or_goto (8, try_nsdq
);
6818 po_reg_or_fail (REG_TYPE_NSDQ
);
6824 po_scalar_or_goto (8, try_ndq
);
6827 po_reg_or_fail (REG_TYPE_NDQ
);
6833 po_scalar_or_goto (8, try_vfd
);
6836 po_reg_or_fail (REG_TYPE_VFD
);
6841 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6842 not careful then bad things might happen. */
6843 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6848 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6851 /* There's a possibility of getting a 64-bit immediate here, so
6852 we need special handling. */
6853 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6856 inst
.error
= _("immediate value is out of range");
6864 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6867 po_imm_or_fail (0, 63, TRUE
);
6872 po_char_or_fail ('[');
6873 po_reg_or_fail (REG_TYPE_RN
);
6874 po_char_or_fail (']');
6880 po_reg_or_fail (REG_TYPE_RN
);
6881 if (skip_past_char (&str
, '!') == SUCCESS
)
6882 inst
.operands
[i
].writeback
= 1;
6886 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6887 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6888 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6889 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6890 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6891 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6892 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6893 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6894 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6895 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6896 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6897 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6899 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6901 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6902 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6904 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6905 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6906 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6907 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6909 /* Immediate variants */
6911 po_char_or_fail ('{');
6912 po_imm_or_fail (0, 255, TRUE
);
6913 po_char_or_fail ('}');
6917 /* The expression parser chokes on a trailing !, so we have
6918 to find it first and zap it. */
6921 while (*s
&& *s
!= ',')
6926 inst
.operands
[i
].writeback
= 1;
6928 po_imm_or_fail (0, 31, TRUE
);
6936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6941 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6946 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6948 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6950 val
= parse_reloc (&str
);
6953 inst
.error
= _("unrecognized relocation suffix");
6956 else if (val
!= BFD_RELOC_UNUSED
)
6958 inst
.operands
[i
].imm
= val
;
6959 inst
.operands
[i
].hasreloc
= 1;
6964 /* Operand for MOVW or MOVT. */
6966 po_misc_or_fail (parse_half (&str
));
6969 /* Register or expression. */
6970 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6971 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6973 /* Register or immediate. */
6974 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6975 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6977 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6979 if (!is_immediate_prefix (*str
))
6982 val
= parse_fpa_immediate (&str
);
6985 /* FPA immediates are encoded as registers 8-15.
6986 parse_fpa_immediate has already applied the offset. */
6987 inst
.operands
[i
].reg
= val
;
6988 inst
.operands
[i
].isreg
= 1;
6991 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6992 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6994 /* Two kinds of register. */
6997 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6999 || (rege
->type
!= REG_TYPE_MMXWR
7000 && rege
->type
!= REG_TYPE_MMXWC
7001 && rege
->type
!= REG_TYPE_MMXWCG
))
7003 inst
.error
= _("iWMMXt data or control register expected");
7006 inst
.operands
[i
].reg
= rege
->number
;
7007 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7013 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7015 || (rege
->type
!= REG_TYPE_MMXWC
7016 && rege
->type
!= REG_TYPE_MMXWCG
))
7018 inst
.error
= _("iWMMXt control register expected");
7021 inst
.operands
[i
].reg
= rege
->number
;
7022 inst
.operands
[i
].isreg
= 1;
7027 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7028 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7029 case OP_oROR
: val
= parse_ror (&str
); break;
7030 case OP_COND
: val
= parse_cond (&str
); break;
7031 case OP_oBARRIER_I15
:
7032 po_barrier_or_imm (str
); break;
7034 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7040 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7041 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7043 inst
.error
= _("Banked registers are not available with this "
7049 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7053 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7056 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7058 if (strncasecmp (str
, "APSR_", 5) == 0)
7065 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7066 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7067 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7068 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7069 default: found
= 16;
7073 inst
.operands
[i
].isvec
= 1;
7074 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7075 inst
.operands
[i
].reg
= REG_PC
;
7082 po_misc_or_fail (parse_tb (&str
));
7085 /* Register lists. */
7087 val
= parse_reg_list (&str
);
7090 inst
.operands
[i
].writeback
= 1;
7096 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7104 /* Allow Q registers too. */
7105 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7110 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7112 inst
.operands
[i
].issingle
= 1;
7117 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7122 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7123 &inst
.operands
[i
].vectype
);
7126 /* Addressing modes */
7128 po_misc_or_fail (parse_address (&str
, i
));
7132 po_misc_or_fail_no_backtrack (
7133 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7137 po_misc_or_fail_no_backtrack (
7138 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7142 po_misc_or_fail_no_backtrack (
7143 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7147 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7151 po_misc_or_fail_no_backtrack (
7152 parse_shifter_operand_group_reloc (&str
, i
));
7156 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7160 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7164 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7168 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7171 /* Various value-based sanity checks and shared operations. We
7172 do not signal immediate failures for the register constraints;
7173 this allows a syntax error to take precedence. */
7174 switch (op_parse_code
)
7182 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7183 inst
.error
= BAD_PC
;
7188 if (inst
.operands
[i
].isreg
)
7190 if (inst
.operands
[i
].reg
== REG_PC
)
7191 inst
.error
= BAD_PC
;
7192 else if (inst
.operands
[i
].reg
== REG_SP
7193 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7194 relaxed since ARMv8-A. */
7195 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7198 inst
.error
= BAD_SP
;
7204 if (inst
.operands
[i
].isreg
7205 && inst
.operands
[i
].reg
== REG_PC
7206 && (inst
.operands
[i
].writeback
|| thumb
))
7207 inst
.error
= BAD_PC
;
7216 case OP_oBARRIER_I15
:
7225 inst
.operands
[i
].imm
= val
;
7232 /* If we get here, this operand was successfully parsed. */
7233 inst
.operands
[i
].present
= 1;
7237 inst
.error
= BAD_ARGS
;
7242 /* The parse routine should already have set inst.error, but set a
7243 default here just in case. */
7245 inst
.error
= _("syntax error");
7249 /* Do not backtrack over a trailing optional argument that
7250 absorbed some text. We will only fail again, with the
7251 'garbage following instruction' error message, which is
7252 probably less helpful than the current one. */
7253 if (backtrack_index
== i
&& backtrack_pos
!= str
7254 && upat
[i
+1] == OP_stop
)
7257 inst
.error
= _("syntax error");
7261 /* Try again, skipping the optional argument at backtrack_pos. */
7262 str
= backtrack_pos
;
7263 inst
.error
= backtrack_error
;
7264 inst
.operands
[backtrack_index
].present
= 0;
7265 i
= backtrack_index
;
7269 /* Check that we have parsed all the arguments. */
7270 if (*str
!= '\0' && !inst
.error
)
7271 inst
.error
= _("garbage following instruction");
7273 return inst
.error
? FAIL
: SUCCESS
;
7276 #undef po_char_or_fail
7277 #undef po_reg_or_fail
7278 #undef po_reg_or_goto
7279 #undef po_imm_or_fail
7280 #undef po_scalar_or_fail
7281 #undef po_barrier_or_imm
7283 /* Shorthand macro for instruction encoding functions issuing errors. */
7284 #define constraint(expr, err) \
7295 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7296 instructions are unpredictable if these registers are used. This
7297 is the BadReg predicate in ARM's Thumb-2 documentation.
7299 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7300 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7301 #define reject_bad_reg(reg) \
7303 if (reg == REG_PC) \
7305 inst.error = BAD_PC; \
7308 else if (reg == REG_SP \
7309 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7311 inst.error = BAD_SP; \
7316 /* If REG is R13 (the stack pointer), warn that its use is
7318 #define warn_deprecated_sp(reg) \
7320 if (warn_on_deprecated && reg == REG_SP) \
7321 as_tsktsk (_("use of r13 is deprecated")); \
7324 /* Functions for operand encoding. ARM, then Thumb. */
7326 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7328 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7330 The only binary encoding difference is the Coprocessor number. Coprocessor
7331 9 is used for half-precision calculations or conversions. The format of the
7332 instruction is the same as the equivalent Coprocessor 10 instruction that
7333 exists for Single-Precision operation. */
7336 do_scalar_fp16_v82_encode (void)
7338 if (inst
.cond
!= COND_ALWAYS
)
7339 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7340 " the behaviour is UNPREDICTABLE"));
7341 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7344 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7345 mark_feature_used (&arm_ext_fp16
);
7348 /* If VAL can be encoded in the immediate field of an ARM instruction,
7349 return the encoded form. Otherwise, return FAIL. */
7352 encode_arm_immediate (unsigned int val
)
7359 for (i
= 2; i
< 32; i
+= 2)
7360 if ((a
= rotate_left (val
, i
)) <= 0xff)
7361 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7366 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7367 return the encoded form. Otherwise, return FAIL. */
7369 encode_thumb32_immediate (unsigned int val
)
7376 for (i
= 1; i
<= 24; i
++)
7379 if ((val
& ~(0xff << i
)) == 0)
7380 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7384 if (val
== ((a
<< 16) | a
))
7386 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7390 if (val
== ((a
<< 16) | a
))
7391 return 0x200 | (a
>> 8);
7395 /* Encode a VFP SP or DP register number into inst.instruction. */
7398 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7400 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7403 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7406 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7409 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7414 first_error (_("D register out of range for selected VFP version"));
7422 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7426 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7430 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7434 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7438 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7442 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7450 /* Encode a <shift> in an ARM-format instruction. The immediate,
7451 if any, is handled by md_apply_fix. */
7453 encode_arm_shift (int i
)
7455 /* register-shifted register. */
7456 if (inst
.operands
[i
].immisreg
)
7459 for (op_index
= 0; op_index
<= i
; ++op_index
)
7461 /* Check the operand only when it's presented. In pre-UAL syntax,
7462 if the destination register is the same as the first operand, two
7463 register form of the instruction can be used. */
7464 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7465 && inst
.operands
[op_index
].reg
== REG_PC
)
7466 as_warn (UNPRED_REG ("r15"));
7469 if (inst
.operands
[i
].imm
== REG_PC
)
7470 as_warn (UNPRED_REG ("r15"));
7473 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7474 inst
.instruction
|= SHIFT_ROR
<< 5;
7477 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7478 if (inst
.operands
[i
].immisreg
)
7480 inst
.instruction
|= SHIFT_BY_REG
;
7481 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7484 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7489 encode_arm_shifter_operand (int i
)
7491 if (inst
.operands
[i
].isreg
)
7493 inst
.instruction
|= inst
.operands
[i
].reg
;
7494 encode_arm_shift (i
);
7498 inst
.instruction
|= INST_IMMEDIATE
;
7499 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7500 inst
.instruction
|= inst
.operands
[i
].imm
;
7504 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7506 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7509 Generate an error if the operand is not a register. */
7510 constraint (!inst
.operands
[i
].isreg
,
7511 _("Instruction does not support =N addresses"));
7513 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7515 if (inst
.operands
[i
].preind
)
7519 inst
.error
= _("instruction does not accept preindexed addressing");
7522 inst
.instruction
|= PRE_INDEX
;
7523 if (inst
.operands
[i
].writeback
)
7524 inst
.instruction
|= WRITE_BACK
;
7527 else if (inst
.operands
[i
].postind
)
7529 gas_assert (inst
.operands
[i
].writeback
);
7531 inst
.instruction
|= WRITE_BACK
;
7533 else /* unindexed - only for coprocessor */
7535 inst
.error
= _("instruction does not accept unindexed addressing");
7539 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7540 && (((inst
.instruction
& 0x000f0000) >> 16)
7541 == ((inst
.instruction
& 0x0000f000) >> 12)))
7542 as_warn ((inst
.instruction
& LOAD_BIT
)
7543 ? _("destination register same as write-back base")
7544 : _("source register same as write-back base"));
7547 /* inst.operands[i] was set up by parse_address. Encode it into an
7548 ARM-format mode 2 load or store instruction. If is_t is true,
7549 reject forms that cannot be used with a T instruction (i.e. not
7552 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7554 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7556 encode_arm_addr_mode_common (i
, is_t
);
7558 if (inst
.operands
[i
].immisreg
)
7560 constraint ((inst
.operands
[i
].imm
== REG_PC
7561 || (is_pc
&& inst
.operands
[i
].writeback
)),
7563 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7564 inst
.instruction
|= inst
.operands
[i
].imm
;
7565 if (!inst
.operands
[i
].negative
)
7566 inst
.instruction
|= INDEX_UP
;
7567 if (inst
.operands
[i
].shifted
)
7569 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7570 inst
.instruction
|= SHIFT_ROR
<< 5;
7573 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7574 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7578 else /* immediate offset in inst.reloc */
7580 if (is_pc
&& !inst
.reloc
.pc_rel
)
7582 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7584 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7585 cannot use PC in addressing.
7586 PC cannot be used in writeback addressing, either. */
7587 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7590 /* Use of PC in str is deprecated for ARMv7. */
7591 if (warn_on_deprecated
7593 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7594 as_tsktsk (_("use of PC in this instruction is deprecated"));
7597 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7599 /* Prefer + for zero encoded value. */
7600 if (!inst
.operands
[i
].negative
)
7601 inst
.instruction
|= INDEX_UP
;
7602 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7607 /* inst.operands[i] was set up by parse_address. Encode it into an
7608 ARM-format mode 3 load or store instruction. Reject forms that
7609 cannot be used with such instructions. If is_t is true, reject
7610 forms that cannot be used with a T instruction (i.e. not
7613 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7615 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7617 inst
.error
= _("instruction does not accept scaled register index");
7621 encode_arm_addr_mode_common (i
, is_t
);
7623 if (inst
.operands
[i
].immisreg
)
7625 constraint ((inst
.operands
[i
].imm
== REG_PC
7626 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7628 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7630 inst
.instruction
|= inst
.operands
[i
].imm
;
7631 if (!inst
.operands
[i
].negative
)
7632 inst
.instruction
|= INDEX_UP
;
7634 else /* immediate offset in inst.reloc */
7636 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7637 && inst
.operands
[i
].writeback
),
7639 inst
.instruction
|= HWOFFSET_IMM
;
7640 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7642 /* Prefer + for zero encoded value. */
7643 if (!inst
.operands
[i
].negative
)
7644 inst
.instruction
|= INDEX_UP
;
7646 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7651 /* Write immediate bits [7:0] to the following locations:
7653 |28/24|23 19|18 16|15 4|3 0|
7654 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7656 This function is used by VMOV/VMVN/VORR/VBIC. */
7659 neon_write_immbits (unsigned immbits
)
7661 inst
.instruction
|= immbits
& 0xf;
7662 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7663 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7666 /* Invert low-order SIZE bits of XHI:XLO. */
7669 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7671 unsigned immlo
= xlo
? *xlo
: 0;
7672 unsigned immhi
= xhi
? *xhi
: 0;
7677 immlo
= (~immlo
) & 0xff;
7681 immlo
= (~immlo
) & 0xffff;
7685 immhi
= (~immhi
) & 0xffffffff;
7689 immlo
= (~immlo
) & 0xffffffff;
7703 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7707 neon_bits_same_in_bytes (unsigned imm
)
7709 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7710 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7711 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7712 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7715 /* For immediate of above form, return 0bABCD. */
7718 neon_squash_bits (unsigned imm
)
7720 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7721 | ((imm
& 0x01000000) >> 21);
7724 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7727 neon_qfloat_bits (unsigned imm
)
7729 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7732 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7733 the instruction. *OP is passed as the initial value of the op field, and
7734 may be set to a different value depending on the constant (i.e.
7735 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7736 MVN). If the immediate looks like a repeated pattern then also
7737 try smaller element sizes. */
7740 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7741 unsigned *immbits
, int *op
, int size
,
7742 enum neon_el_type type
)
7744 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7746 if (type
== NT_float
&& !float_p
)
7749 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7751 if (size
!= 32 || *op
== 1)
7753 *immbits
= neon_qfloat_bits (immlo
);
7759 if (neon_bits_same_in_bytes (immhi
)
7760 && neon_bits_same_in_bytes (immlo
))
7764 *immbits
= (neon_squash_bits (immhi
) << 4)
7765 | neon_squash_bits (immlo
);
7776 if (immlo
== (immlo
& 0x000000ff))
7781 else if (immlo
== (immlo
& 0x0000ff00))
7783 *immbits
= immlo
>> 8;
7786 else if (immlo
== (immlo
& 0x00ff0000))
7788 *immbits
= immlo
>> 16;
7791 else if (immlo
== (immlo
& 0xff000000))
7793 *immbits
= immlo
>> 24;
7796 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7798 *immbits
= (immlo
>> 8) & 0xff;
7801 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7803 *immbits
= (immlo
>> 16) & 0xff;
7807 if ((immlo
& 0xffff) != (immlo
>> 16))
7814 if (immlo
== (immlo
& 0x000000ff))
7819 else if (immlo
== (immlo
& 0x0000ff00))
7821 *immbits
= immlo
>> 8;
7825 if ((immlo
& 0xff) != (immlo
>> 8))
7830 if (immlo
== (immlo
& 0x000000ff))
7832 /* Don't allow MVN with 8-bit immediate. */
7842 #if defined BFD_HOST_64_BIT
7843 /* Returns TRUE if double precision value V may be cast
7844 to single precision without loss of accuracy. */
7847 is_double_a_single (bfd_int64_t v
)
7849 int exp
= (int)((v
>> 52) & 0x7FF);
7850 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7852 return (exp
== 0 || exp
== 0x7FF
7853 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7854 && (mantissa
& 0x1FFFFFFFl
) == 0;
7857 /* Returns a double precision value casted to single precision
7858 (ignoring the least significant bits in exponent and mantissa). */
7861 double_to_single (bfd_int64_t v
)
7863 int sign
= (int) ((v
>> 63) & 1l);
7864 int exp
= (int) ((v
>> 52) & 0x7FF);
7865 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7871 exp
= exp
- 1023 + 127;
7880 /* No denormalized numbers. */
7886 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7888 #endif /* BFD_HOST_64_BIT */
7897 static void do_vfp_nsyn_opcode (const char *);
7899 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7900 Determine whether it can be performed with a move instruction; if
7901 it can, convert inst.instruction to that move instruction and
7902 return TRUE; if it can't, convert inst.instruction to a literal-pool
7903 load and return FALSE. If this is not a valid thing to do in the
7904 current context, set inst.error and return TRUE.
7906 inst.operands[i] describes the destination register. */
7909 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7912 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7913 bfd_boolean arm_p
= (t
== CONST_ARM
);
7916 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7920 if ((inst
.instruction
& tbit
) == 0)
7922 inst
.error
= _("invalid pseudo operation");
7926 if (inst
.reloc
.exp
.X_op
!= O_constant
7927 && inst
.reloc
.exp
.X_op
!= O_symbol
7928 && inst
.reloc
.exp
.X_op
!= O_big
)
7930 inst
.error
= _("constant expression expected");
7934 if (inst
.reloc
.exp
.X_op
== O_constant
7935 || inst
.reloc
.exp
.X_op
== O_big
)
7937 #if defined BFD_HOST_64_BIT
7942 if (inst
.reloc
.exp
.X_op
== O_big
)
7944 LITTLENUM_TYPE w
[X_PRECISION
];
7947 if (inst
.reloc
.exp
.X_add_number
== -1)
7949 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7951 /* FIXME: Should we check words w[2..5] ? */
7956 #if defined BFD_HOST_64_BIT
7958 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7959 << LITTLENUM_NUMBER_OF_BITS
)
7960 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7961 << LITTLENUM_NUMBER_OF_BITS
)
7962 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7963 << LITTLENUM_NUMBER_OF_BITS
)
7964 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7966 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7967 | (l
[0] & LITTLENUM_MASK
);
7971 v
= inst
.reloc
.exp
.X_add_number
;
7973 if (!inst
.operands
[i
].issingle
)
7977 /* LDR should not use lead in a flag-setting instruction being
7978 chosen so we do not check whether movs can be used. */
7980 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7981 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7982 && inst
.operands
[i
].reg
!= 13
7983 && inst
.operands
[i
].reg
!= 15)
7985 /* Check if on thumb2 it can be done with a mov.w, mvn or
7986 movw instruction. */
7987 unsigned int newimm
;
7988 bfd_boolean isNegated
;
7990 newimm
= encode_thumb32_immediate (v
);
7991 if (newimm
!= (unsigned int) FAIL
)
7995 newimm
= encode_thumb32_immediate (~v
);
7996 if (newimm
!= (unsigned int) FAIL
)
8000 /* The number can be loaded with a mov.w or mvn
8002 if (newimm
!= (unsigned int) FAIL
8003 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8005 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8006 | (inst
.operands
[i
].reg
<< 8));
8007 /* Change to MOVN. */
8008 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8009 inst
.instruction
|= (newimm
& 0x800) << 15;
8010 inst
.instruction
|= (newimm
& 0x700) << 4;
8011 inst
.instruction
|= (newimm
& 0x0ff);
8014 /* The number can be loaded with a movw instruction. */
8015 else if ((v
& ~0xFFFF) == 0
8016 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8018 int imm
= v
& 0xFFFF;
8020 inst
.instruction
= 0xf2400000; /* MOVW. */
8021 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8022 inst
.instruction
|= (imm
& 0xf000) << 4;
8023 inst
.instruction
|= (imm
& 0x0800) << 15;
8024 inst
.instruction
|= (imm
& 0x0700) << 4;
8025 inst
.instruction
|= (imm
& 0x00ff);
8032 int value
= encode_arm_immediate (v
);
8036 /* This can be done with a mov instruction. */
8037 inst
.instruction
&= LITERAL_MASK
;
8038 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8039 inst
.instruction
|= value
& 0xfff;
8043 value
= encode_arm_immediate (~ v
);
8046 /* This can be done with a mvn instruction. */
8047 inst
.instruction
&= LITERAL_MASK
;
8048 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8049 inst
.instruction
|= value
& 0xfff;
8053 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8056 unsigned immbits
= 0;
8057 unsigned immlo
= inst
.operands
[1].imm
;
8058 unsigned immhi
= inst
.operands
[1].regisimm
8059 ? inst
.operands
[1].reg
8060 : inst
.reloc
.exp
.X_unsigned
8062 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8063 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8064 &op
, 64, NT_invtype
);
8068 neon_invert_size (&immlo
, &immhi
, 64);
8070 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8071 &op
, 64, NT_invtype
);
8076 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8082 /* Fill other bits in vmov encoding for both thumb and arm. */
8084 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8086 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8087 neon_write_immbits (immbits
);
8095 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8096 if (inst
.operands
[i
].issingle
8097 && is_quarter_float (inst
.operands
[1].imm
)
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8100 inst
.operands
[1].imm
=
8101 neon_qfloat_bits (v
);
8102 do_vfp_nsyn_opcode ("fconsts");
8106 /* If our host does not support a 64-bit type then we cannot perform
8107 the following optimization. This mean that there will be a
8108 discrepancy between the output produced by an assembler built for
8109 a 32-bit-only host and the output produced from a 64-bit host, but
8110 this cannot be helped. */
8111 #if defined BFD_HOST_64_BIT
8112 else if (!inst
.operands
[1].issingle
8113 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8115 if (is_double_a_single (v
)
8116 && is_quarter_float (double_to_single (v
)))
8118 inst
.operands
[1].imm
=
8119 neon_qfloat_bits (double_to_single (v
));
8120 do_vfp_nsyn_opcode ("fconstd");
8128 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8129 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8132 inst
.operands
[1].reg
= REG_PC
;
8133 inst
.operands
[1].isreg
= 1;
8134 inst
.operands
[1].preind
= 1;
8135 inst
.reloc
.pc_rel
= 1;
8136 inst
.reloc
.type
= (thumb_p
8137 ? BFD_RELOC_ARM_THUMB_OFFSET
8139 ? BFD_RELOC_ARM_HWLITERAL
8140 : BFD_RELOC_ARM_LITERAL
));
8144 /* inst.operands[i] was set up by parse_address. Encode it into an
8145 ARM-format instruction. Reject all forms which cannot be encoded
8146 into a coprocessor load/store instruction. If wb_ok is false,
8147 reject use of writeback; if unind_ok is false, reject use of
8148 unindexed addressing. If reloc_override is not 0, use it instead
8149 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8150 (in which case it is preserved). */
8153 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8155 if (!inst
.operands
[i
].isreg
)
8158 if (! inst
.operands
[0].isvec
)
8160 inst
.error
= _("invalid co-processor operand");
8163 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8167 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8169 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8171 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8173 gas_assert (!inst
.operands
[i
].writeback
);
8176 inst
.error
= _("instruction does not support unindexed addressing");
8179 inst
.instruction
|= inst
.operands
[i
].imm
;
8180 inst
.instruction
|= INDEX_UP
;
8184 if (inst
.operands
[i
].preind
)
8185 inst
.instruction
|= PRE_INDEX
;
8187 if (inst
.operands
[i
].writeback
)
8189 if (inst
.operands
[i
].reg
== REG_PC
)
8191 inst
.error
= _("pc may not be used with write-back");
8196 inst
.error
= _("instruction does not support writeback");
8199 inst
.instruction
|= WRITE_BACK
;
8203 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8204 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8205 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8206 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8209 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8211 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8214 /* Prefer + for zero encoded value. */
8215 if (!inst
.operands
[i
].negative
)
8216 inst
.instruction
|= INDEX_UP
;
8221 /* Functions for instruction encoding, sorted by sub-architecture.
8222 First some generics; their names are taken from the conventional
8223 bit positions for register arguments in ARM format instructions. */
8233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8239 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8246 inst
.instruction
|= inst
.operands
[1].reg
;
8252 inst
.instruction
|= inst
.operands
[0].reg
;
8253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8266 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8267 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8273 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8274 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8278 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8280 if (ARM_CPU_IS_ANY (cpu_variant
))
8282 as_tsktsk ("%s", msg
);
8285 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8297 unsigned Rn
= inst
.operands
[2].reg
;
8298 /* Enforce restrictions on SWP instruction. */
8299 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8301 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8302 _("Rn must not overlap other operands"));
8304 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8306 if (!check_obsolete (&arm_ext_v8
,
8307 _("swp{b} use is obsoleted for ARMv8 and later"))
8308 && warn_on_deprecated
8309 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8310 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8314 inst
.instruction
|= inst
.operands
[1].reg
;
8315 inst
.instruction
|= Rn
<< 16;
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8322 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8323 inst
.instruction
|= inst
.operands
[2].reg
;
8329 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8330 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8331 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8332 || inst
.reloc
.exp
.X_add_number
!= 0),
8334 inst
.instruction
|= inst
.operands
[0].reg
;
8335 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8336 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8342 inst
.instruction
|= inst
.operands
[0].imm
;
8348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8349 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8352 /* ARM instructions, in alphabetical order by function name (except
8353 that wrapper functions appear immediately after the function they
8356 /* This is a pseudo-op of the form "adr rd, label" to be converted
8357 into a relative address of the form "add rd, pc, #label-.-8". */
8362 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8364 /* Frag hacking will turn this into a sub instruction if the offset turns
8365 out to be negative. */
8366 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8367 inst
.reloc
.pc_rel
= 1;
8368 inst
.reloc
.exp
.X_add_number
-= 8;
8370 if (inst
.reloc
.exp
.X_op
== O_symbol
8371 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8372 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8373 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8374 inst
.reloc
.exp
.X_add_number
+= 1;
8377 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8378 into a relative address of the form:
8379 add rd, pc, #low(label-.-8)"
8380 add rd, rd, #high(label-.-8)" */
8385 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8387 /* Frag hacking will turn this into a sub instruction if the offset turns
8388 out to be negative. */
8389 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8390 inst
.reloc
.pc_rel
= 1;
8391 inst
.size
= INSN_SIZE
* 2;
8392 inst
.reloc
.exp
.X_add_number
-= 8;
8394 if (inst
.reloc
.exp
.X_op
== O_symbol
8395 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8396 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8397 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8398 inst
.reloc
.exp
.X_add_number
+= 1;
8404 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8405 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8407 if (!inst
.operands
[1].present
)
8408 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8409 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8410 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8411 encode_arm_shifter_operand (2);
8417 if (inst
.operands
[0].present
)
8418 inst
.instruction
|= inst
.operands
[0].imm
;
8420 inst
.instruction
|= 0xf;
8426 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8427 constraint (msb
> 32, _("bit-field extends past end of register"));
8428 /* The instruction encoding stores the LSB and MSB,
8429 not the LSB and width. */
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8432 inst
.instruction
|= (msb
- 1) << 16;
8440 /* #0 in second position is alternative syntax for bfc, which is
8441 the same instruction but with REG_PC in the Rm field. */
8442 if (!inst
.operands
[1].isreg
)
8443 inst
.operands
[1].reg
= REG_PC
;
8445 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8446 constraint (msb
> 32, _("bit-field extends past end of register"));
8447 /* The instruction encoding stores the LSB and MSB,
8448 not the LSB and width. */
8449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8450 inst
.instruction
|= inst
.operands
[1].reg
;
8451 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8452 inst
.instruction
|= (msb
- 1) << 16;
8458 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8459 _("bit-field extends past end of register"));
8460 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8461 inst
.instruction
|= inst
.operands
[1].reg
;
8462 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8463 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8466 /* ARM V5 breakpoint instruction (argument parse)
8467 BKPT <16 bit unsigned immediate>
8468 Instruction is not conditional.
8469 The bit pattern given in insns[] has the COND_ALWAYS condition,
8470 and it is an error if the caller tried to override that. */
8475 /* Top 12 of 16 bits to bits 19:8. */
8476 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8478 /* Bottom 4 of 16 bits to bits 3:0. */
8479 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8483 encode_branch (int default_reloc
)
8485 if (inst
.operands
[0].hasreloc
)
8487 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8488 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8489 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8490 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8491 ? BFD_RELOC_ARM_PLT32
8492 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8495 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8496 inst
.reloc
.pc_rel
= 1;
8503 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8504 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8507 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8514 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8516 if (inst
.cond
== COND_ALWAYS
)
8517 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8519 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8523 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8526 /* ARM V5 branch-link-exchange instruction (argument parse)
8527 BLX <target_addr> ie BLX(1)
8528 BLX{<condition>} <Rm> ie BLX(2)
8529 Unfortunately, there are two different opcodes for this mnemonic.
8530 So, the insns[].value is not used, and the code here zaps values
8531 into inst.instruction.
8532 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8537 if (inst
.operands
[0].isreg
)
8539 /* Arg is a register; the opcode provided by insns[] is correct.
8540 It is not illegal to do "blx pc", just useless. */
8541 if (inst
.operands
[0].reg
== REG_PC
)
8542 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8544 inst
.instruction
|= inst
.operands
[0].reg
;
8548 /* Arg is an address; this instruction cannot be executed
8549 conditionally, and the opcode must be adjusted.
8550 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8551 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8552 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8553 inst
.instruction
= 0xfa000000;
8554 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8561 bfd_boolean want_reloc
;
8563 if (inst
.operands
[0].reg
== REG_PC
)
8564 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8566 inst
.instruction
|= inst
.operands
[0].reg
;
8567 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8568 it is for ARMv4t or earlier. */
8569 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8570 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8574 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8579 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8583 /* ARM v5TEJ. Jump to Jazelle code. */
8588 if (inst
.operands
[0].reg
== REG_PC
)
8589 as_tsktsk (_("use of r15 in bxj is not really useful"));
8591 inst
.instruction
|= inst
.operands
[0].reg
;
8594 /* Co-processor data operation:
8595 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8596 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8600 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8601 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8602 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8603 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8604 inst
.instruction
|= inst
.operands
[4].reg
;
8605 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8611 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8612 encode_arm_shifter_operand (1);
8615 /* Transfer between coprocessor and ARM registers.
8616 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8621 No special properties. */
8623 struct deprecated_coproc_regs_s
8630 arm_feature_set deprecated
;
8631 arm_feature_set obsoleted
;
8632 const char *dep_msg
;
8633 const char *obs_msg
;
8636 #define DEPR_ACCESS_V8 \
8637 N_("This coprocessor register access is deprecated in ARMv8")
8639 /* Table of all deprecated coprocessor registers. */
8640 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8642 {15, 0, 7, 10, 5, /* CP15DMB. */
8643 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8644 DEPR_ACCESS_V8
, NULL
},
8645 {15, 0, 7, 10, 4, /* CP15DSB. */
8646 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8647 DEPR_ACCESS_V8
, NULL
},
8648 {15, 0, 7, 5, 4, /* CP15ISB. */
8649 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8650 DEPR_ACCESS_V8
, NULL
},
8651 {14, 6, 1, 0, 0, /* TEEHBR. */
8652 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8653 DEPR_ACCESS_V8
, NULL
},
8654 {14, 6, 0, 0, 0, /* TEECR. */
8655 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8656 DEPR_ACCESS_V8
, NULL
},
8659 #undef DEPR_ACCESS_V8
8661 static const size_t deprecated_coproc_reg_count
=
8662 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8670 Rd
= inst
.operands
[2].reg
;
8673 if (inst
.instruction
== 0xee000010
8674 || inst
.instruction
== 0xfe000010)
8676 reject_bad_reg (Rd
);
8677 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8679 constraint (Rd
== REG_SP
, BAD_SP
);
8684 if (inst
.instruction
== 0xe000010)
8685 constraint (Rd
== REG_PC
, BAD_PC
);
8688 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8690 const struct deprecated_coproc_regs_s
*r
=
8691 deprecated_coproc_regs
+ i
;
8693 if (inst
.operands
[0].reg
== r
->cp
8694 && inst
.operands
[1].imm
== r
->opc1
8695 && inst
.operands
[3].reg
== r
->crn
8696 && inst
.operands
[4].reg
== r
->crm
8697 && inst
.operands
[5].imm
== r
->opc2
)
8699 if (! ARM_CPU_IS_ANY (cpu_variant
)
8700 && warn_on_deprecated
8701 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8702 as_tsktsk ("%s", r
->dep_msg
);
8706 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8707 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8708 inst
.instruction
|= Rd
<< 12;
8709 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8710 inst
.instruction
|= inst
.operands
[4].reg
;
8711 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8714 /* Transfer between coprocessor register and pair of ARM registers.
8715 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8720 Two XScale instructions are special cases of these:
8722 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8723 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8725 Result unpredictable if Rd or Rn is R15. */
8732 Rd
= inst
.operands
[2].reg
;
8733 Rn
= inst
.operands
[3].reg
;
8737 reject_bad_reg (Rd
);
8738 reject_bad_reg (Rn
);
8742 constraint (Rd
== REG_PC
, BAD_PC
);
8743 constraint (Rn
== REG_PC
, BAD_PC
);
8746 /* Only check the MRRC{2} variants. */
8747 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8749 /* If Rd == Rn, error that the operation is
8750 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8751 constraint (Rd
== Rn
, BAD_OVERLAP
);
8754 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8755 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8756 inst
.instruction
|= Rd
<< 12;
8757 inst
.instruction
|= Rn
<< 16;
8758 inst
.instruction
|= inst
.operands
[4].reg
;
8764 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8765 if (inst
.operands
[1].present
)
8767 inst
.instruction
|= CPSI_MMOD
;
8768 inst
.instruction
|= inst
.operands
[1].imm
;
8775 inst
.instruction
|= inst
.operands
[0].imm
;
8781 unsigned Rd
, Rn
, Rm
;
8783 Rd
= inst
.operands
[0].reg
;
8784 Rn
= (inst
.operands
[1].present
8785 ? inst
.operands
[1].reg
: Rd
);
8786 Rm
= inst
.operands
[2].reg
;
8788 constraint ((Rd
== REG_PC
), BAD_PC
);
8789 constraint ((Rn
== REG_PC
), BAD_PC
);
8790 constraint ((Rm
== REG_PC
), BAD_PC
);
8792 inst
.instruction
|= Rd
<< 16;
8793 inst
.instruction
|= Rn
<< 0;
8794 inst
.instruction
|= Rm
<< 8;
8800 /* There is no IT instruction in ARM mode. We
8801 process it to do the validation as if in
8802 thumb mode, just in case the code gets
8803 assembled for thumb using the unified syntax. */
8808 set_it_insn_type (IT_INSN
);
8809 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8810 now_it
.cc
= inst
.operands
[0].imm
;
8814 /* If there is only one register in the register list,
8815 then return its register number. Otherwise return -1. */
8817 only_one_reg_in_list (int range
)
8819 int i
= ffs (range
) - 1;
8820 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8824 encode_ldmstm(int from_push_pop_mnem
)
8826 int base_reg
= inst
.operands
[0].reg
;
8827 int range
= inst
.operands
[1].imm
;
8830 inst
.instruction
|= base_reg
<< 16;
8831 inst
.instruction
|= range
;
8833 if (inst
.operands
[1].writeback
)
8834 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8836 if (inst
.operands
[0].writeback
)
8838 inst
.instruction
|= WRITE_BACK
;
8839 /* Check for unpredictable uses of writeback. */
8840 if (inst
.instruction
& LOAD_BIT
)
8842 /* Not allowed in LDM type 2. */
8843 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8844 && ((range
& (1 << REG_PC
)) == 0))
8845 as_warn (_("writeback of base register is UNPREDICTABLE"));
8846 /* Only allowed if base reg not in list for other types. */
8847 else if (range
& (1 << base_reg
))
8848 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8852 /* Not allowed for type 2. */
8853 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8854 as_warn (_("writeback of base register is UNPREDICTABLE"));
8855 /* Only allowed if base reg not in list, or first in list. */
8856 else if ((range
& (1 << base_reg
))
8857 && (range
& ((1 << base_reg
) - 1)))
8858 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8862 /* If PUSH/POP has only one register, then use the A2 encoding. */
8863 one_reg
= only_one_reg_in_list (range
);
8864 if (from_push_pop_mnem
&& one_reg
>= 0)
8866 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8868 inst
.instruction
&= A_COND_MASK
;
8869 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8870 inst
.instruction
|= one_reg
<< 12;
8877 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8880 /* ARMv5TE load-consecutive (argument parse)
8889 constraint (inst
.operands
[0].reg
% 2 != 0,
8890 _("first transfer register must be even"));
8891 constraint (inst
.operands
[1].present
8892 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8893 _("can only transfer two consecutive registers"));
8894 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8895 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8897 if (!inst
.operands
[1].present
)
8898 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8900 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8901 register and the first register written; we have to diagnose
8902 overlap between the base and the second register written here. */
8904 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8905 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8906 as_warn (_("base register written back, and overlaps "
8907 "second transfer register"));
8909 if (!(inst
.instruction
& V4_STR_BIT
))
8911 /* For an index-register load, the index register must not overlap the
8912 destination (even if not write-back). */
8913 if (inst
.operands
[2].immisreg
8914 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8915 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8916 as_warn (_("index register overlaps transfer register"));
8918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8919 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8925 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8926 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8927 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8928 || inst
.operands
[1].negative
8929 /* This can arise if the programmer has written
8931 or if they have mistakenly used a register name as the last
8934 It is very difficult to distinguish between these two cases
8935 because "rX" might actually be a label. ie the register
8936 name has been occluded by a symbol of the same name. So we
8937 just generate a general 'bad addressing mode' type error
8938 message and leave it up to the programmer to discover the
8939 true cause and fix their mistake. */
8940 || (inst
.operands
[1].reg
== REG_PC
),
8943 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8944 || inst
.reloc
.exp
.X_add_number
!= 0,
8945 _("offset must be zero in ARM encoding"));
8947 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8951 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8957 constraint (inst
.operands
[0].reg
% 2 != 0,
8958 _("even register required"));
8959 constraint (inst
.operands
[1].present
8960 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8961 _("can only load two consecutive registers"));
8962 /* If op 1 were present and equal to PC, this function wouldn't
8963 have been called in the first place. */
8964 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8967 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8970 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8971 which is not a multiple of four is UNPREDICTABLE. */
8973 check_ldr_r15_aligned (void)
8975 constraint (!(inst
.operands
[1].immisreg
)
8976 && (inst
.operands
[0].reg
== REG_PC
8977 && inst
.operands
[1].reg
== REG_PC
8978 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8979 _("ldr to register 15 must be 4-byte alligned"));
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8986 if (!inst
.operands
[1].isreg
)
8987 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8989 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8990 check_ldr_r15_aligned ();
8996 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8998 if (inst
.operands
[1].preind
)
9000 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9001 || inst
.reloc
.exp
.X_add_number
!= 0,
9002 _("this instruction requires a post-indexed address"));
9004 inst
.operands
[1].preind
= 0;
9005 inst
.operands
[1].postind
= 1;
9006 inst
.operands
[1].writeback
= 1;
9008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9009 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9012 /* Halfword and signed-byte load/store operations. */
9017 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9019 if (!inst
.operands
[1].isreg
)
9020 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9022 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9028 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9030 if (inst
.operands
[1].preind
)
9032 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9033 || inst
.reloc
.exp
.X_add_number
!= 0,
9034 _("this instruction requires a post-indexed address"));
9036 inst
.operands
[1].preind
= 0;
9037 inst
.operands
[1].postind
= 1;
9038 inst
.operands
[1].writeback
= 1;
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9041 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9044 /* Co-processor register load/store.
9045 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9050 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9051 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9057 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9058 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9059 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9060 && !(inst
.instruction
& 0x00400000))
9061 as_tsktsk (_("Rd and Rm should be different in mla"));
9063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9064 inst
.instruction
|= inst
.operands
[1].reg
;
9065 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9066 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9072 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9073 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 encode_arm_shifter_operand (1);
9079 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9086 top
= (inst
.instruction
& 0x00400000) != 0;
9087 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9088 _(":lower16: not allowed in this instruction"));
9089 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9090 _(":upper16: not allowed in this instruction"));
9091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9092 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9094 imm
= inst
.reloc
.exp
.X_add_number
;
9095 /* The value is in two pieces: 0:11, 16:19. */
9096 inst
.instruction
|= (imm
& 0x00000fff);
9097 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9102 do_vfp_nsyn_mrs (void)
9104 if (inst
.operands
[0].isvec
)
9106 if (inst
.operands
[1].reg
!= 1)
9107 first_error (_("operand 1 must be FPSCR"));
9108 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9109 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9110 do_vfp_nsyn_opcode ("fmstat");
9112 else if (inst
.operands
[1].isvec
)
9113 do_vfp_nsyn_opcode ("fmrx");
9121 do_vfp_nsyn_msr (void)
9123 if (inst
.operands
[0].isvec
)
9124 do_vfp_nsyn_opcode ("fmxr");
9134 unsigned Rt
= inst
.operands
[0].reg
;
9136 if (thumb_mode
&& Rt
== REG_SP
)
9138 inst
.error
= BAD_SP
;
9142 /* APSR_ sets isvec. All other refs to PC are illegal. */
9143 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9145 inst
.error
= BAD_PC
;
9149 /* If we get through parsing the register name, we just insert the number
9150 generated into the instruction without further validation. */
9151 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9152 inst
.instruction
|= (Rt
<< 12);
9158 unsigned Rt
= inst
.operands
[1].reg
;
9161 reject_bad_reg (Rt
);
9162 else if (Rt
== REG_PC
)
9164 inst
.error
= BAD_PC
;
9168 /* If we get through parsing the register name, we just insert the number
9169 generated into the instruction without further validation. */
9170 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9171 inst
.instruction
|= (Rt
<< 12);
9179 if (do_vfp_nsyn_mrs () == SUCCESS
)
9182 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9185 if (inst
.operands
[1].isreg
)
9187 br
= inst
.operands
[1].reg
;
9188 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9189 as_bad (_("bad register for mrs"));
9193 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9194 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9196 _("'APSR', 'CPSR' or 'SPSR' expected"));
9197 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9200 inst
.instruction
|= br
;
9203 /* Two possible forms:
9204 "{C|S}PSR_<field>, Rm",
9205 "{C|S}PSR_f, #expression". */
9210 if (do_vfp_nsyn_msr () == SUCCESS
)
9213 inst
.instruction
|= inst
.operands
[0].imm
;
9214 if (inst
.operands
[1].isreg
)
9215 inst
.instruction
|= inst
.operands
[1].reg
;
9218 inst
.instruction
|= INST_IMMEDIATE
;
9219 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9220 inst
.reloc
.pc_rel
= 0;
9227 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9229 if (!inst
.operands
[2].present
)
9230 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9232 inst
.instruction
|= inst
.operands
[1].reg
;
9233 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9235 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9236 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9237 as_tsktsk (_("Rd and Rm should be different in mul"));
9240 /* Long Multiply Parser
9241 UMULL RdLo, RdHi, Rm, Rs
9242 SMULL RdLo, RdHi, Rm, Rs
9243 UMLAL RdLo, RdHi, Rm, Rs
9244 SMLAL RdLo, RdHi, Rm, Rs. */
9249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9250 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9251 inst
.instruction
|= inst
.operands
[2].reg
;
9252 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9254 /* rdhi and rdlo must be different. */
9255 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9256 as_tsktsk (_("rdhi and rdlo must be different"));
9258 /* rdhi, rdlo and rm must all be different before armv6. */
9259 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9260 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9261 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9262 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9268 if (inst
.operands
[0].present
9269 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9271 /* Architectural NOP hints are CPSR sets with no bits selected. */
9272 inst
.instruction
&= 0xf0000000;
9273 inst
.instruction
|= 0x0320f000;
9274 if (inst
.operands
[0].present
)
9275 inst
.instruction
|= inst
.operands
[0].imm
;
9279 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9280 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9281 Condition defaults to COND_ALWAYS.
9282 Error if Rd, Rn or Rm are R15. */
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9289 inst
.instruction
|= inst
.operands
[2].reg
;
9290 if (inst
.operands
[3].present
)
9291 encode_arm_shift (3);
9294 /* ARM V6 PKHTB (Argument Parse). */
9299 if (!inst
.operands
[3].present
)
9301 /* If the shift specifier is omitted, turn the instruction
9302 into pkhbt rd, rm, rn. */
9303 inst
.instruction
&= 0xfff00010;
9304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9305 inst
.instruction
|= inst
.operands
[1].reg
;
9306 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9311 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9312 inst
.instruction
|= inst
.operands
[2].reg
;
9313 encode_arm_shift (3);
9317 /* ARMv5TE: Preload-Cache
9318 MP Extensions: Preload for write
9322 Syntactically, like LDR with B=1, W=0, L=1. */
9327 constraint (!inst
.operands
[0].isreg
,
9328 _("'[' expected after PLD mnemonic"));
9329 constraint (inst
.operands
[0].postind
,
9330 _("post-indexed expression used in preload instruction"));
9331 constraint (inst
.operands
[0].writeback
,
9332 _("writeback used in preload instruction"));
9333 constraint (!inst
.operands
[0].preind
,
9334 _("unindexed addressing used in preload instruction"));
9335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9338 /* ARMv7: PLI <addr_mode> */
9342 constraint (!inst
.operands
[0].isreg
,
9343 _("'[' expected after PLI mnemonic"));
9344 constraint (inst
.operands
[0].postind
,
9345 _("post-indexed expression used in preload instruction"));
9346 constraint (inst
.operands
[0].writeback
,
9347 _("writeback used in preload instruction"));
9348 constraint (!inst
.operands
[0].preind
,
9349 _("unindexed addressing used in preload instruction"));
9350 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9351 inst
.instruction
&= ~PRE_INDEX
;
9357 constraint (inst
.operands
[0].writeback
,
9358 _("push/pop do not support {reglist}^"));
9359 inst
.operands
[1] = inst
.operands
[0];
9360 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9361 inst
.operands
[0].isreg
= 1;
9362 inst
.operands
[0].writeback
= 1;
9363 inst
.operands
[0].reg
= REG_SP
;
9364 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9367 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9368 word at the specified address and the following word
9370 Unconditionally executed.
9371 Error if Rn is R15. */
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9377 if (inst
.operands
[0].writeback
)
9378 inst
.instruction
|= WRITE_BACK
;
9381 /* ARM V6 ssat (argument parse). */
9386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9387 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9388 inst
.instruction
|= inst
.operands
[2].reg
;
9390 if (inst
.operands
[3].present
)
9391 encode_arm_shift (3);
9394 /* ARM V6 usat (argument parse). */
9399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9400 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9401 inst
.instruction
|= inst
.operands
[2].reg
;
9403 if (inst
.operands
[3].present
)
9404 encode_arm_shift (3);
9407 /* ARM V6 ssat16 (argument parse). */
9412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9413 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9414 inst
.instruction
|= inst
.operands
[2].reg
;
9420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9421 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9422 inst
.instruction
|= inst
.operands
[2].reg
;
9425 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9426 preserving the other bits.
9428 setend <endian_specifier>, where <endian_specifier> is either
9434 if (warn_on_deprecated
9435 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9436 as_tsktsk (_("setend use is deprecated for ARMv8"));
9438 if (inst
.operands
[0].imm
)
9439 inst
.instruction
|= 0x200;
9445 unsigned int Rm
= (inst
.operands
[1].present
9446 ? inst
.operands
[1].reg
9447 : inst
.operands
[0].reg
);
9449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9450 inst
.instruction
|= Rm
;
9451 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9453 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9454 inst
.instruction
|= SHIFT_BY_REG
;
9455 /* PR 12854: Error on extraneous shifts. */
9456 constraint (inst
.operands
[2].shifted
,
9457 _("extraneous shift as part of operand to shift insn"));
9460 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9466 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9467 inst
.reloc
.pc_rel
= 0;
9473 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9474 inst
.reloc
.pc_rel
= 0;
9480 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9481 inst
.reloc
.pc_rel
= 0;
9487 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9488 _("selected processor does not support SETPAN instruction"));
9490 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9497 _("selected processor does not support SETPAN instruction"));
9499 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9502 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9503 SMLAxy{cond} Rd,Rm,Rs,Rn
9504 SMLAWy{cond} Rd,Rm,Rs,Rn
9505 Error if any register is R15. */
9510 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9511 inst
.instruction
|= inst
.operands
[1].reg
;
9512 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9513 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9516 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9517 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9518 Error if any register is R15.
9519 Warning if Rdlo == Rdhi. */
9524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9525 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9526 inst
.instruction
|= inst
.operands
[2].reg
;
9527 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9529 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9530 as_tsktsk (_("rdhi and rdlo must be different"));
9533 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9534 SMULxy{cond} Rd,Rm,Rs
9535 Error if any register is R15. */
9540 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9541 inst
.instruction
|= inst
.operands
[1].reg
;
9542 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9545 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9546 the same for both ARM and Thumb-2. */
9553 if (inst
.operands
[0].present
)
9555 reg
= inst
.operands
[0].reg
;
9556 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9561 inst
.instruction
|= reg
<< 16;
9562 inst
.instruction
|= inst
.operands
[1].imm
;
9563 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9564 inst
.instruction
|= WRITE_BACK
;
9567 /* ARM V6 strex (argument parse). */
9572 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9573 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9574 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9575 || inst
.operands
[2].negative
9576 /* See comment in do_ldrex(). */
9577 || (inst
.operands
[2].reg
== REG_PC
),
9580 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9581 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9583 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9584 || inst
.reloc
.exp
.X_add_number
!= 0,
9585 _("offset must be zero in ARM encoding"));
9587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9588 inst
.instruction
|= inst
.operands
[1].reg
;
9589 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9590 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9596 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9597 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9598 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9599 || inst
.operands
[2].negative
,
9602 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9603 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9611 constraint (inst
.operands
[1].reg
% 2 != 0,
9612 _("even register required"));
9613 constraint (inst
.operands
[2].present
9614 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9615 _("can only store two consecutive registers"));
9616 /* If op 2 were present and equal to PC, this function wouldn't
9617 have been called in the first place. */
9618 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9620 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9621 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9622 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9626 inst
.instruction
|= inst
.operands
[1].reg
;
9627 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9634 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9635 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9643 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9644 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9649 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9650 extends it to 32-bits, and adds the result to a value in another
9651 register. You can specify a rotation by 0, 8, 16, or 24 bits
9652 before extracting the 16-bit value.
9653 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9654 Condition defaults to COND_ALWAYS.
9655 Error if any register uses R15. */
9660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9661 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9662 inst
.instruction
|= inst
.operands
[2].reg
;
9663 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9668 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9669 Condition defaults to COND_ALWAYS.
9670 Error if any register uses R15. */
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 inst
.instruction
|= inst
.operands
[1].reg
;
9677 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9680 /* VFP instructions. In a logical order: SP variant first, monad
9681 before dyad, arithmetic then move then load/store. */
9684 do_vfp_sp_monadic (void)
9686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9691 do_vfp_sp_dyadic (void)
9693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9695 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9699 do_vfp_sp_compare_z (void)
9701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9705 do_vfp_dp_sp_cvt (void)
9707 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9708 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9712 do_vfp_sp_dp_cvt (void)
9714 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9715 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9719 do_vfp_reg_from_sp (void)
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9722 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9726 do_vfp_reg2_from_sp2 (void)
9728 constraint (inst
.operands
[2].imm
!= 2,
9729 _("only two consecutive VFP SP registers allowed here"));
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9732 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9736 do_vfp_sp_from_reg (void)
9738 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9739 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9743 do_vfp_sp2_from_reg2 (void)
9745 constraint (inst
.operands
[0].imm
!= 2,
9746 _("only two consecutive VFP SP registers allowed here"));
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9748 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9749 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9753 do_vfp_sp_ldst (void)
9755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9756 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9760 do_vfp_dp_ldst (void)
9762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9763 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9768 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9770 if (inst
.operands
[0].writeback
)
9771 inst
.instruction
|= WRITE_BACK
;
9773 constraint (ldstm_type
!= VFP_LDSTMIA
,
9774 _("this addressing mode requires base-register writeback"));
9775 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9777 inst
.instruction
|= inst
.operands
[1].imm
;
9781 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9785 if (inst
.operands
[0].writeback
)
9786 inst
.instruction
|= WRITE_BACK
;
9788 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9789 _("this addressing mode requires base-register writeback"));
9791 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9792 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9794 count
= inst
.operands
[1].imm
<< 1;
9795 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9798 inst
.instruction
|= count
;
9802 do_vfp_sp_ldstmia (void)
9804 vfp_sp_ldstm (VFP_LDSTMIA
);
9808 do_vfp_sp_ldstmdb (void)
9810 vfp_sp_ldstm (VFP_LDSTMDB
);
9814 do_vfp_dp_ldstmia (void)
9816 vfp_dp_ldstm (VFP_LDSTMIA
);
9820 do_vfp_dp_ldstmdb (void)
9822 vfp_dp_ldstm (VFP_LDSTMDB
);
9826 do_vfp_xp_ldstmia (void)
9828 vfp_dp_ldstm (VFP_LDSTMIAX
);
9832 do_vfp_xp_ldstmdb (void)
9834 vfp_dp_ldstm (VFP_LDSTMDBX
);
9838 do_vfp_dp_rd_rm (void)
9840 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9841 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9845 do_vfp_dp_rn_rd (void)
9847 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9848 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9852 do_vfp_dp_rd_rn (void)
9854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9855 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9859 do_vfp_dp_rd_rn_rm (void)
9861 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9862 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9863 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9869 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9873 do_vfp_dp_rm_rd_rn (void)
9875 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9876 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9877 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9880 /* VFPv3 instructions. */
9882 do_vfp_sp_const (void)
9884 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9885 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9886 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9890 do_vfp_dp_const (void)
9892 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9893 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9894 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9898 vfp_conv (int srcsize
)
9900 int immbits
= srcsize
- inst
.operands
[1].imm
;
9902 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9904 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9905 i.e. immbits must be in range 0 - 16. */
9906 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9909 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9911 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9912 i.e. immbits must be in range 0 - 31. */
9913 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9917 inst
.instruction
|= (immbits
& 1) << 5;
9918 inst
.instruction
|= (immbits
>> 1);
9922 do_vfp_sp_conv_16 (void)
9924 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9929 do_vfp_dp_conv_16 (void)
9931 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9936 do_vfp_sp_conv_32 (void)
9938 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9943 do_vfp_dp_conv_32 (void)
9945 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9949 /* FPA instructions. Also in a logical order. */
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9955 inst
.instruction
|= inst
.operands
[1].reg
;
9959 do_fpa_ldmstm (void)
9961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9962 switch (inst
.operands
[1].imm
)
9964 case 1: inst
.instruction
|= CP_T_X
; break;
9965 case 2: inst
.instruction
|= CP_T_Y
; break;
9966 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9971 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9973 /* The instruction specified "ea" or "fd", so we can only accept
9974 [Rn]{!}. The instruction does not really support stacking or
9975 unstacking, so we have to emulate these by setting appropriate
9976 bits and offsets. */
9977 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9978 || inst
.reloc
.exp
.X_add_number
!= 0,
9979 _("this instruction does not support indexing"));
9981 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9982 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9984 if (!(inst
.instruction
& INDEX_UP
))
9985 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9987 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9989 inst
.operands
[2].preind
= 0;
9990 inst
.operands
[2].postind
= 1;
9994 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9997 /* iWMMXt instructions: strictly in alphabetical order. */
10000 do_iwmmxt_tandorc (void)
10002 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10006 do_iwmmxt_textrc (void)
10008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10009 inst
.instruction
|= inst
.operands
[1].imm
;
10013 do_iwmmxt_textrm (void)
10015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10016 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10017 inst
.instruction
|= inst
.operands
[2].imm
;
10021 do_iwmmxt_tinsr (void)
10023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10024 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10025 inst
.instruction
|= inst
.operands
[2].imm
;
10029 do_iwmmxt_tmia (void)
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10032 inst
.instruction
|= inst
.operands
[1].reg
;
10033 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10037 do_iwmmxt_waligni (void)
10039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10041 inst
.instruction
|= inst
.operands
[2].reg
;
10042 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10046 do_iwmmxt_wmerge (void)
10048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10049 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10050 inst
.instruction
|= inst
.operands
[2].reg
;
10051 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10055 do_iwmmxt_wmov (void)
10057 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10058 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10059 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10060 inst
.instruction
|= inst
.operands
[1].reg
;
10064 do_iwmmxt_wldstbh (void)
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10069 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10071 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10072 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10076 do_iwmmxt_wldstw (void)
10078 /* RIWR_RIWC clears .isreg for a control register. */
10079 if (!inst
.operands
[0].isreg
)
10081 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10082 inst
.instruction
|= 0xf0000000;
10085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10086 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10090 do_iwmmxt_wldstd (void)
10092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10093 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10094 && inst
.operands
[1].immisreg
)
10096 inst
.instruction
&= ~0x1a000ff;
10097 inst
.instruction
|= (0xfU
<< 28);
10098 if (inst
.operands
[1].preind
)
10099 inst
.instruction
|= PRE_INDEX
;
10100 if (!inst
.operands
[1].negative
)
10101 inst
.instruction
|= INDEX_UP
;
10102 if (inst
.operands
[1].writeback
)
10103 inst
.instruction
|= WRITE_BACK
;
10104 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10105 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10106 inst
.instruction
|= inst
.operands
[1].imm
;
10109 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10113 do_iwmmxt_wshufh (void)
10115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10117 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10118 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10122 do_iwmmxt_wzero (void)
10124 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10125 inst
.instruction
|= inst
.operands
[0].reg
;
10126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10127 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10131 do_iwmmxt_wrwrwr_or_imm5 (void)
10133 if (inst
.operands
[2].isreg
)
10136 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10137 _("immediate operand requires iWMMXt2"));
10139 if (inst
.operands
[2].imm
== 0)
10141 switch ((inst
.instruction
>> 20) & 0xf)
10147 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10148 inst
.operands
[2].imm
= 16;
10149 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10155 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10156 inst
.operands
[2].imm
= 32;
10157 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10164 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10166 wrn
= (inst
.instruction
>> 16) & 0xf;
10167 inst
.instruction
&= 0xff0fff0f;
10168 inst
.instruction
|= wrn
;
10169 /* Bail out here; the instruction is now assembled. */
10174 /* Map 32 -> 0, etc. */
10175 inst
.operands
[2].imm
&= 0x1f;
10176 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10180 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10181 operations first, then control, shift, and load/store. */
10183 /* Insns like "foo X,Y,Z". */
10186 do_mav_triple (void)
10188 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10189 inst
.instruction
|= inst
.operands
[1].reg
;
10190 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10193 /* Insns like "foo W,X,Y,Z".
10194 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10199 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10200 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10201 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10202 inst
.instruction
|= inst
.operands
[3].reg
;
10205 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10207 do_mav_dspsc (void)
10209 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10212 /* Maverick shift immediate instructions.
10213 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10214 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10217 do_mav_shift (void)
10219 int imm
= inst
.operands
[2].imm
;
10221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10222 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10224 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10225 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10226 Bit 4 should be 0. */
10227 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10229 inst
.instruction
|= imm
;
10232 /* XScale instructions. Also sorted arithmetic before move. */
10234 /* Xscale multiply-accumulate (argument parse)
10237 MIAxycc acc0,Rm,Rs. */
10242 inst
.instruction
|= inst
.operands
[1].reg
;
10243 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10246 /* Xscale move-accumulator-register (argument parse)
10248 MARcc acc0,RdLo,RdHi. */
10253 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10257 /* Xscale move-register-accumulator (argument parse)
10259 MRAcc RdLo,RdHi,acc0. */
10264 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10266 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10269 /* Encoding functions relevant only to Thumb. */
10271 /* inst.operands[i] is a shifted-register operand; encode
10272 it into inst.instruction in the format used by Thumb32. */
10275 encode_thumb32_shifted_operand (int i
)
10277 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10278 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10280 constraint (inst
.operands
[i
].immisreg
,
10281 _("shift by register not allowed in thumb mode"));
10282 inst
.instruction
|= inst
.operands
[i
].reg
;
10283 if (shift
== SHIFT_RRX
)
10284 inst
.instruction
|= SHIFT_ROR
<< 4;
10287 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10288 _("expression too complex"));
10290 constraint (value
> 32
10291 || (value
== 32 && (shift
== SHIFT_LSL
10292 || shift
== SHIFT_ROR
)),
10293 _("shift expression is too large"));
10297 else if (value
== 32)
10300 inst
.instruction
|= shift
<< 4;
10301 inst
.instruction
|= (value
& 0x1c) << 10;
10302 inst
.instruction
|= (value
& 0x03) << 6;
10307 /* inst.operands[i] was set up by parse_address. Encode it into a
10308 Thumb32 format load or store instruction. Reject forms that cannot
10309 be used with such instructions. If is_t is true, reject forms that
10310 cannot be used with a T instruction; if is_d is true, reject forms
10311 that cannot be used with a D instruction. If it is a store insn,
10312 reject PC in Rn. */
10315 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10317 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10319 constraint (!inst
.operands
[i
].isreg
,
10320 _("Instruction does not support =N addresses"));
10322 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10323 if (inst
.operands
[i
].immisreg
)
10325 constraint (is_pc
, BAD_PC_ADDRESSING
);
10326 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10327 constraint (inst
.operands
[i
].negative
,
10328 _("Thumb does not support negative register indexing"));
10329 constraint (inst
.operands
[i
].postind
,
10330 _("Thumb does not support register post-indexing"));
10331 constraint (inst
.operands
[i
].writeback
,
10332 _("Thumb does not support register indexing with writeback"));
10333 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10334 _("Thumb supports only LSL in shifted register indexing"));
10336 inst
.instruction
|= inst
.operands
[i
].imm
;
10337 if (inst
.operands
[i
].shifted
)
10339 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10340 _("expression too complex"));
10341 constraint (inst
.reloc
.exp
.X_add_number
< 0
10342 || inst
.reloc
.exp
.X_add_number
> 3,
10343 _("shift out of range"));
10344 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10346 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10348 else if (inst
.operands
[i
].preind
)
10350 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10351 constraint (is_t
&& inst
.operands
[i
].writeback
,
10352 _("cannot use writeback with this instruction"));
10353 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10354 BAD_PC_ADDRESSING
);
10358 inst
.instruction
|= 0x01000000;
10359 if (inst
.operands
[i
].writeback
)
10360 inst
.instruction
|= 0x00200000;
10364 inst
.instruction
|= 0x00000c00;
10365 if (inst
.operands
[i
].writeback
)
10366 inst
.instruction
|= 0x00000100;
10368 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10370 else if (inst
.operands
[i
].postind
)
10372 gas_assert (inst
.operands
[i
].writeback
);
10373 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10374 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10377 inst
.instruction
|= 0x00200000;
10379 inst
.instruction
|= 0x00000900;
10380 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10382 else /* unindexed - only for coprocessor */
10383 inst
.error
= _("instruction does not accept unindexed addressing");
10386 /* Table of Thumb instructions which exist in both 16- and 32-bit
10387 encodings (the latter only in post-V6T2 cores). The index is the
10388 value used in the insns table below. When there is more than one
10389 possible 16-bit encoding for the instruction, this table always
10391 Also contains several pseudo-instructions used during relaxation. */
10392 #define T16_32_TAB \
10393 X(_adc, 4140, eb400000), \
10394 X(_adcs, 4140, eb500000), \
10395 X(_add, 1c00, eb000000), \
10396 X(_adds, 1c00, eb100000), \
10397 X(_addi, 0000, f1000000), \
10398 X(_addis, 0000, f1100000), \
10399 X(_add_pc,000f, f20f0000), \
10400 X(_add_sp,000d, f10d0000), \
10401 X(_adr, 000f, f20f0000), \
10402 X(_and, 4000, ea000000), \
10403 X(_ands, 4000, ea100000), \
10404 X(_asr, 1000, fa40f000), \
10405 X(_asrs, 1000, fa50f000), \
10406 X(_b, e000, f000b000), \
10407 X(_bcond, d000, f0008000), \
10408 X(_bic, 4380, ea200000), \
10409 X(_bics, 4380, ea300000), \
10410 X(_cmn, 42c0, eb100f00), \
10411 X(_cmp, 2800, ebb00f00), \
10412 X(_cpsie, b660, f3af8400), \
10413 X(_cpsid, b670, f3af8600), \
10414 X(_cpy, 4600, ea4f0000), \
10415 X(_dec_sp,80dd, f1ad0d00), \
10416 X(_eor, 4040, ea800000), \
10417 X(_eors, 4040, ea900000), \
10418 X(_inc_sp,00dd, f10d0d00), \
10419 X(_ldmia, c800, e8900000), \
10420 X(_ldr, 6800, f8500000), \
10421 X(_ldrb, 7800, f8100000), \
10422 X(_ldrh, 8800, f8300000), \
10423 X(_ldrsb, 5600, f9100000), \
10424 X(_ldrsh, 5e00, f9300000), \
10425 X(_ldr_pc,4800, f85f0000), \
10426 X(_ldr_pc2,4800, f85f0000), \
10427 X(_ldr_sp,9800, f85d0000), \
10428 X(_lsl, 0000, fa00f000), \
10429 X(_lsls, 0000, fa10f000), \
10430 X(_lsr, 0800, fa20f000), \
10431 X(_lsrs, 0800, fa30f000), \
10432 X(_mov, 2000, ea4f0000), \
10433 X(_movs, 2000, ea5f0000), \
10434 X(_mul, 4340, fb00f000), \
10435 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10436 X(_mvn, 43c0, ea6f0000), \
10437 X(_mvns, 43c0, ea7f0000), \
10438 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10439 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10440 X(_orr, 4300, ea400000), \
10441 X(_orrs, 4300, ea500000), \
10442 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10443 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10444 X(_rev, ba00, fa90f080), \
10445 X(_rev16, ba40, fa90f090), \
10446 X(_revsh, bac0, fa90f0b0), \
10447 X(_ror, 41c0, fa60f000), \
10448 X(_rors, 41c0, fa70f000), \
10449 X(_sbc, 4180, eb600000), \
10450 X(_sbcs, 4180, eb700000), \
10451 X(_stmia, c000, e8800000), \
10452 X(_str, 6000, f8400000), \
10453 X(_strb, 7000, f8000000), \
10454 X(_strh, 8000, f8200000), \
10455 X(_str_sp,9000, f84d0000), \
10456 X(_sub, 1e00, eba00000), \
10457 X(_subs, 1e00, ebb00000), \
10458 X(_subi, 8000, f1a00000), \
10459 X(_subis, 8000, f1b00000), \
10460 X(_sxtb, b240, fa4ff080), \
10461 X(_sxth, b200, fa0ff080), \
10462 X(_tst, 4200, ea100f00), \
10463 X(_uxtb, b2c0, fa5ff080), \
10464 X(_uxth, b280, fa1ff080), \
10465 X(_nop, bf00, f3af8000), \
10466 X(_yield, bf10, f3af8001), \
10467 X(_wfe, bf20, f3af8002), \
10468 X(_wfi, bf30, f3af8003), \
10469 X(_sev, bf40, f3af8004), \
10470 X(_sevl, bf50, f3af8005), \
10471 X(_udf, de00, f7f0a000)
10473 /* To catch errors in encoding functions, the codes are all offset by
10474 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10475 as 16-bit instructions. */
10476 #define X(a,b,c) T_MNEM##a
10477 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10480 #define X(a,b,c) 0x##b
10481 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10482 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10485 #define X(a,b,c) 0x##c
10486 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10487 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10488 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10492 /* Thumb instruction encoders, in alphabetical order. */
10494 /* ADDW or SUBW. */
10497 do_t_add_sub_w (void)
10501 Rd
= inst
.operands
[0].reg
;
10502 Rn
= inst
.operands
[1].reg
;
10504 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10505 is the SP-{plus,minus}-immediate form of the instruction. */
10507 constraint (Rd
== REG_PC
, BAD_PC
);
10509 reject_bad_reg (Rd
);
10511 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10512 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10515 /* Parse an add or subtract instruction. We get here with inst.instruction
10516 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10519 do_t_add_sub (void)
10523 Rd
= inst
.operands
[0].reg
;
10524 Rs
= (inst
.operands
[1].present
10525 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10526 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10529 set_it_insn_type_last ();
10531 if (unified_syntax
)
10534 bfd_boolean narrow
;
10537 flags
= (inst
.instruction
== T_MNEM_adds
10538 || inst
.instruction
== T_MNEM_subs
);
10540 narrow
= !in_it_block ();
10542 narrow
= in_it_block ();
10543 if (!inst
.operands
[2].isreg
)
10547 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10548 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10550 add
= (inst
.instruction
== T_MNEM_add
10551 || inst
.instruction
== T_MNEM_adds
);
10553 if (inst
.size_req
!= 4)
10555 /* Attempt to use a narrow opcode, with relaxation if
10557 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10558 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10559 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10560 opcode
= T_MNEM_add_sp
;
10561 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10562 opcode
= T_MNEM_add_pc
;
10563 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10566 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10568 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10572 inst
.instruction
= THUMB_OP16(opcode
);
10573 inst
.instruction
|= (Rd
<< 4) | Rs
;
10574 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10575 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10577 if (inst
.size_req
== 2)
10578 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10580 inst
.relax
= opcode
;
10584 constraint (inst
.size_req
== 2, BAD_HIREG
);
10586 if (inst
.size_req
== 4
10587 || (inst
.size_req
!= 2 && !opcode
))
10589 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10590 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10591 THUMB1_RELOC_ONLY
);
10594 constraint (add
, BAD_PC
);
10595 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10596 _("only SUBS PC, LR, #const allowed"));
10597 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10598 _("expression too complex"));
10599 constraint (inst
.reloc
.exp
.X_add_number
< 0
10600 || inst
.reloc
.exp
.X_add_number
> 0xff,
10601 _("immediate value out of range"));
10602 inst
.instruction
= T2_SUBS_PC_LR
10603 | inst
.reloc
.exp
.X_add_number
;
10604 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10607 else if (Rs
== REG_PC
)
10609 /* Always use addw/subw. */
10610 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10611 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10615 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10616 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10619 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10621 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10623 inst
.instruction
|= Rd
<< 8;
10624 inst
.instruction
|= Rs
<< 16;
10629 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10630 unsigned int shift
= inst
.operands
[2].shift_kind
;
10632 Rn
= inst
.operands
[2].reg
;
10633 /* See if we can do this with a 16-bit instruction. */
10634 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10636 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10641 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10642 || inst
.instruction
== T_MNEM_add
)
10644 : T_OPCODE_SUB_R3
);
10645 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10649 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10651 /* Thumb-1 cores (except v6-M) require at least one high
10652 register in a narrow non flag setting add. */
10653 if (Rd
> 7 || Rn
> 7
10654 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10655 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10662 inst
.instruction
= T_OPCODE_ADD_HI
;
10663 inst
.instruction
|= (Rd
& 8) << 4;
10664 inst
.instruction
|= (Rd
& 7);
10665 inst
.instruction
|= Rn
<< 3;
10671 constraint (Rd
== REG_PC
, BAD_PC
);
10672 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10673 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10674 constraint (Rs
== REG_PC
, BAD_PC
);
10675 reject_bad_reg (Rn
);
10677 /* If we get here, it can't be done in 16 bits. */
10678 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10679 _("shift must be constant"));
10680 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10681 inst
.instruction
|= Rd
<< 8;
10682 inst
.instruction
|= Rs
<< 16;
10683 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10684 _("shift value over 3 not allowed in thumb mode"));
10685 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10686 _("only LSL shift allowed in thumb mode"));
10687 encode_thumb32_shifted_operand (2);
10692 constraint (inst
.instruction
== T_MNEM_adds
10693 || inst
.instruction
== T_MNEM_subs
,
10696 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10698 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10699 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10702 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10703 ? 0x0000 : 0x8000);
10704 inst
.instruction
|= (Rd
<< 4) | Rs
;
10705 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10709 Rn
= inst
.operands
[2].reg
;
10710 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10712 /* We now have Rd, Rs, and Rn set to registers. */
10713 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10715 /* Can't do this for SUB. */
10716 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10717 inst
.instruction
= T_OPCODE_ADD_HI
;
10718 inst
.instruction
|= (Rd
& 8) << 4;
10719 inst
.instruction
|= (Rd
& 7);
10721 inst
.instruction
|= Rn
<< 3;
10723 inst
.instruction
|= Rs
<< 3;
10725 constraint (1, _("dest must overlap one source register"));
10729 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10730 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10731 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10741 Rd
= inst
.operands
[0].reg
;
10742 reject_bad_reg (Rd
);
10744 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10746 /* Defer to section relaxation. */
10747 inst
.relax
= inst
.instruction
;
10748 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10749 inst
.instruction
|= Rd
<< 4;
10751 else if (unified_syntax
&& inst
.size_req
!= 2)
10753 /* Generate a 32-bit opcode. */
10754 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10755 inst
.instruction
|= Rd
<< 8;
10756 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10757 inst
.reloc
.pc_rel
= 1;
10761 /* Generate a 16-bit opcode. */
10762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10763 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10764 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10765 inst
.reloc
.pc_rel
= 1;
10766 inst
.instruction
|= Rd
<< 4;
10769 if (inst
.reloc
.exp
.X_op
== O_symbol
10770 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10771 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10772 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10773 inst
.reloc
.exp
.X_add_number
+= 1;
10776 /* Arithmetic instructions for which there is just one 16-bit
10777 instruction encoding, and it allows only two low registers.
10778 For maximal compatibility with ARM syntax, we allow three register
10779 operands even when Thumb-32 instructions are not available, as long
10780 as the first two are identical. For instance, both "sbc r0,r1" and
10781 "sbc r0,r0,r1" are allowed. */
10787 Rd
= inst
.operands
[0].reg
;
10788 Rs
= (inst
.operands
[1].present
10789 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10790 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10791 Rn
= inst
.operands
[2].reg
;
10793 reject_bad_reg (Rd
);
10794 reject_bad_reg (Rs
);
10795 if (inst
.operands
[2].isreg
)
10796 reject_bad_reg (Rn
);
10798 if (unified_syntax
)
10800 if (!inst
.operands
[2].isreg
)
10802 /* For an immediate, we always generate a 32-bit opcode;
10803 section relaxation will shrink it later if possible. */
10804 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10805 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10806 inst
.instruction
|= Rd
<< 8;
10807 inst
.instruction
|= Rs
<< 16;
10808 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10812 bfd_boolean narrow
;
10814 /* See if we can do this with a 16-bit instruction. */
10815 if (THUMB_SETS_FLAGS (inst
.instruction
))
10816 narrow
= !in_it_block ();
10818 narrow
= in_it_block ();
10820 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10822 if (inst
.operands
[2].shifted
)
10824 if (inst
.size_req
== 4)
10830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10831 inst
.instruction
|= Rd
;
10832 inst
.instruction
|= Rn
<< 3;
10836 /* If we get here, it can't be done in 16 bits. */
10837 constraint (inst
.operands
[2].shifted
10838 && inst
.operands
[2].immisreg
,
10839 _("shift must be constant"));
10840 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10841 inst
.instruction
|= Rd
<< 8;
10842 inst
.instruction
|= Rs
<< 16;
10843 encode_thumb32_shifted_operand (2);
10848 /* On its face this is a lie - the instruction does set the
10849 flags. However, the only supported mnemonic in this mode
10850 says it doesn't. */
10851 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10853 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10854 _("unshifted register required"));
10855 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10856 constraint (Rd
!= Rs
,
10857 _("dest and source1 must be the same register"));
10859 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10860 inst
.instruction
|= Rd
;
10861 inst
.instruction
|= Rn
<< 3;
10865 /* Similarly, but for instructions where the arithmetic operation is
10866 commutative, so we can allow either of them to be different from
10867 the destination operand in a 16-bit instruction. For instance, all
10868 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10875 Rd
= inst
.operands
[0].reg
;
10876 Rs
= (inst
.operands
[1].present
10877 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10878 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10879 Rn
= inst
.operands
[2].reg
;
10881 reject_bad_reg (Rd
);
10882 reject_bad_reg (Rs
);
10883 if (inst
.operands
[2].isreg
)
10884 reject_bad_reg (Rn
);
10886 if (unified_syntax
)
10888 if (!inst
.operands
[2].isreg
)
10890 /* For an immediate, we always generate a 32-bit opcode;
10891 section relaxation will shrink it later if possible. */
10892 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10893 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10894 inst
.instruction
|= Rd
<< 8;
10895 inst
.instruction
|= Rs
<< 16;
10896 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10900 bfd_boolean narrow
;
10902 /* See if we can do this with a 16-bit instruction. */
10903 if (THUMB_SETS_FLAGS (inst
.instruction
))
10904 narrow
= !in_it_block ();
10906 narrow
= in_it_block ();
10908 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10910 if (inst
.operands
[2].shifted
)
10912 if (inst
.size_req
== 4)
10919 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10920 inst
.instruction
|= Rd
;
10921 inst
.instruction
|= Rn
<< 3;
10926 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10927 inst
.instruction
|= Rd
;
10928 inst
.instruction
|= Rs
<< 3;
10933 /* If we get here, it can't be done in 16 bits. */
10934 constraint (inst
.operands
[2].shifted
10935 && inst
.operands
[2].immisreg
,
10936 _("shift must be constant"));
10937 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10938 inst
.instruction
|= Rd
<< 8;
10939 inst
.instruction
|= Rs
<< 16;
10940 encode_thumb32_shifted_operand (2);
10945 /* On its face this is a lie - the instruction does set the
10946 flags. However, the only supported mnemonic in this mode
10947 says it doesn't. */
10948 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10950 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10951 _("unshifted register required"));
10952 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10954 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10955 inst
.instruction
|= Rd
;
10958 inst
.instruction
|= Rn
<< 3;
10960 inst
.instruction
|= Rs
<< 3;
10962 constraint (1, _("dest must overlap one source register"));
10970 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10971 constraint (msb
> 32, _("bit-field extends past end of register"));
10972 /* The instruction encoding stores the LSB and MSB,
10973 not the LSB and width. */
10974 Rd
= inst
.operands
[0].reg
;
10975 reject_bad_reg (Rd
);
10976 inst
.instruction
|= Rd
<< 8;
10977 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10978 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10979 inst
.instruction
|= msb
- 1;
10988 Rd
= inst
.operands
[0].reg
;
10989 reject_bad_reg (Rd
);
10991 /* #0 in second position is alternative syntax for bfc, which is
10992 the same instruction but with REG_PC in the Rm field. */
10993 if (!inst
.operands
[1].isreg
)
10997 Rn
= inst
.operands
[1].reg
;
10998 reject_bad_reg (Rn
);
11001 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11002 constraint (msb
> 32, _("bit-field extends past end of register"));
11003 /* The instruction encoding stores the LSB and MSB,
11004 not the LSB and width. */
11005 inst
.instruction
|= Rd
<< 8;
11006 inst
.instruction
|= Rn
<< 16;
11007 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11008 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11009 inst
.instruction
|= msb
- 1;
11017 Rd
= inst
.operands
[0].reg
;
11018 Rn
= inst
.operands
[1].reg
;
11020 reject_bad_reg (Rd
);
11021 reject_bad_reg (Rn
);
11023 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11024 _("bit-field extends past end of register"));
11025 inst
.instruction
|= Rd
<< 8;
11026 inst
.instruction
|= Rn
<< 16;
11027 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11028 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11029 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11032 /* ARM V5 Thumb BLX (argument parse)
11033 BLX <target_addr> which is BLX(1)
11034 BLX <Rm> which is BLX(2)
11035 Unfortunately, there are two different opcodes for this mnemonic.
11036 So, the insns[].value is not used, and the code here zaps values
11037 into inst.instruction.
11039 ??? How to take advantage of the additional two bits of displacement
11040 available in Thumb32 mode? Need new relocation? */
11045 set_it_insn_type_last ();
11047 if (inst
.operands
[0].isreg
)
11049 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11050 /* We have a register, so this is BLX(2). */
11051 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11055 /* No register. This must be BLX(1). */
11056 inst
.instruction
= 0xf000e800;
11057 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11066 bfd_reloc_code_real_type reloc
;
11069 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11071 if (in_it_block ())
11073 /* Conditional branches inside IT blocks are encoded as unconditional
11075 cond
= COND_ALWAYS
;
11080 if (cond
!= COND_ALWAYS
)
11081 opcode
= T_MNEM_bcond
;
11083 opcode
= inst
.instruction
;
11086 && (inst
.size_req
== 4
11087 || (inst
.size_req
!= 2
11088 && (inst
.operands
[0].hasreloc
11089 || inst
.reloc
.exp
.X_op
== O_constant
))))
11091 inst
.instruction
= THUMB_OP32(opcode
);
11092 if (cond
== COND_ALWAYS
)
11093 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11096 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11097 _("selected architecture does not support "
11098 "wide conditional branch instruction"));
11100 gas_assert (cond
!= 0xF);
11101 inst
.instruction
|= cond
<< 22;
11102 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11107 inst
.instruction
= THUMB_OP16(opcode
);
11108 if (cond
== COND_ALWAYS
)
11109 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11112 inst
.instruction
|= cond
<< 8;
11113 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11115 /* Allow section relaxation. */
11116 if (unified_syntax
&& inst
.size_req
!= 2)
11117 inst
.relax
= opcode
;
11119 inst
.reloc
.type
= reloc
;
11120 inst
.reloc
.pc_rel
= 1;
11123 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11124 between the two is the maximum immediate allowed - which is passed in
11127 do_t_bkpt_hlt1 (int range
)
11129 constraint (inst
.cond
!= COND_ALWAYS
,
11130 _("instruction is always unconditional"));
11131 if (inst
.operands
[0].present
)
11133 constraint (inst
.operands
[0].imm
> range
,
11134 _("immediate value out of range"));
11135 inst
.instruction
|= inst
.operands
[0].imm
;
11138 set_it_insn_type (NEUTRAL_IT_INSN
);
11144 do_t_bkpt_hlt1 (63);
11150 do_t_bkpt_hlt1 (255);
11154 do_t_branch23 (void)
11156 set_it_insn_type_last ();
11157 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11159 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11160 this file. We used to simply ignore the PLT reloc type here --
11161 the branch encoding is now needed to deal with TLSCALL relocs.
11162 So if we see a PLT reloc now, put it back to how it used to be to
11163 keep the preexisting behaviour. */
11164 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11165 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11167 #if defined(OBJ_COFF)
11168 /* If the destination of the branch is a defined symbol which does not have
11169 the THUMB_FUNC attribute, then we must be calling a function which has
11170 the (interfacearm) attribute. We look for the Thumb entry point to that
11171 function and change the branch to refer to that function instead. */
11172 if ( inst
.reloc
.exp
.X_op
== O_symbol
11173 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11174 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11175 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11176 inst
.reloc
.exp
.X_add_symbol
=
11177 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11184 set_it_insn_type_last ();
11185 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11186 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11187 should cause the alignment to be checked once it is known. This is
11188 because BX PC only works if the instruction is word aligned. */
11196 set_it_insn_type_last ();
11197 Rm
= inst
.operands
[0].reg
;
11198 reject_bad_reg (Rm
);
11199 inst
.instruction
|= Rm
<< 16;
11208 Rd
= inst
.operands
[0].reg
;
11209 Rm
= inst
.operands
[1].reg
;
11211 reject_bad_reg (Rd
);
11212 reject_bad_reg (Rm
);
11214 inst
.instruction
|= Rd
<< 8;
11215 inst
.instruction
|= Rm
<< 16;
11216 inst
.instruction
|= Rm
;
11222 set_it_insn_type (OUTSIDE_IT_INSN
);
11223 inst
.instruction
|= inst
.operands
[0].imm
;
11229 set_it_insn_type (OUTSIDE_IT_INSN
);
11231 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11232 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11234 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11235 inst
.instruction
= 0xf3af8000;
11236 inst
.instruction
|= imod
<< 9;
11237 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11238 if (inst
.operands
[1].present
)
11239 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11243 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11244 && (inst
.operands
[0].imm
& 4),
11245 _("selected processor does not support 'A' form "
11246 "of this instruction"));
11247 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11248 _("Thumb does not support the 2-argument "
11249 "form of this instruction"));
11250 inst
.instruction
|= inst
.operands
[0].imm
;
11254 /* THUMB CPY instruction (argument parse). */
11259 if (inst
.size_req
== 4)
11261 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11262 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11263 inst
.instruction
|= inst
.operands
[1].reg
;
11267 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11268 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11269 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11276 set_it_insn_type (OUTSIDE_IT_INSN
);
11277 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11278 inst
.instruction
|= inst
.operands
[0].reg
;
11279 inst
.reloc
.pc_rel
= 1;
11280 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11286 inst
.instruction
|= inst
.operands
[0].imm
;
11292 unsigned Rd
, Rn
, Rm
;
11294 Rd
= inst
.operands
[0].reg
;
11295 Rn
= (inst
.operands
[1].present
11296 ? inst
.operands
[1].reg
: Rd
);
11297 Rm
= inst
.operands
[2].reg
;
11299 reject_bad_reg (Rd
);
11300 reject_bad_reg (Rn
);
11301 reject_bad_reg (Rm
);
11303 inst
.instruction
|= Rd
<< 8;
11304 inst
.instruction
|= Rn
<< 16;
11305 inst
.instruction
|= Rm
;
11311 if (unified_syntax
&& inst
.size_req
== 4)
11312 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11320 unsigned int cond
= inst
.operands
[0].imm
;
11322 set_it_insn_type (IT_INSN
);
11323 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11325 now_it
.warn_deprecated
= FALSE
;
11327 /* If the condition is a negative condition, invert the mask. */
11328 if ((cond
& 0x1) == 0x0)
11330 unsigned int mask
= inst
.instruction
& 0x000f;
11332 if ((mask
& 0x7) == 0)
11334 /* No conversion needed. */
11335 now_it
.block_length
= 1;
11337 else if ((mask
& 0x3) == 0)
11340 now_it
.block_length
= 2;
11342 else if ((mask
& 0x1) == 0)
11345 now_it
.block_length
= 3;
11350 now_it
.block_length
= 4;
11353 inst
.instruction
&= 0xfff0;
11354 inst
.instruction
|= mask
;
11357 inst
.instruction
|= cond
<< 4;
11360 /* Helper function used for both push/pop and ldm/stm. */
11362 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11366 load
= (inst
.instruction
& (1 << 20)) != 0;
11368 if (mask
& (1 << 13))
11369 inst
.error
= _("SP not allowed in register list");
11371 if ((mask
& (1 << base
)) != 0
11373 inst
.error
= _("having the base register in the register list when "
11374 "using write back is UNPREDICTABLE");
11378 if (mask
& (1 << 15))
11380 if (mask
& (1 << 14))
11381 inst
.error
= _("LR and PC should not both be in register list");
11383 set_it_insn_type_last ();
11388 if (mask
& (1 << 15))
11389 inst
.error
= _("PC not allowed in register list");
11392 if ((mask
& (mask
- 1)) == 0)
11394 /* Single register transfers implemented as str/ldr. */
11397 if (inst
.instruction
& (1 << 23))
11398 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11400 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11404 if (inst
.instruction
& (1 << 23))
11405 inst
.instruction
= 0x00800000; /* ia -> [base] */
11407 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11410 inst
.instruction
|= 0xf8400000;
11412 inst
.instruction
|= 0x00100000;
11414 mask
= ffs (mask
) - 1;
11417 else if (writeback
)
11418 inst
.instruction
|= WRITE_BACK
;
11420 inst
.instruction
|= mask
;
11421 inst
.instruction
|= base
<< 16;
11427 /* This really doesn't seem worth it. */
11428 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11429 _("expression too complex"));
11430 constraint (inst
.operands
[1].writeback
,
11431 _("Thumb load/store multiple does not support {reglist}^"));
11433 if (unified_syntax
)
11435 bfd_boolean narrow
;
11439 /* See if we can use a 16-bit instruction. */
11440 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11441 && inst
.size_req
!= 4
11442 && !(inst
.operands
[1].imm
& ~0xff))
11444 mask
= 1 << inst
.operands
[0].reg
;
11446 if (inst
.operands
[0].reg
<= 7)
11448 if (inst
.instruction
== T_MNEM_stmia
11449 ? inst
.operands
[0].writeback
11450 : (inst
.operands
[0].writeback
11451 == !(inst
.operands
[1].imm
& mask
)))
11453 if (inst
.instruction
== T_MNEM_stmia
11454 && (inst
.operands
[1].imm
& mask
)
11455 && (inst
.operands
[1].imm
& (mask
- 1)))
11456 as_warn (_("value stored for r%d is UNKNOWN"),
11457 inst
.operands
[0].reg
);
11459 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11460 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11461 inst
.instruction
|= inst
.operands
[1].imm
;
11464 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11466 /* This means 1 register in reg list one of 3 situations:
11467 1. Instruction is stmia, but without writeback.
11468 2. lmdia without writeback, but with Rn not in
11470 3. ldmia with writeback, but with Rn in reglist.
11471 Case 3 is UNPREDICTABLE behaviour, so we handle
11472 case 1 and 2 which can be converted into a 16-bit
11473 str or ldr. The SP cases are handled below. */
11474 unsigned long opcode
;
11475 /* First, record an error for Case 3. */
11476 if (inst
.operands
[1].imm
& mask
11477 && inst
.operands
[0].writeback
)
11479 _("having the base register in the register list when "
11480 "using write back is UNPREDICTABLE");
11482 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11484 inst
.instruction
= THUMB_OP16 (opcode
);
11485 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11486 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11490 else if (inst
.operands
[0] .reg
== REG_SP
)
11492 if (inst
.operands
[0].writeback
)
11495 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11496 ? T_MNEM_push
: T_MNEM_pop
);
11497 inst
.instruction
|= inst
.operands
[1].imm
;
11500 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11503 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11504 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11505 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11513 if (inst
.instruction
< 0xffff)
11514 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11516 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11517 inst
.operands
[0].writeback
);
11522 constraint (inst
.operands
[0].reg
> 7
11523 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11524 constraint (inst
.instruction
!= T_MNEM_ldmia
11525 && inst
.instruction
!= T_MNEM_stmia
,
11526 _("Thumb-2 instruction only valid in unified syntax"));
11527 if (inst
.instruction
== T_MNEM_stmia
)
11529 if (!inst
.operands
[0].writeback
)
11530 as_warn (_("this instruction will write back the base register"));
11531 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11532 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11533 as_warn (_("value stored for r%d is UNKNOWN"),
11534 inst
.operands
[0].reg
);
11538 if (!inst
.operands
[0].writeback
11539 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11540 as_warn (_("this instruction will write back the base register"));
11541 else if (inst
.operands
[0].writeback
11542 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11543 as_warn (_("this instruction will not write back the base register"));
11546 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11547 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11548 inst
.instruction
|= inst
.operands
[1].imm
;
11555 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11556 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11557 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11558 || inst
.operands
[1].negative
,
11561 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11564 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11565 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11571 if (!inst
.operands
[1].present
)
11573 constraint (inst
.operands
[0].reg
== REG_LR
,
11574 _("r14 not allowed as first register "
11575 "when second register is omitted"));
11576 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11578 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11581 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11582 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11583 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11589 unsigned long opcode
;
11592 if (inst
.operands
[0].isreg
11593 && !inst
.operands
[0].preind
11594 && inst
.operands
[0].reg
== REG_PC
)
11595 set_it_insn_type_last ();
11597 opcode
= inst
.instruction
;
11598 if (unified_syntax
)
11600 if (!inst
.operands
[1].isreg
)
11602 if (opcode
<= 0xffff)
11603 inst
.instruction
= THUMB_OP32 (opcode
);
11604 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11607 if (inst
.operands
[1].isreg
11608 && !inst
.operands
[1].writeback
11609 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11610 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11611 && opcode
<= 0xffff
11612 && inst
.size_req
!= 4)
11614 /* Insn may have a 16-bit form. */
11615 Rn
= inst
.operands
[1].reg
;
11616 if (inst
.operands
[1].immisreg
)
11618 inst
.instruction
= THUMB_OP16 (opcode
);
11620 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11622 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11623 reject_bad_reg (inst
.operands
[1].imm
);
11625 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11626 && opcode
!= T_MNEM_ldrsb
)
11627 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11628 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11635 if (inst
.reloc
.pc_rel
)
11636 opcode
= T_MNEM_ldr_pc2
;
11638 opcode
= T_MNEM_ldr_pc
;
11642 if (opcode
== T_MNEM_ldr
)
11643 opcode
= T_MNEM_ldr_sp
;
11645 opcode
= T_MNEM_str_sp
;
11647 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11651 inst
.instruction
= inst
.operands
[0].reg
;
11652 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11654 inst
.instruction
|= THUMB_OP16 (opcode
);
11655 if (inst
.size_req
== 2)
11656 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11658 inst
.relax
= opcode
;
11662 /* Definitely a 32-bit variant. */
11664 /* Warning for Erratum 752419. */
11665 if (opcode
== T_MNEM_ldr
11666 && inst
.operands
[0].reg
== REG_SP
11667 && inst
.operands
[1].writeback
== 1
11668 && !inst
.operands
[1].immisreg
)
11670 if (no_cpu_selected ()
11671 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11672 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11673 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11674 as_warn (_("This instruction may be unpredictable "
11675 "if executed on M-profile cores "
11676 "with interrupts enabled."));
11679 /* Do some validations regarding addressing modes. */
11680 if (inst
.operands
[1].immisreg
)
11681 reject_bad_reg (inst
.operands
[1].imm
);
11683 constraint (inst
.operands
[1].writeback
== 1
11684 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11687 inst
.instruction
= THUMB_OP32 (opcode
);
11688 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11689 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11690 check_ldr_r15_aligned ();
11694 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11696 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11698 /* Only [Rn,Rm] is acceptable. */
11699 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11700 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11701 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11702 || inst
.operands
[1].negative
,
11703 _("Thumb does not support this addressing mode"));
11704 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11708 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11709 if (!inst
.operands
[1].isreg
)
11710 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11713 constraint (!inst
.operands
[1].preind
11714 || inst
.operands
[1].shifted
11715 || inst
.operands
[1].writeback
,
11716 _("Thumb does not support this addressing mode"));
11717 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11719 constraint (inst
.instruction
& 0x0600,
11720 _("byte or halfword not valid for base register"));
11721 constraint (inst
.operands
[1].reg
== REG_PC
11722 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11723 _("r15 based store not allowed"));
11724 constraint (inst
.operands
[1].immisreg
,
11725 _("invalid base register for register offset"));
11727 if (inst
.operands
[1].reg
== REG_PC
)
11728 inst
.instruction
= T_OPCODE_LDR_PC
;
11729 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11730 inst
.instruction
= T_OPCODE_LDR_SP
;
11732 inst
.instruction
= T_OPCODE_STR_SP
;
11734 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11735 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11739 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11740 if (!inst
.operands
[1].immisreg
)
11742 /* Immediate offset. */
11743 inst
.instruction
|= inst
.operands
[0].reg
;
11744 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11745 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11749 /* Register offset. */
11750 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11751 constraint (inst
.operands
[1].negative
,
11752 _("Thumb does not support this addressing mode"));
11755 switch (inst
.instruction
)
11757 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11758 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11759 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11760 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11761 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11762 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11763 case 0x5600 /* ldrsb */:
11764 case 0x5e00 /* ldrsh */: break;
11768 inst
.instruction
|= inst
.operands
[0].reg
;
11769 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11770 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11776 if (!inst
.operands
[1].present
)
11778 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11779 constraint (inst
.operands
[0].reg
== REG_LR
,
11780 _("r14 not allowed here"));
11781 constraint (inst
.operands
[0].reg
== REG_R12
,
11782 _("r12 not allowed here"));
11785 if (inst
.operands
[2].writeback
11786 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11787 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11788 as_warn (_("base register written back, and overlaps "
11789 "one of transfer registers"));
11791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11792 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11793 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11799 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11800 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11806 unsigned Rd
, Rn
, Rm
, Ra
;
11808 Rd
= inst
.operands
[0].reg
;
11809 Rn
= inst
.operands
[1].reg
;
11810 Rm
= inst
.operands
[2].reg
;
11811 Ra
= inst
.operands
[3].reg
;
11813 reject_bad_reg (Rd
);
11814 reject_bad_reg (Rn
);
11815 reject_bad_reg (Rm
);
11816 reject_bad_reg (Ra
);
11818 inst
.instruction
|= Rd
<< 8;
11819 inst
.instruction
|= Rn
<< 16;
11820 inst
.instruction
|= Rm
;
11821 inst
.instruction
|= Ra
<< 12;
11827 unsigned RdLo
, RdHi
, Rn
, Rm
;
11829 RdLo
= inst
.operands
[0].reg
;
11830 RdHi
= inst
.operands
[1].reg
;
11831 Rn
= inst
.operands
[2].reg
;
11832 Rm
= inst
.operands
[3].reg
;
11834 reject_bad_reg (RdLo
);
11835 reject_bad_reg (RdHi
);
11836 reject_bad_reg (Rn
);
11837 reject_bad_reg (Rm
);
11839 inst
.instruction
|= RdLo
<< 12;
11840 inst
.instruction
|= RdHi
<< 8;
11841 inst
.instruction
|= Rn
<< 16;
11842 inst
.instruction
|= Rm
;
11846 do_t_mov_cmp (void)
11850 Rn
= inst
.operands
[0].reg
;
11851 Rm
= inst
.operands
[1].reg
;
11854 set_it_insn_type_last ();
11856 if (unified_syntax
)
11858 int r0off
= (inst
.instruction
== T_MNEM_mov
11859 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11860 unsigned long opcode
;
11861 bfd_boolean narrow
;
11862 bfd_boolean low_regs
;
11864 low_regs
= (Rn
<= 7 && Rm
<= 7);
11865 opcode
= inst
.instruction
;
11866 if (in_it_block ())
11867 narrow
= opcode
!= T_MNEM_movs
;
11869 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11870 if (inst
.size_req
== 4
11871 || inst
.operands
[1].shifted
)
11874 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11875 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11876 && !inst
.operands
[1].shifted
11880 inst
.instruction
= T2_SUBS_PC_LR
;
11884 if (opcode
== T_MNEM_cmp
)
11886 constraint (Rn
== REG_PC
, BAD_PC
);
11889 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11891 warn_deprecated_sp (Rm
);
11892 /* R15 was documented as a valid choice for Rm in ARMv6,
11893 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11894 tools reject R15, so we do too. */
11895 constraint (Rm
== REG_PC
, BAD_PC
);
11898 reject_bad_reg (Rm
);
11900 else if (opcode
== T_MNEM_mov
11901 || opcode
== T_MNEM_movs
)
11903 if (inst
.operands
[1].isreg
)
11905 if (opcode
== T_MNEM_movs
)
11907 reject_bad_reg (Rn
);
11908 reject_bad_reg (Rm
);
11912 /* This is mov.n. */
11913 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11914 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11916 as_tsktsk (_("Use of r%u as a source register is "
11917 "deprecated when r%u is the destination "
11918 "register."), Rm
, Rn
);
11923 /* This is mov.w. */
11924 constraint (Rn
== REG_PC
, BAD_PC
);
11925 constraint (Rm
== REG_PC
, BAD_PC
);
11926 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11927 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11931 reject_bad_reg (Rn
);
11934 if (!inst
.operands
[1].isreg
)
11936 /* Immediate operand. */
11937 if (!in_it_block () && opcode
== T_MNEM_mov
)
11939 if (low_regs
&& narrow
)
11941 inst
.instruction
= THUMB_OP16 (opcode
);
11942 inst
.instruction
|= Rn
<< 8;
11943 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11944 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11946 if (inst
.size_req
== 2)
11947 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11949 inst
.relax
= opcode
;
11954 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11955 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11956 THUMB1_RELOC_ONLY
);
11958 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11959 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11960 inst
.instruction
|= Rn
<< r0off
;
11961 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11964 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11965 && (inst
.instruction
== T_MNEM_mov
11966 || inst
.instruction
== T_MNEM_movs
))
11968 /* Register shifts are encoded as separate shift instructions. */
11969 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11971 if (in_it_block ())
11976 if (inst
.size_req
== 4)
11979 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11985 switch (inst
.operands
[1].shift_kind
)
11988 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11991 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11994 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11997 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12003 inst
.instruction
= opcode
;
12006 inst
.instruction
|= Rn
;
12007 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12012 inst
.instruction
|= CONDS_BIT
;
12014 inst
.instruction
|= Rn
<< 8;
12015 inst
.instruction
|= Rm
<< 16;
12016 inst
.instruction
|= inst
.operands
[1].imm
;
12021 /* Some mov with immediate shift have narrow variants.
12022 Register shifts are handled above. */
12023 if (low_regs
&& inst
.operands
[1].shifted
12024 && (inst
.instruction
== T_MNEM_mov
12025 || inst
.instruction
== T_MNEM_movs
))
12027 if (in_it_block ())
12028 narrow
= (inst
.instruction
== T_MNEM_mov
);
12030 narrow
= (inst
.instruction
== T_MNEM_movs
);
12035 switch (inst
.operands
[1].shift_kind
)
12037 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12038 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12039 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12040 default: narrow
= FALSE
; break;
12046 inst
.instruction
|= Rn
;
12047 inst
.instruction
|= Rm
<< 3;
12048 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12052 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12053 inst
.instruction
|= Rn
<< r0off
;
12054 encode_thumb32_shifted_operand (1);
12058 switch (inst
.instruction
)
12061 /* In v4t or v5t a move of two lowregs produces unpredictable
12062 results. Don't allow this. */
12065 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12066 "MOV Rd, Rs with two low registers is not "
12067 "permitted on this architecture");
12068 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12072 inst
.instruction
= T_OPCODE_MOV_HR
;
12073 inst
.instruction
|= (Rn
& 0x8) << 4;
12074 inst
.instruction
|= (Rn
& 0x7);
12075 inst
.instruction
|= Rm
<< 3;
12079 /* We know we have low registers at this point.
12080 Generate LSLS Rd, Rs, #0. */
12081 inst
.instruction
= T_OPCODE_LSL_I
;
12082 inst
.instruction
|= Rn
;
12083 inst
.instruction
|= Rm
<< 3;
12089 inst
.instruction
= T_OPCODE_CMP_LR
;
12090 inst
.instruction
|= Rn
;
12091 inst
.instruction
|= Rm
<< 3;
12095 inst
.instruction
= T_OPCODE_CMP_HR
;
12096 inst
.instruction
|= (Rn
& 0x8) << 4;
12097 inst
.instruction
|= (Rn
& 0x7);
12098 inst
.instruction
|= Rm
<< 3;
12105 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12107 /* PR 10443: Do not silently ignore shifted operands. */
12108 constraint (inst
.operands
[1].shifted
,
12109 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12111 if (inst
.operands
[1].isreg
)
12113 if (Rn
< 8 && Rm
< 8)
12115 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12116 since a MOV instruction produces unpredictable results. */
12117 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12118 inst
.instruction
= T_OPCODE_ADD_I3
;
12120 inst
.instruction
= T_OPCODE_CMP_LR
;
12122 inst
.instruction
|= Rn
;
12123 inst
.instruction
|= Rm
<< 3;
12127 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12128 inst
.instruction
= T_OPCODE_MOV_HR
;
12130 inst
.instruction
= T_OPCODE_CMP_HR
;
12136 constraint (Rn
> 7,
12137 _("only lo regs allowed with immediate"));
12138 inst
.instruction
|= Rn
<< 8;
12139 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12150 top
= (inst
.instruction
& 0x00800000) != 0;
12151 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12153 constraint (top
, _(":lower16: not allowed in this instruction"));
12154 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12156 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12158 constraint (!top
, _(":upper16: not allowed in this instruction"));
12159 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12162 Rd
= inst
.operands
[0].reg
;
12163 reject_bad_reg (Rd
);
12165 inst
.instruction
|= Rd
<< 8;
12166 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12168 imm
= inst
.reloc
.exp
.X_add_number
;
12169 inst
.instruction
|= (imm
& 0xf000) << 4;
12170 inst
.instruction
|= (imm
& 0x0800) << 15;
12171 inst
.instruction
|= (imm
& 0x0700) << 4;
12172 inst
.instruction
|= (imm
& 0x00ff);
12177 do_t_mvn_tst (void)
12181 Rn
= inst
.operands
[0].reg
;
12182 Rm
= inst
.operands
[1].reg
;
12184 if (inst
.instruction
== T_MNEM_cmp
12185 || inst
.instruction
== T_MNEM_cmn
)
12186 constraint (Rn
== REG_PC
, BAD_PC
);
12188 reject_bad_reg (Rn
);
12189 reject_bad_reg (Rm
);
12191 if (unified_syntax
)
12193 int r0off
= (inst
.instruction
== T_MNEM_mvn
12194 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12195 bfd_boolean narrow
;
12197 if (inst
.size_req
== 4
12198 || inst
.instruction
> 0xffff
12199 || inst
.operands
[1].shifted
12200 || Rn
> 7 || Rm
> 7)
12202 else if (inst
.instruction
== T_MNEM_cmn
12203 || inst
.instruction
== T_MNEM_tst
)
12205 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12206 narrow
= !in_it_block ();
12208 narrow
= in_it_block ();
12210 if (!inst
.operands
[1].isreg
)
12212 /* For an immediate, we always generate a 32-bit opcode;
12213 section relaxation will shrink it later if possible. */
12214 if (inst
.instruction
< 0xffff)
12215 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12216 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12217 inst
.instruction
|= Rn
<< r0off
;
12218 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12222 /* See if we can do this with a 16-bit instruction. */
12225 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12226 inst
.instruction
|= Rn
;
12227 inst
.instruction
|= Rm
<< 3;
12231 constraint (inst
.operands
[1].shifted
12232 && inst
.operands
[1].immisreg
,
12233 _("shift must be constant"));
12234 if (inst
.instruction
< 0xffff)
12235 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12236 inst
.instruction
|= Rn
<< r0off
;
12237 encode_thumb32_shifted_operand (1);
12243 constraint (inst
.instruction
> 0xffff
12244 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12245 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12246 _("unshifted register required"));
12247 constraint (Rn
> 7 || Rm
> 7,
12250 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12251 inst
.instruction
|= Rn
;
12252 inst
.instruction
|= Rm
<< 3;
12261 if (do_vfp_nsyn_mrs () == SUCCESS
)
12264 Rd
= inst
.operands
[0].reg
;
12265 reject_bad_reg (Rd
);
12266 inst
.instruction
|= Rd
<< 8;
12268 if (inst
.operands
[1].isreg
)
12270 unsigned br
= inst
.operands
[1].reg
;
12271 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12272 as_bad (_("bad register for mrs"));
12274 inst
.instruction
|= br
& (0xf << 16);
12275 inst
.instruction
|= (br
& 0x300) >> 4;
12276 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12280 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12282 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12284 /* PR gas/12698: The constraint is only applied for m_profile.
12285 If the user has specified -march=all, we want to ignore it as
12286 we are building for any CPU type, including non-m variants. */
12287 bfd_boolean m_profile
=
12288 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12289 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12290 "not support requested special purpose register"));
12293 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12295 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12296 _("'APSR', 'CPSR' or 'SPSR' expected"));
12298 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12299 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12300 inst
.instruction
|= 0xf0000;
12310 if (do_vfp_nsyn_msr () == SUCCESS
)
12313 constraint (!inst
.operands
[1].isreg
,
12314 _("Thumb encoding does not support an immediate here"));
12316 if (inst
.operands
[0].isreg
)
12317 flags
= (int)(inst
.operands
[0].reg
);
12319 flags
= inst
.operands
[0].imm
;
12321 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12323 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12325 /* PR gas/12698: The constraint is only applied for m_profile.
12326 If the user has specified -march=all, we want to ignore it as
12327 we are building for any CPU type, including non-m variants. */
12328 bfd_boolean m_profile
=
12329 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12330 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12331 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12332 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12333 && bits
!= PSR_f
)) && m_profile
,
12334 _("selected processor does not support requested special "
12335 "purpose register"));
12338 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12339 "requested special purpose register"));
12341 Rn
= inst
.operands
[1].reg
;
12342 reject_bad_reg (Rn
);
12344 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12345 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12346 inst
.instruction
|= (flags
& 0x300) >> 4;
12347 inst
.instruction
|= (flags
& 0xff);
12348 inst
.instruction
|= Rn
<< 16;
12354 bfd_boolean narrow
;
12355 unsigned Rd
, Rn
, Rm
;
12357 if (!inst
.operands
[2].present
)
12358 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12360 Rd
= inst
.operands
[0].reg
;
12361 Rn
= inst
.operands
[1].reg
;
12362 Rm
= inst
.operands
[2].reg
;
12364 if (unified_syntax
)
12366 if (inst
.size_req
== 4
12372 else if (inst
.instruction
== T_MNEM_muls
)
12373 narrow
= !in_it_block ();
12375 narrow
= in_it_block ();
12379 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12380 constraint (Rn
> 7 || Rm
> 7,
12387 /* 16-bit MULS/Conditional MUL. */
12388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12389 inst
.instruction
|= Rd
;
12392 inst
.instruction
|= Rm
<< 3;
12394 inst
.instruction
|= Rn
<< 3;
12396 constraint (1, _("dest must overlap one source register"));
12400 constraint (inst
.instruction
!= T_MNEM_mul
,
12401 _("Thumb-2 MUL must not set flags"));
12403 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12404 inst
.instruction
|= Rd
<< 8;
12405 inst
.instruction
|= Rn
<< 16;
12406 inst
.instruction
|= Rm
<< 0;
12408 reject_bad_reg (Rd
);
12409 reject_bad_reg (Rn
);
12410 reject_bad_reg (Rm
);
12417 unsigned RdLo
, RdHi
, Rn
, Rm
;
12419 RdLo
= inst
.operands
[0].reg
;
12420 RdHi
= inst
.operands
[1].reg
;
12421 Rn
= inst
.operands
[2].reg
;
12422 Rm
= inst
.operands
[3].reg
;
12424 reject_bad_reg (RdLo
);
12425 reject_bad_reg (RdHi
);
12426 reject_bad_reg (Rn
);
12427 reject_bad_reg (Rm
);
12429 inst
.instruction
|= RdLo
<< 12;
12430 inst
.instruction
|= RdHi
<< 8;
12431 inst
.instruction
|= Rn
<< 16;
12432 inst
.instruction
|= Rm
;
12435 as_tsktsk (_("rdhi and rdlo must be different"));
12441 set_it_insn_type (NEUTRAL_IT_INSN
);
12443 if (unified_syntax
)
12445 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12448 inst
.instruction
|= inst
.operands
[0].imm
;
12452 /* PR9722: Check for Thumb2 availability before
12453 generating a thumb2 nop instruction. */
12454 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12456 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12457 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12460 inst
.instruction
= 0x46c0;
12465 constraint (inst
.operands
[0].present
,
12466 _("Thumb does not support NOP with hints"));
12467 inst
.instruction
= 0x46c0;
12474 if (unified_syntax
)
12476 bfd_boolean narrow
;
12478 if (THUMB_SETS_FLAGS (inst
.instruction
))
12479 narrow
= !in_it_block ();
12481 narrow
= in_it_block ();
12482 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12484 if (inst
.size_req
== 4)
12489 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12490 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12491 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12495 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12496 inst
.instruction
|= inst
.operands
[0].reg
;
12497 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12502 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12504 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12506 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12507 inst
.instruction
|= inst
.operands
[0].reg
;
12508 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12517 Rd
= inst
.operands
[0].reg
;
12518 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12520 reject_bad_reg (Rd
);
12521 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12522 reject_bad_reg (Rn
);
12524 inst
.instruction
|= Rd
<< 8;
12525 inst
.instruction
|= Rn
<< 16;
12527 if (!inst
.operands
[2].isreg
)
12529 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12530 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12536 Rm
= inst
.operands
[2].reg
;
12537 reject_bad_reg (Rm
);
12539 constraint (inst
.operands
[2].shifted
12540 && inst
.operands
[2].immisreg
,
12541 _("shift must be constant"));
12542 encode_thumb32_shifted_operand (2);
12549 unsigned Rd
, Rn
, Rm
;
12551 Rd
= inst
.operands
[0].reg
;
12552 Rn
= inst
.operands
[1].reg
;
12553 Rm
= inst
.operands
[2].reg
;
12555 reject_bad_reg (Rd
);
12556 reject_bad_reg (Rn
);
12557 reject_bad_reg (Rm
);
12559 inst
.instruction
|= Rd
<< 8;
12560 inst
.instruction
|= Rn
<< 16;
12561 inst
.instruction
|= Rm
;
12562 if (inst
.operands
[3].present
)
12564 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12565 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12566 _("expression too complex"));
12567 inst
.instruction
|= (val
& 0x1c) << 10;
12568 inst
.instruction
|= (val
& 0x03) << 6;
12575 if (!inst
.operands
[3].present
)
12579 inst
.instruction
&= ~0x00000020;
12581 /* PR 10168. Swap the Rm and Rn registers. */
12582 Rtmp
= inst
.operands
[1].reg
;
12583 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12584 inst
.operands
[2].reg
= Rtmp
;
12592 if (inst
.operands
[0].immisreg
)
12593 reject_bad_reg (inst
.operands
[0].imm
);
12595 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12599 do_t_push_pop (void)
12603 constraint (inst
.operands
[0].writeback
,
12604 _("push/pop do not support {reglist}^"));
12605 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12606 _("expression too complex"));
12608 mask
= inst
.operands
[0].imm
;
12609 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12610 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12611 else if (inst
.size_req
!= 4
12612 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12613 ? REG_LR
: REG_PC
)))
12615 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12616 inst
.instruction
|= THUMB_PP_PC_LR
;
12617 inst
.instruction
|= mask
& 0xff;
12619 else if (unified_syntax
)
12621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12622 encode_thumb2_ldmstm (13, mask
, TRUE
);
12626 inst
.error
= _("invalid register list to push/pop instruction");
12636 Rd
= inst
.operands
[0].reg
;
12637 Rm
= inst
.operands
[1].reg
;
12639 reject_bad_reg (Rd
);
12640 reject_bad_reg (Rm
);
12642 inst
.instruction
|= Rd
<< 8;
12643 inst
.instruction
|= Rm
<< 16;
12644 inst
.instruction
|= Rm
;
12652 Rd
= inst
.operands
[0].reg
;
12653 Rm
= inst
.operands
[1].reg
;
12655 reject_bad_reg (Rd
);
12656 reject_bad_reg (Rm
);
12658 if (Rd
<= 7 && Rm
<= 7
12659 && inst
.size_req
!= 4)
12661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12662 inst
.instruction
|= Rd
;
12663 inst
.instruction
|= Rm
<< 3;
12665 else if (unified_syntax
)
12667 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12668 inst
.instruction
|= Rd
<< 8;
12669 inst
.instruction
|= Rm
<< 16;
12670 inst
.instruction
|= Rm
;
12673 inst
.error
= BAD_HIREG
;
12681 Rd
= inst
.operands
[0].reg
;
12682 Rm
= inst
.operands
[1].reg
;
12684 reject_bad_reg (Rd
);
12685 reject_bad_reg (Rm
);
12687 inst
.instruction
|= Rd
<< 8;
12688 inst
.instruction
|= Rm
;
12696 Rd
= inst
.operands
[0].reg
;
12697 Rs
= (inst
.operands
[1].present
12698 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12699 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12701 reject_bad_reg (Rd
);
12702 reject_bad_reg (Rs
);
12703 if (inst
.operands
[2].isreg
)
12704 reject_bad_reg (inst
.operands
[2].reg
);
12706 inst
.instruction
|= Rd
<< 8;
12707 inst
.instruction
|= Rs
<< 16;
12708 if (!inst
.operands
[2].isreg
)
12710 bfd_boolean narrow
;
12712 if ((inst
.instruction
& 0x00100000) != 0)
12713 narrow
= !in_it_block ();
12715 narrow
= in_it_block ();
12717 if (Rd
> 7 || Rs
> 7)
12720 if (inst
.size_req
== 4 || !unified_syntax
)
12723 if (inst
.reloc
.exp
.X_op
!= O_constant
12724 || inst
.reloc
.exp
.X_add_number
!= 0)
12727 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12728 relaxation, but it doesn't seem worth the hassle. */
12731 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12732 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12733 inst
.instruction
|= Rs
<< 3;
12734 inst
.instruction
|= Rd
;
12738 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12739 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12743 encode_thumb32_shifted_operand (2);
12749 if (warn_on_deprecated
12750 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12751 as_tsktsk (_("setend use is deprecated for ARMv8"));
12753 set_it_insn_type (OUTSIDE_IT_INSN
);
12754 if (inst
.operands
[0].imm
)
12755 inst
.instruction
|= 0x8;
12761 if (!inst
.operands
[1].present
)
12762 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12764 if (unified_syntax
)
12766 bfd_boolean narrow
;
12769 switch (inst
.instruction
)
12772 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12774 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12776 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12778 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12782 if (THUMB_SETS_FLAGS (inst
.instruction
))
12783 narrow
= !in_it_block ();
12785 narrow
= in_it_block ();
12786 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12788 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12790 if (inst
.operands
[2].isreg
12791 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12792 || inst
.operands
[2].reg
> 7))
12794 if (inst
.size_req
== 4)
12797 reject_bad_reg (inst
.operands
[0].reg
);
12798 reject_bad_reg (inst
.operands
[1].reg
);
12802 if (inst
.operands
[2].isreg
)
12804 reject_bad_reg (inst
.operands
[2].reg
);
12805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12807 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12808 inst
.instruction
|= inst
.operands
[2].reg
;
12810 /* PR 12854: Error on extraneous shifts. */
12811 constraint (inst
.operands
[2].shifted
,
12812 _("extraneous shift as part of operand to shift insn"));
12816 inst
.operands
[1].shifted
= 1;
12817 inst
.operands
[1].shift_kind
= shift_kind
;
12818 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12819 ? T_MNEM_movs
: T_MNEM_mov
);
12820 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12821 encode_thumb32_shifted_operand (1);
12822 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12823 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12828 if (inst
.operands
[2].isreg
)
12830 switch (shift_kind
)
12832 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12833 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12834 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12835 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12839 inst
.instruction
|= inst
.operands
[0].reg
;
12840 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12842 /* PR 12854: Error on extraneous shifts. */
12843 constraint (inst
.operands
[2].shifted
,
12844 _("extraneous shift as part of operand to shift insn"));
12848 switch (shift_kind
)
12850 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12851 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12852 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12855 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12856 inst
.instruction
|= inst
.operands
[0].reg
;
12857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12863 constraint (inst
.operands
[0].reg
> 7
12864 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12865 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12867 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12869 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12870 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12871 _("source1 and dest must be same register"));
12873 switch (inst
.instruction
)
12875 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12876 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12877 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12878 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12882 inst
.instruction
|= inst
.operands
[0].reg
;
12883 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12885 /* PR 12854: Error on extraneous shifts. */
12886 constraint (inst
.operands
[2].shifted
,
12887 _("extraneous shift as part of operand to shift insn"));
12891 switch (inst
.instruction
)
12893 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12894 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12895 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12896 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12899 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12900 inst
.instruction
|= inst
.operands
[0].reg
;
12901 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12909 unsigned Rd
, Rn
, Rm
;
12911 Rd
= inst
.operands
[0].reg
;
12912 Rn
= inst
.operands
[1].reg
;
12913 Rm
= inst
.operands
[2].reg
;
12915 reject_bad_reg (Rd
);
12916 reject_bad_reg (Rn
);
12917 reject_bad_reg (Rm
);
12919 inst
.instruction
|= Rd
<< 8;
12920 inst
.instruction
|= Rn
<< 16;
12921 inst
.instruction
|= Rm
;
12927 unsigned Rd
, Rn
, Rm
;
12929 Rd
= inst
.operands
[0].reg
;
12930 Rm
= inst
.operands
[1].reg
;
12931 Rn
= inst
.operands
[2].reg
;
12933 reject_bad_reg (Rd
);
12934 reject_bad_reg (Rn
);
12935 reject_bad_reg (Rm
);
12937 inst
.instruction
|= Rd
<< 8;
12938 inst
.instruction
|= Rn
<< 16;
12939 inst
.instruction
|= Rm
;
12945 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12946 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12947 _("SMC is not permitted on this architecture"));
12948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12949 _("expression too complex"));
12950 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12951 inst
.instruction
|= (value
& 0xf000) >> 12;
12952 inst
.instruction
|= (value
& 0x0ff0);
12953 inst
.instruction
|= (value
& 0x000f) << 16;
12954 /* PR gas/15623: SMC instructions must be last in an IT block. */
12955 set_it_insn_type_last ();
12961 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12963 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12964 inst
.instruction
|= (value
& 0x0fff);
12965 inst
.instruction
|= (value
& 0xf000) << 4;
12969 do_t_ssat_usat (int bias
)
12973 Rd
= inst
.operands
[0].reg
;
12974 Rn
= inst
.operands
[2].reg
;
12976 reject_bad_reg (Rd
);
12977 reject_bad_reg (Rn
);
12979 inst
.instruction
|= Rd
<< 8;
12980 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12981 inst
.instruction
|= Rn
<< 16;
12983 if (inst
.operands
[3].present
)
12985 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12987 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12989 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12990 _("expression too complex"));
12992 if (shift_amount
!= 0)
12994 constraint (shift_amount
> 31,
12995 _("shift expression is too large"));
12997 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12998 inst
.instruction
|= 0x00200000; /* sh bit. */
13000 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13001 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13009 do_t_ssat_usat (1);
13017 Rd
= inst
.operands
[0].reg
;
13018 Rn
= inst
.operands
[2].reg
;
13020 reject_bad_reg (Rd
);
13021 reject_bad_reg (Rn
);
13023 inst
.instruction
|= Rd
<< 8;
13024 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13025 inst
.instruction
|= Rn
<< 16;
13031 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13032 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13033 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13034 || inst
.operands
[2].negative
,
13037 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13039 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13040 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13041 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13042 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13048 if (!inst
.operands
[2].present
)
13049 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13051 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13052 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13053 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13056 inst
.instruction
|= inst
.operands
[0].reg
;
13057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13058 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13059 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13065 unsigned Rd
, Rn
, Rm
;
13067 Rd
= inst
.operands
[0].reg
;
13068 Rn
= inst
.operands
[1].reg
;
13069 Rm
= inst
.operands
[2].reg
;
13071 reject_bad_reg (Rd
);
13072 reject_bad_reg (Rn
);
13073 reject_bad_reg (Rm
);
13075 inst
.instruction
|= Rd
<< 8;
13076 inst
.instruction
|= Rn
<< 16;
13077 inst
.instruction
|= Rm
;
13078 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13086 Rd
= inst
.operands
[0].reg
;
13087 Rm
= inst
.operands
[1].reg
;
13089 reject_bad_reg (Rd
);
13090 reject_bad_reg (Rm
);
13092 if (inst
.instruction
<= 0xffff
13093 && inst
.size_req
!= 4
13094 && Rd
<= 7 && Rm
<= 7
13095 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13097 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13098 inst
.instruction
|= Rd
;
13099 inst
.instruction
|= Rm
<< 3;
13101 else if (unified_syntax
)
13103 if (inst
.instruction
<= 0xffff)
13104 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13105 inst
.instruction
|= Rd
<< 8;
13106 inst
.instruction
|= Rm
;
13107 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13111 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13112 _("Thumb encoding does not support rotation"));
13113 constraint (1, BAD_HIREG
);
13120 /* We have to do the following check manually as ARM_EXT_OS only applies
13122 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13124 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13125 /* This only applies to the v6m however, not later architectures. */
13126 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13127 as_bad (_("SVC is not permitted on this architecture"));
13128 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13131 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13140 half
= (inst
.instruction
& 0x10) != 0;
13141 set_it_insn_type_last ();
13142 constraint (inst
.operands
[0].immisreg
,
13143 _("instruction requires register index"));
13145 Rn
= inst
.operands
[0].reg
;
13146 Rm
= inst
.operands
[0].imm
;
13148 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13149 constraint (Rn
== REG_SP
, BAD_SP
);
13150 reject_bad_reg (Rm
);
13152 constraint (!half
&& inst
.operands
[0].shifted
,
13153 _("instruction does not allow shifted index"));
13154 inst
.instruction
|= (Rn
<< 16) | Rm
;
13160 if (!inst
.operands
[0].present
)
13161 inst
.operands
[0].imm
= 0;
13163 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13165 constraint (inst
.size_req
== 2,
13166 _("immediate value out of range"));
13167 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13168 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13169 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13173 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13174 inst
.instruction
|= inst
.operands
[0].imm
;
13177 set_it_insn_type (NEUTRAL_IT_INSN
);
13184 do_t_ssat_usat (0);
13192 Rd
= inst
.operands
[0].reg
;
13193 Rn
= inst
.operands
[2].reg
;
13195 reject_bad_reg (Rd
);
13196 reject_bad_reg (Rn
);
13198 inst
.instruction
|= Rd
<< 8;
13199 inst
.instruction
|= inst
.operands
[1].imm
;
13200 inst
.instruction
|= Rn
<< 16;
13203 /* Neon instruction encoder helpers. */
13205 /* Encodings for the different types for various Neon opcodes. */
13207 /* An "invalid" code for the following tables. */
13210 struct neon_tab_entry
13213 unsigned float_or_poly
;
13214 unsigned scalar_or_imm
;
13217 /* Map overloaded Neon opcodes to their respective encodings. */
13218 #define NEON_ENC_TAB \
13219 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13220 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13221 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13222 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13223 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13224 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13225 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13226 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13227 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13228 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13229 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13230 /* Register variants of the following two instructions are encoded as
13231 vcge / vcgt with the operands reversed. */ \
13232 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13233 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13234 X(vfma, N_INV, 0x0000c10, N_INV), \
13235 X(vfms, N_INV, 0x0200c10, N_INV), \
13236 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13237 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13238 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13239 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13240 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13241 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13242 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13243 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13244 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13245 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13246 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13247 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13248 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13249 X(vshl, 0x0000400, N_INV, 0x0800510), \
13250 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13251 X(vand, 0x0000110, N_INV, 0x0800030), \
13252 X(vbic, 0x0100110, N_INV, 0x0800030), \
13253 X(veor, 0x1000110, N_INV, N_INV), \
13254 X(vorn, 0x0300110, N_INV, 0x0800010), \
13255 X(vorr, 0x0200110, N_INV, 0x0800010), \
13256 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13257 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13258 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13259 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13260 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13261 X(vst1, 0x0000000, 0x0800000, N_INV), \
13262 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13263 X(vst2, 0x0000100, 0x0800100, N_INV), \
13264 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13265 X(vst3, 0x0000200, 0x0800200, N_INV), \
13266 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13267 X(vst4, 0x0000300, 0x0800300, N_INV), \
13268 X(vmovn, 0x1b20200, N_INV, N_INV), \
13269 X(vtrn, 0x1b20080, N_INV, N_INV), \
13270 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13271 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13272 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13273 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13274 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13275 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13276 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13277 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13278 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13279 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13280 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13281 X(vseleq, 0xe000a00, N_INV, N_INV), \
13282 X(vselvs, 0xe100a00, N_INV, N_INV), \
13283 X(vselge, 0xe200a00, N_INV, N_INV), \
13284 X(vselgt, 0xe300a00, N_INV, N_INV), \
13285 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13286 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13287 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13288 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13289 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13290 X(aes, 0x3b00300, N_INV, N_INV), \
13291 X(sha3op, 0x2000c00, N_INV, N_INV), \
13292 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13293 X(sha2op, 0x3ba0380, N_INV, N_INV)
13297 #define X(OPC,I,F,S) N_MNEM_##OPC
13302 static const struct neon_tab_entry neon_enc_tab
[] =
13304 #define X(OPC,I,F,S) { (I), (F), (S) }
13309 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13310 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13311 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13312 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13313 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13314 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13315 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13316 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13317 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13318 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13319 #define NEON_ENC_SINGLE_(X) \
13320 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13321 #define NEON_ENC_DOUBLE_(X) \
13322 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13323 #define NEON_ENC_FPV8_(X) \
13324 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13326 #define NEON_ENCODE(type, inst) \
13329 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13330 inst.is_neon = 1; \
13334 #define check_neon_suffixes \
13337 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13339 as_bad (_("invalid neon suffix for non neon instruction")); \
13345 /* Define shapes for instruction operands. The following mnemonic characters
13346 are used in this table:
13348 F - VFP S<n> register
13349 D - Neon D<n> register
13350 Q - Neon Q<n> register
13354 L - D<n> register list
13356 This table is used to generate various data:
13357 - enumerations of the form NS_DDR to be used as arguments to
13359 - a table classifying shapes into single, double, quad, mixed.
13360 - a table used to drive neon_select_shape. */
13362 #define NEON_SHAPE_DEF \
13363 X(3, (D, D, D), DOUBLE), \
13364 X(3, (Q, Q, Q), QUAD), \
13365 X(3, (D, D, I), DOUBLE), \
13366 X(3, (Q, Q, I), QUAD), \
13367 X(3, (D, D, S), DOUBLE), \
13368 X(3, (Q, Q, S), QUAD), \
13369 X(2, (D, D), DOUBLE), \
13370 X(2, (Q, Q), QUAD), \
13371 X(2, (D, S), DOUBLE), \
13372 X(2, (Q, S), QUAD), \
13373 X(2, (D, R), DOUBLE), \
13374 X(2, (Q, R), QUAD), \
13375 X(2, (D, I), DOUBLE), \
13376 X(2, (Q, I), QUAD), \
13377 X(3, (D, L, D), DOUBLE), \
13378 X(2, (D, Q), MIXED), \
13379 X(2, (Q, D), MIXED), \
13380 X(3, (D, Q, I), MIXED), \
13381 X(3, (Q, D, I), MIXED), \
13382 X(3, (Q, D, D), MIXED), \
13383 X(3, (D, Q, Q), MIXED), \
13384 X(3, (Q, Q, D), MIXED), \
13385 X(3, (Q, D, S), MIXED), \
13386 X(3, (D, Q, S), MIXED), \
13387 X(4, (D, D, D, I), DOUBLE), \
13388 X(4, (Q, Q, Q, I), QUAD), \
13389 X(4, (D, D, S, I), DOUBLE), \
13390 X(4, (Q, Q, S, I), QUAD), \
13391 X(2, (F, F), SINGLE), \
13392 X(3, (F, F, F), SINGLE), \
13393 X(2, (F, I), SINGLE), \
13394 X(2, (F, D), MIXED), \
13395 X(2, (D, F), MIXED), \
13396 X(3, (F, F, I), MIXED), \
13397 X(4, (R, R, F, F), SINGLE), \
13398 X(4, (F, F, R, R), SINGLE), \
13399 X(3, (D, R, R), DOUBLE), \
13400 X(3, (R, R, D), DOUBLE), \
13401 X(2, (S, R), SINGLE), \
13402 X(2, (R, S), SINGLE), \
13403 X(2, (F, R), SINGLE), \
13404 X(2, (R, F), SINGLE), \
13405 /* Half float shape supported so far. */\
13406 X (2, (H, D), MIXED), \
13407 X (2, (D, H), MIXED), \
13408 X (2, (H, F), MIXED), \
13409 X (2, (F, H), MIXED), \
13410 X (2, (H, H), HALF), \
13411 X (2, (H, R), HALF), \
13412 X (2, (R, H), HALF), \
13413 X (2, (H, I), HALF), \
13414 X (3, (H, H, H), HALF), \
13415 X (3, (H, F, I), MIXED), \
13416 X (3, (F, H, I), MIXED)
13418 #define S2(A,B) NS_##A##B
13419 #define S3(A,B,C) NS_##A##B##C
13420 #define S4(A,B,C,D) NS_##A##B##C##D
13422 #define X(N, L, C) S##N L
13435 enum neon_shape_class
13444 #define X(N, L, C) SC_##C
13446 static enum neon_shape_class neon_shape_class
[] =
13465 /* Register widths of above. */
13466 static unsigned neon_shape_el_size
[] =
13478 struct neon_shape_info
13481 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13484 #define S2(A,B) { SE_##A, SE_##B }
13485 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13486 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13488 #define X(N, L, C) { N, S##N L }
13490 static struct neon_shape_info neon_shape_tab
[] =
13500 /* Bit masks used in type checking given instructions.
13501 'N_EQK' means the type must be the same as (or based on in some way) the key
13502 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13503 set, various other bits can be set as well in order to modify the meaning of
13504 the type constraint. */
13506 enum neon_type_mask
13530 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13531 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13532 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13533 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13534 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13535 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13536 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13537 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13538 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13539 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13540 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13542 N_MAX_NONSPECIAL
= N_P64
13545 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13547 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13548 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13549 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13550 #define N_S_32 (N_S8 | N_S16 | N_S32)
13551 #define N_F_16_32 (N_F16 | N_F32)
13552 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13553 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13554 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13555 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13557 /* Pass this as the first type argument to neon_check_type to ignore types
13559 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13561 /* Select a "shape" for the current instruction (describing register types or
13562 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13563 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13564 function of operand parsing, so this function doesn't need to be called.
13565 Shapes should be listed in order of decreasing length. */
13567 static enum neon_shape
13568 neon_select_shape (enum neon_shape shape
, ...)
13571 enum neon_shape first_shape
= shape
;
13573 /* Fix missing optional operands. FIXME: we don't know at this point how
13574 many arguments we should have, so this makes the assumption that we have
13575 > 1. This is true of all current Neon opcodes, I think, but may not be
13576 true in the future. */
13577 if (!inst
.operands
[1].present
)
13578 inst
.operands
[1] = inst
.operands
[0];
13580 va_start (ap
, shape
);
13582 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13587 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13589 if (!inst
.operands
[j
].present
)
13595 switch (neon_shape_tab
[shape
].el
[j
])
13597 /* If a .f16, .16, .u16, .s16 type specifier is given over
13598 a VFP single precision register operand, it's essentially
13599 means only half of the register is used.
13601 If the type specifier is given after the mnemonics, the
13602 information is stored in inst.vectype. If the type specifier
13603 is given after register operand, the information is stored
13604 in inst.operands[].vectype.
13606 When there is only one type specifier, and all the register
13607 operands are the same type of hardware register, the type
13608 specifier applies to all register operands.
13610 If no type specifier is given, the shape is inferred from
13611 operand information.
13614 vadd.f16 s0, s1, s2: NS_HHH
13615 vabs.f16 s0, s1: NS_HH
13616 vmov.f16 s0, r1: NS_HR
13617 vmov.f16 r0, s1: NS_RH
13618 vcvt.f16 r0, s1: NS_RH
13619 vcvt.f16.s32 s2, s2, #29: NS_HFI
13620 vcvt.f16.s32 s2, s2: NS_HF
13623 if (!(inst
.operands
[j
].isreg
13624 && inst
.operands
[j
].isvec
13625 && inst
.operands
[j
].issingle
13626 && !inst
.operands
[j
].isquad
13627 && ((inst
.vectype
.elems
== 1
13628 && inst
.vectype
.el
[0].size
== 16)
13629 || (inst
.vectype
.elems
> 1
13630 && inst
.vectype
.el
[j
].size
== 16)
13631 || (inst
.vectype
.elems
== 0
13632 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13633 && inst
.operands
[j
].vectype
.size
== 16))))
13638 if (!(inst
.operands
[j
].isreg
13639 && inst
.operands
[j
].isvec
13640 && inst
.operands
[j
].issingle
13641 && !inst
.operands
[j
].isquad
13642 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13643 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13644 || (inst
.vectype
.elems
== 0
13645 && (inst
.operands
[j
].vectype
.size
== 32
13646 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13651 if (!(inst
.operands
[j
].isreg
13652 && inst
.operands
[j
].isvec
13653 && !inst
.operands
[j
].isquad
13654 && !inst
.operands
[j
].issingle
))
13659 if (!(inst
.operands
[j
].isreg
13660 && !inst
.operands
[j
].isvec
))
13665 if (!(inst
.operands
[j
].isreg
13666 && inst
.operands
[j
].isvec
13667 && inst
.operands
[j
].isquad
13668 && !inst
.operands
[j
].issingle
))
13673 if (!(!inst
.operands
[j
].isreg
13674 && !inst
.operands
[j
].isscalar
))
13679 if (!(!inst
.operands
[j
].isreg
13680 && inst
.operands
[j
].isscalar
))
13690 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13691 /* We've matched all the entries in the shape table, and we don't
13692 have any left over operands which have not been matched. */
13698 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13699 first_error (_("invalid instruction shape"));
13704 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13705 means the Q bit should be set). */
13708 neon_quad (enum neon_shape shape
)
13710 return neon_shape_class
[shape
] == SC_QUAD
;
13714 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13717 /* Allow modification to be made to types which are constrained to be
13718 based on the key element, based on bits set alongside N_EQK. */
13719 if ((typebits
& N_EQK
) != 0)
13721 if ((typebits
& N_HLF
) != 0)
13723 else if ((typebits
& N_DBL
) != 0)
13725 if ((typebits
& N_SGN
) != 0)
13726 *g_type
= NT_signed
;
13727 else if ((typebits
& N_UNS
) != 0)
13728 *g_type
= NT_unsigned
;
13729 else if ((typebits
& N_INT
) != 0)
13730 *g_type
= NT_integer
;
13731 else if ((typebits
& N_FLT
) != 0)
13732 *g_type
= NT_float
;
13733 else if ((typebits
& N_SIZ
) != 0)
13734 *g_type
= NT_untyped
;
13738 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13739 operand type, i.e. the single type specified in a Neon instruction when it
13740 is the only one given. */
13742 static struct neon_type_el
13743 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13745 struct neon_type_el dest
= *key
;
13747 gas_assert ((thisarg
& N_EQK
) != 0);
13749 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13754 /* Convert Neon type and size into compact bitmask representation. */
13756 static enum neon_type_mask
13757 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13764 case 8: return N_8
;
13765 case 16: return N_16
;
13766 case 32: return N_32
;
13767 case 64: return N_64
;
13775 case 8: return N_I8
;
13776 case 16: return N_I16
;
13777 case 32: return N_I32
;
13778 case 64: return N_I64
;
13786 case 16: return N_F16
;
13787 case 32: return N_F32
;
13788 case 64: return N_F64
;
13796 case 8: return N_P8
;
13797 case 16: return N_P16
;
13798 case 64: return N_P64
;
13806 case 8: return N_S8
;
13807 case 16: return N_S16
;
13808 case 32: return N_S32
;
13809 case 64: return N_S64
;
13817 case 8: return N_U8
;
13818 case 16: return N_U16
;
13819 case 32: return N_U32
;
13820 case 64: return N_U64
;
13831 /* Convert compact Neon bitmask type representation to a type and size. Only
13832 handles the case where a single bit is set in the mask. */
13835 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13836 enum neon_type_mask mask
)
13838 if ((mask
& N_EQK
) != 0)
13841 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13843 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13845 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13847 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13852 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13854 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13855 *type
= NT_unsigned
;
13856 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13857 *type
= NT_integer
;
13858 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13859 *type
= NT_untyped
;
13860 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13862 else if ((mask
& (N_F_ALL
)) != 0)
13870 /* Modify a bitmask of allowed types. This is only needed for type
13874 modify_types_allowed (unsigned allowed
, unsigned mods
)
13877 enum neon_el_type type
;
13883 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13885 if (el_type_of_type_chk (&type
, &size
,
13886 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13888 neon_modify_type_size (mods
, &type
, &size
);
13889 destmask
|= type_chk_of_el_type (type
, size
);
13896 /* Check type and return type classification.
13897 The manual states (paraphrase): If one datatype is given, it indicates the
13899 - the second operand, if there is one
13900 - the operand, if there is no second operand
13901 - the result, if there are no operands.
13902 This isn't quite good enough though, so we use a concept of a "key" datatype
13903 which is set on a per-instruction basis, which is the one which matters when
13904 only one data type is written.
13905 Note: this function has side-effects (e.g. filling in missing operands). All
13906 Neon instructions should call it before performing bit encoding. */
13908 static struct neon_type_el
13909 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13912 unsigned i
, pass
, key_el
= 0;
13913 unsigned types
[NEON_MAX_TYPE_ELS
];
13914 enum neon_el_type k_type
= NT_invtype
;
13915 unsigned k_size
= -1u;
13916 struct neon_type_el badtype
= {NT_invtype
, -1};
13917 unsigned key_allowed
= 0;
13919 /* Optional registers in Neon instructions are always (not) in operand 1.
13920 Fill in the missing operand here, if it was omitted. */
13921 if (els
> 1 && !inst
.operands
[1].present
)
13922 inst
.operands
[1] = inst
.operands
[0];
13924 /* Suck up all the varargs. */
13926 for (i
= 0; i
< els
; i
++)
13928 unsigned thisarg
= va_arg (ap
, unsigned);
13929 if (thisarg
== N_IGNORE_TYPE
)
13934 types
[i
] = thisarg
;
13935 if ((thisarg
& N_KEY
) != 0)
13940 if (inst
.vectype
.elems
> 0)
13941 for (i
= 0; i
< els
; i
++)
13942 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13944 first_error (_("types specified in both the mnemonic and operands"));
13948 /* Duplicate inst.vectype elements here as necessary.
13949 FIXME: No idea if this is exactly the same as the ARM assembler,
13950 particularly when an insn takes one register and one non-register
13952 if (inst
.vectype
.elems
== 1 && els
> 1)
13955 inst
.vectype
.elems
= els
;
13956 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13957 for (j
= 0; j
< els
; j
++)
13959 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13962 else if (inst
.vectype
.elems
== 0 && els
> 0)
13965 /* No types were given after the mnemonic, so look for types specified
13966 after each operand. We allow some flexibility here; as long as the
13967 "key" operand has a type, we can infer the others. */
13968 for (j
= 0; j
< els
; j
++)
13969 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13970 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13972 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13974 for (j
= 0; j
< els
; j
++)
13975 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13976 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13981 first_error (_("operand types can't be inferred"));
13985 else if (inst
.vectype
.elems
!= els
)
13987 first_error (_("type specifier has the wrong number of parts"));
13991 for (pass
= 0; pass
< 2; pass
++)
13993 for (i
= 0; i
< els
; i
++)
13995 unsigned thisarg
= types
[i
];
13996 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13997 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13998 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13999 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14001 /* Decay more-specific signed & unsigned types to sign-insensitive
14002 integer types if sign-specific variants are unavailable. */
14003 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14004 && (types_allowed
& N_SU_ALL
) == 0)
14005 g_type
= NT_integer
;
14007 /* If only untyped args are allowed, decay any more specific types to
14008 them. Some instructions only care about signs for some element
14009 sizes, so handle that properly. */
14010 if (((types_allowed
& N_UNT
) == 0)
14011 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14012 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14013 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14014 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14015 g_type
= NT_untyped
;
14019 if ((thisarg
& N_KEY
) != 0)
14023 key_allowed
= thisarg
& ~N_KEY
;
14025 /* Check architecture constraint on FP16 extension. */
14027 && k_type
== NT_float
14028 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14030 inst
.error
= _(BAD_FP16
);
14037 if ((thisarg
& N_VFP
) != 0)
14039 enum neon_shape_el regshape
;
14040 unsigned regwidth
, match
;
14042 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14045 first_error (_("invalid instruction shape"));
14048 regshape
= neon_shape_tab
[ns
].el
[i
];
14049 regwidth
= neon_shape_el_size
[regshape
];
14051 /* In VFP mode, operands must match register widths. If we
14052 have a key operand, use its width, else use the width of
14053 the current operand. */
14059 /* FP16 will use a single precision register. */
14060 if (regwidth
== 32 && match
== 16)
14062 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14066 inst
.error
= _(BAD_FP16
);
14071 if (regwidth
!= match
)
14073 first_error (_("operand size must match register width"));
14078 if ((thisarg
& N_EQK
) == 0)
14080 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14082 if ((given_type
& types_allowed
) == 0)
14084 first_error (_("bad type in Neon instruction"));
14090 enum neon_el_type mod_k_type
= k_type
;
14091 unsigned mod_k_size
= k_size
;
14092 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14093 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14095 first_error (_("inconsistent types in Neon instruction"));
14103 return inst
.vectype
.el
[key_el
];
14106 /* Neon-style VFP instruction forwarding. */
14108 /* Thumb VFP instructions have 0xE in the condition field. */
14111 do_vfp_cond_or_thumb (void)
14116 inst
.instruction
|= 0xe0000000;
14118 inst
.instruction
|= inst
.cond
<< 28;
14121 /* Look up and encode a simple mnemonic, for use as a helper function for the
14122 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14123 etc. It is assumed that operand parsing has already been done, and that the
14124 operands are in the form expected by the given opcode (this isn't necessarily
14125 the same as the form in which they were parsed, hence some massaging must
14126 take place before this function is called).
14127 Checks current arch version against that in the looked-up opcode. */
14130 do_vfp_nsyn_opcode (const char *opname
)
14132 const struct asm_opcode
*opcode
;
14134 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14140 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14147 inst
.instruction
= opcode
->tvalue
;
14148 opcode
->tencode ();
14152 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14153 opcode
->aencode ();
14158 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14160 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14162 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14165 do_vfp_nsyn_opcode ("fadds");
14167 do_vfp_nsyn_opcode ("fsubs");
14169 /* ARMv8.2 fp16 instruction. */
14171 do_scalar_fp16_v82_encode ();
14176 do_vfp_nsyn_opcode ("faddd");
14178 do_vfp_nsyn_opcode ("fsubd");
14182 /* Check operand types to see if this is a VFP instruction, and if so call
14186 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14188 enum neon_shape rs
;
14189 struct neon_type_el et
;
14194 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14195 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14199 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14200 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14201 N_F_ALL
| N_KEY
| N_VFP
);
14208 if (et
.type
!= NT_invtype
)
14219 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14221 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14223 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14226 do_vfp_nsyn_opcode ("fmacs");
14228 do_vfp_nsyn_opcode ("fnmacs");
14230 /* ARMv8.2 fp16 instruction. */
14232 do_scalar_fp16_v82_encode ();
14237 do_vfp_nsyn_opcode ("fmacd");
14239 do_vfp_nsyn_opcode ("fnmacd");
14244 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14246 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14248 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14251 do_vfp_nsyn_opcode ("ffmas");
14253 do_vfp_nsyn_opcode ("ffnmas");
14255 /* ARMv8.2 fp16 instruction. */
14257 do_scalar_fp16_v82_encode ();
14262 do_vfp_nsyn_opcode ("ffmad");
14264 do_vfp_nsyn_opcode ("ffnmad");
14269 do_vfp_nsyn_mul (enum neon_shape rs
)
14271 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14273 do_vfp_nsyn_opcode ("fmuls");
14275 /* ARMv8.2 fp16 instruction. */
14277 do_scalar_fp16_v82_encode ();
14280 do_vfp_nsyn_opcode ("fmuld");
14284 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14286 int is_neg
= (inst
.instruction
& 0x80) != 0;
14287 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14289 if (rs
== NS_FF
|| rs
== NS_HH
)
14292 do_vfp_nsyn_opcode ("fnegs");
14294 do_vfp_nsyn_opcode ("fabss");
14296 /* ARMv8.2 fp16 instruction. */
14298 do_scalar_fp16_v82_encode ();
14303 do_vfp_nsyn_opcode ("fnegd");
14305 do_vfp_nsyn_opcode ("fabsd");
14309 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14310 insns belong to Neon, and are handled elsewhere. */
14313 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14315 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14319 do_vfp_nsyn_opcode ("fldmdbs");
14321 do_vfp_nsyn_opcode ("fldmias");
14326 do_vfp_nsyn_opcode ("fstmdbs");
14328 do_vfp_nsyn_opcode ("fstmias");
14333 do_vfp_nsyn_sqrt (void)
14335 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14336 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14338 if (rs
== NS_FF
|| rs
== NS_HH
)
14340 do_vfp_nsyn_opcode ("fsqrts");
14342 /* ARMv8.2 fp16 instruction. */
14344 do_scalar_fp16_v82_encode ();
14347 do_vfp_nsyn_opcode ("fsqrtd");
14351 do_vfp_nsyn_div (void)
14353 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14354 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14355 N_F_ALL
| N_KEY
| N_VFP
);
14357 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14359 do_vfp_nsyn_opcode ("fdivs");
14361 /* ARMv8.2 fp16 instruction. */
14363 do_scalar_fp16_v82_encode ();
14366 do_vfp_nsyn_opcode ("fdivd");
14370 do_vfp_nsyn_nmul (void)
14372 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14373 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14374 N_F_ALL
| N_KEY
| N_VFP
);
14376 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14378 NEON_ENCODE (SINGLE
, inst
);
14379 do_vfp_sp_dyadic ();
14381 /* ARMv8.2 fp16 instruction. */
14383 do_scalar_fp16_v82_encode ();
14387 NEON_ENCODE (DOUBLE
, inst
);
14388 do_vfp_dp_rd_rn_rm ();
14390 do_vfp_cond_or_thumb ();
14395 do_vfp_nsyn_cmp (void)
14397 enum neon_shape rs
;
14398 if (inst
.operands
[1].isreg
)
14400 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14401 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14403 if (rs
== NS_FF
|| rs
== NS_HH
)
14405 NEON_ENCODE (SINGLE
, inst
);
14406 do_vfp_sp_monadic ();
14410 NEON_ENCODE (DOUBLE
, inst
);
14411 do_vfp_dp_rd_rm ();
14416 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14417 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14419 switch (inst
.instruction
& 0x0fffffff)
14422 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14425 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14431 if (rs
== NS_FI
|| rs
== NS_HI
)
14433 NEON_ENCODE (SINGLE
, inst
);
14434 do_vfp_sp_compare_z ();
14438 NEON_ENCODE (DOUBLE
, inst
);
14442 do_vfp_cond_or_thumb ();
14444 /* ARMv8.2 fp16 instruction. */
14445 if (rs
== NS_HI
|| rs
== NS_HH
)
14446 do_scalar_fp16_v82_encode ();
14450 nsyn_insert_sp (void)
14452 inst
.operands
[1] = inst
.operands
[0];
14453 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14454 inst
.operands
[0].reg
= REG_SP
;
14455 inst
.operands
[0].isreg
= 1;
14456 inst
.operands
[0].writeback
= 1;
14457 inst
.operands
[0].present
= 1;
14461 do_vfp_nsyn_push (void)
14465 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14466 _("register list must contain at least 1 and at most 16 "
14469 if (inst
.operands
[1].issingle
)
14470 do_vfp_nsyn_opcode ("fstmdbs");
14472 do_vfp_nsyn_opcode ("fstmdbd");
14476 do_vfp_nsyn_pop (void)
14480 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14481 _("register list must contain at least 1 and at most 16 "
14484 if (inst
.operands
[1].issingle
)
14485 do_vfp_nsyn_opcode ("fldmias");
14487 do_vfp_nsyn_opcode ("fldmiad");
14490 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14491 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14494 neon_dp_fixup (struct arm_it
* insn
)
14496 unsigned int i
= insn
->instruction
;
14501 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14512 insn
->instruction
= i
;
14515 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14519 neon_logbits (unsigned x
)
14521 return ffs (x
) - 4;
14524 #define LOW4(R) ((R) & 0xf)
14525 #define HI1(R) (((R) >> 4) & 1)
14527 /* Encode insns with bit pattern:
14529 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14530 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14532 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14533 different meaning for some instruction. */
14536 neon_three_same (int isquad
, int ubit
, int size
)
14538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14540 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14541 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14542 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14543 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14544 inst
.instruction
|= (isquad
!= 0) << 6;
14545 inst
.instruction
|= (ubit
!= 0) << 24;
14547 inst
.instruction
|= neon_logbits (size
) << 20;
14549 neon_dp_fixup (&inst
);
14552 /* Encode instructions of the form:
14554 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14555 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14557 Don't write size if SIZE == -1. */
14560 neon_two_same (int qbit
, int ubit
, int size
)
14562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14566 inst
.instruction
|= (qbit
!= 0) << 6;
14567 inst
.instruction
|= (ubit
!= 0) << 24;
14570 inst
.instruction
|= neon_logbits (size
) << 18;
14572 neon_dp_fixup (&inst
);
14575 /* Neon instruction encoders, in approximate order of appearance. */
14578 do_neon_dyadic_i_su (void)
14580 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14581 struct neon_type_el et
= neon_check_type (3, rs
,
14582 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14583 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14587 do_neon_dyadic_i64_su (void)
14589 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14590 struct neon_type_el et
= neon_check_type (3, rs
,
14591 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14592 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14596 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14599 unsigned size
= et
.size
>> 3;
14600 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14601 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14602 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14603 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14604 inst
.instruction
|= (isquad
!= 0) << 6;
14605 inst
.instruction
|= immbits
<< 16;
14606 inst
.instruction
|= (size
>> 3) << 7;
14607 inst
.instruction
|= (size
& 0x7) << 19;
14609 inst
.instruction
|= (uval
!= 0) << 24;
14611 neon_dp_fixup (&inst
);
14615 do_neon_shl_imm (void)
14617 if (!inst
.operands
[2].isreg
)
14619 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14620 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14621 int imm
= inst
.operands
[2].imm
;
14623 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14624 _("immediate out of range for shift"));
14625 NEON_ENCODE (IMMED
, inst
);
14626 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14630 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14631 struct neon_type_el et
= neon_check_type (3, rs
,
14632 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14635 /* VSHL/VQSHL 3-register variants have syntax such as:
14637 whereas other 3-register operations encoded by neon_three_same have
14640 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14642 tmp
= inst
.operands
[2].reg
;
14643 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14644 inst
.operands
[1].reg
= tmp
;
14645 NEON_ENCODE (INTEGER
, inst
);
14646 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14651 do_neon_qshl_imm (void)
14653 if (!inst
.operands
[2].isreg
)
14655 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14656 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14657 int imm
= inst
.operands
[2].imm
;
14659 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14660 _("immediate out of range for shift"));
14661 NEON_ENCODE (IMMED
, inst
);
14662 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14666 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14667 struct neon_type_el et
= neon_check_type (3, rs
,
14668 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14671 /* See note in do_neon_shl_imm. */
14672 tmp
= inst
.operands
[2].reg
;
14673 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14674 inst
.operands
[1].reg
= tmp
;
14675 NEON_ENCODE (INTEGER
, inst
);
14676 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14681 do_neon_rshl (void)
14683 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14684 struct neon_type_el et
= neon_check_type (3, rs
,
14685 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14688 tmp
= inst
.operands
[2].reg
;
14689 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14690 inst
.operands
[1].reg
= tmp
;
14691 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14695 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14697 /* Handle .I8 pseudo-instructions. */
14700 /* Unfortunately, this will make everything apart from zero out-of-range.
14701 FIXME is this the intended semantics? There doesn't seem much point in
14702 accepting .I8 if so. */
14703 immediate
|= immediate
<< 8;
14709 if (immediate
== (immediate
& 0x000000ff))
14711 *immbits
= immediate
;
14714 else if (immediate
== (immediate
& 0x0000ff00))
14716 *immbits
= immediate
>> 8;
14719 else if (immediate
== (immediate
& 0x00ff0000))
14721 *immbits
= immediate
>> 16;
14724 else if (immediate
== (immediate
& 0xff000000))
14726 *immbits
= immediate
>> 24;
14729 if ((immediate
& 0xffff) != (immediate
>> 16))
14730 goto bad_immediate
;
14731 immediate
&= 0xffff;
14734 if (immediate
== (immediate
& 0x000000ff))
14736 *immbits
= immediate
;
14739 else if (immediate
== (immediate
& 0x0000ff00))
14741 *immbits
= immediate
>> 8;
14746 first_error (_("immediate value out of range"));
14751 do_neon_logic (void)
14753 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14755 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14756 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14757 /* U bit and size field were set as part of the bitmask. */
14758 NEON_ENCODE (INTEGER
, inst
);
14759 neon_three_same (neon_quad (rs
), 0, -1);
14763 const int three_ops_form
= (inst
.operands
[2].present
14764 && !inst
.operands
[2].isreg
);
14765 const int immoperand
= (three_ops_form
? 2 : 1);
14766 enum neon_shape rs
= (three_ops_form
14767 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14768 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14769 struct neon_type_el et
= neon_check_type (2, rs
,
14770 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14771 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14775 if (et
.type
== NT_invtype
)
14778 if (three_ops_form
)
14779 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14780 _("first and second operands shall be the same register"));
14782 NEON_ENCODE (IMMED
, inst
);
14784 immbits
= inst
.operands
[immoperand
].imm
;
14787 /* .i64 is a pseudo-op, so the immediate must be a repeating
14789 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14790 inst
.operands
[immoperand
].reg
: 0))
14792 /* Set immbits to an invalid constant. */
14793 immbits
= 0xdeadbeef;
14800 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14804 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14808 /* Pseudo-instruction for VBIC. */
14809 neon_invert_size (&immbits
, 0, et
.size
);
14810 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14814 /* Pseudo-instruction for VORR. */
14815 neon_invert_size (&immbits
, 0, et
.size
);
14816 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14826 inst
.instruction
|= neon_quad (rs
) << 6;
14827 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14828 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14829 inst
.instruction
|= cmode
<< 8;
14830 neon_write_immbits (immbits
);
14832 neon_dp_fixup (&inst
);
14837 do_neon_bitfield (void)
14839 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14840 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14841 neon_three_same (neon_quad (rs
), 0, -1);
14845 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14848 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14849 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14851 if (et
.type
== NT_float
)
14853 NEON_ENCODE (FLOAT
, inst
);
14854 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14858 NEON_ENCODE (INTEGER
, inst
);
14859 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14864 do_neon_dyadic_if_su (void)
14866 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14870 do_neon_dyadic_if_su_d (void)
14872 /* This version only allow D registers, but that constraint is enforced during
14873 operand parsing so we don't need to do anything extra here. */
14874 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14878 do_neon_dyadic_if_i_d (void)
14880 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14881 affected if we specify unsigned args. */
14882 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14885 enum vfp_or_neon_is_neon_bits
14888 NEON_CHECK_ARCH
= 2,
14889 NEON_CHECK_ARCH8
= 4
14892 /* Call this function if an instruction which may have belonged to the VFP or
14893 Neon instruction sets, but turned out to be a Neon instruction (due to the
14894 operand types involved, etc.). We have to check and/or fix-up a couple of
14897 - Make sure the user hasn't attempted to make a Neon instruction
14899 - Alter the value in the condition code field if necessary.
14900 - Make sure that the arch supports Neon instructions.
14902 Which of these operations take place depends on bits from enum
14903 vfp_or_neon_is_neon_bits.
14905 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14906 current instruction's condition is COND_ALWAYS, the condition field is
14907 changed to inst.uncond_value. This is necessary because instructions shared
14908 between VFP and Neon may be conditional for the VFP variants only, and the
14909 unconditional Neon version must have, e.g., 0xF in the condition field. */
14912 vfp_or_neon_is_neon (unsigned check
)
14914 /* Conditions are always legal in Thumb mode (IT blocks). */
14915 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14917 if (inst
.cond
!= COND_ALWAYS
)
14919 first_error (_(BAD_COND
));
14922 if (inst
.uncond_value
!= -1)
14923 inst
.instruction
|= inst
.uncond_value
<< 28;
14926 if ((check
& NEON_CHECK_ARCH
)
14927 && !mark_feature_used (&fpu_neon_ext_v1
))
14929 first_error (_(BAD_FPU
));
14933 if ((check
& NEON_CHECK_ARCH8
)
14934 && !mark_feature_used (&fpu_neon_ext_armv8
))
14936 first_error (_(BAD_FPU
));
14944 do_neon_addsub_if_i (void)
14946 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14949 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14952 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14953 affected if we specify unsigned args. */
14954 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14957 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14959 V<op> A,B (A is operand 0, B is operand 2)
14964 so handle that case specially. */
14967 neon_exchange_operands (void)
14969 if (inst
.operands
[1].present
)
14971 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14973 /* Swap operands[1] and operands[2]. */
14974 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14975 inst
.operands
[1] = inst
.operands
[2];
14976 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14981 inst
.operands
[1] = inst
.operands
[2];
14982 inst
.operands
[2] = inst
.operands
[0];
14987 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14989 if (inst
.operands
[2].isreg
)
14992 neon_exchange_operands ();
14993 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14997 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14998 struct neon_type_el et
= neon_check_type (2, rs
,
14999 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15001 NEON_ENCODE (IMMED
, inst
);
15002 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15003 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15004 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15005 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15006 inst
.instruction
|= neon_quad (rs
) << 6;
15007 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15008 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15010 neon_dp_fixup (&inst
);
15017 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15021 do_neon_cmp_inv (void)
15023 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15029 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15032 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15033 scalars, which are encoded in 5 bits, M : Rm.
15034 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15035 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15039 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15041 unsigned regno
= NEON_SCALAR_REG (scalar
);
15042 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15047 if (regno
> 7 || elno
> 3)
15049 return regno
| (elno
<< 3);
15052 if (regno
> 15 || elno
> 1)
15054 return regno
| (elno
<< 4);
15058 first_error (_("scalar out of range for multiply instruction"));
15064 /* Encode multiply / multiply-accumulate scalar instructions. */
15067 neon_mul_mac (struct neon_type_el et
, int ubit
)
15071 /* Give a more helpful error message if we have an invalid type. */
15072 if (et
.type
== NT_invtype
)
15075 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15080 inst
.instruction
|= LOW4 (scalar
);
15081 inst
.instruction
|= HI1 (scalar
) << 5;
15082 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15083 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15084 inst
.instruction
|= (ubit
!= 0) << 24;
15086 neon_dp_fixup (&inst
);
15090 do_neon_mac_maybe_scalar (void)
15092 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15095 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15098 if (inst
.operands
[2].isscalar
)
15100 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15101 struct neon_type_el et
= neon_check_type (3, rs
,
15102 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15103 NEON_ENCODE (SCALAR
, inst
);
15104 neon_mul_mac (et
, neon_quad (rs
));
15108 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15109 affected if we specify unsigned args. */
15110 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15115 do_neon_fmac (void)
15117 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15120 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15123 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15129 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15130 struct neon_type_el et
= neon_check_type (3, rs
,
15131 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15132 neon_three_same (neon_quad (rs
), 0, et
.size
);
15135 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15136 same types as the MAC equivalents. The polynomial type for this instruction
15137 is encoded the same as the integer type. */
15142 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15145 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15148 if (inst
.operands
[2].isscalar
)
15149 do_neon_mac_maybe_scalar ();
15151 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15155 do_neon_qdmulh (void)
15157 if (inst
.operands
[2].isscalar
)
15159 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15160 struct neon_type_el et
= neon_check_type (3, rs
,
15161 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15162 NEON_ENCODE (SCALAR
, inst
);
15163 neon_mul_mac (et
, neon_quad (rs
));
15167 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15168 struct neon_type_el et
= neon_check_type (3, rs
,
15169 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15170 NEON_ENCODE (INTEGER
, inst
);
15171 /* The U bit (rounding) comes from bit mask. */
15172 neon_three_same (neon_quad (rs
), 0, et
.size
);
15177 do_neon_qrdmlah (void)
15179 /* Check we're on the correct architecture. */
15180 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15182 _("instruction form not available on this architecture.");
15183 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15185 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15186 record_feature_use (&fpu_neon_ext_v8_1
);
15189 if (inst
.operands
[2].isscalar
)
15191 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15192 struct neon_type_el et
= neon_check_type (3, rs
,
15193 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15194 NEON_ENCODE (SCALAR
, inst
);
15195 neon_mul_mac (et
, neon_quad (rs
));
15199 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15200 struct neon_type_el et
= neon_check_type (3, rs
,
15201 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15202 NEON_ENCODE (INTEGER
, inst
);
15203 /* The U bit (rounding) comes from bit mask. */
15204 neon_three_same (neon_quad (rs
), 0, et
.size
);
15209 do_neon_fcmp_absolute (void)
15211 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15212 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15213 N_F_16_32
| N_KEY
);
15214 /* Size field comes from bit mask. */
15215 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15219 do_neon_fcmp_absolute_inv (void)
15221 neon_exchange_operands ();
15222 do_neon_fcmp_absolute ();
15226 do_neon_step (void)
15228 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15229 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15230 N_F_16_32
| N_KEY
);
15231 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15235 do_neon_abs_neg (void)
15237 enum neon_shape rs
;
15238 struct neon_type_el et
;
15240 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15243 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15246 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15247 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15249 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15250 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15251 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15252 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15253 inst
.instruction
|= neon_quad (rs
) << 6;
15254 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15255 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15257 neon_dp_fixup (&inst
);
15263 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15264 struct neon_type_el et
= neon_check_type (2, rs
,
15265 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15266 int imm
= inst
.operands
[2].imm
;
15267 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15268 _("immediate out of range for insert"));
15269 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15275 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15276 struct neon_type_el et
= neon_check_type (2, rs
,
15277 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15278 int imm
= inst
.operands
[2].imm
;
15279 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15280 _("immediate out of range for insert"));
15281 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15285 do_neon_qshlu_imm (void)
15287 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15288 struct neon_type_el et
= neon_check_type (2, rs
,
15289 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15290 int imm
= inst
.operands
[2].imm
;
15291 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15292 _("immediate out of range for shift"));
15293 /* Only encodes the 'U present' variant of the instruction.
15294 In this case, signed types have OP (bit 8) set to 0.
15295 Unsigned types have OP set to 1. */
15296 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15297 /* The rest of the bits are the same as other immediate shifts. */
15298 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15302 do_neon_qmovn (void)
15304 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15305 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15306 /* Saturating move where operands can be signed or unsigned, and the
15307 destination has the same signedness. */
15308 NEON_ENCODE (INTEGER
, inst
);
15309 if (et
.type
== NT_unsigned
)
15310 inst
.instruction
|= 0xc0;
15312 inst
.instruction
|= 0x80;
15313 neon_two_same (0, 1, et
.size
/ 2);
15317 do_neon_qmovun (void)
15319 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15320 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15321 /* Saturating move with unsigned results. Operands must be signed. */
15322 NEON_ENCODE (INTEGER
, inst
);
15323 neon_two_same (0, 1, et
.size
/ 2);
15327 do_neon_rshift_sat_narrow (void)
15329 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15330 or unsigned. If operands are unsigned, results must also be unsigned. */
15331 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15332 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15333 int imm
= inst
.operands
[2].imm
;
15334 /* This gets the bounds check, size encoding and immediate bits calculation
15338 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15339 VQMOVN.I<size> <Dd>, <Qm>. */
15342 inst
.operands
[2].present
= 0;
15343 inst
.instruction
= N_MNEM_vqmovn
;
15348 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15349 _("immediate out of range"));
15350 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15354 do_neon_rshift_sat_narrow_u (void)
15356 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15357 or unsigned. If operands are unsigned, results must also be unsigned. */
15358 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15359 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15360 int imm
= inst
.operands
[2].imm
;
15361 /* This gets the bounds check, size encoding and immediate bits calculation
15365 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15366 VQMOVUN.I<size> <Dd>, <Qm>. */
15369 inst
.operands
[2].present
= 0;
15370 inst
.instruction
= N_MNEM_vqmovun
;
15375 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15376 _("immediate out of range"));
15377 /* FIXME: The manual is kind of unclear about what value U should have in
15378 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15380 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15384 do_neon_movn (void)
15386 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15387 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15388 NEON_ENCODE (INTEGER
, inst
);
15389 neon_two_same (0, 1, et
.size
/ 2);
15393 do_neon_rshift_narrow (void)
15395 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15396 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15397 int imm
= inst
.operands
[2].imm
;
15398 /* This gets the bounds check, size encoding and immediate bits calculation
15402 /* If immediate is zero then we are a pseudo-instruction for
15403 VMOVN.I<size> <Dd>, <Qm> */
15406 inst
.operands
[2].present
= 0;
15407 inst
.instruction
= N_MNEM_vmovn
;
15412 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15413 _("immediate out of range for narrowing operation"));
15414 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15418 do_neon_shll (void)
15420 /* FIXME: Type checking when lengthening. */
15421 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15422 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15423 unsigned imm
= inst
.operands
[2].imm
;
15425 if (imm
== et
.size
)
15427 /* Maximum shift variant. */
15428 NEON_ENCODE (INTEGER
, inst
);
15429 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15430 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15431 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15432 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15433 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15435 neon_dp_fixup (&inst
);
15439 /* A more-specific type check for non-max versions. */
15440 et
= neon_check_type (2, NS_QDI
,
15441 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15442 NEON_ENCODE (IMMED
, inst
);
15443 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15447 /* Check the various types for the VCVT instruction, and return which version
15448 the current instruction is. */
15450 #define CVT_FLAVOUR_VAR \
15451 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15452 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15453 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15454 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15455 /* Half-precision conversions. */ \
15456 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15457 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15458 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15459 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15460 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15461 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15462 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15463 Compared with single/double precision variants, only the co-processor \
15464 field is different, so the encoding flow is reused here. */ \
15465 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15466 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15467 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15468 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15469 /* VFP instructions. */ \
15470 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15471 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15472 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15473 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15474 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15475 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15476 /* VFP instructions with bitshift. */ \
15477 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15478 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15479 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15480 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15481 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15482 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15483 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15484 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15486 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15487 neon_cvt_flavour_##C,
15489 /* The different types of conversions we can do. */
15490 enum neon_cvt_flavour
15493 neon_cvt_flavour_invalid
,
15494 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15499 static enum neon_cvt_flavour
15500 get_neon_cvt_flavour (enum neon_shape rs
)
15502 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15503 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15504 if (et.type != NT_invtype) \
15506 inst.error = NULL; \
15507 return (neon_cvt_flavour_##C); \
15510 struct neon_type_el et
;
15511 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15512 || rs
== NS_FF
) ? N_VFP
: 0;
15513 /* The instruction versions which take an immediate take one register
15514 argument, which is extended to the width of the full register. Thus the
15515 "source" and "destination" registers must have the same width. Hack that
15516 here by making the size equal to the key (wider, in this case) operand. */
15517 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15521 return neon_cvt_flavour_invalid
;
15536 /* Neon-syntax VFP conversions. */
15539 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15541 const char *opname
= 0;
15543 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15544 || rs
== NS_FHI
|| rs
== NS_HFI
)
15546 /* Conversions with immediate bitshift. */
15547 const char *enc
[] =
15549 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15555 if (flavour
< (int) ARRAY_SIZE (enc
))
15557 opname
= enc
[flavour
];
15558 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15559 _("operands 0 and 1 must be the same register"));
15560 inst
.operands
[1] = inst
.operands
[2];
15561 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15566 /* Conversions without bitshift. */
15567 const char *enc
[] =
15569 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15575 if (flavour
< (int) ARRAY_SIZE (enc
))
15576 opname
= enc
[flavour
];
15580 do_vfp_nsyn_opcode (opname
);
15582 /* ARMv8.2 fp16 VCVT instruction. */
15583 if (flavour
== neon_cvt_flavour_s32_f16
15584 || flavour
== neon_cvt_flavour_u32_f16
15585 || flavour
== neon_cvt_flavour_f16_u32
15586 || flavour
== neon_cvt_flavour_f16_s32
)
15587 do_scalar_fp16_v82_encode ();
15591 do_vfp_nsyn_cvtz (void)
15593 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15594 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15595 const char *enc
[] =
15597 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15603 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15604 do_vfp_nsyn_opcode (enc
[flavour
]);
15608 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15609 enum neon_cvt_mode mode
)
15614 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15615 D register operands. */
15616 if (flavour
== neon_cvt_flavour_s32_f64
15617 || flavour
== neon_cvt_flavour_u32_f64
)
15618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15621 if (flavour
== neon_cvt_flavour_s32_f16
15622 || flavour
== neon_cvt_flavour_u32_f16
)
15623 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15626 set_it_insn_type (OUTSIDE_IT_INSN
);
15630 case neon_cvt_flavour_s32_f64
:
15634 case neon_cvt_flavour_s32_f32
:
15638 case neon_cvt_flavour_s32_f16
:
15642 case neon_cvt_flavour_u32_f64
:
15646 case neon_cvt_flavour_u32_f32
:
15650 case neon_cvt_flavour_u32_f16
:
15655 first_error (_("invalid instruction shape"));
15661 case neon_cvt_mode_a
: rm
= 0; break;
15662 case neon_cvt_mode_n
: rm
= 1; break;
15663 case neon_cvt_mode_p
: rm
= 2; break;
15664 case neon_cvt_mode_m
: rm
= 3; break;
15665 default: first_error (_("invalid rounding mode")); return;
15668 NEON_ENCODE (FPV8
, inst
);
15669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15670 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15671 inst
.instruction
|= sz
<< 8;
15673 /* ARMv8.2 fp16 VCVT instruction. */
15674 if (flavour
== neon_cvt_flavour_s32_f16
15675 ||flavour
== neon_cvt_flavour_u32_f16
)
15676 do_scalar_fp16_v82_encode ();
15677 inst
.instruction
|= op
<< 7;
15678 inst
.instruction
|= rm
<< 16;
15679 inst
.instruction
|= 0xf0000000;
15680 inst
.is_neon
= TRUE
;
15684 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15686 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15687 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15688 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15690 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15692 if (flavour
== neon_cvt_flavour_invalid
)
15695 /* PR11109: Handle round-to-zero for VCVT conversions. */
15696 if (mode
== neon_cvt_mode_z
15697 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15698 && (flavour
== neon_cvt_flavour_s16_f16
15699 || flavour
== neon_cvt_flavour_u16_f16
15700 || flavour
== neon_cvt_flavour_s32_f32
15701 || flavour
== neon_cvt_flavour_u32_f32
15702 || flavour
== neon_cvt_flavour_s32_f64
15703 || flavour
== neon_cvt_flavour_u32_f64
)
15704 && (rs
== NS_FD
|| rs
== NS_FF
))
15706 do_vfp_nsyn_cvtz ();
15710 /* ARMv8.2 fp16 VCVT conversions. */
15711 if (mode
== neon_cvt_mode_z
15712 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15713 && (flavour
== neon_cvt_flavour_s32_f16
15714 || flavour
== neon_cvt_flavour_u32_f16
)
15717 do_vfp_nsyn_cvtz ();
15718 do_scalar_fp16_v82_encode ();
15722 /* VFP rather than Neon conversions. */
15723 if (flavour
>= neon_cvt_flavour_first_fp
)
15725 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15726 do_vfp_nsyn_cvt (rs
, flavour
);
15728 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15739 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15740 0x0000100, 0x1000100, 0x0, 0x1000000};
15742 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15745 /* Fixed-point conversion with #0 immediate is encoded as an
15746 integer conversion. */
15747 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15749 NEON_ENCODE (IMMED
, inst
);
15750 if (flavour
!= neon_cvt_flavour_invalid
)
15751 inst
.instruction
|= enctab
[flavour
];
15752 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15753 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15754 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15755 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15756 inst
.instruction
|= neon_quad (rs
) << 6;
15757 inst
.instruction
|= 1 << 21;
15758 if (flavour
< neon_cvt_flavour_s16_f16
)
15760 inst
.instruction
|= 1 << 21;
15761 immbits
= 32 - inst
.operands
[2].imm
;
15762 inst
.instruction
|= immbits
<< 16;
15766 inst
.instruction
|= 3 << 20;
15767 immbits
= 16 - inst
.operands
[2].imm
;
15768 inst
.instruction
|= immbits
<< 16;
15769 inst
.instruction
&= ~(1 << 9);
15772 neon_dp_fixup (&inst
);
15778 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15780 NEON_ENCODE (FLOAT
, inst
);
15781 set_it_insn_type (OUTSIDE_IT_INSN
);
15783 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15790 inst
.instruction
|= neon_quad (rs
) << 6;
15791 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15792 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15793 inst
.instruction
|= mode
<< 8;
15794 if (flavour
== neon_cvt_flavour_u16_f16
15795 || flavour
== neon_cvt_flavour_s16_f16
)
15796 /* Mask off the original size bits and reencode them. */
15797 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15800 inst
.instruction
|= 0xfc000000;
15802 inst
.instruction
|= 0xf0000000;
15808 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15809 0x100, 0x180, 0x0, 0x080};
15811 NEON_ENCODE (INTEGER
, inst
);
15813 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15816 if (flavour
!= neon_cvt_flavour_invalid
)
15817 inst
.instruction
|= enctab
[flavour
];
15819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15821 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15822 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15823 inst
.instruction
|= neon_quad (rs
) << 6;
15824 if (flavour
>= neon_cvt_flavour_s16_f16
15825 && flavour
<= neon_cvt_flavour_f16_u16
)
15826 /* Half precision. */
15827 inst
.instruction
|= 1 << 18;
15829 inst
.instruction
|= 2 << 18;
15831 neon_dp_fixup (&inst
);
15836 /* Half-precision conversions for Advanced SIMD -- neon. */
15841 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15843 as_bad (_("operand size must match register width"));
15848 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15850 as_bad (_("operand size must match register width"));
15855 inst
.instruction
= 0x3b60600;
15857 inst
.instruction
= 0x3b60700;
15859 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15860 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15861 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15862 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15863 neon_dp_fixup (&inst
);
15867 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15868 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15869 do_vfp_nsyn_cvt (rs
, flavour
);
15871 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15876 do_neon_cvtr (void)
15878 do_neon_cvt_1 (neon_cvt_mode_x
);
15884 do_neon_cvt_1 (neon_cvt_mode_z
);
15888 do_neon_cvta (void)
15890 do_neon_cvt_1 (neon_cvt_mode_a
);
15894 do_neon_cvtn (void)
15896 do_neon_cvt_1 (neon_cvt_mode_n
);
15900 do_neon_cvtp (void)
15902 do_neon_cvt_1 (neon_cvt_mode_p
);
15906 do_neon_cvtm (void)
15908 do_neon_cvt_1 (neon_cvt_mode_m
);
15912 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15915 mark_feature_used (&fpu_vfp_ext_armv8
);
15917 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15918 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15919 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15920 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15921 inst
.instruction
|= to
? 0x10000 : 0;
15922 inst
.instruction
|= t
? 0x80 : 0;
15923 inst
.instruction
|= is_double
? 0x100 : 0;
15924 do_vfp_cond_or_thumb ();
15928 do_neon_cvttb_1 (bfd_boolean t
)
15930 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15931 NS_DF
, NS_DH
, NS_NULL
);
15935 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15938 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15940 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15943 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15945 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15947 /* The VCVTB and VCVTT instructions with D-register operands
15948 don't work for SP only targets. */
15949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15953 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15955 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15957 /* The VCVTB and VCVTT instructions with D-register operands
15958 don't work for SP only targets. */
15959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15963 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15970 do_neon_cvtb (void)
15972 do_neon_cvttb_1 (FALSE
);
15977 do_neon_cvtt (void)
15979 do_neon_cvttb_1 (TRUE
);
15983 neon_move_immediate (void)
15985 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15986 struct neon_type_el et
= neon_check_type (2, rs
,
15987 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15988 unsigned immlo
, immhi
= 0, immbits
;
15989 int op
, cmode
, float_p
;
15991 constraint (et
.type
== NT_invtype
,
15992 _("operand size must be specified for immediate VMOV"));
15994 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15995 op
= (inst
.instruction
& (1 << 5)) != 0;
15997 immlo
= inst
.operands
[1].imm
;
15998 if (inst
.operands
[1].regisimm
)
15999 immhi
= inst
.operands
[1].reg
;
16001 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16002 _("immediate has bits set outside the operand size"));
16004 float_p
= inst
.operands
[1].immisfloat
;
16006 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16007 et
.size
, et
.type
)) == FAIL
)
16009 /* Invert relevant bits only. */
16010 neon_invert_size (&immlo
, &immhi
, et
.size
);
16011 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16012 with one or the other; those cases are caught by
16013 neon_cmode_for_move_imm. */
16015 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16016 &op
, et
.size
, et
.type
)) == FAIL
)
16018 first_error (_("immediate out of range"));
16023 inst
.instruction
&= ~(1 << 5);
16024 inst
.instruction
|= op
<< 5;
16026 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16027 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16028 inst
.instruction
|= neon_quad (rs
) << 6;
16029 inst
.instruction
|= cmode
<< 8;
16031 neon_write_immbits (immbits
);
16037 if (inst
.operands
[1].isreg
)
16039 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16041 NEON_ENCODE (INTEGER
, inst
);
16042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16043 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16045 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16046 inst
.instruction
|= neon_quad (rs
) << 6;
16050 NEON_ENCODE (IMMED
, inst
);
16051 neon_move_immediate ();
16054 neon_dp_fixup (&inst
);
16057 /* Encode instructions of form:
16059 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16060 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16063 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16067 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16069 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16070 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16071 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16072 inst
.instruction
|= neon_logbits (size
) << 20;
16074 neon_dp_fixup (&inst
);
16078 do_neon_dyadic_long (void)
16080 /* FIXME: Type checking for lengthening op. */
16081 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16082 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16083 neon_mixed_length (et
, et
.size
);
16087 do_neon_abal (void)
16089 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16090 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16091 neon_mixed_length (et
, et
.size
);
16095 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16097 if (inst
.operands
[2].isscalar
)
16099 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16100 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16101 NEON_ENCODE (SCALAR
, inst
);
16102 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16106 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16107 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16108 NEON_ENCODE (INTEGER
, inst
);
16109 neon_mixed_length (et
, et
.size
);
16114 do_neon_mac_maybe_scalar_long (void)
16116 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16120 do_neon_dyadic_wide (void)
16122 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16123 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16124 neon_mixed_length (et
, et
.size
);
16128 do_neon_dyadic_narrow (void)
16130 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16131 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16132 /* Operand sign is unimportant, and the U bit is part of the opcode,
16133 so force the operand type to integer. */
16134 et
.type
= NT_integer
;
16135 neon_mixed_length (et
, et
.size
/ 2);
16139 do_neon_mul_sat_scalar_long (void)
16141 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16145 do_neon_vmull (void)
16147 if (inst
.operands
[2].isscalar
)
16148 do_neon_mac_maybe_scalar_long ();
16151 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16152 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16154 if (et
.type
== NT_poly
)
16155 NEON_ENCODE (POLY
, inst
);
16157 NEON_ENCODE (INTEGER
, inst
);
16159 /* For polynomial encoding the U bit must be zero, and the size must
16160 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16161 obviously, as 0b10). */
16164 /* Check we're on the correct architecture. */
16165 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16167 _("Instruction form not available on this architecture.");
16172 neon_mixed_length (et
, et
.size
);
16179 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16180 struct neon_type_el et
= neon_check_type (3, rs
,
16181 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16182 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16184 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16185 _("shift out of range"));
16186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16190 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16191 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16192 inst
.instruction
|= neon_quad (rs
) << 6;
16193 inst
.instruction
|= imm
<< 8;
16195 neon_dp_fixup (&inst
);
16201 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16202 struct neon_type_el et
= neon_check_type (2, rs
,
16203 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16204 unsigned op
= (inst
.instruction
>> 7) & 3;
16205 /* N (width of reversed regions) is encoded as part of the bitmask. We
16206 extract it here to check the elements to be reversed are smaller.
16207 Otherwise we'd get a reserved instruction. */
16208 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16209 gas_assert (elsize
!= 0);
16210 constraint (et
.size
>= elsize
,
16211 _("elements must be smaller than reversal region"));
16212 neon_two_same (neon_quad (rs
), 1, et
.size
);
16218 if (inst
.operands
[1].isscalar
)
16220 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16221 struct neon_type_el et
= neon_check_type (2, rs
,
16222 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16223 unsigned sizebits
= et
.size
>> 3;
16224 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16225 int logsize
= neon_logbits (et
.size
);
16226 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16228 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16231 NEON_ENCODE (SCALAR
, inst
);
16232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16234 inst
.instruction
|= LOW4 (dm
);
16235 inst
.instruction
|= HI1 (dm
) << 5;
16236 inst
.instruction
|= neon_quad (rs
) << 6;
16237 inst
.instruction
|= x
<< 17;
16238 inst
.instruction
|= sizebits
<< 16;
16240 neon_dp_fixup (&inst
);
16244 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16245 struct neon_type_el et
= neon_check_type (2, rs
,
16246 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16247 /* Duplicate ARM register to lanes of vector. */
16248 NEON_ENCODE (ARMREG
, inst
);
16251 case 8: inst
.instruction
|= 0x400000; break;
16252 case 16: inst
.instruction
|= 0x000020; break;
16253 case 32: inst
.instruction
|= 0x000000; break;
16256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16257 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16258 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16259 inst
.instruction
|= neon_quad (rs
) << 21;
16260 /* The encoding for this instruction is identical for the ARM and Thumb
16261 variants, except for the condition field. */
16262 do_vfp_cond_or_thumb ();
16266 /* VMOV has particularly many variations. It can be one of:
16267 0. VMOV<c><q> <Qd>, <Qm>
16268 1. VMOV<c><q> <Dd>, <Dm>
16269 (Register operations, which are VORR with Rm = Rn.)
16270 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16271 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16273 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16274 (ARM register to scalar.)
16275 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16276 (Two ARM registers to vector.)
16277 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16278 (Scalar to ARM register.)
16279 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16280 (Vector to two ARM registers.)
16281 8. VMOV.F32 <Sd>, <Sm>
16282 9. VMOV.F64 <Dd>, <Dm>
16283 (VFP register moves.)
16284 10. VMOV.F32 <Sd>, #imm
16285 11. VMOV.F64 <Dd>, #imm
16286 (VFP float immediate load.)
16287 12. VMOV <Rd>, <Sm>
16288 (VFP single to ARM reg.)
16289 13. VMOV <Sd>, <Rm>
16290 (ARM reg to VFP single.)
16291 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16292 (Two ARM regs to two VFP singles.)
16293 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16294 (Two VFP singles to two ARM regs.)
16296 These cases can be disambiguated using neon_select_shape, except cases 1/9
16297 and 3/11 which depend on the operand type too.
16299 All the encoded bits are hardcoded by this function.
16301 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16302 Cases 5, 7 may be used with VFPv2 and above.
16304 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16305 can specify a type where it doesn't make sense to, and is ignored). */
16310 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16311 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16312 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16313 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16314 struct neon_type_el et
;
16315 const char *ldconst
= 0;
16319 case NS_DD
: /* case 1/9. */
16320 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16321 /* It is not an error here if no type is given. */
16323 if (et
.type
== NT_float
&& et
.size
== 64)
16325 do_vfp_nsyn_opcode ("fcpyd");
16328 /* fall through. */
16330 case NS_QQ
: /* case 0/1. */
16332 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16334 /* The architecture manual I have doesn't explicitly state which
16335 value the U bit should have for register->register moves, but
16336 the equivalent VORR instruction has U = 0, so do that. */
16337 inst
.instruction
= 0x0200110;
16338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16339 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16340 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16341 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16342 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16343 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16344 inst
.instruction
|= neon_quad (rs
) << 6;
16346 neon_dp_fixup (&inst
);
16350 case NS_DI
: /* case 3/11. */
16351 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16353 if (et
.type
== NT_float
&& et
.size
== 64)
16355 /* case 11 (fconstd). */
16356 ldconst
= "fconstd";
16357 goto encode_fconstd
;
16359 /* fall through. */
16361 case NS_QI
: /* case 2/3. */
16362 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16364 inst
.instruction
= 0x0800010;
16365 neon_move_immediate ();
16366 neon_dp_fixup (&inst
);
16369 case NS_SR
: /* case 4. */
16371 unsigned bcdebits
= 0;
16373 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16374 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16376 /* .<size> is optional here, defaulting to .32. */
16377 if (inst
.vectype
.elems
== 0
16378 && inst
.operands
[0].vectype
.type
== NT_invtype
16379 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16381 inst
.vectype
.el
[0].type
= NT_untyped
;
16382 inst
.vectype
.el
[0].size
= 32;
16383 inst
.vectype
.elems
= 1;
16386 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16387 logsize
= neon_logbits (et
.size
);
16389 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16391 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16392 && et
.size
!= 32, _(BAD_FPU
));
16393 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16394 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16398 case 8: bcdebits
= 0x8; break;
16399 case 16: bcdebits
= 0x1; break;
16400 case 32: bcdebits
= 0x0; break;
16404 bcdebits
|= x
<< logsize
;
16406 inst
.instruction
= 0xe000b10;
16407 do_vfp_cond_or_thumb ();
16408 inst
.instruction
|= LOW4 (dn
) << 16;
16409 inst
.instruction
|= HI1 (dn
) << 7;
16410 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16411 inst
.instruction
|= (bcdebits
& 3) << 5;
16412 inst
.instruction
|= (bcdebits
>> 2) << 21;
16416 case NS_DRR
: /* case 5 (fmdrr). */
16417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16420 inst
.instruction
= 0xc400b10;
16421 do_vfp_cond_or_thumb ();
16422 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16423 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16424 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16425 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16428 case NS_RS
: /* case 6. */
16431 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16432 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16433 unsigned abcdebits
= 0;
16435 /* .<dt> is optional here, defaulting to .32. */
16436 if (inst
.vectype
.elems
== 0
16437 && inst
.operands
[0].vectype
.type
== NT_invtype
16438 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16440 inst
.vectype
.el
[0].type
= NT_untyped
;
16441 inst
.vectype
.el
[0].size
= 32;
16442 inst
.vectype
.elems
= 1;
16445 et
= neon_check_type (2, NS_NULL
,
16446 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16447 logsize
= neon_logbits (et
.size
);
16449 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16451 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16452 && et
.size
!= 32, _(BAD_FPU
));
16453 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16454 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16458 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16459 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16460 case 32: abcdebits
= 0x00; break;
16464 abcdebits
|= x
<< logsize
;
16465 inst
.instruction
= 0xe100b10;
16466 do_vfp_cond_or_thumb ();
16467 inst
.instruction
|= LOW4 (dn
) << 16;
16468 inst
.instruction
|= HI1 (dn
) << 7;
16469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16470 inst
.instruction
|= (abcdebits
& 3) << 5;
16471 inst
.instruction
|= (abcdebits
>> 2) << 21;
16475 case NS_RRD
: /* case 7 (fmrrd). */
16476 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16479 inst
.instruction
= 0xc500b10;
16480 do_vfp_cond_or_thumb ();
16481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16482 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16483 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16484 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16487 case NS_FF
: /* case 8 (fcpys). */
16488 do_vfp_nsyn_opcode ("fcpys");
16492 case NS_FI
: /* case 10 (fconsts). */
16493 ldconst
= "fconsts";
16495 if (is_quarter_float (inst
.operands
[1].imm
))
16497 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16498 do_vfp_nsyn_opcode (ldconst
);
16500 /* ARMv8.2 fp16 vmov.f16 instruction. */
16502 do_scalar_fp16_v82_encode ();
16505 first_error (_("immediate out of range"));
16509 case NS_RF
: /* case 12 (fmrs). */
16510 do_vfp_nsyn_opcode ("fmrs");
16511 /* ARMv8.2 fp16 vmov.f16 instruction. */
16513 do_scalar_fp16_v82_encode ();
16517 case NS_FR
: /* case 13 (fmsr). */
16518 do_vfp_nsyn_opcode ("fmsr");
16519 /* ARMv8.2 fp16 vmov.f16 instruction. */
16521 do_scalar_fp16_v82_encode ();
16524 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16525 (one of which is a list), but we have parsed four. Do some fiddling to
16526 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16528 case NS_RRFF
: /* case 14 (fmrrs). */
16529 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16530 _("VFP registers must be adjacent"));
16531 inst
.operands
[2].imm
= 2;
16532 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16533 do_vfp_nsyn_opcode ("fmrrs");
16536 case NS_FFRR
: /* case 15 (fmsrr). */
16537 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16538 _("VFP registers must be adjacent"));
16539 inst
.operands
[1] = inst
.operands
[2];
16540 inst
.operands
[2] = inst
.operands
[3];
16541 inst
.operands
[0].imm
= 2;
16542 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16543 do_vfp_nsyn_opcode ("fmsrr");
16547 /* neon_select_shape has determined that the instruction
16548 shape is wrong and has already set the error message. */
16557 do_neon_rshift_round_imm (void)
16559 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16560 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16561 int imm
= inst
.operands
[2].imm
;
16563 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16566 inst
.operands
[2].present
= 0;
16571 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16572 _("immediate out of range for shift"));
16573 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16578 do_neon_movhf (void)
16580 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16581 constraint (rs
!= NS_HH
, _("invalid suffix"));
16583 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16586 do_vfp_sp_monadic ();
16589 inst
.instruction
|= 0xf0000000;
16593 do_neon_movl (void)
16595 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16596 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16597 unsigned sizebits
= et
.size
>> 3;
16598 inst
.instruction
|= sizebits
<< 19;
16599 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16606 struct neon_type_el et
= neon_check_type (2, rs
,
16607 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16608 NEON_ENCODE (INTEGER
, inst
);
16609 neon_two_same (neon_quad (rs
), 1, et
.size
);
16613 do_neon_zip_uzp (void)
16615 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16616 struct neon_type_el et
= neon_check_type (2, rs
,
16617 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16618 if (rs
== NS_DD
&& et
.size
== 32)
16620 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16621 inst
.instruction
= N_MNEM_vtrn
;
16625 neon_two_same (neon_quad (rs
), 1, et
.size
);
16629 do_neon_sat_abs_neg (void)
16631 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16632 struct neon_type_el et
= neon_check_type (2, rs
,
16633 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16634 neon_two_same (neon_quad (rs
), 1, et
.size
);
16638 do_neon_pair_long (void)
16640 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16641 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16642 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16643 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16644 neon_two_same (neon_quad (rs
), 1, et
.size
);
16648 do_neon_recip_est (void)
16650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16651 struct neon_type_el et
= neon_check_type (2, rs
,
16652 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16653 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16654 neon_two_same (neon_quad (rs
), 1, et
.size
);
16660 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16661 struct neon_type_el et
= neon_check_type (2, rs
,
16662 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16663 neon_two_same (neon_quad (rs
), 1, et
.size
);
16669 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16670 struct neon_type_el et
= neon_check_type (2, rs
,
16671 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16672 neon_two_same (neon_quad (rs
), 1, et
.size
);
16678 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16679 struct neon_type_el et
= neon_check_type (2, rs
,
16680 N_EQK
| N_INT
, N_8
| N_KEY
);
16681 neon_two_same (neon_quad (rs
), 1, et
.size
);
16687 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16688 neon_two_same (neon_quad (rs
), 1, -1);
16692 do_neon_tbl_tbx (void)
16694 unsigned listlenbits
;
16695 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16697 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16699 first_error (_("bad list length for table lookup"));
16703 listlenbits
= inst
.operands
[1].imm
- 1;
16704 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16705 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16706 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16707 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16708 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16709 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16710 inst
.instruction
|= listlenbits
<< 8;
16712 neon_dp_fixup (&inst
);
16716 do_neon_ldm_stm (void)
16718 /* P, U and L bits are part of bitmask. */
16719 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16720 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16722 if (inst
.operands
[1].issingle
)
16724 do_vfp_nsyn_ldm_stm (is_dbmode
);
16728 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16729 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16731 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16732 _("register list must contain at least 1 and at most 16 "
16735 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16736 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16737 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16738 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16740 inst
.instruction
|= offsetbits
;
16742 do_vfp_cond_or_thumb ();
16746 do_neon_ldr_str (void)
16748 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16750 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16751 And is UNPREDICTABLE in thumb mode. */
16753 && inst
.operands
[1].reg
== REG_PC
16754 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16757 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16758 else if (warn_on_deprecated
)
16759 as_tsktsk (_("Use of PC here is deprecated"));
16762 if (inst
.operands
[0].issingle
)
16765 do_vfp_nsyn_opcode ("flds");
16767 do_vfp_nsyn_opcode ("fsts");
16769 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16770 if (inst
.vectype
.el
[0].size
== 16)
16771 do_scalar_fp16_v82_encode ();
16776 do_vfp_nsyn_opcode ("fldd");
16778 do_vfp_nsyn_opcode ("fstd");
16782 /* "interleave" version also handles non-interleaving register VLD1/VST1
16786 do_neon_ld_st_interleave (void)
16788 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16789 N_8
| N_16
| N_32
| N_64
);
16790 unsigned alignbits
= 0;
16792 /* The bits in this table go:
16793 0: register stride of one (0) or two (1)
16794 1,2: register list length, minus one (1, 2, 3, 4).
16795 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16796 We use -1 for invalid entries. */
16797 const int typetable
[] =
16799 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16800 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16801 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16802 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16806 if (et
.type
== NT_invtype
)
16809 if (inst
.operands
[1].immisalign
)
16810 switch (inst
.operands
[1].imm
>> 8)
16812 case 64: alignbits
= 1; break;
16814 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16815 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16816 goto bad_alignment
;
16820 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16821 goto bad_alignment
;
16826 first_error (_("bad alignment"));
16830 inst
.instruction
|= alignbits
<< 4;
16831 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16833 /* Bits [4:6] of the immediate in a list specifier encode register stride
16834 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16835 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16836 up the right value for "type" in a table based on this value and the given
16837 list style, then stick it back. */
16838 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16839 | (((inst
.instruction
>> 8) & 3) << 3);
16841 typebits
= typetable
[idx
];
16843 constraint (typebits
== -1, _("bad list type for instruction"));
16844 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16845 _("bad element type for instruction"));
16847 inst
.instruction
&= ~0xf00;
16848 inst
.instruction
|= typebits
<< 8;
16851 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16852 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16853 otherwise. The variable arguments are a list of pairs of legal (size, align)
16854 values, terminated with -1. */
16857 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16860 int result
= FAIL
, thissize
, thisalign
;
16862 if (!inst
.operands
[1].immisalign
)
16868 va_start (ap
, do_alignment
);
16872 thissize
= va_arg (ap
, int);
16873 if (thissize
== -1)
16875 thisalign
= va_arg (ap
, int);
16877 if (size
== thissize
&& align
== thisalign
)
16880 while (result
!= SUCCESS
);
16884 if (result
== SUCCESS
)
16887 first_error (_("unsupported alignment for instruction"));
16893 do_neon_ld_st_lane (void)
16895 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16896 int align_good
, do_alignment
= 0;
16897 int logsize
= neon_logbits (et
.size
);
16898 int align
= inst
.operands
[1].imm
>> 8;
16899 int n
= (inst
.instruction
>> 8) & 3;
16900 int max_el
= 64 / et
.size
;
16902 if (et
.type
== NT_invtype
)
16905 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16906 _("bad list length"));
16907 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16908 _("scalar index out of range"));
16909 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16911 _("stride of 2 unavailable when element size is 8"));
16915 case 0: /* VLD1 / VST1. */
16916 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16918 if (align_good
== FAIL
)
16922 unsigned alignbits
= 0;
16925 case 16: alignbits
= 0x1; break;
16926 case 32: alignbits
= 0x3; break;
16929 inst
.instruction
|= alignbits
<< 4;
16933 case 1: /* VLD2 / VST2. */
16934 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16935 16, 32, 32, 64, -1);
16936 if (align_good
== FAIL
)
16939 inst
.instruction
|= 1 << 4;
16942 case 2: /* VLD3 / VST3. */
16943 constraint (inst
.operands
[1].immisalign
,
16944 _("can't use alignment with this instruction"));
16947 case 3: /* VLD4 / VST4. */
16948 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16949 16, 64, 32, 64, 32, 128, -1);
16950 if (align_good
== FAIL
)
16954 unsigned alignbits
= 0;
16957 case 8: alignbits
= 0x1; break;
16958 case 16: alignbits
= 0x1; break;
16959 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16962 inst
.instruction
|= alignbits
<< 4;
16969 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16970 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16971 inst
.instruction
|= 1 << (4 + logsize
);
16973 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16974 inst
.instruction
|= logsize
<< 10;
16977 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16980 do_neon_ld_dup (void)
16982 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16983 int align_good
, do_alignment
= 0;
16985 if (et
.type
== NT_invtype
)
16988 switch ((inst
.instruction
>> 8) & 3)
16990 case 0: /* VLD1. */
16991 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16992 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16993 &do_alignment
, 16, 16, 32, 32, -1);
16994 if (align_good
== FAIL
)
16996 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16999 case 2: inst
.instruction
|= 1 << 5; break;
17000 default: first_error (_("bad list length")); return;
17002 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17005 case 1: /* VLD2. */
17006 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17007 &do_alignment
, 8, 16, 16, 32, 32, 64,
17009 if (align_good
== FAIL
)
17011 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17012 _("bad list length"));
17013 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17014 inst
.instruction
|= 1 << 5;
17015 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17018 case 2: /* VLD3. */
17019 constraint (inst
.operands
[1].immisalign
,
17020 _("can't use alignment with this instruction"));
17021 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17022 _("bad list length"));
17023 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17024 inst
.instruction
|= 1 << 5;
17025 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17028 case 3: /* VLD4. */
17030 int align
= inst
.operands
[1].imm
>> 8;
17031 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17032 16, 64, 32, 64, 32, 128, -1);
17033 if (align_good
== FAIL
)
17035 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17036 _("bad list length"));
17037 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17038 inst
.instruction
|= 1 << 5;
17039 if (et
.size
== 32 && align
== 128)
17040 inst
.instruction
|= 0x3 << 6;
17042 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17049 inst
.instruction
|= do_alignment
<< 4;
17052 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17053 apart from bits [11:4]. */
17056 do_neon_ldx_stx (void)
17058 if (inst
.operands
[1].isreg
)
17059 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17061 switch (NEON_LANE (inst
.operands
[0].imm
))
17063 case NEON_INTERLEAVE_LANES
:
17064 NEON_ENCODE (INTERLV
, inst
);
17065 do_neon_ld_st_interleave ();
17068 case NEON_ALL_LANES
:
17069 NEON_ENCODE (DUP
, inst
);
17070 if (inst
.instruction
== N_INV
)
17072 first_error ("only loads support such operands");
17079 NEON_ENCODE (LANE
, inst
);
17080 do_neon_ld_st_lane ();
17083 /* L bit comes from bit mask. */
17084 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17085 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17088 if (inst
.operands
[1].postind
)
17090 int postreg
= inst
.operands
[1].imm
& 0xf;
17091 constraint (!inst
.operands
[1].immisreg
,
17092 _("post-index must be a register"));
17093 constraint (postreg
== 0xd || postreg
== 0xf,
17094 _("bad register for post-index"));
17095 inst
.instruction
|= postreg
;
17099 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17100 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17101 || inst
.reloc
.exp
.X_add_number
!= 0,
17104 if (inst
.operands
[1].writeback
)
17106 inst
.instruction
|= 0xd;
17109 inst
.instruction
|= 0xf;
17113 inst
.instruction
|= 0xf9000000;
17115 inst
.instruction
|= 0xf4000000;
17120 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17122 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17123 D register operands. */
17124 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17128 NEON_ENCODE (FPV8
, inst
);
17130 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17132 do_vfp_sp_dyadic ();
17134 /* ARMv8.2 fp16 instruction. */
17136 do_scalar_fp16_v82_encode ();
17139 do_vfp_dp_rd_rn_rm ();
17142 inst
.instruction
|= 0x100;
17144 inst
.instruction
|= 0xf0000000;
17150 set_it_insn_type (OUTSIDE_IT_INSN
);
17152 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17153 first_error (_("invalid instruction shape"));
17159 set_it_insn_type (OUTSIDE_IT_INSN
);
17161 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17164 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17167 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17171 do_vrint_1 (enum neon_cvt_mode mode
)
17173 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17174 struct neon_type_el et
;
17179 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17180 D register operands. */
17181 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17185 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17187 if (et
.type
!= NT_invtype
)
17189 /* VFP encodings. */
17190 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17191 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17192 set_it_insn_type (OUTSIDE_IT_INSN
);
17194 NEON_ENCODE (FPV8
, inst
);
17195 if (rs
== NS_FF
|| rs
== NS_HH
)
17196 do_vfp_sp_monadic ();
17198 do_vfp_dp_rd_rm ();
17202 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17203 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17204 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17205 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17206 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17207 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17208 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17212 inst
.instruction
|= (rs
== NS_DD
) << 8;
17213 do_vfp_cond_or_thumb ();
17215 /* ARMv8.2 fp16 vrint instruction. */
17217 do_scalar_fp16_v82_encode ();
17221 /* Neon encodings (or something broken...). */
17223 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17225 if (et
.type
== NT_invtype
)
17228 set_it_insn_type (OUTSIDE_IT_INSN
);
17229 NEON_ENCODE (FLOAT
, inst
);
17231 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17234 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17235 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17236 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17237 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17238 inst
.instruction
|= neon_quad (rs
) << 6;
17239 /* Mask off the original size bits and reencode them. */
17240 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17241 | neon_logbits (et
.size
) << 18);
17245 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17246 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17247 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17248 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17249 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17250 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17251 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17256 inst
.instruction
|= 0xfc000000;
17258 inst
.instruction
|= 0xf0000000;
17265 do_vrint_1 (neon_cvt_mode_x
);
17271 do_vrint_1 (neon_cvt_mode_z
);
17277 do_vrint_1 (neon_cvt_mode_r
);
17283 do_vrint_1 (neon_cvt_mode_a
);
17289 do_vrint_1 (neon_cvt_mode_n
);
17295 do_vrint_1 (neon_cvt_mode_p
);
17301 do_vrint_1 (neon_cvt_mode_m
);
17305 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17307 unsigned regno
= NEON_SCALAR_REG (opnd
);
17308 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17310 if (elsize
== 16 && elno
< 2 && regno
< 16)
17311 return regno
| (elno
<< 4);
17312 else if (elsize
== 32 && elno
== 0)
17315 first_error (_("scalar out of range"));
17322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17324 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17325 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17326 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17327 _("immediate out of range"));
17329 if (inst
.operands
[2].isscalar
)
17331 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17332 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17333 N_KEY
| N_F16
| N_F32
).size
;
17334 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17336 inst
.instruction
= 0xfe000800;
17337 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17338 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17339 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17340 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17341 inst
.instruction
|= LOW4 (m
);
17342 inst
.instruction
|= HI1 (m
) << 5;
17343 inst
.instruction
|= neon_quad (rs
) << 6;
17344 inst
.instruction
|= rot
<< 20;
17345 inst
.instruction
|= (size
== 32) << 23;
17349 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17350 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17351 N_KEY
| N_F16
| N_F32
).size
;
17352 neon_three_same (neon_quad (rs
), 0, -1);
17353 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17354 inst
.instruction
|= 0xfc200800;
17355 inst
.instruction
|= rot
<< 23;
17356 inst
.instruction
|= (size
== 32) << 20;
17363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17365 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17366 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17367 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17368 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17369 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17370 N_KEY
| N_F16
| N_F32
).size
;
17371 neon_three_same (neon_quad (rs
), 0, -1);
17372 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17373 inst
.instruction
|= 0xfc800800;
17374 inst
.instruction
|= (rot
== 270) << 24;
17375 inst
.instruction
|= (size
== 32) << 20;
17378 /* Crypto v1 instructions. */
17380 do_crypto_2op_1 (unsigned elttype
, int op
)
17382 set_it_insn_type (OUTSIDE_IT_INSN
);
17384 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17390 NEON_ENCODE (INTEGER
, inst
);
17391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17393 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17394 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17396 inst
.instruction
|= op
<< 6;
17399 inst
.instruction
|= 0xfc000000;
17401 inst
.instruction
|= 0xf0000000;
17405 do_crypto_3op_1 (int u
, int op
)
17407 set_it_insn_type (OUTSIDE_IT_INSN
);
17409 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17410 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17415 NEON_ENCODE (INTEGER
, inst
);
17416 neon_three_same (1, u
, 8 << op
);
17422 do_crypto_2op_1 (N_8
, 0);
17428 do_crypto_2op_1 (N_8
, 1);
17434 do_crypto_2op_1 (N_8
, 2);
17440 do_crypto_2op_1 (N_8
, 3);
17446 do_crypto_3op_1 (0, 0);
17452 do_crypto_3op_1 (0, 1);
17458 do_crypto_3op_1 (0, 2);
17464 do_crypto_3op_1 (0, 3);
17470 do_crypto_3op_1 (1, 0);
17476 do_crypto_3op_1 (1, 1);
17480 do_sha256su1 (void)
17482 do_crypto_3op_1 (1, 2);
17488 do_crypto_2op_1 (N_32
, -1);
17494 do_crypto_2op_1 (N_32
, 0);
17498 do_sha256su0 (void)
17500 do_crypto_2op_1 (N_32
, 1);
17504 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17506 unsigned int Rd
= inst
.operands
[0].reg
;
17507 unsigned int Rn
= inst
.operands
[1].reg
;
17508 unsigned int Rm
= inst
.operands
[2].reg
;
17510 set_it_insn_type (OUTSIDE_IT_INSN
);
17511 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17512 inst
.instruction
|= LOW4 (Rn
) << 16;
17513 inst
.instruction
|= LOW4 (Rm
);
17514 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17515 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17517 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17518 as_warn (UNPRED_REG ("r15"));
17519 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17520 as_warn (UNPRED_REG ("r13"));
17562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17564 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17565 do_vfp_sp_dp_cvt ();
17566 do_vfp_cond_or_thumb ();
17570 /* Overall per-instruction processing. */
17572 /* We need to be able to fix up arbitrary expressions in some statements.
17573 This is so that we can handle symbols that are an arbitrary distance from
17574 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17575 which returns part of an address in a form which will be valid for
17576 a data instruction. We do this by pushing the expression into a symbol
17577 in the expr_section, and creating a fix for that. */
17580 fix_new_arm (fragS
* frag
,
17594 /* Create an absolute valued symbol, so we have something to
17595 refer to in the object file. Unfortunately for us, gas's
17596 generic expression parsing will already have folded out
17597 any use of .set foo/.type foo %function that may have
17598 been used to set type information of the target location,
17599 that's being specified symbolically. We have to presume
17600 the user knows what they are doing. */
17604 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17606 symbol
= symbol_find_or_make (name
);
17607 S_SET_SEGMENT (symbol
, absolute_section
);
17608 symbol_set_frag (symbol
, &zero_address_frag
);
17609 S_SET_VALUE (symbol
, exp
->X_add_number
);
17610 exp
->X_op
= O_symbol
;
17611 exp
->X_add_symbol
= symbol
;
17612 exp
->X_add_number
= 0;
17618 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17619 (enum bfd_reloc_code_real
) reloc
);
17623 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17624 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17628 /* Mark whether the fix is to a THUMB instruction, or an ARM
17630 new_fix
->tc_fix_data
= thumb_mode
;
17633 /* Create a frg for an instruction requiring relaxation. */
17635 output_relax_insn (void)
17641 /* The size of the instruction is unknown, so tie the debug info to the
17642 start of the instruction. */
17643 dwarf2_emit_insn (0);
17645 switch (inst
.reloc
.exp
.X_op
)
17648 sym
= inst
.reloc
.exp
.X_add_symbol
;
17649 offset
= inst
.reloc
.exp
.X_add_number
;
17653 offset
= inst
.reloc
.exp
.X_add_number
;
17656 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17660 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17661 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17662 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17665 /* Write a 32-bit thumb instruction to buf. */
17667 put_thumb32_insn (char * buf
, unsigned long insn
)
17669 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17670 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17674 output_inst (const char * str
)
17680 as_bad ("%s -- `%s'", inst
.error
, str
);
17685 output_relax_insn ();
17688 if (inst
.size
== 0)
17691 to
= frag_more (inst
.size
);
17692 /* PR 9814: Record the thumb mode into the current frag so that we know
17693 what type of NOP padding to use, if necessary. We override any previous
17694 setting so that if the mode has changed then the NOPS that we use will
17695 match the encoding of the last instruction in the frag. */
17696 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17698 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17700 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17701 put_thumb32_insn (to
, inst
.instruction
);
17703 else if (inst
.size
> INSN_SIZE
)
17705 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17706 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17707 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17710 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17712 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17713 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17714 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17717 dwarf2_emit_insn (inst
.size
);
17721 output_it_inst (int cond
, int mask
, char * to
)
17723 unsigned long instruction
= 0xbf00;
17726 instruction
|= mask
;
17727 instruction
|= cond
<< 4;
17731 to
= frag_more (2);
17733 dwarf2_emit_insn (2);
17737 md_number_to_chars (to
, instruction
, 2);
17742 /* Tag values used in struct asm_opcode's tag field. */
17745 OT_unconditional
, /* Instruction cannot be conditionalized.
17746 The ARM condition field is still 0xE. */
17747 OT_unconditionalF
, /* Instruction cannot be conditionalized
17748 and carries 0xF in its ARM condition field. */
17749 OT_csuffix
, /* Instruction takes a conditional suffix. */
17750 OT_csuffixF
, /* Some forms of the instruction take a conditional
17751 suffix, others place 0xF where the condition field
17753 OT_cinfix3
, /* Instruction takes a conditional infix,
17754 beginning at character index 3. (In
17755 unified mode, it becomes a suffix.) */
17756 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17757 tsts, cmps, cmns, and teqs. */
17758 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17759 character index 3, even in unified mode. Used for
17760 legacy instructions where suffix and infix forms
17761 may be ambiguous. */
17762 OT_csuf_or_in3
, /* Instruction takes either a conditional
17763 suffix or an infix at character index 3. */
17764 OT_odd_infix_unc
, /* This is the unconditional variant of an
17765 instruction that takes a conditional infix
17766 at an unusual position. In unified mode,
17767 this variant will accept a suffix. */
17768 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17769 are the conditional variants of instructions that
17770 take conditional infixes in unusual positions.
17771 The infix appears at character index
17772 (tag - OT_odd_infix_0). These are not accepted
17773 in unified mode. */
17776 /* Subroutine of md_assemble, responsible for looking up the primary
17777 opcode from the mnemonic the user wrote. STR points to the
17778 beginning of the mnemonic.
17780 This is not simply a hash table lookup, because of conditional
17781 variants. Most instructions have conditional variants, which are
17782 expressed with a _conditional affix_ to the mnemonic. If we were
17783 to encode each conditional variant as a literal string in the opcode
17784 table, it would have approximately 20,000 entries.
17786 Most mnemonics take this affix as a suffix, and in unified syntax,
17787 'most' is upgraded to 'all'. However, in the divided syntax, some
17788 instructions take the affix as an infix, notably the s-variants of
17789 the arithmetic instructions. Of those instructions, all but six
17790 have the infix appear after the third character of the mnemonic.
17792 Accordingly, the algorithm for looking up primary opcodes given
17795 1. Look up the identifier in the opcode table.
17796 If we find a match, go to step U.
17798 2. Look up the last two characters of the identifier in the
17799 conditions table. If we find a match, look up the first N-2
17800 characters of the identifier in the opcode table. If we
17801 find a match, go to step CE.
17803 3. Look up the fourth and fifth characters of the identifier in
17804 the conditions table. If we find a match, extract those
17805 characters from the identifier, and look up the remaining
17806 characters in the opcode table. If we find a match, go
17811 U. Examine the tag field of the opcode structure, in case this is
17812 one of the six instructions with its conditional infix in an
17813 unusual place. If it is, the tag tells us where to find the
17814 infix; look it up in the conditions table and set inst.cond
17815 accordingly. Otherwise, this is an unconditional instruction.
17816 Again set inst.cond accordingly. Return the opcode structure.
17818 CE. Examine the tag field to make sure this is an instruction that
17819 should receive a conditional suffix. If it is not, fail.
17820 Otherwise, set inst.cond from the suffix we already looked up,
17821 and return the opcode structure.
17823 CM. Examine the tag field to make sure this is an instruction that
17824 should receive a conditional infix after the third character.
17825 If it is not, fail. Otherwise, undo the edits to the current
17826 line of input and proceed as for case CE. */
17828 static const struct asm_opcode
*
17829 opcode_lookup (char **str
)
17833 const struct asm_opcode
*opcode
;
17834 const struct asm_cond
*cond
;
17837 /* Scan up to the end of the mnemonic, which must end in white space,
17838 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17839 for (base
= end
= *str
; *end
!= '\0'; end
++)
17840 if (*end
== ' ' || *end
== '.')
17846 /* Handle a possible width suffix and/or Neon type suffix. */
17851 /* The .w and .n suffixes are only valid if the unified syntax is in
17853 if (unified_syntax
&& end
[1] == 'w')
17855 else if (unified_syntax
&& end
[1] == 'n')
17860 inst
.vectype
.elems
= 0;
17862 *str
= end
+ offset
;
17864 if (end
[offset
] == '.')
17866 /* See if we have a Neon type suffix (possible in either unified or
17867 non-unified ARM syntax mode). */
17868 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17871 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17877 /* Look for unaffixed or special-case affixed mnemonic. */
17878 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17883 if (opcode
->tag
< OT_odd_infix_0
)
17885 inst
.cond
= COND_ALWAYS
;
17889 if (warn_on_deprecated
&& unified_syntax
)
17890 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17891 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17892 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17895 inst
.cond
= cond
->value
;
17899 /* Cannot have a conditional suffix on a mnemonic of less than two
17901 if (end
- base
< 3)
17904 /* Look for suffixed mnemonic. */
17906 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17907 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17909 if (opcode
&& cond
)
17912 switch (opcode
->tag
)
17914 case OT_cinfix3_legacy
:
17915 /* Ignore conditional suffixes matched on infix only mnemonics. */
17919 case OT_cinfix3_deprecated
:
17920 case OT_odd_infix_unc
:
17921 if (!unified_syntax
)
17923 /* Fall through. */
17927 case OT_csuf_or_in3
:
17928 inst
.cond
= cond
->value
;
17931 case OT_unconditional
:
17932 case OT_unconditionalF
:
17934 inst
.cond
= cond
->value
;
17937 /* Delayed diagnostic. */
17938 inst
.error
= BAD_COND
;
17939 inst
.cond
= COND_ALWAYS
;
17948 /* Cannot have a usual-position infix on a mnemonic of less than
17949 six characters (five would be a suffix). */
17950 if (end
- base
< 6)
17953 /* Look for infixed mnemonic in the usual position. */
17955 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17959 memcpy (save
, affix
, 2);
17960 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17961 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17963 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17964 memcpy (affix
, save
, 2);
17967 && (opcode
->tag
== OT_cinfix3
17968 || opcode
->tag
== OT_cinfix3_deprecated
17969 || opcode
->tag
== OT_csuf_or_in3
17970 || opcode
->tag
== OT_cinfix3_legacy
))
17973 if (warn_on_deprecated
&& unified_syntax
17974 && (opcode
->tag
== OT_cinfix3
17975 || opcode
->tag
== OT_cinfix3_deprecated
))
17976 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17978 inst
.cond
= cond
->value
;
17985 /* This function generates an initial IT instruction, leaving its block
17986 virtually open for the new instructions. Eventually,
17987 the mask will be updated by now_it_add_mask () each time
17988 a new instruction needs to be included in the IT block.
17989 Finally, the block is closed with close_automatic_it_block ().
17990 The block closure can be requested either from md_assemble (),
17991 a tencode (), or due to a label hook. */
17994 new_automatic_it_block (int cond
)
17996 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17997 now_it
.mask
= 0x18;
17999 now_it
.block_length
= 1;
18000 mapping_state (MAP_THUMB
);
18001 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18002 now_it
.warn_deprecated
= FALSE
;
18003 now_it
.insn_cond
= TRUE
;
18006 /* Close an automatic IT block.
18007 See comments in new_automatic_it_block (). */
18010 close_automatic_it_block (void)
18012 now_it
.mask
= 0x10;
18013 now_it
.block_length
= 0;
18016 /* Update the mask of the current automatically-generated IT
18017 instruction. See comments in new_automatic_it_block (). */
18020 now_it_add_mask (int cond
)
18022 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18023 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18024 | ((bitvalue) << (nbit)))
18025 const int resulting_bit
= (cond
& 1);
18027 now_it
.mask
&= 0xf;
18028 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18030 (5 - now_it
.block_length
));
18031 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18033 ((5 - now_it
.block_length
) - 1) );
18034 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18037 #undef SET_BIT_VALUE
18040 /* The IT blocks handling machinery is accessed through the these functions:
18041 it_fsm_pre_encode () from md_assemble ()
18042 set_it_insn_type () optional, from the tencode functions
18043 set_it_insn_type_last () ditto
18044 in_it_block () ditto
18045 it_fsm_post_encode () from md_assemble ()
18046 force_automatic_it_block_close () from label handling functions
18049 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18050 initializing the IT insn type with a generic initial value depending
18051 on the inst.condition.
18052 2) During the tencode function, two things may happen:
18053 a) The tencode function overrides the IT insn type by
18054 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18055 b) The tencode function queries the IT block state by
18056 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18058 Both set_it_insn_type and in_it_block run the internal FSM state
18059 handling function (handle_it_state), because: a) setting the IT insn
18060 type may incur in an invalid state (exiting the function),
18061 and b) querying the state requires the FSM to be updated.
18062 Specifically we want to avoid creating an IT block for conditional
18063 branches, so it_fsm_pre_encode is actually a guess and we can't
18064 determine whether an IT block is required until the tencode () routine
18065 has decided what type of instruction this actually it.
18066 Because of this, if set_it_insn_type and in_it_block have to be used,
18067 set_it_insn_type has to be called first.
18069 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18070 determines the insn IT type depending on the inst.cond code.
18071 When a tencode () routine encodes an instruction that can be
18072 either outside an IT block, or, in the case of being inside, has to be
18073 the last one, set_it_insn_type_last () will determine the proper
18074 IT instruction type based on the inst.cond code. Otherwise,
18075 set_it_insn_type can be called for overriding that logic or
18076 for covering other cases.
18078 Calling handle_it_state () may not transition the IT block state to
18079 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18080 still queried. Instead, if the FSM determines that the state should
18081 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18082 after the tencode () function: that's what it_fsm_post_encode () does.
18084 Since in_it_block () calls the state handling function to get an
18085 updated state, an error may occur (due to invalid insns combination).
18086 In that case, inst.error is set.
18087 Therefore, inst.error has to be checked after the execution of
18088 the tencode () routine.
18090 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18091 any pending state change (if any) that didn't take place in
18092 handle_it_state () as explained above. */
18095 it_fsm_pre_encode (void)
18097 if (inst
.cond
!= COND_ALWAYS
)
18098 inst
.it_insn_type
= INSIDE_IT_INSN
;
18100 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18102 now_it
.state_handled
= 0;
18105 /* IT state FSM handling function. */
18108 handle_it_state (void)
18110 now_it
.state_handled
= 1;
18111 now_it
.insn_cond
= FALSE
;
18113 switch (now_it
.state
)
18115 case OUTSIDE_IT_BLOCK
:
18116 switch (inst
.it_insn_type
)
18118 case OUTSIDE_IT_INSN
:
18121 case INSIDE_IT_INSN
:
18122 case INSIDE_IT_LAST_INSN
:
18123 if (thumb_mode
== 0)
18126 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18127 as_tsktsk (_("Warning: conditional outside an IT block"\
18132 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18133 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18135 /* Automatically generate the IT instruction. */
18136 new_automatic_it_block (inst
.cond
);
18137 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18138 close_automatic_it_block ();
18142 inst
.error
= BAD_OUT_IT
;
18148 case IF_INSIDE_IT_LAST_INSN
:
18149 case NEUTRAL_IT_INSN
:
18153 now_it
.state
= MANUAL_IT_BLOCK
;
18154 now_it
.block_length
= 0;
18159 case AUTOMATIC_IT_BLOCK
:
18160 /* Three things may happen now:
18161 a) We should increment current it block size;
18162 b) We should close current it block (closing insn or 4 insns);
18163 c) We should close current it block and start a new one (due
18164 to incompatible conditions or
18165 4 insns-length block reached). */
18167 switch (inst
.it_insn_type
)
18169 case OUTSIDE_IT_INSN
:
18170 /* The closure of the block shall happen immediately,
18171 so any in_it_block () call reports the block as closed. */
18172 force_automatic_it_block_close ();
18175 case INSIDE_IT_INSN
:
18176 case INSIDE_IT_LAST_INSN
:
18177 case IF_INSIDE_IT_LAST_INSN
:
18178 now_it
.block_length
++;
18180 if (now_it
.block_length
> 4
18181 || !now_it_compatible (inst
.cond
))
18183 force_automatic_it_block_close ();
18184 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18185 new_automatic_it_block (inst
.cond
);
18189 now_it
.insn_cond
= TRUE
;
18190 now_it_add_mask (inst
.cond
);
18193 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18194 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18195 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18196 close_automatic_it_block ();
18199 case NEUTRAL_IT_INSN
:
18200 now_it
.block_length
++;
18201 now_it
.insn_cond
= TRUE
;
18203 if (now_it
.block_length
> 4)
18204 force_automatic_it_block_close ();
18206 now_it_add_mask (now_it
.cc
& 1);
18210 close_automatic_it_block ();
18211 now_it
.state
= MANUAL_IT_BLOCK
;
18216 case MANUAL_IT_BLOCK
:
18218 /* Check conditional suffixes. */
18219 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18222 now_it
.mask
&= 0x1f;
18223 is_last
= (now_it
.mask
== 0x10);
18224 now_it
.insn_cond
= TRUE
;
18226 switch (inst
.it_insn_type
)
18228 case OUTSIDE_IT_INSN
:
18229 inst
.error
= BAD_NOT_IT
;
18232 case INSIDE_IT_INSN
:
18233 if (cond
!= inst
.cond
)
18235 inst
.error
= BAD_IT_COND
;
18240 case INSIDE_IT_LAST_INSN
:
18241 case IF_INSIDE_IT_LAST_INSN
:
18242 if (cond
!= inst
.cond
)
18244 inst
.error
= BAD_IT_COND
;
18249 inst
.error
= BAD_BRANCH
;
18254 case NEUTRAL_IT_INSN
:
18255 /* The BKPT instruction is unconditional even in an IT block. */
18259 inst
.error
= BAD_IT_IT
;
18269 struct depr_insn_mask
18271 unsigned long pattern
;
18272 unsigned long mask
;
18273 const char* description
;
18276 /* List of 16-bit instruction patterns deprecated in an IT block in
18278 static const struct depr_insn_mask depr_it_insns
[] = {
18279 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18280 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18281 { 0xa000, 0xb800, N_("ADR") },
18282 { 0x4800, 0xf800, N_("Literal loads") },
18283 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18284 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18285 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18286 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18287 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18292 it_fsm_post_encode (void)
18296 if (!now_it
.state_handled
)
18297 handle_it_state ();
18299 if (now_it
.insn_cond
18300 && !now_it
.warn_deprecated
18301 && warn_on_deprecated
18302 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18304 if (inst
.instruction
>= 0x10000)
18306 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18307 "deprecated in ARMv8"));
18308 now_it
.warn_deprecated
= TRUE
;
18312 const struct depr_insn_mask
*p
= depr_it_insns
;
18314 while (p
->mask
!= 0)
18316 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18318 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18319 "of the following class are deprecated in ARMv8: "
18320 "%s"), p
->description
);
18321 now_it
.warn_deprecated
= TRUE
;
18329 if (now_it
.block_length
> 1)
18331 as_tsktsk (_("IT blocks containing more than one conditional "
18332 "instruction are deprecated in ARMv8"));
18333 now_it
.warn_deprecated
= TRUE
;
18337 is_last
= (now_it
.mask
== 0x10);
18340 now_it
.state
= OUTSIDE_IT_BLOCK
;
18346 force_automatic_it_block_close (void)
18348 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18350 close_automatic_it_block ();
18351 now_it
.state
= OUTSIDE_IT_BLOCK
;
18359 if (!now_it
.state_handled
)
18360 handle_it_state ();
18362 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18365 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18366 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18367 here, hence the "known" in the function name. */
18370 known_t32_only_insn (const struct asm_opcode
*opcode
)
18372 /* Original Thumb-1 wide instruction. */
18373 if (opcode
->tencode
== do_t_blx
18374 || opcode
->tencode
== do_t_branch23
18375 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18376 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18379 /* Wide-only instruction added to ARMv8-M Baseline. */
18380 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18381 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18382 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18383 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18389 /* Whether wide instruction variant can be used if available for a valid OPCODE
18393 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18395 if (known_t32_only_insn (opcode
))
18398 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18399 of variant T3 of B.W is checked in do_t_branch. */
18400 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18401 && opcode
->tencode
== do_t_branch
)
18404 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18405 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18406 && opcode
->tencode
== do_t_mov_cmp
18407 /* Make sure CMP instruction is not affected. */
18408 && opcode
->aencode
== do_mov
)
18411 /* Wide instruction variants of all instructions with narrow *and* wide
18412 variants become available with ARMv6t2. Other opcodes are either
18413 narrow-only or wide-only and are thus available if OPCODE is valid. */
18414 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18417 /* OPCODE with narrow only instruction variant or wide variant not
18423 md_assemble (char *str
)
18426 const struct asm_opcode
* opcode
;
18428 /* Align the previous label if needed. */
18429 if (last_label_seen
!= NULL
)
18431 symbol_set_frag (last_label_seen
, frag_now
);
18432 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18433 S_SET_SEGMENT (last_label_seen
, now_seg
);
18436 memset (&inst
, '\0', sizeof (inst
));
18437 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18439 opcode
= opcode_lookup (&p
);
18442 /* It wasn't an instruction, but it might be a register alias of
18443 the form alias .req reg, or a Neon .dn/.qn directive. */
18444 if (! create_register_alias (str
, p
)
18445 && ! create_neon_reg_alias (str
, p
))
18446 as_bad (_("bad instruction `%s'"), str
);
18451 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18452 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18454 /* The value which unconditional instructions should have in place of the
18455 condition field. */
18456 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18460 arm_feature_set variant
;
18462 variant
= cpu_variant
;
18463 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18464 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18465 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18466 /* Check that this instruction is supported for this CPU. */
18467 if (!opcode
->tvariant
18468 || (thumb_mode
== 1
18469 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18471 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18474 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18475 && opcode
->tencode
!= do_t_branch
)
18477 as_bad (_("Thumb does not support conditional execution"));
18481 /* Two things are addressed here:
18482 1) Implicit require narrow instructions on Thumb-1.
18483 This avoids relaxation accidentally introducing Thumb-2
18485 2) Reject wide instructions in non Thumb-2 cores.
18487 Only instructions with narrow and wide variants need to be handled
18488 but selecting all non wide-only instructions is easier. */
18489 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18490 && !t32_insn_ok (variant
, opcode
))
18492 if (inst
.size_req
== 0)
18494 else if (inst
.size_req
== 4)
18496 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18497 as_bad (_("selected processor does not support 32bit wide "
18498 "variant of instruction `%s'"), str
);
18500 as_bad (_("selected processor does not support `%s' in "
18501 "Thumb-2 mode"), str
);
18506 inst
.instruction
= opcode
->tvalue
;
18508 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18510 /* Prepare the it_insn_type for those encodings that don't set
18512 it_fsm_pre_encode ();
18514 opcode
->tencode ();
18516 it_fsm_post_encode ();
18519 if (!(inst
.error
|| inst
.relax
))
18521 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18522 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18523 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18525 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18530 /* Something has gone badly wrong if we try to relax a fixed size
18532 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18534 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18535 *opcode
->tvariant
);
18536 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18537 set those bits when Thumb-2 32-bit instructions are seen. The impact
18538 of relaxable instructions will be considered later after we finish all
18540 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18541 variant
= arm_arch_none
;
18543 variant
= cpu_variant
;
18544 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18548 check_neon_suffixes
;
18552 mapping_state (MAP_THUMB
);
18555 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18559 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18560 is_bx
= (opcode
->aencode
== do_bx
);
18562 /* Check that this instruction is supported for this CPU. */
18563 if (!(is_bx
&& fix_v4bx
)
18564 && !(opcode
->avariant
&&
18565 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18567 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18572 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18576 inst
.instruction
= opcode
->avalue
;
18577 if (opcode
->tag
== OT_unconditionalF
)
18578 inst
.instruction
|= 0xFU
<< 28;
18580 inst
.instruction
|= inst
.cond
<< 28;
18581 inst
.size
= INSN_SIZE
;
18582 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18584 it_fsm_pre_encode ();
18585 opcode
->aencode ();
18586 it_fsm_post_encode ();
18588 /* Arm mode bx is marked as both v4T and v5 because it's still required
18589 on a hypothetical non-thumb v5 core. */
18591 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18593 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18594 *opcode
->avariant
);
18596 check_neon_suffixes
;
18600 mapping_state (MAP_ARM
);
18605 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18613 check_it_blocks_finished (void)
18618 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18619 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18620 == MANUAL_IT_BLOCK
)
18622 as_warn (_("section '%s' finished with an open IT block."),
18626 if (now_it
.state
== MANUAL_IT_BLOCK
)
18627 as_warn (_("file finished with an open IT block."));
18631 /* Various frobbings of labels and their addresses. */
18634 arm_start_line_hook (void)
18636 last_label_seen
= NULL
;
18640 arm_frob_label (symbolS
* sym
)
18642 last_label_seen
= sym
;
18644 ARM_SET_THUMB (sym
, thumb_mode
);
18646 #if defined OBJ_COFF || defined OBJ_ELF
18647 ARM_SET_INTERWORK (sym
, support_interwork
);
18650 force_automatic_it_block_close ();
18652 /* Note - do not allow local symbols (.Lxxx) to be labelled
18653 as Thumb functions. This is because these labels, whilst
18654 they exist inside Thumb code, are not the entry points for
18655 possible ARM->Thumb calls. Also, these labels can be used
18656 as part of a computed goto or switch statement. eg gcc
18657 can generate code that looks like this:
18659 ldr r2, [pc, .Laaa]
18669 The first instruction loads the address of the jump table.
18670 The second instruction converts a table index into a byte offset.
18671 The third instruction gets the jump address out of the table.
18672 The fourth instruction performs the jump.
18674 If the address stored at .Laaa is that of a symbol which has the
18675 Thumb_Func bit set, then the linker will arrange for this address
18676 to have the bottom bit set, which in turn would mean that the
18677 address computation performed by the third instruction would end
18678 up with the bottom bit set. Since the ARM is capable of unaligned
18679 word loads, the instruction would then load the incorrect address
18680 out of the jump table, and chaos would ensue. */
18681 if (label_is_thumb_function_name
18682 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18683 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18685 /* When the address of a Thumb function is taken the bottom
18686 bit of that address should be set. This will allow
18687 interworking between Arm and Thumb functions to work
18690 THUMB_SET_FUNC (sym
, 1);
18692 label_is_thumb_function_name
= FALSE
;
18695 dwarf2_emit_label (sym
);
18699 arm_data_in_code (void)
18701 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18703 *input_line_pointer
= '/';
18704 input_line_pointer
+= 5;
18705 *input_line_pointer
= 0;
18713 arm_canonicalize_symbol_name (char * name
)
18717 if (thumb_mode
&& (len
= strlen (name
)) > 5
18718 && streq (name
+ len
- 5, "/data"))
18719 *(name
+ len
- 5) = 0;
18724 /* Table of all register names defined by default. The user can
18725 define additional names with .req. Note that all register names
18726 should appear in both upper and lowercase variants. Some registers
18727 also have mixed-case names. */
18729 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18730 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18731 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18732 #define REGSET(p,t) \
18733 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18734 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18735 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18736 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18737 #define REGSETH(p,t) \
18738 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18739 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18740 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18741 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18742 #define REGSET2(p,t) \
18743 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18744 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18745 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18746 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18747 #define SPLRBANK(base,bank,t) \
18748 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18749 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18750 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18751 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18752 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18753 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18755 static const struct reg_entry reg_names
[] =
18757 /* ARM integer registers. */
18758 REGSET(r
, RN
), REGSET(R
, RN
),
18760 /* ATPCS synonyms. */
18761 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18762 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18763 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18765 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18766 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18767 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18769 /* Well-known aliases. */
18770 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18771 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18773 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18774 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18776 /* Coprocessor numbers. */
18777 REGSET(p
, CP
), REGSET(P
, CP
),
18779 /* Coprocessor register numbers. The "cr" variants are for backward
18781 REGSET(c
, CN
), REGSET(C
, CN
),
18782 REGSET(cr
, CN
), REGSET(CR
, CN
),
18784 /* ARM banked registers. */
18785 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18786 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18787 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18788 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18789 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18790 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18791 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18793 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18794 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18795 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18796 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18797 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18798 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18799 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18800 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18802 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18803 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18804 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18805 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18806 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18807 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18808 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18809 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18810 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18812 /* FPA registers. */
18813 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18814 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18816 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18817 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18819 /* VFP SP registers. */
18820 REGSET(s
,VFS
), REGSET(S
,VFS
),
18821 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18823 /* VFP DP Registers. */
18824 REGSET(d
,VFD
), REGSET(D
,VFD
),
18825 /* Extra Neon DP registers. */
18826 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18828 /* Neon QP registers. */
18829 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18831 /* VFP control registers. */
18832 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18833 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18834 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18835 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18836 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18837 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18839 /* Maverick DSP coprocessor registers. */
18840 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18841 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18843 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18844 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18845 REGDEF(dspsc
,0,DSPSC
),
18847 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18848 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18849 REGDEF(DSPSC
,0,DSPSC
),
18851 /* iWMMXt data registers - p0, c0-15. */
18852 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18854 /* iWMMXt control registers - p1, c0-3. */
18855 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18856 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18857 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18858 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18860 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18861 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18862 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18863 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18864 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18866 /* XScale accumulator registers. */
18867 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18873 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18874 within psr_required_here. */
18875 static const struct asm_psr psrs
[] =
18877 /* Backward compatibility notation. Note that "all" is no longer
18878 truly all possible PSR bits. */
18879 {"all", PSR_c
| PSR_f
},
18883 /* Individual flags. */
18889 /* Combinations of flags. */
18890 {"fs", PSR_f
| PSR_s
},
18891 {"fx", PSR_f
| PSR_x
},
18892 {"fc", PSR_f
| PSR_c
},
18893 {"sf", PSR_s
| PSR_f
},
18894 {"sx", PSR_s
| PSR_x
},
18895 {"sc", PSR_s
| PSR_c
},
18896 {"xf", PSR_x
| PSR_f
},
18897 {"xs", PSR_x
| PSR_s
},
18898 {"xc", PSR_x
| PSR_c
},
18899 {"cf", PSR_c
| PSR_f
},
18900 {"cs", PSR_c
| PSR_s
},
18901 {"cx", PSR_c
| PSR_x
},
18902 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18903 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18904 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18905 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18906 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18907 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18908 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18909 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18910 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18911 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18912 {"scf", PSR_s
| PSR_c
| PSR_f
},
18913 {"scx", PSR_s
| PSR_c
| PSR_x
},
18914 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18915 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18916 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18917 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18918 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18919 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18920 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18921 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18922 {"csf", PSR_c
| PSR_s
| PSR_f
},
18923 {"csx", PSR_c
| PSR_s
| PSR_x
},
18924 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18925 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18926 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18927 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18928 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18929 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18930 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18931 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18932 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18933 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18934 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18935 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18936 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18937 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18938 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18939 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18940 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18941 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18942 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18943 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18944 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18945 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18946 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18947 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18948 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18949 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18952 /* Table of V7M psr names. */
18953 static const struct asm_psr v7m_psrs
[] =
18955 {"apsr", 0x0 }, {"APSR", 0x0 },
18956 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18957 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18958 {"psr", 0x3 }, {"PSR", 0x3 },
18959 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18960 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18961 {"epsr", 0x6 }, {"EPSR", 0x6 },
18962 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18963 {"msp", 0x8 }, {"MSP", 0x8 },
18964 {"psp", 0x9 }, {"PSP", 0x9 },
18965 {"msplim", 0xa }, {"MSPLIM", 0xa },
18966 {"psplim", 0xb }, {"PSPLIM", 0xb },
18967 {"primask", 0x10}, {"PRIMASK", 0x10},
18968 {"basepri", 0x11}, {"BASEPRI", 0x11},
18969 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18970 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18971 {"control", 0x14}, {"CONTROL", 0x14},
18972 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18973 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18974 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18975 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18976 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18977 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18978 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18979 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18980 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18983 /* Table of all shift-in-operand names. */
18984 static const struct asm_shift_name shift_names
[] =
18986 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18987 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18988 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18989 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18990 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18991 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18994 /* Table of all explicit relocation names. */
18996 static struct reloc_entry reloc_names
[] =
18998 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18999 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19000 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19001 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19002 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19003 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19004 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19005 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19006 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19007 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19008 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19009 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19010 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19011 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19012 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19013 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19014 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19015 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19019 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19020 static const struct asm_cond conds
[] =
19024 {"cs", 0x2}, {"hs", 0x2},
19025 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19039 #define UL_BARRIER(L,U,CODE,FEAT) \
19040 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19041 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19043 static struct asm_barrier_opt barrier_opt_names
[] =
19045 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19046 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19047 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19048 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19049 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19050 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19051 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19052 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19053 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19054 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19055 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19056 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19057 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19058 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19059 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19060 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19065 /* Table of ARM-format instructions. */
19067 /* Macros for gluing together operand strings. N.B. In all cases
19068 other than OPS0, the trailing OP_stop comes from default
19069 zero-initialization of the unspecified elements of the array. */
19070 #define OPS0() { OP_stop, }
19071 #define OPS1(a) { OP_##a, }
19072 #define OPS2(a,b) { OP_##a,OP_##b, }
19073 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19074 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19075 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19076 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19078 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19079 This is useful when mixing operands for ARM and THUMB, i.e. using the
19080 MIX_ARM_THUMB_OPERANDS macro.
19081 In order to use these macros, prefix the number of operands with _
19083 #define OPS_1(a) { a, }
19084 #define OPS_2(a,b) { a,b, }
19085 #define OPS_3(a,b,c) { a,b,c, }
19086 #define OPS_4(a,b,c,d) { a,b,c,d, }
19087 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19088 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19090 /* These macros abstract out the exact format of the mnemonic table and
19091 save some repeated characters. */
19093 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19094 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19095 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19096 THUMB_VARIANT, do_##ae, do_##te }
19098 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19099 a T_MNEM_xyz enumerator. */
19100 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19101 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19102 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19103 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19105 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19106 infix after the third character. */
19107 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19108 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19109 THUMB_VARIANT, do_##ae, do_##te }
19110 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19111 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19112 THUMB_VARIANT, do_##ae, do_##te }
19113 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19114 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19115 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19116 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19117 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19118 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19119 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19120 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19122 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19123 field is still 0xE. Many of the Thumb variants can be executed
19124 conditionally, so this is checked separately. */
19125 #define TUE(mnem, op, top, nops, ops, ae, te) \
19126 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19127 THUMB_VARIANT, do_##ae, do_##te }
19129 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19130 Used by mnemonics that have very minimal differences in the encoding for
19131 ARM and Thumb variants and can be handled in a common function. */
19132 #define TUEc(mnem, op, top, nops, ops, en) \
19133 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19134 THUMB_VARIANT, do_##en, do_##en }
19136 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19137 condition code field. */
19138 #define TUF(mnem, op, top, nops, ops, ae, te) \
19139 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19140 THUMB_VARIANT, do_##ae, do_##te }
19142 /* ARM-only variants of all the above. */
19143 #define CE(mnem, op, nops, ops, ae) \
19144 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19146 #define C3(mnem, op, nops, ops, ae) \
19147 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19149 /* Legacy mnemonics that always have conditional infix after the third
19151 #define CL(mnem, op, nops, ops, ae) \
19152 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19153 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19155 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19156 #define cCE(mnem, op, nops, ops, ae) \
19157 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19159 /* Legacy coprocessor instructions where conditional infix and conditional
19160 suffix are ambiguous. For consistency this includes all FPA instructions,
19161 not just the potentially ambiguous ones. */
19162 #define cCL(mnem, op, nops, ops, ae) \
19163 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19164 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19166 /* Coprocessor, takes either a suffix or a position-3 infix
19167 (for an FPA corner case). */
19168 #define C3E(mnem, op, nops, ops, ae) \
19169 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19170 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19172 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19173 { m1 #m2 m3, OPS##nops ops, \
19174 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19175 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19177 #define CM(m1, m2, op, nops, ops, ae) \
19178 xCM_ (m1, , m2, op, nops, ops, ae), \
19179 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19180 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19181 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19182 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19183 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19184 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19185 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19186 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19187 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19188 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19189 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19190 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19191 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19192 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19193 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19194 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19195 xCM_ (m1, le, m2, op, nops, ops, ae), \
19196 xCM_ (m1, al, m2, op, nops, ops, ae)
19198 #define UE(mnem, op, nops, ops, ae) \
19199 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19201 #define UF(mnem, op, nops, ops, ae) \
19202 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19204 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19205 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19206 use the same encoding function for each. */
19207 #define NUF(mnem, op, nops, ops, enc) \
19208 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19209 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19211 /* Neon data processing, version which indirects through neon_enc_tab for
19212 the various overloaded versions of opcodes. */
19213 #define nUF(mnem, op, nops, ops, enc) \
19214 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19215 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19217 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19219 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19220 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19221 THUMB_VARIANT, do_##enc, do_##enc }
19223 #define NCE(mnem, op, nops, ops, enc) \
19224 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19226 #define NCEF(mnem, op, nops, ops, enc) \
19227 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19229 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19230 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19231 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19232 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19234 #define nCE(mnem, op, nops, ops, enc) \
19235 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19237 #define nCEF(mnem, op, nops, ops, enc) \
19238 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19242 static const struct asm_opcode insns
[] =
19244 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19245 #define THUMB_VARIANT & arm_ext_v4t
19246 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19247 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19248 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19249 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19250 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19251 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19252 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19253 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19254 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19255 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19256 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19257 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19258 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19259 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19260 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19261 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19263 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19264 for setting PSR flag bits. They are obsolete in V6 and do not
19265 have Thumb equivalents. */
19266 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19267 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19268 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19269 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19270 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19271 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19272 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19273 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19274 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19276 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19277 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19278 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19279 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19281 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19282 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19283 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19285 OP_ADDRGLDR
),ldst
, t_ldst
),
19286 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19288 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19289 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19290 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19291 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19292 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19293 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19295 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19296 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19297 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19298 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19301 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19302 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19303 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19304 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19306 /* Thumb-compatibility pseudo ops. */
19307 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19308 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19309 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19310 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19311 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19312 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19313 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19314 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19315 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19316 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19317 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19318 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19320 /* These may simplify to neg. */
19321 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19322 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19324 #undef THUMB_VARIANT
19325 #define THUMB_VARIANT & arm_ext_v6
19327 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19329 /* V1 instructions with no Thumb analogue prior to V6T2. */
19330 #undef THUMB_VARIANT
19331 #define THUMB_VARIANT & arm_ext_v6t2
19333 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19334 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19335 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19337 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19338 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19339 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19340 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19342 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19343 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19345 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19346 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19348 /* V1 instructions with no Thumb analogue at all. */
19349 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19350 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19352 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19353 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19354 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19355 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19356 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19357 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19358 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19359 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19362 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19363 #undef THUMB_VARIANT
19364 #define THUMB_VARIANT & arm_ext_v4t
19366 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19367 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19369 #undef THUMB_VARIANT
19370 #define THUMB_VARIANT & arm_ext_v6t2
19372 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19373 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19375 /* Generic coprocessor instructions. */
19376 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19377 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19378 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19379 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19380 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19381 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19382 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19385 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19387 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19388 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19391 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19392 #undef THUMB_VARIANT
19393 #define THUMB_VARIANT & arm_ext_msr
19395 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19396 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19399 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19400 #undef THUMB_VARIANT
19401 #define THUMB_VARIANT & arm_ext_v6t2
19403 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19404 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19405 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19406 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19407 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19408 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19409 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19410 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19413 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19414 #undef THUMB_VARIANT
19415 #define THUMB_VARIANT & arm_ext_v4t
19417 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19418 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19419 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19420 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19421 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19422 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19425 #define ARM_VARIANT & arm_ext_v4t_5
19427 /* ARM Architecture 4T. */
19428 /* Note: bx (and blx) are required on V5, even if the processor does
19429 not support Thumb. */
19430 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19433 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19434 #undef THUMB_VARIANT
19435 #define THUMB_VARIANT & arm_ext_v5t
19437 /* Note: blx has 2 variants; the .value coded here is for
19438 BLX(2). Only this variant has conditional execution. */
19439 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19440 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19442 #undef THUMB_VARIANT
19443 #define THUMB_VARIANT & arm_ext_v6t2
19445 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19446 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19447 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19448 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19449 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19450 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19451 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19452 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19455 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19456 #undef THUMB_VARIANT
19457 #define THUMB_VARIANT & arm_ext_v5exp
19459 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19460 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19461 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19462 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19464 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19465 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19467 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19468 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19469 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19470 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19472 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19473 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19474 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19475 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19477 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19478 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19480 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19481 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19482 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19483 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19486 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19487 #undef THUMB_VARIANT
19488 #define THUMB_VARIANT & arm_ext_v6t2
19490 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19491 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19493 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19494 ADDRGLDRS
), ldrd
, t_ldstd
),
19496 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19497 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19500 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19502 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19505 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19506 #undef THUMB_VARIANT
19507 #define THUMB_VARIANT & arm_ext_v6
19509 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19510 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19511 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19512 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19513 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19514 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19515 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19516 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19517 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19518 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19520 #undef THUMB_VARIANT
19521 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19523 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19524 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19526 #undef THUMB_VARIANT
19527 #define THUMB_VARIANT & arm_ext_v6t2
19529 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19530 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19532 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19533 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19535 /* ARM V6 not included in V7M. */
19536 #undef THUMB_VARIANT
19537 #define THUMB_VARIANT & arm_ext_v6_notm
19538 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19539 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19540 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19541 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19542 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19543 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19544 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19545 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19546 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19547 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19548 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19549 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19550 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19551 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19552 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19553 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19554 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19555 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19556 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19558 /* ARM V6 not included in V7M (eg. integer SIMD). */
19559 #undef THUMB_VARIANT
19560 #define THUMB_VARIANT & arm_ext_v6_dsp
19561 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19562 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19563 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19564 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19565 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19566 /* Old name for QASX. */
19567 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19569 /* Old name for QSAX. */
19570 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19571 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19572 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19573 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19574 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19576 /* Old name for SASX. */
19577 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19578 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19579 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19580 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 /* Old name for SHASX. */
19582 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19583 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 /* Old name for SHSAX. */
19585 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19586 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19587 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19588 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19589 /* Old name for SSAX. */
19590 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19591 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19592 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19593 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19594 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19595 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19596 /* Old name for UASX. */
19597 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19598 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19599 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19600 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19601 /* Old name for UHASX. */
19602 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19603 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19604 /* Old name for UHSAX. */
19605 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19606 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19607 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19608 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19609 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19610 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19611 /* Old name for UQASX. */
19612 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19613 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19614 /* Old name for UQSAX. */
19615 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19616 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19617 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19618 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19619 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19620 /* Old name for USAX. */
19621 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19622 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19623 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19624 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19625 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19626 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19627 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19628 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19629 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19630 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19631 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19632 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19633 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19634 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19635 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19636 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19637 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19638 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19639 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19640 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19641 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19642 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19643 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19644 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19645 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19646 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19647 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19648 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19649 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19650 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19651 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19652 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19653 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19654 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19657 #define ARM_VARIANT & arm_ext_v6k
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & arm_ext_v6k
19661 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19662 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19663 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19664 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19666 #undef THUMB_VARIANT
19667 #define THUMB_VARIANT & arm_ext_v6_notm
19668 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19670 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19671 RRnpcb
), strexd
, t_strexd
),
19673 #undef THUMB_VARIANT
19674 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19675 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19677 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19679 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19681 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19683 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19686 #define ARM_VARIANT & arm_ext_sec
19687 #undef THUMB_VARIANT
19688 #define THUMB_VARIANT & arm_ext_sec
19690 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19693 #define ARM_VARIANT & arm_ext_virt
19694 #undef THUMB_VARIANT
19695 #define THUMB_VARIANT & arm_ext_virt
19697 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19698 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19701 #define ARM_VARIANT & arm_ext_pan
19702 #undef THUMB_VARIANT
19703 #define THUMB_VARIANT & arm_ext_pan
19705 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19708 #define ARM_VARIANT & arm_ext_v6t2
19709 #undef THUMB_VARIANT
19710 #define THUMB_VARIANT & arm_ext_v6t2
19712 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19713 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19714 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19715 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19717 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19718 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19720 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19721 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19722 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19723 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19725 #undef THUMB_VARIANT
19726 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19727 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19728 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19730 /* Thumb-only instructions. */
19732 #define ARM_VARIANT NULL
19733 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19734 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19736 /* ARM does not really have an IT instruction, so always allow it.
19737 The opcode is copied from Thumb in order to allow warnings in
19738 -mimplicit-it=[never | arm] modes. */
19740 #define ARM_VARIANT & arm_ext_v1
19741 #undef THUMB_VARIANT
19742 #define THUMB_VARIANT & arm_ext_v6t2
19744 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19745 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19746 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19747 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19748 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19749 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19750 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19751 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19752 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19753 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19754 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19755 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19756 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19757 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19758 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19759 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19760 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19761 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19763 /* Thumb2 only instructions. */
19765 #define ARM_VARIANT NULL
19767 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19768 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19769 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19770 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19771 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19772 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19774 /* Hardware division instructions. */
19776 #define ARM_VARIANT & arm_ext_adiv
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_div
19780 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19781 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19783 /* ARM V6M/V7 instructions. */
19785 #define ARM_VARIANT & arm_ext_barrier
19786 #undef THUMB_VARIANT
19787 #define THUMB_VARIANT & arm_ext_barrier
19789 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19790 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19791 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19793 /* ARM V7 instructions. */
19795 #define ARM_VARIANT & arm_ext_v7
19796 #undef THUMB_VARIANT
19797 #define THUMB_VARIANT & arm_ext_v7
19799 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19800 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19803 #define ARM_VARIANT & arm_ext_mp
19804 #undef THUMB_VARIANT
19805 #define THUMB_VARIANT & arm_ext_mp
19807 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19809 /* AArchv8 instructions. */
19811 #define ARM_VARIANT & arm_ext_v8
19813 /* Instructions shared between armv8-a and armv8-m. */
19814 #undef THUMB_VARIANT
19815 #define THUMB_VARIANT & arm_ext_atomics
19817 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19818 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19819 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19820 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19821 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19822 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19823 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19824 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19825 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19826 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19828 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19830 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19832 #undef THUMB_VARIANT
19833 #define THUMB_VARIANT & arm_ext_v8
19835 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19836 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19837 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19839 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19841 /* ARMv8 T32 only. */
19843 #define ARM_VARIANT NULL
19844 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19845 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19846 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19848 /* FP for ARMv8. */
19850 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19851 #undef THUMB_VARIANT
19852 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19854 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19855 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19856 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19857 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19858 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19859 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19860 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19861 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19862 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19863 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19864 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19865 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19866 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19867 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19868 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19869 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19870 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19872 /* Crypto v1 extensions. */
19874 #define ARM_VARIANT & fpu_crypto_ext_armv8
19875 #undef THUMB_VARIANT
19876 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19878 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19879 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19880 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19881 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19882 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19883 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19884 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19885 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19886 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19887 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19888 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19889 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19890 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19891 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19894 #define ARM_VARIANT & crc_ext_armv8
19895 #undef THUMB_VARIANT
19896 #define THUMB_VARIANT & crc_ext_armv8
19897 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19898 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19899 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19900 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19901 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19902 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19904 /* ARMv8.2 RAS extension. */
19906 #define ARM_VARIANT & arm_ext_ras
19907 #undef THUMB_VARIANT
19908 #define THUMB_VARIANT & arm_ext_ras
19909 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19912 #define ARM_VARIANT & arm_ext_v8_3
19913 #undef THUMB_VARIANT
19914 #define THUMB_VARIANT & arm_ext_v8_3
19915 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19916 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19917 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19920 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19921 #undef THUMB_VARIANT
19922 #define THUMB_VARIANT NULL
19924 cCE("wfs", e200110
, 1, (RR
), rd
),
19925 cCE("rfs", e300110
, 1, (RR
), rd
),
19926 cCE("wfc", e400110
, 1, (RR
), rd
),
19927 cCE("rfc", e500110
, 1, (RR
), rd
),
19929 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19930 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19931 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19932 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19934 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19935 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19936 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19937 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19939 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20010 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20023 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20036 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20114 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20115 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20117 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20126 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20127 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20128 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20129 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20130 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20131 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20132 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20134 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20135 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20136 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20137 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20138 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20139 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20140 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20141 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20142 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20143 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20144 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20145 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20147 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20179 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20192 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20201 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20205 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20206 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20208 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20214 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20218 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20219 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20221 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20227 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20231 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20232 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20244 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20283 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20284 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20286 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20295 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20296 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20297 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20298 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20299 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20300 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20301 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20303 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20304 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20305 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20306 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20307 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20308 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20309 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20310 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20311 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20312 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20313 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20314 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20316 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20317 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20318 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20319 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20321 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20322 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20323 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20324 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20325 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20326 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20327 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20328 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20329 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20330 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20331 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20332 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20334 /* The implementation of the FIX instruction is broken on some
20335 assemblers, in that it accepts a precision specifier as well as a
20336 rounding specifier, despite the fact that this is meaningless.
20337 To be more compatible, we accept it as well, though of course it
20338 does not set any bits. */
20339 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20340 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20341 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20342 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20343 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20344 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20345 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20346 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20347 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20348 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20349 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20350 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20351 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20353 /* Instructions that were new with the real FPA, call them V2. */
20355 #define ARM_VARIANT & fpu_fpa_ext_v2
20357 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20358 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20359 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20360 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20361 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20362 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20365 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20367 /* Moves and type conversions. */
20368 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20369 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20370 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20371 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20372 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20373 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20374 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20375 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20376 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20377 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20378 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20379 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20380 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20381 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20383 /* Memory operations. */
20384 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20385 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20386 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20387 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20388 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20389 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20390 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20391 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20392 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20393 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20394 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20395 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20396 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20397 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20398 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20399 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20400 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20401 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20403 /* Monadic operations. */
20404 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20405 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20406 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20408 /* Dyadic operations. */
20409 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20410 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20411 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20412 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20413 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20414 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20415 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20416 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20417 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20420 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20421 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20422 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20423 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20425 /* Double precision load/store are still present on single precision
20426 implementations. */
20427 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20428 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20429 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20430 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20431 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20432 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20433 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20434 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20435 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20436 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20439 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20441 /* Moves and type conversions. */
20442 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20443 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20444 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20445 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20446 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20447 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20448 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20449 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20450 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20451 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20452 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20453 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20454 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20456 /* Monadic operations. */
20457 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20458 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20459 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20461 /* Dyadic operations. */
20462 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20463 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20464 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20465 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20466 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20467 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20468 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20469 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20470 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20473 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20474 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20475 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20476 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20479 #define ARM_VARIANT & fpu_vfp_ext_v2
20481 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20482 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20483 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20484 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20486 /* Instructions which may belong to either the Neon or VFP instruction sets.
20487 Individual encoder functions perform additional architecture checks. */
20489 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20490 #undef THUMB_VARIANT
20491 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20493 /* These mnemonics are unique to VFP. */
20494 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20495 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20496 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20497 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20498 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20499 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20500 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20501 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20502 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20503 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20505 /* Mnemonics shared by Neon and VFP. */
20506 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20507 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20508 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20510 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20511 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20513 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20514 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20516 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20517 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20518 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20519 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20520 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20521 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20522 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20523 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20525 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20526 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20527 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20528 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20531 /* NOTE: All VMOV encoding is special-cased! */
20532 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20533 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20536 #define ARM_VARIANT & arm_ext_fp16
20537 #undef THUMB_VARIANT
20538 #define THUMB_VARIANT & arm_ext_fp16
20539 /* New instructions added from v8.2, allowing the extraction and insertion of
20540 the upper 16 bits of a 32-bit vector register. */
20541 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20542 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20544 #undef THUMB_VARIANT
20545 #define THUMB_VARIANT & fpu_neon_ext_v1
20547 #define ARM_VARIANT & fpu_neon_ext_v1
20549 /* Data processing with three registers of the same length. */
20550 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20551 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20552 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20553 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20554 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20555 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20556 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20557 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20558 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20559 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20560 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20561 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20562 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20563 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20564 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20565 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20566 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20567 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20568 /* If not immediate, fall back to neon_dyadic_i64_su.
20569 shl_imm should accept I8 I16 I32 I64,
20570 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20571 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20572 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20573 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20574 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20575 /* Logic ops, types optional & ignored. */
20576 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20577 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20578 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20579 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20580 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20581 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20582 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20583 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20584 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20585 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20586 /* Bitfield ops, untyped. */
20587 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20588 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20589 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20590 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20591 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20592 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20593 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20594 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20595 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20596 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20597 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20598 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20599 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20600 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20601 back to neon_dyadic_if_su. */
20602 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20603 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20604 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20605 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20606 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20607 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20608 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20609 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20610 /* Comparison. Type I8 I16 I32 F32. */
20611 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20612 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20613 /* As above, D registers only. */
20614 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20615 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20616 /* Int and float variants, signedness unimportant. */
20617 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20618 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20619 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20620 /* Add/sub take types I8 I16 I32 I64 F32. */
20621 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20622 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20623 /* vtst takes sizes 8, 16, 32. */
20624 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20625 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20626 /* VMUL takes I8 I16 I32 F32 P8. */
20627 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20628 /* VQD{R}MULH takes S16 S32. */
20629 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20630 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20631 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20632 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20633 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20634 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20635 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20636 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20637 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20638 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20639 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20640 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20641 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20642 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20643 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20644 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20645 /* ARM v8.1 extension. */
20646 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20647 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20648 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20649 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20651 /* Two address, int/float. Types S8 S16 S32 F32. */
20652 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20653 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20655 /* Data processing with two registers and a shift amount. */
20656 /* Right shifts, and variants with rounding.
20657 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20658 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20659 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20660 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20661 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20662 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20663 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20664 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20665 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20666 /* Shift and insert. Sizes accepted 8 16 32 64. */
20667 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20668 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20669 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20670 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20671 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20672 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20673 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20674 /* Right shift immediate, saturating & narrowing, with rounding variants.
20675 Types accepted S16 S32 S64 U16 U32 U64. */
20676 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20677 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20678 /* As above, unsigned. Types accepted S16 S32 S64. */
20679 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20680 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20681 /* Right shift narrowing. Types accepted I16 I32 I64. */
20682 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20683 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20684 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20685 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20686 /* CVT with optional immediate for fixed-point variant. */
20687 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20689 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20690 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20692 /* Data processing, three registers of different lengths. */
20693 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20694 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20695 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20696 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20697 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20698 /* If not scalar, fall back to neon_dyadic_long.
20699 Vector types as above, scalar types S16 S32 U16 U32. */
20700 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20701 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20702 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20703 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20704 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20705 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20706 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20707 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20708 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20709 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20710 /* Saturating doubling multiplies. Types S16 S32. */
20711 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20712 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20713 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20714 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20715 S16 S32 U16 U32. */
20716 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20718 /* Extract. Size 8. */
20719 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20720 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20722 /* Two registers, miscellaneous. */
20723 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20724 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20725 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20726 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20727 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20728 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20729 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20730 /* Vector replicate. Sizes 8 16 32. */
20731 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20732 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20733 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20734 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20735 /* VMOVN. Types I16 I32 I64. */
20736 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20737 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20738 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20739 /* VQMOVUN. Types S16 S32 S64. */
20740 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20741 /* VZIP / VUZP. Sizes 8 16 32. */
20742 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20743 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20744 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20745 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20746 /* VQABS / VQNEG. Types S8 S16 S32. */
20747 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20748 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20749 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20750 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20751 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20752 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20753 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20754 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20755 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20756 /* Reciprocal estimates. Types U32 F16 F32. */
20757 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20758 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20759 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20760 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20761 /* VCLS. Types S8 S16 S32. */
20762 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20763 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20764 /* VCLZ. Types I8 I16 I32. */
20765 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20766 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20767 /* VCNT. Size 8. */
20768 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20769 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20770 /* Two address, untyped. */
20771 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20772 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20773 /* VTRN. Sizes 8 16 32. */
20774 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20775 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20777 /* Table lookup. Size 8. */
20778 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20779 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20781 #undef THUMB_VARIANT
20782 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20784 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20786 /* Neon element/structure load/store. */
20787 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20788 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20789 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20790 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20791 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20792 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20793 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20794 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20796 #undef THUMB_VARIANT
20797 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20799 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20800 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20801 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20802 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20803 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20804 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20805 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20806 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20807 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20808 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20810 #undef THUMB_VARIANT
20811 #define THUMB_VARIANT & fpu_vfp_ext_v3
20813 #define ARM_VARIANT & fpu_vfp_ext_v3
20815 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20816 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20817 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20818 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20819 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20820 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20821 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20822 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20823 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20826 #define ARM_VARIANT & fpu_vfp_ext_fma
20827 #undef THUMB_VARIANT
20828 #define THUMB_VARIANT & fpu_vfp_ext_fma
20829 /* Mnemonics shared by Neon and VFP. These are included in the
20830 VFP FMA variant; NEON and VFP FMA always includes the NEON
20831 FMA instructions. */
20832 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20833 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20834 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20835 the v form should always be used. */
20836 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20837 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20838 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20839 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20840 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20841 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20843 #undef THUMB_VARIANT
20845 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20847 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20848 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20849 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20850 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20851 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20852 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20853 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20854 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20857 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20859 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20860 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20861 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20862 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20863 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20864 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20865 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20866 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20867 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20868 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20869 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20870 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20871 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20872 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20873 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20874 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20875 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20876 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20877 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20878 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20879 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20880 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20881 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20882 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20883 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20884 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20885 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20886 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20887 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20888 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20889 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20890 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20891 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20892 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20893 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20894 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20895 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20896 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20906 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20924 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20926 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20927 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20928 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20929 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20939 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20940 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20941 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20942 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20943 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20944 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20945 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20946 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20947 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20948 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20949 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20950 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20951 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20952 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20953 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20954 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20955 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20956 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20957 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20958 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20959 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20960 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20961 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20962 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20963 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20964 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20965 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20966 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20967 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20968 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20969 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20970 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20971 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20972 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20973 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20974 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20975 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20976 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20977 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20978 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20979 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20980 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20981 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20982 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20983 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20984 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20985 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20986 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20987 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20988 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20989 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20990 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20991 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20992 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20993 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20994 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20995 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20997 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20999 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21002 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21003 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21004 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21005 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21006 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21007 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21008 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21009 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21010 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21011 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21012 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21013 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21014 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21015 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21016 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21023 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21025 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21026 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21027 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21028 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21029 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21030 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21031 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21046 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21050 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21051 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21056 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21057 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21058 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21059 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21060 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21061 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21062 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21063 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21064 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21065 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21066 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21067 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21068 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21069 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21070 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21071 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21072 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21073 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21074 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21075 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21076 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21077 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21078 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21079 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21080 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21081 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21084 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21086 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21087 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21088 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21089 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21090 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21091 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21092 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21093 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21094 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21095 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21096 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21097 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21098 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21099 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21100 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21101 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21102 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21103 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21104 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21105 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21106 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21107 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21108 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21109 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21110 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21111 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21112 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21113 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21114 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21115 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21116 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21117 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21118 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21119 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21120 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21121 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21122 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21123 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21124 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21125 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21126 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21127 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21128 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21129 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21130 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21131 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21132 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21133 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21134 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21135 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21136 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21137 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21138 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21139 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21140 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21141 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21142 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21143 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21144 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21145 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21146 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21147 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21148 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21149 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21150 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21151 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21152 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21153 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21154 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21155 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21156 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21157 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21158 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21159 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21160 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21161 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21163 /* ARMv8-M instructions. */
21165 #define ARM_VARIANT NULL
21166 #undef THUMB_VARIANT
21167 #define THUMB_VARIANT & arm_ext_v8m
21168 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21169 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21170 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21171 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21172 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21173 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21174 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21176 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21177 instructions behave as nop if no VFP is present. */
21178 #undef THUMB_VARIANT
21179 #define THUMB_VARIANT & arm_ext_v8m_main
21180 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21181 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21184 #undef THUMB_VARIANT
21210 /* MD interface: bits in the object file. */
21212 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21213 for use in the a.out file, and stores them in the array pointed to by buf.
21214 This knows about the endian-ness of the target machine and does
21215 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21216 2 (short) and 4 (long) Floating numbers are put out as a series of
21217 LITTLENUMS (shorts, here at least). */
21220 md_number_to_chars (char * buf
, valueT val
, int n
)
21222 if (target_big_endian
)
21223 number_to_chars_bigendian (buf
, val
, n
);
21225 number_to_chars_littleendian (buf
, val
, n
);
21229 md_chars_to_number (char * buf
, int n
)
21232 unsigned char * where
= (unsigned char *) buf
;
21234 if (target_big_endian
)
21239 result
|= (*where
++ & 255);
21247 result
|= (where
[n
] & 255);
21254 /* MD interface: Sections. */
21256 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21257 that an rs_machine_dependent frag may reach. */
21260 arm_frag_max_var (fragS
*fragp
)
21262 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21263 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21265 Note that we generate relaxable instructions even for cases that don't
21266 really need it, like an immediate that's a trivial constant. So we're
21267 overestimating the instruction size for some of those cases. Rather
21268 than putting more intelligence here, it would probably be better to
21269 avoid generating a relaxation frag in the first place when it can be
21270 determined up front that a short instruction will suffice. */
21272 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21276 /* Estimate the size of a frag before relaxing. Assume everything fits in
21280 md_estimate_size_before_relax (fragS
* fragp
,
21281 segT segtype ATTRIBUTE_UNUSED
)
21287 /* Convert a machine dependent frag. */
21290 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21292 unsigned long insn
;
21293 unsigned long old_op
;
21301 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21303 old_op
= bfd_get_16(abfd
, buf
);
21304 if (fragp
->fr_symbol
)
21306 exp
.X_op
= O_symbol
;
21307 exp
.X_add_symbol
= fragp
->fr_symbol
;
21311 exp
.X_op
= O_constant
;
21313 exp
.X_add_number
= fragp
->fr_offset
;
21314 opcode
= fragp
->fr_subtype
;
21317 case T_MNEM_ldr_pc
:
21318 case T_MNEM_ldr_pc2
:
21319 case T_MNEM_ldr_sp
:
21320 case T_MNEM_str_sp
:
21327 if (fragp
->fr_var
== 4)
21329 insn
= THUMB_OP32 (opcode
);
21330 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21332 insn
|= (old_op
& 0x700) << 4;
21336 insn
|= (old_op
& 7) << 12;
21337 insn
|= (old_op
& 0x38) << 13;
21339 insn
|= 0x00000c00;
21340 put_thumb32_insn (buf
, insn
);
21341 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21345 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21347 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21350 if (fragp
->fr_var
== 4)
21352 insn
= THUMB_OP32 (opcode
);
21353 insn
|= (old_op
& 0xf0) << 4;
21354 put_thumb32_insn (buf
, insn
);
21355 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21359 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21360 exp
.X_add_number
-= 4;
21368 if (fragp
->fr_var
== 4)
21370 int r0off
= (opcode
== T_MNEM_mov
21371 || opcode
== T_MNEM_movs
) ? 0 : 8;
21372 insn
= THUMB_OP32 (opcode
);
21373 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21374 insn
|= (old_op
& 0x700) << r0off
;
21375 put_thumb32_insn (buf
, insn
);
21376 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21380 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21385 if (fragp
->fr_var
== 4)
21387 insn
= THUMB_OP32(opcode
);
21388 put_thumb32_insn (buf
, insn
);
21389 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21392 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21396 if (fragp
->fr_var
== 4)
21398 insn
= THUMB_OP32(opcode
);
21399 insn
|= (old_op
& 0xf00) << 14;
21400 put_thumb32_insn (buf
, insn
);
21401 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21404 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21407 case T_MNEM_add_sp
:
21408 case T_MNEM_add_pc
:
21409 case T_MNEM_inc_sp
:
21410 case T_MNEM_dec_sp
:
21411 if (fragp
->fr_var
== 4)
21413 /* ??? Choose between add and addw. */
21414 insn
= THUMB_OP32 (opcode
);
21415 insn
|= (old_op
& 0xf0) << 4;
21416 put_thumb32_insn (buf
, insn
);
21417 if (opcode
== T_MNEM_add_pc
)
21418 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21420 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21423 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21431 if (fragp
->fr_var
== 4)
21433 insn
= THUMB_OP32 (opcode
);
21434 insn
|= (old_op
& 0xf0) << 4;
21435 insn
|= (old_op
& 0xf) << 16;
21436 put_thumb32_insn (buf
, insn
);
21437 if (insn
& (1 << 20))
21438 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21440 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21443 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21449 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21450 (enum bfd_reloc_code_real
) reloc_type
);
21451 fixp
->fx_file
= fragp
->fr_file
;
21452 fixp
->fx_line
= fragp
->fr_line
;
21453 fragp
->fr_fix
+= fragp
->fr_var
;
21455 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21456 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21457 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21458 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21461 /* Return the size of a relaxable immediate operand instruction.
21462 SHIFT and SIZE specify the form of the allowable immediate. */
21464 relax_immediate (fragS
*fragp
, int size
, int shift
)
21470 /* ??? Should be able to do better than this. */
21471 if (fragp
->fr_symbol
)
21474 low
= (1 << shift
) - 1;
21475 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21476 offset
= fragp
->fr_offset
;
21477 /* Force misaligned offsets to 32-bit variant. */
21480 if (offset
& ~mask
)
21485 /* Get the address of a symbol during relaxation. */
21487 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21493 sym
= fragp
->fr_symbol
;
21494 sym_frag
= symbol_get_frag (sym
);
21495 know (S_GET_SEGMENT (sym
) != absolute_section
21496 || sym_frag
== &zero_address_frag
);
21497 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21499 /* If frag has yet to be reached on this pass, assume it will
21500 move by STRETCH just as we did. If this is not so, it will
21501 be because some frag between grows, and that will force
21505 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21509 /* Adjust stretch for any alignment frag. Note that if have
21510 been expanding the earlier code, the symbol may be
21511 defined in what appears to be an earlier frag. FIXME:
21512 This doesn't handle the fr_subtype field, which specifies
21513 a maximum number of bytes to skip when doing an
21515 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21517 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21520 stretch
= - ((- stretch
)
21521 & ~ ((1 << (int) f
->fr_offset
) - 1));
21523 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21535 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21538 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21543 /* Assume worst case for symbols not known to be in the same section. */
21544 if (fragp
->fr_symbol
== NULL
21545 || !S_IS_DEFINED (fragp
->fr_symbol
)
21546 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21547 || S_IS_WEAK (fragp
->fr_symbol
))
21550 val
= relaxed_symbol_addr (fragp
, stretch
);
21551 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21552 addr
= (addr
+ 4) & ~3;
21553 /* Force misaligned targets to 32-bit variant. */
21557 if (val
< 0 || val
> 1020)
21562 /* Return the size of a relaxable add/sub immediate instruction. */
21564 relax_addsub (fragS
*fragp
, asection
*sec
)
21569 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21570 op
= bfd_get_16(sec
->owner
, buf
);
21571 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21572 return relax_immediate (fragp
, 8, 0);
21574 return relax_immediate (fragp
, 3, 0);
21577 /* Return TRUE iff the definition of symbol S could be pre-empted
21578 (overridden) at link or load time. */
21580 symbol_preemptible (symbolS
*s
)
21582 /* Weak symbols can always be pre-empted. */
21586 /* Non-global symbols cannot be pre-empted. */
21587 if (! S_IS_EXTERNAL (s
))
21591 /* In ELF, a global symbol can be marked protected, or private. In that
21592 case it can't be pre-empted (other definitions in the same link unit
21593 would violate the ODR). */
21594 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21598 /* Other global symbols might be pre-empted. */
21602 /* Return the size of a relaxable branch instruction. BITS is the
21603 size of the offset field in the narrow instruction. */
21606 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21612 /* Assume worst case for symbols not known to be in the same section. */
21613 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21614 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21615 || S_IS_WEAK (fragp
->fr_symbol
))
21619 /* A branch to a function in ARM state will require interworking. */
21620 if (S_IS_DEFINED (fragp
->fr_symbol
)
21621 && ARM_IS_FUNC (fragp
->fr_symbol
))
21625 if (symbol_preemptible (fragp
->fr_symbol
))
21628 val
= relaxed_symbol_addr (fragp
, stretch
);
21629 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21632 /* Offset is a signed value *2 */
21634 if (val
>= limit
|| val
< -limit
)
21640 /* Relax a machine dependent frag. This returns the amount by which
21641 the current size of the frag should change. */
21644 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21649 oldsize
= fragp
->fr_var
;
21650 switch (fragp
->fr_subtype
)
21652 case T_MNEM_ldr_pc2
:
21653 newsize
= relax_adr (fragp
, sec
, stretch
);
21655 case T_MNEM_ldr_pc
:
21656 case T_MNEM_ldr_sp
:
21657 case T_MNEM_str_sp
:
21658 newsize
= relax_immediate (fragp
, 8, 2);
21662 newsize
= relax_immediate (fragp
, 5, 2);
21666 newsize
= relax_immediate (fragp
, 5, 1);
21670 newsize
= relax_immediate (fragp
, 5, 0);
21673 newsize
= relax_adr (fragp
, sec
, stretch
);
21679 newsize
= relax_immediate (fragp
, 8, 0);
21682 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21685 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21687 case T_MNEM_add_sp
:
21688 case T_MNEM_add_pc
:
21689 newsize
= relax_immediate (fragp
, 8, 2);
21691 case T_MNEM_inc_sp
:
21692 case T_MNEM_dec_sp
:
21693 newsize
= relax_immediate (fragp
, 7, 2);
21699 newsize
= relax_addsub (fragp
, sec
);
21705 fragp
->fr_var
= newsize
;
21706 /* Freeze wide instructions that are at or before the same location as
21707 in the previous pass. This avoids infinite loops.
21708 Don't freeze them unconditionally because targets may be artificially
21709 misaligned by the expansion of preceding frags. */
21710 if (stretch
<= 0 && newsize
> 2)
21712 md_convert_frag (sec
->owner
, sec
, fragp
);
21716 return newsize
- oldsize
;
21719 /* Round up a section size to the appropriate boundary. */
21722 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21725 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21726 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21728 /* For a.out, force the section size to be aligned. If we don't do
21729 this, BFD will align it for us, but it will not write out the
21730 final bytes of the section. This may be a bug in BFD, but it is
21731 easier to fix it here since that is how the other a.out targets
21735 align
= bfd_get_section_alignment (stdoutput
, segment
);
21736 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21743 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21744 of an rs_align_code fragment. */
21747 arm_handle_align (fragS
* fragP
)
21749 static unsigned char const arm_noop
[2][2][4] =
21752 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21753 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21756 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21757 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21760 static unsigned char const thumb_noop
[2][2][2] =
21763 {0xc0, 0x46}, /* LE */
21764 {0x46, 0xc0}, /* BE */
21767 {0x00, 0xbf}, /* LE */
21768 {0xbf, 0x00} /* BE */
21771 static unsigned char const wide_thumb_noop
[2][4] =
21772 { /* Wide Thumb-2 */
21773 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21774 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21777 unsigned bytes
, fix
, noop_size
;
21779 const unsigned char * noop
;
21780 const unsigned char *narrow_noop
= NULL
;
21785 if (fragP
->fr_type
!= rs_align_code
)
21788 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21789 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21792 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21793 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21795 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21797 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21799 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21800 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21802 narrow_noop
= thumb_noop
[1][target_big_endian
];
21803 noop
= wide_thumb_noop
[target_big_endian
];
21806 noop
= thumb_noop
[0][target_big_endian
];
21814 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21815 ? selected_cpu
: arm_arch_none
,
21817 [target_big_endian
];
21824 fragP
->fr_var
= noop_size
;
21826 if (bytes
& (noop_size
- 1))
21828 fix
= bytes
& (noop_size
- 1);
21830 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21832 memset (p
, 0, fix
);
21839 if (bytes
& noop_size
)
21841 /* Insert a narrow noop. */
21842 memcpy (p
, narrow_noop
, noop_size
);
21844 bytes
-= noop_size
;
21848 /* Use wide noops for the remainder */
21852 while (bytes
>= noop_size
)
21854 memcpy (p
, noop
, noop_size
);
21856 bytes
-= noop_size
;
21860 fragP
->fr_fix
+= fix
;
21863 /* Called from md_do_align. Used to create an alignment
21864 frag in a code section. */
21867 arm_frag_align_code (int n
, int max
)
21871 /* We assume that there will never be a requirement
21872 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21873 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21878 _("alignments greater than %d bytes not supported in .text sections."),
21879 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21880 as_fatal ("%s", err_msg
);
21883 p
= frag_var (rs_align_code
,
21884 MAX_MEM_FOR_RS_ALIGN_CODE
,
21886 (relax_substateT
) max
,
21893 /* Perform target specific initialisation of a frag.
21894 Note - despite the name this initialisation is not done when the frag
21895 is created, but only when its type is assigned. A frag can be created
21896 and used a long time before its type is set, so beware of assuming that
21897 this initialisation is performed first. */
21901 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21903 /* Record whether this frag is in an ARM or a THUMB area. */
21904 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21907 #else /* OBJ_ELF is defined. */
21909 arm_init_frag (fragS
* fragP
, int max_chars
)
21911 int frag_thumb_mode
;
21913 /* If the current ARM vs THUMB mode has not already
21914 been recorded into this frag then do so now. */
21915 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21916 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21918 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21920 /* Record a mapping symbol for alignment frags. We will delete this
21921 later if the alignment ends up empty. */
21922 switch (fragP
->fr_type
)
21925 case rs_align_test
:
21927 mapping_state_2 (MAP_DATA
, max_chars
);
21929 case rs_align_code
:
21930 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21937 /* When we change sections we need to issue a new mapping symbol. */
21940 arm_elf_change_section (void)
21942 /* Link an unlinked unwind index table section to the .text section. */
21943 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21944 && elf_linked_to_section (now_seg
) == NULL
)
21945 elf_linked_to_section (now_seg
) = text_section
;
21949 arm_elf_section_type (const char * str
, size_t len
)
21951 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21952 return SHT_ARM_EXIDX
;
21957 /* Code to deal with unwinding tables. */
21959 static void add_unwind_adjustsp (offsetT
);
21961 /* Generate any deferred unwind frame offset. */
21964 flush_pending_unwind (void)
21968 offset
= unwind
.pending_offset
;
21969 unwind
.pending_offset
= 0;
21971 add_unwind_adjustsp (offset
);
21974 /* Add an opcode to this list for this function. Two-byte opcodes should
21975 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21979 add_unwind_opcode (valueT op
, int length
)
21981 /* Add any deferred stack adjustment. */
21982 if (unwind
.pending_offset
)
21983 flush_pending_unwind ();
21985 unwind
.sp_restored
= 0;
21987 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21989 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21990 if (unwind
.opcodes
)
21991 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21992 unwind
.opcode_alloc
);
21994 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21999 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22001 unwind
.opcode_count
++;
22005 /* Add unwind opcodes to adjust the stack pointer. */
22008 add_unwind_adjustsp (offsetT offset
)
22012 if (offset
> 0x200)
22014 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22019 /* Long form: 0xb2, uleb128. */
22020 /* This might not fit in a word so add the individual bytes,
22021 remembering the list is built in reverse order. */
22022 o
= (valueT
) ((offset
- 0x204) >> 2);
22024 add_unwind_opcode (0, 1);
22026 /* Calculate the uleb128 encoding of the offset. */
22030 bytes
[n
] = o
& 0x7f;
22036 /* Add the insn. */
22038 add_unwind_opcode (bytes
[n
- 1], 1);
22039 add_unwind_opcode (0xb2, 1);
22041 else if (offset
> 0x100)
22043 /* Two short opcodes. */
22044 add_unwind_opcode (0x3f, 1);
22045 op
= (offset
- 0x104) >> 2;
22046 add_unwind_opcode (op
, 1);
22048 else if (offset
> 0)
22050 /* Short opcode. */
22051 op
= (offset
- 4) >> 2;
22052 add_unwind_opcode (op
, 1);
22054 else if (offset
< 0)
22057 while (offset
> 0x100)
22059 add_unwind_opcode (0x7f, 1);
22062 op
= ((offset
- 4) >> 2) | 0x40;
22063 add_unwind_opcode (op
, 1);
22067 /* Finish the list of unwind opcodes for this function. */
22069 finish_unwind_opcodes (void)
22073 if (unwind
.fp_used
)
22075 /* Adjust sp as necessary. */
22076 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22077 flush_pending_unwind ();
22079 /* After restoring sp from the frame pointer. */
22080 op
= 0x90 | unwind
.fp_reg
;
22081 add_unwind_opcode (op
, 1);
22084 flush_pending_unwind ();
22088 /* Start an exception table entry. If idx is nonzero this is an index table
22092 start_unwind_section (const segT text_seg
, int idx
)
22094 const char * text_name
;
22095 const char * prefix
;
22096 const char * prefix_once
;
22097 const char * group_name
;
22105 prefix
= ELF_STRING_ARM_unwind
;
22106 prefix_once
= ELF_STRING_ARM_unwind_once
;
22107 type
= SHT_ARM_EXIDX
;
22111 prefix
= ELF_STRING_ARM_unwind_info
;
22112 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22113 type
= SHT_PROGBITS
;
22116 text_name
= segment_name (text_seg
);
22117 if (streq (text_name
, ".text"))
22120 if (strncmp (text_name
, ".gnu.linkonce.t.",
22121 strlen (".gnu.linkonce.t.")) == 0)
22123 prefix
= prefix_once
;
22124 text_name
+= strlen (".gnu.linkonce.t.");
22127 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22133 /* Handle COMDAT group. */
22134 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22136 group_name
= elf_group_name (text_seg
);
22137 if (group_name
== NULL
)
22139 as_bad (_("Group section `%s' has no group signature"),
22140 segment_name (text_seg
));
22141 ignore_rest_of_line ();
22144 flags
|= SHF_GROUP
;
22148 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22151 /* Set the section link for index tables. */
22153 elf_linked_to_section (now_seg
) = text_seg
;
22157 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22158 personality routine data. Returns zero, or the index table value for
22159 an inline entry. */
22162 create_unwind_entry (int have_data
)
22167 /* The current word of data. */
22169 /* The number of bytes left in this word. */
22172 finish_unwind_opcodes ();
22174 /* Remember the current text section. */
22175 unwind
.saved_seg
= now_seg
;
22176 unwind
.saved_subseg
= now_subseg
;
22178 start_unwind_section (now_seg
, 0);
22180 if (unwind
.personality_routine
== NULL
)
22182 if (unwind
.personality_index
== -2)
22185 as_bad (_("handlerdata in cantunwind frame"));
22186 return 1; /* EXIDX_CANTUNWIND. */
22189 /* Use a default personality routine if none is specified. */
22190 if (unwind
.personality_index
== -1)
22192 if (unwind
.opcode_count
> 3)
22193 unwind
.personality_index
= 1;
22195 unwind
.personality_index
= 0;
22198 /* Space for the personality routine entry. */
22199 if (unwind
.personality_index
== 0)
22201 if (unwind
.opcode_count
> 3)
22202 as_bad (_("too many unwind opcodes for personality routine 0"));
22206 /* All the data is inline in the index table. */
22209 while (unwind
.opcode_count
> 0)
22211 unwind
.opcode_count
--;
22212 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22216 /* Pad with "finish" opcodes. */
22218 data
= (data
<< 8) | 0xb0;
22225 /* We get two opcodes "free" in the first word. */
22226 size
= unwind
.opcode_count
- 2;
22230 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22231 if (unwind
.personality_index
!= -1)
22233 as_bad (_("attempt to recreate an unwind entry"));
22237 /* An extra byte is required for the opcode count. */
22238 size
= unwind
.opcode_count
+ 1;
22241 size
= (size
+ 3) >> 2;
22243 as_bad (_("too many unwind opcodes"));
22245 frag_align (2, 0, 0);
22246 record_alignment (now_seg
, 2);
22247 unwind
.table_entry
= expr_build_dot ();
22249 /* Allocate the table entry. */
22250 ptr
= frag_more ((size
<< 2) + 4);
22251 /* PR 13449: Zero the table entries in case some of them are not used. */
22252 memset (ptr
, 0, (size
<< 2) + 4);
22253 where
= frag_now_fix () - ((size
<< 2) + 4);
22255 switch (unwind
.personality_index
)
22258 /* ??? Should this be a PLT generating relocation? */
22259 /* Custom personality routine. */
22260 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22261 BFD_RELOC_ARM_PREL31
);
22266 /* Set the first byte to the number of additional words. */
22267 data
= size
> 0 ? size
- 1 : 0;
22271 /* ABI defined personality routines. */
22273 /* Three opcodes bytes are packed into the first word. */
22280 /* The size and first two opcode bytes go in the first word. */
22281 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22286 /* Should never happen. */
22290 /* Pack the opcodes into words (MSB first), reversing the list at the same
22292 while (unwind
.opcode_count
> 0)
22296 md_number_to_chars (ptr
, data
, 4);
22301 unwind
.opcode_count
--;
22303 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22306 /* Finish off the last word. */
22309 /* Pad with "finish" opcodes. */
22311 data
= (data
<< 8) | 0xb0;
22313 md_number_to_chars (ptr
, data
, 4);
22318 /* Add an empty descriptor if there is no user-specified data. */
22319 ptr
= frag_more (4);
22320 md_number_to_chars (ptr
, 0, 4);
22327 /* Initialize the DWARF-2 unwind information for this procedure. */
22330 tc_arm_frame_initial_instructions (void)
22332 cfi_add_CFA_def_cfa (REG_SP
, 0);
22334 #endif /* OBJ_ELF */
22336 /* Convert REGNAME to a DWARF-2 register number. */
22339 tc_arm_regname_to_dw2regnum (char *regname
)
22341 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22345 /* PR 16694: Allow VFP registers as well. */
22346 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22350 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22359 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22363 exp
.X_op
= O_secrel
;
22364 exp
.X_add_symbol
= symbol
;
22365 exp
.X_add_number
= 0;
22366 emit_expr (&exp
, size
);
22370 /* MD interface: Symbol and relocation handling. */
22372 /* Return the address within the segment that a PC-relative fixup is
22373 relative to. For ARM, PC-relative fixups applied to instructions
22374 are generally relative to the location of the fixup plus 8 bytes.
22375 Thumb branches are offset by 4, and Thumb loads relative to PC
22376 require special handling. */
22379 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22381 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22383 /* If this is pc-relative and we are going to emit a relocation
22384 then we just want to put out any pipeline compensation that the linker
22385 will need. Otherwise we want to use the calculated base.
22386 For WinCE we skip the bias for externals as well, since this
22387 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22389 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22390 || (arm_force_relocation (fixP
)
22392 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22398 switch (fixP
->fx_r_type
)
22400 /* PC relative addressing on the Thumb is slightly odd as the
22401 bottom two bits of the PC are forced to zero for the
22402 calculation. This happens *after* application of the
22403 pipeline offset. However, Thumb adrl already adjusts for
22404 this, so we need not do it again. */
22405 case BFD_RELOC_ARM_THUMB_ADD
:
22408 case BFD_RELOC_ARM_THUMB_OFFSET
:
22409 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22410 case BFD_RELOC_ARM_T32_ADD_PC12
:
22411 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22412 return (base
+ 4) & ~3;
22414 /* Thumb branches are simply offset by +4. */
22415 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22416 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22417 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22418 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22419 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22422 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22424 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22425 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22426 && ARM_IS_FUNC (fixP
->fx_addsy
)
22427 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22428 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22431 /* BLX is like branches above, but forces the low two bits of PC to
22433 case BFD_RELOC_THUMB_PCREL_BLX
:
22435 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22436 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22437 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22438 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22439 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22440 return (base
+ 4) & ~3;
22442 /* ARM mode branches are offset by +8. However, the Windows CE
22443 loader expects the relocation not to take this into account. */
22444 case BFD_RELOC_ARM_PCREL_BLX
:
22446 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22447 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22448 && ARM_IS_FUNC (fixP
->fx_addsy
)
22449 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22450 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22453 case BFD_RELOC_ARM_PCREL_CALL
:
22455 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22456 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22457 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22458 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22459 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22462 case BFD_RELOC_ARM_PCREL_BRANCH
:
22463 case BFD_RELOC_ARM_PCREL_JUMP
:
22464 case BFD_RELOC_ARM_PLT32
:
22466 /* When handling fixups immediately, because we have already
22467 discovered the value of a symbol, or the address of the frag involved
22468 we must account for the offset by +8, as the OS loader will never see the reloc.
22469 see fixup_segment() in write.c
22470 The S_IS_EXTERNAL test handles the case of global symbols.
22471 Those need the calculated base, not just the pipe compensation the linker will need. */
22473 && fixP
->fx_addsy
!= NULL
22474 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22475 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22483 /* ARM mode loads relative to PC are also offset by +8. Unlike
22484 branches, the Windows CE loader *does* expect the relocation
22485 to take this into account. */
22486 case BFD_RELOC_ARM_OFFSET_IMM
:
22487 case BFD_RELOC_ARM_OFFSET_IMM8
:
22488 case BFD_RELOC_ARM_HWLITERAL
:
22489 case BFD_RELOC_ARM_LITERAL
:
22490 case BFD_RELOC_ARM_CP_OFF_IMM
:
22494 /* Other PC-relative relocations are un-offset. */
22500 static bfd_boolean flag_warn_syms
= TRUE
;
22503 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22505 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22506 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22507 does mean that the resulting code might be very confusing to the reader.
22508 Also this warning can be triggered if the user omits an operand before
22509 an immediate address, eg:
22513 GAS treats this as an assignment of the value of the symbol foo to a
22514 symbol LDR, and so (without this code) it will not issue any kind of
22515 warning or error message.
22517 Note - ARM instructions are case-insensitive but the strings in the hash
22518 table are all stored in lower case, so we must first ensure that name is
22520 if (flag_warn_syms
&& arm_ops_hsh
)
22522 char * nbuf
= strdup (name
);
22525 for (p
= nbuf
; *p
; p
++)
22527 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22529 static struct hash_control
* already_warned
= NULL
;
22531 if (already_warned
== NULL
)
22532 already_warned
= hash_new ();
22533 /* Only warn about the symbol once. To keep the code
22534 simple we let hash_insert do the lookup for us. */
22535 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22536 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22545 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22546 Otherwise we have no need to default values of symbols. */
22549 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22552 if (name
[0] == '_' && name
[1] == 'G'
22553 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22557 if (symbol_find (name
))
22558 as_bad (_("GOT already in the symbol table"));
22560 GOT_symbol
= symbol_new (name
, undefined_section
,
22561 (valueT
) 0, & zero_address_frag
);
22571 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22572 computed as two separate immediate values, added together. We
22573 already know that this value cannot be computed by just one ARM
22576 static unsigned int
22577 validate_immediate_twopart (unsigned int val
,
22578 unsigned int * highpart
)
22583 for (i
= 0; i
< 32; i
+= 2)
22584 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22590 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22592 else if (a
& 0xff0000)
22594 if (a
& 0xff000000)
22596 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22600 gas_assert (a
& 0xff000000);
22601 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22604 return (a
& 0xff) | (i
<< 7);
22611 validate_offset_imm (unsigned int val
, int hwse
)
22613 if ((hwse
&& val
> 255) || val
> 4095)
22618 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22619 negative immediate constant by altering the instruction. A bit of
22624 by inverting the second operand, and
22627 by negating the second operand. */
22630 negate_data_op (unsigned long * instruction
,
22631 unsigned long value
)
22634 unsigned long negated
, inverted
;
22636 negated
= encode_arm_immediate (-value
);
22637 inverted
= encode_arm_immediate (~value
);
22639 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22642 /* First negates. */
22643 case OPCODE_SUB
: /* ADD <-> SUB */
22644 new_inst
= OPCODE_ADD
;
22649 new_inst
= OPCODE_SUB
;
22653 case OPCODE_CMP
: /* CMP <-> CMN */
22654 new_inst
= OPCODE_CMN
;
22659 new_inst
= OPCODE_CMP
;
22663 /* Now Inverted ops. */
22664 case OPCODE_MOV
: /* MOV <-> MVN */
22665 new_inst
= OPCODE_MVN
;
22670 new_inst
= OPCODE_MOV
;
22674 case OPCODE_AND
: /* AND <-> BIC */
22675 new_inst
= OPCODE_BIC
;
22680 new_inst
= OPCODE_AND
;
22684 case OPCODE_ADC
: /* ADC <-> SBC */
22685 new_inst
= OPCODE_SBC
;
22690 new_inst
= OPCODE_ADC
;
22694 /* We cannot do anything. */
22699 if (value
== (unsigned) FAIL
)
22702 *instruction
&= OPCODE_MASK
;
22703 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22707 /* Like negate_data_op, but for Thumb-2. */
22709 static unsigned int
22710 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22714 unsigned int negated
, inverted
;
22716 negated
= encode_thumb32_immediate (-value
);
22717 inverted
= encode_thumb32_immediate (~value
);
22719 rd
= (*instruction
>> 8) & 0xf;
22720 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22723 /* ADD <-> SUB. Includes CMP <-> CMN. */
22724 case T2_OPCODE_SUB
:
22725 new_inst
= T2_OPCODE_ADD
;
22729 case T2_OPCODE_ADD
:
22730 new_inst
= T2_OPCODE_SUB
;
22734 /* ORR <-> ORN. Includes MOV <-> MVN. */
22735 case T2_OPCODE_ORR
:
22736 new_inst
= T2_OPCODE_ORN
;
22740 case T2_OPCODE_ORN
:
22741 new_inst
= T2_OPCODE_ORR
;
22745 /* AND <-> BIC. TST has no inverted equivalent. */
22746 case T2_OPCODE_AND
:
22747 new_inst
= T2_OPCODE_BIC
;
22754 case T2_OPCODE_BIC
:
22755 new_inst
= T2_OPCODE_AND
;
22760 case T2_OPCODE_ADC
:
22761 new_inst
= T2_OPCODE_SBC
;
22765 case T2_OPCODE_SBC
:
22766 new_inst
= T2_OPCODE_ADC
;
22770 /* We cannot do anything. */
22775 if (value
== (unsigned int)FAIL
)
22778 *instruction
&= T2_OPCODE_MASK
;
22779 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22783 /* Read a 32-bit thumb instruction from buf. */
22784 static unsigned long
22785 get_thumb32_insn (char * buf
)
22787 unsigned long insn
;
22788 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22789 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22795 /* We usually want to set the low bit on the address of thumb function
22796 symbols. In particular .word foo - . should have the low bit set.
22797 Generic code tries to fold the difference of two symbols to
22798 a constant. Prevent this and force a relocation when the first symbols
22799 is a thumb function. */
22802 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22804 if (op
== O_subtract
22805 && l
->X_op
== O_symbol
22806 && r
->X_op
== O_symbol
22807 && THUMB_IS_FUNC (l
->X_add_symbol
))
22809 l
->X_op
= O_subtract
;
22810 l
->X_op_symbol
= r
->X_add_symbol
;
22811 l
->X_add_number
-= r
->X_add_number
;
22815 /* Process as normal. */
22819 /* Encode Thumb2 unconditional branches and calls. The encoding
22820 for the 2 are identical for the immediate values. */
22823 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22825 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22828 addressT S
, I1
, I2
, lo
, hi
;
22830 S
= (value
>> 24) & 0x01;
22831 I1
= (value
>> 23) & 0x01;
22832 I2
= (value
>> 22) & 0x01;
22833 hi
= (value
>> 12) & 0x3ff;
22834 lo
= (value
>> 1) & 0x7ff;
22835 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22836 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22837 newval
|= (S
<< 10) | hi
;
22838 newval2
&= ~T2I1I2MASK
;
22839 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22840 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22841 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22845 md_apply_fix (fixS
* fixP
,
22849 offsetT value
= * valP
;
22851 unsigned int newimm
;
22852 unsigned long temp
;
22854 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22856 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22858 /* Note whether this will delete the relocation. */
22860 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22863 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22864 consistency with the behaviour on 32-bit hosts. Remember value
22866 value
&= 0xffffffff;
22867 value
^= 0x80000000;
22868 value
-= 0x80000000;
22871 fixP
->fx_addnumber
= value
;
22873 /* Same treatment for fixP->fx_offset. */
22874 fixP
->fx_offset
&= 0xffffffff;
22875 fixP
->fx_offset
^= 0x80000000;
22876 fixP
->fx_offset
-= 0x80000000;
22878 switch (fixP
->fx_r_type
)
22880 case BFD_RELOC_NONE
:
22881 /* This will need to go in the object file. */
22885 case BFD_RELOC_ARM_IMMEDIATE
:
22886 /* We claim that this fixup has been processed here,
22887 even if in fact we generate an error because we do
22888 not have a reloc for it, so tc_gen_reloc will reject it. */
22891 if (fixP
->fx_addsy
)
22893 const char *msg
= 0;
22895 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22896 msg
= _("undefined symbol %s used as an immediate value");
22897 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22898 msg
= _("symbol %s is in a different section");
22899 else if (S_IS_WEAK (fixP
->fx_addsy
))
22900 msg
= _("symbol %s is weak and may be overridden later");
22904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22905 msg
, S_GET_NAME (fixP
->fx_addsy
));
22910 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22912 /* If the offset is negative, we should use encoding A2 for ADR. */
22913 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22914 newimm
= negate_data_op (&temp
, value
);
22917 newimm
= encode_arm_immediate (value
);
22919 /* If the instruction will fail, see if we can fix things up by
22920 changing the opcode. */
22921 if (newimm
== (unsigned int) FAIL
)
22922 newimm
= negate_data_op (&temp
, value
);
22923 /* MOV accepts both ARM modified immediate (A1 encoding) and
22924 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22925 When disassembling, MOV is preferred when there is no encoding
22927 if (newimm
== (unsigned int) FAIL
22928 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22929 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22930 && !((temp
>> SBIT_SHIFT
) & 0x1)
22931 && value
>= 0 && value
<= 0xffff)
22933 /* Clear bits[23:20] to change encoding from A1 to A2. */
22934 temp
&= 0xff0fffff;
22935 /* Encoding high 4bits imm. Code below will encode the remaining
22937 temp
|= (value
& 0x0000f000) << 4;
22938 newimm
= value
& 0x00000fff;
22942 if (newimm
== (unsigned int) FAIL
)
22944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22945 _("invalid constant (%lx) after fixup"),
22946 (unsigned long) value
);
22950 newimm
|= (temp
& 0xfffff000);
22951 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22954 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22956 unsigned int highpart
= 0;
22957 unsigned int newinsn
= 0xe1a00000; /* nop. */
22959 if (fixP
->fx_addsy
)
22961 const char *msg
= 0;
22963 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22964 msg
= _("undefined symbol %s used as an immediate value");
22965 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22966 msg
= _("symbol %s is in a different section");
22967 else if (S_IS_WEAK (fixP
->fx_addsy
))
22968 msg
= _("symbol %s is weak and may be overridden later");
22972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22973 msg
, S_GET_NAME (fixP
->fx_addsy
));
22978 newimm
= encode_arm_immediate (value
);
22979 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22981 /* If the instruction will fail, see if we can fix things up by
22982 changing the opcode. */
22983 if (newimm
== (unsigned int) FAIL
22984 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22986 /* No ? OK - try using two ADD instructions to generate
22988 newimm
= validate_immediate_twopart (value
, & highpart
);
22990 /* Yes - then make sure that the second instruction is
22992 if (newimm
!= (unsigned int) FAIL
)
22994 /* Still No ? Try using a negated value. */
22995 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22996 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22997 /* Otherwise - give up. */
23000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23001 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23006 /* Replace the first operand in the 2nd instruction (which
23007 is the PC) with the destination register. We have
23008 already added in the PC in the first instruction and we
23009 do not want to do it again. */
23010 newinsn
&= ~ 0xf0000;
23011 newinsn
|= ((newinsn
& 0x0f000) << 4);
23014 newimm
|= (temp
& 0xfffff000);
23015 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23017 highpart
|= (newinsn
& 0xfffff000);
23018 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23022 case BFD_RELOC_ARM_OFFSET_IMM
:
23023 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23025 /* Fall through. */
23027 case BFD_RELOC_ARM_LITERAL
:
23033 if (validate_offset_imm (value
, 0) == FAIL
)
23035 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23037 _("invalid literal constant: pool needs to be closer"));
23039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23040 _("bad immediate value for offset (%ld)"),
23045 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23047 newval
&= 0xfffff000;
23050 newval
&= 0xff7ff000;
23051 newval
|= value
| (sign
? INDEX_UP
: 0);
23053 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23056 case BFD_RELOC_ARM_OFFSET_IMM8
:
23057 case BFD_RELOC_ARM_HWLITERAL
:
23063 if (validate_offset_imm (value
, 1) == FAIL
)
23065 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23067 _("invalid literal constant: pool needs to be closer"));
23069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23070 _("bad immediate value for 8-bit offset (%ld)"),
23075 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23077 newval
&= 0xfffff0f0;
23080 newval
&= 0xff7ff0f0;
23081 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23083 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23086 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23087 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23089 _("bad immediate value for offset (%ld)"), (long) value
);
23092 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23094 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23097 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23098 /* This is a complicated relocation used for all varieties of Thumb32
23099 load/store instruction with immediate offset:
23101 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23102 *4, optional writeback(W)
23103 (doubleword load/store)
23105 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23106 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23107 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23108 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23109 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23111 Uppercase letters indicate bits that are already encoded at
23112 this point. Lowercase letters are our problem. For the
23113 second block of instructions, the secondary opcode nybble
23114 (bits 8..11) is present, and bit 23 is zero, even if this is
23115 a PC-relative operation. */
23116 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23118 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23120 if ((newval
& 0xf0000000) == 0xe0000000)
23122 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23124 newval
|= (1 << 23);
23127 if (value
% 4 != 0)
23129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23130 _("offset not a multiple of 4"));
23136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23137 _("offset out of range"));
23142 else if ((newval
& 0x000f0000) == 0x000f0000)
23144 /* PC-relative, 12-bit offset. */
23146 newval
|= (1 << 23);
23151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23152 _("offset out of range"));
23157 else if ((newval
& 0x00000100) == 0x00000100)
23159 /* Writeback: 8-bit, +/- offset. */
23161 newval
|= (1 << 9);
23166 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23167 _("offset out of range"));
23172 else if ((newval
& 0x00000f00) == 0x00000e00)
23174 /* T-instruction: positive 8-bit offset. */
23175 if (value
< 0 || value
> 0xff)
23177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23178 _("offset out of range"));
23186 /* Positive 12-bit or negative 8-bit offset. */
23190 newval
|= (1 << 23);
23200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23201 _("offset out of range"));
23208 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23209 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23212 case BFD_RELOC_ARM_SHIFT_IMM
:
23213 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23214 if (((unsigned long) value
) > 32
23216 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23219 _("shift expression is too large"));
23224 /* Shifts of zero must be done as lsl. */
23226 else if (value
== 32)
23228 newval
&= 0xfffff07f;
23229 newval
|= (value
& 0x1f) << 7;
23230 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23233 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23234 case BFD_RELOC_ARM_T32_ADD_IMM
:
23235 case BFD_RELOC_ARM_T32_IMM12
:
23236 case BFD_RELOC_ARM_T32_ADD_PC12
:
23237 /* We claim that this fixup has been processed here,
23238 even if in fact we generate an error because we do
23239 not have a reloc for it, so tc_gen_reloc will reject it. */
23243 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23246 _("undefined symbol %s used as an immediate value"),
23247 S_GET_NAME (fixP
->fx_addsy
));
23251 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23253 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23256 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23257 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23258 Thumb2 modified immediate encoding (T2). */
23259 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23260 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23262 newimm
= encode_thumb32_immediate (value
);
23263 if (newimm
== (unsigned int) FAIL
)
23264 newimm
= thumb32_negate_data_op (&newval
, value
);
23266 if (newimm
== (unsigned int) FAIL
)
23268 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23270 /* Turn add/sum into addw/subw. */
23271 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23272 newval
= (newval
& 0xfeffffff) | 0x02000000;
23273 /* No flat 12-bit imm encoding for addsw/subsw. */
23274 if ((newval
& 0x00100000) == 0)
23276 /* 12 bit immediate for addw/subw. */
23280 newval
^= 0x00a00000;
23283 newimm
= (unsigned int) FAIL
;
23290 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23291 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23292 disassembling, MOV is preferred when there is no encoding
23294 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23295 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23296 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23297 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23298 && value
>= 0 && value
<=0xffff)
23300 /* Toggle bit[25] to change encoding from T2 to T3. */
23302 /* Clear bits[19:16]. */
23303 newval
&= 0xfff0ffff;
23304 /* Encoding high 4bits imm. Code below will encode the
23305 remaining low 12bits. */
23306 newval
|= (value
& 0x0000f000) << 4;
23307 newimm
= value
& 0x00000fff;
23312 if (newimm
== (unsigned int)FAIL
)
23314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23315 _("invalid constant (%lx) after fixup"),
23316 (unsigned long) value
);
23320 newval
|= (newimm
& 0x800) << 15;
23321 newval
|= (newimm
& 0x700) << 4;
23322 newval
|= (newimm
& 0x0ff);
23324 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23325 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23328 case BFD_RELOC_ARM_SMC
:
23329 if (((unsigned long) value
) > 0xffff)
23330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23331 _("invalid smc expression"));
23332 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23333 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23334 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23337 case BFD_RELOC_ARM_HVC
:
23338 if (((unsigned long) value
) > 0xffff)
23339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23340 _("invalid hvc expression"));
23341 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23342 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23343 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23346 case BFD_RELOC_ARM_SWI
:
23347 if (fixP
->tc_fix_data
!= 0)
23349 if (((unsigned long) value
) > 0xff)
23350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23351 _("invalid swi expression"));
23352 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23354 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23358 if (((unsigned long) value
) > 0x00ffffff)
23359 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23360 _("invalid swi expression"));
23361 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23363 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23367 case BFD_RELOC_ARM_MULTI
:
23368 if (((unsigned long) value
) > 0xffff)
23369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23370 _("invalid expression in load/store multiple"));
23371 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23372 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23376 case BFD_RELOC_ARM_PCREL_CALL
:
23378 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23380 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23381 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23382 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23383 /* Flip the bl to blx. This is a simple flip
23384 bit here because we generate PCREL_CALL for
23385 unconditional bls. */
23387 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23388 newval
= newval
| 0x10000000;
23389 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23395 goto arm_branch_common
;
23397 case BFD_RELOC_ARM_PCREL_JUMP
:
23398 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23400 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23401 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23402 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23404 /* This would map to a bl<cond>, b<cond>,
23405 b<always> to a Thumb function. We
23406 need to force a relocation for this particular
23408 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23411 /* Fall through. */
23413 case BFD_RELOC_ARM_PLT32
:
23415 case BFD_RELOC_ARM_PCREL_BRANCH
:
23417 goto arm_branch_common
;
23419 case BFD_RELOC_ARM_PCREL_BLX
:
23422 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23424 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23425 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23426 && ARM_IS_FUNC (fixP
->fx_addsy
))
23428 /* Flip the blx to a bl and warn. */
23429 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23430 newval
= 0xeb000000;
23431 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23432 _("blx to '%s' an ARM ISA state function changed to bl"),
23434 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23440 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23441 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23445 /* We are going to store value (shifted right by two) in the
23446 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23447 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23448 also be be clear. */
23450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23451 _("misaligned branch destination"));
23452 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23453 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23456 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23458 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23459 newval
|= (value
>> 2) & 0x00ffffff;
23460 /* Set the H bit on BLX instructions. */
23464 newval
|= 0x01000000;
23466 newval
&= ~0x01000000;
23468 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23472 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23473 /* CBZ can only branch forward. */
23475 /* Attempts to use CBZ to branch to the next instruction
23476 (which, strictly speaking, are prohibited) will be turned into
23479 FIXME: It may be better to remove the instruction completely and
23480 perform relaxation. */
23483 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23484 newval
= 0xbf00; /* NOP encoding T1 */
23485 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23492 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23494 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23495 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23496 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23501 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23502 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23505 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23507 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23508 newval
|= (value
& 0x1ff) >> 1;
23509 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23513 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23514 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23517 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23519 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23520 newval
|= (value
& 0xfff) >> 1;
23521 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23525 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23527 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23528 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23529 && ARM_IS_FUNC (fixP
->fx_addsy
)
23530 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23532 /* Force a relocation for a branch 20 bits wide. */
23535 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23537 _("conditional branch out of range"));
23539 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23542 addressT S
, J1
, J2
, lo
, hi
;
23544 S
= (value
& 0x00100000) >> 20;
23545 J2
= (value
& 0x00080000) >> 19;
23546 J1
= (value
& 0x00040000) >> 18;
23547 hi
= (value
& 0x0003f000) >> 12;
23548 lo
= (value
& 0x00000ffe) >> 1;
23550 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23551 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23552 newval
|= (S
<< 10) | hi
;
23553 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23554 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23555 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23559 case BFD_RELOC_THUMB_PCREL_BLX
:
23560 /* If there is a blx from a thumb state function to
23561 another thumb function flip this to a bl and warn
23565 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23566 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23567 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23569 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23570 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23571 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23573 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23574 newval
= newval
| 0x1000;
23575 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23576 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23581 goto thumb_bl_common
;
23583 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23584 /* A bl from Thumb state ISA to an internal ARM state function
23585 is converted to a blx. */
23587 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23588 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23589 && ARM_IS_FUNC (fixP
->fx_addsy
)
23590 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23592 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23593 newval
= newval
& ~0x1000;
23594 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23595 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23601 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23602 /* For a BLX instruction, make sure that the relocation is rounded up
23603 to a word boundary. This follows the semantics of the instruction
23604 which specifies that bit 1 of the target address will come from bit
23605 1 of the base address. */
23606 value
= (value
+ 3) & ~ 3;
23609 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23610 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23611 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23614 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23616 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23618 else if ((value
& ~0x1ffffff)
23619 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23621 _("Thumb2 branch out of range"));
23624 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23625 encode_thumb2_b_bl_offset (buf
, value
);
23629 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23630 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23633 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23634 encode_thumb2_b_bl_offset (buf
, value
);
23639 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23645 md_number_to_chars (buf
, value
, 2);
23649 case BFD_RELOC_ARM_TLS_CALL
:
23650 case BFD_RELOC_ARM_THM_TLS_CALL
:
23651 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23652 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23653 case BFD_RELOC_ARM_TLS_GOTDESC
:
23654 case BFD_RELOC_ARM_TLS_GD32
:
23655 case BFD_RELOC_ARM_TLS_LE32
:
23656 case BFD_RELOC_ARM_TLS_IE32
:
23657 case BFD_RELOC_ARM_TLS_LDM32
:
23658 case BFD_RELOC_ARM_TLS_LDO32
:
23659 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23662 case BFD_RELOC_ARM_GOT32
:
23663 case BFD_RELOC_ARM_GOTOFF
:
23666 case BFD_RELOC_ARM_GOT_PREL
:
23667 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23668 md_number_to_chars (buf
, value
, 4);
23671 case BFD_RELOC_ARM_TARGET2
:
23672 /* TARGET2 is not partial-inplace, so we need to write the
23673 addend here for REL targets, because it won't be written out
23674 during reloc processing later. */
23675 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23676 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23680 case BFD_RELOC_RVA
:
23682 case BFD_RELOC_ARM_TARGET1
:
23683 case BFD_RELOC_ARM_ROSEGREL32
:
23684 case BFD_RELOC_ARM_SBREL32
:
23685 case BFD_RELOC_32_PCREL
:
23687 case BFD_RELOC_32_SECREL
:
23689 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23691 /* For WinCE we only do this for pcrel fixups. */
23692 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23694 md_number_to_chars (buf
, value
, 4);
23698 case BFD_RELOC_ARM_PREL31
:
23699 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23701 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23702 if ((value
^ (value
>> 1)) & 0x40000000)
23704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23705 _("rel31 relocation overflow"));
23707 newval
|= value
& 0x7fffffff;
23708 md_number_to_chars (buf
, newval
, 4);
23713 case BFD_RELOC_ARM_CP_OFF_IMM
:
23714 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23715 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23716 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23718 newval
= get_thumb32_insn (buf
);
23719 if ((newval
& 0x0f200f00) == 0x0d000900)
23721 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23722 has permitted values that are multiples of 2, in the range 0
23724 if (value
< -510 || value
> 510 || (value
& 1))
23725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23726 _("co-processor offset out of range"));
23728 else if (value
< -1023 || value
> 1023 || (value
& 3))
23729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23730 _("co-processor offset out of range"));
23735 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23736 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23737 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23739 newval
= get_thumb32_insn (buf
);
23741 newval
&= 0xffffff00;
23744 newval
&= 0xff7fff00;
23745 if ((newval
& 0x0f200f00) == 0x0d000900)
23747 /* This is a fp16 vstr/vldr.
23749 It requires the immediate offset in the instruction is shifted
23750 left by 1 to be a half-word offset.
23752 Here, left shift by 1 first, and later right shift by 2
23753 should get the right offset. */
23756 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23758 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23759 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23760 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23762 put_thumb32_insn (buf
, newval
);
23765 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23766 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23767 if (value
< -255 || value
> 255)
23768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23769 _("co-processor offset out of range"));
23771 goto cp_off_common
;
23773 case BFD_RELOC_ARM_THUMB_OFFSET
:
23774 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23775 /* Exactly what ranges, and where the offset is inserted depends
23776 on the type of instruction, we can establish this from the
23778 switch (newval
>> 12)
23780 case 4: /* PC load. */
23781 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23782 forced to zero for these loads; md_pcrel_from has already
23783 compensated for this. */
23785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23786 _("invalid offset, target not word aligned (0x%08lX)"),
23787 (((unsigned long) fixP
->fx_frag
->fr_address
23788 + (unsigned long) fixP
->fx_where
) & ~3)
23789 + (unsigned long) value
);
23791 if (value
& ~0x3fc)
23792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23793 _("invalid offset, value too big (0x%08lX)"),
23796 newval
|= value
>> 2;
23799 case 9: /* SP load/store. */
23800 if (value
& ~0x3fc)
23801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23802 _("invalid offset, value too big (0x%08lX)"),
23804 newval
|= value
>> 2;
23807 case 6: /* Word load/store. */
23809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23810 _("invalid offset, value too big (0x%08lX)"),
23812 newval
|= value
<< 4; /* 6 - 2. */
23815 case 7: /* Byte load/store. */
23817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23818 _("invalid offset, value too big (0x%08lX)"),
23820 newval
|= value
<< 6;
23823 case 8: /* Halfword load/store. */
23825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23826 _("invalid offset, value too big (0x%08lX)"),
23828 newval
|= value
<< 5; /* 6 - 1. */
23832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23833 "Unable to process relocation for thumb opcode: %lx",
23834 (unsigned long) newval
);
23837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23840 case BFD_RELOC_ARM_THUMB_ADD
:
23841 /* This is a complicated relocation, since we use it for all of
23842 the following immediate relocations:
23846 9bit ADD/SUB SP word-aligned
23847 10bit ADD PC/SP word-aligned
23849 The type of instruction being processed is encoded in the
23856 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23858 int rd
= (newval
>> 4) & 0xf;
23859 int rs
= newval
& 0xf;
23860 int subtract
= !!(newval
& 0x8000);
23862 /* Check for HI regs, only very restricted cases allowed:
23863 Adjusting SP, and using PC or SP to get an address. */
23864 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23865 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23867 _("invalid Hi register with immediate"));
23869 /* If value is negative, choose the opposite instruction. */
23873 subtract
= !subtract
;
23875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23876 _("immediate value out of range"));
23881 if (value
& ~0x1fc)
23882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23883 _("invalid immediate for stack address calculation"));
23884 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23885 newval
|= value
>> 2;
23887 else if (rs
== REG_PC
|| rs
== REG_SP
)
23889 /* PR gas/18541. If the addition is for a defined symbol
23890 within range of an ADR instruction then accept it. */
23893 && fixP
->fx_addsy
!= NULL
)
23897 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23898 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23899 || S_IS_WEAK (fixP
->fx_addsy
))
23901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23902 _("address calculation needs a strongly defined nearby symbol"));
23906 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23908 /* Round up to the next 4-byte boundary. */
23913 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23918 _("symbol too far away"));
23928 if (subtract
|| value
& ~0x3fc)
23929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23930 _("invalid immediate for address calculation (value = 0x%08lX)"),
23931 (unsigned long) (subtract
? - value
: value
));
23932 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23934 newval
|= value
>> 2;
23939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23940 _("immediate value out of range"));
23941 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23942 newval
|= (rd
<< 8) | value
;
23947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23948 _("immediate value out of range"));
23949 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23950 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23953 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23956 case BFD_RELOC_ARM_THUMB_IMM
:
23957 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23958 if (value
< 0 || value
> 255)
23959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23960 _("invalid immediate: %ld is out of range"),
23963 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23966 case BFD_RELOC_ARM_THUMB_SHIFT
:
23967 /* 5bit shift value (0..32). LSL cannot take 32. */
23968 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23969 temp
= newval
& 0xf800;
23970 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23972 _("invalid shift value: %ld"), (long) value
);
23973 /* Shifts of zero must be encoded as LSL. */
23975 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23976 /* Shifts of 32 are encoded as zero. */
23977 else if (value
== 32)
23979 newval
|= value
<< 6;
23980 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23983 case BFD_RELOC_VTABLE_INHERIT
:
23984 case BFD_RELOC_VTABLE_ENTRY
:
23988 case BFD_RELOC_ARM_MOVW
:
23989 case BFD_RELOC_ARM_MOVT
:
23990 case BFD_RELOC_ARM_THUMB_MOVW
:
23991 case BFD_RELOC_ARM_THUMB_MOVT
:
23992 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23994 /* REL format relocations are limited to a 16-bit addend. */
23995 if (!fixP
->fx_done
)
23997 if (value
< -0x8000 || value
> 0x7fff)
23998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23999 _("offset out of range"));
24001 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24002 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24007 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24008 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24010 newval
= get_thumb32_insn (buf
);
24011 newval
&= 0xfbf08f00;
24012 newval
|= (value
& 0xf000) << 4;
24013 newval
|= (value
& 0x0800) << 15;
24014 newval
|= (value
& 0x0700) << 4;
24015 newval
|= (value
& 0x00ff);
24016 put_thumb32_insn (buf
, newval
);
24020 newval
= md_chars_to_number (buf
, 4);
24021 newval
&= 0xfff0f000;
24022 newval
|= value
& 0x0fff;
24023 newval
|= (value
& 0xf000) << 4;
24024 md_number_to_chars (buf
, newval
, 4);
24029 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24030 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24031 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24032 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24033 gas_assert (!fixP
->fx_done
);
24036 bfd_boolean is_mov
;
24037 bfd_vma encoded_addend
= value
;
24039 /* Check that addend can be encoded in instruction. */
24040 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24042 _("the offset 0x%08lX is not representable"),
24043 (unsigned long) encoded_addend
);
24045 /* Extract the instruction. */
24046 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24047 is_mov
= (insn
& 0xf800) == 0x2000;
24052 if (!seg
->use_rela_p
)
24053 insn
|= encoded_addend
;
24059 /* Extract the instruction. */
24060 /* Encoding is the following
24065 /* The following conditions must be true :
24070 rd
= (insn
>> 4) & 0xf;
24072 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24074 _("Unable to process relocation for thumb opcode: %lx"),
24075 (unsigned long) insn
);
24077 /* Encode as ADD immediate8 thumb 1 code. */
24078 insn
= 0x3000 | (rd
<< 8);
24080 /* Place the encoded addend into the first 8 bits of the
24082 if (!seg
->use_rela_p
)
24083 insn
|= encoded_addend
;
24086 /* Update the instruction. */
24087 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24091 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24092 case BFD_RELOC_ARM_ALU_PC_G0
:
24093 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24094 case BFD_RELOC_ARM_ALU_PC_G1
:
24095 case BFD_RELOC_ARM_ALU_PC_G2
:
24096 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24097 case BFD_RELOC_ARM_ALU_SB_G0
:
24098 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24099 case BFD_RELOC_ARM_ALU_SB_G1
:
24100 case BFD_RELOC_ARM_ALU_SB_G2
:
24101 gas_assert (!fixP
->fx_done
);
24102 if (!seg
->use_rela_p
)
24105 bfd_vma encoded_addend
;
24106 bfd_vma addend_abs
= abs (value
);
24108 /* Check that the absolute value of the addend can be
24109 expressed as an 8-bit constant plus a rotation. */
24110 encoded_addend
= encode_arm_immediate (addend_abs
);
24111 if (encoded_addend
== (unsigned int) FAIL
)
24112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24113 _("the offset 0x%08lX is not representable"),
24114 (unsigned long) addend_abs
);
24116 /* Extract the instruction. */
24117 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24119 /* If the addend is positive, use an ADD instruction.
24120 Otherwise use a SUB. Take care not to destroy the S bit. */
24121 insn
&= 0xff1fffff;
24127 /* Place the encoded addend into the first 12 bits of the
24129 insn
&= 0xfffff000;
24130 insn
|= encoded_addend
;
24132 /* Update the instruction. */
24133 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24137 case BFD_RELOC_ARM_LDR_PC_G0
:
24138 case BFD_RELOC_ARM_LDR_PC_G1
:
24139 case BFD_RELOC_ARM_LDR_PC_G2
:
24140 case BFD_RELOC_ARM_LDR_SB_G0
:
24141 case BFD_RELOC_ARM_LDR_SB_G1
:
24142 case BFD_RELOC_ARM_LDR_SB_G2
:
24143 gas_assert (!fixP
->fx_done
);
24144 if (!seg
->use_rela_p
)
24147 bfd_vma addend_abs
= abs (value
);
24149 /* Check that the absolute value of the addend can be
24150 encoded in 12 bits. */
24151 if (addend_abs
>= 0x1000)
24152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24153 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24154 (unsigned long) addend_abs
);
24156 /* Extract the instruction. */
24157 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24159 /* If the addend is negative, clear bit 23 of the instruction.
24160 Otherwise set it. */
24162 insn
&= ~(1 << 23);
24166 /* Place the absolute value of the addend into the first 12 bits
24167 of the instruction. */
24168 insn
&= 0xfffff000;
24169 insn
|= addend_abs
;
24171 /* Update the instruction. */
24172 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24176 case BFD_RELOC_ARM_LDRS_PC_G0
:
24177 case BFD_RELOC_ARM_LDRS_PC_G1
:
24178 case BFD_RELOC_ARM_LDRS_PC_G2
:
24179 case BFD_RELOC_ARM_LDRS_SB_G0
:
24180 case BFD_RELOC_ARM_LDRS_SB_G1
:
24181 case BFD_RELOC_ARM_LDRS_SB_G2
:
24182 gas_assert (!fixP
->fx_done
);
24183 if (!seg
->use_rela_p
)
24186 bfd_vma addend_abs
= abs (value
);
24188 /* Check that the absolute value of the addend can be
24189 encoded in 8 bits. */
24190 if (addend_abs
>= 0x100)
24191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24192 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24193 (unsigned long) addend_abs
);
24195 /* Extract the instruction. */
24196 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24198 /* If the addend is negative, clear bit 23 of the instruction.
24199 Otherwise set it. */
24201 insn
&= ~(1 << 23);
24205 /* Place the first four bits of the absolute value of the addend
24206 into the first 4 bits of the instruction, and the remaining
24207 four into bits 8 .. 11. */
24208 insn
&= 0xfffff0f0;
24209 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24211 /* Update the instruction. */
24212 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24216 case BFD_RELOC_ARM_LDC_PC_G0
:
24217 case BFD_RELOC_ARM_LDC_PC_G1
:
24218 case BFD_RELOC_ARM_LDC_PC_G2
:
24219 case BFD_RELOC_ARM_LDC_SB_G0
:
24220 case BFD_RELOC_ARM_LDC_SB_G1
:
24221 case BFD_RELOC_ARM_LDC_SB_G2
:
24222 gas_assert (!fixP
->fx_done
);
24223 if (!seg
->use_rela_p
)
24226 bfd_vma addend_abs
= abs (value
);
24228 /* Check that the absolute value of the addend is a multiple of
24229 four and, when divided by four, fits in 8 bits. */
24230 if (addend_abs
& 0x3)
24231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24232 _("bad offset 0x%08lX (must be word-aligned)"),
24233 (unsigned long) addend_abs
);
24235 if ((addend_abs
>> 2) > 0xff)
24236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24237 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24238 (unsigned long) addend_abs
);
24240 /* Extract the instruction. */
24241 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24243 /* If the addend is negative, clear bit 23 of the instruction.
24244 Otherwise set it. */
24246 insn
&= ~(1 << 23);
24250 /* Place the addend (divided by four) into the first eight
24251 bits of the instruction. */
24252 insn
&= 0xfffffff0;
24253 insn
|= addend_abs
>> 2;
24255 /* Update the instruction. */
24256 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24260 case BFD_RELOC_ARM_V4BX
:
24261 /* This will need to go in the object file. */
24265 case BFD_RELOC_UNUSED
:
24267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24268 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24272 /* Translate internal representation of relocation info to BFD target
24276 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24279 bfd_reloc_code_real_type code
;
24281 reloc
= XNEW (arelent
);
24283 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24284 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24285 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24287 if (fixp
->fx_pcrel
)
24289 if (section
->use_rela_p
)
24290 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24292 fixp
->fx_offset
= reloc
->address
;
24294 reloc
->addend
= fixp
->fx_offset
;
24296 switch (fixp
->fx_r_type
)
24299 if (fixp
->fx_pcrel
)
24301 code
= BFD_RELOC_8_PCREL
;
24304 /* Fall through. */
24307 if (fixp
->fx_pcrel
)
24309 code
= BFD_RELOC_16_PCREL
;
24312 /* Fall through. */
24315 if (fixp
->fx_pcrel
)
24317 code
= BFD_RELOC_32_PCREL
;
24320 /* Fall through. */
24322 case BFD_RELOC_ARM_MOVW
:
24323 if (fixp
->fx_pcrel
)
24325 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24328 /* Fall through. */
24330 case BFD_RELOC_ARM_MOVT
:
24331 if (fixp
->fx_pcrel
)
24333 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24336 /* Fall through. */
24338 case BFD_RELOC_ARM_THUMB_MOVW
:
24339 if (fixp
->fx_pcrel
)
24341 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24344 /* Fall through. */
24346 case BFD_RELOC_ARM_THUMB_MOVT
:
24347 if (fixp
->fx_pcrel
)
24349 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24352 /* Fall through. */
24354 case BFD_RELOC_NONE
:
24355 case BFD_RELOC_ARM_PCREL_BRANCH
:
24356 case BFD_RELOC_ARM_PCREL_BLX
:
24357 case BFD_RELOC_RVA
:
24358 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24359 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24360 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24361 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24362 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24363 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24364 case BFD_RELOC_VTABLE_ENTRY
:
24365 case BFD_RELOC_VTABLE_INHERIT
:
24367 case BFD_RELOC_32_SECREL
:
24369 code
= fixp
->fx_r_type
;
24372 case BFD_RELOC_THUMB_PCREL_BLX
:
24374 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24375 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24378 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24381 case BFD_RELOC_ARM_LITERAL
:
24382 case BFD_RELOC_ARM_HWLITERAL
:
24383 /* If this is called then the a literal has
24384 been referenced across a section boundary. */
24385 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24386 _("literal referenced across section boundary"));
24390 case BFD_RELOC_ARM_TLS_CALL
:
24391 case BFD_RELOC_ARM_THM_TLS_CALL
:
24392 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24393 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24394 case BFD_RELOC_ARM_GOT32
:
24395 case BFD_RELOC_ARM_GOTOFF
:
24396 case BFD_RELOC_ARM_GOT_PREL
:
24397 case BFD_RELOC_ARM_PLT32
:
24398 case BFD_RELOC_ARM_TARGET1
:
24399 case BFD_RELOC_ARM_ROSEGREL32
:
24400 case BFD_RELOC_ARM_SBREL32
:
24401 case BFD_RELOC_ARM_PREL31
:
24402 case BFD_RELOC_ARM_TARGET2
:
24403 case BFD_RELOC_ARM_TLS_LDO32
:
24404 case BFD_RELOC_ARM_PCREL_CALL
:
24405 case BFD_RELOC_ARM_PCREL_JUMP
:
24406 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24407 case BFD_RELOC_ARM_ALU_PC_G0
:
24408 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24409 case BFD_RELOC_ARM_ALU_PC_G1
:
24410 case BFD_RELOC_ARM_ALU_PC_G2
:
24411 case BFD_RELOC_ARM_LDR_PC_G0
:
24412 case BFD_RELOC_ARM_LDR_PC_G1
:
24413 case BFD_RELOC_ARM_LDR_PC_G2
:
24414 case BFD_RELOC_ARM_LDRS_PC_G0
:
24415 case BFD_RELOC_ARM_LDRS_PC_G1
:
24416 case BFD_RELOC_ARM_LDRS_PC_G2
:
24417 case BFD_RELOC_ARM_LDC_PC_G0
:
24418 case BFD_RELOC_ARM_LDC_PC_G1
:
24419 case BFD_RELOC_ARM_LDC_PC_G2
:
24420 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24421 case BFD_RELOC_ARM_ALU_SB_G0
:
24422 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24423 case BFD_RELOC_ARM_ALU_SB_G1
:
24424 case BFD_RELOC_ARM_ALU_SB_G2
:
24425 case BFD_RELOC_ARM_LDR_SB_G0
:
24426 case BFD_RELOC_ARM_LDR_SB_G1
:
24427 case BFD_RELOC_ARM_LDR_SB_G2
:
24428 case BFD_RELOC_ARM_LDRS_SB_G0
:
24429 case BFD_RELOC_ARM_LDRS_SB_G1
:
24430 case BFD_RELOC_ARM_LDRS_SB_G2
:
24431 case BFD_RELOC_ARM_LDC_SB_G0
:
24432 case BFD_RELOC_ARM_LDC_SB_G1
:
24433 case BFD_RELOC_ARM_LDC_SB_G2
:
24434 case BFD_RELOC_ARM_V4BX
:
24435 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24436 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24437 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24438 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24439 code
= fixp
->fx_r_type
;
24442 case BFD_RELOC_ARM_TLS_GOTDESC
:
24443 case BFD_RELOC_ARM_TLS_GD32
:
24444 case BFD_RELOC_ARM_TLS_LE32
:
24445 case BFD_RELOC_ARM_TLS_IE32
:
24446 case BFD_RELOC_ARM_TLS_LDM32
:
24447 /* BFD will include the symbol's address in the addend.
24448 But we don't want that, so subtract it out again here. */
24449 if (!S_IS_COMMON (fixp
->fx_addsy
))
24450 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24451 code
= fixp
->fx_r_type
;
24455 case BFD_RELOC_ARM_IMMEDIATE
:
24456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24457 _("internal relocation (type: IMMEDIATE) not fixed up"));
24460 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24461 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24462 _("ADRL used for a symbol not defined in the same file"));
24465 case BFD_RELOC_ARM_OFFSET_IMM
:
24466 if (section
->use_rela_p
)
24468 code
= fixp
->fx_r_type
;
24472 if (fixp
->fx_addsy
!= NULL
24473 && !S_IS_DEFINED (fixp
->fx_addsy
)
24474 && S_IS_LOCAL (fixp
->fx_addsy
))
24476 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24477 _("undefined local label `%s'"),
24478 S_GET_NAME (fixp
->fx_addsy
));
24482 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24483 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24490 switch (fixp
->fx_r_type
)
24492 case BFD_RELOC_NONE
: type
= "NONE"; break;
24493 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24494 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24495 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24496 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24497 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24498 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24499 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24500 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24501 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24502 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24503 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24504 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24505 default: type
= _("<unknown>"); break;
24507 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24508 _("cannot represent %s relocation in this object file format"),
24515 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24517 && fixp
->fx_addsy
== GOT_symbol
)
24519 code
= BFD_RELOC_ARM_GOTPC
;
24520 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24524 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24526 if (reloc
->howto
== NULL
)
24528 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24529 _("cannot represent %s relocation in this object file format"),
24530 bfd_get_reloc_code_name (code
));
24534 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24535 vtable entry to be used in the relocation's section offset. */
24536 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24537 reloc
->address
= fixp
->fx_offset
;
24542 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24545 cons_fix_new_arm (fragS
* frag
,
24549 bfd_reloc_code_real_type reloc
)
24554 FIXME: @@ Should look at CPU word size. */
24558 reloc
= BFD_RELOC_8
;
24561 reloc
= BFD_RELOC_16
;
24565 reloc
= BFD_RELOC_32
;
24568 reloc
= BFD_RELOC_64
;
24573 if (exp
->X_op
== O_secrel
)
24575 exp
->X_op
= O_symbol
;
24576 reloc
= BFD_RELOC_32_SECREL
;
24580 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24583 #if defined (OBJ_COFF)
24585 arm_validate_fix (fixS
* fixP
)
24587 /* If the destination of the branch is a defined symbol which does not have
24588 the THUMB_FUNC attribute, then we must be calling a function which has
24589 the (interfacearm) attribute. We look for the Thumb entry point to that
24590 function and change the branch to refer to that function instead. */
24591 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24592 && fixP
->fx_addsy
!= NULL
24593 && S_IS_DEFINED (fixP
->fx_addsy
)
24594 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24596 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24603 arm_force_relocation (struct fix
* fixp
)
24605 #if defined (OBJ_COFF) && defined (TE_PE)
24606 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24610 /* In case we have a call or a branch to a function in ARM ISA mode from
24611 a thumb function or vice-versa force the relocation. These relocations
24612 are cleared off for some cores that might have blx and simple transformations
24616 switch (fixp
->fx_r_type
)
24618 case BFD_RELOC_ARM_PCREL_JUMP
:
24619 case BFD_RELOC_ARM_PCREL_CALL
:
24620 case BFD_RELOC_THUMB_PCREL_BLX
:
24621 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24625 case BFD_RELOC_ARM_PCREL_BLX
:
24626 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24627 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24628 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24629 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24638 /* Resolve these relocations even if the symbol is extern or weak.
24639 Technically this is probably wrong due to symbol preemption.
24640 In practice these relocations do not have enough range to be useful
24641 at dynamic link time, and some code (e.g. in the Linux kernel)
24642 expects these references to be resolved. */
24643 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24644 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24645 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24646 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24647 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24648 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24649 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24650 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24651 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24652 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24653 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24654 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24655 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24656 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24659 /* Always leave these relocations for the linker. */
24660 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24661 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24662 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24665 /* Always generate relocations against function symbols. */
24666 if (fixp
->fx_r_type
== BFD_RELOC_32
24668 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24671 return generic_force_reloc (fixp
);
24674 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24675 /* Relocations against function names must be left unadjusted,
24676 so that the linker can use this information to generate interworking
24677 stubs. The MIPS version of this function
24678 also prevents relocations that are mips-16 specific, but I do not
24679 know why it does this.
24682 There is one other problem that ought to be addressed here, but
24683 which currently is not: Taking the address of a label (rather
24684 than a function) and then later jumping to that address. Such
24685 addresses also ought to have their bottom bit set (assuming that
24686 they reside in Thumb code), but at the moment they will not. */
24689 arm_fix_adjustable (fixS
* fixP
)
24691 if (fixP
->fx_addsy
== NULL
)
24694 /* Preserve relocations against symbols with function type. */
24695 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24698 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24699 && fixP
->fx_subsy
== NULL
)
24702 /* We need the symbol name for the VTABLE entries. */
24703 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24704 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24707 /* Don't allow symbols to be discarded on GOT related relocs. */
24708 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24709 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24710 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24711 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24712 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24713 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24714 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24715 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24716 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24717 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24718 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24719 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24720 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24721 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24724 /* Similarly for group relocations. */
24725 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24726 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24727 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24730 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24731 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24732 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24733 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24734 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24735 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24736 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24737 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24738 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24741 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24742 offsets, so keep these symbols. */
24743 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24744 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24749 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24753 elf32_arm_target_format (void)
24756 return (target_big_endian
24757 ? "elf32-bigarm-symbian"
24758 : "elf32-littlearm-symbian");
24759 #elif defined (TE_VXWORKS)
24760 return (target_big_endian
24761 ? "elf32-bigarm-vxworks"
24762 : "elf32-littlearm-vxworks");
24763 #elif defined (TE_NACL)
24764 return (target_big_endian
24765 ? "elf32-bigarm-nacl"
24766 : "elf32-littlearm-nacl");
24768 if (target_big_endian
)
24769 return "elf32-bigarm";
24771 return "elf32-littlearm";
24776 armelf_frob_symbol (symbolS
* symp
,
24779 elf_frob_symbol (symp
, puntp
);
24783 /* MD interface: Finalization. */
24788 literal_pool
* pool
;
24790 /* Ensure that all the IT blocks are properly closed. */
24791 check_it_blocks_finished ();
24793 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24795 /* Put it at the end of the relevant section. */
24796 subseg_set (pool
->section
, pool
->sub_section
);
24798 arm_elf_change_section ();
24805 /* Remove any excess mapping symbols generated for alignment frags in
24806 SEC. We may have created a mapping symbol before a zero byte
24807 alignment; remove it if there's a mapping symbol after the
24810 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24811 void *dummy ATTRIBUTE_UNUSED
)
24813 segment_info_type
*seginfo
= seg_info (sec
);
24816 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24819 for (fragp
= seginfo
->frchainP
->frch_root
;
24821 fragp
= fragp
->fr_next
)
24823 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24824 fragS
*next
= fragp
->fr_next
;
24826 /* Variable-sized frags have been converted to fixed size by
24827 this point. But if this was variable-sized to start with,
24828 there will be a fixed-size frag after it. So don't handle
24830 if (sym
== NULL
|| next
== NULL
)
24833 if (S_GET_VALUE (sym
) < next
->fr_address
)
24834 /* Not at the end of this frag. */
24836 know (S_GET_VALUE (sym
) == next
->fr_address
);
24840 if (next
->tc_frag_data
.first_map
!= NULL
)
24842 /* Next frag starts with a mapping symbol. Discard this
24844 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24848 if (next
->fr_next
== NULL
)
24850 /* This mapping symbol is at the end of the section. Discard
24852 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24853 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24857 /* As long as we have empty frags without any mapping symbols,
24859 /* If the next frag is non-empty and does not start with a
24860 mapping symbol, then this mapping symbol is required. */
24861 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24864 next
= next
->fr_next
;
24866 while (next
!= NULL
);
24871 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24875 arm_adjust_symtab (void)
24880 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24882 if (ARM_IS_THUMB (sym
))
24884 if (THUMB_IS_FUNC (sym
))
24886 /* Mark the symbol as a Thumb function. */
24887 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24888 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24889 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24891 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24892 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24894 as_bad (_("%s: unexpected function type: %d"),
24895 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24897 else switch (S_GET_STORAGE_CLASS (sym
))
24900 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24903 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24906 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24914 if (ARM_IS_INTERWORK (sym
))
24915 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24922 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24924 if (ARM_IS_THUMB (sym
))
24926 elf_symbol_type
* elf_sym
;
24928 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24929 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24931 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24932 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24934 /* If it's a .thumb_func, declare it as so,
24935 otherwise tag label as .code 16. */
24936 if (THUMB_IS_FUNC (sym
))
24937 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24938 ST_BRANCH_TO_THUMB
);
24939 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24940 elf_sym
->internal_elf_sym
.st_info
=
24941 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24946 /* Remove any overlapping mapping symbols generated by alignment frags. */
24947 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24948 /* Now do generic ELF adjustments. */
24949 elf_adjust_symtab ();
24953 /* MD interface: Initialization. */
24956 set_constant_flonums (void)
24960 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24961 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24965 /* Auto-select Thumb mode if it's the only available instruction set for the
24966 given architecture. */
24969 autoselect_thumb_from_cpu_variant (void)
24971 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24972 opcode_select (16);
24981 if ( (arm_ops_hsh
= hash_new ()) == NULL
24982 || (arm_cond_hsh
= hash_new ()) == NULL
24983 || (arm_shift_hsh
= hash_new ()) == NULL
24984 || (arm_psr_hsh
= hash_new ()) == NULL
24985 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24986 || (arm_reg_hsh
= hash_new ()) == NULL
24987 || (arm_reloc_hsh
= hash_new ()) == NULL
24988 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24989 as_fatal (_("virtual memory exhausted"));
24991 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24992 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24993 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24994 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24995 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24996 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24997 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24998 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24999 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25000 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25001 (void *) (v7m_psrs
+ i
));
25002 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25003 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25005 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25007 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25008 (void *) (barrier_opt_names
+ i
));
25010 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25012 struct reloc_entry
* entry
= reloc_names
+ i
;
25014 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25015 /* This makes encode_branch() use the EABI versions of this relocation. */
25016 entry
->reloc
= BFD_RELOC_UNUSED
;
25018 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25022 set_constant_flonums ();
25024 /* Set the cpu variant based on the command-line options. We prefer
25025 -mcpu= over -march= if both are set (as for GCC); and we prefer
25026 -mfpu= over any other way of setting the floating point unit.
25027 Use of legacy options with new options are faulted. */
25030 if (mcpu_cpu_opt
|| march_cpu_opt
)
25031 as_bad (_("use of old and new-style options to set CPU type"));
25033 mcpu_cpu_opt
= legacy_cpu
;
25035 else if (!mcpu_cpu_opt
)
25036 mcpu_cpu_opt
= march_cpu_opt
;
25041 as_bad (_("use of old and new-style options to set FPU type"));
25043 mfpu_opt
= legacy_fpu
;
25045 else if (!mfpu_opt
)
25047 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25048 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25049 /* Some environments specify a default FPU. If they don't, infer it
25050 from the processor. */
25052 mfpu_opt
= mcpu_fpu_opt
;
25054 mfpu_opt
= march_fpu_opt
;
25056 mfpu_opt
= &fpu_default
;
25062 if (mcpu_cpu_opt
!= NULL
)
25063 mfpu_opt
= &fpu_default
;
25064 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25065 mfpu_opt
= &fpu_arch_vfp_v2
;
25067 mfpu_opt
= &fpu_arch_fpa
;
25073 mcpu_cpu_opt
= &cpu_default
;
25074 selected_cpu
= cpu_default
;
25077 selected_cpu
= *mcpu_cpu_opt
;
25080 selected_cpu
= *mcpu_cpu_opt
;
25082 mcpu_cpu_opt
= &arm_arch_any
;
25085 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25087 autoselect_thumb_from_cpu_variant ();
25089 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25091 #if defined OBJ_COFF || defined OBJ_ELF
25093 unsigned int flags
= 0;
25095 #if defined OBJ_ELF
25096 flags
= meabi_flags
;
25098 switch (meabi_flags
)
25100 case EF_ARM_EABI_UNKNOWN
:
25102 /* Set the flags in the private structure. */
25103 if (uses_apcs_26
) flags
|= F_APCS26
;
25104 if (support_interwork
) flags
|= F_INTERWORK
;
25105 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25106 if (pic_code
) flags
|= F_PIC
;
25107 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25108 flags
|= F_SOFT_FLOAT
;
25110 switch (mfloat_abi_opt
)
25112 case ARM_FLOAT_ABI_SOFT
:
25113 case ARM_FLOAT_ABI_SOFTFP
:
25114 flags
|= F_SOFT_FLOAT
;
25117 case ARM_FLOAT_ABI_HARD
:
25118 if (flags
& F_SOFT_FLOAT
)
25119 as_bad (_("hard-float conflicts with specified fpu"));
25123 /* Using pure-endian doubles (even if soft-float). */
25124 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25125 flags
|= F_VFP_FLOAT
;
25127 #if defined OBJ_ELF
25128 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25129 flags
|= EF_ARM_MAVERICK_FLOAT
;
25132 case EF_ARM_EABI_VER4
:
25133 case EF_ARM_EABI_VER5
:
25134 /* No additional flags to set. */
25141 bfd_set_private_flags (stdoutput
, flags
);
25143 /* We have run out flags in the COFF header to encode the
25144 status of ATPCS support, so instead we create a dummy,
25145 empty, debug section called .arm.atpcs. */
25150 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25154 bfd_set_section_flags
25155 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25156 bfd_set_section_size (stdoutput
, sec
, 0);
25157 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25163 /* Record the CPU type as well. */
25164 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25165 mach
= bfd_mach_arm_iWMMXt2
;
25166 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25167 mach
= bfd_mach_arm_iWMMXt
;
25168 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25169 mach
= bfd_mach_arm_XScale
;
25170 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25171 mach
= bfd_mach_arm_ep9312
;
25172 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25173 mach
= bfd_mach_arm_5TE
;
25174 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25176 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25177 mach
= bfd_mach_arm_5T
;
25179 mach
= bfd_mach_arm_5
;
25181 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25183 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25184 mach
= bfd_mach_arm_4T
;
25186 mach
= bfd_mach_arm_4
;
25188 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25189 mach
= bfd_mach_arm_3M
;
25190 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25191 mach
= bfd_mach_arm_3
;
25192 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25193 mach
= bfd_mach_arm_2a
;
25194 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25195 mach
= bfd_mach_arm_2
;
25197 mach
= bfd_mach_arm_unknown
;
25199 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25202 /* Command line processing. */
25205 Invocation line includes a switch not recognized by the base assembler.
25206 See if it's a processor-specific option.
25208 This routine is somewhat complicated by the need for backwards
25209 compatibility (since older releases of gcc can't be changed).
25210 The new options try to make the interface as compatible as
25213 New options (supported) are:
25215 -mcpu=<cpu name> Assemble for selected processor
25216 -march=<architecture name> Assemble for selected architecture
25217 -mfpu=<fpu architecture> Assemble for selected FPU.
25218 -EB/-mbig-endian Big-endian
25219 -EL/-mlittle-endian Little-endian
25220 -k Generate PIC code
25221 -mthumb Start in Thumb mode
25222 -mthumb-interwork Code supports ARM/Thumb interworking
25224 -m[no-]warn-deprecated Warn about deprecated features
25225 -m[no-]warn-syms Warn when symbols match instructions
25227 For now we will also provide support for:
25229 -mapcs-32 32-bit Program counter
25230 -mapcs-26 26-bit Program counter
25231 -macps-float Floats passed in FP registers
25232 -mapcs-reentrant Reentrant code
25234 (sometime these will probably be replaced with -mapcs=<list of options>
25235 and -matpcs=<list of options>)
25237 The remaining options are only supported for back-wards compatibility.
25238 Cpu variants, the arm part is optional:
25239 -m[arm]1 Currently not supported.
25240 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25241 -m[arm]3 Arm 3 processor
25242 -m[arm]6[xx], Arm 6 processors
25243 -m[arm]7[xx][t][[d]m] Arm 7 processors
25244 -m[arm]8[10] Arm 8 processors
25245 -m[arm]9[20][tdmi] Arm 9 processors
25246 -mstrongarm[110[0]] StrongARM processors
25247 -mxscale XScale processors
25248 -m[arm]v[2345[t[e]]] Arm architectures
25249 -mall All (except the ARM1)
25251 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25252 -mfpe-old (No float load/store multiples)
25253 -mvfpxd VFP Single precision
25255 -mno-fpu Disable all floating point instructions
25257 The following CPU names are recognized:
25258 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25259 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25260 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25261 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25262 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25263 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25264 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25268 const char * md_shortopts
= "m:k";
25270 #ifdef ARM_BI_ENDIAN
25271 #define OPTION_EB (OPTION_MD_BASE + 0)
25272 #define OPTION_EL (OPTION_MD_BASE + 1)
25274 #if TARGET_BYTES_BIG_ENDIAN
25275 #define OPTION_EB (OPTION_MD_BASE + 0)
25277 #define OPTION_EL (OPTION_MD_BASE + 1)
25280 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25282 struct option md_longopts
[] =
25285 {"EB", no_argument
, NULL
, OPTION_EB
},
25288 {"EL", no_argument
, NULL
, OPTION_EL
},
25290 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25291 {NULL
, no_argument
, NULL
, 0}
25295 size_t md_longopts_size
= sizeof (md_longopts
);
25297 struct arm_option_table
25299 const char *option
; /* Option name to match. */
25300 const char *help
; /* Help information. */
25301 int *var
; /* Variable to change. */
25302 int value
; /* What to change it to. */
25303 const char *deprecated
; /* If non-null, print this message. */
25306 struct arm_option_table arm_opts
[] =
25308 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25309 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25310 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25311 &support_interwork
, 1, NULL
},
25312 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25313 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25314 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25316 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25317 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25318 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25319 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25322 /* These are recognized by the assembler, but have no affect on code. */
25323 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25324 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25326 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25327 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25328 &warn_on_deprecated
, 0, NULL
},
25329 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25330 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25331 {NULL
, NULL
, NULL
, 0, NULL
}
25334 struct arm_legacy_option_table
25336 const char *option
; /* Option name to match. */
25337 const arm_feature_set
**var
; /* Variable to change. */
25338 const arm_feature_set value
; /* What to change it to. */
25339 const char *deprecated
; /* If non-null, print this message. */
25342 const struct arm_legacy_option_table arm_legacy_opts
[] =
25344 /* DON'T add any new processors to this list -- we want the whole list
25345 to go away... Add them to the processors table instead. */
25346 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25347 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25348 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25349 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25350 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25351 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25352 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25353 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25354 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25355 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25356 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25357 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25358 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25359 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25360 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25361 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25362 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25363 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25364 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25365 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25366 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25367 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25368 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25369 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25370 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25371 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25372 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25373 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25374 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25375 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25376 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25377 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25378 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25379 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25380 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25381 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25382 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25383 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25384 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25385 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25386 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25387 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25388 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25389 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25390 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25391 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25392 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25393 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25394 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25395 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25396 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25397 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25398 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25399 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25400 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25401 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25402 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25403 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25404 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25405 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25406 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25407 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25408 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25409 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25410 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25411 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25412 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25413 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25414 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25415 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25416 N_("use -mcpu=strongarm110")},
25417 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25418 N_("use -mcpu=strongarm1100")},
25419 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25420 N_("use -mcpu=strongarm1110")},
25421 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25422 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25423 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25425 /* Architecture variants -- don't add any more to this list either. */
25426 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25427 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25428 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25429 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25430 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25431 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25432 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25433 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25434 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25435 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25436 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25437 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25438 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25439 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25440 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25441 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25442 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25443 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25445 /* Floating point variants -- don't add any more to this list either. */
25446 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25447 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25448 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25449 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25450 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25452 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25455 struct arm_cpu_option_table
25459 const arm_feature_set value
;
25460 const arm_feature_set ext
;
25461 /* For some CPUs we assume an FPU unless the user explicitly sets
25463 const arm_feature_set default_fpu
;
25464 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25466 const char *canonical_name
;
25469 /* This list should, at a minimum, contain all the cpu names
25470 recognized by GCC. */
25471 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25472 static const struct arm_cpu_option_table arm_cpus
[] =
25474 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25477 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25480 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25483 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25486 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25489 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25492 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25495 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25498 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25501 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25504 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25507 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25510 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25513 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25516 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25519 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25522 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25525 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25528 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25531 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25534 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25537 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25540 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25543 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25546 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25549 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25552 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25555 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25558 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25561 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25564 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25567 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25570 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25573 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25576 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25579 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25582 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25585 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25588 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25591 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25594 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25597 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25600 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25603 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25606 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25609 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25613 /* For V5 or later processors we default to using VFP; but the user
25614 should really set the FPU type explicitly. */
25615 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25618 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25621 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25624 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25627 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25630 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25633 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25636 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25639 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25642 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25645 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25648 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25651 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25654 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25657 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25660 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25663 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25666 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25669 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25672 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25675 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25678 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25681 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25684 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25687 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25690 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25693 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25696 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25699 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25702 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25705 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25708 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25711 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25714 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25717 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
25720 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
25723 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
25724 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25726 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
25728 FPU_ARCH_NEON_VFP_V4
),
25729 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
25730 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25731 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25732 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
25733 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25734 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25735 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
25737 FPU_ARCH_NEON_VFP_V4
),
25738 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
25740 FPU_ARCH_NEON_VFP_V4
),
25741 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
25743 FPU_ARCH_NEON_VFP_V4
),
25744 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
25745 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25746 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25747 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
25748 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25749 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25750 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
25751 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25752 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25753 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
25754 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25755 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25756 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
25757 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25758 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25759 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
25760 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25761 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25762 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
25765 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
25767 FPU_ARCH_VFP_V3D16
),
25768 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
25769 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25771 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
25772 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25773 FPU_ARCH_VFP_V3D16
),
25774 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
25775 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25776 FPU_ARCH_VFP_V3D16
),
25777 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
25778 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25780 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
25783 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
25786 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
25789 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
25792 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
25795 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
25798 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
25801 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
25802 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25803 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25805 /* ??? XSCALE is really an architecture. */
25806 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
25810 /* ??? iwmmxt is not a processor. */
25811 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
25814 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
25817 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
25822 ARM_CPU_OPT ("ep9312", "ARM920T",
25823 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25824 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
25826 /* Marvell processors. */
25827 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
25828 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25829 FPU_ARCH_VFP_V3D16
),
25830 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
25831 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25832 FPU_ARCH_NEON_VFP_V4
),
25834 /* APM X-Gene family. */
25835 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
25837 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25838 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
25839 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25840 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25842 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25846 struct arm_arch_option_table
25850 const arm_feature_set value
;
25851 const arm_feature_set default_fpu
;
25854 /* This list should, at a minimum, contain all the architecture names
25855 recognized by GCC. */
25856 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25857 static const struct arm_arch_option_table arm_archs
[] =
25859 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25860 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25861 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25862 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25863 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25864 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25865 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25866 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25867 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25868 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25869 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25870 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25871 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25872 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25873 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25874 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25875 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25876 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25877 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25878 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25879 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25880 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25881 kept to preserve existing behaviour. */
25882 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25883 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25884 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25885 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25886 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25887 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25888 kept to preserve existing behaviour. */
25889 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25890 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25891 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25892 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25893 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25894 /* The official spelling of the ARMv7 profile variants is the dashed form.
25895 Accept the non-dashed form for compatibility with old toolchains. */
25896 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25897 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25898 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25899 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25900 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25901 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25902 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25903 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25904 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25905 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25906 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25907 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25908 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25909 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25910 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25911 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25912 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25913 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25915 #undef ARM_ARCH_OPT
25917 /* ISA extensions in the co-processor and main instruction set space. */
25918 struct arm_option_extension_value_table
25922 const arm_feature_set merge_value
;
25923 const arm_feature_set clear_value
;
25924 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25925 indicates that an extension is available for all architectures while
25926 ARM_ANY marks an empty entry. */
25927 const arm_feature_set allowed_archs
[2];
25930 /* The following table must be in alphabetical order with a NULL last entry.
25932 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25933 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25934 static const struct arm_option_extension_value_table arm_extensions
[] =
25936 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25937 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25938 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25939 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25940 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25941 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25942 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25943 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25944 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25945 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25946 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25947 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25949 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25950 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25951 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25952 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25953 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25954 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25955 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25956 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25957 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25958 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25959 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25960 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25961 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25962 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25963 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25964 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25965 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25966 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25967 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25968 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25969 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25970 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25971 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25972 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25973 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25974 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25975 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25976 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25977 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25978 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25979 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25980 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25981 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25982 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25984 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25985 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25986 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25987 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25988 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25992 /* ISA floating-point and Advanced SIMD extensions. */
25993 struct arm_option_fpu_value_table
25996 const arm_feature_set value
;
25999 /* This list should, at a minimum, contain all the fpu names
26000 recognized by GCC. */
26001 static const struct arm_option_fpu_value_table arm_fpus
[] =
26003 {"softfpa", FPU_NONE
},
26004 {"fpe", FPU_ARCH_FPE
},
26005 {"fpe2", FPU_ARCH_FPE
},
26006 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26007 {"fpa", FPU_ARCH_FPA
},
26008 {"fpa10", FPU_ARCH_FPA
},
26009 {"fpa11", FPU_ARCH_FPA
},
26010 {"arm7500fe", FPU_ARCH_FPA
},
26011 {"softvfp", FPU_ARCH_VFP
},
26012 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26013 {"vfp", FPU_ARCH_VFP_V2
},
26014 {"vfp9", FPU_ARCH_VFP_V2
},
26015 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26016 {"vfp10", FPU_ARCH_VFP_V2
},
26017 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26018 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26019 {"vfpv2", FPU_ARCH_VFP_V2
},
26020 {"vfpv3", FPU_ARCH_VFP_V3
},
26021 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26022 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26023 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26024 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26025 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26026 {"arm1020t", FPU_ARCH_VFP_V1
},
26027 {"arm1020e", FPU_ARCH_VFP_V2
},
26028 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26029 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26030 {"maverick", FPU_ARCH_MAVERICK
},
26031 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26032 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26033 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26034 {"vfpv4", FPU_ARCH_VFP_V4
},
26035 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26036 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26037 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26038 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26039 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26040 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26041 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26042 {"crypto-neon-fp-armv8",
26043 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26044 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26045 {"crypto-neon-fp-armv8.1",
26046 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26047 {NULL
, ARM_ARCH_NONE
}
26050 struct arm_option_value_table
26056 static const struct arm_option_value_table arm_float_abis
[] =
26058 {"hard", ARM_FLOAT_ABI_HARD
},
26059 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26060 {"soft", ARM_FLOAT_ABI_SOFT
},
26065 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26066 static const struct arm_option_value_table arm_eabis
[] =
26068 {"gnu", EF_ARM_EABI_UNKNOWN
},
26069 {"4", EF_ARM_EABI_VER4
},
26070 {"5", EF_ARM_EABI_VER5
},
26075 struct arm_long_option_table
26077 const char * option
; /* Substring to match. */
26078 const char * help
; /* Help information. */
26079 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26080 const char * deprecated
; /* If non-null, print this message. */
26084 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
26086 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
26088 /* We insist on extensions being specified in alphabetical order, and with
26089 extensions being added before being removed. We achieve this by having
26090 the global ARM_EXTENSIONS table in alphabetical order, and using the
26091 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26092 or removing it (0) and only allowing it to change in the order
26094 const struct arm_option_extension_value_table
* opt
= NULL
;
26095 const arm_feature_set arm_any
= ARM_ANY
;
26096 int adding_value
= -1;
26098 /* Copy the feature set, so that we can modify it. */
26099 *ext_set
= **opt_p
;
26102 while (str
!= NULL
&& *str
!= 0)
26109 as_bad (_("invalid architectural extension"));
26114 ext
= strchr (str
, '+');
26119 len
= strlen (str
);
26121 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26123 if (adding_value
!= 0)
26126 opt
= arm_extensions
;
26134 if (adding_value
== -1)
26137 opt
= arm_extensions
;
26139 else if (adding_value
!= 1)
26141 as_bad (_("must specify extensions to add before specifying "
26142 "those to remove"));
26149 as_bad (_("missing architectural extension"));
26153 gas_assert (adding_value
!= -1);
26154 gas_assert (opt
!= NULL
);
26156 /* Scan over the options table trying to find an exact match. */
26157 for (; opt
->name
!= NULL
; opt
++)
26158 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26160 int i
, nb_allowed_archs
=
26161 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26162 /* Check we can apply the extension to this architecture. */
26163 for (i
= 0; i
< nb_allowed_archs
; i
++)
26166 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26168 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
26171 if (i
== nb_allowed_archs
)
26173 as_bad (_("extension does not apply to the base architecture"));
26177 /* Add or remove the extension. */
26179 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26181 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26186 if (opt
->name
== NULL
)
26188 /* Did we fail to find an extension because it wasn't specified in
26189 alphabetical order, or because it does not exist? */
26191 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26192 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26195 if (opt
->name
== NULL
)
26196 as_bad (_("unknown architectural extension `%s'"), str
);
26198 as_bad (_("architectural extensions must be specified in "
26199 "alphabetical order"));
26205 /* We should skip the extension we've just matched the next time
26217 arm_parse_cpu (const char *str
)
26219 const struct arm_cpu_option_table
*opt
;
26220 const char *ext
= strchr (str
, '+');
26226 len
= strlen (str
);
26230 as_bad (_("missing cpu name `%s'"), str
);
26234 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26235 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26237 arm_feature_set
*cpu_set
= XNEW (arm_feature_set
);
26238 ARM_MERGE_FEATURE_SETS (*cpu_set
, opt
->value
, opt
->ext
);
26239 mcpu_cpu_opt
= cpu_set
;
26240 mcpu_fpu_opt
= &opt
->default_fpu
;
26241 if (opt
->canonical_name
)
26243 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26244 strcpy (selected_cpu_name
, opt
->canonical_name
);
26250 if (len
>= sizeof selected_cpu_name
)
26251 len
= (sizeof selected_cpu_name
) - 1;
26253 for (i
= 0; i
< len
; i
++)
26254 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26255 selected_cpu_name
[i
] = 0;
26259 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
26264 as_bad (_("unknown cpu `%s'"), str
);
26269 arm_parse_arch (const char *str
)
26271 const struct arm_arch_option_table
*opt
;
26272 const char *ext
= strchr (str
, '+');
26278 len
= strlen (str
);
26282 as_bad (_("missing architecture name `%s'"), str
);
26286 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26287 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26289 march_cpu_opt
= &opt
->value
;
26290 march_fpu_opt
= &opt
->default_fpu
;
26291 strcpy (selected_cpu_name
, opt
->name
);
26294 return arm_parse_extension (ext
, &march_cpu_opt
);
26299 as_bad (_("unknown architecture `%s'\n"), str
);
26304 arm_parse_fpu (const char * str
)
26306 const struct arm_option_fpu_value_table
* opt
;
26308 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26309 if (streq (opt
->name
, str
))
26311 mfpu_opt
= &opt
->value
;
26315 as_bad (_("unknown floating point format `%s'\n"), str
);
26320 arm_parse_float_abi (const char * str
)
26322 const struct arm_option_value_table
* opt
;
26324 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26325 if (streq (opt
->name
, str
))
26327 mfloat_abi_opt
= opt
->value
;
26331 as_bad (_("unknown floating point abi `%s'\n"), str
);
26337 arm_parse_eabi (const char * str
)
26339 const struct arm_option_value_table
*opt
;
26341 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26342 if (streq (opt
->name
, str
))
26344 meabi_flags
= opt
->value
;
26347 as_bad (_("unknown EABI `%s'\n"), str
);
26353 arm_parse_it_mode (const char * str
)
26355 bfd_boolean ret
= TRUE
;
26357 if (streq ("arm", str
))
26358 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26359 else if (streq ("thumb", str
))
26360 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26361 else if (streq ("always", str
))
26362 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26363 else if (streq ("never", str
))
26364 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26367 as_bad (_("unknown implicit IT mode `%s', should be "\
26368 "arm, thumb, always, or never."), str
);
26376 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26378 codecomposer_syntax
= TRUE
;
26379 arm_comment_chars
[0] = ';';
26380 arm_line_separator_chars
[0] = 0;
26384 struct arm_long_option_table arm_long_opts
[] =
26386 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26387 arm_parse_cpu
, NULL
},
26388 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26389 arm_parse_arch
, NULL
},
26390 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26391 arm_parse_fpu
, NULL
},
26392 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26393 arm_parse_float_abi
, NULL
},
26395 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26396 arm_parse_eabi
, NULL
},
26398 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26399 arm_parse_it_mode
, NULL
},
26400 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26401 arm_ccs_mode
, NULL
},
26402 {NULL
, NULL
, 0, NULL
}
26406 md_parse_option (int c
, const char * arg
)
26408 struct arm_option_table
*opt
;
26409 const struct arm_legacy_option_table
*fopt
;
26410 struct arm_long_option_table
*lopt
;
26416 target_big_endian
= 1;
26422 target_big_endian
= 0;
26426 case OPTION_FIX_V4BX
:
26431 /* Listing option. Just ignore these, we don't support additional
26436 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26438 if (c
== opt
->option
[0]
26439 && ((arg
== NULL
&& opt
->option
[1] == 0)
26440 || streq (arg
, opt
->option
+ 1)))
26442 /* If the option is deprecated, tell the user. */
26443 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26444 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26445 arg
? arg
: "", _(opt
->deprecated
));
26447 if (opt
->var
!= NULL
)
26448 *opt
->var
= opt
->value
;
26454 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26456 if (c
== fopt
->option
[0]
26457 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26458 || streq (arg
, fopt
->option
+ 1)))
26460 /* If the option is deprecated, tell the user. */
26461 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26462 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26463 arg
? arg
: "", _(fopt
->deprecated
));
26465 if (fopt
->var
!= NULL
)
26466 *fopt
->var
= &fopt
->value
;
26472 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26474 /* These options are expected to have an argument. */
26475 if (c
== lopt
->option
[0]
26477 && strncmp (arg
, lopt
->option
+ 1,
26478 strlen (lopt
->option
+ 1)) == 0)
26480 /* If the option is deprecated, tell the user. */
26481 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26482 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26483 _(lopt
->deprecated
));
26485 /* Call the sup-option parser. */
26486 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26497 md_show_usage (FILE * fp
)
26499 struct arm_option_table
*opt
;
26500 struct arm_long_option_table
*lopt
;
26502 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26504 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26505 if (opt
->help
!= NULL
)
26506 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26508 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26509 if (lopt
->help
!= NULL
)
26510 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26514 -EB assemble code for a big-endian cpu\n"));
26519 -EL assemble code for a little-endian cpu\n"));
26523 --fix-v4bx Allow BX in ARMv4 code\n"));
26531 arm_feature_set flags
;
26532 } cpu_arch_ver_table
;
26534 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26535 must be sorted least features first but some reordering is needed, eg. for
26536 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26537 static const cpu_arch_ver_table cpu_arch_ver
[] =
26543 {4, ARM_ARCH_V5TE
},
26544 {5, ARM_ARCH_V5TEJ
},
26548 {11, ARM_ARCH_V6M
},
26549 {12, ARM_ARCH_V6SM
},
26550 {8, ARM_ARCH_V6T2
},
26551 {10, ARM_ARCH_V7VE
},
26552 {10, ARM_ARCH_V7R
},
26553 {10, ARM_ARCH_V7M
},
26554 {14, ARM_ARCH_V8A
},
26555 {16, ARM_ARCH_V8M_BASE
},
26556 {17, ARM_ARCH_V8M_MAIN
},
26560 /* Set an attribute if it has not already been set by the user. */
26562 aeabi_set_attribute_int (int tag
, int value
)
26565 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26566 || !attributes_set_explicitly
[tag
])
26567 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26571 aeabi_set_attribute_string (int tag
, const char *value
)
26574 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26575 || !attributes_set_explicitly
[tag
])
26576 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26579 /* Set the public EABI object attributes. */
26581 aeabi_set_public_attributes (void)
26586 int fp16_optional
= 0;
26587 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26588 arm_feature_set flags
;
26589 arm_feature_set tmp
;
26590 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26591 const cpu_arch_ver_table
*p
;
26593 /* Choose the architecture based on the capabilities of the requested cpu
26594 (if any) and/or the instructions actually used. */
26595 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26596 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26597 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26599 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26600 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26602 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26603 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26605 selected_cpu
= flags
;
26607 /* Allow the user to override the reported architecture. */
26610 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26611 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26614 /* We need to make sure that the attributes do not identify us as v6S-M
26615 when the only v6S-M feature in use is the Operating System Extensions. */
26616 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26617 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26618 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26622 for (p
= cpu_arch_ver
; p
->val
; p
++)
26624 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26627 arm_arch
= p
->flags
;
26628 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26632 /* The table lookup above finds the last architecture to contribute
26633 a new feature. Unfortunately, Tag13 is a subset of the union of
26634 v6T2 and v7-M, so it is never seen as contributing a new feature.
26635 We can not search for the last entry which is entirely used,
26636 because if no CPU is specified we build up only those flags
26637 actually used. Perhaps we should separate out the specified
26638 and implicit cases. Avoid taking this path for -march=all by
26639 checking for contradictory v7-A / v7-M features. */
26640 if (arch
== TAG_CPU_ARCH_V7
26641 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26642 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26643 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26645 arch
= TAG_CPU_ARCH_V7E_M
;
26646 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26649 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26650 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26652 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26653 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26656 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26657 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26658 ARMv8-M, -march=all must be detected as ARMv8-A. */
26659 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26660 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26662 arch
= TAG_CPU_ARCH_V8
;
26663 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26666 /* Tag_CPU_name. */
26667 if (selected_cpu_name
[0])
26671 q
= selected_cpu_name
;
26672 if (strncmp (q
, "armv", 4) == 0)
26677 for (i
= 0; q
[i
]; i
++)
26678 q
[i
] = TOUPPER (q
[i
]);
26680 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26683 /* Tag_CPU_arch. */
26684 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26686 /* Tag_CPU_arch_profile. */
26687 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26688 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26689 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26690 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26692 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26694 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26699 if (profile
!= '\0')
26700 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26702 /* Tag_DSP_extension. */
26703 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26705 arm_feature_set ext
;
26707 /* DSP instructions not in architecture. */
26708 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26709 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26710 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26713 /* Tag_ARM_ISA_use. */
26714 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26716 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26718 /* Tag_THUMB_ISA_use. */
26719 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26724 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26725 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26727 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26731 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26734 /* Tag_VFP_arch. */
26735 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26736 aeabi_set_attribute_int (Tag_VFP_arch
,
26737 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26739 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26740 aeabi_set_attribute_int (Tag_VFP_arch
,
26741 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26743 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26746 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26748 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26750 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26753 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26754 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26755 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26756 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26757 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26759 /* Tag_ABI_HardFP_use. */
26760 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26761 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26762 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26764 /* Tag_WMMX_arch. */
26765 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26766 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26767 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26768 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26770 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26771 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26772 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26773 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26774 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26775 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26777 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26779 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26783 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26788 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26789 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26790 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26794 We set Tag_DIV_use to two when integer divide instructions have been used
26795 in ARM state, or when Thumb integer divide instructions have been used,
26796 but we have no architecture profile set, nor have we any ARM instructions.
26798 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26799 by the base architecture.
26801 For new architectures we will have to check these tests. */
26802 gas_assert (arch
<= TAG_CPU_ARCH_V8
26803 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26804 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26805 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26806 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26807 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26808 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26809 || (profile
== '\0'
26810 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26811 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26812 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26814 /* Tag_MP_extension_use. */
26815 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26816 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26818 /* Tag Virtualization_use. */
26819 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26821 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26824 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26827 /* Add the default contents for the .ARM.attributes section. */
26831 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26834 aeabi_set_public_attributes ();
26836 #endif /* OBJ_ELF */
26839 /* Parse a .cpu directive. */
26842 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26844 const struct arm_cpu_option_table
*opt
;
26848 name
= input_line_pointer
;
26849 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26850 input_line_pointer
++;
26851 saved_char
= *input_line_pointer
;
26852 *input_line_pointer
= 0;
26854 /* Skip the first "all" entry. */
26855 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26856 if (streq (opt
->name
, name
))
26858 arm_feature_set
*cpu_set
= XNEW (arm_feature_set
);
26859 ARM_MERGE_FEATURE_SETS (*cpu_set
, opt
->value
, opt
->ext
);
26860 mcpu_cpu_opt
= cpu_set
;
26861 selected_cpu
= *mcpu_cpu_opt
;
26862 if (opt
->canonical_name
)
26863 strcpy (selected_cpu_name
, opt
->canonical_name
);
26867 for (i
= 0; opt
->name
[i
]; i
++)
26868 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26870 selected_cpu_name
[i
] = 0;
26872 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26873 *input_line_pointer
= saved_char
;
26874 demand_empty_rest_of_line ();
26877 as_bad (_("unknown cpu `%s'"), name
);
26878 *input_line_pointer
= saved_char
;
26879 ignore_rest_of_line ();
26883 /* Parse a .arch directive. */
26886 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26888 const struct arm_arch_option_table
*opt
;
26892 name
= input_line_pointer
;
26893 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26894 input_line_pointer
++;
26895 saved_char
= *input_line_pointer
;
26896 *input_line_pointer
= 0;
26898 /* Skip the first "all" entry. */
26899 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26900 if (streq (opt
->name
, name
))
26902 mcpu_cpu_opt
= &opt
->value
;
26903 selected_cpu
= opt
->value
;
26904 strcpy (selected_cpu_name
, opt
->name
);
26905 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26906 *input_line_pointer
= saved_char
;
26907 demand_empty_rest_of_line ();
26911 as_bad (_("unknown architecture `%s'\n"), name
);
26912 *input_line_pointer
= saved_char
;
26913 ignore_rest_of_line ();
26917 /* Parse a .object_arch directive. */
26920 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26922 const struct arm_arch_option_table
*opt
;
26926 name
= input_line_pointer
;
26927 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26928 input_line_pointer
++;
26929 saved_char
= *input_line_pointer
;
26930 *input_line_pointer
= 0;
26932 /* Skip the first "all" entry. */
26933 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26934 if (streq (opt
->name
, name
))
26936 object_arch
= &opt
->value
;
26937 *input_line_pointer
= saved_char
;
26938 demand_empty_rest_of_line ();
26942 as_bad (_("unknown architecture `%s'\n"), name
);
26943 *input_line_pointer
= saved_char
;
26944 ignore_rest_of_line ();
26947 /* Parse a .arch_extension directive. */
26950 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26952 const struct arm_option_extension_value_table
*opt
;
26953 const arm_feature_set arm_any
= ARM_ANY
;
26956 int adding_value
= 1;
26958 name
= input_line_pointer
;
26959 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26960 input_line_pointer
++;
26961 saved_char
= *input_line_pointer
;
26962 *input_line_pointer
= 0;
26964 if (strlen (name
) >= 2
26965 && strncmp (name
, "no", 2) == 0)
26971 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26972 if (streq (opt
->name
, name
))
26974 int i
, nb_allowed_archs
=
26975 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26976 for (i
= 0; i
< nb_allowed_archs
; i
++)
26979 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26981 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26985 if (i
== nb_allowed_archs
)
26987 as_bad (_("architectural extension `%s' is not allowed for the "
26988 "current base architecture"), name
);
26993 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26996 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26998 mcpu_cpu_opt
= &selected_cpu
;
26999 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27000 *input_line_pointer
= saved_char
;
27001 demand_empty_rest_of_line ();
27005 if (opt
->name
== NULL
)
27006 as_bad (_("unknown architecture extension `%s'\n"), name
);
27008 *input_line_pointer
= saved_char
;
27009 ignore_rest_of_line ();
27012 /* Parse a .fpu directive. */
27015 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27017 const struct arm_option_fpu_value_table
*opt
;
27021 name
= input_line_pointer
;
27022 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27023 input_line_pointer
++;
27024 saved_char
= *input_line_pointer
;
27025 *input_line_pointer
= 0;
27027 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27028 if (streq (opt
->name
, name
))
27030 mfpu_opt
= &opt
->value
;
27031 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27032 *input_line_pointer
= saved_char
;
27033 demand_empty_rest_of_line ();
27037 as_bad (_("unknown floating point format `%s'\n"), name
);
27038 *input_line_pointer
= saved_char
;
27039 ignore_rest_of_line ();
27042 /* Copy symbol information. */
27045 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27047 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27051 /* Given a symbolic attribute NAME, return the proper integer value.
27052 Returns -1 if the attribute is not known. */
27055 arm_convert_symbolic_attribute (const char *name
)
27057 static const struct
27062 attribute_table
[] =
27064 /* When you modify this table you should
27065 also modify the list in doc/c-arm.texi. */
27066 #define T(tag) {#tag, tag}
27067 T (Tag_CPU_raw_name
),
27070 T (Tag_CPU_arch_profile
),
27071 T (Tag_ARM_ISA_use
),
27072 T (Tag_THUMB_ISA_use
),
27076 T (Tag_Advanced_SIMD_arch
),
27077 T (Tag_PCS_config
),
27078 T (Tag_ABI_PCS_R9_use
),
27079 T (Tag_ABI_PCS_RW_data
),
27080 T (Tag_ABI_PCS_RO_data
),
27081 T (Tag_ABI_PCS_GOT_use
),
27082 T (Tag_ABI_PCS_wchar_t
),
27083 T (Tag_ABI_FP_rounding
),
27084 T (Tag_ABI_FP_denormal
),
27085 T (Tag_ABI_FP_exceptions
),
27086 T (Tag_ABI_FP_user_exceptions
),
27087 T (Tag_ABI_FP_number_model
),
27088 T (Tag_ABI_align_needed
),
27089 T (Tag_ABI_align8_needed
),
27090 T (Tag_ABI_align_preserved
),
27091 T (Tag_ABI_align8_preserved
),
27092 T (Tag_ABI_enum_size
),
27093 T (Tag_ABI_HardFP_use
),
27094 T (Tag_ABI_VFP_args
),
27095 T (Tag_ABI_WMMX_args
),
27096 T (Tag_ABI_optimization_goals
),
27097 T (Tag_ABI_FP_optimization_goals
),
27098 T (Tag_compatibility
),
27099 T (Tag_CPU_unaligned_access
),
27100 T (Tag_FP_HP_extension
),
27101 T (Tag_VFP_HP_extension
),
27102 T (Tag_ABI_FP_16bit_format
),
27103 T (Tag_MPextension_use
),
27105 T (Tag_nodefaults
),
27106 T (Tag_also_compatible_with
),
27107 T (Tag_conformance
),
27109 T (Tag_Virtualization_use
),
27110 T (Tag_DSP_extension
),
27111 /* We deliberately do not include Tag_MPextension_use_legacy. */
27119 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27120 if (streq (name
, attribute_table
[i
].name
))
27121 return attribute_table
[i
].tag
;
27127 /* Apply sym value for relocations only in the case that they are for
27128 local symbols in the same segment as the fixup and you have the
27129 respective architectural feature for blx and simple switches. */
27131 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27134 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27135 /* PR 17444: If the local symbol is in a different section then a reloc
27136 will always be generated for it, so applying the symbol value now
27137 will result in a double offset being stored in the relocation. */
27138 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27139 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27141 switch (fixP
->fx_r_type
)
27143 case BFD_RELOC_ARM_PCREL_BLX
:
27144 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27145 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27149 case BFD_RELOC_ARM_PCREL_CALL
:
27150 case BFD_RELOC_THUMB_PCREL_BLX
:
27151 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27162 #endif /* OBJ_ELF */