1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
*dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static arm_feature_set
*dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
*march_fpu_opt
= NULL
;
155 static const arm_feature_set
*mfpu_opt
= NULL
;
156 static const arm_feature_set
*object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_v8_3
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
241 static const arm_feature_set arm_arch_any
= ARM_ANY
;
243 static const arm_feature_set fpu_any
= FPU_ANY
;
245 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
246 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
247 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
249 static const arm_feature_set arm_cext_iwmmxt2
=
250 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
251 static const arm_feature_set arm_cext_iwmmxt
=
252 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
253 static const arm_feature_set arm_cext_xscale
=
254 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
255 static const arm_feature_set arm_cext_maverick
=
256 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
257 static const arm_feature_set fpu_fpa_ext_v1
=
258 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
259 static const arm_feature_set fpu_fpa_ext_v2
=
260 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
261 static const arm_feature_set fpu_vfp_ext_v1xd
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
263 static const arm_feature_set fpu_vfp_ext_v1
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
265 static const arm_feature_set fpu_vfp_ext_v2
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
267 static const arm_feature_set fpu_vfp_ext_v3xd
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
269 static const arm_feature_set fpu_vfp_ext_v3
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
271 static const arm_feature_set fpu_vfp_ext_d32
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
273 static const arm_feature_set fpu_neon_ext_v1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
275 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
276 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
278 static const arm_feature_set fpu_vfp_fp16
=
279 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
280 static const arm_feature_set fpu_neon_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
283 static const arm_feature_set fpu_vfp_ext_fma
=
284 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
285 static const arm_feature_set fpu_vfp_ext_armv8
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
287 static const arm_feature_set fpu_vfp_ext_armv8xd
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
289 static const arm_feature_set fpu_neon_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
291 static const arm_feature_set fpu_crypto_ext_armv8
=
292 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
293 static const arm_feature_set crc_ext_armv8
=
294 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
295 static const arm_feature_set fpu_neon_ext_v8_1
=
296 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static const arm_feature_set fpu_neon_ext_dotprod
=
298 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
300 static int mfloat_abi_opt
= -1;
301 /* Record user cpu selection for object attributes. */
302 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
303 /* Must be long enough to hold any of the names in arm_cpus. */
304 static char selected_cpu_name
[20];
306 extern FLONUM_TYPE generic_floating_point_number
;
308 /* Return if no cpu was selected on command-line. */
310 no_cpu_selected (void)
312 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
317 static int meabi_flags
= EABI_DEFAULT
;
319 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
322 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
327 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
332 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
333 symbolS
* GOT_symbol
;
336 /* 0: assemble for ARM,
337 1: assemble for Thumb,
338 2: assemble for Thumb even though target CPU does not support thumb
340 static int thumb_mode
= 0;
341 /* A value distinct from the possible values for thumb_mode that we
342 can use to record whether thumb_mode has been copied into the
343 tc_frag_data field of a frag. */
344 #define MODE_RECORDED (1 << 4)
346 /* Specifies the intrinsic IT insn behavior mode. */
347 enum implicit_it_mode
349 IMPLICIT_IT_MODE_NEVER
= 0x00,
350 IMPLICIT_IT_MODE_ARM
= 0x01,
351 IMPLICIT_IT_MODE_THUMB
= 0x02,
352 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
354 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
356 /* If unified_syntax is true, we are processing the new unified
357 ARM/Thumb syntax. Important differences from the old ARM mode:
359 - Immediate operands do not require a # prefix.
360 - Conditional affixes always appear at the end of the
361 instruction. (For backward compatibility, those instructions
362 that formerly had them in the middle, continue to accept them
364 - The IT instruction may appear, and if it does is validated
365 against subsequent conditional affixes. It does not generate
368 Important differences from the old Thumb mode:
370 - Immediate operands do not require a # prefix.
371 - Most of the V6T2 instructions are only available in unified mode.
372 - The .N and .W suffixes are recognized and honored (it is an error
373 if they cannot be honored).
374 - All instructions set the flags if and only if they have an 's' affix.
375 - Conditional affixes may be used. They are validated against
376 preceding IT instructions. Unlike ARM mode, you cannot use a
377 conditional affix except in the scope of an IT instruction. */
379 static bfd_boolean unified_syntax
= FALSE
;
381 /* An immediate operand can start with #, and ld*, st*, pld operands
382 can contain [ and ]. We need to tell APP not to elide whitespace
383 before a [, which can appear as the first operand for pld.
384 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
385 const char arm_symbol_chars
[] = "#[]{}";
400 enum neon_el_type type
;
404 #define NEON_MAX_TYPE_ELS 4
408 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
412 enum it_instruction_type
417 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
418 if inside, should be the last one. */
419 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
420 i.e. BKPT and NOP. */
421 IT_INSN
/* The IT insn has been parsed. */
424 /* The maximum number of operands we need. */
425 #define ARM_IT_MAX_OPERANDS 6
430 unsigned long instruction
;
434 /* "uncond_value" is set to the value in place of the conditional field in
435 unconditional versions of the instruction, or -1 if nothing is
438 struct neon_type vectype
;
439 /* This does not indicate an actual NEON instruction, only that
440 the mnemonic accepts neon-style type suffixes. */
442 /* Set to the opcode if the instruction needs relaxation.
443 Zero if the instruction is not relaxed. */
447 bfd_reloc_code_real_type type
;
452 enum it_instruction_type it_insn_type
;
458 struct neon_type_el vectype
;
459 unsigned present
: 1; /* Operand present. */
460 unsigned isreg
: 1; /* Operand was a register. */
461 unsigned immisreg
: 1; /* .imm field is a second register. */
462 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
463 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
464 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
465 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
466 instructions. This allows us to disambiguate ARM <-> vector insns. */
467 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
468 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
469 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
470 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
471 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
472 unsigned writeback
: 1; /* Operand has trailing ! */
473 unsigned preind
: 1; /* Preindexed address. */
474 unsigned postind
: 1; /* Postindexed address. */
475 unsigned negative
: 1; /* Index register was negated. */
476 unsigned shifted
: 1; /* Shift applied to operation. */
477 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
478 } operands
[ARM_IT_MAX_OPERANDS
];
481 static struct arm_it inst
;
483 #define NUM_FLOAT_VALS 8
485 const char * fp_const
[] =
487 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
490 /* Number of littlenums required to hold an extended precision number. */
491 #define MAX_LITTLENUMS 6
493 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
503 #define CP_T_X 0x00008000
504 #define CP_T_Y 0x00400000
506 #define CONDS_BIT 0x00100000
507 #define LOAD_BIT 0x00100000
509 #define DOUBLE_LOAD_FLAG 0x00000001
513 const char * template_name
;
517 #define COND_ALWAYS 0xE
521 const char * template_name
;
525 struct asm_barrier_opt
527 const char * template_name
;
529 const arm_feature_set arch
;
532 /* The bit that distinguishes CPSR and SPSR. */
533 #define SPSR_BIT (1 << 22)
535 /* The individual PSR flag bits. */
536 #define PSR_c (1 << 16)
537 #define PSR_x (1 << 17)
538 #define PSR_s (1 << 18)
539 #define PSR_f (1 << 19)
544 bfd_reloc_code_real_type reloc
;
549 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
550 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
555 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
558 /* Bits for DEFINED field in neon_typed_alias. */
559 #define NTA_HASTYPE 1
560 #define NTA_HASINDEX 2
562 struct neon_typed_alias
564 unsigned char defined
;
566 struct neon_type_el eltype
;
569 /* ARM register categories. This includes coprocessor numbers and various
570 architecture extensions' registers. */
597 /* Structure for a hash table entry for a register.
598 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
599 information which states whether a vector type or index is specified (for a
600 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
606 unsigned char builtin
;
607 struct neon_typed_alias
* neon
;
610 /* Diagnostics used when we don't get a register of the expected type. */
611 const char * const reg_expected_msgs
[] =
613 N_("ARM register expected"),
614 N_("bad or missing co-processor number"),
615 N_("co-processor register expected"),
616 N_("FPA register expected"),
617 N_("VFP single precision register expected"),
618 N_("VFP/Neon double precision register expected"),
619 N_("Neon quad precision register expected"),
620 N_("VFP single or double precision register expected"),
621 N_("Neon double or quad precision register expected"),
622 N_("VFP single, double or Neon quad precision register expected"),
623 N_("VFP system register expected"),
624 N_("Maverick MVF register expected"),
625 N_("Maverick MVD register expected"),
626 N_("Maverick MVFX register expected"),
627 N_("Maverick MVDX register expected"),
628 N_("Maverick MVAX register expected"),
629 N_("Maverick DSPSC register expected"),
630 N_("iWMMXt data register expected"),
631 N_("iWMMXt control register expected"),
632 N_("iWMMXt scalar register expected"),
633 N_("XScale accumulator register expected"),
636 /* Some well known registers that we refer to directly elsewhere. */
642 /* ARM instructions take 4bytes in the object file, Thumb instructions
648 /* Basic string to match. */
649 const char * template_name
;
651 /* Parameters to instruction. */
652 unsigned int operands
[8];
654 /* Conditional tag - see opcode_lookup. */
655 unsigned int tag
: 4;
657 /* Basic instruction code. */
658 unsigned int avalue
: 28;
660 /* Thumb-format instruction code. */
663 /* Which architecture variant provides this instruction. */
664 const arm_feature_set
* avariant
;
665 const arm_feature_set
* tvariant
;
667 /* Function to call to encode instruction in ARM format. */
668 void (* aencode
) (void);
670 /* Function to call to encode instruction in Thumb format. */
671 void (* tencode
) (void);
674 /* Defines for various bits that we will want to toggle. */
675 #define INST_IMMEDIATE 0x02000000
676 #define OFFSET_REG 0x02000000
677 #define HWOFFSET_IMM 0x00400000
678 #define SHIFT_BY_REG 0x00000010
679 #define PRE_INDEX 0x01000000
680 #define INDEX_UP 0x00800000
681 #define WRITE_BACK 0x00200000
682 #define LDM_TYPE_2_OR_3 0x00400000
683 #define CPSI_MMOD 0x00020000
685 #define LITERAL_MASK 0xf000f000
686 #define OPCODE_MASK 0xfe1fffff
687 #define V4_STR_BIT 0x00000020
688 #define VLDR_VMOV_SAME 0x0040f000
690 #define T2_SUBS_PC_LR 0xf3de8f00
692 #define DATA_OP_SHIFT 21
693 #define SBIT_SHIFT 20
695 #define T2_OPCODE_MASK 0xfe1fffff
696 #define T2_DATA_OP_SHIFT 21
697 #define T2_SBIT_SHIFT 20
699 #define A_COND_MASK 0xf0000000
700 #define A_PUSH_POP_OP_MASK 0x0fff0000
702 /* Opcodes for pushing/poping registers to/from the stack. */
703 #define A1_OPCODE_PUSH 0x092d0000
704 #define A2_OPCODE_PUSH 0x052d0004
705 #define A2_OPCODE_POP 0x049d0004
707 /* Codes to distinguish the arithmetic instructions. */
718 #define OPCODE_CMP 10
719 #define OPCODE_CMN 11
720 #define OPCODE_ORR 12
721 #define OPCODE_MOV 13
722 #define OPCODE_BIC 14
723 #define OPCODE_MVN 15
725 #define T2_OPCODE_AND 0
726 #define T2_OPCODE_BIC 1
727 #define T2_OPCODE_ORR 2
728 #define T2_OPCODE_ORN 3
729 #define T2_OPCODE_EOR 4
730 #define T2_OPCODE_ADD 8
731 #define T2_OPCODE_ADC 10
732 #define T2_OPCODE_SBC 11
733 #define T2_OPCODE_SUB 13
734 #define T2_OPCODE_RSB 14
736 #define T_OPCODE_MUL 0x4340
737 #define T_OPCODE_TST 0x4200
738 #define T_OPCODE_CMN 0x42c0
739 #define T_OPCODE_NEG 0x4240
740 #define T_OPCODE_MVN 0x43c0
742 #define T_OPCODE_ADD_R3 0x1800
743 #define T_OPCODE_SUB_R3 0x1a00
744 #define T_OPCODE_ADD_HI 0x4400
745 #define T_OPCODE_ADD_ST 0xb000
746 #define T_OPCODE_SUB_ST 0xb080
747 #define T_OPCODE_ADD_SP 0xa800
748 #define T_OPCODE_ADD_PC 0xa000
749 #define T_OPCODE_ADD_I8 0x3000
750 #define T_OPCODE_SUB_I8 0x3800
751 #define T_OPCODE_ADD_I3 0x1c00
752 #define T_OPCODE_SUB_I3 0x1e00
754 #define T_OPCODE_ASR_R 0x4100
755 #define T_OPCODE_LSL_R 0x4080
756 #define T_OPCODE_LSR_R 0x40c0
757 #define T_OPCODE_ROR_R 0x41c0
758 #define T_OPCODE_ASR_I 0x1000
759 #define T_OPCODE_LSL_I 0x0000
760 #define T_OPCODE_LSR_I 0x0800
762 #define T_OPCODE_MOV_I8 0x2000
763 #define T_OPCODE_CMP_I8 0x2800
764 #define T_OPCODE_CMP_LR 0x4280
765 #define T_OPCODE_MOV_HR 0x4600
766 #define T_OPCODE_CMP_HR 0x4500
768 #define T_OPCODE_LDR_PC 0x4800
769 #define T_OPCODE_LDR_SP 0x9800
770 #define T_OPCODE_STR_SP 0x9000
771 #define T_OPCODE_LDR_IW 0x6800
772 #define T_OPCODE_STR_IW 0x6000
773 #define T_OPCODE_LDR_IH 0x8800
774 #define T_OPCODE_STR_IH 0x8000
775 #define T_OPCODE_LDR_IB 0x7800
776 #define T_OPCODE_STR_IB 0x7000
777 #define T_OPCODE_LDR_RW 0x5800
778 #define T_OPCODE_STR_RW 0x5000
779 #define T_OPCODE_LDR_RH 0x5a00
780 #define T_OPCODE_STR_RH 0x5200
781 #define T_OPCODE_LDR_RB 0x5c00
782 #define T_OPCODE_STR_RB 0x5400
784 #define T_OPCODE_PUSH 0xb400
785 #define T_OPCODE_POP 0xbc00
787 #define T_OPCODE_BRANCH 0xe000
789 #define THUMB_SIZE 2 /* Size of thumb instruction. */
790 #define THUMB_PP_PC_LR 0x0100
791 #define THUMB_LOAD_BIT 0x0800
792 #define THUMB2_LOAD_BIT 0x00100000
794 #define BAD_ARGS _("bad arguments to instruction")
795 #define BAD_SP _("r13 not allowed here")
796 #define BAD_PC _("r15 not allowed here")
797 #define BAD_COND _("instruction cannot be conditional")
798 #define BAD_OVERLAP _("registers may not be the same")
799 #define BAD_HIREG _("lo register required")
800 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
801 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
802 #define BAD_BRANCH _("branch must be last instruction in IT block")
803 #define BAD_NOT_IT _("instruction not allowed in IT block")
804 #define BAD_FPU _("selected FPU does not support instruction")
805 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
806 #define BAD_IT_COND _("incorrect condition in IT block")
807 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
808 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
809 #define BAD_PC_ADDRESSING \
810 _("cannot use register index with PC-relative addressing")
811 #define BAD_PC_WRITEBACK \
812 _("cannot use writeback with PC-relative addressing")
813 #define BAD_RANGE _("branch out of range")
814 #define BAD_FP16 _("selected processor does not support fp16 instruction")
815 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
816 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
818 static struct hash_control
* arm_ops_hsh
;
819 static struct hash_control
* arm_cond_hsh
;
820 static struct hash_control
* arm_shift_hsh
;
821 static struct hash_control
* arm_psr_hsh
;
822 static struct hash_control
* arm_v7m_psr_hsh
;
823 static struct hash_control
* arm_reg_hsh
;
824 static struct hash_control
* arm_reloc_hsh
;
825 static struct hash_control
* arm_barrier_opt_hsh
;
827 /* Stuff needed to resolve the label ambiguity
836 symbolS
* last_label_seen
;
837 static int label_is_thumb_function_name
= FALSE
;
839 /* Literal pool structure. Held on a per-section
840 and per-sub-section basis. */
842 #define MAX_LITERAL_POOL_SIZE 1024
843 typedef struct literal_pool
845 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
846 unsigned int next_free_entry
;
852 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
854 struct literal_pool
* next
;
855 unsigned int alignment
;
858 /* Pointer to a linked list of literal pools. */
859 literal_pool
* list_of_pools
= NULL
;
861 typedef enum asmfunc_states
864 WAITING_ASMFUNC_NAME
,
868 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
871 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
873 static struct current_it now_it
;
877 now_it_compatible (int cond
)
879 return (cond
& ~1) == (now_it
.cc
& ~1);
883 conditional_insn (void)
885 return inst
.cond
!= COND_ALWAYS
;
888 static int in_it_block (void);
890 static int handle_it_state (void);
892 static void force_automatic_it_block_close (void);
894 static void it_fsm_post_encode (void);
896 #define set_it_insn_type(type) \
899 inst.it_insn_type = type; \
900 if (handle_it_state () == FAIL) \
905 #define set_it_insn_type_nonvoid(type, failret) \
908 inst.it_insn_type = type; \
909 if (handle_it_state () == FAIL) \
914 #define set_it_insn_type_last() \
917 if (inst.cond == COND_ALWAYS) \
918 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
920 set_it_insn_type (INSIDE_IT_LAST_INSN); \
926 /* This array holds the chars that always start a comment. If the
927 pre-processor is disabled, these aren't very useful. */
928 char arm_comment_chars
[] = "@";
930 /* This array holds the chars that only start a comment at the beginning of
931 a line. If the line seems to have the form '# 123 filename'
932 .line and .file directives will appear in the pre-processed output. */
933 /* Note that input_file.c hand checks for '#' at the beginning of the
934 first line of the input file. This is because the compiler outputs
935 #NO_APP at the beginning of its output. */
936 /* Also note that comments like this one will always work. */
937 const char line_comment_chars
[] = "#";
939 char arm_line_separator_chars
[] = ";";
941 /* Chars that can be used to separate mant
942 from exp in floating point numbers. */
943 const char EXP_CHARS
[] = "eE";
945 /* Chars that mean this number is a floating point constant. */
949 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
951 /* Prefix characters that indicate the start of an immediate
953 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
955 /* Separator character handling. */
957 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
960 skip_past_char (char ** str
, char c
)
962 /* PR gas/14987: Allow for whitespace before the expected character. */
963 skip_whitespace (*str
);
974 #define skip_past_comma(str) skip_past_char (str, ',')
976 /* Arithmetic expressions (possibly involving symbols). */
978 /* Return TRUE if anything in the expression is a bignum. */
981 walk_no_bignums (symbolS
* sp
)
983 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
986 if (symbol_get_value_expression (sp
)->X_add_symbol
)
988 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
989 || (symbol_get_value_expression (sp
)->X_op_symbol
990 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
996 static int in_my_get_expression
= 0;
998 /* Third argument to my_get_expression. */
999 #define GE_NO_PREFIX 0
1000 #define GE_IMM_PREFIX 1
1001 #define GE_OPT_PREFIX 2
1002 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1003 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1004 #define GE_OPT_PREFIX_BIG 3
1007 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1012 /* In unified syntax, all prefixes are optional. */
1014 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1017 switch (prefix_mode
)
1019 case GE_NO_PREFIX
: break;
1021 if (!is_immediate_prefix (**str
))
1023 inst
.error
= _("immediate expression requires a # prefix");
1029 case GE_OPT_PREFIX_BIG
:
1030 if (is_immediate_prefix (**str
))
1036 memset (ep
, 0, sizeof (expressionS
));
1038 save_in
= input_line_pointer
;
1039 input_line_pointer
= *str
;
1040 in_my_get_expression
= 1;
1041 seg
= expression (ep
);
1042 in_my_get_expression
= 0;
1044 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1046 /* We found a bad or missing expression in md_operand(). */
1047 *str
= input_line_pointer
;
1048 input_line_pointer
= save_in
;
1049 if (inst
.error
== NULL
)
1050 inst
.error
= (ep
->X_op
== O_absent
1051 ? _("missing expression") :_("bad expression"));
1056 if (seg
!= absolute_section
1057 && seg
!= text_section
1058 && seg
!= data_section
1059 && seg
!= bss_section
1060 && seg
!= undefined_section
)
1062 inst
.error
= _("bad segment");
1063 *str
= input_line_pointer
;
1064 input_line_pointer
= save_in
;
1071 /* Get rid of any bignums now, so that we don't generate an error for which
1072 we can't establish a line number later on. Big numbers are never valid
1073 in instructions, which is where this routine is always called. */
1074 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1075 && (ep
->X_op
== O_big
1076 || (ep
->X_add_symbol
1077 && (walk_no_bignums (ep
->X_add_symbol
)
1079 && walk_no_bignums (ep
->X_op_symbol
))))))
1081 inst
.error
= _("invalid constant");
1082 *str
= input_line_pointer
;
1083 input_line_pointer
= save_in
;
1087 *str
= input_line_pointer
;
1088 input_line_pointer
= save_in
;
1092 /* Turn a string in input_line_pointer into a floating point constant
1093 of type TYPE, and store the appropriate bytes in *LITP. The number
1094 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1095 returned, or NULL on OK.
1097 Note that fp constants aren't represent in the normal way on the ARM.
1098 In big endian mode, things are as expected. However, in little endian
1099 mode fp constants are big-endian word-wise, and little-endian byte-wise
1100 within the words. For example, (double) 1.1 in big endian mode is
1101 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1102 the byte sequence 99 99 f1 3f 9a 99 99 99.
1104 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1107 md_atof (int type
, char * litP
, int * sizeP
)
1110 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1142 return _("Unrecognized or unsupported floating point constant");
1145 t
= atof_ieee (input_line_pointer
, type
, words
);
1147 input_line_pointer
= t
;
1148 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1150 if (target_big_endian
)
1152 for (i
= 0; i
< prec
; i
++)
1154 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1155 litP
+= sizeof (LITTLENUM_TYPE
);
1160 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1161 for (i
= prec
- 1; i
>= 0; i
--)
1163 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1164 litP
+= sizeof (LITTLENUM_TYPE
);
1167 /* For a 4 byte float the order of elements in `words' is 1 0.
1168 For an 8 byte float the order is 1 0 3 2. */
1169 for (i
= 0; i
< prec
; i
+= 2)
1171 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1172 sizeof (LITTLENUM_TYPE
));
1173 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1174 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1175 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1182 /* We handle all bad expressions here, so that we can report the faulty
1183 instruction in the error message. */
1185 md_operand (expressionS
* exp
)
1187 if (in_my_get_expression
)
1188 exp
->X_op
= O_illegal
;
1191 /* Immediate values. */
1193 /* Generic immediate-value read function for use in directives.
1194 Accepts anything that 'expression' can fold to a constant.
1195 *val receives the number. */
1198 immediate_for_directive (int *val
)
1201 exp
.X_op
= O_illegal
;
1203 if (is_immediate_prefix (*input_line_pointer
))
1205 input_line_pointer
++;
1209 if (exp
.X_op
!= O_constant
)
1211 as_bad (_("expected #constant"));
1212 ignore_rest_of_line ();
1215 *val
= exp
.X_add_number
;
1220 /* Register parsing. */
1222 /* Generic register parser. CCP points to what should be the
1223 beginning of a register name. If it is indeed a valid register
1224 name, advance CCP over it and return the reg_entry structure;
1225 otherwise return NULL. Does not issue diagnostics. */
1227 static struct reg_entry
*
1228 arm_reg_parse_multi (char **ccp
)
1232 struct reg_entry
*reg
;
1234 skip_whitespace (start
);
1236 #ifdef REGISTER_PREFIX
1237 if (*start
!= REGISTER_PREFIX
)
1241 #ifdef OPTIONAL_REGISTER_PREFIX
1242 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1247 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1252 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1254 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1264 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1265 enum arm_reg_type type
)
1267 /* Alternative syntaxes are accepted for a few register classes. */
1274 /* Generic coprocessor register names are allowed for these. */
1275 if (reg
&& reg
->type
== REG_TYPE_CN
)
1280 /* For backward compatibility, a bare number is valid here. */
1282 unsigned long processor
= strtoul (start
, ccp
, 10);
1283 if (*ccp
!= start
&& processor
<= 15)
1288 case REG_TYPE_MMXWC
:
1289 /* WC includes WCG. ??? I'm not sure this is true for all
1290 instructions that take WC registers. */
1291 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1302 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1303 return value is the register number or FAIL. */
1306 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1309 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1312 /* Do not allow a scalar (reg+index) to parse as a register. */
1313 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1316 if (reg
&& reg
->type
== type
)
1319 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1326 /* Parse a Neon type specifier. *STR should point at the leading '.'
1327 character. Does no verification at this stage that the type fits the opcode
1334 Can all be legally parsed by this function.
1336 Fills in neon_type struct pointer with parsed information, and updates STR
1337 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1338 type, FAIL if not. */
1341 parse_neon_type (struct neon_type
*type
, char **str
)
1348 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1350 enum neon_el_type thistype
= NT_untyped
;
1351 unsigned thissize
= -1u;
1358 /* Just a size without an explicit type. */
1362 switch (TOLOWER (*ptr
))
1364 case 'i': thistype
= NT_integer
; break;
1365 case 'f': thistype
= NT_float
; break;
1366 case 'p': thistype
= NT_poly
; break;
1367 case 's': thistype
= NT_signed
; break;
1368 case 'u': thistype
= NT_unsigned
; break;
1370 thistype
= NT_float
;
1375 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1381 /* .f is an abbreviation for .f32. */
1382 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1387 thissize
= strtoul (ptr
, &ptr
, 10);
1389 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1392 as_bad (_("bad size %d in type specifier"), thissize
);
1400 type
->el
[type
->elems
].type
= thistype
;
1401 type
->el
[type
->elems
].size
= thissize
;
1406 /* Empty/missing type is not a successful parse. */
1407 if (type
->elems
== 0)
1415 /* Errors may be set multiple times during parsing or bit encoding
1416 (particularly in the Neon bits), but usually the earliest error which is set
1417 will be the most meaningful. Avoid overwriting it with later (cascading)
1418 errors by calling this function. */
1421 first_error (const char *err
)
1427 /* Parse a single type, e.g. ".s32", leading period included. */
1429 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1432 struct neon_type optype
;
1436 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1438 if (optype
.elems
== 1)
1439 *vectype
= optype
.el
[0];
1442 first_error (_("only one type should be specified for operand"));
1448 first_error (_("vector type expected"));
1460 /* Special meanings for indices (which have a range of 0-7), which will fit into
1463 #define NEON_ALL_LANES 15
1464 #define NEON_INTERLEAVE_LANES 14
1466 /* Parse either a register or a scalar, with an optional type. Return the
1467 register number, and optionally fill in the actual type of the register
1468 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1469 type/index information in *TYPEINFO. */
1472 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1473 enum arm_reg_type
*rtype
,
1474 struct neon_typed_alias
*typeinfo
)
1477 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1478 struct neon_typed_alias atype
;
1479 struct neon_type_el parsetype
;
1483 atype
.eltype
.type
= NT_invtype
;
1484 atype
.eltype
.size
= -1;
1486 /* Try alternate syntax for some types of register. Note these are mutually
1487 exclusive with the Neon syntax extensions. */
1490 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1498 /* Undo polymorphism when a set of register types may be accepted. */
1499 if ((type
== REG_TYPE_NDQ
1500 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1501 || (type
== REG_TYPE_VFSD
1502 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1503 || (type
== REG_TYPE_NSDQ
1504 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1505 || reg
->type
== REG_TYPE_NQ
))
1506 || (type
== REG_TYPE_MMXWC
1507 && (reg
->type
== REG_TYPE_MMXWCG
)))
1508 type
= (enum arm_reg_type
) reg
->type
;
1510 if (type
!= reg
->type
)
1516 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1518 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1520 first_error (_("can't redefine type for operand"));
1523 atype
.defined
|= NTA_HASTYPE
;
1524 atype
.eltype
= parsetype
;
1527 if (skip_past_char (&str
, '[') == SUCCESS
)
1529 if (type
!= REG_TYPE_VFD
)
1531 first_error (_("only D registers may be indexed"));
1535 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1537 first_error (_("can't change index for operand"));
1541 atype
.defined
|= NTA_HASINDEX
;
1543 if (skip_past_char (&str
, ']') == SUCCESS
)
1544 atype
.index
= NEON_ALL_LANES
;
1549 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1551 if (exp
.X_op
!= O_constant
)
1553 first_error (_("constant expression required"));
1557 if (skip_past_char (&str
, ']') == FAIL
)
1560 atype
.index
= exp
.X_add_number
;
1575 /* Like arm_reg_parse, but allow allow the following extra features:
1576 - If RTYPE is non-zero, return the (possibly restricted) type of the
1577 register (e.g. Neon double or quad reg when either has been requested).
1578 - If this is a Neon vector type with additional type information, fill
1579 in the struct pointed to by VECTYPE (if non-NULL).
1580 This function will fault on encountering a scalar. */
1583 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1584 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1586 struct neon_typed_alias atype
;
1588 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1593 /* Do not allow regname(... to parse as a register. */
1597 /* Do not allow a scalar (reg+index) to parse as a register. */
1598 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1600 first_error (_("register operand expected, but got scalar"));
1605 *vectype
= atype
.eltype
;
1612 #define NEON_SCALAR_REG(X) ((X) >> 4)
1613 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1615 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1616 have enough information to be able to do a good job bounds-checking. So, we
1617 just do easy checks here, and do further checks later. */
1620 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1624 struct neon_typed_alias atype
;
1626 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1628 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1631 if (atype
.index
== NEON_ALL_LANES
)
1633 first_error (_("scalar must have an index"));
1636 else if (atype
.index
>= 64 / elsize
)
1638 first_error (_("scalar index out of range"));
1643 *type
= atype
.eltype
;
1647 return reg
* 16 + atype
.index
;
1650 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1653 parse_reg_list (char ** strp
)
1655 char * str
= * strp
;
1659 /* We come back here if we get ranges concatenated by '+' or '|'. */
1662 skip_whitespace (str
);
1676 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1678 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1688 first_error (_("bad range in register list"));
1692 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1694 if (range
& (1 << i
))
1696 (_("Warning: duplicated register (r%d) in register list"),
1704 if (range
& (1 << reg
))
1705 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1707 else if (reg
<= cur_reg
)
1708 as_tsktsk (_("Warning: register range not in ascending order"));
1713 while (skip_past_comma (&str
) != FAIL
1714 || (in_range
= 1, *str
++ == '-'));
1717 if (skip_past_char (&str
, '}') == FAIL
)
1719 first_error (_("missing `}'"));
1727 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1730 if (exp
.X_op
== O_constant
)
1732 if (exp
.X_add_number
1733 != (exp
.X_add_number
& 0x0000ffff))
1735 inst
.error
= _("invalid register mask");
1739 if ((range
& exp
.X_add_number
) != 0)
1741 int regno
= range
& exp
.X_add_number
;
1744 regno
= (1 << regno
) - 1;
1746 (_("Warning: duplicated register (r%d) in register list"),
1750 range
|= exp
.X_add_number
;
1754 if (inst
.reloc
.type
!= 0)
1756 inst
.error
= _("expression too complex");
1760 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1761 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1762 inst
.reloc
.pc_rel
= 0;
1766 if (*str
== '|' || *str
== '+')
1772 while (another_range
);
1778 /* Types of registers in a list. */
1787 /* Parse a VFP register list. If the string is invalid return FAIL.
1788 Otherwise return the number of registers, and set PBASE to the first
1789 register. Parses registers of type ETYPE.
1790 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1791 - Q registers can be used to specify pairs of D registers
1792 - { } can be omitted from around a singleton register list
1793 FIXME: This is not implemented, as it would require backtracking in
1796 This could be done (the meaning isn't really ambiguous), but doesn't
1797 fit in well with the current parsing framework.
1798 - 32 D registers may be used (also true for VFPv3).
1799 FIXME: Types are ignored in these register lists, which is probably a
1803 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1808 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1812 unsigned long mask
= 0;
1815 if (skip_past_char (&str
, '{') == FAIL
)
1817 inst
.error
= _("expecting {");
1824 regtype
= REG_TYPE_VFS
;
1829 regtype
= REG_TYPE_VFD
;
1832 case REGLIST_NEON_D
:
1833 regtype
= REG_TYPE_NDQ
;
1837 if (etype
!= REGLIST_VFP_S
)
1839 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1840 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1844 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1847 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1854 base_reg
= max_regs
;
1858 int setmask
= 1, addregs
= 1;
1860 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1862 if (new_base
== FAIL
)
1864 first_error (_(reg_expected_msgs
[regtype
]));
1868 if (new_base
>= max_regs
)
1870 first_error (_("register out of range in list"));
1874 /* Note: a value of 2 * n is returned for the register Q<n>. */
1875 if (regtype
== REG_TYPE_NQ
)
1881 if (new_base
< base_reg
)
1882 base_reg
= new_base
;
1884 if (mask
& (setmask
<< new_base
))
1886 first_error (_("invalid register list"));
1890 if ((mask
>> new_base
) != 0 && ! warned
)
1892 as_tsktsk (_("register list not in ascending order"));
1896 mask
|= setmask
<< new_base
;
1899 if (*str
== '-') /* We have the start of a range expression */
1905 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1908 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1912 if (high_range
>= max_regs
)
1914 first_error (_("register out of range in list"));
1918 if (regtype
== REG_TYPE_NQ
)
1919 high_range
= high_range
+ 1;
1921 if (high_range
<= new_base
)
1923 inst
.error
= _("register range not in ascending order");
1927 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1929 if (mask
& (setmask
<< new_base
))
1931 inst
.error
= _("invalid register list");
1935 mask
|= setmask
<< new_base
;
1940 while (skip_past_comma (&str
) != FAIL
);
1944 /* Sanity check -- should have raised a parse error above. */
1945 if (count
== 0 || count
> max_regs
)
1950 /* Final test -- the registers must be consecutive. */
1952 for (i
= 0; i
< count
; i
++)
1954 if ((mask
& (1u << i
)) == 0)
1956 inst
.error
= _("non-contiguous register range");
1966 /* True if two alias types are the same. */
1969 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1977 if (a
->defined
!= b
->defined
)
1980 if ((a
->defined
& NTA_HASTYPE
) != 0
1981 && (a
->eltype
.type
!= b
->eltype
.type
1982 || a
->eltype
.size
!= b
->eltype
.size
))
1985 if ((a
->defined
& NTA_HASINDEX
) != 0
1986 && (a
->index
!= b
->index
))
1992 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1993 The base register is put in *PBASE.
1994 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1996 The register stride (minus one) is put in bit 4 of the return value.
1997 Bits [6:5] encode the list length (minus one).
1998 The type of the list elements is put in *ELTYPE, if non-NULL. */
2000 #define NEON_LANE(X) ((X) & 0xf)
2001 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2002 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2005 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2006 struct neon_type_el
*eltype
)
2013 int leading_brace
= 0;
2014 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2015 const char *const incr_error
= _("register stride must be 1 or 2");
2016 const char *const type_error
= _("mismatched element/structure types in list");
2017 struct neon_typed_alias firsttype
;
2018 firsttype
.defined
= 0;
2019 firsttype
.eltype
.type
= NT_invtype
;
2020 firsttype
.eltype
.size
= -1;
2021 firsttype
.index
= -1;
2023 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2028 struct neon_typed_alias atype
;
2029 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2033 first_error (_(reg_expected_msgs
[rtype
]));
2040 if (rtype
== REG_TYPE_NQ
)
2046 else if (reg_incr
== -1)
2048 reg_incr
= getreg
- base_reg
;
2049 if (reg_incr
< 1 || reg_incr
> 2)
2051 first_error (_(incr_error
));
2055 else if (getreg
!= base_reg
+ reg_incr
* count
)
2057 first_error (_(incr_error
));
2061 if (! neon_alias_types_same (&atype
, &firsttype
))
2063 first_error (_(type_error
));
2067 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2071 struct neon_typed_alias htype
;
2072 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2074 lane
= NEON_INTERLEAVE_LANES
;
2075 else if (lane
!= NEON_INTERLEAVE_LANES
)
2077 first_error (_(type_error
));
2082 else if (reg_incr
!= 1)
2084 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2088 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2091 first_error (_(reg_expected_msgs
[rtype
]));
2094 if (! neon_alias_types_same (&htype
, &firsttype
))
2096 first_error (_(type_error
));
2099 count
+= hireg
+ dregs
- getreg
;
2103 /* If we're using Q registers, we can't use [] or [n] syntax. */
2104 if (rtype
== REG_TYPE_NQ
)
2110 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2114 else if (lane
!= atype
.index
)
2116 first_error (_(type_error
));
2120 else if (lane
== -1)
2121 lane
= NEON_INTERLEAVE_LANES
;
2122 else if (lane
!= NEON_INTERLEAVE_LANES
)
2124 first_error (_(type_error
));
2129 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2131 /* No lane set by [x]. We must be interleaving structures. */
2133 lane
= NEON_INTERLEAVE_LANES
;
2136 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2137 || (count
> 1 && reg_incr
== -1))
2139 first_error (_("error parsing element/structure list"));
2143 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2145 first_error (_("expected }"));
2153 *eltype
= firsttype
.eltype
;
2158 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2161 /* Parse an explicit relocation suffix on an expression. This is
2162 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2163 arm_reloc_hsh contains no entries, so this function can only
2164 succeed if there is no () after the word. Returns -1 on error,
2165 BFD_RELOC_UNUSED if there wasn't any suffix. */
2168 parse_reloc (char **str
)
2170 struct reloc_entry
*r
;
2174 return BFD_RELOC_UNUSED
;
2179 while (*q
&& *q
!= ')' && *q
!= ',')
2184 if ((r
= (struct reloc_entry
*)
2185 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2192 /* Directives: register aliases. */
2194 static struct reg_entry
*
2195 insert_reg_alias (char *str
, unsigned number
, int type
)
2197 struct reg_entry
*new_reg
;
2200 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2202 if (new_reg
->builtin
)
2203 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2205 /* Only warn about a redefinition if it's not defined as the
2207 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2208 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2213 name
= xstrdup (str
);
2214 new_reg
= XNEW (struct reg_entry
);
2216 new_reg
->name
= name
;
2217 new_reg
->number
= number
;
2218 new_reg
->type
= type
;
2219 new_reg
->builtin
= FALSE
;
2220 new_reg
->neon
= NULL
;
2222 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2229 insert_neon_reg_alias (char *str
, int number
, int type
,
2230 struct neon_typed_alias
*atype
)
2232 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2236 first_error (_("attempt to redefine typed alias"));
2242 reg
->neon
= XNEW (struct neon_typed_alias
);
2243 *reg
->neon
= *atype
;
2247 /* Look for the .req directive. This is of the form:
2249 new_register_name .req existing_register_name
2251 If we find one, or if it looks sufficiently like one that we want to
2252 handle any error here, return TRUE. Otherwise return FALSE. */
2255 create_register_alias (char * newname
, char *p
)
2257 struct reg_entry
*old
;
2258 char *oldname
, *nbuf
;
2261 /* The input scrubber ensures that whitespace after the mnemonic is
2262 collapsed to single spaces. */
2264 if (strncmp (oldname
, " .req ", 6) != 0)
2268 if (*oldname
== '\0')
2271 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2274 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2278 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2279 the desired alias name, and p points to its end. If not, then
2280 the desired alias name is in the global original_case_string. */
2281 #ifdef TC_CASE_SENSITIVE
2284 newname
= original_case_string
;
2285 nlen
= strlen (newname
);
2288 nbuf
= xmemdup0 (newname
, nlen
);
2290 /* Create aliases under the new name as stated; an all-lowercase
2291 version of the new name; and an all-uppercase version of the new
2293 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2295 for (p
= nbuf
; *p
; p
++)
2298 if (strncmp (nbuf
, newname
, nlen
))
2300 /* If this attempt to create an additional alias fails, do not bother
2301 trying to create the all-lower case alias. We will fail and issue
2302 a second, duplicate error message. This situation arises when the
2303 programmer does something like:
2306 The second .req creates the "Foo" alias but then fails to create
2307 the artificial FOO alias because it has already been created by the
2309 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2316 for (p
= nbuf
; *p
; p
++)
2319 if (strncmp (nbuf
, newname
, nlen
))
2320 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2327 /* Create a Neon typed/indexed register alias using directives, e.g.:
2332 These typed registers can be used instead of the types specified after the
2333 Neon mnemonic, so long as all operands given have types. Types can also be
2334 specified directly, e.g.:
2335 vadd d0.s32, d1.s32, d2.s32 */
2338 create_neon_reg_alias (char *newname
, char *p
)
2340 enum arm_reg_type basetype
;
2341 struct reg_entry
*basereg
;
2342 struct reg_entry mybasereg
;
2343 struct neon_type ntype
;
2344 struct neon_typed_alias typeinfo
;
2345 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2348 typeinfo
.defined
= 0;
2349 typeinfo
.eltype
.type
= NT_invtype
;
2350 typeinfo
.eltype
.size
= -1;
2351 typeinfo
.index
= -1;
2355 if (strncmp (p
, " .dn ", 5) == 0)
2356 basetype
= REG_TYPE_VFD
;
2357 else if (strncmp (p
, " .qn ", 5) == 0)
2358 basetype
= REG_TYPE_NQ
;
2367 basereg
= arm_reg_parse_multi (&p
);
2369 if (basereg
&& basereg
->type
!= basetype
)
2371 as_bad (_("bad type for register"));
2375 if (basereg
== NULL
)
2378 /* Try parsing as an integer. */
2379 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("expression must be constant"));
2385 basereg
= &mybasereg
;
2386 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2392 typeinfo
= *basereg
->neon
;
2394 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2396 /* We got a type. */
2397 if (typeinfo
.defined
& NTA_HASTYPE
)
2399 as_bad (_("can't redefine the type of a register alias"));
2403 typeinfo
.defined
|= NTA_HASTYPE
;
2404 if (ntype
.elems
!= 1)
2406 as_bad (_("you must specify a single type only"));
2409 typeinfo
.eltype
= ntype
.el
[0];
2412 if (skip_past_char (&p
, '[') == SUCCESS
)
2415 /* We got a scalar index. */
2417 if (typeinfo
.defined
& NTA_HASINDEX
)
2419 as_bad (_("can't redefine the index of a scalar alias"));
2423 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2425 if (exp
.X_op
!= O_constant
)
2427 as_bad (_("scalar index must be constant"));
2431 typeinfo
.defined
|= NTA_HASINDEX
;
2432 typeinfo
.index
= exp
.X_add_number
;
2434 if (skip_past_char (&p
, ']') == FAIL
)
2436 as_bad (_("expecting ]"));
2441 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2442 the desired alias name, and p points to its end. If not, then
2443 the desired alias name is in the global original_case_string. */
2444 #ifdef TC_CASE_SENSITIVE
2445 namelen
= nameend
- newname
;
2447 newname
= original_case_string
;
2448 namelen
= strlen (newname
);
2451 namebuf
= xmemdup0 (newname
, namelen
);
2453 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2454 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2456 /* Insert name in all uppercase. */
2457 for (p
= namebuf
; *p
; p
++)
2460 if (strncmp (namebuf
, newname
, namelen
))
2461 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2462 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2464 /* Insert name in all lowercase. */
2465 for (p
= namebuf
; *p
; p
++)
2468 if (strncmp (namebuf
, newname
, namelen
))
2469 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2470 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2476 /* Should never be called, as .req goes between the alias and the
2477 register name, not at the beginning of the line. */
2480 s_req (int a ATTRIBUTE_UNUSED
)
2482 as_bad (_("invalid syntax for .req directive"));
2486 s_dn (int a ATTRIBUTE_UNUSED
)
2488 as_bad (_("invalid syntax for .dn directive"));
2492 s_qn (int a ATTRIBUTE_UNUSED
)
2494 as_bad (_("invalid syntax for .qn directive"));
2497 /* The .unreq directive deletes an alias which was previously defined
2498 by .req. For example:
2504 s_unreq (int a ATTRIBUTE_UNUSED
)
2509 name
= input_line_pointer
;
2511 while (*input_line_pointer
!= 0
2512 && *input_line_pointer
!= ' '
2513 && *input_line_pointer
!= '\n')
2514 ++input_line_pointer
;
2516 saved_char
= *input_line_pointer
;
2517 *input_line_pointer
= 0;
2520 as_bad (_("invalid syntax for .unreq directive"));
2523 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2527 as_bad (_("unknown register alias '%s'"), name
);
2528 else if (reg
->builtin
)
2529 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2536 hash_delete (arm_reg_hsh
, name
, FALSE
);
2537 free ((char *) reg
->name
);
2542 /* Also locate the all upper case and all lower case versions.
2543 Do not complain if we cannot find one or the other as it
2544 was probably deleted above. */
2546 nbuf
= strdup (name
);
2547 for (p
= nbuf
; *p
; p
++)
2549 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2552 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2553 free ((char *) reg
->name
);
2559 for (p
= nbuf
; *p
; p
++)
2561 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2564 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2565 free ((char *) reg
->name
);
2575 *input_line_pointer
= saved_char
;
2576 demand_empty_rest_of_line ();
2579 /* Directives: Instruction set selection. */
2582 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2583 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2584 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2585 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2587 /* Create a new mapping symbol for the transition to STATE. */
2590 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2593 const char * symname
;
2600 type
= BSF_NO_FLAGS
;
2604 type
= BSF_NO_FLAGS
;
2608 type
= BSF_NO_FLAGS
;
2614 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2615 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2620 THUMB_SET_FUNC (symbolP
, 0);
2621 ARM_SET_THUMB (symbolP
, 0);
2622 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2626 THUMB_SET_FUNC (symbolP
, 1);
2627 ARM_SET_THUMB (symbolP
, 1);
2628 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2636 /* Save the mapping symbols for future reference. Also check that
2637 we do not place two mapping symbols at the same offset within a
2638 frag. We'll handle overlap between frags in
2639 check_mapping_symbols.
2641 If .fill or other data filling directive generates zero sized data,
2642 the mapping symbol for the following code will have the same value
2643 as the one generated for the data filling directive. In this case,
2644 we replace the old symbol with the new one at the same address. */
2647 if (frag
->tc_frag_data
.first_map
!= NULL
)
2649 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2650 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2652 frag
->tc_frag_data
.first_map
= symbolP
;
2654 if (frag
->tc_frag_data
.last_map
!= NULL
)
2656 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2657 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2658 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2660 frag
->tc_frag_data
.last_map
= symbolP
;
2663 /* We must sometimes convert a region marked as code to data during
2664 code alignment, if an odd number of bytes have to be padded. The
2665 code mapping symbol is pushed to an aligned address. */
2668 insert_data_mapping_symbol (enum mstate state
,
2669 valueT value
, fragS
*frag
, offsetT bytes
)
2671 /* If there was already a mapping symbol, remove it. */
2672 if (frag
->tc_frag_data
.last_map
!= NULL
2673 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2675 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2679 know (frag
->tc_frag_data
.first_map
== symp
);
2680 frag
->tc_frag_data
.first_map
= NULL
;
2682 frag
->tc_frag_data
.last_map
= NULL
;
2683 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2686 make_mapping_symbol (MAP_DATA
, value
, frag
);
2687 make_mapping_symbol (state
, value
+ bytes
, frag
);
2690 static void mapping_state_2 (enum mstate state
, int max_chars
);
2692 /* Set the mapping state to STATE. Only call this when about to
2693 emit some STATE bytes to the file. */
2695 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2697 mapping_state (enum mstate state
)
2699 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2701 if (mapstate
== state
)
2702 /* The mapping symbol has already been emitted.
2703 There is nothing else to do. */
2706 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2708 All ARM instructions require 4-byte alignment.
2709 (Almost) all Thumb instructions require 2-byte alignment.
2711 When emitting instructions into any section, mark the section
2714 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2715 but themselves require 2-byte alignment; this applies to some
2716 PC- relative forms. However, these cases will involve implicit
2717 literal pool generation or an explicit .align >=2, both of
2718 which will cause the section to me marked with sufficient
2719 alignment. Thus, we don't handle those cases here. */
2720 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2722 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2723 /* This case will be evaluated later. */
2726 mapping_state_2 (state
, 0);
2729 /* Same as mapping_state, but MAX_CHARS bytes have already been
2730 allocated. Put the mapping symbol that far back. */
2733 mapping_state_2 (enum mstate state
, int max_chars
)
2735 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2737 if (!SEG_NORMAL (now_seg
))
2740 if (mapstate
== state
)
2741 /* The mapping symbol has already been emitted.
2742 There is nothing else to do. */
2745 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2746 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2748 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2749 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2752 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2755 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2756 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2760 #define mapping_state(x) ((void)0)
2761 #define mapping_state_2(x, y) ((void)0)
2764 /* Find the real, Thumb encoded start of a Thumb function. */
2768 find_real_start (symbolS
* symbolP
)
2771 const char * name
= S_GET_NAME (symbolP
);
2772 symbolS
* new_target
;
2774 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2775 #define STUB_NAME ".real_start_of"
2780 /* The compiler may generate BL instructions to local labels because
2781 it needs to perform a branch to a far away location. These labels
2782 do not have a corresponding ".real_start_of" label. We check
2783 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2784 the ".real_start_of" convention for nonlocal branches. */
2785 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2788 real_start
= concat (STUB_NAME
, name
, NULL
);
2789 new_target
= symbol_find (real_start
);
2792 if (new_target
== NULL
)
2794 as_warn (_("Failed to find real start of function: %s\n"), name
);
2795 new_target
= symbolP
;
2803 opcode_select (int width
)
2810 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2811 as_bad (_("selected processor does not support THUMB opcodes"));
2814 /* No need to force the alignment, since we will have been
2815 coming from ARM mode, which is word-aligned. */
2816 record_alignment (now_seg
, 1);
2823 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2824 as_bad (_("selected processor does not support ARM opcodes"));
2829 frag_align (2, 0, 0);
2831 record_alignment (now_seg
, 1);
2836 as_bad (_("invalid instruction size selected (%d)"), width
);
2841 s_arm (int ignore ATTRIBUTE_UNUSED
)
2844 demand_empty_rest_of_line ();
2848 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2851 demand_empty_rest_of_line ();
2855 s_code (int unused ATTRIBUTE_UNUSED
)
2859 temp
= get_absolute_expression ();
2864 opcode_select (temp
);
2868 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2873 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2875 /* If we are not already in thumb mode go into it, EVEN if
2876 the target processor does not support thumb instructions.
2877 This is used by gcc/config/arm/lib1funcs.asm for example
2878 to compile interworking support functions even if the
2879 target processor should not support interworking. */
2883 record_alignment (now_seg
, 1);
2886 demand_empty_rest_of_line ();
2890 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2894 /* The following label is the name/address of the start of a Thumb function.
2895 We need to know this for the interworking support. */
2896 label_is_thumb_function_name
= TRUE
;
2899 /* Perform a .set directive, but also mark the alias as
2900 being a thumb function. */
2903 s_thumb_set (int equiv
)
2905 /* XXX the following is a duplicate of the code for s_set() in read.c
2906 We cannot just call that code as we need to get at the symbol that
2913 /* Especial apologies for the random logic:
2914 This just grew, and could be parsed much more simply!
2916 delim
= get_symbol_name (& name
);
2917 end_name
= input_line_pointer
;
2918 (void) restore_line_pointer (delim
);
2920 if (*input_line_pointer
!= ',')
2923 as_bad (_("expected comma after name \"%s\""), name
);
2925 ignore_rest_of_line ();
2929 input_line_pointer
++;
2932 if (name
[0] == '.' && name
[1] == '\0')
2934 /* XXX - this should not happen to .thumb_set. */
2938 if ((symbolP
= symbol_find (name
)) == NULL
2939 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2942 /* When doing symbol listings, play games with dummy fragments living
2943 outside the normal fragment chain to record the file and line info
2945 if (listing
& LISTING_SYMBOLS
)
2947 extern struct list_info_struct
* listing_tail
;
2948 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2950 memset (dummy_frag
, 0, sizeof (fragS
));
2951 dummy_frag
->fr_type
= rs_fill
;
2952 dummy_frag
->line
= listing_tail
;
2953 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2954 dummy_frag
->fr_symbol
= symbolP
;
2958 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2961 /* "set" symbols are local unless otherwise specified. */
2962 SF_SET_LOCAL (symbolP
);
2963 #endif /* OBJ_COFF */
2964 } /* Make a new symbol. */
2966 symbol_table_insert (symbolP
);
2971 && S_IS_DEFINED (symbolP
)
2972 && S_GET_SEGMENT (symbolP
) != reg_section
)
2973 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2975 pseudo_set (symbolP
);
2977 demand_empty_rest_of_line ();
2979 /* XXX Now we come to the Thumb specific bit of code. */
2981 THUMB_SET_FUNC (symbolP
, 1);
2982 ARM_SET_THUMB (symbolP
, 1);
2983 #if defined OBJ_ELF || defined OBJ_COFF
2984 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2988 /* Directives: Mode selection. */
2990 /* .syntax [unified|divided] - choose the new unified syntax
2991 (same for Arm and Thumb encoding, modulo slight differences in what
2992 can be represented) or the old divergent syntax for each mode. */
2994 s_syntax (int unused ATTRIBUTE_UNUSED
)
2998 delim
= get_symbol_name (& name
);
3000 if (!strcasecmp (name
, "unified"))
3001 unified_syntax
= TRUE
;
3002 else if (!strcasecmp (name
, "divided"))
3003 unified_syntax
= FALSE
;
3006 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3009 (void) restore_line_pointer (delim
);
3010 demand_empty_rest_of_line ();
3013 /* Directives: sectioning and alignment. */
3016 s_bss (int ignore ATTRIBUTE_UNUSED
)
3018 /* We don't support putting frags in the BSS segment, we fake it by
3019 marking in_bss, then looking at s_skip for clues. */
3020 subseg_set (bss_section
, 0);
3021 demand_empty_rest_of_line ();
3023 #ifdef md_elf_section_change_hook
3024 md_elf_section_change_hook ();
3029 s_even (int ignore ATTRIBUTE_UNUSED
)
3031 /* Never make frag if expect extra pass. */
3033 frag_align (1, 0, 0);
3035 record_alignment (now_seg
, 1);
3037 demand_empty_rest_of_line ();
3040 /* Directives: CodeComposer Studio. */
3042 /* .ref (for CodeComposer Studio syntax only). */
3044 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3046 if (codecomposer_syntax
)
3047 ignore_rest_of_line ();
3049 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3052 /* If name is not NULL, then it is used for marking the beginning of a
3053 function, whereas if it is NULL then it means the function end. */
3055 asmfunc_debug (const char * name
)
3057 static const char * last_name
= NULL
;
3061 gas_assert (last_name
== NULL
);
3064 if (debug_type
== DEBUG_STABS
)
3065 stabs_generate_asm_func (name
, name
);
3069 gas_assert (last_name
!= NULL
);
3071 if (debug_type
== DEBUG_STABS
)
3072 stabs_generate_asm_endfunc (last_name
, last_name
);
3079 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3081 if (codecomposer_syntax
)
3083 switch (asmfunc_state
)
3085 case OUTSIDE_ASMFUNC
:
3086 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3089 case WAITING_ASMFUNC_NAME
:
3090 as_bad (_(".asmfunc repeated."));
3093 case WAITING_ENDASMFUNC
:
3094 as_bad (_(".asmfunc without function."));
3097 demand_empty_rest_of_line ();
3100 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3104 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3106 if (codecomposer_syntax
)
3108 switch (asmfunc_state
)
3110 case OUTSIDE_ASMFUNC
:
3111 as_bad (_(".endasmfunc without a .asmfunc."));
3114 case WAITING_ASMFUNC_NAME
:
3115 as_bad (_(".endasmfunc without function."));
3118 case WAITING_ENDASMFUNC
:
3119 asmfunc_state
= OUTSIDE_ASMFUNC
;
3120 asmfunc_debug (NULL
);
3123 demand_empty_rest_of_line ();
3126 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3130 s_ccs_def (int name
)
3132 if (codecomposer_syntax
)
3135 as_bad (_(".def pseudo-op only available with -mccs flag."));
3138 /* Directives: Literal pools. */
3140 static literal_pool
*
3141 find_literal_pool (void)
3143 literal_pool
* pool
;
3145 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3147 if (pool
->section
== now_seg
3148 && pool
->sub_section
== now_subseg
)
3155 static literal_pool
*
3156 find_or_make_literal_pool (void)
3158 /* Next literal pool ID number. */
3159 static unsigned int latest_pool_num
= 1;
3160 literal_pool
* pool
;
3162 pool
= find_literal_pool ();
3166 /* Create a new pool. */
3167 pool
= XNEW (literal_pool
);
3171 pool
->next_free_entry
= 0;
3172 pool
->section
= now_seg
;
3173 pool
->sub_section
= now_subseg
;
3174 pool
->next
= list_of_pools
;
3175 pool
->symbol
= NULL
;
3176 pool
->alignment
= 2;
3178 /* Add it to the list. */
3179 list_of_pools
= pool
;
3182 /* New pools, and emptied pools, will have a NULL symbol. */
3183 if (pool
->symbol
== NULL
)
3185 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3186 (valueT
) 0, &zero_address_frag
);
3187 pool
->id
= latest_pool_num
++;
3194 /* Add the literal in the global 'inst'
3195 structure to the relevant literal pool. */
3198 add_to_lit_pool (unsigned int nbytes
)
3200 #define PADDING_SLOT 0x1
3201 #define LIT_ENTRY_SIZE_MASK 0xFF
3202 literal_pool
* pool
;
3203 unsigned int entry
, pool_size
= 0;
3204 bfd_boolean padding_slot_p
= FALSE
;
3210 imm1
= inst
.operands
[1].imm
;
3211 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3212 : inst
.reloc
.exp
.X_unsigned
? 0
3213 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3214 if (target_big_endian
)
3217 imm2
= inst
.operands
[1].imm
;
3221 pool
= find_or_make_literal_pool ();
3223 /* Check if this literal value is already in the pool. */
3224 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3228 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3229 && (inst
.reloc
.exp
.X_op
== O_constant
)
3230 && (pool
->literals
[entry
].X_add_number
3231 == inst
.reloc
.exp
.X_add_number
)
3232 && (pool
->literals
[entry
].X_md
== nbytes
)
3233 && (pool
->literals
[entry
].X_unsigned
3234 == inst
.reloc
.exp
.X_unsigned
))
3237 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3238 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3239 && (pool
->literals
[entry
].X_add_number
3240 == inst
.reloc
.exp
.X_add_number
)
3241 && (pool
->literals
[entry
].X_add_symbol
3242 == inst
.reloc
.exp
.X_add_symbol
)
3243 && (pool
->literals
[entry
].X_op_symbol
3244 == inst
.reloc
.exp
.X_op_symbol
)
3245 && (pool
->literals
[entry
].X_md
== nbytes
))
3248 else if ((nbytes
== 8)
3249 && !(pool_size
& 0x7)
3250 && ((entry
+ 1) != pool
->next_free_entry
)
3251 && (pool
->literals
[entry
].X_op
== O_constant
)
3252 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3253 && (pool
->literals
[entry
].X_unsigned
3254 == inst
.reloc
.exp
.X_unsigned
)
3255 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3256 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3257 && (pool
->literals
[entry
+ 1].X_unsigned
3258 == inst
.reloc
.exp
.X_unsigned
))
3261 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3262 if (padding_slot_p
&& (nbytes
== 4))
3268 /* Do we need to create a new entry? */
3269 if (entry
== pool
->next_free_entry
)
3271 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3273 inst
.error
= _("literal pool overflow");
3279 /* For 8-byte entries, we align to an 8-byte boundary,
3280 and split it into two 4-byte entries, because on 32-bit
3281 host, 8-byte constants are treated as big num, thus
3282 saved in "generic_bignum" which will be overwritten
3283 by later assignments.
3285 We also need to make sure there is enough space for
3288 We also check to make sure the literal operand is a
3290 if (!(inst
.reloc
.exp
.X_op
== O_constant
3291 || inst
.reloc
.exp
.X_op
== O_big
))
3293 inst
.error
= _("invalid type for literal pool");
3296 else if (pool_size
& 0x7)
3298 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3300 inst
.error
= _("literal pool overflow");
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_op
= O_constant
;
3306 pool
->literals
[entry
].X_add_number
= 0;
3307 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3308 pool
->next_free_entry
+= 1;
3311 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3313 inst
.error
= _("literal pool overflow");
3317 pool
->literals
[entry
] = inst
.reloc
.exp
;
3318 pool
->literals
[entry
].X_op
= O_constant
;
3319 pool
->literals
[entry
].X_add_number
= imm1
;
3320 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3321 pool
->literals
[entry
++].X_md
= 4;
3322 pool
->literals
[entry
] = inst
.reloc
.exp
;
3323 pool
->literals
[entry
].X_op
= O_constant
;
3324 pool
->literals
[entry
].X_add_number
= imm2
;
3325 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3326 pool
->literals
[entry
].X_md
= 4;
3327 pool
->alignment
= 3;
3328 pool
->next_free_entry
+= 1;
3332 pool
->literals
[entry
] = inst
.reloc
.exp
;
3333 pool
->literals
[entry
].X_md
= 4;
3337 /* PR ld/12974: Record the location of the first source line to reference
3338 this entry in the literal pool. If it turns out during linking that the
3339 symbol does not exist we will be able to give an accurate line number for
3340 the (first use of the) missing reference. */
3341 if (debug_type
== DEBUG_DWARF2
)
3342 dwarf2_where (pool
->locs
+ entry
);
3344 pool
->next_free_entry
+= 1;
3346 else if (padding_slot_p
)
3348 pool
->literals
[entry
] = inst
.reloc
.exp
;
3349 pool
->literals
[entry
].X_md
= nbytes
;
3352 inst
.reloc
.exp
.X_op
= O_symbol
;
3353 inst
.reloc
.exp
.X_add_number
= pool_size
;
3354 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3360 tc_start_label_without_colon (void)
3362 bfd_boolean ret
= TRUE
;
3364 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3366 const char *label
= input_line_pointer
;
3368 while (!is_end_of_line
[(int) label
[-1]])
3373 as_bad (_("Invalid label '%s'"), label
);
3377 asmfunc_debug (label
);
3379 asmfunc_state
= WAITING_ENDASMFUNC
;
3385 /* Can't use symbol_new here, so have to create a symbol and then at
3386 a later date assign it a value. That's what these functions do. */
3389 symbol_locate (symbolS
* symbolP
,
3390 const char * name
, /* It is copied, the caller can modify. */
3391 segT segment
, /* Segment identifier (SEG_<something>). */
3392 valueT valu
, /* Symbol value. */
3393 fragS
* frag
) /* Associated fragment. */
3396 char * preserved_copy_of_name
;
3398 name_length
= strlen (name
) + 1; /* +1 for \0. */
3399 obstack_grow (¬es
, name
, name_length
);
3400 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3402 #ifdef tc_canonicalize_symbol_name
3403 preserved_copy_of_name
=
3404 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3407 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3409 S_SET_SEGMENT (symbolP
, segment
);
3410 S_SET_VALUE (symbolP
, valu
);
3411 symbol_clear_list_pointers (symbolP
);
3413 symbol_set_frag (symbolP
, frag
);
3415 /* Link to end of symbol chain. */
3417 extern int symbol_table_frozen
;
3419 if (symbol_table_frozen
)
3423 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3425 obj_symbol_new_hook (symbolP
);
3427 #ifdef tc_symbol_new_hook
3428 tc_symbol_new_hook (symbolP
);
3432 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3433 #endif /* DEBUG_SYMS */
3437 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3440 literal_pool
* pool
;
3443 pool
= find_literal_pool ();
3445 || pool
->symbol
== NULL
3446 || pool
->next_free_entry
== 0)
3449 /* Align pool as you have word accesses.
3450 Only make a frag if we have to. */
3452 frag_align (pool
->alignment
, 0, 0);
3454 record_alignment (now_seg
, 2);
3457 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3458 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3460 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3462 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3463 (valueT
) frag_now_fix (), frag_now
);
3464 symbol_table_insert (pool
->symbol
);
3466 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3468 #if defined OBJ_COFF || defined OBJ_ELF
3469 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3472 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3475 if (debug_type
== DEBUG_DWARF2
)
3476 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3478 /* First output the expression in the instruction to the pool. */
3479 emit_expr (&(pool
->literals
[entry
]),
3480 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3483 /* Mark the pool as empty. */
3484 pool
->next_free_entry
= 0;
3485 pool
->symbol
= NULL
;
3489 /* Forward declarations for functions below, in the MD interface
3491 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3492 static valueT
create_unwind_entry (int);
3493 static void start_unwind_section (const segT
, int);
3494 static void add_unwind_opcode (valueT
, int);
3495 static void flush_pending_unwind (void);
3497 /* Directives: Data. */
3500 s_arm_elf_cons (int nbytes
)
3504 #ifdef md_flush_pending_output
3505 md_flush_pending_output ();
3508 if (is_it_end_of_statement ())
3510 demand_empty_rest_of_line ();
3514 #ifdef md_cons_align
3515 md_cons_align (nbytes
);
3518 mapping_state (MAP_DATA
);
3522 char *base
= input_line_pointer
;
3526 if (exp
.X_op
!= O_symbol
)
3527 emit_expr (&exp
, (unsigned int) nbytes
);
3530 char *before_reloc
= input_line_pointer
;
3531 reloc
= parse_reloc (&input_line_pointer
);
3534 as_bad (_("unrecognized relocation suffix"));
3535 ignore_rest_of_line ();
3538 else if (reloc
== BFD_RELOC_UNUSED
)
3539 emit_expr (&exp
, (unsigned int) nbytes
);
3542 reloc_howto_type
*howto
= (reloc_howto_type
*)
3543 bfd_reloc_type_lookup (stdoutput
,
3544 (bfd_reloc_code_real_type
) reloc
);
3545 int size
= bfd_get_reloc_size (howto
);
3547 if (reloc
== BFD_RELOC_ARM_PLT32
)
3549 as_bad (_("(plt) is only valid on branch targets"));
3550 reloc
= BFD_RELOC_UNUSED
;
3555 as_bad (_("%s relocations do not fit in %d bytes"),
3556 howto
->name
, nbytes
);
3559 /* We've parsed an expression stopping at O_symbol.
3560 But there may be more expression left now that we
3561 have parsed the relocation marker. Parse it again.
3562 XXX Surely there is a cleaner way to do this. */
3563 char *p
= input_line_pointer
;
3565 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3567 memcpy (save_buf
, base
, input_line_pointer
- base
);
3568 memmove (base
+ (input_line_pointer
- before_reloc
),
3569 base
, before_reloc
- base
);
3571 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3573 memcpy (base
, save_buf
, p
- base
);
3575 offset
= nbytes
- size
;
3576 p
= frag_more (nbytes
);
3577 memset (p
, 0, nbytes
);
3578 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3579 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3585 while (*input_line_pointer
++ == ',');
3587 /* Put terminator back into stream. */
3588 input_line_pointer
--;
3589 demand_empty_rest_of_line ();
3592 /* Emit an expression containing a 32-bit thumb instruction.
3593 Implementation based on put_thumb32_insn. */
3596 emit_thumb32_expr (expressionS
* exp
)
3598 expressionS exp_high
= *exp
;
3600 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3601 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3602 exp
->X_add_number
&= 0xffff;
3603 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3606 /* Guess the instruction size based on the opcode. */
3609 thumb_insn_size (int opcode
)
3611 if ((unsigned int) opcode
< 0xe800u
)
3613 else if ((unsigned int) opcode
>= 0xe8000000u
)
3620 emit_insn (expressionS
*exp
, int nbytes
)
3624 if (exp
->X_op
== O_constant
)
3629 size
= thumb_insn_size (exp
->X_add_number
);
3633 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3635 as_bad (_(".inst.n operand too big. "\
3636 "Use .inst.w instead"));
3641 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3642 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3644 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3646 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3647 emit_thumb32_expr (exp
);
3649 emit_expr (exp
, (unsigned int) size
);
3651 it_fsm_post_encode ();
3655 as_bad (_("cannot determine Thumb instruction size. " \
3656 "Use .inst.n/.inst.w instead"));
3659 as_bad (_("constant expression required"));
3664 /* Like s_arm_elf_cons but do not use md_cons_align and
3665 set the mapping state to MAP_ARM/MAP_THUMB. */
3668 s_arm_elf_inst (int nbytes
)
3670 if (is_it_end_of_statement ())
3672 demand_empty_rest_of_line ();
3676 /* Calling mapping_state () here will not change ARM/THUMB,
3677 but will ensure not to be in DATA state. */
3680 mapping_state (MAP_THUMB
);
3685 as_bad (_("width suffixes are invalid in ARM mode"));
3686 ignore_rest_of_line ();
3692 mapping_state (MAP_ARM
);
3701 if (! emit_insn (& exp
, nbytes
))
3703 ignore_rest_of_line ();
3707 while (*input_line_pointer
++ == ',');
3709 /* Put terminator back into stream. */
3710 input_line_pointer
--;
3711 demand_empty_rest_of_line ();
3714 /* Parse a .rel31 directive. */
3717 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3724 if (*input_line_pointer
== '1')
3725 highbit
= 0x80000000;
3726 else if (*input_line_pointer
!= '0')
3727 as_bad (_("expected 0 or 1"));
3729 input_line_pointer
++;
3730 if (*input_line_pointer
!= ',')
3731 as_bad (_("missing comma"));
3732 input_line_pointer
++;
3734 #ifdef md_flush_pending_output
3735 md_flush_pending_output ();
3738 #ifdef md_cons_align
3742 mapping_state (MAP_DATA
);
3747 md_number_to_chars (p
, highbit
, 4);
3748 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3749 BFD_RELOC_ARM_PREL31
);
3751 demand_empty_rest_of_line ();
3754 /* Directives: AEABI stack-unwind tables. */
3756 /* Parse an unwind_fnstart directive. Simply records the current location. */
3759 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3761 demand_empty_rest_of_line ();
3762 if (unwind
.proc_start
)
3764 as_bad (_("duplicate .fnstart directive"));
3768 /* Mark the start of the function. */
3769 unwind
.proc_start
= expr_build_dot ();
3771 /* Reset the rest of the unwind info. */
3772 unwind
.opcode_count
= 0;
3773 unwind
.table_entry
= NULL
;
3774 unwind
.personality_routine
= NULL
;
3775 unwind
.personality_index
= -1;
3776 unwind
.frame_size
= 0;
3777 unwind
.fp_offset
= 0;
3778 unwind
.fp_reg
= REG_SP
;
3780 unwind
.sp_restored
= 0;
3784 /* Parse a handlerdata directive. Creates the exception handling table entry
3785 for the function. */
3788 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3790 demand_empty_rest_of_line ();
3791 if (!unwind
.proc_start
)
3792 as_bad (MISSING_FNSTART
);
3794 if (unwind
.table_entry
)
3795 as_bad (_("duplicate .handlerdata directive"));
3797 create_unwind_entry (1);
3800 /* Parse an unwind_fnend directive. Generates the index table entry. */
3803 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3808 unsigned int marked_pr_dependency
;
3810 demand_empty_rest_of_line ();
3812 if (!unwind
.proc_start
)
3814 as_bad (_(".fnend directive without .fnstart"));
3818 /* Add eh table entry. */
3819 if (unwind
.table_entry
== NULL
)
3820 val
= create_unwind_entry (0);
3824 /* Add index table entry. This is two words. */
3825 start_unwind_section (unwind
.saved_seg
, 1);
3826 frag_align (2, 0, 0);
3827 record_alignment (now_seg
, 2);
3829 ptr
= frag_more (8);
3831 where
= frag_now_fix () - 8;
3833 /* Self relative offset of the function start. */
3834 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3835 BFD_RELOC_ARM_PREL31
);
3837 /* Indicate dependency on EHABI-defined personality routines to the
3838 linker, if it hasn't been done already. */
3839 marked_pr_dependency
3840 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3841 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3842 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3844 static const char *const name
[] =
3846 "__aeabi_unwind_cpp_pr0",
3847 "__aeabi_unwind_cpp_pr1",
3848 "__aeabi_unwind_cpp_pr2"
3850 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3851 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3852 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3853 |= 1 << unwind
.personality_index
;
3857 /* Inline exception table entry. */
3858 md_number_to_chars (ptr
+ 4, val
, 4);
3860 /* Self relative offset of the table entry. */
3861 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3862 BFD_RELOC_ARM_PREL31
);
3864 /* Restore the original section. */
3865 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3867 unwind
.proc_start
= NULL
;
3871 /* Parse an unwind_cantunwind directive. */
3874 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3876 demand_empty_rest_of_line ();
3877 if (!unwind
.proc_start
)
3878 as_bad (MISSING_FNSTART
);
3880 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3881 as_bad (_("personality routine specified for cantunwind frame"));
3883 unwind
.personality_index
= -2;
3887 /* Parse a personalityindex directive. */
3890 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3894 if (!unwind
.proc_start
)
3895 as_bad (MISSING_FNSTART
);
3897 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3898 as_bad (_("duplicate .personalityindex directive"));
3902 if (exp
.X_op
!= O_constant
3903 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3905 as_bad (_("bad personality routine number"));
3906 ignore_rest_of_line ();
3910 unwind
.personality_index
= exp
.X_add_number
;
3912 demand_empty_rest_of_line ();
3916 /* Parse a personality directive. */
3919 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3923 if (!unwind
.proc_start
)
3924 as_bad (MISSING_FNSTART
);
3926 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3927 as_bad (_("duplicate .personality directive"));
3929 c
= get_symbol_name (& name
);
3930 p
= input_line_pointer
;
3932 ++ input_line_pointer
;
3933 unwind
.personality_routine
= symbol_find_or_make (name
);
3935 demand_empty_rest_of_line ();
3939 /* Parse a directive saving core registers. */
3942 s_arm_unwind_save_core (void)
3948 range
= parse_reg_list (&input_line_pointer
);
3951 as_bad (_("expected register list"));
3952 ignore_rest_of_line ();
3956 demand_empty_rest_of_line ();
3958 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3959 into .unwind_save {..., sp...}. We aren't bothered about the value of
3960 ip because it is clobbered by calls. */
3961 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3962 && (range
& 0x3000) == 0x1000)
3964 unwind
.opcode_count
--;
3965 unwind
.sp_restored
= 0;
3966 range
= (range
| 0x2000) & ~0x1000;
3967 unwind
.pending_offset
= 0;
3973 /* See if we can use the short opcodes. These pop a block of up to 8
3974 registers starting with r4, plus maybe r14. */
3975 for (n
= 0; n
< 8; n
++)
3977 /* Break at the first non-saved register. */
3978 if ((range
& (1 << (n
+ 4))) == 0)
3981 /* See if there are any other bits set. */
3982 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3984 /* Use the long form. */
3985 op
= 0x8000 | ((range
>> 4) & 0xfff);
3986 add_unwind_opcode (op
, 2);
3990 /* Use the short form. */
3992 op
= 0xa8; /* Pop r14. */
3994 op
= 0xa0; /* Do not pop r14. */
3996 add_unwind_opcode (op
, 1);
4003 op
= 0xb100 | (range
& 0xf);
4004 add_unwind_opcode (op
, 2);
4007 /* Record the number of bytes pushed. */
4008 for (n
= 0; n
< 16; n
++)
4010 if (range
& (1 << n
))
4011 unwind
.frame_size
+= 4;
4016 /* Parse a directive saving FPA registers. */
4019 s_arm_unwind_save_fpa (int reg
)
4025 /* Get Number of registers to transfer. */
4026 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4029 exp
.X_op
= O_illegal
;
4031 if (exp
.X_op
!= O_constant
)
4033 as_bad (_("expected , <constant>"));
4034 ignore_rest_of_line ();
4038 num_regs
= exp
.X_add_number
;
4040 if (num_regs
< 1 || num_regs
> 4)
4042 as_bad (_("number of registers must be in the range [1:4]"));
4043 ignore_rest_of_line ();
4047 demand_empty_rest_of_line ();
4052 op
= 0xb4 | (num_regs
- 1);
4053 add_unwind_opcode (op
, 1);
4058 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4059 add_unwind_opcode (op
, 2);
4061 unwind
.frame_size
+= num_regs
* 12;
4065 /* Parse a directive saving VFP registers for ARMv6 and above. */
4068 s_arm_unwind_save_vfp_armv6 (void)
4073 int num_vfpv3_regs
= 0;
4074 int num_regs_below_16
;
4076 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4086 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4087 than FSTMX/FLDMX-style ones). */
4089 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4091 num_vfpv3_regs
= count
;
4092 else if (start
+ count
> 16)
4093 num_vfpv3_regs
= start
+ count
- 16;
4095 if (num_vfpv3_regs
> 0)
4097 int start_offset
= start
> 16 ? start
- 16 : 0;
4098 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4099 add_unwind_opcode (op
, 2);
4102 /* Generate opcode for registers numbered in the range 0 .. 15. */
4103 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4104 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4105 if (num_regs_below_16
> 0)
4107 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4108 add_unwind_opcode (op
, 2);
4111 unwind
.frame_size
+= count
* 8;
4115 /* Parse a directive saving VFP registers for pre-ARMv6. */
4118 s_arm_unwind_save_vfp (void)
4124 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4127 as_bad (_("expected register list"));
4128 ignore_rest_of_line ();
4132 demand_empty_rest_of_line ();
4137 op
= 0xb8 | (count
- 1);
4138 add_unwind_opcode (op
, 1);
4143 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4144 add_unwind_opcode (op
, 2);
4146 unwind
.frame_size
+= count
* 8 + 4;
4150 /* Parse a directive saving iWMMXt data registers. */
4153 s_arm_unwind_save_mmxwr (void)
4161 if (*input_line_pointer
== '{')
4162 input_line_pointer
++;
4166 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4170 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4175 as_tsktsk (_("register list not in ascending order"));
4178 if (*input_line_pointer
== '-')
4180 input_line_pointer
++;
4181 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4184 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4187 else if (reg
>= hi_reg
)
4189 as_bad (_("bad register range"));
4192 for (; reg
< hi_reg
; reg
++)
4196 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4198 skip_past_char (&input_line_pointer
, '}');
4200 demand_empty_rest_of_line ();
4202 /* Generate any deferred opcodes because we're going to be looking at
4204 flush_pending_unwind ();
4206 for (i
= 0; i
< 16; i
++)
4208 if (mask
& (1 << i
))
4209 unwind
.frame_size
+= 8;
4212 /* Attempt to combine with a previous opcode. We do this because gcc
4213 likes to output separate unwind directives for a single block of
4215 if (unwind
.opcode_count
> 0)
4217 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4218 if ((i
& 0xf8) == 0xc0)
4221 /* Only merge if the blocks are contiguous. */
4224 if ((mask
& 0xfe00) == (1 << 9))
4226 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4227 unwind
.opcode_count
--;
4230 else if (i
== 6 && unwind
.opcode_count
>= 2)
4232 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4236 op
= 0xffff << (reg
- 1);
4238 && ((mask
& op
) == (1u << (reg
- 1))))
4240 op
= (1 << (reg
+ i
+ 1)) - 1;
4241 op
&= ~((1 << reg
) - 1);
4243 unwind
.opcode_count
-= 2;
4250 /* We want to generate opcodes in the order the registers have been
4251 saved, ie. descending order. */
4252 for (reg
= 15; reg
>= -1; reg
--)
4254 /* Save registers in blocks. */
4256 || !(mask
& (1 << reg
)))
4258 /* We found an unsaved reg. Generate opcodes to save the
4265 op
= 0xc0 | (hi_reg
- 10);
4266 add_unwind_opcode (op
, 1);
4271 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4272 add_unwind_opcode (op
, 2);
4281 ignore_rest_of_line ();
4285 s_arm_unwind_save_mmxwcg (void)
4292 if (*input_line_pointer
== '{')
4293 input_line_pointer
++;
4295 skip_whitespace (input_line_pointer
);
4299 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4303 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4309 as_tsktsk (_("register list not in ascending order"));
4312 if (*input_line_pointer
== '-')
4314 input_line_pointer
++;
4315 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4318 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4321 else if (reg
>= hi_reg
)
4323 as_bad (_("bad register range"));
4326 for (; reg
< hi_reg
; reg
++)
4330 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4332 skip_past_char (&input_line_pointer
, '}');
4334 demand_empty_rest_of_line ();
4336 /* Generate any deferred opcodes because we're going to be looking at
4338 flush_pending_unwind ();
4340 for (reg
= 0; reg
< 16; reg
++)
4342 if (mask
& (1 << reg
))
4343 unwind
.frame_size
+= 4;
4346 add_unwind_opcode (op
, 2);
4349 ignore_rest_of_line ();
4353 /* Parse an unwind_save directive.
4354 If the argument is non-zero, this is a .vsave directive. */
4357 s_arm_unwind_save (int arch_v6
)
4360 struct reg_entry
*reg
;
4361 bfd_boolean had_brace
= FALSE
;
4363 if (!unwind
.proc_start
)
4364 as_bad (MISSING_FNSTART
);
4366 /* Figure out what sort of save we have. */
4367 peek
= input_line_pointer
;
4375 reg
= arm_reg_parse_multi (&peek
);
4379 as_bad (_("register expected"));
4380 ignore_rest_of_line ();
4389 as_bad (_("FPA .unwind_save does not take a register list"));
4390 ignore_rest_of_line ();
4393 input_line_pointer
= peek
;
4394 s_arm_unwind_save_fpa (reg
->number
);
4398 s_arm_unwind_save_core ();
4403 s_arm_unwind_save_vfp_armv6 ();
4405 s_arm_unwind_save_vfp ();
4408 case REG_TYPE_MMXWR
:
4409 s_arm_unwind_save_mmxwr ();
4412 case REG_TYPE_MMXWCG
:
4413 s_arm_unwind_save_mmxwcg ();
4417 as_bad (_(".unwind_save does not support this kind of register"));
4418 ignore_rest_of_line ();
4423 /* Parse an unwind_movsp directive. */
4426 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4438 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4439 ignore_rest_of_line ();
4443 /* Optional constant. */
4444 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4446 if (immediate_for_directive (&offset
) == FAIL
)
4452 demand_empty_rest_of_line ();
4454 if (reg
== REG_SP
|| reg
== REG_PC
)
4456 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4460 if (unwind
.fp_reg
!= REG_SP
)
4461 as_bad (_("unexpected .unwind_movsp directive"));
4463 /* Generate opcode to restore the value. */
4465 add_unwind_opcode (op
, 1);
4467 /* Record the information for later. */
4468 unwind
.fp_reg
= reg
;
4469 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4470 unwind
.sp_restored
= 1;
4473 /* Parse an unwind_pad directive. */
4476 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4480 if (!unwind
.proc_start
)
4481 as_bad (MISSING_FNSTART
);
4483 if (immediate_for_directive (&offset
) == FAIL
)
4488 as_bad (_("stack increment must be multiple of 4"));
4489 ignore_rest_of_line ();
4493 /* Don't generate any opcodes, just record the details for later. */
4494 unwind
.frame_size
+= offset
;
4495 unwind
.pending_offset
+= offset
;
4497 demand_empty_rest_of_line ();
4500 /* Parse an unwind_setfp directive. */
4503 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4509 if (!unwind
.proc_start
)
4510 as_bad (MISSING_FNSTART
);
4512 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4513 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4516 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4518 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4520 as_bad (_("expected <reg>, <reg>"));
4521 ignore_rest_of_line ();
4525 /* Optional constant. */
4526 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4528 if (immediate_for_directive (&offset
) == FAIL
)
4534 demand_empty_rest_of_line ();
4536 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4538 as_bad (_("register must be either sp or set by a previous"
4539 "unwind_movsp directive"));
4543 /* Don't generate any opcodes, just record the information for later. */
4544 unwind
.fp_reg
= fp_reg
;
4546 if (sp_reg
== REG_SP
)
4547 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4549 unwind
.fp_offset
-= offset
;
4552 /* Parse an unwind_raw directive. */
4555 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4558 /* This is an arbitrary limit. */
4559 unsigned char op
[16];
4562 if (!unwind
.proc_start
)
4563 as_bad (MISSING_FNSTART
);
4566 if (exp
.X_op
== O_constant
4567 && skip_past_comma (&input_line_pointer
) != FAIL
)
4569 unwind
.frame_size
+= exp
.X_add_number
;
4573 exp
.X_op
= O_illegal
;
4575 if (exp
.X_op
!= O_constant
)
4577 as_bad (_("expected <offset>, <opcode>"));
4578 ignore_rest_of_line ();
4584 /* Parse the opcode. */
4589 as_bad (_("unwind opcode too long"));
4590 ignore_rest_of_line ();
4592 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4594 as_bad (_("invalid unwind opcode"));
4595 ignore_rest_of_line ();
4598 op
[count
++] = exp
.X_add_number
;
4600 /* Parse the next byte. */
4601 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4607 /* Add the opcode bytes in reverse order. */
4609 add_unwind_opcode (op
[count
], 1);
4611 demand_empty_rest_of_line ();
4615 /* Parse a .eabi_attribute directive. */
4618 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4620 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4622 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4623 attributes_set_explicitly
[tag
] = 1;
4626 /* Emit a tls fix for the symbol. */
4629 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4633 #ifdef md_flush_pending_output
4634 md_flush_pending_output ();
4637 #ifdef md_cons_align
4641 /* Since we're just labelling the code, there's no need to define a
4644 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4645 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4646 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4647 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4649 #endif /* OBJ_ELF */
4651 static void s_arm_arch (int);
4652 static void s_arm_object_arch (int);
4653 static void s_arm_cpu (int);
4654 static void s_arm_fpu (int);
4655 static void s_arm_arch_extension (int);
4660 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4667 if (exp
.X_op
== O_symbol
)
4668 exp
.X_op
= O_secrel
;
4670 emit_expr (&exp
, 4);
4672 while (*input_line_pointer
++ == ',');
4674 input_line_pointer
--;
4675 demand_empty_rest_of_line ();
4679 /* This table describes all the machine specific pseudo-ops the assembler
4680 has to support. The fields are:
4681 pseudo-op name without dot
4682 function to call to execute this pseudo-op
4683 Integer arg to pass to the function. */
4685 const pseudo_typeS md_pseudo_table
[] =
4687 /* Never called because '.req' does not start a line. */
4688 { "req", s_req
, 0 },
4689 /* Following two are likewise never called. */
4692 { "unreq", s_unreq
, 0 },
4693 { "bss", s_bss
, 0 },
4694 { "align", s_align_ptwo
, 2 },
4695 { "arm", s_arm
, 0 },
4696 { "thumb", s_thumb
, 0 },
4697 { "code", s_code
, 0 },
4698 { "force_thumb", s_force_thumb
, 0 },
4699 { "thumb_func", s_thumb_func
, 0 },
4700 { "thumb_set", s_thumb_set
, 0 },
4701 { "even", s_even
, 0 },
4702 { "ltorg", s_ltorg
, 0 },
4703 { "pool", s_ltorg
, 0 },
4704 { "syntax", s_syntax
, 0 },
4705 { "cpu", s_arm_cpu
, 0 },
4706 { "arch", s_arm_arch
, 0 },
4707 { "object_arch", s_arm_object_arch
, 0 },
4708 { "fpu", s_arm_fpu
, 0 },
4709 { "arch_extension", s_arm_arch_extension
, 0 },
4711 { "word", s_arm_elf_cons
, 4 },
4712 { "long", s_arm_elf_cons
, 4 },
4713 { "inst.n", s_arm_elf_inst
, 2 },
4714 { "inst.w", s_arm_elf_inst
, 4 },
4715 { "inst", s_arm_elf_inst
, 0 },
4716 { "rel31", s_arm_rel31
, 0 },
4717 { "fnstart", s_arm_unwind_fnstart
, 0 },
4718 { "fnend", s_arm_unwind_fnend
, 0 },
4719 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4720 { "personality", s_arm_unwind_personality
, 0 },
4721 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4722 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4723 { "save", s_arm_unwind_save
, 0 },
4724 { "vsave", s_arm_unwind_save
, 1 },
4725 { "movsp", s_arm_unwind_movsp
, 0 },
4726 { "pad", s_arm_unwind_pad
, 0 },
4727 { "setfp", s_arm_unwind_setfp
, 0 },
4728 { "unwind_raw", s_arm_unwind_raw
, 0 },
4729 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4730 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4734 /* These are used for dwarf. */
4738 /* These are used for dwarf2. */
4739 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4740 { "loc", dwarf2_directive_loc
, 0 },
4741 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4743 { "extend", float_cons
, 'x' },
4744 { "ldouble", float_cons
, 'x' },
4745 { "packed", float_cons
, 'p' },
4747 {"secrel32", pe_directive_secrel
, 0},
4750 /* These are for compatibility with CodeComposer Studio. */
4751 {"ref", s_ccs_ref
, 0},
4752 {"def", s_ccs_def
, 0},
4753 {"asmfunc", s_ccs_asmfunc
, 0},
4754 {"endasmfunc", s_ccs_endasmfunc
, 0},
4759 /* Parser functions used exclusively in instruction operands. */
4761 /* Generic immediate-value read function for use in insn parsing.
4762 STR points to the beginning of the immediate (the leading #);
4763 VAL receives the value; if the value is outside [MIN, MAX]
4764 issue an error. PREFIX_OPT is true if the immediate prefix is
4768 parse_immediate (char **str
, int *val
, int min
, int max
,
4769 bfd_boolean prefix_opt
)
4772 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4773 if (exp
.X_op
!= O_constant
)
4775 inst
.error
= _("constant expression required");
4779 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4781 inst
.error
= _("immediate value out of range");
4785 *val
= exp
.X_add_number
;
4789 /* Less-generic immediate-value read function with the possibility of loading a
4790 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4791 instructions. Puts the result directly in inst.operands[i]. */
4794 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4795 bfd_boolean allow_symbol_p
)
4798 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4801 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4803 if (exp_p
->X_op
== O_constant
)
4805 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4806 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4807 O_constant. We have to be careful not to break compilation for
4808 32-bit X_add_number, though. */
4809 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4811 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4812 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4814 inst
.operands
[i
].regisimm
= 1;
4817 else if (exp_p
->X_op
== O_big
4818 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4820 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4822 /* Bignums have their least significant bits in
4823 generic_bignum[0]. Make sure we put 32 bits in imm and
4824 32 bits in reg, in a (hopefully) portable way. */
4825 gas_assert (parts
!= 0);
4827 /* Make sure that the number is not too big.
4828 PR 11972: Bignums can now be sign-extended to the
4829 size of a .octa so check that the out of range bits
4830 are all zero or all one. */
4831 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4833 LITTLENUM_TYPE m
= -1;
4835 if (generic_bignum
[parts
* 2] != 0
4836 && generic_bignum
[parts
* 2] != m
)
4839 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4840 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4844 inst
.operands
[i
].imm
= 0;
4845 for (j
= 0; j
< parts
; j
++, idx
++)
4846 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4847 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4848 inst
.operands
[i
].reg
= 0;
4849 for (j
= 0; j
< parts
; j
++, idx
++)
4850 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4851 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4852 inst
.operands
[i
].regisimm
= 1;
4854 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4862 /* Returns the pseudo-register number of an FPA immediate constant,
4863 or FAIL if there isn't a valid constant here. */
4866 parse_fpa_immediate (char ** str
)
4868 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4874 /* First try and match exact strings, this is to guarantee
4875 that some formats will work even for cross assembly. */
4877 for (i
= 0; fp_const
[i
]; i
++)
4879 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4883 *str
+= strlen (fp_const
[i
]);
4884 if (is_end_of_line
[(unsigned char) **str
])
4890 /* Just because we didn't get a match doesn't mean that the constant
4891 isn't valid, just that it is in a format that we don't
4892 automatically recognize. Try parsing it with the standard
4893 expression routines. */
4895 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4897 /* Look for a raw floating point number. */
4898 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4899 && is_end_of_line
[(unsigned char) *save_in
])
4901 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4903 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4905 if (words
[j
] != fp_values
[i
][j
])
4909 if (j
== MAX_LITTLENUMS
)
4917 /* Try and parse a more complex expression, this will probably fail
4918 unless the code uses a floating point prefix (eg "0f"). */
4919 save_in
= input_line_pointer
;
4920 input_line_pointer
= *str
;
4921 if (expression (&exp
) == absolute_section
4922 && exp
.X_op
== O_big
4923 && exp
.X_add_number
< 0)
4925 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4927 #define X_PRECISION 5
4928 #define E_PRECISION 15L
4929 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4931 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4933 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4935 if (words
[j
] != fp_values
[i
][j
])
4939 if (j
== MAX_LITTLENUMS
)
4941 *str
= input_line_pointer
;
4942 input_line_pointer
= save_in
;
4949 *str
= input_line_pointer
;
4950 input_line_pointer
= save_in
;
4951 inst
.error
= _("invalid FPA immediate expression");
4955 /* Returns 1 if a number has "quarter-precision" float format
4956 0baBbbbbbc defgh000 00000000 00000000. */
4959 is_quarter_float (unsigned imm
)
4961 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4962 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4966 /* Detect the presence of a floating point or integer zero constant,
4970 parse_ifimm_zero (char **in
)
4974 if (!is_immediate_prefix (**in
))
4976 /* In unified syntax, all prefixes are optional. */
4977 if (!unified_syntax
)
4983 /* Accept #0x0 as a synonym for #0. */
4984 if (strncmp (*in
, "0x", 2) == 0)
4987 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4992 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4993 &generic_floating_point_number
);
4996 && generic_floating_point_number
.sign
== '+'
4997 && (generic_floating_point_number
.low
4998 > generic_floating_point_number
.leader
))
5004 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5005 0baBbbbbbc defgh000 00000000 00000000.
5006 The zero and minus-zero cases need special handling, since they can't be
5007 encoded in the "quarter-precision" float format, but can nonetheless be
5008 loaded as integer constants. */
5011 parse_qfloat_immediate (char **ccp
, int *immed
)
5015 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5016 int found_fpchar
= 0;
5018 skip_past_char (&str
, '#');
5020 /* We must not accidentally parse an integer as a floating-point number. Make
5021 sure that the value we parse is not an integer by checking for special
5022 characters '.' or 'e'.
5023 FIXME: This is a horrible hack, but doing better is tricky because type
5024 information isn't in a very usable state at parse time. */
5026 skip_whitespace (fpnum
);
5028 if (strncmp (fpnum
, "0x", 2) == 0)
5032 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5033 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5043 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5045 unsigned fpword
= 0;
5048 /* Our FP word must be 32 bits (single-precision FP). */
5049 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5051 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5055 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5068 /* Shift operands. */
5071 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5074 struct asm_shift_name
5077 enum shift_kind kind
;
5080 /* Third argument to parse_shift. */
5081 enum parse_shift_mode
5083 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5084 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5085 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5086 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5087 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5090 /* Parse a <shift> specifier on an ARM data processing instruction.
5091 This has three forms:
5093 (LSL|LSR|ASL|ASR|ROR) Rs
5094 (LSL|LSR|ASL|ASR|ROR) #imm
5097 Note that ASL is assimilated to LSL in the instruction encoding, and
5098 RRX to ROR #0 (which cannot be written as such). */
5101 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5103 const struct asm_shift_name
*shift_name
;
5104 enum shift_kind shift
;
5109 for (p
= *str
; ISALPHA (*p
); p
++)
5114 inst
.error
= _("shift expression expected");
5118 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5121 if (shift_name
== NULL
)
5123 inst
.error
= _("shift expression expected");
5127 shift
= shift_name
->kind
;
5131 case NO_SHIFT_RESTRICT
:
5132 case SHIFT_IMMEDIATE
: break;
5134 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5135 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5137 inst
.error
= _("'LSL' or 'ASR' required");
5142 case SHIFT_LSL_IMMEDIATE
:
5143 if (shift
!= SHIFT_LSL
)
5145 inst
.error
= _("'LSL' required");
5150 case SHIFT_ASR_IMMEDIATE
:
5151 if (shift
!= SHIFT_ASR
)
5153 inst
.error
= _("'ASR' required");
5161 if (shift
!= SHIFT_RRX
)
5163 /* Whitespace can appear here if the next thing is a bare digit. */
5164 skip_whitespace (p
);
5166 if (mode
== NO_SHIFT_RESTRICT
5167 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5169 inst
.operands
[i
].imm
= reg
;
5170 inst
.operands
[i
].immisreg
= 1;
5172 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5175 inst
.operands
[i
].shift_kind
= shift
;
5176 inst
.operands
[i
].shifted
= 1;
5181 /* Parse a <shifter_operand> for an ARM data processing instruction:
5184 #<immediate>, <rotate>
5188 where <shift> is defined by parse_shift above, and <rotate> is a
5189 multiple of 2 between 0 and 30. Validation of immediate operands
5190 is deferred to md_apply_fix. */
5193 parse_shifter_operand (char **str
, int i
)
5198 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5200 inst
.operands
[i
].reg
= value
;
5201 inst
.operands
[i
].isreg
= 1;
5203 /* parse_shift will override this if appropriate */
5204 inst
.reloc
.exp
.X_op
= O_constant
;
5205 inst
.reloc
.exp
.X_add_number
= 0;
5207 if (skip_past_comma (str
) == FAIL
)
5210 /* Shift operation on register. */
5211 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5214 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5217 if (skip_past_comma (str
) == SUCCESS
)
5219 /* #x, y -- ie explicit rotation by Y. */
5220 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5223 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5225 inst
.error
= _("constant expression expected");
5229 value
= exp
.X_add_number
;
5230 if (value
< 0 || value
> 30 || value
% 2 != 0)
5232 inst
.error
= _("invalid rotation");
5235 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5237 inst
.error
= _("invalid constant");
5241 /* Encode as specified. */
5242 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5246 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5247 inst
.reloc
.pc_rel
= 0;
5251 /* Group relocation information. Each entry in the table contains the
5252 textual name of the relocation as may appear in assembler source
5253 and must end with a colon.
5254 Along with this textual name are the relocation codes to be used if
5255 the corresponding instruction is an ALU instruction (ADD or SUB only),
5256 an LDR, an LDRS, or an LDC. */
5258 struct group_reloc_table_entry
5269 /* Varieties of non-ALU group relocation. */
5276 static struct group_reloc_table_entry group_reloc_table
[] =
5277 { /* Program counter relative: */
5279 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5284 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5285 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5286 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5287 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5289 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5294 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5295 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5296 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5297 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5299 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5300 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5301 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5302 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5303 /* Section base relative */
5305 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5310 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5311 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5312 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5313 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5315 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5320 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5321 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5322 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5323 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5325 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5326 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5327 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5328 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5329 /* Absolute thumb alu relocations. */
5331 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5336 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5341 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5346 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5351 /* Given the address of a pointer pointing to the textual name of a group
5352 relocation as may appear in assembler source, attempt to find its details
5353 in group_reloc_table. The pointer will be updated to the character after
5354 the trailing colon. On failure, FAIL will be returned; SUCCESS
5355 otherwise. On success, *entry will be updated to point at the relevant
5356 group_reloc_table entry. */
5359 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5362 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5364 int length
= strlen (group_reloc_table
[i
].name
);
5366 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5367 && (*str
)[length
] == ':')
5369 *out
= &group_reloc_table
[i
];
5370 *str
+= (length
+ 1);
5378 /* Parse a <shifter_operand> for an ARM data processing instruction
5379 (as for parse_shifter_operand) where group relocations are allowed:
5382 #<immediate>, <rotate>
5383 #:<group_reloc>:<expression>
5387 where <group_reloc> is one of the strings defined in group_reloc_table.
5388 The hashes are optional.
5390 Everything else is as for parse_shifter_operand. */
5392 static parse_operand_result
5393 parse_shifter_operand_group_reloc (char **str
, int i
)
5395 /* Determine if we have the sequence of characters #: or just :
5396 coming next. If we do, then we check for a group relocation.
5397 If we don't, punt the whole lot to parse_shifter_operand. */
5399 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5400 || (*str
)[0] == ':')
5402 struct group_reloc_table_entry
*entry
;
5404 if ((*str
)[0] == '#')
5409 /* Try to parse a group relocation. Anything else is an error. */
5410 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5412 inst
.error
= _("unknown group relocation");
5413 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5416 /* We now have the group relocation table entry corresponding to
5417 the name in the assembler source. Next, we parse the expression. */
5418 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5419 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5421 /* Record the relocation type (always the ALU variant here). */
5422 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5423 gas_assert (inst
.reloc
.type
!= 0);
5425 return PARSE_OPERAND_SUCCESS
;
5428 return parse_shifter_operand (str
, i
) == SUCCESS
5429 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5431 /* Never reached. */
5434 /* Parse a Neon alignment expression. Information is written to
5435 inst.operands[i]. We assume the initial ':' has been skipped.
5437 align .imm = align << 8, .immisalign=1, .preind=0 */
5438 static parse_operand_result
5439 parse_neon_alignment (char **str
, int i
)
5444 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5446 if (exp
.X_op
!= O_constant
)
5448 inst
.error
= _("alignment must be constant");
5449 return PARSE_OPERAND_FAIL
;
5452 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5453 inst
.operands
[i
].immisalign
= 1;
5454 /* Alignments are not pre-indexes. */
5455 inst
.operands
[i
].preind
= 0;
5458 return PARSE_OPERAND_SUCCESS
;
5461 /* Parse all forms of an ARM address expression. Information is written
5462 to inst.operands[i] and/or inst.reloc.
5464 Preindexed addressing (.preind=1):
5466 [Rn, #offset] .reg=Rn .reloc.exp=offset
5467 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5468 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5469 .shift_kind=shift .reloc.exp=shift_imm
5471 These three may have a trailing ! which causes .writeback to be set also.
5473 Postindexed addressing (.postind=1, .writeback=1):
5475 [Rn], #offset .reg=Rn .reloc.exp=offset
5476 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5477 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5478 .shift_kind=shift .reloc.exp=shift_imm
5480 Unindexed addressing (.preind=0, .postind=0):
5482 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5486 [Rn]{!} shorthand for [Rn,#0]{!}
5487 =immediate .isreg=0 .reloc.exp=immediate
5488 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5490 It is the caller's responsibility to check for addressing modes not
5491 supported by the instruction, and to set inst.reloc.type. */
5493 static parse_operand_result
5494 parse_address_main (char **str
, int i
, int group_relocations
,
5495 group_reloc_type group_type
)
5500 if (skip_past_char (&p
, '[') == FAIL
)
5502 if (skip_past_char (&p
, '=') == FAIL
)
5504 /* Bare address - translate to PC-relative offset. */
5505 inst
.reloc
.pc_rel
= 1;
5506 inst
.operands
[i
].reg
= REG_PC
;
5507 inst
.operands
[i
].isreg
= 1;
5508 inst
.operands
[i
].preind
= 1;
5510 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5511 return PARSE_OPERAND_FAIL
;
5513 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5514 /*allow_symbol_p=*/TRUE
))
5515 return PARSE_OPERAND_FAIL
;
5518 return PARSE_OPERAND_SUCCESS
;
5521 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5522 skip_whitespace (p
);
5524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5527 return PARSE_OPERAND_FAIL
;
5529 inst
.operands
[i
].reg
= reg
;
5530 inst
.operands
[i
].isreg
= 1;
5532 if (skip_past_comma (&p
) == SUCCESS
)
5534 inst
.operands
[i
].preind
= 1;
5537 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5539 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5541 inst
.operands
[i
].imm
= reg
;
5542 inst
.operands
[i
].immisreg
= 1;
5544 if (skip_past_comma (&p
) == SUCCESS
)
5545 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5546 return PARSE_OPERAND_FAIL
;
5548 else if (skip_past_char (&p
, ':') == SUCCESS
)
5550 /* FIXME: '@' should be used here, but it's filtered out by generic
5551 code before we get to see it here. This may be subject to
5553 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5555 if (result
!= PARSE_OPERAND_SUCCESS
)
5560 if (inst
.operands
[i
].negative
)
5562 inst
.operands
[i
].negative
= 0;
5566 if (group_relocations
5567 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5569 struct group_reloc_table_entry
*entry
;
5571 /* Skip over the #: or : sequence. */
5577 /* Try to parse a group relocation. Anything else is an
5579 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5581 inst
.error
= _("unknown group relocation");
5582 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5585 /* We now have the group relocation table entry corresponding to
5586 the name in the assembler source. Next, we parse the
5588 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5589 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5591 /* Record the relocation type. */
5595 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5599 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5603 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5610 if (inst
.reloc
.type
== 0)
5612 inst
.error
= _("this group relocation is not allowed on this instruction");
5613 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5619 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5620 return PARSE_OPERAND_FAIL
;
5621 /* If the offset is 0, find out if it's a +0 or -0. */
5622 if (inst
.reloc
.exp
.X_op
== O_constant
5623 && inst
.reloc
.exp
.X_add_number
== 0)
5625 skip_whitespace (q
);
5629 skip_whitespace (q
);
5632 inst
.operands
[i
].negative
= 1;
5637 else if (skip_past_char (&p
, ':') == SUCCESS
)
5639 /* FIXME: '@' should be used here, but it's filtered out by generic code
5640 before we get to see it here. This may be subject to change. */
5641 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5643 if (result
!= PARSE_OPERAND_SUCCESS
)
5647 if (skip_past_char (&p
, ']') == FAIL
)
5649 inst
.error
= _("']' expected");
5650 return PARSE_OPERAND_FAIL
;
5653 if (skip_past_char (&p
, '!') == SUCCESS
)
5654 inst
.operands
[i
].writeback
= 1;
5656 else if (skip_past_comma (&p
) == SUCCESS
)
5658 if (skip_past_char (&p
, '{') == SUCCESS
)
5660 /* [Rn], {expr} - unindexed, with option */
5661 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5662 0, 255, TRUE
) == FAIL
)
5663 return PARSE_OPERAND_FAIL
;
5665 if (skip_past_char (&p
, '}') == FAIL
)
5667 inst
.error
= _("'}' expected at end of 'option' field");
5668 return PARSE_OPERAND_FAIL
;
5670 if (inst
.operands
[i
].preind
)
5672 inst
.error
= _("cannot combine index with option");
5673 return PARSE_OPERAND_FAIL
;
5676 return PARSE_OPERAND_SUCCESS
;
5680 inst
.operands
[i
].postind
= 1;
5681 inst
.operands
[i
].writeback
= 1;
5683 if (inst
.operands
[i
].preind
)
5685 inst
.error
= _("cannot combine pre- and post-indexing");
5686 return PARSE_OPERAND_FAIL
;
5690 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5692 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5694 /* We might be using the immediate for alignment already. If we
5695 are, OR the register number into the low-order bits. */
5696 if (inst
.operands
[i
].immisalign
)
5697 inst
.operands
[i
].imm
|= reg
;
5699 inst
.operands
[i
].imm
= reg
;
5700 inst
.operands
[i
].immisreg
= 1;
5702 if (skip_past_comma (&p
) == SUCCESS
)
5703 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5704 return PARSE_OPERAND_FAIL
;
5709 if (inst
.operands
[i
].negative
)
5711 inst
.operands
[i
].negative
= 0;
5714 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5715 return PARSE_OPERAND_FAIL
;
5716 /* If the offset is 0, find out if it's a +0 or -0. */
5717 if (inst
.reloc
.exp
.X_op
== O_constant
5718 && inst
.reloc
.exp
.X_add_number
== 0)
5720 skip_whitespace (q
);
5724 skip_whitespace (q
);
5727 inst
.operands
[i
].negative
= 1;
5733 /* If at this point neither .preind nor .postind is set, we have a
5734 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5735 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5737 inst
.operands
[i
].preind
= 1;
5738 inst
.reloc
.exp
.X_op
= O_constant
;
5739 inst
.reloc
.exp
.X_add_number
= 0;
5742 return PARSE_OPERAND_SUCCESS
;
5746 parse_address (char **str
, int i
)
5748 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5752 static parse_operand_result
5753 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5755 return parse_address_main (str
, i
, 1, type
);
5758 /* Parse an operand for a MOVW or MOVT instruction. */
5760 parse_half (char **str
)
5765 skip_past_char (&p
, '#');
5766 if (strncasecmp (p
, ":lower16:", 9) == 0)
5767 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5768 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5769 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5771 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5774 skip_whitespace (p
);
5777 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5780 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5782 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5784 inst
.error
= _("constant expression expected");
5787 if (inst
.reloc
.exp
.X_add_number
< 0
5788 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5790 inst
.error
= _("immediate value out of range");
5798 /* Miscellaneous. */
5800 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5801 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5803 parse_psr (char **str
, bfd_boolean lhs
)
5806 unsigned long psr_field
;
5807 const struct asm_psr
*psr
;
5809 bfd_boolean is_apsr
= FALSE
;
5810 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5812 /* PR gas/12698: If the user has specified -march=all then m_profile will
5813 be TRUE, but we want to ignore it in this case as we are building for any
5814 CPU type, including non-m variants. */
5815 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5818 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5819 feature for ease of use and backwards compatibility. */
5821 if (strncasecmp (p
, "SPSR", 4) == 0)
5824 goto unsupported_psr
;
5826 psr_field
= SPSR_BIT
;
5828 else if (strncasecmp (p
, "CPSR", 4) == 0)
5831 goto unsupported_psr
;
5835 else if (strncasecmp (p
, "APSR", 4) == 0)
5837 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5838 and ARMv7-R architecture CPUs. */
5847 while (ISALNUM (*p
) || *p
== '_');
5849 if (strncasecmp (start
, "iapsr", 5) == 0
5850 || strncasecmp (start
, "eapsr", 5) == 0
5851 || strncasecmp (start
, "xpsr", 4) == 0
5852 || strncasecmp (start
, "psr", 3) == 0)
5853 p
= start
+ strcspn (start
, "rR") + 1;
5855 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5861 /* If APSR is being written, a bitfield may be specified. Note that
5862 APSR itself is handled above. */
5863 if (psr
->field
<= 3)
5865 psr_field
= psr
->field
;
5871 /* M-profile MSR instructions have the mask field set to "10", except
5872 *PSR variants which modify APSR, which may use a different mask (and
5873 have been handled already). Do that by setting the PSR_f field
5875 return psr
->field
| (lhs
? PSR_f
: 0);
5878 goto unsupported_psr
;
5884 /* A suffix follows. */
5890 while (ISALNUM (*p
) || *p
== '_');
5894 /* APSR uses a notation for bits, rather than fields. */
5895 unsigned int nzcvq_bits
= 0;
5896 unsigned int g_bit
= 0;
5899 for (bit
= start
; bit
!= p
; bit
++)
5901 switch (TOLOWER (*bit
))
5904 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5908 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5912 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5916 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5920 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5924 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5928 inst
.error
= _("unexpected bit specified after APSR");
5933 if (nzcvq_bits
== 0x1f)
5938 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5940 inst
.error
= _("selected processor does not "
5941 "support DSP extension");
5948 if ((nzcvq_bits
& 0x20) != 0
5949 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5950 || (g_bit
& 0x2) != 0)
5952 inst
.error
= _("bad bitmask specified after APSR");
5958 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5963 psr_field
|= psr
->field
;
5969 goto error
; /* Garbage after "[CS]PSR". */
5971 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5972 is deprecated, but allow it anyway. */
5976 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5979 else if (!m_profile
)
5980 /* These bits are never right for M-profile devices: don't set them
5981 (only code paths which read/write APSR reach here). */
5982 psr_field
|= (PSR_c
| PSR_f
);
5988 inst
.error
= _("selected processor does not support requested special "
5989 "purpose register");
5993 inst
.error
= _("flag for {c}psr instruction expected");
5997 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5998 value suitable for splatting into the AIF field of the instruction. */
6001 parse_cps_flags (char **str
)
6010 case '\0': case ',':
6013 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6014 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6015 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6018 inst
.error
= _("unrecognized CPS flag");
6023 if (saw_a_flag
== 0)
6025 inst
.error
= _("missing CPS flags");
6033 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6034 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6037 parse_endian_specifier (char **str
)
6042 if (strncasecmp (s
, "BE", 2))
6044 else if (strncasecmp (s
, "LE", 2))
6048 inst
.error
= _("valid endian specifiers are be or le");
6052 if (ISALNUM (s
[2]) || s
[2] == '_')
6054 inst
.error
= _("valid endian specifiers are be or le");
6059 return little_endian
;
6062 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6063 value suitable for poking into the rotate field of an sxt or sxta
6064 instruction, or FAIL on error. */
6067 parse_ror (char **str
)
6072 if (strncasecmp (s
, "ROR", 3) == 0)
6076 inst
.error
= _("missing rotation field after comma");
6080 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6085 case 0: *str
= s
; return 0x0;
6086 case 8: *str
= s
; return 0x1;
6087 case 16: *str
= s
; return 0x2;
6088 case 24: *str
= s
; return 0x3;
6091 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6096 /* Parse a conditional code (from conds[] below). The value returned is in the
6097 range 0 .. 14, or FAIL. */
6099 parse_cond (char **str
)
6102 const struct asm_cond
*c
;
6104 /* Condition codes are always 2 characters, so matching up to
6105 3 characters is sufficient. */
6110 while (ISALPHA (*q
) && n
< 3)
6112 cond
[n
] = TOLOWER (*q
);
6117 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6120 inst
.error
= _("condition required");
6128 /* Record a use of the given feature. */
6130 record_feature_use (const arm_feature_set
*feature
)
6133 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6135 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6138 /* If the given feature available in the selected CPU, mark it as used.
6139 Returns TRUE iff feature is available. */
6141 mark_feature_used (const arm_feature_set
*feature
)
6143 /* Ensure the option is valid on the current architecture. */
6144 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6147 /* Add the appropriate architecture feature for the barrier option used.
6149 record_feature_use (feature
);
6154 /* Parse an option for a barrier instruction. Returns the encoding for the
6157 parse_barrier (char **str
)
6160 const struct asm_barrier_opt
*o
;
6163 while (ISALPHA (*q
))
6166 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6171 if (!mark_feature_used (&o
->arch
))
6178 /* Parse the operands of a table branch instruction. Similar to a memory
6181 parse_tb (char **str
)
6186 if (skip_past_char (&p
, '[') == FAIL
)
6188 inst
.error
= _("'[' expected");
6192 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6194 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6197 inst
.operands
[0].reg
= reg
;
6199 if (skip_past_comma (&p
) == FAIL
)
6201 inst
.error
= _("',' expected");
6205 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6207 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6210 inst
.operands
[0].imm
= reg
;
6212 if (skip_past_comma (&p
) == SUCCESS
)
6214 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6216 if (inst
.reloc
.exp
.X_add_number
!= 1)
6218 inst
.error
= _("invalid shift");
6221 inst
.operands
[0].shifted
= 1;
6224 if (skip_past_char (&p
, ']') == FAIL
)
6226 inst
.error
= _("']' expected");
6233 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6234 information on the types the operands can take and how they are encoded.
6235 Up to four operands may be read; this function handles setting the
6236 ".present" field for each read operand itself.
6237 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6238 else returns FAIL. */
6241 parse_neon_mov (char **str
, int *which_operand
)
6243 int i
= *which_operand
, val
;
6244 enum arm_reg_type rtype
;
6246 struct neon_type_el optype
;
6248 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6250 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isscalar
= 1;
6253 inst
.operands
[i
].vectype
= optype
;
6254 inst
.operands
[i
++].present
= 1;
6256 if (skip_past_comma (&ptr
) == FAIL
)
6259 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6262 inst
.operands
[i
].reg
= val
;
6263 inst
.operands
[i
].isreg
= 1;
6264 inst
.operands
[i
].present
= 1;
6266 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6269 /* Cases 0, 1, 2, 3, 5 (D only). */
6270 if (skip_past_comma (&ptr
) == FAIL
)
6273 inst
.operands
[i
].reg
= val
;
6274 inst
.operands
[i
].isreg
= 1;
6275 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6276 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6277 inst
.operands
[i
].isvec
= 1;
6278 inst
.operands
[i
].vectype
= optype
;
6279 inst
.operands
[i
++].present
= 1;
6281 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6283 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6284 Case 13: VMOV <Sd>, <Rm> */
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isreg
= 1;
6287 inst
.operands
[i
].present
= 1;
6289 if (rtype
== REG_TYPE_NQ
)
6291 first_error (_("can't use Neon quad register here"));
6294 else if (rtype
!= REG_TYPE_VFS
)
6297 if (skip_past_comma (&ptr
) == FAIL
)
6299 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6301 inst
.operands
[i
].reg
= val
;
6302 inst
.operands
[i
].isreg
= 1;
6303 inst
.operands
[i
].present
= 1;
6306 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6309 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6310 Case 1: VMOV<c><q> <Dd>, <Dm>
6311 Case 8: VMOV.F32 <Sd>, <Sm>
6312 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6314 inst
.operands
[i
].reg
= val
;
6315 inst
.operands
[i
].isreg
= 1;
6316 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6317 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6318 inst
.operands
[i
].isvec
= 1;
6319 inst
.operands
[i
].vectype
= optype
;
6320 inst
.operands
[i
].present
= 1;
6322 if (skip_past_comma (&ptr
) == SUCCESS
)
6327 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6330 inst
.operands
[i
].reg
= val
;
6331 inst
.operands
[i
].isreg
= 1;
6332 inst
.operands
[i
++].present
= 1;
6334 if (skip_past_comma (&ptr
) == FAIL
)
6337 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6340 inst
.operands
[i
].reg
= val
;
6341 inst
.operands
[i
].isreg
= 1;
6342 inst
.operands
[i
].present
= 1;
6345 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6346 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6347 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6348 Case 10: VMOV.F32 <Sd>, #<imm>
6349 Case 11: VMOV.F64 <Dd>, #<imm> */
6350 inst
.operands
[i
].immisfloat
= 1;
6351 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6353 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6354 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6358 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6362 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
++].present
= 1;
6369 if (skip_past_comma (&ptr
) == FAIL
)
6372 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6374 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6375 inst
.operands
[i
].reg
= val
;
6376 inst
.operands
[i
].isscalar
= 1;
6377 inst
.operands
[i
].present
= 1;
6378 inst
.operands
[i
].vectype
= optype
;
6380 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6382 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6383 inst
.operands
[i
].reg
= val
;
6384 inst
.operands
[i
].isreg
= 1;
6385 inst
.operands
[i
++].present
= 1;
6387 if (skip_past_comma (&ptr
) == FAIL
)
6390 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6393 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6397 inst
.operands
[i
].reg
= val
;
6398 inst
.operands
[i
].isreg
= 1;
6399 inst
.operands
[i
].isvec
= 1;
6400 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6401 inst
.operands
[i
].vectype
= optype
;
6402 inst
.operands
[i
].present
= 1;
6404 if (rtype
== REG_TYPE_VFS
)
6408 if (skip_past_comma (&ptr
) == FAIL
)
6410 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6413 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6416 inst
.operands
[i
].reg
= val
;
6417 inst
.operands
[i
].isreg
= 1;
6418 inst
.operands
[i
].isvec
= 1;
6419 inst
.operands
[i
].issingle
= 1;
6420 inst
.operands
[i
].vectype
= optype
;
6421 inst
.operands
[i
].present
= 1;
6424 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6428 inst
.operands
[i
].reg
= val
;
6429 inst
.operands
[i
].isreg
= 1;
6430 inst
.operands
[i
].isvec
= 1;
6431 inst
.operands
[i
].issingle
= 1;
6432 inst
.operands
[i
].vectype
= optype
;
6433 inst
.operands
[i
].present
= 1;
6438 first_error (_("parse error"));
6442 /* Successfully parsed the operands. Update args. */
6448 first_error (_("expected comma"));
6452 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6456 /* Use this macro when the operand constraints are different
6457 for ARM and THUMB (e.g. ldrd). */
6458 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6459 ((arm_operand) | ((thumb_operand) << 16))
6461 /* Matcher codes for parse_operands. */
6462 enum operand_parse_code
6464 OP_stop
, /* end of line */
6466 OP_RR
, /* ARM register */
6467 OP_RRnpc
, /* ARM register, not r15 */
6468 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6469 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6470 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6471 optional trailing ! */
6472 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6473 OP_RCP
, /* Coprocessor number */
6474 OP_RCN
, /* Coprocessor register */
6475 OP_RF
, /* FPA register */
6476 OP_RVS
, /* VFP single precision register */
6477 OP_RVD
, /* VFP double precision register (0..15) */
6478 OP_RND
, /* Neon double precision register (0..31) */
6479 OP_RNQ
, /* Neon quad precision register */
6480 OP_RVSD
, /* VFP single or double precision register */
6481 OP_RNDQ
, /* Neon double or quad precision register */
6482 OP_RNSDQ
, /* Neon single, double or quad precision register */
6483 OP_RNSC
, /* Neon scalar D[X] */
6484 OP_RVC
, /* VFP control register */
6485 OP_RMF
, /* Maverick F register */
6486 OP_RMD
, /* Maverick D register */
6487 OP_RMFX
, /* Maverick FX register */
6488 OP_RMDX
, /* Maverick DX register */
6489 OP_RMAX
, /* Maverick AX register */
6490 OP_RMDS
, /* Maverick DSPSC register */
6491 OP_RIWR
, /* iWMMXt wR register */
6492 OP_RIWC
, /* iWMMXt wC register */
6493 OP_RIWG
, /* iWMMXt wCG register */
6494 OP_RXA
, /* XScale accumulator register */
6496 OP_REGLST
, /* ARM register list */
6497 OP_VRSLST
, /* VFP single-precision register list */
6498 OP_VRDLST
, /* VFP double-precision register list */
6499 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6500 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6501 OP_NSTRLST
, /* Neon element/structure list */
6503 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6504 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6505 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6506 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6507 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6508 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6509 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6510 OP_VMOV
, /* Neon VMOV operands. */
6511 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6512 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6513 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6515 OP_I0
, /* immediate zero */
6516 OP_I7
, /* immediate value 0 .. 7 */
6517 OP_I15
, /* 0 .. 15 */
6518 OP_I16
, /* 1 .. 16 */
6519 OP_I16z
, /* 0 .. 16 */
6520 OP_I31
, /* 0 .. 31 */
6521 OP_I31w
, /* 0 .. 31, optional trailing ! */
6522 OP_I32
, /* 1 .. 32 */
6523 OP_I32z
, /* 0 .. 32 */
6524 OP_I63
, /* 0 .. 63 */
6525 OP_I63s
, /* -64 .. 63 */
6526 OP_I64
, /* 1 .. 64 */
6527 OP_I64z
, /* 0 .. 64 */
6528 OP_I255
, /* 0 .. 255 */
6530 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6531 OP_I7b
, /* 0 .. 7 */
6532 OP_I15b
, /* 0 .. 15 */
6533 OP_I31b
, /* 0 .. 31 */
6535 OP_SH
, /* shifter operand */
6536 OP_SHG
, /* shifter operand with possible group relocation */
6537 OP_ADDR
, /* Memory address expression (any mode) */
6538 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6539 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6540 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6541 OP_EXP
, /* arbitrary expression */
6542 OP_EXPi
, /* same, with optional immediate prefix */
6543 OP_EXPr
, /* same, with optional relocation suffix */
6544 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6545 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6546 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6548 OP_CPSF
, /* CPS flags */
6549 OP_ENDI
, /* Endianness specifier */
6550 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6551 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6552 OP_COND
, /* conditional code */
6553 OP_TB
, /* Table branch. */
6555 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6557 OP_RRnpc_I0
, /* ARM register or literal 0 */
6558 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6559 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6560 OP_RF_IF
, /* FPA register or immediate */
6561 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6562 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6564 /* Optional operands. */
6565 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6566 OP_oI31b
, /* 0 .. 31 */
6567 OP_oI32b
, /* 1 .. 32 */
6568 OP_oI32z
, /* 0 .. 32 */
6569 OP_oIffffb
, /* 0 .. 65535 */
6570 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6572 OP_oRR
, /* ARM register */
6573 OP_oRRnpc
, /* ARM register, not the PC */
6574 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6575 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6576 OP_oRND
, /* Optional Neon double precision register */
6577 OP_oRNQ
, /* Optional Neon quad precision register */
6578 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6579 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6580 OP_oSHll
, /* LSL immediate */
6581 OP_oSHar
, /* ASR immediate */
6582 OP_oSHllar
, /* LSL or ASR immediate */
6583 OP_oROR
, /* ROR 0/8/16/24 */
6584 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6586 /* Some pre-defined mixed (ARM/THUMB) operands. */
6587 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6588 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6589 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6591 OP_FIRST_OPTIONAL
= OP_oI7b
6594 /* Generic instruction operand parser. This does no encoding and no
6595 semantic validation; it merely squirrels values away in the inst
6596 structure. Returns SUCCESS or FAIL depending on whether the
6597 specified grammar matched. */
6599 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6601 unsigned const int *upat
= pattern
;
6602 char *backtrack_pos
= 0;
6603 const char *backtrack_error
= 0;
6604 int i
, val
= 0, backtrack_index
= 0;
6605 enum arm_reg_type rtype
;
6606 parse_operand_result result
;
6607 unsigned int op_parse_code
;
6609 #define po_char_or_fail(chr) \
6612 if (skip_past_char (&str, chr) == FAIL) \
6617 #define po_reg_or_fail(regtype) \
6620 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6621 & inst.operands[i].vectype); \
6624 first_error (_(reg_expected_msgs[regtype])); \
6627 inst.operands[i].reg = val; \
6628 inst.operands[i].isreg = 1; \
6629 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6630 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6631 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6632 || rtype == REG_TYPE_VFD \
6633 || rtype == REG_TYPE_NQ); \
6637 #define po_reg_or_goto(regtype, label) \
6640 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6641 & inst.operands[i].vectype); \
6645 inst.operands[i].reg = val; \
6646 inst.operands[i].isreg = 1; \
6647 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6648 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6649 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6650 || rtype == REG_TYPE_VFD \
6651 || rtype == REG_TYPE_NQ); \
6655 #define po_imm_or_fail(min, max, popt) \
6658 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6660 inst.operands[i].imm = val; \
6664 #define po_scalar_or_goto(elsz, label) \
6667 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6670 inst.operands[i].reg = val; \
6671 inst.operands[i].isscalar = 1; \
6675 #define po_misc_or_fail(expr) \
6683 #define po_misc_or_fail_no_backtrack(expr) \
6687 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6688 backtrack_pos = 0; \
6689 if (result != PARSE_OPERAND_SUCCESS) \
6694 #define po_barrier_or_imm(str) \
6697 val = parse_barrier (&str); \
6698 if (val == FAIL && ! ISALPHA (*str)) \
6701 /* ISB can only take SY as an option. */ \
6702 || ((inst.instruction & 0xf0) == 0x60 \
6705 inst.error = _("invalid barrier type"); \
6706 backtrack_pos = 0; \
6712 skip_whitespace (str
);
6714 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6716 op_parse_code
= upat
[i
];
6717 if (op_parse_code
>= 1<<16)
6718 op_parse_code
= thumb
? (op_parse_code
>> 16)
6719 : (op_parse_code
& ((1<<16)-1));
6721 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6723 /* Remember where we are in case we need to backtrack. */
6724 gas_assert (!backtrack_pos
);
6725 backtrack_pos
= str
;
6726 backtrack_error
= inst
.error
;
6727 backtrack_index
= i
;
6730 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6731 po_char_or_fail (',');
6733 switch (op_parse_code
)
6741 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6742 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6743 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6744 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6745 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6746 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6748 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6750 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6752 /* Also accept generic coprocessor regs for unknown registers. */
6754 po_reg_or_fail (REG_TYPE_CN
);
6756 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6757 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6758 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6759 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6760 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6761 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6762 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6763 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6764 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6765 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6767 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6769 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6770 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6772 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6774 /* Neon scalar. Using an element size of 8 means that some invalid
6775 scalars are accepted here, so deal with those in later code. */
6776 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6780 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6783 po_imm_or_fail (0, 0, TRUE
);
6788 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6793 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6796 if (parse_ifimm_zero (&str
))
6797 inst
.operands
[i
].imm
= 0;
6801 = _("only floating point zero is allowed as immediate value");
6809 po_scalar_or_goto (8, try_rr
);
6812 po_reg_or_fail (REG_TYPE_RN
);
6818 po_scalar_or_goto (8, try_nsdq
);
6821 po_reg_or_fail (REG_TYPE_NSDQ
);
6827 po_scalar_or_goto (8, try_ndq
);
6830 po_reg_or_fail (REG_TYPE_NDQ
);
6836 po_scalar_or_goto (8, try_vfd
);
6839 po_reg_or_fail (REG_TYPE_VFD
);
6844 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6845 not careful then bad things might happen. */
6846 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6851 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6854 /* There's a possibility of getting a 64-bit immediate here, so
6855 we need special handling. */
6856 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6859 inst
.error
= _("immediate value is out of range");
6867 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6870 po_imm_or_fail (0, 63, TRUE
);
6875 po_char_or_fail ('[');
6876 po_reg_or_fail (REG_TYPE_RN
);
6877 po_char_or_fail (']');
6883 po_reg_or_fail (REG_TYPE_RN
);
6884 if (skip_past_char (&str
, '!') == SUCCESS
)
6885 inst
.operands
[i
].writeback
= 1;
6889 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6890 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6891 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6892 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6893 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6894 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6895 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6896 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6897 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6898 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6899 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6900 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6902 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6904 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6905 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6907 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6908 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6909 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6910 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6912 /* Immediate variants */
6914 po_char_or_fail ('{');
6915 po_imm_or_fail (0, 255, TRUE
);
6916 po_char_or_fail ('}');
6920 /* The expression parser chokes on a trailing !, so we have
6921 to find it first and zap it. */
6924 while (*s
&& *s
!= ',')
6929 inst
.operands
[i
].writeback
= 1;
6931 po_imm_or_fail (0, 31, TRUE
);
6939 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6944 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6949 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6951 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6953 val
= parse_reloc (&str
);
6956 inst
.error
= _("unrecognized relocation suffix");
6959 else if (val
!= BFD_RELOC_UNUSED
)
6961 inst
.operands
[i
].imm
= val
;
6962 inst
.operands
[i
].hasreloc
= 1;
6967 /* Operand for MOVW or MOVT. */
6969 po_misc_or_fail (parse_half (&str
));
6972 /* Register or expression. */
6973 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6974 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6976 /* Register or immediate. */
6977 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6978 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6980 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6982 if (!is_immediate_prefix (*str
))
6985 val
= parse_fpa_immediate (&str
);
6988 /* FPA immediates are encoded as registers 8-15.
6989 parse_fpa_immediate has already applied the offset. */
6990 inst
.operands
[i
].reg
= val
;
6991 inst
.operands
[i
].isreg
= 1;
6994 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6995 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6997 /* Two kinds of register. */
7000 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7002 || (rege
->type
!= REG_TYPE_MMXWR
7003 && rege
->type
!= REG_TYPE_MMXWC
7004 && rege
->type
!= REG_TYPE_MMXWCG
))
7006 inst
.error
= _("iWMMXt data or control register expected");
7009 inst
.operands
[i
].reg
= rege
->number
;
7010 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7016 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7018 || (rege
->type
!= REG_TYPE_MMXWC
7019 && rege
->type
!= REG_TYPE_MMXWCG
))
7021 inst
.error
= _("iWMMXt control register expected");
7024 inst
.operands
[i
].reg
= rege
->number
;
7025 inst
.operands
[i
].isreg
= 1;
7030 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7031 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7032 case OP_oROR
: val
= parse_ror (&str
); break;
7033 case OP_COND
: val
= parse_cond (&str
); break;
7034 case OP_oBARRIER_I15
:
7035 po_barrier_or_imm (str
); break;
7037 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7043 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7044 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7046 inst
.error
= _("Banked registers are not available with this "
7052 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7056 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7059 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7061 if (strncasecmp (str
, "APSR_", 5) == 0)
7068 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7069 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7070 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7071 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7072 default: found
= 16;
7076 inst
.operands
[i
].isvec
= 1;
7077 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7078 inst
.operands
[i
].reg
= REG_PC
;
7085 po_misc_or_fail (parse_tb (&str
));
7088 /* Register lists. */
7090 val
= parse_reg_list (&str
);
7093 inst
.operands
[i
].writeback
= 1;
7099 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7103 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7107 /* Allow Q registers too. */
7108 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7113 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7115 inst
.operands
[i
].issingle
= 1;
7120 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7125 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7126 &inst
.operands
[i
].vectype
);
7129 /* Addressing modes */
7131 po_misc_or_fail (parse_address (&str
, i
));
7135 po_misc_or_fail_no_backtrack (
7136 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7140 po_misc_or_fail_no_backtrack (
7141 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7145 po_misc_or_fail_no_backtrack (
7146 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7150 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7154 po_misc_or_fail_no_backtrack (
7155 parse_shifter_operand_group_reloc (&str
, i
));
7159 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7163 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7167 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7171 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7174 /* Various value-based sanity checks and shared operations. We
7175 do not signal immediate failures for the register constraints;
7176 this allows a syntax error to take precedence. */
7177 switch (op_parse_code
)
7185 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7186 inst
.error
= BAD_PC
;
7191 if (inst
.operands
[i
].isreg
)
7193 if (inst
.operands
[i
].reg
== REG_PC
)
7194 inst
.error
= BAD_PC
;
7195 else if (inst
.operands
[i
].reg
== REG_SP
7196 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7197 relaxed since ARMv8-A. */
7198 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7201 inst
.error
= BAD_SP
;
7207 if (inst
.operands
[i
].isreg
7208 && inst
.operands
[i
].reg
== REG_PC
7209 && (inst
.operands
[i
].writeback
|| thumb
))
7210 inst
.error
= BAD_PC
;
7219 case OP_oBARRIER_I15
:
7228 inst
.operands
[i
].imm
= val
;
7235 /* If we get here, this operand was successfully parsed. */
7236 inst
.operands
[i
].present
= 1;
7240 inst
.error
= BAD_ARGS
;
7245 /* The parse routine should already have set inst.error, but set a
7246 default here just in case. */
7248 inst
.error
= _("syntax error");
7252 /* Do not backtrack over a trailing optional argument that
7253 absorbed some text. We will only fail again, with the
7254 'garbage following instruction' error message, which is
7255 probably less helpful than the current one. */
7256 if (backtrack_index
== i
&& backtrack_pos
!= str
7257 && upat
[i
+1] == OP_stop
)
7260 inst
.error
= _("syntax error");
7264 /* Try again, skipping the optional argument at backtrack_pos. */
7265 str
= backtrack_pos
;
7266 inst
.error
= backtrack_error
;
7267 inst
.operands
[backtrack_index
].present
= 0;
7268 i
= backtrack_index
;
7272 /* Check that we have parsed all the arguments. */
7273 if (*str
!= '\0' && !inst
.error
)
7274 inst
.error
= _("garbage following instruction");
7276 return inst
.error
? FAIL
: SUCCESS
;
7279 #undef po_char_or_fail
7280 #undef po_reg_or_fail
7281 #undef po_reg_or_goto
7282 #undef po_imm_or_fail
7283 #undef po_scalar_or_fail
7284 #undef po_barrier_or_imm
7286 /* Shorthand macro for instruction encoding functions issuing errors. */
7287 #define constraint(expr, err) \
7298 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7299 instructions are unpredictable if these registers are used. This
7300 is the BadReg predicate in ARM's Thumb-2 documentation.
7302 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7303 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7304 #define reject_bad_reg(reg) \
7306 if (reg == REG_PC) \
7308 inst.error = BAD_PC; \
7311 else if (reg == REG_SP \
7312 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7314 inst.error = BAD_SP; \
7319 /* If REG is R13 (the stack pointer), warn that its use is
7321 #define warn_deprecated_sp(reg) \
7323 if (warn_on_deprecated && reg == REG_SP) \
7324 as_tsktsk (_("use of r13 is deprecated")); \
7327 /* Functions for operand encoding. ARM, then Thumb. */
7329 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7331 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7333 The only binary encoding difference is the Coprocessor number. Coprocessor
7334 9 is used for half-precision calculations or conversions. The format of the
7335 instruction is the same as the equivalent Coprocessor 10 instruction that
7336 exists for Single-Precision operation. */
7339 do_scalar_fp16_v82_encode (void)
7341 if (inst
.cond
!= COND_ALWAYS
)
7342 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7343 " the behaviour is UNPREDICTABLE"));
7344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7347 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7348 mark_feature_used (&arm_ext_fp16
);
7351 /* If VAL can be encoded in the immediate field of an ARM instruction,
7352 return the encoded form. Otherwise, return FAIL. */
7355 encode_arm_immediate (unsigned int val
)
7362 for (i
= 2; i
< 32; i
+= 2)
7363 if ((a
= rotate_left (val
, i
)) <= 0xff)
7364 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7369 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7370 return the encoded form. Otherwise, return FAIL. */
7372 encode_thumb32_immediate (unsigned int val
)
7379 for (i
= 1; i
<= 24; i
++)
7382 if ((val
& ~(0xff << i
)) == 0)
7383 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7387 if (val
== ((a
<< 16) | a
))
7389 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7393 if (val
== ((a
<< 16) | a
))
7394 return 0x200 | (a
>> 8);
7398 /* Encode a VFP SP or DP register number into inst.instruction. */
7401 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7403 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7406 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7409 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7412 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7417 first_error (_("D register out of range for selected VFP version"));
7425 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7429 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7433 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7437 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7441 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7445 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7453 /* Encode a <shift> in an ARM-format instruction. The immediate,
7454 if any, is handled by md_apply_fix. */
7456 encode_arm_shift (int i
)
7458 /* register-shifted register. */
7459 if (inst
.operands
[i
].immisreg
)
7462 for (op_index
= 0; op_index
<= i
; ++op_index
)
7464 /* Check the operand only when it's presented. In pre-UAL syntax,
7465 if the destination register is the same as the first operand, two
7466 register form of the instruction can be used. */
7467 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7468 && inst
.operands
[op_index
].reg
== REG_PC
)
7469 as_warn (UNPRED_REG ("r15"));
7472 if (inst
.operands
[i
].imm
== REG_PC
)
7473 as_warn (UNPRED_REG ("r15"));
7476 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7477 inst
.instruction
|= SHIFT_ROR
<< 5;
7480 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7481 if (inst
.operands
[i
].immisreg
)
7483 inst
.instruction
|= SHIFT_BY_REG
;
7484 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7487 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7492 encode_arm_shifter_operand (int i
)
7494 if (inst
.operands
[i
].isreg
)
7496 inst
.instruction
|= inst
.operands
[i
].reg
;
7497 encode_arm_shift (i
);
7501 inst
.instruction
|= INST_IMMEDIATE
;
7502 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7503 inst
.instruction
|= inst
.operands
[i
].imm
;
7507 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7509 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7512 Generate an error if the operand is not a register. */
7513 constraint (!inst
.operands
[i
].isreg
,
7514 _("Instruction does not support =N addresses"));
7516 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7518 if (inst
.operands
[i
].preind
)
7522 inst
.error
= _("instruction does not accept preindexed addressing");
7525 inst
.instruction
|= PRE_INDEX
;
7526 if (inst
.operands
[i
].writeback
)
7527 inst
.instruction
|= WRITE_BACK
;
7530 else if (inst
.operands
[i
].postind
)
7532 gas_assert (inst
.operands
[i
].writeback
);
7534 inst
.instruction
|= WRITE_BACK
;
7536 else /* unindexed - only for coprocessor */
7538 inst
.error
= _("instruction does not accept unindexed addressing");
7542 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7543 && (((inst
.instruction
& 0x000f0000) >> 16)
7544 == ((inst
.instruction
& 0x0000f000) >> 12)))
7545 as_warn ((inst
.instruction
& LOAD_BIT
)
7546 ? _("destination register same as write-back base")
7547 : _("source register same as write-back base"));
7550 /* inst.operands[i] was set up by parse_address. Encode it into an
7551 ARM-format mode 2 load or store instruction. If is_t is true,
7552 reject forms that cannot be used with a T instruction (i.e. not
7555 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7557 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7559 encode_arm_addr_mode_common (i
, is_t
);
7561 if (inst
.operands
[i
].immisreg
)
7563 constraint ((inst
.operands
[i
].imm
== REG_PC
7564 || (is_pc
&& inst
.operands
[i
].writeback
)),
7566 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7567 inst
.instruction
|= inst
.operands
[i
].imm
;
7568 if (!inst
.operands
[i
].negative
)
7569 inst
.instruction
|= INDEX_UP
;
7570 if (inst
.operands
[i
].shifted
)
7572 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7573 inst
.instruction
|= SHIFT_ROR
<< 5;
7576 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7577 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7581 else /* immediate offset in inst.reloc */
7583 if (is_pc
&& !inst
.reloc
.pc_rel
)
7585 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7587 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7588 cannot use PC in addressing.
7589 PC cannot be used in writeback addressing, either. */
7590 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7593 /* Use of PC in str is deprecated for ARMv7. */
7594 if (warn_on_deprecated
7596 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7597 as_tsktsk (_("use of PC in this instruction is deprecated"));
7600 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7602 /* Prefer + for zero encoded value. */
7603 if (!inst
.operands
[i
].negative
)
7604 inst
.instruction
|= INDEX_UP
;
7605 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7610 /* inst.operands[i] was set up by parse_address. Encode it into an
7611 ARM-format mode 3 load or store instruction. Reject forms that
7612 cannot be used with such instructions. If is_t is true, reject
7613 forms that cannot be used with a T instruction (i.e. not
7616 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7618 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7620 inst
.error
= _("instruction does not accept scaled register index");
7624 encode_arm_addr_mode_common (i
, is_t
);
7626 if (inst
.operands
[i
].immisreg
)
7628 constraint ((inst
.operands
[i
].imm
== REG_PC
7629 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7631 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7633 inst
.instruction
|= inst
.operands
[i
].imm
;
7634 if (!inst
.operands
[i
].negative
)
7635 inst
.instruction
|= INDEX_UP
;
7637 else /* immediate offset in inst.reloc */
7639 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7640 && inst
.operands
[i
].writeback
),
7642 inst
.instruction
|= HWOFFSET_IMM
;
7643 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7645 /* Prefer + for zero encoded value. */
7646 if (!inst
.operands
[i
].negative
)
7647 inst
.instruction
|= INDEX_UP
;
7649 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7654 /* Write immediate bits [7:0] to the following locations:
7656 |28/24|23 19|18 16|15 4|3 0|
7657 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7659 This function is used by VMOV/VMVN/VORR/VBIC. */
7662 neon_write_immbits (unsigned immbits
)
7664 inst
.instruction
|= immbits
& 0xf;
7665 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7666 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7669 /* Invert low-order SIZE bits of XHI:XLO. */
7672 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7674 unsigned immlo
= xlo
? *xlo
: 0;
7675 unsigned immhi
= xhi
? *xhi
: 0;
7680 immlo
= (~immlo
) & 0xff;
7684 immlo
= (~immlo
) & 0xffff;
7688 immhi
= (~immhi
) & 0xffffffff;
7692 immlo
= (~immlo
) & 0xffffffff;
7706 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7710 neon_bits_same_in_bytes (unsigned imm
)
7712 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7713 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7714 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7715 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7718 /* For immediate of above form, return 0bABCD. */
7721 neon_squash_bits (unsigned imm
)
7723 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7724 | ((imm
& 0x01000000) >> 21);
7727 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7730 neon_qfloat_bits (unsigned imm
)
7732 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7735 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7736 the instruction. *OP is passed as the initial value of the op field, and
7737 may be set to a different value depending on the constant (i.e.
7738 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7739 MVN). If the immediate looks like a repeated pattern then also
7740 try smaller element sizes. */
7743 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7744 unsigned *immbits
, int *op
, int size
,
7745 enum neon_el_type type
)
7747 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7749 if (type
== NT_float
&& !float_p
)
7752 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7754 if (size
!= 32 || *op
== 1)
7756 *immbits
= neon_qfloat_bits (immlo
);
7762 if (neon_bits_same_in_bytes (immhi
)
7763 && neon_bits_same_in_bytes (immlo
))
7767 *immbits
= (neon_squash_bits (immhi
) << 4)
7768 | neon_squash_bits (immlo
);
7779 if (immlo
== (immlo
& 0x000000ff))
7784 else if (immlo
== (immlo
& 0x0000ff00))
7786 *immbits
= immlo
>> 8;
7789 else if (immlo
== (immlo
& 0x00ff0000))
7791 *immbits
= immlo
>> 16;
7794 else if (immlo
== (immlo
& 0xff000000))
7796 *immbits
= immlo
>> 24;
7799 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7801 *immbits
= (immlo
>> 8) & 0xff;
7804 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7806 *immbits
= (immlo
>> 16) & 0xff;
7810 if ((immlo
& 0xffff) != (immlo
>> 16))
7817 if (immlo
== (immlo
& 0x000000ff))
7822 else if (immlo
== (immlo
& 0x0000ff00))
7824 *immbits
= immlo
>> 8;
7828 if ((immlo
& 0xff) != (immlo
>> 8))
7833 if (immlo
== (immlo
& 0x000000ff))
7835 /* Don't allow MVN with 8-bit immediate. */
7845 #if defined BFD_HOST_64_BIT
7846 /* Returns TRUE if double precision value V may be cast
7847 to single precision without loss of accuracy. */
7850 is_double_a_single (bfd_int64_t v
)
7852 int exp
= (int)((v
>> 52) & 0x7FF);
7853 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7855 return (exp
== 0 || exp
== 0x7FF
7856 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7857 && (mantissa
& 0x1FFFFFFFl
) == 0;
7860 /* Returns a double precision value casted to single precision
7861 (ignoring the least significant bits in exponent and mantissa). */
7864 double_to_single (bfd_int64_t v
)
7866 int sign
= (int) ((v
>> 63) & 1l);
7867 int exp
= (int) ((v
>> 52) & 0x7FF);
7868 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7874 exp
= exp
- 1023 + 127;
7883 /* No denormalized numbers. */
7889 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7891 #endif /* BFD_HOST_64_BIT */
7900 static void do_vfp_nsyn_opcode (const char *);
7902 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7903 Determine whether it can be performed with a move instruction; if
7904 it can, convert inst.instruction to that move instruction and
7905 return TRUE; if it can't, convert inst.instruction to a literal-pool
7906 load and return FALSE. If this is not a valid thing to do in the
7907 current context, set inst.error and return TRUE.
7909 inst.operands[i] describes the destination register. */
7912 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7915 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7916 bfd_boolean arm_p
= (t
== CONST_ARM
);
7919 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7923 if ((inst
.instruction
& tbit
) == 0)
7925 inst
.error
= _("invalid pseudo operation");
7929 if (inst
.reloc
.exp
.X_op
!= O_constant
7930 && inst
.reloc
.exp
.X_op
!= O_symbol
7931 && inst
.reloc
.exp
.X_op
!= O_big
)
7933 inst
.error
= _("constant expression expected");
7937 if (inst
.reloc
.exp
.X_op
== O_constant
7938 || inst
.reloc
.exp
.X_op
== O_big
)
7940 #if defined BFD_HOST_64_BIT
7945 if (inst
.reloc
.exp
.X_op
== O_big
)
7947 LITTLENUM_TYPE w
[X_PRECISION
];
7950 if (inst
.reloc
.exp
.X_add_number
== -1)
7952 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7954 /* FIXME: Should we check words w[2..5] ? */
7959 #if defined BFD_HOST_64_BIT
7961 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7962 << LITTLENUM_NUMBER_OF_BITS
)
7963 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7964 << LITTLENUM_NUMBER_OF_BITS
)
7965 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7966 << LITTLENUM_NUMBER_OF_BITS
)
7967 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7969 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7970 | (l
[0] & LITTLENUM_MASK
);
7974 v
= inst
.reloc
.exp
.X_add_number
;
7976 if (!inst
.operands
[i
].issingle
)
7980 /* LDR should not use lead in a flag-setting instruction being
7981 chosen so we do not check whether movs can be used. */
7983 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7984 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7985 && inst
.operands
[i
].reg
!= 13
7986 && inst
.operands
[i
].reg
!= 15)
7988 /* Check if on thumb2 it can be done with a mov.w, mvn or
7989 movw instruction. */
7990 unsigned int newimm
;
7991 bfd_boolean isNegated
;
7993 newimm
= encode_thumb32_immediate (v
);
7994 if (newimm
!= (unsigned int) FAIL
)
7998 newimm
= encode_thumb32_immediate (~v
);
7999 if (newimm
!= (unsigned int) FAIL
)
8003 /* The number can be loaded with a mov.w or mvn
8005 if (newimm
!= (unsigned int) FAIL
8006 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8008 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8009 | (inst
.operands
[i
].reg
<< 8));
8010 /* Change to MOVN. */
8011 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8012 inst
.instruction
|= (newimm
& 0x800) << 15;
8013 inst
.instruction
|= (newimm
& 0x700) << 4;
8014 inst
.instruction
|= (newimm
& 0x0ff);
8017 /* The number can be loaded with a movw instruction. */
8018 else if ((v
& ~0xFFFF) == 0
8019 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8021 int imm
= v
& 0xFFFF;
8023 inst
.instruction
= 0xf2400000; /* MOVW. */
8024 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8025 inst
.instruction
|= (imm
& 0xf000) << 4;
8026 inst
.instruction
|= (imm
& 0x0800) << 15;
8027 inst
.instruction
|= (imm
& 0x0700) << 4;
8028 inst
.instruction
|= (imm
& 0x00ff);
8035 int value
= encode_arm_immediate (v
);
8039 /* This can be done with a mov instruction. */
8040 inst
.instruction
&= LITERAL_MASK
;
8041 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8042 inst
.instruction
|= value
& 0xfff;
8046 value
= encode_arm_immediate (~ v
);
8049 /* This can be done with a mvn instruction. */
8050 inst
.instruction
&= LITERAL_MASK
;
8051 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8052 inst
.instruction
|= value
& 0xfff;
8056 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8059 unsigned immbits
= 0;
8060 unsigned immlo
= inst
.operands
[1].imm
;
8061 unsigned immhi
= inst
.operands
[1].regisimm
8062 ? inst
.operands
[1].reg
8063 : inst
.reloc
.exp
.X_unsigned
8065 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8066 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8067 &op
, 64, NT_invtype
);
8071 neon_invert_size (&immlo
, &immhi
, 64);
8073 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8074 &op
, 64, NT_invtype
);
8079 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8085 /* Fill other bits in vmov encoding for both thumb and arm. */
8087 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8089 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8090 neon_write_immbits (immbits
);
8098 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8099 if (inst
.operands
[i
].issingle
8100 && is_quarter_float (inst
.operands
[1].imm
)
8101 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8103 inst
.operands
[1].imm
=
8104 neon_qfloat_bits (v
);
8105 do_vfp_nsyn_opcode ("fconsts");
8109 /* If our host does not support a 64-bit type then we cannot perform
8110 the following optimization. This mean that there will be a
8111 discrepancy between the output produced by an assembler built for
8112 a 32-bit-only host and the output produced from a 64-bit host, but
8113 this cannot be helped. */
8114 #if defined BFD_HOST_64_BIT
8115 else if (!inst
.operands
[1].issingle
8116 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8118 if (is_double_a_single (v
)
8119 && is_quarter_float (double_to_single (v
)))
8121 inst
.operands
[1].imm
=
8122 neon_qfloat_bits (double_to_single (v
));
8123 do_vfp_nsyn_opcode ("fconstd");
8131 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8132 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8135 inst
.operands
[1].reg
= REG_PC
;
8136 inst
.operands
[1].isreg
= 1;
8137 inst
.operands
[1].preind
= 1;
8138 inst
.reloc
.pc_rel
= 1;
8139 inst
.reloc
.type
= (thumb_p
8140 ? BFD_RELOC_ARM_THUMB_OFFSET
8142 ? BFD_RELOC_ARM_HWLITERAL
8143 : BFD_RELOC_ARM_LITERAL
));
8147 /* inst.operands[i] was set up by parse_address. Encode it into an
8148 ARM-format instruction. Reject all forms which cannot be encoded
8149 into a coprocessor load/store instruction. If wb_ok is false,
8150 reject use of writeback; if unind_ok is false, reject use of
8151 unindexed addressing. If reloc_override is not 0, use it instead
8152 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8153 (in which case it is preserved). */
8156 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8158 if (!inst
.operands
[i
].isreg
)
8161 if (! inst
.operands
[0].isvec
)
8163 inst
.error
= _("invalid co-processor operand");
8166 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8170 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8172 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8174 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8176 gas_assert (!inst
.operands
[i
].writeback
);
8179 inst
.error
= _("instruction does not support unindexed addressing");
8182 inst
.instruction
|= inst
.operands
[i
].imm
;
8183 inst
.instruction
|= INDEX_UP
;
8187 if (inst
.operands
[i
].preind
)
8188 inst
.instruction
|= PRE_INDEX
;
8190 if (inst
.operands
[i
].writeback
)
8192 if (inst
.operands
[i
].reg
== REG_PC
)
8194 inst
.error
= _("pc may not be used with write-back");
8199 inst
.error
= _("instruction does not support writeback");
8202 inst
.instruction
|= WRITE_BACK
;
8206 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8207 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8208 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8209 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8212 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8214 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8217 /* Prefer + for zero encoded value. */
8218 if (!inst
.operands
[i
].negative
)
8219 inst
.instruction
|= INDEX_UP
;
8224 /* Functions for instruction encoding, sorted by sub-architecture.
8225 First some generics; their names are taken from the conventional
8226 bit positions for register arguments in ARM format instructions. */
8236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8242 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[1].reg
;
8255 inst
.instruction
|= inst
.operands
[0].reg
;
8256 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8263 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8269 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8270 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8277 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8281 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8283 if (ARM_CPU_IS_ANY (cpu_variant
))
8285 as_tsktsk ("%s", msg
);
8288 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8300 unsigned Rn
= inst
.operands
[2].reg
;
8301 /* Enforce restrictions on SWP instruction. */
8302 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8304 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8305 _("Rn must not overlap other operands"));
8307 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8309 if (!check_obsolete (&arm_ext_v8
,
8310 _("swp{b} use is obsoleted for ARMv8 and later"))
8311 && warn_on_deprecated
8312 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8313 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8317 inst
.instruction
|= inst
.operands
[1].reg
;
8318 inst
.instruction
|= Rn
<< 16;
8324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8326 inst
.instruction
|= inst
.operands
[2].reg
;
8332 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8333 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8334 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8335 || inst
.reloc
.exp
.X_add_number
!= 0),
8337 inst
.instruction
|= inst
.operands
[0].reg
;
8338 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8339 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8345 inst
.instruction
|= inst
.operands
[0].imm
;
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8352 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8355 /* ARM instructions, in alphabetical order by function name (except
8356 that wrapper functions appear immediately after the function they
8359 /* This is a pseudo-op of the form "adr rd, label" to be converted
8360 into a relative address of the form "add rd, pc, #label-.-8". */
8365 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8367 /* Frag hacking will turn this into a sub instruction if the offset turns
8368 out to be negative. */
8369 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8370 inst
.reloc
.pc_rel
= 1;
8371 inst
.reloc
.exp
.X_add_number
-= 8;
8373 if (inst
.reloc
.exp
.X_op
== O_symbol
8374 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8375 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8376 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8377 inst
.reloc
.exp
.X_add_number
+= 1;
8380 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8381 into a relative address of the form:
8382 add rd, pc, #low(label-.-8)"
8383 add rd, rd, #high(label-.-8)" */
8388 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8390 /* Frag hacking will turn this into a sub instruction if the offset turns
8391 out to be negative. */
8392 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8393 inst
.reloc
.pc_rel
= 1;
8394 inst
.size
= INSN_SIZE
* 2;
8395 inst
.reloc
.exp
.X_add_number
-= 8;
8397 if (inst
.reloc
.exp
.X_op
== O_symbol
8398 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8399 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8400 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8401 inst
.reloc
.exp
.X_add_number
+= 1;
8407 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8408 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8410 if (!inst
.operands
[1].present
)
8411 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8413 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8414 encode_arm_shifter_operand (2);
8420 if (inst
.operands
[0].present
)
8421 inst
.instruction
|= inst
.operands
[0].imm
;
8423 inst
.instruction
|= 0xf;
8429 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8430 constraint (msb
> 32, _("bit-field extends past end of register"));
8431 /* The instruction encoding stores the LSB and MSB,
8432 not the LSB and width. */
8433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8434 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8435 inst
.instruction
|= (msb
- 1) << 16;
8443 /* #0 in second position is alternative syntax for bfc, which is
8444 the same instruction but with REG_PC in the Rm field. */
8445 if (!inst
.operands
[1].isreg
)
8446 inst
.operands
[1].reg
= REG_PC
;
8448 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8449 constraint (msb
> 32, _("bit-field extends past end of register"));
8450 /* The instruction encoding stores the LSB and MSB,
8451 not the LSB and width. */
8452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8453 inst
.instruction
|= inst
.operands
[1].reg
;
8454 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8455 inst
.instruction
|= (msb
- 1) << 16;
8461 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8462 _("bit-field extends past end of register"));
8463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8464 inst
.instruction
|= inst
.operands
[1].reg
;
8465 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8466 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8469 /* ARM V5 breakpoint instruction (argument parse)
8470 BKPT <16 bit unsigned immediate>
8471 Instruction is not conditional.
8472 The bit pattern given in insns[] has the COND_ALWAYS condition,
8473 and it is an error if the caller tried to override that. */
8478 /* Top 12 of 16 bits to bits 19:8. */
8479 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8481 /* Bottom 4 of 16 bits to bits 3:0. */
8482 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8486 encode_branch (int default_reloc
)
8488 if (inst
.operands
[0].hasreloc
)
8490 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8491 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8492 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8493 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8494 ? BFD_RELOC_ARM_PLT32
8495 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8498 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8499 inst
.reloc
.pc_rel
= 1;
8506 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8507 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8510 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8517 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8519 if (inst
.cond
== COND_ALWAYS
)
8520 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8522 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8526 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8529 /* ARM V5 branch-link-exchange instruction (argument parse)
8530 BLX <target_addr> ie BLX(1)
8531 BLX{<condition>} <Rm> ie BLX(2)
8532 Unfortunately, there are two different opcodes for this mnemonic.
8533 So, the insns[].value is not used, and the code here zaps values
8534 into inst.instruction.
8535 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8540 if (inst
.operands
[0].isreg
)
8542 /* Arg is a register; the opcode provided by insns[] is correct.
8543 It is not illegal to do "blx pc", just useless. */
8544 if (inst
.operands
[0].reg
== REG_PC
)
8545 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8547 inst
.instruction
|= inst
.operands
[0].reg
;
8551 /* Arg is an address; this instruction cannot be executed
8552 conditionally, and the opcode must be adjusted.
8553 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8554 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8555 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8556 inst
.instruction
= 0xfa000000;
8557 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8564 bfd_boolean want_reloc
;
8566 if (inst
.operands
[0].reg
== REG_PC
)
8567 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8569 inst
.instruction
|= inst
.operands
[0].reg
;
8570 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8571 it is for ARMv4t or earlier. */
8572 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8573 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8577 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8582 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8586 /* ARM v5TEJ. Jump to Jazelle code. */
8591 if (inst
.operands
[0].reg
== REG_PC
)
8592 as_tsktsk (_("use of r15 in bxj is not really useful"));
8594 inst
.instruction
|= inst
.operands
[0].reg
;
8597 /* Co-processor data operation:
8598 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8599 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8603 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8604 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8605 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8606 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8607 inst
.instruction
|= inst
.operands
[4].reg
;
8608 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8614 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8615 encode_arm_shifter_operand (1);
8618 /* Transfer between coprocessor and ARM registers.
8619 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8624 No special properties. */
8626 struct deprecated_coproc_regs_s
8633 arm_feature_set deprecated
;
8634 arm_feature_set obsoleted
;
8635 const char *dep_msg
;
8636 const char *obs_msg
;
8639 #define DEPR_ACCESS_V8 \
8640 N_("This coprocessor register access is deprecated in ARMv8")
8642 /* Table of all deprecated coprocessor registers. */
8643 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8645 {15, 0, 7, 10, 5, /* CP15DMB. */
8646 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8647 DEPR_ACCESS_V8
, NULL
},
8648 {15, 0, 7, 10, 4, /* CP15DSB. */
8649 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8650 DEPR_ACCESS_V8
, NULL
},
8651 {15, 0, 7, 5, 4, /* CP15ISB. */
8652 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8653 DEPR_ACCESS_V8
, NULL
},
8654 {14, 6, 1, 0, 0, /* TEEHBR. */
8655 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8656 DEPR_ACCESS_V8
, NULL
},
8657 {14, 6, 0, 0, 0, /* TEECR. */
8658 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8659 DEPR_ACCESS_V8
, NULL
},
8662 #undef DEPR_ACCESS_V8
8664 static const size_t deprecated_coproc_reg_count
=
8665 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8673 Rd
= inst
.operands
[2].reg
;
8676 if (inst
.instruction
== 0xee000010
8677 || inst
.instruction
== 0xfe000010)
8679 reject_bad_reg (Rd
);
8680 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8682 constraint (Rd
== REG_SP
, BAD_SP
);
8687 if (inst
.instruction
== 0xe000010)
8688 constraint (Rd
== REG_PC
, BAD_PC
);
8691 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8693 const struct deprecated_coproc_regs_s
*r
=
8694 deprecated_coproc_regs
+ i
;
8696 if (inst
.operands
[0].reg
== r
->cp
8697 && inst
.operands
[1].imm
== r
->opc1
8698 && inst
.operands
[3].reg
== r
->crn
8699 && inst
.operands
[4].reg
== r
->crm
8700 && inst
.operands
[5].imm
== r
->opc2
)
8702 if (! ARM_CPU_IS_ANY (cpu_variant
)
8703 && warn_on_deprecated
8704 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8705 as_tsktsk ("%s", r
->dep_msg
);
8709 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8710 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8711 inst
.instruction
|= Rd
<< 12;
8712 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8713 inst
.instruction
|= inst
.operands
[4].reg
;
8714 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8717 /* Transfer between coprocessor register and pair of ARM registers.
8718 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8723 Two XScale instructions are special cases of these:
8725 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8726 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8728 Result unpredictable if Rd or Rn is R15. */
8735 Rd
= inst
.operands
[2].reg
;
8736 Rn
= inst
.operands
[3].reg
;
8740 reject_bad_reg (Rd
);
8741 reject_bad_reg (Rn
);
8745 constraint (Rd
== REG_PC
, BAD_PC
);
8746 constraint (Rn
== REG_PC
, BAD_PC
);
8749 /* Only check the MRRC{2} variants. */
8750 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8752 /* If Rd == Rn, error that the operation is
8753 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8754 constraint (Rd
== Rn
, BAD_OVERLAP
);
8757 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8758 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8759 inst
.instruction
|= Rd
<< 12;
8760 inst
.instruction
|= Rn
<< 16;
8761 inst
.instruction
|= inst
.operands
[4].reg
;
8767 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8768 if (inst
.operands
[1].present
)
8770 inst
.instruction
|= CPSI_MMOD
;
8771 inst
.instruction
|= inst
.operands
[1].imm
;
8778 inst
.instruction
|= inst
.operands
[0].imm
;
8784 unsigned Rd
, Rn
, Rm
;
8786 Rd
= inst
.operands
[0].reg
;
8787 Rn
= (inst
.operands
[1].present
8788 ? inst
.operands
[1].reg
: Rd
);
8789 Rm
= inst
.operands
[2].reg
;
8791 constraint ((Rd
== REG_PC
), BAD_PC
);
8792 constraint ((Rn
== REG_PC
), BAD_PC
);
8793 constraint ((Rm
== REG_PC
), BAD_PC
);
8795 inst
.instruction
|= Rd
<< 16;
8796 inst
.instruction
|= Rn
<< 0;
8797 inst
.instruction
|= Rm
<< 8;
8803 /* There is no IT instruction in ARM mode. We
8804 process it to do the validation as if in
8805 thumb mode, just in case the code gets
8806 assembled for thumb using the unified syntax. */
8811 set_it_insn_type (IT_INSN
);
8812 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8813 now_it
.cc
= inst
.operands
[0].imm
;
8817 /* If there is only one register in the register list,
8818 then return its register number. Otherwise return -1. */
8820 only_one_reg_in_list (int range
)
8822 int i
= ffs (range
) - 1;
8823 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8827 encode_ldmstm(int from_push_pop_mnem
)
8829 int base_reg
= inst
.operands
[0].reg
;
8830 int range
= inst
.operands
[1].imm
;
8833 inst
.instruction
|= base_reg
<< 16;
8834 inst
.instruction
|= range
;
8836 if (inst
.operands
[1].writeback
)
8837 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8839 if (inst
.operands
[0].writeback
)
8841 inst
.instruction
|= WRITE_BACK
;
8842 /* Check for unpredictable uses of writeback. */
8843 if (inst
.instruction
& LOAD_BIT
)
8845 /* Not allowed in LDM type 2. */
8846 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8847 && ((range
& (1 << REG_PC
)) == 0))
8848 as_warn (_("writeback of base register is UNPREDICTABLE"));
8849 /* Only allowed if base reg not in list for other types. */
8850 else if (range
& (1 << base_reg
))
8851 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8855 /* Not allowed for type 2. */
8856 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8857 as_warn (_("writeback of base register is UNPREDICTABLE"));
8858 /* Only allowed if base reg not in list, or first in list. */
8859 else if ((range
& (1 << base_reg
))
8860 && (range
& ((1 << base_reg
) - 1)))
8861 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8865 /* If PUSH/POP has only one register, then use the A2 encoding. */
8866 one_reg
= only_one_reg_in_list (range
);
8867 if (from_push_pop_mnem
&& one_reg
>= 0)
8869 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8871 inst
.instruction
&= A_COND_MASK
;
8872 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8873 inst
.instruction
|= one_reg
<< 12;
8880 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8883 /* ARMv5TE load-consecutive (argument parse)
8892 constraint (inst
.operands
[0].reg
% 2 != 0,
8893 _("first transfer register must be even"));
8894 constraint (inst
.operands
[1].present
8895 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8896 _("can only transfer two consecutive registers"));
8897 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8898 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8900 if (!inst
.operands
[1].present
)
8901 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8903 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8904 register and the first register written; we have to diagnose
8905 overlap between the base and the second register written here. */
8907 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8908 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8909 as_warn (_("base register written back, and overlaps "
8910 "second transfer register"));
8912 if (!(inst
.instruction
& V4_STR_BIT
))
8914 /* For an index-register load, the index register must not overlap the
8915 destination (even if not write-back). */
8916 if (inst
.operands
[2].immisreg
8917 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8918 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8919 as_warn (_("index register overlaps transfer register"));
8921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8922 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8928 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8929 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8930 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8931 || inst
.operands
[1].negative
8932 /* This can arise if the programmer has written
8934 or if they have mistakenly used a register name as the last
8937 It is very difficult to distinguish between these two cases
8938 because "rX" might actually be a label. ie the register
8939 name has been occluded by a symbol of the same name. So we
8940 just generate a general 'bad addressing mode' type error
8941 message and leave it up to the programmer to discover the
8942 true cause and fix their mistake. */
8943 || (inst
.operands
[1].reg
== REG_PC
),
8946 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8947 || inst
.reloc
.exp
.X_add_number
!= 0,
8948 _("offset must be zero in ARM encoding"));
8950 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8954 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8960 constraint (inst
.operands
[0].reg
% 2 != 0,
8961 _("even register required"));
8962 constraint (inst
.operands
[1].present
8963 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8964 _("can only load two consecutive registers"));
8965 /* If op 1 were present and equal to PC, this function wouldn't
8966 have been called in the first place. */
8967 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8970 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8973 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8974 which is not a multiple of four is UNPREDICTABLE. */
8976 check_ldr_r15_aligned (void)
8978 constraint (!(inst
.operands
[1].immisreg
)
8979 && (inst
.operands
[0].reg
== REG_PC
8980 && inst
.operands
[1].reg
== REG_PC
8981 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8982 _("ldr to register 15 must be 4-byte alligned"));
8988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8989 if (!inst
.operands
[1].isreg
)
8990 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8992 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8993 check_ldr_r15_aligned ();
8999 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9001 if (inst
.operands
[1].preind
)
9003 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9004 || inst
.reloc
.exp
.X_add_number
!= 0,
9005 _("this instruction requires a post-indexed address"));
9007 inst
.operands
[1].preind
= 0;
9008 inst
.operands
[1].postind
= 1;
9009 inst
.operands
[1].writeback
= 1;
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9012 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9015 /* Halfword and signed-byte load/store operations. */
9020 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 if (!inst
.operands
[1].isreg
)
9023 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9025 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9031 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9033 if (inst
.operands
[1].preind
)
9035 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9036 || inst
.reloc
.exp
.X_add_number
!= 0,
9037 _("this instruction requires a post-indexed address"));
9039 inst
.operands
[1].preind
= 0;
9040 inst
.operands
[1].postind
= 1;
9041 inst
.operands
[1].writeback
= 1;
9043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9044 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9047 /* Co-processor register load/store.
9048 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9052 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9053 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9054 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9060 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9061 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9062 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9063 && !(inst
.instruction
& 0x00400000))
9064 as_tsktsk (_("Rd and Rm should be different in mla"));
9066 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9067 inst
.instruction
|= inst
.operands
[1].reg
;
9068 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9069 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9075 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9076 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 encode_arm_shifter_operand (1);
9082 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9089 top
= (inst
.instruction
& 0x00400000) != 0;
9090 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9091 _(":lower16: not allowed in this instruction"));
9092 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9093 _(":upper16: not allowed in this instruction"));
9094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9095 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9097 imm
= inst
.reloc
.exp
.X_add_number
;
9098 /* The value is in two pieces: 0:11, 16:19. */
9099 inst
.instruction
|= (imm
& 0x00000fff);
9100 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9105 do_vfp_nsyn_mrs (void)
9107 if (inst
.operands
[0].isvec
)
9109 if (inst
.operands
[1].reg
!= 1)
9110 first_error (_("operand 1 must be FPSCR"));
9111 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9112 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9113 do_vfp_nsyn_opcode ("fmstat");
9115 else if (inst
.operands
[1].isvec
)
9116 do_vfp_nsyn_opcode ("fmrx");
9124 do_vfp_nsyn_msr (void)
9126 if (inst
.operands
[0].isvec
)
9127 do_vfp_nsyn_opcode ("fmxr");
9137 unsigned Rt
= inst
.operands
[0].reg
;
9139 if (thumb_mode
&& Rt
== REG_SP
)
9141 inst
.error
= BAD_SP
;
9145 /* APSR_ sets isvec. All other refs to PC are illegal. */
9146 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9148 inst
.error
= BAD_PC
;
9152 /* If we get through parsing the register name, we just insert the number
9153 generated into the instruction without further validation. */
9154 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9155 inst
.instruction
|= (Rt
<< 12);
9161 unsigned Rt
= inst
.operands
[1].reg
;
9164 reject_bad_reg (Rt
);
9165 else if (Rt
== REG_PC
)
9167 inst
.error
= BAD_PC
;
9171 /* If we get through parsing the register name, we just insert the number
9172 generated into the instruction without further validation. */
9173 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9174 inst
.instruction
|= (Rt
<< 12);
9182 if (do_vfp_nsyn_mrs () == SUCCESS
)
9185 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9188 if (inst
.operands
[1].isreg
)
9190 br
= inst
.operands
[1].reg
;
9191 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9192 as_bad (_("bad register for mrs"));
9196 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9197 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9199 _("'APSR', 'CPSR' or 'SPSR' expected"));
9200 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9203 inst
.instruction
|= br
;
9206 /* Two possible forms:
9207 "{C|S}PSR_<field>, Rm",
9208 "{C|S}PSR_f, #expression". */
9213 if (do_vfp_nsyn_msr () == SUCCESS
)
9216 inst
.instruction
|= inst
.operands
[0].imm
;
9217 if (inst
.operands
[1].isreg
)
9218 inst
.instruction
|= inst
.operands
[1].reg
;
9221 inst
.instruction
|= INST_IMMEDIATE
;
9222 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9223 inst
.reloc
.pc_rel
= 0;
9230 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9232 if (!inst
.operands
[2].present
)
9233 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9235 inst
.instruction
|= inst
.operands
[1].reg
;
9236 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9238 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9239 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9240 as_tsktsk (_("Rd and Rm should be different in mul"));
9243 /* Long Multiply Parser
9244 UMULL RdLo, RdHi, Rm, Rs
9245 SMULL RdLo, RdHi, Rm, Rs
9246 UMLAL RdLo, RdHi, Rm, Rs
9247 SMLAL RdLo, RdHi, Rm, Rs. */
9252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9254 inst
.instruction
|= inst
.operands
[2].reg
;
9255 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9257 /* rdhi and rdlo must be different. */
9258 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9259 as_tsktsk (_("rdhi and rdlo must be different"));
9261 /* rdhi, rdlo and rm must all be different before armv6. */
9262 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9263 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9264 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9265 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9271 if (inst
.operands
[0].present
9272 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9274 /* Architectural NOP hints are CPSR sets with no bits selected. */
9275 inst
.instruction
&= 0xf0000000;
9276 inst
.instruction
|= 0x0320f000;
9277 if (inst
.operands
[0].present
)
9278 inst
.instruction
|= inst
.operands
[0].imm
;
9282 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9283 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9284 Condition defaults to COND_ALWAYS.
9285 Error if Rd, Rn or Rm are R15. */
9290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9292 inst
.instruction
|= inst
.operands
[2].reg
;
9293 if (inst
.operands
[3].present
)
9294 encode_arm_shift (3);
9297 /* ARM V6 PKHTB (Argument Parse). */
9302 if (!inst
.operands
[3].present
)
9304 /* If the shift specifier is omitted, turn the instruction
9305 into pkhbt rd, rm, rn. */
9306 inst
.instruction
&= 0xfff00010;
9307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9308 inst
.instruction
|= inst
.operands
[1].reg
;
9309 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9314 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9315 inst
.instruction
|= inst
.operands
[2].reg
;
9316 encode_arm_shift (3);
9320 /* ARMv5TE: Preload-Cache
9321 MP Extensions: Preload for write
9325 Syntactically, like LDR with B=1, W=0, L=1. */
9330 constraint (!inst
.operands
[0].isreg
,
9331 _("'[' expected after PLD mnemonic"));
9332 constraint (inst
.operands
[0].postind
,
9333 _("post-indexed expression used in preload instruction"));
9334 constraint (inst
.operands
[0].writeback
,
9335 _("writeback used in preload instruction"));
9336 constraint (!inst
.operands
[0].preind
,
9337 _("unindexed addressing used in preload instruction"));
9338 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9341 /* ARMv7: PLI <addr_mode> */
9345 constraint (!inst
.operands
[0].isreg
,
9346 _("'[' expected after PLI mnemonic"));
9347 constraint (inst
.operands
[0].postind
,
9348 _("post-indexed expression used in preload instruction"));
9349 constraint (inst
.operands
[0].writeback
,
9350 _("writeback used in preload instruction"));
9351 constraint (!inst
.operands
[0].preind
,
9352 _("unindexed addressing used in preload instruction"));
9353 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9354 inst
.instruction
&= ~PRE_INDEX
;
9360 constraint (inst
.operands
[0].writeback
,
9361 _("push/pop do not support {reglist}^"));
9362 inst
.operands
[1] = inst
.operands
[0];
9363 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9364 inst
.operands
[0].isreg
= 1;
9365 inst
.operands
[0].writeback
= 1;
9366 inst
.operands
[0].reg
= REG_SP
;
9367 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9370 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9371 word at the specified address and the following word
9373 Unconditionally executed.
9374 Error if Rn is R15. */
9379 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9380 if (inst
.operands
[0].writeback
)
9381 inst
.instruction
|= WRITE_BACK
;
9384 /* ARM V6 ssat (argument parse). */
9389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9390 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9391 inst
.instruction
|= inst
.operands
[2].reg
;
9393 if (inst
.operands
[3].present
)
9394 encode_arm_shift (3);
9397 /* ARM V6 usat (argument parse). */
9402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9403 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9404 inst
.instruction
|= inst
.operands
[2].reg
;
9406 if (inst
.operands
[3].present
)
9407 encode_arm_shift (3);
9410 /* ARM V6 ssat16 (argument parse). */
9415 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9416 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9417 inst
.instruction
|= inst
.operands
[2].reg
;
9423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9424 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9425 inst
.instruction
|= inst
.operands
[2].reg
;
9428 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9429 preserving the other bits.
9431 setend <endian_specifier>, where <endian_specifier> is either
9437 if (warn_on_deprecated
9438 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9439 as_tsktsk (_("setend use is deprecated for ARMv8"));
9441 if (inst
.operands
[0].imm
)
9442 inst
.instruction
|= 0x200;
9448 unsigned int Rm
= (inst
.operands
[1].present
9449 ? inst
.operands
[1].reg
9450 : inst
.operands
[0].reg
);
9452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9453 inst
.instruction
|= Rm
;
9454 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9456 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9457 inst
.instruction
|= SHIFT_BY_REG
;
9458 /* PR 12854: Error on extraneous shifts. */
9459 constraint (inst
.operands
[2].shifted
,
9460 _("extraneous shift as part of operand to shift insn"));
9463 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9469 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9470 inst
.reloc
.pc_rel
= 0;
9476 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9477 inst
.reloc
.pc_rel
= 0;
9483 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9484 inst
.reloc
.pc_rel
= 0;
9490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9491 _("selected processor does not support SETPAN instruction"));
9493 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9500 _("selected processor does not support SETPAN instruction"));
9502 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9505 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9506 SMLAxy{cond} Rd,Rm,Rs,Rn
9507 SMLAWy{cond} Rd,Rm,Rs,Rn
9508 Error if any register is R15. */
9513 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9514 inst
.instruction
|= inst
.operands
[1].reg
;
9515 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9516 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9519 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9520 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9521 Error if any register is R15.
9522 Warning if Rdlo == Rdhi. */
9527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9528 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9529 inst
.instruction
|= inst
.operands
[2].reg
;
9530 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9532 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9533 as_tsktsk (_("rdhi and rdlo must be different"));
9536 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9537 SMULxy{cond} Rd,Rm,Rs
9538 Error if any register is R15. */
9543 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9544 inst
.instruction
|= inst
.operands
[1].reg
;
9545 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9548 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9549 the same for both ARM and Thumb-2. */
9556 if (inst
.operands
[0].present
)
9558 reg
= inst
.operands
[0].reg
;
9559 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9564 inst
.instruction
|= reg
<< 16;
9565 inst
.instruction
|= inst
.operands
[1].imm
;
9566 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9567 inst
.instruction
|= WRITE_BACK
;
9570 /* ARM V6 strex (argument parse). */
9575 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9576 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9577 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9578 || inst
.operands
[2].negative
9579 /* See comment in do_ldrex(). */
9580 || (inst
.operands
[2].reg
== REG_PC
),
9583 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9584 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9587 || inst
.reloc
.exp
.X_add_number
!= 0,
9588 _("offset must be zero in ARM encoding"));
9590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9591 inst
.instruction
|= inst
.operands
[1].reg
;
9592 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9593 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9599 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9600 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9601 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9602 || inst
.operands
[2].negative
,
9605 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9606 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9614 constraint (inst
.operands
[1].reg
% 2 != 0,
9615 _("even register required"));
9616 constraint (inst
.operands
[2].present
9617 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9618 _("can only store two consecutive registers"));
9619 /* If op 2 were present and equal to PC, this function wouldn't
9620 have been called in the first place. */
9621 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9623 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9624 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9625 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9629 inst
.instruction
|= inst
.operands
[1].reg
;
9630 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9637 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9638 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9646 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9647 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9652 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9653 extends it to 32-bits, and adds the result to a value in another
9654 register. You can specify a rotation by 0, 8, 16, or 24 bits
9655 before extracting the 16-bit value.
9656 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9657 Condition defaults to COND_ALWAYS.
9658 Error if any register uses R15. */
9663 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9664 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9665 inst
.instruction
|= inst
.operands
[2].reg
;
9666 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9671 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9672 Condition defaults to COND_ALWAYS.
9673 Error if any register uses R15. */
9678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9679 inst
.instruction
|= inst
.operands
[1].reg
;
9680 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9683 /* VFP instructions. In a logical order: SP variant first, monad
9684 before dyad, arithmetic then move then load/store. */
9687 do_vfp_sp_monadic (void)
9689 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9690 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9694 do_vfp_sp_dyadic (void)
9696 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9697 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9698 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9702 do_vfp_sp_compare_z (void)
9704 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9708 do_vfp_dp_sp_cvt (void)
9710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9711 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9715 do_vfp_sp_dp_cvt (void)
9717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9718 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9722 do_vfp_reg_from_sp (void)
9724 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9725 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9729 do_vfp_reg2_from_sp2 (void)
9731 constraint (inst
.operands
[2].imm
!= 2,
9732 _("only two consecutive VFP SP registers allowed here"));
9733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9734 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9735 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9739 do_vfp_sp_from_reg (void)
9741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9742 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9746 do_vfp_sp2_from_reg2 (void)
9748 constraint (inst
.operands
[0].imm
!= 2,
9749 _("only two consecutive VFP SP registers allowed here"));
9750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9751 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9752 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9756 do_vfp_sp_ldst (void)
9758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9759 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9763 do_vfp_dp_ldst (void)
9765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9766 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9771 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9773 if (inst
.operands
[0].writeback
)
9774 inst
.instruction
|= WRITE_BACK
;
9776 constraint (ldstm_type
!= VFP_LDSTMIA
,
9777 _("this addressing mode requires base-register writeback"));
9778 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9779 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9780 inst
.instruction
|= inst
.operands
[1].imm
;
9784 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9788 if (inst
.operands
[0].writeback
)
9789 inst
.instruction
|= WRITE_BACK
;
9791 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9792 _("this addressing mode requires base-register writeback"));
9794 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9795 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9797 count
= inst
.operands
[1].imm
<< 1;
9798 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9801 inst
.instruction
|= count
;
9805 do_vfp_sp_ldstmia (void)
9807 vfp_sp_ldstm (VFP_LDSTMIA
);
9811 do_vfp_sp_ldstmdb (void)
9813 vfp_sp_ldstm (VFP_LDSTMDB
);
9817 do_vfp_dp_ldstmia (void)
9819 vfp_dp_ldstm (VFP_LDSTMIA
);
9823 do_vfp_dp_ldstmdb (void)
9825 vfp_dp_ldstm (VFP_LDSTMDB
);
9829 do_vfp_xp_ldstmia (void)
9831 vfp_dp_ldstm (VFP_LDSTMIAX
);
9835 do_vfp_xp_ldstmdb (void)
9837 vfp_dp_ldstm (VFP_LDSTMDBX
);
9841 do_vfp_dp_rd_rm (void)
9843 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9844 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9848 do_vfp_dp_rn_rd (void)
9850 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9851 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9855 do_vfp_dp_rd_rn (void)
9857 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9858 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9862 do_vfp_dp_rd_rn_rm (void)
9864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9865 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9866 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9872 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9876 do_vfp_dp_rm_rd_rn (void)
9878 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9879 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9880 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9883 /* VFPv3 instructions. */
9885 do_vfp_sp_const (void)
9887 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9888 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9889 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9893 do_vfp_dp_const (void)
9895 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9896 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9897 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9901 vfp_conv (int srcsize
)
9903 int immbits
= srcsize
- inst
.operands
[1].imm
;
9905 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9907 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9908 i.e. immbits must be in range 0 - 16. */
9909 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9912 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9914 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9915 i.e. immbits must be in range 0 - 31. */
9916 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9920 inst
.instruction
|= (immbits
& 1) << 5;
9921 inst
.instruction
|= (immbits
>> 1);
9925 do_vfp_sp_conv_16 (void)
9927 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9932 do_vfp_dp_conv_16 (void)
9934 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9939 do_vfp_sp_conv_32 (void)
9941 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9946 do_vfp_dp_conv_32 (void)
9948 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9952 /* FPA instructions. Also in a logical order. */
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9958 inst
.instruction
|= inst
.operands
[1].reg
;
9962 do_fpa_ldmstm (void)
9964 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9965 switch (inst
.operands
[1].imm
)
9967 case 1: inst
.instruction
|= CP_T_X
; break;
9968 case 2: inst
.instruction
|= CP_T_Y
; break;
9969 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9974 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9976 /* The instruction specified "ea" or "fd", so we can only accept
9977 [Rn]{!}. The instruction does not really support stacking or
9978 unstacking, so we have to emulate these by setting appropriate
9979 bits and offsets. */
9980 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9981 || inst
.reloc
.exp
.X_add_number
!= 0,
9982 _("this instruction does not support indexing"));
9984 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9985 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9987 if (!(inst
.instruction
& INDEX_UP
))
9988 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9990 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9992 inst
.operands
[2].preind
= 0;
9993 inst
.operands
[2].postind
= 1;
9997 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10000 /* iWMMXt instructions: strictly in alphabetical order. */
10003 do_iwmmxt_tandorc (void)
10005 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10009 do_iwmmxt_textrc (void)
10011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10012 inst
.instruction
|= inst
.operands
[1].imm
;
10016 do_iwmmxt_textrm (void)
10018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10019 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10020 inst
.instruction
|= inst
.operands
[2].imm
;
10024 do_iwmmxt_tinsr (void)
10026 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10027 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10028 inst
.instruction
|= inst
.operands
[2].imm
;
10032 do_iwmmxt_tmia (void)
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10035 inst
.instruction
|= inst
.operands
[1].reg
;
10036 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10040 do_iwmmxt_waligni (void)
10042 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10043 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10044 inst
.instruction
|= inst
.operands
[2].reg
;
10045 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10049 do_iwmmxt_wmerge (void)
10051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10052 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10053 inst
.instruction
|= inst
.operands
[2].reg
;
10054 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10058 do_iwmmxt_wmov (void)
10060 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10062 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10063 inst
.instruction
|= inst
.operands
[1].reg
;
10067 do_iwmmxt_wldstbh (void)
10070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10072 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10074 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10075 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10079 do_iwmmxt_wldstw (void)
10081 /* RIWR_RIWC clears .isreg for a control register. */
10082 if (!inst
.operands
[0].isreg
)
10084 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10085 inst
.instruction
|= 0xf0000000;
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10089 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10093 do_iwmmxt_wldstd (void)
10095 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10096 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10097 && inst
.operands
[1].immisreg
)
10099 inst
.instruction
&= ~0x1a000ff;
10100 inst
.instruction
|= (0xfU
<< 28);
10101 if (inst
.operands
[1].preind
)
10102 inst
.instruction
|= PRE_INDEX
;
10103 if (!inst
.operands
[1].negative
)
10104 inst
.instruction
|= INDEX_UP
;
10105 if (inst
.operands
[1].writeback
)
10106 inst
.instruction
|= WRITE_BACK
;
10107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10108 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10109 inst
.instruction
|= inst
.operands
[1].imm
;
10112 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10116 do_iwmmxt_wshufh (void)
10118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10120 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10121 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10125 do_iwmmxt_wzero (void)
10127 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10128 inst
.instruction
|= inst
.operands
[0].reg
;
10129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10130 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10134 do_iwmmxt_wrwrwr_or_imm5 (void)
10136 if (inst
.operands
[2].isreg
)
10139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10140 _("immediate operand requires iWMMXt2"));
10142 if (inst
.operands
[2].imm
== 0)
10144 switch ((inst
.instruction
>> 20) & 0xf)
10150 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10151 inst
.operands
[2].imm
= 16;
10152 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10158 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10159 inst
.operands
[2].imm
= 32;
10160 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10167 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10169 wrn
= (inst
.instruction
>> 16) & 0xf;
10170 inst
.instruction
&= 0xff0fff0f;
10171 inst
.instruction
|= wrn
;
10172 /* Bail out here; the instruction is now assembled. */
10177 /* Map 32 -> 0, etc. */
10178 inst
.operands
[2].imm
&= 0x1f;
10179 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10183 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10184 operations first, then control, shift, and load/store. */
10186 /* Insns like "foo X,Y,Z". */
10189 do_mav_triple (void)
10191 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10192 inst
.instruction
|= inst
.operands
[1].reg
;
10193 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10196 /* Insns like "foo W,X,Y,Z".
10197 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10202 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10203 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10204 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10205 inst
.instruction
|= inst
.operands
[3].reg
;
10208 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10210 do_mav_dspsc (void)
10212 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10215 /* Maverick shift immediate instructions.
10216 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10217 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10220 do_mav_shift (void)
10222 int imm
= inst
.operands
[2].imm
;
10224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10225 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10227 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10228 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10229 Bit 4 should be 0. */
10230 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10232 inst
.instruction
|= imm
;
10235 /* XScale instructions. Also sorted arithmetic before move. */
10237 /* Xscale multiply-accumulate (argument parse)
10240 MIAxycc acc0,Rm,Rs. */
10245 inst
.instruction
|= inst
.operands
[1].reg
;
10246 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10249 /* Xscale move-accumulator-register (argument parse)
10251 MARcc acc0,RdLo,RdHi. */
10256 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10257 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10260 /* Xscale move-register-accumulator (argument parse)
10262 MRAcc RdLo,RdHi,acc0. */
10267 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10272 /* Encoding functions relevant only to Thumb. */
10274 /* inst.operands[i] is a shifted-register operand; encode
10275 it into inst.instruction in the format used by Thumb32. */
10278 encode_thumb32_shifted_operand (int i
)
10280 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10281 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10283 constraint (inst
.operands
[i
].immisreg
,
10284 _("shift by register not allowed in thumb mode"));
10285 inst
.instruction
|= inst
.operands
[i
].reg
;
10286 if (shift
== SHIFT_RRX
)
10287 inst
.instruction
|= SHIFT_ROR
<< 4;
10290 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10291 _("expression too complex"));
10293 constraint (value
> 32
10294 || (value
== 32 && (shift
== SHIFT_LSL
10295 || shift
== SHIFT_ROR
)),
10296 _("shift expression is too large"));
10300 else if (value
== 32)
10303 inst
.instruction
|= shift
<< 4;
10304 inst
.instruction
|= (value
& 0x1c) << 10;
10305 inst
.instruction
|= (value
& 0x03) << 6;
10310 /* inst.operands[i] was set up by parse_address. Encode it into a
10311 Thumb32 format load or store instruction. Reject forms that cannot
10312 be used with such instructions. If is_t is true, reject forms that
10313 cannot be used with a T instruction; if is_d is true, reject forms
10314 that cannot be used with a D instruction. If it is a store insn,
10315 reject PC in Rn. */
10318 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10320 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10322 constraint (!inst
.operands
[i
].isreg
,
10323 _("Instruction does not support =N addresses"));
10325 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10326 if (inst
.operands
[i
].immisreg
)
10328 constraint (is_pc
, BAD_PC_ADDRESSING
);
10329 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10330 constraint (inst
.operands
[i
].negative
,
10331 _("Thumb does not support negative register indexing"));
10332 constraint (inst
.operands
[i
].postind
,
10333 _("Thumb does not support register post-indexing"));
10334 constraint (inst
.operands
[i
].writeback
,
10335 _("Thumb does not support register indexing with writeback"));
10336 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10337 _("Thumb supports only LSL in shifted register indexing"));
10339 inst
.instruction
|= inst
.operands
[i
].imm
;
10340 if (inst
.operands
[i
].shifted
)
10342 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10343 _("expression too complex"));
10344 constraint (inst
.reloc
.exp
.X_add_number
< 0
10345 || inst
.reloc
.exp
.X_add_number
> 3,
10346 _("shift out of range"));
10347 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10349 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10351 else if (inst
.operands
[i
].preind
)
10353 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10354 constraint (is_t
&& inst
.operands
[i
].writeback
,
10355 _("cannot use writeback with this instruction"));
10356 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10357 BAD_PC_ADDRESSING
);
10361 inst
.instruction
|= 0x01000000;
10362 if (inst
.operands
[i
].writeback
)
10363 inst
.instruction
|= 0x00200000;
10367 inst
.instruction
|= 0x00000c00;
10368 if (inst
.operands
[i
].writeback
)
10369 inst
.instruction
|= 0x00000100;
10371 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10373 else if (inst
.operands
[i
].postind
)
10375 gas_assert (inst
.operands
[i
].writeback
);
10376 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10377 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10380 inst
.instruction
|= 0x00200000;
10382 inst
.instruction
|= 0x00000900;
10383 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10385 else /* unindexed - only for coprocessor */
10386 inst
.error
= _("instruction does not accept unindexed addressing");
10389 /* Table of Thumb instructions which exist in both 16- and 32-bit
10390 encodings (the latter only in post-V6T2 cores). The index is the
10391 value used in the insns table below. When there is more than one
10392 possible 16-bit encoding for the instruction, this table always
10394 Also contains several pseudo-instructions used during relaxation. */
10395 #define T16_32_TAB \
10396 X(_adc, 4140, eb400000), \
10397 X(_adcs, 4140, eb500000), \
10398 X(_add, 1c00, eb000000), \
10399 X(_adds, 1c00, eb100000), \
10400 X(_addi, 0000, f1000000), \
10401 X(_addis, 0000, f1100000), \
10402 X(_add_pc,000f, f20f0000), \
10403 X(_add_sp,000d, f10d0000), \
10404 X(_adr, 000f, f20f0000), \
10405 X(_and, 4000, ea000000), \
10406 X(_ands, 4000, ea100000), \
10407 X(_asr, 1000, fa40f000), \
10408 X(_asrs, 1000, fa50f000), \
10409 X(_b, e000, f000b000), \
10410 X(_bcond, d000, f0008000), \
10411 X(_bic, 4380, ea200000), \
10412 X(_bics, 4380, ea300000), \
10413 X(_cmn, 42c0, eb100f00), \
10414 X(_cmp, 2800, ebb00f00), \
10415 X(_cpsie, b660, f3af8400), \
10416 X(_cpsid, b670, f3af8600), \
10417 X(_cpy, 4600, ea4f0000), \
10418 X(_dec_sp,80dd, f1ad0d00), \
10419 X(_eor, 4040, ea800000), \
10420 X(_eors, 4040, ea900000), \
10421 X(_inc_sp,00dd, f10d0d00), \
10422 X(_ldmia, c800, e8900000), \
10423 X(_ldr, 6800, f8500000), \
10424 X(_ldrb, 7800, f8100000), \
10425 X(_ldrh, 8800, f8300000), \
10426 X(_ldrsb, 5600, f9100000), \
10427 X(_ldrsh, 5e00, f9300000), \
10428 X(_ldr_pc,4800, f85f0000), \
10429 X(_ldr_pc2,4800, f85f0000), \
10430 X(_ldr_sp,9800, f85d0000), \
10431 X(_lsl, 0000, fa00f000), \
10432 X(_lsls, 0000, fa10f000), \
10433 X(_lsr, 0800, fa20f000), \
10434 X(_lsrs, 0800, fa30f000), \
10435 X(_mov, 2000, ea4f0000), \
10436 X(_movs, 2000, ea5f0000), \
10437 X(_mul, 4340, fb00f000), \
10438 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10439 X(_mvn, 43c0, ea6f0000), \
10440 X(_mvns, 43c0, ea7f0000), \
10441 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10442 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10443 X(_orr, 4300, ea400000), \
10444 X(_orrs, 4300, ea500000), \
10445 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10446 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10447 X(_rev, ba00, fa90f080), \
10448 X(_rev16, ba40, fa90f090), \
10449 X(_revsh, bac0, fa90f0b0), \
10450 X(_ror, 41c0, fa60f000), \
10451 X(_rors, 41c0, fa70f000), \
10452 X(_sbc, 4180, eb600000), \
10453 X(_sbcs, 4180, eb700000), \
10454 X(_stmia, c000, e8800000), \
10455 X(_str, 6000, f8400000), \
10456 X(_strb, 7000, f8000000), \
10457 X(_strh, 8000, f8200000), \
10458 X(_str_sp,9000, f84d0000), \
10459 X(_sub, 1e00, eba00000), \
10460 X(_subs, 1e00, ebb00000), \
10461 X(_subi, 8000, f1a00000), \
10462 X(_subis, 8000, f1b00000), \
10463 X(_sxtb, b240, fa4ff080), \
10464 X(_sxth, b200, fa0ff080), \
10465 X(_tst, 4200, ea100f00), \
10466 X(_uxtb, b2c0, fa5ff080), \
10467 X(_uxth, b280, fa1ff080), \
10468 X(_nop, bf00, f3af8000), \
10469 X(_yield, bf10, f3af8001), \
10470 X(_wfe, bf20, f3af8002), \
10471 X(_wfi, bf30, f3af8003), \
10472 X(_sev, bf40, f3af8004), \
10473 X(_sevl, bf50, f3af8005), \
10474 X(_udf, de00, f7f0a000)
10476 /* To catch errors in encoding functions, the codes are all offset by
10477 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10478 as 16-bit instructions. */
10479 #define X(a,b,c) T_MNEM##a
10480 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10483 #define X(a,b,c) 0x##b
10484 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10485 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10488 #define X(a,b,c) 0x##c
10489 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10490 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10491 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10495 /* Thumb instruction encoders, in alphabetical order. */
10497 /* ADDW or SUBW. */
10500 do_t_add_sub_w (void)
10504 Rd
= inst
.operands
[0].reg
;
10505 Rn
= inst
.operands
[1].reg
;
10507 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10508 is the SP-{plus,minus}-immediate form of the instruction. */
10510 constraint (Rd
== REG_PC
, BAD_PC
);
10512 reject_bad_reg (Rd
);
10514 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10515 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10518 /* Parse an add or subtract instruction. We get here with inst.instruction
10519 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10522 do_t_add_sub (void)
10526 Rd
= inst
.operands
[0].reg
;
10527 Rs
= (inst
.operands
[1].present
10528 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10529 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10532 set_it_insn_type_last ();
10534 if (unified_syntax
)
10537 bfd_boolean narrow
;
10540 flags
= (inst
.instruction
== T_MNEM_adds
10541 || inst
.instruction
== T_MNEM_subs
);
10543 narrow
= !in_it_block ();
10545 narrow
= in_it_block ();
10546 if (!inst
.operands
[2].isreg
)
10550 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10551 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10553 add
= (inst
.instruction
== T_MNEM_add
10554 || inst
.instruction
== T_MNEM_adds
);
10556 if (inst
.size_req
!= 4)
10558 /* Attempt to use a narrow opcode, with relaxation if
10560 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10561 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10562 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10563 opcode
= T_MNEM_add_sp
;
10564 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10565 opcode
= T_MNEM_add_pc
;
10566 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10569 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10571 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10575 inst
.instruction
= THUMB_OP16(opcode
);
10576 inst
.instruction
|= (Rd
<< 4) | Rs
;
10577 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10578 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10580 if (inst
.size_req
== 2)
10581 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10583 inst
.relax
= opcode
;
10587 constraint (inst
.size_req
== 2, BAD_HIREG
);
10589 if (inst
.size_req
== 4
10590 || (inst
.size_req
!= 2 && !opcode
))
10592 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10593 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10594 THUMB1_RELOC_ONLY
);
10597 constraint (add
, BAD_PC
);
10598 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10599 _("only SUBS PC, LR, #const allowed"));
10600 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10601 _("expression too complex"));
10602 constraint (inst
.reloc
.exp
.X_add_number
< 0
10603 || inst
.reloc
.exp
.X_add_number
> 0xff,
10604 _("immediate value out of range"));
10605 inst
.instruction
= T2_SUBS_PC_LR
10606 | inst
.reloc
.exp
.X_add_number
;
10607 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10610 else if (Rs
== REG_PC
)
10612 /* Always use addw/subw. */
10613 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10614 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10618 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10619 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10622 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10624 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10626 inst
.instruction
|= Rd
<< 8;
10627 inst
.instruction
|= Rs
<< 16;
10632 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10633 unsigned int shift
= inst
.operands
[2].shift_kind
;
10635 Rn
= inst
.operands
[2].reg
;
10636 /* See if we can do this with a 16-bit instruction. */
10637 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10639 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10644 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10645 || inst
.instruction
== T_MNEM_add
)
10647 : T_OPCODE_SUB_R3
);
10648 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10652 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10654 /* Thumb-1 cores (except v6-M) require at least one high
10655 register in a narrow non flag setting add. */
10656 if (Rd
> 7 || Rn
> 7
10657 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10658 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10665 inst
.instruction
= T_OPCODE_ADD_HI
;
10666 inst
.instruction
|= (Rd
& 8) << 4;
10667 inst
.instruction
|= (Rd
& 7);
10668 inst
.instruction
|= Rn
<< 3;
10674 constraint (Rd
== REG_PC
, BAD_PC
);
10675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10676 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10677 constraint (Rs
== REG_PC
, BAD_PC
);
10678 reject_bad_reg (Rn
);
10680 /* If we get here, it can't be done in 16 bits. */
10681 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10682 _("shift must be constant"));
10683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10684 inst
.instruction
|= Rd
<< 8;
10685 inst
.instruction
|= Rs
<< 16;
10686 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10687 _("shift value over 3 not allowed in thumb mode"));
10688 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10689 _("only LSL shift allowed in thumb mode"));
10690 encode_thumb32_shifted_operand (2);
10695 constraint (inst
.instruction
== T_MNEM_adds
10696 || inst
.instruction
== T_MNEM_subs
,
10699 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10701 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10702 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10705 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10706 ? 0x0000 : 0x8000);
10707 inst
.instruction
|= (Rd
<< 4) | Rs
;
10708 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10712 Rn
= inst
.operands
[2].reg
;
10713 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10715 /* We now have Rd, Rs, and Rn set to registers. */
10716 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10718 /* Can't do this for SUB. */
10719 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10720 inst
.instruction
= T_OPCODE_ADD_HI
;
10721 inst
.instruction
|= (Rd
& 8) << 4;
10722 inst
.instruction
|= (Rd
& 7);
10724 inst
.instruction
|= Rn
<< 3;
10726 inst
.instruction
|= Rs
<< 3;
10728 constraint (1, _("dest must overlap one source register"));
10732 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10733 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10734 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10744 Rd
= inst
.operands
[0].reg
;
10745 reject_bad_reg (Rd
);
10747 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10749 /* Defer to section relaxation. */
10750 inst
.relax
= inst
.instruction
;
10751 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10752 inst
.instruction
|= Rd
<< 4;
10754 else if (unified_syntax
&& inst
.size_req
!= 2)
10756 /* Generate a 32-bit opcode. */
10757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10758 inst
.instruction
|= Rd
<< 8;
10759 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10760 inst
.reloc
.pc_rel
= 1;
10764 /* Generate a 16-bit opcode. */
10765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10766 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10767 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10768 inst
.reloc
.pc_rel
= 1;
10769 inst
.instruction
|= Rd
<< 4;
10772 if (inst
.reloc
.exp
.X_op
== O_symbol
10773 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10774 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10775 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10776 inst
.reloc
.exp
.X_add_number
+= 1;
10779 /* Arithmetic instructions for which there is just one 16-bit
10780 instruction encoding, and it allows only two low registers.
10781 For maximal compatibility with ARM syntax, we allow three register
10782 operands even when Thumb-32 instructions are not available, as long
10783 as the first two are identical. For instance, both "sbc r0,r1" and
10784 "sbc r0,r0,r1" are allowed. */
10790 Rd
= inst
.operands
[0].reg
;
10791 Rs
= (inst
.operands
[1].present
10792 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10793 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10794 Rn
= inst
.operands
[2].reg
;
10796 reject_bad_reg (Rd
);
10797 reject_bad_reg (Rs
);
10798 if (inst
.operands
[2].isreg
)
10799 reject_bad_reg (Rn
);
10801 if (unified_syntax
)
10803 if (!inst
.operands
[2].isreg
)
10805 /* For an immediate, we always generate a 32-bit opcode;
10806 section relaxation will shrink it later if possible. */
10807 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10808 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10809 inst
.instruction
|= Rd
<< 8;
10810 inst
.instruction
|= Rs
<< 16;
10811 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10815 bfd_boolean narrow
;
10817 /* See if we can do this with a 16-bit instruction. */
10818 if (THUMB_SETS_FLAGS (inst
.instruction
))
10819 narrow
= !in_it_block ();
10821 narrow
= in_it_block ();
10823 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10825 if (inst
.operands
[2].shifted
)
10827 if (inst
.size_req
== 4)
10833 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10834 inst
.instruction
|= Rd
;
10835 inst
.instruction
|= Rn
<< 3;
10839 /* If we get here, it can't be done in 16 bits. */
10840 constraint (inst
.operands
[2].shifted
10841 && inst
.operands
[2].immisreg
,
10842 _("shift must be constant"));
10843 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10844 inst
.instruction
|= Rd
<< 8;
10845 inst
.instruction
|= Rs
<< 16;
10846 encode_thumb32_shifted_operand (2);
10851 /* On its face this is a lie - the instruction does set the
10852 flags. However, the only supported mnemonic in this mode
10853 says it doesn't. */
10854 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10856 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10857 _("unshifted register required"));
10858 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10859 constraint (Rd
!= Rs
,
10860 _("dest and source1 must be the same register"));
10862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10863 inst
.instruction
|= Rd
;
10864 inst
.instruction
|= Rn
<< 3;
10868 /* Similarly, but for instructions where the arithmetic operation is
10869 commutative, so we can allow either of them to be different from
10870 the destination operand in a 16-bit instruction. For instance, all
10871 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10878 Rd
= inst
.operands
[0].reg
;
10879 Rs
= (inst
.operands
[1].present
10880 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10881 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10882 Rn
= inst
.operands
[2].reg
;
10884 reject_bad_reg (Rd
);
10885 reject_bad_reg (Rs
);
10886 if (inst
.operands
[2].isreg
)
10887 reject_bad_reg (Rn
);
10889 if (unified_syntax
)
10891 if (!inst
.operands
[2].isreg
)
10893 /* For an immediate, we always generate a 32-bit opcode;
10894 section relaxation will shrink it later if possible. */
10895 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10896 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10897 inst
.instruction
|= Rd
<< 8;
10898 inst
.instruction
|= Rs
<< 16;
10899 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10903 bfd_boolean narrow
;
10905 /* See if we can do this with a 16-bit instruction. */
10906 if (THUMB_SETS_FLAGS (inst
.instruction
))
10907 narrow
= !in_it_block ();
10909 narrow
= in_it_block ();
10911 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10913 if (inst
.operands
[2].shifted
)
10915 if (inst
.size_req
== 4)
10922 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10923 inst
.instruction
|= Rd
;
10924 inst
.instruction
|= Rn
<< 3;
10929 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10930 inst
.instruction
|= Rd
;
10931 inst
.instruction
|= Rs
<< 3;
10936 /* If we get here, it can't be done in 16 bits. */
10937 constraint (inst
.operands
[2].shifted
10938 && inst
.operands
[2].immisreg
,
10939 _("shift must be constant"));
10940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10941 inst
.instruction
|= Rd
<< 8;
10942 inst
.instruction
|= Rs
<< 16;
10943 encode_thumb32_shifted_operand (2);
10948 /* On its face this is a lie - the instruction does set the
10949 flags. However, the only supported mnemonic in this mode
10950 says it doesn't. */
10951 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10953 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10954 _("unshifted register required"));
10955 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10957 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10958 inst
.instruction
|= Rd
;
10961 inst
.instruction
|= Rn
<< 3;
10963 inst
.instruction
|= Rs
<< 3;
10965 constraint (1, _("dest must overlap one source register"));
10973 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10974 constraint (msb
> 32, _("bit-field extends past end of register"));
10975 /* The instruction encoding stores the LSB and MSB,
10976 not the LSB and width. */
10977 Rd
= inst
.operands
[0].reg
;
10978 reject_bad_reg (Rd
);
10979 inst
.instruction
|= Rd
<< 8;
10980 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10981 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10982 inst
.instruction
|= msb
- 1;
10991 Rd
= inst
.operands
[0].reg
;
10992 reject_bad_reg (Rd
);
10994 /* #0 in second position is alternative syntax for bfc, which is
10995 the same instruction but with REG_PC in the Rm field. */
10996 if (!inst
.operands
[1].isreg
)
11000 Rn
= inst
.operands
[1].reg
;
11001 reject_bad_reg (Rn
);
11004 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11005 constraint (msb
> 32, _("bit-field extends past end of register"));
11006 /* The instruction encoding stores the LSB and MSB,
11007 not the LSB and width. */
11008 inst
.instruction
|= Rd
<< 8;
11009 inst
.instruction
|= Rn
<< 16;
11010 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11011 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11012 inst
.instruction
|= msb
- 1;
11020 Rd
= inst
.operands
[0].reg
;
11021 Rn
= inst
.operands
[1].reg
;
11023 reject_bad_reg (Rd
);
11024 reject_bad_reg (Rn
);
11026 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11027 _("bit-field extends past end of register"));
11028 inst
.instruction
|= Rd
<< 8;
11029 inst
.instruction
|= Rn
<< 16;
11030 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11031 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11032 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11035 /* ARM V5 Thumb BLX (argument parse)
11036 BLX <target_addr> which is BLX(1)
11037 BLX <Rm> which is BLX(2)
11038 Unfortunately, there are two different opcodes for this mnemonic.
11039 So, the insns[].value is not used, and the code here zaps values
11040 into inst.instruction.
11042 ??? How to take advantage of the additional two bits of displacement
11043 available in Thumb32 mode? Need new relocation? */
11048 set_it_insn_type_last ();
11050 if (inst
.operands
[0].isreg
)
11052 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11053 /* We have a register, so this is BLX(2). */
11054 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11058 /* No register. This must be BLX(1). */
11059 inst
.instruction
= 0xf000e800;
11060 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11069 bfd_reloc_code_real_type reloc
;
11072 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11074 if (in_it_block ())
11076 /* Conditional branches inside IT blocks are encoded as unconditional
11078 cond
= COND_ALWAYS
;
11083 if (cond
!= COND_ALWAYS
)
11084 opcode
= T_MNEM_bcond
;
11086 opcode
= inst
.instruction
;
11089 && (inst
.size_req
== 4
11090 || (inst
.size_req
!= 2
11091 && (inst
.operands
[0].hasreloc
11092 || inst
.reloc
.exp
.X_op
== O_constant
))))
11094 inst
.instruction
= THUMB_OP32(opcode
);
11095 if (cond
== COND_ALWAYS
)
11096 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11100 _("selected architecture does not support "
11101 "wide conditional branch instruction"));
11103 gas_assert (cond
!= 0xF);
11104 inst
.instruction
|= cond
<< 22;
11105 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11110 inst
.instruction
= THUMB_OP16(opcode
);
11111 if (cond
== COND_ALWAYS
)
11112 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11115 inst
.instruction
|= cond
<< 8;
11116 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11118 /* Allow section relaxation. */
11119 if (unified_syntax
&& inst
.size_req
!= 2)
11120 inst
.relax
= opcode
;
11122 inst
.reloc
.type
= reloc
;
11123 inst
.reloc
.pc_rel
= 1;
11126 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11127 between the two is the maximum immediate allowed - which is passed in
11130 do_t_bkpt_hlt1 (int range
)
11132 constraint (inst
.cond
!= COND_ALWAYS
,
11133 _("instruction is always unconditional"));
11134 if (inst
.operands
[0].present
)
11136 constraint (inst
.operands
[0].imm
> range
,
11137 _("immediate value out of range"));
11138 inst
.instruction
|= inst
.operands
[0].imm
;
11141 set_it_insn_type (NEUTRAL_IT_INSN
);
11147 do_t_bkpt_hlt1 (63);
11153 do_t_bkpt_hlt1 (255);
11157 do_t_branch23 (void)
11159 set_it_insn_type_last ();
11160 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11162 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11163 this file. We used to simply ignore the PLT reloc type here --
11164 the branch encoding is now needed to deal with TLSCALL relocs.
11165 So if we see a PLT reloc now, put it back to how it used to be to
11166 keep the preexisting behaviour. */
11167 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11168 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11170 #if defined(OBJ_COFF)
11171 /* If the destination of the branch is a defined symbol which does not have
11172 the THUMB_FUNC attribute, then we must be calling a function which has
11173 the (interfacearm) attribute. We look for the Thumb entry point to that
11174 function and change the branch to refer to that function instead. */
11175 if ( inst
.reloc
.exp
.X_op
== O_symbol
11176 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11177 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11178 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11179 inst
.reloc
.exp
.X_add_symbol
=
11180 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11187 set_it_insn_type_last ();
11188 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11189 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11190 should cause the alignment to be checked once it is known. This is
11191 because BX PC only works if the instruction is word aligned. */
11199 set_it_insn_type_last ();
11200 Rm
= inst
.operands
[0].reg
;
11201 reject_bad_reg (Rm
);
11202 inst
.instruction
|= Rm
<< 16;
11211 Rd
= inst
.operands
[0].reg
;
11212 Rm
= inst
.operands
[1].reg
;
11214 reject_bad_reg (Rd
);
11215 reject_bad_reg (Rm
);
11217 inst
.instruction
|= Rd
<< 8;
11218 inst
.instruction
|= Rm
<< 16;
11219 inst
.instruction
|= Rm
;
11225 set_it_insn_type (OUTSIDE_IT_INSN
);
11226 inst
.instruction
|= inst
.operands
[0].imm
;
11232 set_it_insn_type (OUTSIDE_IT_INSN
);
11234 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11235 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11237 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11238 inst
.instruction
= 0xf3af8000;
11239 inst
.instruction
|= imod
<< 9;
11240 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11241 if (inst
.operands
[1].present
)
11242 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11246 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11247 && (inst
.operands
[0].imm
& 4),
11248 _("selected processor does not support 'A' form "
11249 "of this instruction"));
11250 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11251 _("Thumb does not support the 2-argument "
11252 "form of this instruction"));
11253 inst
.instruction
|= inst
.operands
[0].imm
;
11257 /* THUMB CPY instruction (argument parse). */
11262 if (inst
.size_req
== 4)
11264 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11265 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11266 inst
.instruction
|= inst
.operands
[1].reg
;
11270 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11271 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11272 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11279 set_it_insn_type (OUTSIDE_IT_INSN
);
11280 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11281 inst
.instruction
|= inst
.operands
[0].reg
;
11282 inst
.reloc
.pc_rel
= 1;
11283 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11289 inst
.instruction
|= inst
.operands
[0].imm
;
11295 unsigned Rd
, Rn
, Rm
;
11297 Rd
= inst
.operands
[0].reg
;
11298 Rn
= (inst
.operands
[1].present
11299 ? inst
.operands
[1].reg
: Rd
);
11300 Rm
= inst
.operands
[2].reg
;
11302 reject_bad_reg (Rd
);
11303 reject_bad_reg (Rn
);
11304 reject_bad_reg (Rm
);
11306 inst
.instruction
|= Rd
<< 8;
11307 inst
.instruction
|= Rn
<< 16;
11308 inst
.instruction
|= Rm
;
11314 if (unified_syntax
&& inst
.size_req
== 4)
11315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11317 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11323 unsigned int cond
= inst
.operands
[0].imm
;
11325 set_it_insn_type (IT_INSN
);
11326 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11328 now_it
.warn_deprecated
= FALSE
;
11330 /* If the condition is a negative condition, invert the mask. */
11331 if ((cond
& 0x1) == 0x0)
11333 unsigned int mask
= inst
.instruction
& 0x000f;
11335 if ((mask
& 0x7) == 0)
11337 /* No conversion needed. */
11338 now_it
.block_length
= 1;
11340 else if ((mask
& 0x3) == 0)
11343 now_it
.block_length
= 2;
11345 else if ((mask
& 0x1) == 0)
11348 now_it
.block_length
= 3;
11353 now_it
.block_length
= 4;
11356 inst
.instruction
&= 0xfff0;
11357 inst
.instruction
|= mask
;
11360 inst
.instruction
|= cond
<< 4;
11363 /* Helper function used for both push/pop and ldm/stm. */
11365 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11369 load
= (inst
.instruction
& (1 << 20)) != 0;
11371 if (mask
& (1 << 13))
11372 inst
.error
= _("SP not allowed in register list");
11374 if ((mask
& (1 << base
)) != 0
11376 inst
.error
= _("having the base register in the register list when "
11377 "using write back is UNPREDICTABLE");
11381 if (mask
& (1 << 15))
11383 if (mask
& (1 << 14))
11384 inst
.error
= _("LR and PC should not both be in register list");
11386 set_it_insn_type_last ();
11391 if (mask
& (1 << 15))
11392 inst
.error
= _("PC not allowed in register list");
11395 if ((mask
& (mask
- 1)) == 0)
11397 /* Single register transfers implemented as str/ldr. */
11400 if (inst
.instruction
& (1 << 23))
11401 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11403 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11407 if (inst
.instruction
& (1 << 23))
11408 inst
.instruction
= 0x00800000; /* ia -> [base] */
11410 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11413 inst
.instruction
|= 0xf8400000;
11415 inst
.instruction
|= 0x00100000;
11417 mask
= ffs (mask
) - 1;
11420 else if (writeback
)
11421 inst
.instruction
|= WRITE_BACK
;
11423 inst
.instruction
|= mask
;
11424 inst
.instruction
|= base
<< 16;
11430 /* This really doesn't seem worth it. */
11431 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11432 _("expression too complex"));
11433 constraint (inst
.operands
[1].writeback
,
11434 _("Thumb load/store multiple does not support {reglist}^"));
11436 if (unified_syntax
)
11438 bfd_boolean narrow
;
11442 /* See if we can use a 16-bit instruction. */
11443 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11444 && inst
.size_req
!= 4
11445 && !(inst
.operands
[1].imm
& ~0xff))
11447 mask
= 1 << inst
.operands
[0].reg
;
11449 if (inst
.operands
[0].reg
<= 7)
11451 if (inst
.instruction
== T_MNEM_stmia
11452 ? inst
.operands
[0].writeback
11453 : (inst
.operands
[0].writeback
11454 == !(inst
.operands
[1].imm
& mask
)))
11456 if (inst
.instruction
== T_MNEM_stmia
11457 && (inst
.operands
[1].imm
& mask
)
11458 && (inst
.operands
[1].imm
& (mask
- 1)))
11459 as_warn (_("value stored for r%d is UNKNOWN"),
11460 inst
.operands
[0].reg
);
11462 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11463 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11464 inst
.instruction
|= inst
.operands
[1].imm
;
11467 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11469 /* This means 1 register in reg list one of 3 situations:
11470 1. Instruction is stmia, but without writeback.
11471 2. lmdia without writeback, but with Rn not in
11473 3. ldmia with writeback, but with Rn in reglist.
11474 Case 3 is UNPREDICTABLE behaviour, so we handle
11475 case 1 and 2 which can be converted into a 16-bit
11476 str or ldr. The SP cases are handled below. */
11477 unsigned long opcode
;
11478 /* First, record an error for Case 3. */
11479 if (inst
.operands
[1].imm
& mask
11480 && inst
.operands
[0].writeback
)
11482 _("having the base register in the register list when "
11483 "using write back is UNPREDICTABLE");
11485 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11487 inst
.instruction
= THUMB_OP16 (opcode
);
11488 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11489 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11493 else if (inst
.operands
[0] .reg
== REG_SP
)
11495 if (inst
.operands
[0].writeback
)
11498 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11499 ? T_MNEM_push
: T_MNEM_pop
);
11500 inst
.instruction
|= inst
.operands
[1].imm
;
11503 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11506 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11507 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11508 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11516 if (inst
.instruction
< 0xffff)
11517 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11519 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11520 inst
.operands
[0].writeback
);
11525 constraint (inst
.operands
[0].reg
> 7
11526 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11527 constraint (inst
.instruction
!= T_MNEM_ldmia
11528 && inst
.instruction
!= T_MNEM_stmia
,
11529 _("Thumb-2 instruction only valid in unified syntax"));
11530 if (inst
.instruction
== T_MNEM_stmia
)
11532 if (!inst
.operands
[0].writeback
)
11533 as_warn (_("this instruction will write back the base register"));
11534 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11535 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11536 as_warn (_("value stored for r%d is UNKNOWN"),
11537 inst
.operands
[0].reg
);
11541 if (!inst
.operands
[0].writeback
11542 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11543 as_warn (_("this instruction will write back the base register"));
11544 else if (inst
.operands
[0].writeback
11545 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11546 as_warn (_("this instruction will not write back the base register"));
11549 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11550 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11551 inst
.instruction
|= inst
.operands
[1].imm
;
11558 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11559 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11560 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11561 || inst
.operands
[1].negative
,
11564 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11566 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11567 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11568 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11574 if (!inst
.operands
[1].present
)
11576 constraint (inst
.operands
[0].reg
== REG_LR
,
11577 _("r14 not allowed as first register "
11578 "when second register is omitted"));
11579 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11581 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11585 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11586 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11592 unsigned long opcode
;
11595 if (inst
.operands
[0].isreg
11596 && !inst
.operands
[0].preind
11597 && inst
.operands
[0].reg
== REG_PC
)
11598 set_it_insn_type_last ();
11600 opcode
= inst
.instruction
;
11601 if (unified_syntax
)
11603 if (!inst
.operands
[1].isreg
)
11605 if (opcode
<= 0xffff)
11606 inst
.instruction
= THUMB_OP32 (opcode
);
11607 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11610 if (inst
.operands
[1].isreg
11611 && !inst
.operands
[1].writeback
11612 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11613 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11614 && opcode
<= 0xffff
11615 && inst
.size_req
!= 4)
11617 /* Insn may have a 16-bit form. */
11618 Rn
= inst
.operands
[1].reg
;
11619 if (inst
.operands
[1].immisreg
)
11621 inst
.instruction
= THUMB_OP16 (opcode
);
11623 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11625 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11626 reject_bad_reg (inst
.operands
[1].imm
);
11628 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11629 && opcode
!= T_MNEM_ldrsb
)
11630 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11631 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11638 if (inst
.reloc
.pc_rel
)
11639 opcode
= T_MNEM_ldr_pc2
;
11641 opcode
= T_MNEM_ldr_pc
;
11645 if (opcode
== T_MNEM_ldr
)
11646 opcode
= T_MNEM_ldr_sp
;
11648 opcode
= T_MNEM_str_sp
;
11650 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11654 inst
.instruction
= inst
.operands
[0].reg
;
11655 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11657 inst
.instruction
|= THUMB_OP16 (opcode
);
11658 if (inst
.size_req
== 2)
11659 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11661 inst
.relax
= opcode
;
11665 /* Definitely a 32-bit variant. */
11667 /* Warning for Erratum 752419. */
11668 if (opcode
== T_MNEM_ldr
11669 && inst
.operands
[0].reg
== REG_SP
11670 && inst
.operands
[1].writeback
== 1
11671 && !inst
.operands
[1].immisreg
)
11673 if (no_cpu_selected ()
11674 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11675 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11676 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11677 as_warn (_("This instruction may be unpredictable "
11678 "if executed on M-profile cores "
11679 "with interrupts enabled."));
11682 /* Do some validations regarding addressing modes. */
11683 if (inst
.operands
[1].immisreg
)
11684 reject_bad_reg (inst
.operands
[1].imm
);
11686 constraint (inst
.operands
[1].writeback
== 1
11687 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11690 inst
.instruction
= THUMB_OP32 (opcode
);
11691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11692 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11693 check_ldr_r15_aligned ();
11697 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11699 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11701 /* Only [Rn,Rm] is acceptable. */
11702 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11703 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11704 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11705 || inst
.operands
[1].negative
,
11706 _("Thumb does not support this addressing mode"));
11707 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11711 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11712 if (!inst
.operands
[1].isreg
)
11713 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11716 constraint (!inst
.operands
[1].preind
11717 || inst
.operands
[1].shifted
11718 || inst
.operands
[1].writeback
,
11719 _("Thumb does not support this addressing mode"));
11720 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11722 constraint (inst
.instruction
& 0x0600,
11723 _("byte or halfword not valid for base register"));
11724 constraint (inst
.operands
[1].reg
== REG_PC
11725 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11726 _("r15 based store not allowed"));
11727 constraint (inst
.operands
[1].immisreg
,
11728 _("invalid base register for register offset"));
11730 if (inst
.operands
[1].reg
== REG_PC
)
11731 inst
.instruction
= T_OPCODE_LDR_PC
;
11732 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11733 inst
.instruction
= T_OPCODE_LDR_SP
;
11735 inst
.instruction
= T_OPCODE_STR_SP
;
11737 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11738 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11742 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11743 if (!inst
.operands
[1].immisreg
)
11745 /* Immediate offset. */
11746 inst
.instruction
|= inst
.operands
[0].reg
;
11747 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11748 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11752 /* Register offset. */
11753 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11754 constraint (inst
.operands
[1].negative
,
11755 _("Thumb does not support this addressing mode"));
11758 switch (inst
.instruction
)
11760 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11761 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11762 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11763 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11764 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11765 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11766 case 0x5600 /* ldrsb */:
11767 case 0x5e00 /* ldrsh */: break;
11771 inst
.instruction
|= inst
.operands
[0].reg
;
11772 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11773 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11779 if (!inst
.operands
[1].present
)
11781 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11782 constraint (inst
.operands
[0].reg
== REG_LR
,
11783 _("r14 not allowed here"));
11784 constraint (inst
.operands
[0].reg
== REG_R12
,
11785 _("r12 not allowed here"));
11788 if (inst
.operands
[2].writeback
11789 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11790 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11791 as_warn (_("base register written back, and overlaps "
11792 "one of transfer registers"));
11794 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11795 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11796 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11803 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11809 unsigned Rd
, Rn
, Rm
, Ra
;
11811 Rd
= inst
.operands
[0].reg
;
11812 Rn
= inst
.operands
[1].reg
;
11813 Rm
= inst
.operands
[2].reg
;
11814 Ra
= inst
.operands
[3].reg
;
11816 reject_bad_reg (Rd
);
11817 reject_bad_reg (Rn
);
11818 reject_bad_reg (Rm
);
11819 reject_bad_reg (Ra
);
11821 inst
.instruction
|= Rd
<< 8;
11822 inst
.instruction
|= Rn
<< 16;
11823 inst
.instruction
|= Rm
;
11824 inst
.instruction
|= Ra
<< 12;
11830 unsigned RdLo
, RdHi
, Rn
, Rm
;
11832 RdLo
= inst
.operands
[0].reg
;
11833 RdHi
= inst
.operands
[1].reg
;
11834 Rn
= inst
.operands
[2].reg
;
11835 Rm
= inst
.operands
[3].reg
;
11837 reject_bad_reg (RdLo
);
11838 reject_bad_reg (RdHi
);
11839 reject_bad_reg (Rn
);
11840 reject_bad_reg (Rm
);
11842 inst
.instruction
|= RdLo
<< 12;
11843 inst
.instruction
|= RdHi
<< 8;
11844 inst
.instruction
|= Rn
<< 16;
11845 inst
.instruction
|= Rm
;
11849 do_t_mov_cmp (void)
11853 Rn
= inst
.operands
[0].reg
;
11854 Rm
= inst
.operands
[1].reg
;
11857 set_it_insn_type_last ();
11859 if (unified_syntax
)
11861 int r0off
= (inst
.instruction
== T_MNEM_mov
11862 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11863 unsigned long opcode
;
11864 bfd_boolean narrow
;
11865 bfd_boolean low_regs
;
11867 low_regs
= (Rn
<= 7 && Rm
<= 7);
11868 opcode
= inst
.instruction
;
11869 if (in_it_block ())
11870 narrow
= opcode
!= T_MNEM_movs
;
11872 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11873 if (inst
.size_req
== 4
11874 || inst
.operands
[1].shifted
)
11877 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11878 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11879 && !inst
.operands
[1].shifted
11883 inst
.instruction
= T2_SUBS_PC_LR
;
11887 if (opcode
== T_MNEM_cmp
)
11889 constraint (Rn
== REG_PC
, BAD_PC
);
11892 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11894 warn_deprecated_sp (Rm
);
11895 /* R15 was documented as a valid choice for Rm in ARMv6,
11896 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11897 tools reject R15, so we do too. */
11898 constraint (Rm
== REG_PC
, BAD_PC
);
11901 reject_bad_reg (Rm
);
11903 else if (opcode
== T_MNEM_mov
11904 || opcode
== T_MNEM_movs
)
11906 if (inst
.operands
[1].isreg
)
11908 if (opcode
== T_MNEM_movs
)
11910 reject_bad_reg (Rn
);
11911 reject_bad_reg (Rm
);
11915 /* This is mov.n. */
11916 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11917 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11919 as_tsktsk (_("Use of r%u as a source register is "
11920 "deprecated when r%u is the destination "
11921 "register."), Rm
, Rn
);
11926 /* This is mov.w. */
11927 constraint (Rn
== REG_PC
, BAD_PC
);
11928 constraint (Rm
== REG_PC
, BAD_PC
);
11929 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11930 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11934 reject_bad_reg (Rn
);
11937 if (!inst
.operands
[1].isreg
)
11939 /* Immediate operand. */
11940 if (!in_it_block () && opcode
== T_MNEM_mov
)
11942 if (low_regs
&& narrow
)
11944 inst
.instruction
= THUMB_OP16 (opcode
);
11945 inst
.instruction
|= Rn
<< 8;
11946 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11947 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11949 if (inst
.size_req
== 2)
11950 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11952 inst
.relax
= opcode
;
11957 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11958 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11959 THUMB1_RELOC_ONLY
);
11961 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11962 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11963 inst
.instruction
|= Rn
<< r0off
;
11964 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11967 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11968 && (inst
.instruction
== T_MNEM_mov
11969 || inst
.instruction
== T_MNEM_movs
))
11971 /* Register shifts are encoded as separate shift instructions. */
11972 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11974 if (in_it_block ())
11979 if (inst
.size_req
== 4)
11982 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11988 switch (inst
.operands
[1].shift_kind
)
11991 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11994 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11997 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12000 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12006 inst
.instruction
= opcode
;
12009 inst
.instruction
|= Rn
;
12010 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12015 inst
.instruction
|= CONDS_BIT
;
12017 inst
.instruction
|= Rn
<< 8;
12018 inst
.instruction
|= Rm
<< 16;
12019 inst
.instruction
|= inst
.operands
[1].imm
;
12024 /* Some mov with immediate shift have narrow variants.
12025 Register shifts are handled above. */
12026 if (low_regs
&& inst
.operands
[1].shifted
12027 && (inst
.instruction
== T_MNEM_mov
12028 || inst
.instruction
== T_MNEM_movs
))
12030 if (in_it_block ())
12031 narrow
= (inst
.instruction
== T_MNEM_mov
);
12033 narrow
= (inst
.instruction
== T_MNEM_movs
);
12038 switch (inst
.operands
[1].shift_kind
)
12040 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12041 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12042 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12043 default: narrow
= FALSE
; break;
12049 inst
.instruction
|= Rn
;
12050 inst
.instruction
|= Rm
<< 3;
12051 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12055 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12056 inst
.instruction
|= Rn
<< r0off
;
12057 encode_thumb32_shifted_operand (1);
12061 switch (inst
.instruction
)
12064 /* In v4t or v5t a move of two lowregs produces unpredictable
12065 results. Don't allow this. */
12068 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12069 "MOV Rd, Rs with two low registers is not "
12070 "permitted on this architecture");
12071 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12075 inst
.instruction
= T_OPCODE_MOV_HR
;
12076 inst
.instruction
|= (Rn
& 0x8) << 4;
12077 inst
.instruction
|= (Rn
& 0x7);
12078 inst
.instruction
|= Rm
<< 3;
12082 /* We know we have low registers at this point.
12083 Generate LSLS Rd, Rs, #0. */
12084 inst
.instruction
= T_OPCODE_LSL_I
;
12085 inst
.instruction
|= Rn
;
12086 inst
.instruction
|= Rm
<< 3;
12092 inst
.instruction
= T_OPCODE_CMP_LR
;
12093 inst
.instruction
|= Rn
;
12094 inst
.instruction
|= Rm
<< 3;
12098 inst
.instruction
= T_OPCODE_CMP_HR
;
12099 inst
.instruction
|= (Rn
& 0x8) << 4;
12100 inst
.instruction
|= (Rn
& 0x7);
12101 inst
.instruction
|= Rm
<< 3;
12108 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12110 /* PR 10443: Do not silently ignore shifted operands. */
12111 constraint (inst
.operands
[1].shifted
,
12112 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12114 if (inst
.operands
[1].isreg
)
12116 if (Rn
< 8 && Rm
< 8)
12118 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12119 since a MOV instruction produces unpredictable results. */
12120 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12121 inst
.instruction
= T_OPCODE_ADD_I3
;
12123 inst
.instruction
= T_OPCODE_CMP_LR
;
12125 inst
.instruction
|= Rn
;
12126 inst
.instruction
|= Rm
<< 3;
12130 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12131 inst
.instruction
= T_OPCODE_MOV_HR
;
12133 inst
.instruction
= T_OPCODE_CMP_HR
;
12139 constraint (Rn
> 7,
12140 _("only lo regs allowed with immediate"));
12141 inst
.instruction
|= Rn
<< 8;
12142 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12153 top
= (inst
.instruction
& 0x00800000) != 0;
12154 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12156 constraint (top
, _(":lower16: not allowed in this instruction"));
12157 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12159 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12161 constraint (!top
, _(":upper16: not allowed in this instruction"));
12162 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12165 Rd
= inst
.operands
[0].reg
;
12166 reject_bad_reg (Rd
);
12168 inst
.instruction
|= Rd
<< 8;
12169 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12171 imm
= inst
.reloc
.exp
.X_add_number
;
12172 inst
.instruction
|= (imm
& 0xf000) << 4;
12173 inst
.instruction
|= (imm
& 0x0800) << 15;
12174 inst
.instruction
|= (imm
& 0x0700) << 4;
12175 inst
.instruction
|= (imm
& 0x00ff);
12180 do_t_mvn_tst (void)
12184 Rn
= inst
.operands
[0].reg
;
12185 Rm
= inst
.operands
[1].reg
;
12187 if (inst
.instruction
== T_MNEM_cmp
12188 || inst
.instruction
== T_MNEM_cmn
)
12189 constraint (Rn
== REG_PC
, BAD_PC
);
12191 reject_bad_reg (Rn
);
12192 reject_bad_reg (Rm
);
12194 if (unified_syntax
)
12196 int r0off
= (inst
.instruction
== T_MNEM_mvn
12197 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12198 bfd_boolean narrow
;
12200 if (inst
.size_req
== 4
12201 || inst
.instruction
> 0xffff
12202 || inst
.operands
[1].shifted
12203 || Rn
> 7 || Rm
> 7)
12205 else if (inst
.instruction
== T_MNEM_cmn
12206 || inst
.instruction
== T_MNEM_tst
)
12208 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12209 narrow
= !in_it_block ();
12211 narrow
= in_it_block ();
12213 if (!inst
.operands
[1].isreg
)
12215 /* For an immediate, we always generate a 32-bit opcode;
12216 section relaxation will shrink it later if possible. */
12217 if (inst
.instruction
< 0xffff)
12218 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12219 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12220 inst
.instruction
|= Rn
<< r0off
;
12221 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12225 /* See if we can do this with a 16-bit instruction. */
12228 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12229 inst
.instruction
|= Rn
;
12230 inst
.instruction
|= Rm
<< 3;
12234 constraint (inst
.operands
[1].shifted
12235 && inst
.operands
[1].immisreg
,
12236 _("shift must be constant"));
12237 if (inst
.instruction
< 0xffff)
12238 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12239 inst
.instruction
|= Rn
<< r0off
;
12240 encode_thumb32_shifted_operand (1);
12246 constraint (inst
.instruction
> 0xffff
12247 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12248 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12249 _("unshifted register required"));
12250 constraint (Rn
> 7 || Rm
> 7,
12253 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12254 inst
.instruction
|= Rn
;
12255 inst
.instruction
|= Rm
<< 3;
12264 if (do_vfp_nsyn_mrs () == SUCCESS
)
12267 Rd
= inst
.operands
[0].reg
;
12268 reject_bad_reg (Rd
);
12269 inst
.instruction
|= Rd
<< 8;
12271 if (inst
.operands
[1].isreg
)
12273 unsigned br
= inst
.operands
[1].reg
;
12274 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12275 as_bad (_("bad register for mrs"));
12277 inst
.instruction
|= br
& (0xf << 16);
12278 inst
.instruction
|= (br
& 0x300) >> 4;
12279 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12283 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12285 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12287 /* PR gas/12698: The constraint is only applied for m_profile.
12288 If the user has specified -march=all, we want to ignore it as
12289 we are building for any CPU type, including non-m variants. */
12290 bfd_boolean m_profile
=
12291 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12292 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12293 "not support requested special purpose register"));
12296 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12298 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12299 _("'APSR', 'CPSR' or 'SPSR' expected"));
12301 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12302 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12303 inst
.instruction
|= 0xf0000;
12313 if (do_vfp_nsyn_msr () == SUCCESS
)
12316 constraint (!inst
.operands
[1].isreg
,
12317 _("Thumb encoding does not support an immediate here"));
12319 if (inst
.operands
[0].isreg
)
12320 flags
= (int)(inst
.operands
[0].reg
);
12322 flags
= inst
.operands
[0].imm
;
12324 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12326 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12328 /* PR gas/12698: The constraint is only applied for m_profile.
12329 If the user has specified -march=all, we want to ignore it as
12330 we are building for any CPU type, including non-m variants. */
12331 bfd_boolean m_profile
=
12332 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12333 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12334 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12335 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12336 && bits
!= PSR_f
)) && m_profile
,
12337 _("selected processor does not support requested special "
12338 "purpose register"));
12341 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12342 "requested special purpose register"));
12344 Rn
= inst
.operands
[1].reg
;
12345 reject_bad_reg (Rn
);
12347 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12348 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12349 inst
.instruction
|= (flags
& 0x300) >> 4;
12350 inst
.instruction
|= (flags
& 0xff);
12351 inst
.instruction
|= Rn
<< 16;
12357 bfd_boolean narrow
;
12358 unsigned Rd
, Rn
, Rm
;
12360 if (!inst
.operands
[2].present
)
12361 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12363 Rd
= inst
.operands
[0].reg
;
12364 Rn
= inst
.operands
[1].reg
;
12365 Rm
= inst
.operands
[2].reg
;
12367 if (unified_syntax
)
12369 if (inst
.size_req
== 4
12375 else if (inst
.instruction
== T_MNEM_muls
)
12376 narrow
= !in_it_block ();
12378 narrow
= in_it_block ();
12382 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12383 constraint (Rn
> 7 || Rm
> 7,
12390 /* 16-bit MULS/Conditional MUL. */
12391 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12392 inst
.instruction
|= Rd
;
12395 inst
.instruction
|= Rm
<< 3;
12397 inst
.instruction
|= Rn
<< 3;
12399 constraint (1, _("dest must overlap one source register"));
12403 constraint (inst
.instruction
!= T_MNEM_mul
,
12404 _("Thumb-2 MUL must not set flags"));
12406 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12407 inst
.instruction
|= Rd
<< 8;
12408 inst
.instruction
|= Rn
<< 16;
12409 inst
.instruction
|= Rm
<< 0;
12411 reject_bad_reg (Rd
);
12412 reject_bad_reg (Rn
);
12413 reject_bad_reg (Rm
);
12420 unsigned RdLo
, RdHi
, Rn
, Rm
;
12422 RdLo
= inst
.operands
[0].reg
;
12423 RdHi
= inst
.operands
[1].reg
;
12424 Rn
= inst
.operands
[2].reg
;
12425 Rm
= inst
.operands
[3].reg
;
12427 reject_bad_reg (RdLo
);
12428 reject_bad_reg (RdHi
);
12429 reject_bad_reg (Rn
);
12430 reject_bad_reg (Rm
);
12432 inst
.instruction
|= RdLo
<< 12;
12433 inst
.instruction
|= RdHi
<< 8;
12434 inst
.instruction
|= Rn
<< 16;
12435 inst
.instruction
|= Rm
;
12438 as_tsktsk (_("rdhi and rdlo must be different"));
12444 set_it_insn_type (NEUTRAL_IT_INSN
);
12446 if (unified_syntax
)
12448 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12451 inst
.instruction
|= inst
.operands
[0].imm
;
12455 /* PR9722: Check for Thumb2 availability before
12456 generating a thumb2 nop instruction. */
12457 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12459 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12460 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12463 inst
.instruction
= 0x46c0;
12468 constraint (inst
.operands
[0].present
,
12469 _("Thumb does not support NOP with hints"));
12470 inst
.instruction
= 0x46c0;
12477 if (unified_syntax
)
12479 bfd_boolean narrow
;
12481 if (THUMB_SETS_FLAGS (inst
.instruction
))
12482 narrow
= !in_it_block ();
12484 narrow
= in_it_block ();
12485 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12487 if (inst
.size_req
== 4)
12492 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12493 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12498 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12499 inst
.instruction
|= inst
.operands
[0].reg
;
12500 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12505 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12507 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12509 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12510 inst
.instruction
|= inst
.operands
[0].reg
;
12511 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12520 Rd
= inst
.operands
[0].reg
;
12521 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12523 reject_bad_reg (Rd
);
12524 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12525 reject_bad_reg (Rn
);
12527 inst
.instruction
|= Rd
<< 8;
12528 inst
.instruction
|= Rn
<< 16;
12530 if (!inst
.operands
[2].isreg
)
12532 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12533 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12539 Rm
= inst
.operands
[2].reg
;
12540 reject_bad_reg (Rm
);
12542 constraint (inst
.operands
[2].shifted
12543 && inst
.operands
[2].immisreg
,
12544 _("shift must be constant"));
12545 encode_thumb32_shifted_operand (2);
12552 unsigned Rd
, Rn
, Rm
;
12554 Rd
= inst
.operands
[0].reg
;
12555 Rn
= inst
.operands
[1].reg
;
12556 Rm
= inst
.operands
[2].reg
;
12558 reject_bad_reg (Rd
);
12559 reject_bad_reg (Rn
);
12560 reject_bad_reg (Rm
);
12562 inst
.instruction
|= Rd
<< 8;
12563 inst
.instruction
|= Rn
<< 16;
12564 inst
.instruction
|= Rm
;
12565 if (inst
.operands
[3].present
)
12567 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12568 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12569 _("expression too complex"));
12570 inst
.instruction
|= (val
& 0x1c) << 10;
12571 inst
.instruction
|= (val
& 0x03) << 6;
12578 if (!inst
.operands
[3].present
)
12582 inst
.instruction
&= ~0x00000020;
12584 /* PR 10168. Swap the Rm and Rn registers. */
12585 Rtmp
= inst
.operands
[1].reg
;
12586 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12587 inst
.operands
[2].reg
= Rtmp
;
12595 if (inst
.operands
[0].immisreg
)
12596 reject_bad_reg (inst
.operands
[0].imm
);
12598 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12602 do_t_push_pop (void)
12606 constraint (inst
.operands
[0].writeback
,
12607 _("push/pop do not support {reglist}^"));
12608 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12609 _("expression too complex"));
12611 mask
= inst
.operands
[0].imm
;
12612 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12613 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12614 else if (inst
.size_req
!= 4
12615 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12616 ? REG_LR
: REG_PC
)))
12618 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12619 inst
.instruction
|= THUMB_PP_PC_LR
;
12620 inst
.instruction
|= mask
& 0xff;
12622 else if (unified_syntax
)
12624 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12625 encode_thumb2_ldmstm (13, mask
, TRUE
);
12629 inst
.error
= _("invalid register list to push/pop instruction");
12639 Rd
= inst
.operands
[0].reg
;
12640 Rm
= inst
.operands
[1].reg
;
12642 reject_bad_reg (Rd
);
12643 reject_bad_reg (Rm
);
12645 inst
.instruction
|= Rd
<< 8;
12646 inst
.instruction
|= Rm
<< 16;
12647 inst
.instruction
|= Rm
;
12655 Rd
= inst
.operands
[0].reg
;
12656 Rm
= inst
.operands
[1].reg
;
12658 reject_bad_reg (Rd
);
12659 reject_bad_reg (Rm
);
12661 if (Rd
<= 7 && Rm
<= 7
12662 && inst
.size_req
!= 4)
12664 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12665 inst
.instruction
|= Rd
;
12666 inst
.instruction
|= Rm
<< 3;
12668 else if (unified_syntax
)
12670 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12671 inst
.instruction
|= Rd
<< 8;
12672 inst
.instruction
|= Rm
<< 16;
12673 inst
.instruction
|= Rm
;
12676 inst
.error
= BAD_HIREG
;
12684 Rd
= inst
.operands
[0].reg
;
12685 Rm
= inst
.operands
[1].reg
;
12687 reject_bad_reg (Rd
);
12688 reject_bad_reg (Rm
);
12690 inst
.instruction
|= Rd
<< 8;
12691 inst
.instruction
|= Rm
;
12699 Rd
= inst
.operands
[0].reg
;
12700 Rs
= (inst
.operands
[1].present
12701 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12702 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12704 reject_bad_reg (Rd
);
12705 reject_bad_reg (Rs
);
12706 if (inst
.operands
[2].isreg
)
12707 reject_bad_reg (inst
.operands
[2].reg
);
12709 inst
.instruction
|= Rd
<< 8;
12710 inst
.instruction
|= Rs
<< 16;
12711 if (!inst
.operands
[2].isreg
)
12713 bfd_boolean narrow
;
12715 if ((inst
.instruction
& 0x00100000) != 0)
12716 narrow
= !in_it_block ();
12718 narrow
= in_it_block ();
12720 if (Rd
> 7 || Rs
> 7)
12723 if (inst
.size_req
== 4 || !unified_syntax
)
12726 if (inst
.reloc
.exp
.X_op
!= O_constant
12727 || inst
.reloc
.exp
.X_add_number
!= 0)
12730 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12731 relaxation, but it doesn't seem worth the hassle. */
12734 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12735 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12736 inst
.instruction
|= Rs
<< 3;
12737 inst
.instruction
|= Rd
;
12741 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12742 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12746 encode_thumb32_shifted_operand (2);
12752 if (warn_on_deprecated
12753 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12754 as_tsktsk (_("setend use is deprecated for ARMv8"));
12756 set_it_insn_type (OUTSIDE_IT_INSN
);
12757 if (inst
.operands
[0].imm
)
12758 inst
.instruction
|= 0x8;
12764 if (!inst
.operands
[1].present
)
12765 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12767 if (unified_syntax
)
12769 bfd_boolean narrow
;
12772 switch (inst
.instruction
)
12775 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12777 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12779 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12781 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12785 if (THUMB_SETS_FLAGS (inst
.instruction
))
12786 narrow
= !in_it_block ();
12788 narrow
= in_it_block ();
12789 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12791 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12793 if (inst
.operands
[2].isreg
12794 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12795 || inst
.operands
[2].reg
> 7))
12797 if (inst
.size_req
== 4)
12800 reject_bad_reg (inst
.operands
[0].reg
);
12801 reject_bad_reg (inst
.operands
[1].reg
);
12805 if (inst
.operands
[2].isreg
)
12807 reject_bad_reg (inst
.operands
[2].reg
);
12808 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12809 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12811 inst
.instruction
|= inst
.operands
[2].reg
;
12813 /* PR 12854: Error on extraneous shifts. */
12814 constraint (inst
.operands
[2].shifted
,
12815 _("extraneous shift as part of operand to shift insn"));
12819 inst
.operands
[1].shifted
= 1;
12820 inst
.operands
[1].shift_kind
= shift_kind
;
12821 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12822 ? T_MNEM_movs
: T_MNEM_mov
);
12823 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12824 encode_thumb32_shifted_operand (1);
12825 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12826 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12831 if (inst
.operands
[2].isreg
)
12833 switch (shift_kind
)
12835 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12836 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12837 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12838 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12842 inst
.instruction
|= inst
.operands
[0].reg
;
12843 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12845 /* PR 12854: Error on extraneous shifts. */
12846 constraint (inst
.operands
[2].shifted
,
12847 _("extraneous shift as part of operand to shift insn"));
12851 switch (shift_kind
)
12853 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12854 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12855 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12858 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12859 inst
.instruction
|= inst
.operands
[0].reg
;
12860 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12866 constraint (inst
.operands
[0].reg
> 7
12867 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12868 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12870 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12872 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12873 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12874 _("source1 and dest must be same register"));
12876 switch (inst
.instruction
)
12878 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12879 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12880 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12881 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12885 inst
.instruction
|= inst
.operands
[0].reg
;
12886 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12888 /* PR 12854: Error on extraneous shifts. */
12889 constraint (inst
.operands
[2].shifted
,
12890 _("extraneous shift as part of operand to shift insn"));
12894 switch (inst
.instruction
)
12896 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12897 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12898 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12899 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12902 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12903 inst
.instruction
|= inst
.operands
[0].reg
;
12904 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12912 unsigned Rd
, Rn
, Rm
;
12914 Rd
= inst
.operands
[0].reg
;
12915 Rn
= inst
.operands
[1].reg
;
12916 Rm
= inst
.operands
[2].reg
;
12918 reject_bad_reg (Rd
);
12919 reject_bad_reg (Rn
);
12920 reject_bad_reg (Rm
);
12922 inst
.instruction
|= Rd
<< 8;
12923 inst
.instruction
|= Rn
<< 16;
12924 inst
.instruction
|= Rm
;
12930 unsigned Rd
, Rn
, Rm
;
12932 Rd
= inst
.operands
[0].reg
;
12933 Rm
= inst
.operands
[1].reg
;
12934 Rn
= inst
.operands
[2].reg
;
12936 reject_bad_reg (Rd
);
12937 reject_bad_reg (Rn
);
12938 reject_bad_reg (Rm
);
12940 inst
.instruction
|= Rd
<< 8;
12941 inst
.instruction
|= Rn
<< 16;
12942 inst
.instruction
|= Rm
;
12948 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12950 _("SMC is not permitted on this architecture"));
12951 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12952 _("expression too complex"));
12953 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12954 inst
.instruction
|= (value
& 0xf000) >> 12;
12955 inst
.instruction
|= (value
& 0x0ff0);
12956 inst
.instruction
|= (value
& 0x000f) << 16;
12957 /* PR gas/15623: SMC instructions must be last in an IT block. */
12958 set_it_insn_type_last ();
12964 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12966 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12967 inst
.instruction
|= (value
& 0x0fff);
12968 inst
.instruction
|= (value
& 0xf000) << 4;
12972 do_t_ssat_usat (int bias
)
12976 Rd
= inst
.operands
[0].reg
;
12977 Rn
= inst
.operands
[2].reg
;
12979 reject_bad_reg (Rd
);
12980 reject_bad_reg (Rn
);
12982 inst
.instruction
|= Rd
<< 8;
12983 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12984 inst
.instruction
|= Rn
<< 16;
12986 if (inst
.operands
[3].present
)
12988 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12990 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12992 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12993 _("expression too complex"));
12995 if (shift_amount
!= 0)
12997 constraint (shift_amount
> 31,
12998 _("shift expression is too large"));
13000 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13001 inst
.instruction
|= 0x00200000; /* sh bit. */
13003 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13004 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13012 do_t_ssat_usat (1);
13020 Rd
= inst
.operands
[0].reg
;
13021 Rn
= inst
.operands
[2].reg
;
13023 reject_bad_reg (Rd
);
13024 reject_bad_reg (Rn
);
13026 inst
.instruction
|= Rd
<< 8;
13027 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13028 inst
.instruction
|= Rn
<< 16;
13034 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13035 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13036 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13037 || inst
.operands
[2].negative
,
13040 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13042 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13043 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13044 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13045 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13051 if (!inst
.operands
[2].present
)
13052 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13054 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13055 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13056 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13059 inst
.instruction
|= inst
.operands
[0].reg
;
13060 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13061 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13062 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13068 unsigned Rd
, Rn
, Rm
;
13070 Rd
= inst
.operands
[0].reg
;
13071 Rn
= inst
.operands
[1].reg
;
13072 Rm
= inst
.operands
[2].reg
;
13074 reject_bad_reg (Rd
);
13075 reject_bad_reg (Rn
);
13076 reject_bad_reg (Rm
);
13078 inst
.instruction
|= Rd
<< 8;
13079 inst
.instruction
|= Rn
<< 16;
13080 inst
.instruction
|= Rm
;
13081 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13089 Rd
= inst
.operands
[0].reg
;
13090 Rm
= inst
.operands
[1].reg
;
13092 reject_bad_reg (Rd
);
13093 reject_bad_reg (Rm
);
13095 if (inst
.instruction
<= 0xffff
13096 && inst
.size_req
!= 4
13097 && Rd
<= 7 && Rm
<= 7
13098 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13100 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13101 inst
.instruction
|= Rd
;
13102 inst
.instruction
|= Rm
<< 3;
13104 else if (unified_syntax
)
13106 if (inst
.instruction
<= 0xffff)
13107 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13108 inst
.instruction
|= Rd
<< 8;
13109 inst
.instruction
|= Rm
;
13110 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13114 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13115 _("Thumb encoding does not support rotation"));
13116 constraint (1, BAD_HIREG
);
13123 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13132 half
= (inst
.instruction
& 0x10) != 0;
13133 set_it_insn_type_last ();
13134 constraint (inst
.operands
[0].immisreg
,
13135 _("instruction requires register index"));
13137 Rn
= inst
.operands
[0].reg
;
13138 Rm
= inst
.operands
[0].imm
;
13140 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13141 constraint (Rn
== REG_SP
, BAD_SP
);
13142 reject_bad_reg (Rm
);
13144 constraint (!half
&& inst
.operands
[0].shifted
,
13145 _("instruction does not allow shifted index"));
13146 inst
.instruction
|= (Rn
<< 16) | Rm
;
13152 if (!inst
.operands
[0].present
)
13153 inst
.operands
[0].imm
= 0;
13155 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13157 constraint (inst
.size_req
== 2,
13158 _("immediate value out of range"));
13159 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13160 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13161 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13165 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13166 inst
.instruction
|= inst
.operands
[0].imm
;
13169 set_it_insn_type (NEUTRAL_IT_INSN
);
13176 do_t_ssat_usat (0);
13184 Rd
= inst
.operands
[0].reg
;
13185 Rn
= inst
.operands
[2].reg
;
13187 reject_bad_reg (Rd
);
13188 reject_bad_reg (Rn
);
13190 inst
.instruction
|= Rd
<< 8;
13191 inst
.instruction
|= inst
.operands
[1].imm
;
13192 inst
.instruction
|= Rn
<< 16;
13195 /* Neon instruction encoder helpers. */
13197 /* Encodings for the different types for various Neon opcodes. */
13199 /* An "invalid" code for the following tables. */
13202 struct neon_tab_entry
13205 unsigned float_or_poly
;
13206 unsigned scalar_or_imm
;
13209 /* Map overloaded Neon opcodes to their respective encodings. */
13210 #define NEON_ENC_TAB \
13211 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13212 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13213 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13214 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13215 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13216 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13217 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13218 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13219 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13220 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13221 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13222 /* Register variants of the following two instructions are encoded as
13223 vcge / vcgt with the operands reversed. */ \
13224 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13225 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13226 X(vfma, N_INV, 0x0000c10, N_INV), \
13227 X(vfms, N_INV, 0x0200c10, N_INV), \
13228 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13229 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13230 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13231 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13232 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13233 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13234 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13235 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13236 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13237 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13238 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13239 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13240 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13241 X(vshl, 0x0000400, N_INV, 0x0800510), \
13242 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13243 X(vand, 0x0000110, N_INV, 0x0800030), \
13244 X(vbic, 0x0100110, N_INV, 0x0800030), \
13245 X(veor, 0x1000110, N_INV, N_INV), \
13246 X(vorn, 0x0300110, N_INV, 0x0800010), \
13247 X(vorr, 0x0200110, N_INV, 0x0800010), \
13248 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13249 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13250 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13251 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13252 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13253 X(vst1, 0x0000000, 0x0800000, N_INV), \
13254 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13255 X(vst2, 0x0000100, 0x0800100, N_INV), \
13256 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13257 X(vst3, 0x0000200, 0x0800200, N_INV), \
13258 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13259 X(vst4, 0x0000300, 0x0800300, N_INV), \
13260 X(vmovn, 0x1b20200, N_INV, N_INV), \
13261 X(vtrn, 0x1b20080, N_INV, N_INV), \
13262 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13263 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13264 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13265 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13266 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13267 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13268 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13269 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13270 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13271 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13272 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13273 X(vseleq, 0xe000a00, N_INV, N_INV), \
13274 X(vselvs, 0xe100a00, N_INV, N_INV), \
13275 X(vselge, 0xe200a00, N_INV, N_INV), \
13276 X(vselgt, 0xe300a00, N_INV, N_INV), \
13277 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13278 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13279 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13280 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13281 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13282 X(aes, 0x3b00300, N_INV, N_INV), \
13283 X(sha3op, 0x2000c00, N_INV, N_INV), \
13284 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13285 X(sha2op, 0x3ba0380, N_INV, N_INV)
13289 #define X(OPC,I,F,S) N_MNEM_##OPC
13294 static const struct neon_tab_entry neon_enc_tab
[] =
13296 #define X(OPC,I,F,S) { (I), (F), (S) }
13301 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13302 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13303 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13304 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13305 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13306 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13307 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13308 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13309 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13310 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13311 #define NEON_ENC_SINGLE_(X) \
13312 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13313 #define NEON_ENC_DOUBLE_(X) \
13314 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13315 #define NEON_ENC_FPV8_(X) \
13316 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13318 #define NEON_ENCODE(type, inst) \
13321 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13322 inst.is_neon = 1; \
13326 #define check_neon_suffixes \
13329 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13331 as_bad (_("invalid neon suffix for non neon instruction")); \
13337 /* Define shapes for instruction operands. The following mnemonic characters
13338 are used in this table:
13340 F - VFP S<n> register
13341 D - Neon D<n> register
13342 Q - Neon Q<n> register
13346 L - D<n> register list
13348 This table is used to generate various data:
13349 - enumerations of the form NS_DDR to be used as arguments to
13351 - a table classifying shapes into single, double, quad, mixed.
13352 - a table used to drive neon_select_shape. */
13354 #define NEON_SHAPE_DEF \
13355 X(3, (D, D, D), DOUBLE), \
13356 X(3, (Q, Q, Q), QUAD), \
13357 X(3, (D, D, I), DOUBLE), \
13358 X(3, (Q, Q, I), QUAD), \
13359 X(3, (D, D, S), DOUBLE), \
13360 X(3, (Q, Q, S), QUAD), \
13361 X(2, (D, D), DOUBLE), \
13362 X(2, (Q, Q), QUAD), \
13363 X(2, (D, S), DOUBLE), \
13364 X(2, (Q, S), QUAD), \
13365 X(2, (D, R), DOUBLE), \
13366 X(2, (Q, R), QUAD), \
13367 X(2, (D, I), DOUBLE), \
13368 X(2, (Q, I), QUAD), \
13369 X(3, (D, L, D), DOUBLE), \
13370 X(2, (D, Q), MIXED), \
13371 X(2, (Q, D), MIXED), \
13372 X(3, (D, Q, I), MIXED), \
13373 X(3, (Q, D, I), MIXED), \
13374 X(3, (Q, D, D), MIXED), \
13375 X(3, (D, Q, Q), MIXED), \
13376 X(3, (Q, Q, D), MIXED), \
13377 X(3, (Q, D, S), MIXED), \
13378 X(3, (D, Q, S), MIXED), \
13379 X(4, (D, D, D, I), DOUBLE), \
13380 X(4, (Q, Q, Q, I), QUAD), \
13381 X(4, (D, D, S, I), DOUBLE), \
13382 X(4, (Q, Q, S, I), QUAD), \
13383 X(2, (F, F), SINGLE), \
13384 X(3, (F, F, F), SINGLE), \
13385 X(2, (F, I), SINGLE), \
13386 X(2, (F, D), MIXED), \
13387 X(2, (D, F), MIXED), \
13388 X(3, (F, F, I), MIXED), \
13389 X(4, (R, R, F, F), SINGLE), \
13390 X(4, (F, F, R, R), SINGLE), \
13391 X(3, (D, R, R), DOUBLE), \
13392 X(3, (R, R, D), DOUBLE), \
13393 X(2, (S, R), SINGLE), \
13394 X(2, (R, S), SINGLE), \
13395 X(2, (F, R), SINGLE), \
13396 X(2, (R, F), SINGLE), \
13397 /* Half float shape supported so far. */\
13398 X (2, (H, D), MIXED), \
13399 X (2, (D, H), MIXED), \
13400 X (2, (H, F), MIXED), \
13401 X (2, (F, H), MIXED), \
13402 X (2, (H, H), HALF), \
13403 X (2, (H, R), HALF), \
13404 X (2, (R, H), HALF), \
13405 X (2, (H, I), HALF), \
13406 X (3, (H, H, H), HALF), \
13407 X (3, (H, F, I), MIXED), \
13408 X (3, (F, H, I), MIXED)
13410 #define S2(A,B) NS_##A##B
13411 #define S3(A,B,C) NS_##A##B##C
13412 #define S4(A,B,C,D) NS_##A##B##C##D
13414 #define X(N, L, C) S##N L
13427 enum neon_shape_class
13436 #define X(N, L, C) SC_##C
13438 static enum neon_shape_class neon_shape_class
[] =
13457 /* Register widths of above. */
13458 static unsigned neon_shape_el_size
[] =
13470 struct neon_shape_info
13473 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13476 #define S2(A,B) { SE_##A, SE_##B }
13477 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13478 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13480 #define X(N, L, C) { N, S##N L }
13482 static struct neon_shape_info neon_shape_tab
[] =
13492 /* Bit masks used in type checking given instructions.
13493 'N_EQK' means the type must be the same as (or based on in some way) the key
13494 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13495 set, various other bits can be set as well in order to modify the meaning of
13496 the type constraint. */
13498 enum neon_type_mask
13522 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13523 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13524 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13525 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13526 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13527 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13528 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13529 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13530 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13531 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13532 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13534 N_MAX_NONSPECIAL
= N_P64
13537 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13539 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13540 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13541 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13542 #define N_S_32 (N_S8 | N_S16 | N_S32)
13543 #define N_F_16_32 (N_F16 | N_F32)
13544 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13545 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13546 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13547 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13549 /* Pass this as the first type argument to neon_check_type to ignore types
13551 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13553 /* Select a "shape" for the current instruction (describing register types or
13554 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13555 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13556 function of operand parsing, so this function doesn't need to be called.
13557 Shapes should be listed in order of decreasing length. */
13559 static enum neon_shape
13560 neon_select_shape (enum neon_shape shape
, ...)
13563 enum neon_shape first_shape
= shape
;
13565 /* Fix missing optional operands. FIXME: we don't know at this point how
13566 many arguments we should have, so this makes the assumption that we have
13567 > 1. This is true of all current Neon opcodes, I think, but may not be
13568 true in the future. */
13569 if (!inst
.operands
[1].present
)
13570 inst
.operands
[1] = inst
.operands
[0];
13572 va_start (ap
, shape
);
13574 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13579 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13581 if (!inst
.operands
[j
].present
)
13587 switch (neon_shape_tab
[shape
].el
[j
])
13589 /* If a .f16, .16, .u16, .s16 type specifier is given over
13590 a VFP single precision register operand, it's essentially
13591 means only half of the register is used.
13593 If the type specifier is given after the mnemonics, the
13594 information is stored in inst.vectype. If the type specifier
13595 is given after register operand, the information is stored
13596 in inst.operands[].vectype.
13598 When there is only one type specifier, and all the register
13599 operands are the same type of hardware register, the type
13600 specifier applies to all register operands.
13602 If no type specifier is given, the shape is inferred from
13603 operand information.
13606 vadd.f16 s0, s1, s2: NS_HHH
13607 vabs.f16 s0, s1: NS_HH
13608 vmov.f16 s0, r1: NS_HR
13609 vmov.f16 r0, s1: NS_RH
13610 vcvt.f16 r0, s1: NS_RH
13611 vcvt.f16.s32 s2, s2, #29: NS_HFI
13612 vcvt.f16.s32 s2, s2: NS_HF
13615 if (!(inst
.operands
[j
].isreg
13616 && inst
.operands
[j
].isvec
13617 && inst
.operands
[j
].issingle
13618 && !inst
.operands
[j
].isquad
13619 && ((inst
.vectype
.elems
== 1
13620 && inst
.vectype
.el
[0].size
== 16)
13621 || (inst
.vectype
.elems
> 1
13622 && inst
.vectype
.el
[j
].size
== 16)
13623 || (inst
.vectype
.elems
== 0
13624 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13625 && inst
.operands
[j
].vectype
.size
== 16))))
13630 if (!(inst
.operands
[j
].isreg
13631 && inst
.operands
[j
].isvec
13632 && inst
.operands
[j
].issingle
13633 && !inst
.operands
[j
].isquad
13634 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13635 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13636 || (inst
.vectype
.elems
== 0
13637 && (inst
.operands
[j
].vectype
.size
== 32
13638 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13643 if (!(inst
.operands
[j
].isreg
13644 && inst
.operands
[j
].isvec
13645 && !inst
.operands
[j
].isquad
13646 && !inst
.operands
[j
].issingle
))
13651 if (!(inst
.operands
[j
].isreg
13652 && !inst
.operands
[j
].isvec
))
13657 if (!(inst
.operands
[j
].isreg
13658 && inst
.operands
[j
].isvec
13659 && inst
.operands
[j
].isquad
13660 && !inst
.operands
[j
].issingle
))
13665 if (!(!inst
.operands
[j
].isreg
13666 && !inst
.operands
[j
].isscalar
))
13671 if (!(!inst
.operands
[j
].isreg
13672 && inst
.operands
[j
].isscalar
))
13682 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13683 /* We've matched all the entries in the shape table, and we don't
13684 have any left over operands which have not been matched. */
13690 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13691 first_error (_("invalid instruction shape"));
13696 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13697 means the Q bit should be set). */
13700 neon_quad (enum neon_shape shape
)
13702 return neon_shape_class
[shape
] == SC_QUAD
;
13706 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13709 /* Allow modification to be made to types which are constrained to be
13710 based on the key element, based on bits set alongside N_EQK. */
13711 if ((typebits
& N_EQK
) != 0)
13713 if ((typebits
& N_HLF
) != 0)
13715 else if ((typebits
& N_DBL
) != 0)
13717 if ((typebits
& N_SGN
) != 0)
13718 *g_type
= NT_signed
;
13719 else if ((typebits
& N_UNS
) != 0)
13720 *g_type
= NT_unsigned
;
13721 else if ((typebits
& N_INT
) != 0)
13722 *g_type
= NT_integer
;
13723 else if ((typebits
& N_FLT
) != 0)
13724 *g_type
= NT_float
;
13725 else if ((typebits
& N_SIZ
) != 0)
13726 *g_type
= NT_untyped
;
13730 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13731 operand type, i.e. the single type specified in a Neon instruction when it
13732 is the only one given. */
13734 static struct neon_type_el
13735 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13737 struct neon_type_el dest
= *key
;
13739 gas_assert ((thisarg
& N_EQK
) != 0);
13741 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13746 /* Convert Neon type and size into compact bitmask representation. */
13748 static enum neon_type_mask
13749 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13756 case 8: return N_8
;
13757 case 16: return N_16
;
13758 case 32: return N_32
;
13759 case 64: return N_64
;
13767 case 8: return N_I8
;
13768 case 16: return N_I16
;
13769 case 32: return N_I32
;
13770 case 64: return N_I64
;
13778 case 16: return N_F16
;
13779 case 32: return N_F32
;
13780 case 64: return N_F64
;
13788 case 8: return N_P8
;
13789 case 16: return N_P16
;
13790 case 64: return N_P64
;
13798 case 8: return N_S8
;
13799 case 16: return N_S16
;
13800 case 32: return N_S32
;
13801 case 64: return N_S64
;
13809 case 8: return N_U8
;
13810 case 16: return N_U16
;
13811 case 32: return N_U32
;
13812 case 64: return N_U64
;
13823 /* Convert compact Neon bitmask type representation to a type and size. Only
13824 handles the case where a single bit is set in the mask. */
13827 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13828 enum neon_type_mask mask
)
13830 if ((mask
& N_EQK
) != 0)
13833 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13835 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13837 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13839 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13844 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13846 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13847 *type
= NT_unsigned
;
13848 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13849 *type
= NT_integer
;
13850 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13851 *type
= NT_untyped
;
13852 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13854 else if ((mask
& (N_F_ALL
)) != 0)
13862 /* Modify a bitmask of allowed types. This is only needed for type
13866 modify_types_allowed (unsigned allowed
, unsigned mods
)
13869 enum neon_el_type type
;
13875 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13877 if (el_type_of_type_chk (&type
, &size
,
13878 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13880 neon_modify_type_size (mods
, &type
, &size
);
13881 destmask
|= type_chk_of_el_type (type
, size
);
13888 /* Check type and return type classification.
13889 The manual states (paraphrase): If one datatype is given, it indicates the
13891 - the second operand, if there is one
13892 - the operand, if there is no second operand
13893 - the result, if there are no operands.
13894 This isn't quite good enough though, so we use a concept of a "key" datatype
13895 which is set on a per-instruction basis, which is the one which matters when
13896 only one data type is written.
13897 Note: this function has side-effects (e.g. filling in missing operands). All
13898 Neon instructions should call it before performing bit encoding. */
13900 static struct neon_type_el
13901 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13904 unsigned i
, pass
, key_el
= 0;
13905 unsigned types
[NEON_MAX_TYPE_ELS
];
13906 enum neon_el_type k_type
= NT_invtype
;
13907 unsigned k_size
= -1u;
13908 struct neon_type_el badtype
= {NT_invtype
, -1};
13909 unsigned key_allowed
= 0;
13911 /* Optional registers in Neon instructions are always (not) in operand 1.
13912 Fill in the missing operand here, if it was omitted. */
13913 if (els
> 1 && !inst
.operands
[1].present
)
13914 inst
.operands
[1] = inst
.operands
[0];
13916 /* Suck up all the varargs. */
13918 for (i
= 0; i
< els
; i
++)
13920 unsigned thisarg
= va_arg (ap
, unsigned);
13921 if (thisarg
== N_IGNORE_TYPE
)
13926 types
[i
] = thisarg
;
13927 if ((thisarg
& N_KEY
) != 0)
13932 if (inst
.vectype
.elems
> 0)
13933 for (i
= 0; i
< els
; i
++)
13934 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13936 first_error (_("types specified in both the mnemonic and operands"));
13940 /* Duplicate inst.vectype elements here as necessary.
13941 FIXME: No idea if this is exactly the same as the ARM assembler,
13942 particularly when an insn takes one register and one non-register
13944 if (inst
.vectype
.elems
== 1 && els
> 1)
13947 inst
.vectype
.elems
= els
;
13948 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13949 for (j
= 0; j
< els
; j
++)
13951 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13954 else if (inst
.vectype
.elems
== 0 && els
> 0)
13957 /* No types were given after the mnemonic, so look for types specified
13958 after each operand. We allow some flexibility here; as long as the
13959 "key" operand has a type, we can infer the others. */
13960 for (j
= 0; j
< els
; j
++)
13961 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13962 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13964 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13966 for (j
= 0; j
< els
; j
++)
13967 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13968 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13973 first_error (_("operand types can't be inferred"));
13977 else if (inst
.vectype
.elems
!= els
)
13979 first_error (_("type specifier has the wrong number of parts"));
13983 for (pass
= 0; pass
< 2; pass
++)
13985 for (i
= 0; i
< els
; i
++)
13987 unsigned thisarg
= types
[i
];
13988 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13989 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13990 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13991 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13993 /* Decay more-specific signed & unsigned types to sign-insensitive
13994 integer types if sign-specific variants are unavailable. */
13995 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13996 && (types_allowed
& N_SU_ALL
) == 0)
13997 g_type
= NT_integer
;
13999 /* If only untyped args are allowed, decay any more specific types to
14000 them. Some instructions only care about signs for some element
14001 sizes, so handle that properly. */
14002 if (((types_allowed
& N_UNT
) == 0)
14003 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14004 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14005 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14006 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14007 g_type
= NT_untyped
;
14011 if ((thisarg
& N_KEY
) != 0)
14015 key_allowed
= thisarg
& ~N_KEY
;
14017 /* Check architecture constraint on FP16 extension. */
14019 && k_type
== NT_float
14020 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14022 inst
.error
= _(BAD_FP16
);
14029 if ((thisarg
& N_VFP
) != 0)
14031 enum neon_shape_el regshape
;
14032 unsigned regwidth
, match
;
14034 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14037 first_error (_("invalid instruction shape"));
14040 regshape
= neon_shape_tab
[ns
].el
[i
];
14041 regwidth
= neon_shape_el_size
[regshape
];
14043 /* In VFP mode, operands must match register widths. If we
14044 have a key operand, use its width, else use the width of
14045 the current operand. */
14051 /* FP16 will use a single precision register. */
14052 if (regwidth
== 32 && match
== 16)
14054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14058 inst
.error
= _(BAD_FP16
);
14063 if (regwidth
!= match
)
14065 first_error (_("operand size must match register width"));
14070 if ((thisarg
& N_EQK
) == 0)
14072 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14074 if ((given_type
& types_allowed
) == 0)
14076 first_error (_("bad type in Neon instruction"));
14082 enum neon_el_type mod_k_type
= k_type
;
14083 unsigned mod_k_size
= k_size
;
14084 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14085 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14087 first_error (_("inconsistent types in Neon instruction"));
14095 return inst
.vectype
.el
[key_el
];
14098 /* Neon-style VFP instruction forwarding. */
14100 /* Thumb VFP instructions have 0xE in the condition field. */
14103 do_vfp_cond_or_thumb (void)
14108 inst
.instruction
|= 0xe0000000;
14110 inst
.instruction
|= inst
.cond
<< 28;
14113 /* Look up and encode a simple mnemonic, for use as a helper function for the
14114 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14115 etc. It is assumed that operand parsing has already been done, and that the
14116 operands are in the form expected by the given opcode (this isn't necessarily
14117 the same as the form in which they were parsed, hence some massaging must
14118 take place before this function is called).
14119 Checks current arch version against that in the looked-up opcode. */
14122 do_vfp_nsyn_opcode (const char *opname
)
14124 const struct asm_opcode
*opcode
;
14126 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14131 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14132 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14139 inst
.instruction
= opcode
->tvalue
;
14140 opcode
->tencode ();
14144 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14145 opcode
->aencode ();
14150 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14152 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14154 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14157 do_vfp_nsyn_opcode ("fadds");
14159 do_vfp_nsyn_opcode ("fsubs");
14161 /* ARMv8.2 fp16 instruction. */
14163 do_scalar_fp16_v82_encode ();
14168 do_vfp_nsyn_opcode ("faddd");
14170 do_vfp_nsyn_opcode ("fsubd");
14174 /* Check operand types to see if this is a VFP instruction, and if so call
14178 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14180 enum neon_shape rs
;
14181 struct neon_type_el et
;
14186 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14187 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14191 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14192 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14193 N_F_ALL
| N_KEY
| N_VFP
);
14200 if (et
.type
!= NT_invtype
)
14211 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14213 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14215 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14218 do_vfp_nsyn_opcode ("fmacs");
14220 do_vfp_nsyn_opcode ("fnmacs");
14222 /* ARMv8.2 fp16 instruction. */
14224 do_scalar_fp16_v82_encode ();
14229 do_vfp_nsyn_opcode ("fmacd");
14231 do_vfp_nsyn_opcode ("fnmacd");
14236 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14238 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14240 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14243 do_vfp_nsyn_opcode ("ffmas");
14245 do_vfp_nsyn_opcode ("ffnmas");
14247 /* ARMv8.2 fp16 instruction. */
14249 do_scalar_fp16_v82_encode ();
14254 do_vfp_nsyn_opcode ("ffmad");
14256 do_vfp_nsyn_opcode ("ffnmad");
14261 do_vfp_nsyn_mul (enum neon_shape rs
)
14263 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14265 do_vfp_nsyn_opcode ("fmuls");
14267 /* ARMv8.2 fp16 instruction. */
14269 do_scalar_fp16_v82_encode ();
14272 do_vfp_nsyn_opcode ("fmuld");
14276 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14278 int is_neg
= (inst
.instruction
& 0x80) != 0;
14279 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14281 if (rs
== NS_FF
|| rs
== NS_HH
)
14284 do_vfp_nsyn_opcode ("fnegs");
14286 do_vfp_nsyn_opcode ("fabss");
14288 /* ARMv8.2 fp16 instruction. */
14290 do_scalar_fp16_v82_encode ();
14295 do_vfp_nsyn_opcode ("fnegd");
14297 do_vfp_nsyn_opcode ("fabsd");
14301 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14302 insns belong to Neon, and are handled elsewhere. */
14305 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14307 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14311 do_vfp_nsyn_opcode ("fldmdbs");
14313 do_vfp_nsyn_opcode ("fldmias");
14318 do_vfp_nsyn_opcode ("fstmdbs");
14320 do_vfp_nsyn_opcode ("fstmias");
14325 do_vfp_nsyn_sqrt (void)
14327 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14328 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14330 if (rs
== NS_FF
|| rs
== NS_HH
)
14332 do_vfp_nsyn_opcode ("fsqrts");
14334 /* ARMv8.2 fp16 instruction. */
14336 do_scalar_fp16_v82_encode ();
14339 do_vfp_nsyn_opcode ("fsqrtd");
14343 do_vfp_nsyn_div (void)
14345 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14346 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14347 N_F_ALL
| N_KEY
| N_VFP
);
14349 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14351 do_vfp_nsyn_opcode ("fdivs");
14353 /* ARMv8.2 fp16 instruction. */
14355 do_scalar_fp16_v82_encode ();
14358 do_vfp_nsyn_opcode ("fdivd");
14362 do_vfp_nsyn_nmul (void)
14364 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14365 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14366 N_F_ALL
| N_KEY
| N_VFP
);
14368 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14370 NEON_ENCODE (SINGLE
, inst
);
14371 do_vfp_sp_dyadic ();
14373 /* ARMv8.2 fp16 instruction. */
14375 do_scalar_fp16_v82_encode ();
14379 NEON_ENCODE (DOUBLE
, inst
);
14380 do_vfp_dp_rd_rn_rm ();
14382 do_vfp_cond_or_thumb ();
14387 do_vfp_nsyn_cmp (void)
14389 enum neon_shape rs
;
14390 if (inst
.operands
[1].isreg
)
14392 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14393 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14395 if (rs
== NS_FF
|| rs
== NS_HH
)
14397 NEON_ENCODE (SINGLE
, inst
);
14398 do_vfp_sp_monadic ();
14402 NEON_ENCODE (DOUBLE
, inst
);
14403 do_vfp_dp_rd_rm ();
14408 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14409 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14411 switch (inst
.instruction
& 0x0fffffff)
14414 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14417 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14423 if (rs
== NS_FI
|| rs
== NS_HI
)
14425 NEON_ENCODE (SINGLE
, inst
);
14426 do_vfp_sp_compare_z ();
14430 NEON_ENCODE (DOUBLE
, inst
);
14434 do_vfp_cond_or_thumb ();
14436 /* ARMv8.2 fp16 instruction. */
14437 if (rs
== NS_HI
|| rs
== NS_HH
)
14438 do_scalar_fp16_v82_encode ();
14442 nsyn_insert_sp (void)
14444 inst
.operands
[1] = inst
.operands
[0];
14445 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14446 inst
.operands
[0].reg
= REG_SP
;
14447 inst
.operands
[0].isreg
= 1;
14448 inst
.operands
[0].writeback
= 1;
14449 inst
.operands
[0].present
= 1;
14453 do_vfp_nsyn_push (void)
14457 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14458 _("register list must contain at least 1 and at most 16 "
14461 if (inst
.operands
[1].issingle
)
14462 do_vfp_nsyn_opcode ("fstmdbs");
14464 do_vfp_nsyn_opcode ("fstmdbd");
14468 do_vfp_nsyn_pop (void)
14472 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14473 _("register list must contain at least 1 and at most 16 "
14476 if (inst
.operands
[1].issingle
)
14477 do_vfp_nsyn_opcode ("fldmias");
14479 do_vfp_nsyn_opcode ("fldmiad");
14482 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14483 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14486 neon_dp_fixup (struct arm_it
* insn
)
14488 unsigned int i
= insn
->instruction
;
14493 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14504 insn
->instruction
= i
;
14507 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14511 neon_logbits (unsigned x
)
14513 return ffs (x
) - 4;
14516 #define LOW4(R) ((R) & 0xf)
14517 #define HI1(R) (((R) >> 4) & 1)
14519 /* Encode insns with bit pattern:
14521 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14522 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14524 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14525 different meaning for some instruction. */
14528 neon_three_same (int isquad
, int ubit
, int size
)
14530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14534 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14535 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14536 inst
.instruction
|= (isquad
!= 0) << 6;
14537 inst
.instruction
|= (ubit
!= 0) << 24;
14539 inst
.instruction
|= neon_logbits (size
) << 20;
14541 neon_dp_fixup (&inst
);
14544 /* Encode instructions of the form:
14546 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14547 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14549 Don't write size if SIZE == -1. */
14552 neon_two_same (int qbit
, int ubit
, int size
)
14554 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14555 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14556 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14557 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14558 inst
.instruction
|= (qbit
!= 0) << 6;
14559 inst
.instruction
|= (ubit
!= 0) << 24;
14562 inst
.instruction
|= neon_logbits (size
) << 18;
14564 neon_dp_fixup (&inst
);
14567 /* Neon instruction encoders, in approximate order of appearance. */
14570 do_neon_dyadic_i_su (void)
14572 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14573 struct neon_type_el et
= neon_check_type (3, rs
,
14574 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14575 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14579 do_neon_dyadic_i64_su (void)
14581 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14582 struct neon_type_el et
= neon_check_type (3, rs
,
14583 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14584 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14588 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14591 unsigned size
= et
.size
>> 3;
14592 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14593 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14594 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14595 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14596 inst
.instruction
|= (isquad
!= 0) << 6;
14597 inst
.instruction
|= immbits
<< 16;
14598 inst
.instruction
|= (size
>> 3) << 7;
14599 inst
.instruction
|= (size
& 0x7) << 19;
14601 inst
.instruction
|= (uval
!= 0) << 24;
14603 neon_dp_fixup (&inst
);
14607 do_neon_shl_imm (void)
14609 if (!inst
.operands
[2].isreg
)
14611 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14612 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14613 int imm
= inst
.operands
[2].imm
;
14615 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14616 _("immediate out of range for shift"));
14617 NEON_ENCODE (IMMED
, inst
);
14618 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14622 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14623 struct neon_type_el et
= neon_check_type (3, rs
,
14624 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14627 /* VSHL/VQSHL 3-register variants have syntax such as:
14629 whereas other 3-register operations encoded by neon_three_same have
14632 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14634 tmp
= inst
.operands
[2].reg
;
14635 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14636 inst
.operands
[1].reg
= tmp
;
14637 NEON_ENCODE (INTEGER
, inst
);
14638 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14643 do_neon_qshl_imm (void)
14645 if (!inst
.operands
[2].isreg
)
14647 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14648 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14649 int imm
= inst
.operands
[2].imm
;
14651 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14652 _("immediate out of range for shift"));
14653 NEON_ENCODE (IMMED
, inst
);
14654 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14658 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14659 struct neon_type_el et
= neon_check_type (3, rs
,
14660 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14663 /* See note in do_neon_shl_imm. */
14664 tmp
= inst
.operands
[2].reg
;
14665 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14666 inst
.operands
[1].reg
= tmp
;
14667 NEON_ENCODE (INTEGER
, inst
);
14668 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14673 do_neon_rshl (void)
14675 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14676 struct neon_type_el et
= neon_check_type (3, rs
,
14677 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14680 tmp
= inst
.operands
[2].reg
;
14681 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14682 inst
.operands
[1].reg
= tmp
;
14683 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14687 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14689 /* Handle .I8 pseudo-instructions. */
14692 /* Unfortunately, this will make everything apart from zero out-of-range.
14693 FIXME is this the intended semantics? There doesn't seem much point in
14694 accepting .I8 if so. */
14695 immediate
|= immediate
<< 8;
14701 if (immediate
== (immediate
& 0x000000ff))
14703 *immbits
= immediate
;
14706 else if (immediate
== (immediate
& 0x0000ff00))
14708 *immbits
= immediate
>> 8;
14711 else if (immediate
== (immediate
& 0x00ff0000))
14713 *immbits
= immediate
>> 16;
14716 else if (immediate
== (immediate
& 0xff000000))
14718 *immbits
= immediate
>> 24;
14721 if ((immediate
& 0xffff) != (immediate
>> 16))
14722 goto bad_immediate
;
14723 immediate
&= 0xffff;
14726 if (immediate
== (immediate
& 0x000000ff))
14728 *immbits
= immediate
;
14731 else if (immediate
== (immediate
& 0x0000ff00))
14733 *immbits
= immediate
>> 8;
14738 first_error (_("immediate value out of range"));
14743 do_neon_logic (void)
14745 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14747 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14748 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14749 /* U bit and size field were set as part of the bitmask. */
14750 NEON_ENCODE (INTEGER
, inst
);
14751 neon_three_same (neon_quad (rs
), 0, -1);
14755 const int three_ops_form
= (inst
.operands
[2].present
14756 && !inst
.operands
[2].isreg
);
14757 const int immoperand
= (three_ops_form
? 2 : 1);
14758 enum neon_shape rs
= (three_ops_form
14759 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14760 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14761 struct neon_type_el et
= neon_check_type (2, rs
,
14762 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14763 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14767 if (et
.type
== NT_invtype
)
14770 if (three_ops_form
)
14771 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14772 _("first and second operands shall be the same register"));
14774 NEON_ENCODE (IMMED
, inst
);
14776 immbits
= inst
.operands
[immoperand
].imm
;
14779 /* .i64 is a pseudo-op, so the immediate must be a repeating
14781 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14782 inst
.operands
[immoperand
].reg
: 0))
14784 /* Set immbits to an invalid constant. */
14785 immbits
= 0xdeadbeef;
14792 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14796 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14800 /* Pseudo-instruction for VBIC. */
14801 neon_invert_size (&immbits
, 0, et
.size
);
14802 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14806 /* Pseudo-instruction for VORR. */
14807 neon_invert_size (&immbits
, 0, et
.size
);
14808 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14818 inst
.instruction
|= neon_quad (rs
) << 6;
14819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14821 inst
.instruction
|= cmode
<< 8;
14822 neon_write_immbits (immbits
);
14824 neon_dp_fixup (&inst
);
14829 do_neon_bitfield (void)
14831 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14832 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14833 neon_three_same (neon_quad (rs
), 0, -1);
14837 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14840 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14841 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14843 if (et
.type
== NT_float
)
14845 NEON_ENCODE (FLOAT
, inst
);
14846 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14850 NEON_ENCODE (INTEGER
, inst
);
14851 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14856 do_neon_dyadic_if_su (void)
14858 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14862 do_neon_dyadic_if_su_d (void)
14864 /* This version only allow D registers, but that constraint is enforced during
14865 operand parsing so we don't need to do anything extra here. */
14866 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14870 do_neon_dyadic_if_i_d (void)
14872 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14873 affected if we specify unsigned args. */
14874 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14877 enum vfp_or_neon_is_neon_bits
14880 NEON_CHECK_ARCH
= 2,
14881 NEON_CHECK_ARCH8
= 4
14884 /* Call this function if an instruction which may have belonged to the VFP or
14885 Neon instruction sets, but turned out to be a Neon instruction (due to the
14886 operand types involved, etc.). We have to check and/or fix-up a couple of
14889 - Make sure the user hasn't attempted to make a Neon instruction
14891 - Alter the value in the condition code field if necessary.
14892 - Make sure that the arch supports Neon instructions.
14894 Which of these operations take place depends on bits from enum
14895 vfp_or_neon_is_neon_bits.
14897 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14898 current instruction's condition is COND_ALWAYS, the condition field is
14899 changed to inst.uncond_value. This is necessary because instructions shared
14900 between VFP and Neon may be conditional for the VFP variants only, and the
14901 unconditional Neon version must have, e.g., 0xF in the condition field. */
14904 vfp_or_neon_is_neon (unsigned check
)
14906 /* Conditions are always legal in Thumb mode (IT blocks). */
14907 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14909 if (inst
.cond
!= COND_ALWAYS
)
14911 first_error (_(BAD_COND
));
14914 if (inst
.uncond_value
!= -1)
14915 inst
.instruction
|= inst
.uncond_value
<< 28;
14918 if ((check
& NEON_CHECK_ARCH
)
14919 && !mark_feature_used (&fpu_neon_ext_v1
))
14921 first_error (_(BAD_FPU
));
14925 if ((check
& NEON_CHECK_ARCH8
)
14926 && !mark_feature_used (&fpu_neon_ext_armv8
))
14928 first_error (_(BAD_FPU
));
14936 do_neon_addsub_if_i (void)
14938 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14941 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14944 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14945 affected if we specify unsigned args. */
14946 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14949 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14951 V<op> A,B (A is operand 0, B is operand 2)
14956 so handle that case specially. */
14959 neon_exchange_operands (void)
14961 if (inst
.operands
[1].present
)
14963 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14965 /* Swap operands[1] and operands[2]. */
14966 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14967 inst
.operands
[1] = inst
.operands
[2];
14968 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14973 inst
.operands
[1] = inst
.operands
[2];
14974 inst
.operands
[2] = inst
.operands
[0];
14979 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14981 if (inst
.operands
[2].isreg
)
14984 neon_exchange_operands ();
14985 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14989 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14990 struct neon_type_el et
= neon_check_type (2, rs
,
14991 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14993 NEON_ENCODE (IMMED
, inst
);
14994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14995 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14996 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14997 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14998 inst
.instruction
|= neon_quad (rs
) << 6;
14999 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15000 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15002 neon_dp_fixup (&inst
);
15009 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15013 do_neon_cmp_inv (void)
15015 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15021 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15024 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15025 scalars, which are encoded in 5 bits, M : Rm.
15026 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15027 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15030 Dot Product instructions are similar to multiply instructions except elsize
15031 should always be 32.
15033 This function translates SCALAR, which is GAS's internal encoding of indexed
15034 scalar register, to raw encoding. There is also register and index range
15035 check based on ELSIZE. */
15038 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15040 unsigned regno
= NEON_SCALAR_REG (scalar
);
15041 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15046 if (regno
> 7 || elno
> 3)
15048 return regno
| (elno
<< 3);
15051 if (regno
> 15 || elno
> 1)
15053 return regno
| (elno
<< 4);
15057 first_error (_("scalar out of range for multiply instruction"));
15063 /* Encode multiply / multiply-accumulate scalar instructions. */
15066 neon_mul_mac (struct neon_type_el et
, int ubit
)
15070 /* Give a more helpful error message if we have an invalid type. */
15071 if (et
.type
== NT_invtype
)
15074 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15075 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15076 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15078 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15079 inst
.instruction
|= LOW4 (scalar
);
15080 inst
.instruction
|= HI1 (scalar
) << 5;
15081 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15082 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15083 inst
.instruction
|= (ubit
!= 0) << 24;
15085 neon_dp_fixup (&inst
);
15089 do_neon_mac_maybe_scalar (void)
15091 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15094 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15097 if (inst
.operands
[2].isscalar
)
15099 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15100 struct neon_type_el et
= neon_check_type (3, rs
,
15101 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15102 NEON_ENCODE (SCALAR
, inst
);
15103 neon_mul_mac (et
, neon_quad (rs
));
15107 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15108 affected if we specify unsigned args. */
15109 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15114 do_neon_fmac (void)
15116 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15119 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15122 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15128 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15129 struct neon_type_el et
= neon_check_type (3, rs
,
15130 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15131 neon_three_same (neon_quad (rs
), 0, et
.size
);
15134 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15135 same types as the MAC equivalents. The polynomial type for this instruction
15136 is encoded the same as the integer type. */
15141 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15144 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15147 if (inst
.operands
[2].isscalar
)
15148 do_neon_mac_maybe_scalar ();
15150 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15154 do_neon_qdmulh (void)
15156 if (inst
.operands
[2].isscalar
)
15158 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15159 struct neon_type_el et
= neon_check_type (3, rs
,
15160 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15161 NEON_ENCODE (SCALAR
, inst
);
15162 neon_mul_mac (et
, neon_quad (rs
));
15166 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15167 struct neon_type_el et
= neon_check_type (3, rs
,
15168 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15169 NEON_ENCODE (INTEGER
, inst
);
15170 /* The U bit (rounding) comes from bit mask. */
15171 neon_three_same (neon_quad (rs
), 0, et
.size
);
15176 do_neon_qrdmlah (void)
15178 /* Check we're on the correct architecture. */
15179 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15181 _("instruction form not available on this architecture.");
15182 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15184 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15185 record_feature_use (&fpu_neon_ext_v8_1
);
15188 if (inst
.operands
[2].isscalar
)
15190 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15191 struct neon_type_el et
= neon_check_type (3, rs
,
15192 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15193 NEON_ENCODE (SCALAR
, inst
);
15194 neon_mul_mac (et
, neon_quad (rs
));
15198 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15199 struct neon_type_el et
= neon_check_type (3, rs
,
15200 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15201 NEON_ENCODE (INTEGER
, inst
);
15202 /* The U bit (rounding) comes from bit mask. */
15203 neon_three_same (neon_quad (rs
), 0, et
.size
);
15208 do_neon_fcmp_absolute (void)
15210 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15211 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15212 N_F_16_32
| N_KEY
);
15213 /* Size field comes from bit mask. */
15214 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15218 do_neon_fcmp_absolute_inv (void)
15220 neon_exchange_operands ();
15221 do_neon_fcmp_absolute ();
15225 do_neon_step (void)
15227 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15228 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15229 N_F_16_32
| N_KEY
);
15230 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15234 do_neon_abs_neg (void)
15236 enum neon_shape rs
;
15237 struct neon_type_el et
;
15239 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15242 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15245 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15246 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15248 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15249 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15250 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15251 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15252 inst
.instruction
|= neon_quad (rs
) << 6;
15253 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15254 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15256 neon_dp_fixup (&inst
);
15262 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15263 struct neon_type_el et
= neon_check_type (2, rs
,
15264 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15265 int imm
= inst
.operands
[2].imm
;
15266 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15267 _("immediate out of range for insert"));
15268 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15275 struct neon_type_el et
= neon_check_type (2, rs
,
15276 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15277 int imm
= inst
.operands
[2].imm
;
15278 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15279 _("immediate out of range for insert"));
15280 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15284 do_neon_qshlu_imm (void)
15286 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15287 struct neon_type_el et
= neon_check_type (2, rs
,
15288 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15289 int imm
= inst
.operands
[2].imm
;
15290 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15291 _("immediate out of range for shift"));
15292 /* Only encodes the 'U present' variant of the instruction.
15293 In this case, signed types have OP (bit 8) set to 0.
15294 Unsigned types have OP set to 1. */
15295 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15296 /* The rest of the bits are the same as other immediate shifts. */
15297 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15301 do_neon_qmovn (void)
15303 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15304 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15305 /* Saturating move where operands can be signed or unsigned, and the
15306 destination has the same signedness. */
15307 NEON_ENCODE (INTEGER
, inst
);
15308 if (et
.type
== NT_unsigned
)
15309 inst
.instruction
|= 0xc0;
15311 inst
.instruction
|= 0x80;
15312 neon_two_same (0, 1, et
.size
/ 2);
15316 do_neon_qmovun (void)
15318 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15319 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15320 /* Saturating move with unsigned results. Operands must be signed. */
15321 NEON_ENCODE (INTEGER
, inst
);
15322 neon_two_same (0, 1, et
.size
/ 2);
15326 do_neon_rshift_sat_narrow (void)
15328 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15329 or unsigned. If operands are unsigned, results must also be unsigned. */
15330 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15331 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15332 int imm
= inst
.operands
[2].imm
;
15333 /* This gets the bounds check, size encoding and immediate bits calculation
15337 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15338 VQMOVN.I<size> <Dd>, <Qm>. */
15341 inst
.operands
[2].present
= 0;
15342 inst
.instruction
= N_MNEM_vqmovn
;
15347 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15348 _("immediate out of range"));
15349 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15353 do_neon_rshift_sat_narrow_u (void)
15355 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15356 or unsigned. If operands are unsigned, results must also be unsigned. */
15357 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15358 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15359 int imm
= inst
.operands
[2].imm
;
15360 /* This gets the bounds check, size encoding and immediate bits calculation
15364 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15365 VQMOVUN.I<size> <Dd>, <Qm>. */
15368 inst
.operands
[2].present
= 0;
15369 inst
.instruction
= N_MNEM_vqmovun
;
15374 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15375 _("immediate out of range"));
15376 /* FIXME: The manual is kind of unclear about what value U should have in
15377 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15379 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15383 do_neon_movn (void)
15385 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15386 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15387 NEON_ENCODE (INTEGER
, inst
);
15388 neon_two_same (0, 1, et
.size
/ 2);
15392 do_neon_rshift_narrow (void)
15394 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15395 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15396 int imm
= inst
.operands
[2].imm
;
15397 /* This gets the bounds check, size encoding and immediate bits calculation
15401 /* If immediate is zero then we are a pseudo-instruction for
15402 VMOVN.I<size> <Dd>, <Qm> */
15405 inst
.operands
[2].present
= 0;
15406 inst
.instruction
= N_MNEM_vmovn
;
15411 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15412 _("immediate out of range for narrowing operation"));
15413 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15417 do_neon_shll (void)
15419 /* FIXME: Type checking when lengthening. */
15420 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15421 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15422 unsigned imm
= inst
.operands
[2].imm
;
15424 if (imm
== et
.size
)
15426 /* Maximum shift variant. */
15427 NEON_ENCODE (INTEGER
, inst
);
15428 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15429 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15430 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15431 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15432 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15434 neon_dp_fixup (&inst
);
15438 /* A more-specific type check for non-max versions. */
15439 et
= neon_check_type (2, NS_QDI
,
15440 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15441 NEON_ENCODE (IMMED
, inst
);
15442 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15446 /* Check the various types for the VCVT instruction, and return which version
15447 the current instruction is. */
15449 #define CVT_FLAVOUR_VAR \
15450 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15451 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15452 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15453 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15454 /* Half-precision conversions. */ \
15455 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15456 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15457 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15458 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15459 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15460 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15461 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15462 Compared with single/double precision variants, only the co-processor \
15463 field is different, so the encoding flow is reused here. */ \
15464 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15465 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15466 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15467 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15468 /* VFP instructions. */ \
15469 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15470 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15471 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15472 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15473 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15474 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15475 /* VFP instructions with bitshift. */ \
15476 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15477 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15478 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15479 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15480 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15481 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15482 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15483 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15485 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15486 neon_cvt_flavour_##C,
15488 /* The different types of conversions we can do. */
15489 enum neon_cvt_flavour
15492 neon_cvt_flavour_invalid
,
15493 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15498 static enum neon_cvt_flavour
15499 get_neon_cvt_flavour (enum neon_shape rs
)
15501 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15502 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15503 if (et.type != NT_invtype) \
15505 inst.error = NULL; \
15506 return (neon_cvt_flavour_##C); \
15509 struct neon_type_el et
;
15510 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15511 || rs
== NS_FF
) ? N_VFP
: 0;
15512 /* The instruction versions which take an immediate take one register
15513 argument, which is extended to the width of the full register. Thus the
15514 "source" and "destination" registers must have the same width. Hack that
15515 here by making the size equal to the key (wider, in this case) operand. */
15516 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15520 return neon_cvt_flavour_invalid
;
15535 /* Neon-syntax VFP conversions. */
15538 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15540 const char *opname
= 0;
15542 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15543 || rs
== NS_FHI
|| rs
== NS_HFI
)
15545 /* Conversions with immediate bitshift. */
15546 const char *enc
[] =
15548 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15554 if (flavour
< (int) ARRAY_SIZE (enc
))
15556 opname
= enc
[flavour
];
15557 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15558 _("operands 0 and 1 must be the same register"));
15559 inst
.operands
[1] = inst
.operands
[2];
15560 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15565 /* Conversions without bitshift. */
15566 const char *enc
[] =
15568 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15574 if (flavour
< (int) ARRAY_SIZE (enc
))
15575 opname
= enc
[flavour
];
15579 do_vfp_nsyn_opcode (opname
);
15581 /* ARMv8.2 fp16 VCVT instruction. */
15582 if (flavour
== neon_cvt_flavour_s32_f16
15583 || flavour
== neon_cvt_flavour_u32_f16
15584 || flavour
== neon_cvt_flavour_f16_u32
15585 || flavour
== neon_cvt_flavour_f16_s32
)
15586 do_scalar_fp16_v82_encode ();
15590 do_vfp_nsyn_cvtz (void)
15592 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15593 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15594 const char *enc
[] =
15596 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15602 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15603 do_vfp_nsyn_opcode (enc
[flavour
]);
15607 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15608 enum neon_cvt_mode mode
)
15613 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15614 D register operands. */
15615 if (flavour
== neon_cvt_flavour_s32_f64
15616 || flavour
== neon_cvt_flavour_u32_f64
)
15617 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15620 if (flavour
== neon_cvt_flavour_s32_f16
15621 || flavour
== neon_cvt_flavour_u32_f16
)
15622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15625 set_it_insn_type (OUTSIDE_IT_INSN
);
15629 case neon_cvt_flavour_s32_f64
:
15633 case neon_cvt_flavour_s32_f32
:
15637 case neon_cvt_flavour_s32_f16
:
15641 case neon_cvt_flavour_u32_f64
:
15645 case neon_cvt_flavour_u32_f32
:
15649 case neon_cvt_flavour_u32_f16
:
15654 first_error (_("invalid instruction shape"));
15660 case neon_cvt_mode_a
: rm
= 0; break;
15661 case neon_cvt_mode_n
: rm
= 1; break;
15662 case neon_cvt_mode_p
: rm
= 2; break;
15663 case neon_cvt_mode_m
: rm
= 3; break;
15664 default: first_error (_("invalid rounding mode")); return;
15667 NEON_ENCODE (FPV8
, inst
);
15668 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15669 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15670 inst
.instruction
|= sz
<< 8;
15672 /* ARMv8.2 fp16 VCVT instruction. */
15673 if (flavour
== neon_cvt_flavour_s32_f16
15674 ||flavour
== neon_cvt_flavour_u32_f16
)
15675 do_scalar_fp16_v82_encode ();
15676 inst
.instruction
|= op
<< 7;
15677 inst
.instruction
|= rm
<< 16;
15678 inst
.instruction
|= 0xf0000000;
15679 inst
.is_neon
= TRUE
;
15683 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15685 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15686 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15687 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15689 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15691 if (flavour
== neon_cvt_flavour_invalid
)
15694 /* PR11109: Handle round-to-zero for VCVT conversions. */
15695 if (mode
== neon_cvt_mode_z
15696 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15697 && (flavour
== neon_cvt_flavour_s16_f16
15698 || flavour
== neon_cvt_flavour_u16_f16
15699 || flavour
== neon_cvt_flavour_s32_f32
15700 || flavour
== neon_cvt_flavour_u32_f32
15701 || flavour
== neon_cvt_flavour_s32_f64
15702 || flavour
== neon_cvt_flavour_u32_f64
)
15703 && (rs
== NS_FD
|| rs
== NS_FF
))
15705 do_vfp_nsyn_cvtz ();
15709 /* ARMv8.2 fp16 VCVT conversions. */
15710 if (mode
== neon_cvt_mode_z
15711 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15712 && (flavour
== neon_cvt_flavour_s32_f16
15713 || flavour
== neon_cvt_flavour_u32_f16
)
15716 do_vfp_nsyn_cvtz ();
15717 do_scalar_fp16_v82_encode ();
15721 /* VFP rather than Neon conversions. */
15722 if (flavour
>= neon_cvt_flavour_first_fp
)
15724 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15725 do_vfp_nsyn_cvt (rs
, flavour
);
15727 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15738 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15739 0x0000100, 0x1000100, 0x0, 0x1000000};
15741 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15744 /* Fixed-point conversion with #0 immediate is encoded as an
15745 integer conversion. */
15746 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15748 NEON_ENCODE (IMMED
, inst
);
15749 if (flavour
!= neon_cvt_flavour_invalid
)
15750 inst
.instruction
|= enctab
[flavour
];
15751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15754 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15755 inst
.instruction
|= neon_quad (rs
) << 6;
15756 inst
.instruction
|= 1 << 21;
15757 if (flavour
< neon_cvt_flavour_s16_f16
)
15759 inst
.instruction
|= 1 << 21;
15760 immbits
= 32 - inst
.operands
[2].imm
;
15761 inst
.instruction
|= immbits
<< 16;
15765 inst
.instruction
|= 3 << 20;
15766 immbits
= 16 - inst
.operands
[2].imm
;
15767 inst
.instruction
|= immbits
<< 16;
15768 inst
.instruction
&= ~(1 << 9);
15771 neon_dp_fixup (&inst
);
15777 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15779 NEON_ENCODE (FLOAT
, inst
);
15780 set_it_insn_type (OUTSIDE_IT_INSN
);
15782 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15785 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15786 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15787 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15788 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15789 inst
.instruction
|= neon_quad (rs
) << 6;
15790 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15791 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15792 inst
.instruction
|= mode
<< 8;
15793 if (flavour
== neon_cvt_flavour_u16_f16
15794 || flavour
== neon_cvt_flavour_s16_f16
)
15795 /* Mask off the original size bits and reencode them. */
15796 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15799 inst
.instruction
|= 0xfc000000;
15801 inst
.instruction
|= 0xf0000000;
15807 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15808 0x100, 0x180, 0x0, 0x080};
15810 NEON_ENCODE (INTEGER
, inst
);
15812 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15815 if (flavour
!= neon_cvt_flavour_invalid
)
15816 inst
.instruction
|= enctab
[flavour
];
15818 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15819 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15820 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15821 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15822 inst
.instruction
|= neon_quad (rs
) << 6;
15823 if (flavour
>= neon_cvt_flavour_s16_f16
15824 && flavour
<= neon_cvt_flavour_f16_u16
)
15825 /* Half precision. */
15826 inst
.instruction
|= 1 << 18;
15828 inst
.instruction
|= 2 << 18;
15830 neon_dp_fixup (&inst
);
15835 /* Half-precision conversions for Advanced SIMD -- neon. */
15840 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15842 as_bad (_("operand size must match register width"));
15847 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15849 as_bad (_("operand size must match register width"));
15854 inst
.instruction
= 0x3b60600;
15856 inst
.instruction
= 0x3b60700;
15858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15859 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15860 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15861 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15862 neon_dp_fixup (&inst
);
15866 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15867 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15868 do_vfp_nsyn_cvt (rs
, flavour
);
15870 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15875 do_neon_cvtr (void)
15877 do_neon_cvt_1 (neon_cvt_mode_x
);
15883 do_neon_cvt_1 (neon_cvt_mode_z
);
15887 do_neon_cvta (void)
15889 do_neon_cvt_1 (neon_cvt_mode_a
);
15893 do_neon_cvtn (void)
15895 do_neon_cvt_1 (neon_cvt_mode_n
);
15899 do_neon_cvtp (void)
15901 do_neon_cvt_1 (neon_cvt_mode_p
);
15905 do_neon_cvtm (void)
15907 do_neon_cvt_1 (neon_cvt_mode_m
);
15911 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15914 mark_feature_used (&fpu_vfp_ext_armv8
);
15916 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15917 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15918 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15919 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15920 inst
.instruction
|= to
? 0x10000 : 0;
15921 inst
.instruction
|= t
? 0x80 : 0;
15922 inst
.instruction
|= is_double
? 0x100 : 0;
15923 do_vfp_cond_or_thumb ();
15927 do_neon_cvttb_1 (bfd_boolean t
)
15929 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15930 NS_DF
, NS_DH
, NS_NULL
);
15934 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15937 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15939 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15942 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15944 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15946 /* The VCVTB and VCVTT instructions with D-register operands
15947 don't work for SP only targets. */
15948 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15952 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15954 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15956 /* The VCVTB and VCVTT instructions with D-register operands
15957 don't work for SP only targets. */
15958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15962 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15969 do_neon_cvtb (void)
15971 do_neon_cvttb_1 (FALSE
);
15976 do_neon_cvtt (void)
15978 do_neon_cvttb_1 (TRUE
);
15982 neon_move_immediate (void)
15984 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15985 struct neon_type_el et
= neon_check_type (2, rs
,
15986 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15987 unsigned immlo
, immhi
= 0, immbits
;
15988 int op
, cmode
, float_p
;
15990 constraint (et
.type
== NT_invtype
,
15991 _("operand size must be specified for immediate VMOV"));
15993 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15994 op
= (inst
.instruction
& (1 << 5)) != 0;
15996 immlo
= inst
.operands
[1].imm
;
15997 if (inst
.operands
[1].regisimm
)
15998 immhi
= inst
.operands
[1].reg
;
16000 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16001 _("immediate has bits set outside the operand size"));
16003 float_p
= inst
.operands
[1].immisfloat
;
16005 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16006 et
.size
, et
.type
)) == FAIL
)
16008 /* Invert relevant bits only. */
16009 neon_invert_size (&immlo
, &immhi
, et
.size
);
16010 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16011 with one or the other; those cases are caught by
16012 neon_cmode_for_move_imm. */
16014 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16015 &op
, et
.size
, et
.type
)) == FAIL
)
16017 first_error (_("immediate out of range"));
16022 inst
.instruction
&= ~(1 << 5);
16023 inst
.instruction
|= op
<< 5;
16025 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16026 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16027 inst
.instruction
|= neon_quad (rs
) << 6;
16028 inst
.instruction
|= cmode
<< 8;
16030 neon_write_immbits (immbits
);
16036 if (inst
.operands
[1].isreg
)
16038 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16040 NEON_ENCODE (INTEGER
, inst
);
16041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16044 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16045 inst
.instruction
|= neon_quad (rs
) << 6;
16049 NEON_ENCODE (IMMED
, inst
);
16050 neon_move_immediate ();
16053 neon_dp_fixup (&inst
);
16056 /* Encode instructions of form:
16058 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16059 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16062 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16064 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16065 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16066 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16067 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16068 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16069 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16070 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16071 inst
.instruction
|= neon_logbits (size
) << 20;
16073 neon_dp_fixup (&inst
);
16077 do_neon_dyadic_long (void)
16079 /* FIXME: Type checking for lengthening op. */
16080 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16081 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16082 neon_mixed_length (et
, et
.size
);
16086 do_neon_abal (void)
16088 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16089 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16090 neon_mixed_length (et
, et
.size
);
16094 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16096 if (inst
.operands
[2].isscalar
)
16098 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16099 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16100 NEON_ENCODE (SCALAR
, inst
);
16101 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16105 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16106 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16107 NEON_ENCODE (INTEGER
, inst
);
16108 neon_mixed_length (et
, et
.size
);
16113 do_neon_mac_maybe_scalar_long (void)
16115 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16119 do_neon_dyadic_wide (void)
16121 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16122 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16123 neon_mixed_length (et
, et
.size
);
16127 do_neon_dyadic_narrow (void)
16129 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16130 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16131 /* Operand sign is unimportant, and the U bit is part of the opcode,
16132 so force the operand type to integer. */
16133 et
.type
= NT_integer
;
16134 neon_mixed_length (et
, et
.size
/ 2);
16138 do_neon_mul_sat_scalar_long (void)
16140 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16144 do_neon_vmull (void)
16146 if (inst
.operands
[2].isscalar
)
16147 do_neon_mac_maybe_scalar_long ();
16150 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16151 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16153 if (et
.type
== NT_poly
)
16154 NEON_ENCODE (POLY
, inst
);
16156 NEON_ENCODE (INTEGER
, inst
);
16158 /* For polynomial encoding the U bit must be zero, and the size must
16159 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16160 obviously, as 0b10). */
16163 /* Check we're on the correct architecture. */
16164 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16166 _("Instruction form not available on this architecture.");
16171 neon_mixed_length (et
, et
.size
);
16178 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16179 struct neon_type_el et
= neon_check_type (3, rs
,
16180 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16181 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16183 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16184 _("shift out of range"));
16185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16187 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16188 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16189 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16190 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16191 inst
.instruction
|= neon_quad (rs
) << 6;
16192 inst
.instruction
|= imm
<< 8;
16194 neon_dp_fixup (&inst
);
16200 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16201 struct neon_type_el et
= neon_check_type (2, rs
,
16202 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16203 unsigned op
= (inst
.instruction
>> 7) & 3;
16204 /* N (width of reversed regions) is encoded as part of the bitmask. We
16205 extract it here to check the elements to be reversed are smaller.
16206 Otherwise we'd get a reserved instruction. */
16207 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16208 gas_assert (elsize
!= 0);
16209 constraint (et
.size
>= elsize
,
16210 _("elements must be smaller than reversal region"));
16211 neon_two_same (neon_quad (rs
), 1, et
.size
);
16217 if (inst
.operands
[1].isscalar
)
16219 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16220 struct neon_type_el et
= neon_check_type (2, rs
,
16221 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16222 unsigned sizebits
= et
.size
>> 3;
16223 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16224 int logsize
= neon_logbits (et
.size
);
16225 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16227 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16230 NEON_ENCODE (SCALAR
, inst
);
16231 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16232 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16233 inst
.instruction
|= LOW4 (dm
);
16234 inst
.instruction
|= HI1 (dm
) << 5;
16235 inst
.instruction
|= neon_quad (rs
) << 6;
16236 inst
.instruction
|= x
<< 17;
16237 inst
.instruction
|= sizebits
<< 16;
16239 neon_dp_fixup (&inst
);
16243 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16244 struct neon_type_el et
= neon_check_type (2, rs
,
16245 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16246 /* Duplicate ARM register to lanes of vector. */
16247 NEON_ENCODE (ARMREG
, inst
);
16250 case 8: inst
.instruction
|= 0x400000; break;
16251 case 16: inst
.instruction
|= 0x000020; break;
16252 case 32: inst
.instruction
|= 0x000000; break;
16255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16256 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16257 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16258 inst
.instruction
|= neon_quad (rs
) << 21;
16259 /* The encoding for this instruction is identical for the ARM and Thumb
16260 variants, except for the condition field. */
16261 do_vfp_cond_or_thumb ();
16265 /* VMOV has particularly many variations. It can be one of:
16266 0. VMOV<c><q> <Qd>, <Qm>
16267 1. VMOV<c><q> <Dd>, <Dm>
16268 (Register operations, which are VORR with Rm = Rn.)
16269 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16270 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16272 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16273 (ARM register to scalar.)
16274 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16275 (Two ARM registers to vector.)
16276 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16277 (Scalar to ARM register.)
16278 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16279 (Vector to two ARM registers.)
16280 8. VMOV.F32 <Sd>, <Sm>
16281 9. VMOV.F64 <Dd>, <Dm>
16282 (VFP register moves.)
16283 10. VMOV.F32 <Sd>, #imm
16284 11. VMOV.F64 <Dd>, #imm
16285 (VFP float immediate load.)
16286 12. VMOV <Rd>, <Sm>
16287 (VFP single to ARM reg.)
16288 13. VMOV <Sd>, <Rm>
16289 (ARM reg to VFP single.)
16290 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16291 (Two ARM regs to two VFP singles.)
16292 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16293 (Two VFP singles to two ARM regs.)
16295 These cases can be disambiguated using neon_select_shape, except cases 1/9
16296 and 3/11 which depend on the operand type too.
16298 All the encoded bits are hardcoded by this function.
16300 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16301 Cases 5, 7 may be used with VFPv2 and above.
16303 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16304 can specify a type where it doesn't make sense to, and is ignored). */
16309 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16310 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16311 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16312 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16313 struct neon_type_el et
;
16314 const char *ldconst
= 0;
16318 case NS_DD
: /* case 1/9. */
16319 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16320 /* It is not an error here if no type is given. */
16322 if (et
.type
== NT_float
&& et
.size
== 64)
16324 do_vfp_nsyn_opcode ("fcpyd");
16327 /* fall through. */
16329 case NS_QQ
: /* case 0/1. */
16331 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16333 /* The architecture manual I have doesn't explicitly state which
16334 value the U bit should have for register->register moves, but
16335 the equivalent VORR instruction has U = 0, so do that. */
16336 inst
.instruction
= 0x0200110;
16337 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16338 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16339 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16340 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16341 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16342 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16343 inst
.instruction
|= neon_quad (rs
) << 6;
16345 neon_dp_fixup (&inst
);
16349 case NS_DI
: /* case 3/11. */
16350 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16352 if (et
.type
== NT_float
&& et
.size
== 64)
16354 /* case 11 (fconstd). */
16355 ldconst
= "fconstd";
16356 goto encode_fconstd
;
16358 /* fall through. */
16360 case NS_QI
: /* case 2/3. */
16361 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16363 inst
.instruction
= 0x0800010;
16364 neon_move_immediate ();
16365 neon_dp_fixup (&inst
);
16368 case NS_SR
: /* case 4. */
16370 unsigned bcdebits
= 0;
16372 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16373 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16375 /* .<size> is optional here, defaulting to .32. */
16376 if (inst
.vectype
.elems
== 0
16377 && inst
.operands
[0].vectype
.type
== NT_invtype
16378 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16380 inst
.vectype
.el
[0].type
= NT_untyped
;
16381 inst
.vectype
.el
[0].size
= 32;
16382 inst
.vectype
.elems
= 1;
16385 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16386 logsize
= neon_logbits (et
.size
);
16388 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16391 && et
.size
!= 32, _(BAD_FPU
));
16392 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16393 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16397 case 8: bcdebits
= 0x8; break;
16398 case 16: bcdebits
= 0x1; break;
16399 case 32: bcdebits
= 0x0; break;
16403 bcdebits
|= x
<< logsize
;
16405 inst
.instruction
= 0xe000b10;
16406 do_vfp_cond_or_thumb ();
16407 inst
.instruction
|= LOW4 (dn
) << 16;
16408 inst
.instruction
|= HI1 (dn
) << 7;
16409 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16410 inst
.instruction
|= (bcdebits
& 3) << 5;
16411 inst
.instruction
|= (bcdebits
>> 2) << 21;
16415 case NS_DRR
: /* case 5 (fmdrr). */
16416 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16419 inst
.instruction
= 0xc400b10;
16420 do_vfp_cond_or_thumb ();
16421 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16422 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16423 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16424 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16427 case NS_RS
: /* case 6. */
16430 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16431 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16432 unsigned abcdebits
= 0;
16434 /* .<dt> is optional here, defaulting to .32. */
16435 if (inst
.vectype
.elems
== 0
16436 && inst
.operands
[0].vectype
.type
== NT_invtype
16437 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16439 inst
.vectype
.el
[0].type
= NT_untyped
;
16440 inst
.vectype
.el
[0].size
= 32;
16441 inst
.vectype
.elems
= 1;
16444 et
= neon_check_type (2, NS_NULL
,
16445 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16446 logsize
= neon_logbits (et
.size
);
16448 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16450 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16451 && et
.size
!= 32, _(BAD_FPU
));
16452 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16453 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16457 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16458 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16459 case 32: abcdebits
= 0x00; break;
16463 abcdebits
|= x
<< logsize
;
16464 inst
.instruction
= 0xe100b10;
16465 do_vfp_cond_or_thumb ();
16466 inst
.instruction
|= LOW4 (dn
) << 16;
16467 inst
.instruction
|= HI1 (dn
) << 7;
16468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16469 inst
.instruction
|= (abcdebits
& 3) << 5;
16470 inst
.instruction
|= (abcdebits
>> 2) << 21;
16474 case NS_RRD
: /* case 7 (fmrrd). */
16475 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16478 inst
.instruction
= 0xc500b10;
16479 do_vfp_cond_or_thumb ();
16480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16481 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16482 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16483 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16486 case NS_FF
: /* case 8 (fcpys). */
16487 do_vfp_nsyn_opcode ("fcpys");
16491 case NS_FI
: /* case 10 (fconsts). */
16492 ldconst
= "fconsts";
16494 if (is_quarter_float (inst
.operands
[1].imm
))
16496 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16497 do_vfp_nsyn_opcode (ldconst
);
16499 /* ARMv8.2 fp16 vmov.f16 instruction. */
16501 do_scalar_fp16_v82_encode ();
16504 first_error (_("immediate out of range"));
16508 case NS_RF
: /* case 12 (fmrs). */
16509 do_vfp_nsyn_opcode ("fmrs");
16510 /* ARMv8.2 fp16 vmov.f16 instruction. */
16512 do_scalar_fp16_v82_encode ();
16516 case NS_FR
: /* case 13 (fmsr). */
16517 do_vfp_nsyn_opcode ("fmsr");
16518 /* ARMv8.2 fp16 vmov.f16 instruction. */
16520 do_scalar_fp16_v82_encode ();
16523 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16524 (one of which is a list), but we have parsed four. Do some fiddling to
16525 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16527 case NS_RRFF
: /* case 14 (fmrrs). */
16528 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16529 _("VFP registers must be adjacent"));
16530 inst
.operands
[2].imm
= 2;
16531 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16532 do_vfp_nsyn_opcode ("fmrrs");
16535 case NS_FFRR
: /* case 15 (fmsrr). */
16536 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16537 _("VFP registers must be adjacent"));
16538 inst
.operands
[1] = inst
.operands
[2];
16539 inst
.operands
[2] = inst
.operands
[3];
16540 inst
.operands
[0].imm
= 2;
16541 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16542 do_vfp_nsyn_opcode ("fmsrr");
16546 /* neon_select_shape has determined that the instruction
16547 shape is wrong and has already set the error message. */
16556 do_neon_rshift_round_imm (void)
16558 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16559 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16560 int imm
= inst
.operands
[2].imm
;
16562 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16565 inst
.operands
[2].present
= 0;
16570 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16571 _("immediate out of range for shift"));
16572 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16577 do_neon_movhf (void)
16579 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16580 constraint (rs
!= NS_HH
, _("invalid suffix"));
16582 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16585 do_vfp_sp_monadic ();
16588 inst
.instruction
|= 0xf0000000;
16592 do_neon_movl (void)
16594 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16595 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16596 unsigned sizebits
= et
.size
>> 3;
16597 inst
.instruction
|= sizebits
<< 19;
16598 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16604 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16605 struct neon_type_el et
= neon_check_type (2, rs
,
16606 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16607 NEON_ENCODE (INTEGER
, inst
);
16608 neon_two_same (neon_quad (rs
), 1, et
.size
);
16612 do_neon_zip_uzp (void)
16614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16615 struct neon_type_el et
= neon_check_type (2, rs
,
16616 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16617 if (rs
== NS_DD
&& et
.size
== 32)
16619 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16620 inst
.instruction
= N_MNEM_vtrn
;
16624 neon_two_same (neon_quad (rs
), 1, et
.size
);
16628 do_neon_sat_abs_neg (void)
16630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16631 struct neon_type_el et
= neon_check_type (2, rs
,
16632 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16633 neon_two_same (neon_quad (rs
), 1, et
.size
);
16637 do_neon_pair_long (void)
16639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16640 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16641 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16642 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16643 neon_two_same (neon_quad (rs
), 1, et
.size
);
16647 do_neon_recip_est (void)
16649 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16650 struct neon_type_el et
= neon_check_type (2, rs
,
16651 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16652 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16653 neon_two_same (neon_quad (rs
), 1, et
.size
);
16659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16660 struct neon_type_el et
= neon_check_type (2, rs
,
16661 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16662 neon_two_same (neon_quad (rs
), 1, et
.size
);
16668 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16669 struct neon_type_el et
= neon_check_type (2, rs
,
16670 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16671 neon_two_same (neon_quad (rs
), 1, et
.size
);
16677 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16678 struct neon_type_el et
= neon_check_type (2, rs
,
16679 N_EQK
| N_INT
, N_8
| N_KEY
);
16680 neon_two_same (neon_quad (rs
), 1, et
.size
);
16686 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16687 neon_two_same (neon_quad (rs
), 1, -1);
16691 do_neon_tbl_tbx (void)
16693 unsigned listlenbits
;
16694 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16696 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16698 first_error (_("bad list length for table lookup"));
16702 listlenbits
= inst
.operands
[1].imm
- 1;
16703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16707 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16708 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16709 inst
.instruction
|= listlenbits
<< 8;
16711 neon_dp_fixup (&inst
);
16715 do_neon_ldm_stm (void)
16717 /* P, U and L bits are part of bitmask. */
16718 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16719 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16721 if (inst
.operands
[1].issingle
)
16723 do_vfp_nsyn_ldm_stm (is_dbmode
);
16727 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16728 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16730 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16731 _("register list must contain at least 1 and at most 16 "
16734 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16735 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16736 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16737 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16739 inst
.instruction
|= offsetbits
;
16741 do_vfp_cond_or_thumb ();
16745 do_neon_ldr_str (void)
16747 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16749 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16750 And is UNPREDICTABLE in thumb mode. */
16752 && inst
.operands
[1].reg
== REG_PC
16753 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16756 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16757 else if (warn_on_deprecated
)
16758 as_tsktsk (_("Use of PC here is deprecated"));
16761 if (inst
.operands
[0].issingle
)
16764 do_vfp_nsyn_opcode ("flds");
16766 do_vfp_nsyn_opcode ("fsts");
16768 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16769 if (inst
.vectype
.el
[0].size
== 16)
16770 do_scalar_fp16_v82_encode ();
16775 do_vfp_nsyn_opcode ("fldd");
16777 do_vfp_nsyn_opcode ("fstd");
16781 /* "interleave" version also handles non-interleaving register VLD1/VST1
16785 do_neon_ld_st_interleave (void)
16787 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16788 N_8
| N_16
| N_32
| N_64
);
16789 unsigned alignbits
= 0;
16791 /* The bits in this table go:
16792 0: register stride of one (0) or two (1)
16793 1,2: register list length, minus one (1, 2, 3, 4).
16794 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16795 We use -1 for invalid entries. */
16796 const int typetable
[] =
16798 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16799 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16800 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16801 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16805 if (et
.type
== NT_invtype
)
16808 if (inst
.operands
[1].immisalign
)
16809 switch (inst
.operands
[1].imm
>> 8)
16811 case 64: alignbits
= 1; break;
16813 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16814 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16815 goto bad_alignment
;
16819 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16820 goto bad_alignment
;
16825 first_error (_("bad alignment"));
16829 inst
.instruction
|= alignbits
<< 4;
16830 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16832 /* Bits [4:6] of the immediate in a list specifier encode register stride
16833 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16834 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16835 up the right value for "type" in a table based on this value and the given
16836 list style, then stick it back. */
16837 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16838 | (((inst
.instruction
>> 8) & 3) << 3);
16840 typebits
= typetable
[idx
];
16842 constraint (typebits
== -1, _("bad list type for instruction"));
16843 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16844 _("bad element type for instruction"));
16846 inst
.instruction
&= ~0xf00;
16847 inst
.instruction
|= typebits
<< 8;
16850 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16851 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16852 otherwise. The variable arguments are a list of pairs of legal (size, align)
16853 values, terminated with -1. */
16856 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16859 int result
= FAIL
, thissize
, thisalign
;
16861 if (!inst
.operands
[1].immisalign
)
16867 va_start (ap
, do_alignment
);
16871 thissize
= va_arg (ap
, int);
16872 if (thissize
== -1)
16874 thisalign
= va_arg (ap
, int);
16876 if (size
== thissize
&& align
== thisalign
)
16879 while (result
!= SUCCESS
);
16883 if (result
== SUCCESS
)
16886 first_error (_("unsupported alignment for instruction"));
16892 do_neon_ld_st_lane (void)
16894 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16895 int align_good
, do_alignment
= 0;
16896 int logsize
= neon_logbits (et
.size
);
16897 int align
= inst
.operands
[1].imm
>> 8;
16898 int n
= (inst
.instruction
>> 8) & 3;
16899 int max_el
= 64 / et
.size
;
16901 if (et
.type
== NT_invtype
)
16904 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16905 _("bad list length"));
16906 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16907 _("scalar index out of range"));
16908 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16910 _("stride of 2 unavailable when element size is 8"));
16914 case 0: /* VLD1 / VST1. */
16915 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16917 if (align_good
== FAIL
)
16921 unsigned alignbits
= 0;
16924 case 16: alignbits
= 0x1; break;
16925 case 32: alignbits
= 0x3; break;
16928 inst
.instruction
|= alignbits
<< 4;
16932 case 1: /* VLD2 / VST2. */
16933 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16934 16, 32, 32, 64, -1);
16935 if (align_good
== FAIL
)
16938 inst
.instruction
|= 1 << 4;
16941 case 2: /* VLD3 / VST3. */
16942 constraint (inst
.operands
[1].immisalign
,
16943 _("can't use alignment with this instruction"));
16946 case 3: /* VLD4 / VST4. */
16947 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16948 16, 64, 32, 64, 32, 128, -1);
16949 if (align_good
== FAIL
)
16953 unsigned alignbits
= 0;
16956 case 8: alignbits
= 0x1; break;
16957 case 16: alignbits
= 0x1; break;
16958 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16961 inst
.instruction
|= alignbits
<< 4;
16968 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16969 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16970 inst
.instruction
|= 1 << (4 + logsize
);
16972 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16973 inst
.instruction
|= logsize
<< 10;
16976 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16979 do_neon_ld_dup (void)
16981 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16982 int align_good
, do_alignment
= 0;
16984 if (et
.type
== NT_invtype
)
16987 switch ((inst
.instruction
>> 8) & 3)
16989 case 0: /* VLD1. */
16990 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16991 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16992 &do_alignment
, 16, 16, 32, 32, -1);
16993 if (align_good
== FAIL
)
16995 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16998 case 2: inst
.instruction
|= 1 << 5; break;
16999 default: first_error (_("bad list length")); return;
17001 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17004 case 1: /* VLD2. */
17005 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17006 &do_alignment
, 8, 16, 16, 32, 32, 64,
17008 if (align_good
== FAIL
)
17010 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17011 _("bad list length"));
17012 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17013 inst
.instruction
|= 1 << 5;
17014 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17017 case 2: /* VLD3. */
17018 constraint (inst
.operands
[1].immisalign
,
17019 _("can't use alignment with this instruction"));
17020 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17021 _("bad list length"));
17022 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17023 inst
.instruction
|= 1 << 5;
17024 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17027 case 3: /* VLD4. */
17029 int align
= inst
.operands
[1].imm
>> 8;
17030 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17031 16, 64, 32, 64, 32, 128, -1);
17032 if (align_good
== FAIL
)
17034 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17035 _("bad list length"));
17036 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17037 inst
.instruction
|= 1 << 5;
17038 if (et
.size
== 32 && align
== 128)
17039 inst
.instruction
|= 0x3 << 6;
17041 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17048 inst
.instruction
|= do_alignment
<< 4;
17051 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17052 apart from bits [11:4]. */
17055 do_neon_ldx_stx (void)
17057 if (inst
.operands
[1].isreg
)
17058 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17060 switch (NEON_LANE (inst
.operands
[0].imm
))
17062 case NEON_INTERLEAVE_LANES
:
17063 NEON_ENCODE (INTERLV
, inst
);
17064 do_neon_ld_st_interleave ();
17067 case NEON_ALL_LANES
:
17068 NEON_ENCODE (DUP
, inst
);
17069 if (inst
.instruction
== N_INV
)
17071 first_error ("only loads support such operands");
17078 NEON_ENCODE (LANE
, inst
);
17079 do_neon_ld_st_lane ();
17082 /* L bit comes from bit mask. */
17083 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17084 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17087 if (inst
.operands
[1].postind
)
17089 int postreg
= inst
.operands
[1].imm
& 0xf;
17090 constraint (!inst
.operands
[1].immisreg
,
17091 _("post-index must be a register"));
17092 constraint (postreg
== 0xd || postreg
== 0xf,
17093 _("bad register for post-index"));
17094 inst
.instruction
|= postreg
;
17098 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17099 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17100 || inst
.reloc
.exp
.X_add_number
!= 0,
17103 if (inst
.operands
[1].writeback
)
17105 inst
.instruction
|= 0xd;
17108 inst
.instruction
|= 0xf;
17112 inst
.instruction
|= 0xf9000000;
17114 inst
.instruction
|= 0xf4000000;
17119 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17121 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17122 D register operands. */
17123 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17124 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17127 NEON_ENCODE (FPV8
, inst
);
17129 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17131 do_vfp_sp_dyadic ();
17133 /* ARMv8.2 fp16 instruction. */
17135 do_scalar_fp16_v82_encode ();
17138 do_vfp_dp_rd_rn_rm ();
17141 inst
.instruction
|= 0x100;
17143 inst
.instruction
|= 0xf0000000;
17149 set_it_insn_type (OUTSIDE_IT_INSN
);
17151 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17152 first_error (_("invalid instruction shape"));
17158 set_it_insn_type (OUTSIDE_IT_INSN
);
17160 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17163 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17166 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17170 do_vrint_1 (enum neon_cvt_mode mode
)
17172 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17173 struct neon_type_el et
;
17178 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17179 D register operands. */
17180 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17181 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17184 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17186 if (et
.type
!= NT_invtype
)
17188 /* VFP encodings. */
17189 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17190 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17191 set_it_insn_type (OUTSIDE_IT_INSN
);
17193 NEON_ENCODE (FPV8
, inst
);
17194 if (rs
== NS_FF
|| rs
== NS_HH
)
17195 do_vfp_sp_monadic ();
17197 do_vfp_dp_rd_rm ();
17201 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17202 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17203 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17204 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17205 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17206 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17207 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17211 inst
.instruction
|= (rs
== NS_DD
) << 8;
17212 do_vfp_cond_or_thumb ();
17214 /* ARMv8.2 fp16 vrint instruction. */
17216 do_scalar_fp16_v82_encode ();
17220 /* Neon encodings (or something broken...). */
17222 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17224 if (et
.type
== NT_invtype
)
17227 set_it_insn_type (OUTSIDE_IT_INSN
);
17228 NEON_ENCODE (FLOAT
, inst
);
17230 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17233 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17234 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17236 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17237 inst
.instruction
|= neon_quad (rs
) << 6;
17238 /* Mask off the original size bits and reencode them. */
17239 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17240 | neon_logbits (et
.size
) << 18);
17244 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17245 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17246 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17247 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17248 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17249 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17250 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17255 inst
.instruction
|= 0xfc000000;
17257 inst
.instruction
|= 0xf0000000;
17264 do_vrint_1 (neon_cvt_mode_x
);
17270 do_vrint_1 (neon_cvt_mode_z
);
17276 do_vrint_1 (neon_cvt_mode_r
);
17282 do_vrint_1 (neon_cvt_mode_a
);
17288 do_vrint_1 (neon_cvt_mode_n
);
17294 do_vrint_1 (neon_cvt_mode_p
);
17300 do_vrint_1 (neon_cvt_mode_m
);
17304 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17306 unsigned regno
= NEON_SCALAR_REG (opnd
);
17307 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17309 if (elsize
== 16 && elno
< 2 && regno
< 16)
17310 return regno
| (elno
<< 4);
17311 else if (elsize
== 32 && elno
== 0)
17314 first_error (_("scalar out of range"));
17321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17323 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17324 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17325 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17326 _("immediate out of range"));
17328 if (inst
.operands
[2].isscalar
)
17330 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17331 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17332 N_KEY
| N_F16
| N_F32
).size
;
17333 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17335 inst
.instruction
= 0xfe000800;
17336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17337 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17338 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17340 inst
.instruction
|= LOW4 (m
);
17341 inst
.instruction
|= HI1 (m
) << 5;
17342 inst
.instruction
|= neon_quad (rs
) << 6;
17343 inst
.instruction
|= rot
<< 20;
17344 inst
.instruction
|= (size
== 32) << 23;
17348 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17349 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17350 N_KEY
| N_F16
| N_F32
).size
;
17351 neon_three_same (neon_quad (rs
), 0, -1);
17352 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17353 inst
.instruction
|= 0xfc200800;
17354 inst
.instruction
|= rot
<< 23;
17355 inst
.instruction
|= (size
== 32) << 20;
17362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17364 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17365 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17366 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17367 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17368 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17369 N_KEY
| N_F16
| N_F32
).size
;
17370 neon_three_same (neon_quad (rs
), 0, -1);
17371 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17372 inst
.instruction
|= 0xfc800800;
17373 inst
.instruction
|= (rot
== 270) << 24;
17374 inst
.instruction
|= (size
== 32) << 20;
17377 /* Dot Product instructions encoding support. */
17380 do_neon_dotproduct (int unsigned_p
)
17382 enum neon_shape rs
;
17383 unsigned scalar_oprd2
= 0;
17386 if (inst
.cond
!= COND_ALWAYS
)
17387 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17388 "is UNPREDICTABLE"));
17390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17393 /* Dot Product instructions are in three-same D/Q register format or the third
17394 operand can be a scalar index register. */
17395 if (inst
.operands
[2].isscalar
)
17397 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17398 high8
= 0xfe000000;
17399 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17403 high8
= 0xfc000000;
17404 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17408 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17410 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17412 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17413 Product instruction, so we pass 0 as the "ubit" parameter. And the
17414 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17415 neon_three_same (neon_quad (rs
), 0, 32);
17417 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17418 different NEON three-same encoding. */
17419 inst
.instruction
&= 0x00ffffff;
17420 inst
.instruction
|= high8
;
17421 /* Encode 'U' bit which indicates signedness. */
17422 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17423 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17424 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17425 the instruction encoding. */
17426 if (inst
.operands
[2].isscalar
)
17428 inst
.instruction
&= 0xffffffd0;
17429 inst
.instruction
|= LOW4 (scalar_oprd2
);
17430 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17434 /* Dot Product instructions for signed integer. */
17437 do_neon_dotproduct_s (void)
17439 return do_neon_dotproduct (0);
17442 /* Dot Product instructions for unsigned integer. */
17445 do_neon_dotproduct_u (void)
17447 return do_neon_dotproduct (1);
17450 /* Crypto v1 instructions. */
17452 do_crypto_2op_1 (unsigned elttype
, int op
)
17454 set_it_insn_type (OUTSIDE_IT_INSN
);
17456 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17462 NEON_ENCODE (INTEGER
, inst
);
17463 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17465 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17466 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17468 inst
.instruction
|= op
<< 6;
17471 inst
.instruction
|= 0xfc000000;
17473 inst
.instruction
|= 0xf0000000;
17477 do_crypto_3op_1 (int u
, int op
)
17479 set_it_insn_type (OUTSIDE_IT_INSN
);
17481 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17482 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17487 NEON_ENCODE (INTEGER
, inst
);
17488 neon_three_same (1, u
, 8 << op
);
17494 do_crypto_2op_1 (N_8
, 0);
17500 do_crypto_2op_1 (N_8
, 1);
17506 do_crypto_2op_1 (N_8
, 2);
17512 do_crypto_2op_1 (N_8
, 3);
17518 do_crypto_3op_1 (0, 0);
17524 do_crypto_3op_1 (0, 1);
17530 do_crypto_3op_1 (0, 2);
17536 do_crypto_3op_1 (0, 3);
17542 do_crypto_3op_1 (1, 0);
17548 do_crypto_3op_1 (1, 1);
17552 do_sha256su1 (void)
17554 do_crypto_3op_1 (1, 2);
17560 do_crypto_2op_1 (N_32
, -1);
17566 do_crypto_2op_1 (N_32
, 0);
17570 do_sha256su0 (void)
17572 do_crypto_2op_1 (N_32
, 1);
17576 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17578 unsigned int Rd
= inst
.operands
[0].reg
;
17579 unsigned int Rn
= inst
.operands
[1].reg
;
17580 unsigned int Rm
= inst
.operands
[2].reg
;
17582 set_it_insn_type (OUTSIDE_IT_INSN
);
17583 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17584 inst
.instruction
|= LOW4 (Rn
) << 16;
17585 inst
.instruction
|= LOW4 (Rm
);
17586 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17587 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17589 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17590 as_warn (UNPRED_REG ("r15"));
17591 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17592 as_warn (UNPRED_REG ("r13"));
17634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17636 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17637 do_vfp_sp_dp_cvt ();
17638 do_vfp_cond_or_thumb ();
17642 /* Overall per-instruction processing. */
17644 /* We need to be able to fix up arbitrary expressions in some statements.
17645 This is so that we can handle symbols that are an arbitrary distance from
17646 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17647 which returns part of an address in a form which will be valid for
17648 a data instruction. We do this by pushing the expression into a symbol
17649 in the expr_section, and creating a fix for that. */
17652 fix_new_arm (fragS
* frag
,
17666 /* Create an absolute valued symbol, so we have something to
17667 refer to in the object file. Unfortunately for us, gas's
17668 generic expression parsing will already have folded out
17669 any use of .set foo/.type foo %function that may have
17670 been used to set type information of the target location,
17671 that's being specified symbolically. We have to presume
17672 the user knows what they are doing. */
17676 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17678 symbol
= symbol_find_or_make (name
);
17679 S_SET_SEGMENT (symbol
, absolute_section
);
17680 symbol_set_frag (symbol
, &zero_address_frag
);
17681 S_SET_VALUE (symbol
, exp
->X_add_number
);
17682 exp
->X_op
= O_symbol
;
17683 exp
->X_add_symbol
= symbol
;
17684 exp
->X_add_number
= 0;
17690 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17691 (enum bfd_reloc_code_real
) reloc
);
17695 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17696 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17700 /* Mark whether the fix is to a THUMB instruction, or an ARM
17702 new_fix
->tc_fix_data
= thumb_mode
;
17705 /* Create a frg for an instruction requiring relaxation. */
17707 output_relax_insn (void)
17713 /* The size of the instruction is unknown, so tie the debug info to the
17714 start of the instruction. */
17715 dwarf2_emit_insn (0);
17717 switch (inst
.reloc
.exp
.X_op
)
17720 sym
= inst
.reloc
.exp
.X_add_symbol
;
17721 offset
= inst
.reloc
.exp
.X_add_number
;
17725 offset
= inst
.reloc
.exp
.X_add_number
;
17728 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17732 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17733 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17734 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17737 /* Write a 32-bit thumb instruction to buf. */
17739 put_thumb32_insn (char * buf
, unsigned long insn
)
17741 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17742 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17746 output_inst (const char * str
)
17752 as_bad ("%s -- `%s'", inst
.error
, str
);
17757 output_relax_insn ();
17760 if (inst
.size
== 0)
17763 to
= frag_more (inst
.size
);
17764 /* PR 9814: Record the thumb mode into the current frag so that we know
17765 what type of NOP padding to use, if necessary. We override any previous
17766 setting so that if the mode has changed then the NOPS that we use will
17767 match the encoding of the last instruction in the frag. */
17768 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17770 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17772 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17773 put_thumb32_insn (to
, inst
.instruction
);
17775 else if (inst
.size
> INSN_SIZE
)
17777 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17778 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17779 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17782 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17784 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17785 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17786 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17789 dwarf2_emit_insn (inst
.size
);
17793 output_it_inst (int cond
, int mask
, char * to
)
17795 unsigned long instruction
= 0xbf00;
17798 instruction
|= mask
;
17799 instruction
|= cond
<< 4;
17803 to
= frag_more (2);
17805 dwarf2_emit_insn (2);
17809 md_number_to_chars (to
, instruction
, 2);
17814 /* Tag values used in struct asm_opcode's tag field. */
17817 OT_unconditional
, /* Instruction cannot be conditionalized.
17818 The ARM condition field is still 0xE. */
17819 OT_unconditionalF
, /* Instruction cannot be conditionalized
17820 and carries 0xF in its ARM condition field. */
17821 OT_csuffix
, /* Instruction takes a conditional suffix. */
17822 OT_csuffixF
, /* Some forms of the instruction take a conditional
17823 suffix, others place 0xF where the condition field
17825 OT_cinfix3
, /* Instruction takes a conditional infix,
17826 beginning at character index 3. (In
17827 unified mode, it becomes a suffix.) */
17828 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17829 tsts, cmps, cmns, and teqs. */
17830 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17831 character index 3, even in unified mode. Used for
17832 legacy instructions where suffix and infix forms
17833 may be ambiguous. */
17834 OT_csuf_or_in3
, /* Instruction takes either a conditional
17835 suffix or an infix at character index 3. */
17836 OT_odd_infix_unc
, /* This is the unconditional variant of an
17837 instruction that takes a conditional infix
17838 at an unusual position. In unified mode,
17839 this variant will accept a suffix. */
17840 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17841 are the conditional variants of instructions that
17842 take conditional infixes in unusual positions.
17843 The infix appears at character index
17844 (tag - OT_odd_infix_0). These are not accepted
17845 in unified mode. */
17848 /* Subroutine of md_assemble, responsible for looking up the primary
17849 opcode from the mnemonic the user wrote. STR points to the
17850 beginning of the mnemonic.
17852 This is not simply a hash table lookup, because of conditional
17853 variants. Most instructions have conditional variants, which are
17854 expressed with a _conditional affix_ to the mnemonic. If we were
17855 to encode each conditional variant as a literal string in the opcode
17856 table, it would have approximately 20,000 entries.
17858 Most mnemonics take this affix as a suffix, and in unified syntax,
17859 'most' is upgraded to 'all'. However, in the divided syntax, some
17860 instructions take the affix as an infix, notably the s-variants of
17861 the arithmetic instructions. Of those instructions, all but six
17862 have the infix appear after the third character of the mnemonic.
17864 Accordingly, the algorithm for looking up primary opcodes given
17867 1. Look up the identifier in the opcode table.
17868 If we find a match, go to step U.
17870 2. Look up the last two characters of the identifier in the
17871 conditions table. If we find a match, look up the first N-2
17872 characters of the identifier in the opcode table. If we
17873 find a match, go to step CE.
17875 3. Look up the fourth and fifth characters of the identifier in
17876 the conditions table. If we find a match, extract those
17877 characters from the identifier, and look up the remaining
17878 characters in the opcode table. If we find a match, go
17883 U. Examine the tag field of the opcode structure, in case this is
17884 one of the six instructions with its conditional infix in an
17885 unusual place. If it is, the tag tells us where to find the
17886 infix; look it up in the conditions table and set inst.cond
17887 accordingly. Otherwise, this is an unconditional instruction.
17888 Again set inst.cond accordingly. Return the opcode structure.
17890 CE. Examine the tag field to make sure this is an instruction that
17891 should receive a conditional suffix. If it is not, fail.
17892 Otherwise, set inst.cond from the suffix we already looked up,
17893 and return the opcode structure.
17895 CM. Examine the tag field to make sure this is an instruction that
17896 should receive a conditional infix after the third character.
17897 If it is not, fail. Otherwise, undo the edits to the current
17898 line of input and proceed as for case CE. */
17900 static const struct asm_opcode
*
17901 opcode_lookup (char **str
)
17905 const struct asm_opcode
*opcode
;
17906 const struct asm_cond
*cond
;
17909 /* Scan up to the end of the mnemonic, which must end in white space,
17910 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17911 for (base
= end
= *str
; *end
!= '\0'; end
++)
17912 if (*end
== ' ' || *end
== '.')
17918 /* Handle a possible width suffix and/or Neon type suffix. */
17923 /* The .w and .n suffixes are only valid if the unified syntax is in
17925 if (unified_syntax
&& end
[1] == 'w')
17927 else if (unified_syntax
&& end
[1] == 'n')
17932 inst
.vectype
.elems
= 0;
17934 *str
= end
+ offset
;
17936 if (end
[offset
] == '.')
17938 /* See if we have a Neon type suffix (possible in either unified or
17939 non-unified ARM syntax mode). */
17940 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17943 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17949 /* Look for unaffixed or special-case affixed mnemonic. */
17950 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17955 if (opcode
->tag
< OT_odd_infix_0
)
17957 inst
.cond
= COND_ALWAYS
;
17961 if (warn_on_deprecated
&& unified_syntax
)
17962 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17963 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17964 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17967 inst
.cond
= cond
->value
;
17971 /* Cannot have a conditional suffix on a mnemonic of less than two
17973 if (end
- base
< 3)
17976 /* Look for suffixed mnemonic. */
17978 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17979 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17981 if (opcode
&& cond
)
17984 switch (opcode
->tag
)
17986 case OT_cinfix3_legacy
:
17987 /* Ignore conditional suffixes matched on infix only mnemonics. */
17991 case OT_cinfix3_deprecated
:
17992 case OT_odd_infix_unc
:
17993 if (!unified_syntax
)
17995 /* Fall through. */
17999 case OT_csuf_or_in3
:
18000 inst
.cond
= cond
->value
;
18003 case OT_unconditional
:
18004 case OT_unconditionalF
:
18006 inst
.cond
= cond
->value
;
18009 /* Delayed diagnostic. */
18010 inst
.error
= BAD_COND
;
18011 inst
.cond
= COND_ALWAYS
;
18020 /* Cannot have a usual-position infix on a mnemonic of less than
18021 six characters (five would be a suffix). */
18022 if (end
- base
< 6)
18025 /* Look for infixed mnemonic in the usual position. */
18027 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18031 memcpy (save
, affix
, 2);
18032 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18033 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18035 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18036 memcpy (affix
, save
, 2);
18039 && (opcode
->tag
== OT_cinfix3
18040 || opcode
->tag
== OT_cinfix3_deprecated
18041 || opcode
->tag
== OT_csuf_or_in3
18042 || opcode
->tag
== OT_cinfix3_legacy
))
18045 if (warn_on_deprecated
&& unified_syntax
18046 && (opcode
->tag
== OT_cinfix3
18047 || opcode
->tag
== OT_cinfix3_deprecated
))
18048 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18050 inst
.cond
= cond
->value
;
18057 /* This function generates an initial IT instruction, leaving its block
18058 virtually open for the new instructions. Eventually,
18059 the mask will be updated by now_it_add_mask () each time
18060 a new instruction needs to be included in the IT block.
18061 Finally, the block is closed with close_automatic_it_block ().
18062 The block closure can be requested either from md_assemble (),
18063 a tencode (), or due to a label hook. */
18066 new_automatic_it_block (int cond
)
18068 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18069 now_it
.mask
= 0x18;
18071 now_it
.block_length
= 1;
18072 mapping_state (MAP_THUMB
);
18073 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18074 now_it
.warn_deprecated
= FALSE
;
18075 now_it
.insn_cond
= TRUE
;
18078 /* Close an automatic IT block.
18079 See comments in new_automatic_it_block (). */
18082 close_automatic_it_block (void)
18084 now_it
.mask
= 0x10;
18085 now_it
.block_length
= 0;
18088 /* Update the mask of the current automatically-generated IT
18089 instruction. See comments in new_automatic_it_block (). */
18092 now_it_add_mask (int cond
)
18094 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18095 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18096 | ((bitvalue) << (nbit)))
18097 const int resulting_bit
= (cond
& 1);
18099 now_it
.mask
&= 0xf;
18100 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18102 (5 - now_it
.block_length
));
18103 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18105 ((5 - now_it
.block_length
) - 1) );
18106 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18109 #undef SET_BIT_VALUE
18112 /* The IT blocks handling machinery is accessed through the these functions:
18113 it_fsm_pre_encode () from md_assemble ()
18114 set_it_insn_type () optional, from the tencode functions
18115 set_it_insn_type_last () ditto
18116 in_it_block () ditto
18117 it_fsm_post_encode () from md_assemble ()
18118 force_automatic_it_block_close () from label handling functions
18121 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18122 initializing the IT insn type with a generic initial value depending
18123 on the inst.condition.
18124 2) During the tencode function, two things may happen:
18125 a) The tencode function overrides the IT insn type by
18126 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18127 b) The tencode function queries the IT block state by
18128 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18130 Both set_it_insn_type and in_it_block run the internal FSM state
18131 handling function (handle_it_state), because: a) setting the IT insn
18132 type may incur in an invalid state (exiting the function),
18133 and b) querying the state requires the FSM to be updated.
18134 Specifically we want to avoid creating an IT block for conditional
18135 branches, so it_fsm_pre_encode is actually a guess and we can't
18136 determine whether an IT block is required until the tencode () routine
18137 has decided what type of instruction this actually it.
18138 Because of this, if set_it_insn_type and in_it_block have to be used,
18139 set_it_insn_type has to be called first.
18141 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18142 determines the insn IT type depending on the inst.cond code.
18143 When a tencode () routine encodes an instruction that can be
18144 either outside an IT block, or, in the case of being inside, has to be
18145 the last one, set_it_insn_type_last () will determine the proper
18146 IT instruction type based on the inst.cond code. Otherwise,
18147 set_it_insn_type can be called for overriding that logic or
18148 for covering other cases.
18150 Calling handle_it_state () may not transition the IT block state to
18151 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18152 still queried. Instead, if the FSM determines that the state should
18153 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18154 after the tencode () function: that's what it_fsm_post_encode () does.
18156 Since in_it_block () calls the state handling function to get an
18157 updated state, an error may occur (due to invalid insns combination).
18158 In that case, inst.error is set.
18159 Therefore, inst.error has to be checked after the execution of
18160 the tencode () routine.
18162 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18163 any pending state change (if any) that didn't take place in
18164 handle_it_state () as explained above. */
18167 it_fsm_pre_encode (void)
18169 if (inst
.cond
!= COND_ALWAYS
)
18170 inst
.it_insn_type
= INSIDE_IT_INSN
;
18172 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18174 now_it
.state_handled
= 0;
18177 /* IT state FSM handling function. */
18180 handle_it_state (void)
18182 now_it
.state_handled
= 1;
18183 now_it
.insn_cond
= FALSE
;
18185 switch (now_it
.state
)
18187 case OUTSIDE_IT_BLOCK
:
18188 switch (inst
.it_insn_type
)
18190 case OUTSIDE_IT_INSN
:
18193 case INSIDE_IT_INSN
:
18194 case INSIDE_IT_LAST_INSN
:
18195 if (thumb_mode
== 0)
18198 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18199 as_tsktsk (_("Warning: conditional outside an IT block"\
18204 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18205 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18207 /* Automatically generate the IT instruction. */
18208 new_automatic_it_block (inst
.cond
);
18209 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18210 close_automatic_it_block ();
18214 inst
.error
= BAD_OUT_IT
;
18220 case IF_INSIDE_IT_LAST_INSN
:
18221 case NEUTRAL_IT_INSN
:
18225 now_it
.state
= MANUAL_IT_BLOCK
;
18226 now_it
.block_length
= 0;
18231 case AUTOMATIC_IT_BLOCK
:
18232 /* Three things may happen now:
18233 a) We should increment current it block size;
18234 b) We should close current it block (closing insn or 4 insns);
18235 c) We should close current it block and start a new one (due
18236 to incompatible conditions or
18237 4 insns-length block reached). */
18239 switch (inst
.it_insn_type
)
18241 case OUTSIDE_IT_INSN
:
18242 /* The closure of the block shall happen immediately,
18243 so any in_it_block () call reports the block as closed. */
18244 force_automatic_it_block_close ();
18247 case INSIDE_IT_INSN
:
18248 case INSIDE_IT_LAST_INSN
:
18249 case IF_INSIDE_IT_LAST_INSN
:
18250 now_it
.block_length
++;
18252 if (now_it
.block_length
> 4
18253 || !now_it_compatible (inst
.cond
))
18255 force_automatic_it_block_close ();
18256 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18257 new_automatic_it_block (inst
.cond
);
18261 now_it
.insn_cond
= TRUE
;
18262 now_it_add_mask (inst
.cond
);
18265 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18266 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18267 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18268 close_automatic_it_block ();
18271 case NEUTRAL_IT_INSN
:
18272 now_it
.block_length
++;
18273 now_it
.insn_cond
= TRUE
;
18275 if (now_it
.block_length
> 4)
18276 force_automatic_it_block_close ();
18278 now_it_add_mask (now_it
.cc
& 1);
18282 close_automatic_it_block ();
18283 now_it
.state
= MANUAL_IT_BLOCK
;
18288 case MANUAL_IT_BLOCK
:
18290 /* Check conditional suffixes. */
18291 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18294 now_it
.mask
&= 0x1f;
18295 is_last
= (now_it
.mask
== 0x10);
18296 now_it
.insn_cond
= TRUE
;
18298 switch (inst
.it_insn_type
)
18300 case OUTSIDE_IT_INSN
:
18301 inst
.error
= BAD_NOT_IT
;
18304 case INSIDE_IT_INSN
:
18305 if (cond
!= inst
.cond
)
18307 inst
.error
= BAD_IT_COND
;
18312 case INSIDE_IT_LAST_INSN
:
18313 case IF_INSIDE_IT_LAST_INSN
:
18314 if (cond
!= inst
.cond
)
18316 inst
.error
= BAD_IT_COND
;
18321 inst
.error
= BAD_BRANCH
;
18326 case NEUTRAL_IT_INSN
:
18327 /* The BKPT instruction is unconditional even in an IT block. */
18331 inst
.error
= BAD_IT_IT
;
18341 struct depr_insn_mask
18343 unsigned long pattern
;
18344 unsigned long mask
;
18345 const char* description
;
18348 /* List of 16-bit instruction patterns deprecated in an IT block in
18350 static const struct depr_insn_mask depr_it_insns
[] = {
18351 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18352 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18353 { 0xa000, 0xb800, N_("ADR") },
18354 { 0x4800, 0xf800, N_("Literal loads") },
18355 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18356 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18357 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18358 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18359 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18364 it_fsm_post_encode (void)
18368 if (!now_it
.state_handled
)
18369 handle_it_state ();
18371 if (now_it
.insn_cond
18372 && !now_it
.warn_deprecated
18373 && warn_on_deprecated
18374 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18376 if (inst
.instruction
>= 0x10000)
18378 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18379 "deprecated in ARMv8"));
18380 now_it
.warn_deprecated
= TRUE
;
18384 const struct depr_insn_mask
*p
= depr_it_insns
;
18386 while (p
->mask
!= 0)
18388 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18390 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18391 "of the following class are deprecated in ARMv8: "
18392 "%s"), p
->description
);
18393 now_it
.warn_deprecated
= TRUE
;
18401 if (now_it
.block_length
> 1)
18403 as_tsktsk (_("IT blocks containing more than one conditional "
18404 "instruction are deprecated in ARMv8"));
18405 now_it
.warn_deprecated
= TRUE
;
18409 is_last
= (now_it
.mask
== 0x10);
18412 now_it
.state
= OUTSIDE_IT_BLOCK
;
18418 force_automatic_it_block_close (void)
18420 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18422 close_automatic_it_block ();
18423 now_it
.state
= OUTSIDE_IT_BLOCK
;
18431 if (!now_it
.state_handled
)
18432 handle_it_state ();
18434 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18437 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18438 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18439 here, hence the "known" in the function name. */
18442 known_t32_only_insn (const struct asm_opcode
*opcode
)
18444 /* Original Thumb-1 wide instruction. */
18445 if (opcode
->tencode
== do_t_blx
18446 || opcode
->tencode
== do_t_branch23
18447 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18448 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18451 /* Wide-only instruction added to ARMv8-M Baseline. */
18452 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18453 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18454 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18455 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18461 /* Whether wide instruction variant can be used if available for a valid OPCODE
18465 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18467 if (known_t32_only_insn (opcode
))
18470 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18471 of variant T3 of B.W is checked in do_t_branch. */
18472 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18473 && opcode
->tencode
== do_t_branch
)
18476 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18477 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18478 && opcode
->tencode
== do_t_mov_cmp
18479 /* Make sure CMP instruction is not affected. */
18480 && opcode
->aencode
== do_mov
)
18483 /* Wide instruction variants of all instructions with narrow *and* wide
18484 variants become available with ARMv6t2. Other opcodes are either
18485 narrow-only or wide-only and are thus available if OPCODE is valid. */
18486 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18489 /* OPCODE with narrow only instruction variant or wide variant not
18495 md_assemble (char *str
)
18498 const struct asm_opcode
* opcode
;
18500 /* Align the previous label if needed. */
18501 if (last_label_seen
!= NULL
)
18503 symbol_set_frag (last_label_seen
, frag_now
);
18504 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18505 S_SET_SEGMENT (last_label_seen
, now_seg
);
18508 memset (&inst
, '\0', sizeof (inst
));
18509 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18511 opcode
= opcode_lookup (&p
);
18514 /* It wasn't an instruction, but it might be a register alias of
18515 the form alias .req reg, or a Neon .dn/.qn directive. */
18516 if (! create_register_alias (str
, p
)
18517 && ! create_neon_reg_alias (str
, p
))
18518 as_bad (_("bad instruction `%s'"), str
);
18523 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18524 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18526 /* The value which unconditional instructions should have in place of the
18527 condition field. */
18528 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18532 arm_feature_set variant
;
18534 variant
= cpu_variant
;
18535 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18536 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18537 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18538 /* Check that this instruction is supported for this CPU. */
18539 if (!opcode
->tvariant
18540 || (thumb_mode
== 1
18541 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18543 if (opcode
->tencode
== do_t_swi
)
18544 as_bad (_("SVC is not permitted on this architecture"));
18546 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18549 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18550 && opcode
->tencode
!= do_t_branch
)
18552 as_bad (_("Thumb does not support conditional execution"));
18556 /* Two things are addressed here:
18557 1) Implicit require narrow instructions on Thumb-1.
18558 This avoids relaxation accidentally introducing Thumb-2
18560 2) Reject wide instructions in non Thumb-2 cores.
18562 Only instructions with narrow and wide variants need to be handled
18563 but selecting all non wide-only instructions is easier. */
18564 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18565 && !t32_insn_ok (variant
, opcode
))
18567 if (inst
.size_req
== 0)
18569 else if (inst
.size_req
== 4)
18571 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18572 as_bad (_("selected processor does not support 32bit wide "
18573 "variant of instruction `%s'"), str
);
18575 as_bad (_("selected processor does not support `%s' in "
18576 "Thumb-2 mode"), str
);
18581 inst
.instruction
= opcode
->tvalue
;
18583 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18585 /* Prepare the it_insn_type for those encodings that don't set
18587 it_fsm_pre_encode ();
18589 opcode
->tencode ();
18591 it_fsm_post_encode ();
18594 if (!(inst
.error
|| inst
.relax
))
18596 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18597 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18598 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18600 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18605 /* Something has gone badly wrong if we try to relax a fixed size
18607 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18609 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18610 *opcode
->tvariant
);
18611 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18612 set those bits when Thumb-2 32-bit instructions are seen. The impact
18613 of relaxable instructions will be considered later after we finish all
18615 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18616 variant
= arm_arch_none
;
18618 variant
= cpu_variant
;
18619 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18620 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18623 check_neon_suffixes
;
18627 mapping_state (MAP_THUMB
);
18630 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18634 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18635 is_bx
= (opcode
->aencode
== do_bx
);
18637 /* Check that this instruction is supported for this CPU. */
18638 if (!(is_bx
&& fix_v4bx
)
18639 && !(opcode
->avariant
&&
18640 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18642 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18647 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18651 inst
.instruction
= opcode
->avalue
;
18652 if (opcode
->tag
== OT_unconditionalF
)
18653 inst
.instruction
|= 0xFU
<< 28;
18655 inst
.instruction
|= inst
.cond
<< 28;
18656 inst
.size
= INSN_SIZE
;
18657 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18659 it_fsm_pre_encode ();
18660 opcode
->aencode ();
18661 it_fsm_post_encode ();
18663 /* Arm mode bx is marked as both v4T and v5 because it's still required
18664 on a hypothetical non-thumb v5 core. */
18666 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18668 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18669 *opcode
->avariant
);
18671 check_neon_suffixes
;
18675 mapping_state (MAP_ARM
);
18680 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18688 check_it_blocks_finished (void)
18693 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18694 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18695 == MANUAL_IT_BLOCK
)
18697 as_warn (_("section '%s' finished with an open IT block."),
18701 if (now_it
.state
== MANUAL_IT_BLOCK
)
18702 as_warn (_("file finished with an open IT block."));
18706 /* Various frobbings of labels and their addresses. */
18709 arm_start_line_hook (void)
18711 last_label_seen
= NULL
;
18715 arm_frob_label (symbolS
* sym
)
18717 last_label_seen
= sym
;
18719 ARM_SET_THUMB (sym
, thumb_mode
);
18721 #if defined OBJ_COFF || defined OBJ_ELF
18722 ARM_SET_INTERWORK (sym
, support_interwork
);
18725 force_automatic_it_block_close ();
18727 /* Note - do not allow local symbols (.Lxxx) to be labelled
18728 as Thumb functions. This is because these labels, whilst
18729 they exist inside Thumb code, are not the entry points for
18730 possible ARM->Thumb calls. Also, these labels can be used
18731 as part of a computed goto or switch statement. eg gcc
18732 can generate code that looks like this:
18734 ldr r2, [pc, .Laaa]
18744 The first instruction loads the address of the jump table.
18745 The second instruction converts a table index into a byte offset.
18746 The third instruction gets the jump address out of the table.
18747 The fourth instruction performs the jump.
18749 If the address stored at .Laaa is that of a symbol which has the
18750 Thumb_Func bit set, then the linker will arrange for this address
18751 to have the bottom bit set, which in turn would mean that the
18752 address computation performed by the third instruction would end
18753 up with the bottom bit set. Since the ARM is capable of unaligned
18754 word loads, the instruction would then load the incorrect address
18755 out of the jump table, and chaos would ensue. */
18756 if (label_is_thumb_function_name
18757 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18758 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18760 /* When the address of a Thumb function is taken the bottom
18761 bit of that address should be set. This will allow
18762 interworking between Arm and Thumb functions to work
18765 THUMB_SET_FUNC (sym
, 1);
18767 label_is_thumb_function_name
= FALSE
;
18770 dwarf2_emit_label (sym
);
18774 arm_data_in_code (void)
18776 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18778 *input_line_pointer
= '/';
18779 input_line_pointer
+= 5;
18780 *input_line_pointer
= 0;
18788 arm_canonicalize_symbol_name (char * name
)
18792 if (thumb_mode
&& (len
= strlen (name
)) > 5
18793 && streq (name
+ len
- 5, "/data"))
18794 *(name
+ len
- 5) = 0;
18799 /* Table of all register names defined by default. The user can
18800 define additional names with .req. Note that all register names
18801 should appear in both upper and lowercase variants. Some registers
18802 also have mixed-case names. */
18804 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18805 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18806 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18807 #define REGSET(p,t) \
18808 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18809 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18810 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18811 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18812 #define REGSETH(p,t) \
18813 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18814 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18815 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18816 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18817 #define REGSET2(p,t) \
18818 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18819 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18820 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18821 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18822 #define SPLRBANK(base,bank,t) \
18823 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18824 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18825 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18826 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18827 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18828 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18830 static const struct reg_entry reg_names
[] =
18832 /* ARM integer registers. */
18833 REGSET(r
, RN
), REGSET(R
, RN
),
18835 /* ATPCS synonyms. */
18836 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18837 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18838 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18840 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18841 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18842 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18844 /* Well-known aliases. */
18845 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18846 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18848 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18849 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18851 /* Coprocessor numbers. */
18852 REGSET(p
, CP
), REGSET(P
, CP
),
18854 /* Coprocessor register numbers. The "cr" variants are for backward
18856 REGSET(c
, CN
), REGSET(C
, CN
),
18857 REGSET(cr
, CN
), REGSET(CR
, CN
),
18859 /* ARM banked registers. */
18860 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18861 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18862 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18863 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18864 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18865 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18866 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18868 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18869 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18870 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18871 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18872 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18873 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18874 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18875 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18877 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18878 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18879 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18880 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18881 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18882 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18883 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18884 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18885 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18887 /* FPA registers. */
18888 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18889 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18891 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18892 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18894 /* VFP SP registers. */
18895 REGSET(s
,VFS
), REGSET(S
,VFS
),
18896 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18898 /* VFP DP Registers. */
18899 REGSET(d
,VFD
), REGSET(D
,VFD
),
18900 /* Extra Neon DP registers. */
18901 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18903 /* Neon QP registers. */
18904 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18906 /* VFP control registers. */
18907 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18908 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18909 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18910 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18911 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18912 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18914 /* Maverick DSP coprocessor registers. */
18915 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18916 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18918 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18919 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18920 REGDEF(dspsc
,0,DSPSC
),
18922 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18923 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18924 REGDEF(DSPSC
,0,DSPSC
),
18926 /* iWMMXt data registers - p0, c0-15. */
18927 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18929 /* iWMMXt control registers - p1, c0-3. */
18930 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18931 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18932 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18933 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18935 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18936 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18937 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18938 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18939 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18941 /* XScale accumulator registers. */
18942 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18948 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18949 within psr_required_here. */
18950 static const struct asm_psr psrs
[] =
18952 /* Backward compatibility notation. Note that "all" is no longer
18953 truly all possible PSR bits. */
18954 {"all", PSR_c
| PSR_f
},
18958 /* Individual flags. */
18964 /* Combinations of flags. */
18965 {"fs", PSR_f
| PSR_s
},
18966 {"fx", PSR_f
| PSR_x
},
18967 {"fc", PSR_f
| PSR_c
},
18968 {"sf", PSR_s
| PSR_f
},
18969 {"sx", PSR_s
| PSR_x
},
18970 {"sc", PSR_s
| PSR_c
},
18971 {"xf", PSR_x
| PSR_f
},
18972 {"xs", PSR_x
| PSR_s
},
18973 {"xc", PSR_x
| PSR_c
},
18974 {"cf", PSR_c
| PSR_f
},
18975 {"cs", PSR_c
| PSR_s
},
18976 {"cx", PSR_c
| PSR_x
},
18977 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18978 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18979 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18980 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18981 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18982 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18983 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18984 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18985 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18986 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18987 {"scf", PSR_s
| PSR_c
| PSR_f
},
18988 {"scx", PSR_s
| PSR_c
| PSR_x
},
18989 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18990 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18991 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18992 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18993 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18994 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18995 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18996 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18997 {"csf", PSR_c
| PSR_s
| PSR_f
},
18998 {"csx", PSR_c
| PSR_s
| PSR_x
},
18999 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19000 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19001 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19002 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19003 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19004 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19005 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19006 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19007 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19008 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19009 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19010 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19011 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19012 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19013 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19014 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19015 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19016 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19017 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19018 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19019 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19020 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19021 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19022 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19023 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19024 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19027 /* Table of V7M psr names. */
19028 static const struct asm_psr v7m_psrs
[] =
19030 {"apsr", 0x0 }, {"APSR", 0x0 },
19031 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19032 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19033 {"psr", 0x3 }, {"PSR", 0x3 },
19034 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19035 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19036 {"epsr", 0x6 }, {"EPSR", 0x6 },
19037 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19038 {"msp", 0x8 }, {"MSP", 0x8 },
19039 {"psp", 0x9 }, {"PSP", 0x9 },
19040 {"msplim", 0xa }, {"MSPLIM", 0xa },
19041 {"psplim", 0xb }, {"PSPLIM", 0xb },
19042 {"primask", 0x10}, {"PRIMASK", 0x10},
19043 {"basepri", 0x11}, {"BASEPRI", 0x11},
19044 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19045 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19046 {"control", 0x14}, {"CONTROL", 0x14},
19047 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19048 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19049 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19050 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19051 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19052 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19053 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19054 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19055 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19058 /* Table of all shift-in-operand names. */
19059 static const struct asm_shift_name shift_names
[] =
19061 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19062 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19063 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19064 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19065 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19066 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19069 /* Table of all explicit relocation names. */
19071 static struct reloc_entry reloc_names
[] =
19073 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19074 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19075 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19076 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19077 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19078 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19079 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19080 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19081 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19082 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19083 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19084 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19085 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19086 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19087 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19088 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19089 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19090 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19094 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19095 static const struct asm_cond conds
[] =
19099 {"cs", 0x2}, {"hs", 0x2},
19100 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19114 #define UL_BARRIER(L,U,CODE,FEAT) \
19115 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19116 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19118 static struct asm_barrier_opt barrier_opt_names
[] =
19120 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19121 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19122 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19123 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19124 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19125 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19126 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19127 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19128 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19129 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19130 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19131 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19132 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19133 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19134 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19135 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19140 /* Table of ARM-format instructions. */
19142 /* Macros for gluing together operand strings. N.B. In all cases
19143 other than OPS0, the trailing OP_stop comes from default
19144 zero-initialization of the unspecified elements of the array. */
19145 #define OPS0() { OP_stop, }
19146 #define OPS1(a) { OP_##a, }
19147 #define OPS2(a,b) { OP_##a,OP_##b, }
19148 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19149 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19150 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19151 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19153 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19154 This is useful when mixing operands for ARM and THUMB, i.e. using the
19155 MIX_ARM_THUMB_OPERANDS macro.
19156 In order to use these macros, prefix the number of operands with _
19158 #define OPS_1(a) { a, }
19159 #define OPS_2(a,b) { a,b, }
19160 #define OPS_3(a,b,c) { a,b,c, }
19161 #define OPS_4(a,b,c,d) { a,b,c,d, }
19162 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19163 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19165 /* These macros abstract out the exact format of the mnemonic table and
19166 save some repeated characters. */
19168 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19169 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19170 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19171 THUMB_VARIANT, do_##ae, do_##te }
19173 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19174 a T_MNEM_xyz enumerator. */
19175 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19176 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19177 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19178 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19180 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19181 infix after the third character. */
19182 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19183 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19184 THUMB_VARIANT, do_##ae, do_##te }
19185 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19186 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19187 THUMB_VARIANT, do_##ae, do_##te }
19188 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19189 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19190 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19191 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19192 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19193 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19194 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19195 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19197 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19198 field is still 0xE. Many of the Thumb variants can be executed
19199 conditionally, so this is checked separately. */
19200 #define TUE(mnem, op, top, nops, ops, ae, te) \
19201 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19202 THUMB_VARIANT, do_##ae, do_##te }
19204 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19205 Used by mnemonics that have very minimal differences in the encoding for
19206 ARM and Thumb variants and can be handled in a common function. */
19207 #define TUEc(mnem, op, top, nops, ops, en) \
19208 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19209 THUMB_VARIANT, do_##en, do_##en }
19211 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19212 condition code field. */
19213 #define TUF(mnem, op, top, nops, ops, ae, te) \
19214 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19215 THUMB_VARIANT, do_##ae, do_##te }
19217 /* ARM-only variants of all the above. */
19218 #define CE(mnem, op, nops, ops, ae) \
19219 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19221 #define C3(mnem, op, nops, ops, ae) \
19222 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19224 /* Legacy mnemonics that always have conditional infix after the third
19226 #define CL(mnem, op, nops, ops, ae) \
19227 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19228 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19230 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19231 #define cCE(mnem, op, nops, ops, ae) \
19232 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19234 /* Legacy coprocessor instructions where conditional infix and conditional
19235 suffix are ambiguous. For consistency this includes all FPA instructions,
19236 not just the potentially ambiguous ones. */
19237 #define cCL(mnem, op, nops, ops, ae) \
19238 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19239 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19241 /* Coprocessor, takes either a suffix or a position-3 infix
19242 (for an FPA corner case). */
19243 #define C3E(mnem, op, nops, ops, ae) \
19244 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19245 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19247 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19248 { m1 #m2 m3, OPS##nops ops, \
19249 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19250 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19252 #define CM(m1, m2, op, nops, ops, ae) \
19253 xCM_ (m1, , m2, op, nops, ops, ae), \
19254 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19255 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19256 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19257 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19258 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19259 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19260 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19261 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19262 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19263 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19264 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19265 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19266 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19267 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19268 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19269 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19270 xCM_ (m1, le, m2, op, nops, ops, ae), \
19271 xCM_ (m1, al, m2, op, nops, ops, ae)
19273 #define UE(mnem, op, nops, ops, ae) \
19274 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19276 #define UF(mnem, op, nops, ops, ae) \
19277 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19279 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19280 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19281 use the same encoding function for each. */
19282 #define NUF(mnem, op, nops, ops, enc) \
19283 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19284 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19286 /* Neon data processing, version which indirects through neon_enc_tab for
19287 the various overloaded versions of opcodes. */
19288 #define nUF(mnem, op, nops, ops, enc) \
19289 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19290 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19292 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19294 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19295 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19296 THUMB_VARIANT, do_##enc, do_##enc }
19298 #define NCE(mnem, op, nops, ops, enc) \
19299 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19301 #define NCEF(mnem, op, nops, ops, enc) \
19302 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19304 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19305 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19306 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19307 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19309 #define nCE(mnem, op, nops, ops, enc) \
19310 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19312 #define nCEF(mnem, op, nops, ops, enc) \
19313 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19317 static const struct asm_opcode insns
[] =
19319 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19320 #define THUMB_VARIANT & arm_ext_v4t
19321 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19322 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19323 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19324 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19325 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19326 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19327 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19328 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19329 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19330 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19331 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19332 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19333 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19334 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19335 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19336 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19338 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19339 for setting PSR flag bits. They are obsolete in V6 and do not
19340 have Thumb equivalents. */
19341 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19342 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19343 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19344 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19345 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19346 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19347 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19348 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19349 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19351 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19352 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19353 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19354 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19356 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19357 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19358 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19360 OP_ADDRGLDR
),ldst
, t_ldst
),
19361 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19363 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19364 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19365 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19366 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19367 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19368 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19370 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19371 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19374 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19375 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19376 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19377 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19379 /* Thumb-compatibility pseudo ops. */
19380 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19381 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19382 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19383 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19384 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19385 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19386 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19387 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19388 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19389 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19390 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19391 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19393 /* These may simplify to neg. */
19394 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19395 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19397 #undef THUMB_VARIANT
19398 #define THUMB_VARIANT & arm_ext_os
19400 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19401 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19403 #undef THUMB_VARIANT
19404 #define THUMB_VARIANT & arm_ext_v6
19406 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19408 /* V1 instructions with no Thumb analogue prior to V6T2. */
19409 #undef THUMB_VARIANT
19410 #define THUMB_VARIANT & arm_ext_v6t2
19412 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19413 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19414 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19416 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19417 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19418 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19419 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19421 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19422 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19424 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19425 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19427 /* V1 instructions with no Thumb analogue at all. */
19428 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19429 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19431 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19432 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19433 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19434 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19435 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19436 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19437 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19438 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19441 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19442 #undef THUMB_VARIANT
19443 #define THUMB_VARIANT & arm_ext_v4t
19445 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19446 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19448 #undef THUMB_VARIANT
19449 #define THUMB_VARIANT & arm_ext_v6t2
19451 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19452 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19454 /* Generic coprocessor instructions. */
19455 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19456 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19457 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19458 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19459 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19460 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19461 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19464 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19466 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19467 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19470 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19471 #undef THUMB_VARIANT
19472 #define THUMB_VARIANT & arm_ext_msr
19474 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19475 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19478 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19479 #undef THUMB_VARIANT
19480 #define THUMB_VARIANT & arm_ext_v6t2
19482 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19483 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19484 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19485 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19486 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19487 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19488 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19489 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19492 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19493 #undef THUMB_VARIANT
19494 #define THUMB_VARIANT & arm_ext_v4t
19496 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19497 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19498 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19499 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19500 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19501 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19504 #define ARM_VARIANT & arm_ext_v4t_5
19506 /* ARM Architecture 4T. */
19507 /* Note: bx (and blx) are required on V5, even if the processor does
19508 not support Thumb. */
19509 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19512 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19513 #undef THUMB_VARIANT
19514 #define THUMB_VARIANT & arm_ext_v5t
19516 /* Note: blx has 2 variants; the .value coded here is for
19517 BLX(2). Only this variant has conditional execution. */
19518 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19519 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19521 #undef THUMB_VARIANT
19522 #define THUMB_VARIANT & arm_ext_v6t2
19524 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19525 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19526 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19527 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19528 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19529 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19530 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19531 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19534 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19535 #undef THUMB_VARIANT
19536 #define THUMB_VARIANT & arm_ext_v5exp
19538 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19539 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19540 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19541 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19543 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19544 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19546 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19547 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19548 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19549 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19551 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19552 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19553 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19554 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19556 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19557 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19559 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19560 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19561 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19562 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19565 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19566 #undef THUMB_VARIANT
19567 #define THUMB_VARIANT & arm_ext_v6t2
19569 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19570 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19572 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19573 ADDRGLDRS
), ldrd
, t_ldstd
),
19575 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19576 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19579 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19581 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19584 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19585 #undef THUMB_VARIANT
19586 #define THUMB_VARIANT & arm_ext_v6
19588 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19589 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19590 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19591 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19592 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19593 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19594 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19595 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19596 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19597 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19599 #undef THUMB_VARIANT
19600 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19602 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19603 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19605 #undef THUMB_VARIANT
19606 #define THUMB_VARIANT & arm_ext_v6t2
19608 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19609 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19611 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19612 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19614 /* ARM V6 not included in V7M. */
19615 #undef THUMB_VARIANT
19616 #define THUMB_VARIANT & arm_ext_v6_notm
19617 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19618 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19619 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19620 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19621 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19622 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19623 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19624 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19625 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19626 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19627 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19628 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19629 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19630 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19631 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19632 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19633 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19634 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19635 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19637 /* ARM V6 not included in V7M (eg. integer SIMD). */
19638 #undef THUMB_VARIANT
19639 #define THUMB_VARIANT & arm_ext_v6_dsp
19640 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19641 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19642 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19643 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19644 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19645 /* Old name for QASX. */
19646 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19647 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19648 /* Old name for QSAX. */
19649 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19650 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19651 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19652 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19653 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19654 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19655 /* Old name for SASX. */
19656 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19657 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19658 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19659 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19660 /* Old name for SHASX. */
19661 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19662 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19663 /* Old name for SHSAX. */
19664 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19665 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19666 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19667 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19668 /* Old name for SSAX. */
19669 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19670 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19671 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19672 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19673 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19674 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19675 /* Old name for UASX. */
19676 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19677 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19678 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19679 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19680 /* Old name for UHASX. */
19681 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19682 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19683 /* Old name for UHSAX. */
19684 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19685 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19686 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19687 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19688 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19689 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19690 /* Old name for UQASX. */
19691 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19692 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19693 /* Old name for UQSAX. */
19694 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19695 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19696 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19697 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19698 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19699 /* Old name for USAX. */
19700 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19701 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19702 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19703 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19704 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19705 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19706 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19707 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19708 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19709 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19710 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19711 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19712 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19713 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19714 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19715 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19716 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19717 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19718 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19719 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19720 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19721 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19722 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19723 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19724 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19725 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19726 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19727 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19728 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19729 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19730 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19731 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19732 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19733 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19736 #define ARM_VARIANT & arm_ext_v6k
19737 #undef THUMB_VARIANT
19738 #define THUMB_VARIANT & arm_ext_v6k
19740 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19741 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19742 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19743 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19745 #undef THUMB_VARIANT
19746 #define THUMB_VARIANT & arm_ext_v6_notm
19747 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19749 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19750 RRnpcb
), strexd
, t_strexd
),
19752 #undef THUMB_VARIANT
19753 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19754 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19756 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19758 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19760 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19762 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19765 #define ARM_VARIANT & arm_ext_sec
19766 #undef THUMB_VARIANT
19767 #define THUMB_VARIANT & arm_ext_sec
19769 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19772 #define ARM_VARIANT & arm_ext_virt
19773 #undef THUMB_VARIANT
19774 #define THUMB_VARIANT & arm_ext_virt
19776 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19777 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19780 #define ARM_VARIANT & arm_ext_pan
19781 #undef THUMB_VARIANT
19782 #define THUMB_VARIANT & arm_ext_pan
19784 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19787 #define ARM_VARIANT & arm_ext_v6t2
19788 #undef THUMB_VARIANT
19789 #define THUMB_VARIANT & arm_ext_v6t2
19791 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19792 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19793 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19794 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19796 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19797 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19799 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19800 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19801 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19802 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19804 #undef THUMB_VARIANT
19805 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19806 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19807 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19809 /* Thumb-only instructions. */
19811 #define ARM_VARIANT NULL
19812 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19813 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19815 /* ARM does not really have an IT instruction, so always allow it.
19816 The opcode is copied from Thumb in order to allow warnings in
19817 -mimplicit-it=[never | arm] modes. */
19819 #define ARM_VARIANT & arm_ext_v1
19820 #undef THUMB_VARIANT
19821 #define THUMB_VARIANT & arm_ext_v6t2
19823 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19824 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19825 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19826 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19827 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19828 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19829 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19830 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19831 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19832 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19833 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19834 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19835 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19836 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19837 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19838 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19839 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19840 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19842 /* Thumb2 only instructions. */
19844 #define ARM_VARIANT NULL
19846 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19847 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19848 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19849 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19850 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19851 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19853 /* Hardware division instructions. */
19855 #define ARM_VARIANT & arm_ext_adiv
19856 #undef THUMB_VARIANT
19857 #define THUMB_VARIANT & arm_ext_div
19859 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19860 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19862 /* ARM V6M/V7 instructions. */
19864 #define ARM_VARIANT & arm_ext_barrier
19865 #undef THUMB_VARIANT
19866 #define THUMB_VARIANT & arm_ext_barrier
19868 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19869 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19870 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19872 /* ARM V7 instructions. */
19874 #define ARM_VARIANT & arm_ext_v7
19875 #undef THUMB_VARIANT
19876 #define THUMB_VARIANT & arm_ext_v7
19878 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19879 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19882 #define ARM_VARIANT & arm_ext_mp
19883 #undef THUMB_VARIANT
19884 #define THUMB_VARIANT & arm_ext_mp
19886 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19888 /* AArchv8 instructions. */
19890 #define ARM_VARIANT & arm_ext_v8
19892 /* Instructions shared between armv8-a and armv8-m. */
19893 #undef THUMB_VARIANT
19894 #define THUMB_VARIANT & arm_ext_atomics
19896 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19897 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19898 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19899 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19900 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19901 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19902 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19903 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19904 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19905 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19907 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19909 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19911 #undef THUMB_VARIANT
19912 #define THUMB_VARIANT & arm_ext_v8
19914 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19915 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19916 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19918 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19920 /* ARMv8 T32 only. */
19922 #define ARM_VARIANT NULL
19923 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19924 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19925 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19927 /* FP for ARMv8. */
19929 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19930 #undef THUMB_VARIANT
19931 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19933 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19934 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19935 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19936 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19937 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19938 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19939 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19940 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19941 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19942 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19943 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19944 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19945 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19946 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19947 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19948 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19949 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19951 /* Crypto v1 extensions. */
19953 #define ARM_VARIANT & fpu_crypto_ext_armv8
19954 #undef THUMB_VARIANT
19955 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19957 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19958 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19959 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19960 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19961 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19962 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19963 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19964 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19965 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19966 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19967 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19968 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19969 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19970 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19973 #define ARM_VARIANT & crc_ext_armv8
19974 #undef THUMB_VARIANT
19975 #define THUMB_VARIANT & crc_ext_armv8
19976 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19977 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19978 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19979 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19980 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19981 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19983 /* ARMv8.2 RAS extension. */
19985 #define ARM_VARIANT & arm_ext_ras
19986 #undef THUMB_VARIANT
19987 #define THUMB_VARIANT & arm_ext_ras
19988 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19991 #define ARM_VARIANT & arm_ext_v8_3
19992 #undef THUMB_VARIANT
19993 #define THUMB_VARIANT & arm_ext_v8_3
19994 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19995 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19996 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19999 #define ARM_VARIANT & fpu_neon_ext_dotprod
20000 #undef THUMB_VARIANT
20001 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20002 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20003 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20006 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20007 #undef THUMB_VARIANT
20008 #define THUMB_VARIANT NULL
20010 cCE("wfs", e200110
, 1, (RR
), rd
),
20011 cCE("rfs", e300110
, 1, (RR
), rd
),
20012 cCE("wfc", e400110
, 1, (RR
), rd
),
20013 cCE("rfc", e500110
, 1, (RR
), rd
),
20015 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20016 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20017 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20018 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20020 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20021 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20022 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20023 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20025 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20036 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20114 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20117 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20120 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20126 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20127 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20129 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20130 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20131 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20132 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20133 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20134 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20135 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20136 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20137 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20138 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20139 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20140 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20142 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20143 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20144 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20145 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20146 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20147 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20148 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20149 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20150 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20151 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20152 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20153 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20155 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20156 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20157 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20158 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20159 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20160 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20161 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20162 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20163 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20164 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20165 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20166 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20168 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20169 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20170 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20171 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20172 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20173 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20174 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20175 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20176 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20177 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20178 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20179 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20181 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20182 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20183 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20184 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20185 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20186 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20187 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20188 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20189 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20190 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20191 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20192 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20194 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20195 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20196 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20197 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20198 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20199 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20200 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20201 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20202 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20203 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20204 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20205 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20207 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20208 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20209 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20210 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20211 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20212 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20213 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20214 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20215 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20216 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20217 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20218 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20220 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20221 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20222 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20223 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20224 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20225 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20226 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20227 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20228 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20229 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20230 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20231 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20233 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20244 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20283 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20286 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20289 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20295 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20296 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20298 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20299 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20300 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20301 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20302 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20303 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20304 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20305 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20306 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20307 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20308 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20309 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20311 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20312 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20313 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20314 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20315 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20316 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20317 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20318 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20319 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20320 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20321 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20322 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20324 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20325 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20326 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20327 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20328 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20329 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20330 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20331 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20332 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20333 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20334 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20335 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20337 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20338 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20339 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20340 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20341 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20342 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20343 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20344 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20345 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20346 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20347 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20348 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20350 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20351 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20352 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20353 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20354 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20355 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20356 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20357 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20358 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20359 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20360 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20361 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20363 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20364 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20365 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20366 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20367 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20368 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20369 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20370 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20371 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20372 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20373 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20374 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20376 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20377 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20378 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20379 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20380 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20381 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20382 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20383 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20384 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20385 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20386 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20387 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20389 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20390 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20391 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20392 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20393 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20394 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20395 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20396 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20397 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20398 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20399 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20400 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20402 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20403 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20404 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20405 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20407 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20408 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20409 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20410 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20411 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20412 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20413 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20414 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20415 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20416 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20417 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20418 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20420 /* The implementation of the FIX instruction is broken on some
20421 assemblers, in that it accepts a precision specifier as well as a
20422 rounding specifier, despite the fact that this is meaningless.
20423 To be more compatible, we accept it as well, though of course it
20424 does not set any bits. */
20425 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20426 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20427 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20428 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20429 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20430 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20431 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20432 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20433 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20434 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20435 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20436 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20437 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20439 /* Instructions that were new with the real FPA, call them V2. */
20441 #define ARM_VARIANT & fpu_fpa_ext_v2
20443 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20444 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20445 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20446 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20447 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20448 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20451 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20453 /* Moves and type conversions. */
20454 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20455 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20456 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20457 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20458 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20459 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20460 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20461 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20462 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20463 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20464 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20465 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20466 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20467 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20469 /* Memory operations. */
20470 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20471 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20472 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20473 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20474 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20475 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20476 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20477 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20478 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20479 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20480 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20481 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20482 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20483 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20484 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20485 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20486 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20487 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20489 /* Monadic operations. */
20490 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20491 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20492 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20494 /* Dyadic operations. */
20495 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20496 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20497 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20498 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20499 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20500 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20501 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20502 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20503 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20506 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20507 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20508 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20509 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20511 /* Double precision load/store are still present on single precision
20512 implementations. */
20513 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20514 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20515 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20516 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20517 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20518 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20519 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20520 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20521 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20522 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20525 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20527 /* Moves and type conversions. */
20528 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20529 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20530 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20531 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20532 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20533 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20534 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20535 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20536 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20537 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20538 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20539 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20540 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20542 /* Monadic operations. */
20543 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20544 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20545 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20547 /* Dyadic operations. */
20548 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20549 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20550 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20551 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20552 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20553 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20554 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20555 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20556 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20559 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20560 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20561 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20562 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20565 #define ARM_VARIANT & fpu_vfp_ext_v2
20567 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20568 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20569 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20570 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20572 /* Instructions which may belong to either the Neon or VFP instruction sets.
20573 Individual encoder functions perform additional architecture checks. */
20575 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20576 #undef THUMB_VARIANT
20577 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20579 /* These mnemonics are unique to VFP. */
20580 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20581 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20582 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20583 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20584 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20585 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20586 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20587 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20588 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20589 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20591 /* Mnemonics shared by Neon and VFP. */
20592 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20593 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20594 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20596 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20597 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20599 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20600 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20602 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20603 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20604 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20605 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20606 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20607 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20608 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20609 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20611 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20612 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20613 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20614 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20617 /* NOTE: All VMOV encoding is special-cased! */
20618 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20619 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20622 #define ARM_VARIANT & arm_ext_fp16
20623 #undef THUMB_VARIANT
20624 #define THUMB_VARIANT & arm_ext_fp16
20625 /* New instructions added from v8.2, allowing the extraction and insertion of
20626 the upper 16 bits of a 32-bit vector register. */
20627 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20628 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20630 #undef THUMB_VARIANT
20631 #define THUMB_VARIANT & fpu_neon_ext_v1
20633 #define ARM_VARIANT & fpu_neon_ext_v1
20635 /* Data processing with three registers of the same length. */
20636 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20637 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20638 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20639 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20640 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20641 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20642 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20643 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20644 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20645 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20646 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20647 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20648 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20649 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20650 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20651 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20652 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20653 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20654 /* If not immediate, fall back to neon_dyadic_i64_su.
20655 shl_imm should accept I8 I16 I32 I64,
20656 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20657 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20658 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20659 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20660 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20661 /* Logic ops, types optional & ignored. */
20662 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20663 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20664 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20665 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20666 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20667 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20668 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20669 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20670 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20671 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20672 /* Bitfield ops, untyped. */
20673 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20674 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20675 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20676 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20677 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20678 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20679 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20680 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20681 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20682 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20683 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20684 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20685 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20686 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20687 back to neon_dyadic_if_su. */
20688 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20689 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20690 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20691 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20692 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20693 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20694 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20695 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20696 /* Comparison. Type I8 I16 I32 F32. */
20697 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20698 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20699 /* As above, D registers only. */
20700 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20701 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20702 /* Int and float variants, signedness unimportant. */
20703 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20704 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20705 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20706 /* Add/sub take types I8 I16 I32 I64 F32. */
20707 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20708 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20709 /* vtst takes sizes 8, 16, 32. */
20710 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20711 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20712 /* VMUL takes I8 I16 I32 F32 P8. */
20713 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20714 /* VQD{R}MULH takes S16 S32. */
20715 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20716 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20717 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20718 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20719 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20720 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20721 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20722 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20723 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20724 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20725 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20726 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20727 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20728 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20729 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20730 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20731 /* ARM v8.1 extension. */
20732 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20733 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20734 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20735 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20737 /* Two address, int/float. Types S8 S16 S32 F32. */
20738 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20739 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20741 /* Data processing with two registers and a shift amount. */
20742 /* Right shifts, and variants with rounding.
20743 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20744 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20745 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20746 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20747 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20748 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20749 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20750 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20751 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20752 /* Shift and insert. Sizes accepted 8 16 32 64. */
20753 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20754 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20755 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20756 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20757 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20758 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20759 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20760 /* Right shift immediate, saturating & narrowing, with rounding variants.
20761 Types accepted S16 S32 S64 U16 U32 U64. */
20762 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20763 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20764 /* As above, unsigned. Types accepted S16 S32 S64. */
20765 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20766 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20767 /* Right shift narrowing. Types accepted I16 I32 I64. */
20768 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20769 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20770 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20771 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20772 /* CVT with optional immediate for fixed-point variant. */
20773 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20775 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20776 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20778 /* Data processing, three registers of different lengths. */
20779 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20780 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20781 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20782 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20783 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20784 /* If not scalar, fall back to neon_dyadic_long.
20785 Vector types as above, scalar types S16 S32 U16 U32. */
20786 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20787 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20788 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20789 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20790 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20791 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20792 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20793 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20794 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20795 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20796 /* Saturating doubling multiplies. Types S16 S32. */
20797 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20798 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20799 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20800 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20801 S16 S32 U16 U32. */
20802 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20804 /* Extract. Size 8. */
20805 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20806 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20808 /* Two registers, miscellaneous. */
20809 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20810 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20811 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20812 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20813 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20814 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20815 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20816 /* Vector replicate. Sizes 8 16 32. */
20817 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20818 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20819 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20820 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20821 /* VMOVN. Types I16 I32 I64. */
20822 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20823 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20824 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20825 /* VQMOVUN. Types S16 S32 S64. */
20826 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20827 /* VZIP / VUZP. Sizes 8 16 32. */
20828 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20829 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20830 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20831 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20832 /* VQABS / VQNEG. Types S8 S16 S32. */
20833 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20834 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20835 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20836 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20837 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20838 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20839 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20840 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20841 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20842 /* Reciprocal estimates. Types U32 F16 F32. */
20843 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20844 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20845 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20846 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20847 /* VCLS. Types S8 S16 S32. */
20848 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20849 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20850 /* VCLZ. Types I8 I16 I32. */
20851 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20852 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20853 /* VCNT. Size 8. */
20854 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20855 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20856 /* Two address, untyped. */
20857 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20858 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20859 /* VTRN. Sizes 8 16 32. */
20860 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20861 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20863 /* Table lookup. Size 8. */
20864 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20865 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20867 #undef THUMB_VARIANT
20868 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20870 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20872 /* Neon element/structure load/store. */
20873 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20874 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20875 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20876 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20877 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20878 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20879 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20880 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20882 #undef THUMB_VARIANT
20883 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20885 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20886 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20887 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20888 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20889 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20890 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20891 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20892 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20893 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20894 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20896 #undef THUMB_VARIANT
20897 #define THUMB_VARIANT & fpu_vfp_ext_v3
20899 #define ARM_VARIANT & fpu_vfp_ext_v3
20901 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20902 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20903 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20904 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20905 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20906 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20907 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20908 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20909 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20912 #define ARM_VARIANT & fpu_vfp_ext_fma
20913 #undef THUMB_VARIANT
20914 #define THUMB_VARIANT & fpu_vfp_ext_fma
20915 /* Mnemonics shared by Neon and VFP. These are included in the
20916 VFP FMA variant; NEON and VFP FMA always includes the NEON
20917 FMA instructions. */
20918 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20919 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20920 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20921 the v form should always be used. */
20922 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20923 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20924 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20925 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20926 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20927 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20929 #undef THUMB_VARIANT
20931 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20933 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20934 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20935 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20936 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20937 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20938 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20939 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20940 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20943 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20945 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20946 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20947 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20948 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20949 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20950 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20951 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20952 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20953 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20954 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20955 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20956 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20957 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20958 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20959 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20960 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20961 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20962 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20963 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20964 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20965 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20966 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20967 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20968 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20969 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20970 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20971 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20972 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20973 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20974 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20975 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20976 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20977 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20978 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20979 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20980 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20981 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20982 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20983 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20984 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20985 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20986 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20987 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20988 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20989 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20990 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20991 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20992 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20993 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20994 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20995 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20997 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20999 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21002 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21003 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21004 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21006 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21007 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21008 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21009 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21010 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21011 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21012 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21013 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21014 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21015 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21021 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21022 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21023 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21024 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21025 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21026 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21027 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21034 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21046 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21047 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21048 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21049 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21050 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21051 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21056 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21057 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21058 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21059 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21060 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21061 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21062 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21063 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21064 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21065 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21066 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21067 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21068 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21069 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21070 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21071 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21072 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21073 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21074 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21075 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21076 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21077 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21078 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21079 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21080 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21081 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21082 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21083 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21084 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21085 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21086 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21087 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21088 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21089 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21090 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21091 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21092 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21093 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21094 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21095 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21096 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21097 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21098 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21099 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21100 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21101 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21102 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21103 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21104 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21105 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21106 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21109 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21111 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21112 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21113 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21114 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21115 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21116 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21117 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21118 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21119 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21120 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21121 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21122 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21123 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21124 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21125 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21126 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21127 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21128 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21129 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21130 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21131 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21132 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21133 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21134 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21135 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21136 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21137 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21138 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21139 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21140 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21141 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21142 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21143 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21144 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21145 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21146 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21147 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21148 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21149 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21150 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21151 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21152 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21153 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21154 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21155 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21156 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21157 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21158 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21159 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21160 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21161 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21162 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21163 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21164 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21165 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21166 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21167 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21170 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21172 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21173 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21174 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21175 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21176 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21177 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21178 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21179 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21180 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21181 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21182 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21183 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21184 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21185 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21186 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21187 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21188 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21189 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21190 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21191 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21192 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21193 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21194 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21195 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21196 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21197 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21198 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21199 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21200 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21201 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21202 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21203 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21204 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21205 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21206 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21207 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21208 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21209 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21210 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21211 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21212 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21213 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21214 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21215 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21216 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21217 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21218 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21219 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21220 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21221 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21222 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21223 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21224 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21225 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21226 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21227 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21228 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21229 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21230 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21231 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21232 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21233 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21234 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21235 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21236 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21237 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21238 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21239 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21240 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21241 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21242 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21243 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21244 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21245 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21246 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21247 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21249 /* ARMv8-M instructions. */
21251 #define ARM_VARIANT NULL
21252 #undef THUMB_VARIANT
21253 #define THUMB_VARIANT & arm_ext_v8m
21254 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21255 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21256 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21257 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21258 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21259 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21260 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21262 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21263 instructions behave as nop if no VFP is present. */
21264 #undef THUMB_VARIANT
21265 #define THUMB_VARIANT & arm_ext_v8m_main
21266 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21267 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21270 #undef THUMB_VARIANT
21296 /* MD interface: bits in the object file. */
21298 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21299 for use in the a.out file, and stores them in the array pointed to by buf.
21300 This knows about the endian-ness of the target machine and does
21301 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21302 2 (short) and 4 (long) Floating numbers are put out as a series of
21303 LITTLENUMS (shorts, here at least). */
21306 md_number_to_chars (char * buf
, valueT val
, int n
)
21308 if (target_big_endian
)
21309 number_to_chars_bigendian (buf
, val
, n
);
21311 number_to_chars_littleendian (buf
, val
, n
);
21315 md_chars_to_number (char * buf
, int n
)
21318 unsigned char * where
= (unsigned char *) buf
;
21320 if (target_big_endian
)
21325 result
|= (*where
++ & 255);
21333 result
|= (where
[n
] & 255);
21340 /* MD interface: Sections. */
21342 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21343 that an rs_machine_dependent frag may reach. */
21346 arm_frag_max_var (fragS
*fragp
)
21348 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21349 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21351 Note that we generate relaxable instructions even for cases that don't
21352 really need it, like an immediate that's a trivial constant. So we're
21353 overestimating the instruction size for some of those cases. Rather
21354 than putting more intelligence here, it would probably be better to
21355 avoid generating a relaxation frag in the first place when it can be
21356 determined up front that a short instruction will suffice. */
21358 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21362 /* Estimate the size of a frag before relaxing. Assume everything fits in
21366 md_estimate_size_before_relax (fragS
* fragp
,
21367 segT segtype ATTRIBUTE_UNUSED
)
21373 /* Convert a machine dependent frag. */
21376 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21378 unsigned long insn
;
21379 unsigned long old_op
;
21387 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21389 old_op
= bfd_get_16(abfd
, buf
);
21390 if (fragp
->fr_symbol
)
21392 exp
.X_op
= O_symbol
;
21393 exp
.X_add_symbol
= fragp
->fr_symbol
;
21397 exp
.X_op
= O_constant
;
21399 exp
.X_add_number
= fragp
->fr_offset
;
21400 opcode
= fragp
->fr_subtype
;
21403 case T_MNEM_ldr_pc
:
21404 case T_MNEM_ldr_pc2
:
21405 case T_MNEM_ldr_sp
:
21406 case T_MNEM_str_sp
:
21413 if (fragp
->fr_var
== 4)
21415 insn
= THUMB_OP32 (opcode
);
21416 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21418 insn
|= (old_op
& 0x700) << 4;
21422 insn
|= (old_op
& 7) << 12;
21423 insn
|= (old_op
& 0x38) << 13;
21425 insn
|= 0x00000c00;
21426 put_thumb32_insn (buf
, insn
);
21427 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21431 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21433 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21436 if (fragp
->fr_var
== 4)
21438 insn
= THUMB_OP32 (opcode
);
21439 insn
|= (old_op
& 0xf0) << 4;
21440 put_thumb32_insn (buf
, insn
);
21441 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21445 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21446 exp
.X_add_number
-= 4;
21454 if (fragp
->fr_var
== 4)
21456 int r0off
= (opcode
== T_MNEM_mov
21457 || opcode
== T_MNEM_movs
) ? 0 : 8;
21458 insn
= THUMB_OP32 (opcode
);
21459 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21460 insn
|= (old_op
& 0x700) << r0off
;
21461 put_thumb32_insn (buf
, insn
);
21462 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21466 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21471 if (fragp
->fr_var
== 4)
21473 insn
= THUMB_OP32(opcode
);
21474 put_thumb32_insn (buf
, insn
);
21475 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21478 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21482 if (fragp
->fr_var
== 4)
21484 insn
= THUMB_OP32(opcode
);
21485 insn
|= (old_op
& 0xf00) << 14;
21486 put_thumb32_insn (buf
, insn
);
21487 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21490 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21493 case T_MNEM_add_sp
:
21494 case T_MNEM_add_pc
:
21495 case T_MNEM_inc_sp
:
21496 case T_MNEM_dec_sp
:
21497 if (fragp
->fr_var
== 4)
21499 /* ??? Choose between add and addw. */
21500 insn
= THUMB_OP32 (opcode
);
21501 insn
|= (old_op
& 0xf0) << 4;
21502 put_thumb32_insn (buf
, insn
);
21503 if (opcode
== T_MNEM_add_pc
)
21504 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21506 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21509 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21517 if (fragp
->fr_var
== 4)
21519 insn
= THUMB_OP32 (opcode
);
21520 insn
|= (old_op
& 0xf0) << 4;
21521 insn
|= (old_op
& 0xf) << 16;
21522 put_thumb32_insn (buf
, insn
);
21523 if (insn
& (1 << 20))
21524 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21526 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21529 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21535 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21536 (enum bfd_reloc_code_real
) reloc_type
);
21537 fixp
->fx_file
= fragp
->fr_file
;
21538 fixp
->fx_line
= fragp
->fr_line
;
21539 fragp
->fr_fix
+= fragp
->fr_var
;
21541 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21542 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21543 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21544 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21547 /* Return the size of a relaxable immediate operand instruction.
21548 SHIFT and SIZE specify the form of the allowable immediate. */
21550 relax_immediate (fragS
*fragp
, int size
, int shift
)
21556 /* ??? Should be able to do better than this. */
21557 if (fragp
->fr_symbol
)
21560 low
= (1 << shift
) - 1;
21561 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21562 offset
= fragp
->fr_offset
;
21563 /* Force misaligned offsets to 32-bit variant. */
21566 if (offset
& ~mask
)
21571 /* Get the address of a symbol during relaxation. */
21573 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21579 sym
= fragp
->fr_symbol
;
21580 sym_frag
= symbol_get_frag (sym
);
21581 know (S_GET_SEGMENT (sym
) != absolute_section
21582 || sym_frag
== &zero_address_frag
);
21583 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21585 /* If frag has yet to be reached on this pass, assume it will
21586 move by STRETCH just as we did. If this is not so, it will
21587 be because some frag between grows, and that will force
21591 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21595 /* Adjust stretch for any alignment frag. Note that if have
21596 been expanding the earlier code, the symbol may be
21597 defined in what appears to be an earlier frag. FIXME:
21598 This doesn't handle the fr_subtype field, which specifies
21599 a maximum number of bytes to skip when doing an
21601 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21603 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21606 stretch
= - ((- stretch
)
21607 & ~ ((1 << (int) f
->fr_offset
) - 1));
21609 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21621 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21624 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21629 /* Assume worst case for symbols not known to be in the same section. */
21630 if (fragp
->fr_symbol
== NULL
21631 || !S_IS_DEFINED (fragp
->fr_symbol
)
21632 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21633 || S_IS_WEAK (fragp
->fr_symbol
))
21636 val
= relaxed_symbol_addr (fragp
, stretch
);
21637 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21638 addr
= (addr
+ 4) & ~3;
21639 /* Force misaligned targets to 32-bit variant. */
21643 if (val
< 0 || val
> 1020)
21648 /* Return the size of a relaxable add/sub immediate instruction. */
21650 relax_addsub (fragS
*fragp
, asection
*sec
)
21655 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21656 op
= bfd_get_16(sec
->owner
, buf
);
21657 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21658 return relax_immediate (fragp
, 8, 0);
21660 return relax_immediate (fragp
, 3, 0);
21663 /* Return TRUE iff the definition of symbol S could be pre-empted
21664 (overridden) at link or load time. */
21666 symbol_preemptible (symbolS
*s
)
21668 /* Weak symbols can always be pre-empted. */
21672 /* Non-global symbols cannot be pre-empted. */
21673 if (! S_IS_EXTERNAL (s
))
21677 /* In ELF, a global symbol can be marked protected, or private. In that
21678 case it can't be pre-empted (other definitions in the same link unit
21679 would violate the ODR). */
21680 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21684 /* Other global symbols might be pre-empted. */
21688 /* Return the size of a relaxable branch instruction. BITS is the
21689 size of the offset field in the narrow instruction. */
21692 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21698 /* Assume worst case for symbols not known to be in the same section. */
21699 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21700 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21701 || S_IS_WEAK (fragp
->fr_symbol
))
21705 /* A branch to a function in ARM state will require interworking. */
21706 if (S_IS_DEFINED (fragp
->fr_symbol
)
21707 && ARM_IS_FUNC (fragp
->fr_symbol
))
21711 if (symbol_preemptible (fragp
->fr_symbol
))
21714 val
= relaxed_symbol_addr (fragp
, stretch
);
21715 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21718 /* Offset is a signed value *2 */
21720 if (val
>= limit
|| val
< -limit
)
21726 /* Relax a machine dependent frag. This returns the amount by which
21727 the current size of the frag should change. */
21730 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21735 oldsize
= fragp
->fr_var
;
21736 switch (fragp
->fr_subtype
)
21738 case T_MNEM_ldr_pc2
:
21739 newsize
= relax_adr (fragp
, sec
, stretch
);
21741 case T_MNEM_ldr_pc
:
21742 case T_MNEM_ldr_sp
:
21743 case T_MNEM_str_sp
:
21744 newsize
= relax_immediate (fragp
, 8, 2);
21748 newsize
= relax_immediate (fragp
, 5, 2);
21752 newsize
= relax_immediate (fragp
, 5, 1);
21756 newsize
= relax_immediate (fragp
, 5, 0);
21759 newsize
= relax_adr (fragp
, sec
, stretch
);
21765 newsize
= relax_immediate (fragp
, 8, 0);
21768 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21771 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21773 case T_MNEM_add_sp
:
21774 case T_MNEM_add_pc
:
21775 newsize
= relax_immediate (fragp
, 8, 2);
21777 case T_MNEM_inc_sp
:
21778 case T_MNEM_dec_sp
:
21779 newsize
= relax_immediate (fragp
, 7, 2);
21785 newsize
= relax_addsub (fragp
, sec
);
21791 fragp
->fr_var
= newsize
;
21792 /* Freeze wide instructions that are at or before the same location as
21793 in the previous pass. This avoids infinite loops.
21794 Don't freeze them unconditionally because targets may be artificially
21795 misaligned by the expansion of preceding frags. */
21796 if (stretch
<= 0 && newsize
> 2)
21798 md_convert_frag (sec
->owner
, sec
, fragp
);
21802 return newsize
- oldsize
;
21805 /* Round up a section size to the appropriate boundary. */
21808 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21811 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21812 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21814 /* For a.out, force the section size to be aligned. If we don't do
21815 this, BFD will align it for us, but it will not write out the
21816 final bytes of the section. This may be a bug in BFD, but it is
21817 easier to fix it here since that is how the other a.out targets
21821 align
= bfd_get_section_alignment (stdoutput
, segment
);
21822 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21829 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21830 of an rs_align_code fragment. */
21833 arm_handle_align (fragS
* fragP
)
21835 static unsigned char const arm_noop
[2][2][4] =
21838 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21839 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21842 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21843 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21846 static unsigned char const thumb_noop
[2][2][2] =
21849 {0xc0, 0x46}, /* LE */
21850 {0x46, 0xc0}, /* BE */
21853 {0x00, 0xbf}, /* LE */
21854 {0xbf, 0x00} /* BE */
21857 static unsigned char const wide_thumb_noop
[2][4] =
21858 { /* Wide Thumb-2 */
21859 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21860 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21863 unsigned bytes
, fix
, noop_size
;
21865 const unsigned char * noop
;
21866 const unsigned char *narrow_noop
= NULL
;
21871 if (fragP
->fr_type
!= rs_align_code
)
21874 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21875 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21878 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21879 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21881 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21883 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21885 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21886 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21888 narrow_noop
= thumb_noop
[1][target_big_endian
];
21889 noop
= wide_thumb_noop
[target_big_endian
];
21892 noop
= thumb_noop
[0][target_big_endian
];
21900 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21901 ? selected_cpu
: arm_arch_none
,
21903 [target_big_endian
];
21910 fragP
->fr_var
= noop_size
;
21912 if (bytes
& (noop_size
- 1))
21914 fix
= bytes
& (noop_size
- 1);
21916 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21918 memset (p
, 0, fix
);
21925 if (bytes
& noop_size
)
21927 /* Insert a narrow noop. */
21928 memcpy (p
, narrow_noop
, noop_size
);
21930 bytes
-= noop_size
;
21934 /* Use wide noops for the remainder */
21938 while (bytes
>= noop_size
)
21940 memcpy (p
, noop
, noop_size
);
21942 bytes
-= noop_size
;
21946 fragP
->fr_fix
+= fix
;
21949 /* Called from md_do_align. Used to create an alignment
21950 frag in a code section. */
21953 arm_frag_align_code (int n
, int max
)
21957 /* We assume that there will never be a requirement
21958 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21959 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21964 _("alignments greater than %d bytes not supported in .text sections."),
21965 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21966 as_fatal ("%s", err_msg
);
21969 p
= frag_var (rs_align_code
,
21970 MAX_MEM_FOR_RS_ALIGN_CODE
,
21972 (relax_substateT
) max
,
21979 /* Perform target specific initialisation of a frag.
21980 Note - despite the name this initialisation is not done when the frag
21981 is created, but only when its type is assigned. A frag can be created
21982 and used a long time before its type is set, so beware of assuming that
21983 this initialisation is performed first. */
21987 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21989 /* Record whether this frag is in an ARM or a THUMB area. */
21990 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21993 #else /* OBJ_ELF is defined. */
21995 arm_init_frag (fragS
* fragP
, int max_chars
)
21997 int frag_thumb_mode
;
21999 /* If the current ARM vs THUMB mode has not already
22000 been recorded into this frag then do so now. */
22001 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22002 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22004 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22006 /* Record a mapping symbol for alignment frags. We will delete this
22007 later if the alignment ends up empty. */
22008 switch (fragP
->fr_type
)
22011 case rs_align_test
:
22013 mapping_state_2 (MAP_DATA
, max_chars
);
22015 case rs_align_code
:
22016 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22023 /* When we change sections we need to issue a new mapping symbol. */
22026 arm_elf_change_section (void)
22028 /* Link an unlinked unwind index table section to the .text section. */
22029 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22030 && elf_linked_to_section (now_seg
) == NULL
)
22031 elf_linked_to_section (now_seg
) = text_section
;
22035 arm_elf_section_type (const char * str
, size_t len
)
22037 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22038 return SHT_ARM_EXIDX
;
22043 /* Code to deal with unwinding tables. */
22045 static void add_unwind_adjustsp (offsetT
);
22047 /* Generate any deferred unwind frame offset. */
22050 flush_pending_unwind (void)
22054 offset
= unwind
.pending_offset
;
22055 unwind
.pending_offset
= 0;
22057 add_unwind_adjustsp (offset
);
22060 /* Add an opcode to this list for this function. Two-byte opcodes should
22061 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22065 add_unwind_opcode (valueT op
, int length
)
22067 /* Add any deferred stack adjustment. */
22068 if (unwind
.pending_offset
)
22069 flush_pending_unwind ();
22071 unwind
.sp_restored
= 0;
22073 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22075 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22076 if (unwind
.opcodes
)
22077 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22078 unwind
.opcode_alloc
);
22080 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22085 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22087 unwind
.opcode_count
++;
22091 /* Add unwind opcodes to adjust the stack pointer. */
22094 add_unwind_adjustsp (offsetT offset
)
22098 if (offset
> 0x200)
22100 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22105 /* Long form: 0xb2, uleb128. */
22106 /* This might not fit in a word so add the individual bytes,
22107 remembering the list is built in reverse order. */
22108 o
= (valueT
) ((offset
- 0x204) >> 2);
22110 add_unwind_opcode (0, 1);
22112 /* Calculate the uleb128 encoding of the offset. */
22116 bytes
[n
] = o
& 0x7f;
22122 /* Add the insn. */
22124 add_unwind_opcode (bytes
[n
- 1], 1);
22125 add_unwind_opcode (0xb2, 1);
22127 else if (offset
> 0x100)
22129 /* Two short opcodes. */
22130 add_unwind_opcode (0x3f, 1);
22131 op
= (offset
- 0x104) >> 2;
22132 add_unwind_opcode (op
, 1);
22134 else if (offset
> 0)
22136 /* Short opcode. */
22137 op
= (offset
- 4) >> 2;
22138 add_unwind_opcode (op
, 1);
22140 else if (offset
< 0)
22143 while (offset
> 0x100)
22145 add_unwind_opcode (0x7f, 1);
22148 op
= ((offset
- 4) >> 2) | 0x40;
22149 add_unwind_opcode (op
, 1);
22153 /* Finish the list of unwind opcodes for this function. */
22155 finish_unwind_opcodes (void)
22159 if (unwind
.fp_used
)
22161 /* Adjust sp as necessary. */
22162 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22163 flush_pending_unwind ();
22165 /* After restoring sp from the frame pointer. */
22166 op
= 0x90 | unwind
.fp_reg
;
22167 add_unwind_opcode (op
, 1);
22170 flush_pending_unwind ();
22174 /* Start an exception table entry. If idx is nonzero this is an index table
22178 start_unwind_section (const segT text_seg
, int idx
)
22180 const char * text_name
;
22181 const char * prefix
;
22182 const char * prefix_once
;
22183 const char * group_name
;
22191 prefix
= ELF_STRING_ARM_unwind
;
22192 prefix_once
= ELF_STRING_ARM_unwind_once
;
22193 type
= SHT_ARM_EXIDX
;
22197 prefix
= ELF_STRING_ARM_unwind_info
;
22198 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22199 type
= SHT_PROGBITS
;
22202 text_name
= segment_name (text_seg
);
22203 if (streq (text_name
, ".text"))
22206 if (strncmp (text_name
, ".gnu.linkonce.t.",
22207 strlen (".gnu.linkonce.t.")) == 0)
22209 prefix
= prefix_once
;
22210 text_name
+= strlen (".gnu.linkonce.t.");
22213 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22219 /* Handle COMDAT group. */
22220 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22222 group_name
= elf_group_name (text_seg
);
22223 if (group_name
== NULL
)
22225 as_bad (_("Group section `%s' has no group signature"),
22226 segment_name (text_seg
));
22227 ignore_rest_of_line ();
22230 flags
|= SHF_GROUP
;
22234 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22237 /* Set the section link for index tables. */
22239 elf_linked_to_section (now_seg
) = text_seg
;
22243 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22244 personality routine data. Returns zero, or the index table value for
22245 an inline entry. */
22248 create_unwind_entry (int have_data
)
22253 /* The current word of data. */
22255 /* The number of bytes left in this word. */
22258 finish_unwind_opcodes ();
22260 /* Remember the current text section. */
22261 unwind
.saved_seg
= now_seg
;
22262 unwind
.saved_subseg
= now_subseg
;
22264 start_unwind_section (now_seg
, 0);
22266 if (unwind
.personality_routine
== NULL
)
22268 if (unwind
.personality_index
== -2)
22271 as_bad (_("handlerdata in cantunwind frame"));
22272 return 1; /* EXIDX_CANTUNWIND. */
22275 /* Use a default personality routine if none is specified. */
22276 if (unwind
.personality_index
== -1)
22278 if (unwind
.opcode_count
> 3)
22279 unwind
.personality_index
= 1;
22281 unwind
.personality_index
= 0;
22284 /* Space for the personality routine entry. */
22285 if (unwind
.personality_index
== 0)
22287 if (unwind
.opcode_count
> 3)
22288 as_bad (_("too many unwind opcodes for personality routine 0"));
22292 /* All the data is inline in the index table. */
22295 while (unwind
.opcode_count
> 0)
22297 unwind
.opcode_count
--;
22298 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22302 /* Pad with "finish" opcodes. */
22304 data
= (data
<< 8) | 0xb0;
22311 /* We get two opcodes "free" in the first word. */
22312 size
= unwind
.opcode_count
- 2;
22316 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22317 if (unwind
.personality_index
!= -1)
22319 as_bad (_("attempt to recreate an unwind entry"));
22323 /* An extra byte is required for the opcode count. */
22324 size
= unwind
.opcode_count
+ 1;
22327 size
= (size
+ 3) >> 2;
22329 as_bad (_("too many unwind opcodes"));
22331 frag_align (2, 0, 0);
22332 record_alignment (now_seg
, 2);
22333 unwind
.table_entry
= expr_build_dot ();
22335 /* Allocate the table entry. */
22336 ptr
= frag_more ((size
<< 2) + 4);
22337 /* PR 13449: Zero the table entries in case some of them are not used. */
22338 memset (ptr
, 0, (size
<< 2) + 4);
22339 where
= frag_now_fix () - ((size
<< 2) + 4);
22341 switch (unwind
.personality_index
)
22344 /* ??? Should this be a PLT generating relocation? */
22345 /* Custom personality routine. */
22346 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22347 BFD_RELOC_ARM_PREL31
);
22352 /* Set the first byte to the number of additional words. */
22353 data
= size
> 0 ? size
- 1 : 0;
22357 /* ABI defined personality routines. */
22359 /* Three opcodes bytes are packed into the first word. */
22366 /* The size and first two opcode bytes go in the first word. */
22367 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22372 /* Should never happen. */
22376 /* Pack the opcodes into words (MSB first), reversing the list at the same
22378 while (unwind
.opcode_count
> 0)
22382 md_number_to_chars (ptr
, data
, 4);
22387 unwind
.opcode_count
--;
22389 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22392 /* Finish off the last word. */
22395 /* Pad with "finish" opcodes. */
22397 data
= (data
<< 8) | 0xb0;
22399 md_number_to_chars (ptr
, data
, 4);
22404 /* Add an empty descriptor if there is no user-specified data. */
22405 ptr
= frag_more (4);
22406 md_number_to_chars (ptr
, 0, 4);
22413 /* Initialize the DWARF-2 unwind information for this procedure. */
22416 tc_arm_frame_initial_instructions (void)
22418 cfi_add_CFA_def_cfa (REG_SP
, 0);
22420 #endif /* OBJ_ELF */
22422 /* Convert REGNAME to a DWARF-2 register number. */
22425 tc_arm_regname_to_dw2regnum (char *regname
)
22427 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22431 /* PR 16694: Allow VFP registers as well. */
22432 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22436 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22445 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22449 exp
.X_op
= O_secrel
;
22450 exp
.X_add_symbol
= symbol
;
22451 exp
.X_add_number
= 0;
22452 emit_expr (&exp
, size
);
22456 /* MD interface: Symbol and relocation handling. */
22458 /* Return the address within the segment that a PC-relative fixup is
22459 relative to. For ARM, PC-relative fixups applied to instructions
22460 are generally relative to the location of the fixup plus 8 bytes.
22461 Thumb branches are offset by 4, and Thumb loads relative to PC
22462 require special handling. */
22465 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22467 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22469 /* If this is pc-relative and we are going to emit a relocation
22470 then we just want to put out any pipeline compensation that the linker
22471 will need. Otherwise we want to use the calculated base.
22472 For WinCE we skip the bias for externals as well, since this
22473 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22475 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22476 || (arm_force_relocation (fixP
)
22478 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22484 switch (fixP
->fx_r_type
)
22486 /* PC relative addressing on the Thumb is slightly odd as the
22487 bottom two bits of the PC are forced to zero for the
22488 calculation. This happens *after* application of the
22489 pipeline offset. However, Thumb adrl already adjusts for
22490 this, so we need not do it again. */
22491 case BFD_RELOC_ARM_THUMB_ADD
:
22494 case BFD_RELOC_ARM_THUMB_OFFSET
:
22495 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22496 case BFD_RELOC_ARM_T32_ADD_PC12
:
22497 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22498 return (base
+ 4) & ~3;
22500 /* Thumb branches are simply offset by +4. */
22501 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22502 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22503 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22504 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22505 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22508 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22510 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22511 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22512 && ARM_IS_FUNC (fixP
->fx_addsy
)
22513 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22514 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22517 /* BLX is like branches above, but forces the low two bits of PC to
22519 case BFD_RELOC_THUMB_PCREL_BLX
:
22521 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22522 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22523 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22524 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22525 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22526 return (base
+ 4) & ~3;
22528 /* ARM mode branches are offset by +8. However, the Windows CE
22529 loader expects the relocation not to take this into account. */
22530 case BFD_RELOC_ARM_PCREL_BLX
:
22532 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22533 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22534 && ARM_IS_FUNC (fixP
->fx_addsy
)
22535 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22536 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22539 case BFD_RELOC_ARM_PCREL_CALL
:
22541 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22542 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22543 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22544 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22545 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22548 case BFD_RELOC_ARM_PCREL_BRANCH
:
22549 case BFD_RELOC_ARM_PCREL_JUMP
:
22550 case BFD_RELOC_ARM_PLT32
:
22552 /* When handling fixups immediately, because we have already
22553 discovered the value of a symbol, or the address of the frag involved
22554 we must account for the offset by +8, as the OS loader will never see the reloc.
22555 see fixup_segment() in write.c
22556 The S_IS_EXTERNAL test handles the case of global symbols.
22557 Those need the calculated base, not just the pipe compensation the linker will need. */
22559 && fixP
->fx_addsy
!= NULL
22560 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22561 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22569 /* ARM mode loads relative to PC are also offset by +8. Unlike
22570 branches, the Windows CE loader *does* expect the relocation
22571 to take this into account. */
22572 case BFD_RELOC_ARM_OFFSET_IMM
:
22573 case BFD_RELOC_ARM_OFFSET_IMM8
:
22574 case BFD_RELOC_ARM_HWLITERAL
:
22575 case BFD_RELOC_ARM_LITERAL
:
22576 case BFD_RELOC_ARM_CP_OFF_IMM
:
22580 /* Other PC-relative relocations are un-offset. */
22586 static bfd_boolean flag_warn_syms
= TRUE
;
22589 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22591 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22592 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22593 does mean that the resulting code might be very confusing to the reader.
22594 Also this warning can be triggered if the user omits an operand before
22595 an immediate address, eg:
22599 GAS treats this as an assignment of the value of the symbol foo to a
22600 symbol LDR, and so (without this code) it will not issue any kind of
22601 warning or error message.
22603 Note - ARM instructions are case-insensitive but the strings in the hash
22604 table are all stored in lower case, so we must first ensure that name is
22606 if (flag_warn_syms
&& arm_ops_hsh
)
22608 char * nbuf
= strdup (name
);
22611 for (p
= nbuf
; *p
; p
++)
22613 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22615 static struct hash_control
* already_warned
= NULL
;
22617 if (already_warned
== NULL
)
22618 already_warned
= hash_new ();
22619 /* Only warn about the symbol once. To keep the code
22620 simple we let hash_insert do the lookup for us. */
22621 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22622 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22631 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22632 Otherwise we have no need to default values of symbols. */
22635 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22638 if (name
[0] == '_' && name
[1] == 'G'
22639 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22643 if (symbol_find (name
))
22644 as_bad (_("GOT already in the symbol table"));
22646 GOT_symbol
= symbol_new (name
, undefined_section
,
22647 (valueT
) 0, & zero_address_frag
);
22657 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22658 computed as two separate immediate values, added together. We
22659 already know that this value cannot be computed by just one ARM
22662 static unsigned int
22663 validate_immediate_twopart (unsigned int val
,
22664 unsigned int * highpart
)
22669 for (i
= 0; i
< 32; i
+= 2)
22670 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22676 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22678 else if (a
& 0xff0000)
22680 if (a
& 0xff000000)
22682 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22686 gas_assert (a
& 0xff000000);
22687 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22690 return (a
& 0xff) | (i
<< 7);
22697 validate_offset_imm (unsigned int val
, int hwse
)
22699 if ((hwse
&& val
> 255) || val
> 4095)
22704 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22705 negative immediate constant by altering the instruction. A bit of
22710 by inverting the second operand, and
22713 by negating the second operand. */
22716 negate_data_op (unsigned long * instruction
,
22717 unsigned long value
)
22720 unsigned long negated
, inverted
;
22722 negated
= encode_arm_immediate (-value
);
22723 inverted
= encode_arm_immediate (~value
);
22725 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22728 /* First negates. */
22729 case OPCODE_SUB
: /* ADD <-> SUB */
22730 new_inst
= OPCODE_ADD
;
22735 new_inst
= OPCODE_SUB
;
22739 case OPCODE_CMP
: /* CMP <-> CMN */
22740 new_inst
= OPCODE_CMN
;
22745 new_inst
= OPCODE_CMP
;
22749 /* Now Inverted ops. */
22750 case OPCODE_MOV
: /* MOV <-> MVN */
22751 new_inst
= OPCODE_MVN
;
22756 new_inst
= OPCODE_MOV
;
22760 case OPCODE_AND
: /* AND <-> BIC */
22761 new_inst
= OPCODE_BIC
;
22766 new_inst
= OPCODE_AND
;
22770 case OPCODE_ADC
: /* ADC <-> SBC */
22771 new_inst
= OPCODE_SBC
;
22776 new_inst
= OPCODE_ADC
;
22780 /* We cannot do anything. */
22785 if (value
== (unsigned) FAIL
)
22788 *instruction
&= OPCODE_MASK
;
22789 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22793 /* Like negate_data_op, but for Thumb-2. */
22795 static unsigned int
22796 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22800 unsigned int negated
, inverted
;
22802 negated
= encode_thumb32_immediate (-value
);
22803 inverted
= encode_thumb32_immediate (~value
);
22805 rd
= (*instruction
>> 8) & 0xf;
22806 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22809 /* ADD <-> SUB. Includes CMP <-> CMN. */
22810 case T2_OPCODE_SUB
:
22811 new_inst
= T2_OPCODE_ADD
;
22815 case T2_OPCODE_ADD
:
22816 new_inst
= T2_OPCODE_SUB
;
22820 /* ORR <-> ORN. Includes MOV <-> MVN. */
22821 case T2_OPCODE_ORR
:
22822 new_inst
= T2_OPCODE_ORN
;
22826 case T2_OPCODE_ORN
:
22827 new_inst
= T2_OPCODE_ORR
;
22831 /* AND <-> BIC. TST has no inverted equivalent. */
22832 case T2_OPCODE_AND
:
22833 new_inst
= T2_OPCODE_BIC
;
22840 case T2_OPCODE_BIC
:
22841 new_inst
= T2_OPCODE_AND
;
22846 case T2_OPCODE_ADC
:
22847 new_inst
= T2_OPCODE_SBC
;
22851 case T2_OPCODE_SBC
:
22852 new_inst
= T2_OPCODE_ADC
;
22856 /* We cannot do anything. */
22861 if (value
== (unsigned int)FAIL
)
22864 *instruction
&= T2_OPCODE_MASK
;
22865 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22869 /* Read a 32-bit thumb instruction from buf. */
22870 static unsigned long
22871 get_thumb32_insn (char * buf
)
22873 unsigned long insn
;
22874 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22875 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22881 /* We usually want to set the low bit on the address of thumb function
22882 symbols. In particular .word foo - . should have the low bit set.
22883 Generic code tries to fold the difference of two symbols to
22884 a constant. Prevent this and force a relocation when the first symbols
22885 is a thumb function. */
22888 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22890 if (op
== O_subtract
22891 && l
->X_op
== O_symbol
22892 && r
->X_op
== O_symbol
22893 && THUMB_IS_FUNC (l
->X_add_symbol
))
22895 l
->X_op
= O_subtract
;
22896 l
->X_op_symbol
= r
->X_add_symbol
;
22897 l
->X_add_number
-= r
->X_add_number
;
22901 /* Process as normal. */
22905 /* Encode Thumb2 unconditional branches and calls. The encoding
22906 for the 2 are identical for the immediate values. */
22909 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22911 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22914 addressT S
, I1
, I2
, lo
, hi
;
22916 S
= (value
>> 24) & 0x01;
22917 I1
= (value
>> 23) & 0x01;
22918 I2
= (value
>> 22) & 0x01;
22919 hi
= (value
>> 12) & 0x3ff;
22920 lo
= (value
>> 1) & 0x7ff;
22921 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22922 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22923 newval
|= (S
<< 10) | hi
;
22924 newval2
&= ~T2I1I2MASK
;
22925 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22926 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22927 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22931 md_apply_fix (fixS
* fixP
,
22935 offsetT value
= * valP
;
22937 unsigned int newimm
;
22938 unsigned long temp
;
22940 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22942 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22944 /* Note whether this will delete the relocation. */
22946 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22949 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22950 consistency with the behaviour on 32-bit hosts. Remember value
22952 value
&= 0xffffffff;
22953 value
^= 0x80000000;
22954 value
-= 0x80000000;
22957 fixP
->fx_addnumber
= value
;
22959 /* Same treatment for fixP->fx_offset. */
22960 fixP
->fx_offset
&= 0xffffffff;
22961 fixP
->fx_offset
^= 0x80000000;
22962 fixP
->fx_offset
-= 0x80000000;
22964 switch (fixP
->fx_r_type
)
22966 case BFD_RELOC_NONE
:
22967 /* This will need to go in the object file. */
22971 case BFD_RELOC_ARM_IMMEDIATE
:
22972 /* We claim that this fixup has been processed here,
22973 even if in fact we generate an error because we do
22974 not have a reloc for it, so tc_gen_reloc will reject it. */
22977 if (fixP
->fx_addsy
)
22979 const char *msg
= 0;
22981 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22982 msg
= _("undefined symbol %s used as an immediate value");
22983 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22984 msg
= _("symbol %s is in a different section");
22985 else if (S_IS_WEAK (fixP
->fx_addsy
))
22986 msg
= _("symbol %s is weak and may be overridden later");
22990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22991 msg
, S_GET_NAME (fixP
->fx_addsy
));
22996 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22998 /* If the offset is negative, we should use encoding A2 for ADR. */
22999 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23000 newimm
= negate_data_op (&temp
, value
);
23003 newimm
= encode_arm_immediate (value
);
23005 /* If the instruction will fail, see if we can fix things up by
23006 changing the opcode. */
23007 if (newimm
== (unsigned int) FAIL
)
23008 newimm
= negate_data_op (&temp
, value
);
23009 /* MOV accepts both ARM modified immediate (A1 encoding) and
23010 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23011 When disassembling, MOV is preferred when there is no encoding
23013 if (newimm
== (unsigned int) FAIL
23014 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23015 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23016 && !((temp
>> SBIT_SHIFT
) & 0x1)
23017 && value
>= 0 && value
<= 0xffff)
23019 /* Clear bits[23:20] to change encoding from A1 to A2. */
23020 temp
&= 0xff0fffff;
23021 /* Encoding high 4bits imm. Code below will encode the remaining
23023 temp
|= (value
& 0x0000f000) << 4;
23024 newimm
= value
& 0x00000fff;
23028 if (newimm
== (unsigned int) FAIL
)
23030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23031 _("invalid constant (%lx) after fixup"),
23032 (unsigned long) value
);
23036 newimm
|= (temp
& 0xfffff000);
23037 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23040 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23042 unsigned int highpart
= 0;
23043 unsigned int newinsn
= 0xe1a00000; /* nop. */
23045 if (fixP
->fx_addsy
)
23047 const char *msg
= 0;
23049 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23050 msg
= _("undefined symbol %s used as an immediate value");
23051 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23052 msg
= _("symbol %s is in a different section");
23053 else if (S_IS_WEAK (fixP
->fx_addsy
))
23054 msg
= _("symbol %s is weak and may be overridden later");
23058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23059 msg
, S_GET_NAME (fixP
->fx_addsy
));
23064 newimm
= encode_arm_immediate (value
);
23065 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23067 /* If the instruction will fail, see if we can fix things up by
23068 changing the opcode. */
23069 if (newimm
== (unsigned int) FAIL
23070 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23072 /* No ? OK - try using two ADD instructions to generate
23074 newimm
= validate_immediate_twopart (value
, & highpart
);
23076 /* Yes - then make sure that the second instruction is
23078 if (newimm
!= (unsigned int) FAIL
)
23080 /* Still No ? Try using a negated value. */
23081 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23082 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23083 /* Otherwise - give up. */
23086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23087 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23092 /* Replace the first operand in the 2nd instruction (which
23093 is the PC) with the destination register. We have
23094 already added in the PC in the first instruction and we
23095 do not want to do it again. */
23096 newinsn
&= ~ 0xf0000;
23097 newinsn
|= ((newinsn
& 0x0f000) << 4);
23100 newimm
|= (temp
& 0xfffff000);
23101 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23103 highpart
|= (newinsn
& 0xfffff000);
23104 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23108 case BFD_RELOC_ARM_OFFSET_IMM
:
23109 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23111 /* Fall through. */
23113 case BFD_RELOC_ARM_LITERAL
:
23119 if (validate_offset_imm (value
, 0) == FAIL
)
23121 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23123 _("invalid literal constant: pool needs to be closer"));
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("bad immediate value for offset (%ld)"),
23131 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23133 newval
&= 0xfffff000;
23136 newval
&= 0xff7ff000;
23137 newval
|= value
| (sign
? INDEX_UP
: 0);
23139 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23142 case BFD_RELOC_ARM_OFFSET_IMM8
:
23143 case BFD_RELOC_ARM_HWLITERAL
:
23149 if (validate_offset_imm (value
, 1) == FAIL
)
23151 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23153 _("invalid literal constant: pool needs to be closer"));
23155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23156 _("bad immediate value for 8-bit offset (%ld)"),
23161 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23163 newval
&= 0xfffff0f0;
23166 newval
&= 0xff7ff0f0;
23167 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23169 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23172 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23173 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23175 _("bad immediate value for offset (%ld)"), (long) value
);
23178 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23180 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23183 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23184 /* This is a complicated relocation used for all varieties of Thumb32
23185 load/store instruction with immediate offset:
23187 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23188 *4, optional writeback(W)
23189 (doubleword load/store)
23191 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23192 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23193 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23194 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23195 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23197 Uppercase letters indicate bits that are already encoded at
23198 this point. Lowercase letters are our problem. For the
23199 second block of instructions, the secondary opcode nybble
23200 (bits 8..11) is present, and bit 23 is zero, even if this is
23201 a PC-relative operation. */
23202 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23204 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23206 if ((newval
& 0xf0000000) == 0xe0000000)
23208 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23210 newval
|= (1 << 23);
23213 if (value
% 4 != 0)
23215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23216 _("offset not a multiple of 4"));
23222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23223 _("offset out of range"));
23228 else if ((newval
& 0x000f0000) == 0x000f0000)
23230 /* PC-relative, 12-bit offset. */
23232 newval
|= (1 << 23);
23237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23238 _("offset out of range"));
23243 else if ((newval
& 0x00000100) == 0x00000100)
23245 /* Writeback: 8-bit, +/- offset. */
23247 newval
|= (1 << 9);
23252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23253 _("offset out of range"));
23258 else if ((newval
& 0x00000f00) == 0x00000e00)
23260 /* T-instruction: positive 8-bit offset. */
23261 if (value
< 0 || value
> 0xff)
23263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23264 _("offset out of range"));
23272 /* Positive 12-bit or negative 8-bit offset. */
23276 newval
|= (1 << 23);
23286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23287 _("offset out of range"));
23294 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23295 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23298 case BFD_RELOC_ARM_SHIFT_IMM
:
23299 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23300 if (((unsigned long) value
) > 32
23302 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23305 _("shift expression is too large"));
23310 /* Shifts of zero must be done as lsl. */
23312 else if (value
== 32)
23314 newval
&= 0xfffff07f;
23315 newval
|= (value
& 0x1f) << 7;
23316 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23319 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23320 case BFD_RELOC_ARM_T32_ADD_IMM
:
23321 case BFD_RELOC_ARM_T32_IMM12
:
23322 case BFD_RELOC_ARM_T32_ADD_PC12
:
23323 /* We claim that this fixup has been processed here,
23324 even if in fact we generate an error because we do
23325 not have a reloc for it, so tc_gen_reloc will reject it. */
23329 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23332 _("undefined symbol %s used as an immediate value"),
23333 S_GET_NAME (fixP
->fx_addsy
));
23337 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23339 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23342 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23343 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23344 Thumb2 modified immediate encoding (T2). */
23345 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23346 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23348 newimm
= encode_thumb32_immediate (value
);
23349 if (newimm
== (unsigned int) FAIL
)
23350 newimm
= thumb32_negate_data_op (&newval
, value
);
23352 if (newimm
== (unsigned int) FAIL
)
23354 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23356 /* Turn add/sum into addw/subw. */
23357 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23358 newval
= (newval
& 0xfeffffff) | 0x02000000;
23359 /* No flat 12-bit imm encoding for addsw/subsw. */
23360 if ((newval
& 0x00100000) == 0)
23362 /* 12 bit immediate for addw/subw. */
23366 newval
^= 0x00a00000;
23369 newimm
= (unsigned int) FAIL
;
23376 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23377 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23378 disassembling, MOV is preferred when there is no encoding
23380 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23381 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23382 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23383 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23384 && value
>= 0 && value
<=0xffff)
23386 /* Toggle bit[25] to change encoding from T2 to T3. */
23388 /* Clear bits[19:16]. */
23389 newval
&= 0xfff0ffff;
23390 /* Encoding high 4bits imm. Code below will encode the
23391 remaining low 12bits. */
23392 newval
|= (value
& 0x0000f000) << 4;
23393 newimm
= value
& 0x00000fff;
23398 if (newimm
== (unsigned int)FAIL
)
23400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23401 _("invalid constant (%lx) after fixup"),
23402 (unsigned long) value
);
23406 newval
|= (newimm
& 0x800) << 15;
23407 newval
|= (newimm
& 0x700) << 4;
23408 newval
|= (newimm
& 0x0ff);
23410 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23411 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23414 case BFD_RELOC_ARM_SMC
:
23415 if (((unsigned long) value
) > 0xffff)
23416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23417 _("invalid smc expression"));
23418 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23419 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23420 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23423 case BFD_RELOC_ARM_HVC
:
23424 if (((unsigned long) value
) > 0xffff)
23425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23426 _("invalid hvc expression"));
23427 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23428 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23429 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23432 case BFD_RELOC_ARM_SWI
:
23433 if (fixP
->tc_fix_data
!= 0)
23435 if (((unsigned long) value
) > 0xff)
23436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23437 _("invalid swi expression"));
23438 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23440 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23444 if (((unsigned long) value
) > 0x00ffffff)
23445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23446 _("invalid swi expression"));
23447 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23449 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23453 case BFD_RELOC_ARM_MULTI
:
23454 if (((unsigned long) value
) > 0xffff)
23455 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23456 _("invalid expression in load/store multiple"));
23457 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23458 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23462 case BFD_RELOC_ARM_PCREL_CALL
:
23464 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23466 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23467 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23468 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23469 /* Flip the bl to blx. This is a simple flip
23470 bit here because we generate PCREL_CALL for
23471 unconditional bls. */
23473 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23474 newval
= newval
| 0x10000000;
23475 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23481 goto arm_branch_common
;
23483 case BFD_RELOC_ARM_PCREL_JUMP
:
23484 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23486 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23487 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23488 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23490 /* This would map to a bl<cond>, b<cond>,
23491 b<always> to a Thumb function. We
23492 need to force a relocation for this particular
23494 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23497 /* Fall through. */
23499 case BFD_RELOC_ARM_PLT32
:
23501 case BFD_RELOC_ARM_PCREL_BRANCH
:
23503 goto arm_branch_common
;
23505 case BFD_RELOC_ARM_PCREL_BLX
:
23508 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23510 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23511 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23512 && ARM_IS_FUNC (fixP
->fx_addsy
))
23514 /* Flip the blx to a bl and warn. */
23515 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23516 newval
= 0xeb000000;
23517 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23518 _("blx to '%s' an ARM ISA state function changed to bl"),
23520 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23526 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23527 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23531 /* We are going to store value (shifted right by two) in the
23532 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23533 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23534 also be be clear. */
23536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23537 _("misaligned branch destination"));
23538 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23539 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23542 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23544 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23545 newval
|= (value
>> 2) & 0x00ffffff;
23546 /* Set the H bit on BLX instructions. */
23550 newval
|= 0x01000000;
23552 newval
&= ~0x01000000;
23554 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23558 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23559 /* CBZ can only branch forward. */
23561 /* Attempts to use CBZ to branch to the next instruction
23562 (which, strictly speaking, are prohibited) will be turned into
23565 FIXME: It may be better to remove the instruction completely and
23566 perform relaxation. */
23569 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23570 newval
= 0xbf00; /* NOP encoding T1 */
23571 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23578 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23580 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23581 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23582 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23587 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23588 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23591 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23593 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23594 newval
|= (value
& 0x1ff) >> 1;
23595 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23599 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23600 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23603 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23605 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23606 newval
|= (value
& 0xfff) >> 1;
23607 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23611 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23613 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23614 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23615 && ARM_IS_FUNC (fixP
->fx_addsy
)
23616 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23618 /* Force a relocation for a branch 20 bits wide. */
23621 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23623 _("conditional branch out of range"));
23625 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23628 addressT S
, J1
, J2
, lo
, hi
;
23630 S
= (value
& 0x00100000) >> 20;
23631 J2
= (value
& 0x00080000) >> 19;
23632 J1
= (value
& 0x00040000) >> 18;
23633 hi
= (value
& 0x0003f000) >> 12;
23634 lo
= (value
& 0x00000ffe) >> 1;
23636 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23637 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23638 newval
|= (S
<< 10) | hi
;
23639 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23640 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23641 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23645 case BFD_RELOC_THUMB_PCREL_BLX
:
23646 /* If there is a blx from a thumb state function to
23647 another thumb function flip this to a bl and warn
23651 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23652 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23653 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23655 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23656 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23657 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23659 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23660 newval
= newval
| 0x1000;
23661 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23662 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23667 goto thumb_bl_common
;
23669 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23670 /* A bl from Thumb state ISA to an internal ARM state function
23671 is converted to a blx. */
23673 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23674 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23675 && ARM_IS_FUNC (fixP
->fx_addsy
)
23676 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23678 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23679 newval
= newval
& ~0x1000;
23680 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23681 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23687 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23688 /* For a BLX instruction, make sure that the relocation is rounded up
23689 to a word boundary. This follows the semantics of the instruction
23690 which specifies that bit 1 of the target address will come from bit
23691 1 of the base address. */
23692 value
= (value
+ 3) & ~ 3;
23695 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23696 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23697 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23700 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23702 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23704 else if ((value
& ~0x1ffffff)
23705 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23707 _("Thumb2 branch out of range"));
23710 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23711 encode_thumb2_b_bl_offset (buf
, value
);
23715 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23716 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23719 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23720 encode_thumb2_b_bl_offset (buf
, value
);
23725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23730 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23731 md_number_to_chars (buf
, value
, 2);
23735 case BFD_RELOC_ARM_TLS_CALL
:
23736 case BFD_RELOC_ARM_THM_TLS_CALL
:
23737 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23738 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23739 case BFD_RELOC_ARM_TLS_GOTDESC
:
23740 case BFD_RELOC_ARM_TLS_GD32
:
23741 case BFD_RELOC_ARM_TLS_LE32
:
23742 case BFD_RELOC_ARM_TLS_IE32
:
23743 case BFD_RELOC_ARM_TLS_LDM32
:
23744 case BFD_RELOC_ARM_TLS_LDO32
:
23745 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23748 case BFD_RELOC_ARM_GOT32
:
23749 case BFD_RELOC_ARM_GOTOFF
:
23752 case BFD_RELOC_ARM_GOT_PREL
:
23753 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23754 md_number_to_chars (buf
, value
, 4);
23757 case BFD_RELOC_ARM_TARGET2
:
23758 /* TARGET2 is not partial-inplace, so we need to write the
23759 addend here for REL targets, because it won't be written out
23760 during reloc processing later. */
23761 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23762 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23766 case BFD_RELOC_RVA
:
23768 case BFD_RELOC_ARM_TARGET1
:
23769 case BFD_RELOC_ARM_ROSEGREL32
:
23770 case BFD_RELOC_ARM_SBREL32
:
23771 case BFD_RELOC_32_PCREL
:
23773 case BFD_RELOC_32_SECREL
:
23775 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23777 /* For WinCE we only do this for pcrel fixups. */
23778 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23780 md_number_to_chars (buf
, value
, 4);
23784 case BFD_RELOC_ARM_PREL31
:
23785 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23787 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23788 if ((value
^ (value
>> 1)) & 0x40000000)
23790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23791 _("rel31 relocation overflow"));
23793 newval
|= value
& 0x7fffffff;
23794 md_number_to_chars (buf
, newval
, 4);
23799 case BFD_RELOC_ARM_CP_OFF_IMM
:
23800 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23801 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23802 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23804 newval
= get_thumb32_insn (buf
);
23805 if ((newval
& 0x0f200f00) == 0x0d000900)
23807 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23808 has permitted values that are multiples of 2, in the range 0
23810 if (value
< -510 || value
> 510 || (value
& 1))
23811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23812 _("co-processor offset out of range"));
23814 else if (value
< -1023 || value
> 1023 || (value
& 3))
23815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23816 _("co-processor offset out of range"));
23821 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23822 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23823 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23825 newval
= get_thumb32_insn (buf
);
23827 newval
&= 0xffffff00;
23830 newval
&= 0xff7fff00;
23831 if ((newval
& 0x0f200f00) == 0x0d000900)
23833 /* This is a fp16 vstr/vldr.
23835 It requires the immediate offset in the instruction is shifted
23836 left by 1 to be a half-word offset.
23838 Here, left shift by 1 first, and later right shift by 2
23839 should get the right offset. */
23842 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23844 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23845 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23846 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23848 put_thumb32_insn (buf
, newval
);
23851 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23852 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23853 if (value
< -255 || value
> 255)
23854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23855 _("co-processor offset out of range"));
23857 goto cp_off_common
;
23859 case BFD_RELOC_ARM_THUMB_OFFSET
:
23860 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23861 /* Exactly what ranges, and where the offset is inserted depends
23862 on the type of instruction, we can establish this from the
23864 switch (newval
>> 12)
23866 case 4: /* PC load. */
23867 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23868 forced to zero for these loads; md_pcrel_from has already
23869 compensated for this. */
23871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23872 _("invalid offset, target not word aligned (0x%08lX)"),
23873 (((unsigned long) fixP
->fx_frag
->fr_address
23874 + (unsigned long) fixP
->fx_where
) & ~3)
23875 + (unsigned long) value
);
23877 if (value
& ~0x3fc)
23878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23879 _("invalid offset, value too big (0x%08lX)"),
23882 newval
|= value
>> 2;
23885 case 9: /* SP load/store. */
23886 if (value
& ~0x3fc)
23887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23888 _("invalid offset, value too big (0x%08lX)"),
23890 newval
|= value
>> 2;
23893 case 6: /* Word load/store. */
23895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23896 _("invalid offset, value too big (0x%08lX)"),
23898 newval
|= value
<< 4; /* 6 - 2. */
23901 case 7: /* Byte load/store. */
23903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23904 _("invalid offset, value too big (0x%08lX)"),
23906 newval
|= value
<< 6;
23909 case 8: /* Halfword load/store. */
23911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23912 _("invalid offset, value too big (0x%08lX)"),
23914 newval
|= value
<< 5; /* 6 - 1. */
23918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23919 "Unable to process relocation for thumb opcode: %lx",
23920 (unsigned long) newval
);
23923 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23926 case BFD_RELOC_ARM_THUMB_ADD
:
23927 /* This is a complicated relocation, since we use it for all of
23928 the following immediate relocations:
23932 9bit ADD/SUB SP word-aligned
23933 10bit ADD PC/SP word-aligned
23935 The type of instruction being processed is encoded in the
23942 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23944 int rd
= (newval
>> 4) & 0xf;
23945 int rs
= newval
& 0xf;
23946 int subtract
= !!(newval
& 0x8000);
23948 /* Check for HI regs, only very restricted cases allowed:
23949 Adjusting SP, and using PC or SP to get an address. */
23950 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23951 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23953 _("invalid Hi register with immediate"));
23955 /* If value is negative, choose the opposite instruction. */
23959 subtract
= !subtract
;
23961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23962 _("immediate value out of range"));
23967 if (value
& ~0x1fc)
23968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23969 _("invalid immediate for stack address calculation"));
23970 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23971 newval
|= value
>> 2;
23973 else if (rs
== REG_PC
|| rs
== REG_SP
)
23975 /* PR gas/18541. If the addition is for a defined symbol
23976 within range of an ADR instruction then accept it. */
23979 && fixP
->fx_addsy
!= NULL
)
23983 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23984 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23985 || S_IS_WEAK (fixP
->fx_addsy
))
23987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23988 _("address calculation needs a strongly defined nearby symbol"));
23992 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23994 /* Round up to the next 4-byte boundary. */
23999 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24004 _("symbol too far away"));
24014 if (subtract
|| value
& ~0x3fc)
24015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24016 _("invalid immediate for address calculation (value = 0x%08lX)"),
24017 (unsigned long) (subtract
? - value
: value
));
24018 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24020 newval
|= value
>> 2;
24025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24026 _("immediate value out of range"));
24027 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24028 newval
|= (rd
<< 8) | value
;
24033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24034 _("immediate value out of range"));
24035 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24036 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24039 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24042 case BFD_RELOC_ARM_THUMB_IMM
:
24043 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24044 if (value
< 0 || value
> 255)
24045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24046 _("invalid immediate: %ld is out of range"),
24049 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24052 case BFD_RELOC_ARM_THUMB_SHIFT
:
24053 /* 5bit shift value (0..32). LSL cannot take 32. */
24054 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24055 temp
= newval
& 0xf800;
24056 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24058 _("invalid shift value: %ld"), (long) value
);
24059 /* Shifts of zero must be encoded as LSL. */
24061 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24062 /* Shifts of 32 are encoded as zero. */
24063 else if (value
== 32)
24065 newval
|= value
<< 6;
24066 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24069 case BFD_RELOC_VTABLE_INHERIT
:
24070 case BFD_RELOC_VTABLE_ENTRY
:
24074 case BFD_RELOC_ARM_MOVW
:
24075 case BFD_RELOC_ARM_MOVT
:
24076 case BFD_RELOC_ARM_THUMB_MOVW
:
24077 case BFD_RELOC_ARM_THUMB_MOVT
:
24078 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24080 /* REL format relocations are limited to a 16-bit addend. */
24081 if (!fixP
->fx_done
)
24083 if (value
< -0x8000 || value
> 0x7fff)
24084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24085 _("offset out of range"));
24087 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24088 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24093 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24094 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24096 newval
= get_thumb32_insn (buf
);
24097 newval
&= 0xfbf08f00;
24098 newval
|= (value
& 0xf000) << 4;
24099 newval
|= (value
& 0x0800) << 15;
24100 newval
|= (value
& 0x0700) << 4;
24101 newval
|= (value
& 0x00ff);
24102 put_thumb32_insn (buf
, newval
);
24106 newval
= md_chars_to_number (buf
, 4);
24107 newval
&= 0xfff0f000;
24108 newval
|= value
& 0x0fff;
24109 newval
|= (value
& 0xf000) << 4;
24110 md_number_to_chars (buf
, newval
, 4);
24115 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24116 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24117 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24118 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24119 gas_assert (!fixP
->fx_done
);
24122 bfd_boolean is_mov
;
24123 bfd_vma encoded_addend
= value
;
24125 /* Check that addend can be encoded in instruction. */
24126 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24128 _("the offset 0x%08lX is not representable"),
24129 (unsigned long) encoded_addend
);
24131 /* Extract the instruction. */
24132 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24133 is_mov
= (insn
& 0xf800) == 0x2000;
24138 if (!seg
->use_rela_p
)
24139 insn
|= encoded_addend
;
24145 /* Extract the instruction. */
24146 /* Encoding is the following
24151 /* The following conditions must be true :
24156 rd
= (insn
>> 4) & 0xf;
24158 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24160 _("Unable to process relocation for thumb opcode: %lx"),
24161 (unsigned long) insn
);
24163 /* Encode as ADD immediate8 thumb 1 code. */
24164 insn
= 0x3000 | (rd
<< 8);
24166 /* Place the encoded addend into the first 8 bits of the
24168 if (!seg
->use_rela_p
)
24169 insn
|= encoded_addend
;
24172 /* Update the instruction. */
24173 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24177 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24178 case BFD_RELOC_ARM_ALU_PC_G0
:
24179 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24180 case BFD_RELOC_ARM_ALU_PC_G1
:
24181 case BFD_RELOC_ARM_ALU_PC_G2
:
24182 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24183 case BFD_RELOC_ARM_ALU_SB_G0
:
24184 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24185 case BFD_RELOC_ARM_ALU_SB_G1
:
24186 case BFD_RELOC_ARM_ALU_SB_G2
:
24187 gas_assert (!fixP
->fx_done
);
24188 if (!seg
->use_rela_p
)
24191 bfd_vma encoded_addend
;
24192 bfd_vma addend_abs
= abs (value
);
24194 /* Check that the absolute value of the addend can be
24195 expressed as an 8-bit constant plus a rotation. */
24196 encoded_addend
= encode_arm_immediate (addend_abs
);
24197 if (encoded_addend
== (unsigned int) FAIL
)
24198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24199 _("the offset 0x%08lX is not representable"),
24200 (unsigned long) addend_abs
);
24202 /* Extract the instruction. */
24203 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24205 /* If the addend is positive, use an ADD instruction.
24206 Otherwise use a SUB. Take care not to destroy the S bit. */
24207 insn
&= 0xff1fffff;
24213 /* Place the encoded addend into the first 12 bits of the
24215 insn
&= 0xfffff000;
24216 insn
|= encoded_addend
;
24218 /* Update the instruction. */
24219 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24223 case BFD_RELOC_ARM_LDR_PC_G0
:
24224 case BFD_RELOC_ARM_LDR_PC_G1
:
24225 case BFD_RELOC_ARM_LDR_PC_G2
:
24226 case BFD_RELOC_ARM_LDR_SB_G0
:
24227 case BFD_RELOC_ARM_LDR_SB_G1
:
24228 case BFD_RELOC_ARM_LDR_SB_G2
:
24229 gas_assert (!fixP
->fx_done
);
24230 if (!seg
->use_rela_p
)
24233 bfd_vma addend_abs
= abs (value
);
24235 /* Check that the absolute value of the addend can be
24236 encoded in 12 bits. */
24237 if (addend_abs
>= 0x1000)
24238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24239 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24240 (unsigned long) addend_abs
);
24242 /* Extract the instruction. */
24243 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24245 /* If the addend is negative, clear bit 23 of the instruction.
24246 Otherwise set it. */
24248 insn
&= ~(1 << 23);
24252 /* Place the absolute value of the addend into the first 12 bits
24253 of the instruction. */
24254 insn
&= 0xfffff000;
24255 insn
|= addend_abs
;
24257 /* Update the instruction. */
24258 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24262 case BFD_RELOC_ARM_LDRS_PC_G0
:
24263 case BFD_RELOC_ARM_LDRS_PC_G1
:
24264 case BFD_RELOC_ARM_LDRS_PC_G2
:
24265 case BFD_RELOC_ARM_LDRS_SB_G0
:
24266 case BFD_RELOC_ARM_LDRS_SB_G1
:
24267 case BFD_RELOC_ARM_LDRS_SB_G2
:
24268 gas_assert (!fixP
->fx_done
);
24269 if (!seg
->use_rela_p
)
24272 bfd_vma addend_abs
= abs (value
);
24274 /* Check that the absolute value of the addend can be
24275 encoded in 8 bits. */
24276 if (addend_abs
>= 0x100)
24277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24278 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24279 (unsigned long) addend_abs
);
24281 /* Extract the instruction. */
24282 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24284 /* If the addend is negative, clear bit 23 of the instruction.
24285 Otherwise set it. */
24287 insn
&= ~(1 << 23);
24291 /* Place the first four bits of the absolute value of the addend
24292 into the first 4 bits of the instruction, and the remaining
24293 four into bits 8 .. 11. */
24294 insn
&= 0xfffff0f0;
24295 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24297 /* Update the instruction. */
24298 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24302 case BFD_RELOC_ARM_LDC_PC_G0
:
24303 case BFD_RELOC_ARM_LDC_PC_G1
:
24304 case BFD_RELOC_ARM_LDC_PC_G2
:
24305 case BFD_RELOC_ARM_LDC_SB_G0
:
24306 case BFD_RELOC_ARM_LDC_SB_G1
:
24307 case BFD_RELOC_ARM_LDC_SB_G2
:
24308 gas_assert (!fixP
->fx_done
);
24309 if (!seg
->use_rela_p
)
24312 bfd_vma addend_abs
= abs (value
);
24314 /* Check that the absolute value of the addend is a multiple of
24315 four and, when divided by four, fits in 8 bits. */
24316 if (addend_abs
& 0x3)
24317 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24318 _("bad offset 0x%08lX (must be word-aligned)"),
24319 (unsigned long) addend_abs
);
24321 if ((addend_abs
>> 2) > 0xff)
24322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24323 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24324 (unsigned long) addend_abs
);
24326 /* Extract the instruction. */
24327 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24329 /* If the addend is negative, clear bit 23 of the instruction.
24330 Otherwise set it. */
24332 insn
&= ~(1 << 23);
24336 /* Place the addend (divided by four) into the first eight
24337 bits of the instruction. */
24338 insn
&= 0xfffffff0;
24339 insn
|= addend_abs
>> 2;
24341 /* Update the instruction. */
24342 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24346 case BFD_RELOC_ARM_V4BX
:
24347 /* This will need to go in the object file. */
24351 case BFD_RELOC_UNUSED
:
24353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24354 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24358 /* Translate internal representation of relocation info to BFD target
24362 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24365 bfd_reloc_code_real_type code
;
24367 reloc
= XNEW (arelent
);
24369 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24370 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24371 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24373 if (fixp
->fx_pcrel
)
24375 if (section
->use_rela_p
)
24376 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24378 fixp
->fx_offset
= reloc
->address
;
24380 reloc
->addend
= fixp
->fx_offset
;
24382 switch (fixp
->fx_r_type
)
24385 if (fixp
->fx_pcrel
)
24387 code
= BFD_RELOC_8_PCREL
;
24390 /* Fall through. */
24393 if (fixp
->fx_pcrel
)
24395 code
= BFD_RELOC_16_PCREL
;
24398 /* Fall through. */
24401 if (fixp
->fx_pcrel
)
24403 code
= BFD_RELOC_32_PCREL
;
24406 /* Fall through. */
24408 case BFD_RELOC_ARM_MOVW
:
24409 if (fixp
->fx_pcrel
)
24411 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24414 /* Fall through. */
24416 case BFD_RELOC_ARM_MOVT
:
24417 if (fixp
->fx_pcrel
)
24419 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24422 /* Fall through. */
24424 case BFD_RELOC_ARM_THUMB_MOVW
:
24425 if (fixp
->fx_pcrel
)
24427 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24430 /* Fall through. */
24432 case BFD_RELOC_ARM_THUMB_MOVT
:
24433 if (fixp
->fx_pcrel
)
24435 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24438 /* Fall through. */
24440 case BFD_RELOC_NONE
:
24441 case BFD_RELOC_ARM_PCREL_BRANCH
:
24442 case BFD_RELOC_ARM_PCREL_BLX
:
24443 case BFD_RELOC_RVA
:
24444 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24445 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24446 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24447 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24448 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24449 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24450 case BFD_RELOC_VTABLE_ENTRY
:
24451 case BFD_RELOC_VTABLE_INHERIT
:
24453 case BFD_RELOC_32_SECREL
:
24455 code
= fixp
->fx_r_type
;
24458 case BFD_RELOC_THUMB_PCREL_BLX
:
24460 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24461 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24464 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24467 case BFD_RELOC_ARM_LITERAL
:
24468 case BFD_RELOC_ARM_HWLITERAL
:
24469 /* If this is called then the a literal has
24470 been referenced across a section boundary. */
24471 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24472 _("literal referenced across section boundary"));
24476 case BFD_RELOC_ARM_TLS_CALL
:
24477 case BFD_RELOC_ARM_THM_TLS_CALL
:
24478 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24479 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24480 case BFD_RELOC_ARM_GOT32
:
24481 case BFD_RELOC_ARM_GOTOFF
:
24482 case BFD_RELOC_ARM_GOT_PREL
:
24483 case BFD_RELOC_ARM_PLT32
:
24484 case BFD_RELOC_ARM_TARGET1
:
24485 case BFD_RELOC_ARM_ROSEGREL32
:
24486 case BFD_RELOC_ARM_SBREL32
:
24487 case BFD_RELOC_ARM_PREL31
:
24488 case BFD_RELOC_ARM_TARGET2
:
24489 case BFD_RELOC_ARM_TLS_LDO32
:
24490 case BFD_RELOC_ARM_PCREL_CALL
:
24491 case BFD_RELOC_ARM_PCREL_JUMP
:
24492 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24493 case BFD_RELOC_ARM_ALU_PC_G0
:
24494 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24495 case BFD_RELOC_ARM_ALU_PC_G1
:
24496 case BFD_RELOC_ARM_ALU_PC_G2
:
24497 case BFD_RELOC_ARM_LDR_PC_G0
:
24498 case BFD_RELOC_ARM_LDR_PC_G1
:
24499 case BFD_RELOC_ARM_LDR_PC_G2
:
24500 case BFD_RELOC_ARM_LDRS_PC_G0
:
24501 case BFD_RELOC_ARM_LDRS_PC_G1
:
24502 case BFD_RELOC_ARM_LDRS_PC_G2
:
24503 case BFD_RELOC_ARM_LDC_PC_G0
:
24504 case BFD_RELOC_ARM_LDC_PC_G1
:
24505 case BFD_RELOC_ARM_LDC_PC_G2
:
24506 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24507 case BFD_RELOC_ARM_ALU_SB_G0
:
24508 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24509 case BFD_RELOC_ARM_ALU_SB_G1
:
24510 case BFD_RELOC_ARM_ALU_SB_G2
:
24511 case BFD_RELOC_ARM_LDR_SB_G0
:
24512 case BFD_RELOC_ARM_LDR_SB_G1
:
24513 case BFD_RELOC_ARM_LDR_SB_G2
:
24514 case BFD_RELOC_ARM_LDRS_SB_G0
:
24515 case BFD_RELOC_ARM_LDRS_SB_G1
:
24516 case BFD_RELOC_ARM_LDRS_SB_G2
:
24517 case BFD_RELOC_ARM_LDC_SB_G0
:
24518 case BFD_RELOC_ARM_LDC_SB_G1
:
24519 case BFD_RELOC_ARM_LDC_SB_G2
:
24520 case BFD_RELOC_ARM_V4BX
:
24521 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24522 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24523 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24524 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24525 code
= fixp
->fx_r_type
;
24528 case BFD_RELOC_ARM_TLS_GOTDESC
:
24529 case BFD_RELOC_ARM_TLS_GD32
:
24530 case BFD_RELOC_ARM_TLS_LE32
:
24531 case BFD_RELOC_ARM_TLS_IE32
:
24532 case BFD_RELOC_ARM_TLS_LDM32
:
24533 /* BFD will include the symbol's address in the addend.
24534 But we don't want that, so subtract it out again here. */
24535 if (!S_IS_COMMON (fixp
->fx_addsy
))
24536 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24537 code
= fixp
->fx_r_type
;
24541 case BFD_RELOC_ARM_IMMEDIATE
:
24542 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24543 _("internal relocation (type: IMMEDIATE) not fixed up"));
24546 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24547 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24548 _("ADRL used for a symbol not defined in the same file"));
24551 case BFD_RELOC_ARM_OFFSET_IMM
:
24552 if (section
->use_rela_p
)
24554 code
= fixp
->fx_r_type
;
24558 if (fixp
->fx_addsy
!= NULL
24559 && !S_IS_DEFINED (fixp
->fx_addsy
)
24560 && S_IS_LOCAL (fixp
->fx_addsy
))
24562 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24563 _("undefined local label `%s'"),
24564 S_GET_NAME (fixp
->fx_addsy
));
24568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24569 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24576 switch (fixp
->fx_r_type
)
24578 case BFD_RELOC_NONE
: type
= "NONE"; break;
24579 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24580 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24581 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24582 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24583 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24584 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24585 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24586 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24587 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24588 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24589 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24590 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24591 default: type
= _("<unknown>"); break;
24593 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24594 _("cannot represent %s relocation in this object file format"),
24601 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24603 && fixp
->fx_addsy
== GOT_symbol
)
24605 code
= BFD_RELOC_ARM_GOTPC
;
24606 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24610 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24612 if (reloc
->howto
== NULL
)
24614 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24615 _("cannot represent %s relocation in this object file format"),
24616 bfd_get_reloc_code_name (code
));
24620 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24621 vtable entry to be used in the relocation's section offset. */
24622 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24623 reloc
->address
= fixp
->fx_offset
;
24628 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24631 cons_fix_new_arm (fragS
* frag
,
24635 bfd_reloc_code_real_type reloc
)
24640 FIXME: @@ Should look at CPU word size. */
24644 reloc
= BFD_RELOC_8
;
24647 reloc
= BFD_RELOC_16
;
24651 reloc
= BFD_RELOC_32
;
24654 reloc
= BFD_RELOC_64
;
24659 if (exp
->X_op
== O_secrel
)
24661 exp
->X_op
= O_symbol
;
24662 reloc
= BFD_RELOC_32_SECREL
;
24666 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24669 #if defined (OBJ_COFF)
24671 arm_validate_fix (fixS
* fixP
)
24673 /* If the destination of the branch is a defined symbol which does not have
24674 the THUMB_FUNC attribute, then we must be calling a function which has
24675 the (interfacearm) attribute. We look for the Thumb entry point to that
24676 function and change the branch to refer to that function instead. */
24677 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24678 && fixP
->fx_addsy
!= NULL
24679 && S_IS_DEFINED (fixP
->fx_addsy
)
24680 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24682 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24689 arm_force_relocation (struct fix
* fixp
)
24691 #if defined (OBJ_COFF) && defined (TE_PE)
24692 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24696 /* In case we have a call or a branch to a function in ARM ISA mode from
24697 a thumb function or vice-versa force the relocation. These relocations
24698 are cleared off for some cores that might have blx and simple transformations
24702 switch (fixp
->fx_r_type
)
24704 case BFD_RELOC_ARM_PCREL_JUMP
:
24705 case BFD_RELOC_ARM_PCREL_CALL
:
24706 case BFD_RELOC_THUMB_PCREL_BLX
:
24707 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24711 case BFD_RELOC_ARM_PCREL_BLX
:
24712 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24713 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24714 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24715 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24724 /* Resolve these relocations even if the symbol is extern or weak.
24725 Technically this is probably wrong due to symbol preemption.
24726 In practice these relocations do not have enough range to be useful
24727 at dynamic link time, and some code (e.g. in the Linux kernel)
24728 expects these references to be resolved. */
24729 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24730 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24731 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24732 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24733 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24734 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24735 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24736 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24737 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24738 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24739 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24740 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24741 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24742 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24745 /* Always leave these relocations for the linker. */
24746 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24747 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24748 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24751 /* Always generate relocations against function symbols. */
24752 if (fixp
->fx_r_type
== BFD_RELOC_32
24754 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24757 return generic_force_reloc (fixp
);
24760 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24761 /* Relocations against function names must be left unadjusted,
24762 so that the linker can use this information to generate interworking
24763 stubs. The MIPS version of this function
24764 also prevents relocations that are mips-16 specific, but I do not
24765 know why it does this.
24768 There is one other problem that ought to be addressed here, but
24769 which currently is not: Taking the address of a label (rather
24770 than a function) and then later jumping to that address. Such
24771 addresses also ought to have their bottom bit set (assuming that
24772 they reside in Thumb code), but at the moment they will not. */
24775 arm_fix_adjustable (fixS
* fixP
)
24777 if (fixP
->fx_addsy
== NULL
)
24780 /* Preserve relocations against symbols with function type. */
24781 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24784 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24785 && fixP
->fx_subsy
== NULL
)
24788 /* We need the symbol name for the VTABLE entries. */
24789 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24790 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24793 /* Don't allow symbols to be discarded on GOT related relocs. */
24794 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24795 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24796 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24797 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24798 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24799 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24800 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24801 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24802 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24803 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24804 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24805 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24806 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24807 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24810 /* Similarly for group relocations. */
24811 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24812 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24813 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24816 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24817 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24818 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24819 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24820 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24821 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24822 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24823 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24824 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24827 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24828 offsets, so keep these symbols. */
24829 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24830 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24835 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24839 elf32_arm_target_format (void)
24842 return (target_big_endian
24843 ? "elf32-bigarm-symbian"
24844 : "elf32-littlearm-symbian");
24845 #elif defined (TE_VXWORKS)
24846 return (target_big_endian
24847 ? "elf32-bigarm-vxworks"
24848 : "elf32-littlearm-vxworks");
24849 #elif defined (TE_NACL)
24850 return (target_big_endian
24851 ? "elf32-bigarm-nacl"
24852 : "elf32-littlearm-nacl");
24854 if (target_big_endian
)
24855 return "elf32-bigarm";
24857 return "elf32-littlearm";
24862 armelf_frob_symbol (symbolS
* symp
,
24865 elf_frob_symbol (symp
, puntp
);
24869 /* MD interface: Finalization. */
24874 literal_pool
* pool
;
24876 /* Ensure that all the IT blocks are properly closed. */
24877 check_it_blocks_finished ();
24879 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24881 /* Put it at the end of the relevant section. */
24882 subseg_set (pool
->section
, pool
->sub_section
);
24884 arm_elf_change_section ();
24891 /* Remove any excess mapping symbols generated for alignment frags in
24892 SEC. We may have created a mapping symbol before a zero byte
24893 alignment; remove it if there's a mapping symbol after the
24896 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24897 void *dummy ATTRIBUTE_UNUSED
)
24899 segment_info_type
*seginfo
= seg_info (sec
);
24902 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24905 for (fragp
= seginfo
->frchainP
->frch_root
;
24907 fragp
= fragp
->fr_next
)
24909 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24910 fragS
*next
= fragp
->fr_next
;
24912 /* Variable-sized frags have been converted to fixed size by
24913 this point. But if this was variable-sized to start with,
24914 there will be a fixed-size frag after it. So don't handle
24916 if (sym
== NULL
|| next
== NULL
)
24919 if (S_GET_VALUE (sym
) < next
->fr_address
)
24920 /* Not at the end of this frag. */
24922 know (S_GET_VALUE (sym
) == next
->fr_address
);
24926 if (next
->tc_frag_data
.first_map
!= NULL
)
24928 /* Next frag starts with a mapping symbol. Discard this
24930 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24934 if (next
->fr_next
== NULL
)
24936 /* This mapping symbol is at the end of the section. Discard
24938 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24939 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24943 /* As long as we have empty frags without any mapping symbols,
24945 /* If the next frag is non-empty and does not start with a
24946 mapping symbol, then this mapping symbol is required. */
24947 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24950 next
= next
->fr_next
;
24952 while (next
!= NULL
);
24957 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24961 arm_adjust_symtab (void)
24966 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24968 if (ARM_IS_THUMB (sym
))
24970 if (THUMB_IS_FUNC (sym
))
24972 /* Mark the symbol as a Thumb function. */
24973 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24974 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24975 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24977 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24978 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24980 as_bad (_("%s: unexpected function type: %d"),
24981 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24983 else switch (S_GET_STORAGE_CLASS (sym
))
24986 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24989 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24992 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25000 if (ARM_IS_INTERWORK (sym
))
25001 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25008 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25010 if (ARM_IS_THUMB (sym
))
25012 elf_symbol_type
* elf_sym
;
25014 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25015 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25017 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25018 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25020 /* If it's a .thumb_func, declare it as so,
25021 otherwise tag label as .code 16. */
25022 if (THUMB_IS_FUNC (sym
))
25023 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25024 ST_BRANCH_TO_THUMB
);
25025 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25026 elf_sym
->internal_elf_sym
.st_info
=
25027 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25032 /* Remove any overlapping mapping symbols generated by alignment frags. */
25033 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25034 /* Now do generic ELF adjustments. */
25035 elf_adjust_symtab ();
25039 /* MD interface: Initialization. */
25042 set_constant_flonums (void)
25046 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25047 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25051 /* Auto-select Thumb mode if it's the only available instruction set for the
25052 given architecture. */
25055 autoselect_thumb_from_cpu_variant (void)
25057 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25058 opcode_select (16);
25067 if ( (arm_ops_hsh
= hash_new ()) == NULL
25068 || (arm_cond_hsh
= hash_new ()) == NULL
25069 || (arm_shift_hsh
= hash_new ()) == NULL
25070 || (arm_psr_hsh
= hash_new ()) == NULL
25071 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25072 || (arm_reg_hsh
= hash_new ()) == NULL
25073 || (arm_reloc_hsh
= hash_new ()) == NULL
25074 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25075 as_fatal (_("virtual memory exhausted"));
25077 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25078 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25079 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25080 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25081 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25082 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25083 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25084 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25085 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25086 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25087 (void *) (v7m_psrs
+ i
));
25088 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25089 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25091 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25093 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25094 (void *) (barrier_opt_names
+ i
));
25096 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25098 struct reloc_entry
* entry
= reloc_names
+ i
;
25100 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25101 /* This makes encode_branch() use the EABI versions of this relocation. */
25102 entry
->reloc
= BFD_RELOC_UNUSED
;
25104 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25108 set_constant_flonums ();
25110 /* Set the cpu variant based on the command-line options. We prefer
25111 -mcpu= over -march= if both are set (as for GCC); and we prefer
25112 -mfpu= over any other way of setting the floating point unit.
25113 Use of legacy options with new options are faulted. */
25116 if (mcpu_cpu_opt
|| march_cpu_opt
)
25117 as_bad (_("use of old and new-style options to set CPU type"));
25119 mcpu_cpu_opt
= legacy_cpu
;
25121 else if (!mcpu_cpu_opt
)
25123 mcpu_cpu_opt
= march_cpu_opt
;
25124 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25125 /* Avoid double free in arm_md_end. */
25126 dyn_march_ext_opt
= NULL
;
25132 as_bad (_("use of old and new-style options to set FPU type"));
25134 mfpu_opt
= legacy_fpu
;
25136 else if (!mfpu_opt
)
25138 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25139 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25140 /* Some environments specify a default FPU. If they don't, infer it
25141 from the processor. */
25143 mfpu_opt
= mcpu_fpu_opt
;
25145 mfpu_opt
= march_fpu_opt
;
25147 mfpu_opt
= &fpu_default
;
25153 if (mcpu_cpu_opt
!= NULL
)
25154 mfpu_opt
= &fpu_default
;
25155 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25156 mfpu_opt
= &fpu_arch_vfp_v2
;
25158 mfpu_opt
= &fpu_arch_fpa
;
25164 mcpu_cpu_opt
= &cpu_default
;
25165 selected_cpu
= cpu_default
;
25167 else if (dyn_mcpu_ext_opt
)
25168 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25170 selected_cpu
= *mcpu_cpu_opt
;
25172 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25173 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25174 else if (mcpu_cpu_opt
)
25175 selected_cpu
= *mcpu_cpu_opt
;
25177 mcpu_cpu_opt
= &arm_arch_any
;
25180 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25181 if (dyn_mcpu_ext_opt
)
25182 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25184 autoselect_thumb_from_cpu_variant ();
25186 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25188 #if defined OBJ_COFF || defined OBJ_ELF
25190 unsigned int flags
= 0;
25192 #if defined OBJ_ELF
25193 flags
= meabi_flags
;
25195 switch (meabi_flags
)
25197 case EF_ARM_EABI_UNKNOWN
:
25199 /* Set the flags in the private structure. */
25200 if (uses_apcs_26
) flags
|= F_APCS26
;
25201 if (support_interwork
) flags
|= F_INTERWORK
;
25202 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25203 if (pic_code
) flags
|= F_PIC
;
25204 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25205 flags
|= F_SOFT_FLOAT
;
25207 switch (mfloat_abi_opt
)
25209 case ARM_FLOAT_ABI_SOFT
:
25210 case ARM_FLOAT_ABI_SOFTFP
:
25211 flags
|= F_SOFT_FLOAT
;
25214 case ARM_FLOAT_ABI_HARD
:
25215 if (flags
& F_SOFT_FLOAT
)
25216 as_bad (_("hard-float conflicts with specified fpu"));
25220 /* Using pure-endian doubles (even if soft-float). */
25221 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25222 flags
|= F_VFP_FLOAT
;
25224 #if defined OBJ_ELF
25225 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25226 flags
|= EF_ARM_MAVERICK_FLOAT
;
25229 case EF_ARM_EABI_VER4
:
25230 case EF_ARM_EABI_VER5
:
25231 /* No additional flags to set. */
25238 bfd_set_private_flags (stdoutput
, flags
);
25240 /* We have run out flags in the COFF header to encode the
25241 status of ATPCS support, so instead we create a dummy,
25242 empty, debug section called .arm.atpcs. */
25247 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25251 bfd_set_section_flags
25252 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25253 bfd_set_section_size (stdoutput
, sec
, 0);
25254 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25260 /* Record the CPU type as well. */
25261 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25262 mach
= bfd_mach_arm_iWMMXt2
;
25263 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25264 mach
= bfd_mach_arm_iWMMXt
;
25265 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25266 mach
= bfd_mach_arm_XScale
;
25267 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25268 mach
= bfd_mach_arm_ep9312
;
25269 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25270 mach
= bfd_mach_arm_5TE
;
25271 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25273 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25274 mach
= bfd_mach_arm_5T
;
25276 mach
= bfd_mach_arm_5
;
25278 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25280 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25281 mach
= bfd_mach_arm_4T
;
25283 mach
= bfd_mach_arm_4
;
25285 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25286 mach
= bfd_mach_arm_3M
;
25287 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25288 mach
= bfd_mach_arm_3
;
25289 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25290 mach
= bfd_mach_arm_2a
;
25291 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25292 mach
= bfd_mach_arm_2
;
25294 mach
= bfd_mach_arm_unknown
;
25296 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25299 /* Command line processing. */
25302 Invocation line includes a switch not recognized by the base assembler.
25303 See if it's a processor-specific option.
25305 This routine is somewhat complicated by the need for backwards
25306 compatibility (since older releases of gcc can't be changed).
25307 The new options try to make the interface as compatible as
25310 New options (supported) are:
25312 -mcpu=<cpu name> Assemble for selected processor
25313 -march=<architecture name> Assemble for selected architecture
25314 -mfpu=<fpu architecture> Assemble for selected FPU.
25315 -EB/-mbig-endian Big-endian
25316 -EL/-mlittle-endian Little-endian
25317 -k Generate PIC code
25318 -mthumb Start in Thumb mode
25319 -mthumb-interwork Code supports ARM/Thumb interworking
25321 -m[no-]warn-deprecated Warn about deprecated features
25322 -m[no-]warn-syms Warn when symbols match instructions
25324 For now we will also provide support for:
25326 -mapcs-32 32-bit Program counter
25327 -mapcs-26 26-bit Program counter
25328 -macps-float Floats passed in FP registers
25329 -mapcs-reentrant Reentrant code
25331 (sometime these will probably be replaced with -mapcs=<list of options>
25332 and -matpcs=<list of options>)
25334 The remaining options are only supported for back-wards compatibility.
25335 Cpu variants, the arm part is optional:
25336 -m[arm]1 Currently not supported.
25337 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25338 -m[arm]3 Arm 3 processor
25339 -m[arm]6[xx], Arm 6 processors
25340 -m[arm]7[xx][t][[d]m] Arm 7 processors
25341 -m[arm]8[10] Arm 8 processors
25342 -m[arm]9[20][tdmi] Arm 9 processors
25343 -mstrongarm[110[0]] StrongARM processors
25344 -mxscale XScale processors
25345 -m[arm]v[2345[t[e]]] Arm architectures
25346 -mall All (except the ARM1)
25348 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25349 -mfpe-old (No float load/store multiples)
25350 -mvfpxd VFP Single precision
25352 -mno-fpu Disable all floating point instructions
25354 The following CPU names are recognized:
25355 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25356 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25357 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25358 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25359 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25360 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25361 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25365 const char * md_shortopts
= "m:k";
25367 #ifdef ARM_BI_ENDIAN
25368 #define OPTION_EB (OPTION_MD_BASE + 0)
25369 #define OPTION_EL (OPTION_MD_BASE + 1)
25371 #if TARGET_BYTES_BIG_ENDIAN
25372 #define OPTION_EB (OPTION_MD_BASE + 0)
25374 #define OPTION_EL (OPTION_MD_BASE + 1)
25377 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25379 struct option md_longopts
[] =
25382 {"EB", no_argument
, NULL
, OPTION_EB
},
25385 {"EL", no_argument
, NULL
, OPTION_EL
},
25387 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25388 {NULL
, no_argument
, NULL
, 0}
25392 size_t md_longopts_size
= sizeof (md_longopts
);
25394 struct arm_option_table
25396 const char *option
; /* Option name to match. */
25397 const char *help
; /* Help information. */
25398 int *var
; /* Variable to change. */
25399 int value
; /* What to change it to. */
25400 const char *deprecated
; /* If non-null, print this message. */
25403 struct arm_option_table arm_opts
[] =
25405 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25406 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25407 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25408 &support_interwork
, 1, NULL
},
25409 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25410 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25411 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25413 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25414 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25415 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25416 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25419 /* These are recognized by the assembler, but have no affect on code. */
25420 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25421 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25423 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25424 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25425 &warn_on_deprecated
, 0, NULL
},
25426 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25427 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25428 {NULL
, NULL
, NULL
, 0, NULL
}
25431 struct arm_legacy_option_table
25433 const char *option
; /* Option name to match. */
25434 const arm_feature_set
**var
; /* Variable to change. */
25435 const arm_feature_set value
; /* What to change it to. */
25436 const char *deprecated
; /* If non-null, print this message. */
25439 const struct arm_legacy_option_table arm_legacy_opts
[] =
25441 /* DON'T add any new processors to this list -- we want the whole list
25442 to go away... Add them to the processors table instead. */
25443 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25444 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25445 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25446 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25447 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25448 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25449 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25450 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25451 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25452 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25453 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25454 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25455 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25456 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25457 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25458 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25459 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25460 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25461 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25462 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25463 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25464 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25465 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25466 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25467 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25468 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25469 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25470 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25471 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25472 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25473 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25474 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25475 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25476 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25477 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25478 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25479 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25480 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25481 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25482 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25483 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25484 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25485 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25486 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25487 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25488 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25489 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25490 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25491 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25492 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25493 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25494 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25495 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25496 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25497 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25498 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25499 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25500 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25501 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25502 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25503 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25504 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25505 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25506 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25507 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25508 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25509 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25510 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25511 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25512 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25513 N_("use -mcpu=strongarm110")},
25514 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25515 N_("use -mcpu=strongarm1100")},
25516 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25517 N_("use -mcpu=strongarm1110")},
25518 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25519 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25520 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25522 /* Architecture variants -- don't add any more to this list either. */
25523 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25524 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25525 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25526 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25527 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25528 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25529 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25530 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25531 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25532 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25533 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25534 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25535 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25536 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25537 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25538 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25539 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25540 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25542 /* Floating point variants -- don't add any more to this list either. */
25543 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25544 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25545 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25546 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25547 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25549 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25552 struct arm_cpu_option_table
25556 const arm_feature_set value
;
25557 const arm_feature_set ext
;
25558 /* For some CPUs we assume an FPU unless the user explicitly sets
25560 const arm_feature_set default_fpu
;
25561 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25563 const char *canonical_name
;
25566 /* This list should, at a minimum, contain all the cpu names
25567 recognized by GCC. */
25568 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25569 static const struct arm_cpu_option_table arm_cpus
[] =
25571 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25574 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25577 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25580 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25583 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25586 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25589 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25592 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25595 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25598 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25601 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25604 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25607 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25610 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25613 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25616 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25619 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25622 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25625 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25628 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25631 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25634 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25637 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25640 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25643 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25646 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25649 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25652 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25655 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25658 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25661 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25664 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25667 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25670 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25673 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25676 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25679 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25682 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25685 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25688 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25691 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25694 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25697 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25700 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25703 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25706 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25710 /* For V5 or later processors we default to using VFP; but the user
25711 should really set the FPU type explicitly. */
25712 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25715 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25718 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25721 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25724 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25727 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25730 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25733 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25736 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25739 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25742 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25745 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25748 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25751 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25754 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25757 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25760 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25763 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25766 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25769 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25772 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25775 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25778 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25781 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25784 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25787 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25790 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25793 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25796 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25799 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25802 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25805 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25808 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25811 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25814 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
25817 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
25820 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
25821 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25823 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
25825 FPU_ARCH_NEON_VFP_V4
),
25826 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
25827 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25828 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25829 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
25830 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25831 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25832 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
25834 FPU_ARCH_NEON_VFP_V4
),
25835 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
25837 FPU_ARCH_NEON_VFP_V4
),
25838 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
25840 FPU_ARCH_NEON_VFP_V4
),
25841 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
25842 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25843 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25844 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
25845 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25846 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25847 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
25848 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25849 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25850 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
25851 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25852 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25853 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
25854 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25855 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25856 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
25857 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25858 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25859 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
25862 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
25864 FPU_ARCH_VFP_V3D16
),
25865 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
25866 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25868 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
25869 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25870 FPU_ARCH_VFP_V3D16
),
25871 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
25872 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25873 FPU_ARCH_VFP_V3D16
),
25874 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
25875 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25876 FPU_ARCH_NEON_VFP_ARMV8
),
25877 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
25878 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25880 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
25883 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
25886 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
25889 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
25892 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
25895 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
25898 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
25901 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
25902 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25903 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25905 /* ??? XSCALE is really an architecture. */
25906 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
25910 /* ??? iwmmxt is not a processor. */
25911 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
25914 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
25917 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
25922 ARM_CPU_OPT ("ep9312", "ARM920T",
25923 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25924 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
25926 /* Marvell processors. */
25927 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
25928 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25929 FPU_ARCH_VFP_V3D16
),
25930 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
25931 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25932 FPU_ARCH_NEON_VFP_V4
),
25934 /* APM X-Gene family. */
25935 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
25937 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25938 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
25939 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25940 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25942 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25946 struct arm_arch_option_table
25950 const arm_feature_set value
;
25951 const arm_feature_set default_fpu
;
25954 /* This list should, at a minimum, contain all the architecture names
25955 recognized by GCC. */
25956 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25957 static const struct arm_arch_option_table arm_archs
[] =
25959 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25960 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25961 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25962 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25963 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25964 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25965 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25966 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25967 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25968 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25969 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25970 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25971 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25972 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25973 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25974 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25975 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25976 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25977 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25978 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25979 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25980 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25981 kept to preserve existing behaviour. */
25982 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25983 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25984 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25985 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25986 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25987 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25988 kept to preserve existing behaviour. */
25989 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25990 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25991 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25992 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25993 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25994 /* The official spelling of the ARMv7 profile variants is the dashed form.
25995 Accept the non-dashed form for compatibility with old toolchains. */
25996 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25997 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25998 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25999 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26000 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26001 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26002 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26003 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26004 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26005 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26006 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26007 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26008 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26009 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26010 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26011 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26012 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26013 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26014 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26016 #undef ARM_ARCH_OPT
26018 /* ISA extensions in the co-processor and main instruction set space. */
26019 struct arm_option_extension_value_table
26023 const arm_feature_set merge_value
;
26024 const arm_feature_set clear_value
;
26025 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26026 indicates that an extension is available for all architectures while
26027 ARM_ANY marks an empty entry. */
26028 const arm_feature_set allowed_archs
[2];
26031 /* The following table must be in alphabetical order with a NULL last entry.
26033 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26034 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26035 static const struct arm_option_extension_value_table arm_extensions
[] =
26037 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26038 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26039 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26040 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26041 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26042 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26043 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26045 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26046 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26047 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26048 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26049 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26050 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26051 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26053 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26054 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26055 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26056 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26057 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26058 Thumb divide instruction. Due to this having the same name as the
26059 previous entry, this will be ignored when doing command-line parsing and
26060 only considered by build attribute selection code. */
26061 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26062 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26063 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26064 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26065 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26066 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26067 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26068 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26069 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26070 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26071 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26072 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26073 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26074 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26075 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26076 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26077 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26078 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26079 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26080 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26081 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26082 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26083 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26084 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26085 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26086 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26087 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26088 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26089 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26090 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26091 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26092 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26093 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26095 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26096 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26097 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26098 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26099 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26103 /* ISA floating-point and Advanced SIMD extensions. */
26104 struct arm_option_fpu_value_table
26107 const arm_feature_set value
;
26110 /* This list should, at a minimum, contain all the fpu names
26111 recognized by GCC. */
26112 static const struct arm_option_fpu_value_table arm_fpus
[] =
26114 {"softfpa", FPU_NONE
},
26115 {"fpe", FPU_ARCH_FPE
},
26116 {"fpe2", FPU_ARCH_FPE
},
26117 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26118 {"fpa", FPU_ARCH_FPA
},
26119 {"fpa10", FPU_ARCH_FPA
},
26120 {"fpa11", FPU_ARCH_FPA
},
26121 {"arm7500fe", FPU_ARCH_FPA
},
26122 {"softvfp", FPU_ARCH_VFP
},
26123 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26124 {"vfp", FPU_ARCH_VFP_V2
},
26125 {"vfp9", FPU_ARCH_VFP_V2
},
26126 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26127 {"vfp10", FPU_ARCH_VFP_V2
},
26128 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26129 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26130 {"vfpv2", FPU_ARCH_VFP_V2
},
26131 {"vfpv3", FPU_ARCH_VFP_V3
},
26132 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26133 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26134 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26135 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26136 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26137 {"arm1020t", FPU_ARCH_VFP_V1
},
26138 {"arm1020e", FPU_ARCH_VFP_V2
},
26139 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26140 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26141 {"maverick", FPU_ARCH_MAVERICK
},
26142 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26143 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26144 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26145 {"vfpv4", FPU_ARCH_VFP_V4
},
26146 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26147 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26148 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26149 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26150 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26151 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26152 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26153 {"crypto-neon-fp-armv8",
26154 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26155 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26156 {"crypto-neon-fp-armv8.1",
26157 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26158 {NULL
, ARM_ARCH_NONE
}
26161 struct arm_option_value_table
26167 static const struct arm_option_value_table arm_float_abis
[] =
26169 {"hard", ARM_FLOAT_ABI_HARD
},
26170 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26171 {"soft", ARM_FLOAT_ABI_SOFT
},
26176 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26177 static const struct arm_option_value_table arm_eabis
[] =
26179 {"gnu", EF_ARM_EABI_UNKNOWN
},
26180 {"4", EF_ARM_EABI_VER4
},
26181 {"5", EF_ARM_EABI_VER5
},
26186 struct arm_long_option_table
26188 const char * option
; /* Substring to match. */
26189 const char * help
; /* Help information. */
26190 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26191 const char * deprecated
; /* If non-null, print this message. */
26195 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26196 arm_feature_set
**ext_set_p
)
26198 /* We insist on extensions being specified in alphabetical order, and with
26199 extensions being added before being removed. We achieve this by having
26200 the global ARM_EXTENSIONS table in alphabetical order, and using the
26201 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26202 or removing it (0) and only allowing it to change in the order
26204 const struct arm_option_extension_value_table
* opt
= NULL
;
26205 const arm_feature_set arm_any
= ARM_ANY
;
26206 int adding_value
= -1;
26210 *ext_set_p
= XNEW (arm_feature_set
);
26211 **ext_set_p
= arm_arch_none
;
26214 while (str
!= NULL
&& *str
!= 0)
26221 as_bad (_("invalid architectural extension"));
26226 ext
= strchr (str
, '+');
26231 len
= strlen (str
);
26233 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26235 if (adding_value
!= 0)
26238 opt
= arm_extensions
;
26246 if (adding_value
== -1)
26249 opt
= arm_extensions
;
26251 else if (adding_value
!= 1)
26253 as_bad (_("must specify extensions to add before specifying "
26254 "those to remove"));
26261 as_bad (_("missing architectural extension"));
26265 gas_assert (adding_value
!= -1);
26266 gas_assert (opt
!= NULL
);
26268 /* Scan over the options table trying to find an exact match. */
26269 for (; opt
->name
!= NULL
; opt
++)
26270 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26272 int i
, nb_allowed_archs
=
26273 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26274 /* Check we can apply the extension to this architecture. */
26275 for (i
= 0; i
< nb_allowed_archs
; i
++)
26278 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26280 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26283 if (i
== nb_allowed_archs
)
26285 as_bad (_("extension does not apply to the base architecture"));
26289 /* Add or remove the extension. */
26291 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26294 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26296 /* Allowing Thumb division instructions for ARMv7 in autodetection
26297 rely on this break so that duplicate extensions (extensions
26298 with the same name as a previous extension in the list) are not
26299 considered for command-line parsing. */
26303 if (opt
->name
== NULL
)
26305 /* Did we fail to find an extension because it wasn't specified in
26306 alphabetical order, or because it does not exist? */
26308 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26309 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26312 if (opt
->name
== NULL
)
26313 as_bad (_("unknown architectural extension `%s'"), str
);
26315 as_bad (_("architectural extensions must be specified in "
26316 "alphabetical order"));
26322 /* We should skip the extension we've just matched the next time
26334 arm_parse_cpu (const char *str
)
26336 const struct arm_cpu_option_table
*opt
;
26337 const char *ext
= strchr (str
, '+');
26343 len
= strlen (str
);
26347 as_bad (_("missing cpu name `%s'"), str
);
26351 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26352 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26354 mcpu_cpu_opt
= &opt
->value
;
26355 if (!dyn_mcpu_ext_opt
)
26356 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26357 *dyn_mcpu_ext_opt
= opt
->ext
;
26358 mcpu_fpu_opt
= &opt
->default_fpu
;
26359 if (opt
->canonical_name
)
26361 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26362 strcpy (selected_cpu_name
, opt
->canonical_name
);
26368 if (len
>= sizeof selected_cpu_name
)
26369 len
= (sizeof selected_cpu_name
) - 1;
26371 for (i
= 0; i
< len
; i
++)
26372 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26373 selected_cpu_name
[i
] = 0;
26377 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26382 as_bad (_("unknown cpu `%s'"), str
);
26387 arm_parse_arch (const char *str
)
26389 const struct arm_arch_option_table
*opt
;
26390 const char *ext
= strchr (str
, '+');
26396 len
= strlen (str
);
26400 as_bad (_("missing architecture name `%s'"), str
);
26404 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26405 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26407 march_cpu_opt
= &opt
->value
;
26408 march_fpu_opt
= &opt
->default_fpu
;
26409 strcpy (selected_cpu_name
, opt
->name
);
26412 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26417 as_bad (_("unknown architecture `%s'\n"), str
);
26422 arm_parse_fpu (const char * str
)
26424 const struct arm_option_fpu_value_table
* opt
;
26426 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26427 if (streq (opt
->name
, str
))
26429 mfpu_opt
= &opt
->value
;
26433 as_bad (_("unknown floating point format `%s'\n"), str
);
26438 arm_parse_float_abi (const char * str
)
26440 const struct arm_option_value_table
* opt
;
26442 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26443 if (streq (opt
->name
, str
))
26445 mfloat_abi_opt
= opt
->value
;
26449 as_bad (_("unknown floating point abi `%s'\n"), str
);
26455 arm_parse_eabi (const char * str
)
26457 const struct arm_option_value_table
*opt
;
26459 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26460 if (streq (opt
->name
, str
))
26462 meabi_flags
= opt
->value
;
26465 as_bad (_("unknown EABI `%s'\n"), str
);
26471 arm_parse_it_mode (const char * str
)
26473 bfd_boolean ret
= TRUE
;
26475 if (streq ("arm", str
))
26476 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26477 else if (streq ("thumb", str
))
26478 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26479 else if (streq ("always", str
))
26480 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26481 else if (streq ("never", str
))
26482 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26485 as_bad (_("unknown implicit IT mode `%s', should be "\
26486 "arm, thumb, always, or never."), str
);
26494 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26496 codecomposer_syntax
= TRUE
;
26497 arm_comment_chars
[0] = ';';
26498 arm_line_separator_chars
[0] = 0;
26502 struct arm_long_option_table arm_long_opts
[] =
26504 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26505 arm_parse_cpu
, NULL
},
26506 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26507 arm_parse_arch
, NULL
},
26508 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26509 arm_parse_fpu
, NULL
},
26510 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26511 arm_parse_float_abi
, NULL
},
26513 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26514 arm_parse_eabi
, NULL
},
26516 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26517 arm_parse_it_mode
, NULL
},
26518 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26519 arm_ccs_mode
, NULL
},
26520 {NULL
, NULL
, 0, NULL
}
26524 md_parse_option (int c
, const char * arg
)
26526 struct arm_option_table
*opt
;
26527 const struct arm_legacy_option_table
*fopt
;
26528 struct arm_long_option_table
*lopt
;
26534 target_big_endian
= 1;
26540 target_big_endian
= 0;
26544 case OPTION_FIX_V4BX
:
26549 /* Listing option. Just ignore these, we don't support additional
26554 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26556 if (c
== opt
->option
[0]
26557 && ((arg
== NULL
&& opt
->option
[1] == 0)
26558 || streq (arg
, opt
->option
+ 1)))
26560 /* If the option is deprecated, tell the user. */
26561 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26562 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26563 arg
? arg
: "", _(opt
->deprecated
));
26565 if (opt
->var
!= NULL
)
26566 *opt
->var
= opt
->value
;
26572 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26574 if (c
== fopt
->option
[0]
26575 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26576 || streq (arg
, fopt
->option
+ 1)))
26578 /* If the option is deprecated, tell the user. */
26579 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26580 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26581 arg
? arg
: "", _(fopt
->deprecated
));
26583 if (fopt
->var
!= NULL
)
26584 *fopt
->var
= &fopt
->value
;
26590 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26592 /* These options are expected to have an argument. */
26593 if (c
== lopt
->option
[0]
26595 && strncmp (arg
, lopt
->option
+ 1,
26596 strlen (lopt
->option
+ 1)) == 0)
26598 /* If the option is deprecated, tell the user. */
26599 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26600 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26601 _(lopt
->deprecated
));
26603 /* Call the sup-option parser. */
26604 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26615 md_show_usage (FILE * fp
)
26617 struct arm_option_table
*opt
;
26618 struct arm_long_option_table
*lopt
;
26620 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26622 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26623 if (opt
->help
!= NULL
)
26624 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26626 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26627 if (lopt
->help
!= NULL
)
26628 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26632 -EB assemble code for a big-endian cpu\n"));
26637 -EL assemble code for a little-endian cpu\n"));
26641 --fix-v4bx Allow BX in ARMv4 code\n"));
26649 arm_feature_set flags
;
26650 } cpu_arch_ver_table
;
26652 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26653 chronologically for architectures, with an exception for ARMv6-M and
26654 ARMv6S-M due to legacy reasons. No new architecture should have a
26655 special case. This allows for build attribute selection results to be
26656 stable when new architectures are added. */
26657 static const cpu_arch_ver_table cpu_arch_ver
[] =
26664 {1, ARM_ARCH_V4xM
},
26666 {2, ARM_ARCH_V4TxM
},
26668 {3, ARM_ARCH_V5xM
},
26670 {3, ARM_ARCH_V5TxM
},
26672 {4, ARM_ARCH_V5TExP
},
26673 {4, ARM_ARCH_V5TE
},
26674 {5, ARM_ARCH_V5TEJ
},
26677 {7, ARM_ARCH_V6KZ
},
26679 {8, ARM_ARCH_V6T2
},
26680 {8, ARM_ARCH_V6KT2
},
26681 {8, ARM_ARCH_V6ZT2
},
26682 {8, ARM_ARCH_V6KZT2
},
26684 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26685 always selected build attributes to match those of ARMv6-M
26686 (resp. ARMv6S-M). However, due to these architectures being a strict
26687 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26688 would be selected when fully respecting chronology of architectures.
26689 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26690 move them before ARMv7 architectures. */
26691 {11, ARM_ARCH_V6M
},
26692 {12, ARM_ARCH_V6SM
},
26695 {10, ARM_ARCH_V7A
},
26696 {10, ARM_ARCH_V7R
},
26697 {10, ARM_ARCH_V7M
},
26698 {10, ARM_ARCH_V7VE
},
26699 {13, ARM_ARCH_V7EM
},
26700 {14, ARM_ARCH_V8A
},
26701 {14, ARM_ARCH_V8_1A
},
26702 {14, ARM_ARCH_V8_2A
},
26703 {14, ARM_ARCH_V8_3A
},
26704 {16, ARM_ARCH_V8M_BASE
},
26705 {17, ARM_ARCH_V8M_MAIN
},
26706 {15, ARM_ARCH_V8R
},
26707 {-1, ARM_ARCH_NONE
}
26710 /* Set an attribute if it has not already been set by the user. */
26712 aeabi_set_attribute_int (int tag
, int value
)
26715 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26716 || !attributes_set_explicitly
[tag
])
26717 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26721 aeabi_set_attribute_string (int tag
, const char *value
)
26724 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26725 || !attributes_set_explicitly
[tag
])
26726 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26729 /* Return whether features in the *NEEDED feature set are available via
26730 extensions for the architecture whose feature set is *ARCH_FSET. */
26732 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26733 const arm_feature_set
*needed
)
26735 int i
, nb_allowed_archs
;
26736 arm_feature_set ext_fset
;
26737 const struct arm_option_extension_value_table
*opt
;
26739 ext_fset
= arm_arch_none
;
26740 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26742 /* Extension does not provide any feature we need. */
26743 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26747 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26748 for (i
= 0; i
< nb_allowed_archs
; i
++)
26751 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26754 /* Extension is available, add it. */
26755 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26756 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26760 /* Can we enable all features in *needed? */
26761 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26764 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26765 a given architecture feature set *ARCH_EXT_FSET including extension feature
26766 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26767 - if true, check for an exact match of the architecture modulo extensions;
26768 - otherwise, select build attribute value of the first superset
26769 architecture released so that results remains stable when new architectures
26771 For -march/-mcpu=all the build attribute value of the most featureful
26772 architecture is returned. Tag_CPU_arch_profile result is returned in
26775 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26776 const arm_feature_set
*ext_fset
,
26777 char *profile
, int exact_match
)
26779 arm_feature_set arch_fset
;
26780 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26782 /* Select most featureful architecture with all its extensions if building
26783 for -march=all as the feature sets used to set build attributes. */
26784 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26786 /* Force revisiting of decision for each new architecture. */
26787 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26789 return TAG_CPU_ARCH_V8
;
26792 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
26794 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
26796 arm_feature_set known_arch_fset
;
26798 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
26801 /* Base architecture match user-specified architecture and
26802 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
26803 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
26808 /* Base architecture match user-specified architecture only
26809 (eg. ARMv6-M in the same case as above). Record it in case we
26810 find a match with above condition. */
26811 else if (p_ver_ret
== NULL
26812 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
26818 /* Architecture has all features wanted. */
26819 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
26821 arm_feature_set added_fset
;
26823 /* Compute features added by this architecture over the one
26824 recorded in p_ver_ret. */
26825 if (p_ver_ret
!= NULL
)
26826 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
26828 /* First architecture that match incl. with extensions, or the
26829 only difference in features over the recorded match is
26830 features that were optional and are now mandatory. */
26831 if (p_ver_ret
== NULL
26832 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
26838 else if (p_ver_ret
== NULL
)
26840 arm_feature_set needed_ext_fset
;
26842 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
26844 /* Architecture has all features needed when using some
26845 extensions. Record it and continue searching in case there
26846 exist an architecture providing all needed features without
26847 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
26849 if (have_ext_for_needed_feat_p (&known_arch_fset
,
26856 if (p_ver_ret
== NULL
)
26860 /* Tag_CPU_arch_profile. */
26861 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
26862 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
26863 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
26864 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
26866 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
26868 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
26872 return p_ver_ret
->val
;
26875 /* Set the public EABI object attributes. */
26877 aeabi_set_public_attributes (void)
26882 int fp16_optional
= 0;
26883 int skip_exact_match
= 0;
26884 arm_feature_set flags
, flags_arch
, flags_ext
;
26886 /* Autodetection mode, choose the architecture based the instructions
26888 if (no_cpu_selected ())
26890 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26892 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26893 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26895 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26896 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26898 /* Code run during relaxation relies on selected_cpu being set. */
26899 selected_cpu
= flags
;
26901 /* Otherwise, choose the architecture based on the capabilities of the
26904 flags
= selected_cpu
;
26905 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26907 /* Allow the user to override the reported architecture. */
26910 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
26911 flags_ext
= arm_arch_none
;
26915 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26916 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
26917 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
26920 /* When this function is run again after relaxation has happened there is no
26921 way to determine whether an architecture or CPU was specified by the user:
26922 - selected_cpu is set above for relaxation to work;
26923 - march_cpu_opt is not set if only -mcpu or .cpu is used;
26924 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
26925 Therefore, if not in -march=all case we first try an exact match and fall
26926 back to autodetection. */
26927 if (!skip_exact_match
)
26928 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
26930 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
26932 as_bad (_("no architecture contains all the instructions used\n"));
26934 /* Tag_CPU_name. */
26935 if (selected_cpu_name
[0])
26939 q
= selected_cpu_name
;
26940 if (strncmp (q
, "armv", 4) == 0)
26945 for (i
= 0; q
[i
]; i
++)
26946 q
[i
] = TOUPPER (q
[i
]);
26948 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26951 /* Tag_CPU_arch. */
26952 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26954 /* Tag_CPU_arch_profile. */
26955 if (profile
!= '\0')
26956 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26958 /* Tag_DSP_extension. */
26959 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
26960 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26962 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26963 /* Tag_ARM_ISA_use. */
26964 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26965 || ARM_FEATURE_ZERO (flags_arch
))
26966 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26968 /* Tag_THUMB_ISA_use. */
26969 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26970 || ARM_FEATURE_ZERO (flags_arch
))
26974 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26975 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26977 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26981 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26984 /* Tag_VFP_arch. */
26985 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26986 aeabi_set_attribute_int (Tag_VFP_arch
,
26987 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26989 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26990 aeabi_set_attribute_int (Tag_VFP_arch
,
26991 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26993 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26996 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26998 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27000 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27003 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27004 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27005 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27006 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27007 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27009 /* Tag_ABI_HardFP_use. */
27010 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27011 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27012 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27014 /* Tag_WMMX_arch. */
27015 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27016 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27017 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27018 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27020 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27021 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27022 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27023 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27024 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27025 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27027 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27029 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27033 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27038 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27039 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27040 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27044 We set Tag_DIV_use to two when integer divide instructions have been used
27045 in ARM state, or when Thumb integer divide instructions have been used,
27046 but we have no architecture profile set, nor have we any ARM instructions.
27048 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27049 by the base architecture.
27051 For new architectures we will have to check these tests. */
27052 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27053 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27054 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27055 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27056 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27057 || (profile
== '\0'
27058 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27059 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27060 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27062 /* Tag_MP_extension_use. */
27063 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27064 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27066 /* Tag Virtualization_use. */
27067 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27069 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27072 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27075 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27076 finished and free extension feature bits which will not be used anymore. */
27078 arm_md_post_relax (void)
27080 aeabi_set_public_attributes ();
27081 XDELETE (dyn_mcpu_ext_opt
);
27082 dyn_mcpu_ext_opt
= NULL
;
27083 XDELETE (dyn_march_ext_opt
);
27084 dyn_march_ext_opt
= NULL
;
27087 /* Add the default contents for the .ARM.attributes section. */
27091 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27094 aeabi_set_public_attributes ();
27096 #endif /* OBJ_ELF */
27099 /* Parse a .cpu directive. */
27102 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27104 const struct arm_cpu_option_table
*opt
;
27108 name
= input_line_pointer
;
27109 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27110 input_line_pointer
++;
27111 saved_char
= *input_line_pointer
;
27112 *input_line_pointer
= 0;
27114 /* Skip the first "all" entry. */
27115 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27116 if (streq (opt
->name
, name
))
27118 mcpu_cpu_opt
= &opt
->value
;
27119 if (!dyn_mcpu_ext_opt
)
27120 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27121 *dyn_mcpu_ext_opt
= opt
->ext
;
27122 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27123 if (opt
->canonical_name
)
27124 strcpy (selected_cpu_name
, opt
->canonical_name
);
27128 for (i
= 0; opt
->name
[i
]; i
++)
27129 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27131 selected_cpu_name
[i
] = 0;
27133 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27134 if (dyn_mcpu_ext_opt
)
27135 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27136 *input_line_pointer
= saved_char
;
27137 demand_empty_rest_of_line ();
27140 as_bad (_("unknown cpu `%s'"), name
);
27141 *input_line_pointer
= saved_char
;
27142 ignore_rest_of_line ();
27146 /* Parse a .arch directive. */
27149 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27151 const struct arm_arch_option_table
*opt
;
27155 name
= input_line_pointer
;
27156 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27157 input_line_pointer
++;
27158 saved_char
= *input_line_pointer
;
27159 *input_line_pointer
= 0;
27161 /* Skip the first "all" entry. */
27162 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27163 if (streq (opt
->name
, name
))
27165 mcpu_cpu_opt
= &opt
->value
;
27166 XDELETE (dyn_mcpu_ext_opt
);
27167 dyn_mcpu_ext_opt
= NULL
;
27168 selected_cpu
= *mcpu_cpu_opt
;
27169 strcpy (selected_cpu_name
, opt
->name
);
27170 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27171 *input_line_pointer
= saved_char
;
27172 demand_empty_rest_of_line ();
27176 as_bad (_("unknown architecture `%s'\n"), name
);
27177 *input_line_pointer
= saved_char
;
27178 ignore_rest_of_line ();
27182 /* Parse a .object_arch directive. */
27185 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27187 const struct arm_arch_option_table
*opt
;
27191 name
= input_line_pointer
;
27192 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27193 input_line_pointer
++;
27194 saved_char
= *input_line_pointer
;
27195 *input_line_pointer
= 0;
27197 /* Skip the first "all" entry. */
27198 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27199 if (streq (opt
->name
, name
))
27201 object_arch
= &opt
->value
;
27202 *input_line_pointer
= saved_char
;
27203 demand_empty_rest_of_line ();
27207 as_bad (_("unknown architecture `%s'\n"), name
);
27208 *input_line_pointer
= saved_char
;
27209 ignore_rest_of_line ();
27212 /* Parse a .arch_extension directive. */
27215 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27217 const struct arm_option_extension_value_table
*opt
;
27218 const arm_feature_set arm_any
= ARM_ANY
;
27221 int adding_value
= 1;
27223 name
= input_line_pointer
;
27224 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27225 input_line_pointer
++;
27226 saved_char
= *input_line_pointer
;
27227 *input_line_pointer
= 0;
27229 if (strlen (name
) >= 2
27230 && strncmp (name
, "no", 2) == 0)
27236 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27237 if (streq (opt
->name
, name
))
27239 int i
, nb_allowed_archs
=
27240 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27241 for (i
= 0; i
< nb_allowed_archs
; i
++)
27244 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27246 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27250 if (i
== nb_allowed_archs
)
27252 as_bad (_("architectural extension `%s' is not allowed for the "
27253 "current base architecture"), name
);
27257 if (!dyn_mcpu_ext_opt
)
27259 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27260 *dyn_mcpu_ext_opt
= arm_arch_none
;
27263 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27266 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27269 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27270 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27271 *input_line_pointer
= saved_char
;
27272 demand_empty_rest_of_line ();
27273 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27274 on this return so that duplicate extensions (extensions with the
27275 same name as a previous extension in the list) are not considered
27276 for command-line parsing. */
27280 if (opt
->name
== NULL
)
27281 as_bad (_("unknown architecture extension `%s'\n"), name
);
27283 *input_line_pointer
= saved_char
;
27284 ignore_rest_of_line ();
27287 /* Parse a .fpu directive. */
27290 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27292 const struct arm_option_fpu_value_table
*opt
;
27296 name
= input_line_pointer
;
27297 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27298 input_line_pointer
++;
27299 saved_char
= *input_line_pointer
;
27300 *input_line_pointer
= 0;
27302 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27303 if (streq (opt
->name
, name
))
27305 mfpu_opt
= &opt
->value
;
27306 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27307 if (dyn_mcpu_ext_opt
)
27308 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27309 *input_line_pointer
= saved_char
;
27310 demand_empty_rest_of_line ();
27314 as_bad (_("unknown floating point format `%s'\n"), name
);
27315 *input_line_pointer
= saved_char
;
27316 ignore_rest_of_line ();
27319 /* Copy symbol information. */
27322 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27324 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27328 /* Given a symbolic attribute NAME, return the proper integer value.
27329 Returns -1 if the attribute is not known. */
27332 arm_convert_symbolic_attribute (const char *name
)
27334 static const struct
27339 attribute_table
[] =
27341 /* When you modify this table you should
27342 also modify the list in doc/c-arm.texi. */
27343 #define T(tag) {#tag, tag}
27344 T (Tag_CPU_raw_name
),
27347 T (Tag_CPU_arch_profile
),
27348 T (Tag_ARM_ISA_use
),
27349 T (Tag_THUMB_ISA_use
),
27353 T (Tag_Advanced_SIMD_arch
),
27354 T (Tag_PCS_config
),
27355 T (Tag_ABI_PCS_R9_use
),
27356 T (Tag_ABI_PCS_RW_data
),
27357 T (Tag_ABI_PCS_RO_data
),
27358 T (Tag_ABI_PCS_GOT_use
),
27359 T (Tag_ABI_PCS_wchar_t
),
27360 T (Tag_ABI_FP_rounding
),
27361 T (Tag_ABI_FP_denormal
),
27362 T (Tag_ABI_FP_exceptions
),
27363 T (Tag_ABI_FP_user_exceptions
),
27364 T (Tag_ABI_FP_number_model
),
27365 T (Tag_ABI_align_needed
),
27366 T (Tag_ABI_align8_needed
),
27367 T (Tag_ABI_align_preserved
),
27368 T (Tag_ABI_align8_preserved
),
27369 T (Tag_ABI_enum_size
),
27370 T (Tag_ABI_HardFP_use
),
27371 T (Tag_ABI_VFP_args
),
27372 T (Tag_ABI_WMMX_args
),
27373 T (Tag_ABI_optimization_goals
),
27374 T (Tag_ABI_FP_optimization_goals
),
27375 T (Tag_compatibility
),
27376 T (Tag_CPU_unaligned_access
),
27377 T (Tag_FP_HP_extension
),
27378 T (Tag_VFP_HP_extension
),
27379 T (Tag_ABI_FP_16bit_format
),
27380 T (Tag_MPextension_use
),
27382 T (Tag_nodefaults
),
27383 T (Tag_also_compatible_with
),
27384 T (Tag_conformance
),
27386 T (Tag_Virtualization_use
),
27387 T (Tag_DSP_extension
),
27388 /* We deliberately do not include Tag_MPextension_use_legacy. */
27396 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27397 if (streq (name
, attribute_table
[i
].name
))
27398 return attribute_table
[i
].tag
;
27404 /* Apply sym value for relocations only in the case that they are for
27405 local symbols in the same segment as the fixup and you have the
27406 respective architectural feature for blx and simple switches. */
27408 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27411 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27412 /* PR 17444: If the local symbol is in a different section then a reloc
27413 will always be generated for it, so applying the symbol value now
27414 will result in a double offset being stored in the relocation. */
27415 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27416 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27418 switch (fixP
->fx_r_type
)
27420 case BFD_RELOC_ARM_PCREL_BLX
:
27421 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27422 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27426 case BFD_RELOC_ARM_PCREL_CALL
:
27427 case BFD_RELOC_THUMB_PCREL_BLX
:
27428 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27439 #endif /* OBJ_ELF */