1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
*dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static arm_feature_set
*dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
*march_fpu_opt
= NULL
;
155 static const arm_feature_set
*mfpu_opt
= NULL
;
156 static const arm_feature_set
*object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_v8_3
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
241 static const arm_feature_set arm_arch_any
= ARM_ANY
;
242 static const arm_feature_set fpu_any
= FPU_ANY
;
243 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
244 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
245 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
247 static const arm_feature_set arm_cext_iwmmxt2
=
248 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
249 static const arm_feature_set arm_cext_iwmmxt
=
250 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
251 static const arm_feature_set arm_cext_xscale
=
252 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
253 static const arm_feature_set arm_cext_maverick
=
254 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
255 static const arm_feature_set fpu_fpa_ext_v1
=
256 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
257 static const arm_feature_set fpu_fpa_ext_v2
=
258 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
259 static const arm_feature_set fpu_vfp_ext_v1xd
=
260 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
261 static const arm_feature_set fpu_vfp_ext_v1
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
263 static const arm_feature_set fpu_vfp_ext_v2
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
265 static const arm_feature_set fpu_vfp_ext_v3xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
267 static const arm_feature_set fpu_vfp_ext_v3
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
269 static const arm_feature_set fpu_vfp_ext_d32
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
271 static const arm_feature_set fpu_neon_ext_v1
=
272 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
273 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
276 static const arm_feature_set fpu_vfp_fp16
=
277 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
278 static const arm_feature_set fpu_neon_ext_fma
=
279 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
281 static const arm_feature_set fpu_vfp_ext_fma
=
282 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
283 static const arm_feature_set fpu_vfp_ext_armv8
=
284 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
285 static const arm_feature_set fpu_vfp_ext_armv8xd
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
287 static const arm_feature_set fpu_neon_ext_armv8
=
288 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
289 static const arm_feature_set fpu_crypto_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
291 static const arm_feature_set crc_ext_armv8
=
292 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
293 static const arm_feature_set fpu_neon_ext_v8_1
=
294 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
296 static int mfloat_abi_opt
= -1;
297 /* Record user cpu selection for object attributes. */
298 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
299 /* Must be long enough to hold any of the names in arm_cpus. */
300 static char selected_cpu_name
[20];
302 extern FLONUM_TYPE generic_floating_point_number
;
304 /* Return if no cpu was selected on command-line. */
306 no_cpu_selected (void)
308 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
313 static int meabi_flags
= EABI_DEFAULT
;
315 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
318 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
323 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
328 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
329 symbolS
* GOT_symbol
;
332 /* 0: assemble for ARM,
333 1: assemble for Thumb,
334 2: assemble for Thumb even though target CPU does not support thumb
336 static int thumb_mode
= 0;
337 /* A value distinct from the possible values for thumb_mode that we
338 can use to record whether thumb_mode has been copied into the
339 tc_frag_data field of a frag. */
340 #define MODE_RECORDED (1 << 4)
342 /* Specifies the intrinsic IT insn behavior mode. */
343 enum implicit_it_mode
345 IMPLICIT_IT_MODE_NEVER
= 0x00,
346 IMPLICIT_IT_MODE_ARM
= 0x01,
347 IMPLICIT_IT_MODE_THUMB
= 0x02,
348 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
350 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
352 /* If unified_syntax is true, we are processing the new unified
353 ARM/Thumb syntax. Important differences from the old ARM mode:
355 - Immediate operands do not require a # prefix.
356 - Conditional affixes always appear at the end of the
357 instruction. (For backward compatibility, those instructions
358 that formerly had them in the middle, continue to accept them
360 - The IT instruction may appear, and if it does is validated
361 against subsequent conditional affixes. It does not generate
364 Important differences from the old Thumb mode:
366 - Immediate operands do not require a # prefix.
367 - Most of the V6T2 instructions are only available in unified mode.
368 - The .N and .W suffixes are recognized and honored (it is an error
369 if they cannot be honored).
370 - All instructions set the flags if and only if they have an 's' affix.
371 - Conditional affixes may be used. They are validated against
372 preceding IT instructions. Unlike ARM mode, you cannot use a
373 conditional affix except in the scope of an IT instruction. */
375 static bfd_boolean unified_syntax
= FALSE
;
377 /* An immediate operand can start with #, and ld*, st*, pld operands
378 can contain [ and ]. We need to tell APP not to elide whitespace
379 before a [, which can appear as the first operand for pld.
380 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
381 const char arm_symbol_chars
[] = "#[]{}";
396 enum neon_el_type type
;
400 #define NEON_MAX_TYPE_ELS 4
404 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
408 enum it_instruction_type
413 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
414 if inside, should be the last one. */
415 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
416 i.e. BKPT and NOP. */
417 IT_INSN
/* The IT insn has been parsed. */
420 /* The maximum number of operands we need. */
421 #define ARM_IT_MAX_OPERANDS 6
426 unsigned long instruction
;
430 /* "uncond_value" is set to the value in place of the conditional field in
431 unconditional versions of the instruction, or -1 if nothing is
434 struct neon_type vectype
;
435 /* This does not indicate an actual NEON instruction, only that
436 the mnemonic accepts neon-style type suffixes. */
438 /* Set to the opcode if the instruction needs relaxation.
439 Zero if the instruction is not relaxed. */
443 bfd_reloc_code_real_type type
;
448 enum it_instruction_type it_insn_type
;
454 struct neon_type_el vectype
;
455 unsigned present
: 1; /* Operand present. */
456 unsigned isreg
: 1; /* Operand was a register. */
457 unsigned immisreg
: 1; /* .imm field is a second register. */
458 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
459 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
460 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
461 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
462 instructions. This allows us to disambiguate ARM <-> vector insns. */
463 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
464 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
465 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
466 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
467 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
468 unsigned writeback
: 1; /* Operand has trailing ! */
469 unsigned preind
: 1; /* Preindexed address. */
470 unsigned postind
: 1; /* Postindexed address. */
471 unsigned negative
: 1; /* Index register was negated. */
472 unsigned shifted
: 1; /* Shift applied to operation. */
473 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
474 } operands
[ARM_IT_MAX_OPERANDS
];
477 static struct arm_it inst
;
479 #define NUM_FLOAT_VALS 8
481 const char * fp_const
[] =
483 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
486 /* Number of littlenums required to hold an extended precision number. */
487 #define MAX_LITTLENUMS 6
489 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
499 #define CP_T_X 0x00008000
500 #define CP_T_Y 0x00400000
502 #define CONDS_BIT 0x00100000
503 #define LOAD_BIT 0x00100000
505 #define DOUBLE_LOAD_FLAG 0x00000001
509 const char * template_name
;
513 #define COND_ALWAYS 0xE
517 const char * template_name
;
521 struct asm_barrier_opt
523 const char * template_name
;
525 const arm_feature_set arch
;
528 /* The bit that distinguishes CPSR and SPSR. */
529 #define SPSR_BIT (1 << 22)
531 /* The individual PSR flag bits. */
532 #define PSR_c (1 << 16)
533 #define PSR_x (1 << 17)
534 #define PSR_s (1 << 18)
535 #define PSR_f (1 << 19)
540 bfd_reloc_code_real_type reloc
;
545 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
546 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
551 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
554 /* Bits for DEFINED field in neon_typed_alias. */
555 #define NTA_HASTYPE 1
556 #define NTA_HASINDEX 2
558 struct neon_typed_alias
560 unsigned char defined
;
562 struct neon_type_el eltype
;
565 /* ARM register categories. This includes coprocessor numbers and various
566 architecture extensions' registers. */
593 /* Structure for a hash table entry for a register.
594 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
595 information which states whether a vector type or index is specified (for a
596 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
602 unsigned char builtin
;
603 struct neon_typed_alias
* neon
;
606 /* Diagnostics used when we don't get a register of the expected type. */
607 const char * const reg_expected_msgs
[] =
609 N_("ARM register expected"),
610 N_("bad or missing co-processor number"),
611 N_("co-processor register expected"),
612 N_("FPA register expected"),
613 N_("VFP single precision register expected"),
614 N_("VFP/Neon double precision register expected"),
615 N_("Neon quad precision register expected"),
616 N_("VFP single or double precision register expected"),
617 N_("Neon double or quad precision register expected"),
618 N_("VFP single, double or Neon quad precision register expected"),
619 N_("VFP system register expected"),
620 N_("Maverick MVF register expected"),
621 N_("Maverick MVD register expected"),
622 N_("Maverick MVFX register expected"),
623 N_("Maverick MVDX register expected"),
624 N_("Maverick MVAX register expected"),
625 N_("Maverick DSPSC register expected"),
626 N_("iWMMXt data register expected"),
627 N_("iWMMXt control register expected"),
628 N_("iWMMXt scalar register expected"),
629 N_("XScale accumulator register expected"),
632 /* Some well known registers that we refer to directly elsewhere. */
638 /* ARM instructions take 4bytes in the object file, Thumb instructions
644 /* Basic string to match. */
645 const char * template_name
;
647 /* Parameters to instruction. */
648 unsigned int operands
[8];
650 /* Conditional tag - see opcode_lookup. */
651 unsigned int tag
: 4;
653 /* Basic instruction code. */
654 unsigned int avalue
: 28;
656 /* Thumb-format instruction code. */
659 /* Which architecture variant provides this instruction. */
660 const arm_feature_set
* avariant
;
661 const arm_feature_set
* tvariant
;
663 /* Function to call to encode instruction in ARM format. */
664 void (* aencode
) (void);
666 /* Function to call to encode instruction in Thumb format. */
667 void (* tencode
) (void);
670 /* Defines for various bits that we will want to toggle. */
671 #define INST_IMMEDIATE 0x02000000
672 #define OFFSET_REG 0x02000000
673 #define HWOFFSET_IMM 0x00400000
674 #define SHIFT_BY_REG 0x00000010
675 #define PRE_INDEX 0x01000000
676 #define INDEX_UP 0x00800000
677 #define WRITE_BACK 0x00200000
678 #define LDM_TYPE_2_OR_3 0x00400000
679 #define CPSI_MMOD 0x00020000
681 #define LITERAL_MASK 0xf000f000
682 #define OPCODE_MASK 0xfe1fffff
683 #define V4_STR_BIT 0x00000020
684 #define VLDR_VMOV_SAME 0x0040f000
686 #define T2_SUBS_PC_LR 0xf3de8f00
688 #define DATA_OP_SHIFT 21
689 #define SBIT_SHIFT 20
691 #define T2_OPCODE_MASK 0xfe1fffff
692 #define T2_DATA_OP_SHIFT 21
693 #define T2_SBIT_SHIFT 20
695 #define A_COND_MASK 0xf0000000
696 #define A_PUSH_POP_OP_MASK 0x0fff0000
698 /* Opcodes for pushing/poping registers to/from the stack. */
699 #define A1_OPCODE_PUSH 0x092d0000
700 #define A2_OPCODE_PUSH 0x052d0004
701 #define A2_OPCODE_POP 0x049d0004
703 /* Codes to distinguish the arithmetic instructions. */
714 #define OPCODE_CMP 10
715 #define OPCODE_CMN 11
716 #define OPCODE_ORR 12
717 #define OPCODE_MOV 13
718 #define OPCODE_BIC 14
719 #define OPCODE_MVN 15
721 #define T2_OPCODE_AND 0
722 #define T2_OPCODE_BIC 1
723 #define T2_OPCODE_ORR 2
724 #define T2_OPCODE_ORN 3
725 #define T2_OPCODE_EOR 4
726 #define T2_OPCODE_ADD 8
727 #define T2_OPCODE_ADC 10
728 #define T2_OPCODE_SBC 11
729 #define T2_OPCODE_SUB 13
730 #define T2_OPCODE_RSB 14
732 #define T_OPCODE_MUL 0x4340
733 #define T_OPCODE_TST 0x4200
734 #define T_OPCODE_CMN 0x42c0
735 #define T_OPCODE_NEG 0x4240
736 #define T_OPCODE_MVN 0x43c0
738 #define T_OPCODE_ADD_R3 0x1800
739 #define T_OPCODE_SUB_R3 0x1a00
740 #define T_OPCODE_ADD_HI 0x4400
741 #define T_OPCODE_ADD_ST 0xb000
742 #define T_OPCODE_SUB_ST 0xb080
743 #define T_OPCODE_ADD_SP 0xa800
744 #define T_OPCODE_ADD_PC 0xa000
745 #define T_OPCODE_ADD_I8 0x3000
746 #define T_OPCODE_SUB_I8 0x3800
747 #define T_OPCODE_ADD_I3 0x1c00
748 #define T_OPCODE_SUB_I3 0x1e00
750 #define T_OPCODE_ASR_R 0x4100
751 #define T_OPCODE_LSL_R 0x4080
752 #define T_OPCODE_LSR_R 0x40c0
753 #define T_OPCODE_ROR_R 0x41c0
754 #define T_OPCODE_ASR_I 0x1000
755 #define T_OPCODE_LSL_I 0x0000
756 #define T_OPCODE_LSR_I 0x0800
758 #define T_OPCODE_MOV_I8 0x2000
759 #define T_OPCODE_CMP_I8 0x2800
760 #define T_OPCODE_CMP_LR 0x4280
761 #define T_OPCODE_MOV_HR 0x4600
762 #define T_OPCODE_CMP_HR 0x4500
764 #define T_OPCODE_LDR_PC 0x4800
765 #define T_OPCODE_LDR_SP 0x9800
766 #define T_OPCODE_STR_SP 0x9000
767 #define T_OPCODE_LDR_IW 0x6800
768 #define T_OPCODE_STR_IW 0x6000
769 #define T_OPCODE_LDR_IH 0x8800
770 #define T_OPCODE_STR_IH 0x8000
771 #define T_OPCODE_LDR_IB 0x7800
772 #define T_OPCODE_STR_IB 0x7000
773 #define T_OPCODE_LDR_RW 0x5800
774 #define T_OPCODE_STR_RW 0x5000
775 #define T_OPCODE_LDR_RH 0x5a00
776 #define T_OPCODE_STR_RH 0x5200
777 #define T_OPCODE_LDR_RB 0x5c00
778 #define T_OPCODE_STR_RB 0x5400
780 #define T_OPCODE_PUSH 0xb400
781 #define T_OPCODE_POP 0xbc00
783 #define T_OPCODE_BRANCH 0xe000
785 #define THUMB_SIZE 2 /* Size of thumb instruction. */
786 #define THUMB_PP_PC_LR 0x0100
787 #define THUMB_LOAD_BIT 0x0800
788 #define THUMB2_LOAD_BIT 0x00100000
790 #define BAD_ARGS _("bad arguments to instruction")
791 #define BAD_SP _("r13 not allowed here")
792 #define BAD_PC _("r15 not allowed here")
793 #define BAD_COND _("instruction cannot be conditional")
794 #define BAD_OVERLAP _("registers may not be the same")
795 #define BAD_HIREG _("lo register required")
796 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
797 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
798 #define BAD_BRANCH _("branch must be last instruction in IT block")
799 #define BAD_NOT_IT _("instruction not allowed in IT block")
800 #define BAD_FPU _("selected FPU does not support instruction")
801 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
802 #define BAD_IT_COND _("incorrect condition in IT block")
803 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
804 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
805 #define BAD_PC_ADDRESSING \
806 _("cannot use register index with PC-relative addressing")
807 #define BAD_PC_WRITEBACK \
808 _("cannot use writeback with PC-relative addressing")
809 #define BAD_RANGE _("branch out of range")
810 #define BAD_FP16 _("selected processor does not support fp16 instruction")
811 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
812 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
814 static struct hash_control
* arm_ops_hsh
;
815 static struct hash_control
* arm_cond_hsh
;
816 static struct hash_control
* arm_shift_hsh
;
817 static struct hash_control
* arm_psr_hsh
;
818 static struct hash_control
* arm_v7m_psr_hsh
;
819 static struct hash_control
* arm_reg_hsh
;
820 static struct hash_control
* arm_reloc_hsh
;
821 static struct hash_control
* arm_barrier_opt_hsh
;
823 /* Stuff needed to resolve the label ambiguity
832 symbolS
* last_label_seen
;
833 static int label_is_thumb_function_name
= FALSE
;
835 /* Literal pool structure. Held on a per-section
836 and per-sub-section basis. */
838 #define MAX_LITERAL_POOL_SIZE 1024
839 typedef struct literal_pool
841 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
842 unsigned int next_free_entry
;
848 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
850 struct literal_pool
* next
;
851 unsigned int alignment
;
854 /* Pointer to a linked list of literal pools. */
855 literal_pool
* list_of_pools
= NULL
;
857 typedef enum asmfunc_states
860 WAITING_ASMFUNC_NAME
,
864 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
867 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
869 static struct current_it now_it
;
873 now_it_compatible (int cond
)
875 return (cond
& ~1) == (now_it
.cc
& ~1);
879 conditional_insn (void)
881 return inst
.cond
!= COND_ALWAYS
;
884 static int in_it_block (void);
886 static int handle_it_state (void);
888 static void force_automatic_it_block_close (void);
890 static void it_fsm_post_encode (void);
892 #define set_it_insn_type(type) \
895 inst.it_insn_type = type; \
896 if (handle_it_state () == FAIL) \
901 #define set_it_insn_type_nonvoid(type, failret) \
904 inst.it_insn_type = type; \
905 if (handle_it_state () == FAIL) \
910 #define set_it_insn_type_last() \
913 if (inst.cond == COND_ALWAYS) \
914 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
916 set_it_insn_type (INSIDE_IT_LAST_INSN); \
922 /* This array holds the chars that always start a comment. If the
923 pre-processor is disabled, these aren't very useful. */
924 char arm_comment_chars
[] = "@";
926 /* This array holds the chars that only start a comment at the beginning of
927 a line. If the line seems to have the form '# 123 filename'
928 .line and .file directives will appear in the pre-processed output. */
929 /* Note that input_file.c hand checks for '#' at the beginning of the
930 first line of the input file. This is because the compiler outputs
931 #NO_APP at the beginning of its output. */
932 /* Also note that comments like this one will always work. */
933 const char line_comment_chars
[] = "#";
935 char arm_line_separator_chars
[] = ";";
937 /* Chars that can be used to separate mant
938 from exp in floating point numbers. */
939 const char EXP_CHARS
[] = "eE";
941 /* Chars that mean this number is a floating point constant. */
945 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
947 /* Prefix characters that indicate the start of an immediate
949 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
951 /* Separator character handling. */
953 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
956 skip_past_char (char ** str
, char c
)
958 /* PR gas/14987: Allow for whitespace before the expected character. */
959 skip_whitespace (*str
);
970 #define skip_past_comma(str) skip_past_char (str, ',')
972 /* Arithmetic expressions (possibly involving symbols). */
974 /* Return TRUE if anything in the expression is a bignum. */
977 walk_no_bignums (symbolS
* sp
)
979 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
982 if (symbol_get_value_expression (sp
)->X_add_symbol
)
984 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
985 || (symbol_get_value_expression (sp
)->X_op_symbol
986 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
992 static int in_my_get_expression
= 0;
994 /* Third argument to my_get_expression. */
995 #define GE_NO_PREFIX 0
996 #define GE_IMM_PREFIX 1
997 #define GE_OPT_PREFIX 2
998 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
999 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1000 #define GE_OPT_PREFIX_BIG 3
1003 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1008 /* In unified syntax, all prefixes are optional. */
1010 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1013 switch (prefix_mode
)
1015 case GE_NO_PREFIX
: break;
1017 if (!is_immediate_prefix (**str
))
1019 inst
.error
= _("immediate expression requires a # prefix");
1025 case GE_OPT_PREFIX_BIG
:
1026 if (is_immediate_prefix (**str
))
1032 memset (ep
, 0, sizeof (expressionS
));
1034 save_in
= input_line_pointer
;
1035 input_line_pointer
= *str
;
1036 in_my_get_expression
= 1;
1037 seg
= expression (ep
);
1038 in_my_get_expression
= 0;
1040 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1042 /* We found a bad or missing expression in md_operand(). */
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1045 if (inst
.error
== NULL
)
1046 inst
.error
= (ep
->X_op
== O_absent
1047 ? _("missing expression") :_("bad expression"));
1052 if (seg
!= absolute_section
1053 && seg
!= text_section
1054 && seg
!= data_section
1055 && seg
!= bss_section
1056 && seg
!= undefined_section
)
1058 inst
.error
= _("bad segment");
1059 *str
= input_line_pointer
;
1060 input_line_pointer
= save_in
;
1067 /* Get rid of any bignums now, so that we don't generate an error for which
1068 we can't establish a line number later on. Big numbers are never valid
1069 in instructions, which is where this routine is always called. */
1070 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1071 && (ep
->X_op
== O_big
1072 || (ep
->X_add_symbol
1073 && (walk_no_bignums (ep
->X_add_symbol
)
1075 && walk_no_bignums (ep
->X_op_symbol
))))))
1077 inst
.error
= _("invalid constant");
1078 *str
= input_line_pointer
;
1079 input_line_pointer
= save_in
;
1083 *str
= input_line_pointer
;
1084 input_line_pointer
= save_in
;
1088 /* Turn a string in input_line_pointer into a floating point constant
1089 of type TYPE, and store the appropriate bytes in *LITP. The number
1090 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1091 returned, or NULL on OK.
1093 Note that fp constants aren't represent in the normal way on the ARM.
1094 In big endian mode, things are as expected. However, in little endian
1095 mode fp constants are big-endian word-wise, and little-endian byte-wise
1096 within the words. For example, (double) 1.1 in big endian mode is
1097 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1098 the byte sequence 99 99 f1 3f 9a 99 99 99.
1100 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1103 md_atof (int type
, char * litP
, int * sizeP
)
1106 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1138 return _("Unrecognized or unsupported floating point constant");
1141 t
= atof_ieee (input_line_pointer
, type
, words
);
1143 input_line_pointer
= t
;
1144 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1146 if (target_big_endian
)
1148 for (i
= 0; i
< prec
; i
++)
1150 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1151 litP
+= sizeof (LITTLENUM_TYPE
);
1156 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1157 for (i
= prec
- 1; i
>= 0; i
--)
1159 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1160 litP
+= sizeof (LITTLENUM_TYPE
);
1163 /* For a 4 byte float the order of elements in `words' is 1 0.
1164 For an 8 byte float the order is 1 0 3 2. */
1165 for (i
= 0; i
< prec
; i
+= 2)
1167 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1168 sizeof (LITTLENUM_TYPE
));
1169 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1170 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1171 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1178 /* We handle all bad expressions here, so that we can report the faulty
1179 instruction in the error message. */
1181 md_operand (expressionS
* exp
)
1183 if (in_my_get_expression
)
1184 exp
->X_op
= O_illegal
;
1187 /* Immediate values. */
1189 /* Generic immediate-value read function for use in directives.
1190 Accepts anything that 'expression' can fold to a constant.
1191 *val receives the number. */
1194 immediate_for_directive (int *val
)
1197 exp
.X_op
= O_illegal
;
1199 if (is_immediate_prefix (*input_line_pointer
))
1201 input_line_pointer
++;
1205 if (exp
.X_op
!= O_constant
)
1207 as_bad (_("expected #constant"));
1208 ignore_rest_of_line ();
1211 *val
= exp
.X_add_number
;
1216 /* Register parsing. */
1218 /* Generic register parser. CCP points to what should be the
1219 beginning of a register name. If it is indeed a valid register
1220 name, advance CCP over it and return the reg_entry structure;
1221 otherwise return NULL. Does not issue diagnostics. */
1223 static struct reg_entry
*
1224 arm_reg_parse_multi (char **ccp
)
1228 struct reg_entry
*reg
;
1230 skip_whitespace (start
);
1232 #ifdef REGISTER_PREFIX
1233 if (*start
!= REGISTER_PREFIX
)
1237 #ifdef OPTIONAL_REGISTER_PREFIX
1238 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1243 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1248 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1250 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1260 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1261 enum arm_reg_type type
)
1263 /* Alternative syntaxes are accepted for a few register classes. */
1270 /* Generic coprocessor register names are allowed for these. */
1271 if (reg
&& reg
->type
== REG_TYPE_CN
)
1276 /* For backward compatibility, a bare number is valid here. */
1278 unsigned long processor
= strtoul (start
, ccp
, 10);
1279 if (*ccp
!= start
&& processor
<= 15)
1284 case REG_TYPE_MMXWC
:
1285 /* WC includes WCG. ??? I'm not sure this is true for all
1286 instructions that take WC registers. */
1287 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1298 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1299 return value is the register number or FAIL. */
1302 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1305 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1308 /* Do not allow a scalar (reg+index) to parse as a register. */
1309 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1312 if (reg
&& reg
->type
== type
)
1315 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1322 /* Parse a Neon type specifier. *STR should point at the leading '.'
1323 character. Does no verification at this stage that the type fits the opcode
1330 Can all be legally parsed by this function.
1332 Fills in neon_type struct pointer with parsed information, and updates STR
1333 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1334 type, FAIL if not. */
1337 parse_neon_type (struct neon_type
*type
, char **str
)
1344 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1346 enum neon_el_type thistype
= NT_untyped
;
1347 unsigned thissize
= -1u;
1354 /* Just a size without an explicit type. */
1358 switch (TOLOWER (*ptr
))
1360 case 'i': thistype
= NT_integer
; break;
1361 case 'f': thistype
= NT_float
; break;
1362 case 'p': thistype
= NT_poly
; break;
1363 case 's': thistype
= NT_signed
; break;
1364 case 'u': thistype
= NT_unsigned
; break;
1366 thistype
= NT_float
;
1371 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1377 /* .f is an abbreviation for .f32. */
1378 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1383 thissize
= strtoul (ptr
, &ptr
, 10);
1385 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1388 as_bad (_("bad size %d in type specifier"), thissize
);
1396 type
->el
[type
->elems
].type
= thistype
;
1397 type
->el
[type
->elems
].size
= thissize
;
1402 /* Empty/missing type is not a successful parse. */
1403 if (type
->elems
== 0)
1411 /* Errors may be set multiple times during parsing or bit encoding
1412 (particularly in the Neon bits), but usually the earliest error which is set
1413 will be the most meaningful. Avoid overwriting it with later (cascading)
1414 errors by calling this function. */
1417 first_error (const char *err
)
1423 /* Parse a single type, e.g. ".s32", leading period included. */
1425 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1428 struct neon_type optype
;
1432 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1434 if (optype
.elems
== 1)
1435 *vectype
= optype
.el
[0];
1438 first_error (_("only one type should be specified for operand"));
1444 first_error (_("vector type expected"));
1456 /* Special meanings for indices (which have a range of 0-7), which will fit into
1459 #define NEON_ALL_LANES 15
1460 #define NEON_INTERLEAVE_LANES 14
1462 /* Parse either a register or a scalar, with an optional type. Return the
1463 register number, and optionally fill in the actual type of the register
1464 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1465 type/index information in *TYPEINFO. */
1468 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1469 enum arm_reg_type
*rtype
,
1470 struct neon_typed_alias
*typeinfo
)
1473 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1474 struct neon_typed_alias atype
;
1475 struct neon_type_el parsetype
;
1479 atype
.eltype
.type
= NT_invtype
;
1480 atype
.eltype
.size
= -1;
1482 /* Try alternate syntax for some types of register. Note these are mutually
1483 exclusive with the Neon syntax extensions. */
1486 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1494 /* Undo polymorphism when a set of register types may be accepted. */
1495 if ((type
== REG_TYPE_NDQ
1496 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1497 || (type
== REG_TYPE_VFSD
1498 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1499 || (type
== REG_TYPE_NSDQ
1500 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1501 || reg
->type
== REG_TYPE_NQ
))
1502 || (type
== REG_TYPE_MMXWC
1503 && (reg
->type
== REG_TYPE_MMXWCG
)))
1504 type
= (enum arm_reg_type
) reg
->type
;
1506 if (type
!= reg
->type
)
1512 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1514 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1516 first_error (_("can't redefine type for operand"));
1519 atype
.defined
|= NTA_HASTYPE
;
1520 atype
.eltype
= parsetype
;
1523 if (skip_past_char (&str
, '[') == SUCCESS
)
1525 if (type
!= REG_TYPE_VFD
)
1527 first_error (_("only D registers may be indexed"));
1531 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1533 first_error (_("can't change index for operand"));
1537 atype
.defined
|= NTA_HASINDEX
;
1539 if (skip_past_char (&str
, ']') == SUCCESS
)
1540 atype
.index
= NEON_ALL_LANES
;
1545 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1547 if (exp
.X_op
!= O_constant
)
1549 first_error (_("constant expression required"));
1553 if (skip_past_char (&str
, ']') == FAIL
)
1556 atype
.index
= exp
.X_add_number
;
1571 /* Like arm_reg_parse, but allow allow the following extra features:
1572 - If RTYPE is non-zero, return the (possibly restricted) type of the
1573 register (e.g. Neon double or quad reg when either has been requested).
1574 - If this is a Neon vector type with additional type information, fill
1575 in the struct pointed to by VECTYPE (if non-NULL).
1576 This function will fault on encountering a scalar. */
1579 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1580 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1582 struct neon_typed_alias atype
;
1584 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1589 /* Do not allow regname(... to parse as a register. */
1593 /* Do not allow a scalar (reg+index) to parse as a register. */
1594 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1596 first_error (_("register operand expected, but got scalar"));
1601 *vectype
= atype
.eltype
;
1608 #define NEON_SCALAR_REG(X) ((X) >> 4)
1609 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1611 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1612 have enough information to be able to do a good job bounds-checking. So, we
1613 just do easy checks here, and do further checks later. */
1616 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1620 struct neon_typed_alias atype
;
1622 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1624 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1627 if (atype
.index
== NEON_ALL_LANES
)
1629 first_error (_("scalar must have an index"));
1632 else if (atype
.index
>= 64 / elsize
)
1634 first_error (_("scalar index out of range"));
1639 *type
= atype
.eltype
;
1643 return reg
* 16 + atype
.index
;
1646 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1649 parse_reg_list (char ** strp
)
1651 char * str
= * strp
;
1655 /* We come back here if we get ranges concatenated by '+' or '|'. */
1658 skip_whitespace (str
);
1672 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1674 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1684 first_error (_("bad range in register list"));
1688 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1690 if (range
& (1 << i
))
1692 (_("Warning: duplicated register (r%d) in register list"),
1700 if (range
& (1 << reg
))
1701 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1703 else if (reg
<= cur_reg
)
1704 as_tsktsk (_("Warning: register range not in ascending order"));
1709 while (skip_past_comma (&str
) != FAIL
1710 || (in_range
= 1, *str
++ == '-'));
1713 if (skip_past_char (&str
, '}') == FAIL
)
1715 first_error (_("missing `}'"));
1723 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1726 if (exp
.X_op
== O_constant
)
1728 if (exp
.X_add_number
1729 != (exp
.X_add_number
& 0x0000ffff))
1731 inst
.error
= _("invalid register mask");
1735 if ((range
& exp
.X_add_number
) != 0)
1737 int regno
= range
& exp
.X_add_number
;
1740 regno
= (1 << regno
) - 1;
1742 (_("Warning: duplicated register (r%d) in register list"),
1746 range
|= exp
.X_add_number
;
1750 if (inst
.reloc
.type
!= 0)
1752 inst
.error
= _("expression too complex");
1756 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1757 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1758 inst
.reloc
.pc_rel
= 0;
1762 if (*str
== '|' || *str
== '+')
1768 while (another_range
);
1774 /* Types of registers in a list. */
1783 /* Parse a VFP register list. If the string is invalid return FAIL.
1784 Otherwise return the number of registers, and set PBASE to the first
1785 register. Parses registers of type ETYPE.
1786 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1787 - Q registers can be used to specify pairs of D registers
1788 - { } can be omitted from around a singleton register list
1789 FIXME: This is not implemented, as it would require backtracking in
1792 This could be done (the meaning isn't really ambiguous), but doesn't
1793 fit in well with the current parsing framework.
1794 - 32 D registers may be used (also true for VFPv3).
1795 FIXME: Types are ignored in these register lists, which is probably a
1799 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1804 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1808 unsigned long mask
= 0;
1811 if (skip_past_char (&str
, '{') == FAIL
)
1813 inst
.error
= _("expecting {");
1820 regtype
= REG_TYPE_VFS
;
1825 regtype
= REG_TYPE_VFD
;
1828 case REGLIST_NEON_D
:
1829 regtype
= REG_TYPE_NDQ
;
1833 if (etype
!= REGLIST_VFP_S
)
1835 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1836 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1840 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1843 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1850 base_reg
= max_regs
;
1854 int setmask
= 1, addregs
= 1;
1856 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1858 if (new_base
== FAIL
)
1860 first_error (_(reg_expected_msgs
[regtype
]));
1864 if (new_base
>= max_regs
)
1866 first_error (_("register out of range in list"));
1870 /* Note: a value of 2 * n is returned for the register Q<n>. */
1871 if (regtype
== REG_TYPE_NQ
)
1877 if (new_base
< base_reg
)
1878 base_reg
= new_base
;
1880 if (mask
& (setmask
<< new_base
))
1882 first_error (_("invalid register list"));
1886 if ((mask
>> new_base
) != 0 && ! warned
)
1888 as_tsktsk (_("register list not in ascending order"));
1892 mask
|= setmask
<< new_base
;
1895 if (*str
== '-') /* We have the start of a range expression */
1901 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1904 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1908 if (high_range
>= max_regs
)
1910 first_error (_("register out of range in list"));
1914 if (regtype
== REG_TYPE_NQ
)
1915 high_range
= high_range
+ 1;
1917 if (high_range
<= new_base
)
1919 inst
.error
= _("register range not in ascending order");
1923 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1925 if (mask
& (setmask
<< new_base
))
1927 inst
.error
= _("invalid register list");
1931 mask
|= setmask
<< new_base
;
1936 while (skip_past_comma (&str
) != FAIL
);
1940 /* Sanity check -- should have raised a parse error above. */
1941 if (count
== 0 || count
> max_regs
)
1946 /* Final test -- the registers must be consecutive. */
1948 for (i
= 0; i
< count
; i
++)
1950 if ((mask
& (1u << i
)) == 0)
1952 inst
.error
= _("non-contiguous register range");
1962 /* True if two alias types are the same. */
1965 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1973 if (a
->defined
!= b
->defined
)
1976 if ((a
->defined
& NTA_HASTYPE
) != 0
1977 && (a
->eltype
.type
!= b
->eltype
.type
1978 || a
->eltype
.size
!= b
->eltype
.size
))
1981 if ((a
->defined
& NTA_HASINDEX
) != 0
1982 && (a
->index
!= b
->index
))
1988 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1989 The base register is put in *PBASE.
1990 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1992 The register stride (minus one) is put in bit 4 of the return value.
1993 Bits [6:5] encode the list length (minus one).
1994 The type of the list elements is put in *ELTYPE, if non-NULL. */
1996 #define NEON_LANE(X) ((X) & 0xf)
1997 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1998 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2001 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2002 struct neon_type_el
*eltype
)
2009 int leading_brace
= 0;
2010 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2011 const char *const incr_error
= _("register stride must be 1 or 2");
2012 const char *const type_error
= _("mismatched element/structure types in list");
2013 struct neon_typed_alias firsttype
;
2014 firsttype
.defined
= 0;
2015 firsttype
.eltype
.type
= NT_invtype
;
2016 firsttype
.eltype
.size
= -1;
2017 firsttype
.index
= -1;
2019 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2024 struct neon_typed_alias atype
;
2025 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2029 first_error (_(reg_expected_msgs
[rtype
]));
2036 if (rtype
== REG_TYPE_NQ
)
2042 else if (reg_incr
== -1)
2044 reg_incr
= getreg
- base_reg
;
2045 if (reg_incr
< 1 || reg_incr
> 2)
2047 first_error (_(incr_error
));
2051 else if (getreg
!= base_reg
+ reg_incr
* count
)
2053 first_error (_(incr_error
));
2057 if (! neon_alias_types_same (&atype
, &firsttype
))
2059 first_error (_(type_error
));
2063 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2067 struct neon_typed_alias htype
;
2068 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2070 lane
= NEON_INTERLEAVE_LANES
;
2071 else if (lane
!= NEON_INTERLEAVE_LANES
)
2073 first_error (_(type_error
));
2078 else if (reg_incr
!= 1)
2080 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2084 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2087 first_error (_(reg_expected_msgs
[rtype
]));
2090 if (! neon_alias_types_same (&htype
, &firsttype
))
2092 first_error (_(type_error
));
2095 count
+= hireg
+ dregs
- getreg
;
2099 /* If we're using Q registers, we can't use [] or [n] syntax. */
2100 if (rtype
== REG_TYPE_NQ
)
2106 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2110 else if (lane
!= atype
.index
)
2112 first_error (_(type_error
));
2116 else if (lane
== -1)
2117 lane
= NEON_INTERLEAVE_LANES
;
2118 else if (lane
!= NEON_INTERLEAVE_LANES
)
2120 first_error (_(type_error
));
2125 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2127 /* No lane set by [x]. We must be interleaving structures. */
2129 lane
= NEON_INTERLEAVE_LANES
;
2132 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2133 || (count
> 1 && reg_incr
== -1))
2135 first_error (_("error parsing element/structure list"));
2139 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2141 first_error (_("expected }"));
2149 *eltype
= firsttype
.eltype
;
2154 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2157 /* Parse an explicit relocation suffix on an expression. This is
2158 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2159 arm_reloc_hsh contains no entries, so this function can only
2160 succeed if there is no () after the word. Returns -1 on error,
2161 BFD_RELOC_UNUSED if there wasn't any suffix. */
2164 parse_reloc (char **str
)
2166 struct reloc_entry
*r
;
2170 return BFD_RELOC_UNUSED
;
2175 while (*q
&& *q
!= ')' && *q
!= ',')
2180 if ((r
= (struct reloc_entry
*)
2181 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2188 /* Directives: register aliases. */
2190 static struct reg_entry
*
2191 insert_reg_alias (char *str
, unsigned number
, int type
)
2193 struct reg_entry
*new_reg
;
2196 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2198 if (new_reg
->builtin
)
2199 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2201 /* Only warn about a redefinition if it's not defined as the
2203 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2204 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2209 name
= xstrdup (str
);
2210 new_reg
= XNEW (struct reg_entry
);
2212 new_reg
->name
= name
;
2213 new_reg
->number
= number
;
2214 new_reg
->type
= type
;
2215 new_reg
->builtin
= FALSE
;
2216 new_reg
->neon
= NULL
;
2218 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2225 insert_neon_reg_alias (char *str
, int number
, int type
,
2226 struct neon_typed_alias
*atype
)
2228 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2232 first_error (_("attempt to redefine typed alias"));
2238 reg
->neon
= XNEW (struct neon_typed_alias
);
2239 *reg
->neon
= *atype
;
2243 /* Look for the .req directive. This is of the form:
2245 new_register_name .req existing_register_name
2247 If we find one, or if it looks sufficiently like one that we want to
2248 handle any error here, return TRUE. Otherwise return FALSE. */
2251 create_register_alias (char * newname
, char *p
)
2253 struct reg_entry
*old
;
2254 char *oldname
, *nbuf
;
2257 /* The input scrubber ensures that whitespace after the mnemonic is
2258 collapsed to single spaces. */
2260 if (strncmp (oldname
, " .req ", 6) != 0)
2264 if (*oldname
== '\0')
2267 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2270 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2274 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2275 the desired alias name, and p points to its end. If not, then
2276 the desired alias name is in the global original_case_string. */
2277 #ifdef TC_CASE_SENSITIVE
2280 newname
= original_case_string
;
2281 nlen
= strlen (newname
);
2284 nbuf
= xmemdup0 (newname
, nlen
);
2286 /* Create aliases under the new name as stated; an all-lowercase
2287 version of the new name; and an all-uppercase version of the new
2289 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2291 for (p
= nbuf
; *p
; p
++)
2294 if (strncmp (nbuf
, newname
, nlen
))
2296 /* If this attempt to create an additional alias fails, do not bother
2297 trying to create the all-lower case alias. We will fail and issue
2298 a second, duplicate error message. This situation arises when the
2299 programmer does something like:
2302 The second .req creates the "Foo" alias but then fails to create
2303 the artificial FOO alias because it has already been created by the
2305 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2312 for (p
= nbuf
; *p
; p
++)
2315 if (strncmp (nbuf
, newname
, nlen
))
2316 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2323 /* Create a Neon typed/indexed register alias using directives, e.g.:
2328 These typed registers can be used instead of the types specified after the
2329 Neon mnemonic, so long as all operands given have types. Types can also be
2330 specified directly, e.g.:
2331 vadd d0.s32, d1.s32, d2.s32 */
2334 create_neon_reg_alias (char *newname
, char *p
)
2336 enum arm_reg_type basetype
;
2337 struct reg_entry
*basereg
;
2338 struct reg_entry mybasereg
;
2339 struct neon_type ntype
;
2340 struct neon_typed_alias typeinfo
;
2341 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2344 typeinfo
.defined
= 0;
2345 typeinfo
.eltype
.type
= NT_invtype
;
2346 typeinfo
.eltype
.size
= -1;
2347 typeinfo
.index
= -1;
2351 if (strncmp (p
, " .dn ", 5) == 0)
2352 basetype
= REG_TYPE_VFD
;
2353 else if (strncmp (p
, " .qn ", 5) == 0)
2354 basetype
= REG_TYPE_NQ
;
2363 basereg
= arm_reg_parse_multi (&p
);
2365 if (basereg
&& basereg
->type
!= basetype
)
2367 as_bad (_("bad type for register"));
2371 if (basereg
== NULL
)
2374 /* Try parsing as an integer. */
2375 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2376 if (exp
.X_op
!= O_constant
)
2378 as_bad (_("expression must be constant"));
2381 basereg
= &mybasereg
;
2382 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2388 typeinfo
= *basereg
->neon
;
2390 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2392 /* We got a type. */
2393 if (typeinfo
.defined
& NTA_HASTYPE
)
2395 as_bad (_("can't redefine the type of a register alias"));
2399 typeinfo
.defined
|= NTA_HASTYPE
;
2400 if (ntype
.elems
!= 1)
2402 as_bad (_("you must specify a single type only"));
2405 typeinfo
.eltype
= ntype
.el
[0];
2408 if (skip_past_char (&p
, '[') == SUCCESS
)
2411 /* We got a scalar index. */
2413 if (typeinfo
.defined
& NTA_HASINDEX
)
2415 as_bad (_("can't redefine the index of a scalar alias"));
2419 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2421 if (exp
.X_op
!= O_constant
)
2423 as_bad (_("scalar index must be constant"));
2427 typeinfo
.defined
|= NTA_HASINDEX
;
2428 typeinfo
.index
= exp
.X_add_number
;
2430 if (skip_past_char (&p
, ']') == FAIL
)
2432 as_bad (_("expecting ]"));
2437 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2438 the desired alias name, and p points to its end. If not, then
2439 the desired alias name is in the global original_case_string. */
2440 #ifdef TC_CASE_SENSITIVE
2441 namelen
= nameend
- newname
;
2443 newname
= original_case_string
;
2444 namelen
= strlen (newname
);
2447 namebuf
= xmemdup0 (newname
, namelen
);
2449 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2450 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2452 /* Insert name in all uppercase. */
2453 for (p
= namebuf
; *p
; p
++)
2456 if (strncmp (namebuf
, newname
, namelen
))
2457 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2458 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2460 /* Insert name in all lowercase. */
2461 for (p
= namebuf
; *p
; p
++)
2464 if (strncmp (namebuf
, newname
, namelen
))
2465 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2466 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2472 /* Should never be called, as .req goes between the alias and the
2473 register name, not at the beginning of the line. */
2476 s_req (int a ATTRIBUTE_UNUSED
)
2478 as_bad (_("invalid syntax for .req directive"));
2482 s_dn (int a ATTRIBUTE_UNUSED
)
2484 as_bad (_("invalid syntax for .dn directive"));
2488 s_qn (int a ATTRIBUTE_UNUSED
)
2490 as_bad (_("invalid syntax for .qn directive"));
2493 /* The .unreq directive deletes an alias which was previously defined
2494 by .req. For example:
2500 s_unreq (int a ATTRIBUTE_UNUSED
)
2505 name
= input_line_pointer
;
2507 while (*input_line_pointer
!= 0
2508 && *input_line_pointer
!= ' '
2509 && *input_line_pointer
!= '\n')
2510 ++input_line_pointer
;
2512 saved_char
= *input_line_pointer
;
2513 *input_line_pointer
= 0;
2516 as_bad (_("invalid syntax for .unreq directive"));
2519 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2523 as_bad (_("unknown register alias '%s'"), name
);
2524 else if (reg
->builtin
)
2525 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2532 hash_delete (arm_reg_hsh
, name
, FALSE
);
2533 free ((char *) reg
->name
);
2538 /* Also locate the all upper case and all lower case versions.
2539 Do not complain if we cannot find one or the other as it
2540 was probably deleted above. */
2542 nbuf
= strdup (name
);
2543 for (p
= nbuf
; *p
; p
++)
2545 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2548 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2549 free ((char *) reg
->name
);
2555 for (p
= nbuf
; *p
; p
++)
2557 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2560 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2561 free ((char *) reg
->name
);
2571 *input_line_pointer
= saved_char
;
2572 demand_empty_rest_of_line ();
2575 /* Directives: Instruction set selection. */
2578 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2579 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2580 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2581 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2583 /* Create a new mapping symbol for the transition to STATE. */
2586 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2589 const char * symname
;
2596 type
= BSF_NO_FLAGS
;
2600 type
= BSF_NO_FLAGS
;
2604 type
= BSF_NO_FLAGS
;
2610 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2611 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2616 THUMB_SET_FUNC (symbolP
, 0);
2617 ARM_SET_THUMB (symbolP
, 0);
2618 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2622 THUMB_SET_FUNC (symbolP
, 1);
2623 ARM_SET_THUMB (symbolP
, 1);
2624 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2632 /* Save the mapping symbols for future reference. Also check that
2633 we do not place two mapping symbols at the same offset within a
2634 frag. We'll handle overlap between frags in
2635 check_mapping_symbols.
2637 If .fill or other data filling directive generates zero sized data,
2638 the mapping symbol for the following code will have the same value
2639 as the one generated for the data filling directive. In this case,
2640 we replace the old symbol with the new one at the same address. */
2643 if (frag
->tc_frag_data
.first_map
!= NULL
)
2645 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2646 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2648 frag
->tc_frag_data
.first_map
= symbolP
;
2650 if (frag
->tc_frag_data
.last_map
!= NULL
)
2652 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2653 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2654 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2656 frag
->tc_frag_data
.last_map
= symbolP
;
2659 /* We must sometimes convert a region marked as code to data during
2660 code alignment, if an odd number of bytes have to be padded. The
2661 code mapping symbol is pushed to an aligned address. */
2664 insert_data_mapping_symbol (enum mstate state
,
2665 valueT value
, fragS
*frag
, offsetT bytes
)
2667 /* If there was already a mapping symbol, remove it. */
2668 if (frag
->tc_frag_data
.last_map
!= NULL
2669 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2671 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2675 know (frag
->tc_frag_data
.first_map
== symp
);
2676 frag
->tc_frag_data
.first_map
= NULL
;
2678 frag
->tc_frag_data
.last_map
= NULL
;
2679 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2682 make_mapping_symbol (MAP_DATA
, value
, frag
);
2683 make_mapping_symbol (state
, value
+ bytes
, frag
);
2686 static void mapping_state_2 (enum mstate state
, int max_chars
);
2688 /* Set the mapping state to STATE. Only call this when about to
2689 emit some STATE bytes to the file. */
2691 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2693 mapping_state (enum mstate state
)
2695 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2697 if (mapstate
== state
)
2698 /* The mapping symbol has already been emitted.
2699 There is nothing else to do. */
2702 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2704 All ARM instructions require 4-byte alignment.
2705 (Almost) all Thumb instructions require 2-byte alignment.
2707 When emitting instructions into any section, mark the section
2710 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2711 but themselves require 2-byte alignment; this applies to some
2712 PC- relative forms. However, these cases will involve implicit
2713 literal pool generation or an explicit .align >=2, both of
2714 which will cause the section to me marked with sufficient
2715 alignment. Thus, we don't handle those cases here. */
2716 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2718 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2719 /* This case will be evaluated later. */
2722 mapping_state_2 (state
, 0);
2725 /* Same as mapping_state, but MAX_CHARS bytes have already been
2726 allocated. Put the mapping symbol that far back. */
2729 mapping_state_2 (enum mstate state
, int max_chars
)
2731 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2733 if (!SEG_NORMAL (now_seg
))
2736 if (mapstate
== state
)
2737 /* The mapping symbol has already been emitted.
2738 There is nothing else to do. */
2741 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2742 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2744 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2745 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2748 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2751 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2752 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2756 #define mapping_state(x) ((void)0)
2757 #define mapping_state_2(x, y) ((void)0)
2760 /* Find the real, Thumb encoded start of a Thumb function. */
2764 find_real_start (symbolS
* symbolP
)
2767 const char * name
= S_GET_NAME (symbolP
);
2768 symbolS
* new_target
;
2770 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2771 #define STUB_NAME ".real_start_of"
2776 /* The compiler may generate BL instructions to local labels because
2777 it needs to perform a branch to a far away location. These labels
2778 do not have a corresponding ".real_start_of" label. We check
2779 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2780 the ".real_start_of" convention for nonlocal branches. */
2781 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2784 real_start
= concat (STUB_NAME
, name
, NULL
);
2785 new_target
= symbol_find (real_start
);
2788 if (new_target
== NULL
)
2790 as_warn (_("Failed to find real start of function: %s\n"), name
);
2791 new_target
= symbolP
;
2799 opcode_select (int width
)
2806 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2807 as_bad (_("selected processor does not support THUMB opcodes"));
2810 /* No need to force the alignment, since we will have been
2811 coming from ARM mode, which is word-aligned. */
2812 record_alignment (now_seg
, 1);
2819 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2820 as_bad (_("selected processor does not support ARM opcodes"));
2825 frag_align (2, 0, 0);
2827 record_alignment (now_seg
, 1);
2832 as_bad (_("invalid instruction size selected (%d)"), width
);
2837 s_arm (int ignore ATTRIBUTE_UNUSED
)
2840 demand_empty_rest_of_line ();
2844 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2847 demand_empty_rest_of_line ();
2851 s_code (int unused ATTRIBUTE_UNUSED
)
2855 temp
= get_absolute_expression ();
2860 opcode_select (temp
);
2864 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2869 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2871 /* If we are not already in thumb mode go into it, EVEN if
2872 the target processor does not support thumb instructions.
2873 This is used by gcc/config/arm/lib1funcs.asm for example
2874 to compile interworking support functions even if the
2875 target processor should not support interworking. */
2879 record_alignment (now_seg
, 1);
2882 demand_empty_rest_of_line ();
2886 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2890 /* The following label is the name/address of the start of a Thumb function.
2891 We need to know this for the interworking support. */
2892 label_is_thumb_function_name
= TRUE
;
2895 /* Perform a .set directive, but also mark the alias as
2896 being a thumb function. */
2899 s_thumb_set (int equiv
)
2901 /* XXX the following is a duplicate of the code for s_set() in read.c
2902 We cannot just call that code as we need to get at the symbol that
2909 /* Especial apologies for the random logic:
2910 This just grew, and could be parsed much more simply!
2912 delim
= get_symbol_name (& name
);
2913 end_name
= input_line_pointer
;
2914 (void) restore_line_pointer (delim
);
2916 if (*input_line_pointer
!= ',')
2919 as_bad (_("expected comma after name \"%s\""), name
);
2921 ignore_rest_of_line ();
2925 input_line_pointer
++;
2928 if (name
[0] == '.' && name
[1] == '\0')
2930 /* XXX - this should not happen to .thumb_set. */
2934 if ((symbolP
= symbol_find (name
)) == NULL
2935 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2938 /* When doing symbol listings, play games with dummy fragments living
2939 outside the normal fragment chain to record the file and line info
2941 if (listing
& LISTING_SYMBOLS
)
2943 extern struct list_info_struct
* listing_tail
;
2944 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2946 memset (dummy_frag
, 0, sizeof (fragS
));
2947 dummy_frag
->fr_type
= rs_fill
;
2948 dummy_frag
->line
= listing_tail
;
2949 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2950 dummy_frag
->fr_symbol
= symbolP
;
2954 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2957 /* "set" symbols are local unless otherwise specified. */
2958 SF_SET_LOCAL (symbolP
);
2959 #endif /* OBJ_COFF */
2960 } /* Make a new symbol. */
2962 symbol_table_insert (symbolP
);
2967 && S_IS_DEFINED (symbolP
)
2968 && S_GET_SEGMENT (symbolP
) != reg_section
)
2969 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2971 pseudo_set (symbolP
);
2973 demand_empty_rest_of_line ();
2975 /* XXX Now we come to the Thumb specific bit of code. */
2977 THUMB_SET_FUNC (symbolP
, 1);
2978 ARM_SET_THUMB (symbolP
, 1);
2979 #if defined OBJ_ELF || defined OBJ_COFF
2980 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2984 /* Directives: Mode selection. */
2986 /* .syntax [unified|divided] - choose the new unified syntax
2987 (same for Arm and Thumb encoding, modulo slight differences in what
2988 can be represented) or the old divergent syntax for each mode. */
2990 s_syntax (int unused ATTRIBUTE_UNUSED
)
2994 delim
= get_symbol_name (& name
);
2996 if (!strcasecmp (name
, "unified"))
2997 unified_syntax
= TRUE
;
2998 else if (!strcasecmp (name
, "divided"))
2999 unified_syntax
= FALSE
;
3002 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3005 (void) restore_line_pointer (delim
);
3006 demand_empty_rest_of_line ();
3009 /* Directives: sectioning and alignment. */
3012 s_bss (int ignore ATTRIBUTE_UNUSED
)
3014 /* We don't support putting frags in the BSS segment, we fake it by
3015 marking in_bss, then looking at s_skip for clues. */
3016 subseg_set (bss_section
, 0);
3017 demand_empty_rest_of_line ();
3019 #ifdef md_elf_section_change_hook
3020 md_elf_section_change_hook ();
3025 s_even (int ignore ATTRIBUTE_UNUSED
)
3027 /* Never make frag if expect extra pass. */
3029 frag_align (1, 0, 0);
3031 record_alignment (now_seg
, 1);
3033 demand_empty_rest_of_line ();
3036 /* Directives: CodeComposer Studio. */
3038 /* .ref (for CodeComposer Studio syntax only). */
3040 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3042 if (codecomposer_syntax
)
3043 ignore_rest_of_line ();
3045 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3048 /* If name is not NULL, then it is used for marking the beginning of a
3049 function, whereas if it is NULL then it means the function end. */
3051 asmfunc_debug (const char * name
)
3053 static const char * last_name
= NULL
;
3057 gas_assert (last_name
== NULL
);
3060 if (debug_type
== DEBUG_STABS
)
3061 stabs_generate_asm_func (name
, name
);
3065 gas_assert (last_name
!= NULL
);
3067 if (debug_type
== DEBUG_STABS
)
3068 stabs_generate_asm_endfunc (last_name
, last_name
);
3075 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3077 if (codecomposer_syntax
)
3079 switch (asmfunc_state
)
3081 case OUTSIDE_ASMFUNC
:
3082 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3085 case WAITING_ASMFUNC_NAME
:
3086 as_bad (_(".asmfunc repeated."));
3089 case WAITING_ENDASMFUNC
:
3090 as_bad (_(".asmfunc without function."));
3093 demand_empty_rest_of_line ();
3096 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3100 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3102 if (codecomposer_syntax
)
3104 switch (asmfunc_state
)
3106 case OUTSIDE_ASMFUNC
:
3107 as_bad (_(".endasmfunc without a .asmfunc."));
3110 case WAITING_ASMFUNC_NAME
:
3111 as_bad (_(".endasmfunc without function."));
3114 case WAITING_ENDASMFUNC
:
3115 asmfunc_state
= OUTSIDE_ASMFUNC
;
3116 asmfunc_debug (NULL
);
3119 demand_empty_rest_of_line ();
3122 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3126 s_ccs_def (int name
)
3128 if (codecomposer_syntax
)
3131 as_bad (_(".def pseudo-op only available with -mccs flag."));
3134 /* Directives: Literal pools. */
3136 static literal_pool
*
3137 find_literal_pool (void)
3139 literal_pool
* pool
;
3141 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3143 if (pool
->section
== now_seg
3144 && pool
->sub_section
== now_subseg
)
3151 static literal_pool
*
3152 find_or_make_literal_pool (void)
3154 /* Next literal pool ID number. */
3155 static unsigned int latest_pool_num
= 1;
3156 literal_pool
* pool
;
3158 pool
= find_literal_pool ();
3162 /* Create a new pool. */
3163 pool
= XNEW (literal_pool
);
3167 pool
->next_free_entry
= 0;
3168 pool
->section
= now_seg
;
3169 pool
->sub_section
= now_subseg
;
3170 pool
->next
= list_of_pools
;
3171 pool
->symbol
= NULL
;
3172 pool
->alignment
= 2;
3174 /* Add it to the list. */
3175 list_of_pools
= pool
;
3178 /* New pools, and emptied pools, will have a NULL symbol. */
3179 if (pool
->symbol
== NULL
)
3181 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3182 (valueT
) 0, &zero_address_frag
);
3183 pool
->id
= latest_pool_num
++;
3190 /* Add the literal in the global 'inst'
3191 structure to the relevant literal pool. */
3194 add_to_lit_pool (unsigned int nbytes
)
3196 #define PADDING_SLOT 0x1
3197 #define LIT_ENTRY_SIZE_MASK 0xFF
3198 literal_pool
* pool
;
3199 unsigned int entry
, pool_size
= 0;
3200 bfd_boolean padding_slot_p
= FALSE
;
3206 imm1
= inst
.operands
[1].imm
;
3207 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3208 : inst
.reloc
.exp
.X_unsigned
? 0
3209 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3210 if (target_big_endian
)
3213 imm2
= inst
.operands
[1].imm
;
3217 pool
= find_or_make_literal_pool ();
3219 /* Check if this literal value is already in the pool. */
3220 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3224 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3225 && (inst
.reloc
.exp
.X_op
== O_constant
)
3226 && (pool
->literals
[entry
].X_add_number
3227 == inst
.reloc
.exp
.X_add_number
)
3228 && (pool
->literals
[entry
].X_md
== nbytes
)
3229 && (pool
->literals
[entry
].X_unsigned
3230 == inst
.reloc
.exp
.X_unsigned
))
3233 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3234 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3235 && (pool
->literals
[entry
].X_add_number
3236 == inst
.reloc
.exp
.X_add_number
)
3237 && (pool
->literals
[entry
].X_add_symbol
3238 == inst
.reloc
.exp
.X_add_symbol
)
3239 && (pool
->literals
[entry
].X_op_symbol
3240 == inst
.reloc
.exp
.X_op_symbol
)
3241 && (pool
->literals
[entry
].X_md
== nbytes
))
3244 else if ((nbytes
== 8)
3245 && !(pool_size
& 0x7)
3246 && ((entry
+ 1) != pool
->next_free_entry
)
3247 && (pool
->literals
[entry
].X_op
== O_constant
)
3248 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3249 && (pool
->literals
[entry
].X_unsigned
3250 == inst
.reloc
.exp
.X_unsigned
)
3251 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3252 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3253 && (pool
->literals
[entry
+ 1].X_unsigned
3254 == inst
.reloc
.exp
.X_unsigned
))
3257 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3258 if (padding_slot_p
&& (nbytes
== 4))
3264 /* Do we need to create a new entry? */
3265 if (entry
== pool
->next_free_entry
)
3267 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3269 inst
.error
= _("literal pool overflow");
3275 /* For 8-byte entries, we align to an 8-byte boundary,
3276 and split it into two 4-byte entries, because on 32-bit
3277 host, 8-byte constants are treated as big num, thus
3278 saved in "generic_bignum" which will be overwritten
3279 by later assignments.
3281 We also need to make sure there is enough space for
3284 We also check to make sure the literal operand is a
3286 if (!(inst
.reloc
.exp
.X_op
== O_constant
3287 || inst
.reloc
.exp
.X_op
== O_big
))
3289 inst
.error
= _("invalid type for literal pool");
3292 else if (pool_size
& 0x7)
3294 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3296 inst
.error
= _("literal pool overflow");
3300 pool
->literals
[entry
] = inst
.reloc
.exp
;
3301 pool
->literals
[entry
].X_op
= O_constant
;
3302 pool
->literals
[entry
].X_add_number
= 0;
3303 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3304 pool
->next_free_entry
+= 1;
3307 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3309 inst
.error
= _("literal pool overflow");
3313 pool
->literals
[entry
] = inst
.reloc
.exp
;
3314 pool
->literals
[entry
].X_op
= O_constant
;
3315 pool
->literals
[entry
].X_add_number
= imm1
;
3316 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3317 pool
->literals
[entry
++].X_md
= 4;
3318 pool
->literals
[entry
] = inst
.reloc
.exp
;
3319 pool
->literals
[entry
].X_op
= O_constant
;
3320 pool
->literals
[entry
].X_add_number
= imm2
;
3321 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3322 pool
->literals
[entry
].X_md
= 4;
3323 pool
->alignment
= 3;
3324 pool
->next_free_entry
+= 1;
3328 pool
->literals
[entry
] = inst
.reloc
.exp
;
3329 pool
->literals
[entry
].X_md
= 4;
3333 /* PR ld/12974: Record the location of the first source line to reference
3334 this entry in the literal pool. If it turns out during linking that the
3335 symbol does not exist we will be able to give an accurate line number for
3336 the (first use of the) missing reference. */
3337 if (debug_type
== DEBUG_DWARF2
)
3338 dwarf2_where (pool
->locs
+ entry
);
3340 pool
->next_free_entry
+= 1;
3342 else if (padding_slot_p
)
3344 pool
->literals
[entry
] = inst
.reloc
.exp
;
3345 pool
->literals
[entry
].X_md
= nbytes
;
3348 inst
.reloc
.exp
.X_op
= O_symbol
;
3349 inst
.reloc
.exp
.X_add_number
= pool_size
;
3350 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3356 tc_start_label_without_colon (void)
3358 bfd_boolean ret
= TRUE
;
3360 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3362 const char *label
= input_line_pointer
;
3364 while (!is_end_of_line
[(int) label
[-1]])
3369 as_bad (_("Invalid label '%s'"), label
);
3373 asmfunc_debug (label
);
3375 asmfunc_state
= WAITING_ENDASMFUNC
;
3381 /* Can't use symbol_new here, so have to create a symbol and then at
3382 a later date assign it a value. That's what these functions do. */
3385 symbol_locate (symbolS
* symbolP
,
3386 const char * name
, /* It is copied, the caller can modify. */
3387 segT segment
, /* Segment identifier (SEG_<something>). */
3388 valueT valu
, /* Symbol value. */
3389 fragS
* frag
) /* Associated fragment. */
3392 char * preserved_copy_of_name
;
3394 name_length
= strlen (name
) + 1; /* +1 for \0. */
3395 obstack_grow (¬es
, name
, name_length
);
3396 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3398 #ifdef tc_canonicalize_symbol_name
3399 preserved_copy_of_name
=
3400 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3403 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3405 S_SET_SEGMENT (symbolP
, segment
);
3406 S_SET_VALUE (symbolP
, valu
);
3407 symbol_clear_list_pointers (symbolP
);
3409 symbol_set_frag (symbolP
, frag
);
3411 /* Link to end of symbol chain. */
3413 extern int symbol_table_frozen
;
3415 if (symbol_table_frozen
)
3419 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3421 obj_symbol_new_hook (symbolP
);
3423 #ifdef tc_symbol_new_hook
3424 tc_symbol_new_hook (symbolP
);
3428 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3429 #endif /* DEBUG_SYMS */
3433 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3436 literal_pool
* pool
;
3439 pool
= find_literal_pool ();
3441 || pool
->symbol
== NULL
3442 || pool
->next_free_entry
== 0)
3445 /* Align pool as you have word accesses.
3446 Only make a frag if we have to. */
3448 frag_align (pool
->alignment
, 0, 0);
3450 record_alignment (now_seg
, 2);
3453 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3454 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3456 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3458 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3459 (valueT
) frag_now_fix (), frag_now
);
3460 symbol_table_insert (pool
->symbol
);
3462 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3464 #if defined OBJ_COFF || defined OBJ_ELF
3465 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3468 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3471 if (debug_type
== DEBUG_DWARF2
)
3472 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3474 /* First output the expression in the instruction to the pool. */
3475 emit_expr (&(pool
->literals
[entry
]),
3476 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3479 /* Mark the pool as empty. */
3480 pool
->next_free_entry
= 0;
3481 pool
->symbol
= NULL
;
3485 /* Forward declarations for functions below, in the MD interface
3487 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3488 static valueT
create_unwind_entry (int);
3489 static void start_unwind_section (const segT
, int);
3490 static void add_unwind_opcode (valueT
, int);
3491 static void flush_pending_unwind (void);
3493 /* Directives: Data. */
3496 s_arm_elf_cons (int nbytes
)
3500 #ifdef md_flush_pending_output
3501 md_flush_pending_output ();
3504 if (is_it_end_of_statement ())
3506 demand_empty_rest_of_line ();
3510 #ifdef md_cons_align
3511 md_cons_align (nbytes
);
3514 mapping_state (MAP_DATA
);
3518 char *base
= input_line_pointer
;
3522 if (exp
.X_op
!= O_symbol
)
3523 emit_expr (&exp
, (unsigned int) nbytes
);
3526 char *before_reloc
= input_line_pointer
;
3527 reloc
= parse_reloc (&input_line_pointer
);
3530 as_bad (_("unrecognized relocation suffix"));
3531 ignore_rest_of_line ();
3534 else if (reloc
== BFD_RELOC_UNUSED
)
3535 emit_expr (&exp
, (unsigned int) nbytes
);
3538 reloc_howto_type
*howto
= (reloc_howto_type
*)
3539 bfd_reloc_type_lookup (stdoutput
,
3540 (bfd_reloc_code_real_type
) reloc
);
3541 int size
= bfd_get_reloc_size (howto
);
3543 if (reloc
== BFD_RELOC_ARM_PLT32
)
3545 as_bad (_("(plt) is only valid on branch targets"));
3546 reloc
= BFD_RELOC_UNUSED
;
3551 as_bad (_("%s relocations do not fit in %d bytes"),
3552 howto
->name
, nbytes
);
3555 /* We've parsed an expression stopping at O_symbol.
3556 But there may be more expression left now that we
3557 have parsed the relocation marker. Parse it again.
3558 XXX Surely there is a cleaner way to do this. */
3559 char *p
= input_line_pointer
;
3561 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3563 memcpy (save_buf
, base
, input_line_pointer
- base
);
3564 memmove (base
+ (input_line_pointer
- before_reloc
),
3565 base
, before_reloc
- base
);
3567 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3569 memcpy (base
, save_buf
, p
- base
);
3571 offset
= nbytes
- size
;
3572 p
= frag_more (nbytes
);
3573 memset (p
, 0, nbytes
);
3574 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3575 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3581 while (*input_line_pointer
++ == ',');
3583 /* Put terminator back into stream. */
3584 input_line_pointer
--;
3585 demand_empty_rest_of_line ();
3588 /* Emit an expression containing a 32-bit thumb instruction.
3589 Implementation based on put_thumb32_insn. */
3592 emit_thumb32_expr (expressionS
* exp
)
3594 expressionS exp_high
= *exp
;
3596 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3597 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3598 exp
->X_add_number
&= 0xffff;
3599 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3602 /* Guess the instruction size based on the opcode. */
3605 thumb_insn_size (int opcode
)
3607 if ((unsigned int) opcode
< 0xe800u
)
3609 else if ((unsigned int) opcode
>= 0xe8000000u
)
3616 emit_insn (expressionS
*exp
, int nbytes
)
3620 if (exp
->X_op
== O_constant
)
3625 size
= thumb_insn_size (exp
->X_add_number
);
3629 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3631 as_bad (_(".inst.n operand too big. "\
3632 "Use .inst.w instead"));
3637 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3638 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3640 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3642 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3643 emit_thumb32_expr (exp
);
3645 emit_expr (exp
, (unsigned int) size
);
3647 it_fsm_post_encode ();
3651 as_bad (_("cannot determine Thumb instruction size. " \
3652 "Use .inst.n/.inst.w instead"));
3655 as_bad (_("constant expression required"));
3660 /* Like s_arm_elf_cons but do not use md_cons_align and
3661 set the mapping state to MAP_ARM/MAP_THUMB. */
3664 s_arm_elf_inst (int nbytes
)
3666 if (is_it_end_of_statement ())
3668 demand_empty_rest_of_line ();
3672 /* Calling mapping_state () here will not change ARM/THUMB,
3673 but will ensure not to be in DATA state. */
3676 mapping_state (MAP_THUMB
);
3681 as_bad (_("width suffixes are invalid in ARM mode"));
3682 ignore_rest_of_line ();
3688 mapping_state (MAP_ARM
);
3697 if (! emit_insn (& exp
, nbytes
))
3699 ignore_rest_of_line ();
3703 while (*input_line_pointer
++ == ',');
3705 /* Put terminator back into stream. */
3706 input_line_pointer
--;
3707 demand_empty_rest_of_line ();
3710 /* Parse a .rel31 directive. */
3713 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3720 if (*input_line_pointer
== '1')
3721 highbit
= 0x80000000;
3722 else if (*input_line_pointer
!= '0')
3723 as_bad (_("expected 0 or 1"));
3725 input_line_pointer
++;
3726 if (*input_line_pointer
!= ',')
3727 as_bad (_("missing comma"));
3728 input_line_pointer
++;
3730 #ifdef md_flush_pending_output
3731 md_flush_pending_output ();
3734 #ifdef md_cons_align
3738 mapping_state (MAP_DATA
);
3743 md_number_to_chars (p
, highbit
, 4);
3744 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3745 BFD_RELOC_ARM_PREL31
);
3747 demand_empty_rest_of_line ();
3750 /* Directives: AEABI stack-unwind tables. */
3752 /* Parse an unwind_fnstart directive. Simply records the current location. */
3755 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3757 demand_empty_rest_of_line ();
3758 if (unwind
.proc_start
)
3760 as_bad (_("duplicate .fnstart directive"));
3764 /* Mark the start of the function. */
3765 unwind
.proc_start
= expr_build_dot ();
3767 /* Reset the rest of the unwind info. */
3768 unwind
.opcode_count
= 0;
3769 unwind
.table_entry
= NULL
;
3770 unwind
.personality_routine
= NULL
;
3771 unwind
.personality_index
= -1;
3772 unwind
.frame_size
= 0;
3773 unwind
.fp_offset
= 0;
3774 unwind
.fp_reg
= REG_SP
;
3776 unwind
.sp_restored
= 0;
3780 /* Parse a handlerdata directive. Creates the exception handling table entry
3781 for the function. */
3784 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3786 demand_empty_rest_of_line ();
3787 if (!unwind
.proc_start
)
3788 as_bad (MISSING_FNSTART
);
3790 if (unwind
.table_entry
)
3791 as_bad (_("duplicate .handlerdata directive"));
3793 create_unwind_entry (1);
3796 /* Parse an unwind_fnend directive. Generates the index table entry. */
3799 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3804 unsigned int marked_pr_dependency
;
3806 demand_empty_rest_of_line ();
3808 if (!unwind
.proc_start
)
3810 as_bad (_(".fnend directive without .fnstart"));
3814 /* Add eh table entry. */
3815 if (unwind
.table_entry
== NULL
)
3816 val
= create_unwind_entry (0);
3820 /* Add index table entry. This is two words. */
3821 start_unwind_section (unwind
.saved_seg
, 1);
3822 frag_align (2, 0, 0);
3823 record_alignment (now_seg
, 2);
3825 ptr
= frag_more (8);
3827 where
= frag_now_fix () - 8;
3829 /* Self relative offset of the function start. */
3830 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3831 BFD_RELOC_ARM_PREL31
);
3833 /* Indicate dependency on EHABI-defined personality routines to the
3834 linker, if it hasn't been done already. */
3835 marked_pr_dependency
3836 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3837 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3838 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3840 static const char *const name
[] =
3842 "__aeabi_unwind_cpp_pr0",
3843 "__aeabi_unwind_cpp_pr1",
3844 "__aeabi_unwind_cpp_pr2"
3846 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3847 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3848 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3849 |= 1 << unwind
.personality_index
;
3853 /* Inline exception table entry. */
3854 md_number_to_chars (ptr
+ 4, val
, 4);
3856 /* Self relative offset of the table entry. */
3857 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3858 BFD_RELOC_ARM_PREL31
);
3860 /* Restore the original section. */
3861 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3863 unwind
.proc_start
= NULL
;
3867 /* Parse an unwind_cantunwind directive. */
3870 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3872 demand_empty_rest_of_line ();
3873 if (!unwind
.proc_start
)
3874 as_bad (MISSING_FNSTART
);
3876 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3877 as_bad (_("personality routine specified for cantunwind frame"));
3879 unwind
.personality_index
= -2;
3883 /* Parse a personalityindex directive. */
3886 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3890 if (!unwind
.proc_start
)
3891 as_bad (MISSING_FNSTART
);
3893 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3894 as_bad (_("duplicate .personalityindex directive"));
3898 if (exp
.X_op
!= O_constant
3899 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3901 as_bad (_("bad personality routine number"));
3902 ignore_rest_of_line ();
3906 unwind
.personality_index
= exp
.X_add_number
;
3908 demand_empty_rest_of_line ();
3912 /* Parse a personality directive. */
3915 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3919 if (!unwind
.proc_start
)
3920 as_bad (MISSING_FNSTART
);
3922 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3923 as_bad (_("duplicate .personality directive"));
3925 c
= get_symbol_name (& name
);
3926 p
= input_line_pointer
;
3928 ++ input_line_pointer
;
3929 unwind
.personality_routine
= symbol_find_or_make (name
);
3931 demand_empty_rest_of_line ();
3935 /* Parse a directive saving core registers. */
3938 s_arm_unwind_save_core (void)
3944 range
= parse_reg_list (&input_line_pointer
);
3947 as_bad (_("expected register list"));
3948 ignore_rest_of_line ();
3952 demand_empty_rest_of_line ();
3954 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3955 into .unwind_save {..., sp...}. We aren't bothered about the value of
3956 ip because it is clobbered by calls. */
3957 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3958 && (range
& 0x3000) == 0x1000)
3960 unwind
.opcode_count
--;
3961 unwind
.sp_restored
= 0;
3962 range
= (range
| 0x2000) & ~0x1000;
3963 unwind
.pending_offset
= 0;
3969 /* See if we can use the short opcodes. These pop a block of up to 8
3970 registers starting with r4, plus maybe r14. */
3971 for (n
= 0; n
< 8; n
++)
3973 /* Break at the first non-saved register. */
3974 if ((range
& (1 << (n
+ 4))) == 0)
3977 /* See if there are any other bits set. */
3978 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3980 /* Use the long form. */
3981 op
= 0x8000 | ((range
>> 4) & 0xfff);
3982 add_unwind_opcode (op
, 2);
3986 /* Use the short form. */
3988 op
= 0xa8; /* Pop r14. */
3990 op
= 0xa0; /* Do not pop r14. */
3992 add_unwind_opcode (op
, 1);
3999 op
= 0xb100 | (range
& 0xf);
4000 add_unwind_opcode (op
, 2);
4003 /* Record the number of bytes pushed. */
4004 for (n
= 0; n
< 16; n
++)
4006 if (range
& (1 << n
))
4007 unwind
.frame_size
+= 4;
4012 /* Parse a directive saving FPA registers. */
4015 s_arm_unwind_save_fpa (int reg
)
4021 /* Get Number of registers to transfer. */
4022 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4025 exp
.X_op
= O_illegal
;
4027 if (exp
.X_op
!= O_constant
)
4029 as_bad (_("expected , <constant>"));
4030 ignore_rest_of_line ();
4034 num_regs
= exp
.X_add_number
;
4036 if (num_regs
< 1 || num_regs
> 4)
4038 as_bad (_("number of registers must be in the range [1:4]"));
4039 ignore_rest_of_line ();
4043 demand_empty_rest_of_line ();
4048 op
= 0xb4 | (num_regs
- 1);
4049 add_unwind_opcode (op
, 1);
4054 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4055 add_unwind_opcode (op
, 2);
4057 unwind
.frame_size
+= num_regs
* 12;
4061 /* Parse a directive saving VFP registers for ARMv6 and above. */
4064 s_arm_unwind_save_vfp_armv6 (void)
4069 int num_vfpv3_regs
= 0;
4070 int num_regs_below_16
;
4072 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4075 as_bad (_("expected register list"));
4076 ignore_rest_of_line ();
4080 demand_empty_rest_of_line ();
4082 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4083 than FSTMX/FLDMX-style ones). */
4085 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4087 num_vfpv3_regs
= count
;
4088 else if (start
+ count
> 16)
4089 num_vfpv3_regs
= start
+ count
- 16;
4091 if (num_vfpv3_regs
> 0)
4093 int start_offset
= start
> 16 ? start
- 16 : 0;
4094 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4095 add_unwind_opcode (op
, 2);
4098 /* Generate opcode for registers numbered in the range 0 .. 15. */
4099 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4100 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4101 if (num_regs_below_16
> 0)
4103 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4104 add_unwind_opcode (op
, 2);
4107 unwind
.frame_size
+= count
* 8;
4111 /* Parse a directive saving VFP registers for pre-ARMv6. */
4114 s_arm_unwind_save_vfp (void)
4120 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4123 as_bad (_("expected register list"));
4124 ignore_rest_of_line ();
4128 demand_empty_rest_of_line ();
4133 op
= 0xb8 | (count
- 1);
4134 add_unwind_opcode (op
, 1);
4139 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4140 add_unwind_opcode (op
, 2);
4142 unwind
.frame_size
+= count
* 8 + 4;
4146 /* Parse a directive saving iWMMXt data registers. */
4149 s_arm_unwind_save_mmxwr (void)
4157 if (*input_line_pointer
== '{')
4158 input_line_pointer
++;
4162 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4166 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4171 as_tsktsk (_("register list not in ascending order"));
4174 if (*input_line_pointer
== '-')
4176 input_line_pointer
++;
4177 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4180 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4183 else if (reg
>= hi_reg
)
4185 as_bad (_("bad register range"));
4188 for (; reg
< hi_reg
; reg
++)
4192 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4194 skip_past_char (&input_line_pointer
, '}');
4196 demand_empty_rest_of_line ();
4198 /* Generate any deferred opcodes because we're going to be looking at
4200 flush_pending_unwind ();
4202 for (i
= 0; i
< 16; i
++)
4204 if (mask
& (1 << i
))
4205 unwind
.frame_size
+= 8;
4208 /* Attempt to combine with a previous opcode. We do this because gcc
4209 likes to output separate unwind directives for a single block of
4211 if (unwind
.opcode_count
> 0)
4213 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4214 if ((i
& 0xf8) == 0xc0)
4217 /* Only merge if the blocks are contiguous. */
4220 if ((mask
& 0xfe00) == (1 << 9))
4222 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4223 unwind
.opcode_count
--;
4226 else if (i
== 6 && unwind
.opcode_count
>= 2)
4228 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4232 op
= 0xffff << (reg
- 1);
4234 && ((mask
& op
) == (1u << (reg
- 1))))
4236 op
= (1 << (reg
+ i
+ 1)) - 1;
4237 op
&= ~((1 << reg
) - 1);
4239 unwind
.opcode_count
-= 2;
4246 /* We want to generate opcodes in the order the registers have been
4247 saved, ie. descending order. */
4248 for (reg
= 15; reg
>= -1; reg
--)
4250 /* Save registers in blocks. */
4252 || !(mask
& (1 << reg
)))
4254 /* We found an unsaved reg. Generate opcodes to save the
4261 op
= 0xc0 | (hi_reg
- 10);
4262 add_unwind_opcode (op
, 1);
4267 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4268 add_unwind_opcode (op
, 2);
4277 ignore_rest_of_line ();
4281 s_arm_unwind_save_mmxwcg (void)
4288 if (*input_line_pointer
== '{')
4289 input_line_pointer
++;
4291 skip_whitespace (input_line_pointer
);
4295 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4299 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4305 as_tsktsk (_("register list not in ascending order"));
4308 if (*input_line_pointer
== '-')
4310 input_line_pointer
++;
4311 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4314 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4317 else if (reg
>= hi_reg
)
4319 as_bad (_("bad register range"));
4322 for (; reg
< hi_reg
; reg
++)
4326 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4328 skip_past_char (&input_line_pointer
, '}');
4330 demand_empty_rest_of_line ();
4332 /* Generate any deferred opcodes because we're going to be looking at
4334 flush_pending_unwind ();
4336 for (reg
= 0; reg
< 16; reg
++)
4338 if (mask
& (1 << reg
))
4339 unwind
.frame_size
+= 4;
4342 add_unwind_opcode (op
, 2);
4345 ignore_rest_of_line ();
4349 /* Parse an unwind_save directive.
4350 If the argument is non-zero, this is a .vsave directive. */
4353 s_arm_unwind_save (int arch_v6
)
4356 struct reg_entry
*reg
;
4357 bfd_boolean had_brace
= FALSE
;
4359 if (!unwind
.proc_start
)
4360 as_bad (MISSING_FNSTART
);
4362 /* Figure out what sort of save we have. */
4363 peek
= input_line_pointer
;
4371 reg
= arm_reg_parse_multi (&peek
);
4375 as_bad (_("register expected"));
4376 ignore_rest_of_line ();
4385 as_bad (_("FPA .unwind_save does not take a register list"));
4386 ignore_rest_of_line ();
4389 input_line_pointer
= peek
;
4390 s_arm_unwind_save_fpa (reg
->number
);
4394 s_arm_unwind_save_core ();
4399 s_arm_unwind_save_vfp_armv6 ();
4401 s_arm_unwind_save_vfp ();
4404 case REG_TYPE_MMXWR
:
4405 s_arm_unwind_save_mmxwr ();
4408 case REG_TYPE_MMXWCG
:
4409 s_arm_unwind_save_mmxwcg ();
4413 as_bad (_(".unwind_save does not support this kind of register"));
4414 ignore_rest_of_line ();
4419 /* Parse an unwind_movsp directive. */
4422 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4428 if (!unwind
.proc_start
)
4429 as_bad (MISSING_FNSTART
);
4431 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4434 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4435 ignore_rest_of_line ();
4439 /* Optional constant. */
4440 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4442 if (immediate_for_directive (&offset
) == FAIL
)
4448 demand_empty_rest_of_line ();
4450 if (reg
== REG_SP
|| reg
== REG_PC
)
4452 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4456 if (unwind
.fp_reg
!= REG_SP
)
4457 as_bad (_("unexpected .unwind_movsp directive"));
4459 /* Generate opcode to restore the value. */
4461 add_unwind_opcode (op
, 1);
4463 /* Record the information for later. */
4464 unwind
.fp_reg
= reg
;
4465 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4466 unwind
.sp_restored
= 1;
4469 /* Parse an unwind_pad directive. */
4472 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4476 if (!unwind
.proc_start
)
4477 as_bad (MISSING_FNSTART
);
4479 if (immediate_for_directive (&offset
) == FAIL
)
4484 as_bad (_("stack increment must be multiple of 4"));
4485 ignore_rest_of_line ();
4489 /* Don't generate any opcodes, just record the details for later. */
4490 unwind
.frame_size
+= offset
;
4491 unwind
.pending_offset
+= offset
;
4493 demand_empty_rest_of_line ();
4496 /* Parse an unwind_setfp directive. */
4499 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4505 if (!unwind
.proc_start
)
4506 as_bad (MISSING_FNSTART
);
4508 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4509 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4512 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4514 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4516 as_bad (_("expected <reg>, <reg>"));
4517 ignore_rest_of_line ();
4521 /* Optional constant. */
4522 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4524 if (immediate_for_directive (&offset
) == FAIL
)
4530 demand_empty_rest_of_line ();
4532 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4534 as_bad (_("register must be either sp or set by a previous"
4535 "unwind_movsp directive"));
4539 /* Don't generate any opcodes, just record the information for later. */
4540 unwind
.fp_reg
= fp_reg
;
4542 if (sp_reg
== REG_SP
)
4543 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4545 unwind
.fp_offset
-= offset
;
4548 /* Parse an unwind_raw directive. */
4551 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4554 /* This is an arbitrary limit. */
4555 unsigned char op
[16];
4558 if (!unwind
.proc_start
)
4559 as_bad (MISSING_FNSTART
);
4562 if (exp
.X_op
== O_constant
4563 && skip_past_comma (&input_line_pointer
) != FAIL
)
4565 unwind
.frame_size
+= exp
.X_add_number
;
4569 exp
.X_op
= O_illegal
;
4571 if (exp
.X_op
!= O_constant
)
4573 as_bad (_("expected <offset>, <opcode>"));
4574 ignore_rest_of_line ();
4580 /* Parse the opcode. */
4585 as_bad (_("unwind opcode too long"));
4586 ignore_rest_of_line ();
4588 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4590 as_bad (_("invalid unwind opcode"));
4591 ignore_rest_of_line ();
4594 op
[count
++] = exp
.X_add_number
;
4596 /* Parse the next byte. */
4597 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4603 /* Add the opcode bytes in reverse order. */
4605 add_unwind_opcode (op
[count
], 1);
4607 demand_empty_rest_of_line ();
4611 /* Parse a .eabi_attribute directive. */
4614 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4616 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4618 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4619 attributes_set_explicitly
[tag
] = 1;
4622 /* Emit a tls fix for the symbol. */
4625 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4629 #ifdef md_flush_pending_output
4630 md_flush_pending_output ();
4633 #ifdef md_cons_align
4637 /* Since we're just labelling the code, there's no need to define a
4640 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4641 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4642 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4643 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4645 #endif /* OBJ_ELF */
4647 static void s_arm_arch (int);
4648 static void s_arm_object_arch (int);
4649 static void s_arm_cpu (int);
4650 static void s_arm_fpu (int);
4651 static void s_arm_arch_extension (int);
4656 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4663 if (exp
.X_op
== O_symbol
)
4664 exp
.X_op
= O_secrel
;
4666 emit_expr (&exp
, 4);
4668 while (*input_line_pointer
++ == ',');
4670 input_line_pointer
--;
4671 demand_empty_rest_of_line ();
4675 /* This table describes all the machine specific pseudo-ops the assembler
4676 has to support. The fields are:
4677 pseudo-op name without dot
4678 function to call to execute this pseudo-op
4679 Integer arg to pass to the function. */
4681 const pseudo_typeS md_pseudo_table
[] =
4683 /* Never called because '.req' does not start a line. */
4684 { "req", s_req
, 0 },
4685 /* Following two are likewise never called. */
4688 { "unreq", s_unreq
, 0 },
4689 { "bss", s_bss
, 0 },
4690 { "align", s_align_ptwo
, 2 },
4691 { "arm", s_arm
, 0 },
4692 { "thumb", s_thumb
, 0 },
4693 { "code", s_code
, 0 },
4694 { "force_thumb", s_force_thumb
, 0 },
4695 { "thumb_func", s_thumb_func
, 0 },
4696 { "thumb_set", s_thumb_set
, 0 },
4697 { "even", s_even
, 0 },
4698 { "ltorg", s_ltorg
, 0 },
4699 { "pool", s_ltorg
, 0 },
4700 { "syntax", s_syntax
, 0 },
4701 { "cpu", s_arm_cpu
, 0 },
4702 { "arch", s_arm_arch
, 0 },
4703 { "object_arch", s_arm_object_arch
, 0 },
4704 { "fpu", s_arm_fpu
, 0 },
4705 { "arch_extension", s_arm_arch_extension
, 0 },
4707 { "word", s_arm_elf_cons
, 4 },
4708 { "long", s_arm_elf_cons
, 4 },
4709 { "inst.n", s_arm_elf_inst
, 2 },
4710 { "inst.w", s_arm_elf_inst
, 4 },
4711 { "inst", s_arm_elf_inst
, 0 },
4712 { "rel31", s_arm_rel31
, 0 },
4713 { "fnstart", s_arm_unwind_fnstart
, 0 },
4714 { "fnend", s_arm_unwind_fnend
, 0 },
4715 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4716 { "personality", s_arm_unwind_personality
, 0 },
4717 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4718 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4719 { "save", s_arm_unwind_save
, 0 },
4720 { "vsave", s_arm_unwind_save
, 1 },
4721 { "movsp", s_arm_unwind_movsp
, 0 },
4722 { "pad", s_arm_unwind_pad
, 0 },
4723 { "setfp", s_arm_unwind_setfp
, 0 },
4724 { "unwind_raw", s_arm_unwind_raw
, 0 },
4725 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4726 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4730 /* These are used for dwarf. */
4734 /* These are used for dwarf2. */
4735 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4736 { "loc", dwarf2_directive_loc
, 0 },
4737 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4739 { "extend", float_cons
, 'x' },
4740 { "ldouble", float_cons
, 'x' },
4741 { "packed", float_cons
, 'p' },
4743 {"secrel32", pe_directive_secrel
, 0},
4746 /* These are for compatibility with CodeComposer Studio. */
4747 {"ref", s_ccs_ref
, 0},
4748 {"def", s_ccs_def
, 0},
4749 {"asmfunc", s_ccs_asmfunc
, 0},
4750 {"endasmfunc", s_ccs_endasmfunc
, 0},
4755 /* Parser functions used exclusively in instruction operands. */
4757 /* Generic immediate-value read function for use in insn parsing.
4758 STR points to the beginning of the immediate (the leading #);
4759 VAL receives the value; if the value is outside [MIN, MAX]
4760 issue an error. PREFIX_OPT is true if the immediate prefix is
4764 parse_immediate (char **str
, int *val
, int min
, int max
,
4765 bfd_boolean prefix_opt
)
4768 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4769 if (exp
.X_op
!= O_constant
)
4771 inst
.error
= _("constant expression required");
4775 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4777 inst
.error
= _("immediate value out of range");
4781 *val
= exp
.X_add_number
;
4785 /* Less-generic immediate-value read function with the possibility of loading a
4786 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4787 instructions. Puts the result directly in inst.operands[i]. */
4790 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4791 bfd_boolean allow_symbol_p
)
4794 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4797 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4799 if (exp_p
->X_op
== O_constant
)
4801 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4802 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4803 O_constant. We have to be careful not to break compilation for
4804 32-bit X_add_number, though. */
4805 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4807 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4808 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4810 inst
.operands
[i
].regisimm
= 1;
4813 else if (exp_p
->X_op
== O_big
4814 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4816 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4818 /* Bignums have their least significant bits in
4819 generic_bignum[0]. Make sure we put 32 bits in imm and
4820 32 bits in reg, in a (hopefully) portable way. */
4821 gas_assert (parts
!= 0);
4823 /* Make sure that the number is not too big.
4824 PR 11972: Bignums can now be sign-extended to the
4825 size of a .octa so check that the out of range bits
4826 are all zero or all one. */
4827 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4829 LITTLENUM_TYPE m
= -1;
4831 if (generic_bignum
[parts
* 2] != 0
4832 && generic_bignum
[parts
* 2] != m
)
4835 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4836 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4840 inst
.operands
[i
].imm
= 0;
4841 for (j
= 0; j
< parts
; j
++, idx
++)
4842 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4843 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4844 inst
.operands
[i
].reg
= 0;
4845 for (j
= 0; j
< parts
; j
++, idx
++)
4846 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4847 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4848 inst
.operands
[i
].regisimm
= 1;
4850 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4858 /* Returns the pseudo-register number of an FPA immediate constant,
4859 or FAIL if there isn't a valid constant here. */
4862 parse_fpa_immediate (char ** str
)
4864 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4870 /* First try and match exact strings, this is to guarantee
4871 that some formats will work even for cross assembly. */
4873 for (i
= 0; fp_const
[i
]; i
++)
4875 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4879 *str
+= strlen (fp_const
[i
]);
4880 if (is_end_of_line
[(unsigned char) **str
])
4886 /* Just because we didn't get a match doesn't mean that the constant
4887 isn't valid, just that it is in a format that we don't
4888 automatically recognize. Try parsing it with the standard
4889 expression routines. */
4891 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4893 /* Look for a raw floating point number. */
4894 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4895 && is_end_of_line
[(unsigned char) *save_in
])
4897 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4899 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4901 if (words
[j
] != fp_values
[i
][j
])
4905 if (j
== MAX_LITTLENUMS
)
4913 /* Try and parse a more complex expression, this will probably fail
4914 unless the code uses a floating point prefix (eg "0f"). */
4915 save_in
= input_line_pointer
;
4916 input_line_pointer
= *str
;
4917 if (expression (&exp
) == absolute_section
4918 && exp
.X_op
== O_big
4919 && exp
.X_add_number
< 0)
4921 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4923 #define X_PRECISION 5
4924 #define E_PRECISION 15L
4925 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4927 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4929 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4931 if (words
[j
] != fp_values
[i
][j
])
4935 if (j
== MAX_LITTLENUMS
)
4937 *str
= input_line_pointer
;
4938 input_line_pointer
= save_in
;
4945 *str
= input_line_pointer
;
4946 input_line_pointer
= save_in
;
4947 inst
.error
= _("invalid FPA immediate expression");
4951 /* Returns 1 if a number has "quarter-precision" float format
4952 0baBbbbbbc defgh000 00000000 00000000. */
4955 is_quarter_float (unsigned imm
)
4957 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4958 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4962 /* Detect the presence of a floating point or integer zero constant,
4966 parse_ifimm_zero (char **in
)
4970 if (!is_immediate_prefix (**in
))
4972 /* In unified syntax, all prefixes are optional. */
4973 if (!unified_syntax
)
4979 /* Accept #0x0 as a synonym for #0. */
4980 if (strncmp (*in
, "0x", 2) == 0)
4983 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4988 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4989 &generic_floating_point_number
);
4992 && generic_floating_point_number
.sign
== '+'
4993 && (generic_floating_point_number
.low
4994 > generic_floating_point_number
.leader
))
5000 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5001 0baBbbbbbc defgh000 00000000 00000000.
5002 The zero and minus-zero cases need special handling, since they can't be
5003 encoded in the "quarter-precision" float format, but can nonetheless be
5004 loaded as integer constants. */
5007 parse_qfloat_immediate (char **ccp
, int *immed
)
5011 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5012 int found_fpchar
= 0;
5014 skip_past_char (&str
, '#');
5016 /* We must not accidentally parse an integer as a floating-point number. Make
5017 sure that the value we parse is not an integer by checking for special
5018 characters '.' or 'e'.
5019 FIXME: This is a horrible hack, but doing better is tricky because type
5020 information isn't in a very usable state at parse time. */
5022 skip_whitespace (fpnum
);
5024 if (strncmp (fpnum
, "0x", 2) == 0)
5028 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5029 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5039 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5041 unsigned fpword
= 0;
5044 /* Our FP word must be 32 bits (single-precision FP). */
5045 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5047 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5051 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5064 /* Shift operands. */
5067 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5070 struct asm_shift_name
5073 enum shift_kind kind
;
5076 /* Third argument to parse_shift. */
5077 enum parse_shift_mode
5079 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5080 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5081 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5082 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5083 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5086 /* Parse a <shift> specifier on an ARM data processing instruction.
5087 This has three forms:
5089 (LSL|LSR|ASL|ASR|ROR) Rs
5090 (LSL|LSR|ASL|ASR|ROR) #imm
5093 Note that ASL is assimilated to LSL in the instruction encoding, and
5094 RRX to ROR #0 (which cannot be written as such). */
5097 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5099 const struct asm_shift_name
*shift_name
;
5100 enum shift_kind shift
;
5105 for (p
= *str
; ISALPHA (*p
); p
++)
5110 inst
.error
= _("shift expression expected");
5114 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5117 if (shift_name
== NULL
)
5119 inst
.error
= _("shift expression expected");
5123 shift
= shift_name
->kind
;
5127 case NO_SHIFT_RESTRICT
:
5128 case SHIFT_IMMEDIATE
: break;
5130 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5131 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5133 inst
.error
= _("'LSL' or 'ASR' required");
5138 case SHIFT_LSL_IMMEDIATE
:
5139 if (shift
!= SHIFT_LSL
)
5141 inst
.error
= _("'LSL' required");
5146 case SHIFT_ASR_IMMEDIATE
:
5147 if (shift
!= SHIFT_ASR
)
5149 inst
.error
= _("'ASR' required");
5157 if (shift
!= SHIFT_RRX
)
5159 /* Whitespace can appear here if the next thing is a bare digit. */
5160 skip_whitespace (p
);
5162 if (mode
== NO_SHIFT_RESTRICT
5163 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5165 inst
.operands
[i
].imm
= reg
;
5166 inst
.operands
[i
].immisreg
= 1;
5168 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5171 inst
.operands
[i
].shift_kind
= shift
;
5172 inst
.operands
[i
].shifted
= 1;
5177 /* Parse a <shifter_operand> for an ARM data processing instruction:
5180 #<immediate>, <rotate>
5184 where <shift> is defined by parse_shift above, and <rotate> is a
5185 multiple of 2 between 0 and 30. Validation of immediate operands
5186 is deferred to md_apply_fix. */
5189 parse_shifter_operand (char **str
, int i
)
5194 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5196 inst
.operands
[i
].reg
= value
;
5197 inst
.operands
[i
].isreg
= 1;
5199 /* parse_shift will override this if appropriate */
5200 inst
.reloc
.exp
.X_op
= O_constant
;
5201 inst
.reloc
.exp
.X_add_number
= 0;
5203 if (skip_past_comma (str
) == FAIL
)
5206 /* Shift operation on register. */
5207 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5210 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5213 if (skip_past_comma (str
) == SUCCESS
)
5215 /* #x, y -- ie explicit rotation by Y. */
5216 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5219 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5221 inst
.error
= _("constant expression expected");
5225 value
= exp
.X_add_number
;
5226 if (value
< 0 || value
> 30 || value
% 2 != 0)
5228 inst
.error
= _("invalid rotation");
5231 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5233 inst
.error
= _("invalid constant");
5237 /* Encode as specified. */
5238 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5242 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5243 inst
.reloc
.pc_rel
= 0;
5247 /* Group relocation information. Each entry in the table contains the
5248 textual name of the relocation as may appear in assembler source
5249 and must end with a colon.
5250 Along with this textual name are the relocation codes to be used if
5251 the corresponding instruction is an ALU instruction (ADD or SUB only),
5252 an LDR, an LDRS, or an LDC. */
5254 struct group_reloc_table_entry
5265 /* Varieties of non-ALU group relocation. */
5272 static struct group_reloc_table_entry group_reloc_table
[] =
5273 { /* Program counter relative: */
5275 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5280 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5281 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5282 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5283 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5285 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5290 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5291 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5292 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5293 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5295 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5296 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5297 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5298 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5299 /* Section base relative */
5301 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5306 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5307 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5308 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5309 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5311 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5316 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5317 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5318 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5319 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5321 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5322 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5323 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5324 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5325 /* Absolute thumb alu relocations. */
5327 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5332 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5337 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5342 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5347 /* Given the address of a pointer pointing to the textual name of a group
5348 relocation as may appear in assembler source, attempt to find its details
5349 in group_reloc_table. The pointer will be updated to the character after
5350 the trailing colon. On failure, FAIL will be returned; SUCCESS
5351 otherwise. On success, *entry will be updated to point at the relevant
5352 group_reloc_table entry. */
5355 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5358 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5360 int length
= strlen (group_reloc_table
[i
].name
);
5362 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5363 && (*str
)[length
] == ':')
5365 *out
= &group_reloc_table
[i
];
5366 *str
+= (length
+ 1);
5374 /* Parse a <shifter_operand> for an ARM data processing instruction
5375 (as for parse_shifter_operand) where group relocations are allowed:
5378 #<immediate>, <rotate>
5379 #:<group_reloc>:<expression>
5383 where <group_reloc> is one of the strings defined in group_reloc_table.
5384 The hashes are optional.
5386 Everything else is as for parse_shifter_operand. */
5388 static parse_operand_result
5389 parse_shifter_operand_group_reloc (char **str
, int i
)
5391 /* Determine if we have the sequence of characters #: or just :
5392 coming next. If we do, then we check for a group relocation.
5393 If we don't, punt the whole lot to parse_shifter_operand. */
5395 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5396 || (*str
)[0] == ':')
5398 struct group_reloc_table_entry
*entry
;
5400 if ((*str
)[0] == '#')
5405 /* Try to parse a group relocation. Anything else is an error. */
5406 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5408 inst
.error
= _("unknown group relocation");
5409 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5412 /* We now have the group relocation table entry corresponding to
5413 the name in the assembler source. Next, we parse the expression. */
5414 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5415 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5417 /* Record the relocation type (always the ALU variant here). */
5418 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5419 gas_assert (inst
.reloc
.type
!= 0);
5421 return PARSE_OPERAND_SUCCESS
;
5424 return parse_shifter_operand (str
, i
) == SUCCESS
5425 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5427 /* Never reached. */
5430 /* Parse a Neon alignment expression. Information is written to
5431 inst.operands[i]. We assume the initial ':' has been skipped.
5433 align .imm = align << 8, .immisalign=1, .preind=0 */
5434 static parse_operand_result
5435 parse_neon_alignment (char **str
, int i
)
5440 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5442 if (exp
.X_op
!= O_constant
)
5444 inst
.error
= _("alignment must be constant");
5445 return PARSE_OPERAND_FAIL
;
5448 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5449 inst
.operands
[i
].immisalign
= 1;
5450 /* Alignments are not pre-indexes. */
5451 inst
.operands
[i
].preind
= 0;
5454 return PARSE_OPERAND_SUCCESS
;
5457 /* Parse all forms of an ARM address expression. Information is written
5458 to inst.operands[i] and/or inst.reloc.
5460 Preindexed addressing (.preind=1):
5462 [Rn, #offset] .reg=Rn .reloc.exp=offset
5463 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5464 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5465 .shift_kind=shift .reloc.exp=shift_imm
5467 These three may have a trailing ! which causes .writeback to be set also.
5469 Postindexed addressing (.postind=1, .writeback=1):
5471 [Rn], #offset .reg=Rn .reloc.exp=offset
5472 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5473 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5474 .shift_kind=shift .reloc.exp=shift_imm
5476 Unindexed addressing (.preind=0, .postind=0):
5478 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5482 [Rn]{!} shorthand for [Rn,#0]{!}
5483 =immediate .isreg=0 .reloc.exp=immediate
5484 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5486 It is the caller's responsibility to check for addressing modes not
5487 supported by the instruction, and to set inst.reloc.type. */
5489 static parse_operand_result
5490 parse_address_main (char **str
, int i
, int group_relocations
,
5491 group_reloc_type group_type
)
5496 if (skip_past_char (&p
, '[') == FAIL
)
5498 if (skip_past_char (&p
, '=') == FAIL
)
5500 /* Bare address - translate to PC-relative offset. */
5501 inst
.reloc
.pc_rel
= 1;
5502 inst
.operands
[i
].reg
= REG_PC
;
5503 inst
.operands
[i
].isreg
= 1;
5504 inst
.operands
[i
].preind
= 1;
5506 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5507 return PARSE_OPERAND_FAIL
;
5509 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5510 /*allow_symbol_p=*/TRUE
))
5511 return PARSE_OPERAND_FAIL
;
5514 return PARSE_OPERAND_SUCCESS
;
5517 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5518 skip_whitespace (p
);
5520 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5522 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5523 return PARSE_OPERAND_FAIL
;
5525 inst
.operands
[i
].reg
= reg
;
5526 inst
.operands
[i
].isreg
= 1;
5528 if (skip_past_comma (&p
) == SUCCESS
)
5530 inst
.operands
[i
].preind
= 1;
5533 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5535 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5537 inst
.operands
[i
].imm
= reg
;
5538 inst
.operands
[i
].immisreg
= 1;
5540 if (skip_past_comma (&p
) == SUCCESS
)
5541 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5542 return PARSE_OPERAND_FAIL
;
5544 else if (skip_past_char (&p
, ':') == SUCCESS
)
5546 /* FIXME: '@' should be used here, but it's filtered out by generic
5547 code before we get to see it here. This may be subject to
5549 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5551 if (result
!= PARSE_OPERAND_SUCCESS
)
5556 if (inst
.operands
[i
].negative
)
5558 inst
.operands
[i
].negative
= 0;
5562 if (group_relocations
5563 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5565 struct group_reloc_table_entry
*entry
;
5567 /* Skip over the #: or : sequence. */
5573 /* Try to parse a group relocation. Anything else is an
5575 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5577 inst
.error
= _("unknown group relocation");
5578 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5581 /* We now have the group relocation table entry corresponding to
5582 the name in the assembler source. Next, we parse the
5584 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5585 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5587 /* Record the relocation type. */
5591 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5595 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5599 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5606 if (inst
.reloc
.type
== 0)
5608 inst
.error
= _("this group relocation is not allowed on this instruction");
5609 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5615 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5616 return PARSE_OPERAND_FAIL
;
5617 /* If the offset is 0, find out if it's a +0 or -0. */
5618 if (inst
.reloc
.exp
.X_op
== O_constant
5619 && inst
.reloc
.exp
.X_add_number
== 0)
5621 skip_whitespace (q
);
5625 skip_whitespace (q
);
5628 inst
.operands
[i
].negative
= 1;
5633 else if (skip_past_char (&p
, ':') == SUCCESS
)
5635 /* FIXME: '@' should be used here, but it's filtered out by generic code
5636 before we get to see it here. This may be subject to change. */
5637 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5639 if (result
!= PARSE_OPERAND_SUCCESS
)
5643 if (skip_past_char (&p
, ']') == FAIL
)
5645 inst
.error
= _("']' expected");
5646 return PARSE_OPERAND_FAIL
;
5649 if (skip_past_char (&p
, '!') == SUCCESS
)
5650 inst
.operands
[i
].writeback
= 1;
5652 else if (skip_past_comma (&p
) == SUCCESS
)
5654 if (skip_past_char (&p
, '{') == SUCCESS
)
5656 /* [Rn], {expr} - unindexed, with option */
5657 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5658 0, 255, TRUE
) == FAIL
)
5659 return PARSE_OPERAND_FAIL
;
5661 if (skip_past_char (&p
, '}') == FAIL
)
5663 inst
.error
= _("'}' expected at end of 'option' field");
5664 return PARSE_OPERAND_FAIL
;
5666 if (inst
.operands
[i
].preind
)
5668 inst
.error
= _("cannot combine index with option");
5669 return PARSE_OPERAND_FAIL
;
5672 return PARSE_OPERAND_SUCCESS
;
5676 inst
.operands
[i
].postind
= 1;
5677 inst
.operands
[i
].writeback
= 1;
5679 if (inst
.operands
[i
].preind
)
5681 inst
.error
= _("cannot combine pre- and post-indexing");
5682 return PARSE_OPERAND_FAIL
;
5686 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5688 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5690 /* We might be using the immediate for alignment already. If we
5691 are, OR the register number into the low-order bits. */
5692 if (inst
.operands
[i
].immisalign
)
5693 inst
.operands
[i
].imm
|= reg
;
5695 inst
.operands
[i
].imm
= reg
;
5696 inst
.operands
[i
].immisreg
= 1;
5698 if (skip_past_comma (&p
) == SUCCESS
)
5699 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5700 return PARSE_OPERAND_FAIL
;
5705 if (inst
.operands
[i
].negative
)
5707 inst
.operands
[i
].negative
= 0;
5710 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5711 return PARSE_OPERAND_FAIL
;
5712 /* If the offset is 0, find out if it's a +0 or -0. */
5713 if (inst
.reloc
.exp
.X_op
== O_constant
5714 && inst
.reloc
.exp
.X_add_number
== 0)
5716 skip_whitespace (q
);
5720 skip_whitespace (q
);
5723 inst
.operands
[i
].negative
= 1;
5729 /* If at this point neither .preind nor .postind is set, we have a
5730 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5731 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5733 inst
.operands
[i
].preind
= 1;
5734 inst
.reloc
.exp
.X_op
= O_constant
;
5735 inst
.reloc
.exp
.X_add_number
= 0;
5738 return PARSE_OPERAND_SUCCESS
;
5742 parse_address (char **str
, int i
)
5744 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5748 static parse_operand_result
5749 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5751 return parse_address_main (str
, i
, 1, type
);
5754 /* Parse an operand for a MOVW or MOVT instruction. */
5756 parse_half (char **str
)
5761 skip_past_char (&p
, '#');
5762 if (strncasecmp (p
, ":lower16:", 9) == 0)
5763 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5764 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5765 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5767 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5770 skip_whitespace (p
);
5773 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5776 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5778 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5780 inst
.error
= _("constant expression expected");
5783 if (inst
.reloc
.exp
.X_add_number
< 0
5784 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5786 inst
.error
= _("immediate value out of range");
5794 /* Miscellaneous. */
5796 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5797 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5799 parse_psr (char **str
, bfd_boolean lhs
)
5802 unsigned long psr_field
;
5803 const struct asm_psr
*psr
;
5805 bfd_boolean is_apsr
= FALSE
;
5806 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5808 /* PR gas/12698: If the user has specified -march=all then m_profile will
5809 be TRUE, but we want to ignore it in this case as we are building for any
5810 CPU type, including non-m variants. */
5811 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5814 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5815 feature for ease of use and backwards compatibility. */
5817 if (strncasecmp (p
, "SPSR", 4) == 0)
5820 goto unsupported_psr
;
5822 psr_field
= SPSR_BIT
;
5824 else if (strncasecmp (p
, "CPSR", 4) == 0)
5827 goto unsupported_psr
;
5831 else if (strncasecmp (p
, "APSR", 4) == 0)
5833 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5834 and ARMv7-R architecture CPUs. */
5843 while (ISALNUM (*p
) || *p
== '_');
5845 if (strncasecmp (start
, "iapsr", 5) == 0
5846 || strncasecmp (start
, "eapsr", 5) == 0
5847 || strncasecmp (start
, "xpsr", 4) == 0
5848 || strncasecmp (start
, "psr", 3) == 0)
5849 p
= start
+ strcspn (start
, "rR") + 1;
5851 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5857 /* If APSR is being written, a bitfield may be specified. Note that
5858 APSR itself is handled above. */
5859 if (psr
->field
<= 3)
5861 psr_field
= psr
->field
;
5867 /* M-profile MSR instructions have the mask field set to "10", except
5868 *PSR variants which modify APSR, which may use a different mask (and
5869 have been handled already). Do that by setting the PSR_f field
5871 return psr
->field
| (lhs
? PSR_f
: 0);
5874 goto unsupported_psr
;
5880 /* A suffix follows. */
5886 while (ISALNUM (*p
) || *p
== '_');
5890 /* APSR uses a notation for bits, rather than fields. */
5891 unsigned int nzcvq_bits
= 0;
5892 unsigned int g_bit
= 0;
5895 for (bit
= start
; bit
!= p
; bit
++)
5897 switch (TOLOWER (*bit
))
5900 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5904 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5908 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5912 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5916 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5920 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5924 inst
.error
= _("unexpected bit specified after APSR");
5929 if (nzcvq_bits
== 0x1f)
5934 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5936 inst
.error
= _("selected processor does not "
5937 "support DSP extension");
5944 if ((nzcvq_bits
& 0x20) != 0
5945 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5946 || (g_bit
& 0x2) != 0)
5948 inst
.error
= _("bad bitmask specified after APSR");
5954 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5959 psr_field
|= psr
->field
;
5965 goto error
; /* Garbage after "[CS]PSR". */
5967 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5968 is deprecated, but allow it anyway. */
5972 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5975 else if (!m_profile
)
5976 /* These bits are never right for M-profile devices: don't set them
5977 (only code paths which read/write APSR reach here). */
5978 psr_field
|= (PSR_c
| PSR_f
);
5984 inst
.error
= _("selected processor does not support requested special "
5985 "purpose register");
5989 inst
.error
= _("flag for {c}psr instruction expected");
5993 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5994 value suitable for splatting into the AIF field of the instruction. */
5997 parse_cps_flags (char **str
)
6006 case '\0': case ',':
6009 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6010 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6011 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6014 inst
.error
= _("unrecognized CPS flag");
6019 if (saw_a_flag
== 0)
6021 inst
.error
= _("missing CPS flags");
6029 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6030 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6033 parse_endian_specifier (char **str
)
6038 if (strncasecmp (s
, "BE", 2))
6040 else if (strncasecmp (s
, "LE", 2))
6044 inst
.error
= _("valid endian specifiers are be or le");
6048 if (ISALNUM (s
[2]) || s
[2] == '_')
6050 inst
.error
= _("valid endian specifiers are be or le");
6055 return little_endian
;
6058 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6059 value suitable for poking into the rotate field of an sxt or sxta
6060 instruction, or FAIL on error. */
6063 parse_ror (char **str
)
6068 if (strncasecmp (s
, "ROR", 3) == 0)
6072 inst
.error
= _("missing rotation field after comma");
6076 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6081 case 0: *str
= s
; return 0x0;
6082 case 8: *str
= s
; return 0x1;
6083 case 16: *str
= s
; return 0x2;
6084 case 24: *str
= s
; return 0x3;
6087 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6092 /* Parse a conditional code (from conds[] below). The value returned is in the
6093 range 0 .. 14, or FAIL. */
6095 parse_cond (char **str
)
6098 const struct asm_cond
*c
;
6100 /* Condition codes are always 2 characters, so matching up to
6101 3 characters is sufficient. */
6106 while (ISALPHA (*q
) && n
< 3)
6108 cond
[n
] = TOLOWER (*q
);
6113 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6116 inst
.error
= _("condition required");
6124 /* Record a use of the given feature. */
6126 record_feature_use (const arm_feature_set
*feature
)
6129 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6131 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6134 /* If the given feature available in the selected CPU, mark it as used.
6135 Returns TRUE iff feature is available. */
6137 mark_feature_used (const arm_feature_set
*feature
)
6139 /* Ensure the option is valid on the current architecture. */
6140 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6143 /* Add the appropriate architecture feature for the barrier option used.
6145 record_feature_use (feature
);
6150 /* Parse an option for a barrier instruction. Returns the encoding for the
6153 parse_barrier (char **str
)
6156 const struct asm_barrier_opt
*o
;
6159 while (ISALPHA (*q
))
6162 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6167 if (!mark_feature_used (&o
->arch
))
6174 /* Parse the operands of a table branch instruction. Similar to a memory
6177 parse_tb (char **str
)
6182 if (skip_past_char (&p
, '[') == FAIL
)
6184 inst
.error
= _("'[' expected");
6188 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6190 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6193 inst
.operands
[0].reg
= reg
;
6195 if (skip_past_comma (&p
) == FAIL
)
6197 inst
.error
= _("',' expected");
6201 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6203 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6206 inst
.operands
[0].imm
= reg
;
6208 if (skip_past_comma (&p
) == SUCCESS
)
6210 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6212 if (inst
.reloc
.exp
.X_add_number
!= 1)
6214 inst
.error
= _("invalid shift");
6217 inst
.operands
[0].shifted
= 1;
6220 if (skip_past_char (&p
, ']') == FAIL
)
6222 inst
.error
= _("']' expected");
6229 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6230 information on the types the operands can take and how they are encoded.
6231 Up to four operands may be read; this function handles setting the
6232 ".present" field for each read operand itself.
6233 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6234 else returns FAIL. */
6237 parse_neon_mov (char **str
, int *which_operand
)
6239 int i
= *which_operand
, val
;
6240 enum arm_reg_type rtype
;
6242 struct neon_type_el optype
;
6244 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6246 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6247 inst
.operands
[i
].reg
= val
;
6248 inst
.operands
[i
].isscalar
= 1;
6249 inst
.operands
[i
].vectype
= optype
;
6250 inst
.operands
[i
++].present
= 1;
6252 if (skip_past_comma (&ptr
) == FAIL
)
6255 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6258 inst
.operands
[i
].reg
= val
;
6259 inst
.operands
[i
].isreg
= 1;
6260 inst
.operands
[i
].present
= 1;
6262 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6265 /* Cases 0, 1, 2, 3, 5 (D only). */
6266 if (skip_past_comma (&ptr
) == FAIL
)
6269 inst
.operands
[i
].reg
= val
;
6270 inst
.operands
[i
].isreg
= 1;
6271 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6272 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6273 inst
.operands
[i
].isvec
= 1;
6274 inst
.operands
[i
].vectype
= optype
;
6275 inst
.operands
[i
++].present
= 1;
6277 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6279 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6280 Case 13: VMOV <Sd>, <Rm> */
6281 inst
.operands
[i
].reg
= val
;
6282 inst
.operands
[i
].isreg
= 1;
6283 inst
.operands
[i
].present
= 1;
6285 if (rtype
== REG_TYPE_NQ
)
6287 first_error (_("can't use Neon quad register here"));
6290 else if (rtype
!= REG_TYPE_VFS
)
6293 if (skip_past_comma (&ptr
) == FAIL
)
6295 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6297 inst
.operands
[i
].reg
= val
;
6298 inst
.operands
[i
].isreg
= 1;
6299 inst
.operands
[i
].present
= 1;
6302 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6305 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6306 Case 1: VMOV<c><q> <Dd>, <Dm>
6307 Case 8: VMOV.F32 <Sd>, <Sm>
6308 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6310 inst
.operands
[i
].reg
= val
;
6311 inst
.operands
[i
].isreg
= 1;
6312 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6313 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6314 inst
.operands
[i
].isvec
= 1;
6315 inst
.operands
[i
].vectype
= optype
;
6316 inst
.operands
[i
].present
= 1;
6318 if (skip_past_comma (&ptr
) == SUCCESS
)
6323 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
++].present
= 1;
6330 if (skip_past_comma (&ptr
) == FAIL
)
6333 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isreg
= 1;
6338 inst
.operands
[i
].present
= 1;
6341 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6342 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6343 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6344 Case 10: VMOV.F32 <Sd>, #<imm>
6345 Case 11: VMOV.F64 <Dd>, #<imm> */
6346 inst
.operands
[i
].immisfloat
= 1;
6347 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6349 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6350 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6354 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6358 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6361 inst
.operands
[i
].reg
= val
;
6362 inst
.operands
[i
].isreg
= 1;
6363 inst
.operands
[i
++].present
= 1;
6365 if (skip_past_comma (&ptr
) == FAIL
)
6368 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6370 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6371 inst
.operands
[i
].reg
= val
;
6372 inst
.operands
[i
].isscalar
= 1;
6373 inst
.operands
[i
].present
= 1;
6374 inst
.operands
[i
].vectype
= optype
;
6376 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6378 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6379 inst
.operands
[i
].reg
= val
;
6380 inst
.operands
[i
].isreg
= 1;
6381 inst
.operands
[i
++].present
= 1;
6383 if (skip_past_comma (&ptr
) == FAIL
)
6386 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6389 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6393 inst
.operands
[i
].reg
= val
;
6394 inst
.operands
[i
].isreg
= 1;
6395 inst
.operands
[i
].isvec
= 1;
6396 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6397 inst
.operands
[i
].vectype
= optype
;
6398 inst
.operands
[i
].present
= 1;
6400 if (rtype
== REG_TYPE_VFS
)
6404 if (skip_past_comma (&ptr
) == FAIL
)
6406 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6409 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6412 inst
.operands
[i
].reg
= val
;
6413 inst
.operands
[i
].isreg
= 1;
6414 inst
.operands
[i
].isvec
= 1;
6415 inst
.operands
[i
].issingle
= 1;
6416 inst
.operands
[i
].vectype
= optype
;
6417 inst
.operands
[i
].present
= 1;
6420 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6424 inst
.operands
[i
].reg
= val
;
6425 inst
.operands
[i
].isreg
= 1;
6426 inst
.operands
[i
].isvec
= 1;
6427 inst
.operands
[i
].issingle
= 1;
6428 inst
.operands
[i
].vectype
= optype
;
6429 inst
.operands
[i
].present
= 1;
6434 first_error (_("parse error"));
6438 /* Successfully parsed the operands. Update args. */
6444 first_error (_("expected comma"));
6448 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6452 /* Use this macro when the operand constraints are different
6453 for ARM and THUMB (e.g. ldrd). */
6454 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6455 ((arm_operand) | ((thumb_operand) << 16))
6457 /* Matcher codes for parse_operands. */
6458 enum operand_parse_code
6460 OP_stop
, /* end of line */
6462 OP_RR
, /* ARM register */
6463 OP_RRnpc
, /* ARM register, not r15 */
6464 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6465 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6466 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6467 optional trailing ! */
6468 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6469 OP_RCP
, /* Coprocessor number */
6470 OP_RCN
, /* Coprocessor register */
6471 OP_RF
, /* FPA register */
6472 OP_RVS
, /* VFP single precision register */
6473 OP_RVD
, /* VFP double precision register (0..15) */
6474 OP_RND
, /* Neon double precision register (0..31) */
6475 OP_RNQ
, /* Neon quad precision register */
6476 OP_RVSD
, /* VFP single or double precision register */
6477 OP_RNDQ
, /* Neon double or quad precision register */
6478 OP_RNSDQ
, /* Neon single, double or quad precision register */
6479 OP_RNSC
, /* Neon scalar D[X] */
6480 OP_RVC
, /* VFP control register */
6481 OP_RMF
, /* Maverick F register */
6482 OP_RMD
, /* Maverick D register */
6483 OP_RMFX
, /* Maverick FX register */
6484 OP_RMDX
, /* Maverick DX register */
6485 OP_RMAX
, /* Maverick AX register */
6486 OP_RMDS
, /* Maverick DSPSC register */
6487 OP_RIWR
, /* iWMMXt wR register */
6488 OP_RIWC
, /* iWMMXt wC register */
6489 OP_RIWG
, /* iWMMXt wCG register */
6490 OP_RXA
, /* XScale accumulator register */
6492 OP_REGLST
, /* ARM register list */
6493 OP_VRSLST
, /* VFP single-precision register list */
6494 OP_VRDLST
, /* VFP double-precision register list */
6495 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6496 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6497 OP_NSTRLST
, /* Neon element/structure list */
6499 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6500 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6501 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6502 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6503 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6504 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6505 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6506 OP_VMOV
, /* Neon VMOV operands. */
6507 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6508 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6509 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6511 OP_I0
, /* immediate zero */
6512 OP_I7
, /* immediate value 0 .. 7 */
6513 OP_I15
, /* 0 .. 15 */
6514 OP_I16
, /* 1 .. 16 */
6515 OP_I16z
, /* 0 .. 16 */
6516 OP_I31
, /* 0 .. 31 */
6517 OP_I31w
, /* 0 .. 31, optional trailing ! */
6518 OP_I32
, /* 1 .. 32 */
6519 OP_I32z
, /* 0 .. 32 */
6520 OP_I63
, /* 0 .. 63 */
6521 OP_I63s
, /* -64 .. 63 */
6522 OP_I64
, /* 1 .. 64 */
6523 OP_I64z
, /* 0 .. 64 */
6524 OP_I255
, /* 0 .. 255 */
6526 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6527 OP_I7b
, /* 0 .. 7 */
6528 OP_I15b
, /* 0 .. 15 */
6529 OP_I31b
, /* 0 .. 31 */
6531 OP_SH
, /* shifter operand */
6532 OP_SHG
, /* shifter operand with possible group relocation */
6533 OP_ADDR
, /* Memory address expression (any mode) */
6534 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6535 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6536 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6537 OP_EXP
, /* arbitrary expression */
6538 OP_EXPi
, /* same, with optional immediate prefix */
6539 OP_EXPr
, /* same, with optional relocation suffix */
6540 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6541 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6542 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6544 OP_CPSF
, /* CPS flags */
6545 OP_ENDI
, /* Endianness specifier */
6546 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6547 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6548 OP_COND
, /* conditional code */
6549 OP_TB
, /* Table branch. */
6551 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6553 OP_RRnpc_I0
, /* ARM register or literal 0 */
6554 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6555 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6556 OP_RF_IF
, /* FPA register or immediate */
6557 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6558 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6560 /* Optional operands. */
6561 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6562 OP_oI31b
, /* 0 .. 31 */
6563 OP_oI32b
, /* 1 .. 32 */
6564 OP_oI32z
, /* 0 .. 32 */
6565 OP_oIffffb
, /* 0 .. 65535 */
6566 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6568 OP_oRR
, /* ARM register */
6569 OP_oRRnpc
, /* ARM register, not the PC */
6570 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6571 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6572 OP_oRND
, /* Optional Neon double precision register */
6573 OP_oRNQ
, /* Optional Neon quad precision register */
6574 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6575 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6576 OP_oSHll
, /* LSL immediate */
6577 OP_oSHar
, /* ASR immediate */
6578 OP_oSHllar
, /* LSL or ASR immediate */
6579 OP_oROR
, /* ROR 0/8/16/24 */
6580 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6582 /* Some pre-defined mixed (ARM/THUMB) operands. */
6583 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6584 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6585 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6587 OP_FIRST_OPTIONAL
= OP_oI7b
6590 /* Generic instruction operand parser. This does no encoding and no
6591 semantic validation; it merely squirrels values away in the inst
6592 structure. Returns SUCCESS or FAIL depending on whether the
6593 specified grammar matched. */
6595 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6597 unsigned const int *upat
= pattern
;
6598 char *backtrack_pos
= 0;
6599 const char *backtrack_error
= 0;
6600 int i
, val
= 0, backtrack_index
= 0;
6601 enum arm_reg_type rtype
;
6602 parse_operand_result result
;
6603 unsigned int op_parse_code
;
6605 #define po_char_or_fail(chr) \
6608 if (skip_past_char (&str, chr) == FAIL) \
6613 #define po_reg_or_fail(regtype) \
6616 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6617 & inst.operands[i].vectype); \
6620 first_error (_(reg_expected_msgs[regtype])); \
6623 inst.operands[i].reg = val; \
6624 inst.operands[i].isreg = 1; \
6625 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6626 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6627 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6628 || rtype == REG_TYPE_VFD \
6629 || rtype == REG_TYPE_NQ); \
6633 #define po_reg_or_goto(regtype, label) \
6636 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6637 & inst.operands[i].vectype); \
6641 inst.operands[i].reg = val; \
6642 inst.operands[i].isreg = 1; \
6643 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6644 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6645 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6646 || rtype == REG_TYPE_VFD \
6647 || rtype == REG_TYPE_NQ); \
6651 #define po_imm_or_fail(min, max, popt) \
6654 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6656 inst.operands[i].imm = val; \
6660 #define po_scalar_or_goto(elsz, label) \
6663 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6666 inst.operands[i].reg = val; \
6667 inst.operands[i].isscalar = 1; \
6671 #define po_misc_or_fail(expr) \
6679 #define po_misc_or_fail_no_backtrack(expr) \
6683 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6684 backtrack_pos = 0; \
6685 if (result != PARSE_OPERAND_SUCCESS) \
6690 #define po_barrier_or_imm(str) \
6693 val = parse_barrier (&str); \
6694 if (val == FAIL && ! ISALPHA (*str)) \
6697 /* ISB can only take SY as an option. */ \
6698 || ((inst.instruction & 0xf0) == 0x60 \
6701 inst.error = _("invalid barrier type"); \
6702 backtrack_pos = 0; \
6708 skip_whitespace (str
);
6710 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6712 op_parse_code
= upat
[i
];
6713 if (op_parse_code
>= 1<<16)
6714 op_parse_code
= thumb
? (op_parse_code
>> 16)
6715 : (op_parse_code
& ((1<<16)-1));
6717 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6719 /* Remember where we are in case we need to backtrack. */
6720 gas_assert (!backtrack_pos
);
6721 backtrack_pos
= str
;
6722 backtrack_error
= inst
.error
;
6723 backtrack_index
= i
;
6726 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6727 po_char_or_fail (',');
6729 switch (op_parse_code
)
6737 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6738 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6739 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6740 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6741 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6742 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6744 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6746 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6748 /* Also accept generic coprocessor regs for unknown registers. */
6750 po_reg_or_fail (REG_TYPE_CN
);
6752 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6753 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6754 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6755 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6756 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6757 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6758 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6759 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6760 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6761 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6763 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6765 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6766 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6768 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6770 /* Neon scalar. Using an element size of 8 means that some invalid
6771 scalars are accepted here, so deal with those in later code. */
6772 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6776 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6779 po_imm_or_fail (0, 0, TRUE
);
6784 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6789 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6792 if (parse_ifimm_zero (&str
))
6793 inst
.operands
[i
].imm
= 0;
6797 = _("only floating point zero is allowed as immediate value");
6805 po_scalar_or_goto (8, try_rr
);
6808 po_reg_or_fail (REG_TYPE_RN
);
6814 po_scalar_or_goto (8, try_nsdq
);
6817 po_reg_or_fail (REG_TYPE_NSDQ
);
6823 po_scalar_or_goto (8, try_ndq
);
6826 po_reg_or_fail (REG_TYPE_NDQ
);
6832 po_scalar_or_goto (8, try_vfd
);
6835 po_reg_or_fail (REG_TYPE_VFD
);
6840 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6841 not careful then bad things might happen. */
6842 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6847 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6850 /* There's a possibility of getting a 64-bit immediate here, so
6851 we need special handling. */
6852 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6855 inst
.error
= _("immediate value is out of range");
6863 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6866 po_imm_or_fail (0, 63, TRUE
);
6871 po_char_or_fail ('[');
6872 po_reg_or_fail (REG_TYPE_RN
);
6873 po_char_or_fail (']');
6879 po_reg_or_fail (REG_TYPE_RN
);
6880 if (skip_past_char (&str
, '!') == SUCCESS
)
6881 inst
.operands
[i
].writeback
= 1;
6885 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6886 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6887 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6888 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6889 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6890 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6891 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6892 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6893 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6894 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6895 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6896 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6898 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6900 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6901 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6903 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6904 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6905 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6906 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6908 /* Immediate variants */
6910 po_char_or_fail ('{');
6911 po_imm_or_fail (0, 255, TRUE
);
6912 po_char_or_fail ('}');
6916 /* The expression parser chokes on a trailing !, so we have
6917 to find it first and zap it. */
6920 while (*s
&& *s
!= ',')
6925 inst
.operands
[i
].writeback
= 1;
6927 po_imm_or_fail (0, 31, TRUE
);
6935 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6940 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6945 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6947 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6949 val
= parse_reloc (&str
);
6952 inst
.error
= _("unrecognized relocation suffix");
6955 else if (val
!= BFD_RELOC_UNUSED
)
6957 inst
.operands
[i
].imm
= val
;
6958 inst
.operands
[i
].hasreloc
= 1;
6963 /* Operand for MOVW or MOVT. */
6965 po_misc_or_fail (parse_half (&str
));
6968 /* Register or expression. */
6969 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6970 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6972 /* Register or immediate. */
6973 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6974 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6976 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6978 if (!is_immediate_prefix (*str
))
6981 val
= parse_fpa_immediate (&str
);
6984 /* FPA immediates are encoded as registers 8-15.
6985 parse_fpa_immediate has already applied the offset. */
6986 inst
.operands
[i
].reg
= val
;
6987 inst
.operands
[i
].isreg
= 1;
6990 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6991 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6993 /* Two kinds of register. */
6996 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6998 || (rege
->type
!= REG_TYPE_MMXWR
6999 && rege
->type
!= REG_TYPE_MMXWC
7000 && rege
->type
!= REG_TYPE_MMXWCG
))
7002 inst
.error
= _("iWMMXt data or control register expected");
7005 inst
.operands
[i
].reg
= rege
->number
;
7006 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7012 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7014 || (rege
->type
!= REG_TYPE_MMXWC
7015 && rege
->type
!= REG_TYPE_MMXWCG
))
7017 inst
.error
= _("iWMMXt control register expected");
7020 inst
.operands
[i
].reg
= rege
->number
;
7021 inst
.operands
[i
].isreg
= 1;
7026 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7027 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7028 case OP_oROR
: val
= parse_ror (&str
); break;
7029 case OP_COND
: val
= parse_cond (&str
); break;
7030 case OP_oBARRIER_I15
:
7031 po_barrier_or_imm (str
); break;
7033 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7039 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7040 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7042 inst
.error
= _("Banked registers are not available with this "
7048 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7052 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7055 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7057 if (strncasecmp (str
, "APSR_", 5) == 0)
7064 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7065 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7066 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7067 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7068 default: found
= 16;
7072 inst
.operands
[i
].isvec
= 1;
7073 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7074 inst
.operands
[i
].reg
= REG_PC
;
7081 po_misc_or_fail (parse_tb (&str
));
7084 /* Register lists. */
7086 val
= parse_reg_list (&str
);
7089 inst
.operands
[i
].writeback
= 1;
7095 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7099 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7103 /* Allow Q registers too. */
7104 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7109 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7111 inst
.operands
[i
].issingle
= 1;
7116 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7121 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7122 &inst
.operands
[i
].vectype
);
7125 /* Addressing modes */
7127 po_misc_or_fail (parse_address (&str
, i
));
7131 po_misc_or_fail_no_backtrack (
7132 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7136 po_misc_or_fail_no_backtrack (
7137 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7141 po_misc_or_fail_no_backtrack (
7142 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7146 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7150 po_misc_or_fail_no_backtrack (
7151 parse_shifter_operand_group_reloc (&str
, i
));
7155 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7159 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7163 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7167 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7170 /* Various value-based sanity checks and shared operations. We
7171 do not signal immediate failures for the register constraints;
7172 this allows a syntax error to take precedence. */
7173 switch (op_parse_code
)
7181 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7182 inst
.error
= BAD_PC
;
7187 if (inst
.operands
[i
].isreg
)
7189 if (inst
.operands
[i
].reg
== REG_PC
)
7190 inst
.error
= BAD_PC
;
7191 else if (inst
.operands
[i
].reg
== REG_SP
7192 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7193 relaxed since ARMv8-A. */
7194 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7197 inst
.error
= BAD_SP
;
7203 if (inst
.operands
[i
].isreg
7204 && inst
.operands
[i
].reg
== REG_PC
7205 && (inst
.operands
[i
].writeback
|| thumb
))
7206 inst
.error
= BAD_PC
;
7215 case OP_oBARRIER_I15
:
7224 inst
.operands
[i
].imm
= val
;
7231 /* If we get here, this operand was successfully parsed. */
7232 inst
.operands
[i
].present
= 1;
7236 inst
.error
= BAD_ARGS
;
7241 /* The parse routine should already have set inst.error, but set a
7242 default here just in case. */
7244 inst
.error
= _("syntax error");
7248 /* Do not backtrack over a trailing optional argument that
7249 absorbed some text. We will only fail again, with the
7250 'garbage following instruction' error message, which is
7251 probably less helpful than the current one. */
7252 if (backtrack_index
== i
&& backtrack_pos
!= str
7253 && upat
[i
+1] == OP_stop
)
7256 inst
.error
= _("syntax error");
7260 /* Try again, skipping the optional argument at backtrack_pos. */
7261 str
= backtrack_pos
;
7262 inst
.error
= backtrack_error
;
7263 inst
.operands
[backtrack_index
].present
= 0;
7264 i
= backtrack_index
;
7268 /* Check that we have parsed all the arguments. */
7269 if (*str
!= '\0' && !inst
.error
)
7270 inst
.error
= _("garbage following instruction");
7272 return inst
.error
? FAIL
: SUCCESS
;
7275 #undef po_char_or_fail
7276 #undef po_reg_or_fail
7277 #undef po_reg_or_goto
7278 #undef po_imm_or_fail
7279 #undef po_scalar_or_fail
7280 #undef po_barrier_or_imm
7282 /* Shorthand macro for instruction encoding functions issuing errors. */
7283 #define constraint(expr, err) \
7294 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7295 instructions are unpredictable if these registers are used. This
7296 is the BadReg predicate in ARM's Thumb-2 documentation.
7298 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7299 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7300 #define reject_bad_reg(reg) \
7302 if (reg == REG_PC) \
7304 inst.error = BAD_PC; \
7307 else if (reg == REG_SP \
7308 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7310 inst.error = BAD_SP; \
7315 /* If REG is R13 (the stack pointer), warn that its use is
7317 #define warn_deprecated_sp(reg) \
7319 if (warn_on_deprecated && reg == REG_SP) \
7320 as_tsktsk (_("use of r13 is deprecated")); \
7323 /* Functions for operand encoding. ARM, then Thumb. */
7325 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7327 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7329 The only binary encoding difference is the Coprocessor number. Coprocessor
7330 9 is used for half-precision calculations or conversions. The format of the
7331 instruction is the same as the equivalent Coprocessor 10 instruction that
7332 exists for Single-Precision operation. */
7335 do_scalar_fp16_v82_encode (void)
7337 if (inst
.cond
!= COND_ALWAYS
)
7338 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7339 " the behaviour is UNPREDICTABLE"));
7340 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7343 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7344 mark_feature_used (&arm_ext_fp16
);
7347 /* If VAL can be encoded in the immediate field of an ARM instruction,
7348 return the encoded form. Otherwise, return FAIL. */
7351 encode_arm_immediate (unsigned int val
)
7358 for (i
= 2; i
< 32; i
+= 2)
7359 if ((a
= rotate_left (val
, i
)) <= 0xff)
7360 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7365 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7366 return the encoded form. Otherwise, return FAIL. */
7368 encode_thumb32_immediate (unsigned int val
)
7375 for (i
= 1; i
<= 24; i
++)
7378 if ((val
& ~(0xff << i
)) == 0)
7379 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7383 if (val
== ((a
<< 16) | a
))
7385 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7389 if (val
== ((a
<< 16) | a
))
7390 return 0x200 | (a
>> 8);
7394 /* Encode a VFP SP or DP register number into inst.instruction. */
7397 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7399 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7402 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7405 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7408 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7413 first_error (_("D register out of range for selected VFP version"));
7421 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7425 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7429 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7433 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7437 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7441 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7449 /* Encode a <shift> in an ARM-format instruction. The immediate,
7450 if any, is handled by md_apply_fix. */
7452 encode_arm_shift (int i
)
7454 /* register-shifted register. */
7455 if (inst
.operands
[i
].immisreg
)
7458 for (op_index
= 0; op_index
<= i
; ++op_index
)
7460 /* Check the operand only when it's presented. In pre-UAL syntax,
7461 if the destination register is the same as the first operand, two
7462 register form of the instruction can be used. */
7463 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7464 && inst
.operands
[op_index
].reg
== REG_PC
)
7465 as_warn (UNPRED_REG ("r15"));
7468 if (inst
.operands
[i
].imm
== REG_PC
)
7469 as_warn (UNPRED_REG ("r15"));
7472 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7473 inst
.instruction
|= SHIFT_ROR
<< 5;
7476 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7477 if (inst
.operands
[i
].immisreg
)
7479 inst
.instruction
|= SHIFT_BY_REG
;
7480 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7483 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7488 encode_arm_shifter_operand (int i
)
7490 if (inst
.operands
[i
].isreg
)
7492 inst
.instruction
|= inst
.operands
[i
].reg
;
7493 encode_arm_shift (i
);
7497 inst
.instruction
|= INST_IMMEDIATE
;
7498 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7499 inst
.instruction
|= inst
.operands
[i
].imm
;
7503 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7505 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7508 Generate an error if the operand is not a register. */
7509 constraint (!inst
.operands
[i
].isreg
,
7510 _("Instruction does not support =N addresses"));
7512 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7514 if (inst
.operands
[i
].preind
)
7518 inst
.error
= _("instruction does not accept preindexed addressing");
7521 inst
.instruction
|= PRE_INDEX
;
7522 if (inst
.operands
[i
].writeback
)
7523 inst
.instruction
|= WRITE_BACK
;
7526 else if (inst
.operands
[i
].postind
)
7528 gas_assert (inst
.operands
[i
].writeback
);
7530 inst
.instruction
|= WRITE_BACK
;
7532 else /* unindexed - only for coprocessor */
7534 inst
.error
= _("instruction does not accept unindexed addressing");
7538 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7539 && (((inst
.instruction
& 0x000f0000) >> 16)
7540 == ((inst
.instruction
& 0x0000f000) >> 12)))
7541 as_warn ((inst
.instruction
& LOAD_BIT
)
7542 ? _("destination register same as write-back base")
7543 : _("source register same as write-back base"));
7546 /* inst.operands[i] was set up by parse_address. Encode it into an
7547 ARM-format mode 2 load or store instruction. If is_t is true,
7548 reject forms that cannot be used with a T instruction (i.e. not
7551 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7553 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7555 encode_arm_addr_mode_common (i
, is_t
);
7557 if (inst
.operands
[i
].immisreg
)
7559 constraint ((inst
.operands
[i
].imm
== REG_PC
7560 || (is_pc
&& inst
.operands
[i
].writeback
)),
7562 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7563 inst
.instruction
|= inst
.operands
[i
].imm
;
7564 if (!inst
.operands
[i
].negative
)
7565 inst
.instruction
|= INDEX_UP
;
7566 if (inst
.operands
[i
].shifted
)
7568 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7569 inst
.instruction
|= SHIFT_ROR
<< 5;
7572 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7573 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7577 else /* immediate offset in inst.reloc */
7579 if (is_pc
&& !inst
.reloc
.pc_rel
)
7581 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7583 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7584 cannot use PC in addressing.
7585 PC cannot be used in writeback addressing, either. */
7586 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7589 /* Use of PC in str is deprecated for ARMv7. */
7590 if (warn_on_deprecated
7592 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7593 as_tsktsk (_("use of PC in this instruction is deprecated"));
7596 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7598 /* Prefer + for zero encoded value. */
7599 if (!inst
.operands
[i
].negative
)
7600 inst
.instruction
|= INDEX_UP
;
7601 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7606 /* inst.operands[i] was set up by parse_address. Encode it into an
7607 ARM-format mode 3 load or store instruction. Reject forms that
7608 cannot be used with such instructions. If is_t is true, reject
7609 forms that cannot be used with a T instruction (i.e. not
7612 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7614 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7616 inst
.error
= _("instruction does not accept scaled register index");
7620 encode_arm_addr_mode_common (i
, is_t
);
7622 if (inst
.operands
[i
].immisreg
)
7624 constraint ((inst
.operands
[i
].imm
== REG_PC
7625 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7627 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7629 inst
.instruction
|= inst
.operands
[i
].imm
;
7630 if (!inst
.operands
[i
].negative
)
7631 inst
.instruction
|= INDEX_UP
;
7633 else /* immediate offset in inst.reloc */
7635 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7636 && inst
.operands
[i
].writeback
),
7638 inst
.instruction
|= HWOFFSET_IMM
;
7639 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7641 /* Prefer + for zero encoded value. */
7642 if (!inst
.operands
[i
].negative
)
7643 inst
.instruction
|= INDEX_UP
;
7645 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7650 /* Write immediate bits [7:0] to the following locations:
7652 |28/24|23 19|18 16|15 4|3 0|
7653 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7655 This function is used by VMOV/VMVN/VORR/VBIC. */
7658 neon_write_immbits (unsigned immbits
)
7660 inst
.instruction
|= immbits
& 0xf;
7661 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7662 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7665 /* Invert low-order SIZE bits of XHI:XLO. */
7668 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7670 unsigned immlo
= xlo
? *xlo
: 0;
7671 unsigned immhi
= xhi
? *xhi
: 0;
7676 immlo
= (~immlo
) & 0xff;
7680 immlo
= (~immlo
) & 0xffff;
7684 immhi
= (~immhi
) & 0xffffffff;
7688 immlo
= (~immlo
) & 0xffffffff;
7702 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7706 neon_bits_same_in_bytes (unsigned imm
)
7708 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7709 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7710 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7711 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7714 /* For immediate of above form, return 0bABCD. */
7717 neon_squash_bits (unsigned imm
)
7719 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7720 | ((imm
& 0x01000000) >> 21);
7723 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7726 neon_qfloat_bits (unsigned imm
)
7728 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7731 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7732 the instruction. *OP is passed as the initial value of the op field, and
7733 may be set to a different value depending on the constant (i.e.
7734 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7735 MVN). If the immediate looks like a repeated pattern then also
7736 try smaller element sizes. */
7739 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7740 unsigned *immbits
, int *op
, int size
,
7741 enum neon_el_type type
)
7743 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7745 if (type
== NT_float
&& !float_p
)
7748 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7750 if (size
!= 32 || *op
== 1)
7752 *immbits
= neon_qfloat_bits (immlo
);
7758 if (neon_bits_same_in_bytes (immhi
)
7759 && neon_bits_same_in_bytes (immlo
))
7763 *immbits
= (neon_squash_bits (immhi
) << 4)
7764 | neon_squash_bits (immlo
);
7775 if (immlo
== (immlo
& 0x000000ff))
7780 else if (immlo
== (immlo
& 0x0000ff00))
7782 *immbits
= immlo
>> 8;
7785 else if (immlo
== (immlo
& 0x00ff0000))
7787 *immbits
= immlo
>> 16;
7790 else if (immlo
== (immlo
& 0xff000000))
7792 *immbits
= immlo
>> 24;
7795 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7797 *immbits
= (immlo
>> 8) & 0xff;
7800 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7802 *immbits
= (immlo
>> 16) & 0xff;
7806 if ((immlo
& 0xffff) != (immlo
>> 16))
7813 if (immlo
== (immlo
& 0x000000ff))
7818 else if (immlo
== (immlo
& 0x0000ff00))
7820 *immbits
= immlo
>> 8;
7824 if ((immlo
& 0xff) != (immlo
>> 8))
7829 if (immlo
== (immlo
& 0x000000ff))
7831 /* Don't allow MVN with 8-bit immediate. */
7841 #if defined BFD_HOST_64_BIT
7842 /* Returns TRUE if double precision value V may be cast
7843 to single precision without loss of accuracy. */
7846 is_double_a_single (bfd_int64_t v
)
7848 int exp
= (int)((v
>> 52) & 0x7FF);
7849 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7851 return (exp
== 0 || exp
== 0x7FF
7852 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7853 && (mantissa
& 0x1FFFFFFFl
) == 0;
7856 /* Returns a double precision value casted to single precision
7857 (ignoring the least significant bits in exponent and mantissa). */
7860 double_to_single (bfd_int64_t v
)
7862 int sign
= (int) ((v
>> 63) & 1l);
7863 int exp
= (int) ((v
>> 52) & 0x7FF);
7864 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7870 exp
= exp
- 1023 + 127;
7879 /* No denormalized numbers. */
7885 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7887 #endif /* BFD_HOST_64_BIT */
7896 static void do_vfp_nsyn_opcode (const char *);
7898 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7899 Determine whether it can be performed with a move instruction; if
7900 it can, convert inst.instruction to that move instruction and
7901 return TRUE; if it can't, convert inst.instruction to a literal-pool
7902 load and return FALSE. If this is not a valid thing to do in the
7903 current context, set inst.error and return TRUE.
7905 inst.operands[i] describes the destination register. */
7908 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7911 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7912 bfd_boolean arm_p
= (t
== CONST_ARM
);
7915 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7919 if ((inst
.instruction
& tbit
) == 0)
7921 inst
.error
= _("invalid pseudo operation");
7925 if (inst
.reloc
.exp
.X_op
!= O_constant
7926 && inst
.reloc
.exp
.X_op
!= O_symbol
7927 && inst
.reloc
.exp
.X_op
!= O_big
)
7929 inst
.error
= _("constant expression expected");
7933 if (inst
.reloc
.exp
.X_op
== O_constant
7934 || inst
.reloc
.exp
.X_op
== O_big
)
7936 #if defined BFD_HOST_64_BIT
7941 if (inst
.reloc
.exp
.X_op
== O_big
)
7943 LITTLENUM_TYPE w
[X_PRECISION
];
7946 if (inst
.reloc
.exp
.X_add_number
== -1)
7948 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7950 /* FIXME: Should we check words w[2..5] ? */
7955 #if defined BFD_HOST_64_BIT
7957 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7958 << LITTLENUM_NUMBER_OF_BITS
)
7959 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7960 << LITTLENUM_NUMBER_OF_BITS
)
7961 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7962 << LITTLENUM_NUMBER_OF_BITS
)
7963 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7965 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7966 | (l
[0] & LITTLENUM_MASK
);
7970 v
= inst
.reloc
.exp
.X_add_number
;
7972 if (!inst
.operands
[i
].issingle
)
7976 /* LDR should not use lead in a flag-setting instruction being
7977 chosen so we do not check whether movs can be used. */
7979 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7980 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7981 && inst
.operands
[i
].reg
!= 13
7982 && inst
.operands
[i
].reg
!= 15)
7984 /* Check if on thumb2 it can be done with a mov.w, mvn or
7985 movw instruction. */
7986 unsigned int newimm
;
7987 bfd_boolean isNegated
;
7989 newimm
= encode_thumb32_immediate (v
);
7990 if (newimm
!= (unsigned int) FAIL
)
7994 newimm
= encode_thumb32_immediate (~v
);
7995 if (newimm
!= (unsigned int) FAIL
)
7999 /* The number can be loaded with a mov.w or mvn
8001 if (newimm
!= (unsigned int) FAIL
8002 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8004 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8005 | (inst
.operands
[i
].reg
<< 8));
8006 /* Change to MOVN. */
8007 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8008 inst
.instruction
|= (newimm
& 0x800) << 15;
8009 inst
.instruction
|= (newimm
& 0x700) << 4;
8010 inst
.instruction
|= (newimm
& 0x0ff);
8013 /* The number can be loaded with a movw instruction. */
8014 else if ((v
& ~0xFFFF) == 0
8015 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8017 int imm
= v
& 0xFFFF;
8019 inst
.instruction
= 0xf2400000; /* MOVW. */
8020 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8021 inst
.instruction
|= (imm
& 0xf000) << 4;
8022 inst
.instruction
|= (imm
& 0x0800) << 15;
8023 inst
.instruction
|= (imm
& 0x0700) << 4;
8024 inst
.instruction
|= (imm
& 0x00ff);
8031 int value
= encode_arm_immediate (v
);
8035 /* This can be done with a mov instruction. */
8036 inst
.instruction
&= LITERAL_MASK
;
8037 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8038 inst
.instruction
|= value
& 0xfff;
8042 value
= encode_arm_immediate (~ v
);
8045 /* This can be done with a mvn instruction. */
8046 inst
.instruction
&= LITERAL_MASK
;
8047 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8048 inst
.instruction
|= value
& 0xfff;
8052 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8055 unsigned immbits
= 0;
8056 unsigned immlo
= inst
.operands
[1].imm
;
8057 unsigned immhi
= inst
.operands
[1].regisimm
8058 ? inst
.operands
[1].reg
8059 : inst
.reloc
.exp
.X_unsigned
8061 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8062 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8063 &op
, 64, NT_invtype
);
8067 neon_invert_size (&immlo
, &immhi
, 64);
8069 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8070 &op
, 64, NT_invtype
);
8075 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8081 /* Fill other bits in vmov encoding for both thumb and arm. */
8083 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8085 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8086 neon_write_immbits (immbits
);
8094 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8095 if (inst
.operands
[i
].issingle
8096 && is_quarter_float (inst
.operands
[1].imm
)
8097 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8099 inst
.operands
[1].imm
=
8100 neon_qfloat_bits (v
);
8101 do_vfp_nsyn_opcode ("fconsts");
8105 /* If our host does not support a 64-bit type then we cannot perform
8106 the following optimization. This mean that there will be a
8107 discrepancy between the output produced by an assembler built for
8108 a 32-bit-only host and the output produced from a 64-bit host, but
8109 this cannot be helped. */
8110 #if defined BFD_HOST_64_BIT
8111 else if (!inst
.operands
[1].issingle
8112 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8114 if (is_double_a_single (v
)
8115 && is_quarter_float (double_to_single (v
)))
8117 inst
.operands
[1].imm
=
8118 neon_qfloat_bits (double_to_single (v
));
8119 do_vfp_nsyn_opcode ("fconstd");
8127 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8128 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8131 inst
.operands
[1].reg
= REG_PC
;
8132 inst
.operands
[1].isreg
= 1;
8133 inst
.operands
[1].preind
= 1;
8134 inst
.reloc
.pc_rel
= 1;
8135 inst
.reloc
.type
= (thumb_p
8136 ? BFD_RELOC_ARM_THUMB_OFFSET
8138 ? BFD_RELOC_ARM_HWLITERAL
8139 : BFD_RELOC_ARM_LITERAL
));
8143 /* inst.operands[i] was set up by parse_address. Encode it into an
8144 ARM-format instruction. Reject all forms which cannot be encoded
8145 into a coprocessor load/store instruction. If wb_ok is false,
8146 reject use of writeback; if unind_ok is false, reject use of
8147 unindexed addressing. If reloc_override is not 0, use it instead
8148 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8149 (in which case it is preserved). */
8152 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8154 if (!inst
.operands
[i
].isreg
)
8157 if (! inst
.operands
[0].isvec
)
8159 inst
.error
= _("invalid co-processor operand");
8162 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8166 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8168 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8170 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8172 gas_assert (!inst
.operands
[i
].writeback
);
8175 inst
.error
= _("instruction does not support unindexed addressing");
8178 inst
.instruction
|= inst
.operands
[i
].imm
;
8179 inst
.instruction
|= INDEX_UP
;
8183 if (inst
.operands
[i
].preind
)
8184 inst
.instruction
|= PRE_INDEX
;
8186 if (inst
.operands
[i
].writeback
)
8188 if (inst
.operands
[i
].reg
== REG_PC
)
8190 inst
.error
= _("pc may not be used with write-back");
8195 inst
.error
= _("instruction does not support writeback");
8198 inst
.instruction
|= WRITE_BACK
;
8202 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8203 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8204 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8205 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8208 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8210 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8213 /* Prefer + for zero encoded value. */
8214 if (!inst
.operands
[i
].negative
)
8215 inst
.instruction
|= INDEX_UP
;
8220 /* Functions for instruction encoding, sorted by sub-architecture.
8221 First some generics; their names are taken from the conventional
8222 bit positions for register arguments in ARM format instructions. */
8232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8238 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].reg
;
8251 inst
.instruction
|= inst
.operands
[0].reg
;
8252 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8258 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8265 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8266 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8272 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8273 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8277 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8279 if (ARM_CPU_IS_ANY (cpu_variant
))
8281 as_tsktsk ("%s", msg
);
8284 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8296 unsigned Rn
= inst
.operands
[2].reg
;
8297 /* Enforce restrictions on SWP instruction. */
8298 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8300 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8301 _("Rn must not overlap other operands"));
8303 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8305 if (!check_obsolete (&arm_ext_v8
,
8306 _("swp{b} use is obsoleted for ARMv8 and later"))
8307 && warn_on_deprecated
8308 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8309 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8313 inst
.instruction
|= inst
.operands
[1].reg
;
8314 inst
.instruction
|= Rn
<< 16;
8320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8322 inst
.instruction
|= inst
.operands
[2].reg
;
8328 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8329 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8330 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8331 || inst
.reloc
.exp
.X_add_number
!= 0),
8333 inst
.instruction
|= inst
.operands
[0].reg
;
8334 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8335 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8341 inst
.instruction
|= inst
.operands
[0].imm
;
8347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8348 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8351 /* ARM instructions, in alphabetical order by function name (except
8352 that wrapper functions appear immediately after the function they
8355 /* This is a pseudo-op of the form "adr rd, label" to be converted
8356 into a relative address of the form "add rd, pc, #label-.-8". */
8361 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8363 /* Frag hacking will turn this into a sub instruction if the offset turns
8364 out to be negative. */
8365 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8366 inst
.reloc
.pc_rel
= 1;
8367 inst
.reloc
.exp
.X_add_number
-= 8;
8369 if (inst
.reloc
.exp
.X_op
== O_symbol
8370 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8371 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8372 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8373 inst
.reloc
.exp
.X_add_number
+= 1;
8376 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8377 into a relative address of the form:
8378 add rd, pc, #low(label-.-8)"
8379 add rd, rd, #high(label-.-8)" */
8384 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8386 /* Frag hacking will turn this into a sub instruction if the offset turns
8387 out to be negative. */
8388 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8389 inst
.reloc
.pc_rel
= 1;
8390 inst
.size
= INSN_SIZE
* 2;
8391 inst
.reloc
.exp
.X_add_number
-= 8;
8393 if (inst
.reloc
.exp
.X_op
== O_symbol
8394 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8395 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8396 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8397 inst
.reloc
.exp
.X_add_number
+= 1;
8403 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8404 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8406 if (!inst
.operands
[1].present
)
8407 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8409 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8410 encode_arm_shifter_operand (2);
8416 if (inst
.operands
[0].present
)
8417 inst
.instruction
|= inst
.operands
[0].imm
;
8419 inst
.instruction
|= 0xf;
8425 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8426 constraint (msb
> 32, _("bit-field extends past end of register"));
8427 /* The instruction encoding stores the LSB and MSB,
8428 not the LSB and width. */
8429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8430 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8431 inst
.instruction
|= (msb
- 1) << 16;
8439 /* #0 in second position is alternative syntax for bfc, which is
8440 the same instruction but with REG_PC in the Rm field. */
8441 if (!inst
.operands
[1].isreg
)
8442 inst
.operands
[1].reg
= REG_PC
;
8444 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8445 constraint (msb
> 32, _("bit-field extends past end of register"));
8446 /* The instruction encoding stores the LSB and MSB,
8447 not the LSB and width. */
8448 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8449 inst
.instruction
|= inst
.operands
[1].reg
;
8450 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8451 inst
.instruction
|= (msb
- 1) << 16;
8457 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8458 _("bit-field extends past end of register"));
8459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8460 inst
.instruction
|= inst
.operands
[1].reg
;
8461 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8462 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8465 /* ARM V5 breakpoint instruction (argument parse)
8466 BKPT <16 bit unsigned immediate>
8467 Instruction is not conditional.
8468 The bit pattern given in insns[] has the COND_ALWAYS condition,
8469 and it is an error if the caller tried to override that. */
8474 /* Top 12 of 16 bits to bits 19:8. */
8475 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8477 /* Bottom 4 of 16 bits to bits 3:0. */
8478 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8482 encode_branch (int default_reloc
)
8484 if (inst
.operands
[0].hasreloc
)
8486 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8487 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8488 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8489 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8490 ? BFD_RELOC_ARM_PLT32
8491 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8494 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8495 inst
.reloc
.pc_rel
= 1;
8502 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8503 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8506 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8513 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8515 if (inst
.cond
== COND_ALWAYS
)
8516 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8518 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8522 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8525 /* ARM V5 branch-link-exchange instruction (argument parse)
8526 BLX <target_addr> ie BLX(1)
8527 BLX{<condition>} <Rm> ie BLX(2)
8528 Unfortunately, there are two different opcodes for this mnemonic.
8529 So, the insns[].value is not used, and the code here zaps values
8530 into inst.instruction.
8531 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8536 if (inst
.operands
[0].isreg
)
8538 /* Arg is a register; the opcode provided by insns[] is correct.
8539 It is not illegal to do "blx pc", just useless. */
8540 if (inst
.operands
[0].reg
== REG_PC
)
8541 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8543 inst
.instruction
|= inst
.operands
[0].reg
;
8547 /* Arg is an address; this instruction cannot be executed
8548 conditionally, and the opcode must be adjusted.
8549 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8550 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8551 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8552 inst
.instruction
= 0xfa000000;
8553 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8560 bfd_boolean want_reloc
;
8562 if (inst
.operands
[0].reg
== REG_PC
)
8563 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8565 inst
.instruction
|= inst
.operands
[0].reg
;
8566 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8567 it is for ARMv4t or earlier. */
8568 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8569 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8573 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8578 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8582 /* ARM v5TEJ. Jump to Jazelle code. */
8587 if (inst
.operands
[0].reg
== REG_PC
)
8588 as_tsktsk (_("use of r15 in bxj is not really useful"));
8590 inst
.instruction
|= inst
.operands
[0].reg
;
8593 /* Co-processor data operation:
8594 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8595 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8599 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8600 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8601 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8602 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8603 inst
.instruction
|= inst
.operands
[4].reg
;
8604 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8611 encode_arm_shifter_operand (1);
8614 /* Transfer between coprocessor and ARM registers.
8615 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8620 No special properties. */
8622 struct deprecated_coproc_regs_s
8629 arm_feature_set deprecated
;
8630 arm_feature_set obsoleted
;
8631 const char *dep_msg
;
8632 const char *obs_msg
;
8635 #define DEPR_ACCESS_V8 \
8636 N_("This coprocessor register access is deprecated in ARMv8")
8638 /* Table of all deprecated coprocessor registers. */
8639 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8641 {15, 0, 7, 10, 5, /* CP15DMB. */
8642 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8643 DEPR_ACCESS_V8
, NULL
},
8644 {15, 0, 7, 10, 4, /* CP15DSB. */
8645 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8646 DEPR_ACCESS_V8
, NULL
},
8647 {15, 0, 7, 5, 4, /* CP15ISB. */
8648 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8649 DEPR_ACCESS_V8
, NULL
},
8650 {14, 6, 1, 0, 0, /* TEEHBR. */
8651 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8652 DEPR_ACCESS_V8
, NULL
},
8653 {14, 6, 0, 0, 0, /* TEECR. */
8654 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8655 DEPR_ACCESS_V8
, NULL
},
8658 #undef DEPR_ACCESS_V8
8660 static const size_t deprecated_coproc_reg_count
=
8661 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8669 Rd
= inst
.operands
[2].reg
;
8672 if (inst
.instruction
== 0xee000010
8673 || inst
.instruction
== 0xfe000010)
8675 reject_bad_reg (Rd
);
8676 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8678 constraint (Rd
== REG_SP
, BAD_SP
);
8683 if (inst
.instruction
== 0xe000010)
8684 constraint (Rd
== REG_PC
, BAD_PC
);
8687 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8689 const struct deprecated_coproc_regs_s
*r
=
8690 deprecated_coproc_regs
+ i
;
8692 if (inst
.operands
[0].reg
== r
->cp
8693 && inst
.operands
[1].imm
== r
->opc1
8694 && inst
.operands
[3].reg
== r
->crn
8695 && inst
.operands
[4].reg
== r
->crm
8696 && inst
.operands
[5].imm
== r
->opc2
)
8698 if (! ARM_CPU_IS_ANY (cpu_variant
)
8699 && warn_on_deprecated
8700 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8701 as_tsktsk ("%s", r
->dep_msg
);
8705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8706 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8707 inst
.instruction
|= Rd
<< 12;
8708 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8709 inst
.instruction
|= inst
.operands
[4].reg
;
8710 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8713 /* Transfer between coprocessor register and pair of ARM registers.
8714 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8719 Two XScale instructions are special cases of these:
8721 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8722 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8724 Result unpredictable if Rd or Rn is R15. */
8731 Rd
= inst
.operands
[2].reg
;
8732 Rn
= inst
.operands
[3].reg
;
8736 reject_bad_reg (Rd
);
8737 reject_bad_reg (Rn
);
8741 constraint (Rd
== REG_PC
, BAD_PC
);
8742 constraint (Rn
== REG_PC
, BAD_PC
);
8745 /* Only check the MRRC{2} variants. */
8746 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8748 /* If Rd == Rn, error that the operation is
8749 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8750 constraint (Rd
== Rn
, BAD_OVERLAP
);
8753 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8754 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8755 inst
.instruction
|= Rd
<< 12;
8756 inst
.instruction
|= Rn
<< 16;
8757 inst
.instruction
|= inst
.operands
[4].reg
;
8763 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8764 if (inst
.operands
[1].present
)
8766 inst
.instruction
|= CPSI_MMOD
;
8767 inst
.instruction
|= inst
.operands
[1].imm
;
8774 inst
.instruction
|= inst
.operands
[0].imm
;
8780 unsigned Rd
, Rn
, Rm
;
8782 Rd
= inst
.operands
[0].reg
;
8783 Rn
= (inst
.operands
[1].present
8784 ? inst
.operands
[1].reg
: Rd
);
8785 Rm
= inst
.operands
[2].reg
;
8787 constraint ((Rd
== REG_PC
), BAD_PC
);
8788 constraint ((Rn
== REG_PC
), BAD_PC
);
8789 constraint ((Rm
== REG_PC
), BAD_PC
);
8791 inst
.instruction
|= Rd
<< 16;
8792 inst
.instruction
|= Rn
<< 0;
8793 inst
.instruction
|= Rm
<< 8;
8799 /* There is no IT instruction in ARM mode. We
8800 process it to do the validation as if in
8801 thumb mode, just in case the code gets
8802 assembled for thumb using the unified syntax. */
8807 set_it_insn_type (IT_INSN
);
8808 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8809 now_it
.cc
= inst
.operands
[0].imm
;
8813 /* If there is only one register in the register list,
8814 then return its register number. Otherwise return -1. */
8816 only_one_reg_in_list (int range
)
8818 int i
= ffs (range
) - 1;
8819 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8823 encode_ldmstm(int from_push_pop_mnem
)
8825 int base_reg
= inst
.operands
[0].reg
;
8826 int range
= inst
.operands
[1].imm
;
8829 inst
.instruction
|= base_reg
<< 16;
8830 inst
.instruction
|= range
;
8832 if (inst
.operands
[1].writeback
)
8833 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8835 if (inst
.operands
[0].writeback
)
8837 inst
.instruction
|= WRITE_BACK
;
8838 /* Check for unpredictable uses of writeback. */
8839 if (inst
.instruction
& LOAD_BIT
)
8841 /* Not allowed in LDM type 2. */
8842 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8843 && ((range
& (1 << REG_PC
)) == 0))
8844 as_warn (_("writeback of base register is UNPREDICTABLE"));
8845 /* Only allowed if base reg not in list for other types. */
8846 else if (range
& (1 << base_reg
))
8847 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8851 /* Not allowed for type 2. */
8852 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8853 as_warn (_("writeback of base register is UNPREDICTABLE"));
8854 /* Only allowed if base reg not in list, or first in list. */
8855 else if ((range
& (1 << base_reg
))
8856 && (range
& ((1 << base_reg
) - 1)))
8857 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8861 /* If PUSH/POP has only one register, then use the A2 encoding. */
8862 one_reg
= only_one_reg_in_list (range
);
8863 if (from_push_pop_mnem
&& one_reg
>= 0)
8865 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8867 inst
.instruction
&= A_COND_MASK
;
8868 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8869 inst
.instruction
|= one_reg
<< 12;
8876 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8879 /* ARMv5TE load-consecutive (argument parse)
8888 constraint (inst
.operands
[0].reg
% 2 != 0,
8889 _("first transfer register must be even"));
8890 constraint (inst
.operands
[1].present
8891 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8892 _("can only transfer two consecutive registers"));
8893 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8894 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8896 if (!inst
.operands
[1].present
)
8897 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8899 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8900 register and the first register written; we have to diagnose
8901 overlap between the base and the second register written here. */
8903 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8904 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8905 as_warn (_("base register written back, and overlaps "
8906 "second transfer register"));
8908 if (!(inst
.instruction
& V4_STR_BIT
))
8910 /* For an index-register load, the index register must not overlap the
8911 destination (even if not write-back). */
8912 if (inst
.operands
[2].immisreg
8913 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8914 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8915 as_warn (_("index register overlaps transfer register"));
8917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8918 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8924 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8925 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8926 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8927 || inst
.operands
[1].negative
8928 /* This can arise if the programmer has written
8930 or if they have mistakenly used a register name as the last
8933 It is very difficult to distinguish between these two cases
8934 because "rX" might actually be a label. ie the register
8935 name has been occluded by a symbol of the same name. So we
8936 just generate a general 'bad addressing mode' type error
8937 message and leave it up to the programmer to discover the
8938 true cause and fix their mistake. */
8939 || (inst
.operands
[1].reg
== REG_PC
),
8942 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8943 || inst
.reloc
.exp
.X_add_number
!= 0,
8944 _("offset must be zero in ARM encoding"));
8946 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8950 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8956 constraint (inst
.operands
[0].reg
% 2 != 0,
8957 _("even register required"));
8958 constraint (inst
.operands
[1].present
8959 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8960 _("can only load two consecutive registers"));
8961 /* If op 1 were present and equal to PC, this function wouldn't
8962 have been called in the first place. */
8963 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8966 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8969 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8970 which is not a multiple of four is UNPREDICTABLE. */
8972 check_ldr_r15_aligned (void)
8974 constraint (!(inst
.operands
[1].immisreg
)
8975 && (inst
.operands
[0].reg
== REG_PC
8976 && inst
.operands
[1].reg
== REG_PC
8977 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8978 _("ldr to register 15 must be 4-byte alligned"));
8984 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8985 if (!inst
.operands
[1].isreg
)
8986 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8988 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8989 check_ldr_r15_aligned ();
8995 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8997 if (inst
.operands
[1].preind
)
8999 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9000 || inst
.reloc
.exp
.X_add_number
!= 0,
9001 _("this instruction requires a post-indexed address"));
9003 inst
.operands
[1].preind
= 0;
9004 inst
.operands
[1].postind
= 1;
9005 inst
.operands
[1].writeback
= 1;
9007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9008 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9011 /* Halfword and signed-byte load/store operations. */
9016 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9018 if (!inst
.operands
[1].isreg
)
9019 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9021 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9027 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9029 if (inst
.operands
[1].preind
)
9031 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9032 || inst
.reloc
.exp
.X_add_number
!= 0,
9033 _("this instruction requires a post-indexed address"));
9035 inst
.operands
[1].preind
= 0;
9036 inst
.operands
[1].postind
= 1;
9037 inst
.operands
[1].writeback
= 1;
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9040 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9043 /* Co-processor register load/store.
9044 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9048 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9049 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9050 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9056 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9057 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9058 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9059 && !(inst
.instruction
& 0x00400000))
9060 as_tsktsk (_("Rd and Rm should be different in mla"));
9062 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9063 inst
.instruction
|= inst
.operands
[1].reg
;
9064 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9065 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9071 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9072 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9075 encode_arm_shifter_operand (1);
9078 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9085 top
= (inst
.instruction
& 0x00400000) != 0;
9086 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9087 _(":lower16: not allowed in this instruction"));
9088 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9089 _(":upper16: not allowed in this instruction"));
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9091 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9093 imm
= inst
.reloc
.exp
.X_add_number
;
9094 /* The value is in two pieces: 0:11, 16:19. */
9095 inst
.instruction
|= (imm
& 0x00000fff);
9096 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9101 do_vfp_nsyn_mrs (void)
9103 if (inst
.operands
[0].isvec
)
9105 if (inst
.operands
[1].reg
!= 1)
9106 first_error (_("operand 1 must be FPSCR"));
9107 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9108 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9109 do_vfp_nsyn_opcode ("fmstat");
9111 else if (inst
.operands
[1].isvec
)
9112 do_vfp_nsyn_opcode ("fmrx");
9120 do_vfp_nsyn_msr (void)
9122 if (inst
.operands
[0].isvec
)
9123 do_vfp_nsyn_opcode ("fmxr");
9133 unsigned Rt
= inst
.operands
[0].reg
;
9135 if (thumb_mode
&& Rt
== REG_SP
)
9137 inst
.error
= BAD_SP
;
9141 /* APSR_ sets isvec. All other refs to PC are illegal. */
9142 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9144 inst
.error
= BAD_PC
;
9148 /* If we get through parsing the register name, we just insert the number
9149 generated into the instruction without further validation. */
9150 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9151 inst
.instruction
|= (Rt
<< 12);
9157 unsigned Rt
= inst
.operands
[1].reg
;
9160 reject_bad_reg (Rt
);
9161 else if (Rt
== REG_PC
)
9163 inst
.error
= BAD_PC
;
9167 /* If we get through parsing the register name, we just insert the number
9168 generated into the instruction without further validation. */
9169 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9170 inst
.instruction
|= (Rt
<< 12);
9178 if (do_vfp_nsyn_mrs () == SUCCESS
)
9181 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9182 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9184 if (inst
.operands
[1].isreg
)
9186 br
= inst
.operands
[1].reg
;
9187 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9188 as_bad (_("bad register for mrs"));
9192 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9193 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9195 _("'APSR', 'CPSR' or 'SPSR' expected"));
9196 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9199 inst
.instruction
|= br
;
9202 /* Two possible forms:
9203 "{C|S}PSR_<field>, Rm",
9204 "{C|S}PSR_f, #expression". */
9209 if (do_vfp_nsyn_msr () == SUCCESS
)
9212 inst
.instruction
|= inst
.operands
[0].imm
;
9213 if (inst
.operands
[1].isreg
)
9214 inst
.instruction
|= inst
.operands
[1].reg
;
9217 inst
.instruction
|= INST_IMMEDIATE
;
9218 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9219 inst
.reloc
.pc_rel
= 0;
9226 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9228 if (!inst
.operands
[2].present
)
9229 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9230 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9231 inst
.instruction
|= inst
.operands
[1].reg
;
9232 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9234 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9235 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9236 as_tsktsk (_("Rd and Rm should be different in mul"));
9239 /* Long Multiply Parser
9240 UMULL RdLo, RdHi, Rm, Rs
9241 SMULL RdLo, RdHi, Rm, Rs
9242 UMLAL RdLo, RdHi, Rm, Rs
9243 SMLAL RdLo, RdHi, Rm, Rs. */
9248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9250 inst
.instruction
|= inst
.operands
[2].reg
;
9251 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9253 /* rdhi and rdlo must be different. */
9254 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9255 as_tsktsk (_("rdhi and rdlo must be different"));
9257 /* rdhi, rdlo and rm must all be different before armv6. */
9258 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9259 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9260 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9261 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9267 if (inst
.operands
[0].present
9268 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9270 /* Architectural NOP hints are CPSR sets with no bits selected. */
9271 inst
.instruction
&= 0xf0000000;
9272 inst
.instruction
|= 0x0320f000;
9273 if (inst
.operands
[0].present
)
9274 inst
.instruction
|= inst
.operands
[0].imm
;
9278 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9279 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9280 Condition defaults to COND_ALWAYS.
9281 Error if Rd, Rn or Rm are R15. */
9286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9288 inst
.instruction
|= inst
.operands
[2].reg
;
9289 if (inst
.operands
[3].present
)
9290 encode_arm_shift (3);
9293 /* ARM V6 PKHTB (Argument Parse). */
9298 if (!inst
.operands
[3].present
)
9300 /* If the shift specifier is omitted, turn the instruction
9301 into pkhbt rd, rm, rn. */
9302 inst
.instruction
&= 0xfff00010;
9303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9304 inst
.instruction
|= inst
.operands
[1].reg
;
9305 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9310 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9311 inst
.instruction
|= inst
.operands
[2].reg
;
9312 encode_arm_shift (3);
9316 /* ARMv5TE: Preload-Cache
9317 MP Extensions: Preload for write
9321 Syntactically, like LDR with B=1, W=0, L=1. */
9326 constraint (!inst
.operands
[0].isreg
,
9327 _("'[' expected after PLD mnemonic"));
9328 constraint (inst
.operands
[0].postind
,
9329 _("post-indexed expression used in preload instruction"));
9330 constraint (inst
.operands
[0].writeback
,
9331 _("writeback used in preload instruction"));
9332 constraint (!inst
.operands
[0].preind
,
9333 _("unindexed addressing used in preload instruction"));
9334 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9337 /* ARMv7: PLI <addr_mode> */
9341 constraint (!inst
.operands
[0].isreg
,
9342 _("'[' expected after PLI mnemonic"));
9343 constraint (inst
.operands
[0].postind
,
9344 _("post-indexed expression used in preload instruction"));
9345 constraint (inst
.operands
[0].writeback
,
9346 _("writeback used in preload instruction"));
9347 constraint (!inst
.operands
[0].preind
,
9348 _("unindexed addressing used in preload instruction"));
9349 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9350 inst
.instruction
&= ~PRE_INDEX
;
9356 constraint (inst
.operands
[0].writeback
,
9357 _("push/pop do not support {reglist}^"));
9358 inst
.operands
[1] = inst
.operands
[0];
9359 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9360 inst
.operands
[0].isreg
= 1;
9361 inst
.operands
[0].writeback
= 1;
9362 inst
.operands
[0].reg
= REG_SP
;
9363 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9366 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9367 word at the specified address and the following word
9369 Unconditionally executed.
9370 Error if Rn is R15. */
9375 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9376 if (inst
.operands
[0].writeback
)
9377 inst
.instruction
|= WRITE_BACK
;
9380 /* ARM V6 ssat (argument parse). */
9385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9386 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9387 inst
.instruction
|= inst
.operands
[2].reg
;
9389 if (inst
.operands
[3].present
)
9390 encode_arm_shift (3);
9393 /* ARM V6 usat (argument parse). */
9398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9399 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9400 inst
.instruction
|= inst
.operands
[2].reg
;
9402 if (inst
.operands
[3].present
)
9403 encode_arm_shift (3);
9406 /* ARM V6 ssat16 (argument parse). */
9411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9412 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9413 inst
.instruction
|= inst
.operands
[2].reg
;
9419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9420 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9421 inst
.instruction
|= inst
.operands
[2].reg
;
9424 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9425 preserving the other bits.
9427 setend <endian_specifier>, where <endian_specifier> is either
9433 if (warn_on_deprecated
9434 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9435 as_tsktsk (_("setend use is deprecated for ARMv8"));
9437 if (inst
.operands
[0].imm
)
9438 inst
.instruction
|= 0x200;
9444 unsigned int Rm
= (inst
.operands
[1].present
9445 ? inst
.operands
[1].reg
9446 : inst
.operands
[0].reg
);
9448 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9449 inst
.instruction
|= Rm
;
9450 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9452 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9453 inst
.instruction
|= SHIFT_BY_REG
;
9454 /* PR 12854: Error on extraneous shifts. */
9455 constraint (inst
.operands
[2].shifted
,
9456 _("extraneous shift as part of operand to shift insn"));
9459 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9465 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9466 inst
.reloc
.pc_rel
= 0;
9472 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9473 inst
.reloc
.pc_rel
= 0;
9479 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9480 inst
.reloc
.pc_rel
= 0;
9486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9487 _("selected processor does not support SETPAN instruction"));
9489 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9496 _("selected processor does not support SETPAN instruction"));
9498 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9501 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9502 SMLAxy{cond} Rd,Rm,Rs,Rn
9503 SMLAWy{cond} Rd,Rm,Rs,Rn
9504 Error if any register is R15. */
9509 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9510 inst
.instruction
|= inst
.operands
[1].reg
;
9511 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9512 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9515 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9516 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9517 Error if any register is R15.
9518 Warning if Rdlo == Rdhi. */
9523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9525 inst
.instruction
|= inst
.operands
[2].reg
;
9526 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9528 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9529 as_tsktsk (_("rdhi and rdlo must be different"));
9532 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9533 SMULxy{cond} Rd,Rm,Rs
9534 Error if any register is R15. */
9539 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9540 inst
.instruction
|= inst
.operands
[1].reg
;
9541 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9544 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9545 the same for both ARM and Thumb-2. */
9552 if (inst
.operands
[0].present
)
9554 reg
= inst
.operands
[0].reg
;
9555 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9560 inst
.instruction
|= reg
<< 16;
9561 inst
.instruction
|= inst
.operands
[1].imm
;
9562 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9563 inst
.instruction
|= WRITE_BACK
;
9566 /* ARM V6 strex (argument parse). */
9571 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9572 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9573 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9574 || inst
.operands
[2].negative
9575 /* See comment in do_ldrex(). */
9576 || (inst
.operands
[2].reg
== REG_PC
),
9579 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9580 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9582 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9583 || inst
.reloc
.exp
.X_add_number
!= 0,
9584 _("offset must be zero in ARM encoding"));
9586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9587 inst
.instruction
|= inst
.operands
[1].reg
;
9588 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9589 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9595 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9596 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9597 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9598 || inst
.operands
[2].negative
,
9601 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9602 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9610 constraint (inst
.operands
[1].reg
% 2 != 0,
9611 _("even register required"));
9612 constraint (inst
.operands
[2].present
9613 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9614 _("can only store two consecutive registers"));
9615 /* If op 2 were present and equal to PC, this function wouldn't
9616 have been called in the first place. */
9617 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9619 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9620 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9621 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9625 inst
.instruction
|= inst
.operands
[1].reg
;
9626 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9633 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9634 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9642 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9643 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9648 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9649 extends it to 32-bits, and adds the result to a value in another
9650 register. You can specify a rotation by 0, 8, 16, or 24 bits
9651 before extracting the 16-bit value.
9652 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9653 Condition defaults to COND_ALWAYS.
9654 Error if any register uses R15. */
9659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9661 inst
.instruction
|= inst
.operands
[2].reg
;
9662 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9667 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9668 Condition defaults to COND_ALWAYS.
9669 Error if any register uses R15. */
9674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9675 inst
.instruction
|= inst
.operands
[1].reg
;
9676 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9679 /* VFP instructions. In a logical order: SP variant first, monad
9680 before dyad, arithmetic then move then load/store. */
9683 do_vfp_sp_monadic (void)
9685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9690 do_vfp_sp_dyadic (void)
9692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9694 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9698 do_vfp_sp_compare_z (void)
9700 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9704 do_vfp_dp_sp_cvt (void)
9706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9707 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9711 do_vfp_sp_dp_cvt (void)
9713 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9714 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9718 do_vfp_reg_from_sp (void)
9720 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9721 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9725 do_vfp_reg2_from_sp2 (void)
9727 constraint (inst
.operands
[2].imm
!= 2,
9728 _("only two consecutive VFP SP registers allowed here"));
9729 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9730 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9731 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9735 do_vfp_sp_from_reg (void)
9737 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9738 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9742 do_vfp_sp2_from_reg2 (void)
9744 constraint (inst
.operands
[0].imm
!= 2,
9745 _("only two consecutive VFP SP registers allowed here"));
9746 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9747 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9748 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9752 do_vfp_sp_ldst (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9755 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9759 do_vfp_dp_ldst (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9762 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9767 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9769 if (inst
.operands
[0].writeback
)
9770 inst
.instruction
|= WRITE_BACK
;
9772 constraint (ldstm_type
!= VFP_LDSTMIA
,
9773 _("this addressing mode requires base-register writeback"));
9774 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9775 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9776 inst
.instruction
|= inst
.operands
[1].imm
;
9780 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9784 if (inst
.operands
[0].writeback
)
9785 inst
.instruction
|= WRITE_BACK
;
9787 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9788 _("this addressing mode requires base-register writeback"));
9790 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9791 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9793 count
= inst
.operands
[1].imm
<< 1;
9794 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9797 inst
.instruction
|= count
;
9801 do_vfp_sp_ldstmia (void)
9803 vfp_sp_ldstm (VFP_LDSTMIA
);
9807 do_vfp_sp_ldstmdb (void)
9809 vfp_sp_ldstm (VFP_LDSTMDB
);
9813 do_vfp_dp_ldstmia (void)
9815 vfp_dp_ldstm (VFP_LDSTMIA
);
9819 do_vfp_dp_ldstmdb (void)
9821 vfp_dp_ldstm (VFP_LDSTMDB
);
9825 do_vfp_xp_ldstmia (void)
9827 vfp_dp_ldstm (VFP_LDSTMIAX
);
9831 do_vfp_xp_ldstmdb (void)
9833 vfp_dp_ldstm (VFP_LDSTMDBX
);
9837 do_vfp_dp_rd_rm (void)
9839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9844 do_vfp_dp_rn_rd (void)
9846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9847 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9851 do_vfp_dp_rd_rn (void)
9853 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9854 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9858 do_vfp_dp_rd_rn_rm (void)
9860 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9861 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9862 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9872 do_vfp_dp_rm_rd_rn (void)
9874 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9875 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9876 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9879 /* VFPv3 instructions. */
9881 do_vfp_sp_const (void)
9883 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9884 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9885 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9889 do_vfp_dp_const (void)
9891 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9892 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9893 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9897 vfp_conv (int srcsize
)
9899 int immbits
= srcsize
- inst
.operands
[1].imm
;
9901 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9903 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9904 i.e. immbits must be in range 0 - 16. */
9905 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9908 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9910 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9911 i.e. immbits must be in range 0 - 31. */
9912 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9916 inst
.instruction
|= (immbits
& 1) << 5;
9917 inst
.instruction
|= (immbits
>> 1);
9921 do_vfp_sp_conv_16 (void)
9923 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9928 do_vfp_dp_conv_16 (void)
9930 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9935 do_vfp_sp_conv_32 (void)
9937 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9942 do_vfp_dp_conv_32 (void)
9944 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9948 /* FPA instructions. Also in a logical order. */
9953 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9954 inst
.instruction
|= inst
.operands
[1].reg
;
9958 do_fpa_ldmstm (void)
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9961 switch (inst
.operands
[1].imm
)
9963 case 1: inst
.instruction
|= CP_T_X
; break;
9964 case 2: inst
.instruction
|= CP_T_Y
; break;
9965 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9970 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9972 /* The instruction specified "ea" or "fd", so we can only accept
9973 [Rn]{!}. The instruction does not really support stacking or
9974 unstacking, so we have to emulate these by setting appropriate
9975 bits and offsets. */
9976 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9977 || inst
.reloc
.exp
.X_add_number
!= 0,
9978 _("this instruction does not support indexing"));
9980 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9981 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9983 if (!(inst
.instruction
& INDEX_UP
))
9984 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9986 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9988 inst
.operands
[2].preind
= 0;
9989 inst
.operands
[2].postind
= 1;
9993 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9996 /* iWMMXt instructions: strictly in alphabetical order. */
9999 do_iwmmxt_tandorc (void)
10001 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10005 do_iwmmxt_textrc (void)
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10008 inst
.instruction
|= inst
.operands
[1].imm
;
10012 do_iwmmxt_textrm (void)
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10015 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10016 inst
.instruction
|= inst
.operands
[2].imm
;
10020 do_iwmmxt_tinsr (void)
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10024 inst
.instruction
|= inst
.operands
[2].imm
;
10028 do_iwmmxt_tmia (void)
10030 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10031 inst
.instruction
|= inst
.operands
[1].reg
;
10032 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10036 do_iwmmxt_waligni (void)
10038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10040 inst
.instruction
|= inst
.operands
[2].reg
;
10041 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10045 do_iwmmxt_wmerge (void)
10047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10048 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10049 inst
.instruction
|= inst
.operands
[2].reg
;
10050 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10054 do_iwmmxt_wmov (void)
10056 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10058 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10059 inst
.instruction
|= inst
.operands
[1].reg
;
10063 do_iwmmxt_wldstbh (void)
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10068 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10070 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10071 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10075 do_iwmmxt_wldstw (void)
10077 /* RIWR_RIWC clears .isreg for a control register. */
10078 if (!inst
.operands
[0].isreg
)
10080 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10081 inst
.instruction
|= 0xf0000000;
10084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10085 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10089 do_iwmmxt_wldstd (void)
10091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10092 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10093 && inst
.operands
[1].immisreg
)
10095 inst
.instruction
&= ~0x1a000ff;
10096 inst
.instruction
|= (0xfU
<< 28);
10097 if (inst
.operands
[1].preind
)
10098 inst
.instruction
|= PRE_INDEX
;
10099 if (!inst
.operands
[1].negative
)
10100 inst
.instruction
|= INDEX_UP
;
10101 if (inst
.operands
[1].writeback
)
10102 inst
.instruction
|= WRITE_BACK
;
10103 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10104 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10105 inst
.instruction
|= inst
.operands
[1].imm
;
10108 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10112 do_iwmmxt_wshufh (void)
10114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10115 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10116 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10117 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10121 do_iwmmxt_wzero (void)
10123 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10124 inst
.instruction
|= inst
.operands
[0].reg
;
10125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10126 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10130 do_iwmmxt_wrwrwr_or_imm5 (void)
10132 if (inst
.operands
[2].isreg
)
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10136 _("immediate operand requires iWMMXt2"));
10138 if (inst
.operands
[2].imm
== 0)
10140 switch ((inst
.instruction
>> 20) & 0xf)
10146 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10147 inst
.operands
[2].imm
= 16;
10148 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10154 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10155 inst
.operands
[2].imm
= 32;
10156 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10163 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10165 wrn
= (inst
.instruction
>> 16) & 0xf;
10166 inst
.instruction
&= 0xff0fff0f;
10167 inst
.instruction
|= wrn
;
10168 /* Bail out here; the instruction is now assembled. */
10173 /* Map 32 -> 0, etc. */
10174 inst
.operands
[2].imm
&= 0x1f;
10175 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10179 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10180 operations first, then control, shift, and load/store. */
10182 /* Insns like "foo X,Y,Z". */
10185 do_mav_triple (void)
10187 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10188 inst
.instruction
|= inst
.operands
[1].reg
;
10189 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10192 /* Insns like "foo W,X,Y,Z".
10193 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10198 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10199 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10200 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10201 inst
.instruction
|= inst
.operands
[3].reg
;
10204 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10206 do_mav_dspsc (void)
10208 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10211 /* Maverick shift immediate instructions.
10212 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10213 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10216 do_mav_shift (void)
10218 int imm
= inst
.operands
[2].imm
;
10220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10221 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10223 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10224 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10225 Bit 4 should be 0. */
10226 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10228 inst
.instruction
|= imm
;
10231 /* XScale instructions. Also sorted arithmetic before move. */
10233 /* Xscale multiply-accumulate (argument parse)
10236 MIAxycc acc0,Rm,Rs. */
10241 inst
.instruction
|= inst
.operands
[1].reg
;
10242 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10245 /* Xscale move-accumulator-register (argument parse)
10247 MARcc acc0,RdLo,RdHi. */
10252 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10253 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10256 /* Xscale move-register-accumulator (argument parse)
10258 MRAcc RdLo,RdHi,acc0. */
10263 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10268 /* Encoding functions relevant only to Thumb. */
10270 /* inst.operands[i] is a shifted-register operand; encode
10271 it into inst.instruction in the format used by Thumb32. */
10274 encode_thumb32_shifted_operand (int i
)
10276 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10277 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10279 constraint (inst
.operands
[i
].immisreg
,
10280 _("shift by register not allowed in thumb mode"));
10281 inst
.instruction
|= inst
.operands
[i
].reg
;
10282 if (shift
== SHIFT_RRX
)
10283 inst
.instruction
|= SHIFT_ROR
<< 4;
10286 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10287 _("expression too complex"));
10289 constraint (value
> 32
10290 || (value
== 32 && (shift
== SHIFT_LSL
10291 || shift
== SHIFT_ROR
)),
10292 _("shift expression is too large"));
10296 else if (value
== 32)
10299 inst
.instruction
|= shift
<< 4;
10300 inst
.instruction
|= (value
& 0x1c) << 10;
10301 inst
.instruction
|= (value
& 0x03) << 6;
10306 /* inst.operands[i] was set up by parse_address. Encode it into a
10307 Thumb32 format load or store instruction. Reject forms that cannot
10308 be used with such instructions. If is_t is true, reject forms that
10309 cannot be used with a T instruction; if is_d is true, reject forms
10310 that cannot be used with a D instruction. If it is a store insn,
10311 reject PC in Rn. */
10314 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10316 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10318 constraint (!inst
.operands
[i
].isreg
,
10319 _("Instruction does not support =N addresses"));
10321 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10322 if (inst
.operands
[i
].immisreg
)
10324 constraint (is_pc
, BAD_PC_ADDRESSING
);
10325 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10326 constraint (inst
.operands
[i
].negative
,
10327 _("Thumb does not support negative register indexing"));
10328 constraint (inst
.operands
[i
].postind
,
10329 _("Thumb does not support register post-indexing"));
10330 constraint (inst
.operands
[i
].writeback
,
10331 _("Thumb does not support register indexing with writeback"));
10332 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10333 _("Thumb supports only LSL in shifted register indexing"));
10335 inst
.instruction
|= inst
.operands
[i
].imm
;
10336 if (inst
.operands
[i
].shifted
)
10338 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10339 _("expression too complex"));
10340 constraint (inst
.reloc
.exp
.X_add_number
< 0
10341 || inst
.reloc
.exp
.X_add_number
> 3,
10342 _("shift out of range"));
10343 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10345 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10347 else if (inst
.operands
[i
].preind
)
10349 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10350 constraint (is_t
&& inst
.operands
[i
].writeback
,
10351 _("cannot use writeback with this instruction"));
10352 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10353 BAD_PC_ADDRESSING
);
10357 inst
.instruction
|= 0x01000000;
10358 if (inst
.operands
[i
].writeback
)
10359 inst
.instruction
|= 0x00200000;
10363 inst
.instruction
|= 0x00000c00;
10364 if (inst
.operands
[i
].writeback
)
10365 inst
.instruction
|= 0x00000100;
10367 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10369 else if (inst
.operands
[i
].postind
)
10371 gas_assert (inst
.operands
[i
].writeback
);
10372 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10373 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10376 inst
.instruction
|= 0x00200000;
10378 inst
.instruction
|= 0x00000900;
10379 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10381 else /* unindexed - only for coprocessor */
10382 inst
.error
= _("instruction does not accept unindexed addressing");
10385 /* Table of Thumb instructions which exist in both 16- and 32-bit
10386 encodings (the latter only in post-V6T2 cores). The index is the
10387 value used in the insns table below. When there is more than one
10388 possible 16-bit encoding for the instruction, this table always
10390 Also contains several pseudo-instructions used during relaxation. */
10391 #define T16_32_TAB \
10392 X(_adc, 4140, eb400000), \
10393 X(_adcs, 4140, eb500000), \
10394 X(_add, 1c00, eb000000), \
10395 X(_adds, 1c00, eb100000), \
10396 X(_addi, 0000, f1000000), \
10397 X(_addis, 0000, f1100000), \
10398 X(_add_pc,000f, f20f0000), \
10399 X(_add_sp,000d, f10d0000), \
10400 X(_adr, 000f, f20f0000), \
10401 X(_and, 4000, ea000000), \
10402 X(_ands, 4000, ea100000), \
10403 X(_asr, 1000, fa40f000), \
10404 X(_asrs, 1000, fa50f000), \
10405 X(_b, e000, f000b000), \
10406 X(_bcond, d000, f0008000), \
10407 X(_bic, 4380, ea200000), \
10408 X(_bics, 4380, ea300000), \
10409 X(_cmn, 42c0, eb100f00), \
10410 X(_cmp, 2800, ebb00f00), \
10411 X(_cpsie, b660, f3af8400), \
10412 X(_cpsid, b670, f3af8600), \
10413 X(_cpy, 4600, ea4f0000), \
10414 X(_dec_sp,80dd, f1ad0d00), \
10415 X(_eor, 4040, ea800000), \
10416 X(_eors, 4040, ea900000), \
10417 X(_inc_sp,00dd, f10d0d00), \
10418 X(_ldmia, c800, e8900000), \
10419 X(_ldr, 6800, f8500000), \
10420 X(_ldrb, 7800, f8100000), \
10421 X(_ldrh, 8800, f8300000), \
10422 X(_ldrsb, 5600, f9100000), \
10423 X(_ldrsh, 5e00, f9300000), \
10424 X(_ldr_pc,4800, f85f0000), \
10425 X(_ldr_pc2,4800, f85f0000), \
10426 X(_ldr_sp,9800, f85d0000), \
10427 X(_lsl, 0000, fa00f000), \
10428 X(_lsls, 0000, fa10f000), \
10429 X(_lsr, 0800, fa20f000), \
10430 X(_lsrs, 0800, fa30f000), \
10431 X(_mov, 2000, ea4f0000), \
10432 X(_movs, 2000, ea5f0000), \
10433 X(_mul, 4340, fb00f000), \
10434 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10435 X(_mvn, 43c0, ea6f0000), \
10436 X(_mvns, 43c0, ea7f0000), \
10437 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10438 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10439 X(_orr, 4300, ea400000), \
10440 X(_orrs, 4300, ea500000), \
10441 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10442 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10443 X(_rev, ba00, fa90f080), \
10444 X(_rev16, ba40, fa90f090), \
10445 X(_revsh, bac0, fa90f0b0), \
10446 X(_ror, 41c0, fa60f000), \
10447 X(_rors, 41c0, fa70f000), \
10448 X(_sbc, 4180, eb600000), \
10449 X(_sbcs, 4180, eb700000), \
10450 X(_stmia, c000, e8800000), \
10451 X(_str, 6000, f8400000), \
10452 X(_strb, 7000, f8000000), \
10453 X(_strh, 8000, f8200000), \
10454 X(_str_sp,9000, f84d0000), \
10455 X(_sub, 1e00, eba00000), \
10456 X(_subs, 1e00, ebb00000), \
10457 X(_subi, 8000, f1a00000), \
10458 X(_subis, 8000, f1b00000), \
10459 X(_sxtb, b240, fa4ff080), \
10460 X(_sxth, b200, fa0ff080), \
10461 X(_tst, 4200, ea100f00), \
10462 X(_uxtb, b2c0, fa5ff080), \
10463 X(_uxth, b280, fa1ff080), \
10464 X(_nop, bf00, f3af8000), \
10465 X(_yield, bf10, f3af8001), \
10466 X(_wfe, bf20, f3af8002), \
10467 X(_wfi, bf30, f3af8003), \
10468 X(_sev, bf40, f3af8004), \
10469 X(_sevl, bf50, f3af8005), \
10470 X(_udf, de00, f7f0a000)
10472 /* To catch errors in encoding functions, the codes are all offset by
10473 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10474 as 16-bit instructions. */
10475 #define X(a,b,c) T_MNEM##a
10476 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10479 #define X(a,b,c) 0x##b
10480 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10481 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10484 #define X(a,b,c) 0x##c
10485 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10486 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10487 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10491 /* Thumb instruction encoders, in alphabetical order. */
10493 /* ADDW or SUBW. */
10496 do_t_add_sub_w (void)
10500 Rd
= inst
.operands
[0].reg
;
10501 Rn
= inst
.operands
[1].reg
;
10503 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10504 is the SP-{plus,minus}-immediate form of the instruction. */
10506 constraint (Rd
== REG_PC
, BAD_PC
);
10508 reject_bad_reg (Rd
);
10510 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10511 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10514 /* Parse an add or subtract instruction. We get here with inst.instruction
10515 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10518 do_t_add_sub (void)
10522 Rd
= inst
.operands
[0].reg
;
10523 Rs
= (inst
.operands
[1].present
10524 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10525 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10528 set_it_insn_type_last ();
10530 if (unified_syntax
)
10533 bfd_boolean narrow
;
10536 flags
= (inst
.instruction
== T_MNEM_adds
10537 || inst
.instruction
== T_MNEM_subs
);
10539 narrow
= !in_it_block ();
10541 narrow
= in_it_block ();
10542 if (!inst
.operands
[2].isreg
)
10546 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10547 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10549 add
= (inst
.instruction
== T_MNEM_add
10550 || inst
.instruction
== T_MNEM_adds
);
10552 if (inst
.size_req
!= 4)
10554 /* Attempt to use a narrow opcode, with relaxation if
10556 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10557 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10558 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10559 opcode
= T_MNEM_add_sp
;
10560 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10561 opcode
= T_MNEM_add_pc
;
10562 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10565 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10567 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10571 inst
.instruction
= THUMB_OP16(opcode
);
10572 inst
.instruction
|= (Rd
<< 4) | Rs
;
10573 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10574 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10576 if (inst
.size_req
== 2)
10577 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10579 inst
.relax
= opcode
;
10583 constraint (inst
.size_req
== 2, BAD_HIREG
);
10585 if (inst
.size_req
== 4
10586 || (inst
.size_req
!= 2 && !opcode
))
10588 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10589 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10590 THUMB1_RELOC_ONLY
);
10593 constraint (add
, BAD_PC
);
10594 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10595 _("only SUBS PC, LR, #const allowed"));
10596 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10597 _("expression too complex"));
10598 constraint (inst
.reloc
.exp
.X_add_number
< 0
10599 || inst
.reloc
.exp
.X_add_number
> 0xff,
10600 _("immediate value out of range"));
10601 inst
.instruction
= T2_SUBS_PC_LR
10602 | inst
.reloc
.exp
.X_add_number
;
10603 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10606 else if (Rs
== REG_PC
)
10608 /* Always use addw/subw. */
10609 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10610 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10614 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10615 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10618 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10620 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10622 inst
.instruction
|= Rd
<< 8;
10623 inst
.instruction
|= Rs
<< 16;
10628 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10629 unsigned int shift
= inst
.operands
[2].shift_kind
;
10631 Rn
= inst
.operands
[2].reg
;
10632 /* See if we can do this with a 16-bit instruction. */
10633 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10635 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10640 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10641 || inst
.instruction
== T_MNEM_add
)
10643 : T_OPCODE_SUB_R3
);
10644 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10648 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10650 /* Thumb-1 cores (except v6-M) require at least one high
10651 register in a narrow non flag setting add. */
10652 if (Rd
> 7 || Rn
> 7
10653 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10654 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10661 inst
.instruction
= T_OPCODE_ADD_HI
;
10662 inst
.instruction
|= (Rd
& 8) << 4;
10663 inst
.instruction
|= (Rd
& 7);
10664 inst
.instruction
|= Rn
<< 3;
10670 constraint (Rd
== REG_PC
, BAD_PC
);
10671 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10672 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10673 constraint (Rs
== REG_PC
, BAD_PC
);
10674 reject_bad_reg (Rn
);
10676 /* If we get here, it can't be done in 16 bits. */
10677 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10678 _("shift must be constant"));
10679 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10680 inst
.instruction
|= Rd
<< 8;
10681 inst
.instruction
|= Rs
<< 16;
10682 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10683 _("shift value over 3 not allowed in thumb mode"));
10684 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10685 _("only LSL shift allowed in thumb mode"));
10686 encode_thumb32_shifted_operand (2);
10691 constraint (inst
.instruction
== T_MNEM_adds
10692 || inst
.instruction
== T_MNEM_subs
,
10695 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10697 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10698 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10701 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10702 ? 0x0000 : 0x8000);
10703 inst
.instruction
|= (Rd
<< 4) | Rs
;
10704 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10708 Rn
= inst
.operands
[2].reg
;
10709 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10711 /* We now have Rd, Rs, and Rn set to registers. */
10712 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10714 /* Can't do this for SUB. */
10715 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10716 inst
.instruction
= T_OPCODE_ADD_HI
;
10717 inst
.instruction
|= (Rd
& 8) << 4;
10718 inst
.instruction
|= (Rd
& 7);
10720 inst
.instruction
|= Rn
<< 3;
10722 inst
.instruction
|= Rs
<< 3;
10724 constraint (1, _("dest must overlap one source register"));
10728 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10729 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10730 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10740 Rd
= inst
.operands
[0].reg
;
10741 reject_bad_reg (Rd
);
10743 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10745 /* Defer to section relaxation. */
10746 inst
.relax
= inst
.instruction
;
10747 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10748 inst
.instruction
|= Rd
<< 4;
10750 else if (unified_syntax
&& inst
.size_req
!= 2)
10752 /* Generate a 32-bit opcode. */
10753 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10754 inst
.instruction
|= Rd
<< 8;
10755 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10756 inst
.reloc
.pc_rel
= 1;
10760 /* Generate a 16-bit opcode. */
10761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10762 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10763 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10764 inst
.reloc
.pc_rel
= 1;
10765 inst
.instruction
|= Rd
<< 4;
10768 if (inst
.reloc
.exp
.X_op
== O_symbol
10769 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10770 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10771 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10772 inst
.reloc
.exp
.X_add_number
+= 1;
10775 /* Arithmetic instructions for which there is just one 16-bit
10776 instruction encoding, and it allows only two low registers.
10777 For maximal compatibility with ARM syntax, we allow three register
10778 operands even when Thumb-32 instructions are not available, as long
10779 as the first two are identical. For instance, both "sbc r0,r1" and
10780 "sbc r0,r0,r1" are allowed. */
10786 Rd
= inst
.operands
[0].reg
;
10787 Rs
= (inst
.operands
[1].present
10788 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10789 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10790 Rn
= inst
.operands
[2].reg
;
10792 reject_bad_reg (Rd
);
10793 reject_bad_reg (Rs
);
10794 if (inst
.operands
[2].isreg
)
10795 reject_bad_reg (Rn
);
10797 if (unified_syntax
)
10799 if (!inst
.operands
[2].isreg
)
10801 /* For an immediate, we always generate a 32-bit opcode;
10802 section relaxation will shrink it later if possible. */
10803 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10804 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10805 inst
.instruction
|= Rd
<< 8;
10806 inst
.instruction
|= Rs
<< 16;
10807 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10811 bfd_boolean narrow
;
10813 /* See if we can do this with a 16-bit instruction. */
10814 if (THUMB_SETS_FLAGS (inst
.instruction
))
10815 narrow
= !in_it_block ();
10817 narrow
= in_it_block ();
10819 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10821 if (inst
.operands
[2].shifted
)
10823 if (inst
.size_req
== 4)
10829 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10830 inst
.instruction
|= Rd
;
10831 inst
.instruction
|= Rn
<< 3;
10835 /* If we get here, it can't be done in 16 bits. */
10836 constraint (inst
.operands
[2].shifted
10837 && inst
.operands
[2].immisreg
,
10838 _("shift must be constant"));
10839 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10840 inst
.instruction
|= Rd
<< 8;
10841 inst
.instruction
|= Rs
<< 16;
10842 encode_thumb32_shifted_operand (2);
10847 /* On its face this is a lie - the instruction does set the
10848 flags. However, the only supported mnemonic in this mode
10849 says it doesn't. */
10850 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10852 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10853 _("unshifted register required"));
10854 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10855 constraint (Rd
!= Rs
,
10856 _("dest and source1 must be the same register"));
10858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10859 inst
.instruction
|= Rd
;
10860 inst
.instruction
|= Rn
<< 3;
10864 /* Similarly, but for instructions where the arithmetic operation is
10865 commutative, so we can allow either of them to be different from
10866 the destination operand in a 16-bit instruction. For instance, all
10867 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10874 Rd
= inst
.operands
[0].reg
;
10875 Rs
= (inst
.operands
[1].present
10876 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10877 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10878 Rn
= inst
.operands
[2].reg
;
10880 reject_bad_reg (Rd
);
10881 reject_bad_reg (Rs
);
10882 if (inst
.operands
[2].isreg
)
10883 reject_bad_reg (Rn
);
10885 if (unified_syntax
)
10887 if (!inst
.operands
[2].isreg
)
10889 /* For an immediate, we always generate a 32-bit opcode;
10890 section relaxation will shrink it later if possible. */
10891 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10892 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10893 inst
.instruction
|= Rd
<< 8;
10894 inst
.instruction
|= Rs
<< 16;
10895 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10899 bfd_boolean narrow
;
10901 /* See if we can do this with a 16-bit instruction. */
10902 if (THUMB_SETS_FLAGS (inst
.instruction
))
10903 narrow
= !in_it_block ();
10905 narrow
= in_it_block ();
10907 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10909 if (inst
.operands
[2].shifted
)
10911 if (inst
.size_req
== 4)
10918 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10919 inst
.instruction
|= Rd
;
10920 inst
.instruction
|= Rn
<< 3;
10925 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10926 inst
.instruction
|= Rd
;
10927 inst
.instruction
|= Rs
<< 3;
10932 /* If we get here, it can't be done in 16 bits. */
10933 constraint (inst
.operands
[2].shifted
10934 && inst
.operands
[2].immisreg
,
10935 _("shift must be constant"));
10936 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10937 inst
.instruction
|= Rd
<< 8;
10938 inst
.instruction
|= Rs
<< 16;
10939 encode_thumb32_shifted_operand (2);
10944 /* On its face this is a lie - the instruction does set the
10945 flags. However, the only supported mnemonic in this mode
10946 says it doesn't. */
10947 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10949 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10950 _("unshifted register required"));
10951 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10953 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10954 inst
.instruction
|= Rd
;
10957 inst
.instruction
|= Rn
<< 3;
10959 inst
.instruction
|= Rs
<< 3;
10961 constraint (1, _("dest must overlap one source register"));
10969 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10970 constraint (msb
> 32, _("bit-field extends past end of register"));
10971 /* The instruction encoding stores the LSB and MSB,
10972 not the LSB and width. */
10973 Rd
= inst
.operands
[0].reg
;
10974 reject_bad_reg (Rd
);
10975 inst
.instruction
|= Rd
<< 8;
10976 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10977 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10978 inst
.instruction
|= msb
- 1;
10987 Rd
= inst
.operands
[0].reg
;
10988 reject_bad_reg (Rd
);
10990 /* #0 in second position is alternative syntax for bfc, which is
10991 the same instruction but with REG_PC in the Rm field. */
10992 if (!inst
.operands
[1].isreg
)
10996 Rn
= inst
.operands
[1].reg
;
10997 reject_bad_reg (Rn
);
11000 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11001 constraint (msb
> 32, _("bit-field extends past end of register"));
11002 /* The instruction encoding stores the LSB and MSB,
11003 not the LSB and width. */
11004 inst
.instruction
|= Rd
<< 8;
11005 inst
.instruction
|= Rn
<< 16;
11006 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11007 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11008 inst
.instruction
|= msb
- 1;
11016 Rd
= inst
.operands
[0].reg
;
11017 Rn
= inst
.operands
[1].reg
;
11019 reject_bad_reg (Rd
);
11020 reject_bad_reg (Rn
);
11022 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11023 _("bit-field extends past end of register"));
11024 inst
.instruction
|= Rd
<< 8;
11025 inst
.instruction
|= Rn
<< 16;
11026 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11027 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11028 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11031 /* ARM V5 Thumb BLX (argument parse)
11032 BLX <target_addr> which is BLX(1)
11033 BLX <Rm> which is BLX(2)
11034 Unfortunately, there are two different opcodes for this mnemonic.
11035 So, the insns[].value is not used, and the code here zaps values
11036 into inst.instruction.
11038 ??? How to take advantage of the additional two bits of displacement
11039 available in Thumb32 mode? Need new relocation? */
11044 set_it_insn_type_last ();
11046 if (inst
.operands
[0].isreg
)
11048 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11049 /* We have a register, so this is BLX(2). */
11050 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11054 /* No register. This must be BLX(1). */
11055 inst
.instruction
= 0xf000e800;
11056 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11065 bfd_reloc_code_real_type reloc
;
11068 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11070 if (in_it_block ())
11072 /* Conditional branches inside IT blocks are encoded as unconditional
11074 cond
= COND_ALWAYS
;
11079 if (cond
!= COND_ALWAYS
)
11080 opcode
= T_MNEM_bcond
;
11082 opcode
= inst
.instruction
;
11085 && (inst
.size_req
== 4
11086 || (inst
.size_req
!= 2
11087 && (inst
.operands
[0].hasreloc
11088 || inst
.reloc
.exp
.X_op
== O_constant
))))
11090 inst
.instruction
= THUMB_OP32(opcode
);
11091 if (cond
== COND_ALWAYS
)
11092 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11096 _("selected architecture does not support "
11097 "wide conditional branch instruction"));
11099 gas_assert (cond
!= 0xF);
11100 inst
.instruction
|= cond
<< 22;
11101 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11106 inst
.instruction
= THUMB_OP16(opcode
);
11107 if (cond
== COND_ALWAYS
)
11108 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11111 inst
.instruction
|= cond
<< 8;
11112 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11114 /* Allow section relaxation. */
11115 if (unified_syntax
&& inst
.size_req
!= 2)
11116 inst
.relax
= opcode
;
11118 inst
.reloc
.type
= reloc
;
11119 inst
.reloc
.pc_rel
= 1;
11122 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11123 between the two is the maximum immediate allowed - which is passed in
11126 do_t_bkpt_hlt1 (int range
)
11128 constraint (inst
.cond
!= COND_ALWAYS
,
11129 _("instruction is always unconditional"));
11130 if (inst
.operands
[0].present
)
11132 constraint (inst
.operands
[0].imm
> range
,
11133 _("immediate value out of range"));
11134 inst
.instruction
|= inst
.operands
[0].imm
;
11137 set_it_insn_type (NEUTRAL_IT_INSN
);
11143 do_t_bkpt_hlt1 (63);
11149 do_t_bkpt_hlt1 (255);
11153 do_t_branch23 (void)
11155 set_it_insn_type_last ();
11156 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11158 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11159 this file. We used to simply ignore the PLT reloc type here --
11160 the branch encoding is now needed to deal with TLSCALL relocs.
11161 So if we see a PLT reloc now, put it back to how it used to be to
11162 keep the preexisting behaviour. */
11163 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11164 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11166 #if defined(OBJ_COFF)
11167 /* If the destination of the branch is a defined symbol which does not have
11168 the THUMB_FUNC attribute, then we must be calling a function which has
11169 the (interfacearm) attribute. We look for the Thumb entry point to that
11170 function and change the branch to refer to that function instead. */
11171 if ( inst
.reloc
.exp
.X_op
== O_symbol
11172 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11173 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11174 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11175 inst
.reloc
.exp
.X_add_symbol
=
11176 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11183 set_it_insn_type_last ();
11184 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11185 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11186 should cause the alignment to be checked once it is known. This is
11187 because BX PC only works if the instruction is word aligned. */
11195 set_it_insn_type_last ();
11196 Rm
= inst
.operands
[0].reg
;
11197 reject_bad_reg (Rm
);
11198 inst
.instruction
|= Rm
<< 16;
11207 Rd
= inst
.operands
[0].reg
;
11208 Rm
= inst
.operands
[1].reg
;
11210 reject_bad_reg (Rd
);
11211 reject_bad_reg (Rm
);
11213 inst
.instruction
|= Rd
<< 8;
11214 inst
.instruction
|= Rm
<< 16;
11215 inst
.instruction
|= Rm
;
11221 set_it_insn_type (OUTSIDE_IT_INSN
);
11222 inst
.instruction
|= inst
.operands
[0].imm
;
11228 set_it_insn_type (OUTSIDE_IT_INSN
);
11230 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11231 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11233 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11234 inst
.instruction
= 0xf3af8000;
11235 inst
.instruction
|= imod
<< 9;
11236 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11237 if (inst
.operands
[1].present
)
11238 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11242 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11243 && (inst
.operands
[0].imm
& 4),
11244 _("selected processor does not support 'A' form "
11245 "of this instruction"));
11246 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11247 _("Thumb does not support the 2-argument "
11248 "form of this instruction"));
11249 inst
.instruction
|= inst
.operands
[0].imm
;
11253 /* THUMB CPY instruction (argument parse). */
11258 if (inst
.size_req
== 4)
11260 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11261 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11262 inst
.instruction
|= inst
.operands
[1].reg
;
11266 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11267 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11268 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11275 set_it_insn_type (OUTSIDE_IT_INSN
);
11276 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11277 inst
.instruction
|= inst
.operands
[0].reg
;
11278 inst
.reloc
.pc_rel
= 1;
11279 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11285 inst
.instruction
|= inst
.operands
[0].imm
;
11291 unsigned Rd
, Rn
, Rm
;
11293 Rd
= inst
.operands
[0].reg
;
11294 Rn
= (inst
.operands
[1].present
11295 ? inst
.operands
[1].reg
: Rd
);
11296 Rm
= inst
.operands
[2].reg
;
11298 reject_bad_reg (Rd
);
11299 reject_bad_reg (Rn
);
11300 reject_bad_reg (Rm
);
11302 inst
.instruction
|= Rd
<< 8;
11303 inst
.instruction
|= Rn
<< 16;
11304 inst
.instruction
|= Rm
;
11310 if (unified_syntax
&& inst
.size_req
== 4)
11311 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11313 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11319 unsigned int cond
= inst
.operands
[0].imm
;
11321 set_it_insn_type (IT_INSN
);
11322 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11324 now_it
.warn_deprecated
= FALSE
;
11326 /* If the condition is a negative condition, invert the mask. */
11327 if ((cond
& 0x1) == 0x0)
11329 unsigned int mask
= inst
.instruction
& 0x000f;
11331 if ((mask
& 0x7) == 0)
11333 /* No conversion needed. */
11334 now_it
.block_length
= 1;
11336 else if ((mask
& 0x3) == 0)
11339 now_it
.block_length
= 2;
11341 else if ((mask
& 0x1) == 0)
11344 now_it
.block_length
= 3;
11349 now_it
.block_length
= 4;
11352 inst
.instruction
&= 0xfff0;
11353 inst
.instruction
|= mask
;
11356 inst
.instruction
|= cond
<< 4;
11359 /* Helper function used for both push/pop and ldm/stm. */
11361 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11365 load
= (inst
.instruction
& (1 << 20)) != 0;
11367 if (mask
& (1 << 13))
11368 inst
.error
= _("SP not allowed in register list");
11370 if ((mask
& (1 << base
)) != 0
11372 inst
.error
= _("having the base register in the register list when "
11373 "using write back is UNPREDICTABLE");
11377 if (mask
& (1 << 15))
11379 if (mask
& (1 << 14))
11380 inst
.error
= _("LR and PC should not both be in register list");
11382 set_it_insn_type_last ();
11387 if (mask
& (1 << 15))
11388 inst
.error
= _("PC not allowed in register list");
11391 if ((mask
& (mask
- 1)) == 0)
11393 /* Single register transfers implemented as str/ldr. */
11396 if (inst
.instruction
& (1 << 23))
11397 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11399 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11403 if (inst
.instruction
& (1 << 23))
11404 inst
.instruction
= 0x00800000; /* ia -> [base] */
11406 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11409 inst
.instruction
|= 0xf8400000;
11411 inst
.instruction
|= 0x00100000;
11413 mask
= ffs (mask
) - 1;
11416 else if (writeback
)
11417 inst
.instruction
|= WRITE_BACK
;
11419 inst
.instruction
|= mask
;
11420 inst
.instruction
|= base
<< 16;
11426 /* This really doesn't seem worth it. */
11427 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11428 _("expression too complex"));
11429 constraint (inst
.operands
[1].writeback
,
11430 _("Thumb load/store multiple does not support {reglist}^"));
11432 if (unified_syntax
)
11434 bfd_boolean narrow
;
11438 /* See if we can use a 16-bit instruction. */
11439 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11440 && inst
.size_req
!= 4
11441 && !(inst
.operands
[1].imm
& ~0xff))
11443 mask
= 1 << inst
.operands
[0].reg
;
11445 if (inst
.operands
[0].reg
<= 7)
11447 if (inst
.instruction
== T_MNEM_stmia
11448 ? inst
.operands
[0].writeback
11449 : (inst
.operands
[0].writeback
11450 == !(inst
.operands
[1].imm
& mask
)))
11452 if (inst
.instruction
== T_MNEM_stmia
11453 && (inst
.operands
[1].imm
& mask
)
11454 && (inst
.operands
[1].imm
& (mask
- 1)))
11455 as_warn (_("value stored for r%d is UNKNOWN"),
11456 inst
.operands
[0].reg
);
11458 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11460 inst
.instruction
|= inst
.operands
[1].imm
;
11463 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11465 /* This means 1 register in reg list one of 3 situations:
11466 1. Instruction is stmia, but without writeback.
11467 2. lmdia without writeback, but with Rn not in
11469 3. ldmia with writeback, but with Rn in reglist.
11470 Case 3 is UNPREDICTABLE behaviour, so we handle
11471 case 1 and 2 which can be converted into a 16-bit
11472 str or ldr. The SP cases are handled below. */
11473 unsigned long opcode
;
11474 /* First, record an error for Case 3. */
11475 if (inst
.operands
[1].imm
& mask
11476 && inst
.operands
[0].writeback
)
11478 _("having the base register in the register list when "
11479 "using write back is UNPREDICTABLE");
11481 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11483 inst
.instruction
= THUMB_OP16 (opcode
);
11484 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11485 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11489 else if (inst
.operands
[0] .reg
== REG_SP
)
11491 if (inst
.operands
[0].writeback
)
11494 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11495 ? T_MNEM_push
: T_MNEM_pop
);
11496 inst
.instruction
|= inst
.operands
[1].imm
;
11499 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11502 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11503 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11504 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11512 if (inst
.instruction
< 0xffff)
11513 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11515 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11516 inst
.operands
[0].writeback
);
11521 constraint (inst
.operands
[0].reg
> 7
11522 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11523 constraint (inst
.instruction
!= T_MNEM_ldmia
11524 && inst
.instruction
!= T_MNEM_stmia
,
11525 _("Thumb-2 instruction only valid in unified syntax"));
11526 if (inst
.instruction
== T_MNEM_stmia
)
11528 if (!inst
.operands
[0].writeback
)
11529 as_warn (_("this instruction will write back the base register"));
11530 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11531 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11532 as_warn (_("value stored for r%d is UNKNOWN"),
11533 inst
.operands
[0].reg
);
11537 if (!inst
.operands
[0].writeback
11538 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11539 as_warn (_("this instruction will write back the base register"));
11540 else if (inst
.operands
[0].writeback
11541 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11542 as_warn (_("this instruction will not write back the base register"));
11545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11546 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11547 inst
.instruction
|= inst
.operands
[1].imm
;
11554 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11555 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11556 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11557 || inst
.operands
[1].negative
,
11560 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11564 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11570 if (!inst
.operands
[1].present
)
11572 constraint (inst
.operands
[0].reg
== REG_LR
,
11573 _("r14 not allowed as first register "
11574 "when second register is omitted"));
11575 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11577 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11580 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11581 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11582 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11588 unsigned long opcode
;
11591 if (inst
.operands
[0].isreg
11592 && !inst
.operands
[0].preind
11593 && inst
.operands
[0].reg
== REG_PC
)
11594 set_it_insn_type_last ();
11596 opcode
= inst
.instruction
;
11597 if (unified_syntax
)
11599 if (!inst
.operands
[1].isreg
)
11601 if (opcode
<= 0xffff)
11602 inst
.instruction
= THUMB_OP32 (opcode
);
11603 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11606 if (inst
.operands
[1].isreg
11607 && !inst
.operands
[1].writeback
11608 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11609 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11610 && opcode
<= 0xffff
11611 && inst
.size_req
!= 4)
11613 /* Insn may have a 16-bit form. */
11614 Rn
= inst
.operands
[1].reg
;
11615 if (inst
.operands
[1].immisreg
)
11617 inst
.instruction
= THUMB_OP16 (opcode
);
11619 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11621 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11622 reject_bad_reg (inst
.operands
[1].imm
);
11624 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11625 && opcode
!= T_MNEM_ldrsb
)
11626 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11627 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11634 if (inst
.reloc
.pc_rel
)
11635 opcode
= T_MNEM_ldr_pc2
;
11637 opcode
= T_MNEM_ldr_pc
;
11641 if (opcode
== T_MNEM_ldr
)
11642 opcode
= T_MNEM_ldr_sp
;
11644 opcode
= T_MNEM_str_sp
;
11646 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11650 inst
.instruction
= inst
.operands
[0].reg
;
11651 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11653 inst
.instruction
|= THUMB_OP16 (opcode
);
11654 if (inst
.size_req
== 2)
11655 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11657 inst
.relax
= opcode
;
11661 /* Definitely a 32-bit variant. */
11663 /* Warning for Erratum 752419. */
11664 if (opcode
== T_MNEM_ldr
11665 && inst
.operands
[0].reg
== REG_SP
11666 && inst
.operands
[1].writeback
== 1
11667 && !inst
.operands
[1].immisreg
)
11669 if (no_cpu_selected ()
11670 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11671 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11672 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11673 as_warn (_("This instruction may be unpredictable "
11674 "if executed on M-profile cores "
11675 "with interrupts enabled."));
11678 /* Do some validations regarding addressing modes. */
11679 if (inst
.operands
[1].immisreg
)
11680 reject_bad_reg (inst
.operands
[1].imm
);
11682 constraint (inst
.operands
[1].writeback
== 1
11683 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11686 inst
.instruction
= THUMB_OP32 (opcode
);
11687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11688 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11689 check_ldr_r15_aligned ();
11693 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11695 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11697 /* Only [Rn,Rm] is acceptable. */
11698 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11699 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11700 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11701 || inst
.operands
[1].negative
,
11702 _("Thumb does not support this addressing mode"));
11703 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11707 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11708 if (!inst
.operands
[1].isreg
)
11709 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11712 constraint (!inst
.operands
[1].preind
11713 || inst
.operands
[1].shifted
11714 || inst
.operands
[1].writeback
,
11715 _("Thumb does not support this addressing mode"));
11716 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11718 constraint (inst
.instruction
& 0x0600,
11719 _("byte or halfword not valid for base register"));
11720 constraint (inst
.operands
[1].reg
== REG_PC
11721 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11722 _("r15 based store not allowed"));
11723 constraint (inst
.operands
[1].immisreg
,
11724 _("invalid base register for register offset"));
11726 if (inst
.operands
[1].reg
== REG_PC
)
11727 inst
.instruction
= T_OPCODE_LDR_PC
;
11728 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11729 inst
.instruction
= T_OPCODE_LDR_SP
;
11731 inst
.instruction
= T_OPCODE_STR_SP
;
11733 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11734 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11738 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11739 if (!inst
.operands
[1].immisreg
)
11741 /* Immediate offset. */
11742 inst
.instruction
|= inst
.operands
[0].reg
;
11743 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11744 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11748 /* Register offset. */
11749 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11750 constraint (inst
.operands
[1].negative
,
11751 _("Thumb does not support this addressing mode"));
11754 switch (inst
.instruction
)
11756 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11757 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11758 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11759 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11760 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11761 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11762 case 0x5600 /* ldrsb */:
11763 case 0x5e00 /* ldrsh */: break;
11767 inst
.instruction
|= inst
.operands
[0].reg
;
11768 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11769 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11775 if (!inst
.operands
[1].present
)
11777 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11778 constraint (inst
.operands
[0].reg
== REG_LR
,
11779 _("r14 not allowed here"));
11780 constraint (inst
.operands
[0].reg
== REG_R12
,
11781 _("r12 not allowed here"));
11784 if (inst
.operands
[2].writeback
11785 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11786 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11787 as_warn (_("base register written back, and overlaps "
11788 "one of transfer registers"));
11790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11791 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11792 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11799 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11805 unsigned Rd
, Rn
, Rm
, Ra
;
11807 Rd
= inst
.operands
[0].reg
;
11808 Rn
= inst
.operands
[1].reg
;
11809 Rm
= inst
.operands
[2].reg
;
11810 Ra
= inst
.operands
[3].reg
;
11812 reject_bad_reg (Rd
);
11813 reject_bad_reg (Rn
);
11814 reject_bad_reg (Rm
);
11815 reject_bad_reg (Ra
);
11817 inst
.instruction
|= Rd
<< 8;
11818 inst
.instruction
|= Rn
<< 16;
11819 inst
.instruction
|= Rm
;
11820 inst
.instruction
|= Ra
<< 12;
11826 unsigned RdLo
, RdHi
, Rn
, Rm
;
11828 RdLo
= inst
.operands
[0].reg
;
11829 RdHi
= inst
.operands
[1].reg
;
11830 Rn
= inst
.operands
[2].reg
;
11831 Rm
= inst
.operands
[3].reg
;
11833 reject_bad_reg (RdLo
);
11834 reject_bad_reg (RdHi
);
11835 reject_bad_reg (Rn
);
11836 reject_bad_reg (Rm
);
11838 inst
.instruction
|= RdLo
<< 12;
11839 inst
.instruction
|= RdHi
<< 8;
11840 inst
.instruction
|= Rn
<< 16;
11841 inst
.instruction
|= Rm
;
11845 do_t_mov_cmp (void)
11849 Rn
= inst
.operands
[0].reg
;
11850 Rm
= inst
.operands
[1].reg
;
11853 set_it_insn_type_last ();
11855 if (unified_syntax
)
11857 int r0off
= (inst
.instruction
== T_MNEM_mov
11858 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11859 unsigned long opcode
;
11860 bfd_boolean narrow
;
11861 bfd_boolean low_regs
;
11863 low_regs
= (Rn
<= 7 && Rm
<= 7);
11864 opcode
= inst
.instruction
;
11865 if (in_it_block ())
11866 narrow
= opcode
!= T_MNEM_movs
;
11868 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11869 if (inst
.size_req
== 4
11870 || inst
.operands
[1].shifted
)
11873 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11874 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11875 && !inst
.operands
[1].shifted
11879 inst
.instruction
= T2_SUBS_PC_LR
;
11883 if (opcode
== T_MNEM_cmp
)
11885 constraint (Rn
== REG_PC
, BAD_PC
);
11888 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11890 warn_deprecated_sp (Rm
);
11891 /* R15 was documented as a valid choice for Rm in ARMv6,
11892 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11893 tools reject R15, so we do too. */
11894 constraint (Rm
== REG_PC
, BAD_PC
);
11897 reject_bad_reg (Rm
);
11899 else if (opcode
== T_MNEM_mov
11900 || opcode
== T_MNEM_movs
)
11902 if (inst
.operands
[1].isreg
)
11904 if (opcode
== T_MNEM_movs
)
11906 reject_bad_reg (Rn
);
11907 reject_bad_reg (Rm
);
11911 /* This is mov.n. */
11912 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11913 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11915 as_tsktsk (_("Use of r%u as a source register is "
11916 "deprecated when r%u is the destination "
11917 "register."), Rm
, Rn
);
11922 /* This is mov.w. */
11923 constraint (Rn
== REG_PC
, BAD_PC
);
11924 constraint (Rm
== REG_PC
, BAD_PC
);
11925 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11926 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11930 reject_bad_reg (Rn
);
11933 if (!inst
.operands
[1].isreg
)
11935 /* Immediate operand. */
11936 if (!in_it_block () && opcode
== T_MNEM_mov
)
11938 if (low_regs
&& narrow
)
11940 inst
.instruction
= THUMB_OP16 (opcode
);
11941 inst
.instruction
|= Rn
<< 8;
11942 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11943 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11945 if (inst
.size_req
== 2)
11946 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11948 inst
.relax
= opcode
;
11953 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11954 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11955 THUMB1_RELOC_ONLY
);
11957 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11958 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11959 inst
.instruction
|= Rn
<< r0off
;
11960 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11963 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11964 && (inst
.instruction
== T_MNEM_mov
11965 || inst
.instruction
== T_MNEM_movs
))
11967 /* Register shifts are encoded as separate shift instructions. */
11968 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11970 if (in_it_block ())
11975 if (inst
.size_req
== 4)
11978 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11984 switch (inst
.operands
[1].shift_kind
)
11987 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11990 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11993 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11996 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12002 inst
.instruction
= opcode
;
12005 inst
.instruction
|= Rn
;
12006 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12011 inst
.instruction
|= CONDS_BIT
;
12013 inst
.instruction
|= Rn
<< 8;
12014 inst
.instruction
|= Rm
<< 16;
12015 inst
.instruction
|= inst
.operands
[1].imm
;
12020 /* Some mov with immediate shift have narrow variants.
12021 Register shifts are handled above. */
12022 if (low_regs
&& inst
.operands
[1].shifted
12023 && (inst
.instruction
== T_MNEM_mov
12024 || inst
.instruction
== T_MNEM_movs
))
12026 if (in_it_block ())
12027 narrow
= (inst
.instruction
== T_MNEM_mov
);
12029 narrow
= (inst
.instruction
== T_MNEM_movs
);
12034 switch (inst
.operands
[1].shift_kind
)
12036 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12037 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12038 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12039 default: narrow
= FALSE
; break;
12045 inst
.instruction
|= Rn
;
12046 inst
.instruction
|= Rm
<< 3;
12047 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12051 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12052 inst
.instruction
|= Rn
<< r0off
;
12053 encode_thumb32_shifted_operand (1);
12057 switch (inst
.instruction
)
12060 /* In v4t or v5t a move of two lowregs produces unpredictable
12061 results. Don't allow this. */
12064 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12065 "MOV Rd, Rs with two low registers is not "
12066 "permitted on this architecture");
12067 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12071 inst
.instruction
= T_OPCODE_MOV_HR
;
12072 inst
.instruction
|= (Rn
& 0x8) << 4;
12073 inst
.instruction
|= (Rn
& 0x7);
12074 inst
.instruction
|= Rm
<< 3;
12078 /* We know we have low registers at this point.
12079 Generate LSLS Rd, Rs, #0. */
12080 inst
.instruction
= T_OPCODE_LSL_I
;
12081 inst
.instruction
|= Rn
;
12082 inst
.instruction
|= Rm
<< 3;
12088 inst
.instruction
= T_OPCODE_CMP_LR
;
12089 inst
.instruction
|= Rn
;
12090 inst
.instruction
|= Rm
<< 3;
12094 inst
.instruction
= T_OPCODE_CMP_HR
;
12095 inst
.instruction
|= (Rn
& 0x8) << 4;
12096 inst
.instruction
|= (Rn
& 0x7);
12097 inst
.instruction
|= Rm
<< 3;
12104 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12106 /* PR 10443: Do not silently ignore shifted operands. */
12107 constraint (inst
.operands
[1].shifted
,
12108 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12110 if (inst
.operands
[1].isreg
)
12112 if (Rn
< 8 && Rm
< 8)
12114 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12115 since a MOV instruction produces unpredictable results. */
12116 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12117 inst
.instruction
= T_OPCODE_ADD_I3
;
12119 inst
.instruction
= T_OPCODE_CMP_LR
;
12121 inst
.instruction
|= Rn
;
12122 inst
.instruction
|= Rm
<< 3;
12126 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12127 inst
.instruction
= T_OPCODE_MOV_HR
;
12129 inst
.instruction
= T_OPCODE_CMP_HR
;
12135 constraint (Rn
> 7,
12136 _("only lo regs allowed with immediate"));
12137 inst
.instruction
|= Rn
<< 8;
12138 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12149 top
= (inst
.instruction
& 0x00800000) != 0;
12150 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12152 constraint (top
, _(":lower16: not allowed in this instruction"));
12153 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12155 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12157 constraint (!top
, _(":upper16: not allowed in this instruction"));
12158 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12161 Rd
= inst
.operands
[0].reg
;
12162 reject_bad_reg (Rd
);
12164 inst
.instruction
|= Rd
<< 8;
12165 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12167 imm
= inst
.reloc
.exp
.X_add_number
;
12168 inst
.instruction
|= (imm
& 0xf000) << 4;
12169 inst
.instruction
|= (imm
& 0x0800) << 15;
12170 inst
.instruction
|= (imm
& 0x0700) << 4;
12171 inst
.instruction
|= (imm
& 0x00ff);
12176 do_t_mvn_tst (void)
12180 Rn
= inst
.operands
[0].reg
;
12181 Rm
= inst
.operands
[1].reg
;
12183 if (inst
.instruction
== T_MNEM_cmp
12184 || inst
.instruction
== T_MNEM_cmn
)
12185 constraint (Rn
== REG_PC
, BAD_PC
);
12187 reject_bad_reg (Rn
);
12188 reject_bad_reg (Rm
);
12190 if (unified_syntax
)
12192 int r0off
= (inst
.instruction
== T_MNEM_mvn
12193 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12194 bfd_boolean narrow
;
12196 if (inst
.size_req
== 4
12197 || inst
.instruction
> 0xffff
12198 || inst
.operands
[1].shifted
12199 || Rn
> 7 || Rm
> 7)
12201 else if (inst
.instruction
== T_MNEM_cmn
12202 || inst
.instruction
== T_MNEM_tst
)
12204 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12205 narrow
= !in_it_block ();
12207 narrow
= in_it_block ();
12209 if (!inst
.operands
[1].isreg
)
12211 /* For an immediate, we always generate a 32-bit opcode;
12212 section relaxation will shrink it later if possible. */
12213 if (inst
.instruction
< 0xffff)
12214 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12215 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12216 inst
.instruction
|= Rn
<< r0off
;
12217 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12221 /* See if we can do this with a 16-bit instruction. */
12224 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12225 inst
.instruction
|= Rn
;
12226 inst
.instruction
|= Rm
<< 3;
12230 constraint (inst
.operands
[1].shifted
12231 && inst
.operands
[1].immisreg
,
12232 _("shift must be constant"));
12233 if (inst
.instruction
< 0xffff)
12234 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12235 inst
.instruction
|= Rn
<< r0off
;
12236 encode_thumb32_shifted_operand (1);
12242 constraint (inst
.instruction
> 0xffff
12243 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12244 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12245 _("unshifted register required"));
12246 constraint (Rn
> 7 || Rm
> 7,
12249 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12250 inst
.instruction
|= Rn
;
12251 inst
.instruction
|= Rm
<< 3;
12260 if (do_vfp_nsyn_mrs () == SUCCESS
)
12263 Rd
= inst
.operands
[0].reg
;
12264 reject_bad_reg (Rd
);
12265 inst
.instruction
|= Rd
<< 8;
12267 if (inst
.operands
[1].isreg
)
12269 unsigned br
= inst
.operands
[1].reg
;
12270 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12271 as_bad (_("bad register for mrs"));
12273 inst
.instruction
|= br
& (0xf << 16);
12274 inst
.instruction
|= (br
& 0x300) >> 4;
12275 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12279 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12281 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12283 /* PR gas/12698: The constraint is only applied for m_profile.
12284 If the user has specified -march=all, we want to ignore it as
12285 we are building for any CPU type, including non-m variants. */
12286 bfd_boolean m_profile
=
12287 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12288 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12289 "not support requested special purpose register"));
12292 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12294 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12295 _("'APSR', 'CPSR' or 'SPSR' expected"));
12297 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12298 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12299 inst
.instruction
|= 0xf0000;
12309 if (do_vfp_nsyn_msr () == SUCCESS
)
12312 constraint (!inst
.operands
[1].isreg
,
12313 _("Thumb encoding does not support an immediate here"));
12315 if (inst
.operands
[0].isreg
)
12316 flags
= (int)(inst
.operands
[0].reg
);
12318 flags
= inst
.operands
[0].imm
;
12320 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12322 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12324 /* PR gas/12698: The constraint is only applied for m_profile.
12325 If the user has specified -march=all, we want to ignore it as
12326 we are building for any CPU type, including non-m variants. */
12327 bfd_boolean m_profile
=
12328 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12329 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12330 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12331 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12332 && bits
!= PSR_f
)) && m_profile
,
12333 _("selected processor does not support requested special "
12334 "purpose register"));
12337 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12338 "requested special purpose register"));
12340 Rn
= inst
.operands
[1].reg
;
12341 reject_bad_reg (Rn
);
12343 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12344 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12345 inst
.instruction
|= (flags
& 0x300) >> 4;
12346 inst
.instruction
|= (flags
& 0xff);
12347 inst
.instruction
|= Rn
<< 16;
12353 bfd_boolean narrow
;
12354 unsigned Rd
, Rn
, Rm
;
12356 if (!inst
.operands
[2].present
)
12357 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12359 Rd
= inst
.operands
[0].reg
;
12360 Rn
= inst
.operands
[1].reg
;
12361 Rm
= inst
.operands
[2].reg
;
12363 if (unified_syntax
)
12365 if (inst
.size_req
== 4
12371 else if (inst
.instruction
== T_MNEM_muls
)
12372 narrow
= !in_it_block ();
12374 narrow
= in_it_block ();
12378 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12379 constraint (Rn
> 7 || Rm
> 7,
12386 /* 16-bit MULS/Conditional MUL. */
12387 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12388 inst
.instruction
|= Rd
;
12391 inst
.instruction
|= Rm
<< 3;
12393 inst
.instruction
|= Rn
<< 3;
12395 constraint (1, _("dest must overlap one source register"));
12399 constraint (inst
.instruction
!= T_MNEM_mul
,
12400 _("Thumb-2 MUL must not set flags"));
12402 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12403 inst
.instruction
|= Rd
<< 8;
12404 inst
.instruction
|= Rn
<< 16;
12405 inst
.instruction
|= Rm
<< 0;
12407 reject_bad_reg (Rd
);
12408 reject_bad_reg (Rn
);
12409 reject_bad_reg (Rm
);
12416 unsigned RdLo
, RdHi
, Rn
, Rm
;
12418 RdLo
= inst
.operands
[0].reg
;
12419 RdHi
= inst
.operands
[1].reg
;
12420 Rn
= inst
.operands
[2].reg
;
12421 Rm
= inst
.operands
[3].reg
;
12423 reject_bad_reg (RdLo
);
12424 reject_bad_reg (RdHi
);
12425 reject_bad_reg (Rn
);
12426 reject_bad_reg (Rm
);
12428 inst
.instruction
|= RdLo
<< 12;
12429 inst
.instruction
|= RdHi
<< 8;
12430 inst
.instruction
|= Rn
<< 16;
12431 inst
.instruction
|= Rm
;
12434 as_tsktsk (_("rdhi and rdlo must be different"));
12440 set_it_insn_type (NEUTRAL_IT_INSN
);
12442 if (unified_syntax
)
12444 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12446 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12447 inst
.instruction
|= inst
.operands
[0].imm
;
12451 /* PR9722: Check for Thumb2 availability before
12452 generating a thumb2 nop instruction. */
12453 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12455 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12456 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12459 inst
.instruction
= 0x46c0;
12464 constraint (inst
.operands
[0].present
,
12465 _("Thumb does not support NOP with hints"));
12466 inst
.instruction
= 0x46c0;
12473 if (unified_syntax
)
12475 bfd_boolean narrow
;
12477 if (THUMB_SETS_FLAGS (inst
.instruction
))
12478 narrow
= !in_it_block ();
12480 narrow
= in_it_block ();
12481 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12483 if (inst
.size_req
== 4)
12488 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12489 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12490 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12494 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12495 inst
.instruction
|= inst
.operands
[0].reg
;
12496 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12501 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12503 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12505 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12506 inst
.instruction
|= inst
.operands
[0].reg
;
12507 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12516 Rd
= inst
.operands
[0].reg
;
12517 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12519 reject_bad_reg (Rd
);
12520 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12521 reject_bad_reg (Rn
);
12523 inst
.instruction
|= Rd
<< 8;
12524 inst
.instruction
|= Rn
<< 16;
12526 if (!inst
.operands
[2].isreg
)
12528 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12529 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12535 Rm
= inst
.operands
[2].reg
;
12536 reject_bad_reg (Rm
);
12538 constraint (inst
.operands
[2].shifted
12539 && inst
.operands
[2].immisreg
,
12540 _("shift must be constant"));
12541 encode_thumb32_shifted_operand (2);
12548 unsigned Rd
, Rn
, Rm
;
12550 Rd
= inst
.operands
[0].reg
;
12551 Rn
= inst
.operands
[1].reg
;
12552 Rm
= inst
.operands
[2].reg
;
12554 reject_bad_reg (Rd
);
12555 reject_bad_reg (Rn
);
12556 reject_bad_reg (Rm
);
12558 inst
.instruction
|= Rd
<< 8;
12559 inst
.instruction
|= Rn
<< 16;
12560 inst
.instruction
|= Rm
;
12561 if (inst
.operands
[3].present
)
12563 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12564 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12565 _("expression too complex"));
12566 inst
.instruction
|= (val
& 0x1c) << 10;
12567 inst
.instruction
|= (val
& 0x03) << 6;
12574 if (!inst
.operands
[3].present
)
12578 inst
.instruction
&= ~0x00000020;
12580 /* PR 10168. Swap the Rm and Rn registers. */
12581 Rtmp
= inst
.operands
[1].reg
;
12582 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12583 inst
.operands
[2].reg
= Rtmp
;
12591 if (inst
.operands
[0].immisreg
)
12592 reject_bad_reg (inst
.operands
[0].imm
);
12594 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12598 do_t_push_pop (void)
12602 constraint (inst
.operands
[0].writeback
,
12603 _("push/pop do not support {reglist}^"));
12604 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12605 _("expression too complex"));
12607 mask
= inst
.operands
[0].imm
;
12608 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12609 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12610 else if (inst
.size_req
!= 4
12611 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12612 ? REG_LR
: REG_PC
)))
12614 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12615 inst
.instruction
|= THUMB_PP_PC_LR
;
12616 inst
.instruction
|= mask
& 0xff;
12618 else if (unified_syntax
)
12620 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12621 encode_thumb2_ldmstm (13, mask
, TRUE
);
12625 inst
.error
= _("invalid register list to push/pop instruction");
12635 Rd
= inst
.operands
[0].reg
;
12636 Rm
= inst
.operands
[1].reg
;
12638 reject_bad_reg (Rd
);
12639 reject_bad_reg (Rm
);
12641 inst
.instruction
|= Rd
<< 8;
12642 inst
.instruction
|= Rm
<< 16;
12643 inst
.instruction
|= Rm
;
12651 Rd
= inst
.operands
[0].reg
;
12652 Rm
= inst
.operands
[1].reg
;
12654 reject_bad_reg (Rd
);
12655 reject_bad_reg (Rm
);
12657 if (Rd
<= 7 && Rm
<= 7
12658 && inst
.size_req
!= 4)
12660 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12661 inst
.instruction
|= Rd
;
12662 inst
.instruction
|= Rm
<< 3;
12664 else if (unified_syntax
)
12666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12667 inst
.instruction
|= Rd
<< 8;
12668 inst
.instruction
|= Rm
<< 16;
12669 inst
.instruction
|= Rm
;
12672 inst
.error
= BAD_HIREG
;
12680 Rd
= inst
.operands
[0].reg
;
12681 Rm
= inst
.operands
[1].reg
;
12683 reject_bad_reg (Rd
);
12684 reject_bad_reg (Rm
);
12686 inst
.instruction
|= Rd
<< 8;
12687 inst
.instruction
|= Rm
;
12695 Rd
= inst
.operands
[0].reg
;
12696 Rs
= (inst
.operands
[1].present
12697 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12698 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12700 reject_bad_reg (Rd
);
12701 reject_bad_reg (Rs
);
12702 if (inst
.operands
[2].isreg
)
12703 reject_bad_reg (inst
.operands
[2].reg
);
12705 inst
.instruction
|= Rd
<< 8;
12706 inst
.instruction
|= Rs
<< 16;
12707 if (!inst
.operands
[2].isreg
)
12709 bfd_boolean narrow
;
12711 if ((inst
.instruction
& 0x00100000) != 0)
12712 narrow
= !in_it_block ();
12714 narrow
= in_it_block ();
12716 if (Rd
> 7 || Rs
> 7)
12719 if (inst
.size_req
== 4 || !unified_syntax
)
12722 if (inst
.reloc
.exp
.X_op
!= O_constant
12723 || inst
.reloc
.exp
.X_add_number
!= 0)
12726 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12727 relaxation, but it doesn't seem worth the hassle. */
12730 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12731 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12732 inst
.instruction
|= Rs
<< 3;
12733 inst
.instruction
|= Rd
;
12737 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12738 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12742 encode_thumb32_shifted_operand (2);
12748 if (warn_on_deprecated
12749 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12750 as_tsktsk (_("setend use is deprecated for ARMv8"));
12752 set_it_insn_type (OUTSIDE_IT_INSN
);
12753 if (inst
.operands
[0].imm
)
12754 inst
.instruction
|= 0x8;
12760 if (!inst
.operands
[1].present
)
12761 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12763 if (unified_syntax
)
12765 bfd_boolean narrow
;
12768 switch (inst
.instruction
)
12771 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12773 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12775 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12777 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12781 if (THUMB_SETS_FLAGS (inst
.instruction
))
12782 narrow
= !in_it_block ();
12784 narrow
= in_it_block ();
12785 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12787 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12789 if (inst
.operands
[2].isreg
12790 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12791 || inst
.operands
[2].reg
> 7))
12793 if (inst
.size_req
== 4)
12796 reject_bad_reg (inst
.operands
[0].reg
);
12797 reject_bad_reg (inst
.operands
[1].reg
);
12801 if (inst
.operands
[2].isreg
)
12803 reject_bad_reg (inst
.operands
[2].reg
);
12804 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12805 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12806 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12807 inst
.instruction
|= inst
.operands
[2].reg
;
12809 /* PR 12854: Error on extraneous shifts. */
12810 constraint (inst
.operands
[2].shifted
,
12811 _("extraneous shift as part of operand to shift insn"));
12815 inst
.operands
[1].shifted
= 1;
12816 inst
.operands
[1].shift_kind
= shift_kind
;
12817 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12818 ? T_MNEM_movs
: T_MNEM_mov
);
12819 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12820 encode_thumb32_shifted_operand (1);
12821 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12822 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12827 if (inst
.operands
[2].isreg
)
12829 switch (shift_kind
)
12831 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12832 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12833 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12834 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12838 inst
.instruction
|= inst
.operands
[0].reg
;
12839 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12841 /* PR 12854: Error on extraneous shifts. */
12842 constraint (inst
.operands
[2].shifted
,
12843 _("extraneous shift as part of operand to shift insn"));
12847 switch (shift_kind
)
12849 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12850 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12851 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12854 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12855 inst
.instruction
|= inst
.operands
[0].reg
;
12856 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12862 constraint (inst
.operands
[0].reg
> 7
12863 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12864 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12866 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12868 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12869 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12870 _("source1 and dest must be same register"));
12872 switch (inst
.instruction
)
12874 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12875 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12876 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12877 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12881 inst
.instruction
|= inst
.operands
[0].reg
;
12882 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12884 /* PR 12854: Error on extraneous shifts. */
12885 constraint (inst
.operands
[2].shifted
,
12886 _("extraneous shift as part of operand to shift insn"));
12890 switch (inst
.instruction
)
12892 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12893 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12894 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12895 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12898 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12899 inst
.instruction
|= inst
.operands
[0].reg
;
12900 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12908 unsigned Rd
, Rn
, Rm
;
12910 Rd
= inst
.operands
[0].reg
;
12911 Rn
= inst
.operands
[1].reg
;
12912 Rm
= inst
.operands
[2].reg
;
12914 reject_bad_reg (Rd
);
12915 reject_bad_reg (Rn
);
12916 reject_bad_reg (Rm
);
12918 inst
.instruction
|= Rd
<< 8;
12919 inst
.instruction
|= Rn
<< 16;
12920 inst
.instruction
|= Rm
;
12926 unsigned Rd
, Rn
, Rm
;
12928 Rd
= inst
.operands
[0].reg
;
12929 Rm
= inst
.operands
[1].reg
;
12930 Rn
= inst
.operands
[2].reg
;
12932 reject_bad_reg (Rd
);
12933 reject_bad_reg (Rn
);
12934 reject_bad_reg (Rm
);
12936 inst
.instruction
|= Rd
<< 8;
12937 inst
.instruction
|= Rn
<< 16;
12938 inst
.instruction
|= Rm
;
12944 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12945 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12946 _("SMC is not permitted on this architecture"));
12947 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12948 _("expression too complex"));
12949 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12950 inst
.instruction
|= (value
& 0xf000) >> 12;
12951 inst
.instruction
|= (value
& 0x0ff0);
12952 inst
.instruction
|= (value
& 0x000f) << 16;
12953 /* PR gas/15623: SMC instructions must be last in an IT block. */
12954 set_it_insn_type_last ();
12960 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12962 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12963 inst
.instruction
|= (value
& 0x0fff);
12964 inst
.instruction
|= (value
& 0xf000) << 4;
12968 do_t_ssat_usat (int bias
)
12972 Rd
= inst
.operands
[0].reg
;
12973 Rn
= inst
.operands
[2].reg
;
12975 reject_bad_reg (Rd
);
12976 reject_bad_reg (Rn
);
12978 inst
.instruction
|= Rd
<< 8;
12979 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12980 inst
.instruction
|= Rn
<< 16;
12982 if (inst
.operands
[3].present
)
12984 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12986 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12988 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12989 _("expression too complex"));
12991 if (shift_amount
!= 0)
12993 constraint (shift_amount
> 31,
12994 _("shift expression is too large"));
12996 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12997 inst
.instruction
|= 0x00200000; /* sh bit. */
12999 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13000 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13008 do_t_ssat_usat (1);
13016 Rd
= inst
.operands
[0].reg
;
13017 Rn
= inst
.operands
[2].reg
;
13019 reject_bad_reg (Rd
);
13020 reject_bad_reg (Rn
);
13022 inst
.instruction
|= Rd
<< 8;
13023 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13024 inst
.instruction
|= Rn
<< 16;
13030 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13031 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13032 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13033 || inst
.operands
[2].negative
,
13036 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13038 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13039 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13040 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13041 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13047 if (!inst
.operands
[2].present
)
13048 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13050 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13051 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13052 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13055 inst
.instruction
|= inst
.operands
[0].reg
;
13056 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13057 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13058 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13064 unsigned Rd
, Rn
, Rm
;
13066 Rd
= inst
.operands
[0].reg
;
13067 Rn
= inst
.operands
[1].reg
;
13068 Rm
= inst
.operands
[2].reg
;
13070 reject_bad_reg (Rd
);
13071 reject_bad_reg (Rn
);
13072 reject_bad_reg (Rm
);
13074 inst
.instruction
|= Rd
<< 8;
13075 inst
.instruction
|= Rn
<< 16;
13076 inst
.instruction
|= Rm
;
13077 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13085 Rd
= inst
.operands
[0].reg
;
13086 Rm
= inst
.operands
[1].reg
;
13088 reject_bad_reg (Rd
);
13089 reject_bad_reg (Rm
);
13091 if (inst
.instruction
<= 0xffff
13092 && inst
.size_req
!= 4
13093 && Rd
<= 7 && Rm
<= 7
13094 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13096 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13097 inst
.instruction
|= Rd
;
13098 inst
.instruction
|= Rm
<< 3;
13100 else if (unified_syntax
)
13102 if (inst
.instruction
<= 0xffff)
13103 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13104 inst
.instruction
|= Rd
<< 8;
13105 inst
.instruction
|= Rm
;
13106 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13110 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13111 _("Thumb encoding does not support rotation"));
13112 constraint (1, BAD_HIREG
);
13119 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13128 half
= (inst
.instruction
& 0x10) != 0;
13129 set_it_insn_type_last ();
13130 constraint (inst
.operands
[0].immisreg
,
13131 _("instruction requires register index"));
13133 Rn
= inst
.operands
[0].reg
;
13134 Rm
= inst
.operands
[0].imm
;
13136 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13137 constraint (Rn
== REG_SP
, BAD_SP
);
13138 reject_bad_reg (Rm
);
13140 constraint (!half
&& inst
.operands
[0].shifted
,
13141 _("instruction does not allow shifted index"));
13142 inst
.instruction
|= (Rn
<< 16) | Rm
;
13148 if (!inst
.operands
[0].present
)
13149 inst
.operands
[0].imm
= 0;
13151 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13153 constraint (inst
.size_req
== 2,
13154 _("immediate value out of range"));
13155 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13156 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13157 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13161 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13162 inst
.instruction
|= inst
.operands
[0].imm
;
13165 set_it_insn_type (NEUTRAL_IT_INSN
);
13172 do_t_ssat_usat (0);
13180 Rd
= inst
.operands
[0].reg
;
13181 Rn
= inst
.operands
[2].reg
;
13183 reject_bad_reg (Rd
);
13184 reject_bad_reg (Rn
);
13186 inst
.instruction
|= Rd
<< 8;
13187 inst
.instruction
|= inst
.operands
[1].imm
;
13188 inst
.instruction
|= Rn
<< 16;
13191 /* Neon instruction encoder helpers. */
13193 /* Encodings for the different types for various Neon opcodes. */
13195 /* An "invalid" code for the following tables. */
13198 struct neon_tab_entry
13201 unsigned float_or_poly
;
13202 unsigned scalar_or_imm
;
13205 /* Map overloaded Neon opcodes to their respective encodings. */
13206 #define NEON_ENC_TAB \
13207 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13208 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13209 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13210 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13211 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13212 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13213 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13214 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13215 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13216 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13217 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13218 /* Register variants of the following two instructions are encoded as
13219 vcge / vcgt with the operands reversed. */ \
13220 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13221 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13222 X(vfma, N_INV, 0x0000c10, N_INV), \
13223 X(vfms, N_INV, 0x0200c10, N_INV), \
13224 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13225 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13226 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13227 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13228 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13229 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13230 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13231 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13232 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13233 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13234 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13235 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13236 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13237 X(vshl, 0x0000400, N_INV, 0x0800510), \
13238 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13239 X(vand, 0x0000110, N_INV, 0x0800030), \
13240 X(vbic, 0x0100110, N_INV, 0x0800030), \
13241 X(veor, 0x1000110, N_INV, N_INV), \
13242 X(vorn, 0x0300110, N_INV, 0x0800010), \
13243 X(vorr, 0x0200110, N_INV, 0x0800010), \
13244 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13245 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13246 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13247 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13248 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13249 X(vst1, 0x0000000, 0x0800000, N_INV), \
13250 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13251 X(vst2, 0x0000100, 0x0800100, N_INV), \
13252 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13253 X(vst3, 0x0000200, 0x0800200, N_INV), \
13254 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13255 X(vst4, 0x0000300, 0x0800300, N_INV), \
13256 X(vmovn, 0x1b20200, N_INV, N_INV), \
13257 X(vtrn, 0x1b20080, N_INV, N_INV), \
13258 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13259 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13260 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13261 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13262 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13263 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13264 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13265 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13266 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13267 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13268 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13269 X(vseleq, 0xe000a00, N_INV, N_INV), \
13270 X(vselvs, 0xe100a00, N_INV, N_INV), \
13271 X(vselge, 0xe200a00, N_INV, N_INV), \
13272 X(vselgt, 0xe300a00, N_INV, N_INV), \
13273 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13274 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13275 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13276 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13277 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13278 X(aes, 0x3b00300, N_INV, N_INV), \
13279 X(sha3op, 0x2000c00, N_INV, N_INV), \
13280 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13281 X(sha2op, 0x3ba0380, N_INV, N_INV)
13285 #define X(OPC,I,F,S) N_MNEM_##OPC
13290 static const struct neon_tab_entry neon_enc_tab
[] =
13292 #define X(OPC,I,F,S) { (I), (F), (S) }
13297 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13298 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13299 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13300 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13301 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13302 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13303 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13304 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13305 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13306 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13307 #define NEON_ENC_SINGLE_(X) \
13308 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13309 #define NEON_ENC_DOUBLE_(X) \
13310 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13311 #define NEON_ENC_FPV8_(X) \
13312 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13314 #define NEON_ENCODE(type, inst) \
13317 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13318 inst.is_neon = 1; \
13322 #define check_neon_suffixes \
13325 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13327 as_bad (_("invalid neon suffix for non neon instruction")); \
13333 /* Define shapes for instruction operands. The following mnemonic characters
13334 are used in this table:
13336 F - VFP S<n> register
13337 D - Neon D<n> register
13338 Q - Neon Q<n> register
13342 L - D<n> register list
13344 This table is used to generate various data:
13345 - enumerations of the form NS_DDR to be used as arguments to
13347 - a table classifying shapes into single, double, quad, mixed.
13348 - a table used to drive neon_select_shape. */
13350 #define NEON_SHAPE_DEF \
13351 X(3, (D, D, D), DOUBLE), \
13352 X(3, (Q, Q, Q), QUAD), \
13353 X(3, (D, D, I), DOUBLE), \
13354 X(3, (Q, Q, I), QUAD), \
13355 X(3, (D, D, S), DOUBLE), \
13356 X(3, (Q, Q, S), QUAD), \
13357 X(2, (D, D), DOUBLE), \
13358 X(2, (Q, Q), QUAD), \
13359 X(2, (D, S), DOUBLE), \
13360 X(2, (Q, S), QUAD), \
13361 X(2, (D, R), DOUBLE), \
13362 X(2, (Q, R), QUAD), \
13363 X(2, (D, I), DOUBLE), \
13364 X(2, (Q, I), QUAD), \
13365 X(3, (D, L, D), DOUBLE), \
13366 X(2, (D, Q), MIXED), \
13367 X(2, (Q, D), MIXED), \
13368 X(3, (D, Q, I), MIXED), \
13369 X(3, (Q, D, I), MIXED), \
13370 X(3, (Q, D, D), MIXED), \
13371 X(3, (D, Q, Q), MIXED), \
13372 X(3, (Q, Q, D), MIXED), \
13373 X(3, (Q, D, S), MIXED), \
13374 X(3, (D, Q, S), MIXED), \
13375 X(4, (D, D, D, I), DOUBLE), \
13376 X(4, (Q, Q, Q, I), QUAD), \
13377 X(4, (D, D, S, I), DOUBLE), \
13378 X(4, (Q, Q, S, I), QUAD), \
13379 X(2, (F, F), SINGLE), \
13380 X(3, (F, F, F), SINGLE), \
13381 X(2, (F, I), SINGLE), \
13382 X(2, (F, D), MIXED), \
13383 X(2, (D, F), MIXED), \
13384 X(3, (F, F, I), MIXED), \
13385 X(4, (R, R, F, F), SINGLE), \
13386 X(4, (F, F, R, R), SINGLE), \
13387 X(3, (D, R, R), DOUBLE), \
13388 X(3, (R, R, D), DOUBLE), \
13389 X(2, (S, R), SINGLE), \
13390 X(2, (R, S), SINGLE), \
13391 X(2, (F, R), SINGLE), \
13392 X(2, (R, F), SINGLE), \
13393 /* Half float shape supported so far. */\
13394 X (2, (H, D), MIXED), \
13395 X (2, (D, H), MIXED), \
13396 X (2, (H, F), MIXED), \
13397 X (2, (F, H), MIXED), \
13398 X (2, (H, H), HALF), \
13399 X (2, (H, R), HALF), \
13400 X (2, (R, H), HALF), \
13401 X (2, (H, I), HALF), \
13402 X (3, (H, H, H), HALF), \
13403 X (3, (H, F, I), MIXED), \
13404 X (3, (F, H, I), MIXED)
13406 #define S2(A,B) NS_##A##B
13407 #define S3(A,B,C) NS_##A##B##C
13408 #define S4(A,B,C,D) NS_##A##B##C##D
13410 #define X(N, L, C) S##N L
13423 enum neon_shape_class
13432 #define X(N, L, C) SC_##C
13434 static enum neon_shape_class neon_shape_class
[] =
13453 /* Register widths of above. */
13454 static unsigned neon_shape_el_size
[] =
13466 struct neon_shape_info
13469 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13472 #define S2(A,B) { SE_##A, SE_##B }
13473 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13474 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13476 #define X(N, L, C) { N, S##N L }
13478 static struct neon_shape_info neon_shape_tab
[] =
13488 /* Bit masks used in type checking given instructions.
13489 'N_EQK' means the type must be the same as (or based on in some way) the key
13490 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13491 set, various other bits can be set as well in order to modify the meaning of
13492 the type constraint. */
13494 enum neon_type_mask
13518 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13519 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13520 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13521 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13522 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13523 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13524 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13525 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13526 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13527 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13528 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13530 N_MAX_NONSPECIAL
= N_P64
13533 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13535 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13536 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13537 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13538 #define N_S_32 (N_S8 | N_S16 | N_S32)
13539 #define N_F_16_32 (N_F16 | N_F32)
13540 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13541 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13542 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13543 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13545 /* Pass this as the first type argument to neon_check_type to ignore types
13547 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13549 /* Select a "shape" for the current instruction (describing register types or
13550 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13551 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13552 function of operand parsing, so this function doesn't need to be called.
13553 Shapes should be listed in order of decreasing length. */
13555 static enum neon_shape
13556 neon_select_shape (enum neon_shape shape
, ...)
13559 enum neon_shape first_shape
= shape
;
13561 /* Fix missing optional operands. FIXME: we don't know at this point how
13562 many arguments we should have, so this makes the assumption that we have
13563 > 1. This is true of all current Neon opcodes, I think, but may not be
13564 true in the future. */
13565 if (!inst
.operands
[1].present
)
13566 inst
.operands
[1] = inst
.operands
[0];
13568 va_start (ap
, shape
);
13570 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13575 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13577 if (!inst
.operands
[j
].present
)
13583 switch (neon_shape_tab
[shape
].el
[j
])
13585 /* If a .f16, .16, .u16, .s16 type specifier is given over
13586 a VFP single precision register operand, it's essentially
13587 means only half of the register is used.
13589 If the type specifier is given after the mnemonics, the
13590 information is stored in inst.vectype. If the type specifier
13591 is given after register operand, the information is stored
13592 in inst.operands[].vectype.
13594 When there is only one type specifier, and all the register
13595 operands are the same type of hardware register, the type
13596 specifier applies to all register operands.
13598 If no type specifier is given, the shape is inferred from
13599 operand information.
13602 vadd.f16 s0, s1, s2: NS_HHH
13603 vabs.f16 s0, s1: NS_HH
13604 vmov.f16 s0, r1: NS_HR
13605 vmov.f16 r0, s1: NS_RH
13606 vcvt.f16 r0, s1: NS_RH
13607 vcvt.f16.s32 s2, s2, #29: NS_HFI
13608 vcvt.f16.s32 s2, s2: NS_HF
13611 if (!(inst
.operands
[j
].isreg
13612 && inst
.operands
[j
].isvec
13613 && inst
.operands
[j
].issingle
13614 && !inst
.operands
[j
].isquad
13615 && ((inst
.vectype
.elems
== 1
13616 && inst
.vectype
.el
[0].size
== 16)
13617 || (inst
.vectype
.elems
> 1
13618 && inst
.vectype
.el
[j
].size
== 16)
13619 || (inst
.vectype
.elems
== 0
13620 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13621 && inst
.operands
[j
].vectype
.size
== 16))))
13626 if (!(inst
.operands
[j
].isreg
13627 && inst
.operands
[j
].isvec
13628 && inst
.operands
[j
].issingle
13629 && !inst
.operands
[j
].isquad
13630 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13631 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13632 || (inst
.vectype
.elems
== 0
13633 && (inst
.operands
[j
].vectype
.size
== 32
13634 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13639 if (!(inst
.operands
[j
].isreg
13640 && inst
.operands
[j
].isvec
13641 && !inst
.operands
[j
].isquad
13642 && !inst
.operands
[j
].issingle
))
13647 if (!(inst
.operands
[j
].isreg
13648 && !inst
.operands
[j
].isvec
))
13653 if (!(inst
.operands
[j
].isreg
13654 && inst
.operands
[j
].isvec
13655 && inst
.operands
[j
].isquad
13656 && !inst
.operands
[j
].issingle
))
13661 if (!(!inst
.operands
[j
].isreg
13662 && !inst
.operands
[j
].isscalar
))
13667 if (!(!inst
.operands
[j
].isreg
13668 && inst
.operands
[j
].isscalar
))
13678 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13679 /* We've matched all the entries in the shape table, and we don't
13680 have any left over operands which have not been matched. */
13686 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13687 first_error (_("invalid instruction shape"));
13692 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13693 means the Q bit should be set). */
13696 neon_quad (enum neon_shape shape
)
13698 return neon_shape_class
[shape
] == SC_QUAD
;
13702 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13705 /* Allow modification to be made to types which are constrained to be
13706 based on the key element, based on bits set alongside N_EQK. */
13707 if ((typebits
& N_EQK
) != 0)
13709 if ((typebits
& N_HLF
) != 0)
13711 else if ((typebits
& N_DBL
) != 0)
13713 if ((typebits
& N_SGN
) != 0)
13714 *g_type
= NT_signed
;
13715 else if ((typebits
& N_UNS
) != 0)
13716 *g_type
= NT_unsigned
;
13717 else if ((typebits
& N_INT
) != 0)
13718 *g_type
= NT_integer
;
13719 else if ((typebits
& N_FLT
) != 0)
13720 *g_type
= NT_float
;
13721 else if ((typebits
& N_SIZ
) != 0)
13722 *g_type
= NT_untyped
;
13726 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13727 operand type, i.e. the single type specified in a Neon instruction when it
13728 is the only one given. */
13730 static struct neon_type_el
13731 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13733 struct neon_type_el dest
= *key
;
13735 gas_assert ((thisarg
& N_EQK
) != 0);
13737 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13742 /* Convert Neon type and size into compact bitmask representation. */
13744 static enum neon_type_mask
13745 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13752 case 8: return N_8
;
13753 case 16: return N_16
;
13754 case 32: return N_32
;
13755 case 64: return N_64
;
13763 case 8: return N_I8
;
13764 case 16: return N_I16
;
13765 case 32: return N_I32
;
13766 case 64: return N_I64
;
13774 case 16: return N_F16
;
13775 case 32: return N_F32
;
13776 case 64: return N_F64
;
13784 case 8: return N_P8
;
13785 case 16: return N_P16
;
13786 case 64: return N_P64
;
13794 case 8: return N_S8
;
13795 case 16: return N_S16
;
13796 case 32: return N_S32
;
13797 case 64: return N_S64
;
13805 case 8: return N_U8
;
13806 case 16: return N_U16
;
13807 case 32: return N_U32
;
13808 case 64: return N_U64
;
13819 /* Convert compact Neon bitmask type representation to a type and size. Only
13820 handles the case where a single bit is set in the mask. */
13823 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13824 enum neon_type_mask mask
)
13826 if ((mask
& N_EQK
) != 0)
13829 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13831 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13833 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13835 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13840 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13842 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13843 *type
= NT_unsigned
;
13844 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13845 *type
= NT_integer
;
13846 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13847 *type
= NT_untyped
;
13848 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13850 else if ((mask
& (N_F_ALL
)) != 0)
13858 /* Modify a bitmask of allowed types. This is only needed for type
13862 modify_types_allowed (unsigned allowed
, unsigned mods
)
13865 enum neon_el_type type
;
13871 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13873 if (el_type_of_type_chk (&type
, &size
,
13874 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13876 neon_modify_type_size (mods
, &type
, &size
);
13877 destmask
|= type_chk_of_el_type (type
, size
);
13884 /* Check type and return type classification.
13885 The manual states (paraphrase): If one datatype is given, it indicates the
13887 - the second operand, if there is one
13888 - the operand, if there is no second operand
13889 - the result, if there are no operands.
13890 This isn't quite good enough though, so we use a concept of a "key" datatype
13891 which is set on a per-instruction basis, which is the one which matters when
13892 only one data type is written.
13893 Note: this function has side-effects (e.g. filling in missing operands). All
13894 Neon instructions should call it before performing bit encoding. */
13896 static struct neon_type_el
13897 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13900 unsigned i
, pass
, key_el
= 0;
13901 unsigned types
[NEON_MAX_TYPE_ELS
];
13902 enum neon_el_type k_type
= NT_invtype
;
13903 unsigned k_size
= -1u;
13904 struct neon_type_el badtype
= {NT_invtype
, -1};
13905 unsigned key_allowed
= 0;
13907 /* Optional registers in Neon instructions are always (not) in operand 1.
13908 Fill in the missing operand here, if it was omitted. */
13909 if (els
> 1 && !inst
.operands
[1].present
)
13910 inst
.operands
[1] = inst
.operands
[0];
13912 /* Suck up all the varargs. */
13914 for (i
= 0; i
< els
; i
++)
13916 unsigned thisarg
= va_arg (ap
, unsigned);
13917 if (thisarg
== N_IGNORE_TYPE
)
13922 types
[i
] = thisarg
;
13923 if ((thisarg
& N_KEY
) != 0)
13928 if (inst
.vectype
.elems
> 0)
13929 for (i
= 0; i
< els
; i
++)
13930 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13932 first_error (_("types specified in both the mnemonic and operands"));
13936 /* Duplicate inst.vectype elements here as necessary.
13937 FIXME: No idea if this is exactly the same as the ARM assembler,
13938 particularly when an insn takes one register and one non-register
13940 if (inst
.vectype
.elems
== 1 && els
> 1)
13943 inst
.vectype
.elems
= els
;
13944 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13945 for (j
= 0; j
< els
; j
++)
13947 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13950 else if (inst
.vectype
.elems
== 0 && els
> 0)
13953 /* No types were given after the mnemonic, so look for types specified
13954 after each operand. We allow some flexibility here; as long as the
13955 "key" operand has a type, we can infer the others. */
13956 for (j
= 0; j
< els
; j
++)
13957 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13958 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13960 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13962 for (j
= 0; j
< els
; j
++)
13963 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13964 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13969 first_error (_("operand types can't be inferred"));
13973 else if (inst
.vectype
.elems
!= els
)
13975 first_error (_("type specifier has the wrong number of parts"));
13979 for (pass
= 0; pass
< 2; pass
++)
13981 for (i
= 0; i
< els
; i
++)
13983 unsigned thisarg
= types
[i
];
13984 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13985 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13986 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13987 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13989 /* Decay more-specific signed & unsigned types to sign-insensitive
13990 integer types if sign-specific variants are unavailable. */
13991 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13992 && (types_allowed
& N_SU_ALL
) == 0)
13993 g_type
= NT_integer
;
13995 /* If only untyped args are allowed, decay any more specific types to
13996 them. Some instructions only care about signs for some element
13997 sizes, so handle that properly. */
13998 if (((types_allowed
& N_UNT
) == 0)
13999 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14000 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14001 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14002 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14003 g_type
= NT_untyped
;
14007 if ((thisarg
& N_KEY
) != 0)
14011 key_allowed
= thisarg
& ~N_KEY
;
14013 /* Check architecture constraint on FP16 extension. */
14015 && k_type
== NT_float
14016 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14018 inst
.error
= _(BAD_FP16
);
14025 if ((thisarg
& N_VFP
) != 0)
14027 enum neon_shape_el regshape
;
14028 unsigned regwidth
, match
;
14030 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14033 first_error (_("invalid instruction shape"));
14036 regshape
= neon_shape_tab
[ns
].el
[i
];
14037 regwidth
= neon_shape_el_size
[regshape
];
14039 /* In VFP mode, operands must match register widths. If we
14040 have a key operand, use its width, else use the width of
14041 the current operand. */
14047 /* FP16 will use a single precision register. */
14048 if (regwidth
== 32 && match
== 16)
14050 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14054 inst
.error
= _(BAD_FP16
);
14059 if (regwidth
!= match
)
14061 first_error (_("operand size must match register width"));
14066 if ((thisarg
& N_EQK
) == 0)
14068 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14070 if ((given_type
& types_allowed
) == 0)
14072 first_error (_("bad type in Neon instruction"));
14078 enum neon_el_type mod_k_type
= k_type
;
14079 unsigned mod_k_size
= k_size
;
14080 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14081 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14083 first_error (_("inconsistent types in Neon instruction"));
14091 return inst
.vectype
.el
[key_el
];
14094 /* Neon-style VFP instruction forwarding. */
14096 /* Thumb VFP instructions have 0xE in the condition field. */
14099 do_vfp_cond_or_thumb (void)
14104 inst
.instruction
|= 0xe0000000;
14106 inst
.instruction
|= inst
.cond
<< 28;
14109 /* Look up and encode a simple mnemonic, for use as a helper function for the
14110 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14111 etc. It is assumed that operand parsing has already been done, and that the
14112 operands are in the form expected by the given opcode (this isn't necessarily
14113 the same as the form in which they were parsed, hence some massaging must
14114 take place before this function is called).
14115 Checks current arch version against that in the looked-up opcode. */
14118 do_vfp_nsyn_opcode (const char *opname
)
14120 const struct asm_opcode
*opcode
;
14122 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14128 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14135 inst
.instruction
= opcode
->tvalue
;
14136 opcode
->tencode ();
14140 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14141 opcode
->aencode ();
14146 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14148 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14150 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14153 do_vfp_nsyn_opcode ("fadds");
14155 do_vfp_nsyn_opcode ("fsubs");
14157 /* ARMv8.2 fp16 instruction. */
14159 do_scalar_fp16_v82_encode ();
14164 do_vfp_nsyn_opcode ("faddd");
14166 do_vfp_nsyn_opcode ("fsubd");
14170 /* Check operand types to see if this is a VFP instruction, and if so call
14174 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14176 enum neon_shape rs
;
14177 struct neon_type_el et
;
14182 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14183 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14187 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14188 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14189 N_F_ALL
| N_KEY
| N_VFP
);
14196 if (et
.type
!= NT_invtype
)
14207 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14209 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14211 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14214 do_vfp_nsyn_opcode ("fmacs");
14216 do_vfp_nsyn_opcode ("fnmacs");
14218 /* ARMv8.2 fp16 instruction. */
14220 do_scalar_fp16_v82_encode ();
14225 do_vfp_nsyn_opcode ("fmacd");
14227 do_vfp_nsyn_opcode ("fnmacd");
14232 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14234 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14236 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14239 do_vfp_nsyn_opcode ("ffmas");
14241 do_vfp_nsyn_opcode ("ffnmas");
14243 /* ARMv8.2 fp16 instruction. */
14245 do_scalar_fp16_v82_encode ();
14250 do_vfp_nsyn_opcode ("ffmad");
14252 do_vfp_nsyn_opcode ("ffnmad");
14257 do_vfp_nsyn_mul (enum neon_shape rs
)
14259 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14261 do_vfp_nsyn_opcode ("fmuls");
14263 /* ARMv8.2 fp16 instruction. */
14265 do_scalar_fp16_v82_encode ();
14268 do_vfp_nsyn_opcode ("fmuld");
14272 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14274 int is_neg
= (inst
.instruction
& 0x80) != 0;
14275 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14277 if (rs
== NS_FF
|| rs
== NS_HH
)
14280 do_vfp_nsyn_opcode ("fnegs");
14282 do_vfp_nsyn_opcode ("fabss");
14284 /* ARMv8.2 fp16 instruction. */
14286 do_scalar_fp16_v82_encode ();
14291 do_vfp_nsyn_opcode ("fnegd");
14293 do_vfp_nsyn_opcode ("fabsd");
14297 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14298 insns belong to Neon, and are handled elsewhere. */
14301 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14303 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14307 do_vfp_nsyn_opcode ("fldmdbs");
14309 do_vfp_nsyn_opcode ("fldmias");
14314 do_vfp_nsyn_opcode ("fstmdbs");
14316 do_vfp_nsyn_opcode ("fstmias");
14321 do_vfp_nsyn_sqrt (void)
14323 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14324 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14326 if (rs
== NS_FF
|| rs
== NS_HH
)
14328 do_vfp_nsyn_opcode ("fsqrts");
14330 /* ARMv8.2 fp16 instruction. */
14332 do_scalar_fp16_v82_encode ();
14335 do_vfp_nsyn_opcode ("fsqrtd");
14339 do_vfp_nsyn_div (void)
14341 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14342 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14343 N_F_ALL
| N_KEY
| N_VFP
);
14345 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14347 do_vfp_nsyn_opcode ("fdivs");
14349 /* ARMv8.2 fp16 instruction. */
14351 do_scalar_fp16_v82_encode ();
14354 do_vfp_nsyn_opcode ("fdivd");
14358 do_vfp_nsyn_nmul (void)
14360 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14361 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14362 N_F_ALL
| N_KEY
| N_VFP
);
14364 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14366 NEON_ENCODE (SINGLE
, inst
);
14367 do_vfp_sp_dyadic ();
14369 /* ARMv8.2 fp16 instruction. */
14371 do_scalar_fp16_v82_encode ();
14375 NEON_ENCODE (DOUBLE
, inst
);
14376 do_vfp_dp_rd_rn_rm ();
14378 do_vfp_cond_or_thumb ();
14383 do_vfp_nsyn_cmp (void)
14385 enum neon_shape rs
;
14386 if (inst
.operands
[1].isreg
)
14388 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14389 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14391 if (rs
== NS_FF
|| rs
== NS_HH
)
14393 NEON_ENCODE (SINGLE
, inst
);
14394 do_vfp_sp_monadic ();
14398 NEON_ENCODE (DOUBLE
, inst
);
14399 do_vfp_dp_rd_rm ();
14404 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14405 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14407 switch (inst
.instruction
& 0x0fffffff)
14410 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14413 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14419 if (rs
== NS_FI
|| rs
== NS_HI
)
14421 NEON_ENCODE (SINGLE
, inst
);
14422 do_vfp_sp_compare_z ();
14426 NEON_ENCODE (DOUBLE
, inst
);
14430 do_vfp_cond_or_thumb ();
14432 /* ARMv8.2 fp16 instruction. */
14433 if (rs
== NS_HI
|| rs
== NS_HH
)
14434 do_scalar_fp16_v82_encode ();
14438 nsyn_insert_sp (void)
14440 inst
.operands
[1] = inst
.operands
[0];
14441 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14442 inst
.operands
[0].reg
= REG_SP
;
14443 inst
.operands
[0].isreg
= 1;
14444 inst
.operands
[0].writeback
= 1;
14445 inst
.operands
[0].present
= 1;
14449 do_vfp_nsyn_push (void)
14453 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14454 _("register list must contain at least 1 and at most 16 "
14457 if (inst
.operands
[1].issingle
)
14458 do_vfp_nsyn_opcode ("fstmdbs");
14460 do_vfp_nsyn_opcode ("fstmdbd");
14464 do_vfp_nsyn_pop (void)
14468 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14469 _("register list must contain at least 1 and at most 16 "
14472 if (inst
.operands
[1].issingle
)
14473 do_vfp_nsyn_opcode ("fldmias");
14475 do_vfp_nsyn_opcode ("fldmiad");
14478 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14479 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14482 neon_dp_fixup (struct arm_it
* insn
)
14484 unsigned int i
= insn
->instruction
;
14489 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14500 insn
->instruction
= i
;
14503 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14507 neon_logbits (unsigned x
)
14509 return ffs (x
) - 4;
14512 #define LOW4(R) ((R) & 0xf)
14513 #define HI1(R) (((R) >> 4) & 1)
14515 /* Encode insns with bit pattern:
14517 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14518 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14520 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14521 different meaning for some instruction. */
14524 neon_three_same (int isquad
, int ubit
, int size
)
14526 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14527 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14528 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14529 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14530 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14531 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14532 inst
.instruction
|= (isquad
!= 0) << 6;
14533 inst
.instruction
|= (ubit
!= 0) << 24;
14535 inst
.instruction
|= neon_logbits (size
) << 20;
14537 neon_dp_fixup (&inst
);
14540 /* Encode instructions of the form:
14542 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14543 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14545 Don't write size if SIZE == -1. */
14548 neon_two_same (int qbit
, int ubit
, int size
)
14550 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14551 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14552 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14553 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14554 inst
.instruction
|= (qbit
!= 0) << 6;
14555 inst
.instruction
|= (ubit
!= 0) << 24;
14558 inst
.instruction
|= neon_logbits (size
) << 18;
14560 neon_dp_fixup (&inst
);
14563 /* Neon instruction encoders, in approximate order of appearance. */
14566 do_neon_dyadic_i_su (void)
14568 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14569 struct neon_type_el et
= neon_check_type (3, rs
,
14570 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14571 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14575 do_neon_dyadic_i64_su (void)
14577 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14578 struct neon_type_el et
= neon_check_type (3, rs
,
14579 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14580 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14584 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14587 unsigned size
= et
.size
>> 3;
14588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14590 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14591 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14592 inst
.instruction
|= (isquad
!= 0) << 6;
14593 inst
.instruction
|= immbits
<< 16;
14594 inst
.instruction
|= (size
>> 3) << 7;
14595 inst
.instruction
|= (size
& 0x7) << 19;
14597 inst
.instruction
|= (uval
!= 0) << 24;
14599 neon_dp_fixup (&inst
);
14603 do_neon_shl_imm (void)
14605 if (!inst
.operands
[2].isreg
)
14607 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14608 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14609 int imm
= inst
.operands
[2].imm
;
14611 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14612 _("immediate out of range for shift"));
14613 NEON_ENCODE (IMMED
, inst
);
14614 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14618 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14619 struct neon_type_el et
= neon_check_type (3, rs
,
14620 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14623 /* VSHL/VQSHL 3-register variants have syntax such as:
14625 whereas other 3-register operations encoded by neon_three_same have
14628 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14630 tmp
= inst
.operands
[2].reg
;
14631 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14632 inst
.operands
[1].reg
= tmp
;
14633 NEON_ENCODE (INTEGER
, inst
);
14634 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14639 do_neon_qshl_imm (void)
14641 if (!inst
.operands
[2].isreg
)
14643 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14644 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14645 int imm
= inst
.operands
[2].imm
;
14647 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14648 _("immediate out of range for shift"));
14649 NEON_ENCODE (IMMED
, inst
);
14650 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14654 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14655 struct neon_type_el et
= neon_check_type (3, rs
,
14656 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14659 /* See note in do_neon_shl_imm. */
14660 tmp
= inst
.operands
[2].reg
;
14661 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14662 inst
.operands
[1].reg
= tmp
;
14663 NEON_ENCODE (INTEGER
, inst
);
14664 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14669 do_neon_rshl (void)
14671 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14672 struct neon_type_el et
= neon_check_type (3, rs
,
14673 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14676 tmp
= inst
.operands
[2].reg
;
14677 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14678 inst
.operands
[1].reg
= tmp
;
14679 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14683 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14685 /* Handle .I8 pseudo-instructions. */
14688 /* Unfortunately, this will make everything apart from zero out-of-range.
14689 FIXME is this the intended semantics? There doesn't seem much point in
14690 accepting .I8 if so. */
14691 immediate
|= immediate
<< 8;
14697 if (immediate
== (immediate
& 0x000000ff))
14699 *immbits
= immediate
;
14702 else if (immediate
== (immediate
& 0x0000ff00))
14704 *immbits
= immediate
>> 8;
14707 else if (immediate
== (immediate
& 0x00ff0000))
14709 *immbits
= immediate
>> 16;
14712 else if (immediate
== (immediate
& 0xff000000))
14714 *immbits
= immediate
>> 24;
14717 if ((immediate
& 0xffff) != (immediate
>> 16))
14718 goto bad_immediate
;
14719 immediate
&= 0xffff;
14722 if (immediate
== (immediate
& 0x000000ff))
14724 *immbits
= immediate
;
14727 else if (immediate
== (immediate
& 0x0000ff00))
14729 *immbits
= immediate
>> 8;
14734 first_error (_("immediate value out of range"));
14739 do_neon_logic (void)
14741 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14743 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14744 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14745 /* U bit and size field were set as part of the bitmask. */
14746 NEON_ENCODE (INTEGER
, inst
);
14747 neon_three_same (neon_quad (rs
), 0, -1);
14751 const int three_ops_form
= (inst
.operands
[2].present
14752 && !inst
.operands
[2].isreg
);
14753 const int immoperand
= (three_ops_form
? 2 : 1);
14754 enum neon_shape rs
= (three_ops_form
14755 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14756 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14757 struct neon_type_el et
= neon_check_type (2, rs
,
14758 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14759 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14763 if (et
.type
== NT_invtype
)
14766 if (three_ops_form
)
14767 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14768 _("first and second operands shall be the same register"));
14770 NEON_ENCODE (IMMED
, inst
);
14772 immbits
= inst
.operands
[immoperand
].imm
;
14775 /* .i64 is a pseudo-op, so the immediate must be a repeating
14777 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14778 inst
.operands
[immoperand
].reg
: 0))
14780 /* Set immbits to an invalid constant. */
14781 immbits
= 0xdeadbeef;
14788 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14792 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14796 /* Pseudo-instruction for VBIC. */
14797 neon_invert_size (&immbits
, 0, et
.size
);
14798 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14802 /* Pseudo-instruction for VORR. */
14803 neon_invert_size (&immbits
, 0, et
.size
);
14804 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14814 inst
.instruction
|= neon_quad (rs
) << 6;
14815 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14816 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14817 inst
.instruction
|= cmode
<< 8;
14818 neon_write_immbits (immbits
);
14820 neon_dp_fixup (&inst
);
14825 do_neon_bitfield (void)
14827 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14828 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14829 neon_three_same (neon_quad (rs
), 0, -1);
14833 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14836 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14837 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14839 if (et
.type
== NT_float
)
14841 NEON_ENCODE (FLOAT
, inst
);
14842 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14846 NEON_ENCODE (INTEGER
, inst
);
14847 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14852 do_neon_dyadic_if_su (void)
14854 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14858 do_neon_dyadic_if_su_d (void)
14860 /* This version only allow D registers, but that constraint is enforced during
14861 operand parsing so we don't need to do anything extra here. */
14862 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14866 do_neon_dyadic_if_i_d (void)
14868 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14869 affected if we specify unsigned args. */
14870 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14873 enum vfp_or_neon_is_neon_bits
14876 NEON_CHECK_ARCH
= 2,
14877 NEON_CHECK_ARCH8
= 4
14880 /* Call this function if an instruction which may have belonged to the VFP or
14881 Neon instruction sets, but turned out to be a Neon instruction (due to the
14882 operand types involved, etc.). We have to check and/or fix-up a couple of
14885 - Make sure the user hasn't attempted to make a Neon instruction
14887 - Alter the value in the condition code field if necessary.
14888 - Make sure that the arch supports Neon instructions.
14890 Which of these operations take place depends on bits from enum
14891 vfp_or_neon_is_neon_bits.
14893 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14894 current instruction's condition is COND_ALWAYS, the condition field is
14895 changed to inst.uncond_value. This is necessary because instructions shared
14896 between VFP and Neon may be conditional for the VFP variants only, and the
14897 unconditional Neon version must have, e.g., 0xF in the condition field. */
14900 vfp_or_neon_is_neon (unsigned check
)
14902 /* Conditions are always legal in Thumb mode (IT blocks). */
14903 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14905 if (inst
.cond
!= COND_ALWAYS
)
14907 first_error (_(BAD_COND
));
14910 if (inst
.uncond_value
!= -1)
14911 inst
.instruction
|= inst
.uncond_value
<< 28;
14914 if ((check
& NEON_CHECK_ARCH
)
14915 && !mark_feature_used (&fpu_neon_ext_v1
))
14917 first_error (_(BAD_FPU
));
14921 if ((check
& NEON_CHECK_ARCH8
)
14922 && !mark_feature_used (&fpu_neon_ext_armv8
))
14924 first_error (_(BAD_FPU
));
14932 do_neon_addsub_if_i (void)
14934 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14937 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14940 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14941 affected if we specify unsigned args. */
14942 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14945 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14947 V<op> A,B (A is operand 0, B is operand 2)
14952 so handle that case specially. */
14955 neon_exchange_operands (void)
14957 if (inst
.operands
[1].present
)
14959 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14961 /* Swap operands[1] and operands[2]. */
14962 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14963 inst
.operands
[1] = inst
.operands
[2];
14964 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14969 inst
.operands
[1] = inst
.operands
[2];
14970 inst
.operands
[2] = inst
.operands
[0];
14975 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14977 if (inst
.operands
[2].isreg
)
14980 neon_exchange_operands ();
14981 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14985 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14986 struct neon_type_el et
= neon_check_type (2, rs
,
14987 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14989 NEON_ENCODE (IMMED
, inst
);
14990 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14991 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14992 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14993 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14994 inst
.instruction
|= neon_quad (rs
) << 6;
14995 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14996 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14998 neon_dp_fixup (&inst
);
15005 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15009 do_neon_cmp_inv (void)
15011 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15017 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15020 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15021 scalars, which are encoded in 5 bits, M : Rm.
15022 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15023 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15027 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15029 unsigned regno
= NEON_SCALAR_REG (scalar
);
15030 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15035 if (regno
> 7 || elno
> 3)
15037 return regno
| (elno
<< 3);
15040 if (regno
> 15 || elno
> 1)
15042 return regno
| (elno
<< 4);
15046 first_error (_("scalar out of range for multiply instruction"));
15052 /* Encode multiply / multiply-accumulate scalar instructions. */
15055 neon_mul_mac (struct neon_type_el et
, int ubit
)
15059 /* Give a more helpful error message if we have an invalid type. */
15060 if (et
.type
== NT_invtype
)
15063 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15064 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15065 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15066 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15067 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15068 inst
.instruction
|= LOW4 (scalar
);
15069 inst
.instruction
|= HI1 (scalar
) << 5;
15070 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15071 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15072 inst
.instruction
|= (ubit
!= 0) << 24;
15074 neon_dp_fixup (&inst
);
15078 do_neon_mac_maybe_scalar (void)
15080 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15083 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15086 if (inst
.operands
[2].isscalar
)
15088 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15089 struct neon_type_el et
= neon_check_type (3, rs
,
15090 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15091 NEON_ENCODE (SCALAR
, inst
);
15092 neon_mul_mac (et
, neon_quad (rs
));
15096 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15097 affected if we specify unsigned args. */
15098 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15103 do_neon_fmac (void)
15105 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15108 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15111 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15117 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15118 struct neon_type_el et
= neon_check_type (3, rs
,
15119 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15120 neon_three_same (neon_quad (rs
), 0, et
.size
);
15123 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15124 same types as the MAC equivalents. The polynomial type for this instruction
15125 is encoded the same as the integer type. */
15130 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15133 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15136 if (inst
.operands
[2].isscalar
)
15137 do_neon_mac_maybe_scalar ();
15139 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15143 do_neon_qdmulh (void)
15145 if (inst
.operands
[2].isscalar
)
15147 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15148 struct neon_type_el et
= neon_check_type (3, rs
,
15149 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15150 NEON_ENCODE (SCALAR
, inst
);
15151 neon_mul_mac (et
, neon_quad (rs
));
15155 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15156 struct neon_type_el et
= neon_check_type (3, rs
,
15157 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15158 NEON_ENCODE (INTEGER
, inst
);
15159 /* The U bit (rounding) comes from bit mask. */
15160 neon_three_same (neon_quad (rs
), 0, et
.size
);
15165 do_neon_qrdmlah (void)
15167 /* Check we're on the correct architecture. */
15168 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15170 _("instruction form not available on this architecture.");
15171 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15173 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15174 record_feature_use (&fpu_neon_ext_v8_1
);
15177 if (inst
.operands
[2].isscalar
)
15179 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15180 struct neon_type_el et
= neon_check_type (3, rs
,
15181 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15182 NEON_ENCODE (SCALAR
, inst
);
15183 neon_mul_mac (et
, neon_quad (rs
));
15187 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15188 struct neon_type_el et
= neon_check_type (3, rs
,
15189 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15190 NEON_ENCODE (INTEGER
, inst
);
15191 /* The U bit (rounding) comes from bit mask. */
15192 neon_three_same (neon_quad (rs
), 0, et
.size
);
15197 do_neon_fcmp_absolute (void)
15199 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15200 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15201 N_F_16_32
| N_KEY
);
15202 /* Size field comes from bit mask. */
15203 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15207 do_neon_fcmp_absolute_inv (void)
15209 neon_exchange_operands ();
15210 do_neon_fcmp_absolute ();
15214 do_neon_step (void)
15216 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15217 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15218 N_F_16_32
| N_KEY
);
15219 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15223 do_neon_abs_neg (void)
15225 enum neon_shape rs
;
15226 struct neon_type_el et
;
15228 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15231 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15234 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15235 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15238 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15241 inst
.instruction
|= neon_quad (rs
) << 6;
15242 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15243 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15245 neon_dp_fixup (&inst
);
15251 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15252 struct neon_type_el et
= neon_check_type (2, rs
,
15253 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15254 int imm
= inst
.operands
[2].imm
;
15255 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15256 _("immediate out of range for insert"));
15257 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15263 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15264 struct neon_type_el et
= neon_check_type (2, rs
,
15265 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15266 int imm
= inst
.operands
[2].imm
;
15267 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15268 _("immediate out of range for insert"));
15269 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15273 do_neon_qshlu_imm (void)
15275 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15276 struct neon_type_el et
= neon_check_type (2, rs
,
15277 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15278 int imm
= inst
.operands
[2].imm
;
15279 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15280 _("immediate out of range for shift"));
15281 /* Only encodes the 'U present' variant of the instruction.
15282 In this case, signed types have OP (bit 8) set to 0.
15283 Unsigned types have OP set to 1. */
15284 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15285 /* The rest of the bits are the same as other immediate shifts. */
15286 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15290 do_neon_qmovn (void)
15292 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15293 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15294 /* Saturating move where operands can be signed or unsigned, and the
15295 destination has the same signedness. */
15296 NEON_ENCODE (INTEGER
, inst
);
15297 if (et
.type
== NT_unsigned
)
15298 inst
.instruction
|= 0xc0;
15300 inst
.instruction
|= 0x80;
15301 neon_two_same (0, 1, et
.size
/ 2);
15305 do_neon_qmovun (void)
15307 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15308 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15309 /* Saturating move with unsigned results. Operands must be signed. */
15310 NEON_ENCODE (INTEGER
, inst
);
15311 neon_two_same (0, 1, et
.size
/ 2);
15315 do_neon_rshift_sat_narrow (void)
15317 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15318 or unsigned. If operands are unsigned, results must also be unsigned. */
15319 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15320 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15321 int imm
= inst
.operands
[2].imm
;
15322 /* This gets the bounds check, size encoding and immediate bits calculation
15326 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15327 VQMOVN.I<size> <Dd>, <Qm>. */
15330 inst
.operands
[2].present
= 0;
15331 inst
.instruction
= N_MNEM_vqmovn
;
15336 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15337 _("immediate out of range"));
15338 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15342 do_neon_rshift_sat_narrow_u (void)
15344 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15345 or unsigned. If operands are unsigned, results must also be unsigned. */
15346 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15347 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15348 int imm
= inst
.operands
[2].imm
;
15349 /* This gets the bounds check, size encoding and immediate bits calculation
15353 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15354 VQMOVUN.I<size> <Dd>, <Qm>. */
15357 inst
.operands
[2].present
= 0;
15358 inst
.instruction
= N_MNEM_vqmovun
;
15363 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15364 _("immediate out of range"));
15365 /* FIXME: The manual is kind of unclear about what value U should have in
15366 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15368 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15372 do_neon_movn (void)
15374 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15375 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15376 NEON_ENCODE (INTEGER
, inst
);
15377 neon_two_same (0, 1, et
.size
/ 2);
15381 do_neon_rshift_narrow (void)
15383 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15384 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15385 int imm
= inst
.operands
[2].imm
;
15386 /* This gets the bounds check, size encoding and immediate bits calculation
15390 /* If immediate is zero then we are a pseudo-instruction for
15391 VMOVN.I<size> <Dd>, <Qm> */
15394 inst
.operands
[2].present
= 0;
15395 inst
.instruction
= N_MNEM_vmovn
;
15400 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15401 _("immediate out of range for narrowing operation"));
15402 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15406 do_neon_shll (void)
15408 /* FIXME: Type checking when lengthening. */
15409 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15410 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15411 unsigned imm
= inst
.operands
[2].imm
;
15413 if (imm
== et
.size
)
15415 /* Maximum shift variant. */
15416 NEON_ENCODE (INTEGER
, inst
);
15417 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15418 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15419 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15420 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15421 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15423 neon_dp_fixup (&inst
);
15427 /* A more-specific type check for non-max versions. */
15428 et
= neon_check_type (2, NS_QDI
,
15429 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15430 NEON_ENCODE (IMMED
, inst
);
15431 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15435 /* Check the various types for the VCVT instruction, and return which version
15436 the current instruction is. */
15438 #define CVT_FLAVOUR_VAR \
15439 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15440 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15441 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15442 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15443 /* Half-precision conversions. */ \
15444 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15445 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15446 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15447 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15448 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15449 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15450 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15451 Compared with single/double precision variants, only the co-processor \
15452 field is different, so the encoding flow is reused here. */ \
15453 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15454 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15455 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15456 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15457 /* VFP instructions. */ \
15458 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15459 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15460 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15461 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15462 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15463 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15464 /* VFP instructions with bitshift. */ \
15465 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15466 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15467 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15468 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15469 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15470 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15471 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15472 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15474 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15475 neon_cvt_flavour_##C,
15477 /* The different types of conversions we can do. */
15478 enum neon_cvt_flavour
15481 neon_cvt_flavour_invalid
,
15482 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15487 static enum neon_cvt_flavour
15488 get_neon_cvt_flavour (enum neon_shape rs
)
15490 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15491 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15492 if (et.type != NT_invtype) \
15494 inst.error = NULL; \
15495 return (neon_cvt_flavour_##C); \
15498 struct neon_type_el et
;
15499 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15500 || rs
== NS_FF
) ? N_VFP
: 0;
15501 /* The instruction versions which take an immediate take one register
15502 argument, which is extended to the width of the full register. Thus the
15503 "source" and "destination" registers must have the same width. Hack that
15504 here by making the size equal to the key (wider, in this case) operand. */
15505 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15509 return neon_cvt_flavour_invalid
;
15524 /* Neon-syntax VFP conversions. */
15527 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15529 const char *opname
= 0;
15531 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15532 || rs
== NS_FHI
|| rs
== NS_HFI
)
15534 /* Conversions with immediate bitshift. */
15535 const char *enc
[] =
15537 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15543 if (flavour
< (int) ARRAY_SIZE (enc
))
15545 opname
= enc
[flavour
];
15546 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15547 _("operands 0 and 1 must be the same register"));
15548 inst
.operands
[1] = inst
.operands
[2];
15549 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15554 /* Conversions without bitshift. */
15555 const char *enc
[] =
15557 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15563 if (flavour
< (int) ARRAY_SIZE (enc
))
15564 opname
= enc
[flavour
];
15568 do_vfp_nsyn_opcode (opname
);
15570 /* ARMv8.2 fp16 VCVT instruction. */
15571 if (flavour
== neon_cvt_flavour_s32_f16
15572 || flavour
== neon_cvt_flavour_u32_f16
15573 || flavour
== neon_cvt_flavour_f16_u32
15574 || flavour
== neon_cvt_flavour_f16_s32
)
15575 do_scalar_fp16_v82_encode ();
15579 do_vfp_nsyn_cvtz (void)
15581 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15582 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15583 const char *enc
[] =
15585 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15591 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15592 do_vfp_nsyn_opcode (enc
[flavour
]);
15596 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15597 enum neon_cvt_mode mode
)
15602 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15603 D register operands. */
15604 if (flavour
== neon_cvt_flavour_s32_f64
15605 || flavour
== neon_cvt_flavour_u32_f64
)
15606 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15609 if (flavour
== neon_cvt_flavour_s32_f16
15610 || flavour
== neon_cvt_flavour_u32_f16
)
15611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15614 set_it_insn_type (OUTSIDE_IT_INSN
);
15618 case neon_cvt_flavour_s32_f64
:
15622 case neon_cvt_flavour_s32_f32
:
15626 case neon_cvt_flavour_s32_f16
:
15630 case neon_cvt_flavour_u32_f64
:
15634 case neon_cvt_flavour_u32_f32
:
15638 case neon_cvt_flavour_u32_f16
:
15643 first_error (_("invalid instruction shape"));
15649 case neon_cvt_mode_a
: rm
= 0; break;
15650 case neon_cvt_mode_n
: rm
= 1; break;
15651 case neon_cvt_mode_p
: rm
= 2; break;
15652 case neon_cvt_mode_m
: rm
= 3; break;
15653 default: first_error (_("invalid rounding mode")); return;
15656 NEON_ENCODE (FPV8
, inst
);
15657 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15658 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15659 inst
.instruction
|= sz
<< 8;
15661 /* ARMv8.2 fp16 VCVT instruction. */
15662 if (flavour
== neon_cvt_flavour_s32_f16
15663 ||flavour
== neon_cvt_flavour_u32_f16
)
15664 do_scalar_fp16_v82_encode ();
15665 inst
.instruction
|= op
<< 7;
15666 inst
.instruction
|= rm
<< 16;
15667 inst
.instruction
|= 0xf0000000;
15668 inst
.is_neon
= TRUE
;
15672 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15674 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15675 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15676 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15678 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15680 if (flavour
== neon_cvt_flavour_invalid
)
15683 /* PR11109: Handle round-to-zero for VCVT conversions. */
15684 if (mode
== neon_cvt_mode_z
15685 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15686 && (flavour
== neon_cvt_flavour_s16_f16
15687 || flavour
== neon_cvt_flavour_u16_f16
15688 || flavour
== neon_cvt_flavour_s32_f32
15689 || flavour
== neon_cvt_flavour_u32_f32
15690 || flavour
== neon_cvt_flavour_s32_f64
15691 || flavour
== neon_cvt_flavour_u32_f64
)
15692 && (rs
== NS_FD
|| rs
== NS_FF
))
15694 do_vfp_nsyn_cvtz ();
15698 /* ARMv8.2 fp16 VCVT conversions. */
15699 if (mode
== neon_cvt_mode_z
15700 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15701 && (flavour
== neon_cvt_flavour_s32_f16
15702 || flavour
== neon_cvt_flavour_u32_f16
)
15705 do_vfp_nsyn_cvtz ();
15706 do_scalar_fp16_v82_encode ();
15710 /* VFP rather than Neon conversions. */
15711 if (flavour
>= neon_cvt_flavour_first_fp
)
15713 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15714 do_vfp_nsyn_cvt (rs
, flavour
);
15716 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15727 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15728 0x0000100, 0x1000100, 0x0, 0x1000000};
15730 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15733 /* Fixed-point conversion with #0 immediate is encoded as an
15734 integer conversion. */
15735 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15737 NEON_ENCODE (IMMED
, inst
);
15738 if (flavour
!= neon_cvt_flavour_invalid
)
15739 inst
.instruction
|= enctab
[flavour
];
15740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15742 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15743 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15744 inst
.instruction
|= neon_quad (rs
) << 6;
15745 inst
.instruction
|= 1 << 21;
15746 if (flavour
< neon_cvt_flavour_s16_f16
)
15748 inst
.instruction
|= 1 << 21;
15749 immbits
= 32 - inst
.operands
[2].imm
;
15750 inst
.instruction
|= immbits
<< 16;
15754 inst
.instruction
|= 3 << 20;
15755 immbits
= 16 - inst
.operands
[2].imm
;
15756 inst
.instruction
|= immbits
<< 16;
15757 inst
.instruction
&= ~(1 << 9);
15760 neon_dp_fixup (&inst
);
15766 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15768 NEON_ENCODE (FLOAT
, inst
);
15769 set_it_insn_type (OUTSIDE_IT_INSN
);
15771 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15778 inst
.instruction
|= neon_quad (rs
) << 6;
15779 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15780 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15781 inst
.instruction
|= mode
<< 8;
15782 if (flavour
== neon_cvt_flavour_u16_f16
15783 || flavour
== neon_cvt_flavour_s16_f16
)
15784 /* Mask off the original size bits and reencode them. */
15785 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15788 inst
.instruction
|= 0xfc000000;
15790 inst
.instruction
|= 0xf0000000;
15796 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15797 0x100, 0x180, 0x0, 0x080};
15799 NEON_ENCODE (INTEGER
, inst
);
15801 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15804 if (flavour
!= neon_cvt_flavour_invalid
)
15805 inst
.instruction
|= enctab
[flavour
];
15807 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15808 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15809 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15810 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15811 inst
.instruction
|= neon_quad (rs
) << 6;
15812 if (flavour
>= neon_cvt_flavour_s16_f16
15813 && flavour
<= neon_cvt_flavour_f16_u16
)
15814 /* Half precision. */
15815 inst
.instruction
|= 1 << 18;
15817 inst
.instruction
|= 2 << 18;
15819 neon_dp_fixup (&inst
);
15824 /* Half-precision conversions for Advanced SIMD -- neon. */
15829 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15831 as_bad (_("operand size must match register width"));
15836 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15838 as_bad (_("operand size must match register width"));
15843 inst
.instruction
= 0x3b60600;
15845 inst
.instruction
= 0x3b60700;
15847 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15848 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15849 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15850 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15851 neon_dp_fixup (&inst
);
15855 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15856 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15857 do_vfp_nsyn_cvt (rs
, flavour
);
15859 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15864 do_neon_cvtr (void)
15866 do_neon_cvt_1 (neon_cvt_mode_x
);
15872 do_neon_cvt_1 (neon_cvt_mode_z
);
15876 do_neon_cvta (void)
15878 do_neon_cvt_1 (neon_cvt_mode_a
);
15882 do_neon_cvtn (void)
15884 do_neon_cvt_1 (neon_cvt_mode_n
);
15888 do_neon_cvtp (void)
15890 do_neon_cvt_1 (neon_cvt_mode_p
);
15894 do_neon_cvtm (void)
15896 do_neon_cvt_1 (neon_cvt_mode_m
);
15900 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15903 mark_feature_used (&fpu_vfp_ext_armv8
);
15905 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15906 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15907 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15908 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15909 inst
.instruction
|= to
? 0x10000 : 0;
15910 inst
.instruction
|= t
? 0x80 : 0;
15911 inst
.instruction
|= is_double
? 0x100 : 0;
15912 do_vfp_cond_or_thumb ();
15916 do_neon_cvttb_1 (bfd_boolean t
)
15918 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15919 NS_DF
, NS_DH
, NS_NULL
);
15923 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15926 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15928 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15931 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15933 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15935 /* The VCVTB and VCVTT instructions with D-register operands
15936 don't work for SP only targets. */
15937 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15941 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15943 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15945 /* The VCVTB and VCVTT instructions with D-register operands
15946 don't work for SP only targets. */
15947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15951 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15958 do_neon_cvtb (void)
15960 do_neon_cvttb_1 (FALSE
);
15965 do_neon_cvtt (void)
15967 do_neon_cvttb_1 (TRUE
);
15971 neon_move_immediate (void)
15973 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15974 struct neon_type_el et
= neon_check_type (2, rs
,
15975 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15976 unsigned immlo
, immhi
= 0, immbits
;
15977 int op
, cmode
, float_p
;
15979 constraint (et
.type
== NT_invtype
,
15980 _("operand size must be specified for immediate VMOV"));
15982 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15983 op
= (inst
.instruction
& (1 << 5)) != 0;
15985 immlo
= inst
.operands
[1].imm
;
15986 if (inst
.operands
[1].regisimm
)
15987 immhi
= inst
.operands
[1].reg
;
15989 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15990 _("immediate has bits set outside the operand size"));
15992 float_p
= inst
.operands
[1].immisfloat
;
15994 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15995 et
.size
, et
.type
)) == FAIL
)
15997 /* Invert relevant bits only. */
15998 neon_invert_size (&immlo
, &immhi
, et
.size
);
15999 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16000 with one or the other; those cases are caught by
16001 neon_cmode_for_move_imm. */
16003 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16004 &op
, et
.size
, et
.type
)) == FAIL
)
16006 first_error (_("immediate out of range"));
16011 inst
.instruction
&= ~(1 << 5);
16012 inst
.instruction
|= op
<< 5;
16014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16016 inst
.instruction
|= neon_quad (rs
) << 6;
16017 inst
.instruction
|= cmode
<< 8;
16019 neon_write_immbits (immbits
);
16025 if (inst
.operands
[1].isreg
)
16027 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16029 NEON_ENCODE (INTEGER
, inst
);
16030 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16031 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16032 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16033 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16034 inst
.instruction
|= neon_quad (rs
) << 6;
16038 NEON_ENCODE (IMMED
, inst
);
16039 neon_move_immediate ();
16042 neon_dp_fixup (&inst
);
16045 /* Encode instructions of form:
16047 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16048 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16051 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16053 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16054 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16055 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16056 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16057 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16058 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16059 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16060 inst
.instruction
|= neon_logbits (size
) << 20;
16062 neon_dp_fixup (&inst
);
16066 do_neon_dyadic_long (void)
16068 /* FIXME: Type checking for lengthening op. */
16069 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16070 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16071 neon_mixed_length (et
, et
.size
);
16075 do_neon_abal (void)
16077 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16078 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16079 neon_mixed_length (et
, et
.size
);
16083 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16085 if (inst
.operands
[2].isscalar
)
16087 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16088 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16089 NEON_ENCODE (SCALAR
, inst
);
16090 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16094 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16095 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16096 NEON_ENCODE (INTEGER
, inst
);
16097 neon_mixed_length (et
, et
.size
);
16102 do_neon_mac_maybe_scalar_long (void)
16104 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16108 do_neon_dyadic_wide (void)
16110 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16111 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16112 neon_mixed_length (et
, et
.size
);
16116 do_neon_dyadic_narrow (void)
16118 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16119 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16120 /* Operand sign is unimportant, and the U bit is part of the opcode,
16121 so force the operand type to integer. */
16122 et
.type
= NT_integer
;
16123 neon_mixed_length (et
, et
.size
/ 2);
16127 do_neon_mul_sat_scalar_long (void)
16129 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16133 do_neon_vmull (void)
16135 if (inst
.operands
[2].isscalar
)
16136 do_neon_mac_maybe_scalar_long ();
16139 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16140 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16142 if (et
.type
== NT_poly
)
16143 NEON_ENCODE (POLY
, inst
);
16145 NEON_ENCODE (INTEGER
, inst
);
16147 /* For polynomial encoding the U bit must be zero, and the size must
16148 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16149 obviously, as 0b10). */
16152 /* Check we're on the correct architecture. */
16153 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16155 _("Instruction form not available on this architecture.");
16160 neon_mixed_length (et
, et
.size
);
16167 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16168 struct neon_type_el et
= neon_check_type (3, rs
,
16169 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16170 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16172 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16173 _("shift out of range"));
16174 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16175 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16176 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16177 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16178 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16179 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16180 inst
.instruction
|= neon_quad (rs
) << 6;
16181 inst
.instruction
|= imm
<< 8;
16183 neon_dp_fixup (&inst
);
16189 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16190 struct neon_type_el et
= neon_check_type (2, rs
,
16191 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16192 unsigned op
= (inst
.instruction
>> 7) & 3;
16193 /* N (width of reversed regions) is encoded as part of the bitmask. We
16194 extract it here to check the elements to be reversed are smaller.
16195 Otherwise we'd get a reserved instruction. */
16196 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16197 gas_assert (elsize
!= 0);
16198 constraint (et
.size
>= elsize
,
16199 _("elements must be smaller than reversal region"));
16200 neon_two_same (neon_quad (rs
), 1, et
.size
);
16206 if (inst
.operands
[1].isscalar
)
16208 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16209 struct neon_type_el et
= neon_check_type (2, rs
,
16210 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16211 unsigned sizebits
= et
.size
>> 3;
16212 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16213 int logsize
= neon_logbits (et
.size
);
16214 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16216 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16219 NEON_ENCODE (SCALAR
, inst
);
16220 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16221 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16222 inst
.instruction
|= LOW4 (dm
);
16223 inst
.instruction
|= HI1 (dm
) << 5;
16224 inst
.instruction
|= neon_quad (rs
) << 6;
16225 inst
.instruction
|= x
<< 17;
16226 inst
.instruction
|= sizebits
<< 16;
16228 neon_dp_fixup (&inst
);
16232 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16233 struct neon_type_el et
= neon_check_type (2, rs
,
16234 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16235 /* Duplicate ARM register to lanes of vector. */
16236 NEON_ENCODE (ARMREG
, inst
);
16239 case 8: inst
.instruction
|= 0x400000; break;
16240 case 16: inst
.instruction
|= 0x000020; break;
16241 case 32: inst
.instruction
|= 0x000000; break;
16244 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16247 inst
.instruction
|= neon_quad (rs
) << 21;
16248 /* The encoding for this instruction is identical for the ARM and Thumb
16249 variants, except for the condition field. */
16250 do_vfp_cond_or_thumb ();
16254 /* VMOV has particularly many variations. It can be one of:
16255 0. VMOV<c><q> <Qd>, <Qm>
16256 1. VMOV<c><q> <Dd>, <Dm>
16257 (Register operations, which are VORR with Rm = Rn.)
16258 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16259 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16261 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16262 (ARM register to scalar.)
16263 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16264 (Two ARM registers to vector.)
16265 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16266 (Scalar to ARM register.)
16267 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16268 (Vector to two ARM registers.)
16269 8. VMOV.F32 <Sd>, <Sm>
16270 9. VMOV.F64 <Dd>, <Dm>
16271 (VFP register moves.)
16272 10. VMOV.F32 <Sd>, #imm
16273 11. VMOV.F64 <Dd>, #imm
16274 (VFP float immediate load.)
16275 12. VMOV <Rd>, <Sm>
16276 (VFP single to ARM reg.)
16277 13. VMOV <Sd>, <Rm>
16278 (ARM reg to VFP single.)
16279 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16280 (Two ARM regs to two VFP singles.)
16281 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16282 (Two VFP singles to two ARM regs.)
16284 These cases can be disambiguated using neon_select_shape, except cases 1/9
16285 and 3/11 which depend on the operand type too.
16287 All the encoded bits are hardcoded by this function.
16289 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16290 Cases 5, 7 may be used with VFPv2 and above.
16292 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16293 can specify a type where it doesn't make sense to, and is ignored). */
16298 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16299 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16300 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16301 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16302 struct neon_type_el et
;
16303 const char *ldconst
= 0;
16307 case NS_DD
: /* case 1/9. */
16308 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16309 /* It is not an error here if no type is given. */
16311 if (et
.type
== NT_float
&& et
.size
== 64)
16313 do_vfp_nsyn_opcode ("fcpyd");
16316 /* fall through. */
16318 case NS_QQ
: /* case 0/1. */
16320 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16322 /* The architecture manual I have doesn't explicitly state which
16323 value the U bit should have for register->register moves, but
16324 the equivalent VORR instruction has U = 0, so do that. */
16325 inst
.instruction
= 0x0200110;
16326 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16327 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16328 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16329 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16332 inst
.instruction
|= neon_quad (rs
) << 6;
16334 neon_dp_fixup (&inst
);
16338 case NS_DI
: /* case 3/11. */
16339 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16341 if (et
.type
== NT_float
&& et
.size
== 64)
16343 /* case 11 (fconstd). */
16344 ldconst
= "fconstd";
16345 goto encode_fconstd
;
16347 /* fall through. */
16349 case NS_QI
: /* case 2/3. */
16350 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16352 inst
.instruction
= 0x0800010;
16353 neon_move_immediate ();
16354 neon_dp_fixup (&inst
);
16357 case NS_SR
: /* case 4. */
16359 unsigned bcdebits
= 0;
16361 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16362 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16364 /* .<size> is optional here, defaulting to .32. */
16365 if (inst
.vectype
.elems
== 0
16366 && inst
.operands
[0].vectype
.type
== NT_invtype
16367 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16369 inst
.vectype
.el
[0].type
= NT_untyped
;
16370 inst
.vectype
.el
[0].size
= 32;
16371 inst
.vectype
.elems
= 1;
16374 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16375 logsize
= neon_logbits (et
.size
);
16377 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16379 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16380 && et
.size
!= 32, _(BAD_FPU
));
16381 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16382 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16386 case 8: bcdebits
= 0x8; break;
16387 case 16: bcdebits
= 0x1; break;
16388 case 32: bcdebits
= 0x0; break;
16392 bcdebits
|= x
<< logsize
;
16394 inst
.instruction
= 0xe000b10;
16395 do_vfp_cond_or_thumb ();
16396 inst
.instruction
|= LOW4 (dn
) << 16;
16397 inst
.instruction
|= HI1 (dn
) << 7;
16398 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16399 inst
.instruction
|= (bcdebits
& 3) << 5;
16400 inst
.instruction
|= (bcdebits
>> 2) << 21;
16404 case NS_DRR
: /* case 5 (fmdrr). */
16405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16408 inst
.instruction
= 0xc400b10;
16409 do_vfp_cond_or_thumb ();
16410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16411 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16412 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16413 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16416 case NS_RS
: /* case 6. */
16419 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16420 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16421 unsigned abcdebits
= 0;
16423 /* .<dt> is optional here, defaulting to .32. */
16424 if (inst
.vectype
.elems
== 0
16425 && inst
.operands
[0].vectype
.type
== NT_invtype
16426 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16428 inst
.vectype
.el
[0].type
= NT_untyped
;
16429 inst
.vectype
.el
[0].size
= 32;
16430 inst
.vectype
.elems
= 1;
16433 et
= neon_check_type (2, NS_NULL
,
16434 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16435 logsize
= neon_logbits (et
.size
);
16437 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16439 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16440 && et
.size
!= 32, _(BAD_FPU
));
16441 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16442 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16446 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16447 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16448 case 32: abcdebits
= 0x00; break;
16452 abcdebits
|= x
<< logsize
;
16453 inst
.instruction
= 0xe100b10;
16454 do_vfp_cond_or_thumb ();
16455 inst
.instruction
|= LOW4 (dn
) << 16;
16456 inst
.instruction
|= HI1 (dn
) << 7;
16457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16458 inst
.instruction
|= (abcdebits
& 3) << 5;
16459 inst
.instruction
|= (abcdebits
>> 2) << 21;
16463 case NS_RRD
: /* case 7 (fmrrd). */
16464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16467 inst
.instruction
= 0xc500b10;
16468 do_vfp_cond_or_thumb ();
16469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16470 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16471 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16472 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16475 case NS_FF
: /* case 8 (fcpys). */
16476 do_vfp_nsyn_opcode ("fcpys");
16480 case NS_FI
: /* case 10 (fconsts). */
16481 ldconst
= "fconsts";
16483 if (is_quarter_float (inst
.operands
[1].imm
))
16485 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16486 do_vfp_nsyn_opcode (ldconst
);
16488 /* ARMv8.2 fp16 vmov.f16 instruction. */
16490 do_scalar_fp16_v82_encode ();
16493 first_error (_("immediate out of range"));
16497 case NS_RF
: /* case 12 (fmrs). */
16498 do_vfp_nsyn_opcode ("fmrs");
16499 /* ARMv8.2 fp16 vmov.f16 instruction. */
16501 do_scalar_fp16_v82_encode ();
16505 case NS_FR
: /* case 13 (fmsr). */
16506 do_vfp_nsyn_opcode ("fmsr");
16507 /* ARMv8.2 fp16 vmov.f16 instruction. */
16509 do_scalar_fp16_v82_encode ();
16512 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16513 (one of which is a list), but we have parsed four. Do some fiddling to
16514 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16516 case NS_RRFF
: /* case 14 (fmrrs). */
16517 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16518 _("VFP registers must be adjacent"));
16519 inst
.operands
[2].imm
= 2;
16520 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16521 do_vfp_nsyn_opcode ("fmrrs");
16524 case NS_FFRR
: /* case 15 (fmsrr). */
16525 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16526 _("VFP registers must be adjacent"));
16527 inst
.operands
[1] = inst
.operands
[2];
16528 inst
.operands
[2] = inst
.operands
[3];
16529 inst
.operands
[0].imm
= 2;
16530 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16531 do_vfp_nsyn_opcode ("fmsrr");
16535 /* neon_select_shape has determined that the instruction
16536 shape is wrong and has already set the error message. */
16545 do_neon_rshift_round_imm (void)
16547 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16548 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16549 int imm
= inst
.operands
[2].imm
;
16551 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16554 inst
.operands
[2].present
= 0;
16559 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16560 _("immediate out of range for shift"));
16561 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16566 do_neon_movhf (void)
16568 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16569 constraint (rs
!= NS_HH
, _("invalid suffix"));
16571 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16574 do_vfp_sp_monadic ();
16577 inst
.instruction
|= 0xf0000000;
16581 do_neon_movl (void)
16583 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16584 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16585 unsigned sizebits
= et
.size
>> 3;
16586 inst
.instruction
|= sizebits
<< 19;
16587 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16593 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16594 struct neon_type_el et
= neon_check_type (2, rs
,
16595 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16596 NEON_ENCODE (INTEGER
, inst
);
16597 neon_two_same (neon_quad (rs
), 1, et
.size
);
16601 do_neon_zip_uzp (void)
16603 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16604 struct neon_type_el et
= neon_check_type (2, rs
,
16605 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16606 if (rs
== NS_DD
&& et
.size
== 32)
16608 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16609 inst
.instruction
= N_MNEM_vtrn
;
16613 neon_two_same (neon_quad (rs
), 1, et
.size
);
16617 do_neon_sat_abs_neg (void)
16619 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16620 struct neon_type_el et
= neon_check_type (2, rs
,
16621 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16622 neon_two_same (neon_quad (rs
), 1, et
.size
);
16626 do_neon_pair_long (void)
16628 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16629 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16630 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16631 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16632 neon_two_same (neon_quad (rs
), 1, et
.size
);
16636 do_neon_recip_est (void)
16638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16639 struct neon_type_el et
= neon_check_type (2, rs
,
16640 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16641 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16642 neon_two_same (neon_quad (rs
), 1, et
.size
);
16648 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16649 struct neon_type_el et
= neon_check_type (2, rs
,
16650 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16651 neon_two_same (neon_quad (rs
), 1, et
.size
);
16657 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16658 struct neon_type_el et
= neon_check_type (2, rs
,
16659 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16660 neon_two_same (neon_quad (rs
), 1, et
.size
);
16666 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16667 struct neon_type_el et
= neon_check_type (2, rs
,
16668 N_EQK
| N_INT
, N_8
| N_KEY
);
16669 neon_two_same (neon_quad (rs
), 1, et
.size
);
16675 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16676 neon_two_same (neon_quad (rs
), 1, -1);
16680 do_neon_tbl_tbx (void)
16682 unsigned listlenbits
;
16683 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16685 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16687 first_error (_("bad list length for table lookup"));
16691 listlenbits
= inst
.operands
[1].imm
- 1;
16692 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16693 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16695 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16696 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16697 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16698 inst
.instruction
|= listlenbits
<< 8;
16700 neon_dp_fixup (&inst
);
16704 do_neon_ldm_stm (void)
16706 /* P, U and L bits are part of bitmask. */
16707 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16708 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16710 if (inst
.operands
[1].issingle
)
16712 do_vfp_nsyn_ldm_stm (is_dbmode
);
16716 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16717 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16719 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16720 _("register list must contain at least 1 and at most 16 "
16723 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16724 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16725 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16726 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16728 inst
.instruction
|= offsetbits
;
16730 do_vfp_cond_or_thumb ();
16734 do_neon_ldr_str (void)
16736 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16738 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16739 And is UNPREDICTABLE in thumb mode. */
16741 && inst
.operands
[1].reg
== REG_PC
16742 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16745 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16746 else if (warn_on_deprecated
)
16747 as_tsktsk (_("Use of PC here is deprecated"));
16750 if (inst
.operands
[0].issingle
)
16753 do_vfp_nsyn_opcode ("flds");
16755 do_vfp_nsyn_opcode ("fsts");
16757 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16758 if (inst
.vectype
.el
[0].size
== 16)
16759 do_scalar_fp16_v82_encode ();
16764 do_vfp_nsyn_opcode ("fldd");
16766 do_vfp_nsyn_opcode ("fstd");
16770 /* "interleave" version also handles non-interleaving register VLD1/VST1
16774 do_neon_ld_st_interleave (void)
16776 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16777 N_8
| N_16
| N_32
| N_64
);
16778 unsigned alignbits
= 0;
16780 /* The bits in this table go:
16781 0: register stride of one (0) or two (1)
16782 1,2: register list length, minus one (1, 2, 3, 4).
16783 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16784 We use -1 for invalid entries. */
16785 const int typetable
[] =
16787 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16788 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16789 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16790 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16794 if (et
.type
== NT_invtype
)
16797 if (inst
.operands
[1].immisalign
)
16798 switch (inst
.operands
[1].imm
>> 8)
16800 case 64: alignbits
= 1; break;
16802 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16803 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16804 goto bad_alignment
;
16808 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16809 goto bad_alignment
;
16814 first_error (_("bad alignment"));
16818 inst
.instruction
|= alignbits
<< 4;
16819 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16821 /* Bits [4:6] of the immediate in a list specifier encode register stride
16822 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16823 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16824 up the right value for "type" in a table based on this value and the given
16825 list style, then stick it back. */
16826 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16827 | (((inst
.instruction
>> 8) & 3) << 3);
16829 typebits
= typetable
[idx
];
16831 constraint (typebits
== -1, _("bad list type for instruction"));
16832 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16833 _("bad element type for instruction"));
16835 inst
.instruction
&= ~0xf00;
16836 inst
.instruction
|= typebits
<< 8;
16839 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16840 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16841 otherwise. The variable arguments are a list of pairs of legal (size, align)
16842 values, terminated with -1. */
16845 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16848 int result
= FAIL
, thissize
, thisalign
;
16850 if (!inst
.operands
[1].immisalign
)
16856 va_start (ap
, do_alignment
);
16860 thissize
= va_arg (ap
, int);
16861 if (thissize
== -1)
16863 thisalign
= va_arg (ap
, int);
16865 if (size
== thissize
&& align
== thisalign
)
16868 while (result
!= SUCCESS
);
16872 if (result
== SUCCESS
)
16875 first_error (_("unsupported alignment for instruction"));
16881 do_neon_ld_st_lane (void)
16883 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16884 int align_good
, do_alignment
= 0;
16885 int logsize
= neon_logbits (et
.size
);
16886 int align
= inst
.operands
[1].imm
>> 8;
16887 int n
= (inst
.instruction
>> 8) & 3;
16888 int max_el
= 64 / et
.size
;
16890 if (et
.type
== NT_invtype
)
16893 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16894 _("bad list length"));
16895 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16896 _("scalar index out of range"));
16897 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16899 _("stride of 2 unavailable when element size is 8"));
16903 case 0: /* VLD1 / VST1. */
16904 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16906 if (align_good
== FAIL
)
16910 unsigned alignbits
= 0;
16913 case 16: alignbits
= 0x1; break;
16914 case 32: alignbits
= 0x3; break;
16917 inst
.instruction
|= alignbits
<< 4;
16921 case 1: /* VLD2 / VST2. */
16922 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16923 16, 32, 32, 64, -1);
16924 if (align_good
== FAIL
)
16927 inst
.instruction
|= 1 << 4;
16930 case 2: /* VLD3 / VST3. */
16931 constraint (inst
.operands
[1].immisalign
,
16932 _("can't use alignment with this instruction"));
16935 case 3: /* VLD4 / VST4. */
16936 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16937 16, 64, 32, 64, 32, 128, -1);
16938 if (align_good
== FAIL
)
16942 unsigned alignbits
= 0;
16945 case 8: alignbits
= 0x1; break;
16946 case 16: alignbits
= 0x1; break;
16947 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16950 inst
.instruction
|= alignbits
<< 4;
16957 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16958 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16959 inst
.instruction
|= 1 << (4 + logsize
);
16961 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16962 inst
.instruction
|= logsize
<< 10;
16965 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16968 do_neon_ld_dup (void)
16970 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16971 int align_good
, do_alignment
= 0;
16973 if (et
.type
== NT_invtype
)
16976 switch ((inst
.instruction
>> 8) & 3)
16978 case 0: /* VLD1. */
16979 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16980 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16981 &do_alignment
, 16, 16, 32, 32, -1);
16982 if (align_good
== FAIL
)
16984 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16987 case 2: inst
.instruction
|= 1 << 5; break;
16988 default: first_error (_("bad list length")); return;
16990 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16993 case 1: /* VLD2. */
16994 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16995 &do_alignment
, 8, 16, 16, 32, 32, 64,
16997 if (align_good
== FAIL
)
16999 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17000 _("bad list length"));
17001 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17002 inst
.instruction
|= 1 << 5;
17003 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17006 case 2: /* VLD3. */
17007 constraint (inst
.operands
[1].immisalign
,
17008 _("can't use alignment with this instruction"));
17009 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17010 _("bad list length"));
17011 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17012 inst
.instruction
|= 1 << 5;
17013 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17016 case 3: /* VLD4. */
17018 int align
= inst
.operands
[1].imm
>> 8;
17019 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17020 16, 64, 32, 64, 32, 128, -1);
17021 if (align_good
== FAIL
)
17023 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17024 _("bad list length"));
17025 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17026 inst
.instruction
|= 1 << 5;
17027 if (et
.size
== 32 && align
== 128)
17028 inst
.instruction
|= 0x3 << 6;
17030 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17037 inst
.instruction
|= do_alignment
<< 4;
17040 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17041 apart from bits [11:4]. */
17044 do_neon_ldx_stx (void)
17046 if (inst
.operands
[1].isreg
)
17047 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17049 switch (NEON_LANE (inst
.operands
[0].imm
))
17051 case NEON_INTERLEAVE_LANES
:
17052 NEON_ENCODE (INTERLV
, inst
);
17053 do_neon_ld_st_interleave ();
17056 case NEON_ALL_LANES
:
17057 NEON_ENCODE (DUP
, inst
);
17058 if (inst
.instruction
== N_INV
)
17060 first_error ("only loads support such operands");
17067 NEON_ENCODE (LANE
, inst
);
17068 do_neon_ld_st_lane ();
17071 /* L bit comes from bit mask. */
17072 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17073 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17074 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17076 if (inst
.operands
[1].postind
)
17078 int postreg
= inst
.operands
[1].imm
& 0xf;
17079 constraint (!inst
.operands
[1].immisreg
,
17080 _("post-index must be a register"));
17081 constraint (postreg
== 0xd || postreg
== 0xf,
17082 _("bad register for post-index"));
17083 inst
.instruction
|= postreg
;
17087 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17088 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17089 || inst
.reloc
.exp
.X_add_number
!= 0,
17092 if (inst
.operands
[1].writeback
)
17094 inst
.instruction
|= 0xd;
17097 inst
.instruction
|= 0xf;
17101 inst
.instruction
|= 0xf9000000;
17103 inst
.instruction
|= 0xf4000000;
17108 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17110 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17111 D register operands. */
17112 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17113 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17116 NEON_ENCODE (FPV8
, inst
);
17118 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17120 do_vfp_sp_dyadic ();
17122 /* ARMv8.2 fp16 instruction. */
17124 do_scalar_fp16_v82_encode ();
17127 do_vfp_dp_rd_rn_rm ();
17130 inst
.instruction
|= 0x100;
17132 inst
.instruction
|= 0xf0000000;
17138 set_it_insn_type (OUTSIDE_IT_INSN
);
17140 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17141 first_error (_("invalid instruction shape"));
17147 set_it_insn_type (OUTSIDE_IT_INSN
);
17149 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17152 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17155 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17159 do_vrint_1 (enum neon_cvt_mode mode
)
17161 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17162 struct neon_type_el et
;
17167 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17168 D register operands. */
17169 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17170 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17173 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17175 if (et
.type
!= NT_invtype
)
17177 /* VFP encodings. */
17178 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17179 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17180 set_it_insn_type (OUTSIDE_IT_INSN
);
17182 NEON_ENCODE (FPV8
, inst
);
17183 if (rs
== NS_FF
|| rs
== NS_HH
)
17184 do_vfp_sp_monadic ();
17186 do_vfp_dp_rd_rm ();
17190 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17191 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17192 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17193 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17194 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17195 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17196 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17200 inst
.instruction
|= (rs
== NS_DD
) << 8;
17201 do_vfp_cond_or_thumb ();
17203 /* ARMv8.2 fp16 vrint instruction. */
17205 do_scalar_fp16_v82_encode ();
17209 /* Neon encodings (or something broken...). */
17211 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17213 if (et
.type
== NT_invtype
)
17216 set_it_insn_type (OUTSIDE_IT_INSN
);
17217 NEON_ENCODE (FLOAT
, inst
);
17219 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17223 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17224 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17225 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17226 inst
.instruction
|= neon_quad (rs
) << 6;
17227 /* Mask off the original size bits and reencode them. */
17228 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17229 | neon_logbits (et
.size
) << 18);
17233 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17234 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17235 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17236 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17237 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17238 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17239 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17244 inst
.instruction
|= 0xfc000000;
17246 inst
.instruction
|= 0xf0000000;
17253 do_vrint_1 (neon_cvt_mode_x
);
17259 do_vrint_1 (neon_cvt_mode_z
);
17265 do_vrint_1 (neon_cvt_mode_r
);
17271 do_vrint_1 (neon_cvt_mode_a
);
17277 do_vrint_1 (neon_cvt_mode_n
);
17283 do_vrint_1 (neon_cvt_mode_p
);
17289 do_vrint_1 (neon_cvt_mode_m
);
17293 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17295 unsigned regno
= NEON_SCALAR_REG (opnd
);
17296 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17298 if (elsize
== 16 && elno
< 2 && regno
< 16)
17299 return regno
| (elno
<< 4);
17300 else if (elsize
== 32 && elno
== 0)
17303 first_error (_("scalar out of range"));
17310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17312 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17313 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17314 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17315 _("immediate out of range"));
17317 if (inst
.operands
[2].isscalar
)
17319 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17320 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17321 N_KEY
| N_F16
| N_F32
).size
;
17322 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17324 inst
.instruction
= 0xfe000800;
17325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17327 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17328 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17329 inst
.instruction
|= LOW4 (m
);
17330 inst
.instruction
|= HI1 (m
) << 5;
17331 inst
.instruction
|= neon_quad (rs
) << 6;
17332 inst
.instruction
|= rot
<< 20;
17333 inst
.instruction
|= (size
== 32) << 23;
17337 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17338 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17339 N_KEY
| N_F16
| N_F32
).size
;
17340 neon_three_same (neon_quad (rs
), 0, -1);
17341 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17342 inst
.instruction
|= 0xfc200800;
17343 inst
.instruction
|= rot
<< 23;
17344 inst
.instruction
|= (size
== 32) << 20;
17351 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17353 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17354 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17355 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17356 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17357 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17358 N_KEY
| N_F16
| N_F32
).size
;
17359 neon_three_same (neon_quad (rs
), 0, -1);
17360 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17361 inst
.instruction
|= 0xfc800800;
17362 inst
.instruction
|= (rot
== 270) << 24;
17363 inst
.instruction
|= (size
== 32) << 20;
17366 /* Crypto v1 instructions. */
17368 do_crypto_2op_1 (unsigned elttype
, int op
)
17370 set_it_insn_type (OUTSIDE_IT_INSN
);
17372 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17378 NEON_ENCODE (INTEGER
, inst
);
17379 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17380 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17381 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17382 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17384 inst
.instruction
|= op
<< 6;
17387 inst
.instruction
|= 0xfc000000;
17389 inst
.instruction
|= 0xf0000000;
17393 do_crypto_3op_1 (int u
, int op
)
17395 set_it_insn_type (OUTSIDE_IT_INSN
);
17397 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17398 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17403 NEON_ENCODE (INTEGER
, inst
);
17404 neon_three_same (1, u
, 8 << op
);
17410 do_crypto_2op_1 (N_8
, 0);
17416 do_crypto_2op_1 (N_8
, 1);
17422 do_crypto_2op_1 (N_8
, 2);
17428 do_crypto_2op_1 (N_8
, 3);
17434 do_crypto_3op_1 (0, 0);
17440 do_crypto_3op_1 (0, 1);
17446 do_crypto_3op_1 (0, 2);
17452 do_crypto_3op_1 (0, 3);
17458 do_crypto_3op_1 (1, 0);
17464 do_crypto_3op_1 (1, 1);
17468 do_sha256su1 (void)
17470 do_crypto_3op_1 (1, 2);
17476 do_crypto_2op_1 (N_32
, -1);
17482 do_crypto_2op_1 (N_32
, 0);
17486 do_sha256su0 (void)
17488 do_crypto_2op_1 (N_32
, 1);
17492 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17494 unsigned int Rd
= inst
.operands
[0].reg
;
17495 unsigned int Rn
= inst
.operands
[1].reg
;
17496 unsigned int Rm
= inst
.operands
[2].reg
;
17498 set_it_insn_type (OUTSIDE_IT_INSN
);
17499 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17500 inst
.instruction
|= LOW4 (Rn
) << 16;
17501 inst
.instruction
|= LOW4 (Rm
);
17502 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17503 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17505 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17506 as_warn (UNPRED_REG ("r15"));
17507 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17508 as_warn (UNPRED_REG ("r13"));
17550 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17552 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17553 do_vfp_sp_dp_cvt ();
17554 do_vfp_cond_or_thumb ();
17558 /* Overall per-instruction processing. */
17560 /* We need to be able to fix up arbitrary expressions in some statements.
17561 This is so that we can handle symbols that are an arbitrary distance from
17562 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17563 which returns part of an address in a form which will be valid for
17564 a data instruction. We do this by pushing the expression into a symbol
17565 in the expr_section, and creating a fix for that. */
17568 fix_new_arm (fragS
* frag
,
17582 /* Create an absolute valued symbol, so we have something to
17583 refer to in the object file. Unfortunately for us, gas's
17584 generic expression parsing will already have folded out
17585 any use of .set foo/.type foo %function that may have
17586 been used to set type information of the target location,
17587 that's being specified symbolically. We have to presume
17588 the user knows what they are doing. */
17592 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17594 symbol
= symbol_find_or_make (name
);
17595 S_SET_SEGMENT (symbol
, absolute_section
);
17596 symbol_set_frag (symbol
, &zero_address_frag
);
17597 S_SET_VALUE (symbol
, exp
->X_add_number
);
17598 exp
->X_op
= O_symbol
;
17599 exp
->X_add_symbol
= symbol
;
17600 exp
->X_add_number
= 0;
17606 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17607 (enum bfd_reloc_code_real
) reloc
);
17611 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17612 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17616 /* Mark whether the fix is to a THUMB instruction, or an ARM
17618 new_fix
->tc_fix_data
= thumb_mode
;
17621 /* Create a frg for an instruction requiring relaxation. */
17623 output_relax_insn (void)
17629 /* The size of the instruction is unknown, so tie the debug info to the
17630 start of the instruction. */
17631 dwarf2_emit_insn (0);
17633 switch (inst
.reloc
.exp
.X_op
)
17636 sym
= inst
.reloc
.exp
.X_add_symbol
;
17637 offset
= inst
.reloc
.exp
.X_add_number
;
17641 offset
= inst
.reloc
.exp
.X_add_number
;
17644 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17648 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17649 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17650 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17653 /* Write a 32-bit thumb instruction to buf. */
17655 put_thumb32_insn (char * buf
, unsigned long insn
)
17657 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17658 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17662 output_inst (const char * str
)
17668 as_bad ("%s -- `%s'", inst
.error
, str
);
17673 output_relax_insn ();
17676 if (inst
.size
== 0)
17679 to
= frag_more (inst
.size
);
17680 /* PR 9814: Record the thumb mode into the current frag so that we know
17681 what type of NOP padding to use, if necessary. We override any previous
17682 setting so that if the mode has changed then the NOPS that we use will
17683 match the encoding of the last instruction in the frag. */
17684 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17686 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17688 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17689 put_thumb32_insn (to
, inst
.instruction
);
17691 else if (inst
.size
> INSN_SIZE
)
17693 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17694 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17695 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17698 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17700 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17701 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17702 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17705 dwarf2_emit_insn (inst
.size
);
17709 output_it_inst (int cond
, int mask
, char * to
)
17711 unsigned long instruction
= 0xbf00;
17714 instruction
|= mask
;
17715 instruction
|= cond
<< 4;
17719 to
= frag_more (2);
17721 dwarf2_emit_insn (2);
17725 md_number_to_chars (to
, instruction
, 2);
17730 /* Tag values used in struct asm_opcode's tag field. */
17733 OT_unconditional
, /* Instruction cannot be conditionalized.
17734 The ARM condition field is still 0xE. */
17735 OT_unconditionalF
, /* Instruction cannot be conditionalized
17736 and carries 0xF in its ARM condition field. */
17737 OT_csuffix
, /* Instruction takes a conditional suffix. */
17738 OT_csuffixF
, /* Some forms of the instruction take a conditional
17739 suffix, others place 0xF where the condition field
17741 OT_cinfix3
, /* Instruction takes a conditional infix,
17742 beginning at character index 3. (In
17743 unified mode, it becomes a suffix.) */
17744 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17745 tsts, cmps, cmns, and teqs. */
17746 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17747 character index 3, even in unified mode. Used for
17748 legacy instructions where suffix and infix forms
17749 may be ambiguous. */
17750 OT_csuf_or_in3
, /* Instruction takes either a conditional
17751 suffix or an infix at character index 3. */
17752 OT_odd_infix_unc
, /* This is the unconditional variant of an
17753 instruction that takes a conditional infix
17754 at an unusual position. In unified mode,
17755 this variant will accept a suffix. */
17756 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17757 are the conditional variants of instructions that
17758 take conditional infixes in unusual positions.
17759 The infix appears at character index
17760 (tag - OT_odd_infix_0). These are not accepted
17761 in unified mode. */
17764 /* Subroutine of md_assemble, responsible for looking up the primary
17765 opcode from the mnemonic the user wrote. STR points to the
17766 beginning of the mnemonic.
17768 This is not simply a hash table lookup, because of conditional
17769 variants. Most instructions have conditional variants, which are
17770 expressed with a _conditional affix_ to the mnemonic. If we were
17771 to encode each conditional variant as a literal string in the opcode
17772 table, it would have approximately 20,000 entries.
17774 Most mnemonics take this affix as a suffix, and in unified syntax,
17775 'most' is upgraded to 'all'. However, in the divided syntax, some
17776 instructions take the affix as an infix, notably the s-variants of
17777 the arithmetic instructions. Of those instructions, all but six
17778 have the infix appear after the third character of the mnemonic.
17780 Accordingly, the algorithm for looking up primary opcodes given
17783 1. Look up the identifier in the opcode table.
17784 If we find a match, go to step U.
17786 2. Look up the last two characters of the identifier in the
17787 conditions table. If we find a match, look up the first N-2
17788 characters of the identifier in the opcode table. If we
17789 find a match, go to step CE.
17791 3. Look up the fourth and fifth characters of the identifier in
17792 the conditions table. If we find a match, extract those
17793 characters from the identifier, and look up the remaining
17794 characters in the opcode table. If we find a match, go
17799 U. Examine the tag field of the opcode structure, in case this is
17800 one of the six instructions with its conditional infix in an
17801 unusual place. If it is, the tag tells us where to find the
17802 infix; look it up in the conditions table and set inst.cond
17803 accordingly. Otherwise, this is an unconditional instruction.
17804 Again set inst.cond accordingly. Return the opcode structure.
17806 CE. Examine the tag field to make sure this is an instruction that
17807 should receive a conditional suffix. If it is not, fail.
17808 Otherwise, set inst.cond from the suffix we already looked up,
17809 and return the opcode structure.
17811 CM. Examine the tag field to make sure this is an instruction that
17812 should receive a conditional infix after the third character.
17813 If it is not, fail. Otherwise, undo the edits to the current
17814 line of input and proceed as for case CE. */
17816 static const struct asm_opcode
*
17817 opcode_lookup (char **str
)
17821 const struct asm_opcode
*opcode
;
17822 const struct asm_cond
*cond
;
17825 /* Scan up to the end of the mnemonic, which must end in white space,
17826 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17827 for (base
= end
= *str
; *end
!= '\0'; end
++)
17828 if (*end
== ' ' || *end
== '.')
17834 /* Handle a possible width suffix and/or Neon type suffix. */
17839 /* The .w and .n suffixes are only valid if the unified syntax is in
17841 if (unified_syntax
&& end
[1] == 'w')
17843 else if (unified_syntax
&& end
[1] == 'n')
17848 inst
.vectype
.elems
= 0;
17850 *str
= end
+ offset
;
17852 if (end
[offset
] == '.')
17854 /* See if we have a Neon type suffix (possible in either unified or
17855 non-unified ARM syntax mode). */
17856 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17859 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17865 /* Look for unaffixed or special-case affixed mnemonic. */
17866 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17871 if (opcode
->tag
< OT_odd_infix_0
)
17873 inst
.cond
= COND_ALWAYS
;
17877 if (warn_on_deprecated
&& unified_syntax
)
17878 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17879 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17880 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17883 inst
.cond
= cond
->value
;
17887 /* Cannot have a conditional suffix on a mnemonic of less than two
17889 if (end
- base
< 3)
17892 /* Look for suffixed mnemonic. */
17894 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17895 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17897 if (opcode
&& cond
)
17900 switch (opcode
->tag
)
17902 case OT_cinfix3_legacy
:
17903 /* Ignore conditional suffixes matched on infix only mnemonics. */
17907 case OT_cinfix3_deprecated
:
17908 case OT_odd_infix_unc
:
17909 if (!unified_syntax
)
17911 /* Fall through. */
17915 case OT_csuf_or_in3
:
17916 inst
.cond
= cond
->value
;
17919 case OT_unconditional
:
17920 case OT_unconditionalF
:
17922 inst
.cond
= cond
->value
;
17925 /* Delayed diagnostic. */
17926 inst
.error
= BAD_COND
;
17927 inst
.cond
= COND_ALWAYS
;
17936 /* Cannot have a usual-position infix on a mnemonic of less than
17937 six characters (five would be a suffix). */
17938 if (end
- base
< 6)
17941 /* Look for infixed mnemonic in the usual position. */
17943 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17947 memcpy (save
, affix
, 2);
17948 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17949 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17951 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17952 memcpy (affix
, save
, 2);
17955 && (opcode
->tag
== OT_cinfix3
17956 || opcode
->tag
== OT_cinfix3_deprecated
17957 || opcode
->tag
== OT_csuf_or_in3
17958 || opcode
->tag
== OT_cinfix3_legacy
))
17961 if (warn_on_deprecated
&& unified_syntax
17962 && (opcode
->tag
== OT_cinfix3
17963 || opcode
->tag
== OT_cinfix3_deprecated
))
17964 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17966 inst
.cond
= cond
->value
;
17973 /* This function generates an initial IT instruction, leaving its block
17974 virtually open for the new instructions. Eventually,
17975 the mask will be updated by now_it_add_mask () each time
17976 a new instruction needs to be included in the IT block.
17977 Finally, the block is closed with close_automatic_it_block ().
17978 The block closure can be requested either from md_assemble (),
17979 a tencode (), or due to a label hook. */
17982 new_automatic_it_block (int cond
)
17984 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17985 now_it
.mask
= 0x18;
17987 now_it
.block_length
= 1;
17988 mapping_state (MAP_THUMB
);
17989 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17990 now_it
.warn_deprecated
= FALSE
;
17991 now_it
.insn_cond
= TRUE
;
17994 /* Close an automatic IT block.
17995 See comments in new_automatic_it_block (). */
17998 close_automatic_it_block (void)
18000 now_it
.mask
= 0x10;
18001 now_it
.block_length
= 0;
18004 /* Update the mask of the current automatically-generated IT
18005 instruction. See comments in new_automatic_it_block (). */
18008 now_it_add_mask (int cond
)
18010 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18011 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18012 | ((bitvalue) << (nbit)))
18013 const int resulting_bit
= (cond
& 1);
18015 now_it
.mask
&= 0xf;
18016 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18018 (5 - now_it
.block_length
));
18019 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18021 ((5 - now_it
.block_length
) - 1) );
18022 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18025 #undef SET_BIT_VALUE
18028 /* The IT blocks handling machinery is accessed through the these functions:
18029 it_fsm_pre_encode () from md_assemble ()
18030 set_it_insn_type () optional, from the tencode functions
18031 set_it_insn_type_last () ditto
18032 in_it_block () ditto
18033 it_fsm_post_encode () from md_assemble ()
18034 force_automatic_it_block_close () from label handling functions
18037 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18038 initializing the IT insn type with a generic initial value depending
18039 on the inst.condition.
18040 2) During the tencode function, two things may happen:
18041 a) The tencode function overrides the IT insn type by
18042 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18043 b) The tencode function queries the IT block state by
18044 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18046 Both set_it_insn_type and in_it_block run the internal FSM state
18047 handling function (handle_it_state), because: a) setting the IT insn
18048 type may incur in an invalid state (exiting the function),
18049 and b) querying the state requires the FSM to be updated.
18050 Specifically we want to avoid creating an IT block for conditional
18051 branches, so it_fsm_pre_encode is actually a guess and we can't
18052 determine whether an IT block is required until the tencode () routine
18053 has decided what type of instruction this actually it.
18054 Because of this, if set_it_insn_type and in_it_block have to be used,
18055 set_it_insn_type has to be called first.
18057 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18058 determines the insn IT type depending on the inst.cond code.
18059 When a tencode () routine encodes an instruction that can be
18060 either outside an IT block, or, in the case of being inside, has to be
18061 the last one, set_it_insn_type_last () will determine the proper
18062 IT instruction type based on the inst.cond code. Otherwise,
18063 set_it_insn_type can be called for overriding that logic or
18064 for covering other cases.
18066 Calling handle_it_state () may not transition the IT block state to
18067 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18068 still queried. Instead, if the FSM determines that the state should
18069 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18070 after the tencode () function: that's what it_fsm_post_encode () does.
18072 Since in_it_block () calls the state handling function to get an
18073 updated state, an error may occur (due to invalid insns combination).
18074 In that case, inst.error is set.
18075 Therefore, inst.error has to be checked after the execution of
18076 the tencode () routine.
18078 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18079 any pending state change (if any) that didn't take place in
18080 handle_it_state () as explained above. */
18083 it_fsm_pre_encode (void)
18085 if (inst
.cond
!= COND_ALWAYS
)
18086 inst
.it_insn_type
= INSIDE_IT_INSN
;
18088 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18090 now_it
.state_handled
= 0;
18093 /* IT state FSM handling function. */
18096 handle_it_state (void)
18098 now_it
.state_handled
= 1;
18099 now_it
.insn_cond
= FALSE
;
18101 switch (now_it
.state
)
18103 case OUTSIDE_IT_BLOCK
:
18104 switch (inst
.it_insn_type
)
18106 case OUTSIDE_IT_INSN
:
18109 case INSIDE_IT_INSN
:
18110 case INSIDE_IT_LAST_INSN
:
18111 if (thumb_mode
== 0)
18114 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18115 as_tsktsk (_("Warning: conditional outside an IT block"\
18120 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18121 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18123 /* Automatically generate the IT instruction. */
18124 new_automatic_it_block (inst
.cond
);
18125 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18126 close_automatic_it_block ();
18130 inst
.error
= BAD_OUT_IT
;
18136 case IF_INSIDE_IT_LAST_INSN
:
18137 case NEUTRAL_IT_INSN
:
18141 now_it
.state
= MANUAL_IT_BLOCK
;
18142 now_it
.block_length
= 0;
18147 case AUTOMATIC_IT_BLOCK
:
18148 /* Three things may happen now:
18149 a) We should increment current it block size;
18150 b) We should close current it block (closing insn or 4 insns);
18151 c) We should close current it block and start a new one (due
18152 to incompatible conditions or
18153 4 insns-length block reached). */
18155 switch (inst
.it_insn_type
)
18157 case OUTSIDE_IT_INSN
:
18158 /* The closure of the block shall happen immediately,
18159 so any in_it_block () call reports the block as closed. */
18160 force_automatic_it_block_close ();
18163 case INSIDE_IT_INSN
:
18164 case INSIDE_IT_LAST_INSN
:
18165 case IF_INSIDE_IT_LAST_INSN
:
18166 now_it
.block_length
++;
18168 if (now_it
.block_length
> 4
18169 || !now_it_compatible (inst
.cond
))
18171 force_automatic_it_block_close ();
18172 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18173 new_automatic_it_block (inst
.cond
);
18177 now_it
.insn_cond
= TRUE
;
18178 now_it_add_mask (inst
.cond
);
18181 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18182 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18183 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18184 close_automatic_it_block ();
18187 case NEUTRAL_IT_INSN
:
18188 now_it
.block_length
++;
18189 now_it
.insn_cond
= TRUE
;
18191 if (now_it
.block_length
> 4)
18192 force_automatic_it_block_close ();
18194 now_it_add_mask (now_it
.cc
& 1);
18198 close_automatic_it_block ();
18199 now_it
.state
= MANUAL_IT_BLOCK
;
18204 case MANUAL_IT_BLOCK
:
18206 /* Check conditional suffixes. */
18207 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18210 now_it
.mask
&= 0x1f;
18211 is_last
= (now_it
.mask
== 0x10);
18212 now_it
.insn_cond
= TRUE
;
18214 switch (inst
.it_insn_type
)
18216 case OUTSIDE_IT_INSN
:
18217 inst
.error
= BAD_NOT_IT
;
18220 case INSIDE_IT_INSN
:
18221 if (cond
!= inst
.cond
)
18223 inst
.error
= BAD_IT_COND
;
18228 case INSIDE_IT_LAST_INSN
:
18229 case IF_INSIDE_IT_LAST_INSN
:
18230 if (cond
!= inst
.cond
)
18232 inst
.error
= BAD_IT_COND
;
18237 inst
.error
= BAD_BRANCH
;
18242 case NEUTRAL_IT_INSN
:
18243 /* The BKPT instruction is unconditional even in an IT block. */
18247 inst
.error
= BAD_IT_IT
;
18257 struct depr_insn_mask
18259 unsigned long pattern
;
18260 unsigned long mask
;
18261 const char* description
;
18264 /* List of 16-bit instruction patterns deprecated in an IT block in
18266 static const struct depr_insn_mask depr_it_insns
[] = {
18267 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18268 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18269 { 0xa000, 0xb800, N_("ADR") },
18270 { 0x4800, 0xf800, N_("Literal loads") },
18271 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18272 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18273 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18274 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18275 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18280 it_fsm_post_encode (void)
18284 if (!now_it
.state_handled
)
18285 handle_it_state ();
18287 if (now_it
.insn_cond
18288 && !now_it
.warn_deprecated
18289 && warn_on_deprecated
18290 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18292 if (inst
.instruction
>= 0x10000)
18294 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18295 "deprecated in ARMv8"));
18296 now_it
.warn_deprecated
= TRUE
;
18300 const struct depr_insn_mask
*p
= depr_it_insns
;
18302 while (p
->mask
!= 0)
18304 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18306 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18307 "of the following class are deprecated in ARMv8: "
18308 "%s"), p
->description
);
18309 now_it
.warn_deprecated
= TRUE
;
18317 if (now_it
.block_length
> 1)
18319 as_tsktsk (_("IT blocks containing more than one conditional "
18320 "instruction are deprecated in ARMv8"));
18321 now_it
.warn_deprecated
= TRUE
;
18325 is_last
= (now_it
.mask
== 0x10);
18328 now_it
.state
= OUTSIDE_IT_BLOCK
;
18334 force_automatic_it_block_close (void)
18336 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18338 close_automatic_it_block ();
18339 now_it
.state
= OUTSIDE_IT_BLOCK
;
18347 if (!now_it
.state_handled
)
18348 handle_it_state ();
18350 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18353 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18354 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18355 here, hence the "known" in the function name. */
18358 known_t32_only_insn (const struct asm_opcode
*opcode
)
18360 /* Original Thumb-1 wide instruction. */
18361 if (opcode
->tencode
== do_t_blx
18362 || opcode
->tencode
== do_t_branch23
18363 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18364 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18367 /* Wide-only instruction added to ARMv8-M Baseline. */
18368 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18369 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18370 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18371 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18377 /* Whether wide instruction variant can be used if available for a valid OPCODE
18381 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18383 if (known_t32_only_insn (opcode
))
18386 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18387 of variant T3 of B.W is checked in do_t_branch. */
18388 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18389 && opcode
->tencode
== do_t_branch
)
18392 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18393 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18394 && opcode
->tencode
== do_t_mov_cmp
18395 /* Make sure CMP instruction is not affected. */
18396 && opcode
->aencode
== do_mov
)
18399 /* Wide instruction variants of all instructions with narrow *and* wide
18400 variants become available with ARMv6t2. Other opcodes are either
18401 narrow-only or wide-only and are thus available if OPCODE is valid. */
18402 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18405 /* OPCODE with narrow only instruction variant or wide variant not
18411 md_assemble (char *str
)
18414 const struct asm_opcode
* opcode
;
18416 /* Align the previous label if needed. */
18417 if (last_label_seen
!= NULL
)
18419 symbol_set_frag (last_label_seen
, frag_now
);
18420 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18421 S_SET_SEGMENT (last_label_seen
, now_seg
);
18424 memset (&inst
, '\0', sizeof (inst
));
18425 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18427 opcode
= opcode_lookup (&p
);
18430 /* It wasn't an instruction, but it might be a register alias of
18431 the form alias .req reg, or a Neon .dn/.qn directive. */
18432 if (! create_register_alias (str
, p
)
18433 && ! create_neon_reg_alias (str
, p
))
18434 as_bad (_("bad instruction `%s'"), str
);
18439 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18440 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18442 /* The value which unconditional instructions should have in place of the
18443 condition field. */
18444 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18448 arm_feature_set variant
;
18450 variant
= cpu_variant
;
18451 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18452 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18453 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18454 /* Check that this instruction is supported for this CPU. */
18455 if (!opcode
->tvariant
18456 || (thumb_mode
== 1
18457 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18459 if (opcode
->tencode
== do_t_swi
)
18460 as_bad (_("SVC is not permitted on this architecture"));
18462 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18465 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18466 && opcode
->tencode
!= do_t_branch
)
18468 as_bad (_("Thumb does not support conditional execution"));
18472 /* Two things are addressed here:
18473 1) Implicit require narrow instructions on Thumb-1.
18474 This avoids relaxation accidentally introducing Thumb-2
18476 2) Reject wide instructions in non Thumb-2 cores.
18478 Only instructions with narrow and wide variants need to be handled
18479 but selecting all non wide-only instructions is easier. */
18480 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18481 && !t32_insn_ok (variant
, opcode
))
18483 if (inst
.size_req
== 0)
18485 else if (inst
.size_req
== 4)
18487 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18488 as_bad (_("selected processor does not support 32bit wide "
18489 "variant of instruction `%s'"), str
);
18491 as_bad (_("selected processor does not support `%s' in "
18492 "Thumb-2 mode"), str
);
18497 inst
.instruction
= opcode
->tvalue
;
18499 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18501 /* Prepare the it_insn_type for those encodings that don't set
18503 it_fsm_pre_encode ();
18505 opcode
->tencode ();
18507 it_fsm_post_encode ();
18510 if (!(inst
.error
|| inst
.relax
))
18512 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18513 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18514 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18516 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18521 /* Something has gone badly wrong if we try to relax a fixed size
18523 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18525 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18526 *opcode
->tvariant
);
18527 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18528 set those bits when Thumb-2 32-bit instructions are seen. The impact
18529 of relaxable instructions will be considered later after we finish all
18531 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18532 variant
= arm_arch_none
;
18534 variant
= cpu_variant
;
18535 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18536 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18539 check_neon_suffixes
;
18543 mapping_state (MAP_THUMB
);
18546 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18550 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18551 is_bx
= (opcode
->aencode
== do_bx
);
18553 /* Check that this instruction is supported for this CPU. */
18554 if (!(is_bx
&& fix_v4bx
)
18555 && !(opcode
->avariant
&&
18556 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18558 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18563 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18567 inst
.instruction
= opcode
->avalue
;
18568 if (opcode
->tag
== OT_unconditionalF
)
18569 inst
.instruction
|= 0xFU
<< 28;
18571 inst
.instruction
|= inst
.cond
<< 28;
18572 inst
.size
= INSN_SIZE
;
18573 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18575 it_fsm_pre_encode ();
18576 opcode
->aencode ();
18577 it_fsm_post_encode ();
18579 /* Arm mode bx is marked as both v4T and v5 because it's still required
18580 on a hypothetical non-thumb v5 core. */
18582 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18584 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18585 *opcode
->avariant
);
18587 check_neon_suffixes
;
18591 mapping_state (MAP_ARM
);
18596 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18604 check_it_blocks_finished (void)
18609 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18610 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18611 == MANUAL_IT_BLOCK
)
18613 as_warn (_("section '%s' finished with an open IT block."),
18617 if (now_it
.state
== MANUAL_IT_BLOCK
)
18618 as_warn (_("file finished with an open IT block."));
18622 /* Various frobbings of labels and their addresses. */
18625 arm_start_line_hook (void)
18627 last_label_seen
= NULL
;
18631 arm_frob_label (symbolS
* sym
)
18633 last_label_seen
= sym
;
18635 ARM_SET_THUMB (sym
, thumb_mode
);
18637 #if defined OBJ_COFF || defined OBJ_ELF
18638 ARM_SET_INTERWORK (sym
, support_interwork
);
18641 force_automatic_it_block_close ();
18643 /* Note - do not allow local symbols (.Lxxx) to be labelled
18644 as Thumb functions. This is because these labels, whilst
18645 they exist inside Thumb code, are not the entry points for
18646 possible ARM->Thumb calls. Also, these labels can be used
18647 as part of a computed goto or switch statement. eg gcc
18648 can generate code that looks like this:
18650 ldr r2, [pc, .Laaa]
18660 The first instruction loads the address of the jump table.
18661 The second instruction converts a table index into a byte offset.
18662 The third instruction gets the jump address out of the table.
18663 The fourth instruction performs the jump.
18665 If the address stored at .Laaa is that of a symbol which has the
18666 Thumb_Func bit set, then the linker will arrange for this address
18667 to have the bottom bit set, which in turn would mean that the
18668 address computation performed by the third instruction would end
18669 up with the bottom bit set. Since the ARM is capable of unaligned
18670 word loads, the instruction would then load the incorrect address
18671 out of the jump table, and chaos would ensue. */
18672 if (label_is_thumb_function_name
18673 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18674 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18676 /* When the address of a Thumb function is taken the bottom
18677 bit of that address should be set. This will allow
18678 interworking between Arm and Thumb functions to work
18681 THUMB_SET_FUNC (sym
, 1);
18683 label_is_thumb_function_name
= FALSE
;
18686 dwarf2_emit_label (sym
);
18690 arm_data_in_code (void)
18692 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18694 *input_line_pointer
= '/';
18695 input_line_pointer
+= 5;
18696 *input_line_pointer
= 0;
18704 arm_canonicalize_symbol_name (char * name
)
18708 if (thumb_mode
&& (len
= strlen (name
)) > 5
18709 && streq (name
+ len
- 5, "/data"))
18710 *(name
+ len
- 5) = 0;
18715 /* Table of all register names defined by default. The user can
18716 define additional names with .req. Note that all register names
18717 should appear in both upper and lowercase variants. Some registers
18718 also have mixed-case names. */
18720 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18721 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18722 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18723 #define REGSET(p,t) \
18724 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18725 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18726 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18727 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18728 #define REGSETH(p,t) \
18729 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18730 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18731 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18732 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18733 #define REGSET2(p,t) \
18734 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18735 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18736 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18737 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18738 #define SPLRBANK(base,bank,t) \
18739 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18740 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18741 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18742 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18743 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18744 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18746 static const struct reg_entry reg_names
[] =
18748 /* ARM integer registers. */
18749 REGSET(r
, RN
), REGSET(R
, RN
),
18751 /* ATPCS synonyms. */
18752 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18753 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18754 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18756 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18757 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18758 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18760 /* Well-known aliases. */
18761 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18762 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18764 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18765 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18767 /* Coprocessor numbers. */
18768 REGSET(p
, CP
), REGSET(P
, CP
),
18770 /* Coprocessor register numbers. The "cr" variants are for backward
18772 REGSET(c
, CN
), REGSET(C
, CN
),
18773 REGSET(cr
, CN
), REGSET(CR
, CN
),
18775 /* ARM banked registers. */
18776 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18777 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18778 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18779 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18780 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18781 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18782 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18784 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18785 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18786 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18787 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18788 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18789 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18790 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18791 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18793 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18794 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18795 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18796 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18797 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18798 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18799 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18800 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18801 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18803 /* FPA registers. */
18804 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18805 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18807 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18808 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18810 /* VFP SP registers. */
18811 REGSET(s
,VFS
), REGSET(S
,VFS
),
18812 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18814 /* VFP DP Registers. */
18815 REGSET(d
,VFD
), REGSET(D
,VFD
),
18816 /* Extra Neon DP registers. */
18817 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18819 /* Neon QP registers. */
18820 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18822 /* VFP control registers. */
18823 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18824 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18825 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18826 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18827 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18828 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18830 /* Maverick DSP coprocessor registers. */
18831 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18832 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18834 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18835 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18836 REGDEF(dspsc
,0,DSPSC
),
18838 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18839 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18840 REGDEF(DSPSC
,0,DSPSC
),
18842 /* iWMMXt data registers - p0, c0-15. */
18843 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18845 /* iWMMXt control registers - p1, c0-3. */
18846 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18847 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18848 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18849 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18851 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18852 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18853 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18854 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18855 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18857 /* XScale accumulator registers. */
18858 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18864 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18865 within psr_required_here. */
18866 static const struct asm_psr psrs
[] =
18868 /* Backward compatibility notation. Note that "all" is no longer
18869 truly all possible PSR bits. */
18870 {"all", PSR_c
| PSR_f
},
18874 /* Individual flags. */
18880 /* Combinations of flags. */
18881 {"fs", PSR_f
| PSR_s
},
18882 {"fx", PSR_f
| PSR_x
},
18883 {"fc", PSR_f
| PSR_c
},
18884 {"sf", PSR_s
| PSR_f
},
18885 {"sx", PSR_s
| PSR_x
},
18886 {"sc", PSR_s
| PSR_c
},
18887 {"xf", PSR_x
| PSR_f
},
18888 {"xs", PSR_x
| PSR_s
},
18889 {"xc", PSR_x
| PSR_c
},
18890 {"cf", PSR_c
| PSR_f
},
18891 {"cs", PSR_c
| PSR_s
},
18892 {"cx", PSR_c
| PSR_x
},
18893 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18894 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18895 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18896 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18897 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18898 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18899 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18900 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18901 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18902 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18903 {"scf", PSR_s
| PSR_c
| PSR_f
},
18904 {"scx", PSR_s
| PSR_c
| PSR_x
},
18905 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18906 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18907 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18908 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18909 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18910 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18911 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18912 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18913 {"csf", PSR_c
| PSR_s
| PSR_f
},
18914 {"csx", PSR_c
| PSR_s
| PSR_x
},
18915 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18916 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18917 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18918 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18919 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18920 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18921 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18922 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18923 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18924 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18925 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18926 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18927 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18928 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18929 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18930 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18931 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18932 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18933 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18934 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18935 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18936 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18937 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18938 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18939 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18940 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18943 /* Table of V7M psr names. */
18944 static const struct asm_psr v7m_psrs
[] =
18946 {"apsr", 0x0 }, {"APSR", 0x0 },
18947 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18948 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18949 {"psr", 0x3 }, {"PSR", 0x3 },
18950 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18951 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18952 {"epsr", 0x6 }, {"EPSR", 0x6 },
18953 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18954 {"msp", 0x8 }, {"MSP", 0x8 },
18955 {"psp", 0x9 }, {"PSP", 0x9 },
18956 {"msplim", 0xa }, {"MSPLIM", 0xa },
18957 {"psplim", 0xb }, {"PSPLIM", 0xb },
18958 {"primask", 0x10}, {"PRIMASK", 0x10},
18959 {"basepri", 0x11}, {"BASEPRI", 0x11},
18960 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18961 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18962 {"control", 0x14}, {"CONTROL", 0x14},
18963 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18964 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18965 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18966 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18967 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18968 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18969 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18970 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18971 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18974 /* Table of all shift-in-operand names. */
18975 static const struct asm_shift_name shift_names
[] =
18977 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18978 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18979 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18980 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18981 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18982 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18985 /* Table of all explicit relocation names. */
18987 static struct reloc_entry reloc_names
[] =
18989 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18990 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18991 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18992 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18993 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18994 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18995 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18996 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18997 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18998 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18999 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19000 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19001 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19002 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19003 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19004 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19005 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19006 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19010 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19011 static const struct asm_cond conds
[] =
19015 {"cs", 0x2}, {"hs", 0x2},
19016 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19030 #define UL_BARRIER(L,U,CODE,FEAT) \
19031 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19032 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19034 static struct asm_barrier_opt barrier_opt_names
[] =
19036 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19037 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19038 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19039 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19040 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19041 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19042 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19043 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19044 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19045 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19046 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19047 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19048 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19049 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19050 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19051 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19056 /* Table of ARM-format instructions. */
19058 /* Macros for gluing together operand strings. N.B. In all cases
19059 other than OPS0, the trailing OP_stop comes from default
19060 zero-initialization of the unspecified elements of the array. */
19061 #define OPS0() { OP_stop, }
19062 #define OPS1(a) { OP_##a, }
19063 #define OPS2(a,b) { OP_##a,OP_##b, }
19064 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19065 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19066 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19067 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19069 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19070 This is useful when mixing operands for ARM and THUMB, i.e. using the
19071 MIX_ARM_THUMB_OPERANDS macro.
19072 In order to use these macros, prefix the number of operands with _
19074 #define OPS_1(a) { a, }
19075 #define OPS_2(a,b) { a,b, }
19076 #define OPS_3(a,b,c) { a,b,c, }
19077 #define OPS_4(a,b,c,d) { a,b,c,d, }
19078 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19079 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19081 /* These macros abstract out the exact format of the mnemonic table and
19082 save some repeated characters. */
19084 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19085 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19086 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19087 THUMB_VARIANT, do_##ae, do_##te }
19089 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19090 a T_MNEM_xyz enumerator. */
19091 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19092 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19093 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19094 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19096 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19097 infix after the third character. */
19098 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19099 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19100 THUMB_VARIANT, do_##ae, do_##te }
19101 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19102 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19103 THUMB_VARIANT, do_##ae, do_##te }
19104 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19105 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19106 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19107 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19108 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19109 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19110 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19111 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19113 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19114 field is still 0xE. Many of the Thumb variants can be executed
19115 conditionally, so this is checked separately. */
19116 #define TUE(mnem, op, top, nops, ops, ae, te) \
19117 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19118 THUMB_VARIANT, do_##ae, do_##te }
19120 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19121 Used by mnemonics that have very minimal differences in the encoding for
19122 ARM and Thumb variants and can be handled in a common function. */
19123 #define TUEc(mnem, op, top, nops, ops, en) \
19124 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19125 THUMB_VARIANT, do_##en, do_##en }
19127 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19128 condition code field. */
19129 #define TUF(mnem, op, top, nops, ops, ae, te) \
19130 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19131 THUMB_VARIANT, do_##ae, do_##te }
19133 /* ARM-only variants of all the above. */
19134 #define CE(mnem, op, nops, ops, ae) \
19135 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19137 #define C3(mnem, op, nops, ops, ae) \
19138 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19140 /* Legacy mnemonics that always have conditional infix after the third
19142 #define CL(mnem, op, nops, ops, ae) \
19143 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19144 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19146 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19147 #define cCE(mnem, op, nops, ops, ae) \
19148 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19150 /* Legacy coprocessor instructions where conditional infix and conditional
19151 suffix are ambiguous. For consistency this includes all FPA instructions,
19152 not just the potentially ambiguous ones. */
19153 #define cCL(mnem, op, nops, ops, ae) \
19154 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19155 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19157 /* Coprocessor, takes either a suffix or a position-3 infix
19158 (for an FPA corner case). */
19159 #define C3E(mnem, op, nops, ops, ae) \
19160 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19161 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19163 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19164 { m1 #m2 m3, OPS##nops ops, \
19165 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19166 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19168 #define CM(m1, m2, op, nops, ops, ae) \
19169 xCM_ (m1, , m2, op, nops, ops, ae), \
19170 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19171 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19172 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19173 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19174 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19175 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19176 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19177 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19178 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19179 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19180 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19181 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19182 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19183 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19184 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19185 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19186 xCM_ (m1, le, m2, op, nops, ops, ae), \
19187 xCM_ (m1, al, m2, op, nops, ops, ae)
19189 #define UE(mnem, op, nops, ops, ae) \
19190 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19192 #define UF(mnem, op, nops, ops, ae) \
19193 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19195 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19196 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19197 use the same encoding function for each. */
19198 #define NUF(mnem, op, nops, ops, enc) \
19199 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19200 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19202 /* Neon data processing, version which indirects through neon_enc_tab for
19203 the various overloaded versions of opcodes. */
19204 #define nUF(mnem, op, nops, ops, enc) \
19205 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19206 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19208 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19210 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19211 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19212 THUMB_VARIANT, do_##enc, do_##enc }
19214 #define NCE(mnem, op, nops, ops, enc) \
19215 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19217 #define NCEF(mnem, op, nops, ops, enc) \
19218 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19220 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19221 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19222 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19223 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19225 #define nCE(mnem, op, nops, ops, enc) \
19226 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19228 #define nCEF(mnem, op, nops, ops, enc) \
19229 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19233 static const struct asm_opcode insns
[] =
19235 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19236 #define THUMB_VARIANT & arm_ext_v4t
19237 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19238 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19239 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19240 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19241 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19242 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19243 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19244 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19245 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19246 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19247 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19248 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19249 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19250 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19251 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19252 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19254 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19255 for setting PSR flag bits. They are obsolete in V6 and do not
19256 have Thumb equivalents. */
19257 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19258 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19259 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19260 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19261 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19262 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19263 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19264 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19265 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19267 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19268 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19269 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19270 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19272 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19273 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19274 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19276 OP_ADDRGLDR
),ldst
, t_ldst
),
19277 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19279 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19280 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19281 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19282 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19283 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19284 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19286 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19287 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19290 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19291 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19292 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19293 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19295 /* Thumb-compatibility pseudo ops. */
19296 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19297 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19298 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19299 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19300 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19301 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19302 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19303 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19304 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19305 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19306 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19307 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19309 /* These may simplify to neg. */
19310 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19311 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19313 #undef THUMB_VARIANT
19314 #define THUMB_VARIANT & arm_ext_os
19316 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19317 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19319 #undef THUMB_VARIANT
19320 #define THUMB_VARIANT & arm_ext_v6
19322 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19324 /* V1 instructions with no Thumb analogue prior to V6T2. */
19325 #undef THUMB_VARIANT
19326 #define THUMB_VARIANT & arm_ext_v6t2
19328 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19329 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19330 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19332 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19333 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19334 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19335 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19337 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19338 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19340 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19341 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19343 /* V1 instructions with no Thumb analogue at all. */
19344 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19345 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19347 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19348 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19349 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19350 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19351 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19352 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19353 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19354 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19357 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19358 #undef THUMB_VARIANT
19359 #define THUMB_VARIANT & arm_ext_v4t
19361 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19362 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19364 #undef THUMB_VARIANT
19365 #define THUMB_VARIANT & arm_ext_v6t2
19367 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19368 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19370 /* Generic coprocessor instructions. */
19371 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19372 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19373 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19374 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19375 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19376 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19377 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19380 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19382 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19383 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19386 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19387 #undef THUMB_VARIANT
19388 #define THUMB_VARIANT & arm_ext_msr
19390 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19391 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19394 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19395 #undef THUMB_VARIANT
19396 #define THUMB_VARIANT & arm_ext_v6t2
19398 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19399 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19400 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19401 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19402 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19403 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19404 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19405 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19408 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19409 #undef THUMB_VARIANT
19410 #define THUMB_VARIANT & arm_ext_v4t
19412 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19413 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19414 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19415 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19416 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19417 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19420 #define ARM_VARIANT & arm_ext_v4t_5
19422 /* ARM Architecture 4T. */
19423 /* Note: bx (and blx) are required on V5, even if the processor does
19424 not support Thumb. */
19425 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19428 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19429 #undef THUMB_VARIANT
19430 #define THUMB_VARIANT & arm_ext_v5t
19432 /* Note: blx has 2 variants; the .value coded here is for
19433 BLX(2). Only this variant has conditional execution. */
19434 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19435 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19437 #undef THUMB_VARIANT
19438 #define THUMB_VARIANT & arm_ext_v6t2
19440 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19441 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19442 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19443 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19444 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19445 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19446 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19447 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19450 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19451 #undef THUMB_VARIANT
19452 #define THUMB_VARIANT & arm_ext_v5exp
19454 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19455 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19456 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19457 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19459 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19460 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19462 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19463 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19464 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19465 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19467 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19468 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19469 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19470 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19472 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19473 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19475 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19476 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19477 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19478 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19481 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19482 #undef THUMB_VARIANT
19483 #define THUMB_VARIANT & arm_ext_v6t2
19485 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19486 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19488 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19489 ADDRGLDRS
), ldrd
, t_ldstd
),
19491 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19492 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19495 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19497 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19500 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & arm_ext_v6
19504 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19505 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19506 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19507 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19508 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19509 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19510 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19511 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19512 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19513 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19515 #undef THUMB_VARIANT
19516 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19518 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19519 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19521 #undef THUMB_VARIANT
19522 #define THUMB_VARIANT & arm_ext_v6t2
19524 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19525 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19527 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19528 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19530 /* ARM V6 not included in V7M. */
19531 #undef THUMB_VARIANT
19532 #define THUMB_VARIANT & arm_ext_v6_notm
19533 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19534 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19535 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19536 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19537 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19538 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19539 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19540 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19541 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19542 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19543 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19544 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19545 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19546 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19547 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19548 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19549 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19550 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19551 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19553 /* ARM V6 not included in V7M (eg. integer SIMD). */
19554 #undef THUMB_VARIANT
19555 #define THUMB_VARIANT & arm_ext_v6_dsp
19556 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19557 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19558 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19559 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19560 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19561 /* Old name for QASX. */
19562 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19563 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19564 /* Old name for QSAX. */
19565 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19566 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19567 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19569 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19570 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19571 /* Old name for SASX. */
19572 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19573 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19574 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19576 /* Old name for SHASX. */
19577 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19578 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19579 /* Old name for SHSAX. */
19580 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19582 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19583 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 /* Old name for SSAX. */
19585 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19586 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19587 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19588 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19589 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19590 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19591 /* Old name for UASX. */
19592 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19593 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19594 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19595 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19596 /* Old name for UHASX. */
19597 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19598 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19599 /* Old name for UHSAX. */
19600 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19601 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19602 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19603 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19604 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19605 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19606 /* Old name for UQASX. */
19607 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19608 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19609 /* Old name for UQSAX. */
19610 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19611 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19612 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19613 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19614 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19615 /* Old name for USAX. */
19616 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19617 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19618 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19619 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19620 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19621 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19622 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19623 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19624 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19625 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19626 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19627 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19628 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19629 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19630 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19631 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19632 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19633 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19634 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19635 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19636 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19637 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19638 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19639 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19640 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19641 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19642 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19643 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19644 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19645 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19646 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19647 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19648 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19649 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19652 #define ARM_VARIANT & arm_ext_v6k
19653 #undef THUMB_VARIANT
19654 #define THUMB_VARIANT & arm_ext_v6k
19656 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19657 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19658 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19659 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19661 #undef THUMB_VARIANT
19662 #define THUMB_VARIANT & arm_ext_v6_notm
19663 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19665 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19666 RRnpcb
), strexd
, t_strexd
),
19668 #undef THUMB_VARIANT
19669 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19670 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19672 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19674 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19676 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19678 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19681 #define ARM_VARIANT & arm_ext_sec
19682 #undef THUMB_VARIANT
19683 #define THUMB_VARIANT & arm_ext_sec
19685 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19688 #define ARM_VARIANT & arm_ext_virt
19689 #undef THUMB_VARIANT
19690 #define THUMB_VARIANT & arm_ext_virt
19692 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19693 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19696 #define ARM_VARIANT & arm_ext_pan
19697 #undef THUMB_VARIANT
19698 #define THUMB_VARIANT & arm_ext_pan
19700 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19703 #define ARM_VARIANT & arm_ext_v6t2
19704 #undef THUMB_VARIANT
19705 #define THUMB_VARIANT & arm_ext_v6t2
19707 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19708 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19709 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19710 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19712 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19713 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19715 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19716 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19717 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19718 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19720 #undef THUMB_VARIANT
19721 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19722 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19723 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19725 /* Thumb-only instructions. */
19727 #define ARM_VARIANT NULL
19728 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19729 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19731 /* ARM does not really have an IT instruction, so always allow it.
19732 The opcode is copied from Thumb in order to allow warnings in
19733 -mimplicit-it=[never | arm] modes. */
19735 #define ARM_VARIANT & arm_ext_v1
19736 #undef THUMB_VARIANT
19737 #define THUMB_VARIANT & arm_ext_v6t2
19739 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19740 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19741 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19742 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19743 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19744 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19745 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19746 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19747 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19748 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19749 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19750 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19751 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19752 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19753 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19754 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19755 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19756 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19758 /* Thumb2 only instructions. */
19760 #define ARM_VARIANT NULL
19762 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19763 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19764 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19765 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19766 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19767 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19769 /* Hardware division instructions. */
19771 #define ARM_VARIANT & arm_ext_adiv
19772 #undef THUMB_VARIANT
19773 #define THUMB_VARIANT & arm_ext_div
19775 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19776 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19778 /* ARM V6M/V7 instructions. */
19780 #define ARM_VARIANT & arm_ext_barrier
19781 #undef THUMB_VARIANT
19782 #define THUMB_VARIANT & arm_ext_barrier
19784 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19785 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19786 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19788 /* ARM V7 instructions. */
19790 #define ARM_VARIANT & arm_ext_v7
19791 #undef THUMB_VARIANT
19792 #define THUMB_VARIANT & arm_ext_v7
19794 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19795 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19798 #define ARM_VARIANT & arm_ext_mp
19799 #undef THUMB_VARIANT
19800 #define THUMB_VARIANT & arm_ext_mp
19802 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19804 /* AArchv8 instructions. */
19806 #define ARM_VARIANT & arm_ext_v8
19808 /* Instructions shared between armv8-a and armv8-m. */
19809 #undef THUMB_VARIANT
19810 #define THUMB_VARIANT & arm_ext_atomics
19812 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19813 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19814 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19815 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19816 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19817 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19818 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19819 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19820 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19821 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19823 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19825 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19827 #undef THUMB_VARIANT
19828 #define THUMB_VARIANT & arm_ext_v8
19830 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19831 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19832 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19834 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19836 /* ARMv8 T32 only. */
19838 #define ARM_VARIANT NULL
19839 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19840 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19841 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19843 /* FP for ARMv8. */
19845 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19846 #undef THUMB_VARIANT
19847 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19849 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19850 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19851 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19852 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19853 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19854 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19855 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19856 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19857 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19858 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19859 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19860 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19861 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19862 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19863 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19864 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19865 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19867 /* Crypto v1 extensions. */
19869 #define ARM_VARIANT & fpu_crypto_ext_armv8
19870 #undef THUMB_VARIANT
19871 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19873 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19874 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19875 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19876 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19877 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19878 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19879 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19880 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19881 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19882 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19883 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19884 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19885 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19886 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19889 #define ARM_VARIANT & crc_ext_armv8
19890 #undef THUMB_VARIANT
19891 #define THUMB_VARIANT & crc_ext_armv8
19892 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19893 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19894 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19895 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19896 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19897 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19899 /* ARMv8.2 RAS extension. */
19901 #define ARM_VARIANT & arm_ext_ras
19902 #undef THUMB_VARIANT
19903 #define THUMB_VARIANT & arm_ext_ras
19904 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19907 #define ARM_VARIANT & arm_ext_v8_3
19908 #undef THUMB_VARIANT
19909 #define THUMB_VARIANT & arm_ext_v8_3
19910 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19911 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19912 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19915 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19916 #undef THUMB_VARIANT
19917 #define THUMB_VARIANT NULL
19919 cCE("wfs", e200110
, 1, (RR
), rd
),
19920 cCE("rfs", e300110
, 1, (RR
), rd
),
19921 cCE("wfc", e400110
, 1, (RR
), rd
),
19922 cCE("rfc", e500110
, 1, (RR
), rd
),
19924 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19925 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19926 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19927 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19929 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19930 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19931 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19932 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19934 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20010 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20023 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20036 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20114 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20117 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20120 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20126 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20127 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20129 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20130 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20131 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20132 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20133 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20134 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20135 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20136 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20137 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20138 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20139 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20140 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20142 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20179 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20192 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20201 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20205 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20208 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20211 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20214 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20218 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20221 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20224 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20227 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20231 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20244 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20283 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20286 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20289 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20295 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20296 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20298 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20299 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20300 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20301 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20302 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20303 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20304 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20305 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20306 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20307 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20308 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20309 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20311 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20312 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20313 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20314 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20316 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20317 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20318 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20319 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20320 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20321 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20322 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20323 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20324 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20325 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20326 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20327 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20329 /* The implementation of the FIX instruction is broken on some
20330 assemblers, in that it accepts a precision specifier as well as a
20331 rounding specifier, despite the fact that this is meaningless.
20332 To be more compatible, we accept it as well, though of course it
20333 does not set any bits. */
20334 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20335 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20336 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20337 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20338 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20339 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20340 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20341 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20342 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20343 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20344 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20345 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20346 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20348 /* Instructions that were new with the real FPA, call them V2. */
20350 #define ARM_VARIANT & fpu_fpa_ext_v2
20352 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20353 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20354 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20355 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20356 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20357 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20360 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20362 /* Moves and type conversions. */
20363 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20364 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20365 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20366 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20367 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20368 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20369 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20370 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20371 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20372 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20373 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20374 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20375 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20376 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20378 /* Memory operations. */
20379 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20380 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20381 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20382 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20383 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20384 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20385 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20386 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20387 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20388 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20389 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20390 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20391 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20392 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20393 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20394 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20395 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20396 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20398 /* Monadic operations. */
20399 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20400 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20401 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20403 /* Dyadic operations. */
20404 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20405 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20406 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20407 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20408 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20409 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20410 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20411 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20412 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20415 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20416 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20417 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20418 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20420 /* Double precision load/store are still present on single precision
20421 implementations. */
20422 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20423 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20424 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20425 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20426 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20427 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20428 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20429 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20430 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20431 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20434 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20436 /* Moves and type conversions. */
20437 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20438 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20439 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20440 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20441 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20442 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20443 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20444 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20445 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20446 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20447 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20448 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20449 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20451 /* Monadic operations. */
20452 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20453 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20454 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20456 /* Dyadic operations. */
20457 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20458 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20459 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20460 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20461 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20462 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20463 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20464 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20465 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20468 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20469 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20470 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20471 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20474 #define ARM_VARIANT & fpu_vfp_ext_v2
20476 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20477 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20478 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20479 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20481 /* Instructions which may belong to either the Neon or VFP instruction sets.
20482 Individual encoder functions perform additional architecture checks. */
20484 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20485 #undef THUMB_VARIANT
20486 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20488 /* These mnemonics are unique to VFP. */
20489 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20490 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20491 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20492 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20493 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20494 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20495 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20496 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20497 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20498 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20500 /* Mnemonics shared by Neon and VFP. */
20501 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20502 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20503 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20505 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20506 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20508 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20509 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20511 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20512 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20513 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20514 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20515 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20516 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20517 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20518 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20520 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20521 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20522 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20523 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20526 /* NOTE: All VMOV encoding is special-cased! */
20527 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20528 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20531 #define ARM_VARIANT & arm_ext_fp16
20532 #undef THUMB_VARIANT
20533 #define THUMB_VARIANT & arm_ext_fp16
20534 /* New instructions added from v8.2, allowing the extraction and insertion of
20535 the upper 16 bits of a 32-bit vector register. */
20536 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20537 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20539 #undef THUMB_VARIANT
20540 #define THUMB_VARIANT & fpu_neon_ext_v1
20542 #define ARM_VARIANT & fpu_neon_ext_v1
20544 /* Data processing with three registers of the same length. */
20545 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20546 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20547 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20548 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20549 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20550 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20551 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20552 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20553 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20554 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20555 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20556 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20557 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20558 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20559 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20560 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20561 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20562 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20563 /* If not immediate, fall back to neon_dyadic_i64_su.
20564 shl_imm should accept I8 I16 I32 I64,
20565 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20566 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20567 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20568 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20569 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20570 /* Logic ops, types optional & ignored. */
20571 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20572 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20573 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20574 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20575 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20576 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20577 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20578 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20579 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20580 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20581 /* Bitfield ops, untyped. */
20582 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20583 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20584 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20585 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20586 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20587 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20588 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20589 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20590 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20591 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20592 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20593 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20594 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20595 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20596 back to neon_dyadic_if_su. */
20597 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20598 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20599 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20600 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20601 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20602 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20603 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20604 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20605 /* Comparison. Type I8 I16 I32 F32. */
20606 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20607 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20608 /* As above, D registers only. */
20609 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20610 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20611 /* Int and float variants, signedness unimportant. */
20612 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20613 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20614 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20615 /* Add/sub take types I8 I16 I32 I64 F32. */
20616 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20617 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20618 /* vtst takes sizes 8, 16, 32. */
20619 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20620 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20621 /* VMUL takes I8 I16 I32 F32 P8. */
20622 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20623 /* VQD{R}MULH takes S16 S32. */
20624 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20625 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20626 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20627 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20628 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20629 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20630 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20631 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20632 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20633 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20634 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20635 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20636 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20637 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20638 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20639 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20640 /* ARM v8.1 extension. */
20641 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20642 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20643 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20644 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20646 /* Two address, int/float. Types S8 S16 S32 F32. */
20647 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20648 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20650 /* Data processing with two registers and a shift amount. */
20651 /* Right shifts, and variants with rounding.
20652 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20653 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20654 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20655 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20656 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20657 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20658 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20659 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20660 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20661 /* Shift and insert. Sizes accepted 8 16 32 64. */
20662 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20663 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20664 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20665 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20666 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20667 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20668 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20669 /* Right shift immediate, saturating & narrowing, with rounding variants.
20670 Types accepted S16 S32 S64 U16 U32 U64. */
20671 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20672 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20673 /* As above, unsigned. Types accepted S16 S32 S64. */
20674 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20675 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20676 /* Right shift narrowing. Types accepted I16 I32 I64. */
20677 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20678 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20679 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20680 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20681 /* CVT with optional immediate for fixed-point variant. */
20682 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20684 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20685 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20687 /* Data processing, three registers of different lengths. */
20688 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20689 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20690 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20691 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20692 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20693 /* If not scalar, fall back to neon_dyadic_long.
20694 Vector types as above, scalar types S16 S32 U16 U32. */
20695 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20696 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20697 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20698 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20699 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20700 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20701 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20702 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20703 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20704 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20705 /* Saturating doubling multiplies. Types S16 S32. */
20706 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20707 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20708 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20709 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20710 S16 S32 U16 U32. */
20711 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20713 /* Extract. Size 8. */
20714 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20715 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20717 /* Two registers, miscellaneous. */
20718 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20719 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20720 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20721 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20722 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20723 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20724 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20725 /* Vector replicate. Sizes 8 16 32. */
20726 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20727 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20728 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20729 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20730 /* VMOVN. Types I16 I32 I64. */
20731 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20732 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20733 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20734 /* VQMOVUN. Types S16 S32 S64. */
20735 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20736 /* VZIP / VUZP. Sizes 8 16 32. */
20737 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20738 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20739 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20740 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20741 /* VQABS / VQNEG. Types S8 S16 S32. */
20742 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20743 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20744 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20745 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20746 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20747 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20748 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20749 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20750 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20751 /* Reciprocal estimates. Types U32 F16 F32. */
20752 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20753 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20754 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20755 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20756 /* VCLS. Types S8 S16 S32. */
20757 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20758 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20759 /* VCLZ. Types I8 I16 I32. */
20760 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20761 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20762 /* VCNT. Size 8. */
20763 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20764 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20765 /* Two address, untyped. */
20766 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20767 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20768 /* VTRN. Sizes 8 16 32. */
20769 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20770 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20772 /* Table lookup. Size 8. */
20773 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20774 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20776 #undef THUMB_VARIANT
20777 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20779 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20781 /* Neon element/structure load/store. */
20782 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20783 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20784 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20785 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20786 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20787 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20788 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20789 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20791 #undef THUMB_VARIANT
20792 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20794 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20795 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20796 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20797 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20798 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20799 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20800 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20801 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20802 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20803 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20805 #undef THUMB_VARIANT
20806 #define THUMB_VARIANT & fpu_vfp_ext_v3
20808 #define ARM_VARIANT & fpu_vfp_ext_v3
20810 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20811 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20812 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20813 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20814 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20815 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20816 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20817 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20818 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20821 #define ARM_VARIANT & fpu_vfp_ext_fma
20822 #undef THUMB_VARIANT
20823 #define THUMB_VARIANT & fpu_vfp_ext_fma
20824 /* Mnemonics shared by Neon and VFP. These are included in the
20825 VFP FMA variant; NEON and VFP FMA always includes the NEON
20826 FMA instructions. */
20827 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20828 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20829 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20830 the v form should always be used. */
20831 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20832 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20833 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20834 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20835 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20836 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20838 #undef THUMB_VARIANT
20840 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20842 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20843 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20844 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20845 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20846 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20847 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20848 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20849 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20852 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20854 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20855 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20856 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20857 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20858 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20859 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20860 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20861 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20862 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20863 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20864 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20865 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20866 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20867 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20868 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20869 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20870 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20871 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20872 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20873 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20874 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20875 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20876 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20877 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20878 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20879 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20880 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20881 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20882 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20883 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20884 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20885 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20886 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20887 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20888 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20889 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20890 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20891 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20901 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20921 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20922 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20923 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20924 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20926 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20928 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20929 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20939 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20940 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20941 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20942 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20943 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20944 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20945 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20946 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20947 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20948 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20949 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20950 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20951 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20952 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20953 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20954 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20955 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20956 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20957 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20958 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20959 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20960 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20961 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20962 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20963 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20964 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20965 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20966 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20967 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20968 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20969 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20970 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20971 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20972 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20973 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20974 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20975 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20976 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20977 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20978 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20979 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20980 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20981 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20982 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20983 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20984 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20985 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20986 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20987 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20988 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20989 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20990 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20991 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20992 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20993 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20994 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20995 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20997 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20998 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20999 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21000 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21001 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21002 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21003 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21004 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21006 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21007 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21008 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21009 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21010 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21011 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21012 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21013 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21014 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21018 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21020 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21021 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21022 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21023 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21024 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21025 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21026 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21027 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21041 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21046 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21050 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21051 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21056 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21057 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21058 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21059 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21060 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21061 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21062 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21063 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21064 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21065 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21066 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21067 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21068 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21069 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21070 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21071 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21072 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21073 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21074 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21075 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21076 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21079 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21081 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21082 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21083 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21084 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21085 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21086 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21087 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21088 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21089 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21090 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21091 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21092 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21093 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21094 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21095 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21096 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21097 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21098 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21099 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21100 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21101 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21102 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21103 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21104 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21105 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21106 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21107 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21108 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21109 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21110 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21111 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21112 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21113 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21114 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21115 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21116 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21117 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21118 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21119 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21120 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21121 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21122 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21123 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21124 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21125 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21126 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21127 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21128 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21129 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21130 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21131 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21132 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21133 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21134 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21135 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21136 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21137 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21138 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21139 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21140 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21141 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21142 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21143 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21144 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21145 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21146 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21147 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21148 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21149 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21150 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21151 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21152 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21153 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21154 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21155 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21156 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21158 /* ARMv8-M instructions. */
21160 #define ARM_VARIANT NULL
21161 #undef THUMB_VARIANT
21162 #define THUMB_VARIANT & arm_ext_v8m
21163 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21164 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21165 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21166 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21167 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21168 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21169 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21171 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21172 instructions behave as nop if no VFP is present. */
21173 #undef THUMB_VARIANT
21174 #define THUMB_VARIANT & arm_ext_v8m_main
21175 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21176 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21179 #undef THUMB_VARIANT
21205 /* MD interface: bits in the object file. */
21207 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21208 for use in the a.out file, and stores them in the array pointed to by buf.
21209 This knows about the endian-ness of the target machine and does
21210 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21211 2 (short) and 4 (long) Floating numbers are put out as a series of
21212 LITTLENUMS (shorts, here at least). */
21215 md_number_to_chars (char * buf
, valueT val
, int n
)
21217 if (target_big_endian
)
21218 number_to_chars_bigendian (buf
, val
, n
);
21220 number_to_chars_littleendian (buf
, val
, n
);
21224 md_chars_to_number (char * buf
, int n
)
21227 unsigned char * where
= (unsigned char *) buf
;
21229 if (target_big_endian
)
21234 result
|= (*where
++ & 255);
21242 result
|= (where
[n
] & 255);
21249 /* MD interface: Sections. */
21251 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21252 that an rs_machine_dependent frag may reach. */
21255 arm_frag_max_var (fragS
*fragp
)
21257 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21258 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21260 Note that we generate relaxable instructions even for cases that don't
21261 really need it, like an immediate that's a trivial constant. So we're
21262 overestimating the instruction size for some of those cases. Rather
21263 than putting more intelligence here, it would probably be better to
21264 avoid generating a relaxation frag in the first place when it can be
21265 determined up front that a short instruction will suffice. */
21267 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21271 /* Estimate the size of a frag before relaxing. Assume everything fits in
21275 md_estimate_size_before_relax (fragS
* fragp
,
21276 segT segtype ATTRIBUTE_UNUSED
)
21282 /* Convert a machine dependent frag. */
21285 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21287 unsigned long insn
;
21288 unsigned long old_op
;
21296 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21298 old_op
= bfd_get_16(abfd
, buf
);
21299 if (fragp
->fr_symbol
)
21301 exp
.X_op
= O_symbol
;
21302 exp
.X_add_symbol
= fragp
->fr_symbol
;
21306 exp
.X_op
= O_constant
;
21308 exp
.X_add_number
= fragp
->fr_offset
;
21309 opcode
= fragp
->fr_subtype
;
21312 case T_MNEM_ldr_pc
:
21313 case T_MNEM_ldr_pc2
:
21314 case T_MNEM_ldr_sp
:
21315 case T_MNEM_str_sp
:
21322 if (fragp
->fr_var
== 4)
21324 insn
= THUMB_OP32 (opcode
);
21325 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21327 insn
|= (old_op
& 0x700) << 4;
21331 insn
|= (old_op
& 7) << 12;
21332 insn
|= (old_op
& 0x38) << 13;
21334 insn
|= 0x00000c00;
21335 put_thumb32_insn (buf
, insn
);
21336 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21340 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21342 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21345 if (fragp
->fr_var
== 4)
21347 insn
= THUMB_OP32 (opcode
);
21348 insn
|= (old_op
& 0xf0) << 4;
21349 put_thumb32_insn (buf
, insn
);
21350 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21354 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21355 exp
.X_add_number
-= 4;
21363 if (fragp
->fr_var
== 4)
21365 int r0off
= (opcode
== T_MNEM_mov
21366 || opcode
== T_MNEM_movs
) ? 0 : 8;
21367 insn
= THUMB_OP32 (opcode
);
21368 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21369 insn
|= (old_op
& 0x700) << r0off
;
21370 put_thumb32_insn (buf
, insn
);
21371 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21375 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21380 if (fragp
->fr_var
== 4)
21382 insn
= THUMB_OP32(opcode
);
21383 put_thumb32_insn (buf
, insn
);
21384 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21387 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21391 if (fragp
->fr_var
== 4)
21393 insn
= THUMB_OP32(opcode
);
21394 insn
|= (old_op
& 0xf00) << 14;
21395 put_thumb32_insn (buf
, insn
);
21396 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21399 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21402 case T_MNEM_add_sp
:
21403 case T_MNEM_add_pc
:
21404 case T_MNEM_inc_sp
:
21405 case T_MNEM_dec_sp
:
21406 if (fragp
->fr_var
== 4)
21408 /* ??? Choose between add and addw. */
21409 insn
= THUMB_OP32 (opcode
);
21410 insn
|= (old_op
& 0xf0) << 4;
21411 put_thumb32_insn (buf
, insn
);
21412 if (opcode
== T_MNEM_add_pc
)
21413 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21415 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21418 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21426 if (fragp
->fr_var
== 4)
21428 insn
= THUMB_OP32 (opcode
);
21429 insn
|= (old_op
& 0xf0) << 4;
21430 insn
|= (old_op
& 0xf) << 16;
21431 put_thumb32_insn (buf
, insn
);
21432 if (insn
& (1 << 20))
21433 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21435 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21438 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21444 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21445 (enum bfd_reloc_code_real
) reloc_type
);
21446 fixp
->fx_file
= fragp
->fr_file
;
21447 fixp
->fx_line
= fragp
->fr_line
;
21448 fragp
->fr_fix
+= fragp
->fr_var
;
21450 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21451 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21452 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21453 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21456 /* Return the size of a relaxable immediate operand instruction.
21457 SHIFT and SIZE specify the form of the allowable immediate. */
21459 relax_immediate (fragS
*fragp
, int size
, int shift
)
21465 /* ??? Should be able to do better than this. */
21466 if (fragp
->fr_symbol
)
21469 low
= (1 << shift
) - 1;
21470 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21471 offset
= fragp
->fr_offset
;
21472 /* Force misaligned offsets to 32-bit variant. */
21475 if (offset
& ~mask
)
21480 /* Get the address of a symbol during relaxation. */
21482 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21488 sym
= fragp
->fr_symbol
;
21489 sym_frag
= symbol_get_frag (sym
);
21490 know (S_GET_SEGMENT (sym
) != absolute_section
21491 || sym_frag
== &zero_address_frag
);
21492 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21494 /* If frag has yet to be reached on this pass, assume it will
21495 move by STRETCH just as we did. If this is not so, it will
21496 be because some frag between grows, and that will force
21500 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21504 /* Adjust stretch for any alignment frag. Note that if have
21505 been expanding the earlier code, the symbol may be
21506 defined in what appears to be an earlier frag. FIXME:
21507 This doesn't handle the fr_subtype field, which specifies
21508 a maximum number of bytes to skip when doing an
21510 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21512 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21515 stretch
= - ((- stretch
)
21516 & ~ ((1 << (int) f
->fr_offset
) - 1));
21518 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21530 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21533 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21538 /* Assume worst case for symbols not known to be in the same section. */
21539 if (fragp
->fr_symbol
== NULL
21540 || !S_IS_DEFINED (fragp
->fr_symbol
)
21541 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21542 || S_IS_WEAK (fragp
->fr_symbol
))
21545 val
= relaxed_symbol_addr (fragp
, stretch
);
21546 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21547 addr
= (addr
+ 4) & ~3;
21548 /* Force misaligned targets to 32-bit variant. */
21552 if (val
< 0 || val
> 1020)
21557 /* Return the size of a relaxable add/sub immediate instruction. */
21559 relax_addsub (fragS
*fragp
, asection
*sec
)
21564 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21565 op
= bfd_get_16(sec
->owner
, buf
);
21566 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21567 return relax_immediate (fragp
, 8, 0);
21569 return relax_immediate (fragp
, 3, 0);
21572 /* Return TRUE iff the definition of symbol S could be pre-empted
21573 (overridden) at link or load time. */
21575 symbol_preemptible (symbolS
*s
)
21577 /* Weak symbols can always be pre-empted. */
21581 /* Non-global symbols cannot be pre-empted. */
21582 if (! S_IS_EXTERNAL (s
))
21586 /* In ELF, a global symbol can be marked protected, or private. In that
21587 case it can't be pre-empted (other definitions in the same link unit
21588 would violate the ODR). */
21589 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21593 /* Other global symbols might be pre-empted. */
21597 /* Return the size of a relaxable branch instruction. BITS is the
21598 size of the offset field in the narrow instruction. */
21601 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21607 /* Assume worst case for symbols not known to be in the same section. */
21608 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21609 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21610 || S_IS_WEAK (fragp
->fr_symbol
))
21614 /* A branch to a function in ARM state will require interworking. */
21615 if (S_IS_DEFINED (fragp
->fr_symbol
)
21616 && ARM_IS_FUNC (fragp
->fr_symbol
))
21620 if (symbol_preemptible (fragp
->fr_symbol
))
21623 val
= relaxed_symbol_addr (fragp
, stretch
);
21624 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21627 /* Offset is a signed value *2 */
21629 if (val
>= limit
|| val
< -limit
)
21635 /* Relax a machine dependent frag. This returns the amount by which
21636 the current size of the frag should change. */
21639 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21644 oldsize
= fragp
->fr_var
;
21645 switch (fragp
->fr_subtype
)
21647 case T_MNEM_ldr_pc2
:
21648 newsize
= relax_adr (fragp
, sec
, stretch
);
21650 case T_MNEM_ldr_pc
:
21651 case T_MNEM_ldr_sp
:
21652 case T_MNEM_str_sp
:
21653 newsize
= relax_immediate (fragp
, 8, 2);
21657 newsize
= relax_immediate (fragp
, 5, 2);
21661 newsize
= relax_immediate (fragp
, 5, 1);
21665 newsize
= relax_immediate (fragp
, 5, 0);
21668 newsize
= relax_adr (fragp
, sec
, stretch
);
21674 newsize
= relax_immediate (fragp
, 8, 0);
21677 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21680 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21682 case T_MNEM_add_sp
:
21683 case T_MNEM_add_pc
:
21684 newsize
= relax_immediate (fragp
, 8, 2);
21686 case T_MNEM_inc_sp
:
21687 case T_MNEM_dec_sp
:
21688 newsize
= relax_immediate (fragp
, 7, 2);
21694 newsize
= relax_addsub (fragp
, sec
);
21700 fragp
->fr_var
= newsize
;
21701 /* Freeze wide instructions that are at or before the same location as
21702 in the previous pass. This avoids infinite loops.
21703 Don't freeze them unconditionally because targets may be artificially
21704 misaligned by the expansion of preceding frags. */
21705 if (stretch
<= 0 && newsize
> 2)
21707 md_convert_frag (sec
->owner
, sec
, fragp
);
21711 return newsize
- oldsize
;
21714 /* Round up a section size to the appropriate boundary. */
21717 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21720 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21721 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21723 /* For a.out, force the section size to be aligned. If we don't do
21724 this, BFD will align it for us, but it will not write out the
21725 final bytes of the section. This may be a bug in BFD, but it is
21726 easier to fix it here since that is how the other a.out targets
21730 align
= bfd_get_section_alignment (stdoutput
, segment
);
21731 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21738 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21739 of an rs_align_code fragment. */
21742 arm_handle_align (fragS
* fragP
)
21744 static unsigned char const arm_noop
[2][2][4] =
21747 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21748 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21751 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21752 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21755 static unsigned char const thumb_noop
[2][2][2] =
21758 {0xc0, 0x46}, /* LE */
21759 {0x46, 0xc0}, /* BE */
21762 {0x00, 0xbf}, /* LE */
21763 {0xbf, 0x00} /* BE */
21766 static unsigned char const wide_thumb_noop
[2][4] =
21767 { /* Wide Thumb-2 */
21768 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21769 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21772 unsigned bytes
, fix
, noop_size
;
21774 const unsigned char * noop
;
21775 const unsigned char *narrow_noop
= NULL
;
21780 if (fragP
->fr_type
!= rs_align_code
)
21783 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21784 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21787 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21788 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21790 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21792 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21794 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21795 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21797 narrow_noop
= thumb_noop
[1][target_big_endian
];
21798 noop
= wide_thumb_noop
[target_big_endian
];
21801 noop
= thumb_noop
[0][target_big_endian
];
21809 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21810 ? selected_cpu
: arm_arch_none
,
21812 [target_big_endian
];
21819 fragP
->fr_var
= noop_size
;
21821 if (bytes
& (noop_size
- 1))
21823 fix
= bytes
& (noop_size
- 1);
21825 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21827 memset (p
, 0, fix
);
21834 if (bytes
& noop_size
)
21836 /* Insert a narrow noop. */
21837 memcpy (p
, narrow_noop
, noop_size
);
21839 bytes
-= noop_size
;
21843 /* Use wide noops for the remainder */
21847 while (bytes
>= noop_size
)
21849 memcpy (p
, noop
, noop_size
);
21851 bytes
-= noop_size
;
21855 fragP
->fr_fix
+= fix
;
21858 /* Called from md_do_align. Used to create an alignment
21859 frag in a code section. */
21862 arm_frag_align_code (int n
, int max
)
21866 /* We assume that there will never be a requirement
21867 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21868 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21873 _("alignments greater than %d bytes not supported in .text sections."),
21874 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21875 as_fatal ("%s", err_msg
);
21878 p
= frag_var (rs_align_code
,
21879 MAX_MEM_FOR_RS_ALIGN_CODE
,
21881 (relax_substateT
) max
,
21888 /* Perform target specific initialisation of a frag.
21889 Note - despite the name this initialisation is not done when the frag
21890 is created, but only when its type is assigned. A frag can be created
21891 and used a long time before its type is set, so beware of assuming that
21892 this initialisation is performed first. */
21896 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21898 /* Record whether this frag is in an ARM or a THUMB area. */
21899 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21902 #else /* OBJ_ELF is defined. */
21904 arm_init_frag (fragS
* fragP
, int max_chars
)
21906 int frag_thumb_mode
;
21908 /* If the current ARM vs THUMB mode has not already
21909 been recorded into this frag then do so now. */
21910 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21911 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21913 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21915 /* Record a mapping symbol for alignment frags. We will delete this
21916 later if the alignment ends up empty. */
21917 switch (fragP
->fr_type
)
21920 case rs_align_test
:
21922 mapping_state_2 (MAP_DATA
, max_chars
);
21924 case rs_align_code
:
21925 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21932 /* When we change sections we need to issue a new mapping symbol. */
21935 arm_elf_change_section (void)
21937 /* Link an unlinked unwind index table section to the .text section. */
21938 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21939 && elf_linked_to_section (now_seg
) == NULL
)
21940 elf_linked_to_section (now_seg
) = text_section
;
21944 arm_elf_section_type (const char * str
, size_t len
)
21946 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21947 return SHT_ARM_EXIDX
;
21952 /* Code to deal with unwinding tables. */
21954 static void add_unwind_adjustsp (offsetT
);
21956 /* Generate any deferred unwind frame offset. */
21959 flush_pending_unwind (void)
21963 offset
= unwind
.pending_offset
;
21964 unwind
.pending_offset
= 0;
21966 add_unwind_adjustsp (offset
);
21969 /* Add an opcode to this list for this function. Two-byte opcodes should
21970 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21974 add_unwind_opcode (valueT op
, int length
)
21976 /* Add any deferred stack adjustment. */
21977 if (unwind
.pending_offset
)
21978 flush_pending_unwind ();
21980 unwind
.sp_restored
= 0;
21982 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21984 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21985 if (unwind
.opcodes
)
21986 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21987 unwind
.opcode_alloc
);
21989 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21994 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21996 unwind
.opcode_count
++;
22000 /* Add unwind opcodes to adjust the stack pointer. */
22003 add_unwind_adjustsp (offsetT offset
)
22007 if (offset
> 0x200)
22009 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22014 /* Long form: 0xb2, uleb128. */
22015 /* This might not fit in a word so add the individual bytes,
22016 remembering the list is built in reverse order. */
22017 o
= (valueT
) ((offset
- 0x204) >> 2);
22019 add_unwind_opcode (0, 1);
22021 /* Calculate the uleb128 encoding of the offset. */
22025 bytes
[n
] = o
& 0x7f;
22031 /* Add the insn. */
22033 add_unwind_opcode (bytes
[n
- 1], 1);
22034 add_unwind_opcode (0xb2, 1);
22036 else if (offset
> 0x100)
22038 /* Two short opcodes. */
22039 add_unwind_opcode (0x3f, 1);
22040 op
= (offset
- 0x104) >> 2;
22041 add_unwind_opcode (op
, 1);
22043 else if (offset
> 0)
22045 /* Short opcode. */
22046 op
= (offset
- 4) >> 2;
22047 add_unwind_opcode (op
, 1);
22049 else if (offset
< 0)
22052 while (offset
> 0x100)
22054 add_unwind_opcode (0x7f, 1);
22057 op
= ((offset
- 4) >> 2) | 0x40;
22058 add_unwind_opcode (op
, 1);
22062 /* Finish the list of unwind opcodes for this function. */
22064 finish_unwind_opcodes (void)
22068 if (unwind
.fp_used
)
22070 /* Adjust sp as necessary. */
22071 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22072 flush_pending_unwind ();
22074 /* After restoring sp from the frame pointer. */
22075 op
= 0x90 | unwind
.fp_reg
;
22076 add_unwind_opcode (op
, 1);
22079 flush_pending_unwind ();
22083 /* Start an exception table entry. If idx is nonzero this is an index table
22087 start_unwind_section (const segT text_seg
, int idx
)
22089 const char * text_name
;
22090 const char * prefix
;
22091 const char * prefix_once
;
22092 const char * group_name
;
22100 prefix
= ELF_STRING_ARM_unwind
;
22101 prefix_once
= ELF_STRING_ARM_unwind_once
;
22102 type
= SHT_ARM_EXIDX
;
22106 prefix
= ELF_STRING_ARM_unwind_info
;
22107 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22108 type
= SHT_PROGBITS
;
22111 text_name
= segment_name (text_seg
);
22112 if (streq (text_name
, ".text"))
22115 if (strncmp (text_name
, ".gnu.linkonce.t.",
22116 strlen (".gnu.linkonce.t.")) == 0)
22118 prefix
= prefix_once
;
22119 text_name
+= strlen (".gnu.linkonce.t.");
22122 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22128 /* Handle COMDAT group. */
22129 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22131 group_name
= elf_group_name (text_seg
);
22132 if (group_name
== NULL
)
22134 as_bad (_("Group section `%s' has no group signature"),
22135 segment_name (text_seg
));
22136 ignore_rest_of_line ();
22139 flags
|= SHF_GROUP
;
22143 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22146 /* Set the section link for index tables. */
22148 elf_linked_to_section (now_seg
) = text_seg
;
22152 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22153 personality routine data. Returns zero, or the index table value for
22154 an inline entry. */
22157 create_unwind_entry (int have_data
)
22162 /* The current word of data. */
22164 /* The number of bytes left in this word. */
22167 finish_unwind_opcodes ();
22169 /* Remember the current text section. */
22170 unwind
.saved_seg
= now_seg
;
22171 unwind
.saved_subseg
= now_subseg
;
22173 start_unwind_section (now_seg
, 0);
22175 if (unwind
.personality_routine
== NULL
)
22177 if (unwind
.personality_index
== -2)
22180 as_bad (_("handlerdata in cantunwind frame"));
22181 return 1; /* EXIDX_CANTUNWIND. */
22184 /* Use a default personality routine if none is specified. */
22185 if (unwind
.personality_index
== -1)
22187 if (unwind
.opcode_count
> 3)
22188 unwind
.personality_index
= 1;
22190 unwind
.personality_index
= 0;
22193 /* Space for the personality routine entry. */
22194 if (unwind
.personality_index
== 0)
22196 if (unwind
.opcode_count
> 3)
22197 as_bad (_("too many unwind opcodes for personality routine 0"));
22201 /* All the data is inline in the index table. */
22204 while (unwind
.opcode_count
> 0)
22206 unwind
.opcode_count
--;
22207 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22211 /* Pad with "finish" opcodes. */
22213 data
= (data
<< 8) | 0xb0;
22220 /* We get two opcodes "free" in the first word. */
22221 size
= unwind
.opcode_count
- 2;
22225 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22226 if (unwind
.personality_index
!= -1)
22228 as_bad (_("attempt to recreate an unwind entry"));
22232 /* An extra byte is required for the opcode count. */
22233 size
= unwind
.opcode_count
+ 1;
22236 size
= (size
+ 3) >> 2;
22238 as_bad (_("too many unwind opcodes"));
22240 frag_align (2, 0, 0);
22241 record_alignment (now_seg
, 2);
22242 unwind
.table_entry
= expr_build_dot ();
22244 /* Allocate the table entry. */
22245 ptr
= frag_more ((size
<< 2) + 4);
22246 /* PR 13449: Zero the table entries in case some of them are not used. */
22247 memset (ptr
, 0, (size
<< 2) + 4);
22248 where
= frag_now_fix () - ((size
<< 2) + 4);
22250 switch (unwind
.personality_index
)
22253 /* ??? Should this be a PLT generating relocation? */
22254 /* Custom personality routine. */
22255 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22256 BFD_RELOC_ARM_PREL31
);
22261 /* Set the first byte to the number of additional words. */
22262 data
= size
> 0 ? size
- 1 : 0;
22266 /* ABI defined personality routines. */
22268 /* Three opcodes bytes are packed into the first word. */
22275 /* The size and first two opcode bytes go in the first word. */
22276 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22281 /* Should never happen. */
22285 /* Pack the opcodes into words (MSB first), reversing the list at the same
22287 while (unwind
.opcode_count
> 0)
22291 md_number_to_chars (ptr
, data
, 4);
22296 unwind
.opcode_count
--;
22298 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22301 /* Finish off the last word. */
22304 /* Pad with "finish" opcodes. */
22306 data
= (data
<< 8) | 0xb0;
22308 md_number_to_chars (ptr
, data
, 4);
22313 /* Add an empty descriptor if there is no user-specified data. */
22314 ptr
= frag_more (4);
22315 md_number_to_chars (ptr
, 0, 4);
22322 /* Initialize the DWARF-2 unwind information for this procedure. */
22325 tc_arm_frame_initial_instructions (void)
22327 cfi_add_CFA_def_cfa (REG_SP
, 0);
22329 #endif /* OBJ_ELF */
22331 /* Convert REGNAME to a DWARF-2 register number. */
22334 tc_arm_regname_to_dw2regnum (char *regname
)
22336 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22340 /* PR 16694: Allow VFP registers as well. */
22341 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22345 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22354 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22358 exp
.X_op
= O_secrel
;
22359 exp
.X_add_symbol
= symbol
;
22360 exp
.X_add_number
= 0;
22361 emit_expr (&exp
, size
);
22365 /* MD interface: Symbol and relocation handling. */
22367 /* Return the address within the segment that a PC-relative fixup is
22368 relative to. For ARM, PC-relative fixups applied to instructions
22369 are generally relative to the location of the fixup plus 8 bytes.
22370 Thumb branches are offset by 4, and Thumb loads relative to PC
22371 require special handling. */
22374 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22376 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22378 /* If this is pc-relative and we are going to emit a relocation
22379 then we just want to put out any pipeline compensation that the linker
22380 will need. Otherwise we want to use the calculated base.
22381 For WinCE we skip the bias for externals as well, since this
22382 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22384 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22385 || (arm_force_relocation (fixP
)
22387 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22393 switch (fixP
->fx_r_type
)
22395 /* PC relative addressing on the Thumb is slightly odd as the
22396 bottom two bits of the PC are forced to zero for the
22397 calculation. This happens *after* application of the
22398 pipeline offset. However, Thumb adrl already adjusts for
22399 this, so we need not do it again. */
22400 case BFD_RELOC_ARM_THUMB_ADD
:
22403 case BFD_RELOC_ARM_THUMB_OFFSET
:
22404 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22405 case BFD_RELOC_ARM_T32_ADD_PC12
:
22406 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22407 return (base
+ 4) & ~3;
22409 /* Thumb branches are simply offset by +4. */
22410 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22411 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22412 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22413 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22414 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22417 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22419 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22420 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22421 && ARM_IS_FUNC (fixP
->fx_addsy
)
22422 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22423 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22426 /* BLX is like branches above, but forces the low two bits of PC to
22428 case BFD_RELOC_THUMB_PCREL_BLX
:
22430 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22431 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22432 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22433 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22434 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22435 return (base
+ 4) & ~3;
22437 /* ARM mode branches are offset by +8. However, the Windows CE
22438 loader expects the relocation not to take this into account. */
22439 case BFD_RELOC_ARM_PCREL_BLX
:
22441 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22442 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22443 && ARM_IS_FUNC (fixP
->fx_addsy
)
22444 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22445 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22448 case BFD_RELOC_ARM_PCREL_CALL
:
22450 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22451 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22452 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22453 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22454 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22457 case BFD_RELOC_ARM_PCREL_BRANCH
:
22458 case BFD_RELOC_ARM_PCREL_JUMP
:
22459 case BFD_RELOC_ARM_PLT32
:
22461 /* When handling fixups immediately, because we have already
22462 discovered the value of a symbol, or the address of the frag involved
22463 we must account for the offset by +8, as the OS loader will never see the reloc.
22464 see fixup_segment() in write.c
22465 The S_IS_EXTERNAL test handles the case of global symbols.
22466 Those need the calculated base, not just the pipe compensation the linker will need. */
22468 && fixP
->fx_addsy
!= NULL
22469 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22470 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22478 /* ARM mode loads relative to PC are also offset by +8. Unlike
22479 branches, the Windows CE loader *does* expect the relocation
22480 to take this into account. */
22481 case BFD_RELOC_ARM_OFFSET_IMM
:
22482 case BFD_RELOC_ARM_OFFSET_IMM8
:
22483 case BFD_RELOC_ARM_HWLITERAL
:
22484 case BFD_RELOC_ARM_LITERAL
:
22485 case BFD_RELOC_ARM_CP_OFF_IMM
:
22489 /* Other PC-relative relocations are un-offset. */
22495 static bfd_boolean flag_warn_syms
= TRUE
;
22498 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22500 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22501 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22502 does mean that the resulting code might be very confusing to the reader.
22503 Also this warning can be triggered if the user omits an operand before
22504 an immediate address, eg:
22508 GAS treats this as an assignment of the value of the symbol foo to a
22509 symbol LDR, and so (without this code) it will not issue any kind of
22510 warning or error message.
22512 Note - ARM instructions are case-insensitive but the strings in the hash
22513 table are all stored in lower case, so we must first ensure that name is
22515 if (flag_warn_syms
&& arm_ops_hsh
)
22517 char * nbuf
= strdup (name
);
22520 for (p
= nbuf
; *p
; p
++)
22522 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22524 static struct hash_control
* already_warned
= NULL
;
22526 if (already_warned
== NULL
)
22527 already_warned
= hash_new ();
22528 /* Only warn about the symbol once. To keep the code
22529 simple we let hash_insert do the lookup for us. */
22530 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22531 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22540 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22541 Otherwise we have no need to default values of symbols. */
22544 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22547 if (name
[0] == '_' && name
[1] == 'G'
22548 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22552 if (symbol_find (name
))
22553 as_bad (_("GOT already in the symbol table"));
22555 GOT_symbol
= symbol_new (name
, undefined_section
,
22556 (valueT
) 0, & zero_address_frag
);
22566 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22567 computed as two separate immediate values, added together. We
22568 already know that this value cannot be computed by just one ARM
22571 static unsigned int
22572 validate_immediate_twopart (unsigned int val
,
22573 unsigned int * highpart
)
22578 for (i
= 0; i
< 32; i
+= 2)
22579 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22585 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22587 else if (a
& 0xff0000)
22589 if (a
& 0xff000000)
22591 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22595 gas_assert (a
& 0xff000000);
22596 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22599 return (a
& 0xff) | (i
<< 7);
22606 validate_offset_imm (unsigned int val
, int hwse
)
22608 if ((hwse
&& val
> 255) || val
> 4095)
22613 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22614 negative immediate constant by altering the instruction. A bit of
22619 by inverting the second operand, and
22622 by negating the second operand. */
22625 negate_data_op (unsigned long * instruction
,
22626 unsigned long value
)
22629 unsigned long negated
, inverted
;
22631 negated
= encode_arm_immediate (-value
);
22632 inverted
= encode_arm_immediate (~value
);
22634 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22637 /* First negates. */
22638 case OPCODE_SUB
: /* ADD <-> SUB */
22639 new_inst
= OPCODE_ADD
;
22644 new_inst
= OPCODE_SUB
;
22648 case OPCODE_CMP
: /* CMP <-> CMN */
22649 new_inst
= OPCODE_CMN
;
22654 new_inst
= OPCODE_CMP
;
22658 /* Now Inverted ops. */
22659 case OPCODE_MOV
: /* MOV <-> MVN */
22660 new_inst
= OPCODE_MVN
;
22665 new_inst
= OPCODE_MOV
;
22669 case OPCODE_AND
: /* AND <-> BIC */
22670 new_inst
= OPCODE_BIC
;
22675 new_inst
= OPCODE_AND
;
22679 case OPCODE_ADC
: /* ADC <-> SBC */
22680 new_inst
= OPCODE_SBC
;
22685 new_inst
= OPCODE_ADC
;
22689 /* We cannot do anything. */
22694 if (value
== (unsigned) FAIL
)
22697 *instruction
&= OPCODE_MASK
;
22698 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22702 /* Like negate_data_op, but for Thumb-2. */
22704 static unsigned int
22705 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22709 unsigned int negated
, inverted
;
22711 negated
= encode_thumb32_immediate (-value
);
22712 inverted
= encode_thumb32_immediate (~value
);
22714 rd
= (*instruction
>> 8) & 0xf;
22715 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22718 /* ADD <-> SUB. Includes CMP <-> CMN. */
22719 case T2_OPCODE_SUB
:
22720 new_inst
= T2_OPCODE_ADD
;
22724 case T2_OPCODE_ADD
:
22725 new_inst
= T2_OPCODE_SUB
;
22729 /* ORR <-> ORN. Includes MOV <-> MVN. */
22730 case T2_OPCODE_ORR
:
22731 new_inst
= T2_OPCODE_ORN
;
22735 case T2_OPCODE_ORN
:
22736 new_inst
= T2_OPCODE_ORR
;
22740 /* AND <-> BIC. TST has no inverted equivalent. */
22741 case T2_OPCODE_AND
:
22742 new_inst
= T2_OPCODE_BIC
;
22749 case T2_OPCODE_BIC
:
22750 new_inst
= T2_OPCODE_AND
;
22755 case T2_OPCODE_ADC
:
22756 new_inst
= T2_OPCODE_SBC
;
22760 case T2_OPCODE_SBC
:
22761 new_inst
= T2_OPCODE_ADC
;
22765 /* We cannot do anything. */
22770 if (value
== (unsigned int)FAIL
)
22773 *instruction
&= T2_OPCODE_MASK
;
22774 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22778 /* Read a 32-bit thumb instruction from buf. */
22779 static unsigned long
22780 get_thumb32_insn (char * buf
)
22782 unsigned long insn
;
22783 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22784 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22790 /* We usually want to set the low bit on the address of thumb function
22791 symbols. In particular .word foo - . should have the low bit set.
22792 Generic code tries to fold the difference of two symbols to
22793 a constant. Prevent this and force a relocation when the first symbols
22794 is a thumb function. */
22797 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22799 if (op
== O_subtract
22800 && l
->X_op
== O_symbol
22801 && r
->X_op
== O_symbol
22802 && THUMB_IS_FUNC (l
->X_add_symbol
))
22804 l
->X_op
= O_subtract
;
22805 l
->X_op_symbol
= r
->X_add_symbol
;
22806 l
->X_add_number
-= r
->X_add_number
;
22810 /* Process as normal. */
22814 /* Encode Thumb2 unconditional branches and calls. The encoding
22815 for the 2 are identical for the immediate values. */
22818 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22820 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22823 addressT S
, I1
, I2
, lo
, hi
;
22825 S
= (value
>> 24) & 0x01;
22826 I1
= (value
>> 23) & 0x01;
22827 I2
= (value
>> 22) & 0x01;
22828 hi
= (value
>> 12) & 0x3ff;
22829 lo
= (value
>> 1) & 0x7ff;
22830 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22831 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22832 newval
|= (S
<< 10) | hi
;
22833 newval2
&= ~T2I1I2MASK
;
22834 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22835 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22836 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22840 md_apply_fix (fixS
* fixP
,
22844 offsetT value
= * valP
;
22846 unsigned int newimm
;
22847 unsigned long temp
;
22849 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22851 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22853 /* Note whether this will delete the relocation. */
22855 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22858 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22859 consistency with the behaviour on 32-bit hosts. Remember value
22861 value
&= 0xffffffff;
22862 value
^= 0x80000000;
22863 value
-= 0x80000000;
22866 fixP
->fx_addnumber
= value
;
22868 /* Same treatment for fixP->fx_offset. */
22869 fixP
->fx_offset
&= 0xffffffff;
22870 fixP
->fx_offset
^= 0x80000000;
22871 fixP
->fx_offset
-= 0x80000000;
22873 switch (fixP
->fx_r_type
)
22875 case BFD_RELOC_NONE
:
22876 /* This will need to go in the object file. */
22880 case BFD_RELOC_ARM_IMMEDIATE
:
22881 /* We claim that this fixup has been processed here,
22882 even if in fact we generate an error because we do
22883 not have a reloc for it, so tc_gen_reloc will reject it. */
22886 if (fixP
->fx_addsy
)
22888 const char *msg
= 0;
22890 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22891 msg
= _("undefined symbol %s used as an immediate value");
22892 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22893 msg
= _("symbol %s is in a different section");
22894 else if (S_IS_WEAK (fixP
->fx_addsy
))
22895 msg
= _("symbol %s is weak and may be overridden later");
22899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22900 msg
, S_GET_NAME (fixP
->fx_addsy
));
22905 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22907 /* If the offset is negative, we should use encoding A2 for ADR. */
22908 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22909 newimm
= negate_data_op (&temp
, value
);
22912 newimm
= encode_arm_immediate (value
);
22914 /* If the instruction will fail, see if we can fix things up by
22915 changing the opcode. */
22916 if (newimm
== (unsigned int) FAIL
)
22917 newimm
= negate_data_op (&temp
, value
);
22918 /* MOV accepts both ARM modified immediate (A1 encoding) and
22919 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22920 When disassembling, MOV is preferred when there is no encoding
22922 if (newimm
== (unsigned int) FAIL
22923 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22924 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22925 && !((temp
>> SBIT_SHIFT
) & 0x1)
22926 && value
>= 0 && value
<= 0xffff)
22928 /* Clear bits[23:20] to change encoding from A1 to A2. */
22929 temp
&= 0xff0fffff;
22930 /* Encoding high 4bits imm. Code below will encode the remaining
22932 temp
|= (value
& 0x0000f000) << 4;
22933 newimm
= value
& 0x00000fff;
22937 if (newimm
== (unsigned int) FAIL
)
22939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22940 _("invalid constant (%lx) after fixup"),
22941 (unsigned long) value
);
22945 newimm
|= (temp
& 0xfffff000);
22946 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22949 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22951 unsigned int highpart
= 0;
22952 unsigned int newinsn
= 0xe1a00000; /* nop. */
22954 if (fixP
->fx_addsy
)
22956 const char *msg
= 0;
22958 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22959 msg
= _("undefined symbol %s used as an immediate value");
22960 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22961 msg
= _("symbol %s is in a different section");
22962 else if (S_IS_WEAK (fixP
->fx_addsy
))
22963 msg
= _("symbol %s is weak and may be overridden later");
22967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22968 msg
, S_GET_NAME (fixP
->fx_addsy
));
22973 newimm
= encode_arm_immediate (value
);
22974 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22976 /* If the instruction will fail, see if we can fix things up by
22977 changing the opcode. */
22978 if (newimm
== (unsigned int) FAIL
22979 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22981 /* No ? OK - try using two ADD instructions to generate
22983 newimm
= validate_immediate_twopart (value
, & highpart
);
22985 /* Yes - then make sure that the second instruction is
22987 if (newimm
!= (unsigned int) FAIL
)
22989 /* Still No ? Try using a negated value. */
22990 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22991 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22992 /* Otherwise - give up. */
22995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22996 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23001 /* Replace the first operand in the 2nd instruction (which
23002 is the PC) with the destination register. We have
23003 already added in the PC in the first instruction and we
23004 do not want to do it again. */
23005 newinsn
&= ~ 0xf0000;
23006 newinsn
|= ((newinsn
& 0x0f000) << 4);
23009 newimm
|= (temp
& 0xfffff000);
23010 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23012 highpart
|= (newinsn
& 0xfffff000);
23013 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23017 case BFD_RELOC_ARM_OFFSET_IMM
:
23018 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23020 /* Fall through. */
23022 case BFD_RELOC_ARM_LITERAL
:
23028 if (validate_offset_imm (value
, 0) == FAIL
)
23030 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23032 _("invalid literal constant: pool needs to be closer"));
23034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23035 _("bad immediate value for offset (%ld)"),
23040 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23042 newval
&= 0xfffff000;
23045 newval
&= 0xff7ff000;
23046 newval
|= value
| (sign
? INDEX_UP
: 0);
23048 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23051 case BFD_RELOC_ARM_OFFSET_IMM8
:
23052 case BFD_RELOC_ARM_HWLITERAL
:
23058 if (validate_offset_imm (value
, 1) == FAIL
)
23060 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23062 _("invalid literal constant: pool needs to be closer"));
23064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23065 _("bad immediate value for 8-bit offset (%ld)"),
23070 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23072 newval
&= 0xfffff0f0;
23075 newval
&= 0xff7ff0f0;
23076 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23078 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23081 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23082 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23084 _("bad immediate value for offset (%ld)"), (long) value
);
23087 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23089 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23092 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23093 /* This is a complicated relocation used for all varieties of Thumb32
23094 load/store instruction with immediate offset:
23096 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23097 *4, optional writeback(W)
23098 (doubleword load/store)
23100 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23101 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23102 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23103 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23104 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23106 Uppercase letters indicate bits that are already encoded at
23107 this point. Lowercase letters are our problem. For the
23108 second block of instructions, the secondary opcode nybble
23109 (bits 8..11) is present, and bit 23 is zero, even if this is
23110 a PC-relative operation. */
23111 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23113 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23115 if ((newval
& 0xf0000000) == 0xe0000000)
23117 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23119 newval
|= (1 << 23);
23122 if (value
% 4 != 0)
23124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23125 _("offset not a multiple of 4"));
23131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23132 _("offset out of range"));
23137 else if ((newval
& 0x000f0000) == 0x000f0000)
23139 /* PC-relative, 12-bit offset. */
23141 newval
|= (1 << 23);
23146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23147 _("offset out of range"));
23152 else if ((newval
& 0x00000100) == 0x00000100)
23154 /* Writeback: 8-bit, +/- offset. */
23156 newval
|= (1 << 9);
23161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23162 _("offset out of range"));
23167 else if ((newval
& 0x00000f00) == 0x00000e00)
23169 /* T-instruction: positive 8-bit offset. */
23170 if (value
< 0 || value
> 0xff)
23172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23173 _("offset out of range"));
23181 /* Positive 12-bit or negative 8-bit offset. */
23185 newval
|= (1 << 23);
23195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23196 _("offset out of range"));
23203 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23204 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23207 case BFD_RELOC_ARM_SHIFT_IMM
:
23208 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23209 if (((unsigned long) value
) > 32
23211 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23214 _("shift expression is too large"));
23219 /* Shifts of zero must be done as lsl. */
23221 else if (value
== 32)
23223 newval
&= 0xfffff07f;
23224 newval
|= (value
& 0x1f) << 7;
23225 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23228 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23229 case BFD_RELOC_ARM_T32_ADD_IMM
:
23230 case BFD_RELOC_ARM_T32_IMM12
:
23231 case BFD_RELOC_ARM_T32_ADD_PC12
:
23232 /* We claim that this fixup has been processed here,
23233 even if in fact we generate an error because we do
23234 not have a reloc for it, so tc_gen_reloc will reject it. */
23238 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23241 _("undefined symbol %s used as an immediate value"),
23242 S_GET_NAME (fixP
->fx_addsy
));
23246 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23248 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23251 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23252 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23253 Thumb2 modified immediate encoding (T2). */
23254 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23255 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23257 newimm
= encode_thumb32_immediate (value
);
23258 if (newimm
== (unsigned int) FAIL
)
23259 newimm
= thumb32_negate_data_op (&newval
, value
);
23261 if (newimm
== (unsigned int) FAIL
)
23263 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23265 /* Turn add/sum into addw/subw. */
23266 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23267 newval
= (newval
& 0xfeffffff) | 0x02000000;
23268 /* No flat 12-bit imm encoding for addsw/subsw. */
23269 if ((newval
& 0x00100000) == 0)
23271 /* 12 bit immediate for addw/subw. */
23275 newval
^= 0x00a00000;
23278 newimm
= (unsigned int) FAIL
;
23285 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23286 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23287 disassembling, MOV is preferred when there is no encoding
23289 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23290 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23291 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23292 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23293 && value
>= 0 && value
<=0xffff)
23295 /* Toggle bit[25] to change encoding from T2 to T3. */
23297 /* Clear bits[19:16]. */
23298 newval
&= 0xfff0ffff;
23299 /* Encoding high 4bits imm. Code below will encode the
23300 remaining low 12bits. */
23301 newval
|= (value
& 0x0000f000) << 4;
23302 newimm
= value
& 0x00000fff;
23307 if (newimm
== (unsigned int)FAIL
)
23309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23310 _("invalid constant (%lx) after fixup"),
23311 (unsigned long) value
);
23315 newval
|= (newimm
& 0x800) << 15;
23316 newval
|= (newimm
& 0x700) << 4;
23317 newval
|= (newimm
& 0x0ff);
23319 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23320 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23323 case BFD_RELOC_ARM_SMC
:
23324 if (((unsigned long) value
) > 0xffff)
23325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23326 _("invalid smc expression"));
23327 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23328 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23329 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23332 case BFD_RELOC_ARM_HVC
:
23333 if (((unsigned long) value
) > 0xffff)
23334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23335 _("invalid hvc expression"));
23336 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23337 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23338 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23341 case BFD_RELOC_ARM_SWI
:
23342 if (fixP
->tc_fix_data
!= 0)
23344 if (((unsigned long) value
) > 0xff)
23345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23346 _("invalid swi expression"));
23347 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23349 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23353 if (((unsigned long) value
) > 0x00ffffff)
23354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23355 _("invalid swi expression"));
23356 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23358 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23362 case BFD_RELOC_ARM_MULTI
:
23363 if (((unsigned long) value
) > 0xffff)
23364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23365 _("invalid expression in load/store multiple"));
23366 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23367 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23371 case BFD_RELOC_ARM_PCREL_CALL
:
23373 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23375 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23376 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23377 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23378 /* Flip the bl to blx. This is a simple flip
23379 bit here because we generate PCREL_CALL for
23380 unconditional bls. */
23382 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23383 newval
= newval
| 0x10000000;
23384 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23390 goto arm_branch_common
;
23392 case BFD_RELOC_ARM_PCREL_JUMP
:
23393 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23395 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23396 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23397 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23399 /* This would map to a bl<cond>, b<cond>,
23400 b<always> to a Thumb function. We
23401 need to force a relocation for this particular
23403 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23406 /* Fall through. */
23408 case BFD_RELOC_ARM_PLT32
:
23410 case BFD_RELOC_ARM_PCREL_BRANCH
:
23412 goto arm_branch_common
;
23414 case BFD_RELOC_ARM_PCREL_BLX
:
23417 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23419 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23420 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23421 && ARM_IS_FUNC (fixP
->fx_addsy
))
23423 /* Flip the blx to a bl and warn. */
23424 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23425 newval
= 0xeb000000;
23426 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23427 _("blx to '%s' an ARM ISA state function changed to bl"),
23429 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23435 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23436 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23440 /* We are going to store value (shifted right by two) in the
23441 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23442 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23443 also be be clear. */
23445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23446 _("misaligned branch destination"));
23447 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23448 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23451 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23453 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23454 newval
|= (value
>> 2) & 0x00ffffff;
23455 /* Set the H bit on BLX instructions. */
23459 newval
|= 0x01000000;
23461 newval
&= ~0x01000000;
23463 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23467 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23468 /* CBZ can only branch forward. */
23470 /* Attempts to use CBZ to branch to the next instruction
23471 (which, strictly speaking, are prohibited) will be turned into
23474 FIXME: It may be better to remove the instruction completely and
23475 perform relaxation. */
23478 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23479 newval
= 0xbf00; /* NOP encoding T1 */
23480 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23487 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23489 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23490 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23491 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23496 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23497 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23500 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23502 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23503 newval
|= (value
& 0x1ff) >> 1;
23504 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23508 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23509 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23512 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23514 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23515 newval
|= (value
& 0xfff) >> 1;
23516 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23520 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23522 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23523 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23524 && ARM_IS_FUNC (fixP
->fx_addsy
)
23525 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23527 /* Force a relocation for a branch 20 bits wide. */
23530 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23532 _("conditional branch out of range"));
23534 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23537 addressT S
, J1
, J2
, lo
, hi
;
23539 S
= (value
& 0x00100000) >> 20;
23540 J2
= (value
& 0x00080000) >> 19;
23541 J1
= (value
& 0x00040000) >> 18;
23542 hi
= (value
& 0x0003f000) >> 12;
23543 lo
= (value
& 0x00000ffe) >> 1;
23545 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23546 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23547 newval
|= (S
<< 10) | hi
;
23548 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23549 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23550 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23554 case BFD_RELOC_THUMB_PCREL_BLX
:
23555 /* If there is a blx from a thumb state function to
23556 another thumb function flip this to a bl and warn
23560 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23561 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23562 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23564 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23565 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23566 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23568 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23569 newval
= newval
| 0x1000;
23570 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23571 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23576 goto thumb_bl_common
;
23578 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23579 /* A bl from Thumb state ISA to an internal ARM state function
23580 is converted to a blx. */
23582 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23583 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23584 && ARM_IS_FUNC (fixP
->fx_addsy
)
23585 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23587 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23588 newval
= newval
& ~0x1000;
23589 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23590 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23596 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23597 /* For a BLX instruction, make sure that the relocation is rounded up
23598 to a word boundary. This follows the semantics of the instruction
23599 which specifies that bit 1 of the target address will come from bit
23600 1 of the base address. */
23601 value
= (value
+ 3) & ~ 3;
23604 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23605 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23606 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23609 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23611 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23613 else if ((value
& ~0x1ffffff)
23614 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23616 _("Thumb2 branch out of range"));
23619 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23620 encode_thumb2_b_bl_offset (buf
, value
);
23624 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23625 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23628 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23629 encode_thumb2_b_bl_offset (buf
, value
);
23634 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23639 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23640 md_number_to_chars (buf
, value
, 2);
23644 case BFD_RELOC_ARM_TLS_CALL
:
23645 case BFD_RELOC_ARM_THM_TLS_CALL
:
23646 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23647 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23648 case BFD_RELOC_ARM_TLS_GOTDESC
:
23649 case BFD_RELOC_ARM_TLS_GD32
:
23650 case BFD_RELOC_ARM_TLS_LE32
:
23651 case BFD_RELOC_ARM_TLS_IE32
:
23652 case BFD_RELOC_ARM_TLS_LDM32
:
23653 case BFD_RELOC_ARM_TLS_LDO32
:
23654 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23657 case BFD_RELOC_ARM_GOT32
:
23658 case BFD_RELOC_ARM_GOTOFF
:
23661 case BFD_RELOC_ARM_GOT_PREL
:
23662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23663 md_number_to_chars (buf
, value
, 4);
23666 case BFD_RELOC_ARM_TARGET2
:
23667 /* TARGET2 is not partial-inplace, so we need to write the
23668 addend here for REL targets, because it won't be written out
23669 during reloc processing later. */
23670 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23671 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23675 case BFD_RELOC_RVA
:
23677 case BFD_RELOC_ARM_TARGET1
:
23678 case BFD_RELOC_ARM_ROSEGREL32
:
23679 case BFD_RELOC_ARM_SBREL32
:
23680 case BFD_RELOC_32_PCREL
:
23682 case BFD_RELOC_32_SECREL
:
23684 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23686 /* For WinCE we only do this for pcrel fixups. */
23687 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23689 md_number_to_chars (buf
, value
, 4);
23693 case BFD_RELOC_ARM_PREL31
:
23694 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23696 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23697 if ((value
^ (value
>> 1)) & 0x40000000)
23699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23700 _("rel31 relocation overflow"));
23702 newval
|= value
& 0x7fffffff;
23703 md_number_to_chars (buf
, newval
, 4);
23708 case BFD_RELOC_ARM_CP_OFF_IMM
:
23709 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23710 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23711 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23713 newval
= get_thumb32_insn (buf
);
23714 if ((newval
& 0x0f200f00) == 0x0d000900)
23716 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23717 has permitted values that are multiples of 2, in the range 0
23719 if (value
< -510 || value
> 510 || (value
& 1))
23720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23721 _("co-processor offset out of range"));
23723 else if (value
< -1023 || value
> 1023 || (value
& 3))
23724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23725 _("co-processor offset out of range"));
23730 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23731 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23732 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23734 newval
= get_thumb32_insn (buf
);
23736 newval
&= 0xffffff00;
23739 newval
&= 0xff7fff00;
23740 if ((newval
& 0x0f200f00) == 0x0d000900)
23742 /* This is a fp16 vstr/vldr.
23744 It requires the immediate offset in the instruction is shifted
23745 left by 1 to be a half-word offset.
23747 Here, left shift by 1 first, and later right shift by 2
23748 should get the right offset. */
23751 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23753 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23754 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23755 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23757 put_thumb32_insn (buf
, newval
);
23760 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23761 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23762 if (value
< -255 || value
> 255)
23763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23764 _("co-processor offset out of range"));
23766 goto cp_off_common
;
23768 case BFD_RELOC_ARM_THUMB_OFFSET
:
23769 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23770 /* Exactly what ranges, and where the offset is inserted depends
23771 on the type of instruction, we can establish this from the
23773 switch (newval
>> 12)
23775 case 4: /* PC load. */
23776 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23777 forced to zero for these loads; md_pcrel_from has already
23778 compensated for this. */
23780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23781 _("invalid offset, target not word aligned (0x%08lX)"),
23782 (((unsigned long) fixP
->fx_frag
->fr_address
23783 + (unsigned long) fixP
->fx_where
) & ~3)
23784 + (unsigned long) value
);
23786 if (value
& ~0x3fc)
23787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23788 _("invalid offset, value too big (0x%08lX)"),
23791 newval
|= value
>> 2;
23794 case 9: /* SP load/store. */
23795 if (value
& ~0x3fc)
23796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23797 _("invalid offset, value too big (0x%08lX)"),
23799 newval
|= value
>> 2;
23802 case 6: /* Word load/store. */
23804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23805 _("invalid offset, value too big (0x%08lX)"),
23807 newval
|= value
<< 4; /* 6 - 2. */
23810 case 7: /* Byte load/store. */
23812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23813 _("invalid offset, value too big (0x%08lX)"),
23815 newval
|= value
<< 6;
23818 case 8: /* Halfword load/store. */
23820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23821 _("invalid offset, value too big (0x%08lX)"),
23823 newval
|= value
<< 5; /* 6 - 1. */
23827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23828 "Unable to process relocation for thumb opcode: %lx",
23829 (unsigned long) newval
);
23832 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23835 case BFD_RELOC_ARM_THUMB_ADD
:
23836 /* This is a complicated relocation, since we use it for all of
23837 the following immediate relocations:
23841 9bit ADD/SUB SP word-aligned
23842 10bit ADD PC/SP word-aligned
23844 The type of instruction being processed is encoded in the
23851 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23853 int rd
= (newval
>> 4) & 0xf;
23854 int rs
= newval
& 0xf;
23855 int subtract
= !!(newval
& 0x8000);
23857 /* Check for HI regs, only very restricted cases allowed:
23858 Adjusting SP, and using PC or SP to get an address. */
23859 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23860 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23862 _("invalid Hi register with immediate"));
23864 /* If value is negative, choose the opposite instruction. */
23868 subtract
= !subtract
;
23870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23871 _("immediate value out of range"));
23876 if (value
& ~0x1fc)
23877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23878 _("invalid immediate for stack address calculation"));
23879 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23880 newval
|= value
>> 2;
23882 else if (rs
== REG_PC
|| rs
== REG_SP
)
23884 /* PR gas/18541. If the addition is for a defined symbol
23885 within range of an ADR instruction then accept it. */
23888 && fixP
->fx_addsy
!= NULL
)
23892 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23893 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23894 || S_IS_WEAK (fixP
->fx_addsy
))
23896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23897 _("address calculation needs a strongly defined nearby symbol"));
23901 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23903 /* Round up to the next 4-byte boundary. */
23908 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23913 _("symbol too far away"));
23923 if (subtract
|| value
& ~0x3fc)
23924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23925 _("invalid immediate for address calculation (value = 0x%08lX)"),
23926 (unsigned long) (subtract
? - value
: value
));
23927 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23929 newval
|= value
>> 2;
23934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23935 _("immediate value out of range"));
23936 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23937 newval
|= (rd
<< 8) | value
;
23942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23943 _("immediate value out of range"));
23944 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23945 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23948 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23951 case BFD_RELOC_ARM_THUMB_IMM
:
23952 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23953 if (value
< 0 || value
> 255)
23954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23955 _("invalid immediate: %ld is out of range"),
23958 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23961 case BFD_RELOC_ARM_THUMB_SHIFT
:
23962 /* 5bit shift value (0..32). LSL cannot take 32. */
23963 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23964 temp
= newval
& 0xf800;
23965 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23967 _("invalid shift value: %ld"), (long) value
);
23968 /* Shifts of zero must be encoded as LSL. */
23970 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23971 /* Shifts of 32 are encoded as zero. */
23972 else if (value
== 32)
23974 newval
|= value
<< 6;
23975 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23978 case BFD_RELOC_VTABLE_INHERIT
:
23979 case BFD_RELOC_VTABLE_ENTRY
:
23983 case BFD_RELOC_ARM_MOVW
:
23984 case BFD_RELOC_ARM_MOVT
:
23985 case BFD_RELOC_ARM_THUMB_MOVW
:
23986 case BFD_RELOC_ARM_THUMB_MOVT
:
23987 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23989 /* REL format relocations are limited to a 16-bit addend. */
23990 if (!fixP
->fx_done
)
23992 if (value
< -0x8000 || value
> 0x7fff)
23993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23994 _("offset out of range"));
23996 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23997 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24002 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24003 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24005 newval
= get_thumb32_insn (buf
);
24006 newval
&= 0xfbf08f00;
24007 newval
|= (value
& 0xf000) << 4;
24008 newval
|= (value
& 0x0800) << 15;
24009 newval
|= (value
& 0x0700) << 4;
24010 newval
|= (value
& 0x00ff);
24011 put_thumb32_insn (buf
, newval
);
24015 newval
= md_chars_to_number (buf
, 4);
24016 newval
&= 0xfff0f000;
24017 newval
|= value
& 0x0fff;
24018 newval
|= (value
& 0xf000) << 4;
24019 md_number_to_chars (buf
, newval
, 4);
24024 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24025 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24026 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24027 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24028 gas_assert (!fixP
->fx_done
);
24031 bfd_boolean is_mov
;
24032 bfd_vma encoded_addend
= value
;
24034 /* Check that addend can be encoded in instruction. */
24035 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24037 _("the offset 0x%08lX is not representable"),
24038 (unsigned long) encoded_addend
);
24040 /* Extract the instruction. */
24041 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24042 is_mov
= (insn
& 0xf800) == 0x2000;
24047 if (!seg
->use_rela_p
)
24048 insn
|= encoded_addend
;
24054 /* Extract the instruction. */
24055 /* Encoding is the following
24060 /* The following conditions must be true :
24065 rd
= (insn
>> 4) & 0xf;
24067 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24069 _("Unable to process relocation for thumb opcode: %lx"),
24070 (unsigned long) insn
);
24072 /* Encode as ADD immediate8 thumb 1 code. */
24073 insn
= 0x3000 | (rd
<< 8);
24075 /* Place the encoded addend into the first 8 bits of the
24077 if (!seg
->use_rela_p
)
24078 insn
|= encoded_addend
;
24081 /* Update the instruction. */
24082 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24086 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24087 case BFD_RELOC_ARM_ALU_PC_G0
:
24088 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24089 case BFD_RELOC_ARM_ALU_PC_G1
:
24090 case BFD_RELOC_ARM_ALU_PC_G2
:
24091 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24092 case BFD_RELOC_ARM_ALU_SB_G0
:
24093 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24094 case BFD_RELOC_ARM_ALU_SB_G1
:
24095 case BFD_RELOC_ARM_ALU_SB_G2
:
24096 gas_assert (!fixP
->fx_done
);
24097 if (!seg
->use_rela_p
)
24100 bfd_vma encoded_addend
;
24101 bfd_vma addend_abs
= abs (value
);
24103 /* Check that the absolute value of the addend can be
24104 expressed as an 8-bit constant plus a rotation. */
24105 encoded_addend
= encode_arm_immediate (addend_abs
);
24106 if (encoded_addend
== (unsigned int) FAIL
)
24107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24108 _("the offset 0x%08lX is not representable"),
24109 (unsigned long) addend_abs
);
24111 /* Extract the instruction. */
24112 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24114 /* If the addend is positive, use an ADD instruction.
24115 Otherwise use a SUB. Take care not to destroy the S bit. */
24116 insn
&= 0xff1fffff;
24122 /* Place the encoded addend into the first 12 bits of the
24124 insn
&= 0xfffff000;
24125 insn
|= encoded_addend
;
24127 /* Update the instruction. */
24128 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24132 case BFD_RELOC_ARM_LDR_PC_G0
:
24133 case BFD_RELOC_ARM_LDR_PC_G1
:
24134 case BFD_RELOC_ARM_LDR_PC_G2
:
24135 case BFD_RELOC_ARM_LDR_SB_G0
:
24136 case BFD_RELOC_ARM_LDR_SB_G1
:
24137 case BFD_RELOC_ARM_LDR_SB_G2
:
24138 gas_assert (!fixP
->fx_done
);
24139 if (!seg
->use_rela_p
)
24142 bfd_vma addend_abs
= abs (value
);
24144 /* Check that the absolute value of the addend can be
24145 encoded in 12 bits. */
24146 if (addend_abs
>= 0x1000)
24147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24148 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24149 (unsigned long) addend_abs
);
24151 /* Extract the instruction. */
24152 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24154 /* If the addend is negative, clear bit 23 of the instruction.
24155 Otherwise set it. */
24157 insn
&= ~(1 << 23);
24161 /* Place the absolute value of the addend into the first 12 bits
24162 of the instruction. */
24163 insn
&= 0xfffff000;
24164 insn
|= addend_abs
;
24166 /* Update the instruction. */
24167 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24171 case BFD_RELOC_ARM_LDRS_PC_G0
:
24172 case BFD_RELOC_ARM_LDRS_PC_G1
:
24173 case BFD_RELOC_ARM_LDRS_PC_G2
:
24174 case BFD_RELOC_ARM_LDRS_SB_G0
:
24175 case BFD_RELOC_ARM_LDRS_SB_G1
:
24176 case BFD_RELOC_ARM_LDRS_SB_G2
:
24177 gas_assert (!fixP
->fx_done
);
24178 if (!seg
->use_rela_p
)
24181 bfd_vma addend_abs
= abs (value
);
24183 /* Check that the absolute value of the addend can be
24184 encoded in 8 bits. */
24185 if (addend_abs
>= 0x100)
24186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24187 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24188 (unsigned long) addend_abs
);
24190 /* Extract the instruction. */
24191 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24193 /* If the addend is negative, clear bit 23 of the instruction.
24194 Otherwise set it. */
24196 insn
&= ~(1 << 23);
24200 /* Place the first four bits of the absolute value of the addend
24201 into the first 4 bits of the instruction, and the remaining
24202 four into bits 8 .. 11. */
24203 insn
&= 0xfffff0f0;
24204 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24206 /* Update the instruction. */
24207 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24211 case BFD_RELOC_ARM_LDC_PC_G0
:
24212 case BFD_RELOC_ARM_LDC_PC_G1
:
24213 case BFD_RELOC_ARM_LDC_PC_G2
:
24214 case BFD_RELOC_ARM_LDC_SB_G0
:
24215 case BFD_RELOC_ARM_LDC_SB_G1
:
24216 case BFD_RELOC_ARM_LDC_SB_G2
:
24217 gas_assert (!fixP
->fx_done
);
24218 if (!seg
->use_rela_p
)
24221 bfd_vma addend_abs
= abs (value
);
24223 /* Check that the absolute value of the addend is a multiple of
24224 four and, when divided by four, fits in 8 bits. */
24225 if (addend_abs
& 0x3)
24226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24227 _("bad offset 0x%08lX (must be word-aligned)"),
24228 (unsigned long) addend_abs
);
24230 if ((addend_abs
>> 2) > 0xff)
24231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24232 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24233 (unsigned long) addend_abs
);
24235 /* Extract the instruction. */
24236 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24238 /* If the addend is negative, clear bit 23 of the instruction.
24239 Otherwise set it. */
24241 insn
&= ~(1 << 23);
24245 /* Place the addend (divided by four) into the first eight
24246 bits of the instruction. */
24247 insn
&= 0xfffffff0;
24248 insn
|= addend_abs
>> 2;
24250 /* Update the instruction. */
24251 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24255 case BFD_RELOC_ARM_V4BX
:
24256 /* This will need to go in the object file. */
24260 case BFD_RELOC_UNUSED
:
24262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24263 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24267 /* Translate internal representation of relocation info to BFD target
24271 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24274 bfd_reloc_code_real_type code
;
24276 reloc
= XNEW (arelent
);
24278 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24279 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24280 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24282 if (fixp
->fx_pcrel
)
24284 if (section
->use_rela_p
)
24285 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24287 fixp
->fx_offset
= reloc
->address
;
24289 reloc
->addend
= fixp
->fx_offset
;
24291 switch (fixp
->fx_r_type
)
24294 if (fixp
->fx_pcrel
)
24296 code
= BFD_RELOC_8_PCREL
;
24299 /* Fall through. */
24302 if (fixp
->fx_pcrel
)
24304 code
= BFD_RELOC_16_PCREL
;
24307 /* Fall through. */
24310 if (fixp
->fx_pcrel
)
24312 code
= BFD_RELOC_32_PCREL
;
24315 /* Fall through. */
24317 case BFD_RELOC_ARM_MOVW
:
24318 if (fixp
->fx_pcrel
)
24320 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24323 /* Fall through. */
24325 case BFD_RELOC_ARM_MOVT
:
24326 if (fixp
->fx_pcrel
)
24328 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24331 /* Fall through. */
24333 case BFD_RELOC_ARM_THUMB_MOVW
:
24334 if (fixp
->fx_pcrel
)
24336 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24339 /* Fall through. */
24341 case BFD_RELOC_ARM_THUMB_MOVT
:
24342 if (fixp
->fx_pcrel
)
24344 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24347 /* Fall through. */
24349 case BFD_RELOC_NONE
:
24350 case BFD_RELOC_ARM_PCREL_BRANCH
:
24351 case BFD_RELOC_ARM_PCREL_BLX
:
24352 case BFD_RELOC_RVA
:
24353 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24354 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24355 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24356 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24357 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24358 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24359 case BFD_RELOC_VTABLE_ENTRY
:
24360 case BFD_RELOC_VTABLE_INHERIT
:
24362 case BFD_RELOC_32_SECREL
:
24364 code
= fixp
->fx_r_type
;
24367 case BFD_RELOC_THUMB_PCREL_BLX
:
24369 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24370 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24373 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24376 case BFD_RELOC_ARM_LITERAL
:
24377 case BFD_RELOC_ARM_HWLITERAL
:
24378 /* If this is called then the a literal has
24379 been referenced across a section boundary. */
24380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24381 _("literal referenced across section boundary"));
24385 case BFD_RELOC_ARM_TLS_CALL
:
24386 case BFD_RELOC_ARM_THM_TLS_CALL
:
24387 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24388 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24389 case BFD_RELOC_ARM_GOT32
:
24390 case BFD_RELOC_ARM_GOTOFF
:
24391 case BFD_RELOC_ARM_GOT_PREL
:
24392 case BFD_RELOC_ARM_PLT32
:
24393 case BFD_RELOC_ARM_TARGET1
:
24394 case BFD_RELOC_ARM_ROSEGREL32
:
24395 case BFD_RELOC_ARM_SBREL32
:
24396 case BFD_RELOC_ARM_PREL31
:
24397 case BFD_RELOC_ARM_TARGET2
:
24398 case BFD_RELOC_ARM_TLS_LDO32
:
24399 case BFD_RELOC_ARM_PCREL_CALL
:
24400 case BFD_RELOC_ARM_PCREL_JUMP
:
24401 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24402 case BFD_RELOC_ARM_ALU_PC_G0
:
24403 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24404 case BFD_RELOC_ARM_ALU_PC_G1
:
24405 case BFD_RELOC_ARM_ALU_PC_G2
:
24406 case BFD_RELOC_ARM_LDR_PC_G0
:
24407 case BFD_RELOC_ARM_LDR_PC_G1
:
24408 case BFD_RELOC_ARM_LDR_PC_G2
:
24409 case BFD_RELOC_ARM_LDRS_PC_G0
:
24410 case BFD_RELOC_ARM_LDRS_PC_G1
:
24411 case BFD_RELOC_ARM_LDRS_PC_G2
:
24412 case BFD_RELOC_ARM_LDC_PC_G0
:
24413 case BFD_RELOC_ARM_LDC_PC_G1
:
24414 case BFD_RELOC_ARM_LDC_PC_G2
:
24415 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24416 case BFD_RELOC_ARM_ALU_SB_G0
:
24417 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24418 case BFD_RELOC_ARM_ALU_SB_G1
:
24419 case BFD_RELOC_ARM_ALU_SB_G2
:
24420 case BFD_RELOC_ARM_LDR_SB_G0
:
24421 case BFD_RELOC_ARM_LDR_SB_G1
:
24422 case BFD_RELOC_ARM_LDR_SB_G2
:
24423 case BFD_RELOC_ARM_LDRS_SB_G0
:
24424 case BFD_RELOC_ARM_LDRS_SB_G1
:
24425 case BFD_RELOC_ARM_LDRS_SB_G2
:
24426 case BFD_RELOC_ARM_LDC_SB_G0
:
24427 case BFD_RELOC_ARM_LDC_SB_G1
:
24428 case BFD_RELOC_ARM_LDC_SB_G2
:
24429 case BFD_RELOC_ARM_V4BX
:
24430 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24431 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24432 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24433 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24434 code
= fixp
->fx_r_type
;
24437 case BFD_RELOC_ARM_TLS_GOTDESC
:
24438 case BFD_RELOC_ARM_TLS_GD32
:
24439 case BFD_RELOC_ARM_TLS_LE32
:
24440 case BFD_RELOC_ARM_TLS_IE32
:
24441 case BFD_RELOC_ARM_TLS_LDM32
:
24442 /* BFD will include the symbol's address in the addend.
24443 But we don't want that, so subtract it out again here. */
24444 if (!S_IS_COMMON (fixp
->fx_addsy
))
24445 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24446 code
= fixp
->fx_r_type
;
24450 case BFD_RELOC_ARM_IMMEDIATE
:
24451 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24452 _("internal relocation (type: IMMEDIATE) not fixed up"));
24455 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24457 _("ADRL used for a symbol not defined in the same file"));
24460 case BFD_RELOC_ARM_OFFSET_IMM
:
24461 if (section
->use_rela_p
)
24463 code
= fixp
->fx_r_type
;
24467 if (fixp
->fx_addsy
!= NULL
24468 && !S_IS_DEFINED (fixp
->fx_addsy
)
24469 && S_IS_LOCAL (fixp
->fx_addsy
))
24471 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24472 _("undefined local label `%s'"),
24473 S_GET_NAME (fixp
->fx_addsy
));
24477 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24478 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24485 switch (fixp
->fx_r_type
)
24487 case BFD_RELOC_NONE
: type
= "NONE"; break;
24488 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24489 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24490 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24491 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24492 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24493 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24494 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24495 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24496 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24497 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24498 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24499 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24500 default: type
= _("<unknown>"); break;
24502 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24503 _("cannot represent %s relocation in this object file format"),
24510 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24512 && fixp
->fx_addsy
== GOT_symbol
)
24514 code
= BFD_RELOC_ARM_GOTPC
;
24515 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24519 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24521 if (reloc
->howto
== NULL
)
24523 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24524 _("cannot represent %s relocation in this object file format"),
24525 bfd_get_reloc_code_name (code
));
24529 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24530 vtable entry to be used in the relocation's section offset. */
24531 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24532 reloc
->address
= fixp
->fx_offset
;
24537 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24540 cons_fix_new_arm (fragS
* frag
,
24544 bfd_reloc_code_real_type reloc
)
24549 FIXME: @@ Should look at CPU word size. */
24553 reloc
= BFD_RELOC_8
;
24556 reloc
= BFD_RELOC_16
;
24560 reloc
= BFD_RELOC_32
;
24563 reloc
= BFD_RELOC_64
;
24568 if (exp
->X_op
== O_secrel
)
24570 exp
->X_op
= O_symbol
;
24571 reloc
= BFD_RELOC_32_SECREL
;
24575 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24578 #if defined (OBJ_COFF)
24580 arm_validate_fix (fixS
* fixP
)
24582 /* If the destination of the branch is a defined symbol which does not have
24583 the THUMB_FUNC attribute, then we must be calling a function which has
24584 the (interfacearm) attribute. We look for the Thumb entry point to that
24585 function and change the branch to refer to that function instead. */
24586 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24587 && fixP
->fx_addsy
!= NULL
24588 && S_IS_DEFINED (fixP
->fx_addsy
)
24589 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24591 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24598 arm_force_relocation (struct fix
* fixp
)
24600 #if defined (OBJ_COFF) && defined (TE_PE)
24601 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24605 /* In case we have a call or a branch to a function in ARM ISA mode from
24606 a thumb function or vice-versa force the relocation. These relocations
24607 are cleared off for some cores that might have blx and simple transformations
24611 switch (fixp
->fx_r_type
)
24613 case BFD_RELOC_ARM_PCREL_JUMP
:
24614 case BFD_RELOC_ARM_PCREL_CALL
:
24615 case BFD_RELOC_THUMB_PCREL_BLX
:
24616 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24620 case BFD_RELOC_ARM_PCREL_BLX
:
24621 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24622 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24623 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24624 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24633 /* Resolve these relocations even if the symbol is extern or weak.
24634 Technically this is probably wrong due to symbol preemption.
24635 In practice these relocations do not have enough range to be useful
24636 at dynamic link time, and some code (e.g. in the Linux kernel)
24637 expects these references to be resolved. */
24638 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24639 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24640 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24641 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24642 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24643 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24644 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24645 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24646 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24647 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24648 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24649 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24650 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24651 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24654 /* Always leave these relocations for the linker. */
24655 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24656 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24657 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24660 /* Always generate relocations against function symbols. */
24661 if (fixp
->fx_r_type
== BFD_RELOC_32
24663 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24666 return generic_force_reloc (fixp
);
24669 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24670 /* Relocations against function names must be left unadjusted,
24671 so that the linker can use this information to generate interworking
24672 stubs. The MIPS version of this function
24673 also prevents relocations that are mips-16 specific, but I do not
24674 know why it does this.
24677 There is one other problem that ought to be addressed here, but
24678 which currently is not: Taking the address of a label (rather
24679 than a function) and then later jumping to that address. Such
24680 addresses also ought to have their bottom bit set (assuming that
24681 they reside in Thumb code), but at the moment they will not. */
24684 arm_fix_adjustable (fixS
* fixP
)
24686 if (fixP
->fx_addsy
== NULL
)
24689 /* Preserve relocations against symbols with function type. */
24690 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24693 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24694 && fixP
->fx_subsy
== NULL
)
24697 /* We need the symbol name for the VTABLE entries. */
24698 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24699 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24702 /* Don't allow symbols to be discarded on GOT related relocs. */
24703 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24704 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24705 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24706 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24707 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24708 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24709 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24710 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24711 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24712 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24713 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24714 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24715 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24716 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24719 /* Similarly for group relocations. */
24720 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24721 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24722 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24725 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24726 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24727 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24728 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24729 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24730 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24731 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24732 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24733 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24736 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24737 offsets, so keep these symbols. */
24738 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24739 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24744 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24748 elf32_arm_target_format (void)
24751 return (target_big_endian
24752 ? "elf32-bigarm-symbian"
24753 : "elf32-littlearm-symbian");
24754 #elif defined (TE_VXWORKS)
24755 return (target_big_endian
24756 ? "elf32-bigarm-vxworks"
24757 : "elf32-littlearm-vxworks");
24758 #elif defined (TE_NACL)
24759 return (target_big_endian
24760 ? "elf32-bigarm-nacl"
24761 : "elf32-littlearm-nacl");
24763 if (target_big_endian
)
24764 return "elf32-bigarm";
24766 return "elf32-littlearm";
24771 armelf_frob_symbol (symbolS
* symp
,
24774 elf_frob_symbol (symp
, puntp
);
24778 /* MD interface: Finalization. */
24783 literal_pool
* pool
;
24785 /* Ensure that all the IT blocks are properly closed. */
24786 check_it_blocks_finished ();
24788 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24790 /* Put it at the end of the relevant section. */
24791 subseg_set (pool
->section
, pool
->sub_section
);
24793 arm_elf_change_section ();
24800 /* Remove any excess mapping symbols generated for alignment frags in
24801 SEC. We may have created a mapping symbol before a zero byte
24802 alignment; remove it if there's a mapping symbol after the
24805 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24806 void *dummy ATTRIBUTE_UNUSED
)
24808 segment_info_type
*seginfo
= seg_info (sec
);
24811 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24814 for (fragp
= seginfo
->frchainP
->frch_root
;
24816 fragp
= fragp
->fr_next
)
24818 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24819 fragS
*next
= fragp
->fr_next
;
24821 /* Variable-sized frags have been converted to fixed size by
24822 this point. But if this was variable-sized to start with,
24823 there will be a fixed-size frag after it. So don't handle
24825 if (sym
== NULL
|| next
== NULL
)
24828 if (S_GET_VALUE (sym
) < next
->fr_address
)
24829 /* Not at the end of this frag. */
24831 know (S_GET_VALUE (sym
) == next
->fr_address
);
24835 if (next
->tc_frag_data
.first_map
!= NULL
)
24837 /* Next frag starts with a mapping symbol. Discard this
24839 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24843 if (next
->fr_next
== NULL
)
24845 /* This mapping symbol is at the end of the section. Discard
24847 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24848 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24852 /* As long as we have empty frags without any mapping symbols,
24854 /* If the next frag is non-empty and does not start with a
24855 mapping symbol, then this mapping symbol is required. */
24856 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24859 next
= next
->fr_next
;
24861 while (next
!= NULL
);
24866 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24870 arm_adjust_symtab (void)
24875 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24877 if (ARM_IS_THUMB (sym
))
24879 if (THUMB_IS_FUNC (sym
))
24881 /* Mark the symbol as a Thumb function. */
24882 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24883 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24884 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24886 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24887 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24889 as_bad (_("%s: unexpected function type: %d"),
24890 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24892 else switch (S_GET_STORAGE_CLASS (sym
))
24895 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24898 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24901 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24909 if (ARM_IS_INTERWORK (sym
))
24910 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24917 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24919 if (ARM_IS_THUMB (sym
))
24921 elf_symbol_type
* elf_sym
;
24923 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24924 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24926 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24927 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24929 /* If it's a .thumb_func, declare it as so,
24930 otherwise tag label as .code 16. */
24931 if (THUMB_IS_FUNC (sym
))
24932 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24933 ST_BRANCH_TO_THUMB
);
24934 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24935 elf_sym
->internal_elf_sym
.st_info
=
24936 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24941 /* Remove any overlapping mapping symbols generated by alignment frags. */
24942 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24943 /* Now do generic ELF adjustments. */
24944 elf_adjust_symtab ();
24948 /* MD interface: Initialization. */
24951 set_constant_flonums (void)
24955 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24956 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24960 /* Auto-select Thumb mode if it's the only available instruction set for the
24961 given architecture. */
24964 autoselect_thumb_from_cpu_variant (void)
24966 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24967 opcode_select (16);
24976 if ( (arm_ops_hsh
= hash_new ()) == NULL
24977 || (arm_cond_hsh
= hash_new ()) == NULL
24978 || (arm_shift_hsh
= hash_new ()) == NULL
24979 || (arm_psr_hsh
= hash_new ()) == NULL
24980 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24981 || (arm_reg_hsh
= hash_new ()) == NULL
24982 || (arm_reloc_hsh
= hash_new ()) == NULL
24983 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24984 as_fatal (_("virtual memory exhausted"));
24986 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24987 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24988 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24989 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24990 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24991 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24992 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24993 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24994 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24995 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24996 (void *) (v7m_psrs
+ i
));
24997 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24998 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25000 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25002 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25003 (void *) (barrier_opt_names
+ i
));
25005 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25007 struct reloc_entry
* entry
= reloc_names
+ i
;
25009 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25010 /* This makes encode_branch() use the EABI versions of this relocation. */
25011 entry
->reloc
= BFD_RELOC_UNUSED
;
25013 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25017 set_constant_flonums ();
25019 /* Set the cpu variant based on the command-line options. We prefer
25020 -mcpu= over -march= if both are set (as for GCC); and we prefer
25021 -mfpu= over any other way of setting the floating point unit.
25022 Use of legacy options with new options are faulted. */
25025 if (mcpu_cpu_opt
|| march_cpu_opt
)
25026 as_bad (_("use of old and new-style options to set CPU type"));
25028 mcpu_cpu_opt
= legacy_cpu
;
25030 else if (!mcpu_cpu_opt
)
25032 mcpu_cpu_opt
= march_cpu_opt
;
25033 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25034 /* Avoid double free in arm_md_end. */
25035 dyn_march_ext_opt
= NULL
;
25041 as_bad (_("use of old and new-style options to set FPU type"));
25043 mfpu_opt
= legacy_fpu
;
25045 else if (!mfpu_opt
)
25047 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25048 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25049 /* Some environments specify a default FPU. If they don't, infer it
25050 from the processor. */
25052 mfpu_opt
= mcpu_fpu_opt
;
25054 mfpu_opt
= march_fpu_opt
;
25056 mfpu_opt
= &fpu_default
;
25062 if (mcpu_cpu_opt
!= NULL
)
25063 mfpu_opt
= &fpu_default
;
25064 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25065 mfpu_opt
= &fpu_arch_vfp_v2
;
25067 mfpu_opt
= &fpu_arch_fpa
;
25073 mcpu_cpu_opt
= &cpu_default
;
25074 selected_cpu
= cpu_default
;
25076 else if (dyn_mcpu_ext_opt
)
25077 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25079 selected_cpu
= *mcpu_cpu_opt
;
25081 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25082 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25083 else if (mcpu_cpu_opt
)
25084 selected_cpu
= *mcpu_cpu_opt
;
25086 mcpu_cpu_opt
= &arm_arch_any
;
25089 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25090 if (dyn_mcpu_ext_opt
)
25091 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25093 autoselect_thumb_from_cpu_variant ();
25095 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25097 #if defined OBJ_COFF || defined OBJ_ELF
25099 unsigned int flags
= 0;
25101 #if defined OBJ_ELF
25102 flags
= meabi_flags
;
25104 switch (meabi_flags
)
25106 case EF_ARM_EABI_UNKNOWN
:
25108 /* Set the flags in the private structure. */
25109 if (uses_apcs_26
) flags
|= F_APCS26
;
25110 if (support_interwork
) flags
|= F_INTERWORK
;
25111 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25112 if (pic_code
) flags
|= F_PIC
;
25113 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25114 flags
|= F_SOFT_FLOAT
;
25116 switch (mfloat_abi_opt
)
25118 case ARM_FLOAT_ABI_SOFT
:
25119 case ARM_FLOAT_ABI_SOFTFP
:
25120 flags
|= F_SOFT_FLOAT
;
25123 case ARM_FLOAT_ABI_HARD
:
25124 if (flags
& F_SOFT_FLOAT
)
25125 as_bad (_("hard-float conflicts with specified fpu"));
25129 /* Using pure-endian doubles (even if soft-float). */
25130 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25131 flags
|= F_VFP_FLOAT
;
25133 #if defined OBJ_ELF
25134 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25135 flags
|= EF_ARM_MAVERICK_FLOAT
;
25138 case EF_ARM_EABI_VER4
:
25139 case EF_ARM_EABI_VER5
:
25140 /* No additional flags to set. */
25147 bfd_set_private_flags (stdoutput
, flags
);
25149 /* We have run out flags in the COFF header to encode the
25150 status of ATPCS support, so instead we create a dummy,
25151 empty, debug section called .arm.atpcs. */
25156 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25160 bfd_set_section_flags
25161 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25162 bfd_set_section_size (stdoutput
, sec
, 0);
25163 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25169 /* Record the CPU type as well. */
25170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25171 mach
= bfd_mach_arm_iWMMXt2
;
25172 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25173 mach
= bfd_mach_arm_iWMMXt
;
25174 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25175 mach
= bfd_mach_arm_XScale
;
25176 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25177 mach
= bfd_mach_arm_ep9312
;
25178 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25179 mach
= bfd_mach_arm_5TE
;
25180 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25182 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25183 mach
= bfd_mach_arm_5T
;
25185 mach
= bfd_mach_arm_5
;
25187 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25189 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25190 mach
= bfd_mach_arm_4T
;
25192 mach
= bfd_mach_arm_4
;
25194 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25195 mach
= bfd_mach_arm_3M
;
25196 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25197 mach
= bfd_mach_arm_3
;
25198 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25199 mach
= bfd_mach_arm_2a
;
25200 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25201 mach
= bfd_mach_arm_2
;
25203 mach
= bfd_mach_arm_unknown
;
25205 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25208 /* Command line processing. */
25211 Invocation line includes a switch not recognized by the base assembler.
25212 See if it's a processor-specific option.
25214 This routine is somewhat complicated by the need for backwards
25215 compatibility (since older releases of gcc can't be changed).
25216 The new options try to make the interface as compatible as
25219 New options (supported) are:
25221 -mcpu=<cpu name> Assemble for selected processor
25222 -march=<architecture name> Assemble for selected architecture
25223 -mfpu=<fpu architecture> Assemble for selected FPU.
25224 -EB/-mbig-endian Big-endian
25225 -EL/-mlittle-endian Little-endian
25226 -k Generate PIC code
25227 -mthumb Start in Thumb mode
25228 -mthumb-interwork Code supports ARM/Thumb interworking
25230 -m[no-]warn-deprecated Warn about deprecated features
25231 -m[no-]warn-syms Warn when symbols match instructions
25233 For now we will also provide support for:
25235 -mapcs-32 32-bit Program counter
25236 -mapcs-26 26-bit Program counter
25237 -macps-float Floats passed in FP registers
25238 -mapcs-reentrant Reentrant code
25240 (sometime these will probably be replaced with -mapcs=<list of options>
25241 and -matpcs=<list of options>)
25243 The remaining options are only supported for back-wards compatibility.
25244 Cpu variants, the arm part is optional:
25245 -m[arm]1 Currently not supported.
25246 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25247 -m[arm]3 Arm 3 processor
25248 -m[arm]6[xx], Arm 6 processors
25249 -m[arm]7[xx][t][[d]m] Arm 7 processors
25250 -m[arm]8[10] Arm 8 processors
25251 -m[arm]9[20][tdmi] Arm 9 processors
25252 -mstrongarm[110[0]] StrongARM processors
25253 -mxscale XScale processors
25254 -m[arm]v[2345[t[e]]] Arm architectures
25255 -mall All (except the ARM1)
25257 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25258 -mfpe-old (No float load/store multiples)
25259 -mvfpxd VFP Single precision
25261 -mno-fpu Disable all floating point instructions
25263 The following CPU names are recognized:
25264 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25265 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25266 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25267 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25268 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25269 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25270 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25274 const char * md_shortopts
= "m:k";
25276 #ifdef ARM_BI_ENDIAN
25277 #define OPTION_EB (OPTION_MD_BASE + 0)
25278 #define OPTION_EL (OPTION_MD_BASE + 1)
25280 #if TARGET_BYTES_BIG_ENDIAN
25281 #define OPTION_EB (OPTION_MD_BASE + 0)
25283 #define OPTION_EL (OPTION_MD_BASE + 1)
25286 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25288 struct option md_longopts
[] =
25291 {"EB", no_argument
, NULL
, OPTION_EB
},
25294 {"EL", no_argument
, NULL
, OPTION_EL
},
25296 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25297 {NULL
, no_argument
, NULL
, 0}
25301 size_t md_longopts_size
= sizeof (md_longopts
);
25303 struct arm_option_table
25305 const char *option
; /* Option name to match. */
25306 const char *help
; /* Help information. */
25307 int *var
; /* Variable to change. */
25308 int value
; /* What to change it to. */
25309 const char *deprecated
; /* If non-null, print this message. */
25312 struct arm_option_table arm_opts
[] =
25314 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25315 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25316 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25317 &support_interwork
, 1, NULL
},
25318 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25319 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25320 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25322 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25323 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25324 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25325 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25328 /* These are recognized by the assembler, but have no affect on code. */
25329 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25330 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25332 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25333 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25334 &warn_on_deprecated
, 0, NULL
},
25335 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25336 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25337 {NULL
, NULL
, NULL
, 0, NULL
}
25340 struct arm_legacy_option_table
25342 const char *option
; /* Option name to match. */
25343 const arm_feature_set
**var
; /* Variable to change. */
25344 const arm_feature_set value
; /* What to change it to. */
25345 const char *deprecated
; /* If non-null, print this message. */
25348 const struct arm_legacy_option_table arm_legacy_opts
[] =
25350 /* DON'T add any new processors to this list -- we want the whole list
25351 to go away... Add them to the processors table instead. */
25352 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25353 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25354 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25355 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25356 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25357 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25358 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25359 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25360 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25361 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25362 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25363 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25364 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25365 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25366 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25367 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25368 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25369 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25370 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25371 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25372 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25373 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25374 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25375 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25376 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25377 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25378 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25379 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25380 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25381 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25382 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25383 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25384 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25385 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25386 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25387 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25388 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25389 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25390 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25391 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25392 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25393 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25394 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25395 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25396 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25397 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25398 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25399 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25400 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25401 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25402 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25403 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25404 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25405 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25406 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25407 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25408 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25409 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25410 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25411 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25412 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25413 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25414 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25415 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25416 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25417 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25418 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25419 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25420 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25421 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25422 N_("use -mcpu=strongarm110")},
25423 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25424 N_("use -mcpu=strongarm1100")},
25425 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25426 N_("use -mcpu=strongarm1110")},
25427 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25428 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25429 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25431 /* Architecture variants -- don't add any more to this list either. */
25432 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25433 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25434 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25435 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25436 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25437 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25438 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25439 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25440 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25441 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25442 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25443 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25444 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25445 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25446 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25447 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25448 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25449 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25451 /* Floating point variants -- don't add any more to this list either. */
25452 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25453 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25454 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25455 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25456 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25458 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25461 struct arm_cpu_option_table
25465 const arm_feature_set value
;
25466 const arm_feature_set ext
;
25467 /* For some CPUs we assume an FPU unless the user explicitly sets
25469 const arm_feature_set default_fpu
;
25470 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25472 const char *canonical_name
;
25475 /* This list should, at a minimum, contain all the cpu names
25476 recognized by GCC. */
25477 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25478 static const struct arm_cpu_option_table arm_cpus
[] =
25480 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25483 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25486 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25489 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25492 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25495 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25498 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25501 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25504 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25507 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25510 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25513 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25516 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25519 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25522 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25525 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25528 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25531 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25534 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25537 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25540 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25543 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25546 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25549 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25552 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25555 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25558 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25561 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25564 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25567 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25570 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25573 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25576 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25579 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25582 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25585 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25588 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25591 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25594 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25597 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25600 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25603 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25606 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25609 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25612 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25615 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25619 /* For V5 or later processors we default to using VFP; but the user
25620 should really set the FPU type explicitly. */
25621 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25624 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25627 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25630 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25633 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25636 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25639 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25642 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25645 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25648 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25651 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25654 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25657 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25660 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25663 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25666 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25669 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25672 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25675 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25678 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25681 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25684 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25687 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25690 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25693 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25696 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25699 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25702 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25705 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25708 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25711 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25714 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25717 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25720 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25723 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
25726 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
25729 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
25730 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25732 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
25734 FPU_ARCH_NEON_VFP_V4
),
25735 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
25736 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25737 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25738 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
25739 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25740 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25741 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
25743 FPU_ARCH_NEON_VFP_V4
),
25744 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
25746 FPU_ARCH_NEON_VFP_V4
),
25747 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
25749 FPU_ARCH_NEON_VFP_V4
),
25750 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
25751 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25752 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25753 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
25754 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25755 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25756 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
25757 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25758 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25759 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
25760 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25761 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25762 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
25763 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25764 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25765 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
25766 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25767 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25768 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
25771 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
25773 FPU_ARCH_VFP_V3D16
),
25774 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
25775 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25777 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
25778 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25779 FPU_ARCH_VFP_V3D16
),
25780 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
25781 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25782 FPU_ARCH_VFP_V3D16
),
25783 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
25784 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25786 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
25789 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
25792 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
25795 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
25798 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
25801 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
25804 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
25807 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
25808 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25809 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25811 /* ??? XSCALE is really an architecture. */
25812 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
25816 /* ??? iwmmxt is not a processor. */
25817 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
25820 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
25823 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
25828 ARM_CPU_OPT ("ep9312", "ARM920T",
25829 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25830 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
25832 /* Marvell processors. */
25833 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
25834 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25835 FPU_ARCH_VFP_V3D16
),
25836 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
25837 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25838 FPU_ARCH_NEON_VFP_V4
),
25840 /* APM X-Gene family. */
25841 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
25843 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25844 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
25845 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25846 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25848 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25852 struct arm_arch_option_table
25856 const arm_feature_set value
;
25857 const arm_feature_set default_fpu
;
25860 /* This list should, at a minimum, contain all the architecture names
25861 recognized by GCC. */
25862 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25863 static const struct arm_arch_option_table arm_archs
[] =
25865 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25866 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25867 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25868 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25869 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25870 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25871 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25872 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25873 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25874 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25875 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25876 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25877 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25878 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25879 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25880 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25881 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25882 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25883 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25884 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25885 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25886 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25887 kept to preserve existing behaviour. */
25888 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25889 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25890 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25891 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25892 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25893 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25894 kept to preserve existing behaviour. */
25895 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25896 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25897 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25898 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25899 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25900 /* The official spelling of the ARMv7 profile variants is the dashed form.
25901 Accept the non-dashed form for compatibility with old toolchains. */
25902 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25903 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25904 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25905 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25906 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25907 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25908 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25909 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25910 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25911 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25912 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25913 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25914 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25915 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25916 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
25917 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25918 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25919 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25920 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25922 #undef ARM_ARCH_OPT
25924 /* ISA extensions in the co-processor and main instruction set space. */
25925 struct arm_option_extension_value_table
25929 const arm_feature_set merge_value
;
25930 const arm_feature_set clear_value
;
25931 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25932 indicates that an extension is available for all architectures while
25933 ARM_ANY marks an empty entry. */
25934 const arm_feature_set allowed_archs
[2];
25937 /* The following table must be in alphabetical order with a NULL last entry.
25939 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25940 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25941 static const struct arm_option_extension_value_table arm_extensions
[] =
25943 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25944 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25945 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25946 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25947 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25948 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25949 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25950 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25951 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25952 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25953 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25954 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25956 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25957 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25958 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25959 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25960 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
25961 Thumb divide instruction. Due to this having the same name as the
25962 previous entry, this will be ignored when doing command-line parsing and
25963 only considered by build attribute selection code. */
25964 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
25965 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
25966 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
25967 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25968 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25969 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25970 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25971 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25972 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25973 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25974 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25975 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25976 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25977 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25978 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25979 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25980 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25981 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25982 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25983 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25984 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25985 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25986 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25987 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25988 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
25989 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25990 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25991 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25992 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25993 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25994 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25995 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25996 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25998 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25999 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26000 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26001 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26002 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26006 /* ISA floating-point and Advanced SIMD extensions. */
26007 struct arm_option_fpu_value_table
26010 const arm_feature_set value
;
26013 /* This list should, at a minimum, contain all the fpu names
26014 recognized by GCC. */
26015 static const struct arm_option_fpu_value_table arm_fpus
[] =
26017 {"softfpa", FPU_NONE
},
26018 {"fpe", FPU_ARCH_FPE
},
26019 {"fpe2", FPU_ARCH_FPE
},
26020 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26021 {"fpa", FPU_ARCH_FPA
},
26022 {"fpa10", FPU_ARCH_FPA
},
26023 {"fpa11", FPU_ARCH_FPA
},
26024 {"arm7500fe", FPU_ARCH_FPA
},
26025 {"softvfp", FPU_ARCH_VFP
},
26026 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26027 {"vfp", FPU_ARCH_VFP_V2
},
26028 {"vfp9", FPU_ARCH_VFP_V2
},
26029 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26030 {"vfp10", FPU_ARCH_VFP_V2
},
26031 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26032 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26033 {"vfpv2", FPU_ARCH_VFP_V2
},
26034 {"vfpv3", FPU_ARCH_VFP_V3
},
26035 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26036 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26037 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26038 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26039 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26040 {"arm1020t", FPU_ARCH_VFP_V1
},
26041 {"arm1020e", FPU_ARCH_VFP_V2
},
26042 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26043 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26044 {"maverick", FPU_ARCH_MAVERICK
},
26045 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26046 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26047 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26048 {"vfpv4", FPU_ARCH_VFP_V4
},
26049 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26050 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26051 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26052 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26053 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26054 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26055 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26056 {"crypto-neon-fp-armv8",
26057 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26058 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26059 {"crypto-neon-fp-armv8.1",
26060 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26061 {NULL
, ARM_ARCH_NONE
}
26064 struct arm_option_value_table
26070 static const struct arm_option_value_table arm_float_abis
[] =
26072 {"hard", ARM_FLOAT_ABI_HARD
},
26073 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26074 {"soft", ARM_FLOAT_ABI_SOFT
},
26079 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26080 static const struct arm_option_value_table arm_eabis
[] =
26082 {"gnu", EF_ARM_EABI_UNKNOWN
},
26083 {"4", EF_ARM_EABI_VER4
},
26084 {"5", EF_ARM_EABI_VER5
},
26089 struct arm_long_option_table
26091 const char * option
; /* Substring to match. */
26092 const char * help
; /* Help information. */
26093 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26094 const char * deprecated
; /* If non-null, print this message. */
26098 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26099 arm_feature_set
**ext_set_p
)
26101 /* We insist on extensions being specified in alphabetical order, and with
26102 extensions being added before being removed. We achieve this by having
26103 the global ARM_EXTENSIONS table in alphabetical order, and using the
26104 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26105 or removing it (0) and only allowing it to change in the order
26107 const struct arm_option_extension_value_table
* opt
= NULL
;
26108 const arm_feature_set arm_any
= ARM_ANY
;
26109 int adding_value
= -1;
26113 *ext_set_p
= XNEW (arm_feature_set
);
26114 **ext_set_p
= arm_arch_none
;
26117 while (str
!= NULL
&& *str
!= 0)
26124 as_bad (_("invalid architectural extension"));
26129 ext
= strchr (str
, '+');
26134 len
= strlen (str
);
26136 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26138 if (adding_value
!= 0)
26141 opt
= arm_extensions
;
26149 if (adding_value
== -1)
26152 opt
= arm_extensions
;
26154 else if (adding_value
!= 1)
26156 as_bad (_("must specify extensions to add before specifying "
26157 "those to remove"));
26164 as_bad (_("missing architectural extension"));
26168 gas_assert (adding_value
!= -1);
26169 gas_assert (opt
!= NULL
);
26171 /* Scan over the options table trying to find an exact match. */
26172 for (; opt
->name
!= NULL
; opt
++)
26173 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26175 int i
, nb_allowed_archs
=
26176 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26177 /* Check we can apply the extension to this architecture. */
26178 for (i
= 0; i
< nb_allowed_archs
; i
++)
26181 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26183 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26186 if (i
== nb_allowed_archs
)
26188 as_bad (_("extension does not apply to the base architecture"));
26192 /* Add or remove the extension. */
26194 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26197 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26199 /* Allowing Thumb division instructions for ARMv7 in autodetection
26200 rely on this break so that duplicate extensions (extensions
26201 with the same name as a previous extension in the list) are not
26202 considered for command-line parsing. */
26206 if (opt
->name
== NULL
)
26208 /* Did we fail to find an extension because it wasn't specified in
26209 alphabetical order, or because it does not exist? */
26211 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26212 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26215 if (opt
->name
== NULL
)
26216 as_bad (_("unknown architectural extension `%s'"), str
);
26218 as_bad (_("architectural extensions must be specified in "
26219 "alphabetical order"));
26225 /* We should skip the extension we've just matched the next time
26237 arm_parse_cpu (const char *str
)
26239 const struct arm_cpu_option_table
*opt
;
26240 const char *ext
= strchr (str
, '+');
26246 len
= strlen (str
);
26250 as_bad (_("missing cpu name `%s'"), str
);
26254 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26255 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26257 mcpu_cpu_opt
= &opt
->value
;
26258 if (!dyn_mcpu_ext_opt
)
26259 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26260 *dyn_mcpu_ext_opt
= opt
->ext
;
26261 mcpu_fpu_opt
= &opt
->default_fpu
;
26262 if (opt
->canonical_name
)
26264 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26265 strcpy (selected_cpu_name
, opt
->canonical_name
);
26271 if (len
>= sizeof selected_cpu_name
)
26272 len
= (sizeof selected_cpu_name
) - 1;
26274 for (i
= 0; i
< len
; i
++)
26275 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26276 selected_cpu_name
[i
] = 0;
26280 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26285 as_bad (_("unknown cpu `%s'"), str
);
26290 arm_parse_arch (const char *str
)
26292 const struct arm_arch_option_table
*opt
;
26293 const char *ext
= strchr (str
, '+');
26299 len
= strlen (str
);
26303 as_bad (_("missing architecture name `%s'"), str
);
26307 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26308 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26310 march_cpu_opt
= &opt
->value
;
26311 march_fpu_opt
= &opt
->default_fpu
;
26312 strcpy (selected_cpu_name
, opt
->name
);
26315 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26320 as_bad (_("unknown architecture `%s'\n"), str
);
26325 arm_parse_fpu (const char * str
)
26327 const struct arm_option_fpu_value_table
* opt
;
26329 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26330 if (streq (opt
->name
, str
))
26332 mfpu_opt
= &opt
->value
;
26336 as_bad (_("unknown floating point format `%s'\n"), str
);
26341 arm_parse_float_abi (const char * str
)
26343 const struct arm_option_value_table
* opt
;
26345 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26346 if (streq (opt
->name
, str
))
26348 mfloat_abi_opt
= opt
->value
;
26352 as_bad (_("unknown floating point abi `%s'\n"), str
);
26358 arm_parse_eabi (const char * str
)
26360 const struct arm_option_value_table
*opt
;
26362 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26363 if (streq (opt
->name
, str
))
26365 meabi_flags
= opt
->value
;
26368 as_bad (_("unknown EABI `%s'\n"), str
);
26374 arm_parse_it_mode (const char * str
)
26376 bfd_boolean ret
= TRUE
;
26378 if (streq ("arm", str
))
26379 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26380 else if (streq ("thumb", str
))
26381 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26382 else if (streq ("always", str
))
26383 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26384 else if (streq ("never", str
))
26385 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26388 as_bad (_("unknown implicit IT mode `%s', should be "\
26389 "arm, thumb, always, or never."), str
);
26397 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26399 codecomposer_syntax
= TRUE
;
26400 arm_comment_chars
[0] = ';';
26401 arm_line_separator_chars
[0] = 0;
26405 struct arm_long_option_table arm_long_opts
[] =
26407 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26408 arm_parse_cpu
, NULL
},
26409 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26410 arm_parse_arch
, NULL
},
26411 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26412 arm_parse_fpu
, NULL
},
26413 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26414 arm_parse_float_abi
, NULL
},
26416 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26417 arm_parse_eabi
, NULL
},
26419 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26420 arm_parse_it_mode
, NULL
},
26421 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26422 arm_ccs_mode
, NULL
},
26423 {NULL
, NULL
, 0, NULL
}
26427 md_parse_option (int c
, const char * arg
)
26429 struct arm_option_table
*opt
;
26430 const struct arm_legacy_option_table
*fopt
;
26431 struct arm_long_option_table
*lopt
;
26437 target_big_endian
= 1;
26443 target_big_endian
= 0;
26447 case OPTION_FIX_V4BX
:
26452 /* Listing option. Just ignore these, we don't support additional
26457 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26459 if (c
== opt
->option
[0]
26460 && ((arg
== NULL
&& opt
->option
[1] == 0)
26461 || streq (arg
, opt
->option
+ 1)))
26463 /* If the option is deprecated, tell the user. */
26464 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26465 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26466 arg
? arg
: "", _(opt
->deprecated
));
26468 if (opt
->var
!= NULL
)
26469 *opt
->var
= opt
->value
;
26475 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26477 if (c
== fopt
->option
[0]
26478 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26479 || streq (arg
, fopt
->option
+ 1)))
26481 /* If the option is deprecated, tell the user. */
26482 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26483 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26484 arg
? arg
: "", _(fopt
->deprecated
));
26486 if (fopt
->var
!= NULL
)
26487 *fopt
->var
= &fopt
->value
;
26493 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26495 /* These options are expected to have an argument. */
26496 if (c
== lopt
->option
[0]
26498 && strncmp (arg
, lopt
->option
+ 1,
26499 strlen (lopt
->option
+ 1)) == 0)
26501 /* If the option is deprecated, tell the user. */
26502 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26503 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26504 _(lopt
->deprecated
));
26506 /* Call the sup-option parser. */
26507 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26518 md_show_usage (FILE * fp
)
26520 struct arm_option_table
*opt
;
26521 struct arm_long_option_table
*lopt
;
26523 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26525 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26526 if (opt
->help
!= NULL
)
26527 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26529 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26530 if (lopt
->help
!= NULL
)
26531 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26535 -EB assemble code for a big-endian cpu\n"));
26540 -EL assemble code for a little-endian cpu\n"));
26544 --fix-v4bx Allow BX in ARMv4 code\n"));
26552 arm_feature_set flags
;
26553 } cpu_arch_ver_table
;
26555 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26556 chronologically for architectures, with an exception for ARMv6-M and
26557 ARMv6S-M due to legacy reasons. No new architecture should have a
26558 special case. This allows for build attribute selection results to be
26559 stable when new architectures are added. */
26560 static const cpu_arch_ver_table cpu_arch_ver
[] =
26567 {1, ARM_ARCH_V4xM
},
26569 {2, ARM_ARCH_V4TxM
},
26571 {3, ARM_ARCH_V5xM
},
26573 {3, ARM_ARCH_V5TxM
},
26575 {4, ARM_ARCH_V5TExP
},
26576 {4, ARM_ARCH_V5TE
},
26577 {5, ARM_ARCH_V5TEJ
},
26580 {7, ARM_ARCH_V6KZ
},
26582 {8, ARM_ARCH_V6T2
},
26583 {8, ARM_ARCH_V6KT2
},
26584 {8, ARM_ARCH_V6ZT2
},
26585 {8, ARM_ARCH_V6KZT2
},
26587 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26588 always selected build attributes to match those of ARMv6-M
26589 (resp. ARMv6S-M). However, due to these architectures being a strict
26590 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26591 would be selected when fully respecting chronology of architectures.
26592 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26593 move them before ARMv7 architectures. */
26594 {11, ARM_ARCH_V6M
},
26595 {12, ARM_ARCH_V6SM
},
26598 {10, ARM_ARCH_V7A
},
26599 {10, ARM_ARCH_V7R
},
26600 {10, ARM_ARCH_V7M
},
26601 {10, ARM_ARCH_V7VE
},
26602 {13, ARM_ARCH_V7EM
},
26603 {14, ARM_ARCH_V8A
},
26604 {14, ARM_ARCH_V8_1A
},
26605 {14, ARM_ARCH_V8_2A
},
26606 {14, ARM_ARCH_V8_3A
},
26607 {16, ARM_ARCH_V8M_BASE
},
26608 {17, ARM_ARCH_V8M_MAIN
},
26609 {15, ARM_ARCH_V8R
},
26610 {-1, ARM_ARCH_NONE
}
26613 /* Set an attribute if it has not already been set by the user. */
26615 aeabi_set_attribute_int (int tag
, int value
)
26618 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26619 || !attributes_set_explicitly
[tag
])
26620 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26624 aeabi_set_attribute_string (int tag
, const char *value
)
26627 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26628 || !attributes_set_explicitly
[tag
])
26629 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26632 /* Return whether features in the *NEEDED feature set are available via
26633 extensions for the architecture whose feature set is *ARCH_FSET. */
26635 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26636 const arm_feature_set
*needed
)
26638 int i
, nb_allowed_archs
;
26639 arm_feature_set ext_fset
;
26640 const struct arm_option_extension_value_table
*opt
;
26642 ext_fset
= arm_arch_none
;
26643 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26645 /* Extension does not provide any feature we need. */
26646 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26650 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26651 for (i
= 0; i
< nb_allowed_archs
; i
++)
26654 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26657 /* Extension is available, add it. */
26658 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26659 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26663 /* Can we enable all features in *needed? */
26664 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26667 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26668 a given architecture feature set *ARCH_EXT_FSET including extension feature
26669 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26670 - if true, check for an exact match of the architecture modulo extensions;
26671 - otherwise, select build attribute value of the first superset
26672 architecture released so that results remains stable when new architectures
26674 For -march/-mcpu=all the build attribute value of the most featureful
26675 architecture is returned. Tag_CPU_arch_profile result is returned in
26678 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26679 const arm_feature_set
*ext_fset
,
26680 char *profile
, int exact_match
)
26682 arm_feature_set arch_fset
;
26683 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26685 /* Select most featureful architecture with all its extensions if building
26686 for -march=all as the feature sets used to set build attributes. */
26687 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26689 /* Force revisiting of decision for each new architecture. */
26690 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26692 return TAG_CPU_ARCH_V8
;
26695 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
26697 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
26699 arm_feature_set known_arch_fset
;
26701 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
26704 /* Base architecture match user-specified architecture and
26705 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
26706 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
26711 /* Base architecture match user-specified architecture only
26712 (eg. ARMv6-M in the same case as above). Record it in case we
26713 find a match with above condition. */
26714 else if (p_ver_ret
== NULL
26715 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
26721 /* Architecture has all features wanted. */
26722 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
26724 arm_feature_set added_fset
;
26726 /* Compute features added by this architecture over the one
26727 recorded in p_ver_ret. */
26728 if (p_ver_ret
!= NULL
)
26729 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
26731 /* First architecture that match incl. with extensions, or the
26732 only difference in features over the recorded match is
26733 features that were optional and are now mandatory. */
26734 if (p_ver_ret
== NULL
26735 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
26741 else if (p_ver_ret
== NULL
)
26743 arm_feature_set needed_ext_fset
;
26745 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
26747 /* Architecture has all features needed when using some
26748 extensions. Record it and continue searching in case there
26749 exist an architecture providing all needed features without
26750 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
26752 if (have_ext_for_needed_feat_p (&known_arch_fset
,
26759 if (p_ver_ret
== NULL
)
26763 /* Tag_CPU_arch_profile. */
26764 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
26765 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
26766 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
26767 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
26769 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
26771 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
26775 return p_ver_ret
->val
;
26778 /* Set the public EABI object attributes. */
26780 aeabi_set_public_attributes (void)
26785 int fp16_optional
= 0;
26786 int skip_exact_match
= 0;
26787 arm_feature_set flags
, flags_arch
, flags_ext
;
26789 /* Autodetection mode, choose the architecture based the instructions
26791 if (no_cpu_selected ())
26793 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26795 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26796 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26798 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26799 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26801 /* Code run during relaxation relies on selected_cpu being set. */
26802 selected_cpu
= flags
;
26804 /* Otherwise, choose the architecture based on the capabilities of the
26807 flags
= selected_cpu
;
26808 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26810 /* Allow the user to override the reported architecture. */
26813 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
26814 flags_ext
= arm_arch_none
;
26818 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26819 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
26820 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
26823 /* When this function is run again after relaxation has happened there is no
26824 way to determine whether an architecture or CPU was specified by the user:
26825 - selected_cpu is set above for relaxation to work;
26826 - march_cpu_opt is not set if only -mcpu or .cpu is used;
26827 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
26828 Therefore, if not in -march=all case we first try an exact match and fall
26829 back to autodetection. */
26830 if (!skip_exact_match
)
26831 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
26833 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
26835 as_bad (_("no architecture contains all the instructions used\n"));
26837 /* Tag_CPU_name. */
26838 if (selected_cpu_name
[0])
26842 q
= selected_cpu_name
;
26843 if (strncmp (q
, "armv", 4) == 0)
26848 for (i
= 0; q
[i
]; i
++)
26849 q
[i
] = TOUPPER (q
[i
]);
26851 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26854 /* Tag_CPU_arch. */
26855 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26857 /* Tag_CPU_arch_profile. */
26858 if (profile
!= '\0')
26859 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26861 /* Tag_DSP_extension. */
26862 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
26863 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26865 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26866 /* Tag_ARM_ISA_use. */
26867 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26868 || ARM_FEATURE_ZERO (flags_arch
))
26869 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26871 /* Tag_THUMB_ISA_use. */
26872 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26873 || ARM_FEATURE_ZERO (flags_arch
))
26877 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26878 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26880 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26884 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26887 /* Tag_VFP_arch. */
26888 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26889 aeabi_set_attribute_int (Tag_VFP_arch
,
26890 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26892 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26893 aeabi_set_attribute_int (Tag_VFP_arch
,
26894 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26896 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26899 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26901 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26903 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26906 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26907 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26908 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26909 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26910 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26912 /* Tag_ABI_HardFP_use. */
26913 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26914 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26915 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26917 /* Tag_WMMX_arch. */
26918 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26919 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26920 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26921 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26923 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26924 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26925 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26926 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26927 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26928 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26930 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26932 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26936 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26941 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26942 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26943 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26947 We set Tag_DIV_use to two when integer divide instructions have been used
26948 in ARM state, or when Thumb integer divide instructions have been used,
26949 but we have no architecture profile set, nor have we any ARM instructions.
26951 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26952 by the base architecture.
26954 For new architectures we will have to check these tests. */
26955 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
26956 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26957 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26958 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26959 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26960 || (profile
== '\0'
26961 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26962 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26963 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26965 /* Tag_MP_extension_use. */
26966 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26967 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26969 /* Tag Virtualization_use. */
26970 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26972 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26975 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26978 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
26979 finished and free extension feature bits which will not be used anymore. */
26981 arm_md_post_relax (void)
26983 aeabi_set_public_attributes ();
26984 XDELETE (dyn_mcpu_ext_opt
);
26985 dyn_mcpu_ext_opt
= NULL
;
26986 XDELETE (dyn_march_ext_opt
);
26987 dyn_march_ext_opt
= NULL
;
26990 /* Add the default contents for the .ARM.attributes section. */
26994 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26997 aeabi_set_public_attributes ();
26999 #endif /* OBJ_ELF */
27002 /* Parse a .cpu directive. */
27005 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27007 const struct arm_cpu_option_table
*opt
;
27011 name
= input_line_pointer
;
27012 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27013 input_line_pointer
++;
27014 saved_char
= *input_line_pointer
;
27015 *input_line_pointer
= 0;
27017 /* Skip the first "all" entry. */
27018 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27019 if (streq (opt
->name
, name
))
27021 mcpu_cpu_opt
= &opt
->value
;
27022 if (!dyn_mcpu_ext_opt
)
27023 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27024 *dyn_mcpu_ext_opt
= opt
->ext
;
27025 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27026 if (opt
->canonical_name
)
27027 strcpy (selected_cpu_name
, opt
->canonical_name
);
27031 for (i
= 0; opt
->name
[i
]; i
++)
27032 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27034 selected_cpu_name
[i
] = 0;
27036 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27037 if (dyn_mcpu_ext_opt
)
27038 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27039 *input_line_pointer
= saved_char
;
27040 demand_empty_rest_of_line ();
27043 as_bad (_("unknown cpu `%s'"), name
);
27044 *input_line_pointer
= saved_char
;
27045 ignore_rest_of_line ();
27049 /* Parse a .arch directive. */
27052 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27054 const struct arm_arch_option_table
*opt
;
27058 name
= input_line_pointer
;
27059 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27060 input_line_pointer
++;
27061 saved_char
= *input_line_pointer
;
27062 *input_line_pointer
= 0;
27064 /* Skip the first "all" entry. */
27065 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27066 if (streq (opt
->name
, name
))
27068 mcpu_cpu_opt
= &opt
->value
;
27069 XDELETE (dyn_mcpu_ext_opt
);
27070 dyn_mcpu_ext_opt
= NULL
;
27071 selected_cpu
= *mcpu_cpu_opt
;
27072 strcpy (selected_cpu_name
, opt
->name
);
27073 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27074 *input_line_pointer
= saved_char
;
27075 demand_empty_rest_of_line ();
27079 as_bad (_("unknown architecture `%s'\n"), name
);
27080 *input_line_pointer
= saved_char
;
27081 ignore_rest_of_line ();
27085 /* Parse a .object_arch directive. */
27088 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27090 const struct arm_arch_option_table
*opt
;
27094 name
= input_line_pointer
;
27095 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27096 input_line_pointer
++;
27097 saved_char
= *input_line_pointer
;
27098 *input_line_pointer
= 0;
27100 /* Skip the first "all" entry. */
27101 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27102 if (streq (opt
->name
, name
))
27104 object_arch
= &opt
->value
;
27105 *input_line_pointer
= saved_char
;
27106 demand_empty_rest_of_line ();
27110 as_bad (_("unknown architecture `%s'\n"), name
);
27111 *input_line_pointer
= saved_char
;
27112 ignore_rest_of_line ();
27115 /* Parse a .arch_extension directive. */
27118 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27120 const struct arm_option_extension_value_table
*opt
;
27121 const arm_feature_set arm_any
= ARM_ANY
;
27124 int adding_value
= 1;
27126 name
= input_line_pointer
;
27127 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27128 input_line_pointer
++;
27129 saved_char
= *input_line_pointer
;
27130 *input_line_pointer
= 0;
27132 if (strlen (name
) >= 2
27133 && strncmp (name
, "no", 2) == 0)
27139 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27140 if (streq (opt
->name
, name
))
27142 int i
, nb_allowed_archs
=
27143 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27144 for (i
= 0; i
< nb_allowed_archs
; i
++)
27147 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27149 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27153 if (i
== nb_allowed_archs
)
27155 as_bad (_("architectural extension `%s' is not allowed for the "
27156 "current base architecture"), name
);
27160 if (!dyn_mcpu_ext_opt
)
27162 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27163 *dyn_mcpu_ext_opt
= arm_arch_none
;
27166 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27169 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27172 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27173 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27174 *input_line_pointer
= saved_char
;
27175 demand_empty_rest_of_line ();
27176 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27177 on this return so that duplicate extensions (extensions with the
27178 same name as a previous extension in the list) are not considered
27179 for command-line parsing. */
27183 if (opt
->name
== NULL
)
27184 as_bad (_("unknown architecture extension `%s'\n"), name
);
27186 *input_line_pointer
= saved_char
;
27187 ignore_rest_of_line ();
27190 /* Parse a .fpu directive. */
27193 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27195 const struct arm_option_fpu_value_table
*opt
;
27199 name
= input_line_pointer
;
27200 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27201 input_line_pointer
++;
27202 saved_char
= *input_line_pointer
;
27203 *input_line_pointer
= 0;
27205 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27206 if (streq (opt
->name
, name
))
27208 mfpu_opt
= &opt
->value
;
27209 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27210 if (dyn_mcpu_ext_opt
)
27211 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27212 *input_line_pointer
= saved_char
;
27213 demand_empty_rest_of_line ();
27217 as_bad (_("unknown floating point format `%s'\n"), name
);
27218 *input_line_pointer
= saved_char
;
27219 ignore_rest_of_line ();
27222 /* Copy symbol information. */
27225 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27227 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27231 /* Given a symbolic attribute NAME, return the proper integer value.
27232 Returns -1 if the attribute is not known. */
27235 arm_convert_symbolic_attribute (const char *name
)
27237 static const struct
27242 attribute_table
[] =
27244 /* When you modify this table you should
27245 also modify the list in doc/c-arm.texi. */
27246 #define T(tag) {#tag, tag}
27247 T (Tag_CPU_raw_name
),
27250 T (Tag_CPU_arch_profile
),
27251 T (Tag_ARM_ISA_use
),
27252 T (Tag_THUMB_ISA_use
),
27256 T (Tag_Advanced_SIMD_arch
),
27257 T (Tag_PCS_config
),
27258 T (Tag_ABI_PCS_R9_use
),
27259 T (Tag_ABI_PCS_RW_data
),
27260 T (Tag_ABI_PCS_RO_data
),
27261 T (Tag_ABI_PCS_GOT_use
),
27262 T (Tag_ABI_PCS_wchar_t
),
27263 T (Tag_ABI_FP_rounding
),
27264 T (Tag_ABI_FP_denormal
),
27265 T (Tag_ABI_FP_exceptions
),
27266 T (Tag_ABI_FP_user_exceptions
),
27267 T (Tag_ABI_FP_number_model
),
27268 T (Tag_ABI_align_needed
),
27269 T (Tag_ABI_align8_needed
),
27270 T (Tag_ABI_align_preserved
),
27271 T (Tag_ABI_align8_preserved
),
27272 T (Tag_ABI_enum_size
),
27273 T (Tag_ABI_HardFP_use
),
27274 T (Tag_ABI_VFP_args
),
27275 T (Tag_ABI_WMMX_args
),
27276 T (Tag_ABI_optimization_goals
),
27277 T (Tag_ABI_FP_optimization_goals
),
27278 T (Tag_compatibility
),
27279 T (Tag_CPU_unaligned_access
),
27280 T (Tag_FP_HP_extension
),
27281 T (Tag_VFP_HP_extension
),
27282 T (Tag_ABI_FP_16bit_format
),
27283 T (Tag_MPextension_use
),
27285 T (Tag_nodefaults
),
27286 T (Tag_also_compatible_with
),
27287 T (Tag_conformance
),
27289 T (Tag_Virtualization_use
),
27290 T (Tag_DSP_extension
),
27291 /* We deliberately do not include Tag_MPextension_use_legacy. */
27299 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27300 if (streq (name
, attribute_table
[i
].name
))
27301 return attribute_table
[i
].tag
;
27307 /* Apply sym value for relocations only in the case that they are for
27308 local symbols in the same segment as the fixup and you have the
27309 respective architectural feature for blx and simple switches. */
27311 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27314 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27315 /* PR 17444: If the local symbol is in a different section then a reloc
27316 will always be generated for it, so applying the symbol value now
27317 will result in a double offset being stored in the relocation. */
27318 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27319 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27321 switch (fixP
->fx_r_type
)
27323 case BFD_RELOC_ARM_PCREL_BLX
:
27324 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27325 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27329 case BFD_RELOC_ARM_PCREL_CALL
:
27330 case BFD_RELOC_THUMB_PCREL_BLX
:
27331 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27342 #endif /* OBJ_ELF */