1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
306 static const arm_feature_set fpu_vfp_fp16
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
308 static const arm_feature_set fpu_neon_ext_fma
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_fma
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
313 static const arm_feature_set fpu_vfp_ext_armv8
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
315 static const arm_feature_set fpu_vfp_ext_armv8xd
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
317 static const arm_feature_set fpu_neon_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
319 static const arm_feature_set fpu_crypto_ext_armv8
=
320 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
321 static const arm_feature_set crc_ext_armv8
=
322 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
323 static const arm_feature_set fpu_neon_ext_v8_1
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
325 static const arm_feature_set fpu_neon_ext_dotprod
=
326 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
328 static int mfloat_abi_opt
= -1;
329 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
331 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
332 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
334 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
335 /* Feature bits selected by the last -mcpu/-march or by the combination of the
336 last .cpu/.arch directive .arch_extension directives since that
338 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
339 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
340 static arm_feature_set selected_fpu
= FPU_NONE
;
341 /* Feature bits selected by the last .object_arch directive. */
342 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
343 /* Must be long enough to hold any of the names in arm_cpus. */
344 static char selected_cpu_name
[20];
346 extern FLONUM_TYPE generic_floating_point_number
;
348 /* Return if no cpu was selected on command-line. */
350 no_cpu_selected (void)
352 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
357 static int meabi_flags
= EABI_DEFAULT
;
359 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
362 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
367 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
372 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
373 symbolS
* GOT_symbol
;
376 /* 0: assemble for ARM,
377 1: assemble for Thumb,
378 2: assemble for Thumb even though target CPU does not support thumb
380 static int thumb_mode
= 0;
381 /* A value distinct from the possible values for thumb_mode that we
382 can use to record whether thumb_mode has been copied into the
383 tc_frag_data field of a frag. */
384 #define MODE_RECORDED (1 << 4)
386 /* Specifies the intrinsic IT insn behavior mode. */
387 enum implicit_it_mode
389 IMPLICIT_IT_MODE_NEVER
= 0x00,
390 IMPLICIT_IT_MODE_ARM
= 0x01,
391 IMPLICIT_IT_MODE_THUMB
= 0x02,
392 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
394 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
396 /* If unified_syntax is true, we are processing the new unified
397 ARM/Thumb syntax. Important differences from the old ARM mode:
399 - Immediate operands do not require a # prefix.
400 - Conditional affixes always appear at the end of the
401 instruction. (For backward compatibility, those instructions
402 that formerly had them in the middle, continue to accept them
404 - The IT instruction may appear, and if it does is validated
405 against subsequent conditional affixes. It does not generate
408 Important differences from the old Thumb mode:
410 - Immediate operands do not require a # prefix.
411 - Most of the V6T2 instructions are only available in unified mode.
412 - The .N and .W suffixes are recognized and honored (it is an error
413 if they cannot be honored).
414 - All instructions set the flags if and only if they have an 's' affix.
415 - Conditional affixes may be used. They are validated against
416 preceding IT instructions. Unlike ARM mode, you cannot use a
417 conditional affix except in the scope of an IT instruction. */
419 static bfd_boolean unified_syntax
= FALSE
;
421 /* An immediate operand can start with #, and ld*, st*, pld operands
422 can contain [ and ]. We need to tell APP not to elide whitespace
423 before a [, which can appear as the first operand for pld.
424 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
425 const char arm_symbol_chars
[] = "#[]{}";
440 enum neon_el_type type
;
444 #define NEON_MAX_TYPE_ELS 4
448 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
452 enum it_instruction_type
457 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
458 if inside, should be the last one. */
459 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
460 i.e. BKPT and NOP. */
461 IT_INSN
/* The IT insn has been parsed. */
464 /* The maximum number of operands we need. */
465 #define ARM_IT_MAX_OPERANDS 6
470 unsigned long instruction
;
474 /* "uncond_value" is set to the value in place of the conditional field in
475 unconditional versions of the instruction, or -1 if nothing is
478 struct neon_type vectype
;
479 /* This does not indicate an actual NEON instruction, only that
480 the mnemonic accepts neon-style type suffixes. */
482 /* Set to the opcode if the instruction needs relaxation.
483 Zero if the instruction is not relaxed. */
487 bfd_reloc_code_real_type type
;
492 enum it_instruction_type it_insn_type
;
498 struct neon_type_el vectype
;
499 unsigned present
: 1; /* Operand present. */
500 unsigned isreg
: 1; /* Operand was a register. */
501 unsigned immisreg
: 1; /* .imm field is a second register. */
502 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
503 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
504 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
505 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
506 instructions. This allows us to disambiguate ARM <-> vector insns. */
507 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
508 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
509 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
510 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
511 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
512 unsigned writeback
: 1; /* Operand has trailing ! */
513 unsigned preind
: 1; /* Preindexed address. */
514 unsigned postind
: 1; /* Postindexed address. */
515 unsigned negative
: 1; /* Index register was negated. */
516 unsigned shifted
: 1; /* Shift applied to operation. */
517 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
518 } operands
[ARM_IT_MAX_OPERANDS
];
521 static struct arm_it inst
;
523 #define NUM_FLOAT_VALS 8
525 const char * fp_const
[] =
527 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
530 /* Number of littlenums required to hold an extended precision number. */
531 #define MAX_LITTLENUMS 6
533 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
543 #define CP_T_X 0x00008000
544 #define CP_T_Y 0x00400000
546 #define CONDS_BIT 0x00100000
547 #define LOAD_BIT 0x00100000
549 #define DOUBLE_LOAD_FLAG 0x00000001
553 const char * template_name
;
557 #define COND_ALWAYS 0xE
561 const char * template_name
;
565 struct asm_barrier_opt
567 const char * template_name
;
569 const arm_feature_set arch
;
572 /* The bit that distinguishes CPSR and SPSR. */
573 #define SPSR_BIT (1 << 22)
575 /* The individual PSR flag bits. */
576 #define PSR_c (1 << 16)
577 #define PSR_x (1 << 17)
578 #define PSR_s (1 << 18)
579 #define PSR_f (1 << 19)
584 bfd_reloc_code_real_type reloc
;
589 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
590 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
595 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
598 /* Bits for DEFINED field in neon_typed_alias. */
599 #define NTA_HASTYPE 1
600 #define NTA_HASINDEX 2
602 struct neon_typed_alias
604 unsigned char defined
;
606 struct neon_type_el eltype
;
609 /* ARM register categories. This includes coprocessor numbers and various
610 architecture extensions' registers. Each entry should have an error message
611 in reg_expected_msgs below. */
639 /* Structure for a hash table entry for a register.
640 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
641 information which states whether a vector type or index is specified (for a
642 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
648 unsigned char builtin
;
649 struct neon_typed_alias
* neon
;
652 /* Diagnostics used when we don't get a register of the expected type. */
653 const char * const reg_expected_msgs
[] =
655 [REG_TYPE_RN
] = N_("ARM register expected"),
656 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
657 [REG_TYPE_CN
] = N_("co-processor register expected"),
658 [REG_TYPE_FN
] = N_("FPA register expected"),
659 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
660 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
661 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
662 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
663 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
664 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
665 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
667 [REG_TYPE_VFC
] = N_("VFP system register expected"),
668 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
669 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
670 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
671 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
672 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
673 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
674 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
675 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
676 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
677 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
678 [REG_TYPE_RNB
] = N_("")
681 /* Some well known registers that we refer to directly elsewhere. */
687 /* ARM instructions take 4bytes in the object file, Thumb instructions
693 /* Basic string to match. */
694 const char * template_name
;
696 /* Parameters to instruction. */
697 unsigned int operands
[8];
699 /* Conditional tag - see opcode_lookup. */
700 unsigned int tag
: 4;
702 /* Basic instruction code. */
703 unsigned int avalue
: 28;
705 /* Thumb-format instruction code. */
708 /* Which architecture variant provides this instruction. */
709 const arm_feature_set
* avariant
;
710 const arm_feature_set
* tvariant
;
712 /* Function to call to encode instruction in ARM format. */
713 void (* aencode
) (void);
715 /* Function to call to encode instruction in Thumb format. */
716 void (* tencode
) (void);
719 /* Defines for various bits that we will want to toggle. */
720 #define INST_IMMEDIATE 0x02000000
721 #define OFFSET_REG 0x02000000
722 #define HWOFFSET_IMM 0x00400000
723 #define SHIFT_BY_REG 0x00000010
724 #define PRE_INDEX 0x01000000
725 #define INDEX_UP 0x00800000
726 #define WRITE_BACK 0x00200000
727 #define LDM_TYPE_2_OR_3 0x00400000
728 #define CPSI_MMOD 0x00020000
730 #define LITERAL_MASK 0xf000f000
731 #define OPCODE_MASK 0xfe1fffff
732 #define V4_STR_BIT 0x00000020
733 #define VLDR_VMOV_SAME 0x0040f000
735 #define T2_SUBS_PC_LR 0xf3de8f00
737 #define DATA_OP_SHIFT 21
738 #define SBIT_SHIFT 20
740 #define T2_OPCODE_MASK 0xfe1fffff
741 #define T2_DATA_OP_SHIFT 21
742 #define T2_SBIT_SHIFT 20
744 #define A_COND_MASK 0xf0000000
745 #define A_PUSH_POP_OP_MASK 0x0fff0000
747 /* Opcodes for pushing/poping registers to/from the stack. */
748 #define A1_OPCODE_PUSH 0x092d0000
749 #define A2_OPCODE_PUSH 0x052d0004
750 #define A2_OPCODE_POP 0x049d0004
752 /* Codes to distinguish the arithmetic instructions. */
763 #define OPCODE_CMP 10
764 #define OPCODE_CMN 11
765 #define OPCODE_ORR 12
766 #define OPCODE_MOV 13
767 #define OPCODE_BIC 14
768 #define OPCODE_MVN 15
770 #define T2_OPCODE_AND 0
771 #define T2_OPCODE_BIC 1
772 #define T2_OPCODE_ORR 2
773 #define T2_OPCODE_ORN 3
774 #define T2_OPCODE_EOR 4
775 #define T2_OPCODE_ADD 8
776 #define T2_OPCODE_ADC 10
777 #define T2_OPCODE_SBC 11
778 #define T2_OPCODE_SUB 13
779 #define T2_OPCODE_RSB 14
781 #define T_OPCODE_MUL 0x4340
782 #define T_OPCODE_TST 0x4200
783 #define T_OPCODE_CMN 0x42c0
784 #define T_OPCODE_NEG 0x4240
785 #define T_OPCODE_MVN 0x43c0
787 #define T_OPCODE_ADD_R3 0x1800
788 #define T_OPCODE_SUB_R3 0x1a00
789 #define T_OPCODE_ADD_HI 0x4400
790 #define T_OPCODE_ADD_ST 0xb000
791 #define T_OPCODE_SUB_ST 0xb080
792 #define T_OPCODE_ADD_SP 0xa800
793 #define T_OPCODE_ADD_PC 0xa000
794 #define T_OPCODE_ADD_I8 0x3000
795 #define T_OPCODE_SUB_I8 0x3800
796 #define T_OPCODE_ADD_I3 0x1c00
797 #define T_OPCODE_SUB_I3 0x1e00
799 #define T_OPCODE_ASR_R 0x4100
800 #define T_OPCODE_LSL_R 0x4080
801 #define T_OPCODE_LSR_R 0x40c0
802 #define T_OPCODE_ROR_R 0x41c0
803 #define T_OPCODE_ASR_I 0x1000
804 #define T_OPCODE_LSL_I 0x0000
805 #define T_OPCODE_LSR_I 0x0800
807 #define T_OPCODE_MOV_I8 0x2000
808 #define T_OPCODE_CMP_I8 0x2800
809 #define T_OPCODE_CMP_LR 0x4280
810 #define T_OPCODE_MOV_HR 0x4600
811 #define T_OPCODE_CMP_HR 0x4500
813 #define T_OPCODE_LDR_PC 0x4800
814 #define T_OPCODE_LDR_SP 0x9800
815 #define T_OPCODE_STR_SP 0x9000
816 #define T_OPCODE_LDR_IW 0x6800
817 #define T_OPCODE_STR_IW 0x6000
818 #define T_OPCODE_LDR_IH 0x8800
819 #define T_OPCODE_STR_IH 0x8000
820 #define T_OPCODE_LDR_IB 0x7800
821 #define T_OPCODE_STR_IB 0x7000
822 #define T_OPCODE_LDR_RW 0x5800
823 #define T_OPCODE_STR_RW 0x5000
824 #define T_OPCODE_LDR_RH 0x5a00
825 #define T_OPCODE_STR_RH 0x5200
826 #define T_OPCODE_LDR_RB 0x5c00
827 #define T_OPCODE_STR_RB 0x5400
829 #define T_OPCODE_PUSH 0xb400
830 #define T_OPCODE_POP 0xbc00
832 #define T_OPCODE_BRANCH 0xe000
834 #define THUMB_SIZE 2 /* Size of thumb instruction. */
835 #define THUMB_PP_PC_LR 0x0100
836 #define THUMB_LOAD_BIT 0x0800
837 #define THUMB2_LOAD_BIT 0x00100000
839 #define BAD_ARGS _("bad arguments to instruction")
840 #define BAD_SP _("r13 not allowed here")
841 #define BAD_PC _("r15 not allowed here")
842 #define BAD_COND _("instruction cannot be conditional")
843 #define BAD_OVERLAP _("registers may not be the same")
844 #define BAD_HIREG _("lo register required")
845 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
846 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
847 #define BAD_BRANCH _("branch must be last instruction in IT block")
848 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
849 #define BAD_NOT_IT _("instruction not allowed in IT block")
850 #define BAD_FPU _("selected FPU does not support instruction")
851 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
852 #define BAD_IT_COND _("incorrect condition in IT block")
853 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
854 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
855 #define BAD_PC_ADDRESSING \
856 _("cannot use register index with PC-relative addressing")
857 #define BAD_PC_WRITEBACK \
858 _("cannot use writeback with PC-relative addressing")
859 #define BAD_RANGE _("branch out of range")
860 #define BAD_FP16 _("selected processor does not support fp16 instruction")
861 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
862 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
864 static struct hash_control
* arm_ops_hsh
;
865 static struct hash_control
* arm_cond_hsh
;
866 static struct hash_control
* arm_shift_hsh
;
867 static struct hash_control
* arm_psr_hsh
;
868 static struct hash_control
* arm_v7m_psr_hsh
;
869 static struct hash_control
* arm_reg_hsh
;
870 static struct hash_control
* arm_reloc_hsh
;
871 static struct hash_control
* arm_barrier_opt_hsh
;
873 /* Stuff needed to resolve the label ambiguity
882 symbolS
* last_label_seen
;
883 static int label_is_thumb_function_name
= FALSE
;
885 /* Literal pool structure. Held on a per-section
886 and per-sub-section basis. */
888 #define MAX_LITERAL_POOL_SIZE 1024
889 typedef struct literal_pool
891 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
892 unsigned int next_free_entry
;
898 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
900 struct literal_pool
* next
;
901 unsigned int alignment
;
904 /* Pointer to a linked list of literal pools. */
905 literal_pool
* list_of_pools
= NULL
;
907 typedef enum asmfunc_states
910 WAITING_ASMFUNC_NAME
,
914 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
917 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
919 static struct current_it now_it
;
923 now_it_compatible (int cond
)
925 return (cond
& ~1) == (now_it
.cc
& ~1);
929 conditional_insn (void)
931 return inst
.cond
!= COND_ALWAYS
;
934 static int in_it_block (void);
936 static int handle_it_state (void);
938 static void force_automatic_it_block_close (void);
940 static void it_fsm_post_encode (void);
942 #define set_it_insn_type(type) \
945 inst.it_insn_type = type; \
946 if (handle_it_state () == FAIL) \
951 #define set_it_insn_type_nonvoid(type, failret) \
954 inst.it_insn_type = type; \
955 if (handle_it_state () == FAIL) \
960 #define set_it_insn_type_last() \
963 if (inst.cond == COND_ALWAYS) \
964 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
966 set_it_insn_type (INSIDE_IT_LAST_INSN); \
972 /* This array holds the chars that always start a comment. If the
973 pre-processor is disabled, these aren't very useful. */
974 char arm_comment_chars
[] = "@";
976 /* This array holds the chars that only start a comment at the beginning of
977 a line. If the line seems to have the form '# 123 filename'
978 .line and .file directives will appear in the pre-processed output. */
979 /* Note that input_file.c hand checks for '#' at the beginning of the
980 first line of the input file. This is because the compiler outputs
981 #NO_APP at the beginning of its output. */
982 /* Also note that comments like this one will always work. */
983 const char line_comment_chars
[] = "#";
985 char arm_line_separator_chars
[] = ";";
987 /* Chars that can be used to separate mant
988 from exp in floating point numbers. */
989 const char EXP_CHARS
[] = "eE";
991 /* Chars that mean this number is a floating point constant. */
995 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
997 /* Prefix characters that indicate the start of an immediate
999 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1001 /* Separator character handling. */
1003 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1006 skip_past_char (char ** str
, char c
)
1008 /* PR gas/14987: Allow for whitespace before the expected character. */
1009 skip_whitespace (*str
);
1020 #define skip_past_comma(str) skip_past_char (str, ',')
1022 /* Arithmetic expressions (possibly involving symbols). */
1024 /* Return TRUE if anything in the expression is a bignum. */
1027 walk_no_bignums (symbolS
* sp
)
1029 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1032 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1034 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1035 || (symbol_get_value_expression (sp
)->X_op_symbol
1036 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1042 static bfd_boolean in_my_get_expression
= FALSE
;
1044 /* Third argument to my_get_expression. */
1045 #define GE_NO_PREFIX 0
1046 #define GE_IMM_PREFIX 1
1047 #define GE_OPT_PREFIX 2
1048 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1049 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1050 #define GE_OPT_PREFIX_BIG 3
1053 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1057 /* In unified syntax, all prefixes are optional. */
1059 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1062 switch (prefix_mode
)
1064 case GE_NO_PREFIX
: break;
1066 if (!is_immediate_prefix (**str
))
1068 inst
.error
= _("immediate expression requires a # prefix");
1074 case GE_OPT_PREFIX_BIG
:
1075 if (is_immediate_prefix (**str
))
1082 memset (ep
, 0, sizeof (expressionS
));
1084 save_in
= input_line_pointer
;
1085 input_line_pointer
= *str
;
1086 in_my_get_expression
= TRUE
;
1088 in_my_get_expression
= FALSE
;
1090 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1092 /* We found a bad or missing expression in md_operand(). */
1093 *str
= input_line_pointer
;
1094 input_line_pointer
= save_in
;
1095 if (inst
.error
== NULL
)
1096 inst
.error
= (ep
->X_op
== O_absent
1097 ? _("missing expression") :_("bad expression"));
1101 /* Get rid of any bignums now, so that we don't generate an error for which
1102 we can't establish a line number later on. Big numbers are never valid
1103 in instructions, which is where this routine is always called. */
1104 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1105 && (ep
->X_op
== O_big
1106 || (ep
->X_add_symbol
1107 && (walk_no_bignums (ep
->X_add_symbol
)
1109 && walk_no_bignums (ep
->X_op_symbol
))))))
1111 inst
.error
= _("invalid constant");
1112 *str
= input_line_pointer
;
1113 input_line_pointer
= save_in
;
1117 *str
= input_line_pointer
;
1118 input_line_pointer
= save_in
;
1122 /* Turn a string in input_line_pointer into a floating point constant
1123 of type TYPE, and store the appropriate bytes in *LITP. The number
1124 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1125 returned, or NULL on OK.
1127 Note that fp constants aren't represent in the normal way on the ARM.
1128 In big endian mode, things are as expected. However, in little endian
1129 mode fp constants are big-endian word-wise, and little-endian byte-wise
1130 within the words. For example, (double) 1.1 in big endian mode is
1131 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1132 the byte sequence 99 99 f1 3f 9a 99 99 99.
1134 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1137 md_atof (int type
, char * litP
, int * sizeP
)
1140 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1172 return _("Unrecognized or unsupported floating point constant");
1175 t
= atof_ieee (input_line_pointer
, type
, words
);
1177 input_line_pointer
= t
;
1178 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1180 if (target_big_endian
)
1182 for (i
= 0; i
< prec
; i
++)
1184 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1185 litP
+= sizeof (LITTLENUM_TYPE
);
1190 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1191 for (i
= prec
- 1; i
>= 0; i
--)
1193 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1194 litP
+= sizeof (LITTLENUM_TYPE
);
1197 /* For a 4 byte float the order of elements in `words' is 1 0.
1198 For an 8 byte float the order is 1 0 3 2. */
1199 for (i
= 0; i
< prec
; i
+= 2)
1201 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1202 sizeof (LITTLENUM_TYPE
));
1203 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1204 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1205 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1212 /* We handle all bad expressions here, so that we can report the faulty
1213 instruction in the error message. */
1216 md_operand (expressionS
* exp
)
1218 if (in_my_get_expression
)
1219 exp
->X_op
= O_illegal
;
1222 /* Immediate values. */
1225 /* Generic immediate-value read function for use in directives.
1226 Accepts anything that 'expression' can fold to a constant.
1227 *val receives the number. */
1230 immediate_for_directive (int *val
)
1233 exp
.X_op
= O_illegal
;
1235 if (is_immediate_prefix (*input_line_pointer
))
1237 input_line_pointer
++;
1241 if (exp
.X_op
!= O_constant
)
1243 as_bad (_("expected #constant"));
1244 ignore_rest_of_line ();
1247 *val
= exp
.X_add_number
;
1252 /* Register parsing. */
1254 /* Generic register parser. CCP points to what should be the
1255 beginning of a register name. If it is indeed a valid register
1256 name, advance CCP over it and return the reg_entry structure;
1257 otherwise return NULL. Does not issue diagnostics. */
1259 static struct reg_entry
*
1260 arm_reg_parse_multi (char **ccp
)
1264 struct reg_entry
*reg
;
1266 skip_whitespace (start
);
1268 #ifdef REGISTER_PREFIX
1269 if (*start
!= REGISTER_PREFIX
)
1273 #ifdef OPTIONAL_REGISTER_PREFIX
1274 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1279 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1284 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1286 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1296 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1297 enum arm_reg_type type
)
1299 /* Alternative syntaxes are accepted for a few register classes. */
1306 /* Generic coprocessor register names are allowed for these. */
1307 if (reg
&& reg
->type
== REG_TYPE_CN
)
1312 /* For backward compatibility, a bare number is valid here. */
1314 unsigned long processor
= strtoul (start
, ccp
, 10);
1315 if (*ccp
!= start
&& processor
<= 15)
1320 case REG_TYPE_MMXWC
:
1321 /* WC includes WCG. ??? I'm not sure this is true for all
1322 instructions that take WC registers. */
1323 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1334 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1335 return value is the register number or FAIL. */
1338 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1341 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1344 /* Do not allow a scalar (reg+index) to parse as a register. */
1345 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1348 if (reg
&& reg
->type
== type
)
1351 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1358 /* Parse a Neon type specifier. *STR should point at the leading '.'
1359 character. Does no verification at this stage that the type fits the opcode
1366 Can all be legally parsed by this function.
1368 Fills in neon_type struct pointer with parsed information, and updates STR
1369 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1370 type, FAIL if not. */
1373 parse_neon_type (struct neon_type
*type
, char **str
)
1380 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1382 enum neon_el_type thistype
= NT_untyped
;
1383 unsigned thissize
= -1u;
1390 /* Just a size without an explicit type. */
1394 switch (TOLOWER (*ptr
))
1396 case 'i': thistype
= NT_integer
; break;
1397 case 'f': thistype
= NT_float
; break;
1398 case 'p': thistype
= NT_poly
; break;
1399 case 's': thistype
= NT_signed
; break;
1400 case 'u': thistype
= NT_unsigned
; break;
1402 thistype
= NT_float
;
1407 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1413 /* .f is an abbreviation for .f32. */
1414 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1419 thissize
= strtoul (ptr
, &ptr
, 10);
1421 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1424 as_bad (_("bad size %d in type specifier"), thissize
);
1432 type
->el
[type
->elems
].type
= thistype
;
1433 type
->el
[type
->elems
].size
= thissize
;
1438 /* Empty/missing type is not a successful parse. */
1439 if (type
->elems
== 0)
1447 /* Errors may be set multiple times during parsing or bit encoding
1448 (particularly in the Neon bits), but usually the earliest error which is set
1449 will be the most meaningful. Avoid overwriting it with later (cascading)
1450 errors by calling this function. */
1453 first_error (const char *err
)
1459 /* Parse a single type, e.g. ".s32", leading period included. */
1461 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1464 struct neon_type optype
;
1468 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1470 if (optype
.elems
== 1)
1471 *vectype
= optype
.el
[0];
1474 first_error (_("only one type should be specified for operand"));
1480 first_error (_("vector type expected"));
1492 /* Special meanings for indices (which have a range of 0-7), which will fit into
1495 #define NEON_ALL_LANES 15
1496 #define NEON_INTERLEAVE_LANES 14
1498 /* Parse either a register or a scalar, with an optional type. Return the
1499 register number, and optionally fill in the actual type of the register
1500 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1501 type/index information in *TYPEINFO. */
1504 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1505 enum arm_reg_type
*rtype
,
1506 struct neon_typed_alias
*typeinfo
)
1509 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1510 struct neon_typed_alias atype
;
1511 struct neon_type_el parsetype
;
1515 atype
.eltype
.type
= NT_invtype
;
1516 atype
.eltype
.size
= -1;
1518 /* Try alternate syntax for some types of register. Note these are mutually
1519 exclusive with the Neon syntax extensions. */
1522 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1530 /* Undo polymorphism when a set of register types may be accepted. */
1531 if ((type
== REG_TYPE_NDQ
1532 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1533 || (type
== REG_TYPE_VFSD
1534 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1535 || (type
== REG_TYPE_NSDQ
1536 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1537 || reg
->type
== REG_TYPE_NQ
))
1538 || (type
== REG_TYPE_NSD
1539 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1540 || (type
== REG_TYPE_MMXWC
1541 && (reg
->type
== REG_TYPE_MMXWCG
)))
1542 type
= (enum arm_reg_type
) reg
->type
;
1544 if (type
!= reg
->type
)
1550 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1552 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1554 first_error (_("can't redefine type for operand"));
1557 atype
.defined
|= NTA_HASTYPE
;
1558 atype
.eltype
= parsetype
;
1561 if (skip_past_char (&str
, '[') == SUCCESS
)
1563 if (type
!= REG_TYPE_VFD
1564 && !(type
== REG_TYPE_VFS
1565 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1567 first_error (_("only D registers may be indexed"));
1571 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1573 first_error (_("can't change index for operand"));
1577 atype
.defined
|= NTA_HASINDEX
;
1579 if (skip_past_char (&str
, ']') == SUCCESS
)
1580 atype
.index
= NEON_ALL_LANES
;
1585 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1587 if (exp
.X_op
!= O_constant
)
1589 first_error (_("constant expression required"));
1593 if (skip_past_char (&str
, ']') == FAIL
)
1596 atype
.index
= exp
.X_add_number
;
1611 /* Like arm_reg_parse, but allow allow the following extra features:
1612 - If RTYPE is non-zero, return the (possibly restricted) type of the
1613 register (e.g. Neon double or quad reg when either has been requested).
1614 - If this is a Neon vector type with additional type information, fill
1615 in the struct pointed to by VECTYPE (if non-NULL).
1616 This function will fault on encountering a scalar. */
1619 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1620 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1622 struct neon_typed_alias atype
;
1624 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1629 /* Do not allow regname(... to parse as a register. */
1633 /* Do not allow a scalar (reg+index) to parse as a register. */
1634 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1636 first_error (_("register operand expected, but got scalar"));
1641 *vectype
= atype
.eltype
;
1648 #define NEON_SCALAR_REG(X) ((X) >> 4)
1649 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1651 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1652 have enough information to be able to do a good job bounds-checking. So, we
1653 just do easy checks here, and do further checks later. */
1656 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1660 struct neon_typed_alias atype
;
1661 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1664 reg_type
= REG_TYPE_VFS
;
1666 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1668 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1671 if (atype
.index
== NEON_ALL_LANES
)
1673 first_error (_("scalar must have an index"));
1676 else if (atype
.index
>= 64 / elsize
)
1678 first_error (_("scalar index out of range"));
1683 *type
= atype
.eltype
;
1687 return reg
* 16 + atype
.index
;
1690 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1693 parse_reg_list (char ** strp
)
1695 char * str
= * strp
;
1699 /* We come back here if we get ranges concatenated by '+' or '|'. */
1702 skip_whitespace (str
);
1716 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1718 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1728 first_error (_("bad range in register list"));
1732 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1734 if (range
& (1 << i
))
1736 (_("Warning: duplicated register (r%d) in register list"),
1744 if (range
& (1 << reg
))
1745 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1747 else if (reg
<= cur_reg
)
1748 as_tsktsk (_("Warning: register range not in ascending order"));
1753 while (skip_past_comma (&str
) != FAIL
1754 || (in_range
= 1, *str
++ == '-'));
1757 if (skip_past_char (&str
, '}') == FAIL
)
1759 first_error (_("missing `}'"));
1767 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1770 if (exp
.X_op
== O_constant
)
1772 if (exp
.X_add_number
1773 != (exp
.X_add_number
& 0x0000ffff))
1775 inst
.error
= _("invalid register mask");
1779 if ((range
& exp
.X_add_number
) != 0)
1781 int regno
= range
& exp
.X_add_number
;
1784 regno
= (1 << regno
) - 1;
1786 (_("Warning: duplicated register (r%d) in register list"),
1790 range
|= exp
.X_add_number
;
1794 if (inst
.reloc
.type
!= 0)
1796 inst
.error
= _("expression too complex");
1800 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1801 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1802 inst
.reloc
.pc_rel
= 0;
1806 if (*str
== '|' || *str
== '+')
1812 while (another_range
);
1818 /* Types of registers in a list. */
1827 /* Parse a VFP register list. If the string is invalid return FAIL.
1828 Otherwise return the number of registers, and set PBASE to the first
1829 register. Parses registers of type ETYPE.
1830 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1831 - Q registers can be used to specify pairs of D registers
1832 - { } can be omitted from around a singleton register list
1833 FIXME: This is not implemented, as it would require backtracking in
1836 This could be done (the meaning isn't really ambiguous), but doesn't
1837 fit in well with the current parsing framework.
1838 - 32 D registers may be used (also true for VFPv3).
1839 FIXME: Types are ignored in these register lists, which is probably a
1843 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1848 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1852 unsigned long mask
= 0;
1855 if (skip_past_char (&str
, '{') == FAIL
)
1857 inst
.error
= _("expecting {");
1864 regtype
= REG_TYPE_VFS
;
1869 regtype
= REG_TYPE_VFD
;
1872 case REGLIST_NEON_D
:
1873 regtype
= REG_TYPE_NDQ
;
1877 if (etype
!= REGLIST_VFP_S
)
1879 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1880 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1884 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1887 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1894 base_reg
= max_regs
;
1898 int setmask
= 1, addregs
= 1;
1900 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1902 if (new_base
== FAIL
)
1904 first_error (_(reg_expected_msgs
[regtype
]));
1908 if (new_base
>= max_regs
)
1910 first_error (_("register out of range in list"));
1914 /* Note: a value of 2 * n is returned for the register Q<n>. */
1915 if (regtype
== REG_TYPE_NQ
)
1921 if (new_base
< base_reg
)
1922 base_reg
= new_base
;
1924 if (mask
& (setmask
<< new_base
))
1926 first_error (_("invalid register list"));
1930 if ((mask
>> new_base
) != 0 && ! warned
)
1932 as_tsktsk (_("register list not in ascending order"));
1936 mask
|= setmask
<< new_base
;
1939 if (*str
== '-') /* We have the start of a range expression */
1945 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1948 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1952 if (high_range
>= max_regs
)
1954 first_error (_("register out of range in list"));
1958 if (regtype
== REG_TYPE_NQ
)
1959 high_range
= high_range
+ 1;
1961 if (high_range
<= new_base
)
1963 inst
.error
= _("register range not in ascending order");
1967 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1969 if (mask
& (setmask
<< new_base
))
1971 inst
.error
= _("invalid register list");
1975 mask
|= setmask
<< new_base
;
1980 while (skip_past_comma (&str
) != FAIL
);
1984 /* Sanity check -- should have raised a parse error above. */
1985 if (count
== 0 || count
> max_regs
)
1990 /* Final test -- the registers must be consecutive. */
1992 for (i
= 0; i
< count
; i
++)
1994 if ((mask
& (1u << i
)) == 0)
1996 inst
.error
= _("non-contiguous register range");
2006 /* True if two alias types are the same. */
2009 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2017 if (a
->defined
!= b
->defined
)
2020 if ((a
->defined
& NTA_HASTYPE
) != 0
2021 && (a
->eltype
.type
!= b
->eltype
.type
2022 || a
->eltype
.size
!= b
->eltype
.size
))
2025 if ((a
->defined
& NTA_HASINDEX
) != 0
2026 && (a
->index
!= b
->index
))
2032 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2033 The base register is put in *PBASE.
2034 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2036 The register stride (minus one) is put in bit 4 of the return value.
2037 Bits [6:5] encode the list length (minus one).
2038 The type of the list elements is put in *ELTYPE, if non-NULL. */
2040 #define NEON_LANE(X) ((X) & 0xf)
2041 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2042 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2045 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2046 struct neon_type_el
*eltype
)
2053 int leading_brace
= 0;
2054 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2055 const char *const incr_error
= _("register stride must be 1 or 2");
2056 const char *const type_error
= _("mismatched element/structure types in list");
2057 struct neon_typed_alias firsttype
;
2058 firsttype
.defined
= 0;
2059 firsttype
.eltype
.type
= NT_invtype
;
2060 firsttype
.eltype
.size
= -1;
2061 firsttype
.index
= -1;
2063 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2068 struct neon_typed_alias atype
;
2069 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2073 first_error (_(reg_expected_msgs
[rtype
]));
2080 if (rtype
== REG_TYPE_NQ
)
2086 else if (reg_incr
== -1)
2088 reg_incr
= getreg
- base_reg
;
2089 if (reg_incr
< 1 || reg_incr
> 2)
2091 first_error (_(incr_error
));
2095 else if (getreg
!= base_reg
+ reg_incr
* count
)
2097 first_error (_(incr_error
));
2101 if (! neon_alias_types_same (&atype
, &firsttype
))
2103 first_error (_(type_error
));
2107 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2111 struct neon_typed_alias htype
;
2112 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2114 lane
= NEON_INTERLEAVE_LANES
;
2115 else if (lane
!= NEON_INTERLEAVE_LANES
)
2117 first_error (_(type_error
));
2122 else if (reg_incr
!= 1)
2124 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2128 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2131 first_error (_(reg_expected_msgs
[rtype
]));
2134 if (! neon_alias_types_same (&htype
, &firsttype
))
2136 first_error (_(type_error
));
2139 count
+= hireg
+ dregs
- getreg
;
2143 /* If we're using Q registers, we can't use [] or [n] syntax. */
2144 if (rtype
== REG_TYPE_NQ
)
2150 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2154 else if (lane
!= atype
.index
)
2156 first_error (_(type_error
));
2160 else if (lane
== -1)
2161 lane
= NEON_INTERLEAVE_LANES
;
2162 else if (lane
!= NEON_INTERLEAVE_LANES
)
2164 first_error (_(type_error
));
2169 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2171 /* No lane set by [x]. We must be interleaving structures. */
2173 lane
= NEON_INTERLEAVE_LANES
;
2176 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2177 || (count
> 1 && reg_incr
== -1))
2179 first_error (_("error parsing element/structure list"));
2183 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2185 first_error (_("expected }"));
2193 *eltype
= firsttype
.eltype
;
2198 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2201 /* Parse an explicit relocation suffix on an expression. This is
2202 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2203 arm_reloc_hsh contains no entries, so this function can only
2204 succeed if there is no () after the word. Returns -1 on error,
2205 BFD_RELOC_UNUSED if there wasn't any suffix. */
2208 parse_reloc (char **str
)
2210 struct reloc_entry
*r
;
2214 return BFD_RELOC_UNUSED
;
2219 while (*q
&& *q
!= ')' && *q
!= ',')
2224 if ((r
= (struct reloc_entry
*)
2225 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2232 /* Directives: register aliases. */
2234 static struct reg_entry
*
2235 insert_reg_alias (char *str
, unsigned number
, int type
)
2237 struct reg_entry
*new_reg
;
2240 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2242 if (new_reg
->builtin
)
2243 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2245 /* Only warn about a redefinition if it's not defined as the
2247 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2248 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2253 name
= xstrdup (str
);
2254 new_reg
= XNEW (struct reg_entry
);
2256 new_reg
->name
= name
;
2257 new_reg
->number
= number
;
2258 new_reg
->type
= type
;
2259 new_reg
->builtin
= FALSE
;
2260 new_reg
->neon
= NULL
;
2262 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2269 insert_neon_reg_alias (char *str
, int number
, int type
,
2270 struct neon_typed_alias
*atype
)
2272 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2276 first_error (_("attempt to redefine typed alias"));
2282 reg
->neon
= XNEW (struct neon_typed_alias
);
2283 *reg
->neon
= *atype
;
2287 /* Look for the .req directive. This is of the form:
2289 new_register_name .req existing_register_name
2291 If we find one, or if it looks sufficiently like one that we want to
2292 handle any error here, return TRUE. Otherwise return FALSE. */
2295 create_register_alias (char * newname
, char *p
)
2297 struct reg_entry
*old
;
2298 char *oldname
, *nbuf
;
2301 /* The input scrubber ensures that whitespace after the mnemonic is
2302 collapsed to single spaces. */
2304 if (strncmp (oldname
, " .req ", 6) != 0)
2308 if (*oldname
== '\0')
2311 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2314 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2318 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2319 the desired alias name, and p points to its end. If not, then
2320 the desired alias name is in the global original_case_string. */
2321 #ifdef TC_CASE_SENSITIVE
2324 newname
= original_case_string
;
2325 nlen
= strlen (newname
);
2328 nbuf
= xmemdup0 (newname
, nlen
);
2330 /* Create aliases under the new name as stated; an all-lowercase
2331 version of the new name; and an all-uppercase version of the new
2333 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2335 for (p
= nbuf
; *p
; p
++)
2338 if (strncmp (nbuf
, newname
, nlen
))
2340 /* If this attempt to create an additional alias fails, do not bother
2341 trying to create the all-lower case alias. We will fail and issue
2342 a second, duplicate error message. This situation arises when the
2343 programmer does something like:
2346 The second .req creates the "Foo" alias but then fails to create
2347 the artificial FOO alias because it has already been created by the
2349 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2356 for (p
= nbuf
; *p
; p
++)
2359 if (strncmp (nbuf
, newname
, nlen
))
2360 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2367 /* Create a Neon typed/indexed register alias using directives, e.g.:
2372 These typed registers can be used instead of the types specified after the
2373 Neon mnemonic, so long as all operands given have types. Types can also be
2374 specified directly, e.g.:
2375 vadd d0.s32, d1.s32, d2.s32 */
2378 create_neon_reg_alias (char *newname
, char *p
)
2380 enum arm_reg_type basetype
;
2381 struct reg_entry
*basereg
;
2382 struct reg_entry mybasereg
;
2383 struct neon_type ntype
;
2384 struct neon_typed_alias typeinfo
;
2385 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2388 typeinfo
.defined
= 0;
2389 typeinfo
.eltype
.type
= NT_invtype
;
2390 typeinfo
.eltype
.size
= -1;
2391 typeinfo
.index
= -1;
2395 if (strncmp (p
, " .dn ", 5) == 0)
2396 basetype
= REG_TYPE_VFD
;
2397 else if (strncmp (p
, " .qn ", 5) == 0)
2398 basetype
= REG_TYPE_NQ
;
2407 basereg
= arm_reg_parse_multi (&p
);
2409 if (basereg
&& basereg
->type
!= basetype
)
2411 as_bad (_("bad type for register"));
2415 if (basereg
== NULL
)
2418 /* Try parsing as an integer. */
2419 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2420 if (exp
.X_op
!= O_constant
)
2422 as_bad (_("expression must be constant"));
2425 basereg
= &mybasereg
;
2426 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2432 typeinfo
= *basereg
->neon
;
2434 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2436 /* We got a type. */
2437 if (typeinfo
.defined
& NTA_HASTYPE
)
2439 as_bad (_("can't redefine the type of a register alias"));
2443 typeinfo
.defined
|= NTA_HASTYPE
;
2444 if (ntype
.elems
!= 1)
2446 as_bad (_("you must specify a single type only"));
2449 typeinfo
.eltype
= ntype
.el
[0];
2452 if (skip_past_char (&p
, '[') == SUCCESS
)
2455 /* We got a scalar index. */
2457 if (typeinfo
.defined
& NTA_HASINDEX
)
2459 as_bad (_("can't redefine the index of a scalar alias"));
2463 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2465 if (exp
.X_op
!= O_constant
)
2467 as_bad (_("scalar index must be constant"));
2471 typeinfo
.defined
|= NTA_HASINDEX
;
2472 typeinfo
.index
= exp
.X_add_number
;
2474 if (skip_past_char (&p
, ']') == FAIL
)
2476 as_bad (_("expecting ]"));
2481 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2482 the desired alias name, and p points to its end. If not, then
2483 the desired alias name is in the global original_case_string. */
2484 #ifdef TC_CASE_SENSITIVE
2485 namelen
= nameend
- newname
;
2487 newname
= original_case_string
;
2488 namelen
= strlen (newname
);
2491 namebuf
= xmemdup0 (newname
, namelen
);
2493 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2494 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2496 /* Insert name in all uppercase. */
2497 for (p
= namebuf
; *p
; p
++)
2500 if (strncmp (namebuf
, newname
, namelen
))
2501 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2502 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2504 /* Insert name in all lowercase. */
2505 for (p
= namebuf
; *p
; p
++)
2508 if (strncmp (namebuf
, newname
, namelen
))
2509 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2510 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2516 /* Should never be called, as .req goes between the alias and the
2517 register name, not at the beginning of the line. */
2520 s_req (int a ATTRIBUTE_UNUSED
)
2522 as_bad (_("invalid syntax for .req directive"));
2526 s_dn (int a ATTRIBUTE_UNUSED
)
2528 as_bad (_("invalid syntax for .dn directive"));
2532 s_qn (int a ATTRIBUTE_UNUSED
)
2534 as_bad (_("invalid syntax for .qn directive"));
2537 /* The .unreq directive deletes an alias which was previously defined
2538 by .req. For example:
2544 s_unreq (int a ATTRIBUTE_UNUSED
)
2549 name
= input_line_pointer
;
2551 while (*input_line_pointer
!= 0
2552 && *input_line_pointer
!= ' '
2553 && *input_line_pointer
!= '\n')
2554 ++input_line_pointer
;
2556 saved_char
= *input_line_pointer
;
2557 *input_line_pointer
= 0;
2560 as_bad (_("invalid syntax for .unreq directive"));
2563 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2567 as_bad (_("unknown register alias '%s'"), name
);
2568 else if (reg
->builtin
)
2569 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2576 hash_delete (arm_reg_hsh
, name
, FALSE
);
2577 free ((char *) reg
->name
);
2582 /* Also locate the all upper case and all lower case versions.
2583 Do not complain if we cannot find one or the other as it
2584 was probably deleted above. */
2586 nbuf
= strdup (name
);
2587 for (p
= nbuf
; *p
; p
++)
2589 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2592 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2593 free ((char *) reg
->name
);
2599 for (p
= nbuf
; *p
; p
++)
2601 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2604 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2605 free ((char *) reg
->name
);
2615 *input_line_pointer
= saved_char
;
2616 demand_empty_rest_of_line ();
2619 /* Directives: Instruction set selection. */
2622 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2623 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2624 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2625 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2627 /* Create a new mapping symbol for the transition to STATE. */
2630 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2633 const char * symname
;
2640 type
= BSF_NO_FLAGS
;
2644 type
= BSF_NO_FLAGS
;
2648 type
= BSF_NO_FLAGS
;
2654 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2655 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2660 THUMB_SET_FUNC (symbolP
, 0);
2661 ARM_SET_THUMB (symbolP
, 0);
2662 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2666 THUMB_SET_FUNC (symbolP
, 1);
2667 ARM_SET_THUMB (symbolP
, 1);
2668 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2676 /* Save the mapping symbols for future reference. Also check that
2677 we do not place two mapping symbols at the same offset within a
2678 frag. We'll handle overlap between frags in
2679 check_mapping_symbols.
2681 If .fill or other data filling directive generates zero sized data,
2682 the mapping symbol for the following code will have the same value
2683 as the one generated for the data filling directive. In this case,
2684 we replace the old symbol with the new one at the same address. */
2687 if (frag
->tc_frag_data
.first_map
!= NULL
)
2689 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2690 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2692 frag
->tc_frag_data
.first_map
= symbolP
;
2694 if (frag
->tc_frag_data
.last_map
!= NULL
)
2696 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2697 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2698 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2700 frag
->tc_frag_data
.last_map
= symbolP
;
2703 /* We must sometimes convert a region marked as code to data during
2704 code alignment, if an odd number of bytes have to be padded. The
2705 code mapping symbol is pushed to an aligned address. */
2708 insert_data_mapping_symbol (enum mstate state
,
2709 valueT value
, fragS
*frag
, offsetT bytes
)
2711 /* If there was already a mapping symbol, remove it. */
2712 if (frag
->tc_frag_data
.last_map
!= NULL
2713 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2715 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2719 know (frag
->tc_frag_data
.first_map
== symp
);
2720 frag
->tc_frag_data
.first_map
= NULL
;
2722 frag
->tc_frag_data
.last_map
= NULL
;
2723 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2726 make_mapping_symbol (MAP_DATA
, value
, frag
);
2727 make_mapping_symbol (state
, value
+ bytes
, frag
);
2730 static void mapping_state_2 (enum mstate state
, int max_chars
);
2732 /* Set the mapping state to STATE. Only call this when about to
2733 emit some STATE bytes to the file. */
2735 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2737 mapping_state (enum mstate state
)
2739 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2741 if (mapstate
== state
)
2742 /* The mapping symbol has already been emitted.
2743 There is nothing else to do. */
2746 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2748 All ARM instructions require 4-byte alignment.
2749 (Almost) all Thumb instructions require 2-byte alignment.
2751 When emitting instructions into any section, mark the section
2754 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2755 but themselves require 2-byte alignment; this applies to some
2756 PC- relative forms. However, these cases will involve implicit
2757 literal pool generation or an explicit .align >=2, both of
2758 which will cause the section to me marked with sufficient
2759 alignment. Thus, we don't handle those cases here. */
2760 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2762 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2763 /* This case will be evaluated later. */
2766 mapping_state_2 (state
, 0);
2769 /* Same as mapping_state, but MAX_CHARS bytes have already been
2770 allocated. Put the mapping symbol that far back. */
2773 mapping_state_2 (enum mstate state
, int max_chars
)
2775 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2777 if (!SEG_NORMAL (now_seg
))
2780 if (mapstate
== state
)
2781 /* The mapping symbol has already been emitted.
2782 There is nothing else to do. */
2785 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2786 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2788 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2789 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2792 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2795 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2796 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2800 #define mapping_state(x) ((void)0)
2801 #define mapping_state_2(x, y) ((void)0)
2804 /* Find the real, Thumb encoded start of a Thumb function. */
2808 find_real_start (symbolS
* symbolP
)
2811 const char * name
= S_GET_NAME (symbolP
);
2812 symbolS
* new_target
;
2814 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2815 #define STUB_NAME ".real_start_of"
2820 /* The compiler may generate BL instructions to local labels because
2821 it needs to perform a branch to a far away location. These labels
2822 do not have a corresponding ".real_start_of" label. We check
2823 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2824 the ".real_start_of" convention for nonlocal branches. */
2825 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2828 real_start
= concat (STUB_NAME
, name
, NULL
);
2829 new_target
= symbol_find (real_start
);
2832 if (new_target
== NULL
)
2834 as_warn (_("Failed to find real start of function: %s\n"), name
);
2835 new_target
= symbolP
;
2843 opcode_select (int width
)
2850 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2851 as_bad (_("selected processor does not support THUMB opcodes"));
2854 /* No need to force the alignment, since we will have been
2855 coming from ARM mode, which is word-aligned. */
2856 record_alignment (now_seg
, 1);
2863 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2864 as_bad (_("selected processor does not support ARM opcodes"));
2869 frag_align (2, 0, 0);
2871 record_alignment (now_seg
, 1);
2876 as_bad (_("invalid instruction size selected (%d)"), width
);
2881 s_arm (int ignore ATTRIBUTE_UNUSED
)
2884 demand_empty_rest_of_line ();
2888 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2891 demand_empty_rest_of_line ();
2895 s_code (int unused ATTRIBUTE_UNUSED
)
2899 temp
= get_absolute_expression ();
2904 opcode_select (temp
);
2908 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2913 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2915 /* If we are not already in thumb mode go into it, EVEN if
2916 the target processor does not support thumb instructions.
2917 This is used by gcc/config/arm/lib1funcs.asm for example
2918 to compile interworking support functions even if the
2919 target processor should not support interworking. */
2923 record_alignment (now_seg
, 1);
2926 demand_empty_rest_of_line ();
2930 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2934 /* The following label is the name/address of the start of a Thumb function.
2935 We need to know this for the interworking support. */
2936 label_is_thumb_function_name
= TRUE
;
2939 /* Perform a .set directive, but also mark the alias as
2940 being a thumb function. */
2943 s_thumb_set (int equiv
)
2945 /* XXX the following is a duplicate of the code for s_set() in read.c
2946 We cannot just call that code as we need to get at the symbol that
2953 /* Especial apologies for the random logic:
2954 This just grew, and could be parsed much more simply!
2956 delim
= get_symbol_name (& name
);
2957 end_name
= input_line_pointer
;
2958 (void) restore_line_pointer (delim
);
2960 if (*input_line_pointer
!= ',')
2963 as_bad (_("expected comma after name \"%s\""), name
);
2965 ignore_rest_of_line ();
2969 input_line_pointer
++;
2972 if (name
[0] == '.' && name
[1] == '\0')
2974 /* XXX - this should not happen to .thumb_set. */
2978 if ((symbolP
= symbol_find (name
)) == NULL
2979 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2982 /* When doing symbol listings, play games with dummy fragments living
2983 outside the normal fragment chain to record the file and line info
2985 if (listing
& LISTING_SYMBOLS
)
2987 extern struct list_info_struct
* listing_tail
;
2988 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2990 memset (dummy_frag
, 0, sizeof (fragS
));
2991 dummy_frag
->fr_type
= rs_fill
;
2992 dummy_frag
->line
= listing_tail
;
2993 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2994 dummy_frag
->fr_symbol
= symbolP
;
2998 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3001 /* "set" symbols are local unless otherwise specified. */
3002 SF_SET_LOCAL (symbolP
);
3003 #endif /* OBJ_COFF */
3004 } /* Make a new symbol. */
3006 symbol_table_insert (symbolP
);
3011 && S_IS_DEFINED (symbolP
)
3012 && S_GET_SEGMENT (symbolP
) != reg_section
)
3013 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3015 pseudo_set (symbolP
);
3017 demand_empty_rest_of_line ();
3019 /* XXX Now we come to the Thumb specific bit of code. */
3021 THUMB_SET_FUNC (symbolP
, 1);
3022 ARM_SET_THUMB (symbolP
, 1);
3023 #if defined OBJ_ELF || defined OBJ_COFF
3024 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3028 /* Directives: Mode selection. */
3030 /* .syntax [unified|divided] - choose the new unified syntax
3031 (same for Arm and Thumb encoding, modulo slight differences in what
3032 can be represented) or the old divergent syntax for each mode. */
3034 s_syntax (int unused ATTRIBUTE_UNUSED
)
3038 delim
= get_symbol_name (& name
);
3040 if (!strcasecmp (name
, "unified"))
3041 unified_syntax
= TRUE
;
3042 else if (!strcasecmp (name
, "divided"))
3043 unified_syntax
= FALSE
;
3046 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3049 (void) restore_line_pointer (delim
);
3050 demand_empty_rest_of_line ();
3053 /* Directives: sectioning and alignment. */
3056 s_bss (int ignore ATTRIBUTE_UNUSED
)
3058 /* We don't support putting frags in the BSS segment, we fake it by
3059 marking in_bss, then looking at s_skip for clues. */
3060 subseg_set (bss_section
, 0);
3061 demand_empty_rest_of_line ();
3063 #ifdef md_elf_section_change_hook
3064 md_elf_section_change_hook ();
3069 s_even (int ignore ATTRIBUTE_UNUSED
)
3071 /* Never make frag if expect extra pass. */
3073 frag_align (1, 0, 0);
3075 record_alignment (now_seg
, 1);
3077 demand_empty_rest_of_line ();
3080 /* Directives: CodeComposer Studio. */
3082 /* .ref (for CodeComposer Studio syntax only). */
3084 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3086 if (codecomposer_syntax
)
3087 ignore_rest_of_line ();
3089 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3092 /* If name is not NULL, then it is used for marking the beginning of a
3093 function, whereas if it is NULL then it means the function end. */
3095 asmfunc_debug (const char * name
)
3097 static const char * last_name
= NULL
;
3101 gas_assert (last_name
== NULL
);
3104 if (debug_type
== DEBUG_STABS
)
3105 stabs_generate_asm_func (name
, name
);
3109 gas_assert (last_name
!= NULL
);
3111 if (debug_type
== DEBUG_STABS
)
3112 stabs_generate_asm_endfunc (last_name
, last_name
);
3119 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3121 if (codecomposer_syntax
)
3123 switch (asmfunc_state
)
3125 case OUTSIDE_ASMFUNC
:
3126 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3129 case WAITING_ASMFUNC_NAME
:
3130 as_bad (_(".asmfunc repeated."));
3133 case WAITING_ENDASMFUNC
:
3134 as_bad (_(".asmfunc without function."));
3137 demand_empty_rest_of_line ();
3140 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3144 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3146 if (codecomposer_syntax
)
3148 switch (asmfunc_state
)
3150 case OUTSIDE_ASMFUNC
:
3151 as_bad (_(".endasmfunc without a .asmfunc."));
3154 case WAITING_ASMFUNC_NAME
:
3155 as_bad (_(".endasmfunc without function."));
3158 case WAITING_ENDASMFUNC
:
3159 asmfunc_state
= OUTSIDE_ASMFUNC
;
3160 asmfunc_debug (NULL
);
3163 demand_empty_rest_of_line ();
3166 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3170 s_ccs_def (int name
)
3172 if (codecomposer_syntax
)
3175 as_bad (_(".def pseudo-op only available with -mccs flag."));
3178 /* Directives: Literal pools. */
3180 static literal_pool
*
3181 find_literal_pool (void)
3183 literal_pool
* pool
;
3185 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3187 if (pool
->section
== now_seg
3188 && pool
->sub_section
== now_subseg
)
3195 static literal_pool
*
3196 find_or_make_literal_pool (void)
3198 /* Next literal pool ID number. */
3199 static unsigned int latest_pool_num
= 1;
3200 literal_pool
* pool
;
3202 pool
= find_literal_pool ();
3206 /* Create a new pool. */
3207 pool
= XNEW (literal_pool
);
3211 pool
->next_free_entry
= 0;
3212 pool
->section
= now_seg
;
3213 pool
->sub_section
= now_subseg
;
3214 pool
->next
= list_of_pools
;
3215 pool
->symbol
= NULL
;
3216 pool
->alignment
= 2;
3218 /* Add it to the list. */
3219 list_of_pools
= pool
;
3222 /* New pools, and emptied pools, will have a NULL symbol. */
3223 if (pool
->symbol
== NULL
)
3225 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3226 (valueT
) 0, &zero_address_frag
);
3227 pool
->id
= latest_pool_num
++;
3234 /* Add the literal in the global 'inst'
3235 structure to the relevant literal pool. */
3238 add_to_lit_pool (unsigned int nbytes
)
3240 #define PADDING_SLOT 0x1
3241 #define LIT_ENTRY_SIZE_MASK 0xFF
3242 literal_pool
* pool
;
3243 unsigned int entry
, pool_size
= 0;
3244 bfd_boolean padding_slot_p
= FALSE
;
3250 imm1
= inst
.operands
[1].imm
;
3251 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3252 : inst
.reloc
.exp
.X_unsigned
? 0
3253 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3254 if (target_big_endian
)
3257 imm2
= inst
.operands
[1].imm
;
3261 pool
= find_or_make_literal_pool ();
3263 /* Check if this literal value is already in the pool. */
3264 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3268 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3269 && (inst
.reloc
.exp
.X_op
== O_constant
)
3270 && (pool
->literals
[entry
].X_add_number
3271 == inst
.reloc
.exp
.X_add_number
)
3272 && (pool
->literals
[entry
].X_md
== nbytes
)
3273 && (pool
->literals
[entry
].X_unsigned
3274 == inst
.reloc
.exp
.X_unsigned
))
3277 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3278 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3279 && (pool
->literals
[entry
].X_add_number
3280 == inst
.reloc
.exp
.X_add_number
)
3281 && (pool
->literals
[entry
].X_add_symbol
3282 == inst
.reloc
.exp
.X_add_symbol
)
3283 && (pool
->literals
[entry
].X_op_symbol
3284 == inst
.reloc
.exp
.X_op_symbol
)
3285 && (pool
->literals
[entry
].X_md
== nbytes
))
3288 else if ((nbytes
== 8)
3289 && !(pool_size
& 0x7)
3290 && ((entry
+ 1) != pool
->next_free_entry
)
3291 && (pool
->literals
[entry
].X_op
== O_constant
)
3292 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3293 && (pool
->literals
[entry
].X_unsigned
3294 == inst
.reloc
.exp
.X_unsigned
)
3295 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3296 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3297 && (pool
->literals
[entry
+ 1].X_unsigned
3298 == inst
.reloc
.exp
.X_unsigned
))
3301 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3302 if (padding_slot_p
&& (nbytes
== 4))
3308 /* Do we need to create a new entry? */
3309 if (entry
== pool
->next_free_entry
)
3311 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3313 inst
.error
= _("literal pool overflow");
3319 /* For 8-byte entries, we align to an 8-byte boundary,
3320 and split it into two 4-byte entries, because on 32-bit
3321 host, 8-byte constants are treated as big num, thus
3322 saved in "generic_bignum" which will be overwritten
3323 by later assignments.
3325 We also need to make sure there is enough space for
3328 We also check to make sure the literal operand is a
3330 if (!(inst
.reloc
.exp
.X_op
== O_constant
3331 || inst
.reloc
.exp
.X_op
== O_big
))
3333 inst
.error
= _("invalid type for literal pool");
3336 else if (pool_size
& 0x7)
3338 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3340 inst
.error
= _("literal pool overflow");
3344 pool
->literals
[entry
] = inst
.reloc
.exp
;
3345 pool
->literals
[entry
].X_op
= O_constant
;
3346 pool
->literals
[entry
].X_add_number
= 0;
3347 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3348 pool
->next_free_entry
+= 1;
3351 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3353 inst
.error
= _("literal pool overflow");
3357 pool
->literals
[entry
] = inst
.reloc
.exp
;
3358 pool
->literals
[entry
].X_op
= O_constant
;
3359 pool
->literals
[entry
].X_add_number
= imm1
;
3360 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3361 pool
->literals
[entry
++].X_md
= 4;
3362 pool
->literals
[entry
] = inst
.reloc
.exp
;
3363 pool
->literals
[entry
].X_op
= O_constant
;
3364 pool
->literals
[entry
].X_add_number
= imm2
;
3365 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3366 pool
->literals
[entry
].X_md
= 4;
3367 pool
->alignment
= 3;
3368 pool
->next_free_entry
+= 1;
3372 pool
->literals
[entry
] = inst
.reloc
.exp
;
3373 pool
->literals
[entry
].X_md
= 4;
3377 /* PR ld/12974: Record the location of the first source line to reference
3378 this entry in the literal pool. If it turns out during linking that the
3379 symbol does not exist we will be able to give an accurate line number for
3380 the (first use of the) missing reference. */
3381 if (debug_type
== DEBUG_DWARF2
)
3382 dwarf2_where (pool
->locs
+ entry
);
3384 pool
->next_free_entry
+= 1;
3386 else if (padding_slot_p
)
3388 pool
->literals
[entry
] = inst
.reloc
.exp
;
3389 pool
->literals
[entry
].X_md
= nbytes
;
3392 inst
.reloc
.exp
.X_op
= O_symbol
;
3393 inst
.reloc
.exp
.X_add_number
= pool_size
;
3394 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3400 tc_start_label_without_colon (void)
3402 bfd_boolean ret
= TRUE
;
3404 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3406 const char *label
= input_line_pointer
;
3408 while (!is_end_of_line
[(int) label
[-1]])
3413 as_bad (_("Invalid label '%s'"), label
);
3417 asmfunc_debug (label
);
3419 asmfunc_state
= WAITING_ENDASMFUNC
;
3425 /* Can't use symbol_new here, so have to create a symbol and then at
3426 a later date assign it a value. That's what these functions do. */
3429 symbol_locate (symbolS
* symbolP
,
3430 const char * name
, /* It is copied, the caller can modify. */
3431 segT segment
, /* Segment identifier (SEG_<something>). */
3432 valueT valu
, /* Symbol value. */
3433 fragS
* frag
) /* Associated fragment. */
3436 char * preserved_copy_of_name
;
3438 name_length
= strlen (name
) + 1; /* +1 for \0. */
3439 obstack_grow (¬es
, name
, name_length
);
3440 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3442 #ifdef tc_canonicalize_symbol_name
3443 preserved_copy_of_name
=
3444 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3447 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3449 S_SET_SEGMENT (symbolP
, segment
);
3450 S_SET_VALUE (symbolP
, valu
);
3451 symbol_clear_list_pointers (symbolP
);
3453 symbol_set_frag (symbolP
, frag
);
3455 /* Link to end of symbol chain. */
3457 extern int symbol_table_frozen
;
3459 if (symbol_table_frozen
)
3463 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3465 obj_symbol_new_hook (symbolP
);
3467 #ifdef tc_symbol_new_hook
3468 tc_symbol_new_hook (symbolP
);
3472 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3473 #endif /* DEBUG_SYMS */
3477 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3480 literal_pool
* pool
;
3483 pool
= find_literal_pool ();
3485 || pool
->symbol
== NULL
3486 || pool
->next_free_entry
== 0)
3489 /* Align pool as you have word accesses.
3490 Only make a frag if we have to. */
3492 frag_align (pool
->alignment
, 0, 0);
3494 record_alignment (now_seg
, 2);
3497 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3498 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3500 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3502 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3503 (valueT
) frag_now_fix (), frag_now
);
3504 symbol_table_insert (pool
->symbol
);
3506 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3508 #if defined OBJ_COFF || defined OBJ_ELF
3509 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3512 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3515 if (debug_type
== DEBUG_DWARF2
)
3516 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3518 /* First output the expression in the instruction to the pool. */
3519 emit_expr (&(pool
->literals
[entry
]),
3520 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3523 /* Mark the pool as empty. */
3524 pool
->next_free_entry
= 0;
3525 pool
->symbol
= NULL
;
3529 /* Forward declarations for functions below, in the MD interface
3531 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3532 static valueT
create_unwind_entry (int);
3533 static void start_unwind_section (const segT
, int);
3534 static void add_unwind_opcode (valueT
, int);
3535 static void flush_pending_unwind (void);
3537 /* Directives: Data. */
3540 s_arm_elf_cons (int nbytes
)
3544 #ifdef md_flush_pending_output
3545 md_flush_pending_output ();
3548 if (is_it_end_of_statement ())
3550 demand_empty_rest_of_line ();
3554 #ifdef md_cons_align
3555 md_cons_align (nbytes
);
3558 mapping_state (MAP_DATA
);
3562 char *base
= input_line_pointer
;
3566 if (exp
.X_op
!= O_symbol
)
3567 emit_expr (&exp
, (unsigned int) nbytes
);
3570 char *before_reloc
= input_line_pointer
;
3571 reloc
= parse_reloc (&input_line_pointer
);
3574 as_bad (_("unrecognized relocation suffix"));
3575 ignore_rest_of_line ();
3578 else if (reloc
== BFD_RELOC_UNUSED
)
3579 emit_expr (&exp
, (unsigned int) nbytes
);
3582 reloc_howto_type
*howto
= (reloc_howto_type
*)
3583 bfd_reloc_type_lookup (stdoutput
,
3584 (bfd_reloc_code_real_type
) reloc
);
3585 int size
= bfd_get_reloc_size (howto
);
3587 if (reloc
== BFD_RELOC_ARM_PLT32
)
3589 as_bad (_("(plt) is only valid on branch targets"));
3590 reloc
= BFD_RELOC_UNUSED
;
3595 as_bad (ngettext ("%s relocations do not fit in %d byte",
3596 "%s relocations do not fit in %d bytes",
3598 howto
->name
, nbytes
);
3601 /* We've parsed an expression stopping at O_symbol.
3602 But there may be more expression left now that we
3603 have parsed the relocation marker. Parse it again.
3604 XXX Surely there is a cleaner way to do this. */
3605 char *p
= input_line_pointer
;
3607 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3609 memcpy (save_buf
, base
, input_line_pointer
- base
);
3610 memmove (base
+ (input_line_pointer
- before_reloc
),
3611 base
, before_reloc
- base
);
3613 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3615 memcpy (base
, save_buf
, p
- base
);
3617 offset
= nbytes
- size
;
3618 p
= frag_more (nbytes
);
3619 memset (p
, 0, nbytes
);
3620 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3621 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3627 while (*input_line_pointer
++ == ',');
3629 /* Put terminator back into stream. */
3630 input_line_pointer
--;
3631 demand_empty_rest_of_line ();
3634 /* Emit an expression containing a 32-bit thumb instruction.
3635 Implementation based on put_thumb32_insn. */
3638 emit_thumb32_expr (expressionS
* exp
)
3640 expressionS exp_high
= *exp
;
3642 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3643 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3644 exp
->X_add_number
&= 0xffff;
3645 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3648 /* Guess the instruction size based on the opcode. */
3651 thumb_insn_size (int opcode
)
3653 if ((unsigned int) opcode
< 0xe800u
)
3655 else if ((unsigned int) opcode
>= 0xe8000000u
)
3662 emit_insn (expressionS
*exp
, int nbytes
)
3666 if (exp
->X_op
== O_constant
)
3671 size
= thumb_insn_size (exp
->X_add_number
);
3675 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3677 as_bad (_(".inst.n operand too big. "\
3678 "Use .inst.w instead"));
3683 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3684 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3686 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3688 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3689 emit_thumb32_expr (exp
);
3691 emit_expr (exp
, (unsigned int) size
);
3693 it_fsm_post_encode ();
3697 as_bad (_("cannot determine Thumb instruction size. " \
3698 "Use .inst.n/.inst.w instead"));
3701 as_bad (_("constant expression required"));
3706 /* Like s_arm_elf_cons but do not use md_cons_align and
3707 set the mapping state to MAP_ARM/MAP_THUMB. */
3710 s_arm_elf_inst (int nbytes
)
3712 if (is_it_end_of_statement ())
3714 demand_empty_rest_of_line ();
3718 /* Calling mapping_state () here will not change ARM/THUMB,
3719 but will ensure not to be in DATA state. */
3722 mapping_state (MAP_THUMB
);
3727 as_bad (_("width suffixes are invalid in ARM mode"));
3728 ignore_rest_of_line ();
3734 mapping_state (MAP_ARM
);
3743 if (! emit_insn (& exp
, nbytes
))
3745 ignore_rest_of_line ();
3749 while (*input_line_pointer
++ == ',');
3751 /* Put terminator back into stream. */
3752 input_line_pointer
--;
3753 demand_empty_rest_of_line ();
3756 /* Parse a .rel31 directive. */
3759 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3766 if (*input_line_pointer
== '1')
3767 highbit
= 0x80000000;
3768 else if (*input_line_pointer
!= '0')
3769 as_bad (_("expected 0 or 1"));
3771 input_line_pointer
++;
3772 if (*input_line_pointer
!= ',')
3773 as_bad (_("missing comma"));
3774 input_line_pointer
++;
3776 #ifdef md_flush_pending_output
3777 md_flush_pending_output ();
3780 #ifdef md_cons_align
3784 mapping_state (MAP_DATA
);
3789 md_number_to_chars (p
, highbit
, 4);
3790 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3791 BFD_RELOC_ARM_PREL31
);
3793 demand_empty_rest_of_line ();
3796 /* Directives: AEABI stack-unwind tables. */
3798 /* Parse an unwind_fnstart directive. Simply records the current location. */
3801 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3803 demand_empty_rest_of_line ();
3804 if (unwind
.proc_start
)
3806 as_bad (_("duplicate .fnstart directive"));
3810 /* Mark the start of the function. */
3811 unwind
.proc_start
= expr_build_dot ();
3813 /* Reset the rest of the unwind info. */
3814 unwind
.opcode_count
= 0;
3815 unwind
.table_entry
= NULL
;
3816 unwind
.personality_routine
= NULL
;
3817 unwind
.personality_index
= -1;
3818 unwind
.frame_size
= 0;
3819 unwind
.fp_offset
= 0;
3820 unwind
.fp_reg
= REG_SP
;
3822 unwind
.sp_restored
= 0;
3826 /* Parse a handlerdata directive. Creates the exception handling table entry
3827 for the function. */
3830 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3832 demand_empty_rest_of_line ();
3833 if (!unwind
.proc_start
)
3834 as_bad (MISSING_FNSTART
);
3836 if (unwind
.table_entry
)
3837 as_bad (_("duplicate .handlerdata directive"));
3839 create_unwind_entry (1);
3842 /* Parse an unwind_fnend directive. Generates the index table entry. */
3845 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3850 unsigned int marked_pr_dependency
;
3852 demand_empty_rest_of_line ();
3854 if (!unwind
.proc_start
)
3856 as_bad (_(".fnend directive without .fnstart"));
3860 /* Add eh table entry. */
3861 if (unwind
.table_entry
== NULL
)
3862 val
= create_unwind_entry (0);
3866 /* Add index table entry. This is two words. */
3867 start_unwind_section (unwind
.saved_seg
, 1);
3868 frag_align (2, 0, 0);
3869 record_alignment (now_seg
, 2);
3871 ptr
= frag_more (8);
3873 where
= frag_now_fix () - 8;
3875 /* Self relative offset of the function start. */
3876 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3877 BFD_RELOC_ARM_PREL31
);
3879 /* Indicate dependency on EHABI-defined personality routines to the
3880 linker, if it hasn't been done already. */
3881 marked_pr_dependency
3882 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3883 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3884 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3886 static const char *const name
[] =
3888 "__aeabi_unwind_cpp_pr0",
3889 "__aeabi_unwind_cpp_pr1",
3890 "__aeabi_unwind_cpp_pr2"
3892 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3893 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3894 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3895 |= 1 << unwind
.personality_index
;
3899 /* Inline exception table entry. */
3900 md_number_to_chars (ptr
+ 4, val
, 4);
3902 /* Self relative offset of the table entry. */
3903 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3904 BFD_RELOC_ARM_PREL31
);
3906 /* Restore the original section. */
3907 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3909 unwind
.proc_start
= NULL
;
3913 /* Parse an unwind_cantunwind directive. */
3916 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3918 demand_empty_rest_of_line ();
3919 if (!unwind
.proc_start
)
3920 as_bad (MISSING_FNSTART
);
3922 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3923 as_bad (_("personality routine specified for cantunwind frame"));
3925 unwind
.personality_index
= -2;
3929 /* Parse a personalityindex directive. */
3932 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3936 if (!unwind
.proc_start
)
3937 as_bad (MISSING_FNSTART
);
3939 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3940 as_bad (_("duplicate .personalityindex directive"));
3944 if (exp
.X_op
!= O_constant
3945 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3947 as_bad (_("bad personality routine number"));
3948 ignore_rest_of_line ();
3952 unwind
.personality_index
= exp
.X_add_number
;
3954 demand_empty_rest_of_line ();
3958 /* Parse a personality directive. */
3961 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3965 if (!unwind
.proc_start
)
3966 as_bad (MISSING_FNSTART
);
3968 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3969 as_bad (_("duplicate .personality directive"));
3971 c
= get_symbol_name (& name
);
3972 p
= input_line_pointer
;
3974 ++ input_line_pointer
;
3975 unwind
.personality_routine
= symbol_find_or_make (name
);
3977 demand_empty_rest_of_line ();
3981 /* Parse a directive saving core registers. */
3984 s_arm_unwind_save_core (void)
3990 range
= parse_reg_list (&input_line_pointer
);
3993 as_bad (_("expected register list"));
3994 ignore_rest_of_line ();
3998 demand_empty_rest_of_line ();
4000 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4001 into .unwind_save {..., sp...}. We aren't bothered about the value of
4002 ip because it is clobbered by calls. */
4003 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4004 && (range
& 0x3000) == 0x1000)
4006 unwind
.opcode_count
--;
4007 unwind
.sp_restored
= 0;
4008 range
= (range
| 0x2000) & ~0x1000;
4009 unwind
.pending_offset
= 0;
4015 /* See if we can use the short opcodes. These pop a block of up to 8
4016 registers starting with r4, plus maybe r14. */
4017 for (n
= 0; n
< 8; n
++)
4019 /* Break at the first non-saved register. */
4020 if ((range
& (1 << (n
+ 4))) == 0)
4023 /* See if there are any other bits set. */
4024 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4026 /* Use the long form. */
4027 op
= 0x8000 | ((range
>> 4) & 0xfff);
4028 add_unwind_opcode (op
, 2);
4032 /* Use the short form. */
4034 op
= 0xa8; /* Pop r14. */
4036 op
= 0xa0; /* Do not pop r14. */
4038 add_unwind_opcode (op
, 1);
4045 op
= 0xb100 | (range
& 0xf);
4046 add_unwind_opcode (op
, 2);
4049 /* Record the number of bytes pushed. */
4050 for (n
= 0; n
< 16; n
++)
4052 if (range
& (1 << n
))
4053 unwind
.frame_size
+= 4;
4058 /* Parse a directive saving FPA registers. */
4061 s_arm_unwind_save_fpa (int reg
)
4067 /* Get Number of registers to transfer. */
4068 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4071 exp
.X_op
= O_illegal
;
4073 if (exp
.X_op
!= O_constant
)
4075 as_bad (_("expected , <constant>"));
4076 ignore_rest_of_line ();
4080 num_regs
= exp
.X_add_number
;
4082 if (num_regs
< 1 || num_regs
> 4)
4084 as_bad (_("number of registers must be in the range [1:4]"));
4085 ignore_rest_of_line ();
4089 demand_empty_rest_of_line ();
4094 op
= 0xb4 | (num_regs
- 1);
4095 add_unwind_opcode (op
, 1);
4100 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4101 add_unwind_opcode (op
, 2);
4103 unwind
.frame_size
+= num_regs
* 12;
4107 /* Parse a directive saving VFP registers for ARMv6 and above. */
4110 s_arm_unwind_save_vfp_armv6 (void)
4115 int num_vfpv3_regs
= 0;
4116 int num_regs_below_16
;
4118 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4121 as_bad (_("expected register list"));
4122 ignore_rest_of_line ();
4126 demand_empty_rest_of_line ();
4128 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4129 than FSTMX/FLDMX-style ones). */
4131 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4133 num_vfpv3_regs
= count
;
4134 else if (start
+ count
> 16)
4135 num_vfpv3_regs
= start
+ count
- 16;
4137 if (num_vfpv3_regs
> 0)
4139 int start_offset
= start
> 16 ? start
- 16 : 0;
4140 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4141 add_unwind_opcode (op
, 2);
4144 /* Generate opcode for registers numbered in the range 0 .. 15. */
4145 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4146 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4147 if (num_regs_below_16
> 0)
4149 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4150 add_unwind_opcode (op
, 2);
4153 unwind
.frame_size
+= count
* 8;
4157 /* Parse a directive saving VFP registers for pre-ARMv6. */
4160 s_arm_unwind_save_vfp (void)
4166 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4169 as_bad (_("expected register list"));
4170 ignore_rest_of_line ();
4174 demand_empty_rest_of_line ();
4179 op
= 0xb8 | (count
- 1);
4180 add_unwind_opcode (op
, 1);
4185 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4186 add_unwind_opcode (op
, 2);
4188 unwind
.frame_size
+= count
* 8 + 4;
4192 /* Parse a directive saving iWMMXt data registers. */
4195 s_arm_unwind_save_mmxwr (void)
4203 if (*input_line_pointer
== '{')
4204 input_line_pointer
++;
4208 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4212 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4217 as_tsktsk (_("register list not in ascending order"));
4220 if (*input_line_pointer
== '-')
4222 input_line_pointer
++;
4223 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4226 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4229 else if (reg
>= hi_reg
)
4231 as_bad (_("bad register range"));
4234 for (; reg
< hi_reg
; reg
++)
4238 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4240 skip_past_char (&input_line_pointer
, '}');
4242 demand_empty_rest_of_line ();
4244 /* Generate any deferred opcodes because we're going to be looking at
4246 flush_pending_unwind ();
4248 for (i
= 0; i
< 16; i
++)
4250 if (mask
& (1 << i
))
4251 unwind
.frame_size
+= 8;
4254 /* Attempt to combine with a previous opcode. We do this because gcc
4255 likes to output separate unwind directives for a single block of
4257 if (unwind
.opcode_count
> 0)
4259 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4260 if ((i
& 0xf8) == 0xc0)
4263 /* Only merge if the blocks are contiguous. */
4266 if ((mask
& 0xfe00) == (1 << 9))
4268 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4269 unwind
.opcode_count
--;
4272 else if (i
== 6 && unwind
.opcode_count
>= 2)
4274 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4278 op
= 0xffff << (reg
- 1);
4280 && ((mask
& op
) == (1u << (reg
- 1))))
4282 op
= (1 << (reg
+ i
+ 1)) - 1;
4283 op
&= ~((1 << reg
) - 1);
4285 unwind
.opcode_count
-= 2;
4292 /* We want to generate opcodes in the order the registers have been
4293 saved, ie. descending order. */
4294 for (reg
= 15; reg
>= -1; reg
--)
4296 /* Save registers in blocks. */
4298 || !(mask
& (1 << reg
)))
4300 /* We found an unsaved reg. Generate opcodes to save the
4307 op
= 0xc0 | (hi_reg
- 10);
4308 add_unwind_opcode (op
, 1);
4313 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4314 add_unwind_opcode (op
, 2);
4323 ignore_rest_of_line ();
4327 s_arm_unwind_save_mmxwcg (void)
4334 if (*input_line_pointer
== '{')
4335 input_line_pointer
++;
4337 skip_whitespace (input_line_pointer
);
4341 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4345 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4351 as_tsktsk (_("register list not in ascending order"));
4354 if (*input_line_pointer
== '-')
4356 input_line_pointer
++;
4357 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4360 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4363 else if (reg
>= hi_reg
)
4365 as_bad (_("bad register range"));
4368 for (; reg
< hi_reg
; reg
++)
4372 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4374 skip_past_char (&input_line_pointer
, '}');
4376 demand_empty_rest_of_line ();
4378 /* Generate any deferred opcodes because we're going to be looking at
4380 flush_pending_unwind ();
4382 for (reg
= 0; reg
< 16; reg
++)
4384 if (mask
& (1 << reg
))
4385 unwind
.frame_size
+= 4;
4388 add_unwind_opcode (op
, 2);
4391 ignore_rest_of_line ();
4395 /* Parse an unwind_save directive.
4396 If the argument is non-zero, this is a .vsave directive. */
4399 s_arm_unwind_save (int arch_v6
)
4402 struct reg_entry
*reg
;
4403 bfd_boolean had_brace
= FALSE
;
4405 if (!unwind
.proc_start
)
4406 as_bad (MISSING_FNSTART
);
4408 /* Figure out what sort of save we have. */
4409 peek
= input_line_pointer
;
4417 reg
= arm_reg_parse_multi (&peek
);
4421 as_bad (_("register expected"));
4422 ignore_rest_of_line ();
4431 as_bad (_("FPA .unwind_save does not take a register list"));
4432 ignore_rest_of_line ();
4435 input_line_pointer
= peek
;
4436 s_arm_unwind_save_fpa (reg
->number
);
4440 s_arm_unwind_save_core ();
4445 s_arm_unwind_save_vfp_armv6 ();
4447 s_arm_unwind_save_vfp ();
4450 case REG_TYPE_MMXWR
:
4451 s_arm_unwind_save_mmxwr ();
4454 case REG_TYPE_MMXWCG
:
4455 s_arm_unwind_save_mmxwcg ();
4459 as_bad (_(".unwind_save does not support this kind of register"));
4460 ignore_rest_of_line ();
4465 /* Parse an unwind_movsp directive. */
4468 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4474 if (!unwind
.proc_start
)
4475 as_bad (MISSING_FNSTART
);
4477 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4480 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4481 ignore_rest_of_line ();
4485 /* Optional constant. */
4486 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4488 if (immediate_for_directive (&offset
) == FAIL
)
4494 demand_empty_rest_of_line ();
4496 if (reg
== REG_SP
|| reg
== REG_PC
)
4498 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4502 if (unwind
.fp_reg
!= REG_SP
)
4503 as_bad (_("unexpected .unwind_movsp directive"));
4505 /* Generate opcode to restore the value. */
4507 add_unwind_opcode (op
, 1);
4509 /* Record the information for later. */
4510 unwind
.fp_reg
= reg
;
4511 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4512 unwind
.sp_restored
= 1;
4515 /* Parse an unwind_pad directive. */
4518 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4522 if (!unwind
.proc_start
)
4523 as_bad (MISSING_FNSTART
);
4525 if (immediate_for_directive (&offset
) == FAIL
)
4530 as_bad (_("stack increment must be multiple of 4"));
4531 ignore_rest_of_line ();
4535 /* Don't generate any opcodes, just record the details for later. */
4536 unwind
.frame_size
+= offset
;
4537 unwind
.pending_offset
+= offset
;
4539 demand_empty_rest_of_line ();
4542 /* Parse an unwind_setfp directive. */
4545 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4551 if (!unwind
.proc_start
)
4552 as_bad (MISSING_FNSTART
);
4554 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4555 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4558 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4560 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4562 as_bad (_("expected <reg>, <reg>"));
4563 ignore_rest_of_line ();
4567 /* Optional constant. */
4568 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4570 if (immediate_for_directive (&offset
) == FAIL
)
4576 demand_empty_rest_of_line ();
4578 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4580 as_bad (_("register must be either sp or set by a previous"
4581 "unwind_movsp directive"));
4585 /* Don't generate any opcodes, just record the information for later. */
4586 unwind
.fp_reg
= fp_reg
;
4588 if (sp_reg
== REG_SP
)
4589 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4591 unwind
.fp_offset
-= offset
;
4594 /* Parse an unwind_raw directive. */
4597 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4600 /* This is an arbitrary limit. */
4601 unsigned char op
[16];
4604 if (!unwind
.proc_start
)
4605 as_bad (MISSING_FNSTART
);
4608 if (exp
.X_op
== O_constant
4609 && skip_past_comma (&input_line_pointer
) != FAIL
)
4611 unwind
.frame_size
+= exp
.X_add_number
;
4615 exp
.X_op
= O_illegal
;
4617 if (exp
.X_op
!= O_constant
)
4619 as_bad (_("expected <offset>, <opcode>"));
4620 ignore_rest_of_line ();
4626 /* Parse the opcode. */
4631 as_bad (_("unwind opcode too long"));
4632 ignore_rest_of_line ();
4634 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4636 as_bad (_("invalid unwind opcode"));
4637 ignore_rest_of_line ();
4640 op
[count
++] = exp
.X_add_number
;
4642 /* Parse the next byte. */
4643 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4649 /* Add the opcode bytes in reverse order. */
4651 add_unwind_opcode (op
[count
], 1);
4653 demand_empty_rest_of_line ();
4657 /* Parse a .eabi_attribute directive. */
4660 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4662 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4664 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4665 attributes_set_explicitly
[tag
] = 1;
4668 /* Emit a tls fix for the symbol. */
4671 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4675 #ifdef md_flush_pending_output
4676 md_flush_pending_output ();
4679 #ifdef md_cons_align
4683 /* Since we're just labelling the code, there's no need to define a
4686 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4687 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4688 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4689 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4691 #endif /* OBJ_ELF */
4693 static void s_arm_arch (int);
4694 static void s_arm_object_arch (int);
4695 static void s_arm_cpu (int);
4696 static void s_arm_fpu (int);
4697 static void s_arm_arch_extension (int);
4702 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4709 if (exp
.X_op
== O_symbol
)
4710 exp
.X_op
= O_secrel
;
4712 emit_expr (&exp
, 4);
4714 while (*input_line_pointer
++ == ',');
4716 input_line_pointer
--;
4717 demand_empty_rest_of_line ();
4721 /* This table describes all the machine specific pseudo-ops the assembler
4722 has to support. The fields are:
4723 pseudo-op name without dot
4724 function to call to execute this pseudo-op
4725 Integer arg to pass to the function. */
4727 const pseudo_typeS md_pseudo_table
[] =
4729 /* Never called because '.req' does not start a line. */
4730 { "req", s_req
, 0 },
4731 /* Following two are likewise never called. */
4734 { "unreq", s_unreq
, 0 },
4735 { "bss", s_bss
, 0 },
4736 { "align", s_align_ptwo
, 2 },
4737 { "arm", s_arm
, 0 },
4738 { "thumb", s_thumb
, 0 },
4739 { "code", s_code
, 0 },
4740 { "force_thumb", s_force_thumb
, 0 },
4741 { "thumb_func", s_thumb_func
, 0 },
4742 { "thumb_set", s_thumb_set
, 0 },
4743 { "even", s_even
, 0 },
4744 { "ltorg", s_ltorg
, 0 },
4745 { "pool", s_ltorg
, 0 },
4746 { "syntax", s_syntax
, 0 },
4747 { "cpu", s_arm_cpu
, 0 },
4748 { "arch", s_arm_arch
, 0 },
4749 { "object_arch", s_arm_object_arch
, 0 },
4750 { "fpu", s_arm_fpu
, 0 },
4751 { "arch_extension", s_arm_arch_extension
, 0 },
4753 { "word", s_arm_elf_cons
, 4 },
4754 { "long", s_arm_elf_cons
, 4 },
4755 { "inst.n", s_arm_elf_inst
, 2 },
4756 { "inst.w", s_arm_elf_inst
, 4 },
4757 { "inst", s_arm_elf_inst
, 0 },
4758 { "rel31", s_arm_rel31
, 0 },
4759 { "fnstart", s_arm_unwind_fnstart
, 0 },
4760 { "fnend", s_arm_unwind_fnend
, 0 },
4761 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4762 { "personality", s_arm_unwind_personality
, 0 },
4763 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4764 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4765 { "save", s_arm_unwind_save
, 0 },
4766 { "vsave", s_arm_unwind_save
, 1 },
4767 { "movsp", s_arm_unwind_movsp
, 0 },
4768 { "pad", s_arm_unwind_pad
, 0 },
4769 { "setfp", s_arm_unwind_setfp
, 0 },
4770 { "unwind_raw", s_arm_unwind_raw
, 0 },
4771 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4772 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4776 /* These are used for dwarf. */
4780 /* These are used for dwarf2. */
4781 { "file", dwarf2_directive_file
, 0 },
4782 { "loc", dwarf2_directive_loc
, 0 },
4783 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4785 { "extend", float_cons
, 'x' },
4786 { "ldouble", float_cons
, 'x' },
4787 { "packed", float_cons
, 'p' },
4789 {"secrel32", pe_directive_secrel
, 0},
4792 /* These are for compatibility with CodeComposer Studio. */
4793 {"ref", s_ccs_ref
, 0},
4794 {"def", s_ccs_def
, 0},
4795 {"asmfunc", s_ccs_asmfunc
, 0},
4796 {"endasmfunc", s_ccs_endasmfunc
, 0},
4801 /* Parser functions used exclusively in instruction operands. */
4803 /* Generic immediate-value read function for use in insn parsing.
4804 STR points to the beginning of the immediate (the leading #);
4805 VAL receives the value; if the value is outside [MIN, MAX]
4806 issue an error. PREFIX_OPT is true if the immediate prefix is
4810 parse_immediate (char **str
, int *val
, int min
, int max
,
4811 bfd_boolean prefix_opt
)
4815 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4816 if (exp
.X_op
!= O_constant
)
4818 inst
.error
= _("constant expression required");
4822 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4824 inst
.error
= _("immediate value out of range");
4828 *val
= exp
.X_add_number
;
4832 /* Less-generic immediate-value read function with the possibility of loading a
4833 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4834 instructions. Puts the result directly in inst.operands[i]. */
4837 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4838 bfd_boolean allow_symbol_p
)
4841 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4844 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4846 if (exp_p
->X_op
== O_constant
)
4848 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4849 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4850 O_constant. We have to be careful not to break compilation for
4851 32-bit X_add_number, though. */
4852 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4854 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4855 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4857 inst
.operands
[i
].regisimm
= 1;
4860 else if (exp_p
->X_op
== O_big
4861 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4863 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4865 /* Bignums have their least significant bits in
4866 generic_bignum[0]. Make sure we put 32 bits in imm and
4867 32 bits in reg, in a (hopefully) portable way. */
4868 gas_assert (parts
!= 0);
4870 /* Make sure that the number is not too big.
4871 PR 11972: Bignums can now be sign-extended to the
4872 size of a .octa so check that the out of range bits
4873 are all zero or all one. */
4874 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4876 LITTLENUM_TYPE m
= -1;
4878 if (generic_bignum
[parts
* 2] != 0
4879 && generic_bignum
[parts
* 2] != m
)
4882 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4883 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4887 inst
.operands
[i
].imm
= 0;
4888 for (j
= 0; j
< parts
; j
++, idx
++)
4889 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4890 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4891 inst
.operands
[i
].reg
= 0;
4892 for (j
= 0; j
< parts
; j
++, idx
++)
4893 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4894 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4895 inst
.operands
[i
].regisimm
= 1;
4897 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4905 /* Returns the pseudo-register number of an FPA immediate constant,
4906 or FAIL if there isn't a valid constant here. */
4909 parse_fpa_immediate (char ** str
)
4911 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4917 /* First try and match exact strings, this is to guarantee
4918 that some formats will work even for cross assembly. */
4920 for (i
= 0; fp_const
[i
]; i
++)
4922 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4926 *str
+= strlen (fp_const
[i
]);
4927 if (is_end_of_line
[(unsigned char) **str
])
4933 /* Just because we didn't get a match doesn't mean that the constant
4934 isn't valid, just that it is in a format that we don't
4935 automatically recognize. Try parsing it with the standard
4936 expression routines. */
4938 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4940 /* Look for a raw floating point number. */
4941 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4942 && is_end_of_line
[(unsigned char) *save_in
])
4944 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4946 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4948 if (words
[j
] != fp_values
[i
][j
])
4952 if (j
== MAX_LITTLENUMS
)
4960 /* Try and parse a more complex expression, this will probably fail
4961 unless the code uses a floating point prefix (eg "0f"). */
4962 save_in
= input_line_pointer
;
4963 input_line_pointer
= *str
;
4964 if (expression (&exp
) == absolute_section
4965 && exp
.X_op
== O_big
4966 && exp
.X_add_number
< 0)
4968 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4970 #define X_PRECISION 5
4971 #define E_PRECISION 15L
4972 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4974 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4976 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4978 if (words
[j
] != fp_values
[i
][j
])
4982 if (j
== MAX_LITTLENUMS
)
4984 *str
= input_line_pointer
;
4985 input_line_pointer
= save_in
;
4992 *str
= input_line_pointer
;
4993 input_line_pointer
= save_in
;
4994 inst
.error
= _("invalid FPA immediate expression");
4998 /* Returns 1 if a number has "quarter-precision" float format
4999 0baBbbbbbc defgh000 00000000 00000000. */
5002 is_quarter_float (unsigned imm
)
5004 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5005 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5009 /* Detect the presence of a floating point or integer zero constant,
5013 parse_ifimm_zero (char **in
)
5017 if (!is_immediate_prefix (**in
))
5019 /* In unified syntax, all prefixes are optional. */
5020 if (!unified_syntax
)
5026 /* Accept #0x0 as a synonym for #0. */
5027 if (strncmp (*in
, "0x", 2) == 0)
5030 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5035 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5036 &generic_floating_point_number
);
5039 && generic_floating_point_number
.sign
== '+'
5040 && (generic_floating_point_number
.low
5041 > generic_floating_point_number
.leader
))
5047 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5048 0baBbbbbbc defgh000 00000000 00000000.
5049 The zero and minus-zero cases need special handling, since they can't be
5050 encoded in the "quarter-precision" float format, but can nonetheless be
5051 loaded as integer constants. */
5054 parse_qfloat_immediate (char **ccp
, int *immed
)
5058 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5059 int found_fpchar
= 0;
5061 skip_past_char (&str
, '#');
5063 /* We must not accidentally parse an integer as a floating-point number. Make
5064 sure that the value we parse is not an integer by checking for special
5065 characters '.' or 'e'.
5066 FIXME: This is a horrible hack, but doing better is tricky because type
5067 information isn't in a very usable state at parse time. */
5069 skip_whitespace (fpnum
);
5071 if (strncmp (fpnum
, "0x", 2) == 0)
5075 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5076 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5086 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5088 unsigned fpword
= 0;
5091 /* Our FP word must be 32 bits (single-precision FP). */
5092 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5094 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5098 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5111 /* Shift operands. */
5114 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5117 struct asm_shift_name
5120 enum shift_kind kind
;
5123 /* Third argument to parse_shift. */
5124 enum parse_shift_mode
5126 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5127 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5128 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5129 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5130 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5133 /* Parse a <shift> specifier on an ARM data processing instruction.
5134 This has three forms:
5136 (LSL|LSR|ASL|ASR|ROR) Rs
5137 (LSL|LSR|ASL|ASR|ROR) #imm
5140 Note that ASL is assimilated to LSL in the instruction encoding, and
5141 RRX to ROR #0 (which cannot be written as such). */
5144 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5146 const struct asm_shift_name
*shift_name
;
5147 enum shift_kind shift
;
5152 for (p
= *str
; ISALPHA (*p
); p
++)
5157 inst
.error
= _("shift expression expected");
5161 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5164 if (shift_name
== NULL
)
5166 inst
.error
= _("shift expression expected");
5170 shift
= shift_name
->kind
;
5174 case NO_SHIFT_RESTRICT
:
5175 case SHIFT_IMMEDIATE
: break;
5177 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5178 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5180 inst
.error
= _("'LSL' or 'ASR' required");
5185 case SHIFT_LSL_IMMEDIATE
:
5186 if (shift
!= SHIFT_LSL
)
5188 inst
.error
= _("'LSL' required");
5193 case SHIFT_ASR_IMMEDIATE
:
5194 if (shift
!= SHIFT_ASR
)
5196 inst
.error
= _("'ASR' required");
5204 if (shift
!= SHIFT_RRX
)
5206 /* Whitespace can appear here if the next thing is a bare digit. */
5207 skip_whitespace (p
);
5209 if (mode
== NO_SHIFT_RESTRICT
5210 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5212 inst
.operands
[i
].imm
= reg
;
5213 inst
.operands
[i
].immisreg
= 1;
5215 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5218 inst
.operands
[i
].shift_kind
= shift
;
5219 inst
.operands
[i
].shifted
= 1;
5224 /* Parse a <shifter_operand> for an ARM data processing instruction:
5227 #<immediate>, <rotate>
5231 where <shift> is defined by parse_shift above, and <rotate> is a
5232 multiple of 2 between 0 and 30. Validation of immediate operands
5233 is deferred to md_apply_fix. */
5236 parse_shifter_operand (char **str
, int i
)
5241 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5243 inst
.operands
[i
].reg
= value
;
5244 inst
.operands
[i
].isreg
= 1;
5246 /* parse_shift will override this if appropriate */
5247 inst
.reloc
.exp
.X_op
= O_constant
;
5248 inst
.reloc
.exp
.X_add_number
= 0;
5250 if (skip_past_comma (str
) == FAIL
)
5253 /* Shift operation on register. */
5254 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5257 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5260 if (skip_past_comma (str
) == SUCCESS
)
5262 /* #x, y -- ie explicit rotation by Y. */
5263 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5266 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5268 inst
.error
= _("constant expression expected");
5272 value
= exp
.X_add_number
;
5273 if (value
< 0 || value
> 30 || value
% 2 != 0)
5275 inst
.error
= _("invalid rotation");
5278 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5280 inst
.error
= _("invalid constant");
5284 /* Encode as specified. */
5285 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5289 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5290 inst
.reloc
.pc_rel
= 0;
5294 /* Group relocation information. Each entry in the table contains the
5295 textual name of the relocation as may appear in assembler source
5296 and must end with a colon.
5297 Along with this textual name are the relocation codes to be used if
5298 the corresponding instruction is an ALU instruction (ADD or SUB only),
5299 an LDR, an LDRS, or an LDC. */
5301 struct group_reloc_table_entry
5312 /* Varieties of non-ALU group relocation. */
5319 static struct group_reloc_table_entry group_reloc_table
[] =
5320 { /* Program counter relative: */
5322 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5327 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5328 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5329 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5330 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5332 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5337 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5338 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5339 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5340 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5342 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5343 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5344 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5345 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5346 /* Section base relative */
5348 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5353 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5354 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5355 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5356 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5358 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5363 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5364 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5365 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5366 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5368 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5369 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5370 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5371 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5372 /* Absolute thumb alu relocations. */
5374 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5379 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5384 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5389 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5394 /* Given the address of a pointer pointing to the textual name of a group
5395 relocation as may appear in assembler source, attempt to find its details
5396 in group_reloc_table. The pointer will be updated to the character after
5397 the trailing colon. On failure, FAIL will be returned; SUCCESS
5398 otherwise. On success, *entry will be updated to point at the relevant
5399 group_reloc_table entry. */
5402 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5405 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5407 int length
= strlen (group_reloc_table
[i
].name
);
5409 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5410 && (*str
)[length
] == ':')
5412 *out
= &group_reloc_table
[i
];
5413 *str
+= (length
+ 1);
5421 /* Parse a <shifter_operand> for an ARM data processing instruction
5422 (as for parse_shifter_operand) where group relocations are allowed:
5425 #<immediate>, <rotate>
5426 #:<group_reloc>:<expression>
5430 where <group_reloc> is one of the strings defined in group_reloc_table.
5431 The hashes are optional.
5433 Everything else is as for parse_shifter_operand. */
5435 static parse_operand_result
5436 parse_shifter_operand_group_reloc (char **str
, int i
)
5438 /* Determine if we have the sequence of characters #: or just :
5439 coming next. If we do, then we check for a group relocation.
5440 If we don't, punt the whole lot to parse_shifter_operand. */
5442 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5443 || (*str
)[0] == ':')
5445 struct group_reloc_table_entry
*entry
;
5447 if ((*str
)[0] == '#')
5452 /* Try to parse a group relocation. Anything else is an error. */
5453 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5455 inst
.error
= _("unknown group relocation");
5456 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5459 /* We now have the group relocation table entry corresponding to
5460 the name in the assembler source. Next, we parse the expression. */
5461 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5462 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5464 /* Record the relocation type (always the ALU variant here). */
5465 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5466 gas_assert (inst
.reloc
.type
!= 0);
5468 return PARSE_OPERAND_SUCCESS
;
5471 return parse_shifter_operand (str
, i
) == SUCCESS
5472 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5474 /* Never reached. */
5477 /* Parse a Neon alignment expression. Information is written to
5478 inst.operands[i]. We assume the initial ':' has been skipped.
5480 align .imm = align << 8, .immisalign=1, .preind=0 */
5481 static parse_operand_result
5482 parse_neon_alignment (char **str
, int i
)
5487 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5489 if (exp
.X_op
!= O_constant
)
5491 inst
.error
= _("alignment must be constant");
5492 return PARSE_OPERAND_FAIL
;
5495 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5496 inst
.operands
[i
].immisalign
= 1;
5497 /* Alignments are not pre-indexes. */
5498 inst
.operands
[i
].preind
= 0;
5501 return PARSE_OPERAND_SUCCESS
;
5504 /* Parse all forms of an ARM address expression. Information is written
5505 to inst.operands[i] and/or inst.reloc.
5507 Preindexed addressing (.preind=1):
5509 [Rn, #offset] .reg=Rn .reloc.exp=offset
5510 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5511 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5512 .shift_kind=shift .reloc.exp=shift_imm
5514 These three may have a trailing ! which causes .writeback to be set also.
5516 Postindexed addressing (.postind=1, .writeback=1):
5518 [Rn], #offset .reg=Rn .reloc.exp=offset
5519 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5520 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5521 .shift_kind=shift .reloc.exp=shift_imm
5523 Unindexed addressing (.preind=0, .postind=0):
5525 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5529 [Rn]{!} shorthand for [Rn,#0]{!}
5530 =immediate .isreg=0 .reloc.exp=immediate
5531 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5533 It is the caller's responsibility to check for addressing modes not
5534 supported by the instruction, and to set inst.reloc.type. */
5536 static parse_operand_result
5537 parse_address_main (char **str
, int i
, int group_relocations
,
5538 group_reloc_type group_type
)
5543 if (skip_past_char (&p
, '[') == FAIL
)
5545 if (skip_past_char (&p
, '=') == FAIL
)
5547 /* Bare address - translate to PC-relative offset. */
5548 inst
.reloc
.pc_rel
= 1;
5549 inst
.operands
[i
].reg
= REG_PC
;
5550 inst
.operands
[i
].isreg
= 1;
5551 inst
.operands
[i
].preind
= 1;
5553 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5554 return PARSE_OPERAND_FAIL
;
5556 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5557 /*allow_symbol_p=*/TRUE
))
5558 return PARSE_OPERAND_FAIL
;
5561 return PARSE_OPERAND_SUCCESS
;
5564 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5565 skip_whitespace (p
);
5567 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5569 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5570 return PARSE_OPERAND_FAIL
;
5572 inst
.operands
[i
].reg
= reg
;
5573 inst
.operands
[i
].isreg
= 1;
5575 if (skip_past_comma (&p
) == SUCCESS
)
5577 inst
.operands
[i
].preind
= 1;
5580 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5582 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5584 inst
.operands
[i
].imm
= reg
;
5585 inst
.operands
[i
].immisreg
= 1;
5587 if (skip_past_comma (&p
) == SUCCESS
)
5588 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5589 return PARSE_OPERAND_FAIL
;
5591 else if (skip_past_char (&p
, ':') == SUCCESS
)
5593 /* FIXME: '@' should be used here, but it's filtered out by generic
5594 code before we get to see it here. This may be subject to
5596 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5598 if (result
!= PARSE_OPERAND_SUCCESS
)
5603 if (inst
.operands
[i
].negative
)
5605 inst
.operands
[i
].negative
= 0;
5609 if (group_relocations
5610 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5612 struct group_reloc_table_entry
*entry
;
5614 /* Skip over the #: or : sequence. */
5620 /* Try to parse a group relocation. Anything else is an
5622 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5624 inst
.error
= _("unknown group relocation");
5625 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5628 /* We now have the group relocation table entry corresponding to
5629 the name in the assembler source. Next, we parse the
5631 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5632 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5634 /* Record the relocation type. */
5638 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5642 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5646 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5653 if (inst
.reloc
.type
== 0)
5655 inst
.error
= _("this group relocation is not allowed on this instruction");
5656 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5663 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5664 return PARSE_OPERAND_FAIL
;
5665 /* If the offset is 0, find out if it's a +0 or -0. */
5666 if (inst
.reloc
.exp
.X_op
== O_constant
5667 && inst
.reloc
.exp
.X_add_number
== 0)
5669 skip_whitespace (q
);
5673 skip_whitespace (q
);
5676 inst
.operands
[i
].negative
= 1;
5681 else if (skip_past_char (&p
, ':') == SUCCESS
)
5683 /* FIXME: '@' should be used here, but it's filtered out by generic code
5684 before we get to see it here. This may be subject to change. */
5685 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5687 if (result
!= PARSE_OPERAND_SUCCESS
)
5691 if (skip_past_char (&p
, ']') == FAIL
)
5693 inst
.error
= _("']' expected");
5694 return PARSE_OPERAND_FAIL
;
5697 if (skip_past_char (&p
, '!') == SUCCESS
)
5698 inst
.operands
[i
].writeback
= 1;
5700 else if (skip_past_comma (&p
) == SUCCESS
)
5702 if (skip_past_char (&p
, '{') == SUCCESS
)
5704 /* [Rn], {expr} - unindexed, with option */
5705 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5706 0, 255, TRUE
) == FAIL
)
5707 return PARSE_OPERAND_FAIL
;
5709 if (skip_past_char (&p
, '}') == FAIL
)
5711 inst
.error
= _("'}' expected at end of 'option' field");
5712 return PARSE_OPERAND_FAIL
;
5714 if (inst
.operands
[i
].preind
)
5716 inst
.error
= _("cannot combine index with option");
5717 return PARSE_OPERAND_FAIL
;
5720 return PARSE_OPERAND_SUCCESS
;
5724 inst
.operands
[i
].postind
= 1;
5725 inst
.operands
[i
].writeback
= 1;
5727 if (inst
.operands
[i
].preind
)
5729 inst
.error
= _("cannot combine pre- and post-indexing");
5730 return PARSE_OPERAND_FAIL
;
5734 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5736 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5738 /* We might be using the immediate for alignment already. If we
5739 are, OR the register number into the low-order bits. */
5740 if (inst
.operands
[i
].immisalign
)
5741 inst
.operands
[i
].imm
|= reg
;
5743 inst
.operands
[i
].imm
= reg
;
5744 inst
.operands
[i
].immisreg
= 1;
5746 if (skip_past_comma (&p
) == SUCCESS
)
5747 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5748 return PARSE_OPERAND_FAIL
;
5754 if (inst
.operands
[i
].negative
)
5756 inst
.operands
[i
].negative
= 0;
5759 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5760 return PARSE_OPERAND_FAIL
;
5761 /* If the offset is 0, find out if it's a +0 or -0. */
5762 if (inst
.reloc
.exp
.X_op
== O_constant
5763 && inst
.reloc
.exp
.X_add_number
== 0)
5765 skip_whitespace (q
);
5769 skip_whitespace (q
);
5772 inst
.operands
[i
].negative
= 1;
5778 /* If at this point neither .preind nor .postind is set, we have a
5779 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5780 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5782 inst
.operands
[i
].preind
= 1;
5783 inst
.reloc
.exp
.X_op
= O_constant
;
5784 inst
.reloc
.exp
.X_add_number
= 0;
5787 return PARSE_OPERAND_SUCCESS
;
5791 parse_address (char **str
, int i
)
5793 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5797 static parse_operand_result
5798 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5800 return parse_address_main (str
, i
, 1, type
);
5803 /* Parse an operand for a MOVW or MOVT instruction. */
5805 parse_half (char **str
)
5810 skip_past_char (&p
, '#');
5811 if (strncasecmp (p
, ":lower16:", 9) == 0)
5812 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5813 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5814 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5816 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5819 skip_whitespace (p
);
5822 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5825 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5827 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5829 inst
.error
= _("constant expression expected");
5832 if (inst
.reloc
.exp
.X_add_number
< 0
5833 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5835 inst
.error
= _("immediate value out of range");
5843 /* Miscellaneous. */
5845 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5846 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5848 parse_psr (char **str
, bfd_boolean lhs
)
5851 unsigned long psr_field
;
5852 const struct asm_psr
*psr
;
5854 bfd_boolean is_apsr
= FALSE
;
5855 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5857 /* PR gas/12698: If the user has specified -march=all then m_profile will
5858 be TRUE, but we want to ignore it in this case as we are building for any
5859 CPU type, including non-m variants. */
5860 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5863 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5864 feature for ease of use and backwards compatibility. */
5866 if (strncasecmp (p
, "SPSR", 4) == 0)
5869 goto unsupported_psr
;
5871 psr_field
= SPSR_BIT
;
5873 else if (strncasecmp (p
, "CPSR", 4) == 0)
5876 goto unsupported_psr
;
5880 else if (strncasecmp (p
, "APSR", 4) == 0)
5882 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5883 and ARMv7-R architecture CPUs. */
5892 while (ISALNUM (*p
) || *p
== '_');
5894 if (strncasecmp (start
, "iapsr", 5) == 0
5895 || strncasecmp (start
, "eapsr", 5) == 0
5896 || strncasecmp (start
, "xpsr", 4) == 0
5897 || strncasecmp (start
, "psr", 3) == 0)
5898 p
= start
+ strcspn (start
, "rR") + 1;
5900 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5906 /* If APSR is being written, a bitfield may be specified. Note that
5907 APSR itself is handled above. */
5908 if (psr
->field
<= 3)
5910 psr_field
= psr
->field
;
5916 /* M-profile MSR instructions have the mask field set to "10", except
5917 *PSR variants which modify APSR, which may use a different mask (and
5918 have been handled already). Do that by setting the PSR_f field
5920 return psr
->field
| (lhs
? PSR_f
: 0);
5923 goto unsupported_psr
;
5929 /* A suffix follows. */
5935 while (ISALNUM (*p
) || *p
== '_');
5939 /* APSR uses a notation for bits, rather than fields. */
5940 unsigned int nzcvq_bits
= 0;
5941 unsigned int g_bit
= 0;
5944 for (bit
= start
; bit
!= p
; bit
++)
5946 switch (TOLOWER (*bit
))
5949 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5953 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5957 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5961 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5965 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5969 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5973 inst
.error
= _("unexpected bit specified after APSR");
5978 if (nzcvq_bits
== 0x1f)
5983 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5985 inst
.error
= _("selected processor does not "
5986 "support DSP extension");
5993 if ((nzcvq_bits
& 0x20) != 0
5994 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5995 || (g_bit
& 0x2) != 0)
5997 inst
.error
= _("bad bitmask specified after APSR");
6003 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6008 psr_field
|= psr
->field
;
6014 goto error
; /* Garbage after "[CS]PSR". */
6016 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6017 is deprecated, but allow it anyway. */
6021 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6024 else if (!m_profile
)
6025 /* These bits are never right for M-profile devices: don't set them
6026 (only code paths which read/write APSR reach here). */
6027 psr_field
|= (PSR_c
| PSR_f
);
6033 inst
.error
= _("selected processor does not support requested special "
6034 "purpose register");
6038 inst
.error
= _("flag for {c}psr instruction expected");
6042 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6043 value suitable for splatting into the AIF field of the instruction. */
6046 parse_cps_flags (char **str
)
6055 case '\0': case ',':
6058 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6059 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6060 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6063 inst
.error
= _("unrecognized CPS flag");
6068 if (saw_a_flag
== 0)
6070 inst
.error
= _("missing CPS flags");
6078 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6079 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6082 parse_endian_specifier (char **str
)
6087 if (strncasecmp (s
, "BE", 2))
6089 else if (strncasecmp (s
, "LE", 2))
6093 inst
.error
= _("valid endian specifiers are be or le");
6097 if (ISALNUM (s
[2]) || s
[2] == '_')
6099 inst
.error
= _("valid endian specifiers are be or le");
6104 return little_endian
;
6107 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6108 value suitable for poking into the rotate field of an sxt or sxta
6109 instruction, or FAIL on error. */
6112 parse_ror (char **str
)
6117 if (strncasecmp (s
, "ROR", 3) == 0)
6121 inst
.error
= _("missing rotation field after comma");
6125 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6130 case 0: *str
= s
; return 0x0;
6131 case 8: *str
= s
; return 0x1;
6132 case 16: *str
= s
; return 0x2;
6133 case 24: *str
= s
; return 0x3;
6136 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6141 /* Parse a conditional code (from conds[] below). The value returned is in the
6142 range 0 .. 14, or FAIL. */
6144 parse_cond (char **str
)
6147 const struct asm_cond
*c
;
6149 /* Condition codes are always 2 characters, so matching up to
6150 3 characters is sufficient. */
6155 while (ISALPHA (*q
) && n
< 3)
6157 cond
[n
] = TOLOWER (*q
);
6162 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6165 inst
.error
= _("condition required");
6173 /* Record a use of the given feature. */
6175 record_feature_use (const arm_feature_set
*feature
)
6178 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6180 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6183 /* If the given feature is currently allowed, mark it as used and return TRUE.
6184 Return FALSE otherwise. */
6186 mark_feature_used (const arm_feature_set
*feature
)
6188 /* Ensure the option is currently allowed. */
6189 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6192 /* Add the appropriate architecture feature for the barrier option used. */
6193 record_feature_use (feature
);
6198 /* Parse an option for a barrier instruction. Returns the encoding for the
6201 parse_barrier (char **str
)
6204 const struct asm_barrier_opt
*o
;
6207 while (ISALPHA (*q
))
6210 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6215 if (!mark_feature_used (&o
->arch
))
6222 /* Parse the operands of a table branch instruction. Similar to a memory
6225 parse_tb (char **str
)
6230 if (skip_past_char (&p
, '[') == FAIL
)
6232 inst
.error
= _("'[' expected");
6236 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6238 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6241 inst
.operands
[0].reg
= reg
;
6243 if (skip_past_comma (&p
) == FAIL
)
6245 inst
.error
= _("',' expected");
6249 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6251 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6254 inst
.operands
[0].imm
= reg
;
6256 if (skip_past_comma (&p
) == SUCCESS
)
6258 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6260 if (inst
.reloc
.exp
.X_add_number
!= 1)
6262 inst
.error
= _("invalid shift");
6265 inst
.operands
[0].shifted
= 1;
6268 if (skip_past_char (&p
, ']') == FAIL
)
6270 inst
.error
= _("']' expected");
6277 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6278 information on the types the operands can take and how they are encoded.
6279 Up to four operands may be read; this function handles setting the
6280 ".present" field for each read operand itself.
6281 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6282 else returns FAIL. */
6285 parse_neon_mov (char **str
, int *which_operand
)
6287 int i
= *which_operand
, val
;
6288 enum arm_reg_type rtype
;
6290 struct neon_type_el optype
;
6292 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6294 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6295 inst
.operands
[i
].reg
= val
;
6296 inst
.operands
[i
].isscalar
= 1;
6297 inst
.operands
[i
].vectype
= optype
;
6298 inst
.operands
[i
++].present
= 1;
6300 if (skip_past_comma (&ptr
) == FAIL
)
6303 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6306 inst
.operands
[i
].reg
= val
;
6307 inst
.operands
[i
].isreg
= 1;
6308 inst
.operands
[i
].present
= 1;
6310 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6313 /* Cases 0, 1, 2, 3, 5 (D only). */
6314 if (skip_past_comma (&ptr
) == FAIL
)
6317 inst
.operands
[i
].reg
= val
;
6318 inst
.operands
[i
].isreg
= 1;
6319 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6320 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6321 inst
.operands
[i
].isvec
= 1;
6322 inst
.operands
[i
].vectype
= optype
;
6323 inst
.operands
[i
++].present
= 1;
6325 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6327 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6328 Case 13: VMOV <Sd>, <Rm> */
6329 inst
.operands
[i
].reg
= val
;
6330 inst
.operands
[i
].isreg
= 1;
6331 inst
.operands
[i
].present
= 1;
6333 if (rtype
== REG_TYPE_NQ
)
6335 first_error (_("can't use Neon quad register here"));
6338 else if (rtype
!= REG_TYPE_VFS
)
6341 if (skip_past_comma (&ptr
) == FAIL
)
6343 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6345 inst
.operands
[i
].reg
= val
;
6346 inst
.operands
[i
].isreg
= 1;
6347 inst
.operands
[i
].present
= 1;
6350 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6353 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6354 Case 1: VMOV<c><q> <Dd>, <Dm>
6355 Case 8: VMOV.F32 <Sd>, <Sm>
6356 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6358 inst
.operands
[i
].reg
= val
;
6359 inst
.operands
[i
].isreg
= 1;
6360 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6361 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6362 inst
.operands
[i
].isvec
= 1;
6363 inst
.operands
[i
].vectype
= optype
;
6364 inst
.operands
[i
].present
= 1;
6366 if (skip_past_comma (&ptr
) == SUCCESS
)
6371 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6374 inst
.operands
[i
].reg
= val
;
6375 inst
.operands
[i
].isreg
= 1;
6376 inst
.operands
[i
++].present
= 1;
6378 if (skip_past_comma (&ptr
) == FAIL
)
6381 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6384 inst
.operands
[i
].reg
= val
;
6385 inst
.operands
[i
].isreg
= 1;
6386 inst
.operands
[i
].present
= 1;
6389 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6390 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6391 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6392 Case 10: VMOV.F32 <Sd>, #<imm>
6393 Case 11: VMOV.F64 <Dd>, #<imm> */
6394 inst
.operands
[i
].immisfloat
= 1;
6395 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6397 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6398 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6402 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6406 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6409 inst
.operands
[i
].reg
= val
;
6410 inst
.operands
[i
].isreg
= 1;
6411 inst
.operands
[i
++].present
= 1;
6413 if (skip_past_comma (&ptr
) == FAIL
)
6416 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6418 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6419 inst
.operands
[i
].reg
= val
;
6420 inst
.operands
[i
].isscalar
= 1;
6421 inst
.operands
[i
].present
= 1;
6422 inst
.operands
[i
].vectype
= optype
;
6424 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6426 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6427 inst
.operands
[i
].reg
= val
;
6428 inst
.operands
[i
].isreg
= 1;
6429 inst
.operands
[i
++].present
= 1;
6431 if (skip_past_comma (&ptr
) == FAIL
)
6434 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6437 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6441 inst
.operands
[i
].reg
= val
;
6442 inst
.operands
[i
].isreg
= 1;
6443 inst
.operands
[i
].isvec
= 1;
6444 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6445 inst
.operands
[i
].vectype
= optype
;
6446 inst
.operands
[i
].present
= 1;
6448 if (rtype
== REG_TYPE_VFS
)
6452 if (skip_past_comma (&ptr
) == FAIL
)
6454 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6457 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6460 inst
.operands
[i
].reg
= val
;
6461 inst
.operands
[i
].isreg
= 1;
6462 inst
.operands
[i
].isvec
= 1;
6463 inst
.operands
[i
].issingle
= 1;
6464 inst
.operands
[i
].vectype
= optype
;
6465 inst
.operands
[i
].present
= 1;
6468 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6472 inst
.operands
[i
].reg
= val
;
6473 inst
.operands
[i
].isreg
= 1;
6474 inst
.operands
[i
].isvec
= 1;
6475 inst
.operands
[i
].issingle
= 1;
6476 inst
.operands
[i
].vectype
= optype
;
6477 inst
.operands
[i
].present
= 1;
6482 first_error (_("parse error"));
6486 /* Successfully parsed the operands. Update args. */
6492 first_error (_("expected comma"));
6496 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6500 /* Use this macro when the operand constraints are different
6501 for ARM and THUMB (e.g. ldrd). */
6502 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6503 ((arm_operand) | ((thumb_operand) << 16))
6505 /* Matcher codes for parse_operands. */
6506 enum operand_parse_code
6508 OP_stop
, /* end of line */
6510 OP_RR
, /* ARM register */
6511 OP_RRnpc
, /* ARM register, not r15 */
6512 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6513 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6514 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6515 optional trailing ! */
6516 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6517 OP_RCP
, /* Coprocessor number */
6518 OP_RCN
, /* Coprocessor register */
6519 OP_RF
, /* FPA register */
6520 OP_RVS
, /* VFP single precision register */
6521 OP_RVD
, /* VFP double precision register (0..15) */
6522 OP_RND
, /* Neon double precision register (0..31) */
6523 OP_RNQ
, /* Neon quad precision register */
6524 OP_RVSD
, /* VFP single or double precision register */
6525 OP_RNSD
, /* Neon single or double precision register */
6526 OP_RNDQ
, /* Neon double or quad precision register */
6527 OP_RNSDQ
, /* Neon single, double or quad precision register */
6528 OP_RNSC
, /* Neon scalar D[X] */
6529 OP_RVC
, /* VFP control register */
6530 OP_RMF
, /* Maverick F register */
6531 OP_RMD
, /* Maverick D register */
6532 OP_RMFX
, /* Maverick FX register */
6533 OP_RMDX
, /* Maverick DX register */
6534 OP_RMAX
, /* Maverick AX register */
6535 OP_RMDS
, /* Maverick DSPSC register */
6536 OP_RIWR
, /* iWMMXt wR register */
6537 OP_RIWC
, /* iWMMXt wC register */
6538 OP_RIWG
, /* iWMMXt wCG register */
6539 OP_RXA
, /* XScale accumulator register */
6541 OP_REGLST
, /* ARM register list */
6542 OP_VRSLST
, /* VFP single-precision register list */
6543 OP_VRDLST
, /* VFP double-precision register list */
6544 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6545 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6546 OP_NSTRLST
, /* Neon element/structure list */
6548 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6549 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6550 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6551 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6552 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6553 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6554 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6555 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6556 OP_VMOV
, /* Neon VMOV operands. */
6557 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6558 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6559 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6561 OP_I0
, /* immediate zero */
6562 OP_I7
, /* immediate value 0 .. 7 */
6563 OP_I15
, /* 0 .. 15 */
6564 OP_I16
, /* 1 .. 16 */
6565 OP_I16z
, /* 0 .. 16 */
6566 OP_I31
, /* 0 .. 31 */
6567 OP_I31w
, /* 0 .. 31, optional trailing ! */
6568 OP_I32
, /* 1 .. 32 */
6569 OP_I32z
, /* 0 .. 32 */
6570 OP_I63
, /* 0 .. 63 */
6571 OP_I63s
, /* -64 .. 63 */
6572 OP_I64
, /* 1 .. 64 */
6573 OP_I64z
, /* 0 .. 64 */
6574 OP_I255
, /* 0 .. 255 */
6576 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6577 OP_I7b
, /* 0 .. 7 */
6578 OP_I15b
, /* 0 .. 15 */
6579 OP_I31b
, /* 0 .. 31 */
6581 OP_SH
, /* shifter operand */
6582 OP_SHG
, /* shifter operand with possible group relocation */
6583 OP_ADDR
, /* Memory address expression (any mode) */
6584 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6585 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6586 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6587 OP_EXP
, /* arbitrary expression */
6588 OP_EXPi
, /* same, with optional immediate prefix */
6589 OP_EXPr
, /* same, with optional relocation suffix */
6590 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6591 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6592 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6594 OP_CPSF
, /* CPS flags */
6595 OP_ENDI
, /* Endianness specifier */
6596 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6597 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6598 OP_COND
, /* conditional code */
6599 OP_TB
, /* Table branch. */
6601 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6603 OP_RRnpc_I0
, /* ARM register or literal 0 */
6604 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6605 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6606 OP_RF_IF
, /* FPA register or immediate */
6607 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6608 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6610 /* Optional operands. */
6611 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6612 OP_oI31b
, /* 0 .. 31 */
6613 OP_oI32b
, /* 1 .. 32 */
6614 OP_oI32z
, /* 0 .. 32 */
6615 OP_oIffffb
, /* 0 .. 65535 */
6616 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6618 OP_oRR
, /* ARM register */
6619 OP_oRRnpc
, /* ARM register, not the PC */
6620 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6621 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6622 OP_oRND
, /* Optional Neon double precision register */
6623 OP_oRNQ
, /* Optional Neon quad precision register */
6624 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6625 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6626 OP_oSHll
, /* LSL immediate */
6627 OP_oSHar
, /* ASR immediate */
6628 OP_oSHllar
, /* LSL or ASR immediate */
6629 OP_oROR
, /* ROR 0/8/16/24 */
6630 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6632 /* Some pre-defined mixed (ARM/THUMB) operands. */
6633 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6634 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6635 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6637 OP_FIRST_OPTIONAL
= OP_oI7b
6640 /* Generic instruction operand parser. This does no encoding and no
6641 semantic validation; it merely squirrels values away in the inst
6642 structure. Returns SUCCESS or FAIL depending on whether the
6643 specified grammar matched. */
6645 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6647 unsigned const int *upat
= pattern
;
6648 char *backtrack_pos
= 0;
6649 const char *backtrack_error
= 0;
6650 int i
, val
= 0, backtrack_index
= 0;
6651 enum arm_reg_type rtype
;
6652 parse_operand_result result
;
6653 unsigned int op_parse_code
;
6655 #define po_char_or_fail(chr) \
6658 if (skip_past_char (&str, chr) == FAIL) \
6663 #define po_reg_or_fail(regtype) \
6666 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6667 & inst.operands[i].vectype); \
6670 first_error (_(reg_expected_msgs[regtype])); \
6673 inst.operands[i].reg = val; \
6674 inst.operands[i].isreg = 1; \
6675 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6676 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6677 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6678 || rtype == REG_TYPE_VFD \
6679 || rtype == REG_TYPE_NQ); \
6683 #define po_reg_or_goto(regtype, label) \
6686 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6687 & inst.operands[i].vectype); \
6691 inst.operands[i].reg = val; \
6692 inst.operands[i].isreg = 1; \
6693 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6694 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6695 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6696 || rtype == REG_TYPE_VFD \
6697 || rtype == REG_TYPE_NQ); \
6701 #define po_imm_or_fail(min, max, popt) \
6704 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6706 inst.operands[i].imm = val; \
6710 #define po_scalar_or_goto(elsz, label) \
6713 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6716 inst.operands[i].reg = val; \
6717 inst.operands[i].isscalar = 1; \
6721 #define po_misc_or_fail(expr) \
6729 #define po_misc_or_fail_no_backtrack(expr) \
6733 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6734 backtrack_pos = 0; \
6735 if (result != PARSE_OPERAND_SUCCESS) \
6740 #define po_barrier_or_imm(str) \
6743 val = parse_barrier (&str); \
6744 if (val == FAIL && ! ISALPHA (*str)) \
6747 /* ISB can only take SY as an option. */ \
6748 || ((inst.instruction & 0xf0) == 0x60 \
6751 inst.error = _("invalid barrier type"); \
6752 backtrack_pos = 0; \
6758 skip_whitespace (str
);
6760 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6762 op_parse_code
= upat
[i
];
6763 if (op_parse_code
>= 1<<16)
6764 op_parse_code
= thumb
? (op_parse_code
>> 16)
6765 : (op_parse_code
& ((1<<16)-1));
6767 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6769 /* Remember where we are in case we need to backtrack. */
6770 gas_assert (!backtrack_pos
);
6771 backtrack_pos
= str
;
6772 backtrack_error
= inst
.error
;
6773 backtrack_index
= i
;
6776 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6777 po_char_or_fail (',');
6779 switch (op_parse_code
)
6787 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6788 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6789 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6790 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6791 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6792 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6794 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6796 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6798 /* Also accept generic coprocessor regs for unknown registers. */
6800 po_reg_or_fail (REG_TYPE_CN
);
6802 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6803 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6804 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6805 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6806 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6807 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6808 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6809 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6810 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6811 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6813 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6814 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6816 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6817 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6819 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6821 /* Neon scalar. Using an element size of 8 means that some invalid
6822 scalars are accepted here, so deal with those in later code. */
6823 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6827 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6830 po_imm_or_fail (0, 0, TRUE
);
6835 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6840 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6843 if (parse_ifimm_zero (&str
))
6844 inst
.operands
[i
].imm
= 0;
6848 = _("only floating point zero is allowed as immediate value");
6856 po_scalar_or_goto (8, try_rr
);
6859 po_reg_or_fail (REG_TYPE_RN
);
6865 po_scalar_or_goto (8, try_nsdq
);
6868 po_reg_or_fail (REG_TYPE_NSDQ
);
6874 po_scalar_or_goto (8, try_s_scalar
);
6877 po_scalar_or_goto (4, try_nsd
);
6880 po_reg_or_fail (REG_TYPE_NSD
);
6886 po_scalar_or_goto (8, try_ndq
);
6889 po_reg_or_fail (REG_TYPE_NDQ
);
6895 po_scalar_or_goto (8, try_vfd
);
6898 po_reg_or_fail (REG_TYPE_VFD
);
6903 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6904 not careful then bad things might happen. */
6905 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6910 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6913 /* There's a possibility of getting a 64-bit immediate here, so
6914 we need special handling. */
6915 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6918 inst
.error
= _("immediate value is out of range");
6926 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6929 po_imm_or_fail (0, 63, TRUE
);
6934 po_char_or_fail ('[');
6935 po_reg_or_fail (REG_TYPE_RN
);
6936 po_char_or_fail (']');
6942 po_reg_or_fail (REG_TYPE_RN
);
6943 if (skip_past_char (&str
, '!') == SUCCESS
)
6944 inst
.operands
[i
].writeback
= 1;
6948 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6949 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6950 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6951 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6952 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6953 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6954 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6955 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6956 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6957 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6958 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6959 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6961 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6963 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6964 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6966 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6967 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6968 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6969 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6971 /* Immediate variants */
6973 po_char_or_fail ('{');
6974 po_imm_or_fail (0, 255, TRUE
);
6975 po_char_or_fail ('}');
6979 /* The expression parser chokes on a trailing !, so we have
6980 to find it first and zap it. */
6983 while (*s
&& *s
!= ',')
6988 inst
.operands
[i
].writeback
= 1;
6990 po_imm_or_fail (0, 31, TRUE
);
6998 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7003 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7008 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7010 if (inst
.reloc
.exp
.X_op
== O_symbol
)
7012 val
= parse_reloc (&str
);
7015 inst
.error
= _("unrecognized relocation suffix");
7018 else if (val
!= BFD_RELOC_UNUSED
)
7020 inst
.operands
[i
].imm
= val
;
7021 inst
.operands
[i
].hasreloc
= 1;
7026 /* Operand for MOVW or MOVT. */
7028 po_misc_or_fail (parse_half (&str
));
7031 /* Register or expression. */
7032 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7033 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7035 /* Register or immediate. */
7036 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7037 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7039 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7041 if (!is_immediate_prefix (*str
))
7044 val
= parse_fpa_immediate (&str
);
7047 /* FPA immediates are encoded as registers 8-15.
7048 parse_fpa_immediate has already applied the offset. */
7049 inst
.operands
[i
].reg
= val
;
7050 inst
.operands
[i
].isreg
= 1;
7053 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7054 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7056 /* Two kinds of register. */
7059 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7061 || (rege
->type
!= REG_TYPE_MMXWR
7062 && rege
->type
!= REG_TYPE_MMXWC
7063 && rege
->type
!= REG_TYPE_MMXWCG
))
7065 inst
.error
= _("iWMMXt data or control register expected");
7068 inst
.operands
[i
].reg
= rege
->number
;
7069 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7075 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7077 || (rege
->type
!= REG_TYPE_MMXWC
7078 && rege
->type
!= REG_TYPE_MMXWCG
))
7080 inst
.error
= _("iWMMXt control register expected");
7083 inst
.operands
[i
].reg
= rege
->number
;
7084 inst
.operands
[i
].isreg
= 1;
7089 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7090 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7091 case OP_oROR
: val
= parse_ror (&str
); break;
7092 case OP_COND
: val
= parse_cond (&str
); break;
7093 case OP_oBARRIER_I15
:
7094 po_barrier_or_imm (str
); break;
7096 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7102 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7103 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7105 inst
.error
= _("Banked registers are not available with this "
7111 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7115 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7118 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7120 if (strncasecmp (str
, "APSR_", 5) == 0)
7127 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7128 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7129 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7130 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7131 default: found
= 16;
7135 inst
.operands
[i
].isvec
= 1;
7136 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7137 inst
.operands
[i
].reg
= REG_PC
;
7144 po_misc_or_fail (parse_tb (&str
));
7147 /* Register lists. */
7149 val
= parse_reg_list (&str
);
7152 inst
.operands
[i
].writeback
= 1;
7158 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7162 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7166 /* Allow Q registers too. */
7167 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7172 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7174 inst
.operands
[i
].issingle
= 1;
7179 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7184 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7185 &inst
.operands
[i
].vectype
);
7188 /* Addressing modes */
7190 po_misc_or_fail (parse_address (&str
, i
));
7194 po_misc_or_fail_no_backtrack (
7195 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7199 po_misc_or_fail_no_backtrack (
7200 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7204 po_misc_or_fail_no_backtrack (
7205 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7209 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7213 po_misc_or_fail_no_backtrack (
7214 parse_shifter_operand_group_reloc (&str
, i
));
7218 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7222 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7226 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7230 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7233 /* Various value-based sanity checks and shared operations. We
7234 do not signal immediate failures for the register constraints;
7235 this allows a syntax error to take precedence. */
7236 switch (op_parse_code
)
7244 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7245 inst
.error
= BAD_PC
;
7250 if (inst
.operands
[i
].isreg
)
7252 if (inst
.operands
[i
].reg
== REG_PC
)
7253 inst
.error
= BAD_PC
;
7254 else if (inst
.operands
[i
].reg
== REG_SP
7255 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7256 relaxed since ARMv8-A. */
7257 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7260 inst
.error
= BAD_SP
;
7266 if (inst
.operands
[i
].isreg
7267 && inst
.operands
[i
].reg
== REG_PC
7268 && (inst
.operands
[i
].writeback
|| thumb
))
7269 inst
.error
= BAD_PC
;
7278 case OP_oBARRIER_I15
:
7287 inst
.operands
[i
].imm
= val
;
7294 /* If we get here, this operand was successfully parsed. */
7295 inst
.operands
[i
].present
= 1;
7299 inst
.error
= BAD_ARGS
;
7304 /* The parse routine should already have set inst.error, but set a
7305 default here just in case. */
7307 inst
.error
= _("syntax error");
7311 /* Do not backtrack over a trailing optional argument that
7312 absorbed some text. We will only fail again, with the
7313 'garbage following instruction' error message, which is
7314 probably less helpful than the current one. */
7315 if (backtrack_index
== i
&& backtrack_pos
!= str
7316 && upat
[i
+1] == OP_stop
)
7319 inst
.error
= _("syntax error");
7323 /* Try again, skipping the optional argument at backtrack_pos. */
7324 str
= backtrack_pos
;
7325 inst
.error
= backtrack_error
;
7326 inst
.operands
[backtrack_index
].present
= 0;
7327 i
= backtrack_index
;
7331 /* Check that we have parsed all the arguments. */
7332 if (*str
!= '\0' && !inst
.error
)
7333 inst
.error
= _("garbage following instruction");
7335 return inst
.error
? FAIL
: SUCCESS
;
7338 #undef po_char_or_fail
7339 #undef po_reg_or_fail
7340 #undef po_reg_or_goto
7341 #undef po_imm_or_fail
7342 #undef po_scalar_or_fail
7343 #undef po_barrier_or_imm
7345 /* Shorthand macro for instruction encoding functions issuing errors. */
7346 #define constraint(expr, err) \
7357 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7358 instructions are unpredictable if these registers are used. This
7359 is the BadReg predicate in ARM's Thumb-2 documentation.
7361 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7362 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7363 #define reject_bad_reg(reg) \
7365 if (reg == REG_PC) \
7367 inst.error = BAD_PC; \
7370 else if (reg == REG_SP \
7371 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7373 inst.error = BAD_SP; \
7378 /* If REG is R13 (the stack pointer), warn that its use is
7380 #define warn_deprecated_sp(reg) \
7382 if (warn_on_deprecated && reg == REG_SP) \
7383 as_tsktsk (_("use of r13 is deprecated")); \
7386 /* Functions for operand encoding. ARM, then Thumb. */
7388 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7390 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7392 The only binary encoding difference is the Coprocessor number. Coprocessor
7393 9 is used for half-precision calculations or conversions. The format of the
7394 instruction is the same as the equivalent Coprocessor 10 instruction that
7395 exists for Single-Precision operation. */
7398 do_scalar_fp16_v82_encode (void)
7400 if (inst
.cond
!= COND_ALWAYS
)
7401 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7402 " the behaviour is UNPREDICTABLE"));
7403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7406 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7407 mark_feature_used (&arm_ext_fp16
);
7410 /* If VAL can be encoded in the immediate field of an ARM instruction,
7411 return the encoded form. Otherwise, return FAIL. */
7414 encode_arm_immediate (unsigned int val
)
7421 for (i
= 2; i
< 32; i
+= 2)
7422 if ((a
= rotate_left (val
, i
)) <= 0xff)
7423 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7428 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7429 return the encoded form. Otherwise, return FAIL. */
7431 encode_thumb32_immediate (unsigned int val
)
7438 for (i
= 1; i
<= 24; i
++)
7441 if ((val
& ~(0xff << i
)) == 0)
7442 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7446 if (val
== ((a
<< 16) | a
))
7448 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7452 if (val
== ((a
<< 16) | a
))
7453 return 0x200 | (a
>> 8);
7457 /* Encode a VFP SP or DP register number into inst.instruction. */
7460 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7462 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7465 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7468 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7471 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7476 first_error (_("D register out of range for selected VFP version"));
7484 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7488 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7492 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7496 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7500 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7504 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7512 /* Encode a <shift> in an ARM-format instruction. The immediate,
7513 if any, is handled by md_apply_fix. */
7515 encode_arm_shift (int i
)
7517 /* register-shifted register. */
7518 if (inst
.operands
[i
].immisreg
)
7521 for (op_index
= 0; op_index
<= i
; ++op_index
)
7523 /* Check the operand only when it's presented. In pre-UAL syntax,
7524 if the destination register is the same as the first operand, two
7525 register form of the instruction can be used. */
7526 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7527 && inst
.operands
[op_index
].reg
== REG_PC
)
7528 as_warn (UNPRED_REG ("r15"));
7531 if (inst
.operands
[i
].imm
== REG_PC
)
7532 as_warn (UNPRED_REG ("r15"));
7535 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7536 inst
.instruction
|= SHIFT_ROR
<< 5;
7539 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7540 if (inst
.operands
[i
].immisreg
)
7542 inst
.instruction
|= SHIFT_BY_REG
;
7543 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7546 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7551 encode_arm_shifter_operand (int i
)
7553 if (inst
.operands
[i
].isreg
)
7555 inst
.instruction
|= inst
.operands
[i
].reg
;
7556 encode_arm_shift (i
);
7560 inst
.instruction
|= INST_IMMEDIATE
;
7561 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7562 inst
.instruction
|= inst
.operands
[i
].imm
;
7566 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7568 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7571 Generate an error if the operand is not a register. */
7572 constraint (!inst
.operands
[i
].isreg
,
7573 _("Instruction does not support =N addresses"));
7575 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7577 if (inst
.operands
[i
].preind
)
7581 inst
.error
= _("instruction does not accept preindexed addressing");
7584 inst
.instruction
|= PRE_INDEX
;
7585 if (inst
.operands
[i
].writeback
)
7586 inst
.instruction
|= WRITE_BACK
;
7589 else if (inst
.operands
[i
].postind
)
7591 gas_assert (inst
.operands
[i
].writeback
);
7593 inst
.instruction
|= WRITE_BACK
;
7595 else /* unindexed - only for coprocessor */
7597 inst
.error
= _("instruction does not accept unindexed addressing");
7601 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7602 && (((inst
.instruction
& 0x000f0000) >> 16)
7603 == ((inst
.instruction
& 0x0000f000) >> 12)))
7604 as_warn ((inst
.instruction
& LOAD_BIT
)
7605 ? _("destination register same as write-back base")
7606 : _("source register same as write-back base"));
7609 /* inst.operands[i] was set up by parse_address. Encode it into an
7610 ARM-format mode 2 load or store instruction. If is_t is true,
7611 reject forms that cannot be used with a T instruction (i.e. not
7614 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7616 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7618 encode_arm_addr_mode_common (i
, is_t
);
7620 if (inst
.operands
[i
].immisreg
)
7622 constraint ((inst
.operands
[i
].imm
== REG_PC
7623 || (is_pc
&& inst
.operands
[i
].writeback
)),
7625 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7626 inst
.instruction
|= inst
.operands
[i
].imm
;
7627 if (!inst
.operands
[i
].negative
)
7628 inst
.instruction
|= INDEX_UP
;
7629 if (inst
.operands
[i
].shifted
)
7631 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7632 inst
.instruction
|= SHIFT_ROR
<< 5;
7635 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7636 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7640 else /* immediate offset in inst.reloc */
7642 if (is_pc
&& !inst
.reloc
.pc_rel
)
7644 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7646 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7647 cannot use PC in addressing.
7648 PC cannot be used in writeback addressing, either. */
7649 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7652 /* Use of PC in str is deprecated for ARMv7. */
7653 if (warn_on_deprecated
7655 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7656 as_tsktsk (_("use of PC in this instruction is deprecated"));
7659 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7661 /* Prefer + for zero encoded value. */
7662 if (!inst
.operands
[i
].negative
)
7663 inst
.instruction
|= INDEX_UP
;
7664 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7669 /* inst.operands[i] was set up by parse_address. Encode it into an
7670 ARM-format mode 3 load or store instruction. Reject forms that
7671 cannot be used with such instructions. If is_t is true, reject
7672 forms that cannot be used with a T instruction (i.e. not
7675 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7677 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7679 inst
.error
= _("instruction does not accept scaled register index");
7683 encode_arm_addr_mode_common (i
, is_t
);
7685 if (inst
.operands
[i
].immisreg
)
7687 constraint ((inst
.operands
[i
].imm
== REG_PC
7688 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7690 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7692 inst
.instruction
|= inst
.operands
[i
].imm
;
7693 if (!inst
.operands
[i
].negative
)
7694 inst
.instruction
|= INDEX_UP
;
7696 else /* immediate offset in inst.reloc */
7698 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7699 && inst
.operands
[i
].writeback
),
7701 inst
.instruction
|= HWOFFSET_IMM
;
7702 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7704 /* Prefer + for zero encoded value. */
7705 if (!inst
.operands
[i
].negative
)
7706 inst
.instruction
|= INDEX_UP
;
7708 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7713 /* Write immediate bits [7:0] to the following locations:
7715 |28/24|23 19|18 16|15 4|3 0|
7716 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7718 This function is used by VMOV/VMVN/VORR/VBIC. */
7721 neon_write_immbits (unsigned immbits
)
7723 inst
.instruction
|= immbits
& 0xf;
7724 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7725 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7728 /* Invert low-order SIZE bits of XHI:XLO. */
7731 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7733 unsigned immlo
= xlo
? *xlo
: 0;
7734 unsigned immhi
= xhi
? *xhi
: 0;
7739 immlo
= (~immlo
) & 0xff;
7743 immlo
= (~immlo
) & 0xffff;
7747 immhi
= (~immhi
) & 0xffffffff;
7751 immlo
= (~immlo
) & 0xffffffff;
7765 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7769 neon_bits_same_in_bytes (unsigned imm
)
7771 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7772 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7773 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7774 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7777 /* For immediate of above form, return 0bABCD. */
7780 neon_squash_bits (unsigned imm
)
7782 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7783 | ((imm
& 0x01000000) >> 21);
7786 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7789 neon_qfloat_bits (unsigned imm
)
7791 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7794 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7795 the instruction. *OP is passed as the initial value of the op field, and
7796 may be set to a different value depending on the constant (i.e.
7797 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7798 MVN). If the immediate looks like a repeated pattern then also
7799 try smaller element sizes. */
7802 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7803 unsigned *immbits
, int *op
, int size
,
7804 enum neon_el_type type
)
7806 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7808 if (type
== NT_float
&& !float_p
)
7811 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7813 if (size
!= 32 || *op
== 1)
7815 *immbits
= neon_qfloat_bits (immlo
);
7821 if (neon_bits_same_in_bytes (immhi
)
7822 && neon_bits_same_in_bytes (immlo
))
7826 *immbits
= (neon_squash_bits (immhi
) << 4)
7827 | neon_squash_bits (immlo
);
7838 if (immlo
== (immlo
& 0x000000ff))
7843 else if (immlo
== (immlo
& 0x0000ff00))
7845 *immbits
= immlo
>> 8;
7848 else if (immlo
== (immlo
& 0x00ff0000))
7850 *immbits
= immlo
>> 16;
7853 else if (immlo
== (immlo
& 0xff000000))
7855 *immbits
= immlo
>> 24;
7858 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7860 *immbits
= (immlo
>> 8) & 0xff;
7863 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7865 *immbits
= (immlo
>> 16) & 0xff;
7869 if ((immlo
& 0xffff) != (immlo
>> 16))
7876 if (immlo
== (immlo
& 0x000000ff))
7881 else if (immlo
== (immlo
& 0x0000ff00))
7883 *immbits
= immlo
>> 8;
7887 if ((immlo
& 0xff) != (immlo
>> 8))
7892 if (immlo
== (immlo
& 0x000000ff))
7894 /* Don't allow MVN with 8-bit immediate. */
7904 #if defined BFD_HOST_64_BIT
7905 /* Returns TRUE if double precision value V may be cast
7906 to single precision without loss of accuracy. */
7909 is_double_a_single (bfd_int64_t v
)
7911 int exp
= (int)((v
>> 52) & 0x7FF);
7912 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7914 return (exp
== 0 || exp
== 0x7FF
7915 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7916 && (mantissa
& 0x1FFFFFFFl
) == 0;
7919 /* Returns a double precision value casted to single precision
7920 (ignoring the least significant bits in exponent and mantissa). */
7923 double_to_single (bfd_int64_t v
)
7925 int sign
= (int) ((v
>> 63) & 1l);
7926 int exp
= (int) ((v
>> 52) & 0x7FF);
7927 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7933 exp
= exp
- 1023 + 127;
7942 /* No denormalized numbers. */
7948 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7950 #endif /* BFD_HOST_64_BIT */
7959 static void do_vfp_nsyn_opcode (const char *);
7961 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7962 Determine whether it can be performed with a move instruction; if
7963 it can, convert inst.instruction to that move instruction and
7964 return TRUE; if it can't, convert inst.instruction to a literal-pool
7965 load and return FALSE. If this is not a valid thing to do in the
7966 current context, set inst.error and return TRUE.
7968 inst.operands[i] describes the destination register. */
7971 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7974 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7975 bfd_boolean arm_p
= (t
== CONST_ARM
);
7978 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7982 if ((inst
.instruction
& tbit
) == 0)
7984 inst
.error
= _("invalid pseudo operation");
7988 if (inst
.reloc
.exp
.X_op
!= O_constant
7989 && inst
.reloc
.exp
.X_op
!= O_symbol
7990 && inst
.reloc
.exp
.X_op
!= O_big
)
7992 inst
.error
= _("constant expression expected");
7996 if (inst
.reloc
.exp
.X_op
== O_constant
7997 || inst
.reloc
.exp
.X_op
== O_big
)
7999 #if defined BFD_HOST_64_BIT
8004 if (inst
.reloc
.exp
.X_op
== O_big
)
8006 LITTLENUM_TYPE w
[X_PRECISION
];
8009 if (inst
.reloc
.exp
.X_add_number
== -1)
8011 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8013 /* FIXME: Should we check words w[2..5] ? */
8018 #if defined BFD_HOST_64_BIT
8020 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8021 << LITTLENUM_NUMBER_OF_BITS
)
8022 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8023 << LITTLENUM_NUMBER_OF_BITS
)
8024 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8025 << LITTLENUM_NUMBER_OF_BITS
)
8026 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8028 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8029 | (l
[0] & LITTLENUM_MASK
);
8033 v
= inst
.reloc
.exp
.X_add_number
;
8035 if (!inst
.operands
[i
].issingle
)
8039 /* LDR should not use lead in a flag-setting instruction being
8040 chosen so we do not check whether movs can be used. */
8042 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8043 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8044 && inst
.operands
[i
].reg
!= 13
8045 && inst
.operands
[i
].reg
!= 15)
8047 /* Check if on thumb2 it can be done with a mov.w, mvn or
8048 movw instruction. */
8049 unsigned int newimm
;
8050 bfd_boolean isNegated
;
8052 newimm
= encode_thumb32_immediate (v
);
8053 if (newimm
!= (unsigned int) FAIL
)
8057 newimm
= encode_thumb32_immediate (~v
);
8058 if (newimm
!= (unsigned int) FAIL
)
8062 /* The number can be loaded with a mov.w or mvn
8064 if (newimm
!= (unsigned int) FAIL
8065 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8067 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8068 | (inst
.operands
[i
].reg
<< 8));
8069 /* Change to MOVN. */
8070 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8071 inst
.instruction
|= (newimm
& 0x800) << 15;
8072 inst
.instruction
|= (newimm
& 0x700) << 4;
8073 inst
.instruction
|= (newimm
& 0x0ff);
8076 /* The number can be loaded with a movw instruction. */
8077 else if ((v
& ~0xFFFF) == 0
8078 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8080 int imm
= v
& 0xFFFF;
8082 inst
.instruction
= 0xf2400000; /* MOVW. */
8083 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8084 inst
.instruction
|= (imm
& 0xf000) << 4;
8085 inst
.instruction
|= (imm
& 0x0800) << 15;
8086 inst
.instruction
|= (imm
& 0x0700) << 4;
8087 inst
.instruction
|= (imm
& 0x00ff);
8094 int value
= encode_arm_immediate (v
);
8098 /* This can be done with a mov instruction. */
8099 inst
.instruction
&= LITERAL_MASK
;
8100 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8101 inst
.instruction
|= value
& 0xfff;
8105 value
= encode_arm_immediate (~ v
);
8108 /* This can be done with a mvn instruction. */
8109 inst
.instruction
&= LITERAL_MASK
;
8110 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8111 inst
.instruction
|= value
& 0xfff;
8115 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8118 unsigned immbits
= 0;
8119 unsigned immlo
= inst
.operands
[1].imm
;
8120 unsigned immhi
= inst
.operands
[1].regisimm
8121 ? inst
.operands
[1].reg
8122 : inst
.reloc
.exp
.X_unsigned
8124 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8125 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8126 &op
, 64, NT_invtype
);
8130 neon_invert_size (&immlo
, &immhi
, 64);
8132 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8133 &op
, 64, NT_invtype
);
8138 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8144 /* Fill other bits in vmov encoding for both thumb and arm. */
8146 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8148 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8149 neon_write_immbits (immbits
);
8157 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8158 if (inst
.operands
[i
].issingle
8159 && is_quarter_float (inst
.operands
[1].imm
)
8160 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8162 inst
.operands
[1].imm
=
8163 neon_qfloat_bits (v
);
8164 do_vfp_nsyn_opcode ("fconsts");
8168 /* If our host does not support a 64-bit type then we cannot perform
8169 the following optimization. This mean that there will be a
8170 discrepancy between the output produced by an assembler built for
8171 a 32-bit-only host and the output produced from a 64-bit host, but
8172 this cannot be helped. */
8173 #if defined BFD_HOST_64_BIT
8174 else if (!inst
.operands
[1].issingle
8175 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8177 if (is_double_a_single (v
)
8178 && is_quarter_float (double_to_single (v
)))
8180 inst
.operands
[1].imm
=
8181 neon_qfloat_bits (double_to_single (v
));
8182 do_vfp_nsyn_opcode ("fconstd");
8190 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8191 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8194 inst
.operands
[1].reg
= REG_PC
;
8195 inst
.operands
[1].isreg
= 1;
8196 inst
.operands
[1].preind
= 1;
8197 inst
.reloc
.pc_rel
= 1;
8198 inst
.reloc
.type
= (thumb_p
8199 ? BFD_RELOC_ARM_THUMB_OFFSET
8201 ? BFD_RELOC_ARM_HWLITERAL
8202 : BFD_RELOC_ARM_LITERAL
));
8206 /* inst.operands[i] was set up by parse_address. Encode it into an
8207 ARM-format instruction. Reject all forms which cannot be encoded
8208 into a coprocessor load/store instruction. If wb_ok is false,
8209 reject use of writeback; if unind_ok is false, reject use of
8210 unindexed addressing. If reloc_override is not 0, use it instead
8211 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8212 (in which case it is preserved). */
8215 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8217 if (!inst
.operands
[i
].isreg
)
8220 if (! inst
.operands
[0].isvec
)
8222 inst
.error
= _("invalid co-processor operand");
8225 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8229 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8231 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8233 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8235 gas_assert (!inst
.operands
[i
].writeback
);
8238 inst
.error
= _("instruction does not support unindexed addressing");
8241 inst
.instruction
|= inst
.operands
[i
].imm
;
8242 inst
.instruction
|= INDEX_UP
;
8246 if (inst
.operands
[i
].preind
)
8247 inst
.instruction
|= PRE_INDEX
;
8249 if (inst
.operands
[i
].writeback
)
8251 if (inst
.operands
[i
].reg
== REG_PC
)
8253 inst
.error
= _("pc may not be used with write-back");
8258 inst
.error
= _("instruction does not support writeback");
8261 inst
.instruction
|= WRITE_BACK
;
8265 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8266 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8267 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8268 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8271 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8273 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8276 /* Prefer + for zero encoded value. */
8277 if (!inst
.operands
[i
].negative
)
8278 inst
.instruction
|= INDEX_UP
;
8283 /* Functions for instruction encoding, sorted by sub-architecture.
8284 First some generics; their names are taken from the conventional
8285 bit positions for register arguments in ARM format instructions. */
8295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8301 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8308 inst
.instruction
|= inst
.operands
[1].reg
;
8314 inst
.instruction
|= inst
.operands
[0].reg
;
8315 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8322 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8328 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8329 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8335 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8340 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8342 if (ARM_CPU_IS_ANY (cpu_variant
))
8344 as_tsktsk ("%s", msg
);
8347 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8359 unsigned Rn
= inst
.operands
[2].reg
;
8360 /* Enforce restrictions on SWP instruction. */
8361 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8363 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8364 _("Rn must not overlap other operands"));
8366 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8368 if (!check_obsolete (&arm_ext_v8
,
8369 _("swp{b} use is obsoleted for ARMv8 and later"))
8370 && warn_on_deprecated
8371 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8372 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8376 inst
.instruction
|= inst
.operands
[1].reg
;
8377 inst
.instruction
|= Rn
<< 16;
8383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8384 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8385 inst
.instruction
|= inst
.operands
[2].reg
;
8391 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8392 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8393 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8394 || inst
.reloc
.exp
.X_add_number
!= 0),
8396 inst
.instruction
|= inst
.operands
[0].reg
;
8397 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8398 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8404 inst
.instruction
|= inst
.operands
[0].imm
;
8410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8411 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8414 /* ARM instructions, in alphabetical order by function name (except
8415 that wrapper functions appear immediately after the function they
8418 /* This is a pseudo-op of the form "adr rd, label" to be converted
8419 into a relative address of the form "add rd, pc, #label-.-8". */
8424 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8426 /* Frag hacking will turn this into a sub instruction if the offset turns
8427 out to be negative. */
8428 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8429 inst
.reloc
.pc_rel
= 1;
8430 inst
.reloc
.exp
.X_add_number
-= 8;
8432 if (support_interwork
8433 && inst
.reloc
.exp
.X_op
== O_symbol
8434 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8435 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8436 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8437 inst
.reloc
.exp
.X_add_number
|= 1;
8440 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8441 into a relative address of the form:
8442 add rd, pc, #low(label-.-8)"
8443 add rd, rd, #high(label-.-8)" */
8448 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8450 /* Frag hacking will turn this into a sub instruction if the offset turns
8451 out to be negative. */
8452 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8453 inst
.reloc
.pc_rel
= 1;
8454 inst
.size
= INSN_SIZE
* 2;
8455 inst
.reloc
.exp
.X_add_number
-= 8;
8457 if (support_interwork
8458 && inst
.reloc
.exp
.X_op
== O_symbol
8459 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8460 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8461 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8462 inst
.reloc
.exp
.X_add_number
|= 1;
8468 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8469 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8471 if (!inst
.operands
[1].present
)
8472 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8474 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8475 encode_arm_shifter_operand (2);
8481 if (inst
.operands
[0].present
)
8482 inst
.instruction
|= inst
.operands
[0].imm
;
8484 inst
.instruction
|= 0xf;
8490 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8491 constraint (msb
> 32, _("bit-field extends past end of register"));
8492 /* The instruction encoding stores the LSB and MSB,
8493 not the LSB and width. */
8494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8495 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8496 inst
.instruction
|= (msb
- 1) << 16;
8504 /* #0 in second position is alternative syntax for bfc, which is
8505 the same instruction but with REG_PC in the Rm field. */
8506 if (!inst
.operands
[1].isreg
)
8507 inst
.operands
[1].reg
= REG_PC
;
8509 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8510 constraint (msb
> 32, _("bit-field extends past end of register"));
8511 /* The instruction encoding stores the LSB and MSB,
8512 not the LSB and width. */
8513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8514 inst
.instruction
|= inst
.operands
[1].reg
;
8515 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8516 inst
.instruction
|= (msb
- 1) << 16;
8522 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8523 _("bit-field extends past end of register"));
8524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8525 inst
.instruction
|= inst
.operands
[1].reg
;
8526 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8527 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8530 /* ARM V5 breakpoint instruction (argument parse)
8531 BKPT <16 bit unsigned immediate>
8532 Instruction is not conditional.
8533 The bit pattern given in insns[] has the COND_ALWAYS condition,
8534 and it is an error if the caller tried to override that. */
8539 /* Top 12 of 16 bits to bits 19:8. */
8540 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8542 /* Bottom 4 of 16 bits to bits 3:0. */
8543 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8547 encode_branch (int default_reloc
)
8549 if (inst
.operands
[0].hasreloc
)
8551 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8552 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8553 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8554 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8555 ? BFD_RELOC_ARM_PLT32
8556 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8559 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8560 inst
.reloc
.pc_rel
= 1;
8567 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8568 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8571 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8578 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8580 if (inst
.cond
== COND_ALWAYS
)
8581 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8583 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8587 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8590 /* ARM V5 branch-link-exchange instruction (argument parse)
8591 BLX <target_addr> ie BLX(1)
8592 BLX{<condition>} <Rm> ie BLX(2)
8593 Unfortunately, there are two different opcodes for this mnemonic.
8594 So, the insns[].value is not used, and the code here zaps values
8595 into inst.instruction.
8596 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8601 if (inst
.operands
[0].isreg
)
8603 /* Arg is a register; the opcode provided by insns[] is correct.
8604 It is not illegal to do "blx pc", just useless. */
8605 if (inst
.operands
[0].reg
== REG_PC
)
8606 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8608 inst
.instruction
|= inst
.operands
[0].reg
;
8612 /* Arg is an address; this instruction cannot be executed
8613 conditionally, and the opcode must be adjusted.
8614 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8615 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8616 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8617 inst
.instruction
= 0xfa000000;
8618 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8625 bfd_boolean want_reloc
;
8627 if (inst
.operands
[0].reg
== REG_PC
)
8628 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8630 inst
.instruction
|= inst
.operands
[0].reg
;
8631 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8632 it is for ARMv4t or earlier. */
8633 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8634 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8635 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8639 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8644 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8648 /* ARM v5TEJ. Jump to Jazelle code. */
8653 if (inst
.operands
[0].reg
== REG_PC
)
8654 as_tsktsk (_("use of r15 in bxj is not really useful"));
8656 inst
.instruction
|= inst
.operands
[0].reg
;
8659 /* Co-processor data operation:
8660 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8661 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8665 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8666 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8667 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8668 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8669 inst
.instruction
|= inst
.operands
[4].reg
;
8670 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8676 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8677 encode_arm_shifter_operand (1);
8680 /* Transfer between coprocessor and ARM registers.
8681 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8686 No special properties. */
8688 struct deprecated_coproc_regs_s
8695 arm_feature_set deprecated
;
8696 arm_feature_set obsoleted
;
8697 const char *dep_msg
;
8698 const char *obs_msg
;
8701 #define DEPR_ACCESS_V8 \
8702 N_("This coprocessor register access is deprecated in ARMv8")
8704 /* Table of all deprecated coprocessor registers. */
8705 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8707 {15, 0, 7, 10, 5, /* CP15DMB. */
8708 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8709 DEPR_ACCESS_V8
, NULL
},
8710 {15, 0, 7, 10, 4, /* CP15DSB. */
8711 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8712 DEPR_ACCESS_V8
, NULL
},
8713 {15, 0, 7, 5, 4, /* CP15ISB. */
8714 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8715 DEPR_ACCESS_V8
, NULL
},
8716 {14, 6, 1, 0, 0, /* TEEHBR. */
8717 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8718 DEPR_ACCESS_V8
, NULL
},
8719 {14, 6, 0, 0, 0, /* TEECR. */
8720 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8721 DEPR_ACCESS_V8
, NULL
},
8724 #undef DEPR_ACCESS_V8
8726 static const size_t deprecated_coproc_reg_count
=
8727 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8735 Rd
= inst
.operands
[2].reg
;
8738 if (inst
.instruction
== 0xee000010
8739 || inst
.instruction
== 0xfe000010)
8741 reject_bad_reg (Rd
);
8742 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8744 constraint (Rd
== REG_SP
, BAD_SP
);
8749 if (inst
.instruction
== 0xe000010)
8750 constraint (Rd
== REG_PC
, BAD_PC
);
8753 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8755 const struct deprecated_coproc_regs_s
*r
=
8756 deprecated_coproc_regs
+ i
;
8758 if (inst
.operands
[0].reg
== r
->cp
8759 && inst
.operands
[1].imm
== r
->opc1
8760 && inst
.operands
[3].reg
== r
->crn
8761 && inst
.operands
[4].reg
== r
->crm
8762 && inst
.operands
[5].imm
== r
->opc2
)
8764 if (! ARM_CPU_IS_ANY (cpu_variant
)
8765 && warn_on_deprecated
8766 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8767 as_tsktsk ("%s", r
->dep_msg
);
8771 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8772 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8773 inst
.instruction
|= Rd
<< 12;
8774 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8775 inst
.instruction
|= inst
.operands
[4].reg
;
8776 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8779 /* Transfer between coprocessor register and pair of ARM registers.
8780 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8785 Two XScale instructions are special cases of these:
8787 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8788 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8790 Result unpredictable if Rd or Rn is R15. */
8797 Rd
= inst
.operands
[2].reg
;
8798 Rn
= inst
.operands
[3].reg
;
8802 reject_bad_reg (Rd
);
8803 reject_bad_reg (Rn
);
8807 constraint (Rd
== REG_PC
, BAD_PC
);
8808 constraint (Rn
== REG_PC
, BAD_PC
);
8811 /* Only check the MRRC{2} variants. */
8812 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8814 /* If Rd == Rn, error that the operation is
8815 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8816 constraint (Rd
== Rn
, BAD_OVERLAP
);
8819 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8820 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8821 inst
.instruction
|= Rd
<< 12;
8822 inst
.instruction
|= Rn
<< 16;
8823 inst
.instruction
|= inst
.operands
[4].reg
;
8829 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8830 if (inst
.operands
[1].present
)
8832 inst
.instruction
|= CPSI_MMOD
;
8833 inst
.instruction
|= inst
.operands
[1].imm
;
8840 inst
.instruction
|= inst
.operands
[0].imm
;
8846 unsigned Rd
, Rn
, Rm
;
8848 Rd
= inst
.operands
[0].reg
;
8849 Rn
= (inst
.operands
[1].present
8850 ? inst
.operands
[1].reg
: Rd
);
8851 Rm
= inst
.operands
[2].reg
;
8853 constraint ((Rd
== REG_PC
), BAD_PC
);
8854 constraint ((Rn
== REG_PC
), BAD_PC
);
8855 constraint ((Rm
== REG_PC
), BAD_PC
);
8857 inst
.instruction
|= Rd
<< 16;
8858 inst
.instruction
|= Rn
<< 0;
8859 inst
.instruction
|= Rm
<< 8;
8865 /* There is no IT instruction in ARM mode. We
8866 process it to do the validation as if in
8867 thumb mode, just in case the code gets
8868 assembled for thumb using the unified syntax. */
8873 set_it_insn_type (IT_INSN
);
8874 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8875 now_it
.cc
= inst
.operands
[0].imm
;
8879 /* If there is only one register in the register list,
8880 then return its register number. Otherwise return -1. */
8882 only_one_reg_in_list (int range
)
8884 int i
= ffs (range
) - 1;
8885 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8889 encode_ldmstm(int from_push_pop_mnem
)
8891 int base_reg
= inst
.operands
[0].reg
;
8892 int range
= inst
.operands
[1].imm
;
8895 inst
.instruction
|= base_reg
<< 16;
8896 inst
.instruction
|= range
;
8898 if (inst
.operands
[1].writeback
)
8899 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8901 if (inst
.operands
[0].writeback
)
8903 inst
.instruction
|= WRITE_BACK
;
8904 /* Check for unpredictable uses of writeback. */
8905 if (inst
.instruction
& LOAD_BIT
)
8907 /* Not allowed in LDM type 2. */
8908 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8909 && ((range
& (1 << REG_PC
)) == 0))
8910 as_warn (_("writeback of base register is UNPREDICTABLE"));
8911 /* Only allowed if base reg not in list for other types. */
8912 else if (range
& (1 << base_reg
))
8913 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8917 /* Not allowed for type 2. */
8918 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8919 as_warn (_("writeback of base register is UNPREDICTABLE"));
8920 /* Only allowed if base reg not in list, or first in list. */
8921 else if ((range
& (1 << base_reg
))
8922 && (range
& ((1 << base_reg
) - 1)))
8923 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8927 /* If PUSH/POP has only one register, then use the A2 encoding. */
8928 one_reg
= only_one_reg_in_list (range
);
8929 if (from_push_pop_mnem
&& one_reg
>= 0)
8931 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8933 if (is_push
&& one_reg
== 13 /* SP */)
8934 /* PR 22483: The A2 encoding cannot be used when
8935 pushing the stack pointer as this is UNPREDICTABLE. */
8938 inst
.instruction
&= A_COND_MASK
;
8939 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8940 inst
.instruction
|= one_reg
<< 12;
8947 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8950 /* ARMv5TE load-consecutive (argument parse)
8959 constraint (inst
.operands
[0].reg
% 2 != 0,
8960 _("first transfer register must be even"));
8961 constraint (inst
.operands
[1].present
8962 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8963 _("can only transfer two consecutive registers"));
8964 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8965 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8967 if (!inst
.operands
[1].present
)
8968 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8970 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8971 register and the first register written; we have to diagnose
8972 overlap between the base and the second register written here. */
8974 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8975 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8976 as_warn (_("base register written back, and overlaps "
8977 "second transfer register"));
8979 if (!(inst
.instruction
& V4_STR_BIT
))
8981 /* For an index-register load, the index register must not overlap the
8982 destination (even if not write-back). */
8983 if (inst
.operands
[2].immisreg
8984 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8985 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8986 as_warn (_("index register overlaps transfer register"));
8988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8989 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8995 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8996 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8997 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8998 || inst
.operands
[1].negative
8999 /* This can arise if the programmer has written
9001 or if they have mistakenly used a register name as the last
9004 It is very difficult to distinguish between these two cases
9005 because "rX" might actually be a label. ie the register
9006 name has been occluded by a symbol of the same name. So we
9007 just generate a general 'bad addressing mode' type error
9008 message and leave it up to the programmer to discover the
9009 true cause and fix their mistake. */
9010 || (inst
.operands
[1].reg
== REG_PC
),
9013 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9014 || inst
.reloc
.exp
.X_add_number
!= 0,
9015 _("offset must be zero in ARM encoding"));
9017 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9021 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9027 constraint (inst
.operands
[0].reg
% 2 != 0,
9028 _("even register required"));
9029 constraint (inst
.operands
[1].present
9030 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9031 _("can only load two consecutive registers"));
9032 /* If op 1 were present and equal to PC, this function wouldn't
9033 have been called in the first place. */
9034 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9036 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9037 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9040 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9041 which is not a multiple of four is UNPREDICTABLE. */
9043 check_ldr_r15_aligned (void)
9045 constraint (!(inst
.operands
[1].immisreg
)
9046 && (inst
.operands
[0].reg
== REG_PC
9047 && inst
.operands
[1].reg
== REG_PC
9048 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9049 _("ldr to register 15 must be 4-byte aligned"));
9055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9056 if (!inst
.operands
[1].isreg
)
9057 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9059 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9060 check_ldr_r15_aligned ();
9066 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9068 if (inst
.operands
[1].preind
)
9070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9071 || inst
.reloc
.exp
.X_add_number
!= 0,
9072 _("this instruction requires a post-indexed address"));
9074 inst
.operands
[1].preind
= 0;
9075 inst
.operands
[1].postind
= 1;
9076 inst
.operands
[1].writeback
= 1;
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9082 /* Halfword and signed-byte load/store operations. */
9087 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9089 if (!inst
.operands
[1].isreg
)
9090 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9092 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9098 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9100 if (inst
.operands
[1].preind
)
9102 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9103 || inst
.reloc
.exp
.X_add_number
!= 0,
9104 _("this instruction requires a post-indexed address"));
9106 inst
.operands
[1].preind
= 0;
9107 inst
.operands
[1].postind
= 1;
9108 inst
.operands
[1].writeback
= 1;
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9111 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9114 /* Co-processor register load/store.
9115 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9119 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9120 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9121 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9127 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9128 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9129 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9130 && !(inst
.instruction
& 0x00400000))
9131 as_tsktsk (_("Rd and Rm should be different in mla"));
9133 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9134 inst
.instruction
|= inst
.operands
[1].reg
;
9135 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9136 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9142 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9143 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9146 encode_arm_shifter_operand (1);
9149 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9156 top
= (inst
.instruction
& 0x00400000) != 0;
9157 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9158 _(":lower16: not allowed in this instruction"));
9159 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9160 _(":upper16: not allowed in this instruction"));
9161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9162 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9164 imm
= inst
.reloc
.exp
.X_add_number
;
9165 /* The value is in two pieces: 0:11, 16:19. */
9166 inst
.instruction
|= (imm
& 0x00000fff);
9167 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9172 do_vfp_nsyn_mrs (void)
9174 if (inst
.operands
[0].isvec
)
9176 if (inst
.operands
[1].reg
!= 1)
9177 first_error (_("operand 1 must be FPSCR"));
9178 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9179 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9180 do_vfp_nsyn_opcode ("fmstat");
9182 else if (inst
.operands
[1].isvec
)
9183 do_vfp_nsyn_opcode ("fmrx");
9191 do_vfp_nsyn_msr (void)
9193 if (inst
.operands
[0].isvec
)
9194 do_vfp_nsyn_opcode ("fmxr");
9204 unsigned Rt
= inst
.operands
[0].reg
;
9206 if (thumb_mode
&& Rt
== REG_SP
)
9208 inst
.error
= BAD_SP
;
9212 /* MVFR2 is only valid at ARMv8-A. */
9213 if (inst
.operands
[1].reg
== 5)
9214 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9217 /* APSR_ sets isvec. All other refs to PC are illegal. */
9218 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9220 inst
.error
= BAD_PC
;
9224 /* If we get through parsing the register name, we just insert the number
9225 generated into the instruction without further validation. */
9226 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9227 inst
.instruction
|= (Rt
<< 12);
9233 unsigned Rt
= inst
.operands
[1].reg
;
9236 reject_bad_reg (Rt
);
9237 else if (Rt
== REG_PC
)
9239 inst
.error
= BAD_PC
;
9243 /* MVFR2 is only valid for ARMv8-A. */
9244 if (inst
.operands
[0].reg
== 5)
9245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9248 /* If we get through parsing the register name, we just insert the number
9249 generated into the instruction without further validation. */
9250 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9251 inst
.instruction
|= (Rt
<< 12);
9259 if (do_vfp_nsyn_mrs () == SUCCESS
)
9262 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9265 if (inst
.operands
[1].isreg
)
9267 br
= inst
.operands
[1].reg
;
9268 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9269 as_bad (_("bad register for mrs"));
9273 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9274 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9276 _("'APSR', 'CPSR' or 'SPSR' expected"));
9277 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9280 inst
.instruction
|= br
;
9283 /* Two possible forms:
9284 "{C|S}PSR_<field>, Rm",
9285 "{C|S}PSR_f, #expression". */
9290 if (do_vfp_nsyn_msr () == SUCCESS
)
9293 inst
.instruction
|= inst
.operands
[0].imm
;
9294 if (inst
.operands
[1].isreg
)
9295 inst
.instruction
|= inst
.operands
[1].reg
;
9298 inst
.instruction
|= INST_IMMEDIATE
;
9299 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9300 inst
.reloc
.pc_rel
= 0;
9307 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9309 if (!inst
.operands
[2].present
)
9310 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9311 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9312 inst
.instruction
|= inst
.operands
[1].reg
;
9313 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9315 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9316 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9317 as_tsktsk (_("Rd and Rm should be different in mul"));
9320 /* Long Multiply Parser
9321 UMULL RdLo, RdHi, Rm, Rs
9322 SMULL RdLo, RdHi, Rm, Rs
9323 UMLAL RdLo, RdHi, Rm, Rs
9324 SMLAL RdLo, RdHi, Rm, Rs. */
9329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9330 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9331 inst
.instruction
|= inst
.operands
[2].reg
;
9332 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9334 /* rdhi and rdlo must be different. */
9335 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9336 as_tsktsk (_("rdhi and rdlo must be different"));
9338 /* rdhi, rdlo and rm must all be different before armv6. */
9339 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9340 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9341 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9342 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9348 if (inst
.operands
[0].present
9349 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9351 /* Architectural NOP hints are CPSR sets with no bits selected. */
9352 inst
.instruction
&= 0xf0000000;
9353 inst
.instruction
|= 0x0320f000;
9354 if (inst
.operands
[0].present
)
9355 inst
.instruction
|= inst
.operands
[0].imm
;
9359 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9360 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9361 Condition defaults to COND_ALWAYS.
9362 Error if Rd, Rn or Rm are R15. */
9367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9368 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9369 inst
.instruction
|= inst
.operands
[2].reg
;
9370 if (inst
.operands
[3].present
)
9371 encode_arm_shift (3);
9374 /* ARM V6 PKHTB (Argument Parse). */
9379 if (!inst
.operands
[3].present
)
9381 /* If the shift specifier is omitted, turn the instruction
9382 into pkhbt rd, rm, rn. */
9383 inst
.instruction
&= 0xfff00010;
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9385 inst
.instruction
|= inst
.operands
[1].reg
;
9386 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9390 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9391 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9392 inst
.instruction
|= inst
.operands
[2].reg
;
9393 encode_arm_shift (3);
9397 /* ARMv5TE: Preload-Cache
9398 MP Extensions: Preload for write
9402 Syntactically, like LDR with B=1, W=0, L=1. */
9407 constraint (!inst
.operands
[0].isreg
,
9408 _("'[' expected after PLD mnemonic"));
9409 constraint (inst
.operands
[0].postind
,
9410 _("post-indexed expression used in preload instruction"));
9411 constraint (inst
.operands
[0].writeback
,
9412 _("writeback used in preload instruction"));
9413 constraint (!inst
.operands
[0].preind
,
9414 _("unindexed addressing used in preload instruction"));
9415 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9418 /* ARMv7: PLI <addr_mode> */
9422 constraint (!inst
.operands
[0].isreg
,
9423 _("'[' expected after PLI mnemonic"));
9424 constraint (inst
.operands
[0].postind
,
9425 _("post-indexed expression used in preload instruction"));
9426 constraint (inst
.operands
[0].writeback
,
9427 _("writeback used in preload instruction"));
9428 constraint (!inst
.operands
[0].preind
,
9429 _("unindexed addressing used in preload instruction"));
9430 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9431 inst
.instruction
&= ~PRE_INDEX
;
9437 constraint (inst
.operands
[0].writeback
,
9438 _("push/pop do not support {reglist}^"));
9439 inst
.operands
[1] = inst
.operands
[0];
9440 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9441 inst
.operands
[0].isreg
= 1;
9442 inst
.operands
[0].writeback
= 1;
9443 inst
.operands
[0].reg
= REG_SP
;
9444 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9447 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9448 word at the specified address and the following word
9450 Unconditionally executed.
9451 Error if Rn is R15. */
9456 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9457 if (inst
.operands
[0].writeback
)
9458 inst
.instruction
|= WRITE_BACK
;
9461 /* ARM V6 ssat (argument parse). */
9466 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9467 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9468 inst
.instruction
|= inst
.operands
[2].reg
;
9470 if (inst
.operands
[3].present
)
9471 encode_arm_shift (3);
9474 /* ARM V6 usat (argument parse). */
9479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9480 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9481 inst
.instruction
|= inst
.operands
[2].reg
;
9483 if (inst
.operands
[3].present
)
9484 encode_arm_shift (3);
9487 /* ARM V6 ssat16 (argument parse). */
9492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9493 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9494 inst
.instruction
|= inst
.operands
[2].reg
;
9500 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9501 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9502 inst
.instruction
|= inst
.operands
[2].reg
;
9505 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9506 preserving the other bits.
9508 setend <endian_specifier>, where <endian_specifier> is either
9514 if (warn_on_deprecated
9515 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9516 as_tsktsk (_("setend use is deprecated for ARMv8"));
9518 if (inst
.operands
[0].imm
)
9519 inst
.instruction
|= 0x200;
9525 unsigned int Rm
= (inst
.operands
[1].present
9526 ? inst
.operands
[1].reg
9527 : inst
.operands
[0].reg
);
9529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9530 inst
.instruction
|= Rm
;
9531 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9533 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9534 inst
.instruction
|= SHIFT_BY_REG
;
9535 /* PR 12854: Error on extraneous shifts. */
9536 constraint (inst
.operands
[2].shifted
,
9537 _("extraneous shift as part of operand to shift insn"));
9540 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9546 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9547 inst
.reloc
.pc_rel
= 0;
9553 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9554 inst
.reloc
.pc_rel
= 0;
9560 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9561 inst
.reloc
.pc_rel
= 0;
9567 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9568 _("selected processor does not support SETPAN instruction"));
9570 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9577 _("selected processor does not support SETPAN instruction"));
9579 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9582 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9583 SMLAxy{cond} Rd,Rm,Rs,Rn
9584 SMLAWy{cond} Rd,Rm,Rs,Rn
9585 Error if any register is R15. */
9590 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9591 inst
.instruction
|= inst
.operands
[1].reg
;
9592 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9593 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9596 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9597 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9598 Error if any register is R15.
9599 Warning if Rdlo == Rdhi. */
9604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9605 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9606 inst
.instruction
|= inst
.operands
[2].reg
;
9607 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9609 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9610 as_tsktsk (_("rdhi and rdlo must be different"));
9613 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9614 SMULxy{cond} Rd,Rm,Rs
9615 Error if any register is R15. */
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9621 inst
.instruction
|= inst
.operands
[1].reg
;
9622 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9625 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9626 the same for both ARM and Thumb-2. */
9633 if (inst
.operands
[0].present
)
9635 reg
= inst
.operands
[0].reg
;
9636 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9641 inst
.instruction
|= reg
<< 16;
9642 inst
.instruction
|= inst
.operands
[1].imm
;
9643 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9644 inst
.instruction
|= WRITE_BACK
;
9647 /* ARM V6 strex (argument parse). */
9652 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9653 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9654 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9655 || inst
.operands
[2].negative
9656 /* See comment in do_ldrex(). */
9657 || (inst
.operands
[2].reg
== REG_PC
),
9660 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9661 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9663 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9664 || inst
.reloc
.exp
.X_add_number
!= 0,
9665 _("offset must be zero in ARM encoding"));
9667 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9668 inst
.instruction
|= inst
.operands
[1].reg
;
9669 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9670 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9676 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9677 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9678 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9679 || inst
.operands
[2].negative
,
9682 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9683 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9691 constraint (inst
.operands
[1].reg
% 2 != 0,
9692 _("even register required"));
9693 constraint (inst
.operands
[2].present
9694 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9695 _("can only store two consecutive registers"));
9696 /* If op 2 were present and equal to PC, this function wouldn't
9697 have been called in the first place. */
9698 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9700 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9701 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9702 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9706 inst
.instruction
|= inst
.operands
[1].reg
;
9707 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9714 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9715 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9723 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9724 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9729 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9730 extends it to 32-bits, and adds the result to a value in another
9731 register. You can specify a rotation by 0, 8, 16, or 24 bits
9732 before extracting the 16-bit value.
9733 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9734 Condition defaults to COND_ALWAYS.
9735 Error if any register uses R15. */
9740 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9741 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9742 inst
.instruction
|= inst
.operands
[2].reg
;
9743 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9748 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9749 Condition defaults to COND_ALWAYS.
9750 Error if any register uses R15. */
9755 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9756 inst
.instruction
|= inst
.operands
[1].reg
;
9757 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9760 /* VFP instructions. In a logical order: SP variant first, monad
9761 before dyad, arithmetic then move then load/store. */
9764 do_vfp_sp_monadic (void)
9766 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9767 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9771 do_vfp_sp_dyadic (void)
9773 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9774 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9775 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9779 do_vfp_sp_compare_z (void)
9781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9785 do_vfp_dp_sp_cvt (void)
9787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9788 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9792 do_vfp_sp_dp_cvt (void)
9794 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9795 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9799 do_vfp_reg_from_sp (void)
9801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9802 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9806 do_vfp_reg2_from_sp2 (void)
9808 constraint (inst
.operands
[2].imm
!= 2,
9809 _("only two consecutive VFP SP registers allowed here"));
9810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9811 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9812 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9816 do_vfp_sp_from_reg (void)
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9819 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9823 do_vfp_sp2_from_reg2 (void)
9825 constraint (inst
.operands
[0].imm
!= 2,
9826 _("only two consecutive VFP SP registers allowed here"));
9827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9828 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9829 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9833 do_vfp_sp_ldst (void)
9835 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9836 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9840 do_vfp_dp_ldst (void)
9842 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9843 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9848 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9850 if (inst
.operands
[0].writeback
)
9851 inst
.instruction
|= WRITE_BACK
;
9853 constraint (ldstm_type
!= VFP_LDSTMIA
,
9854 _("this addressing mode requires base-register writeback"));
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9856 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9857 inst
.instruction
|= inst
.operands
[1].imm
;
9861 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9865 if (inst
.operands
[0].writeback
)
9866 inst
.instruction
|= WRITE_BACK
;
9868 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9869 _("this addressing mode requires base-register writeback"));
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9872 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9874 count
= inst
.operands
[1].imm
<< 1;
9875 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9878 inst
.instruction
|= count
;
9882 do_vfp_sp_ldstmia (void)
9884 vfp_sp_ldstm (VFP_LDSTMIA
);
9888 do_vfp_sp_ldstmdb (void)
9890 vfp_sp_ldstm (VFP_LDSTMDB
);
9894 do_vfp_dp_ldstmia (void)
9896 vfp_dp_ldstm (VFP_LDSTMIA
);
9900 do_vfp_dp_ldstmdb (void)
9902 vfp_dp_ldstm (VFP_LDSTMDB
);
9906 do_vfp_xp_ldstmia (void)
9908 vfp_dp_ldstm (VFP_LDSTMIAX
);
9912 do_vfp_xp_ldstmdb (void)
9914 vfp_dp_ldstm (VFP_LDSTMDBX
);
9918 do_vfp_dp_rd_rm (void)
9920 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9921 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9925 do_vfp_dp_rn_rd (void)
9927 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9928 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9932 do_vfp_dp_rd_rn (void)
9934 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9935 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9939 do_vfp_dp_rd_rn_rm (void)
9941 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9942 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9943 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9949 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9953 do_vfp_dp_rm_rd_rn (void)
9955 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9956 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9957 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9960 /* VFPv3 instructions. */
9962 do_vfp_sp_const (void)
9964 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9965 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9966 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9970 do_vfp_dp_const (void)
9972 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9973 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9974 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9978 vfp_conv (int srcsize
)
9980 int immbits
= srcsize
- inst
.operands
[1].imm
;
9982 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9984 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9985 i.e. immbits must be in range 0 - 16. */
9986 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9989 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9991 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9992 i.e. immbits must be in range 0 - 31. */
9993 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9997 inst
.instruction
|= (immbits
& 1) << 5;
9998 inst
.instruction
|= (immbits
>> 1);
10002 do_vfp_sp_conv_16 (void)
10004 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10009 do_vfp_dp_conv_16 (void)
10011 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10016 do_vfp_sp_conv_32 (void)
10018 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10023 do_vfp_dp_conv_32 (void)
10025 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10029 /* FPA instructions. Also in a logical order. */
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10035 inst
.instruction
|= inst
.operands
[1].reg
;
10039 do_fpa_ldmstm (void)
10041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10042 switch (inst
.operands
[1].imm
)
10044 case 1: inst
.instruction
|= CP_T_X
; break;
10045 case 2: inst
.instruction
|= CP_T_Y
; break;
10046 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10051 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10053 /* The instruction specified "ea" or "fd", so we can only accept
10054 [Rn]{!}. The instruction does not really support stacking or
10055 unstacking, so we have to emulate these by setting appropriate
10056 bits and offsets. */
10057 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10058 || inst
.reloc
.exp
.X_add_number
!= 0,
10059 _("this instruction does not support indexing"));
10061 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10062 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10064 if (!(inst
.instruction
& INDEX_UP
))
10065 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10067 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10069 inst
.operands
[2].preind
= 0;
10070 inst
.operands
[2].postind
= 1;
10074 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10077 /* iWMMXt instructions: strictly in alphabetical order. */
10080 do_iwmmxt_tandorc (void)
10082 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10086 do_iwmmxt_textrc (void)
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10089 inst
.instruction
|= inst
.operands
[1].imm
;
10093 do_iwmmxt_textrm (void)
10095 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10096 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10097 inst
.instruction
|= inst
.operands
[2].imm
;
10101 do_iwmmxt_tinsr (void)
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10104 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10105 inst
.instruction
|= inst
.operands
[2].imm
;
10109 do_iwmmxt_tmia (void)
10111 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10112 inst
.instruction
|= inst
.operands
[1].reg
;
10113 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10117 do_iwmmxt_waligni (void)
10119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10120 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10121 inst
.instruction
|= inst
.operands
[2].reg
;
10122 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10126 do_iwmmxt_wmerge (void)
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10130 inst
.instruction
|= inst
.operands
[2].reg
;
10131 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10135 do_iwmmxt_wmov (void)
10137 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10140 inst
.instruction
|= inst
.operands
[1].reg
;
10144 do_iwmmxt_wldstbh (void)
10147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10149 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10151 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10152 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10156 do_iwmmxt_wldstw (void)
10158 /* RIWR_RIWC clears .isreg for a control register. */
10159 if (!inst
.operands
[0].isreg
)
10161 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10162 inst
.instruction
|= 0xf0000000;
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10166 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10170 do_iwmmxt_wldstd (void)
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10173 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10174 && inst
.operands
[1].immisreg
)
10176 inst
.instruction
&= ~0x1a000ff;
10177 inst
.instruction
|= (0xfU
<< 28);
10178 if (inst
.operands
[1].preind
)
10179 inst
.instruction
|= PRE_INDEX
;
10180 if (!inst
.operands
[1].negative
)
10181 inst
.instruction
|= INDEX_UP
;
10182 if (inst
.operands
[1].writeback
)
10183 inst
.instruction
|= WRITE_BACK
;
10184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10185 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10186 inst
.instruction
|= inst
.operands
[1].imm
;
10189 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10193 do_iwmmxt_wshufh (void)
10195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10196 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10197 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10198 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10202 do_iwmmxt_wzero (void)
10204 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10205 inst
.instruction
|= inst
.operands
[0].reg
;
10206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10207 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10211 do_iwmmxt_wrwrwr_or_imm5 (void)
10213 if (inst
.operands
[2].isreg
)
10216 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10217 _("immediate operand requires iWMMXt2"));
10219 if (inst
.operands
[2].imm
== 0)
10221 switch ((inst
.instruction
>> 20) & 0xf)
10227 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10228 inst
.operands
[2].imm
= 16;
10229 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10235 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10236 inst
.operands
[2].imm
= 32;
10237 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10244 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10246 wrn
= (inst
.instruction
>> 16) & 0xf;
10247 inst
.instruction
&= 0xff0fff0f;
10248 inst
.instruction
|= wrn
;
10249 /* Bail out here; the instruction is now assembled. */
10254 /* Map 32 -> 0, etc. */
10255 inst
.operands
[2].imm
&= 0x1f;
10256 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10260 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10261 operations first, then control, shift, and load/store. */
10263 /* Insns like "foo X,Y,Z". */
10266 do_mav_triple (void)
10268 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10269 inst
.instruction
|= inst
.operands
[1].reg
;
10270 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10273 /* Insns like "foo W,X,Y,Z".
10274 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10279 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10280 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10281 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10282 inst
.instruction
|= inst
.operands
[3].reg
;
10285 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10287 do_mav_dspsc (void)
10289 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10292 /* Maverick shift immediate instructions.
10293 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10294 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10297 do_mav_shift (void)
10299 int imm
= inst
.operands
[2].imm
;
10301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10302 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10304 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10305 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10306 Bit 4 should be 0. */
10307 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10309 inst
.instruction
|= imm
;
10312 /* XScale instructions. Also sorted arithmetic before move. */
10314 /* Xscale multiply-accumulate (argument parse)
10317 MIAxycc acc0,Rm,Rs. */
10322 inst
.instruction
|= inst
.operands
[1].reg
;
10323 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10326 /* Xscale move-accumulator-register (argument parse)
10328 MARcc acc0,RdLo,RdHi. */
10333 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10334 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10337 /* Xscale move-register-accumulator (argument parse)
10339 MRAcc RdLo,RdHi,acc0. */
10344 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10346 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10349 /* Encoding functions relevant only to Thumb. */
10351 /* inst.operands[i] is a shifted-register operand; encode
10352 it into inst.instruction in the format used by Thumb32. */
10355 encode_thumb32_shifted_operand (int i
)
10357 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10358 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10360 constraint (inst
.operands
[i
].immisreg
,
10361 _("shift by register not allowed in thumb mode"));
10362 inst
.instruction
|= inst
.operands
[i
].reg
;
10363 if (shift
== SHIFT_RRX
)
10364 inst
.instruction
|= SHIFT_ROR
<< 4;
10367 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10368 _("expression too complex"));
10370 constraint (value
> 32
10371 || (value
== 32 && (shift
== SHIFT_LSL
10372 || shift
== SHIFT_ROR
)),
10373 _("shift expression is too large"));
10377 else if (value
== 32)
10380 inst
.instruction
|= shift
<< 4;
10381 inst
.instruction
|= (value
& 0x1c) << 10;
10382 inst
.instruction
|= (value
& 0x03) << 6;
10387 /* inst.operands[i] was set up by parse_address. Encode it into a
10388 Thumb32 format load or store instruction. Reject forms that cannot
10389 be used with such instructions. If is_t is true, reject forms that
10390 cannot be used with a T instruction; if is_d is true, reject forms
10391 that cannot be used with a D instruction. If it is a store insn,
10392 reject PC in Rn. */
10395 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10397 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10399 constraint (!inst
.operands
[i
].isreg
,
10400 _("Instruction does not support =N addresses"));
10402 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10403 if (inst
.operands
[i
].immisreg
)
10405 constraint (is_pc
, BAD_PC_ADDRESSING
);
10406 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10407 constraint (inst
.operands
[i
].negative
,
10408 _("Thumb does not support negative register indexing"));
10409 constraint (inst
.operands
[i
].postind
,
10410 _("Thumb does not support register post-indexing"));
10411 constraint (inst
.operands
[i
].writeback
,
10412 _("Thumb does not support register indexing with writeback"));
10413 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10414 _("Thumb supports only LSL in shifted register indexing"));
10416 inst
.instruction
|= inst
.operands
[i
].imm
;
10417 if (inst
.operands
[i
].shifted
)
10419 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10420 _("expression too complex"));
10421 constraint (inst
.reloc
.exp
.X_add_number
< 0
10422 || inst
.reloc
.exp
.X_add_number
> 3,
10423 _("shift out of range"));
10424 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10426 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10428 else if (inst
.operands
[i
].preind
)
10430 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10431 constraint (is_t
&& inst
.operands
[i
].writeback
,
10432 _("cannot use writeback with this instruction"));
10433 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10434 BAD_PC_ADDRESSING
);
10438 inst
.instruction
|= 0x01000000;
10439 if (inst
.operands
[i
].writeback
)
10440 inst
.instruction
|= 0x00200000;
10444 inst
.instruction
|= 0x00000c00;
10445 if (inst
.operands
[i
].writeback
)
10446 inst
.instruction
|= 0x00000100;
10448 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10450 else if (inst
.operands
[i
].postind
)
10452 gas_assert (inst
.operands
[i
].writeback
);
10453 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10454 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10457 inst
.instruction
|= 0x00200000;
10459 inst
.instruction
|= 0x00000900;
10460 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10462 else /* unindexed - only for coprocessor */
10463 inst
.error
= _("instruction does not accept unindexed addressing");
10466 /* Table of Thumb instructions which exist in both 16- and 32-bit
10467 encodings (the latter only in post-V6T2 cores). The index is the
10468 value used in the insns table below. When there is more than one
10469 possible 16-bit encoding for the instruction, this table always
10471 Also contains several pseudo-instructions used during relaxation. */
10472 #define T16_32_TAB \
10473 X(_adc, 4140, eb400000), \
10474 X(_adcs, 4140, eb500000), \
10475 X(_add, 1c00, eb000000), \
10476 X(_adds, 1c00, eb100000), \
10477 X(_addi, 0000, f1000000), \
10478 X(_addis, 0000, f1100000), \
10479 X(_add_pc,000f, f20f0000), \
10480 X(_add_sp,000d, f10d0000), \
10481 X(_adr, 000f, f20f0000), \
10482 X(_and, 4000, ea000000), \
10483 X(_ands, 4000, ea100000), \
10484 X(_asr, 1000, fa40f000), \
10485 X(_asrs, 1000, fa50f000), \
10486 X(_b, e000, f000b000), \
10487 X(_bcond, d000, f0008000), \
10488 X(_bic, 4380, ea200000), \
10489 X(_bics, 4380, ea300000), \
10490 X(_cmn, 42c0, eb100f00), \
10491 X(_cmp, 2800, ebb00f00), \
10492 X(_cpsie, b660, f3af8400), \
10493 X(_cpsid, b670, f3af8600), \
10494 X(_cpy, 4600, ea4f0000), \
10495 X(_dec_sp,80dd, f1ad0d00), \
10496 X(_eor, 4040, ea800000), \
10497 X(_eors, 4040, ea900000), \
10498 X(_inc_sp,00dd, f10d0d00), \
10499 X(_ldmia, c800, e8900000), \
10500 X(_ldr, 6800, f8500000), \
10501 X(_ldrb, 7800, f8100000), \
10502 X(_ldrh, 8800, f8300000), \
10503 X(_ldrsb, 5600, f9100000), \
10504 X(_ldrsh, 5e00, f9300000), \
10505 X(_ldr_pc,4800, f85f0000), \
10506 X(_ldr_pc2,4800, f85f0000), \
10507 X(_ldr_sp,9800, f85d0000), \
10508 X(_lsl, 0000, fa00f000), \
10509 X(_lsls, 0000, fa10f000), \
10510 X(_lsr, 0800, fa20f000), \
10511 X(_lsrs, 0800, fa30f000), \
10512 X(_mov, 2000, ea4f0000), \
10513 X(_movs, 2000, ea5f0000), \
10514 X(_mul, 4340, fb00f000), \
10515 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10516 X(_mvn, 43c0, ea6f0000), \
10517 X(_mvns, 43c0, ea7f0000), \
10518 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10519 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10520 X(_orr, 4300, ea400000), \
10521 X(_orrs, 4300, ea500000), \
10522 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10523 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10524 X(_rev, ba00, fa90f080), \
10525 X(_rev16, ba40, fa90f090), \
10526 X(_revsh, bac0, fa90f0b0), \
10527 X(_ror, 41c0, fa60f000), \
10528 X(_rors, 41c0, fa70f000), \
10529 X(_sbc, 4180, eb600000), \
10530 X(_sbcs, 4180, eb700000), \
10531 X(_stmia, c000, e8800000), \
10532 X(_str, 6000, f8400000), \
10533 X(_strb, 7000, f8000000), \
10534 X(_strh, 8000, f8200000), \
10535 X(_str_sp,9000, f84d0000), \
10536 X(_sub, 1e00, eba00000), \
10537 X(_subs, 1e00, ebb00000), \
10538 X(_subi, 8000, f1a00000), \
10539 X(_subis, 8000, f1b00000), \
10540 X(_sxtb, b240, fa4ff080), \
10541 X(_sxth, b200, fa0ff080), \
10542 X(_tst, 4200, ea100f00), \
10543 X(_uxtb, b2c0, fa5ff080), \
10544 X(_uxth, b280, fa1ff080), \
10545 X(_nop, bf00, f3af8000), \
10546 X(_yield, bf10, f3af8001), \
10547 X(_wfe, bf20, f3af8002), \
10548 X(_wfi, bf30, f3af8003), \
10549 X(_sev, bf40, f3af8004), \
10550 X(_sevl, bf50, f3af8005), \
10551 X(_udf, de00, f7f0a000)
10553 /* To catch errors in encoding functions, the codes are all offset by
10554 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10555 as 16-bit instructions. */
10556 #define X(a,b,c) T_MNEM##a
10557 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10560 #define X(a,b,c) 0x##b
10561 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10562 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10565 #define X(a,b,c) 0x##c
10566 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10567 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10568 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10572 /* Thumb instruction encoders, in alphabetical order. */
10574 /* ADDW or SUBW. */
10577 do_t_add_sub_w (void)
10581 Rd
= inst
.operands
[0].reg
;
10582 Rn
= inst
.operands
[1].reg
;
10584 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10585 is the SP-{plus,minus}-immediate form of the instruction. */
10587 constraint (Rd
== REG_PC
, BAD_PC
);
10589 reject_bad_reg (Rd
);
10591 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10592 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10595 /* Parse an add or subtract instruction. We get here with inst.instruction
10596 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10599 do_t_add_sub (void)
10603 Rd
= inst
.operands
[0].reg
;
10604 Rs
= (inst
.operands
[1].present
10605 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10606 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10609 set_it_insn_type_last ();
10611 if (unified_syntax
)
10614 bfd_boolean narrow
;
10617 flags
= (inst
.instruction
== T_MNEM_adds
10618 || inst
.instruction
== T_MNEM_subs
);
10620 narrow
= !in_it_block ();
10622 narrow
= in_it_block ();
10623 if (!inst
.operands
[2].isreg
)
10627 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10628 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10630 add
= (inst
.instruction
== T_MNEM_add
10631 || inst
.instruction
== T_MNEM_adds
);
10633 if (inst
.size_req
!= 4)
10635 /* Attempt to use a narrow opcode, with relaxation if
10637 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10638 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10639 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10640 opcode
= T_MNEM_add_sp
;
10641 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10642 opcode
= T_MNEM_add_pc
;
10643 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10646 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10648 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10652 inst
.instruction
= THUMB_OP16(opcode
);
10653 inst
.instruction
|= (Rd
<< 4) | Rs
;
10654 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10655 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10657 if (inst
.size_req
== 2)
10658 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10660 inst
.relax
= opcode
;
10664 constraint (inst
.size_req
== 2, BAD_HIREG
);
10666 if (inst
.size_req
== 4
10667 || (inst
.size_req
!= 2 && !opcode
))
10669 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10670 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10671 THUMB1_RELOC_ONLY
);
10674 constraint (add
, BAD_PC
);
10675 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10676 _("only SUBS PC, LR, #const allowed"));
10677 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10678 _("expression too complex"));
10679 constraint (inst
.reloc
.exp
.X_add_number
< 0
10680 || inst
.reloc
.exp
.X_add_number
> 0xff,
10681 _("immediate value out of range"));
10682 inst
.instruction
= T2_SUBS_PC_LR
10683 | inst
.reloc
.exp
.X_add_number
;
10684 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10687 else if (Rs
== REG_PC
)
10689 /* Always use addw/subw. */
10690 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10691 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10696 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10699 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10701 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10703 inst
.instruction
|= Rd
<< 8;
10704 inst
.instruction
|= Rs
<< 16;
10709 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10710 unsigned int shift
= inst
.operands
[2].shift_kind
;
10712 Rn
= inst
.operands
[2].reg
;
10713 /* See if we can do this with a 16-bit instruction. */
10714 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10716 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10721 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10722 || inst
.instruction
== T_MNEM_add
)
10724 : T_OPCODE_SUB_R3
);
10725 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10729 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10731 /* Thumb-1 cores (except v6-M) require at least one high
10732 register in a narrow non flag setting add. */
10733 if (Rd
> 7 || Rn
> 7
10734 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10735 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10742 inst
.instruction
= T_OPCODE_ADD_HI
;
10743 inst
.instruction
|= (Rd
& 8) << 4;
10744 inst
.instruction
|= (Rd
& 7);
10745 inst
.instruction
|= Rn
<< 3;
10751 constraint (Rd
== REG_PC
, BAD_PC
);
10752 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10753 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10754 constraint (Rs
== REG_PC
, BAD_PC
);
10755 reject_bad_reg (Rn
);
10757 /* If we get here, it can't be done in 16 bits. */
10758 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10759 _("shift must be constant"));
10760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10761 inst
.instruction
|= Rd
<< 8;
10762 inst
.instruction
|= Rs
<< 16;
10763 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10764 _("shift value over 3 not allowed in thumb mode"));
10765 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10766 _("only LSL shift allowed in thumb mode"));
10767 encode_thumb32_shifted_operand (2);
10772 constraint (inst
.instruction
== T_MNEM_adds
10773 || inst
.instruction
== T_MNEM_subs
,
10776 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10778 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10779 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10782 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10783 ? 0x0000 : 0x8000);
10784 inst
.instruction
|= (Rd
<< 4) | Rs
;
10785 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10789 Rn
= inst
.operands
[2].reg
;
10790 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10792 /* We now have Rd, Rs, and Rn set to registers. */
10793 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10795 /* Can't do this for SUB. */
10796 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10797 inst
.instruction
= T_OPCODE_ADD_HI
;
10798 inst
.instruction
|= (Rd
& 8) << 4;
10799 inst
.instruction
|= (Rd
& 7);
10801 inst
.instruction
|= Rn
<< 3;
10803 inst
.instruction
|= Rs
<< 3;
10805 constraint (1, _("dest must overlap one source register"));
10809 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10810 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10811 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10821 Rd
= inst
.operands
[0].reg
;
10822 reject_bad_reg (Rd
);
10824 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10826 /* Defer to section relaxation. */
10827 inst
.relax
= inst
.instruction
;
10828 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10829 inst
.instruction
|= Rd
<< 4;
10831 else if (unified_syntax
&& inst
.size_req
!= 2)
10833 /* Generate a 32-bit opcode. */
10834 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10835 inst
.instruction
|= Rd
<< 8;
10836 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10837 inst
.reloc
.pc_rel
= 1;
10841 /* Generate a 16-bit opcode. */
10842 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10843 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10844 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10845 inst
.reloc
.pc_rel
= 1;
10846 inst
.instruction
|= Rd
<< 4;
10849 if (inst
.reloc
.exp
.X_op
== O_symbol
10850 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10851 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10852 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10853 inst
.reloc
.exp
.X_add_number
+= 1;
10856 /* Arithmetic instructions for which there is just one 16-bit
10857 instruction encoding, and it allows only two low registers.
10858 For maximal compatibility with ARM syntax, we allow three register
10859 operands even when Thumb-32 instructions are not available, as long
10860 as the first two are identical. For instance, both "sbc r0,r1" and
10861 "sbc r0,r0,r1" are allowed. */
10867 Rd
= inst
.operands
[0].reg
;
10868 Rs
= (inst
.operands
[1].present
10869 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10870 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10871 Rn
= inst
.operands
[2].reg
;
10873 reject_bad_reg (Rd
);
10874 reject_bad_reg (Rs
);
10875 if (inst
.operands
[2].isreg
)
10876 reject_bad_reg (Rn
);
10878 if (unified_syntax
)
10880 if (!inst
.operands
[2].isreg
)
10882 /* For an immediate, we always generate a 32-bit opcode;
10883 section relaxation will shrink it later if possible. */
10884 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10885 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10886 inst
.instruction
|= Rd
<< 8;
10887 inst
.instruction
|= Rs
<< 16;
10888 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10892 bfd_boolean narrow
;
10894 /* See if we can do this with a 16-bit instruction. */
10895 if (THUMB_SETS_FLAGS (inst
.instruction
))
10896 narrow
= !in_it_block ();
10898 narrow
= in_it_block ();
10900 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10902 if (inst
.operands
[2].shifted
)
10904 if (inst
.size_req
== 4)
10910 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10911 inst
.instruction
|= Rd
;
10912 inst
.instruction
|= Rn
<< 3;
10916 /* If we get here, it can't be done in 16 bits. */
10917 constraint (inst
.operands
[2].shifted
10918 && inst
.operands
[2].immisreg
,
10919 _("shift must be constant"));
10920 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10921 inst
.instruction
|= Rd
<< 8;
10922 inst
.instruction
|= Rs
<< 16;
10923 encode_thumb32_shifted_operand (2);
10928 /* On its face this is a lie - the instruction does set the
10929 flags. However, the only supported mnemonic in this mode
10930 says it doesn't. */
10931 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10933 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10934 _("unshifted register required"));
10935 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10936 constraint (Rd
!= Rs
,
10937 _("dest and source1 must be the same register"));
10939 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10940 inst
.instruction
|= Rd
;
10941 inst
.instruction
|= Rn
<< 3;
10945 /* Similarly, but for instructions where the arithmetic operation is
10946 commutative, so we can allow either of them to be different from
10947 the destination operand in a 16-bit instruction. For instance, all
10948 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10955 Rd
= inst
.operands
[0].reg
;
10956 Rs
= (inst
.operands
[1].present
10957 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10958 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10959 Rn
= inst
.operands
[2].reg
;
10961 reject_bad_reg (Rd
);
10962 reject_bad_reg (Rs
);
10963 if (inst
.operands
[2].isreg
)
10964 reject_bad_reg (Rn
);
10966 if (unified_syntax
)
10968 if (!inst
.operands
[2].isreg
)
10970 /* For an immediate, we always generate a 32-bit opcode;
10971 section relaxation will shrink it later if possible. */
10972 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10973 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10974 inst
.instruction
|= Rd
<< 8;
10975 inst
.instruction
|= Rs
<< 16;
10976 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10980 bfd_boolean narrow
;
10982 /* See if we can do this with a 16-bit instruction. */
10983 if (THUMB_SETS_FLAGS (inst
.instruction
))
10984 narrow
= !in_it_block ();
10986 narrow
= in_it_block ();
10988 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10990 if (inst
.operands
[2].shifted
)
10992 if (inst
.size_req
== 4)
10999 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11000 inst
.instruction
|= Rd
;
11001 inst
.instruction
|= Rn
<< 3;
11006 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11007 inst
.instruction
|= Rd
;
11008 inst
.instruction
|= Rs
<< 3;
11013 /* If we get here, it can't be done in 16 bits. */
11014 constraint (inst
.operands
[2].shifted
11015 && inst
.operands
[2].immisreg
,
11016 _("shift must be constant"));
11017 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11018 inst
.instruction
|= Rd
<< 8;
11019 inst
.instruction
|= Rs
<< 16;
11020 encode_thumb32_shifted_operand (2);
11025 /* On its face this is a lie - the instruction does set the
11026 flags. However, the only supported mnemonic in this mode
11027 says it doesn't. */
11028 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11030 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11031 _("unshifted register required"));
11032 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11034 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11035 inst
.instruction
|= Rd
;
11038 inst
.instruction
|= Rn
<< 3;
11040 inst
.instruction
|= Rs
<< 3;
11042 constraint (1, _("dest must overlap one source register"));
11050 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11051 constraint (msb
> 32, _("bit-field extends past end of register"));
11052 /* The instruction encoding stores the LSB and MSB,
11053 not the LSB and width. */
11054 Rd
= inst
.operands
[0].reg
;
11055 reject_bad_reg (Rd
);
11056 inst
.instruction
|= Rd
<< 8;
11057 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11058 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11059 inst
.instruction
|= msb
- 1;
11068 Rd
= inst
.operands
[0].reg
;
11069 reject_bad_reg (Rd
);
11071 /* #0 in second position is alternative syntax for bfc, which is
11072 the same instruction but with REG_PC in the Rm field. */
11073 if (!inst
.operands
[1].isreg
)
11077 Rn
= inst
.operands
[1].reg
;
11078 reject_bad_reg (Rn
);
11081 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11082 constraint (msb
> 32, _("bit-field extends past end of register"));
11083 /* The instruction encoding stores the LSB and MSB,
11084 not the LSB and width. */
11085 inst
.instruction
|= Rd
<< 8;
11086 inst
.instruction
|= Rn
<< 16;
11087 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11088 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11089 inst
.instruction
|= msb
- 1;
11097 Rd
= inst
.operands
[0].reg
;
11098 Rn
= inst
.operands
[1].reg
;
11100 reject_bad_reg (Rd
);
11101 reject_bad_reg (Rn
);
11103 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11104 _("bit-field extends past end of register"));
11105 inst
.instruction
|= Rd
<< 8;
11106 inst
.instruction
|= Rn
<< 16;
11107 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11108 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11109 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11112 /* ARM V5 Thumb BLX (argument parse)
11113 BLX <target_addr> which is BLX(1)
11114 BLX <Rm> which is BLX(2)
11115 Unfortunately, there are two different opcodes for this mnemonic.
11116 So, the insns[].value is not used, and the code here zaps values
11117 into inst.instruction.
11119 ??? How to take advantage of the additional two bits of displacement
11120 available in Thumb32 mode? Need new relocation? */
11125 set_it_insn_type_last ();
11127 if (inst
.operands
[0].isreg
)
11129 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11130 /* We have a register, so this is BLX(2). */
11131 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11135 /* No register. This must be BLX(1). */
11136 inst
.instruction
= 0xf000e800;
11137 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11146 bfd_reloc_code_real_type reloc
;
11149 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11151 if (in_it_block ())
11153 /* Conditional branches inside IT blocks are encoded as unconditional
11155 cond
= COND_ALWAYS
;
11160 if (cond
!= COND_ALWAYS
)
11161 opcode
= T_MNEM_bcond
;
11163 opcode
= inst
.instruction
;
11166 && (inst
.size_req
== 4
11167 || (inst
.size_req
!= 2
11168 && (inst
.operands
[0].hasreloc
11169 || inst
.reloc
.exp
.X_op
== O_constant
))))
11171 inst
.instruction
= THUMB_OP32(opcode
);
11172 if (cond
== COND_ALWAYS
)
11173 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11176 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11177 _("selected architecture does not support "
11178 "wide conditional branch instruction"));
11180 gas_assert (cond
!= 0xF);
11181 inst
.instruction
|= cond
<< 22;
11182 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11187 inst
.instruction
= THUMB_OP16(opcode
);
11188 if (cond
== COND_ALWAYS
)
11189 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11192 inst
.instruction
|= cond
<< 8;
11193 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11195 /* Allow section relaxation. */
11196 if (unified_syntax
&& inst
.size_req
!= 2)
11197 inst
.relax
= opcode
;
11199 inst
.reloc
.type
= reloc
;
11200 inst
.reloc
.pc_rel
= 1;
11203 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11204 between the two is the maximum immediate allowed - which is passed in
11207 do_t_bkpt_hlt1 (int range
)
11209 constraint (inst
.cond
!= COND_ALWAYS
,
11210 _("instruction is always unconditional"));
11211 if (inst
.operands
[0].present
)
11213 constraint (inst
.operands
[0].imm
> range
,
11214 _("immediate value out of range"));
11215 inst
.instruction
|= inst
.operands
[0].imm
;
11218 set_it_insn_type (NEUTRAL_IT_INSN
);
11224 do_t_bkpt_hlt1 (63);
11230 do_t_bkpt_hlt1 (255);
11234 do_t_branch23 (void)
11236 set_it_insn_type_last ();
11237 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11239 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11240 this file. We used to simply ignore the PLT reloc type here --
11241 the branch encoding is now needed to deal with TLSCALL relocs.
11242 So if we see a PLT reloc now, put it back to how it used to be to
11243 keep the preexisting behaviour. */
11244 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11245 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11247 #if defined(OBJ_COFF)
11248 /* If the destination of the branch is a defined symbol which does not have
11249 the THUMB_FUNC attribute, then we must be calling a function which has
11250 the (interfacearm) attribute. We look for the Thumb entry point to that
11251 function and change the branch to refer to that function instead. */
11252 if ( inst
.reloc
.exp
.X_op
== O_symbol
11253 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11254 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11255 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11256 inst
.reloc
.exp
.X_add_symbol
=
11257 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11264 set_it_insn_type_last ();
11265 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11266 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11267 should cause the alignment to be checked once it is known. This is
11268 because BX PC only works if the instruction is word aligned. */
11276 set_it_insn_type_last ();
11277 Rm
= inst
.operands
[0].reg
;
11278 reject_bad_reg (Rm
);
11279 inst
.instruction
|= Rm
<< 16;
11288 Rd
= inst
.operands
[0].reg
;
11289 Rm
= inst
.operands
[1].reg
;
11291 reject_bad_reg (Rd
);
11292 reject_bad_reg (Rm
);
11294 inst
.instruction
|= Rd
<< 8;
11295 inst
.instruction
|= Rm
<< 16;
11296 inst
.instruction
|= Rm
;
11302 set_it_insn_type (OUTSIDE_IT_INSN
);
11308 set_it_insn_type (OUTSIDE_IT_INSN
);
11309 inst
.instruction
|= inst
.operands
[0].imm
;
11315 set_it_insn_type (OUTSIDE_IT_INSN
);
11317 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11318 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11320 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11321 inst
.instruction
= 0xf3af8000;
11322 inst
.instruction
|= imod
<< 9;
11323 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11324 if (inst
.operands
[1].present
)
11325 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11330 && (inst
.operands
[0].imm
& 4),
11331 _("selected processor does not support 'A' form "
11332 "of this instruction"));
11333 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11334 _("Thumb does not support the 2-argument "
11335 "form of this instruction"));
11336 inst
.instruction
|= inst
.operands
[0].imm
;
11340 /* THUMB CPY instruction (argument parse). */
11345 if (inst
.size_req
== 4)
11347 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11348 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11349 inst
.instruction
|= inst
.operands
[1].reg
;
11353 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11354 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11355 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11362 set_it_insn_type (OUTSIDE_IT_INSN
);
11363 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11364 inst
.instruction
|= inst
.operands
[0].reg
;
11365 inst
.reloc
.pc_rel
= 1;
11366 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11372 inst
.instruction
|= inst
.operands
[0].imm
;
11378 unsigned Rd
, Rn
, Rm
;
11380 Rd
= inst
.operands
[0].reg
;
11381 Rn
= (inst
.operands
[1].present
11382 ? inst
.operands
[1].reg
: Rd
);
11383 Rm
= inst
.operands
[2].reg
;
11385 reject_bad_reg (Rd
);
11386 reject_bad_reg (Rn
);
11387 reject_bad_reg (Rm
);
11389 inst
.instruction
|= Rd
<< 8;
11390 inst
.instruction
|= Rn
<< 16;
11391 inst
.instruction
|= Rm
;
11397 if (unified_syntax
&& inst
.size_req
== 4)
11398 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11406 unsigned int cond
= inst
.operands
[0].imm
;
11408 set_it_insn_type (IT_INSN
);
11409 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11411 now_it
.warn_deprecated
= FALSE
;
11413 /* If the condition is a negative condition, invert the mask. */
11414 if ((cond
& 0x1) == 0x0)
11416 unsigned int mask
= inst
.instruction
& 0x000f;
11418 if ((mask
& 0x7) == 0)
11420 /* No conversion needed. */
11421 now_it
.block_length
= 1;
11423 else if ((mask
& 0x3) == 0)
11426 now_it
.block_length
= 2;
11428 else if ((mask
& 0x1) == 0)
11431 now_it
.block_length
= 3;
11436 now_it
.block_length
= 4;
11439 inst
.instruction
&= 0xfff0;
11440 inst
.instruction
|= mask
;
11443 inst
.instruction
|= cond
<< 4;
11446 /* Helper function used for both push/pop and ldm/stm. */
11448 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11452 load
= (inst
.instruction
& (1 << 20)) != 0;
11454 if (mask
& (1 << 13))
11455 inst
.error
= _("SP not allowed in register list");
11457 if ((mask
& (1 << base
)) != 0
11459 inst
.error
= _("having the base register in the register list when "
11460 "using write back is UNPREDICTABLE");
11464 if (mask
& (1 << 15))
11466 if (mask
& (1 << 14))
11467 inst
.error
= _("LR and PC should not both be in register list");
11469 set_it_insn_type_last ();
11474 if (mask
& (1 << 15))
11475 inst
.error
= _("PC not allowed in register list");
11478 if ((mask
& (mask
- 1)) == 0)
11480 /* Single register transfers implemented as str/ldr. */
11483 if (inst
.instruction
& (1 << 23))
11484 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11486 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11490 if (inst
.instruction
& (1 << 23))
11491 inst
.instruction
= 0x00800000; /* ia -> [base] */
11493 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11496 inst
.instruction
|= 0xf8400000;
11498 inst
.instruction
|= 0x00100000;
11500 mask
= ffs (mask
) - 1;
11503 else if (writeback
)
11504 inst
.instruction
|= WRITE_BACK
;
11506 inst
.instruction
|= mask
;
11507 inst
.instruction
|= base
<< 16;
11513 /* This really doesn't seem worth it. */
11514 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11515 _("expression too complex"));
11516 constraint (inst
.operands
[1].writeback
,
11517 _("Thumb load/store multiple does not support {reglist}^"));
11519 if (unified_syntax
)
11521 bfd_boolean narrow
;
11525 /* See if we can use a 16-bit instruction. */
11526 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11527 && inst
.size_req
!= 4
11528 && !(inst
.operands
[1].imm
& ~0xff))
11530 mask
= 1 << inst
.operands
[0].reg
;
11532 if (inst
.operands
[0].reg
<= 7)
11534 if (inst
.instruction
== T_MNEM_stmia
11535 ? inst
.operands
[0].writeback
11536 : (inst
.operands
[0].writeback
11537 == !(inst
.operands
[1].imm
& mask
)))
11539 if (inst
.instruction
== T_MNEM_stmia
11540 && (inst
.operands
[1].imm
& mask
)
11541 && (inst
.operands
[1].imm
& (mask
- 1)))
11542 as_warn (_("value stored for r%d is UNKNOWN"),
11543 inst
.operands
[0].reg
);
11545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11546 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11547 inst
.instruction
|= inst
.operands
[1].imm
;
11550 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11552 /* This means 1 register in reg list one of 3 situations:
11553 1. Instruction is stmia, but without writeback.
11554 2. lmdia without writeback, but with Rn not in
11556 3. ldmia with writeback, but with Rn in reglist.
11557 Case 3 is UNPREDICTABLE behaviour, so we handle
11558 case 1 and 2 which can be converted into a 16-bit
11559 str or ldr. The SP cases are handled below. */
11560 unsigned long opcode
;
11561 /* First, record an error for Case 3. */
11562 if (inst
.operands
[1].imm
& mask
11563 && inst
.operands
[0].writeback
)
11565 _("having the base register in the register list when "
11566 "using write back is UNPREDICTABLE");
11568 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11570 inst
.instruction
= THUMB_OP16 (opcode
);
11571 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11572 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11576 else if (inst
.operands
[0] .reg
== REG_SP
)
11578 if (inst
.operands
[0].writeback
)
11581 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11582 ? T_MNEM_push
: T_MNEM_pop
);
11583 inst
.instruction
|= inst
.operands
[1].imm
;
11586 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11589 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11590 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11591 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11599 if (inst
.instruction
< 0xffff)
11600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11602 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11603 inst
.operands
[0].writeback
);
11608 constraint (inst
.operands
[0].reg
> 7
11609 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11610 constraint (inst
.instruction
!= T_MNEM_ldmia
11611 && inst
.instruction
!= T_MNEM_stmia
,
11612 _("Thumb-2 instruction only valid in unified syntax"));
11613 if (inst
.instruction
== T_MNEM_stmia
)
11615 if (!inst
.operands
[0].writeback
)
11616 as_warn (_("this instruction will write back the base register"));
11617 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11618 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11619 as_warn (_("value stored for r%d is UNKNOWN"),
11620 inst
.operands
[0].reg
);
11624 if (!inst
.operands
[0].writeback
11625 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11626 as_warn (_("this instruction will write back the base register"));
11627 else if (inst
.operands
[0].writeback
11628 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11629 as_warn (_("this instruction will not write back the base register"));
11632 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11633 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11634 inst
.instruction
|= inst
.operands
[1].imm
;
11641 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11642 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11643 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11644 || inst
.operands
[1].negative
,
11647 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11649 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11650 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11651 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11657 if (!inst
.operands
[1].present
)
11659 constraint (inst
.operands
[0].reg
== REG_LR
,
11660 _("r14 not allowed as first register "
11661 "when second register is omitted"));
11662 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11664 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11667 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11668 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11669 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11675 unsigned long opcode
;
11678 if (inst
.operands
[0].isreg
11679 && !inst
.operands
[0].preind
11680 && inst
.operands
[0].reg
== REG_PC
)
11681 set_it_insn_type_last ();
11683 opcode
= inst
.instruction
;
11684 if (unified_syntax
)
11686 if (!inst
.operands
[1].isreg
)
11688 if (opcode
<= 0xffff)
11689 inst
.instruction
= THUMB_OP32 (opcode
);
11690 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11693 if (inst
.operands
[1].isreg
11694 && !inst
.operands
[1].writeback
11695 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11696 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11697 && opcode
<= 0xffff
11698 && inst
.size_req
!= 4)
11700 /* Insn may have a 16-bit form. */
11701 Rn
= inst
.operands
[1].reg
;
11702 if (inst
.operands
[1].immisreg
)
11704 inst
.instruction
= THUMB_OP16 (opcode
);
11706 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11708 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11709 reject_bad_reg (inst
.operands
[1].imm
);
11711 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11712 && opcode
!= T_MNEM_ldrsb
)
11713 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11714 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11721 if (inst
.reloc
.pc_rel
)
11722 opcode
= T_MNEM_ldr_pc2
;
11724 opcode
= T_MNEM_ldr_pc
;
11728 if (opcode
== T_MNEM_ldr
)
11729 opcode
= T_MNEM_ldr_sp
;
11731 opcode
= T_MNEM_str_sp
;
11733 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11737 inst
.instruction
= inst
.operands
[0].reg
;
11738 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11740 inst
.instruction
|= THUMB_OP16 (opcode
);
11741 if (inst
.size_req
== 2)
11742 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11744 inst
.relax
= opcode
;
11748 /* Definitely a 32-bit variant. */
11750 /* Warning for Erratum 752419. */
11751 if (opcode
== T_MNEM_ldr
11752 && inst
.operands
[0].reg
== REG_SP
11753 && inst
.operands
[1].writeback
== 1
11754 && !inst
.operands
[1].immisreg
)
11756 if (no_cpu_selected ()
11757 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11758 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11759 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11760 as_warn (_("This instruction may be unpredictable "
11761 "if executed on M-profile cores "
11762 "with interrupts enabled."));
11765 /* Do some validations regarding addressing modes. */
11766 if (inst
.operands
[1].immisreg
)
11767 reject_bad_reg (inst
.operands
[1].imm
);
11769 constraint (inst
.operands
[1].writeback
== 1
11770 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11773 inst
.instruction
= THUMB_OP32 (opcode
);
11774 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11775 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11776 check_ldr_r15_aligned ();
11780 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11782 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11784 /* Only [Rn,Rm] is acceptable. */
11785 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11786 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11787 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11788 || inst
.operands
[1].negative
,
11789 _("Thumb does not support this addressing mode"));
11790 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11794 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11795 if (!inst
.operands
[1].isreg
)
11796 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11799 constraint (!inst
.operands
[1].preind
11800 || inst
.operands
[1].shifted
11801 || inst
.operands
[1].writeback
,
11802 _("Thumb does not support this addressing mode"));
11803 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11805 constraint (inst
.instruction
& 0x0600,
11806 _("byte or halfword not valid for base register"));
11807 constraint (inst
.operands
[1].reg
== REG_PC
11808 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11809 _("r15 based store not allowed"));
11810 constraint (inst
.operands
[1].immisreg
,
11811 _("invalid base register for register offset"));
11813 if (inst
.operands
[1].reg
== REG_PC
)
11814 inst
.instruction
= T_OPCODE_LDR_PC
;
11815 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11816 inst
.instruction
= T_OPCODE_LDR_SP
;
11818 inst
.instruction
= T_OPCODE_STR_SP
;
11820 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11825 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11826 if (!inst
.operands
[1].immisreg
)
11828 /* Immediate offset. */
11829 inst
.instruction
|= inst
.operands
[0].reg
;
11830 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11831 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11835 /* Register offset. */
11836 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11837 constraint (inst
.operands
[1].negative
,
11838 _("Thumb does not support this addressing mode"));
11841 switch (inst
.instruction
)
11843 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11844 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11845 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11846 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11847 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11848 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11849 case 0x5600 /* ldrsb */:
11850 case 0x5e00 /* ldrsh */: break;
11854 inst
.instruction
|= inst
.operands
[0].reg
;
11855 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11856 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11862 if (!inst
.operands
[1].present
)
11864 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11865 constraint (inst
.operands
[0].reg
== REG_LR
,
11866 _("r14 not allowed here"));
11867 constraint (inst
.operands
[0].reg
== REG_R12
,
11868 _("r12 not allowed here"));
11871 if (inst
.operands
[2].writeback
11872 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11873 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11874 as_warn (_("base register written back, and overlaps "
11875 "one of transfer registers"));
11877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11878 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11879 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11885 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11886 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11892 unsigned Rd
, Rn
, Rm
, Ra
;
11894 Rd
= inst
.operands
[0].reg
;
11895 Rn
= inst
.operands
[1].reg
;
11896 Rm
= inst
.operands
[2].reg
;
11897 Ra
= inst
.operands
[3].reg
;
11899 reject_bad_reg (Rd
);
11900 reject_bad_reg (Rn
);
11901 reject_bad_reg (Rm
);
11902 reject_bad_reg (Ra
);
11904 inst
.instruction
|= Rd
<< 8;
11905 inst
.instruction
|= Rn
<< 16;
11906 inst
.instruction
|= Rm
;
11907 inst
.instruction
|= Ra
<< 12;
11913 unsigned RdLo
, RdHi
, Rn
, Rm
;
11915 RdLo
= inst
.operands
[0].reg
;
11916 RdHi
= inst
.operands
[1].reg
;
11917 Rn
= inst
.operands
[2].reg
;
11918 Rm
= inst
.operands
[3].reg
;
11920 reject_bad_reg (RdLo
);
11921 reject_bad_reg (RdHi
);
11922 reject_bad_reg (Rn
);
11923 reject_bad_reg (Rm
);
11925 inst
.instruction
|= RdLo
<< 12;
11926 inst
.instruction
|= RdHi
<< 8;
11927 inst
.instruction
|= Rn
<< 16;
11928 inst
.instruction
|= Rm
;
11932 do_t_mov_cmp (void)
11936 Rn
= inst
.operands
[0].reg
;
11937 Rm
= inst
.operands
[1].reg
;
11940 set_it_insn_type_last ();
11942 if (unified_syntax
)
11944 int r0off
= (inst
.instruction
== T_MNEM_mov
11945 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11946 unsigned long opcode
;
11947 bfd_boolean narrow
;
11948 bfd_boolean low_regs
;
11950 low_regs
= (Rn
<= 7 && Rm
<= 7);
11951 opcode
= inst
.instruction
;
11952 if (in_it_block ())
11953 narrow
= opcode
!= T_MNEM_movs
;
11955 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11956 if (inst
.size_req
== 4
11957 || inst
.operands
[1].shifted
)
11960 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11961 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11962 && !inst
.operands
[1].shifted
11966 inst
.instruction
= T2_SUBS_PC_LR
;
11970 if (opcode
== T_MNEM_cmp
)
11972 constraint (Rn
== REG_PC
, BAD_PC
);
11975 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11977 warn_deprecated_sp (Rm
);
11978 /* R15 was documented as a valid choice for Rm in ARMv6,
11979 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11980 tools reject R15, so we do too. */
11981 constraint (Rm
== REG_PC
, BAD_PC
);
11984 reject_bad_reg (Rm
);
11986 else if (opcode
== T_MNEM_mov
11987 || opcode
== T_MNEM_movs
)
11989 if (inst
.operands
[1].isreg
)
11991 if (opcode
== T_MNEM_movs
)
11993 reject_bad_reg (Rn
);
11994 reject_bad_reg (Rm
);
11998 /* This is mov.n. */
11999 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12000 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12002 as_tsktsk (_("Use of r%u as a source register is "
12003 "deprecated when r%u is the destination "
12004 "register."), Rm
, Rn
);
12009 /* This is mov.w. */
12010 constraint (Rn
== REG_PC
, BAD_PC
);
12011 constraint (Rm
== REG_PC
, BAD_PC
);
12012 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12013 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12017 reject_bad_reg (Rn
);
12020 if (!inst
.operands
[1].isreg
)
12022 /* Immediate operand. */
12023 if (!in_it_block () && opcode
== T_MNEM_mov
)
12025 if (low_regs
&& narrow
)
12027 inst
.instruction
= THUMB_OP16 (opcode
);
12028 inst
.instruction
|= Rn
<< 8;
12029 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12030 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12032 if (inst
.size_req
== 2)
12033 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12035 inst
.relax
= opcode
;
12040 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12041 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12042 THUMB1_RELOC_ONLY
);
12044 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12045 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12046 inst
.instruction
|= Rn
<< r0off
;
12047 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12050 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12051 && (inst
.instruction
== T_MNEM_mov
12052 || inst
.instruction
== T_MNEM_movs
))
12054 /* Register shifts are encoded as separate shift instructions. */
12055 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12057 if (in_it_block ())
12062 if (inst
.size_req
== 4)
12065 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12071 switch (inst
.operands
[1].shift_kind
)
12074 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12077 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12080 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12083 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12089 inst
.instruction
= opcode
;
12092 inst
.instruction
|= Rn
;
12093 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12098 inst
.instruction
|= CONDS_BIT
;
12100 inst
.instruction
|= Rn
<< 8;
12101 inst
.instruction
|= Rm
<< 16;
12102 inst
.instruction
|= inst
.operands
[1].imm
;
12107 /* Some mov with immediate shift have narrow variants.
12108 Register shifts are handled above. */
12109 if (low_regs
&& inst
.operands
[1].shifted
12110 && (inst
.instruction
== T_MNEM_mov
12111 || inst
.instruction
== T_MNEM_movs
))
12113 if (in_it_block ())
12114 narrow
= (inst
.instruction
== T_MNEM_mov
);
12116 narrow
= (inst
.instruction
== T_MNEM_movs
);
12121 switch (inst
.operands
[1].shift_kind
)
12123 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12124 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12125 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12126 default: narrow
= FALSE
; break;
12132 inst
.instruction
|= Rn
;
12133 inst
.instruction
|= Rm
<< 3;
12134 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12138 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12139 inst
.instruction
|= Rn
<< r0off
;
12140 encode_thumb32_shifted_operand (1);
12144 switch (inst
.instruction
)
12147 /* In v4t or v5t a move of two lowregs produces unpredictable
12148 results. Don't allow this. */
12151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12152 "MOV Rd, Rs with two low registers is not "
12153 "permitted on this architecture");
12154 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12158 inst
.instruction
= T_OPCODE_MOV_HR
;
12159 inst
.instruction
|= (Rn
& 0x8) << 4;
12160 inst
.instruction
|= (Rn
& 0x7);
12161 inst
.instruction
|= Rm
<< 3;
12165 /* We know we have low registers at this point.
12166 Generate LSLS Rd, Rs, #0. */
12167 inst
.instruction
= T_OPCODE_LSL_I
;
12168 inst
.instruction
|= Rn
;
12169 inst
.instruction
|= Rm
<< 3;
12175 inst
.instruction
= T_OPCODE_CMP_LR
;
12176 inst
.instruction
|= Rn
;
12177 inst
.instruction
|= Rm
<< 3;
12181 inst
.instruction
= T_OPCODE_CMP_HR
;
12182 inst
.instruction
|= (Rn
& 0x8) << 4;
12183 inst
.instruction
|= (Rn
& 0x7);
12184 inst
.instruction
|= Rm
<< 3;
12191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12193 /* PR 10443: Do not silently ignore shifted operands. */
12194 constraint (inst
.operands
[1].shifted
,
12195 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12197 if (inst
.operands
[1].isreg
)
12199 if (Rn
< 8 && Rm
< 8)
12201 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12202 since a MOV instruction produces unpredictable results. */
12203 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12204 inst
.instruction
= T_OPCODE_ADD_I3
;
12206 inst
.instruction
= T_OPCODE_CMP_LR
;
12208 inst
.instruction
|= Rn
;
12209 inst
.instruction
|= Rm
<< 3;
12213 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12214 inst
.instruction
= T_OPCODE_MOV_HR
;
12216 inst
.instruction
= T_OPCODE_CMP_HR
;
12222 constraint (Rn
> 7,
12223 _("only lo regs allowed with immediate"));
12224 inst
.instruction
|= Rn
<< 8;
12225 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12236 top
= (inst
.instruction
& 0x00800000) != 0;
12237 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12239 constraint (top
, _(":lower16: not allowed in this instruction"));
12240 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12242 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12244 constraint (!top
, _(":upper16: not allowed in this instruction"));
12245 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12248 Rd
= inst
.operands
[0].reg
;
12249 reject_bad_reg (Rd
);
12251 inst
.instruction
|= Rd
<< 8;
12252 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12254 imm
= inst
.reloc
.exp
.X_add_number
;
12255 inst
.instruction
|= (imm
& 0xf000) << 4;
12256 inst
.instruction
|= (imm
& 0x0800) << 15;
12257 inst
.instruction
|= (imm
& 0x0700) << 4;
12258 inst
.instruction
|= (imm
& 0x00ff);
12263 do_t_mvn_tst (void)
12267 Rn
= inst
.operands
[0].reg
;
12268 Rm
= inst
.operands
[1].reg
;
12270 if (inst
.instruction
== T_MNEM_cmp
12271 || inst
.instruction
== T_MNEM_cmn
)
12272 constraint (Rn
== REG_PC
, BAD_PC
);
12274 reject_bad_reg (Rn
);
12275 reject_bad_reg (Rm
);
12277 if (unified_syntax
)
12279 int r0off
= (inst
.instruction
== T_MNEM_mvn
12280 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12281 bfd_boolean narrow
;
12283 if (inst
.size_req
== 4
12284 || inst
.instruction
> 0xffff
12285 || inst
.operands
[1].shifted
12286 || Rn
> 7 || Rm
> 7)
12288 else if (inst
.instruction
== T_MNEM_cmn
12289 || inst
.instruction
== T_MNEM_tst
)
12291 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12292 narrow
= !in_it_block ();
12294 narrow
= in_it_block ();
12296 if (!inst
.operands
[1].isreg
)
12298 /* For an immediate, we always generate a 32-bit opcode;
12299 section relaxation will shrink it later if possible. */
12300 if (inst
.instruction
< 0xffff)
12301 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12302 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12303 inst
.instruction
|= Rn
<< r0off
;
12304 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12308 /* See if we can do this with a 16-bit instruction. */
12311 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12312 inst
.instruction
|= Rn
;
12313 inst
.instruction
|= Rm
<< 3;
12317 constraint (inst
.operands
[1].shifted
12318 && inst
.operands
[1].immisreg
,
12319 _("shift must be constant"));
12320 if (inst
.instruction
< 0xffff)
12321 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12322 inst
.instruction
|= Rn
<< r0off
;
12323 encode_thumb32_shifted_operand (1);
12329 constraint (inst
.instruction
> 0xffff
12330 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12331 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12332 _("unshifted register required"));
12333 constraint (Rn
> 7 || Rm
> 7,
12336 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12337 inst
.instruction
|= Rn
;
12338 inst
.instruction
|= Rm
<< 3;
12347 if (do_vfp_nsyn_mrs () == SUCCESS
)
12350 Rd
= inst
.operands
[0].reg
;
12351 reject_bad_reg (Rd
);
12352 inst
.instruction
|= Rd
<< 8;
12354 if (inst
.operands
[1].isreg
)
12356 unsigned br
= inst
.operands
[1].reg
;
12357 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12358 as_bad (_("bad register for mrs"));
12360 inst
.instruction
|= br
& (0xf << 16);
12361 inst
.instruction
|= (br
& 0x300) >> 4;
12362 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12366 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12368 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12370 /* PR gas/12698: The constraint is only applied for m_profile.
12371 If the user has specified -march=all, we want to ignore it as
12372 we are building for any CPU type, including non-m variants. */
12373 bfd_boolean m_profile
=
12374 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12375 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12376 "not support requested special purpose register"));
12379 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12381 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12382 _("'APSR', 'CPSR' or 'SPSR' expected"));
12384 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12385 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12386 inst
.instruction
|= 0xf0000;
12396 if (do_vfp_nsyn_msr () == SUCCESS
)
12399 constraint (!inst
.operands
[1].isreg
,
12400 _("Thumb encoding does not support an immediate here"));
12402 if (inst
.operands
[0].isreg
)
12403 flags
= (int)(inst
.operands
[0].reg
);
12405 flags
= inst
.operands
[0].imm
;
12407 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12409 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12411 /* PR gas/12698: The constraint is only applied for m_profile.
12412 If the user has specified -march=all, we want to ignore it as
12413 we are building for any CPU type, including non-m variants. */
12414 bfd_boolean m_profile
=
12415 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12416 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12417 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12418 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12419 && bits
!= PSR_f
)) && m_profile
,
12420 _("selected processor does not support requested special "
12421 "purpose register"));
12424 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12425 "requested special purpose register"));
12427 Rn
= inst
.operands
[1].reg
;
12428 reject_bad_reg (Rn
);
12430 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12431 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12432 inst
.instruction
|= (flags
& 0x300) >> 4;
12433 inst
.instruction
|= (flags
& 0xff);
12434 inst
.instruction
|= Rn
<< 16;
12440 bfd_boolean narrow
;
12441 unsigned Rd
, Rn
, Rm
;
12443 if (!inst
.operands
[2].present
)
12444 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12446 Rd
= inst
.operands
[0].reg
;
12447 Rn
= inst
.operands
[1].reg
;
12448 Rm
= inst
.operands
[2].reg
;
12450 if (unified_syntax
)
12452 if (inst
.size_req
== 4
12458 else if (inst
.instruction
== T_MNEM_muls
)
12459 narrow
= !in_it_block ();
12461 narrow
= in_it_block ();
12465 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12466 constraint (Rn
> 7 || Rm
> 7,
12473 /* 16-bit MULS/Conditional MUL. */
12474 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12475 inst
.instruction
|= Rd
;
12478 inst
.instruction
|= Rm
<< 3;
12480 inst
.instruction
|= Rn
<< 3;
12482 constraint (1, _("dest must overlap one source register"));
12486 constraint (inst
.instruction
!= T_MNEM_mul
,
12487 _("Thumb-2 MUL must not set flags"));
12489 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12490 inst
.instruction
|= Rd
<< 8;
12491 inst
.instruction
|= Rn
<< 16;
12492 inst
.instruction
|= Rm
<< 0;
12494 reject_bad_reg (Rd
);
12495 reject_bad_reg (Rn
);
12496 reject_bad_reg (Rm
);
12503 unsigned RdLo
, RdHi
, Rn
, Rm
;
12505 RdLo
= inst
.operands
[0].reg
;
12506 RdHi
= inst
.operands
[1].reg
;
12507 Rn
= inst
.operands
[2].reg
;
12508 Rm
= inst
.operands
[3].reg
;
12510 reject_bad_reg (RdLo
);
12511 reject_bad_reg (RdHi
);
12512 reject_bad_reg (Rn
);
12513 reject_bad_reg (Rm
);
12515 inst
.instruction
|= RdLo
<< 12;
12516 inst
.instruction
|= RdHi
<< 8;
12517 inst
.instruction
|= Rn
<< 16;
12518 inst
.instruction
|= Rm
;
12521 as_tsktsk (_("rdhi and rdlo must be different"));
12527 set_it_insn_type (NEUTRAL_IT_INSN
);
12529 if (unified_syntax
)
12531 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12533 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12534 inst
.instruction
|= inst
.operands
[0].imm
;
12538 /* PR9722: Check for Thumb2 availability before
12539 generating a thumb2 nop instruction. */
12540 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12542 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12543 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12546 inst
.instruction
= 0x46c0;
12551 constraint (inst
.operands
[0].present
,
12552 _("Thumb does not support NOP with hints"));
12553 inst
.instruction
= 0x46c0;
12560 if (unified_syntax
)
12562 bfd_boolean narrow
;
12564 if (THUMB_SETS_FLAGS (inst
.instruction
))
12565 narrow
= !in_it_block ();
12567 narrow
= in_it_block ();
12568 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12570 if (inst
.size_req
== 4)
12575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12576 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12577 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12581 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12582 inst
.instruction
|= inst
.operands
[0].reg
;
12583 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12588 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12590 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12592 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12593 inst
.instruction
|= inst
.operands
[0].reg
;
12594 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12603 Rd
= inst
.operands
[0].reg
;
12604 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12606 reject_bad_reg (Rd
);
12607 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12608 reject_bad_reg (Rn
);
12610 inst
.instruction
|= Rd
<< 8;
12611 inst
.instruction
|= Rn
<< 16;
12613 if (!inst
.operands
[2].isreg
)
12615 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12616 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12622 Rm
= inst
.operands
[2].reg
;
12623 reject_bad_reg (Rm
);
12625 constraint (inst
.operands
[2].shifted
12626 && inst
.operands
[2].immisreg
,
12627 _("shift must be constant"));
12628 encode_thumb32_shifted_operand (2);
12635 unsigned Rd
, Rn
, Rm
;
12637 Rd
= inst
.operands
[0].reg
;
12638 Rn
= inst
.operands
[1].reg
;
12639 Rm
= inst
.operands
[2].reg
;
12641 reject_bad_reg (Rd
);
12642 reject_bad_reg (Rn
);
12643 reject_bad_reg (Rm
);
12645 inst
.instruction
|= Rd
<< 8;
12646 inst
.instruction
|= Rn
<< 16;
12647 inst
.instruction
|= Rm
;
12648 if (inst
.operands
[3].present
)
12650 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12651 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12652 _("expression too complex"));
12653 inst
.instruction
|= (val
& 0x1c) << 10;
12654 inst
.instruction
|= (val
& 0x03) << 6;
12661 if (!inst
.operands
[3].present
)
12665 inst
.instruction
&= ~0x00000020;
12667 /* PR 10168. Swap the Rm and Rn registers. */
12668 Rtmp
= inst
.operands
[1].reg
;
12669 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12670 inst
.operands
[2].reg
= Rtmp
;
12678 if (inst
.operands
[0].immisreg
)
12679 reject_bad_reg (inst
.operands
[0].imm
);
12681 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12685 do_t_push_pop (void)
12689 constraint (inst
.operands
[0].writeback
,
12690 _("push/pop do not support {reglist}^"));
12691 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12692 _("expression too complex"));
12694 mask
= inst
.operands
[0].imm
;
12695 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12696 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12697 else if (inst
.size_req
!= 4
12698 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12699 ? REG_LR
: REG_PC
)))
12701 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12702 inst
.instruction
|= THUMB_PP_PC_LR
;
12703 inst
.instruction
|= mask
& 0xff;
12705 else if (unified_syntax
)
12707 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12708 encode_thumb2_ldmstm (13, mask
, TRUE
);
12712 inst
.error
= _("invalid register list to push/pop instruction");
12722 Rd
= inst
.operands
[0].reg
;
12723 Rm
= inst
.operands
[1].reg
;
12725 reject_bad_reg (Rd
);
12726 reject_bad_reg (Rm
);
12728 inst
.instruction
|= Rd
<< 8;
12729 inst
.instruction
|= Rm
<< 16;
12730 inst
.instruction
|= Rm
;
12738 Rd
= inst
.operands
[0].reg
;
12739 Rm
= inst
.operands
[1].reg
;
12741 reject_bad_reg (Rd
);
12742 reject_bad_reg (Rm
);
12744 if (Rd
<= 7 && Rm
<= 7
12745 && inst
.size_req
!= 4)
12747 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12748 inst
.instruction
|= Rd
;
12749 inst
.instruction
|= Rm
<< 3;
12751 else if (unified_syntax
)
12753 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12754 inst
.instruction
|= Rd
<< 8;
12755 inst
.instruction
|= Rm
<< 16;
12756 inst
.instruction
|= Rm
;
12759 inst
.error
= BAD_HIREG
;
12767 Rd
= inst
.operands
[0].reg
;
12768 Rm
= inst
.operands
[1].reg
;
12770 reject_bad_reg (Rd
);
12771 reject_bad_reg (Rm
);
12773 inst
.instruction
|= Rd
<< 8;
12774 inst
.instruction
|= Rm
;
12782 Rd
= inst
.operands
[0].reg
;
12783 Rs
= (inst
.operands
[1].present
12784 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12785 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12787 reject_bad_reg (Rd
);
12788 reject_bad_reg (Rs
);
12789 if (inst
.operands
[2].isreg
)
12790 reject_bad_reg (inst
.operands
[2].reg
);
12792 inst
.instruction
|= Rd
<< 8;
12793 inst
.instruction
|= Rs
<< 16;
12794 if (!inst
.operands
[2].isreg
)
12796 bfd_boolean narrow
;
12798 if ((inst
.instruction
& 0x00100000) != 0)
12799 narrow
= !in_it_block ();
12801 narrow
= in_it_block ();
12803 if (Rd
> 7 || Rs
> 7)
12806 if (inst
.size_req
== 4 || !unified_syntax
)
12809 if (inst
.reloc
.exp
.X_op
!= O_constant
12810 || inst
.reloc
.exp
.X_add_number
!= 0)
12813 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12814 relaxation, but it doesn't seem worth the hassle. */
12817 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12818 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12819 inst
.instruction
|= Rs
<< 3;
12820 inst
.instruction
|= Rd
;
12824 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12825 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12829 encode_thumb32_shifted_operand (2);
12835 if (warn_on_deprecated
12836 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12837 as_tsktsk (_("setend use is deprecated for ARMv8"));
12839 set_it_insn_type (OUTSIDE_IT_INSN
);
12840 if (inst
.operands
[0].imm
)
12841 inst
.instruction
|= 0x8;
12847 if (!inst
.operands
[1].present
)
12848 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12850 if (unified_syntax
)
12852 bfd_boolean narrow
;
12855 switch (inst
.instruction
)
12858 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12860 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12862 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12864 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12868 if (THUMB_SETS_FLAGS (inst
.instruction
))
12869 narrow
= !in_it_block ();
12871 narrow
= in_it_block ();
12872 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12874 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12876 if (inst
.operands
[2].isreg
12877 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12878 || inst
.operands
[2].reg
> 7))
12880 if (inst
.size_req
== 4)
12883 reject_bad_reg (inst
.operands
[0].reg
);
12884 reject_bad_reg (inst
.operands
[1].reg
);
12888 if (inst
.operands
[2].isreg
)
12890 reject_bad_reg (inst
.operands
[2].reg
);
12891 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12892 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12893 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12894 inst
.instruction
|= inst
.operands
[2].reg
;
12896 /* PR 12854: Error on extraneous shifts. */
12897 constraint (inst
.operands
[2].shifted
,
12898 _("extraneous shift as part of operand to shift insn"));
12902 inst
.operands
[1].shifted
= 1;
12903 inst
.operands
[1].shift_kind
= shift_kind
;
12904 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12905 ? T_MNEM_movs
: T_MNEM_mov
);
12906 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12907 encode_thumb32_shifted_operand (1);
12908 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12909 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12914 if (inst
.operands
[2].isreg
)
12916 switch (shift_kind
)
12918 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12919 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12920 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12921 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12925 inst
.instruction
|= inst
.operands
[0].reg
;
12926 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12928 /* PR 12854: Error on extraneous shifts. */
12929 constraint (inst
.operands
[2].shifted
,
12930 _("extraneous shift as part of operand to shift insn"));
12934 switch (shift_kind
)
12936 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12937 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12938 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12941 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12942 inst
.instruction
|= inst
.operands
[0].reg
;
12943 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12949 constraint (inst
.operands
[0].reg
> 7
12950 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12951 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12953 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12955 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12956 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12957 _("source1 and dest must be same register"));
12959 switch (inst
.instruction
)
12961 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12962 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12963 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12964 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12968 inst
.instruction
|= inst
.operands
[0].reg
;
12969 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12971 /* PR 12854: Error on extraneous shifts. */
12972 constraint (inst
.operands
[2].shifted
,
12973 _("extraneous shift as part of operand to shift insn"));
12977 switch (inst
.instruction
)
12979 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12980 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12981 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12982 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12985 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12986 inst
.instruction
|= inst
.operands
[0].reg
;
12987 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12995 unsigned Rd
, Rn
, Rm
;
12997 Rd
= inst
.operands
[0].reg
;
12998 Rn
= inst
.operands
[1].reg
;
12999 Rm
= inst
.operands
[2].reg
;
13001 reject_bad_reg (Rd
);
13002 reject_bad_reg (Rn
);
13003 reject_bad_reg (Rm
);
13005 inst
.instruction
|= Rd
<< 8;
13006 inst
.instruction
|= Rn
<< 16;
13007 inst
.instruction
|= Rm
;
13013 unsigned Rd
, Rn
, Rm
;
13015 Rd
= inst
.operands
[0].reg
;
13016 Rm
= inst
.operands
[1].reg
;
13017 Rn
= inst
.operands
[2].reg
;
13019 reject_bad_reg (Rd
);
13020 reject_bad_reg (Rn
);
13021 reject_bad_reg (Rm
);
13023 inst
.instruction
|= Rd
<< 8;
13024 inst
.instruction
|= Rn
<< 16;
13025 inst
.instruction
|= Rm
;
13031 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13033 _("SMC is not permitted on this architecture"));
13034 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13035 _("expression too complex"));
13036 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13037 inst
.instruction
|= (value
& 0xf000) >> 12;
13038 inst
.instruction
|= (value
& 0x0ff0);
13039 inst
.instruction
|= (value
& 0x000f) << 16;
13040 /* PR gas/15623: SMC instructions must be last in an IT block. */
13041 set_it_insn_type_last ();
13047 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13049 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13050 inst
.instruction
|= (value
& 0x0fff);
13051 inst
.instruction
|= (value
& 0xf000) << 4;
13055 do_t_ssat_usat (int bias
)
13059 Rd
= inst
.operands
[0].reg
;
13060 Rn
= inst
.operands
[2].reg
;
13062 reject_bad_reg (Rd
);
13063 reject_bad_reg (Rn
);
13065 inst
.instruction
|= Rd
<< 8;
13066 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13067 inst
.instruction
|= Rn
<< 16;
13069 if (inst
.operands
[3].present
)
13071 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13073 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13075 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13076 _("expression too complex"));
13078 if (shift_amount
!= 0)
13080 constraint (shift_amount
> 31,
13081 _("shift expression is too large"));
13083 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13084 inst
.instruction
|= 0x00200000; /* sh bit. */
13086 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13087 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13095 do_t_ssat_usat (1);
13103 Rd
= inst
.operands
[0].reg
;
13104 Rn
= inst
.operands
[2].reg
;
13106 reject_bad_reg (Rd
);
13107 reject_bad_reg (Rn
);
13109 inst
.instruction
|= Rd
<< 8;
13110 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13111 inst
.instruction
|= Rn
<< 16;
13117 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13118 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13119 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13120 || inst
.operands
[2].negative
,
13123 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13125 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13126 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13127 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13128 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13134 if (!inst
.operands
[2].present
)
13135 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13137 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13138 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13139 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13142 inst
.instruction
|= inst
.operands
[0].reg
;
13143 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13144 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13145 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13151 unsigned Rd
, Rn
, Rm
;
13153 Rd
= inst
.operands
[0].reg
;
13154 Rn
= inst
.operands
[1].reg
;
13155 Rm
= inst
.operands
[2].reg
;
13157 reject_bad_reg (Rd
);
13158 reject_bad_reg (Rn
);
13159 reject_bad_reg (Rm
);
13161 inst
.instruction
|= Rd
<< 8;
13162 inst
.instruction
|= Rn
<< 16;
13163 inst
.instruction
|= Rm
;
13164 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13172 Rd
= inst
.operands
[0].reg
;
13173 Rm
= inst
.operands
[1].reg
;
13175 reject_bad_reg (Rd
);
13176 reject_bad_reg (Rm
);
13178 if (inst
.instruction
<= 0xffff
13179 && inst
.size_req
!= 4
13180 && Rd
<= 7 && Rm
<= 7
13181 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13183 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13184 inst
.instruction
|= Rd
;
13185 inst
.instruction
|= Rm
<< 3;
13187 else if (unified_syntax
)
13189 if (inst
.instruction
<= 0xffff)
13190 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13191 inst
.instruction
|= Rd
<< 8;
13192 inst
.instruction
|= Rm
;
13193 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13197 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13198 _("Thumb encoding does not support rotation"));
13199 constraint (1, BAD_HIREG
);
13206 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13215 half
= (inst
.instruction
& 0x10) != 0;
13216 set_it_insn_type_last ();
13217 constraint (inst
.operands
[0].immisreg
,
13218 _("instruction requires register index"));
13220 Rn
= inst
.operands
[0].reg
;
13221 Rm
= inst
.operands
[0].imm
;
13223 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13224 constraint (Rn
== REG_SP
, BAD_SP
);
13225 reject_bad_reg (Rm
);
13227 constraint (!half
&& inst
.operands
[0].shifted
,
13228 _("instruction does not allow shifted index"));
13229 inst
.instruction
|= (Rn
<< 16) | Rm
;
13235 if (!inst
.operands
[0].present
)
13236 inst
.operands
[0].imm
= 0;
13238 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13240 constraint (inst
.size_req
== 2,
13241 _("immediate value out of range"));
13242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13243 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13244 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13248 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13249 inst
.instruction
|= inst
.operands
[0].imm
;
13252 set_it_insn_type (NEUTRAL_IT_INSN
);
13259 do_t_ssat_usat (0);
13267 Rd
= inst
.operands
[0].reg
;
13268 Rn
= inst
.operands
[2].reg
;
13270 reject_bad_reg (Rd
);
13271 reject_bad_reg (Rn
);
13273 inst
.instruction
|= Rd
<< 8;
13274 inst
.instruction
|= inst
.operands
[1].imm
;
13275 inst
.instruction
|= Rn
<< 16;
13278 /* Checking the range of the branch offset (VAL) with NBITS bits
13279 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13281 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13283 gas_assert (nbits
> 0 && nbits
<= 32);
13286 int cmp
= (1 << (nbits
- 1));
13287 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13292 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13298 /* Neon instruction encoder helpers. */
13300 /* Encodings for the different types for various Neon opcodes. */
13302 /* An "invalid" code for the following tables. */
13305 struct neon_tab_entry
13308 unsigned float_or_poly
;
13309 unsigned scalar_or_imm
;
13312 /* Map overloaded Neon opcodes to their respective encodings. */
13313 #define NEON_ENC_TAB \
13314 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13315 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13316 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13317 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13318 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13319 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13320 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13321 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13322 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13323 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13324 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13325 /* Register variants of the following two instructions are encoded as
13326 vcge / vcgt with the operands reversed. */ \
13327 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13328 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13329 X(vfma, N_INV, 0x0000c10, N_INV), \
13330 X(vfms, N_INV, 0x0200c10, N_INV), \
13331 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13332 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13333 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13334 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13335 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13336 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13337 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13338 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13339 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13340 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13341 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13342 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13343 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13344 X(vshl, 0x0000400, N_INV, 0x0800510), \
13345 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13346 X(vand, 0x0000110, N_INV, 0x0800030), \
13347 X(vbic, 0x0100110, N_INV, 0x0800030), \
13348 X(veor, 0x1000110, N_INV, N_INV), \
13349 X(vorn, 0x0300110, N_INV, 0x0800010), \
13350 X(vorr, 0x0200110, N_INV, 0x0800010), \
13351 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13352 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13353 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13354 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13355 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13356 X(vst1, 0x0000000, 0x0800000, N_INV), \
13357 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13358 X(vst2, 0x0000100, 0x0800100, N_INV), \
13359 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13360 X(vst3, 0x0000200, 0x0800200, N_INV), \
13361 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13362 X(vst4, 0x0000300, 0x0800300, N_INV), \
13363 X(vmovn, 0x1b20200, N_INV, N_INV), \
13364 X(vtrn, 0x1b20080, N_INV, N_INV), \
13365 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13366 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13367 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13368 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13369 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13370 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13371 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13372 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13373 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13374 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13375 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13376 X(vseleq, 0xe000a00, N_INV, N_INV), \
13377 X(vselvs, 0xe100a00, N_INV, N_INV), \
13378 X(vselge, 0xe200a00, N_INV, N_INV), \
13379 X(vselgt, 0xe300a00, N_INV, N_INV), \
13380 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13381 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13382 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13383 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13384 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13385 X(aes, 0x3b00300, N_INV, N_INV), \
13386 X(sha3op, 0x2000c00, N_INV, N_INV), \
13387 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13388 X(sha2op, 0x3ba0380, N_INV, N_INV)
13392 #define X(OPC,I,F,S) N_MNEM_##OPC
13397 static const struct neon_tab_entry neon_enc_tab
[] =
13399 #define X(OPC,I,F,S) { (I), (F), (S) }
13404 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13405 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13406 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13407 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13408 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13409 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13410 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13411 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13412 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13413 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13414 #define NEON_ENC_SINGLE_(X) \
13415 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13416 #define NEON_ENC_DOUBLE_(X) \
13417 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13418 #define NEON_ENC_FPV8_(X) \
13419 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13421 #define NEON_ENCODE(type, inst) \
13424 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13425 inst.is_neon = 1; \
13429 #define check_neon_suffixes \
13432 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13434 as_bad (_("invalid neon suffix for non neon instruction")); \
13440 /* Define shapes for instruction operands. The following mnemonic characters
13441 are used in this table:
13443 F - VFP S<n> register
13444 D - Neon D<n> register
13445 Q - Neon Q<n> register
13449 L - D<n> register list
13451 This table is used to generate various data:
13452 - enumerations of the form NS_DDR to be used as arguments to
13454 - a table classifying shapes into single, double, quad, mixed.
13455 - a table used to drive neon_select_shape. */
13457 #define NEON_SHAPE_DEF \
13458 X(3, (D, D, D), DOUBLE), \
13459 X(3, (Q, Q, Q), QUAD), \
13460 X(3, (D, D, I), DOUBLE), \
13461 X(3, (Q, Q, I), QUAD), \
13462 X(3, (D, D, S), DOUBLE), \
13463 X(3, (Q, Q, S), QUAD), \
13464 X(2, (D, D), DOUBLE), \
13465 X(2, (Q, Q), QUAD), \
13466 X(2, (D, S), DOUBLE), \
13467 X(2, (Q, S), QUAD), \
13468 X(2, (D, R), DOUBLE), \
13469 X(2, (Q, R), QUAD), \
13470 X(2, (D, I), DOUBLE), \
13471 X(2, (Q, I), QUAD), \
13472 X(3, (D, L, D), DOUBLE), \
13473 X(2, (D, Q), MIXED), \
13474 X(2, (Q, D), MIXED), \
13475 X(3, (D, Q, I), MIXED), \
13476 X(3, (Q, D, I), MIXED), \
13477 X(3, (Q, D, D), MIXED), \
13478 X(3, (D, Q, Q), MIXED), \
13479 X(3, (Q, Q, D), MIXED), \
13480 X(3, (Q, D, S), MIXED), \
13481 X(3, (D, Q, S), MIXED), \
13482 X(4, (D, D, D, I), DOUBLE), \
13483 X(4, (Q, Q, Q, I), QUAD), \
13484 X(4, (D, D, S, I), DOUBLE), \
13485 X(4, (Q, Q, S, I), QUAD), \
13486 X(2, (F, F), SINGLE), \
13487 X(3, (F, F, F), SINGLE), \
13488 X(2, (F, I), SINGLE), \
13489 X(2, (F, D), MIXED), \
13490 X(2, (D, F), MIXED), \
13491 X(3, (F, F, I), MIXED), \
13492 X(4, (R, R, F, F), SINGLE), \
13493 X(4, (F, F, R, R), SINGLE), \
13494 X(3, (D, R, R), DOUBLE), \
13495 X(3, (R, R, D), DOUBLE), \
13496 X(2, (S, R), SINGLE), \
13497 X(2, (R, S), SINGLE), \
13498 X(2, (F, R), SINGLE), \
13499 X(2, (R, F), SINGLE), \
13500 /* Half float shape supported so far. */\
13501 X (2, (H, D), MIXED), \
13502 X (2, (D, H), MIXED), \
13503 X (2, (H, F), MIXED), \
13504 X (2, (F, H), MIXED), \
13505 X (2, (H, H), HALF), \
13506 X (2, (H, R), HALF), \
13507 X (2, (R, H), HALF), \
13508 X (2, (H, I), HALF), \
13509 X (3, (H, H, H), HALF), \
13510 X (3, (H, F, I), MIXED), \
13511 X (3, (F, H, I), MIXED), \
13512 X (3, (D, H, H), MIXED), \
13513 X (3, (D, H, S), MIXED)
13515 #define S2(A,B) NS_##A##B
13516 #define S3(A,B,C) NS_##A##B##C
13517 #define S4(A,B,C,D) NS_##A##B##C##D
13519 #define X(N, L, C) S##N L
13532 enum neon_shape_class
13541 #define X(N, L, C) SC_##C
13543 static enum neon_shape_class neon_shape_class
[] =
13562 /* Register widths of above. */
13563 static unsigned neon_shape_el_size
[] =
13575 struct neon_shape_info
13578 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13581 #define S2(A,B) { SE_##A, SE_##B }
13582 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13583 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13585 #define X(N, L, C) { N, S##N L }
13587 static struct neon_shape_info neon_shape_tab
[] =
13597 /* Bit masks used in type checking given instructions.
13598 'N_EQK' means the type must be the same as (or based on in some way) the key
13599 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13600 set, various other bits can be set as well in order to modify the meaning of
13601 the type constraint. */
13603 enum neon_type_mask
13627 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13628 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13629 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13630 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13631 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13632 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13633 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13634 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13635 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13636 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13637 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13639 N_MAX_NONSPECIAL
= N_P64
13642 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13644 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13645 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13646 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13647 #define N_S_32 (N_S8 | N_S16 | N_S32)
13648 #define N_F_16_32 (N_F16 | N_F32)
13649 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13650 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13651 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13652 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13654 /* Pass this as the first type argument to neon_check_type to ignore types
13656 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13658 /* Select a "shape" for the current instruction (describing register types or
13659 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13660 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13661 function of operand parsing, so this function doesn't need to be called.
13662 Shapes should be listed in order of decreasing length. */
13664 static enum neon_shape
13665 neon_select_shape (enum neon_shape shape
, ...)
13668 enum neon_shape first_shape
= shape
;
13670 /* Fix missing optional operands. FIXME: we don't know at this point how
13671 many arguments we should have, so this makes the assumption that we have
13672 > 1. This is true of all current Neon opcodes, I think, but may not be
13673 true in the future. */
13674 if (!inst
.operands
[1].present
)
13675 inst
.operands
[1] = inst
.operands
[0];
13677 va_start (ap
, shape
);
13679 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13684 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13686 if (!inst
.operands
[j
].present
)
13692 switch (neon_shape_tab
[shape
].el
[j
])
13694 /* If a .f16, .16, .u16, .s16 type specifier is given over
13695 a VFP single precision register operand, it's essentially
13696 means only half of the register is used.
13698 If the type specifier is given after the mnemonics, the
13699 information is stored in inst.vectype. If the type specifier
13700 is given after register operand, the information is stored
13701 in inst.operands[].vectype.
13703 When there is only one type specifier, and all the register
13704 operands are the same type of hardware register, the type
13705 specifier applies to all register operands.
13707 If no type specifier is given, the shape is inferred from
13708 operand information.
13711 vadd.f16 s0, s1, s2: NS_HHH
13712 vabs.f16 s0, s1: NS_HH
13713 vmov.f16 s0, r1: NS_HR
13714 vmov.f16 r0, s1: NS_RH
13715 vcvt.f16 r0, s1: NS_RH
13716 vcvt.f16.s32 s2, s2, #29: NS_HFI
13717 vcvt.f16.s32 s2, s2: NS_HF
13720 if (!(inst
.operands
[j
].isreg
13721 && inst
.operands
[j
].isvec
13722 && inst
.operands
[j
].issingle
13723 && !inst
.operands
[j
].isquad
13724 && ((inst
.vectype
.elems
== 1
13725 && inst
.vectype
.el
[0].size
== 16)
13726 || (inst
.vectype
.elems
> 1
13727 && inst
.vectype
.el
[j
].size
== 16)
13728 || (inst
.vectype
.elems
== 0
13729 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13730 && inst
.operands
[j
].vectype
.size
== 16))))
13735 if (!(inst
.operands
[j
].isreg
13736 && inst
.operands
[j
].isvec
13737 && inst
.operands
[j
].issingle
13738 && !inst
.operands
[j
].isquad
13739 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13740 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13741 || (inst
.vectype
.elems
== 0
13742 && (inst
.operands
[j
].vectype
.size
== 32
13743 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13748 if (!(inst
.operands
[j
].isreg
13749 && inst
.operands
[j
].isvec
13750 && !inst
.operands
[j
].isquad
13751 && !inst
.operands
[j
].issingle
))
13756 if (!(inst
.operands
[j
].isreg
13757 && !inst
.operands
[j
].isvec
))
13762 if (!(inst
.operands
[j
].isreg
13763 && inst
.operands
[j
].isvec
13764 && inst
.operands
[j
].isquad
13765 && !inst
.operands
[j
].issingle
))
13770 if (!(!inst
.operands
[j
].isreg
13771 && !inst
.operands
[j
].isscalar
))
13776 if (!(!inst
.operands
[j
].isreg
13777 && inst
.operands
[j
].isscalar
))
13787 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13788 /* We've matched all the entries in the shape table, and we don't
13789 have any left over operands which have not been matched. */
13795 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13796 first_error (_("invalid instruction shape"));
13801 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13802 means the Q bit should be set). */
13805 neon_quad (enum neon_shape shape
)
13807 return neon_shape_class
[shape
] == SC_QUAD
;
13811 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13814 /* Allow modification to be made to types which are constrained to be
13815 based on the key element, based on bits set alongside N_EQK. */
13816 if ((typebits
& N_EQK
) != 0)
13818 if ((typebits
& N_HLF
) != 0)
13820 else if ((typebits
& N_DBL
) != 0)
13822 if ((typebits
& N_SGN
) != 0)
13823 *g_type
= NT_signed
;
13824 else if ((typebits
& N_UNS
) != 0)
13825 *g_type
= NT_unsigned
;
13826 else if ((typebits
& N_INT
) != 0)
13827 *g_type
= NT_integer
;
13828 else if ((typebits
& N_FLT
) != 0)
13829 *g_type
= NT_float
;
13830 else if ((typebits
& N_SIZ
) != 0)
13831 *g_type
= NT_untyped
;
13835 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13836 operand type, i.e. the single type specified in a Neon instruction when it
13837 is the only one given. */
13839 static struct neon_type_el
13840 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13842 struct neon_type_el dest
= *key
;
13844 gas_assert ((thisarg
& N_EQK
) != 0);
13846 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13851 /* Convert Neon type and size into compact bitmask representation. */
13853 static enum neon_type_mask
13854 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13861 case 8: return N_8
;
13862 case 16: return N_16
;
13863 case 32: return N_32
;
13864 case 64: return N_64
;
13872 case 8: return N_I8
;
13873 case 16: return N_I16
;
13874 case 32: return N_I32
;
13875 case 64: return N_I64
;
13883 case 16: return N_F16
;
13884 case 32: return N_F32
;
13885 case 64: return N_F64
;
13893 case 8: return N_P8
;
13894 case 16: return N_P16
;
13895 case 64: return N_P64
;
13903 case 8: return N_S8
;
13904 case 16: return N_S16
;
13905 case 32: return N_S32
;
13906 case 64: return N_S64
;
13914 case 8: return N_U8
;
13915 case 16: return N_U16
;
13916 case 32: return N_U32
;
13917 case 64: return N_U64
;
13928 /* Convert compact Neon bitmask type representation to a type and size. Only
13929 handles the case where a single bit is set in the mask. */
13932 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13933 enum neon_type_mask mask
)
13935 if ((mask
& N_EQK
) != 0)
13938 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13940 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13942 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13944 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13949 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13951 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13952 *type
= NT_unsigned
;
13953 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13954 *type
= NT_integer
;
13955 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13956 *type
= NT_untyped
;
13957 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13959 else if ((mask
& (N_F_ALL
)) != 0)
13967 /* Modify a bitmask of allowed types. This is only needed for type
13971 modify_types_allowed (unsigned allowed
, unsigned mods
)
13974 enum neon_el_type type
;
13980 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13982 if (el_type_of_type_chk (&type
, &size
,
13983 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13985 neon_modify_type_size (mods
, &type
, &size
);
13986 destmask
|= type_chk_of_el_type (type
, size
);
13993 /* Check type and return type classification.
13994 The manual states (paraphrase): If one datatype is given, it indicates the
13996 - the second operand, if there is one
13997 - the operand, if there is no second operand
13998 - the result, if there are no operands.
13999 This isn't quite good enough though, so we use a concept of a "key" datatype
14000 which is set on a per-instruction basis, which is the one which matters when
14001 only one data type is written.
14002 Note: this function has side-effects (e.g. filling in missing operands). All
14003 Neon instructions should call it before performing bit encoding. */
14005 static struct neon_type_el
14006 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14009 unsigned i
, pass
, key_el
= 0;
14010 unsigned types
[NEON_MAX_TYPE_ELS
];
14011 enum neon_el_type k_type
= NT_invtype
;
14012 unsigned k_size
= -1u;
14013 struct neon_type_el badtype
= {NT_invtype
, -1};
14014 unsigned key_allowed
= 0;
14016 /* Optional registers in Neon instructions are always (not) in operand 1.
14017 Fill in the missing operand here, if it was omitted. */
14018 if (els
> 1 && !inst
.operands
[1].present
)
14019 inst
.operands
[1] = inst
.operands
[0];
14021 /* Suck up all the varargs. */
14023 for (i
= 0; i
< els
; i
++)
14025 unsigned thisarg
= va_arg (ap
, unsigned);
14026 if (thisarg
== N_IGNORE_TYPE
)
14031 types
[i
] = thisarg
;
14032 if ((thisarg
& N_KEY
) != 0)
14037 if (inst
.vectype
.elems
> 0)
14038 for (i
= 0; i
< els
; i
++)
14039 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14041 first_error (_("types specified in both the mnemonic and operands"));
14045 /* Duplicate inst.vectype elements here as necessary.
14046 FIXME: No idea if this is exactly the same as the ARM assembler,
14047 particularly when an insn takes one register and one non-register
14049 if (inst
.vectype
.elems
== 1 && els
> 1)
14052 inst
.vectype
.elems
= els
;
14053 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14054 for (j
= 0; j
< els
; j
++)
14056 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14059 else if (inst
.vectype
.elems
== 0 && els
> 0)
14062 /* No types were given after the mnemonic, so look for types specified
14063 after each operand. We allow some flexibility here; as long as the
14064 "key" operand has a type, we can infer the others. */
14065 for (j
= 0; j
< els
; j
++)
14066 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14067 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14069 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14071 for (j
= 0; j
< els
; j
++)
14072 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14073 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14078 first_error (_("operand types can't be inferred"));
14082 else if (inst
.vectype
.elems
!= els
)
14084 first_error (_("type specifier has the wrong number of parts"));
14088 for (pass
= 0; pass
< 2; pass
++)
14090 for (i
= 0; i
< els
; i
++)
14092 unsigned thisarg
= types
[i
];
14093 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14094 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14095 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14096 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14098 /* Decay more-specific signed & unsigned types to sign-insensitive
14099 integer types if sign-specific variants are unavailable. */
14100 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14101 && (types_allowed
& N_SU_ALL
) == 0)
14102 g_type
= NT_integer
;
14104 /* If only untyped args are allowed, decay any more specific types to
14105 them. Some instructions only care about signs for some element
14106 sizes, so handle that properly. */
14107 if (((types_allowed
& N_UNT
) == 0)
14108 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14109 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14110 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14111 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14112 g_type
= NT_untyped
;
14116 if ((thisarg
& N_KEY
) != 0)
14120 key_allowed
= thisarg
& ~N_KEY
;
14122 /* Check architecture constraint on FP16 extension. */
14124 && k_type
== NT_float
14125 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14127 inst
.error
= _(BAD_FP16
);
14134 if ((thisarg
& N_VFP
) != 0)
14136 enum neon_shape_el regshape
;
14137 unsigned regwidth
, match
;
14139 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14142 first_error (_("invalid instruction shape"));
14145 regshape
= neon_shape_tab
[ns
].el
[i
];
14146 regwidth
= neon_shape_el_size
[regshape
];
14148 /* In VFP mode, operands must match register widths. If we
14149 have a key operand, use its width, else use the width of
14150 the current operand. */
14156 /* FP16 will use a single precision register. */
14157 if (regwidth
== 32 && match
== 16)
14159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14163 inst
.error
= _(BAD_FP16
);
14168 if (regwidth
!= match
)
14170 first_error (_("operand size must match register width"));
14175 if ((thisarg
& N_EQK
) == 0)
14177 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14179 if ((given_type
& types_allowed
) == 0)
14181 first_error (_("bad type in Neon instruction"));
14187 enum neon_el_type mod_k_type
= k_type
;
14188 unsigned mod_k_size
= k_size
;
14189 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14190 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14192 first_error (_("inconsistent types in Neon instruction"));
14200 return inst
.vectype
.el
[key_el
];
14203 /* Neon-style VFP instruction forwarding. */
14205 /* Thumb VFP instructions have 0xE in the condition field. */
14208 do_vfp_cond_or_thumb (void)
14213 inst
.instruction
|= 0xe0000000;
14215 inst
.instruction
|= inst
.cond
<< 28;
14218 /* Look up and encode a simple mnemonic, for use as a helper function for the
14219 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14220 etc. It is assumed that operand parsing has already been done, and that the
14221 operands are in the form expected by the given opcode (this isn't necessarily
14222 the same as the form in which they were parsed, hence some massaging must
14223 take place before this function is called).
14224 Checks current arch version against that in the looked-up opcode. */
14227 do_vfp_nsyn_opcode (const char *opname
)
14229 const struct asm_opcode
*opcode
;
14231 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14236 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14237 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14244 inst
.instruction
= opcode
->tvalue
;
14245 opcode
->tencode ();
14249 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14250 opcode
->aencode ();
14255 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14257 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14259 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14262 do_vfp_nsyn_opcode ("fadds");
14264 do_vfp_nsyn_opcode ("fsubs");
14266 /* ARMv8.2 fp16 instruction. */
14268 do_scalar_fp16_v82_encode ();
14273 do_vfp_nsyn_opcode ("faddd");
14275 do_vfp_nsyn_opcode ("fsubd");
14279 /* Check operand types to see if this is a VFP instruction, and if so call
14283 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14285 enum neon_shape rs
;
14286 struct neon_type_el et
;
14291 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14292 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14296 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14297 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14298 N_F_ALL
| N_KEY
| N_VFP
);
14305 if (et
.type
!= NT_invtype
)
14316 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14318 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14320 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14323 do_vfp_nsyn_opcode ("fmacs");
14325 do_vfp_nsyn_opcode ("fnmacs");
14327 /* ARMv8.2 fp16 instruction. */
14329 do_scalar_fp16_v82_encode ();
14334 do_vfp_nsyn_opcode ("fmacd");
14336 do_vfp_nsyn_opcode ("fnmacd");
14341 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14343 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14345 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14348 do_vfp_nsyn_opcode ("ffmas");
14350 do_vfp_nsyn_opcode ("ffnmas");
14352 /* ARMv8.2 fp16 instruction. */
14354 do_scalar_fp16_v82_encode ();
14359 do_vfp_nsyn_opcode ("ffmad");
14361 do_vfp_nsyn_opcode ("ffnmad");
14366 do_vfp_nsyn_mul (enum neon_shape rs
)
14368 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14370 do_vfp_nsyn_opcode ("fmuls");
14372 /* ARMv8.2 fp16 instruction. */
14374 do_scalar_fp16_v82_encode ();
14377 do_vfp_nsyn_opcode ("fmuld");
14381 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14383 int is_neg
= (inst
.instruction
& 0x80) != 0;
14384 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14386 if (rs
== NS_FF
|| rs
== NS_HH
)
14389 do_vfp_nsyn_opcode ("fnegs");
14391 do_vfp_nsyn_opcode ("fabss");
14393 /* ARMv8.2 fp16 instruction. */
14395 do_scalar_fp16_v82_encode ();
14400 do_vfp_nsyn_opcode ("fnegd");
14402 do_vfp_nsyn_opcode ("fabsd");
14406 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14407 insns belong to Neon, and are handled elsewhere. */
14410 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14412 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14416 do_vfp_nsyn_opcode ("fldmdbs");
14418 do_vfp_nsyn_opcode ("fldmias");
14423 do_vfp_nsyn_opcode ("fstmdbs");
14425 do_vfp_nsyn_opcode ("fstmias");
14430 do_vfp_nsyn_sqrt (void)
14432 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14433 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14435 if (rs
== NS_FF
|| rs
== NS_HH
)
14437 do_vfp_nsyn_opcode ("fsqrts");
14439 /* ARMv8.2 fp16 instruction. */
14441 do_scalar_fp16_v82_encode ();
14444 do_vfp_nsyn_opcode ("fsqrtd");
14448 do_vfp_nsyn_div (void)
14450 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14451 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14452 N_F_ALL
| N_KEY
| N_VFP
);
14454 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14456 do_vfp_nsyn_opcode ("fdivs");
14458 /* ARMv8.2 fp16 instruction. */
14460 do_scalar_fp16_v82_encode ();
14463 do_vfp_nsyn_opcode ("fdivd");
14467 do_vfp_nsyn_nmul (void)
14469 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14470 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14471 N_F_ALL
| N_KEY
| N_VFP
);
14473 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14475 NEON_ENCODE (SINGLE
, inst
);
14476 do_vfp_sp_dyadic ();
14478 /* ARMv8.2 fp16 instruction. */
14480 do_scalar_fp16_v82_encode ();
14484 NEON_ENCODE (DOUBLE
, inst
);
14485 do_vfp_dp_rd_rn_rm ();
14487 do_vfp_cond_or_thumb ();
14492 do_vfp_nsyn_cmp (void)
14494 enum neon_shape rs
;
14495 if (inst
.operands
[1].isreg
)
14497 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14498 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14500 if (rs
== NS_FF
|| rs
== NS_HH
)
14502 NEON_ENCODE (SINGLE
, inst
);
14503 do_vfp_sp_monadic ();
14507 NEON_ENCODE (DOUBLE
, inst
);
14508 do_vfp_dp_rd_rm ();
14513 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14514 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14516 switch (inst
.instruction
& 0x0fffffff)
14519 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14522 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14528 if (rs
== NS_FI
|| rs
== NS_HI
)
14530 NEON_ENCODE (SINGLE
, inst
);
14531 do_vfp_sp_compare_z ();
14535 NEON_ENCODE (DOUBLE
, inst
);
14539 do_vfp_cond_or_thumb ();
14541 /* ARMv8.2 fp16 instruction. */
14542 if (rs
== NS_HI
|| rs
== NS_HH
)
14543 do_scalar_fp16_v82_encode ();
14547 nsyn_insert_sp (void)
14549 inst
.operands
[1] = inst
.operands
[0];
14550 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14551 inst
.operands
[0].reg
= REG_SP
;
14552 inst
.operands
[0].isreg
= 1;
14553 inst
.operands
[0].writeback
= 1;
14554 inst
.operands
[0].present
= 1;
14558 do_vfp_nsyn_push (void)
14562 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14563 _("register list must contain at least 1 and at most 16 "
14566 if (inst
.operands
[1].issingle
)
14567 do_vfp_nsyn_opcode ("fstmdbs");
14569 do_vfp_nsyn_opcode ("fstmdbd");
14573 do_vfp_nsyn_pop (void)
14577 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14578 _("register list must contain at least 1 and at most 16 "
14581 if (inst
.operands
[1].issingle
)
14582 do_vfp_nsyn_opcode ("fldmias");
14584 do_vfp_nsyn_opcode ("fldmiad");
14587 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14588 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14591 neon_dp_fixup (struct arm_it
* insn
)
14593 unsigned int i
= insn
->instruction
;
14598 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14609 insn
->instruction
= i
;
14612 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14616 neon_logbits (unsigned x
)
14618 return ffs (x
) - 4;
14621 #define LOW4(R) ((R) & 0xf)
14622 #define HI1(R) (((R) >> 4) & 1)
14624 /* Encode insns with bit pattern:
14626 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14627 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14629 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14630 different meaning for some instruction. */
14633 neon_three_same (int isquad
, int ubit
, int size
)
14635 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14636 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14637 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14638 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14639 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14640 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14641 inst
.instruction
|= (isquad
!= 0) << 6;
14642 inst
.instruction
|= (ubit
!= 0) << 24;
14644 inst
.instruction
|= neon_logbits (size
) << 20;
14646 neon_dp_fixup (&inst
);
14649 /* Encode instructions of the form:
14651 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14652 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14654 Don't write size if SIZE == -1. */
14657 neon_two_same (int qbit
, int ubit
, int size
)
14659 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14660 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14661 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14662 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14663 inst
.instruction
|= (qbit
!= 0) << 6;
14664 inst
.instruction
|= (ubit
!= 0) << 24;
14667 inst
.instruction
|= neon_logbits (size
) << 18;
14669 neon_dp_fixup (&inst
);
14672 /* Neon instruction encoders, in approximate order of appearance. */
14675 do_neon_dyadic_i_su (void)
14677 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14678 struct neon_type_el et
= neon_check_type (3, rs
,
14679 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14680 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14684 do_neon_dyadic_i64_su (void)
14686 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14687 struct neon_type_el et
= neon_check_type (3, rs
,
14688 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14689 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14693 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14696 unsigned size
= et
.size
>> 3;
14697 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14698 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14699 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14701 inst
.instruction
|= (isquad
!= 0) << 6;
14702 inst
.instruction
|= immbits
<< 16;
14703 inst
.instruction
|= (size
>> 3) << 7;
14704 inst
.instruction
|= (size
& 0x7) << 19;
14706 inst
.instruction
|= (uval
!= 0) << 24;
14708 neon_dp_fixup (&inst
);
14712 do_neon_shl_imm (void)
14714 if (!inst
.operands
[2].isreg
)
14716 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14717 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14718 int imm
= inst
.operands
[2].imm
;
14720 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14721 _("immediate out of range for shift"));
14722 NEON_ENCODE (IMMED
, inst
);
14723 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14727 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14728 struct neon_type_el et
= neon_check_type (3, rs
,
14729 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14732 /* VSHL/VQSHL 3-register variants have syntax such as:
14734 whereas other 3-register operations encoded by neon_three_same have
14737 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14739 tmp
= inst
.operands
[2].reg
;
14740 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14741 inst
.operands
[1].reg
= tmp
;
14742 NEON_ENCODE (INTEGER
, inst
);
14743 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14748 do_neon_qshl_imm (void)
14750 if (!inst
.operands
[2].isreg
)
14752 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14753 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14754 int imm
= inst
.operands
[2].imm
;
14756 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14757 _("immediate out of range for shift"));
14758 NEON_ENCODE (IMMED
, inst
);
14759 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14763 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14764 struct neon_type_el et
= neon_check_type (3, rs
,
14765 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14768 /* See note in do_neon_shl_imm. */
14769 tmp
= inst
.operands
[2].reg
;
14770 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14771 inst
.operands
[1].reg
= tmp
;
14772 NEON_ENCODE (INTEGER
, inst
);
14773 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14778 do_neon_rshl (void)
14780 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14781 struct neon_type_el et
= neon_check_type (3, rs
,
14782 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14785 tmp
= inst
.operands
[2].reg
;
14786 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14787 inst
.operands
[1].reg
= tmp
;
14788 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14792 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14794 /* Handle .I8 pseudo-instructions. */
14797 /* Unfortunately, this will make everything apart from zero out-of-range.
14798 FIXME is this the intended semantics? There doesn't seem much point in
14799 accepting .I8 if so. */
14800 immediate
|= immediate
<< 8;
14806 if (immediate
== (immediate
& 0x000000ff))
14808 *immbits
= immediate
;
14811 else if (immediate
== (immediate
& 0x0000ff00))
14813 *immbits
= immediate
>> 8;
14816 else if (immediate
== (immediate
& 0x00ff0000))
14818 *immbits
= immediate
>> 16;
14821 else if (immediate
== (immediate
& 0xff000000))
14823 *immbits
= immediate
>> 24;
14826 if ((immediate
& 0xffff) != (immediate
>> 16))
14827 goto bad_immediate
;
14828 immediate
&= 0xffff;
14831 if (immediate
== (immediate
& 0x000000ff))
14833 *immbits
= immediate
;
14836 else if (immediate
== (immediate
& 0x0000ff00))
14838 *immbits
= immediate
>> 8;
14843 first_error (_("immediate value out of range"));
14848 do_neon_logic (void)
14850 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14852 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14853 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14854 /* U bit and size field were set as part of the bitmask. */
14855 NEON_ENCODE (INTEGER
, inst
);
14856 neon_three_same (neon_quad (rs
), 0, -1);
14860 const int three_ops_form
= (inst
.operands
[2].present
14861 && !inst
.operands
[2].isreg
);
14862 const int immoperand
= (three_ops_form
? 2 : 1);
14863 enum neon_shape rs
= (three_ops_form
14864 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14865 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14866 struct neon_type_el et
= neon_check_type (2, rs
,
14867 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14868 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14872 if (et
.type
== NT_invtype
)
14875 if (three_ops_form
)
14876 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14877 _("first and second operands shall be the same register"));
14879 NEON_ENCODE (IMMED
, inst
);
14881 immbits
= inst
.operands
[immoperand
].imm
;
14884 /* .i64 is a pseudo-op, so the immediate must be a repeating
14886 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14887 inst
.operands
[immoperand
].reg
: 0))
14889 /* Set immbits to an invalid constant. */
14890 immbits
= 0xdeadbeef;
14897 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14901 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14905 /* Pseudo-instruction for VBIC. */
14906 neon_invert_size (&immbits
, 0, et
.size
);
14907 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14911 /* Pseudo-instruction for VORR. */
14912 neon_invert_size (&immbits
, 0, et
.size
);
14913 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14923 inst
.instruction
|= neon_quad (rs
) << 6;
14924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14925 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14926 inst
.instruction
|= cmode
<< 8;
14927 neon_write_immbits (immbits
);
14929 neon_dp_fixup (&inst
);
14934 do_neon_bitfield (void)
14936 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14937 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14938 neon_three_same (neon_quad (rs
), 0, -1);
14942 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14945 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14946 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14948 if (et
.type
== NT_float
)
14950 NEON_ENCODE (FLOAT
, inst
);
14951 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14955 NEON_ENCODE (INTEGER
, inst
);
14956 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14961 do_neon_dyadic_if_su (void)
14963 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14967 do_neon_dyadic_if_su_d (void)
14969 /* This version only allow D registers, but that constraint is enforced during
14970 operand parsing so we don't need to do anything extra here. */
14971 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14975 do_neon_dyadic_if_i_d (void)
14977 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14978 affected if we specify unsigned args. */
14979 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14982 enum vfp_or_neon_is_neon_bits
14985 NEON_CHECK_ARCH
= 2,
14986 NEON_CHECK_ARCH8
= 4
14989 /* Call this function if an instruction which may have belonged to the VFP or
14990 Neon instruction sets, but turned out to be a Neon instruction (due to the
14991 operand types involved, etc.). We have to check and/or fix-up a couple of
14994 - Make sure the user hasn't attempted to make a Neon instruction
14996 - Alter the value in the condition code field if necessary.
14997 - Make sure that the arch supports Neon instructions.
14999 Which of these operations take place depends on bits from enum
15000 vfp_or_neon_is_neon_bits.
15002 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15003 current instruction's condition is COND_ALWAYS, the condition field is
15004 changed to inst.uncond_value. This is necessary because instructions shared
15005 between VFP and Neon may be conditional for the VFP variants only, and the
15006 unconditional Neon version must have, e.g., 0xF in the condition field. */
15009 vfp_or_neon_is_neon (unsigned check
)
15011 /* Conditions are always legal in Thumb mode (IT blocks). */
15012 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15014 if (inst
.cond
!= COND_ALWAYS
)
15016 first_error (_(BAD_COND
));
15019 if (inst
.uncond_value
!= -1)
15020 inst
.instruction
|= inst
.uncond_value
<< 28;
15023 if ((check
& NEON_CHECK_ARCH
)
15024 && !mark_feature_used (&fpu_neon_ext_v1
))
15026 first_error (_(BAD_FPU
));
15030 if ((check
& NEON_CHECK_ARCH8
)
15031 && !mark_feature_used (&fpu_neon_ext_armv8
))
15033 first_error (_(BAD_FPU
));
15041 do_neon_addsub_if_i (void)
15043 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15046 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15049 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15050 affected if we specify unsigned args. */
15051 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15054 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15056 V<op> A,B (A is operand 0, B is operand 2)
15061 so handle that case specially. */
15064 neon_exchange_operands (void)
15066 if (inst
.operands
[1].present
)
15068 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15070 /* Swap operands[1] and operands[2]. */
15071 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15072 inst
.operands
[1] = inst
.operands
[2];
15073 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15078 inst
.operands
[1] = inst
.operands
[2];
15079 inst
.operands
[2] = inst
.operands
[0];
15084 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15086 if (inst
.operands
[2].isreg
)
15089 neon_exchange_operands ();
15090 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15094 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15095 struct neon_type_el et
= neon_check_type (2, rs
,
15096 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15098 NEON_ENCODE (IMMED
, inst
);
15099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15103 inst
.instruction
|= neon_quad (rs
) << 6;
15104 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15105 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15107 neon_dp_fixup (&inst
);
15114 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15118 do_neon_cmp_inv (void)
15120 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15126 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15129 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15130 scalars, which are encoded in 5 bits, M : Rm.
15131 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15132 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15135 Dot Product instructions are similar to multiply instructions except elsize
15136 should always be 32.
15138 This function translates SCALAR, which is GAS's internal encoding of indexed
15139 scalar register, to raw encoding. There is also register and index range
15140 check based on ELSIZE. */
15143 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15145 unsigned regno
= NEON_SCALAR_REG (scalar
);
15146 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15151 if (regno
> 7 || elno
> 3)
15153 return regno
| (elno
<< 3);
15156 if (regno
> 15 || elno
> 1)
15158 return regno
| (elno
<< 4);
15162 first_error (_("scalar out of range for multiply instruction"));
15168 /* Encode multiply / multiply-accumulate scalar instructions. */
15171 neon_mul_mac (struct neon_type_el et
, int ubit
)
15175 /* Give a more helpful error message if we have an invalid type. */
15176 if (et
.type
== NT_invtype
)
15179 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15180 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15181 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15182 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15183 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15184 inst
.instruction
|= LOW4 (scalar
);
15185 inst
.instruction
|= HI1 (scalar
) << 5;
15186 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15187 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15188 inst
.instruction
|= (ubit
!= 0) << 24;
15190 neon_dp_fixup (&inst
);
15194 do_neon_mac_maybe_scalar (void)
15196 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15199 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15202 if (inst
.operands
[2].isscalar
)
15204 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15205 struct neon_type_el et
= neon_check_type (3, rs
,
15206 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15207 NEON_ENCODE (SCALAR
, inst
);
15208 neon_mul_mac (et
, neon_quad (rs
));
15212 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15213 affected if we specify unsigned args. */
15214 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15219 do_neon_fmac (void)
15221 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15224 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15227 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15233 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15234 struct neon_type_el et
= neon_check_type (3, rs
,
15235 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15236 neon_three_same (neon_quad (rs
), 0, et
.size
);
15239 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15240 same types as the MAC equivalents. The polynomial type for this instruction
15241 is encoded the same as the integer type. */
15246 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15249 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15252 if (inst
.operands
[2].isscalar
)
15253 do_neon_mac_maybe_scalar ();
15255 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15259 do_neon_qdmulh (void)
15261 if (inst
.operands
[2].isscalar
)
15263 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15264 struct neon_type_el et
= neon_check_type (3, rs
,
15265 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15266 NEON_ENCODE (SCALAR
, inst
);
15267 neon_mul_mac (et
, neon_quad (rs
));
15271 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15272 struct neon_type_el et
= neon_check_type (3, rs
,
15273 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15274 NEON_ENCODE (INTEGER
, inst
);
15275 /* The U bit (rounding) comes from bit mask. */
15276 neon_three_same (neon_quad (rs
), 0, et
.size
);
15281 do_neon_qrdmlah (void)
15283 /* Check we're on the correct architecture. */
15284 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15286 _("instruction form not available on this architecture.");
15287 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15289 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15290 record_feature_use (&fpu_neon_ext_v8_1
);
15293 if (inst
.operands
[2].isscalar
)
15295 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15296 struct neon_type_el et
= neon_check_type (3, rs
,
15297 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15298 NEON_ENCODE (SCALAR
, inst
);
15299 neon_mul_mac (et
, neon_quad (rs
));
15303 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15304 struct neon_type_el et
= neon_check_type (3, rs
,
15305 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15306 NEON_ENCODE (INTEGER
, inst
);
15307 /* The U bit (rounding) comes from bit mask. */
15308 neon_three_same (neon_quad (rs
), 0, et
.size
);
15313 do_neon_fcmp_absolute (void)
15315 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15316 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15317 N_F_16_32
| N_KEY
);
15318 /* Size field comes from bit mask. */
15319 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15323 do_neon_fcmp_absolute_inv (void)
15325 neon_exchange_operands ();
15326 do_neon_fcmp_absolute ();
15330 do_neon_step (void)
15332 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15333 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15334 N_F_16_32
| N_KEY
);
15335 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15339 do_neon_abs_neg (void)
15341 enum neon_shape rs
;
15342 struct neon_type_el et
;
15344 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15347 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15350 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15351 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15353 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15354 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15355 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15356 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15357 inst
.instruction
|= neon_quad (rs
) << 6;
15358 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15359 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15361 neon_dp_fixup (&inst
);
15367 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15368 struct neon_type_el et
= neon_check_type (2, rs
,
15369 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15370 int imm
= inst
.operands
[2].imm
;
15371 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15372 _("immediate out of range for insert"));
15373 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15379 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15380 struct neon_type_el et
= neon_check_type (2, rs
,
15381 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15382 int imm
= inst
.operands
[2].imm
;
15383 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15384 _("immediate out of range for insert"));
15385 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15389 do_neon_qshlu_imm (void)
15391 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15392 struct neon_type_el et
= neon_check_type (2, rs
,
15393 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15394 int imm
= inst
.operands
[2].imm
;
15395 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15396 _("immediate out of range for shift"));
15397 /* Only encodes the 'U present' variant of the instruction.
15398 In this case, signed types have OP (bit 8) set to 0.
15399 Unsigned types have OP set to 1. */
15400 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15401 /* The rest of the bits are the same as other immediate shifts. */
15402 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15406 do_neon_qmovn (void)
15408 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15409 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15410 /* Saturating move where operands can be signed or unsigned, and the
15411 destination has the same signedness. */
15412 NEON_ENCODE (INTEGER
, inst
);
15413 if (et
.type
== NT_unsigned
)
15414 inst
.instruction
|= 0xc0;
15416 inst
.instruction
|= 0x80;
15417 neon_two_same (0, 1, et
.size
/ 2);
15421 do_neon_qmovun (void)
15423 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15424 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15425 /* Saturating move with unsigned results. Operands must be signed. */
15426 NEON_ENCODE (INTEGER
, inst
);
15427 neon_two_same (0, 1, et
.size
/ 2);
15431 do_neon_rshift_sat_narrow (void)
15433 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15434 or unsigned. If operands are unsigned, results must also be unsigned. */
15435 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15436 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15437 int imm
= inst
.operands
[2].imm
;
15438 /* This gets the bounds check, size encoding and immediate bits calculation
15442 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15443 VQMOVN.I<size> <Dd>, <Qm>. */
15446 inst
.operands
[2].present
= 0;
15447 inst
.instruction
= N_MNEM_vqmovn
;
15452 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15453 _("immediate out of range"));
15454 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15458 do_neon_rshift_sat_narrow_u (void)
15460 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15461 or unsigned. If operands are unsigned, results must also be unsigned. */
15462 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15463 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15464 int imm
= inst
.operands
[2].imm
;
15465 /* This gets the bounds check, size encoding and immediate bits calculation
15469 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15470 VQMOVUN.I<size> <Dd>, <Qm>. */
15473 inst
.operands
[2].present
= 0;
15474 inst
.instruction
= N_MNEM_vqmovun
;
15479 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15480 _("immediate out of range"));
15481 /* FIXME: The manual is kind of unclear about what value U should have in
15482 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15484 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15488 do_neon_movn (void)
15490 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15491 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15492 NEON_ENCODE (INTEGER
, inst
);
15493 neon_two_same (0, 1, et
.size
/ 2);
15497 do_neon_rshift_narrow (void)
15499 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15500 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15501 int imm
= inst
.operands
[2].imm
;
15502 /* This gets the bounds check, size encoding and immediate bits calculation
15506 /* If immediate is zero then we are a pseudo-instruction for
15507 VMOVN.I<size> <Dd>, <Qm> */
15510 inst
.operands
[2].present
= 0;
15511 inst
.instruction
= N_MNEM_vmovn
;
15516 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15517 _("immediate out of range for narrowing operation"));
15518 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15522 do_neon_shll (void)
15524 /* FIXME: Type checking when lengthening. */
15525 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15526 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15527 unsigned imm
= inst
.operands
[2].imm
;
15529 if (imm
== et
.size
)
15531 /* Maximum shift variant. */
15532 NEON_ENCODE (INTEGER
, inst
);
15533 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15534 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15535 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15536 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15537 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15539 neon_dp_fixup (&inst
);
15543 /* A more-specific type check for non-max versions. */
15544 et
= neon_check_type (2, NS_QDI
,
15545 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15546 NEON_ENCODE (IMMED
, inst
);
15547 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15551 /* Check the various types for the VCVT instruction, and return which version
15552 the current instruction is. */
15554 #define CVT_FLAVOUR_VAR \
15555 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15556 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15557 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15558 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15559 /* Half-precision conversions. */ \
15560 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15561 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15562 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15563 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15564 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15565 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15566 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15567 Compared with single/double precision variants, only the co-processor \
15568 field is different, so the encoding flow is reused here. */ \
15569 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15570 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15571 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15572 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15573 /* VFP instructions. */ \
15574 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15575 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15576 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15577 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15578 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15579 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15580 /* VFP instructions with bitshift. */ \
15581 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15582 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15583 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15584 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15585 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15586 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15587 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15588 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15590 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15591 neon_cvt_flavour_##C,
15593 /* The different types of conversions we can do. */
15594 enum neon_cvt_flavour
15597 neon_cvt_flavour_invalid
,
15598 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15603 static enum neon_cvt_flavour
15604 get_neon_cvt_flavour (enum neon_shape rs
)
15606 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15607 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15608 if (et.type != NT_invtype) \
15610 inst.error = NULL; \
15611 return (neon_cvt_flavour_##C); \
15614 struct neon_type_el et
;
15615 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15616 || rs
== NS_FF
) ? N_VFP
: 0;
15617 /* The instruction versions which take an immediate take one register
15618 argument, which is extended to the width of the full register. Thus the
15619 "source" and "destination" registers must have the same width. Hack that
15620 here by making the size equal to the key (wider, in this case) operand. */
15621 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15625 return neon_cvt_flavour_invalid
;
15640 /* Neon-syntax VFP conversions. */
15643 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15645 const char *opname
= 0;
15647 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15648 || rs
== NS_FHI
|| rs
== NS_HFI
)
15650 /* Conversions with immediate bitshift. */
15651 const char *enc
[] =
15653 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15659 if (flavour
< (int) ARRAY_SIZE (enc
))
15661 opname
= enc
[flavour
];
15662 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15663 _("operands 0 and 1 must be the same register"));
15664 inst
.operands
[1] = inst
.operands
[2];
15665 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15670 /* Conversions without bitshift. */
15671 const char *enc
[] =
15673 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15679 if (flavour
< (int) ARRAY_SIZE (enc
))
15680 opname
= enc
[flavour
];
15684 do_vfp_nsyn_opcode (opname
);
15686 /* ARMv8.2 fp16 VCVT instruction. */
15687 if (flavour
== neon_cvt_flavour_s32_f16
15688 || flavour
== neon_cvt_flavour_u32_f16
15689 || flavour
== neon_cvt_flavour_f16_u32
15690 || flavour
== neon_cvt_flavour_f16_s32
)
15691 do_scalar_fp16_v82_encode ();
15695 do_vfp_nsyn_cvtz (void)
15697 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15698 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15699 const char *enc
[] =
15701 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15707 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15708 do_vfp_nsyn_opcode (enc
[flavour
]);
15712 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15713 enum neon_cvt_mode mode
)
15718 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15719 D register operands. */
15720 if (flavour
== neon_cvt_flavour_s32_f64
15721 || flavour
== neon_cvt_flavour_u32_f64
)
15722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15725 if (flavour
== neon_cvt_flavour_s32_f16
15726 || flavour
== neon_cvt_flavour_u32_f16
)
15727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15730 set_it_insn_type (OUTSIDE_IT_INSN
);
15734 case neon_cvt_flavour_s32_f64
:
15738 case neon_cvt_flavour_s32_f32
:
15742 case neon_cvt_flavour_s32_f16
:
15746 case neon_cvt_flavour_u32_f64
:
15750 case neon_cvt_flavour_u32_f32
:
15754 case neon_cvt_flavour_u32_f16
:
15759 first_error (_("invalid instruction shape"));
15765 case neon_cvt_mode_a
: rm
= 0; break;
15766 case neon_cvt_mode_n
: rm
= 1; break;
15767 case neon_cvt_mode_p
: rm
= 2; break;
15768 case neon_cvt_mode_m
: rm
= 3; break;
15769 default: first_error (_("invalid rounding mode")); return;
15772 NEON_ENCODE (FPV8
, inst
);
15773 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15774 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15775 inst
.instruction
|= sz
<< 8;
15777 /* ARMv8.2 fp16 VCVT instruction. */
15778 if (flavour
== neon_cvt_flavour_s32_f16
15779 ||flavour
== neon_cvt_flavour_u32_f16
)
15780 do_scalar_fp16_v82_encode ();
15781 inst
.instruction
|= op
<< 7;
15782 inst
.instruction
|= rm
<< 16;
15783 inst
.instruction
|= 0xf0000000;
15784 inst
.is_neon
= TRUE
;
15788 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15790 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15791 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15792 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15794 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15796 if (flavour
== neon_cvt_flavour_invalid
)
15799 /* PR11109: Handle round-to-zero for VCVT conversions. */
15800 if (mode
== neon_cvt_mode_z
15801 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15802 && (flavour
== neon_cvt_flavour_s16_f16
15803 || flavour
== neon_cvt_flavour_u16_f16
15804 || flavour
== neon_cvt_flavour_s32_f32
15805 || flavour
== neon_cvt_flavour_u32_f32
15806 || flavour
== neon_cvt_flavour_s32_f64
15807 || flavour
== neon_cvt_flavour_u32_f64
)
15808 && (rs
== NS_FD
|| rs
== NS_FF
))
15810 do_vfp_nsyn_cvtz ();
15814 /* ARMv8.2 fp16 VCVT conversions. */
15815 if (mode
== neon_cvt_mode_z
15816 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15817 && (flavour
== neon_cvt_flavour_s32_f16
15818 || flavour
== neon_cvt_flavour_u32_f16
)
15821 do_vfp_nsyn_cvtz ();
15822 do_scalar_fp16_v82_encode ();
15826 /* VFP rather than Neon conversions. */
15827 if (flavour
>= neon_cvt_flavour_first_fp
)
15829 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15830 do_vfp_nsyn_cvt (rs
, flavour
);
15832 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15843 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15844 0x0000100, 0x1000100, 0x0, 0x1000000};
15846 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15849 /* Fixed-point conversion with #0 immediate is encoded as an
15850 integer conversion. */
15851 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15853 NEON_ENCODE (IMMED
, inst
);
15854 if (flavour
!= neon_cvt_flavour_invalid
)
15855 inst
.instruction
|= enctab
[flavour
];
15856 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15857 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15858 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15859 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15860 inst
.instruction
|= neon_quad (rs
) << 6;
15861 inst
.instruction
|= 1 << 21;
15862 if (flavour
< neon_cvt_flavour_s16_f16
)
15864 inst
.instruction
|= 1 << 21;
15865 immbits
= 32 - inst
.operands
[2].imm
;
15866 inst
.instruction
|= immbits
<< 16;
15870 inst
.instruction
|= 3 << 20;
15871 immbits
= 16 - inst
.operands
[2].imm
;
15872 inst
.instruction
|= immbits
<< 16;
15873 inst
.instruction
&= ~(1 << 9);
15876 neon_dp_fixup (&inst
);
15882 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15884 NEON_ENCODE (FLOAT
, inst
);
15885 set_it_insn_type (OUTSIDE_IT_INSN
);
15887 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15890 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15891 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15892 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15893 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15894 inst
.instruction
|= neon_quad (rs
) << 6;
15895 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15896 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15897 inst
.instruction
|= mode
<< 8;
15898 if (flavour
== neon_cvt_flavour_u16_f16
15899 || flavour
== neon_cvt_flavour_s16_f16
)
15900 /* Mask off the original size bits and reencode them. */
15901 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15904 inst
.instruction
|= 0xfc000000;
15906 inst
.instruction
|= 0xf0000000;
15912 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15913 0x100, 0x180, 0x0, 0x080};
15915 NEON_ENCODE (INTEGER
, inst
);
15917 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15920 if (flavour
!= neon_cvt_flavour_invalid
)
15921 inst
.instruction
|= enctab
[flavour
];
15923 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15924 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15925 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15926 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15927 inst
.instruction
|= neon_quad (rs
) << 6;
15928 if (flavour
>= neon_cvt_flavour_s16_f16
15929 && flavour
<= neon_cvt_flavour_f16_u16
)
15930 /* Half precision. */
15931 inst
.instruction
|= 1 << 18;
15933 inst
.instruction
|= 2 << 18;
15935 neon_dp_fixup (&inst
);
15940 /* Half-precision conversions for Advanced SIMD -- neon. */
15943 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15947 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15949 as_bad (_("operand size must match register width"));
15954 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15956 as_bad (_("operand size must match register width"));
15961 inst
.instruction
= 0x3b60600;
15963 inst
.instruction
= 0x3b60700;
15965 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15966 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15967 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15968 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15969 neon_dp_fixup (&inst
);
15973 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15974 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15975 do_vfp_nsyn_cvt (rs
, flavour
);
15977 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15982 do_neon_cvtr (void)
15984 do_neon_cvt_1 (neon_cvt_mode_x
);
15990 do_neon_cvt_1 (neon_cvt_mode_z
);
15994 do_neon_cvta (void)
15996 do_neon_cvt_1 (neon_cvt_mode_a
);
16000 do_neon_cvtn (void)
16002 do_neon_cvt_1 (neon_cvt_mode_n
);
16006 do_neon_cvtp (void)
16008 do_neon_cvt_1 (neon_cvt_mode_p
);
16012 do_neon_cvtm (void)
16014 do_neon_cvt_1 (neon_cvt_mode_m
);
16018 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16021 mark_feature_used (&fpu_vfp_ext_armv8
);
16023 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16024 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16025 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16026 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16027 inst
.instruction
|= to
? 0x10000 : 0;
16028 inst
.instruction
|= t
? 0x80 : 0;
16029 inst
.instruction
|= is_double
? 0x100 : 0;
16030 do_vfp_cond_or_thumb ();
16034 do_neon_cvttb_1 (bfd_boolean t
)
16036 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16037 NS_DF
, NS_DH
, NS_NULL
);
16041 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16044 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16046 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16049 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16051 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16053 /* The VCVTB and VCVTT instructions with D-register operands
16054 don't work for SP only targets. */
16055 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16059 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16061 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16063 /* The VCVTB and VCVTT instructions with D-register operands
16064 don't work for SP only targets. */
16065 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16069 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16076 do_neon_cvtb (void)
16078 do_neon_cvttb_1 (FALSE
);
16083 do_neon_cvtt (void)
16085 do_neon_cvttb_1 (TRUE
);
16089 neon_move_immediate (void)
16091 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16092 struct neon_type_el et
= neon_check_type (2, rs
,
16093 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16094 unsigned immlo
, immhi
= 0, immbits
;
16095 int op
, cmode
, float_p
;
16097 constraint (et
.type
== NT_invtype
,
16098 _("operand size must be specified for immediate VMOV"));
16100 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16101 op
= (inst
.instruction
& (1 << 5)) != 0;
16103 immlo
= inst
.operands
[1].imm
;
16104 if (inst
.operands
[1].regisimm
)
16105 immhi
= inst
.operands
[1].reg
;
16107 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16108 _("immediate has bits set outside the operand size"));
16110 float_p
= inst
.operands
[1].immisfloat
;
16112 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16113 et
.size
, et
.type
)) == FAIL
)
16115 /* Invert relevant bits only. */
16116 neon_invert_size (&immlo
, &immhi
, et
.size
);
16117 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16118 with one or the other; those cases are caught by
16119 neon_cmode_for_move_imm. */
16121 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16122 &op
, et
.size
, et
.type
)) == FAIL
)
16124 first_error (_("immediate out of range"));
16129 inst
.instruction
&= ~(1 << 5);
16130 inst
.instruction
|= op
<< 5;
16132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16134 inst
.instruction
|= neon_quad (rs
) << 6;
16135 inst
.instruction
|= cmode
<< 8;
16137 neon_write_immbits (immbits
);
16143 if (inst
.operands
[1].isreg
)
16145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16147 NEON_ENCODE (INTEGER
, inst
);
16148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16152 inst
.instruction
|= neon_quad (rs
) << 6;
16156 NEON_ENCODE (IMMED
, inst
);
16157 neon_move_immediate ();
16160 neon_dp_fixup (&inst
);
16163 /* Encode instructions of form:
16165 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16166 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16169 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16171 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16172 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16174 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16175 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16176 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16177 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16178 inst
.instruction
|= neon_logbits (size
) << 20;
16180 neon_dp_fixup (&inst
);
16184 do_neon_dyadic_long (void)
16186 /* FIXME: Type checking for lengthening op. */
16187 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16188 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16189 neon_mixed_length (et
, et
.size
);
16193 do_neon_abal (void)
16195 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16196 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16197 neon_mixed_length (et
, et
.size
);
16201 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16203 if (inst
.operands
[2].isscalar
)
16205 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16206 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16207 NEON_ENCODE (SCALAR
, inst
);
16208 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16212 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16213 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16214 NEON_ENCODE (INTEGER
, inst
);
16215 neon_mixed_length (et
, et
.size
);
16220 do_neon_mac_maybe_scalar_long (void)
16222 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16225 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16226 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16229 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16231 unsigned regno
= NEON_SCALAR_REG (scalar
);
16232 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16236 if (regno
> 7 || elno
> 3)
16239 return ((regno
& 0x7)
16240 | ((elno
& 0x1) << 3)
16241 | (((elno
>> 1) & 0x1) << 5));
16245 if (regno
> 15 || elno
> 1)
16248 return (((regno
& 0x1) << 5)
16249 | ((regno
>> 1) & 0x7)
16250 | ((elno
& 0x1) << 3));
16254 first_error (_("scalar out of range for multiply instruction"));
16259 do_neon_fmac_maybe_scalar_long (int subtype
)
16261 enum neon_shape rs
;
16263 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16264 field (bits[21:20]) has different meaning. For scalar index variant, it's
16265 used to differentiate add and subtract, otherwise it's with fixed value
16269 if (inst
.cond
!= COND_ALWAYS
)
16270 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16271 "behaviour is UNPREDICTABLE"));
16273 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16276 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16279 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16280 be a scalar index register. */
16281 if (inst
.operands
[2].isscalar
)
16283 high8
= 0xfe000000;
16286 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16290 high8
= 0xfc000000;
16293 inst
.instruction
|= (0x1 << 23);
16294 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16297 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16299 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16300 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16301 so we simply pass -1 as size. */
16302 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16303 neon_three_same (quad_p
, 0, size
);
16305 /* Undo neon_dp_fixup. Redo the high eight bits. */
16306 inst
.instruction
&= 0x00ffffff;
16307 inst
.instruction
|= high8
;
16309 #define LOW1(R) ((R) & 0x1)
16310 #define HI4(R) (((R) >> 1) & 0xf)
16311 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16312 whether the instruction is in Q form and whether Vm is a scalar indexed
16314 if (inst
.operands
[2].isscalar
)
16317 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16318 inst
.instruction
&= 0xffffffd0;
16319 inst
.instruction
|= rm
;
16323 /* Redo Rn as well. */
16324 inst
.instruction
&= 0xfff0ff7f;
16325 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16326 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16331 /* Redo Rn and Rm. */
16332 inst
.instruction
&= 0xfff0ff50;
16333 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16334 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16335 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16336 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16341 do_neon_vfmal (void)
16343 return do_neon_fmac_maybe_scalar_long (0);
16347 do_neon_vfmsl (void)
16349 return do_neon_fmac_maybe_scalar_long (1);
16353 do_neon_dyadic_wide (void)
16355 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16356 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16357 neon_mixed_length (et
, et
.size
);
16361 do_neon_dyadic_narrow (void)
16363 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16364 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16365 /* Operand sign is unimportant, and the U bit is part of the opcode,
16366 so force the operand type to integer. */
16367 et
.type
= NT_integer
;
16368 neon_mixed_length (et
, et
.size
/ 2);
16372 do_neon_mul_sat_scalar_long (void)
16374 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16378 do_neon_vmull (void)
16380 if (inst
.operands
[2].isscalar
)
16381 do_neon_mac_maybe_scalar_long ();
16384 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16385 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16387 if (et
.type
== NT_poly
)
16388 NEON_ENCODE (POLY
, inst
);
16390 NEON_ENCODE (INTEGER
, inst
);
16392 /* For polynomial encoding the U bit must be zero, and the size must
16393 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16394 obviously, as 0b10). */
16397 /* Check we're on the correct architecture. */
16398 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16400 _("Instruction form not available on this architecture.");
16405 neon_mixed_length (et
, et
.size
);
16412 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16413 struct neon_type_el et
= neon_check_type (3, rs
,
16414 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16415 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16417 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16418 _("shift out of range"));
16419 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16420 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16421 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16423 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16424 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16425 inst
.instruction
|= neon_quad (rs
) << 6;
16426 inst
.instruction
|= imm
<< 8;
16428 neon_dp_fixup (&inst
);
16434 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16435 struct neon_type_el et
= neon_check_type (2, rs
,
16436 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16437 unsigned op
= (inst
.instruction
>> 7) & 3;
16438 /* N (width of reversed regions) is encoded as part of the bitmask. We
16439 extract it here to check the elements to be reversed are smaller.
16440 Otherwise we'd get a reserved instruction. */
16441 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16442 gas_assert (elsize
!= 0);
16443 constraint (et
.size
>= elsize
,
16444 _("elements must be smaller than reversal region"));
16445 neon_two_same (neon_quad (rs
), 1, et
.size
);
16451 if (inst
.operands
[1].isscalar
)
16453 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16454 struct neon_type_el et
= neon_check_type (2, rs
,
16455 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16456 unsigned sizebits
= et
.size
>> 3;
16457 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16458 int logsize
= neon_logbits (et
.size
);
16459 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16461 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16464 NEON_ENCODE (SCALAR
, inst
);
16465 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16466 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16467 inst
.instruction
|= LOW4 (dm
);
16468 inst
.instruction
|= HI1 (dm
) << 5;
16469 inst
.instruction
|= neon_quad (rs
) << 6;
16470 inst
.instruction
|= x
<< 17;
16471 inst
.instruction
|= sizebits
<< 16;
16473 neon_dp_fixup (&inst
);
16477 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16478 struct neon_type_el et
= neon_check_type (2, rs
,
16479 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16480 /* Duplicate ARM register to lanes of vector. */
16481 NEON_ENCODE (ARMREG
, inst
);
16484 case 8: inst
.instruction
|= 0x400000; break;
16485 case 16: inst
.instruction
|= 0x000020; break;
16486 case 32: inst
.instruction
|= 0x000000; break;
16489 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16490 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16491 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16492 inst
.instruction
|= neon_quad (rs
) << 21;
16493 /* The encoding for this instruction is identical for the ARM and Thumb
16494 variants, except for the condition field. */
16495 do_vfp_cond_or_thumb ();
16499 /* VMOV has particularly many variations. It can be one of:
16500 0. VMOV<c><q> <Qd>, <Qm>
16501 1. VMOV<c><q> <Dd>, <Dm>
16502 (Register operations, which are VORR with Rm = Rn.)
16503 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16504 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16506 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16507 (ARM register to scalar.)
16508 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16509 (Two ARM registers to vector.)
16510 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16511 (Scalar to ARM register.)
16512 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16513 (Vector to two ARM registers.)
16514 8. VMOV.F32 <Sd>, <Sm>
16515 9. VMOV.F64 <Dd>, <Dm>
16516 (VFP register moves.)
16517 10. VMOV.F32 <Sd>, #imm
16518 11. VMOV.F64 <Dd>, #imm
16519 (VFP float immediate load.)
16520 12. VMOV <Rd>, <Sm>
16521 (VFP single to ARM reg.)
16522 13. VMOV <Sd>, <Rm>
16523 (ARM reg to VFP single.)
16524 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16525 (Two ARM regs to two VFP singles.)
16526 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16527 (Two VFP singles to two ARM regs.)
16529 These cases can be disambiguated using neon_select_shape, except cases 1/9
16530 and 3/11 which depend on the operand type too.
16532 All the encoded bits are hardcoded by this function.
16534 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16535 Cases 5, 7 may be used with VFPv2 and above.
16537 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16538 can specify a type where it doesn't make sense to, and is ignored). */
16543 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16544 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16545 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16546 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16547 struct neon_type_el et
;
16548 const char *ldconst
= 0;
16552 case NS_DD
: /* case 1/9. */
16553 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16554 /* It is not an error here if no type is given. */
16556 if (et
.type
== NT_float
&& et
.size
== 64)
16558 do_vfp_nsyn_opcode ("fcpyd");
16561 /* fall through. */
16563 case NS_QQ
: /* case 0/1. */
16565 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16567 /* The architecture manual I have doesn't explicitly state which
16568 value the U bit should have for register->register moves, but
16569 the equivalent VORR instruction has U = 0, so do that. */
16570 inst
.instruction
= 0x0200110;
16571 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16572 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16573 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16574 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16575 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16576 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16577 inst
.instruction
|= neon_quad (rs
) << 6;
16579 neon_dp_fixup (&inst
);
16583 case NS_DI
: /* case 3/11. */
16584 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16586 if (et
.type
== NT_float
&& et
.size
== 64)
16588 /* case 11 (fconstd). */
16589 ldconst
= "fconstd";
16590 goto encode_fconstd
;
16592 /* fall through. */
16594 case NS_QI
: /* case 2/3. */
16595 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16597 inst
.instruction
= 0x0800010;
16598 neon_move_immediate ();
16599 neon_dp_fixup (&inst
);
16602 case NS_SR
: /* case 4. */
16604 unsigned bcdebits
= 0;
16606 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16607 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16609 /* .<size> is optional here, defaulting to .32. */
16610 if (inst
.vectype
.elems
== 0
16611 && inst
.operands
[0].vectype
.type
== NT_invtype
16612 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16614 inst
.vectype
.el
[0].type
= NT_untyped
;
16615 inst
.vectype
.el
[0].size
= 32;
16616 inst
.vectype
.elems
= 1;
16619 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16620 logsize
= neon_logbits (et
.size
);
16622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16625 && et
.size
!= 32, _(BAD_FPU
));
16626 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16627 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16631 case 8: bcdebits
= 0x8; break;
16632 case 16: bcdebits
= 0x1; break;
16633 case 32: bcdebits
= 0x0; break;
16637 bcdebits
|= x
<< logsize
;
16639 inst
.instruction
= 0xe000b10;
16640 do_vfp_cond_or_thumb ();
16641 inst
.instruction
|= LOW4 (dn
) << 16;
16642 inst
.instruction
|= HI1 (dn
) << 7;
16643 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16644 inst
.instruction
|= (bcdebits
& 3) << 5;
16645 inst
.instruction
|= (bcdebits
>> 2) << 21;
16649 case NS_DRR
: /* case 5 (fmdrr). */
16650 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16653 inst
.instruction
= 0xc400b10;
16654 do_vfp_cond_or_thumb ();
16655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16657 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16658 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16661 case NS_RS
: /* case 6. */
16664 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16665 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16666 unsigned abcdebits
= 0;
16668 /* .<dt> is optional here, defaulting to .32. */
16669 if (inst
.vectype
.elems
== 0
16670 && inst
.operands
[0].vectype
.type
== NT_invtype
16671 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16673 inst
.vectype
.el
[0].type
= NT_untyped
;
16674 inst
.vectype
.el
[0].size
= 32;
16675 inst
.vectype
.elems
= 1;
16678 et
= neon_check_type (2, NS_NULL
,
16679 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16680 logsize
= neon_logbits (et
.size
);
16682 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16684 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16685 && et
.size
!= 32, _(BAD_FPU
));
16686 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16687 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16691 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16692 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16693 case 32: abcdebits
= 0x00; break;
16697 abcdebits
|= x
<< logsize
;
16698 inst
.instruction
= 0xe100b10;
16699 do_vfp_cond_or_thumb ();
16700 inst
.instruction
|= LOW4 (dn
) << 16;
16701 inst
.instruction
|= HI1 (dn
) << 7;
16702 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16703 inst
.instruction
|= (abcdebits
& 3) << 5;
16704 inst
.instruction
|= (abcdebits
>> 2) << 21;
16708 case NS_RRD
: /* case 7 (fmrrd). */
16709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16712 inst
.instruction
= 0xc500b10;
16713 do_vfp_cond_or_thumb ();
16714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16715 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16716 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16717 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16720 case NS_FF
: /* case 8 (fcpys). */
16721 do_vfp_nsyn_opcode ("fcpys");
16725 case NS_FI
: /* case 10 (fconsts). */
16726 ldconst
= "fconsts";
16728 if (!inst
.operands
[1].immisfloat
)
16731 /* Immediate has to fit in 8 bits so float is enough. */
16732 float imm
= (float) inst
.operands
[1].imm
;
16733 memcpy (&new_imm
, &imm
, sizeof (float));
16734 /* But the assembly may have been written to provide an integer
16735 bit pattern that equates to a float, so check that the
16736 conversion has worked. */
16737 if (is_quarter_float (new_imm
))
16739 if (is_quarter_float (inst
.operands
[1].imm
))
16740 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16742 inst
.operands
[1].imm
= new_imm
;
16743 inst
.operands
[1].immisfloat
= 1;
16747 if (is_quarter_float (inst
.operands
[1].imm
))
16749 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16750 do_vfp_nsyn_opcode (ldconst
);
16752 /* ARMv8.2 fp16 vmov.f16 instruction. */
16754 do_scalar_fp16_v82_encode ();
16757 first_error (_("immediate out of range"));
16761 case NS_RF
: /* case 12 (fmrs). */
16762 do_vfp_nsyn_opcode ("fmrs");
16763 /* ARMv8.2 fp16 vmov.f16 instruction. */
16765 do_scalar_fp16_v82_encode ();
16769 case NS_FR
: /* case 13 (fmsr). */
16770 do_vfp_nsyn_opcode ("fmsr");
16771 /* ARMv8.2 fp16 vmov.f16 instruction. */
16773 do_scalar_fp16_v82_encode ();
16776 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16777 (one of which is a list), but we have parsed four. Do some fiddling to
16778 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16780 case NS_RRFF
: /* case 14 (fmrrs). */
16781 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16782 _("VFP registers must be adjacent"));
16783 inst
.operands
[2].imm
= 2;
16784 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16785 do_vfp_nsyn_opcode ("fmrrs");
16788 case NS_FFRR
: /* case 15 (fmsrr). */
16789 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16790 _("VFP registers must be adjacent"));
16791 inst
.operands
[1] = inst
.operands
[2];
16792 inst
.operands
[2] = inst
.operands
[3];
16793 inst
.operands
[0].imm
= 2;
16794 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16795 do_vfp_nsyn_opcode ("fmsrr");
16799 /* neon_select_shape has determined that the instruction
16800 shape is wrong and has already set the error message. */
16809 do_neon_rshift_round_imm (void)
16811 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16812 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16813 int imm
= inst
.operands
[2].imm
;
16815 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16818 inst
.operands
[2].present
= 0;
16823 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16824 _("immediate out of range for shift"));
16825 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16830 do_neon_movhf (void)
16832 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16833 constraint (rs
!= NS_HH
, _("invalid suffix"));
16835 if (inst
.cond
!= COND_ALWAYS
)
16839 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16840 " the behaviour is UNPREDICTABLE"));
16844 inst
.error
= BAD_COND
;
16849 do_vfp_sp_monadic ();
16852 inst
.instruction
|= 0xf0000000;
16856 do_neon_movl (void)
16858 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16859 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16860 unsigned sizebits
= et
.size
>> 3;
16861 inst
.instruction
|= sizebits
<< 19;
16862 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16868 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16869 struct neon_type_el et
= neon_check_type (2, rs
,
16870 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16871 NEON_ENCODE (INTEGER
, inst
);
16872 neon_two_same (neon_quad (rs
), 1, et
.size
);
16876 do_neon_zip_uzp (void)
16878 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16879 struct neon_type_el et
= neon_check_type (2, rs
,
16880 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16881 if (rs
== NS_DD
&& et
.size
== 32)
16883 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16884 inst
.instruction
= N_MNEM_vtrn
;
16888 neon_two_same (neon_quad (rs
), 1, et
.size
);
16892 do_neon_sat_abs_neg (void)
16894 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16895 struct neon_type_el et
= neon_check_type (2, rs
,
16896 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16897 neon_two_same (neon_quad (rs
), 1, et
.size
);
16901 do_neon_pair_long (void)
16903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16904 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16905 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16906 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16907 neon_two_same (neon_quad (rs
), 1, et
.size
);
16911 do_neon_recip_est (void)
16913 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16914 struct neon_type_el et
= neon_check_type (2, rs
,
16915 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16916 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16917 neon_two_same (neon_quad (rs
), 1, et
.size
);
16923 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16924 struct neon_type_el et
= neon_check_type (2, rs
,
16925 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16926 neon_two_same (neon_quad (rs
), 1, et
.size
);
16932 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16933 struct neon_type_el et
= neon_check_type (2, rs
,
16934 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16935 neon_two_same (neon_quad (rs
), 1, et
.size
);
16941 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16942 struct neon_type_el et
= neon_check_type (2, rs
,
16943 N_EQK
| N_INT
, N_8
| N_KEY
);
16944 neon_two_same (neon_quad (rs
), 1, et
.size
);
16950 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16951 neon_two_same (neon_quad (rs
), 1, -1);
16955 do_neon_tbl_tbx (void)
16957 unsigned listlenbits
;
16958 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16960 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16962 first_error (_("bad list length for table lookup"));
16966 listlenbits
= inst
.operands
[1].imm
- 1;
16967 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16968 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16969 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16970 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16971 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16972 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16973 inst
.instruction
|= listlenbits
<< 8;
16975 neon_dp_fixup (&inst
);
16979 do_neon_ldm_stm (void)
16981 /* P, U and L bits are part of bitmask. */
16982 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16983 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16985 if (inst
.operands
[1].issingle
)
16987 do_vfp_nsyn_ldm_stm (is_dbmode
);
16991 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16992 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16994 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16995 _("register list must contain at least 1 and at most 16 "
16998 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16999 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17000 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17001 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17003 inst
.instruction
|= offsetbits
;
17005 do_vfp_cond_or_thumb ();
17009 do_neon_ldr_str (void)
17011 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17013 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17014 And is UNPREDICTABLE in thumb mode. */
17016 && inst
.operands
[1].reg
== REG_PC
17017 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17020 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17021 else if (warn_on_deprecated
)
17022 as_tsktsk (_("Use of PC here is deprecated"));
17025 if (inst
.operands
[0].issingle
)
17028 do_vfp_nsyn_opcode ("flds");
17030 do_vfp_nsyn_opcode ("fsts");
17032 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17033 if (inst
.vectype
.el
[0].size
== 16)
17034 do_scalar_fp16_v82_encode ();
17039 do_vfp_nsyn_opcode ("fldd");
17041 do_vfp_nsyn_opcode ("fstd");
17045 /* "interleave" version also handles non-interleaving register VLD1/VST1
17049 do_neon_ld_st_interleave (void)
17051 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17052 N_8
| N_16
| N_32
| N_64
);
17053 unsigned alignbits
= 0;
17055 /* The bits in this table go:
17056 0: register stride of one (0) or two (1)
17057 1,2: register list length, minus one (1, 2, 3, 4).
17058 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17059 We use -1 for invalid entries. */
17060 const int typetable
[] =
17062 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17063 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17064 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17065 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17069 if (et
.type
== NT_invtype
)
17072 if (inst
.operands
[1].immisalign
)
17073 switch (inst
.operands
[1].imm
>> 8)
17075 case 64: alignbits
= 1; break;
17077 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17078 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17079 goto bad_alignment
;
17083 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17084 goto bad_alignment
;
17089 first_error (_("bad alignment"));
17093 inst
.instruction
|= alignbits
<< 4;
17094 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17096 /* Bits [4:6] of the immediate in a list specifier encode register stride
17097 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17098 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17099 up the right value for "type" in a table based on this value and the given
17100 list style, then stick it back. */
17101 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17102 | (((inst
.instruction
>> 8) & 3) << 3);
17104 typebits
= typetable
[idx
];
17106 constraint (typebits
== -1, _("bad list type for instruction"));
17107 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17108 _("bad element type for instruction"));
17110 inst
.instruction
&= ~0xf00;
17111 inst
.instruction
|= typebits
<< 8;
17114 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17115 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17116 otherwise. The variable arguments are a list of pairs of legal (size, align)
17117 values, terminated with -1. */
17120 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17123 int result
= FAIL
, thissize
, thisalign
;
17125 if (!inst
.operands
[1].immisalign
)
17131 va_start (ap
, do_alignment
);
17135 thissize
= va_arg (ap
, int);
17136 if (thissize
== -1)
17138 thisalign
= va_arg (ap
, int);
17140 if (size
== thissize
&& align
== thisalign
)
17143 while (result
!= SUCCESS
);
17147 if (result
== SUCCESS
)
17150 first_error (_("unsupported alignment for instruction"));
17156 do_neon_ld_st_lane (void)
17158 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17159 int align_good
, do_alignment
= 0;
17160 int logsize
= neon_logbits (et
.size
);
17161 int align
= inst
.operands
[1].imm
>> 8;
17162 int n
= (inst
.instruction
>> 8) & 3;
17163 int max_el
= 64 / et
.size
;
17165 if (et
.type
== NT_invtype
)
17168 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17169 _("bad list length"));
17170 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17171 _("scalar index out of range"));
17172 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17174 _("stride of 2 unavailable when element size is 8"));
17178 case 0: /* VLD1 / VST1. */
17179 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17181 if (align_good
== FAIL
)
17185 unsigned alignbits
= 0;
17188 case 16: alignbits
= 0x1; break;
17189 case 32: alignbits
= 0x3; break;
17192 inst
.instruction
|= alignbits
<< 4;
17196 case 1: /* VLD2 / VST2. */
17197 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17198 16, 32, 32, 64, -1);
17199 if (align_good
== FAIL
)
17202 inst
.instruction
|= 1 << 4;
17205 case 2: /* VLD3 / VST3. */
17206 constraint (inst
.operands
[1].immisalign
,
17207 _("can't use alignment with this instruction"));
17210 case 3: /* VLD4 / VST4. */
17211 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17212 16, 64, 32, 64, 32, 128, -1);
17213 if (align_good
== FAIL
)
17217 unsigned alignbits
= 0;
17220 case 8: alignbits
= 0x1; break;
17221 case 16: alignbits
= 0x1; break;
17222 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17225 inst
.instruction
|= alignbits
<< 4;
17232 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17233 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17234 inst
.instruction
|= 1 << (4 + logsize
);
17236 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17237 inst
.instruction
|= logsize
<< 10;
17240 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17243 do_neon_ld_dup (void)
17245 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17246 int align_good
, do_alignment
= 0;
17248 if (et
.type
== NT_invtype
)
17251 switch ((inst
.instruction
>> 8) & 3)
17253 case 0: /* VLD1. */
17254 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17255 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17256 &do_alignment
, 16, 16, 32, 32, -1);
17257 if (align_good
== FAIL
)
17259 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17262 case 2: inst
.instruction
|= 1 << 5; break;
17263 default: first_error (_("bad list length")); return;
17265 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17268 case 1: /* VLD2. */
17269 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17270 &do_alignment
, 8, 16, 16, 32, 32, 64,
17272 if (align_good
== FAIL
)
17274 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17275 _("bad list length"));
17276 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17277 inst
.instruction
|= 1 << 5;
17278 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17281 case 2: /* VLD3. */
17282 constraint (inst
.operands
[1].immisalign
,
17283 _("can't use alignment with this instruction"));
17284 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17285 _("bad list length"));
17286 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17287 inst
.instruction
|= 1 << 5;
17288 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17291 case 3: /* VLD4. */
17293 int align
= inst
.operands
[1].imm
>> 8;
17294 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17295 16, 64, 32, 64, 32, 128, -1);
17296 if (align_good
== FAIL
)
17298 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17299 _("bad list length"));
17300 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17301 inst
.instruction
|= 1 << 5;
17302 if (et
.size
== 32 && align
== 128)
17303 inst
.instruction
|= 0x3 << 6;
17305 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17312 inst
.instruction
|= do_alignment
<< 4;
17315 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17316 apart from bits [11:4]. */
17319 do_neon_ldx_stx (void)
17321 if (inst
.operands
[1].isreg
)
17322 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17324 switch (NEON_LANE (inst
.operands
[0].imm
))
17326 case NEON_INTERLEAVE_LANES
:
17327 NEON_ENCODE (INTERLV
, inst
);
17328 do_neon_ld_st_interleave ();
17331 case NEON_ALL_LANES
:
17332 NEON_ENCODE (DUP
, inst
);
17333 if (inst
.instruction
== N_INV
)
17335 first_error ("only loads support such operands");
17342 NEON_ENCODE (LANE
, inst
);
17343 do_neon_ld_st_lane ();
17346 /* L bit comes from bit mask. */
17347 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17348 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17349 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17351 if (inst
.operands
[1].postind
)
17353 int postreg
= inst
.operands
[1].imm
& 0xf;
17354 constraint (!inst
.operands
[1].immisreg
,
17355 _("post-index must be a register"));
17356 constraint (postreg
== 0xd || postreg
== 0xf,
17357 _("bad register for post-index"));
17358 inst
.instruction
|= postreg
;
17362 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17363 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17364 || inst
.reloc
.exp
.X_add_number
!= 0,
17367 if (inst
.operands
[1].writeback
)
17369 inst
.instruction
|= 0xd;
17372 inst
.instruction
|= 0xf;
17376 inst
.instruction
|= 0xf9000000;
17378 inst
.instruction
|= 0xf4000000;
17383 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17385 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17386 D register operands. */
17387 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17388 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17391 NEON_ENCODE (FPV8
, inst
);
17393 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17395 do_vfp_sp_dyadic ();
17397 /* ARMv8.2 fp16 instruction. */
17399 do_scalar_fp16_v82_encode ();
17402 do_vfp_dp_rd_rn_rm ();
17405 inst
.instruction
|= 0x100;
17407 inst
.instruction
|= 0xf0000000;
17413 set_it_insn_type (OUTSIDE_IT_INSN
);
17415 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17416 first_error (_("invalid instruction shape"));
17422 set_it_insn_type (OUTSIDE_IT_INSN
);
17424 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17427 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17430 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17434 do_vrint_1 (enum neon_cvt_mode mode
)
17436 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17437 struct neon_type_el et
;
17442 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17443 D register operands. */
17444 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17445 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17448 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17450 if (et
.type
!= NT_invtype
)
17452 /* VFP encodings. */
17453 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17454 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17455 set_it_insn_type (OUTSIDE_IT_INSN
);
17457 NEON_ENCODE (FPV8
, inst
);
17458 if (rs
== NS_FF
|| rs
== NS_HH
)
17459 do_vfp_sp_monadic ();
17461 do_vfp_dp_rd_rm ();
17465 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17466 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17467 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17468 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17469 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17470 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17471 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17475 inst
.instruction
|= (rs
== NS_DD
) << 8;
17476 do_vfp_cond_or_thumb ();
17478 /* ARMv8.2 fp16 vrint instruction. */
17480 do_scalar_fp16_v82_encode ();
17484 /* Neon encodings (or something broken...). */
17486 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17488 if (et
.type
== NT_invtype
)
17491 set_it_insn_type (OUTSIDE_IT_INSN
);
17492 NEON_ENCODE (FLOAT
, inst
);
17494 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17497 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17498 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17499 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17500 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17501 inst
.instruction
|= neon_quad (rs
) << 6;
17502 /* Mask off the original size bits and reencode them. */
17503 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17504 | neon_logbits (et
.size
) << 18);
17508 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17509 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17510 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17511 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17512 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17513 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17514 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17519 inst
.instruction
|= 0xfc000000;
17521 inst
.instruction
|= 0xf0000000;
17528 do_vrint_1 (neon_cvt_mode_x
);
17534 do_vrint_1 (neon_cvt_mode_z
);
17540 do_vrint_1 (neon_cvt_mode_r
);
17546 do_vrint_1 (neon_cvt_mode_a
);
17552 do_vrint_1 (neon_cvt_mode_n
);
17558 do_vrint_1 (neon_cvt_mode_p
);
17564 do_vrint_1 (neon_cvt_mode_m
);
17568 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17570 unsigned regno
= NEON_SCALAR_REG (opnd
);
17571 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17573 if (elsize
== 16 && elno
< 2 && regno
< 16)
17574 return regno
| (elno
<< 4);
17575 else if (elsize
== 32 && elno
== 0)
17578 first_error (_("scalar out of range"));
17585 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17587 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17588 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17589 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17590 _("immediate out of range"));
17592 if (inst
.operands
[2].isscalar
)
17594 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17595 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17596 N_KEY
| N_F16
| N_F32
).size
;
17597 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17599 inst
.instruction
= 0xfe000800;
17600 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17601 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17602 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17603 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17604 inst
.instruction
|= LOW4 (m
);
17605 inst
.instruction
|= HI1 (m
) << 5;
17606 inst
.instruction
|= neon_quad (rs
) << 6;
17607 inst
.instruction
|= rot
<< 20;
17608 inst
.instruction
|= (size
== 32) << 23;
17612 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17613 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17614 N_KEY
| N_F16
| N_F32
).size
;
17615 neon_three_same (neon_quad (rs
), 0, -1);
17616 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17617 inst
.instruction
|= 0xfc200800;
17618 inst
.instruction
|= rot
<< 23;
17619 inst
.instruction
|= (size
== 32) << 20;
17626 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17628 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17629 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17630 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17631 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17632 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17633 N_KEY
| N_F16
| N_F32
).size
;
17634 neon_three_same (neon_quad (rs
), 0, -1);
17635 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17636 inst
.instruction
|= 0xfc800800;
17637 inst
.instruction
|= (rot
== 270) << 24;
17638 inst
.instruction
|= (size
== 32) << 20;
17641 /* Dot Product instructions encoding support. */
17644 do_neon_dotproduct (int unsigned_p
)
17646 enum neon_shape rs
;
17647 unsigned scalar_oprd2
= 0;
17650 if (inst
.cond
!= COND_ALWAYS
)
17651 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17652 "is UNPREDICTABLE"));
17654 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17657 /* Dot Product instructions are in three-same D/Q register format or the third
17658 operand can be a scalar index register. */
17659 if (inst
.operands
[2].isscalar
)
17661 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17662 high8
= 0xfe000000;
17663 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17667 high8
= 0xfc000000;
17668 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17672 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17674 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17676 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17677 Product instruction, so we pass 0 as the "ubit" parameter. And the
17678 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17679 neon_three_same (neon_quad (rs
), 0, 32);
17681 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17682 different NEON three-same encoding. */
17683 inst
.instruction
&= 0x00ffffff;
17684 inst
.instruction
|= high8
;
17685 /* Encode 'U' bit which indicates signedness. */
17686 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17687 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17688 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17689 the instruction encoding. */
17690 if (inst
.operands
[2].isscalar
)
17692 inst
.instruction
&= 0xffffffd0;
17693 inst
.instruction
|= LOW4 (scalar_oprd2
);
17694 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17698 /* Dot Product instructions for signed integer. */
17701 do_neon_dotproduct_s (void)
17703 return do_neon_dotproduct (0);
17706 /* Dot Product instructions for unsigned integer. */
17709 do_neon_dotproduct_u (void)
17711 return do_neon_dotproduct (1);
17714 /* Crypto v1 instructions. */
17716 do_crypto_2op_1 (unsigned elttype
, int op
)
17718 set_it_insn_type (OUTSIDE_IT_INSN
);
17720 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17726 NEON_ENCODE (INTEGER
, inst
);
17727 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17728 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17729 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17730 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17732 inst
.instruction
|= op
<< 6;
17735 inst
.instruction
|= 0xfc000000;
17737 inst
.instruction
|= 0xf0000000;
17741 do_crypto_3op_1 (int u
, int op
)
17743 set_it_insn_type (OUTSIDE_IT_INSN
);
17745 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17746 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17751 NEON_ENCODE (INTEGER
, inst
);
17752 neon_three_same (1, u
, 8 << op
);
17758 do_crypto_2op_1 (N_8
, 0);
17764 do_crypto_2op_1 (N_8
, 1);
17770 do_crypto_2op_1 (N_8
, 2);
17776 do_crypto_2op_1 (N_8
, 3);
17782 do_crypto_3op_1 (0, 0);
17788 do_crypto_3op_1 (0, 1);
17794 do_crypto_3op_1 (0, 2);
17800 do_crypto_3op_1 (0, 3);
17806 do_crypto_3op_1 (1, 0);
17812 do_crypto_3op_1 (1, 1);
17816 do_sha256su1 (void)
17818 do_crypto_3op_1 (1, 2);
17824 do_crypto_2op_1 (N_32
, -1);
17830 do_crypto_2op_1 (N_32
, 0);
17834 do_sha256su0 (void)
17836 do_crypto_2op_1 (N_32
, 1);
17840 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17842 unsigned int Rd
= inst
.operands
[0].reg
;
17843 unsigned int Rn
= inst
.operands
[1].reg
;
17844 unsigned int Rm
= inst
.operands
[2].reg
;
17846 set_it_insn_type (OUTSIDE_IT_INSN
);
17847 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17848 inst
.instruction
|= LOW4 (Rn
) << 16;
17849 inst
.instruction
|= LOW4 (Rm
);
17850 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17851 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17853 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17854 as_warn (UNPRED_REG ("r15"));
17896 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17898 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17899 do_vfp_sp_dp_cvt ();
17900 do_vfp_cond_or_thumb ();
17904 /* Overall per-instruction processing. */
17906 /* We need to be able to fix up arbitrary expressions in some statements.
17907 This is so that we can handle symbols that are an arbitrary distance from
17908 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17909 which returns part of an address in a form which will be valid for
17910 a data instruction. We do this by pushing the expression into a symbol
17911 in the expr_section, and creating a fix for that. */
17914 fix_new_arm (fragS
* frag
,
17928 /* Create an absolute valued symbol, so we have something to
17929 refer to in the object file. Unfortunately for us, gas's
17930 generic expression parsing will already have folded out
17931 any use of .set foo/.type foo %function that may have
17932 been used to set type information of the target location,
17933 that's being specified symbolically. We have to presume
17934 the user knows what they are doing. */
17938 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17940 symbol
= symbol_find_or_make (name
);
17941 S_SET_SEGMENT (symbol
, absolute_section
);
17942 symbol_set_frag (symbol
, &zero_address_frag
);
17943 S_SET_VALUE (symbol
, exp
->X_add_number
);
17944 exp
->X_op
= O_symbol
;
17945 exp
->X_add_symbol
= symbol
;
17946 exp
->X_add_number
= 0;
17952 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17953 (enum bfd_reloc_code_real
) reloc
);
17957 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17958 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17962 /* Mark whether the fix is to a THUMB instruction, or an ARM
17964 new_fix
->tc_fix_data
= thumb_mode
;
17967 /* Create a frg for an instruction requiring relaxation. */
17969 output_relax_insn (void)
17975 /* The size of the instruction is unknown, so tie the debug info to the
17976 start of the instruction. */
17977 dwarf2_emit_insn (0);
17979 switch (inst
.reloc
.exp
.X_op
)
17982 sym
= inst
.reloc
.exp
.X_add_symbol
;
17983 offset
= inst
.reloc
.exp
.X_add_number
;
17987 offset
= inst
.reloc
.exp
.X_add_number
;
17990 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17994 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17995 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17996 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17999 /* Write a 32-bit thumb instruction to buf. */
18001 put_thumb32_insn (char * buf
, unsigned long insn
)
18003 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18004 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18008 output_inst (const char * str
)
18014 as_bad ("%s -- `%s'", inst
.error
, str
);
18019 output_relax_insn ();
18022 if (inst
.size
== 0)
18025 to
= frag_more (inst
.size
);
18026 /* PR 9814: Record the thumb mode into the current frag so that we know
18027 what type of NOP padding to use, if necessary. We override any previous
18028 setting so that if the mode has changed then the NOPS that we use will
18029 match the encoding of the last instruction in the frag. */
18030 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18032 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18034 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18035 put_thumb32_insn (to
, inst
.instruction
);
18037 else if (inst
.size
> INSN_SIZE
)
18039 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18040 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18041 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18044 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18046 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
18047 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18048 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
18051 dwarf2_emit_insn (inst
.size
);
18055 output_it_inst (int cond
, int mask
, char * to
)
18057 unsigned long instruction
= 0xbf00;
18060 instruction
|= mask
;
18061 instruction
|= cond
<< 4;
18065 to
= frag_more (2);
18067 dwarf2_emit_insn (2);
18071 md_number_to_chars (to
, instruction
, 2);
18076 /* Tag values used in struct asm_opcode's tag field. */
18079 OT_unconditional
, /* Instruction cannot be conditionalized.
18080 The ARM condition field is still 0xE. */
18081 OT_unconditionalF
, /* Instruction cannot be conditionalized
18082 and carries 0xF in its ARM condition field. */
18083 OT_csuffix
, /* Instruction takes a conditional suffix. */
18084 OT_csuffixF
, /* Some forms of the instruction take a conditional
18085 suffix, others place 0xF where the condition field
18087 OT_cinfix3
, /* Instruction takes a conditional infix,
18088 beginning at character index 3. (In
18089 unified mode, it becomes a suffix.) */
18090 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18091 tsts, cmps, cmns, and teqs. */
18092 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18093 character index 3, even in unified mode. Used for
18094 legacy instructions where suffix and infix forms
18095 may be ambiguous. */
18096 OT_csuf_or_in3
, /* Instruction takes either a conditional
18097 suffix or an infix at character index 3. */
18098 OT_odd_infix_unc
, /* This is the unconditional variant of an
18099 instruction that takes a conditional infix
18100 at an unusual position. In unified mode,
18101 this variant will accept a suffix. */
18102 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18103 are the conditional variants of instructions that
18104 take conditional infixes in unusual positions.
18105 The infix appears at character index
18106 (tag - OT_odd_infix_0). These are not accepted
18107 in unified mode. */
18110 /* Subroutine of md_assemble, responsible for looking up the primary
18111 opcode from the mnemonic the user wrote. STR points to the
18112 beginning of the mnemonic.
18114 This is not simply a hash table lookup, because of conditional
18115 variants. Most instructions have conditional variants, which are
18116 expressed with a _conditional affix_ to the mnemonic. If we were
18117 to encode each conditional variant as a literal string in the opcode
18118 table, it would have approximately 20,000 entries.
18120 Most mnemonics take this affix as a suffix, and in unified syntax,
18121 'most' is upgraded to 'all'. However, in the divided syntax, some
18122 instructions take the affix as an infix, notably the s-variants of
18123 the arithmetic instructions. Of those instructions, all but six
18124 have the infix appear after the third character of the mnemonic.
18126 Accordingly, the algorithm for looking up primary opcodes given
18129 1. Look up the identifier in the opcode table.
18130 If we find a match, go to step U.
18132 2. Look up the last two characters of the identifier in the
18133 conditions table. If we find a match, look up the first N-2
18134 characters of the identifier in the opcode table. If we
18135 find a match, go to step CE.
18137 3. Look up the fourth and fifth characters of the identifier in
18138 the conditions table. If we find a match, extract those
18139 characters from the identifier, and look up the remaining
18140 characters in the opcode table. If we find a match, go
18145 U. Examine the tag field of the opcode structure, in case this is
18146 one of the six instructions with its conditional infix in an
18147 unusual place. If it is, the tag tells us where to find the
18148 infix; look it up in the conditions table and set inst.cond
18149 accordingly. Otherwise, this is an unconditional instruction.
18150 Again set inst.cond accordingly. Return the opcode structure.
18152 CE. Examine the tag field to make sure this is an instruction that
18153 should receive a conditional suffix. If it is not, fail.
18154 Otherwise, set inst.cond from the suffix we already looked up,
18155 and return the opcode structure.
18157 CM. Examine the tag field to make sure this is an instruction that
18158 should receive a conditional infix after the third character.
18159 If it is not, fail. Otherwise, undo the edits to the current
18160 line of input and proceed as for case CE. */
18162 static const struct asm_opcode
*
18163 opcode_lookup (char **str
)
18167 const struct asm_opcode
*opcode
;
18168 const struct asm_cond
*cond
;
18171 /* Scan up to the end of the mnemonic, which must end in white space,
18172 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18173 for (base
= end
= *str
; *end
!= '\0'; end
++)
18174 if (*end
== ' ' || *end
== '.')
18180 /* Handle a possible width suffix and/or Neon type suffix. */
18185 /* The .w and .n suffixes are only valid if the unified syntax is in
18187 if (unified_syntax
&& end
[1] == 'w')
18189 else if (unified_syntax
&& end
[1] == 'n')
18194 inst
.vectype
.elems
= 0;
18196 *str
= end
+ offset
;
18198 if (end
[offset
] == '.')
18200 /* See if we have a Neon type suffix (possible in either unified or
18201 non-unified ARM syntax mode). */
18202 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18205 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18211 /* Look for unaffixed or special-case affixed mnemonic. */
18212 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18217 if (opcode
->tag
< OT_odd_infix_0
)
18219 inst
.cond
= COND_ALWAYS
;
18223 if (warn_on_deprecated
&& unified_syntax
)
18224 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18225 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18226 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18229 inst
.cond
= cond
->value
;
18233 /* Cannot have a conditional suffix on a mnemonic of less than two
18235 if (end
- base
< 3)
18238 /* Look for suffixed mnemonic. */
18240 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18241 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18243 if (opcode
&& cond
)
18246 switch (opcode
->tag
)
18248 case OT_cinfix3_legacy
:
18249 /* Ignore conditional suffixes matched on infix only mnemonics. */
18253 case OT_cinfix3_deprecated
:
18254 case OT_odd_infix_unc
:
18255 if (!unified_syntax
)
18257 /* Fall through. */
18261 case OT_csuf_or_in3
:
18262 inst
.cond
= cond
->value
;
18265 case OT_unconditional
:
18266 case OT_unconditionalF
:
18268 inst
.cond
= cond
->value
;
18271 /* Delayed diagnostic. */
18272 inst
.error
= BAD_COND
;
18273 inst
.cond
= COND_ALWAYS
;
18282 /* Cannot have a usual-position infix on a mnemonic of less than
18283 six characters (five would be a suffix). */
18284 if (end
- base
< 6)
18287 /* Look for infixed mnemonic in the usual position. */
18289 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18293 memcpy (save
, affix
, 2);
18294 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18295 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18297 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18298 memcpy (affix
, save
, 2);
18301 && (opcode
->tag
== OT_cinfix3
18302 || opcode
->tag
== OT_cinfix3_deprecated
18303 || opcode
->tag
== OT_csuf_or_in3
18304 || opcode
->tag
== OT_cinfix3_legacy
))
18307 if (warn_on_deprecated
&& unified_syntax
18308 && (opcode
->tag
== OT_cinfix3
18309 || opcode
->tag
== OT_cinfix3_deprecated
))
18310 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18312 inst
.cond
= cond
->value
;
18319 /* This function generates an initial IT instruction, leaving its block
18320 virtually open for the new instructions. Eventually,
18321 the mask will be updated by now_it_add_mask () each time
18322 a new instruction needs to be included in the IT block.
18323 Finally, the block is closed with close_automatic_it_block ().
18324 The block closure can be requested either from md_assemble (),
18325 a tencode (), or due to a label hook. */
18328 new_automatic_it_block (int cond
)
18330 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18331 now_it
.mask
= 0x18;
18333 now_it
.block_length
= 1;
18334 mapping_state (MAP_THUMB
);
18335 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18336 now_it
.warn_deprecated
= FALSE
;
18337 now_it
.insn_cond
= TRUE
;
18340 /* Close an automatic IT block.
18341 See comments in new_automatic_it_block (). */
18344 close_automatic_it_block (void)
18346 now_it
.mask
= 0x10;
18347 now_it
.block_length
= 0;
18350 /* Update the mask of the current automatically-generated IT
18351 instruction. See comments in new_automatic_it_block (). */
18354 now_it_add_mask (int cond
)
18356 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18357 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18358 | ((bitvalue) << (nbit)))
18359 const int resulting_bit
= (cond
& 1);
18361 now_it
.mask
&= 0xf;
18362 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18364 (5 - now_it
.block_length
));
18365 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18367 ((5 - now_it
.block_length
) - 1) );
18368 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18371 #undef SET_BIT_VALUE
18374 /* The IT blocks handling machinery is accessed through the these functions:
18375 it_fsm_pre_encode () from md_assemble ()
18376 set_it_insn_type () optional, from the tencode functions
18377 set_it_insn_type_last () ditto
18378 in_it_block () ditto
18379 it_fsm_post_encode () from md_assemble ()
18380 force_automatic_it_block_close () from label handling functions
18383 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18384 initializing the IT insn type with a generic initial value depending
18385 on the inst.condition.
18386 2) During the tencode function, two things may happen:
18387 a) The tencode function overrides the IT insn type by
18388 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18389 b) The tencode function queries the IT block state by
18390 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18392 Both set_it_insn_type and in_it_block run the internal FSM state
18393 handling function (handle_it_state), because: a) setting the IT insn
18394 type may incur in an invalid state (exiting the function),
18395 and b) querying the state requires the FSM to be updated.
18396 Specifically we want to avoid creating an IT block for conditional
18397 branches, so it_fsm_pre_encode is actually a guess and we can't
18398 determine whether an IT block is required until the tencode () routine
18399 has decided what type of instruction this actually it.
18400 Because of this, if set_it_insn_type and in_it_block have to be used,
18401 set_it_insn_type has to be called first.
18403 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18404 determines the insn IT type depending on the inst.cond code.
18405 When a tencode () routine encodes an instruction that can be
18406 either outside an IT block, or, in the case of being inside, has to be
18407 the last one, set_it_insn_type_last () will determine the proper
18408 IT instruction type based on the inst.cond code. Otherwise,
18409 set_it_insn_type can be called for overriding that logic or
18410 for covering other cases.
18412 Calling handle_it_state () may not transition the IT block state to
18413 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18414 still queried. Instead, if the FSM determines that the state should
18415 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18416 after the tencode () function: that's what it_fsm_post_encode () does.
18418 Since in_it_block () calls the state handling function to get an
18419 updated state, an error may occur (due to invalid insns combination).
18420 In that case, inst.error is set.
18421 Therefore, inst.error has to be checked after the execution of
18422 the tencode () routine.
18424 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18425 any pending state change (if any) that didn't take place in
18426 handle_it_state () as explained above. */
18429 it_fsm_pre_encode (void)
18431 if (inst
.cond
!= COND_ALWAYS
)
18432 inst
.it_insn_type
= INSIDE_IT_INSN
;
18434 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18436 now_it
.state_handled
= 0;
18439 /* IT state FSM handling function. */
18442 handle_it_state (void)
18444 now_it
.state_handled
= 1;
18445 now_it
.insn_cond
= FALSE
;
18447 switch (now_it
.state
)
18449 case OUTSIDE_IT_BLOCK
:
18450 switch (inst
.it_insn_type
)
18452 case OUTSIDE_IT_INSN
:
18455 case INSIDE_IT_INSN
:
18456 case INSIDE_IT_LAST_INSN
:
18457 if (thumb_mode
== 0)
18460 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18461 as_tsktsk (_("Warning: conditional outside an IT block"\
18466 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18467 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18469 /* Automatically generate the IT instruction. */
18470 new_automatic_it_block (inst
.cond
);
18471 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18472 close_automatic_it_block ();
18476 inst
.error
= BAD_OUT_IT
;
18482 case IF_INSIDE_IT_LAST_INSN
:
18483 case NEUTRAL_IT_INSN
:
18487 now_it
.state
= MANUAL_IT_BLOCK
;
18488 now_it
.block_length
= 0;
18493 case AUTOMATIC_IT_BLOCK
:
18494 /* Three things may happen now:
18495 a) We should increment current it block size;
18496 b) We should close current it block (closing insn or 4 insns);
18497 c) We should close current it block and start a new one (due
18498 to incompatible conditions or
18499 4 insns-length block reached). */
18501 switch (inst
.it_insn_type
)
18503 case OUTSIDE_IT_INSN
:
18504 /* The closure of the block shall happen immediately,
18505 so any in_it_block () call reports the block as closed. */
18506 force_automatic_it_block_close ();
18509 case INSIDE_IT_INSN
:
18510 case INSIDE_IT_LAST_INSN
:
18511 case IF_INSIDE_IT_LAST_INSN
:
18512 now_it
.block_length
++;
18514 if (now_it
.block_length
> 4
18515 || !now_it_compatible (inst
.cond
))
18517 force_automatic_it_block_close ();
18518 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18519 new_automatic_it_block (inst
.cond
);
18523 now_it
.insn_cond
= TRUE
;
18524 now_it_add_mask (inst
.cond
);
18527 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18528 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18529 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18530 close_automatic_it_block ();
18533 case NEUTRAL_IT_INSN
:
18534 now_it
.block_length
++;
18535 now_it
.insn_cond
= TRUE
;
18537 if (now_it
.block_length
> 4)
18538 force_automatic_it_block_close ();
18540 now_it_add_mask (now_it
.cc
& 1);
18544 close_automatic_it_block ();
18545 now_it
.state
= MANUAL_IT_BLOCK
;
18550 case MANUAL_IT_BLOCK
:
18552 /* Check conditional suffixes. */
18553 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18556 now_it
.mask
&= 0x1f;
18557 is_last
= (now_it
.mask
== 0x10);
18558 now_it
.insn_cond
= TRUE
;
18560 switch (inst
.it_insn_type
)
18562 case OUTSIDE_IT_INSN
:
18563 inst
.error
= BAD_NOT_IT
;
18566 case INSIDE_IT_INSN
:
18567 if (cond
!= inst
.cond
)
18569 inst
.error
= BAD_IT_COND
;
18574 case INSIDE_IT_LAST_INSN
:
18575 case IF_INSIDE_IT_LAST_INSN
:
18576 if (cond
!= inst
.cond
)
18578 inst
.error
= BAD_IT_COND
;
18583 inst
.error
= BAD_BRANCH
;
18588 case NEUTRAL_IT_INSN
:
18589 /* The BKPT instruction is unconditional even in an IT block. */
18593 inst
.error
= BAD_IT_IT
;
18603 struct depr_insn_mask
18605 unsigned long pattern
;
18606 unsigned long mask
;
18607 const char* description
;
18610 /* List of 16-bit instruction patterns deprecated in an IT block in
18612 static const struct depr_insn_mask depr_it_insns
[] = {
18613 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18614 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18615 { 0xa000, 0xb800, N_("ADR") },
18616 { 0x4800, 0xf800, N_("Literal loads") },
18617 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18618 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18619 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18620 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18621 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18626 it_fsm_post_encode (void)
18630 if (!now_it
.state_handled
)
18631 handle_it_state ();
18633 if (now_it
.insn_cond
18634 && !now_it
.warn_deprecated
18635 && warn_on_deprecated
18636 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18637 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18639 if (inst
.instruction
>= 0x10000)
18641 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18642 "performance deprecated in ARMv8-A and ARMv8-R"));
18643 now_it
.warn_deprecated
= TRUE
;
18647 const struct depr_insn_mask
*p
= depr_it_insns
;
18649 while (p
->mask
!= 0)
18651 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18653 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18654 "instructions of the following class are "
18655 "performance deprecated in ARMv8-A and "
18656 "ARMv8-R: %s"), p
->description
);
18657 now_it
.warn_deprecated
= TRUE
;
18665 if (now_it
.block_length
> 1)
18667 as_tsktsk (_("IT blocks containing more than one conditional "
18668 "instruction are performance deprecated in ARMv8-A and "
18670 now_it
.warn_deprecated
= TRUE
;
18674 is_last
= (now_it
.mask
== 0x10);
18677 now_it
.state
= OUTSIDE_IT_BLOCK
;
18683 force_automatic_it_block_close (void)
18685 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18687 close_automatic_it_block ();
18688 now_it
.state
= OUTSIDE_IT_BLOCK
;
18696 if (!now_it
.state_handled
)
18697 handle_it_state ();
18699 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18702 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18703 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18704 here, hence the "known" in the function name. */
18707 known_t32_only_insn (const struct asm_opcode
*opcode
)
18709 /* Original Thumb-1 wide instruction. */
18710 if (opcode
->tencode
== do_t_blx
18711 || opcode
->tencode
== do_t_branch23
18712 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18713 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18716 /* Wide-only instruction added to ARMv8-M Baseline. */
18717 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18718 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18719 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18720 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18726 /* Whether wide instruction variant can be used if available for a valid OPCODE
18730 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18732 if (known_t32_only_insn (opcode
))
18735 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18736 of variant T3 of B.W is checked in do_t_branch. */
18737 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18738 && opcode
->tencode
== do_t_branch
)
18741 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18742 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18743 && opcode
->tencode
== do_t_mov_cmp
18744 /* Make sure CMP instruction is not affected. */
18745 && opcode
->aencode
== do_mov
)
18748 /* Wide instruction variants of all instructions with narrow *and* wide
18749 variants become available with ARMv6t2. Other opcodes are either
18750 narrow-only or wide-only and are thus available if OPCODE is valid. */
18751 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18754 /* OPCODE with narrow only instruction variant or wide variant not
18760 md_assemble (char *str
)
18763 const struct asm_opcode
* opcode
;
18765 /* Align the previous label if needed. */
18766 if (last_label_seen
!= NULL
)
18768 symbol_set_frag (last_label_seen
, frag_now
);
18769 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18770 S_SET_SEGMENT (last_label_seen
, now_seg
);
18773 memset (&inst
, '\0', sizeof (inst
));
18774 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18776 opcode
= opcode_lookup (&p
);
18779 /* It wasn't an instruction, but it might be a register alias of
18780 the form alias .req reg, or a Neon .dn/.qn directive. */
18781 if (! create_register_alias (str
, p
)
18782 && ! create_neon_reg_alias (str
, p
))
18783 as_bad (_("bad instruction `%s'"), str
);
18788 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18789 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18791 /* The value which unconditional instructions should have in place of the
18792 condition field. */
18793 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18797 arm_feature_set variant
;
18799 variant
= cpu_variant
;
18800 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18801 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18802 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18803 /* Check that this instruction is supported for this CPU. */
18804 if (!opcode
->tvariant
18805 || (thumb_mode
== 1
18806 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18808 if (opcode
->tencode
== do_t_swi
)
18809 as_bad (_("SVC is not permitted on this architecture"));
18811 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18814 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18815 && opcode
->tencode
!= do_t_branch
)
18817 as_bad (_("Thumb does not support conditional execution"));
18821 /* Two things are addressed here:
18822 1) Implicit require narrow instructions on Thumb-1.
18823 This avoids relaxation accidentally introducing Thumb-2
18825 2) Reject wide instructions in non Thumb-2 cores.
18827 Only instructions with narrow and wide variants need to be handled
18828 but selecting all non wide-only instructions is easier. */
18829 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18830 && !t32_insn_ok (variant
, opcode
))
18832 if (inst
.size_req
== 0)
18834 else if (inst
.size_req
== 4)
18836 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18837 as_bad (_("selected processor does not support 32bit wide "
18838 "variant of instruction `%s'"), str
);
18840 as_bad (_("selected processor does not support `%s' in "
18841 "Thumb-2 mode"), str
);
18846 inst
.instruction
= opcode
->tvalue
;
18848 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18850 /* Prepare the it_insn_type for those encodings that don't set
18852 it_fsm_pre_encode ();
18854 opcode
->tencode ();
18856 it_fsm_post_encode ();
18859 if (!(inst
.error
|| inst
.relax
))
18861 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18862 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18863 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18865 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18870 /* Something has gone badly wrong if we try to relax a fixed size
18872 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18874 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18875 *opcode
->tvariant
);
18876 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18877 set those bits when Thumb-2 32-bit instructions are seen. The impact
18878 of relaxable instructions will be considered later after we finish all
18880 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18881 variant
= arm_arch_none
;
18883 variant
= cpu_variant
;
18884 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18885 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18888 check_neon_suffixes
;
18892 mapping_state (MAP_THUMB
);
18895 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18899 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18900 is_bx
= (opcode
->aencode
== do_bx
);
18902 /* Check that this instruction is supported for this CPU. */
18903 if (!(is_bx
&& fix_v4bx
)
18904 && !(opcode
->avariant
&&
18905 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18907 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18912 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18916 inst
.instruction
= opcode
->avalue
;
18917 if (opcode
->tag
== OT_unconditionalF
)
18918 inst
.instruction
|= 0xFU
<< 28;
18920 inst
.instruction
|= inst
.cond
<< 28;
18921 inst
.size
= INSN_SIZE
;
18922 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18924 it_fsm_pre_encode ();
18925 opcode
->aencode ();
18926 it_fsm_post_encode ();
18928 /* Arm mode bx is marked as both v4T and v5 because it's still required
18929 on a hypothetical non-thumb v5 core. */
18931 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18933 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18934 *opcode
->avariant
);
18936 check_neon_suffixes
;
18940 mapping_state (MAP_ARM
);
18945 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18953 check_it_blocks_finished (void)
18958 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18959 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18960 == MANUAL_IT_BLOCK
)
18962 as_warn (_("section '%s' finished with an open IT block."),
18966 if (now_it
.state
== MANUAL_IT_BLOCK
)
18967 as_warn (_("file finished with an open IT block."));
18971 /* Various frobbings of labels and their addresses. */
18974 arm_start_line_hook (void)
18976 last_label_seen
= NULL
;
18980 arm_frob_label (symbolS
* sym
)
18982 last_label_seen
= sym
;
18984 ARM_SET_THUMB (sym
, thumb_mode
);
18986 #if defined OBJ_COFF || defined OBJ_ELF
18987 ARM_SET_INTERWORK (sym
, support_interwork
);
18990 force_automatic_it_block_close ();
18992 /* Note - do not allow local symbols (.Lxxx) to be labelled
18993 as Thumb functions. This is because these labels, whilst
18994 they exist inside Thumb code, are not the entry points for
18995 possible ARM->Thumb calls. Also, these labels can be used
18996 as part of a computed goto or switch statement. eg gcc
18997 can generate code that looks like this:
18999 ldr r2, [pc, .Laaa]
19009 The first instruction loads the address of the jump table.
19010 The second instruction converts a table index into a byte offset.
19011 The third instruction gets the jump address out of the table.
19012 The fourth instruction performs the jump.
19014 If the address stored at .Laaa is that of a symbol which has the
19015 Thumb_Func bit set, then the linker will arrange for this address
19016 to have the bottom bit set, which in turn would mean that the
19017 address computation performed by the third instruction would end
19018 up with the bottom bit set. Since the ARM is capable of unaligned
19019 word loads, the instruction would then load the incorrect address
19020 out of the jump table, and chaos would ensue. */
19021 if (label_is_thumb_function_name
19022 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19023 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19025 /* When the address of a Thumb function is taken the bottom
19026 bit of that address should be set. This will allow
19027 interworking between Arm and Thumb functions to work
19030 THUMB_SET_FUNC (sym
, 1);
19032 label_is_thumb_function_name
= FALSE
;
19035 dwarf2_emit_label (sym
);
19039 arm_data_in_code (void)
19041 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19043 *input_line_pointer
= '/';
19044 input_line_pointer
+= 5;
19045 *input_line_pointer
= 0;
19053 arm_canonicalize_symbol_name (char * name
)
19057 if (thumb_mode
&& (len
= strlen (name
)) > 5
19058 && streq (name
+ len
- 5, "/data"))
19059 *(name
+ len
- 5) = 0;
19064 /* Table of all register names defined by default. The user can
19065 define additional names with .req. Note that all register names
19066 should appear in both upper and lowercase variants. Some registers
19067 also have mixed-case names. */
19069 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19070 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19071 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19072 #define REGSET(p,t) \
19073 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19074 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19075 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19076 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19077 #define REGSETH(p,t) \
19078 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19079 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19080 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19081 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19082 #define REGSET2(p,t) \
19083 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19084 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19085 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19086 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19087 #define SPLRBANK(base,bank,t) \
19088 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19089 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19090 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19091 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19092 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19093 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19095 static const struct reg_entry reg_names
[] =
19097 /* ARM integer registers. */
19098 REGSET(r
, RN
), REGSET(R
, RN
),
19100 /* ATPCS synonyms. */
19101 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19102 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19103 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19105 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19106 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19107 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19109 /* Well-known aliases. */
19110 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19111 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19113 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19114 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19116 /* Coprocessor numbers. */
19117 REGSET(p
, CP
), REGSET(P
, CP
),
19119 /* Coprocessor register numbers. The "cr" variants are for backward
19121 REGSET(c
, CN
), REGSET(C
, CN
),
19122 REGSET(cr
, CN
), REGSET(CR
, CN
),
19124 /* ARM banked registers. */
19125 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19126 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19127 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19128 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19129 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19130 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19131 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19133 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19134 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19135 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19136 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19137 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19138 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19139 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19140 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19142 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19143 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19144 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19145 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19146 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19147 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19148 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19149 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19150 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19152 /* FPA registers. */
19153 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19154 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19156 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19157 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19159 /* VFP SP registers. */
19160 REGSET(s
,VFS
), REGSET(S
,VFS
),
19161 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19163 /* VFP DP Registers. */
19164 REGSET(d
,VFD
), REGSET(D
,VFD
),
19165 /* Extra Neon DP registers. */
19166 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19168 /* Neon QP registers. */
19169 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19171 /* VFP control registers. */
19172 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19173 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19174 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19175 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19176 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19177 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19178 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19180 /* Maverick DSP coprocessor registers. */
19181 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19182 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19184 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19185 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19186 REGDEF(dspsc
,0,DSPSC
),
19188 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19189 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19190 REGDEF(DSPSC
,0,DSPSC
),
19192 /* iWMMXt data registers - p0, c0-15. */
19193 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19195 /* iWMMXt control registers - p1, c0-3. */
19196 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19197 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19198 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19199 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19201 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19202 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19203 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19204 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19205 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19207 /* XScale accumulator registers. */
19208 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19214 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19215 within psr_required_here. */
19216 static const struct asm_psr psrs
[] =
19218 /* Backward compatibility notation. Note that "all" is no longer
19219 truly all possible PSR bits. */
19220 {"all", PSR_c
| PSR_f
},
19224 /* Individual flags. */
19230 /* Combinations of flags. */
19231 {"fs", PSR_f
| PSR_s
},
19232 {"fx", PSR_f
| PSR_x
},
19233 {"fc", PSR_f
| PSR_c
},
19234 {"sf", PSR_s
| PSR_f
},
19235 {"sx", PSR_s
| PSR_x
},
19236 {"sc", PSR_s
| PSR_c
},
19237 {"xf", PSR_x
| PSR_f
},
19238 {"xs", PSR_x
| PSR_s
},
19239 {"xc", PSR_x
| PSR_c
},
19240 {"cf", PSR_c
| PSR_f
},
19241 {"cs", PSR_c
| PSR_s
},
19242 {"cx", PSR_c
| PSR_x
},
19243 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19244 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19245 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19246 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19247 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19248 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19249 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19250 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19251 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19252 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19253 {"scf", PSR_s
| PSR_c
| PSR_f
},
19254 {"scx", PSR_s
| PSR_c
| PSR_x
},
19255 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19256 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19257 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19258 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19259 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19260 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19261 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19262 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19263 {"csf", PSR_c
| PSR_s
| PSR_f
},
19264 {"csx", PSR_c
| PSR_s
| PSR_x
},
19265 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19266 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19267 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19268 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19269 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19270 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19271 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19272 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19273 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19274 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19275 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19276 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19277 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19278 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19279 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19280 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19281 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19282 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19283 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19284 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19285 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19286 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19287 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19288 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19289 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19290 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19293 /* Table of V7M psr names. */
19294 static const struct asm_psr v7m_psrs
[] =
19296 {"apsr", 0x0 }, {"APSR", 0x0 },
19297 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19298 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19299 {"psr", 0x3 }, {"PSR", 0x3 },
19300 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19301 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19302 {"epsr", 0x6 }, {"EPSR", 0x6 },
19303 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19304 {"msp", 0x8 }, {"MSP", 0x8 },
19305 {"psp", 0x9 }, {"PSP", 0x9 },
19306 {"msplim", 0xa }, {"MSPLIM", 0xa },
19307 {"psplim", 0xb }, {"PSPLIM", 0xb },
19308 {"primask", 0x10}, {"PRIMASK", 0x10},
19309 {"basepri", 0x11}, {"BASEPRI", 0x11},
19310 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19311 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19312 {"control", 0x14}, {"CONTROL", 0x14},
19313 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19314 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19315 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19316 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19317 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19318 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19319 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19320 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19321 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19324 /* Table of all shift-in-operand names. */
19325 static const struct asm_shift_name shift_names
[] =
19327 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19328 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19329 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19330 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19331 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19332 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19335 /* Table of all explicit relocation names. */
19337 static struct reloc_entry reloc_names
[] =
19339 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19340 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19341 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19342 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19343 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19344 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19345 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19346 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19347 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19348 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19349 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19350 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19351 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19352 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19353 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19354 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19355 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19356 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19357 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19358 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19359 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19360 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19361 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19362 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19363 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19364 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19365 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19369 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19370 static const struct asm_cond conds
[] =
19374 {"cs", 0x2}, {"hs", 0x2},
19375 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19389 #define UL_BARRIER(L,U,CODE,FEAT) \
19390 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19391 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19393 static struct asm_barrier_opt barrier_opt_names
[] =
19395 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19396 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19397 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19398 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19399 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19400 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19401 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19402 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19403 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19404 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19405 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19406 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19407 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19408 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19409 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19410 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19415 /* Table of ARM-format instructions. */
19417 /* Macros for gluing together operand strings. N.B. In all cases
19418 other than OPS0, the trailing OP_stop comes from default
19419 zero-initialization of the unspecified elements of the array. */
19420 #define OPS0() { OP_stop, }
19421 #define OPS1(a) { OP_##a, }
19422 #define OPS2(a,b) { OP_##a,OP_##b, }
19423 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19424 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19425 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19426 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19428 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19429 This is useful when mixing operands for ARM and THUMB, i.e. using the
19430 MIX_ARM_THUMB_OPERANDS macro.
19431 In order to use these macros, prefix the number of operands with _
19433 #define OPS_1(a) { a, }
19434 #define OPS_2(a,b) { a,b, }
19435 #define OPS_3(a,b,c) { a,b,c, }
19436 #define OPS_4(a,b,c,d) { a,b,c,d, }
19437 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19438 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19440 /* These macros abstract out the exact format of the mnemonic table and
19441 save some repeated characters. */
19443 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19444 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19445 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19446 THUMB_VARIANT, do_##ae, do_##te }
19448 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19449 a T_MNEM_xyz enumerator. */
19450 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19451 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19452 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19453 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19455 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19456 infix after the third character. */
19457 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19458 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19459 THUMB_VARIANT, do_##ae, do_##te }
19460 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19461 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19462 THUMB_VARIANT, do_##ae, do_##te }
19463 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19464 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19465 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19466 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19467 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19468 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19469 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19470 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19472 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19473 field is still 0xE. Many of the Thumb variants can be executed
19474 conditionally, so this is checked separately. */
19475 #define TUE(mnem, op, top, nops, ops, ae, te) \
19476 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19477 THUMB_VARIANT, do_##ae, do_##te }
19479 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19480 Used by mnemonics that have very minimal differences in the encoding for
19481 ARM and Thumb variants and can be handled in a common function. */
19482 #define TUEc(mnem, op, top, nops, ops, en) \
19483 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19484 THUMB_VARIANT, do_##en, do_##en }
19486 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19487 condition code field. */
19488 #define TUF(mnem, op, top, nops, ops, ae, te) \
19489 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19490 THUMB_VARIANT, do_##ae, do_##te }
19492 /* ARM-only variants of all the above. */
19493 #define CE(mnem, op, nops, ops, ae) \
19494 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19496 #define C3(mnem, op, nops, ops, ae) \
19497 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19499 /* Thumb-only variants of TCE and TUE. */
19500 #define ToC(mnem, top, nops, ops, te) \
19501 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19504 #define ToU(mnem, top, nops, ops, te) \
19505 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19508 /* Legacy mnemonics that always have conditional infix after the third
19510 #define CL(mnem, op, nops, ops, ae) \
19511 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19512 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19514 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19515 #define cCE(mnem, op, nops, ops, ae) \
19516 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19518 /* Legacy coprocessor instructions where conditional infix and conditional
19519 suffix are ambiguous. For consistency this includes all FPA instructions,
19520 not just the potentially ambiguous ones. */
19521 #define cCL(mnem, op, nops, ops, ae) \
19522 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19523 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19525 /* Coprocessor, takes either a suffix or a position-3 infix
19526 (for an FPA corner case). */
19527 #define C3E(mnem, op, nops, ops, ae) \
19528 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19529 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19531 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19532 { m1 #m2 m3, OPS##nops ops, \
19533 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19534 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19536 #define CM(m1, m2, op, nops, ops, ae) \
19537 xCM_ (m1, , m2, op, nops, ops, ae), \
19538 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19539 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19540 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19541 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19542 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19543 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19544 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19545 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19546 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19547 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19548 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19549 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19550 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19551 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19552 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19553 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19554 xCM_ (m1, le, m2, op, nops, ops, ae), \
19555 xCM_ (m1, al, m2, op, nops, ops, ae)
19557 #define UE(mnem, op, nops, ops, ae) \
19558 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19560 #define UF(mnem, op, nops, ops, ae) \
19561 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19563 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19564 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19565 use the same encoding function for each. */
19566 #define NUF(mnem, op, nops, ops, enc) \
19567 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19568 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19570 /* Neon data processing, version which indirects through neon_enc_tab for
19571 the various overloaded versions of opcodes. */
19572 #define nUF(mnem, op, nops, ops, enc) \
19573 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19574 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19576 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19578 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19579 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19580 THUMB_VARIANT, do_##enc, do_##enc }
19582 #define NCE(mnem, op, nops, ops, enc) \
19583 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19585 #define NCEF(mnem, op, nops, ops, enc) \
19586 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19588 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19589 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19590 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19591 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19593 #define nCE(mnem, op, nops, ops, enc) \
19594 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19596 #define nCEF(mnem, op, nops, ops, enc) \
19597 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19601 static const struct asm_opcode insns
[] =
19603 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19604 #define THUMB_VARIANT & arm_ext_v4t
19605 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19606 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19607 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19608 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19609 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19610 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19611 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19612 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19613 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19614 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19615 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19616 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19617 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19618 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19619 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19620 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19622 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19623 for setting PSR flag bits. They are obsolete in V6 and do not
19624 have Thumb equivalents. */
19625 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19626 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19627 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19628 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19629 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19630 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19631 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19632 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19633 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19635 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19636 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19637 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19638 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19640 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19641 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19642 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19644 OP_ADDRGLDR
),ldst
, t_ldst
),
19645 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19647 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19648 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19649 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19650 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19651 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19652 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19654 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19655 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19658 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19659 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19660 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19661 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19663 /* Thumb-compatibility pseudo ops. */
19664 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19665 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19666 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19667 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19668 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19669 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19670 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19671 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19672 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19673 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19674 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19675 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19677 /* These may simplify to neg. */
19678 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19679 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19681 #undef THUMB_VARIANT
19682 #define THUMB_VARIANT & arm_ext_os
19684 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19685 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19687 #undef THUMB_VARIANT
19688 #define THUMB_VARIANT & arm_ext_v6
19690 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19692 /* V1 instructions with no Thumb analogue prior to V6T2. */
19693 #undef THUMB_VARIANT
19694 #define THUMB_VARIANT & arm_ext_v6t2
19696 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19697 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19698 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19700 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19701 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19702 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19703 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19705 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19706 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19708 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19709 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19711 /* V1 instructions with no Thumb analogue at all. */
19712 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19713 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19715 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19716 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19717 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19718 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19719 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19720 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19721 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19722 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19725 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19726 #undef THUMB_VARIANT
19727 #define THUMB_VARIANT & arm_ext_v4t
19729 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19730 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19732 #undef THUMB_VARIANT
19733 #define THUMB_VARIANT & arm_ext_v6t2
19735 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19736 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19738 /* Generic coprocessor instructions. */
19739 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19740 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19741 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19742 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19743 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19744 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19745 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19748 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19750 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19751 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19754 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19755 #undef THUMB_VARIANT
19756 #define THUMB_VARIANT & arm_ext_msr
19758 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19759 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19762 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19763 #undef THUMB_VARIANT
19764 #define THUMB_VARIANT & arm_ext_v6t2
19766 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19767 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19768 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19769 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19770 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19771 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19772 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19773 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19776 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_v4t
19780 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19781 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19782 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19783 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19784 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19785 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19788 #define ARM_VARIANT & arm_ext_v4t_5
19790 /* ARM Architecture 4T. */
19791 /* Note: bx (and blx) are required on V5, even if the processor does
19792 not support Thumb. */
19793 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19796 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19797 #undef THUMB_VARIANT
19798 #define THUMB_VARIANT & arm_ext_v5t
19800 /* Note: blx has 2 variants; the .value coded here is for
19801 BLX(2). Only this variant has conditional execution. */
19802 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19803 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19805 #undef THUMB_VARIANT
19806 #define THUMB_VARIANT & arm_ext_v6t2
19808 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19809 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19810 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19811 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19812 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19813 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19814 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19815 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19818 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19819 #undef THUMB_VARIANT
19820 #define THUMB_VARIANT & arm_ext_v5exp
19822 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19823 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19824 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19825 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19827 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19828 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19830 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19831 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19832 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19833 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19835 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19836 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19837 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19838 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19840 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19841 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19843 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19844 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19845 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19846 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19849 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19850 #undef THUMB_VARIANT
19851 #define THUMB_VARIANT & arm_ext_v6t2
19853 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19854 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19856 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19857 ADDRGLDRS
), ldrd
, t_ldstd
),
19859 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19860 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19863 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19865 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19868 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19869 #undef THUMB_VARIANT
19870 #define THUMB_VARIANT & arm_ext_v6
19872 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19873 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19874 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19875 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19876 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19877 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19878 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19879 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19880 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19881 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19883 #undef THUMB_VARIANT
19884 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19886 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19887 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19889 #undef THUMB_VARIANT
19890 #define THUMB_VARIANT & arm_ext_v6t2
19892 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19893 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19895 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19896 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19898 /* ARM V6 not included in V7M. */
19899 #undef THUMB_VARIANT
19900 #define THUMB_VARIANT & arm_ext_v6_notm
19901 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19902 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19903 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19904 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19905 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19906 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19907 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19908 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19909 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19910 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19911 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19912 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19913 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19914 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19915 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19916 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19917 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19918 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19919 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19921 /* ARM V6 not included in V7M (eg. integer SIMD). */
19922 #undef THUMB_VARIANT
19923 #define THUMB_VARIANT & arm_ext_v6_dsp
19924 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19925 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19926 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19927 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19928 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19929 /* Old name for QASX. */
19930 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19931 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19932 /* Old name for QSAX. */
19933 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19934 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19935 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19936 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19937 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19938 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19939 /* Old name for SASX. */
19940 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19941 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19942 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19943 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19944 /* Old name for SHASX. */
19945 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19946 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19947 /* Old name for SHSAX. */
19948 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19949 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19950 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19951 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19952 /* Old name for SSAX. */
19953 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19954 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19955 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19956 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19957 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19958 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19959 /* Old name for UASX. */
19960 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19961 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19962 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19963 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19964 /* Old name for UHASX. */
19965 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19966 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19967 /* Old name for UHSAX. */
19968 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19969 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19970 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19971 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19972 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19973 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19974 /* Old name for UQASX. */
19975 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19976 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19977 /* Old name for UQSAX. */
19978 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19979 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19980 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19981 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19982 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19983 /* Old name for USAX. */
19984 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19985 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19986 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19987 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19988 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19989 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19990 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19991 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19992 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19993 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19994 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19995 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19996 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19997 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19998 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19999 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20000 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20001 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20002 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20003 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20004 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20005 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20006 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20007 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20008 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20009 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20010 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20011 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20012 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20013 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
20014 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
20015 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20016 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20017 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20020 #define ARM_VARIANT & arm_ext_v6k_v6t2
20021 #undef THUMB_VARIANT
20022 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20024 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20025 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20026 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20027 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20029 #undef THUMB_VARIANT
20030 #define THUMB_VARIANT & arm_ext_v6_notm
20031 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20033 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20034 RRnpcb
), strexd
, t_strexd
),
20036 #undef THUMB_VARIANT
20037 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20038 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20040 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20042 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20044 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20046 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20049 #define ARM_VARIANT & arm_ext_sec
20050 #undef THUMB_VARIANT
20051 #define THUMB_VARIANT & arm_ext_sec
20053 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20056 #define ARM_VARIANT & arm_ext_virt
20057 #undef THUMB_VARIANT
20058 #define THUMB_VARIANT & arm_ext_virt
20060 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20061 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20064 #define ARM_VARIANT & arm_ext_pan
20065 #undef THUMB_VARIANT
20066 #define THUMB_VARIANT & arm_ext_pan
20068 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20071 #define ARM_VARIANT & arm_ext_v6t2
20072 #undef THUMB_VARIANT
20073 #define THUMB_VARIANT & arm_ext_v6t2
20075 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20076 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20077 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20078 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20080 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20081 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20083 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20084 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20085 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20086 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20089 #define ARM_VARIANT & arm_ext_v3
20090 #undef THUMB_VARIANT
20091 #define THUMB_VARIANT & arm_ext_v6t2
20093 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20094 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20095 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20098 #define ARM_VARIANT & arm_ext_v6t2
20099 #undef THUMB_VARIANT
20100 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20101 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20102 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20104 /* Thumb-only instructions. */
20106 #define ARM_VARIANT NULL
20107 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20108 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20110 /* ARM does not really have an IT instruction, so always allow it.
20111 The opcode is copied from Thumb in order to allow warnings in
20112 -mimplicit-it=[never | arm] modes. */
20114 #define ARM_VARIANT & arm_ext_v1
20115 #undef THUMB_VARIANT
20116 #define THUMB_VARIANT & arm_ext_v6t2
20118 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20119 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20120 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20121 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20122 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20123 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20124 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20125 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20126 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20127 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20128 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20129 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20130 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20131 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20132 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20133 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20134 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20135 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20137 /* Thumb2 only instructions. */
20139 #define ARM_VARIANT NULL
20141 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20142 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20143 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20144 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20145 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20146 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20148 /* Hardware division instructions. */
20150 #define ARM_VARIANT & arm_ext_adiv
20151 #undef THUMB_VARIANT
20152 #define THUMB_VARIANT & arm_ext_div
20154 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20155 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20157 /* ARM V6M/V7 instructions. */
20159 #define ARM_VARIANT & arm_ext_barrier
20160 #undef THUMB_VARIANT
20161 #define THUMB_VARIANT & arm_ext_barrier
20163 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20164 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20165 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20167 /* ARM V7 instructions. */
20169 #define ARM_VARIANT & arm_ext_v7
20170 #undef THUMB_VARIANT
20171 #define THUMB_VARIANT & arm_ext_v7
20173 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20174 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20177 #define ARM_VARIANT & arm_ext_mp
20178 #undef THUMB_VARIANT
20179 #define THUMB_VARIANT & arm_ext_mp
20181 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20183 /* AArchv8 instructions. */
20185 #define ARM_VARIANT & arm_ext_v8
20187 /* Instructions shared between armv8-a and armv8-m. */
20188 #undef THUMB_VARIANT
20189 #define THUMB_VARIANT & arm_ext_atomics
20191 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20192 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20193 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20194 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20195 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20196 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20197 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20198 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20199 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20200 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20202 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20204 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20206 #undef THUMB_VARIANT
20207 #define THUMB_VARIANT & arm_ext_v8
20209 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20210 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20212 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20215 /* Defined in V8 but is in undefined encoding space for earlier
20216 architectures. However earlier architectures are required to treat
20217 this instuction as a semihosting trap as well. Hence while not explicitly
20218 defined as such, it is in fact correct to define the instruction for all
20220 #undef THUMB_VARIANT
20221 #define THUMB_VARIANT & arm_ext_v1
20223 #define ARM_VARIANT & arm_ext_v1
20224 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20226 /* ARMv8 T32 only. */
20228 #define ARM_VARIANT NULL
20229 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20230 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20231 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20233 /* FP for ARMv8. */
20235 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20236 #undef THUMB_VARIANT
20237 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20239 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20240 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20241 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20242 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20243 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20244 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20245 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20246 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20247 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20248 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20249 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20250 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20251 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20252 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20253 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20254 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20255 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20257 /* Crypto v1 extensions. */
20259 #define ARM_VARIANT & fpu_crypto_ext_armv8
20260 #undef THUMB_VARIANT
20261 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20263 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20264 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20265 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20266 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20267 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20268 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20269 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20270 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20271 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20272 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20273 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20274 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20275 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20276 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20279 #define ARM_VARIANT & crc_ext_armv8
20280 #undef THUMB_VARIANT
20281 #define THUMB_VARIANT & crc_ext_armv8
20282 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20283 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20284 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20285 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20286 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20287 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20289 /* ARMv8.2 RAS extension. */
20291 #define ARM_VARIANT & arm_ext_ras
20292 #undef THUMB_VARIANT
20293 #define THUMB_VARIANT & arm_ext_ras
20294 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20297 #define ARM_VARIANT & arm_ext_v8_3
20298 #undef THUMB_VARIANT
20299 #define THUMB_VARIANT & arm_ext_v8_3
20300 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20301 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20302 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20305 #define ARM_VARIANT & fpu_neon_ext_dotprod
20306 #undef THUMB_VARIANT
20307 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20308 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20309 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20312 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20313 #undef THUMB_VARIANT
20314 #define THUMB_VARIANT NULL
20316 cCE("wfs", e200110
, 1, (RR
), rd
),
20317 cCE("rfs", e300110
, 1, (RR
), rd
),
20318 cCE("wfc", e400110
, 1, (RR
), rd
),
20319 cCE("rfc", e500110
, 1, (RR
), rd
),
20321 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20322 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20323 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20324 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20326 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20327 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20328 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20329 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20331 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20414 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20415 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20417 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20418 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20419 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20420 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20422 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20423 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20424 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20425 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20426 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20427 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20428 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20429 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20430 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20431 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20432 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20433 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20435 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20436 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20437 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20438 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20439 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20440 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20441 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20442 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20444 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20446 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20453 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20454 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20457 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20459 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20466 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20467 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20470 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20472 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20479 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20480 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20482 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20483 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20484 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20485 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20487 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20488 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20489 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20490 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20491 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20492 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20493 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20494 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20495 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20496 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20497 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20498 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20500 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20501 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20502 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20503 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20504 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20505 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20506 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20507 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20508 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20509 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20510 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20511 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20513 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20514 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20515 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20516 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20517 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20518 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20519 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20520 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20521 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20522 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20523 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20524 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20526 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20527 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20528 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20529 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20530 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20531 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20532 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20533 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20534 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20535 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20536 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20537 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20539 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20583 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20584 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20586 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20587 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20588 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20589 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20591 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20592 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20593 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20594 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20595 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20596 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20597 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20598 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20599 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20600 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20601 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20602 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20604 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20605 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20606 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20607 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20608 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20609 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20610 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20611 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20612 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20613 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20614 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20615 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20617 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20618 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20619 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20620 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20621 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20622 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20623 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20624 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20625 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20626 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20627 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20628 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20630 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20631 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20632 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20633 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20634 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20635 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20636 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20637 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20638 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20639 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20640 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20641 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20643 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20644 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20645 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20646 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20647 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20648 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20649 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20650 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20651 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20652 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20653 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20654 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20656 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20657 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20658 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20659 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20660 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20661 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20662 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20663 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20664 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20665 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20666 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20667 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20669 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20670 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20671 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20672 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20673 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20674 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20675 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20676 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20677 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20678 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20679 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20680 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20682 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20683 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20684 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20685 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20686 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20687 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20688 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20689 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20690 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20691 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20692 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20693 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20695 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20696 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20697 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20698 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20699 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20700 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20701 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20702 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20703 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20704 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20705 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20706 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20708 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20709 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20710 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20711 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20713 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20714 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20715 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20716 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20717 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20718 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20719 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20720 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20721 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20722 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20723 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20724 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20726 /* The implementation of the FIX instruction is broken on some
20727 assemblers, in that it accepts a precision specifier as well as a
20728 rounding specifier, despite the fact that this is meaningless.
20729 To be more compatible, we accept it as well, though of course it
20730 does not set any bits. */
20731 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20732 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20733 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20734 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20735 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20736 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20737 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20738 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20739 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20740 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20741 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20742 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20743 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20745 /* Instructions that were new with the real FPA, call them V2. */
20747 #define ARM_VARIANT & fpu_fpa_ext_v2
20749 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20750 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20751 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20752 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20753 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20754 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20757 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20759 /* Moves and type conversions. */
20760 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20761 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20762 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20763 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20764 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20765 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20766 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20767 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20768 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20769 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20770 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20771 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20772 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20773 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20775 /* Memory operations. */
20776 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20777 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20778 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20779 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20780 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20781 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20782 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20783 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20784 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20785 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20786 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20787 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20788 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20789 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20790 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20791 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20792 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20793 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20795 /* Monadic operations. */
20796 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20797 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20798 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20800 /* Dyadic operations. */
20801 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20802 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20803 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20804 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20805 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20806 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20807 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20808 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20809 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20812 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20813 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20814 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20815 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20817 /* Double precision load/store are still present on single precision
20818 implementations. */
20819 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20820 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20821 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20822 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20823 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20824 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20825 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20826 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20827 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20828 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20831 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20833 /* Moves and type conversions. */
20834 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20835 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20836 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20837 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20838 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20839 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20840 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20841 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20842 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20843 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20844 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20845 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20846 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20848 /* Monadic operations. */
20849 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20850 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20851 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20853 /* Dyadic operations. */
20854 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20855 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20856 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20857 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20858 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20859 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20860 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20861 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20862 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20865 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20866 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20867 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20868 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20871 #define ARM_VARIANT & fpu_vfp_ext_v2
20873 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20874 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20875 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20876 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20878 /* Instructions which may belong to either the Neon or VFP instruction sets.
20879 Individual encoder functions perform additional architecture checks. */
20881 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20882 #undef THUMB_VARIANT
20883 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20885 /* These mnemonics are unique to VFP. */
20886 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20887 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20888 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20889 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20890 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20891 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20892 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20893 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20894 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20895 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20897 /* Mnemonics shared by Neon and VFP. */
20898 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20899 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20900 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20902 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20903 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20905 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20906 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20908 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20909 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20910 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20911 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20912 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20913 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20914 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20915 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20917 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20918 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20919 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20920 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20923 /* NOTE: All VMOV encoding is special-cased! */
20924 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20925 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20928 #define ARM_VARIANT & arm_ext_fp16
20929 #undef THUMB_VARIANT
20930 #define THUMB_VARIANT & arm_ext_fp16
20931 /* New instructions added from v8.2, allowing the extraction and insertion of
20932 the upper 16 bits of a 32-bit vector register. */
20933 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20934 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20936 /* New backported fma/fms instructions optional in v8.2. */
20937 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20938 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20940 #undef THUMB_VARIANT
20941 #define THUMB_VARIANT & fpu_neon_ext_v1
20943 #define ARM_VARIANT & fpu_neon_ext_v1
20945 /* Data processing with three registers of the same length. */
20946 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20947 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20948 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20949 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20950 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20951 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20952 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20953 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20954 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20955 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20956 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20957 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20958 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20959 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20960 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20961 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20962 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20963 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20964 /* If not immediate, fall back to neon_dyadic_i64_su.
20965 shl_imm should accept I8 I16 I32 I64,
20966 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20967 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20968 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20969 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20970 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20971 /* Logic ops, types optional & ignored. */
20972 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20973 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20974 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20975 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20976 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20977 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20978 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20979 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20980 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20981 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20982 /* Bitfield ops, untyped. */
20983 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20984 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20985 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20986 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20987 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20988 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20989 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20990 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20991 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20992 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20993 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20994 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20995 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20996 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20997 back to neon_dyadic_if_su. */
20998 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20999 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21000 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21001 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21002 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21003 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21004 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21005 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21006 /* Comparison. Type I8 I16 I32 F32. */
21007 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
21008 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
21009 /* As above, D registers only. */
21010 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21011 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21012 /* Int and float variants, signedness unimportant. */
21013 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21014 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21015 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
21016 /* Add/sub take types I8 I16 I32 I64 F32. */
21017 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21018 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21019 /* vtst takes sizes 8, 16, 32. */
21020 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21021 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21022 /* VMUL takes I8 I16 I32 F32 P8. */
21023 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21024 /* VQD{R}MULH takes S16 S32. */
21025 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21026 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21027 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21028 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21029 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21030 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21031 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21032 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21033 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21034 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21035 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21036 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21037 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21038 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21039 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21040 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21041 /* ARM v8.1 extension. */
21042 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21043 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21044 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21045 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21047 /* Two address, int/float. Types S8 S16 S32 F32. */
21048 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21049 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21051 /* Data processing with two registers and a shift amount. */
21052 /* Right shifts, and variants with rounding.
21053 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21054 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21055 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21056 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21057 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21058 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21059 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21060 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21061 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21062 /* Shift and insert. Sizes accepted 8 16 32 64. */
21063 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21064 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21065 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21066 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21067 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21068 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21069 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21070 /* Right shift immediate, saturating & narrowing, with rounding variants.
21071 Types accepted S16 S32 S64 U16 U32 U64. */
21072 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21073 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21074 /* As above, unsigned. Types accepted S16 S32 S64. */
21075 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21076 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21077 /* Right shift narrowing. Types accepted I16 I32 I64. */
21078 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21079 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21080 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21081 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21082 /* CVT with optional immediate for fixed-point variant. */
21083 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21085 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21086 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21088 /* Data processing, three registers of different lengths. */
21089 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21090 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21091 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21092 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21093 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21094 /* If not scalar, fall back to neon_dyadic_long.
21095 Vector types as above, scalar types S16 S32 U16 U32. */
21096 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21097 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21098 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21099 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21100 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21101 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21102 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21103 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21104 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21105 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21106 /* Saturating doubling multiplies. Types S16 S32. */
21107 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21108 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21109 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21110 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21111 S16 S32 U16 U32. */
21112 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21114 /* Extract. Size 8. */
21115 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21116 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21118 /* Two registers, miscellaneous. */
21119 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21120 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21121 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21122 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21123 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21124 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21125 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21126 /* Vector replicate. Sizes 8 16 32. */
21127 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21128 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21129 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21130 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21131 /* VMOVN. Types I16 I32 I64. */
21132 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21133 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21134 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21135 /* VQMOVUN. Types S16 S32 S64. */
21136 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21137 /* VZIP / VUZP. Sizes 8 16 32. */
21138 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21139 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21140 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21141 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21142 /* VQABS / VQNEG. Types S8 S16 S32. */
21143 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21144 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21145 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21146 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21147 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21148 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21149 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21150 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21151 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21152 /* Reciprocal estimates. Types U32 F16 F32. */
21153 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21154 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21155 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21156 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21157 /* VCLS. Types S8 S16 S32. */
21158 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21159 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21160 /* VCLZ. Types I8 I16 I32. */
21161 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21162 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21163 /* VCNT. Size 8. */
21164 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21165 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21166 /* Two address, untyped. */
21167 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21168 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21169 /* VTRN. Sizes 8 16 32. */
21170 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21171 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21173 /* Table lookup. Size 8. */
21174 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21175 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21177 #undef THUMB_VARIANT
21178 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21180 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21182 /* Neon element/structure load/store. */
21183 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21184 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21185 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21186 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21187 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21188 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21189 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21190 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21192 #undef THUMB_VARIANT
21193 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21195 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21196 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21197 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21198 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21199 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21200 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21201 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21202 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21203 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21204 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21206 #undef THUMB_VARIANT
21207 #define THUMB_VARIANT & fpu_vfp_ext_v3
21209 #define ARM_VARIANT & fpu_vfp_ext_v3
21211 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21212 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21213 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21214 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21215 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21216 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21217 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21218 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21219 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21222 #define ARM_VARIANT & fpu_vfp_ext_fma
21223 #undef THUMB_VARIANT
21224 #define THUMB_VARIANT & fpu_vfp_ext_fma
21225 /* Mnemonics shared by Neon and VFP. These are included in the
21226 VFP FMA variant; NEON and VFP FMA always includes the NEON
21227 FMA instructions. */
21228 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21229 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21230 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21231 the v form should always be used. */
21232 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21233 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21234 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21235 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21236 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21237 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21239 #undef THUMB_VARIANT
21241 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21243 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21244 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21245 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21246 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21247 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21248 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21249 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21250 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21253 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21255 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21256 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21257 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21258 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21259 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21260 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21261 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21262 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21263 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21264 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21265 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21266 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21267 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21268 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21269 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21270 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21271 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21272 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21273 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21274 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21275 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21276 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21277 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21278 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21279 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21280 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21281 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21282 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21283 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21284 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21285 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21286 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21287 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21288 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21289 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21290 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21291 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21292 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21294 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21298 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21299 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21301 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21302 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21303 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21304 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21314 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21316 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21317 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21318 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21319 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21320 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21321 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21322 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21323 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21324 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21325 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21326 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21327 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21328 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21329 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21330 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21340 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21341 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21343 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21344 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21345 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21346 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21347 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21348 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21349 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21350 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21351 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21352 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21353 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21354 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21355 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21356 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21357 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21358 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21359 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21360 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21361 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21362 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21363 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21364 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21365 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21366 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21367 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21368 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21369 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21370 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21371 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21372 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21373 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21374 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21375 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21376 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21377 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21378 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21379 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21380 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21381 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21382 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21383 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21384 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21385 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21386 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21387 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21388 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21389 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21390 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21391 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21392 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21393 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21394 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21395 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21396 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21397 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21398 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21399 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21400 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21401 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21402 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21403 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21404 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21405 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21406 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21407 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21408 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21409 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21410 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21411 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21412 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21413 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21419 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21421 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21422 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21423 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21424 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21425 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21426 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21427 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21428 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21429 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21430 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21431 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21432 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21433 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21434 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21435 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21436 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21437 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21438 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21439 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21440 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21441 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21442 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21443 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21444 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21445 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21446 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21447 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21448 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21449 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21450 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21451 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21452 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21453 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21454 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21455 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21456 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21457 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21458 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21459 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21460 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21461 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21462 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21463 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21464 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21465 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21466 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21467 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21468 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21469 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21470 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21471 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21472 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21473 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21474 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21475 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21476 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21477 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21480 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21482 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21483 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21484 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21485 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21486 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21487 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21488 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21489 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21490 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21491 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21492 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21493 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21494 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21495 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21496 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21497 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21498 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21499 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21500 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21501 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21502 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21503 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21504 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21505 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21506 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21507 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21508 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21509 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21510 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21511 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21512 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21513 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21514 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21515 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21516 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21517 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21518 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21519 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21520 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21521 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21522 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21523 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21524 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21525 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21526 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21527 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21528 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21529 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21530 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21531 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21532 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21533 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21534 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21535 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21536 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21537 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21538 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21539 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21540 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21541 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21542 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21543 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21544 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21545 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21546 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21547 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21548 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21549 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21550 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21551 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21552 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21553 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21554 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21555 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21556 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21557 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21559 /* ARMv8.5-A instructions. */
21561 #define ARM_VARIANT & arm_ext_sb
21562 #undef THUMB_VARIANT
21563 #define THUMB_VARIANT & arm_ext_sb
21564 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21567 #define ARM_VARIANT & arm_ext_predres
21568 #undef THUMB_VARIANT
21569 #define THUMB_VARIANT & arm_ext_predres
21570 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21571 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21572 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21574 /* ARMv8-M instructions. */
21576 #define ARM_VARIANT NULL
21577 #undef THUMB_VARIANT
21578 #define THUMB_VARIANT & arm_ext_v8m
21579 ToU("sg", e97fe97f
, 0, (), noargs
),
21580 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21581 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21582 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21583 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21584 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21585 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21587 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21588 instructions behave as nop if no VFP is present. */
21589 #undef THUMB_VARIANT
21590 #define THUMB_VARIANT & arm_ext_v8m_main
21591 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21592 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21595 #undef THUMB_VARIANT
21621 /* MD interface: bits in the object file. */
21623 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21624 for use in the a.out file, and stores them in the array pointed to by buf.
21625 This knows about the endian-ness of the target machine and does
21626 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21627 2 (short) and 4 (long) Floating numbers are put out as a series of
21628 LITTLENUMS (shorts, here at least). */
21631 md_number_to_chars (char * buf
, valueT val
, int n
)
21633 if (target_big_endian
)
21634 number_to_chars_bigendian (buf
, val
, n
);
21636 number_to_chars_littleendian (buf
, val
, n
);
21640 md_chars_to_number (char * buf
, int n
)
21643 unsigned char * where
= (unsigned char *) buf
;
21645 if (target_big_endian
)
21650 result
|= (*where
++ & 255);
21658 result
|= (where
[n
] & 255);
21665 /* MD interface: Sections. */
21667 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21668 that an rs_machine_dependent frag may reach. */
21671 arm_frag_max_var (fragS
*fragp
)
21673 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21674 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21676 Note that we generate relaxable instructions even for cases that don't
21677 really need it, like an immediate that's a trivial constant. So we're
21678 overestimating the instruction size for some of those cases. Rather
21679 than putting more intelligence here, it would probably be better to
21680 avoid generating a relaxation frag in the first place when it can be
21681 determined up front that a short instruction will suffice. */
21683 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21687 /* Estimate the size of a frag before relaxing. Assume everything fits in
21691 md_estimate_size_before_relax (fragS
* fragp
,
21692 segT segtype ATTRIBUTE_UNUSED
)
21698 /* Convert a machine dependent frag. */
21701 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21703 unsigned long insn
;
21704 unsigned long old_op
;
21712 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21714 old_op
= bfd_get_16(abfd
, buf
);
21715 if (fragp
->fr_symbol
)
21717 exp
.X_op
= O_symbol
;
21718 exp
.X_add_symbol
= fragp
->fr_symbol
;
21722 exp
.X_op
= O_constant
;
21724 exp
.X_add_number
= fragp
->fr_offset
;
21725 opcode
= fragp
->fr_subtype
;
21728 case T_MNEM_ldr_pc
:
21729 case T_MNEM_ldr_pc2
:
21730 case T_MNEM_ldr_sp
:
21731 case T_MNEM_str_sp
:
21738 if (fragp
->fr_var
== 4)
21740 insn
= THUMB_OP32 (opcode
);
21741 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21743 insn
|= (old_op
& 0x700) << 4;
21747 insn
|= (old_op
& 7) << 12;
21748 insn
|= (old_op
& 0x38) << 13;
21750 insn
|= 0x00000c00;
21751 put_thumb32_insn (buf
, insn
);
21752 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21756 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21758 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21761 if (fragp
->fr_var
== 4)
21763 insn
= THUMB_OP32 (opcode
);
21764 insn
|= (old_op
& 0xf0) << 4;
21765 put_thumb32_insn (buf
, insn
);
21766 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21770 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21771 exp
.X_add_number
-= 4;
21779 if (fragp
->fr_var
== 4)
21781 int r0off
= (opcode
== T_MNEM_mov
21782 || opcode
== T_MNEM_movs
) ? 0 : 8;
21783 insn
= THUMB_OP32 (opcode
);
21784 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21785 insn
|= (old_op
& 0x700) << r0off
;
21786 put_thumb32_insn (buf
, insn
);
21787 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21791 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21796 if (fragp
->fr_var
== 4)
21798 insn
= THUMB_OP32(opcode
);
21799 put_thumb32_insn (buf
, insn
);
21800 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21803 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21807 if (fragp
->fr_var
== 4)
21809 insn
= THUMB_OP32(opcode
);
21810 insn
|= (old_op
& 0xf00) << 14;
21811 put_thumb32_insn (buf
, insn
);
21812 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21815 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21818 case T_MNEM_add_sp
:
21819 case T_MNEM_add_pc
:
21820 case T_MNEM_inc_sp
:
21821 case T_MNEM_dec_sp
:
21822 if (fragp
->fr_var
== 4)
21824 /* ??? Choose between add and addw. */
21825 insn
= THUMB_OP32 (opcode
);
21826 insn
|= (old_op
& 0xf0) << 4;
21827 put_thumb32_insn (buf
, insn
);
21828 if (opcode
== T_MNEM_add_pc
)
21829 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21831 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21834 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21842 if (fragp
->fr_var
== 4)
21844 insn
= THUMB_OP32 (opcode
);
21845 insn
|= (old_op
& 0xf0) << 4;
21846 insn
|= (old_op
& 0xf) << 16;
21847 put_thumb32_insn (buf
, insn
);
21848 if (insn
& (1 << 20))
21849 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21851 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21854 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21860 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21861 (enum bfd_reloc_code_real
) reloc_type
);
21862 fixp
->fx_file
= fragp
->fr_file
;
21863 fixp
->fx_line
= fragp
->fr_line
;
21864 fragp
->fr_fix
+= fragp
->fr_var
;
21866 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21867 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21868 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21869 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21872 /* Return the size of a relaxable immediate operand instruction.
21873 SHIFT and SIZE specify the form of the allowable immediate. */
21875 relax_immediate (fragS
*fragp
, int size
, int shift
)
21881 /* ??? Should be able to do better than this. */
21882 if (fragp
->fr_symbol
)
21885 low
= (1 << shift
) - 1;
21886 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21887 offset
= fragp
->fr_offset
;
21888 /* Force misaligned offsets to 32-bit variant. */
21891 if (offset
& ~mask
)
21896 /* Get the address of a symbol during relaxation. */
21898 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21904 sym
= fragp
->fr_symbol
;
21905 sym_frag
= symbol_get_frag (sym
);
21906 know (S_GET_SEGMENT (sym
) != absolute_section
21907 || sym_frag
== &zero_address_frag
);
21908 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21910 /* If frag has yet to be reached on this pass, assume it will
21911 move by STRETCH just as we did. If this is not so, it will
21912 be because some frag between grows, and that will force
21916 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21920 /* Adjust stretch for any alignment frag. Note that if have
21921 been expanding the earlier code, the symbol may be
21922 defined in what appears to be an earlier frag. FIXME:
21923 This doesn't handle the fr_subtype field, which specifies
21924 a maximum number of bytes to skip when doing an
21926 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21928 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21931 stretch
= - ((- stretch
)
21932 & ~ ((1 << (int) f
->fr_offset
) - 1));
21934 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21946 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21949 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21954 /* Assume worst case for symbols not known to be in the same section. */
21955 if (fragp
->fr_symbol
== NULL
21956 || !S_IS_DEFINED (fragp
->fr_symbol
)
21957 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21958 || S_IS_WEAK (fragp
->fr_symbol
))
21961 val
= relaxed_symbol_addr (fragp
, stretch
);
21962 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21963 addr
= (addr
+ 4) & ~3;
21964 /* Force misaligned targets to 32-bit variant. */
21968 if (val
< 0 || val
> 1020)
21973 /* Return the size of a relaxable add/sub immediate instruction. */
21975 relax_addsub (fragS
*fragp
, asection
*sec
)
21980 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21981 op
= bfd_get_16(sec
->owner
, buf
);
21982 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21983 return relax_immediate (fragp
, 8, 0);
21985 return relax_immediate (fragp
, 3, 0);
21988 /* Return TRUE iff the definition of symbol S could be pre-empted
21989 (overridden) at link or load time. */
21991 symbol_preemptible (symbolS
*s
)
21993 /* Weak symbols can always be pre-empted. */
21997 /* Non-global symbols cannot be pre-empted. */
21998 if (! S_IS_EXTERNAL (s
))
22002 /* In ELF, a global symbol can be marked protected, or private. In that
22003 case it can't be pre-empted (other definitions in the same link unit
22004 would violate the ODR). */
22005 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
22009 /* Other global symbols might be pre-empted. */
22013 /* Return the size of a relaxable branch instruction. BITS is the
22014 size of the offset field in the narrow instruction. */
22017 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22023 /* Assume worst case for symbols not known to be in the same section. */
22024 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22025 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22026 || S_IS_WEAK (fragp
->fr_symbol
))
22030 /* A branch to a function in ARM state will require interworking. */
22031 if (S_IS_DEFINED (fragp
->fr_symbol
)
22032 && ARM_IS_FUNC (fragp
->fr_symbol
))
22036 if (symbol_preemptible (fragp
->fr_symbol
))
22039 val
= relaxed_symbol_addr (fragp
, stretch
);
22040 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22043 /* Offset is a signed value *2 */
22045 if (val
>= limit
|| val
< -limit
)
22051 /* Relax a machine dependent frag. This returns the amount by which
22052 the current size of the frag should change. */
22055 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22060 oldsize
= fragp
->fr_var
;
22061 switch (fragp
->fr_subtype
)
22063 case T_MNEM_ldr_pc2
:
22064 newsize
= relax_adr (fragp
, sec
, stretch
);
22066 case T_MNEM_ldr_pc
:
22067 case T_MNEM_ldr_sp
:
22068 case T_MNEM_str_sp
:
22069 newsize
= relax_immediate (fragp
, 8, 2);
22073 newsize
= relax_immediate (fragp
, 5, 2);
22077 newsize
= relax_immediate (fragp
, 5, 1);
22081 newsize
= relax_immediate (fragp
, 5, 0);
22084 newsize
= relax_adr (fragp
, sec
, stretch
);
22090 newsize
= relax_immediate (fragp
, 8, 0);
22093 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22096 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22098 case T_MNEM_add_sp
:
22099 case T_MNEM_add_pc
:
22100 newsize
= relax_immediate (fragp
, 8, 2);
22102 case T_MNEM_inc_sp
:
22103 case T_MNEM_dec_sp
:
22104 newsize
= relax_immediate (fragp
, 7, 2);
22110 newsize
= relax_addsub (fragp
, sec
);
22116 fragp
->fr_var
= newsize
;
22117 /* Freeze wide instructions that are at or before the same location as
22118 in the previous pass. This avoids infinite loops.
22119 Don't freeze them unconditionally because targets may be artificially
22120 misaligned by the expansion of preceding frags. */
22121 if (stretch
<= 0 && newsize
> 2)
22123 md_convert_frag (sec
->owner
, sec
, fragp
);
22127 return newsize
- oldsize
;
22130 /* Round up a section size to the appropriate boundary. */
22133 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22139 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22140 of an rs_align_code fragment. */
22143 arm_handle_align (fragS
* fragP
)
22145 static unsigned char const arm_noop
[2][2][4] =
22148 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22149 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22152 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22153 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22156 static unsigned char const thumb_noop
[2][2][2] =
22159 {0xc0, 0x46}, /* LE */
22160 {0x46, 0xc0}, /* BE */
22163 {0x00, 0xbf}, /* LE */
22164 {0xbf, 0x00} /* BE */
22167 static unsigned char const wide_thumb_noop
[2][4] =
22168 { /* Wide Thumb-2 */
22169 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22170 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22173 unsigned bytes
, fix
, noop_size
;
22175 const unsigned char * noop
;
22176 const unsigned char *narrow_noop
= NULL
;
22181 if (fragP
->fr_type
!= rs_align_code
)
22184 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22185 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22188 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22189 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22191 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22193 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22195 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22196 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22198 narrow_noop
= thumb_noop
[1][target_big_endian
];
22199 noop
= wide_thumb_noop
[target_big_endian
];
22202 noop
= thumb_noop
[0][target_big_endian
];
22210 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22211 ? selected_cpu
: arm_arch_none
,
22213 [target_big_endian
];
22220 fragP
->fr_var
= noop_size
;
22222 if (bytes
& (noop_size
- 1))
22224 fix
= bytes
& (noop_size
- 1);
22226 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22228 memset (p
, 0, fix
);
22235 if (bytes
& noop_size
)
22237 /* Insert a narrow noop. */
22238 memcpy (p
, narrow_noop
, noop_size
);
22240 bytes
-= noop_size
;
22244 /* Use wide noops for the remainder */
22248 while (bytes
>= noop_size
)
22250 memcpy (p
, noop
, noop_size
);
22252 bytes
-= noop_size
;
22256 fragP
->fr_fix
+= fix
;
22259 /* Called from md_do_align. Used to create an alignment
22260 frag in a code section. */
22263 arm_frag_align_code (int n
, int max
)
22267 /* We assume that there will never be a requirement
22268 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22269 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22274 _("alignments greater than %d bytes not supported in .text sections."),
22275 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22276 as_fatal ("%s", err_msg
);
22279 p
= frag_var (rs_align_code
,
22280 MAX_MEM_FOR_RS_ALIGN_CODE
,
22282 (relax_substateT
) max
,
22289 /* Perform target specific initialisation of a frag.
22290 Note - despite the name this initialisation is not done when the frag
22291 is created, but only when its type is assigned. A frag can be created
22292 and used a long time before its type is set, so beware of assuming that
22293 this initialisation is performed first. */
22297 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22299 /* Record whether this frag is in an ARM or a THUMB area. */
22300 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22303 #else /* OBJ_ELF is defined. */
22305 arm_init_frag (fragS
* fragP
, int max_chars
)
22307 bfd_boolean frag_thumb_mode
;
22309 /* If the current ARM vs THUMB mode has not already
22310 been recorded into this frag then do so now. */
22311 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22312 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22314 /* PR 21809: Do not set a mapping state for debug sections
22315 - it just confuses other tools. */
22316 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22319 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22321 /* Record a mapping symbol for alignment frags. We will delete this
22322 later if the alignment ends up empty. */
22323 switch (fragP
->fr_type
)
22326 case rs_align_test
:
22328 mapping_state_2 (MAP_DATA
, max_chars
);
22330 case rs_align_code
:
22331 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22338 /* When we change sections we need to issue a new mapping symbol. */
22341 arm_elf_change_section (void)
22343 /* Link an unlinked unwind index table section to the .text section. */
22344 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22345 && elf_linked_to_section (now_seg
) == NULL
)
22346 elf_linked_to_section (now_seg
) = text_section
;
22350 arm_elf_section_type (const char * str
, size_t len
)
22352 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22353 return SHT_ARM_EXIDX
;
22358 /* Code to deal with unwinding tables. */
22360 static void add_unwind_adjustsp (offsetT
);
22362 /* Generate any deferred unwind frame offset. */
22365 flush_pending_unwind (void)
22369 offset
= unwind
.pending_offset
;
22370 unwind
.pending_offset
= 0;
22372 add_unwind_adjustsp (offset
);
22375 /* Add an opcode to this list for this function. Two-byte opcodes should
22376 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22380 add_unwind_opcode (valueT op
, int length
)
22382 /* Add any deferred stack adjustment. */
22383 if (unwind
.pending_offset
)
22384 flush_pending_unwind ();
22386 unwind
.sp_restored
= 0;
22388 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22390 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22391 if (unwind
.opcodes
)
22392 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22393 unwind
.opcode_alloc
);
22395 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22400 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22402 unwind
.opcode_count
++;
22406 /* Add unwind opcodes to adjust the stack pointer. */
22409 add_unwind_adjustsp (offsetT offset
)
22413 if (offset
> 0x200)
22415 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22420 /* Long form: 0xb2, uleb128. */
22421 /* This might not fit in a word so add the individual bytes,
22422 remembering the list is built in reverse order. */
22423 o
= (valueT
) ((offset
- 0x204) >> 2);
22425 add_unwind_opcode (0, 1);
22427 /* Calculate the uleb128 encoding of the offset. */
22431 bytes
[n
] = o
& 0x7f;
22437 /* Add the insn. */
22439 add_unwind_opcode (bytes
[n
- 1], 1);
22440 add_unwind_opcode (0xb2, 1);
22442 else if (offset
> 0x100)
22444 /* Two short opcodes. */
22445 add_unwind_opcode (0x3f, 1);
22446 op
= (offset
- 0x104) >> 2;
22447 add_unwind_opcode (op
, 1);
22449 else if (offset
> 0)
22451 /* Short opcode. */
22452 op
= (offset
- 4) >> 2;
22453 add_unwind_opcode (op
, 1);
22455 else if (offset
< 0)
22458 while (offset
> 0x100)
22460 add_unwind_opcode (0x7f, 1);
22463 op
= ((offset
- 4) >> 2) | 0x40;
22464 add_unwind_opcode (op
, 1);
22468 /* Finish the list of unwind opcodes for this function. */
22471 finish_unwind_opcodes (void)
22475 if (unwind
.fp_used
)
22477 /* Adjust sp as necessary. */
22478 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22479 flush_pending_unwind ();
22481 /* After restoring sp from the frame pointer. */
22482 op
= 0x90 | unwind
.fp_reg
;
22483 add_unwind_opcode (op
, 1);
22486 flush_pending_unwind ();
22490 /* Start an exception table entry. If idx is nonzero this is an index table
22494 start_unwind_section (const segT text_seg
, int idx
)
22496 const char * text_name
;
22497 const char * prefix
;
22498 const char * prefix_once
;
22499 const char * group_name
;
22507 prefix
= ELF_STRING_ARM_unwind
;
22508 prefix_once
= ELF_STRING_ARM_unwind_once
;
22509 type
= SHT_ARM_EXIDX
;
22513 prefix
= ELF_STRING_ARM_unwind_info
;
22514 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22515 type
= SHT_PROGBITS
;
22518 text_name
= segment_name (text_seg
);
22519 if (streq (text_name
, ".text"))
22522 if (strncmp (text_name
, ".gnu.linkonce.t.",
22523 strlen (".gnu.linkonce.t.")) == 0)
22525 prefix
= prefix_once
;
22526 text_name
+= strlen (".gnu.linkonce.t.");
22529 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22535 /* Handle COMDAT group. */
22536 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22538 group_name
= elf_group_name (text_seg
);
22539 if (group_name
== NULL
)
22541 as_bad (_("Group section `%s' has no group signature"),
22542 segment_name (text_seg
));
22543 ignore_rest_of_line ();
22546 flags
|= SHF_GROUP
;
22550 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22553 /* Set the section link for index tables. */
22555 elf_linked_to_section (now_seg
) = text_seg
;
22559 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22560 personality routine data. Returns zero, or the index table value for
22561 an inline entry. */
22564 create_unwind_entry (int have_data
)
22569 /* The current word of data. */
22571 /* The number of bytes left in this word. */
22574 finish_unwind_opcodes ();
22576 /* Remember the current text section. */
22577 unwind
.saved_seg
= now_seg
;
22578 unwind
.saved_subseg
= now_subseg
;
22580 start_unwind_section (now_seg
, 0);
22582 if (unwind
.personality_routine
== NULL
)
22584 if (unwind
.personality_index
== -2)
22587 as_bad (_("handlerdata in cantunwind frame"));
22588 return 1; /* EXIDX_CANTUNWIND. */
22591 /* Use a default personality routine if none is specified. */
22592 if (unwind
.personality_index
== -1)
22594 if (unwind
.opcode_count
> 3)
22595 unwind
.personality_index
= 1;
22597 unwind
.personality_index
= 0;
22600 /* Space for the personality routine entry. */
22601 if (unwind
.personality_index
== 0)
22603 if (unwind
.opcode_count
> 3)
22604 as_bad (_("too many unwind opcodes for personality routine 0"));
22608 /* All the data is inline in the index table. */
22611 while (unwind
.opcode_count
> 0)
22613 unwind
.opcode_count
--;
22614 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22618 /* Pad with "finish" opcodes. */
22620 data
= (data
<< 8) | 0xb0;
22627 /* We get two opcodes "free" in the first word. */
22628 size
= unwind
.opcode_count
- 2;
22632 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22633 if (unwind
.personality_index
!= -1)
22635 as_bad (_("attempt to recreate an unwind entry"));
22639 /* An extra byte is required for the opcode count. */
22640 size
= unwind
.opcode_count
+ 1;
22643 size
= (size
+ 3) >> 2;
22645 as_bad (_("too many unwind opcodes"));
22647 frag_align (2, 0, 0);
22648 record_alignment (now_seg
, 2);
22649 unwind
.table_entry
= expr_build_dot ();
22651 /* Allocate the table entry. */
22652 ptr
= frag_more ((size
<< 2) + 4);
22653 /* PR 13449: Zero the table entries in case some of them are not used. */
22654 memset (ptr
, 0, (size
<< 2) + 4);
22655 where
= frag_now_fix () - ((size
<< 2) + 4);
22657 switch (unwind
.personality_index
)
22660 /* ??? Should this be a PLT generating relocation? */
22661 /* Custom personality routine. */
22662 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22663 BFD_RELOC_ARM_PREL31
);
22668 /* Set the first byte to the number of additional words. */
22669 data
= size
> 0 ? size
- 1 : 0;
22673 /* ABI defined personality routines. */
22675 /* Three opcodes bytes are packed into the first word. */
22682 /* The size and first two opcode bytes go in the first word. */
22683 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22688 /* Should never happen. */
22692 /* Pack the opcodes into words (MSB first), reversing the list at the same
22694 while (unwind
.opcode_count
> 0)
22698 md_number_to_chars (ptr
, data
, 4);
22703 unwind
.opcode_count
--;
22705 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22708 /* Finish off the last word. */
22711 /* Pad with "finish" opcodes. */
22713 data
= (data
<< 8) | 0xb0;
22715 md_number_to_chars (ptr
, data
, 4);
22720 /* Add an empty descriptor if there is no user-specified data. */
22721 ptr
= frag_more (4);
22722 md_number_to_chars (ptr
, 0, 4);
22729 /* Initialize the DWARF-2 unwind information for this procedure. */
22732 tc_arm_frame_initial_instructions (void)
22734 cfi_add_CFA_def_cfa (REG_SP
, 0);
22736 #endif /* OBJ_ELF */
22738 /* Convert REGNAME to a DWARF-2 register number. */
22741 tc_arm_regname_to_dw2regnum (char *regname
)
22743 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22747 /* PR 16694: Allow VFP registers as well. */
22748 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22752 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22761 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22765 exp
.X_op
= O_secrel
;
22766 exp
.X_add_symbol
= symbol
;
22767 exp
.X_add_number
= 0;
22768 emit_expr (&exp
, size
);
22772 /* MD interface: Symbol and relocation handling. */
22774 /* Return the address within the segment that a PC-relative fixup is
22775 relative to. For ARM, PC-relative fixups applied to instructions
22776 are generally relative to the location of the fixup plus 8 bytes.
22777 Thumb branches are offset by 4, and Thumb loads relative to PC
22778 require special handling. */
22781 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22783 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22785 /* If this is pc-relative and we are going to emit a relocation
22786 then we just want to put out any pipeline compensation that the linker
22787 will need. Otherwise we want to use the calculated base.
22788 For WinCE we skip the bias for externals as well, since this
22789 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22791 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22792 || (arm_force_relocation (fixP
)
22794 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22800 switch (fixP
->fx_r_type
)
22802 /* PC relative addressing on the Thumb is slightly odd as the
22803 bottom two bits of the PC are forced to zero for the
22804 calculation. This happens *after* application of the
22805 pipeline offset. However, Thumb adrl already adjusts for
22806 this, so we need not do it again. */
22807 case BFD_RELOC_ARM_THUMB_ADD
:
22810 case BFD_RELOC_ARM_THUMB_OFFSET
:
22811 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22812 case BFD_RELOC_ARM_T32_ADD_PC12
:
22813 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22814 return (base
+ 4) & ~3;
22816 /* Thumb branches are simply offset by +4. */
22817 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
22818 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22819 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22820 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22821 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22822 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22825 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22827 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22828 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22829 && ARM_IS_FUNC (fixP
->fx_addsy
)
22830 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22831 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22834 /* BLX is like branches above, but forces the low two bits of PC to
22836 case BFD_RELOC_THUMB_PCREL_BLX
:
22838 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22839 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22840 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22841 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22842 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22843 return (base
+ 4) & ~3;
22845 /* ARM mode branches are offset by +8. However, the Windows CE
22846 loader expects the relocation not to take this into account. */
22847 case BFD_RELOC_ARM_PCREL_BLX
:
22849 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22850 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22851 && ARM_IS_FUNC (fixP
->fx_addsy
)
22852 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22853 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22856 case BFD_RELOC_ARM_PCREL_CALL
:
22858 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22859 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22860 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22861 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22862 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22865 case BFD_RELOC_ARM_PCREL_BRANCH
:
22866 case BFD_RELOC_ARM_PCREL_JUMP
:
22867 case BFD_RELOC_ARM_PLT32
:
22869 /* When handling fixups immediately, because we have already
22870 discovered the value of a symbol, or the address of the frag involved
22871 we must account for the offset by +8, as the OS loader will never see the reloc.
22872 see fixup_segment() in write.c
22873 The S_IS_EXTERNAL test handles the case of global symbols.
22874 Those need the calculated base, not just the pipe compensation the linker will need. */
22876 && fixP
->fx_addsy
!= NULL
22877 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22878 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22886 /* ARM mode loads relative to PC are also offset by +8. Unlike
22887 branches, the Windows CE loader *does* expect the relocation
22888 to take this into account. */
22889 case BFD_RELOC_ARM_OFFSET_IMM
:
22890 case BFD_RELOC_ARM_OFFSET_IMM8
:
22891 case BFD_RELOC_ARM_HWLITERAL
:
22892 case BFD_RELOC_ARM_LITERAL
:
22893 case BFD_RELOC_ARM_CP_OFF_IMM
:
22897 /* Other PC-relative relocations are un-offset. */
22903 static bfd_boolean flag_warn_syms
= TRUE
;
22906 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22908 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22909 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22910 does mean that the resulting code might be very confusing to the reader.
22911 Also this warning can be triggered if the user omits an operand before
22912 an immediate address, eg:
22916 GAS treats this as an assignment of the value of the symbol foo to a
22917 symbol LDR, and so (without this code) it will not issue any kind of
22918 warning or error message.
22920 Note - ARM instructions are case-insensitive but the strings in the hash
22921 table are all stored in lower case, so we must first ensure that name is
22923 if (flag_warn_syms
&& arm_ops_hsh
)
22925 char * nbuf
= strdup (name
);
22928 for (p
= nbuf
; *p
; p
++)
22930 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22932 static struct hash_control
* already_warned
= NULL
;
22934 if (already_warned
== NULL
)
22935 already_warned
= hash_new ();
22936 /* Only warn about the symbol once. To keep the code
22937 simple we let hash_insert do the lookup for us. */
22938 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22939 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22948 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22949 Otherwise we have no need to default values of symbols. */
22952 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22955 if (name
[0] == '_' && name
[1] == 'G'
22956 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22960 if (symbol_find (name
))
22961 as_bad (_("GOT already in the symbol table"));
22963 GOT_symbol
= symbol_new (name
, undefined_section
,
22964 (valueT
) 0, & zero_address_frag
);
22974 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22975 computed as two separate immediate values, added together. We
22976 already know that this value cannot be computed by just one ARM
22979 static unsigned int
22980 validate_immediate_twopart (unsigned int val
,
22981 unsigned int * highpart
)
22986 for (i
= 0; i
< 32; i
+= 2)
22987 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22993 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22995 else if (a
& 0xff0000)
22997 if (a
& 0xff000000)
22999 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
23003 gas_assert (a
& 0xff000000);
23004 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
23007 return (a
& 0xff) | (i
<< 7);
23014 validate_offset_imm (unsigned int val
, int hwse
)
23016 if ((hwse
&& val
> 255) || val
> 4095)
23021 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23022 negative immediate constant by altering the instruction. A bit of
23027 by inverting the second operand, and
23030 by negating the second operand. */
23033 negate_data_op (unsigned long * instruction
,
23034 unsigned long value
)
23037 unsigned long negated
, inverted
;
23039 negated
= encode_arm_immediate (-value
);
23040 inverted
= encode_arm_immediate (~value
);
23042 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23045 /* First negates. */
23046 case OPCODE_SUB
: /* ADD <-> SUB */
23047 new_inst
= OPCODE_ADD
;
23052 new_inst
= OPCODE_SUB
;
23056 case OPCODE_CMP
: /* CMP <-> CMN */
23057 new_inst
= OPCODE_CMN
;
23062 new_inst
= OPCODE_CMP
;
23066 /* Now Inverted ops. */
23067 case OPCODE_MOV
: /* MOV <-> MVN */
23068 new_inst
= OPCODE_MVN
;
23073 new_inst
= OPCODE_MOV
;
23077 case OPCODE_AND
: /* AND <-> BIC */
23078 new_inst
= OPCODE_BIC
;
23083 new_inst
= OPCODE_AND
;
23087 case OPCODE_ADC
: /* ADC <-> SBC */
23088 new_inst
= OPCODE_SBC
;
23093 new_inst
= OPCODE_ADC
;
23097 /* We cannot do anything. */
23102 if (value
== (unsigned) FAIL
)
23105 *instruction
&= OPCODE_MASK
;
23106 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23110 /* Like negate_data_op, but for Thumb-2. */
23112 static unsigned int
23113 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23117 unsigned int negated
, inverted
;
23119 negated
= encode_thumb32_immediate (-value
);
23120 inverted
= encode_thumb32_immediate (~value
);
23122 rd
= (*instruction
>> 8) & 0xf;
23123 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23126 /* ADD <-> SUB. Includes CMP <-> CMN. */
23127 case T2_OPCODE_SUB
:
23128 new_inst
= T2_OPCODE_ADD
;
23132 case T2_OPCODE_ADD
:
23133 new_inst
= T2_OPCODE_SUB
;
23137 /* ORR <-> ORN. Includes MOV <-> MVN. */
23138 case T2_OPCODE_ORR
:
23139 new_inst
= T2_OPCODE_ORN
;
23143 case T2_OPCODE_ORN
:
23144 new_inst
= T2_OPCODE_ORR
;
23148 /* AND <-> BIC. TST has no inverted equivalent. */
23149 case T2_OPCODE_AND
:
23150 new_inst
= T2_OPCODE_BIC
;
23157 case T2_OPCODE_BIC
:
23158 new_inst
= T2_OPCODE_AND
;
23163 case T2_OPCODE_ADC
:
23164 new_inst
= T2_OPCODE_SBC
;
23168 case T2_OPCODE_SBC
:
23169 new_inst
= T2_OPCODE_ADC
;
23173 /* We cannot do anything. */
23178 if (value
== (unsigned int)FAIL
)
23181 *instruction
&= T2_OPCODE_MASK
;
23182 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23186 /* Read a 32-bit thumb instruction from buf. */
23188 static unsigned long
23189 get_thumb32_insn (char * buf
)
23191 unsigned long insn
;
23192 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23193 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23198 /* We usually want to set the low bit on the address of thumb function
23199 symbols. In particular .word foo - . should have the low bit set.
23200 Generic code tries to fold the difference of two symbols to
23201 a constant. Prevent this and force a relocation when the first symbols
23202 is a thumb function. */
23205 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23207 if (op
== O_subtract
23208 && l
->X_op
== O_symbol
23209 && r
->X_op
== O_symbol
23210 && THUMB_IS_FUNC (l
->X_add_symbol
))
23212 l
->X_op
= O_subtract
;
23213 l
->X_op_symbol
= r
->X_add_symbol
;
23214 l
->X_add_number
-= r
->X_add_number
;
23218 /* Process as normal. */
23222 /* Encode Thumb2 unconditional branches and calls. The encoding
23223 for the 2 are identical for the immediate values. */
23226 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23228 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23231 addressT S
, I1
, I2
, lo
, hi
;
23233 S
= (value
>> 24) & 0x01;
23234 I1
= (value
>> 23) & 0x01;
23235 I2
= (value
>> 22) & 0x01;
23236 hi
= (value
>> 12) & 0x3ff;
23237 lo
= (value
>> 1) & 0x7ff;
23238 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23239 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23240 newval
|= (S
<< 10) | hi
;
23241 newval2
&= ~T2I1I2MASK
;
23242 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23243 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23244 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23248 md_apply_fix (fixS
* fixP
,
23252 offsetT value
= * valP
;
23254 unsigned int newimm
;
23255 unsigned long temp
;
23257 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23259 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23261 /* Note whether this will delete the relocation. */
23263 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23266 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23267 consistency with the behaviour on 32-bit hosts. Remember value
23269 value
&= 0xffffffff;
23270 value
^= 0x80000000;
23271 value
-= 0x80000000;
23274 fixP
->fx_addnumber
= value
;
23276 /* Same treatment for fixP->fx_offset. */
23277 fixP
->fx_offset
&= 0xffffffff;
23278 fixP
->fx_offset
^= 0x80000000;
23279 fixP
->fx_offset
-= 0x80000000;
23281 switch (fixP
->fx_r_type
)
23283 case BFD_RELOC_NONE
:
23284 /* This will need to go in the object file. */
23288 case BFD_RELOC_ARM_IMMEDIATE
:
23289 /* We claim that this fixup has been processed here,
23290 even if in fact we generate an error because we do
23291 not have a reloc for it, so tc_gen_reloc will reject it. */
23294 if (fixP
->fx_addsy
)
23296 const char *msg
= 0;
23298 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23299 msg
= _("undefined symbol %s used as an immediate value");
23300 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23301 msg
= _("symbol %s is in a different section");
23302 else if (S_IS_WEAK (fixP
->fx_addsy
))
23303 msg
= _("symbol %s is weak and may be overridden later");
23307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23308 msg
, S_GET_NAME (fixP
->fx_addsy
));
23313 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23315 /* If the offset is negative, we should use encoding A2 for ADR. */
23316 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23317 newimm
= negate_data_op (&temp
, value
);
23320 newimm
= encode_arm_immediate (value
);
23322 /* If the instruction will fail, see if we can fix things up by
23323 changing the opcode. */
23324 if (newimm
== (unsigned int) FAIL
)
23325 newimm
= negate_data_op (&temp
, value
);
23326 /* MOV accepts both ARM modified immediate (A1 encoding) and
23327 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23328 When disassembling, MOV is preferred when there is no encoding
23330 if (newimm
== (unsigned int) FAIL
23331 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23332 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23333 && !((temp
>> SBIT_SHIFT
) & 0x1)
23334 && value
>= 0 && value
<= 0xffff)
23336 /* Clear bits[23:20] to change encoding from A1 to A2. */
23337 temp
&= 0xff0fffff;
23338 /* Encoding high 4bits imm. Code below will encode the remaining
23340 temp
|= (value
& 0x0000f000) << 4;
23341 newimm
= value
& 0x00000fff;
23345 if (newimm
== (unsigned int) FAIL
)
23347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23348 _("invalid constant (%lx) after fixup"),
23349 (unsigned long) value
);
23353 newimm
|= (temp
& 0xfffff000);
23354 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23357 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23359 unsigned int highpart
= 0;
23360 unsigned int newinsn
= 0xe1a00000; /* nop. */
23362 if (fixP
->fx_addsy
)
23364 const char *msg
= 0;
23366 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23367 msg
= _("undefined symbol %s used as an immediate value");
23368 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23369 msg
= _("symbol %s is in a different section");
23370 else if (S_IS_WEAK (fixP
->fx_addsy
))
23371 msg
= _("symbol %s is weak and may be overridden later");
23375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23376 msg
, S_GET_NAME (fixP
->fx_addsy
));
23381 newimm
= encode_arm_immediate (value
);
23382 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23384 /* If the instruction will fail, see if we can fix things up by
23385 changing the opcode. */
23386 if (newimm
== (unsigned int) FAIL
23387 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23389 /* No ? OK - try using two ADD instructions to generate
23391 newimm
= validate_immediate_twopart (value
, & highpart
);
23393 /* Yes - then make sure that the second instruction is
23395 if (newimm
!= (unsigned int) FAIL
)
23397 /* Still No ? Try using a negated value. */
23398 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23399 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23400 /* Otherwise - give up. */
23403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23404 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23409 /* Replace the first operand in the 2nd instruction (which
23410 is the PC) with the destination register. We have
23411 already added in the PC in the first instruction and we
23412 do not want to do it again. */
23413 newinsn
&= ~ 0xf0000;
23414 newinsn
|= ((newinsn
& 0x0f000) << 4);
23417 newimm
|= (temp
& 0xfffff000);
23418 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23420 highpart
|= (newinsn
& 0xfffff000);
23421 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23425 case BFD_RELOC_ARM_OFFSET_IMM
:
23426 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23428 /* Fall through. */
23430 case BFD_RELOC_ARM_LITERAL
:
23436 if (validate_offset_imm (value
, 0) == FAIL
)
23438 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23440 _("invalid literal constant: pool needs to be closer"));
23442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23443 _("bad immediate value for offset (%ld)"),
23448 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23450 newval
&= 0xfffff000;
23453 newval
&= 0xff7ff000;
23454 newval
|= value
| (sign
? INDEX_UP
: 0);
23456 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23459 case BFD_RELOC_ARM_OFFSET_IMM8
:
23460 case BFD_RELOC_ARM_HWLITERAL
:
23466 if (validate_offset_imm (value
, 1) == FAIL
)
23468 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23470 _("invalid literal constant: pool needs to be closer"));
23472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23473 _("bad immediate value for 8-bit offset (%ld)"),
23478 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23480 newval
&= 0xfffff0f0;
23483 newval
&= 0xff7ff0f0;
23484 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23486 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23489 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23490 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23492 _("bad immediate value for offset (%ld)"), (long) value
);
23495 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23497 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23500 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23501 /* This is a complicated relocation used for all varieties of Thumb32
23502 load/store instruction with immediate offset:
23504 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23505 *4, optional writeback(W)
23506 (doubleword load/store)
23508 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23509 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23510 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23511 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23512 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23514 Uppercase letters indicate bits that are already encoded at
23515 this point. Lowercase letters are our problem. For the
23516 second block of instructions, the secondary opcode nybble
23517 (bits 8..11) is present, and bit 23 is zero, even if this is
23518 a PC-relative operation. */
23519 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23521 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23523 if ((newval
& 0xf0000000) == 0xe0000000)
23525 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23527 newval
|= (1 << 23);
23530 if (value
% 4 != 0)
23532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23533 _("offset not a multiple of 4"));
23539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23540 _("offset out of range"));
23545 else if ((newval
& 0x000f0000) == 0x000f0000)
23547 /* PC-relative, 12-bit offset. */
23549 newval
|= (1 << 23);
23554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23555 _("offset out of range"));
23560 else if ((newval
& 0x00000100) == 0x00000100)
23562 /* Writeback: 8-bit, +/- offset. */
23564 newval
|= (1 << 9);
23569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23570 _("offset out of range"));
23575 else if ((newval
& 0x00000f00) == 0x00000e00)
23577 /* T-instruction: positive 8-bit offset. */
23578 if (value
< 0 || value
> 0xff)
23580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23581 _("offset out of range"));
23589 /* Positive 12-bit or negative 8-bit offset. */
23593 newval
|= (1 << 23);
23603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23604 _("offset out of range"));
23611 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23612 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23615 case BFD_RELOC_ARM_SHIFT_IMM
:
23616 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23617 if (((unsigned long) value
) > 32
23619 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23622 _("shift expression is too large"));
23627 /* Shifts of zero must be done as lsl. */
23629 else if (value
== 32)
23631 newval
&= 0xfffff07f;
23632 newval
|= (value
& 0x1f) << 7;
23633 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23636 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23637 case BFD_RELOC_ARM_T32_ADD_IMM
:
23638 case BFD_RELOC_ARM_T32_IMM12
:
23639 case BFD_RELOC_ARM_T32_ADD_PC12
:
23640 /* We claim that this fixup has been processed here,
23641 even if in fact we generate an error because we do
23642 not have a reloc for it, so tc_gen_reloc will reject it. */
23646 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23649 _("undefined symbol %s used as an immediate value"),
23650 S_GET_NAME (fixP
->fx_addsy
));
23654 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23656 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23659 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23660 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23661 Thumb2 modified immediate encoding (T2). */
23662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23663 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23665 newimm
= encode_thumb32_immediate (value
);
23666 if (newimm
== (unsigned int) FAIL
)
23667 newimm
= thumb32_negate_data_op (&newval
, value
);
23669 if (newimm
== (unsigned int) FAIL
)
23671 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23673 /* Turn add/sum into addw/subw. */
23674 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23675 newval
= (newval
& 0xfeffffff) | 0x02000000;
23676 /* No flat 12-bit imm encoding for addsw/subsw. */
23677 if ((newval
& 0x00100000) == 0)
23679 /* 12 bit immediate for addw/subw. */
23683 newval
^= 0x00a00000;
23686 newimm
= (unsigned int) FAIL
;
23693 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23694 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23695 disassembling, MOV is preferred when there is no encoding
23697 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23698 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23699 but with the Rn field [19:16] set to 1111. */
23700 && (((newval
>> 16) & 0xf) == 0xf)
23701 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23702 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23703 && value
>= 0 && value
<= 0xffff)
23705 /* Toggle bit[25] to change encoding from T2 to T3. */
23707 /* Clear bits[19:16]. */
23708 newval
&= 0xfff0ffff;
23709 /* Encoding high 4bits imm. Code below will encode the
23710 remaining low 12bits. */
23711 newval
|= (value
& 0x0000f000) << 4;
23712 newimm
= value
& 0x00000fff;
23717 if (newimm
== (unsigned int)FAIL
)
23719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23720 _("invalid constant (%lx) after fixup"),
23721 (unsigned long) value
);
23725 newval
|= (newimm
& 0x800) << 15;
23726 newval
|= (newimm
& 0x700) << 4;
23727 newval
|= (newimm
& 0x0ff);
23729 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23730 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23733 case BFD_RELOC_ARM_SMC
:
23734 if (((unsigned long) value
) > 0xffff)
23735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23736 _("invalid smc expression"));
23737 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23738 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23742 case BFD_RELOC_ARM_HVC
:
23743 if (((unsigned long) value
) > 0xffff)
23744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23745 _("invalid hvc expression"));
23746 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23747 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23748 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23751 case BFD_RELOC_ARM_SWI
:
23752 if (fixP
->tc_fix_data
!= 0)
23754 if (((unsigned long) value
) > 0xff)
23755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23756 _("invalid swi expression"));
23757 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23759 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23763 if (((unsigned long) value
) > 0x00ffffff)
23764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23765 _("invalid swi expression"));
23766 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23768 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23772 case BFD_RELOC_ARM_MULTI
:
23773 if (((unsigned long) value
) > 0xffff)
23774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23775 _("invalid expression in load/store multiple"));
23776 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23777 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23781 case BFD_RELOC_ARM_PCREL_CALL
:
23783 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23785 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23786 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23787 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23788 /* Flip the bl to blx. This is a simple flip
23789 bit here because we generate PCREL_CALL for
23790 unconditional bls. */
23792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23793 newval
= newval
| 0x10000000;
23794 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23800 goto arm_branch_common
;
23802 case BFD_RELOC_ARM_PCREL_JUMP
:
23803 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23805 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23807 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23809 /* This would map to a bl<cond>, b<cond>,
23810 b<always> to a Thumb function. We
23811 need to force a relocation for this particular
23813 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23816 /* Fall through. */
23818 case BFD_RELOC_ARM_PLT32
:
23820 case BFD_RELOC_ARM_PCREL_BRANCH
:
23822 goto arm_branch_common
;
23824 case BFD_RELOC_ARM_PCREL_BLX
:
23827 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23829 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23830 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23831 && ARM_IS_FUNC (fixP
->fx_addsy
))
23833 /* Flip the blx to a bl and warn. */
23834 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23835 newval
= 0xeb000000;
23836 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23837 _("blx to '%s' an ARM ISA state function changed to bl"),
23839 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23845 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23846 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23850 /* We are going to store value (shifted right by two) in the
23851 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23852 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23856 _("misaligned branch destination"));
23857 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23858 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23861 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23863 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23864 newval
|= (value
>> 2) & 0x00ffffff;
23865 /* Set the H bit on BLX instructions. */
23869 newval
|= 0x01000000;
23871 newval
&= ~0x01000000;
23873 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23877 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23878 /* CBZ can only branch forward. */
23880 /* Attempts to use CBZ to branch to the next instruction
23881 (which, strictly speaking, are prohibited) will be turned into
23884 FIXME: It may be better to remove the instruction completely and
23885 perform relaxation. */
23888 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23889 newval
= 0xbf00; /* NOP encoding T1 */
23890 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23899 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23900 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23901 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23906 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23907 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23910 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23912 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23913 newval
|= (value
& 0x1ff) >> 1;
23914 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23918 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23919 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23924 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23925 newval
|= (value
& 0xfff) >> 1;
23926 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23930 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23932 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23933 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23934 && ARM_IS_FUNC (fixP
->fx_addsy
)
23935 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23937 /* Force a relocation for a branch 20 bits wide. */
23940 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23942 _("conditional branch out of range"));
23944 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23947 addressT S
, J1
, J2
, lo
, hi
;
23949 S
= (value
& 0x00100000) >> 20;
23950 J2
= (value
& 0x00080000) >> 19;
23951 J1
= (value
& 0x00040000) >> 18;
23952 hi
= (value
& 0x0003f000) >> 12;
23953 lo
= (value
& 0x00000ffe) >> 1;
23955 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23956 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23957 newval
|= (S
<< 10) | hi
;
23958 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23959 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23960 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23964 case BFD_RELOC_THUMB_PCREL_BLX
:
23965 /* If there is a blx from a thumb state function to
23966 another thumb function flip this to a bl and warn
23970 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23971 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23972 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23974 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23975 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23976 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23978 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23979 newval
= newval
| 0x1000;
23980 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23981 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23986 goto thumb_bl_common
;
23988 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23989 /* A bl from Thumb state ISA to an internal ARM state function
23990 is converted to a blx. */
23992 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23993 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23994 && ARM_IS_FUNC (fixP
->fx_addsy
)
23995 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23997 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23998 newval
= newval
& ~0x1000;
23999 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24000 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
24006 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24007 /* For a BLX instruction, make sure that the relocation is rounded up
24008 to a word boundary. This follows the semantics of the instruction
24009 which specifies that bit 1 of the target address will come from bit
24010 1 of the base address. */
24011 value
= (value
+ 3) & ~ 3;
24014 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
24015 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24016 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24019 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24021 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24023 else if ((value
& ~0x1ffffff)
24024 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24026 _("Thumb2 branch out of range"));
24029 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24030 encode_thumb2_b_bl_offset (buf
, value
);
24034 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24035 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24038 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24039 encode_thumb2_b_bl_offset (buf
, value
);
24044 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24049 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24050 md_number_to_chars (buf
, value
, 2);
24054 case BFD_RELOC_ARM_TLS_CALL
:
24055 case BFD_RELOC_ARM_THM_TLS_CALL
:
24056 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24057 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24058 case BFD_RELOC_ARM_TLS_GOTDESC
:
24059 case BFD_RELOC_ARM_TLS_GD32
:
24060 case BFD_RELOC_ARM_TLS_LE32
:
24061 case BFD_RELOC_ARM_TLS_IE32
:
24062 case BFD_RELOC_ARM_TLS_LDM32
:
24063 case BFD_RELOC_ARM_TLS_LDO32
:
24064 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24067 /* Same handling as above, but with the arm_fdpic guard. */
24068 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24069 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24070 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24073 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24078 _("Relocation supported only in FDPIC mode"));
24082 case BFD_RELOC_ARM_GOT32
:
24083 case BFD_RELOC_ARM_GOTOFF
:
24086 case BFD_RELOC_ARM_GOT_PREL
:
24087 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24088 md_number_to_chars (buf
, value
, 4);
24091 case BFD_RELOC_ARM_TARGET2
:
24092 /* TARGET2 is not partial-inplace, so we need to write the
24093 addend here for REL targets, because it won't be written out
24094 during reloc processing later. */
24095 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24096 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24099 /* Relocations for FDPIC. */
24100 case BFD_RELOC_ARM_GOTFUNCDESC
:
24101 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24102 case BFD_RELOC_ARM_FUNCDESC
:
24105 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24106 md_number_to_chars (buf
, 0, 4);
24110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24111 _("Relocation supported only in FDPIC mode"));
24116 case BFD_RELOC_RVA
:
24118 case BFD_RELOC_ARM_TARGET1
:
24119 case BFD_RELOC_ARM_ROSEGREL32
:
24120 case BFD_RELOC_ARM_SBREL32
:
24121 case BFD_RELOC_32_PCREL
:
24123 case BFD_RELOC_32_SECREL
:
24125 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24127 /* For WinCE we only do this for pcrel fixups. */
24128 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24130 md_number_to_chars (buf
, value
, 4);
24134 case BFD_RELOC_ARM_PREL31
:
24135 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24137 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24138 if ((value
^ (value
>> 1)) & 0x40000000)
24140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24141 _("rel31 relocation overflow"));
24143 newval
|= value
& 0x7fffffff;
24144 md_number_to_chars (buf
, newval
, 4);
24149 case BFD_RELOC_ARM_CP_OFF_IMM
:
24150 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24151 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24152 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24154 newval
= get_thumb32_insn (buf
);
24155 if ((newval
& 0x0f200f00) == 0x0d000900)
24157 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24158 has permitted values that are multiples of 2, in the range 0
24160 if (value
< -510 || value
> 510 || (value
& 1))
24161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24162 _("co-processor offset out of range"));
24164 else if (value
< -1023 || value
> 1023 || (value
& 3))
24165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24166 _("co-processor offset out of range"));
24171 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24172 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24173 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24175 newval
= get_thumb32_insn (buf
);
24177 newval
&= 0xffffff00;
24180 newval
&= 0xff7fff00;
24181 if ((newval
& 0x0f200f00) == 0x0d000900)
24183 /* This is a fp16 vstr/vldr.
24185 It requires the immediate offset in the instruction is shifted
24186 left by 1 to be a half-word offset.
24188 Here, left shift by 1 first, and later right shift by 2
24189 should get the right offset. */
24192 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24194 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24195 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24196 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24198 put_thumb32_insn (buf
, newval
);
24201 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24202 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24203 if (value
< -255 || value
> 255)
24204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24205 _("co-processor offset out of range"));
24207 goto cp_off_common
;
24209 case BFD_RELOC_ARM_THUMB_OFFSET
:
24210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24211 /* Exactly what ranges, and where the offset is inserted depends
24212 on the type of instruction, we can establish this from the
24214 switch (newval
>> 12)
24216 case 4: /* PC load. */
24217 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24218 forced to zero for these loads; md_pcrel_from has already
24219 compensated for this. */
24221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24222 _("invalid offset, target not word aligned (0x%08lX)"),
24223 (((unsigned long) fixP
->fx_frag
->fr_address
24224 + (unsigned long) fixP
->fx_where
) & ~3)
24225 + (unsigned long) value
);
24227 if (value
& ~0x3fc)
24228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24229 _("invalid offset, value too big (0x%08lX)"),
24232 newval
|= value
>> 2;
24235 case 9: /* SP load/store. */
24236 if (value
& ~0x3fc)
24237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24238 _("invalid offset, value too big (0x%08lX)"),
24240 newval
|= value
>> 2;
24243 case 6: /* Word load/store. */
24245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24246 _("invalid offset, value too big (0x%08lX)"),
24248 newval
|= value
<< 4; /* 6 - 2. */
24251 case 7: /* Byte load/store. */
24253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24254 _("invalid offset, value too big (0x%08lX)"),
24256 newval
|= value
<< 6;
24259 case 8: /* Halfword load/store. */
24261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24262 _("invalid offset, value too big (0x%08lX)"),
24264 newval
|= value
<< 5; /* 6 - 1. */
24268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24269 "Unable to process relocation for thumb opcode: %lx",
24270 (unsigned long) newval
);
24273 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24276 case BFD_RELOC_ARM_THUMB_ADD
:
24277 /* This is a complicated relocation, since we use it for all of
24278 the following immediate relocations:
24282 9bit ADD/SUB SP word-aligned
24283 10bit ADD PC/SP word-aligned
24285 The type of instruction being processed is encoded in the
24292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24294 int rd
= (newval
>> 4) & 0xf;
24295 int rs
= newval
& 0xf;
24296 int subtract
= !!(newval
& 0x8000);
24298 /* Check for HI regs, only very restricted cases allowed:
24299 Adjusting SP, and using PC or SP to get an address. */
24300 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24301 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24303 _("invalid Hi register with immediate"));
24305 /* If value is negative, choose the opposite instruction. */
24309 subtract
= !subtract
;
24311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24312 _("immediate value out of range"));
24317 if (value
& ~0x1fc)
24318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24319 _("invalid immediate for stack address calculation"));
24320 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24321 newval
|= value
>> 2;
24323 else if (rs
== REG_PC
|| rs
== REG_SP
)
24325 /* PR gas/18541. If the addition is for a defined symbol
24326 within range of an ADR instruction then accept it. */
24329 && fixP
->fx_addsy
!= NULL
)
24333 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24334 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24335 || S_IS_WEAK (fixP
->fx_addsy
))
24337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24338 _("address calculation needs a strongly defined nearby symbol"));
24342 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24344 /* Round up to the next 4-byte boundary. */
24349 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24354 _("symbol too far away"));
24364 if (subtract
|| value
& ~0x3fc)
24365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24366 _("invalid immediate for address calculation (value = 0x%08lX)"),
24367 (unsigned long) (subtract
? - value
: value
));
24368 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24370 newval
|= value
>> 2;
24375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24376 _("immediate value out of range"));
24377 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24378 newval
|= (rd
<< 8) | value
;
24383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24384 _("immediate value out of range"));
24385 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24386 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24389 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24392 case BFD_RELOC_ARM_THUMB_IMM
:
24393 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24394 if (value
< 0 || value
> 255)
24395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24396 _("invalid immediate: %ld is out of range"),
24399 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24402 case BFD_RELOC_ARM_THUMB_SHIFT
:
24403 /* 5bit shift value (0..32). LSL cannot take 32. */
24404 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24405 temp
= newval
& 0xf800;
24406 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24408 _("invalid shift value: %ld"), (long) value
);
24409 /* Shifts of zero must be encoded as LSL. */
24411 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24412 /* Shifts of 32 are encoded as zero. */
24413 else if (value
== 32)
24415 newval
|= value
<< 6;
24416 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24419 case BFD_RELOC_VTABLE_INHERIT
:
24420 case BFD_RELOC_VTABLE_ENTRY
:
24424 case BFD_RELOC_ARM_MOVW
:
24425 case BFD_RELOC_ARM_MOVT
:
24426 case BFD_RELOC_ARM_THUMB_MOVW
:
24427 case BFD_RELOC_ARM_THUMB_MOVT
:
24428 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24430 /* REL format relocations are limited to a 16-bit addend. */
24431 if (!fixP
->fx_done
)
24433 if (value
< -0x8000 || value
> 0x7fff)
24434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24435 _("offset out of range"));
24437 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24438 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24443 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24444 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24446 newval
= get_thumb32_insn (buf
);
24447 newval
&= 0xfbf08f00;
24448 newval
|= (value
& 0xf000) << 4;
24449 newval
|= (value
& 0x0800) << 15;
24450 newval
|= (value
& 0x0700) << 4;
24451 newval
|= (value
& 0x00ff);
24452 put_thumb32_insn (buf
, newval
);
24456 newval
= md_chars_to_number (buf
, 4);
24457 newval
&= 0xfff0f000;
24458 newval
|= value
& 0x0fff;
24459 newval
|= (value
& 0xf000) << 4;
24460 md_number_to_chars (buf
, newval
, 4);
24465 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24466 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24467 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24468 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24469 gas_assert (!fixP
->fx_done
);
24472 bfd_boolean is_mov
;
24473 bfd_vma encoded_addend
= value
;
24475 /* Check that addend can be encoded in instruction. */
24476 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24478 _("the offset 0x%08lX is not representable"),
24479 (unsigned long) encoded_addend
);
24481 /* Extract the instruction. */
24482 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24483 is_mov
= (insn
& 0xf800) == 0x2000;
24488 if (!seg
->use_rela_p
)
24489 insn
|= encoded_addend
;
24495 /* Extract the instruction. */
24496 /* Encoding is the following
24501 /* The following conditions must be true :
24506 rd
= (insn
>> 4) & 0xf;
24508 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24510 _("Unable to process relocation for thumb opcode: %lx"),
24511 (unsigned long) insn
);
24513 /* Encode as ADD immediate8 thumb 1 code. */
24514 insn
= 0x3000 | (rd
<< 8);
24516 /* Place the encoded addend into the first 8 bits of the
24518 if (!seg
->use_rela_p
)
24519 insn
|= encoded_addend
;
24522 /* Update the instruction. */
24523 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24527 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24528 case BFD_RELOC_ARM_ALU_PC_G0
:
24529 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24530 case BFD_RELOC_ARM_ALU_PC_G1
:
24531 case BFD_RELOC_ARM_ALU_PC_G2
:
24532 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24533 case BFD_RELOC_ARM_ALU_SB_G0
:
24534 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24535 case BFD_RELOC_ARM_ALU_SB_G1
:
24536 case BFD_RELOC_ARM_ALU_SB_G2
:
24537 gas_assert (!fixP
->fx_done
);
24538 if (!seg
->use_rela_p
)
24541 bfd_vma encoded_addend
;
24542 bfd_vma addend_abs
= llabs (value
);
24544 /* Check that the absolute value of the addend can be
24545 expressed as an 8-bit constant plus a rotation. */
24546 encoded_addend
= encode_arm_immediate (addend_abs
);
24547 if (encoded_addend
== (unsigned int) FAIL
)
24548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24549 _("the offset 0x%08lX is not representable"),
24550 (unsigned long) addend_abs
);
24552 /* Extract the instruction. */
24553 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24555 /* If the addend is positive, use an ADD instruction.
24556 Otherwise use a SUB. Take care not to destroy the S bit. */
24557 insn
&= 0xff1fffff;
24563 /* Place the encoded addend into the first 12 bits of the
24565 insn
&= 0xfffff000;
24566 insn
|= encoded_addend
;
24568 /* Update the instruction. */
24569 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24573 case BFD_RELOC_ARM_LDR_PC_G0
:
24574 case BFD_RELOC_ARM_LDR_PC_G1
:
24575 case BFD_RELOC_ARM_LDR_PC_G2
:
24576 case BFD_RELOC_ARM_LDR_SB_G0
:
24577 case BFD_RELOC_ARM_LDR_SB_G1
:
24578 case BFD_RELOC_ARM_LDR_SB_G2
:
24579 gas_assert (!fixP
->fx_done
);
24580 if (!seg
->use_rela_p
)
24583 bfd_vma addend_abs
= llabs (value
);
24585 /* Check that the absolute value of the addend can be
24586 encoded in 12 bits. */
24587 if (addend_abs
>= 0x1000)
24588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24589 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24590 (unsigned long) addend_abs
);
24592 /* Extract the instruction. */
24593 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24595 /* If the addend is negative, clear bit 23 of the instruction.
24596 Otherwise set it. */
24598 insn
&= ~(1 << 23);
24602 /* Place the absolute value of the addend into the first 12 bits
24603 of the instruction. */
24604 insn
&= 0xfffff000;
24605 insn
|= addend_abs
;
24607 /* Update the instruction. */
24608 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24612 case BFD_RELOC_ARM_LDRS_PC_G0
:
24613 case BFD_RELOC_ARM_LDRS_PC_G1
:
24614 case BFD_RELOC_ARM_LDRS_PC_G2
:
24615 case BFD_RELOC_ARM_LDRS_SB_G0
:
24616 case BFD_RELOC_ARM_LDRS_SB_G1
:
24617 case BFD_RELOC_ARM_LDRS_SB_G2
:
24618 gas_assert (!fixP
->fx_done
);
24619 if (!seg
->use_rela_p
)
24622 bfd_vma addend_abs
= llabs (value
);
24624 /* Check that the absolute value of the addend can be
24625 encoded in 8 bits. */
24626 if (addend_abs
>= 0x100)
24627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24628 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24629 (unsigned long) addend_abs
);
24631 /* Extract the instruction. */
24632 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24634 /* If the addend is negative, clear bit 23 of the instruction.
24635 Otherwise set it. */
24637 insn
&= ~(1 << 23);
24641 /* Place the first four bits of the absolute value of the addend
24642 into the first 4 bits of the instruction, and the remaining
24643 four into bits 8 .. 11. */
24644 insn
&= 0xfffff0f0;
24645 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24647 /* Update the instruction. */
24648 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24652 case BFD_RELOC_ARM_LDC_PC_G0
:
24653 case BFD_RELOC_ARM_LDC_PC_G1
:
24654 case BFD_RELOC_ARM_LDC_PC_G2
:
24655 case BFD_RELOC_ARM_LDC_SB_G0
:
24656 case BFD_RELOC_ARM_LDC_SB_G1
:
24657 case BFD_RELOC_ARM_LDC_SB_G2
:
24658 gas_assert (!fixP
->fx_done
);
24659 if (!seg
->use_rela_p
)
24662 bfd_vma addend_abs
= llabs (value
);
24664 /* Check that the absolute value of the addend is a multiple of
24665 four and, when divided by four, fits in 8 bits. */
24666 if (addend_abs
& 0x3)
24667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24668 _("bad offset 0x%08lX (must be word-aligned)"),
24669 (unsigned long) addend_abs
);
24671 if ((addend_abs
>> 2) > 0xff)
24672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24673 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24674 (unsigned long) addend_abs
);
24676 /* Extract the instruction. */
24677 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24679 /* If the addend is negative, clear bit 23 of the instruction.
24680 Otherwise set it. */
24682 insn
&= ~(1 << 23);
24686 /* Place the addend (divided by four) into the first eight
24687 bits of the instruction. */
24688 insn
&= 0xfffffff0;
24689 insn
|= addend_abs
>> 2;
24691 /* Update the instruction. */
24692 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24696 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24698 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24699 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24700 && ARM_IS_FUNC (fixP
->fx_addsy
)
24701 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24703 /* Force a relocation for a branch 5 bits wide. */
24706 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
24707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24710 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24712 addressT boff
= value
>> 1;
24714 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24715 newval
|= (boff
<< 7);
24716 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24720 case BFD_RELOC_ARM_V4BX
:
24721 /* This will need to go in the object file. */
24725 case BFD_RELOC_UNUSED
:
24727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24728 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24732 /* Translate internal representation of relocation info to BFD target
24736 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24739 bfd_reloc_code_real_type code
;
24741 reloc
= XNEW (arelent
);
24743 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24744 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24745 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24747 if (fixp
->fx_pcrel
)
24749 if (section
->use_rela_p
)
24750 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24752 fixp
->fx_offset
= reloc
->address
;
24754 reloc
->addend
= fixp
->fx_offset
;
24756 switch (fixp
->fx_r_type
)
24759 if (fixp
->fx_pcrel
)
24761 code
= BFD_RELOC_8_PCREL
;
24764 /* Fall through. */
24767 if (fixp
->fx_pcrel
)
24769 code
= BFD_RELOC_16_PCREL
;
24772 /* Fall through. */
24775 if (fixp
->fx_pcrel
)
24777 code
= BFD_RELOC_32_PCREL
;
24780 /* Fall through. */
24782 case BFD_RELOC_ARM_MOVW
:
24783 if (fixp
->fx_pcrel
)
24785 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24788 /* Fall through. */
24790 case BFD_RELOC_ARM_MOVT
:
24791 if (fixp
->fx_pcrel
)
24793 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24796 /* Fall through. */
24798 case BFD_RELOC_ARM_THUMB_MOVW
:
24799 if (fixp
->fx_pcrel
)
24801 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24804 /* Fall through. */
24806 case BFD_RELOC_ARM_THUMB_MOVT
:
24807 if (fixp
->fx_pcrel
)
24809 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24812 /* Fall through. */
24814 case BFD_RELOC_NONE
:
24815 case BFD_RELOC_ARM_PCREL_BRANCH
:
24816 case BFD_RELOC_ARM_PCREL_BLX
:
24817 case BFD_RELOC_RVA
:
24818 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24819 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24820 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24821 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24822 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24823 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24824 case BFD_RELOC_VTABLE_ENTRY
:
24825 case BFD_RELOC_VTABLE_INHERIT
:
24827 case BFD_RELOC_32_SECREL
:
24829 code
= fixp
->fx_r_type
;
24832 case BFD_RELOC_THUMB_PCREL_BLX
:
24834 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24835 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24838 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24841 case BFD_RELOC_ARM_LITERAL
:
24842 case BFD_RELOC_ARM_HWLITERAL
:
24843 /* If this is called then the a literal has
24844 been referenced across a section boundary. */
24845 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24846 _("literal referenced across section boundary"));
24850 case BFD_RELOC_ARM_TLS_CALL
:
24851 case BFD_RELOC_ARM_THM_TLS_CALL
:
24852 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24853 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24854 case BFD_RELOC_ARM_GOT32
:
24855 case BFD_RELOC_ARM_GOTOFF
:
24856 case BFD_RELOC_ARM_GOT_PREL
:
24857 case BFD_RELOC_ARM_PLT32
:
24858 case BFD_RELOC_ARM_TARGET1
:
24859 case BFD_RELOC_ARM_ROSEGREL32
:
24860 case BFD_RELOC_ARM_SBREL32
:
24861 case BFD_RELOC_ARM_PREL31
:
24862 case BFD_RELOC_ARM_TARGET2
:
24863 case BFD_RELOC_ARM_TLS_LDO32
:
24864 case BFD_RELOC_ARM_PCREL_CALL
:
24865 case BFD_RELOC_ARM_PCREL_JUMP
:
24866 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24867 case BFD_RELOC_ARM_ALU_PC_G0
:
24868 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24869 case BFD_RELOC_ARM_ALU_PC_G1
:
24870 case BFD_RELOC_ARM_ALU_PC_G2
:
24871 case BFD_RELOC_ARM_LDR_PC_G0
:
24872 case BFD_RELOC_ARM_LDR_PC_G1
:
24873 case BFD_RELOC_ARM_LDR_PC_G2
:
24874 case BFD_RELOC_ARM_LDRS_PC_G0
:
24875 case BFD_RELOC_ARM_LDRS_PC_G1
:
24876 case BFD_RELOC_ARM_LDRS_PC_G2
:
24877 case BFD_RELOC_ARM_LDC_PC_G0
:
24878 case BFD_RELOC_ARM_LDC_PC_G1
:
24879 case BFD_RELOC_ARM_LDC_PC_G2
:
24880 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24881 case BFD_RELOC_ARM_ALU_SB_G0
:
24882 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24883 case BFD_RELOC_ARM_ALU_SB_G1
:
24884 case BFD_RELOC_ARM_ALU_SB_G2
:
24885 case BFD_RELOC_ARM_LDR_SB_G0
:
24886 case BFD_RELOC_ARM_LDR_SB_G1
:
24887 case BFD_RELOC_ARM_LDR_SB_G2
:
24888 case BFD_RELOC_ARM_LDRS_SB_G0
:
24889 case BFD_RELOC_ARM_LDRS_SB_G1
:
24890 case BFD_RELOC_ARM_LDRS_SB_G2
:
24891 case BFD_RELOC_ARM_LDC_SB_G0
:
24892 case BFD_RELOC_ARM_LDC_SB_G1
:
24893 case BFD_RELOC_ARM_LDC_SB_G2
:
24894 case BFD_RELOC_ARM_V4BX
:
24895 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24896 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24897 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24898 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24899 case BFD_RELOC_ARM_GOTFUNCDESC
:
24900 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24901 case BFD_RELOC_ARM_FUNCDESC
:
24902 code
= fixp
->fx_r_type
;
24905 case BFD_RELOC_ARM_TLS_GOTDESC
:
24906 case BFD_RELOC_ARM_TLS_GD32
:
24907 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24908 case BFD_RELOC_ARM_TLS_LE32
:
24909 case BFD_RELOC_ARM_TLS_IE32
:
24910 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24911 case BFD_RELOC_ARM_TLS_LDM32
:
24912 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24913 /* BFD will include the symbol's address in the addend.
24914 But we don't want that, so subtract it out again here. */
24915 if (!S_IS_COMMON (fixp
->fx_addsy
))
24916 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24917 code
= fixp
->fx_r_type
;
24921 case BFD_RELOC_ARM_IMMEDIATE
:
24922 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24923 _("internal relocation (type: IMMEDIATE) not fixed up"));
24926 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24927 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24928 _("ADRL used for a symbol not defined in the same file"));
24931 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24932 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24933 _("%s used for a symbol not defined in the same file"),
24934 bfd_get_reloc_code_name (fixp
->fx_r_type
));
24937 case BFD_RELOC_ARM_OFFSET_IMM
:
24938 if (section
->use_rela_p
)
24940 code
= fixp
->fx_r_type
;
24944 if (fixp
->fx_addsy
!= NULL
24945 && !S_IS_DEFINED (fixp
->fx_addsy
)
24946 && S_IS_LOCAL (fixp
->fx_addsy
))
24948 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24949 _("undefined local label `%s'"),
24950 S_GET_NAME (fixp
->fx_addsy
));
24954 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24955 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24962 switch (fixp
->fx_r_type
)
24964 case BFD_RELOC_NONE
: type
= "NONE"; break;
24965 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24966 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24967 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24968 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24969 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24970 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24971 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24972 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24973 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24974 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24975 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24976 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24977 default: type
= _("<unknown>"); break;
24979 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24980 _("cannot represent %s relocation in this object file format"),
24987 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24989 && fixp
->fx_addsy
== GOT_symbol
)
24991 code
= BFD_RELOC_ARM_GOTPC
;
24992 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24996 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24998 if (reloc
->howto
== NULL
)
25000 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25001 _("cannot represent %s relocation in this object file format"),
25002 bfd_get_reloc_code_name (code
));
25006 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
25007 vtable entry to be used in the relocation's section offset. */
25008 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25009 reloc
->address
= fixp
->fx_offset
;
25014 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
25017 cons_fix_new_arm (fragS
* frag
,
25021 bfd_reloc_code_real_type reloc
)
25026 FIXME: @@ Should look at CPU word size. */
25030 reloc
= BFD_RELOC_8
;
25033 reloc
= BFD_RELOC_16
;
25037 reloc
= BFD_RELOC_32
;
25040 reloc
= BFD_RELOC_64
;
25045 if (exp
->X_op
== O_secrel
)
25047 exp
->X_op
= O_symbol
;
25048 reloc
= BFD_RELOC_32_SECREL
;
25052 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25055 #if defined (OBJ_COFF)
25057 arm_validate_fix (fixS
* fixP
)
25059 /* If the destination of the branch is a defined symbol which does not have
25060 the THUMB_FUNC attribute, then we must be calling a function which has
25061 the (interfacearm) attribute. We look for the Thumb entry point to that
25062 function and change the branch to refer to that function instead. */
25063 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25064 && fixP
->fx_addsy
!= NULL
25065 && S_IS_DEFINED (fixP
->fx_addsy
)
25066 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25068 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25075 arm_force_relocation (struct fix
* fixp
)
25077 #if defined (OBJ_COFF) && defined (TE_PE)
25078 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25082 /* In case we have a call or a branch to a function in ARM ISA mode from
25083 a thumb function or vice-versa force the relocation. These relocations
25084 are cleared off for some cores that might have blx and simple transformations
25088 switch (fixp
->fx_r_type
)
25090 case BFD_RELOC_ARM_PCREL_JUMP
:
25091 case BFD_RELOC_ARM_PCREL_CALL
:
25092 case BFD_RELOC_THUMB_PCREL_BLX
:
25093 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25097 case BFD_RELOC_ARM_PCREL_BLX
:
25098 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25099 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25100 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25101 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25110 /* Resolve these relocations even if the symbol is extern or weak.
25111 Technically this is probably wrong due to symbol preemption.
25112 In practice these relocations do not have enough range to be useful
25113 at dynamic link time, and some code (e.g. in the Linux kernel)
25114 expects these references to be resolved. */
25115 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25116 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25117 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25118 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25119 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25120 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25121 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25122 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25123 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25124 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25125 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25126 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25127 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25128 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25131 /* Always leave these relocations for the linker. */
25132 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25133 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25134 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25137 /* Always generate relocations against function symbols. */
25138 if (fixp
->fx_r_type
== BFD_RELOC_32
25140 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25143 return generic_force_reloc (fixp
);
25146 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25147 /* Relocations against function names must be left unadjusted,
25148 so that the linker can use this information to generate interworking
25149 stubs. The MIPS version of this function
25150 also prevents relocations that are mips-16 specific, but I do not
25151 know why it does this.
25154 There is one other problem that ought to be addressed here, but
25155 which currently is not: Taking the address of a label (rather
25156 than a function) and then later jumping to that address. Such
25157 addresses also ought to have their bottom bit set (assuming that
25158 they reside in Thumb code), but at the moment they will not. */
25161 arm_fix_adjustable (fixS
* fixP
)
25163 if (fixP
->fx_addsy
== NULL
)
25166 /* Preserve relocations against symbols with function type. */
25167 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25170 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25171 && fixP
->fx_subsy
== NULL
)
25174 /* We need the symbol name for the VTABLE entries. */
25175 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25176 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25179 /* Don't allow symbols to be discarded on GOT related relocs. */
25180 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25181 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25182 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25183 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25184 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25185 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25186 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25187 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25188 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25189 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25190 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25191 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25192 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25193 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25194 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25195 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25196 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25199 /* Similarly for group relocations. */
25200 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25201 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25202 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25205 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25206 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25207 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25208 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25209 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25210 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25211 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25212 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25213 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25216 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25217 offsets, so keep these symbols. */
25218 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25219 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25224 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25228 elf32_arm_target_format (void)
25231 return (target_big_endian
25232 ? "elf32-bigarm-symbian"
25233 : "elf32-littlearm-symbian");
25234 #elif defined (TE_VXWORKS)
25235 return (target_big_endian
25236 ? "elf32-bigarm-vxworks"
25237 : "elf32-littlearm-vxworks");
25238 #elif defined (TE_NACL)
25239 return (target_big_endian
25240 ? "elf32-bigarm-nacl"
25241 : "elf32-littlearm-nacl");
25245 if (target_big_endian
)
25246 return "elf32-bigarm-fdpic";
25248 return "elf32-littlearm-fdpic";
25252 if (target_big_endian
)
25253 return "elf32-bigarm";
25255 return "elf32-littlearm";
25261 armelf_frob_symbol (symbolS
* symp
,
25264 elf_frob_symbol (symp
, puntp
);
25268 /* MD interface: Finalization. */
25273 literal_pool
* pool
;
25275 /* Ensure that all the IT blocks are properly closed. */
25276 check_it_blocks_finished ();
25278 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25280 /* Put it at the end of the relevant section. */
25281 subseg_set (pool
->section
, pool
->sub_section
);
25283 arm_elf_change_section ();
25290 /* Remove any excess mapping symbols generated for alignment frags in
25291 SEC. We may have created a mapping symbol before a zero byte
25292 alignment; remove it if there's a mapping symbol after the
25295 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25296 void *dummy ATTRIBUTE_UNUSED
)
25298 segment_info_type
*seginfo
= seg_info (sec
);
25301 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25304 for (fragp
= seginfo
->frchainP
->frch_root
;
25306 fragp
= fragp
->fr_next
)
25308 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25309 fragS
*next
= fragp
->fr_next
;
25311 /* Variable-sized frags have been converted to fixed size by
25312 this point. But if this was variable-sized to start with,
25313 there will be a fixed-size frag after it. So don't handle
25315 if (sym
== NULL
|| next
== NULL
)
25318 if (S_GET_VALUE (sym
) < next
->fr_address
)
25319 /* Not at the end of this frag. */
25321 know (S_GET_VALUE (sym
) == next
->fr_address
);
25325 if (next
->tc_frag_data
.first_map
!= NULL
)
25327 /* Next frag starts with a mapping symbol. Discard this
25329 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25333 if (next
->fr_next
== NULL
)
25335 /* This mapping symbol is at the end of the section. Discard
25337 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25338 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25342 /* As long as we have empty frags without any mapping symbols,
25344 /* If the next frag is non-empty and does not start with a
25345 mapping symbol, then this mapping symbol is required. */
25346 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25349 next
= next
->fr_next
;
25351 while (next
!= NULL
);
25356 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25360 arm_adjust_symtab (void)
25365 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25367 if (ARM_IS_THUMB (sym
))
25369 if (THUMB_IS_FUNC (sym
))
25371 /* Mark the symbol as a Thumb function. */
25372 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25373 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25374 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25376 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25377 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25379 as_bad (_("%s: unexpected function type: %d"),
25380 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25382 else switch (S_GET_STORAGE_CLASS (sym
))
25385 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25388 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25391 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25399 if (ARM_IS_INTERWORK (sym
))
25400 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25407 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25409 if (ARM_IS_THUMB (sym
))
25411 elf_symbol_type
* elf_sym
;
25413 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25414 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25416 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25417 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25419 /* If it's a .thumb_func, declare it as so,
25420 otherwise tag label as .code 16. */
25421 if (THUMB_IS_FUNC (sym
))
25422 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25423 ST_BRANCH_TO_THUMB
);
25424 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25425 elf_sym
->internal_elf_sym
.st_info
=
25426 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25431 /* Remove any overlapping mapping symbols generated by alignment frags. */
25432 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25433 /* Now do generic ELF adjustments. */
25434 elf_adjust_symtab ();
25438 /* MD interface: Initialization. */
25441 set_constant_flonums (void)
25445 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25446 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25450 /* Auto-select Thumb mode if it's the only available instruction set for the
25451 given architecture. */
25454 autoselect_thumb_from_cpu_variant (void)
25456 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25457 opcode_select (16);
25466 if ( (arm_ops_hsh
= hash_new ()) == NULL
25467 || (arm_cond_hsh
= hash_new ()) == NULL
25468 || (arm_shift_hsh
= hash_new ()) == NULL
25469 || (arm_psr_hsh
= hash_new ()) == NULL
25470 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25471 || (arm_reg_hsh
= hash_new ()) == NULL
25472 || (arm_reloc_hsh
= hash_new ()) == NULL
25473 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25474 as_fatal (_("virtual memory exhausted"));
25476 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25477 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25478 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25479 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25480 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25481 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25482 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25483 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25484 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25485 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25486 (void *) (v7m_psrs
+ i
));
25487 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25488 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25490 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25492 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25493 (void *) (barrier_opt_names
+ i
));
25495 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25497 struct reloc_entry
* entry
= reloc_names
+ i
;
25499 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25500 /* This makes encode_branch() use the EABI versions of this relocation. */
25501 entry
->reloc
= BFD_RELOC_UNUSED
;
25503 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25507 set_constant_flonums ();
25509 /* Set the cpu variant based on the command-line options. We prefer
25510 -mcpu= over -march= if both are set (as for GCC); and we prefer
25511 -mfpu= over any other way of setting the floating point unit.
25512 Use of legacy options with new options are faulted. */
25515 if (mcpu_cpu_opt
|| march_cpu_opt
)
25516 as_bad (_("use of old and new-style options to set CPU type"));
25518 selected_arch
= *legacy_cpu
;
25520 else if (mcpu_cpu_opt
)
25522 selected_arch
= *mcpu_cpu_opt
;
25523 selected_ext
= *mcpu_ext_opt
;
25525 else if (march_cpu_opt
)
25527 selected_arch
= *march_cpu_opt
;
25528 selected_ext
= *march_ext_opt
;
25530 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25535 as_bad (_("use of old and new-style options to set FPU type"));
25537 selected_fpu
= *legacy_fpu
;
25540 selected_fpu
= *mfpu_opt
;
25543 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25544 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25545 /* Some environments specify a default FPU. If they don't, infer it
25546 from the processor. */
25548 selected_fpu
= *mcpu_fpu_opt
;
25549 else if (march_fpu_opt
)
25550 selected_fpu
= *march_fpu_opt
;
25552 selected_fpu
= fpu_default
;
25556 if (ARM_FEATURE_ZERO (selected_fpu
))
25558 if (!no_cpu_selected ())
25559 selected_fpu
= fpu_default
;
25561 selected_fpu
= fpu_arch_fpa
;
25565 if (ARM_FEATURE_ZERO (selected_arch
))
25567 selected_arch
= cpu_default
;
25568 selected_cpu
= selected_arch
;
25570 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25572 /* Autodection of feature mode: allow all features in cpu_variant but leave
25573 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25574 after all instruction have been processed and we can decide what CPU
25575 should be selected. */
25576 if (ARM_FEATURE_ZERO (selected_arch
))
25577 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25579 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25582 autoselect_thumb_from_cpu_variant ();
25584 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25586 #if defined OBJ_COFF || defined OBJ_ELF
25588 unsigned int flags
= 0;
25590 #if defined OBJ_ELF
25591 flags
= meabi_flags
;
25593 switch (meabi_flags
)
25595 case EF_ARM_EABI_UNKNOWN
:
25597 /* Set the flags in the private structure. */
25598 if (uses_apcs_26
) flags
|= F_APCS26
;
25599 if (support_interwork
) flags
|= F_INTERWORK
;
25600 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25601 if (pic_code
) flags
|= F_PIC
;
25602 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25603 flags
|= F_SOFT_FLOAT
;
25605 switch (mfloat_abi_opt
)
25607 case ARM_FLOAT_ABI_SOFT
:
25608 case ARM_FLOAT_ABI_SOFTFP
:
25609 flags
|= F_SOFT_FLOAT
;
25612 case ARM_FLOAT_ABI_HARD
:
25613 if (flags
& F_SOFT_FLOAT
)
25614 as_bad (_("hard-float conflicts with specified fpu"));
25618 /* Using pure-endian doubles (even if soft-float). */
25619 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25620 flags
|= F_VFP_FLOAT
;
25622 #if defined OBJ_ELF
25623 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25624 flags
|= EF_ARM_MAVERICK_FLOAT
;
25627 case EF_ARM_EABI_VER4
:
25628 case EF_ARM_EABI_VER5
:
25629 /* No additional flags to set. */
25636 bfd_set_private_flags (stdoutput
, flags
);
25638 /* We have run out flags in the COFF header to encode the
25639 status of ATPCS support, so instead we create a dummy,
25640 empty, debug section called .arm.atpcs. */
25645 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25649 bfd_set_section_flags
25650 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25651 bfd_set_section_size (stdoutput
, sec
, 0);
25652 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25658 /* Record the CPU type as well. */
25659 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25660 mach
= bfd_mach_arm_iWMMXt2
;
25661 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25662 mach
= bfd_mach_arm_iWMMXt
;
25663 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25664 mach
= bfd_mach_arm_XScale
;
25665 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25666 mach
= bfd_mach_arm_ep9312
;
25667 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25668 mach
= bfd_mach_arm_5TE
;
25669 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25671 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25672 mach
= bfd_mach_arm_5T
;
25674 mach
= bfd_mach_arm_5
;
25676 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25678 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25679 mach
= bfd_mach_arm_4T
;
25681 mach
= bfd_mach_arm_4
;
25683 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25684 mach
= bfd_mach_arm_3M
;
25685 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25686 mach
= bfd_mach_arm_3
;
25687 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25688 mach
= bfd_mach_arm_2a
;
25689 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25690 mach
= bfd_mach_arm_2
;
25692 mach
= bfd_mach_arm_unknown
;
25694 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25697 /* Command line processing. */
25700 Invocation line includes a switch not recognized by the base assembler.
25701 See if it's a processor-specific option.
25703 This routine is somewhat complicated by the need for backwards
25704 compatibility (since older releases of gcc can't be changed).
25705 The new options try to make the interface as compatible as
25708 New options (supported) are:
25710 -mcpu=<cpu name> Assemble for selected processor
25711 -march=<architecture name> Assemble for selected architecture
25712 -mfpu=<fpu architecture> Assemble for selected FPU.
25713 -EB/-mbig-endian Big-endian
25714 -EL/-mlittle-endian Little-endian
25715 -k Generate PIC code
25716 -mthumb Start in Thumb mode
25717 -mthumb-interwork Code supports ARM/Thumb interworking
25719 -m[no-]warn-deprecated Warn about deprecated features
25720 -m[no-]warn-syms Warn when symbols match instructions
25722 For now we will also provide support for:
25724 -mapcs-32 32-bit Program counter
25725 -mapcs-26 26-bit Program counter
25726 -macps-float Floats passed in FP registers
25727 -mapcs-reentrant Reentrant code
25729 (sometime these will probably be replaced with -mapcs=<list of options>
25730 and -matpcs=<list of options>)
25732 The remaining options are only supported for back-wards compatibility.
25733 Cpu variants, the arm part is optional:
25734 -m[arm]1 Currently not supported.
25735 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25736 -m[arm]3 Arm 3 processor
25737 -m[arm]6[xx], Arm 6 processors
25738 -m[arm]7[xx][t][[d]m] Arm 7 processors
25739 -m[arm]8[10] Arm 8 processors
25740 -m[arm]9[20][tdmi] Arm 9 processors
25741 -mstrongarm[110[0]] StrongARM processors
25742 -mxscale XScale processors
25743 -m[arm]v[2345[t[e]]] Arm architectures
25744 -mall All (except the ARM1)
25746 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25747 -mfpe-old (No float load/store multiples)
25748 -mvfpxd VFP Single precision
25750 -mno-fpu Disable all floating point instructions
25752 The following CPU names are recognized:
25753 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25754 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25755 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25756 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25757 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25758 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25759 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25763 const char * md_shortopts
= "m:k";
25765 #ifdef ARM_BI_ENDIAN
25766 #define OPTION_EB (OPTION_MD_BASE + 0)
25767 #define OPTION_EL (OPTION_MD_BASE + 1)
25769 #if TARGET_BYTES_BIG_ENDIAN
25770 #define OPTION_EB (OPTION_MD_BASE + 0)
25772 #define OPTION_EL (OPTION_MD_BASE + 1)
25775 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25776 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
25778 struct option md_longopts
[] =
25781 {"EB", no_argument
, NULL
, OPTION_EB
},
25784 {"EL", no_argument
, NULL
, OPTION_EL
},
25786 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25788 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
25790 {NULL
, no_argument
, NULL
, 0}
25793 size_t md_longopts_size
= sizeof (md_longopts
);
25795 struct arm_option_table
25797 const char * option
; /* Option name to match. */
25798 const char * help
; /* Help information. */
25799 int * var
; /* Variable to change. */
25800 int value
; /* What to change it to. */
25801 const char * deprecated
; /* If non-null, print this message. */
25804 struct arm_option_table arm_opts
[] =
25806 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25807 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25808 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25809 &support_interwork
, 1, NULL
},
25810 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25811 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25812 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25814 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25815 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25816 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25817 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25820 /* These are recognized by the assembler, but have no affect on code. */
25821 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25822 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25824 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25825 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25826 &warn_on_deprecated
, 0, NULL
},
25827 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25828 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25829 {NULL
, NULL
, NULL
, 0, NULL
}
25832 struct arm_legacy_option_table
25834 const char * option
; /* Option name to match. */
25835 const arm_feature_set
** var
; /* Variable to change. */
25836 const arm_feature_set value
; /* What to change it to. */
25837 const char * deprecated
; /* If non-null, print this message. */
25840 const struct arm_legacy_option_table arm_legacy_opts
[] =
25842 /* DON'T add any new processors to this list -- we want the whole list
25843 to go away... Add them to the processors table instead. */
25844 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25845 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25846 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25847 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25848 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25849 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25850 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25851 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25852 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25853 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25854 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25855 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25856 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25857 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25858 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25859 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25860 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25861 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25862 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25863 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25864 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25865 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25866 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25867 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25868 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25869 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25870 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25871 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25872 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25873 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25874 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25875 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25876 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25877 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25878 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25879 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25880 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25881 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25882 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25883 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25884 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25885 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25886 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25887 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25888 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25889 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25890 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25891 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25892 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25893 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25894 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25895 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25896 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25897 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25898 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25899 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25900 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25901 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25902 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25903 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25904 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25905 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25906 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25907 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25908 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25909 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25910 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25911 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25912 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25913 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25914 N_("use -mcpu=strongarm110")},
25915 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25916 N_("use -mcpu=strongarm1100")},
25917 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25918 N_("use -mcpu=strongarm1110")},
25919 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25920 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25921 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25923 /* Architecture variants -- don't add any more to this list either. */
25924 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25925 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25926 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25927 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25928 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25929 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25930 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25931 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25932 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25933 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25934 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25935 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25936 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25937 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25938 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25939 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25940 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25941 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25943 /* Floating point variants -- don't add any more to this list either. */
25944 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25945 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25946 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25947 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25948 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25950 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25953 struct arm_cpu_option_table
25957 const arm_feature_set value
;
25958 const arm_feature_set ext
;
25959 /* For some CPUs we assume an FPU unless the user explicitly sets
25961 const arm_feature_set default_fpu
;
25962 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25964 const char * canonical_name
;
25967 /* This list should, at a minimum, contain all the cpu names
25968 recognized by GCC. */
25969 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25971 static const struct arm_cpu_option_table arm_cpus
[] =
25973 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25976 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25979 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25982 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25985 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25988 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25991 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25994 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25997 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
26000 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
26003 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
26006 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
26009 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
26012 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
26015 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
26018 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
26021 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
26024 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
26027 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
26030 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
26033 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
26036 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
26039 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
26042 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
26045 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
26048 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26051 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26054 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26057 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26060 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26063 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26066 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26069 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26072 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26075 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26078 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26081 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26084 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26087 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26090 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26093 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26096 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26099 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26102 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26105 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26108 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26112 /* For V5 or later processors we default to using VFP; but the user
26113 should really set the FPU type explicitly. */
26114 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26117 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26120 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26123 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26126 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26129 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26132 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26135 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26138 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26141 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26144 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26147 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26150 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26153 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26156 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26159 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26162 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26165 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26168 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26171 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26174 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26177 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26180 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26183 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26186 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26189 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26192 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26195 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26198 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26201 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26204 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26207 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26210 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26213 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26216 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26219 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26222 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26223 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26225 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26227 FPU_ARCH_NEON_VFP_V4
),
26228 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26229 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26230 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26231 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26232 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26233 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26234 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26236 FPU_ARCH_NEON_VFP_V4
),
26237 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26239 FPU_ARCH_NEON_VFP_V4
),
26240 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26242 FPU_ARCH_NEON_VFP_V4
),
26243 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26244 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26245 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26246 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26247 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26248 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26249 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26250 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26251 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26252 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26253 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26254 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26255 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26256 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26257 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26258 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26259 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26260 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26261 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26262 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26263 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26264 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26266 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26267 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26268 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26269 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26270 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26272 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26273 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26276 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26278 FPU_ARCH_VFP_V3D16
),
26279 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26280 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26282 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26283 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26284 FPU_ARCH_VFP_V3D16
),
26285 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26286 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26287 FPU_ARCH_VFP_V3D16
),
26288 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26289 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26290 FPU_ARCH_NEON_VFP_ARMV8
),
26291 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26292 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26294 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26297 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26300 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26303 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26306 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26309 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26312 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26315 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26316 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26317 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26318 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26319 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26320 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26321 /* ??? XSCALE is really an architecture. */
26322 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26326 /* ??? iwmmxt is not a processor. */
26327 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26330 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26333 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26338 ARM_CPU_OPT ("ep9312", "ARM920T",
26339 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26340 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26342 /* Marvell processors. */
26343 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26344 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26345 FPU_ARCH_VFP_V3D16
),
26346 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26347 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26348 FPU_ARCH_NEON_VFP_V4
),
26350 /* APM X-Gene family. */
26351 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26353 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26354 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26355 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26356 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26358 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26362 struct arm_ext_table
26366 const arm_feature_set merge
;
26367 const arm_feature_set clear
;
26370 struct arm_arch_option_table
26374 const arm_feature_set value
;
26375 const arm_feature_set default_fpu
;
26376 const struct arm_ext_table
* ext_table
;
26379 /* Used to add support for +E and +noE extension. */
26380 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26381 /* Used to add support for a +E extension. */
26382 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26383 /* Used to add support for a +noE extension. */
26384 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26386 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26387 ~0 & ~FPU_ENDIAN_PURE)
26389 static const struct arm_ext_table armv5te_ext_table
[] =
26391 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26392 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26395 static const struct arm_ext_table armv7_ext_table
[] =
26397 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26398 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26401 static const struct arm_ext_table armv7ve_ext_table
[] =
26403 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26404 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26405 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26406 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26407 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26408 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26409 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26411 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26412 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26414 /* Aliases for +simd. */
26415 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26417 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26418 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26419 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26421 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26424 static const struct arm_ext_table armv7a_ext_table
[] =
26426 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26427 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26428 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26429 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26430 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26431 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
26432 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26434 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
26435 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26437 /* Aliases for +simd. */
26438 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26439 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26441 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26442 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26444 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
26445 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
26446 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26449 static const struct arm_ext_table armv7r_ext_table
[] =
26451 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
26452 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
26453 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26454 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26455 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
26456 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26457 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26458 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
26459 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26462 static const struct arm_ext_table armv7em_ext_table
[] =
26464 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
26465 /* Alias for +fp, used to be known as fpv4-sp-d16. */
26466 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
26467 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
26468 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26469 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
26470 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26473 static const struct arm_ext_table armv8a_ext_table
[] =
26475 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26476 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26477 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26478 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26480 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26481 should use the +simd option to turn on FP. */
26482 ARM_REMOVE ("fp", ALL_FP
),
26483 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26484 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26485 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26489 static const struct arm_ext_table armv81a_ext_table
[] =
26491 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26492 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26493 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26495 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26496 should use the +simd option to turn on FP. */
26497 ARM_REMOVE ("fp", ALL_FP
),
26498 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26499 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26500 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26503 static const struct arm_ext_table armv82a_ext_table
[] =
26505 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26506 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
26507 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
26508 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26509 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26510 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26512 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26513 should use the +simd option to turn on FP. */
26514 ARM_REMOVE ("fp", ALL_FP
),
26515 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26516 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26517 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26520 static const struct arm_ext_table armv84a_ext_table
[] =
26522 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26523 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26524 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26525 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26527 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26528 should use the +simd option to turn on FP. */
26529 ARM_REMOVE ("fp", ALL_FP
),
26530 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26531 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26532 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26535 static const struct arm_ext_table armv85a_ext_table
[] =
26537 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26538 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26539 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26540 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26542 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26543 should use the +simd option to turn on FP. */
26544 ARM_REMOVE ("fp", ALL_FP
),
26545 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26548 static const struct arm_ext_table armv8m_main_ext_table
[] =
26550 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26551 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26552 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
26553 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26554 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26557 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
26559 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26560 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26562 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26563 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
26566 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26567 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
26568 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26571 static const struct arm_ext_table armv8r_ext_table
[] =
26573 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26574 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26575 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26576 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26577 ARM_REMOVE ("fp", ALL_FP
),
26578 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
26579 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26582 /* This list should, at a minimum, contain all the architecture names
26583 recognized by GCC. */
26584 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
26585 #define ARM_ARCH_OPT2(N, V, DF, ext) \
26586 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
26588 static const struct arm_arch_option_table arm_archs
[] =
26590 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26591 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26592 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26593 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26594 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26595 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26596 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26597 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26598 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26599 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26600 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26601 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26602 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26603 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26604 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
26605 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
26606 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
26607 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26608 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26609 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
26610 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
26611 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26612 kept to preserve existing behaviour. */
26613 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26614 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26615 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
26616 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
26617 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
26618 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26619 kept to preserve existing behaviour. */
26620 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26621 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26622 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26623 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26624 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
26625 /* The official spelling of the ARMv7 profile variants is the dashed form.
26626 Accept the non-dashed form for compatibility with old toolchains. */
26627 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26628 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
26629 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26630 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26631 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26632 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26633 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26634 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
26635 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26636 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
26638 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
26640 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
26641 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
26642 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
26643 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
26644 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
26645 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
26646 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
26647 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26648 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26649 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
26650 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26652 #undef ARM_ARCH_OPT
26654 /* ISA extensions in the co-processor and main instruction set space. */
26656 struct arm_option_extension_value_table
26660 const arm_feature_set merge_value
;
26661 const arm_feature_set clear_value
;
26662 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26663 indicates that an extension is available for all architectures while
26664 ARM_ANY marks an empty entry. */
26665 const arm_feature_set allowed_archs
[2];
26668 /* The following table must be in alphabetical order with a NULL last entry. */
26670 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26671 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26673 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
26674 use the context sensitive approach using arm_ext_table's. */
26675 static const struct arm_option_extension_value_table arm_extensions
[] =
26677 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26678 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26679 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26680 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26681 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26682 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26683 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26685 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26686 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26687 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26688 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26689 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26690 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26691 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26693 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26694 | ARM_EXT2_FP16_FML
),
26695 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26696 | ARM_EXT2_FP16_FML
),
26698 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26699 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26700 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26701 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26702 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26703 Thumb divide instruction. Due to this having the same name as the
26704 previous entry, this will be ignored when doing command-line parsing and
26705 only considered by build attribute selection code. */
26706 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26707 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26708 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26709 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26710 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26711 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26712 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26713 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26714 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26715 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26716 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26717 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26718 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26719 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26720 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26721 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26722 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26723 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26724 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26725 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26726 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26728 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26729 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26730 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26731 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26732 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26733 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26734 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26735 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26737 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26738 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26739 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26740 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26741 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26742 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26743 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26744 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26746 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26747 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26748 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26749 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26750 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26754 /* ISA floating-point and Advanced SIMD extensions. */
26755 struct arm_option_fpu_value_table
26758 const arm_feature_set value
;
26761 /* This list should, at a minimum, contain all the fpu names
26762 recognized by GCC. */
26763 static const struct arm_option_fpu_value_table arm_fpus
[] =
26765 {"softfpa", FPU_NONE
},
26766 {"fpe", FPU_ARCH_FPE
},
26767 {"fpe2", FPU_ARCH_FPE
},
26768 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26769 {"fpa", FPU_ARCH_FPA
},
26770 {"fpa10", FPU_ARCH_FPA
},
26771 {"fpa11", FPU_ARCH_FPA
},
26772 {"arm7500fe", FPU_ARCH_FPA
},
26773 {"softvfp", FPU_ARCH_VFP
},
26774 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26775 {"vfp", FPU_ARCH_VFP_V2
},
26776 {"vfp9", FPU_ARCH_VFP_V2
},
26777 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26778 {"vfp10", FPU_ARCH_VFP_V2
},
26779 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26780 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26781 {"vfpv2", FPU_ARCH_VFP_V2
},
26782 {"vfpv3", FPU_ARCH_VFP_V3
},
26783 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26784 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26785 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26786 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26787 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26788 {"arm1020t", FPU_ARCH_VFP_V1
},
26789 {"arm1020e", FPU_ARCH_VFP_V2
},
26790 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26791 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26792 {"maverick", FPU_ARCH_MAVERICK
},
26793 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26794 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26795 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26796 {"vfpv4", FPU_ARCH_VFP_V4
},
26797 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26798 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26799 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26800 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26801 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26802 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26803 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26804 {"crypto-neon-fp-armv8",
26805 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26806 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26807 {"crypto-neon-fp-armv8.1",
26808 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26809 {NULL
, ARM_ARCH_NONE
}
26812 struct arm_option_value_table
26818 static const struct arm_option_value_table arm_float_abis
[] =
26820 {"hard", ARM_FLOAT_ABI_HARD
},
26821 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26822 {"soft", ARM_FLOAT_ABI_SOFT
},
26827 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26828 static const struct arm_option_value_table arm_eabis
[] =
26830 {"gnu", EF_ARM_EABI_UNKNOWN
},
26831 {"4", EF_ARM_EABI_VER4
},
26832 {"5", EF_ARM_EABI_VER5
},
26837 struct arm_long_option_table
26839 const char * option
; /* Substring to match. */
26840 const char * help
; /* Help information. */
26841 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26842 const char * deprecated
; /* If non-null, print this message. */
26846 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26847 arm_feature_set
*ext_set
,
26848 const struct arm_ext_table
*ext_table
)
26850 /* We insist on extensions being specified in alphabetical order, and with
26851 extensions being added before being removed. We achieve this by having
26852 the global ARM_EXTENSIONS table in alphabetical order, and using the
26853 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26854 or removing it (0) and only allowing it to change in the order
26856 const struct arm_option_extension_value_table
* opt
= NULL
;
26857 const arm_feature_set arm_any
= ARM_ANY
;
26858 int adding_value
= -1;
26860 while (str
!= NULL
&& *str
!= 0)
26867 as_bad (_("invalid architectural extension"));
26872 ext
= strchr (str
, '+');
26877 len
= strlen (str
);
26879 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26881 if (adding_value
!= 0)
26884 opt
= arm_extensions
;
26892 if (adding_value
== -1)
26895 opt
= arm_extensions
;
26897 else if (adding_value
!= 1)
26899 as_bad (_("must specify extensions to add before specifying "
26900 "those to remove"));
26907 as_bad (_("missing architectural extension"));
26911 gas_assert (adding_value
!= -1);
26912 gas_assert (opt
!= NULL
);
26914 if (ext_table
!= NULL
)
26916 const struct arm_ext_table
* ext_opt
= ext_table
;
26917 bfd_boolean found
= FALSE
;
26918 for (; ext_opt
->name
!= NULL
; ext_opt
++)
26919 if (ext_opt
->name_len
== len
26920 && strncmp (ext_opt
->name
, str
, len
) == 0)
26924 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
26925 /* TODO: Option not supported. When we remove the
26926 legacy table this case should error out. */
26929 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
26933 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
26934 /* TODO: Option not supported. When we remove the
26935 legacy table this case should error out. */
26937 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
26949 /* Scan over the options table trying to find an exact match. */
26950 for (; opt
->name
!= NULL
; opt
++)
26951 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26953 int i
, nb_allowed_archs
=
26954 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26955 /* Check we can apply the extension to this architecture. */
26956 for (i
= 0; i
< nb_allowed_archs
; i
++)
26959 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26961 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26964 if (i
== nb_allowed_archs
)
26966 as_bad (_("extension does not apply to the base architecture"));
26970 /* Add or remove the extension. */
26972 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26974 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26976 /* Allowing Thumb division instructions for ARMv7 in autodetection
26977 rely on this break so that duplicate extensions (extensions
26978 with the same name as a previous extension in the list) are not
26979 considered for command-line parsing. */
26983 if (opt
->name
== NULL
)
26985 /* Did we fail to find an extension because it wasn't specified in
26986 alphabetical order, or because it does not exist? */
26988 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26989 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26992 if (opt
->name
== NULL
)
26993 as_bad (_("unknown architectural extension `%s'"), str
);
26995 as_bad (_("architectural extensions must be specified in "
26996 "alphabetical order"));
27002 /* We should skip the extension we've just matched the next time
27014 arm_parse_cpu (const char *str
)
27016 const struct arm_cpu_option_table
*opt
;
27017 const char *ext
= strchr (str
, '+');
27023 len
= strlen (str
);
27027 as_bad (_("missing cpu name `%s'"), str
);
27031 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
27032 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27034 mcpu_cpu_opt
= &opt
->value
;
27035 if (mcpu_ext_opt
== NULL
)
27036 mcpu_ext_opt
= XNEW (arm_feature_set
);
27037 *mcpu_ext_opt
= opt
->ext
;
27038 mcpu_fpu_opt
= &opt
->default_fpu
;
27039 if (opt
->canonical_name
)
27041 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
27042 strcpy (selected_cpu_name
, opt
->canonical_name
);
27048 if (len
>= sizeof selected_cpu_name
)
27049 len
= (sizeof selected_cpu_name
) - 1;
27051 for (i
= 0; i
< len
; i
++)
27052 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27053 selected_cpu_name
[i
] = 0;
27057 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
27062 as_bad (_("unknown cpu `%s'"), str
);
27067 arm_parse_arch (const char *str
)
27069 const struct arm_arch_option_table
*opt
;
27070 const char *ext
= strchr (str
, '+');
27076 len
= strlen (str
);
27080 as_bad (_("missing architecture name `%s'"), str
);
27084 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27085 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27087 march_cpu_opt
= &opt
->value
;
27088 if (march_ext_opt
== NULL
)
27089 march_ext_opt
= XNEW (arm_feature_set
);
27090 *march_ext_opt
= arm_arch_none
;
27091 march_fpu_opt
= &opt
->default_fpu
;
27092 strcpy (selected_cpu_name
, opt
->name
);
27095 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27101 as_bad (_("unknown architecture `%s'\n"), str
);
27106 arm_parse_fpu (const char * str
)
27108 const struct arm_option_fpu_value_table
* opt
;
27110 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27111 if (streq (opt
->name
, str
))
27113 mfpu_opt
= &opt
->value
;
27117 as_bad (_("unknown floating point format `%s'\n"), str
);
27122 arm_parse_float_abi (const char * str
)
27124 const struct arm_option_value_table
* opt
;
27126 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27127 if (streq (opt
->name
, str
))
27129 mfloat_abi_opt
= opt
->value
;
27133 as_bad (_("unknown floating point abi `%s'\n"), str
);
27139 arm_parse_eabi (const char * str
)
27141 const struct arm_option_value_table
*opt
;
27143 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27144 if (streq (opt
->name
, str
))
27146 meabi_flags
= opt
->value
;
27149 as_bad (_("unknown EABI `%s'\n"), str
);
27155 arm_parse_it_mode (const char * str
)
27157 bfd_boolean ret
= TRUE
;
27159 if (streq ("arm", str
))
27160 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27161 else if (streq ("thumb", str
))
27162 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27163 else if (streq ("always", str
))
27164 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27165 else if (streq ("never", str
))
27166 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27169 as_bad (_("unknown implicit IT mode `%s', should be "\
27170 "arm, thumb, always, or never."), str
);
27178 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27180 codecomposer_syntax
= TRUE
;
27181 arm_comment_chars
[0] = ';';
27182 arm_line_separator_chars
[0] = 0;
27186 struct arm_long_option_table arm_long_opts
[] =
27188 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27189 arm_parse_cpu
, NULL
},
27190 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27191 arm_parse_arch
, NULL
},
27192 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27193 arm_parse_fpu
, NULL
},
27194 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27195 arm_parse_float_abi
, NULL
},
27197 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27198 arm_parse_eabi
, NULL
},
27200 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27201 arm_parse_it_mode
, NULL
},
27202 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27203 arm_ccs_mode
, NULL
},
27204 {NULL
, NULL
, 0, NULL
}
27208 md_parse_option (int c
, const char * arg
)
27210 struct arm_option_table
*opt
;
27211 const struct arm_legacy_option_table
*fopt
;
27212 struct arm_long_option_table
*lopt
;
27218 target_big_endian
= 1;
27224 target_big_endian
= 0;
27228 case OPTION_FIX_V4BX
:
27236 #endif /* OBJ_ELF */
27239 /* Listing option. Just ignore these, we don't support additional
27244 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27246 if (c
== opt
->option
[0]
27247 && ((arg
== NULL
&& opt
->option
[1] == 0)
27248 || streq (arg
, opt
->option
+ 1)))
27250 /* If the option is deprecated, tell the user. */
27251 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27252 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27253 arg
? arg
: "", _(opt
->deprecated
));
27255 if (opt
->var
!= NULL
)
27256 *opt
->var
= opt
->value
;
27262 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27264 if (c
== fopt
->option
[0]
27265 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27266 || streq (arg
, fopt
->option
+ 1)))
27268 /* If the option is deprecated, tell the user. */
27269 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27270 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27271 arg
? arg
: "", _(fopt
->deprecated
));
27273 if (fopt
->var
!= NULL
)
27274 *fopt
->var
= &fopt
->value
;
27280 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27282 /* These options are expected to have an argument. */
27283 if (c
== lopt
->option
[0]
27285 && strncmp (arg
, lopt
->option
+ 1,
27286 strlen (lopt
->option
+ 1)) == 0)
27288 /* If the option is deprecated, tell the user. */
27289 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27290 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27291 _(lopt
->deprecated
));
27293 /* Call the sup-option parser. */
27294 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27305 md_show_usage (FILE * fp
)
27307 struct arm_option_table
*opt
;
27308 struct arm_long_option_table
*lopt
;
27310 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27312 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27313 if (opt
->help
!= NULL
)
27314 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27316 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27317 if (lopt
->help
!= NULL
)
27318 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27322 -EB assemble code for a big-endian cpu\n"));
27327 -EL assemble code for a little-endian cpu\n"));
27331 --fix-v4bx Allow BX in ARMv4 code\n"));
27335 --fdpic generate an FDPIC object file\n"));
27336 #endif /* OBJ_ELF */
27344 arm_feature_set flags
;
27345 } cpu_arch_ver_table
;
27347 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27348 chronologically for architectures, with an exception for ARMv6-M and
27349 ARMv6S-M due to legacy reasons. No new architecture should have a
27350 special case. This allows for build attribute selection results to be
27351 stable when new architectures are added. */
27352 static const cpu_arch_ver_table cpu_arch_ver
[] =
27354 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27355 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27356 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27357 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27358 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27359 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27360 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27361 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27362 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27363 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27364 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27365 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27366 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27367 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27368 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27369 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27370 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27371 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27372 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27373 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27374 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27375 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27376 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27377 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27379 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27380 always selected build attributes to match those of ARMv6-M
27381 (resp. ARMv6S-M). However, due to these architectures being a strict
27382 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27383 would be selected when fully respecting chronology of architectures.
27384 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27385 move them before ARMv7 architectures. */
27386 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27387 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27389 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27390 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27391 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27392 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27393 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27394 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27395 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27396 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27397 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27398 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27399 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27400 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27401 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27402 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27403 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27404 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27405 {-1, ARM_ARCH_NONE
}
27408 /* Set an attribute if it has not already been set by the user. */
27411 aeabi_set_attribute_int (int tag
, int value
)
27414 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27415 || !attributes_set_explicitly
[tag
])
27416 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27420 aeabi_set_attribute_string (int tag
, const char *value
)
27423 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27424 || !attributes_set_explicitly
[tag
])
27425 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27428 /* Return whether features in the *NEEDED feature set are available via
27429 extensions for the architecture whose feature set is *ARCH_FSET. */
27432 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27433 const arm_feature_set
*needed
)
27435 int i
, nb_allowed_archs
;
27436 arm_feature_set ext_fset
;
27437 const struct arm_option_extension_value_table
*opt
;
27439 ext_fset
= arm_arch_none
;
27440 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27442 /* Extension does not provide any feature we need. */
27443 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27447 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27448 for (i
= 0; i
< nb_allowed_archs
; i
++)
27451 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27454 /* Extension is available, add it. */
27455 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27456 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27460 /* Can we enable all features in *needed? */
27461 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27464 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27465 a given architecture feature set *ARCH_EXT_FSET including extension feature
27466 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27467 - if true, check for an exact match of the architecture modulo extensions;
27468 - otherwise, select build attribute value of the first superset
27469 architecture released so that results remains stable when new architectures
27471 For -march/-mcpu=all the build attribute value of the most featureful
27472 architecture is returned. Tag_CPU_arch_profile result is returned in
27476 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27477 const arm_feature_set
*ext_fset
,
27478 char *profile
, int exact_match
)
27480 arm_feature_set arch_fset
;
27481 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27483 /* Select most featureful architecture with all its extensions if building
27484 for -march=all as the feature sets used to set build attributes. */
27485 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27487 /* Force revisiting of decision for each new architecture. */
27488 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27490 return TAG_CPU_ARCH_V8
;
27493 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27495 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27497 arm_feature_set known_arch_fset
;
27499 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27502 /* Base architecture match user-specified architecture and
27503 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27504 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27509 /* Base architecture match user-specified architecture only
27510 (eg. ARMv6-M in the same case as above). Record it in case we
27511 find a match with above condition. */
27512 else if (p_ver_ret
== NULL
27513 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27519 /* Architecture has all features wanted. */
27520 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27522 arm_feature_set added_fset
;
27524 /* Compute features added by this architecture over the one
27525 recorded in p_ver_ret. */
27526 if (p_ver_ret
!= NULL
)
27527 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27529 /* First architecture that match incl. with extensions, or the
27530 only difference in features over the recorded match is
27531 features that were optional and are now mandatory. */
27532 if (p_ver_ret
== NULL
27533 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27539 else if (p_ver_ret
== NULL
)
27541 arm_feature_set needed_ext_fset
;
27543 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27545 /* Architecture has all features needed when using some
27546 extensions. Record it and continue searching in case there
27547 exist an architecture providing all needed features without
27548 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27550 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27557 if (p_ver_ret
== NULL
)
27561 /* Tag_CPU_arch_profile. */
27562 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27563 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27564 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27565 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27567 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27569 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27573 return p_ver_ret
->val
;
27576 /* Set the public EABI object attributes. */
27579 aeabi_set_public_attributes (void)
27581 char profile
= '\0';
27584 int fp16_optional
= 0;
27585 int skip_exact_match
= 0;
27586 arm_feature_set flags
, flags_arch
, flags_ext
;
27588 /* Autodetection mode, choose the architecture based the instructions
27590 if (no_cpu_selected ())
27592 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27594 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27595 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27597 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27598 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27600 /* Code run during relaxation relies on selected_cpu being set. */
27601 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27602 flags_ext
= arm_arch_none
;
27603 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27604 selected_ext
= flags_ext
;
27605 selected_cpu
= flags
;
27607 /* Otherwise, choose the architecture based on the capabilities of the
27611 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27612 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27613 flags_ext
= selected_ext
;
27614 flags
= selected_cpu
;
27616 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27618 /* Allow the user to override the reported architecture. */
27619 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27621 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27622 flags_ext
= arm_arch_none
;
27625 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27627 /* When this function is run again after relaxation has happened there is no
27628 way to determine whether an architecture or CPU was specified by the user:
27629 - selected_cpu is set above for relaxation to work;
27630 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27631 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27632 Therefore, if not in -march=all case we first try an exact match and fall
27633 back to autodetection. */
27634 if (!skip_exact_match
)
27635 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27637 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27639 as_bad (_("no architecture contains all the instructions used\n"));
27641 /* Tag_CPU_name. */
27642 if (selected_cpu_name
[0])
27646 q
= selected_cpu_name
;
27647 if (strncmp (q
, "armv", 4) == 0)
27652 for (i
= 0; q
[i
]; i
++)
27653 q
[i
] = TOUPPER (q
[i
]);
27655 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27658 /* Tag_CPU_arch. */
27659 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27661 /* Tag_CPU_arch_profile. */
27662 if (profile
!= '\0')
27663 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27665 /* Tag_DSP_extension. */
27666 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27667 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27669 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27670 /* Tag_ARM_ISA_use. */
27671 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27672 || ARM_FEATURE_ZERO (flags_arch
))
27673 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27675 /* Tag_THUMB_ISA_use. */
27676 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27677 || ARM_FEATURE_ZERO (flags_arch
))
27681 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27682 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27684 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27688 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27691 /* Tag_VFP_arch. */
27692 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27693 aeabi_set_attribute_int (Tag_VFP_arch
,
27694 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27696 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27697 aeabi_set_attribute_int (Tag_VFP_arch
,
27698 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27700 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27703 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27705 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27707 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27710 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27711 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27712 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27713 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27714 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27716 /* Tag_ABI_HardFP_use. */
27717 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27718 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27719 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27721 /* Tag_WMMX_arch. */
27722 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27723 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27724 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27725 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27727 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27728 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27729 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27730 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27731 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27732 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27734 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27736 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27740 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27745 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27746 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27747 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27751 We set Tag_DIV_use to two when integer divide instructions have been used
27752 in ARM state, or when Thumb integer divide instructions have been used,
27753 but we have no architecture profile set, nor have we any ARM instructions.
27755 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27756 by the base architecture.
27758 For new architectures we will have to check these tests. */
27759 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27760 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27761 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27762 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27763 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27764 || (profile
== '\0'
27765 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27766 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27767 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27769 /* Tag_MP_extension_use. */
27770 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27771 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27773 /* Tag Virtualization_use. */
27774 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27776 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27779 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27782 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27783 finished and free extension feature bits which will not be used anymore. */
27786 arm_md_post_relax (void)
27788 aeabi_set_public_attributes ();
27789 XDELETE (mcpu_ext_opt
);
27790 mcpu_ext_opt
= NULL
;
27791 XDELETE (march_ext_opt
);
27792 march_ext_opt
= NULL
;
27795 /* Add the default contents for the .ARM.attributes section. */
27800 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27803 aeabi_set_public_attributes ();
27805 #endif /* OBJ_ELF */
27807 /* Parse a .cpu directive. */
27810 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27812 const struct arm_cpu_option_table
*opt
;
27816 name
= input_line_pointer
;
27817 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27818 input_line_pointer
++;
27819 saved_char
= *input_line_pointer
;
27820 *input_line_pointer
= 0;
27822 /* Skip the first "all" entry. */
27823 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27824 if (streq (opt
->name
, name
))
27826 selected_arch
= opt
->value
;
27827 selected_ext
= opt
->ext
;
27828 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27829 if (opt
->canonical_name
)
27830 strcpy (selected_cpu_name
, opt
->canonical_name
);
27834 for (i
= 0; opt
->name
[i
]; i
++)
27835 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27837 selected_cpu_name
[i
] = 0;
27839 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27841 *input_line_pointer
= saved_char
;
27842 demand_empty_rest_of_line ();
27845 as_bad (_("unknown cpu `%s'"), name
);
27846 *input_line_pointer
= saved_char
;
27847 ignore_rest_of_line ();
27850 /* Parse a .arch directive. */
27853 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27855 const struct arm_arch_option_table
*opt
;
27859 name
= input_line_pointer
;
27860 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27861 input_line_pointer
++;
27862 saved_char
= *input_line_pointer
;
27863 *input_line_pointer
= 0;
27865 /* Skip the first "all" entry. */
27866 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27867 if (streq (opt
->name
, name
))
27869 selected_arch
= opt
->value
;
27870 selected_ext
= arm_arch_none
;
27871 selected_cpu
= selected_arch
;
27872 strcpy (selected_cpu_name
, opt
->name
);
27873 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27874 *input_line_pointer
= saved_char
;
27875 demand_empty_rest_of_line ();
27879 as_bad (_("unknown architecture `%s'\n"), name
);
27880 *input_line_pointer
= saved_char
;
27881 ignore_rest_of_line ();
27884 /* Parse a .object_arch directive. */
27887 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27889 const struct arm_arch_option_table
*opt
;
27893 name
= input_line_pointer
;
27894 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27895 input_line_pointer
++;
27896 saved_char
= *input_line_pointer
;
27897 *input_line_pointer
= 0;
27899 /* Skip the first "all" entry. */
27900 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27901 if (streq (opt
->name
, name
))
27903 selected_object_arch
= opt
->value
;
27904 *input_line_pointer
= saved_char
;
27905 demand_empty_rest_of_line ();
27909 as_bad (_("unknown architecture `%s'\n"), name
);
27910 *input_line_pointer
= saved_char
;
27911 ignore_rest_of_line ();
27914 /* Parse a .arch_extension directive. */
27917 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27919 const struct arm_option_extension_value_table
*opt
;
27922 int adding_value
= 1;
27924 name
= input_line_pointer
;
27925 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27926 input_line_pointer
++;
27927 saved_char
= *input_line_pointer
;
27928 *input_line_pointer
= 0;
27930 if (strlen (name
) >= 2
27931 && strncmp (name
, "no", 2) == 0)
27937 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27938 if (streq (opt
->name
, name
))
27940 int i
, nb_allowed_archs
=
27941 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27942 for (i
= 0; i
< nb_allowed_archs
; i
++)
27945 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
27947 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
27951 if (i
== nb_allowed_archs
)
27953 as_bad (_("architectural extension `%s' is not allowed for the "
27954 "current base architecture"), name
);
27959 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
27962 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
27964 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27965 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27966 *input_line_pointer
= saved_char
;
27967 demand_empty_rest_of_line ();
27968 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27969 on this return so that duplicate extensions (extensions with the
27970 same name as a previous extension in the list) are not considered
27971 for command-line parsing. */
27975 if (opt
->name
== NULL
)
27976 as_bad (_("unknown architecture extension `%s'\n"), name
);
27978 *input_line_pointer
= saved_char
;
27979 ignore_rest_of_line ();
27982 /* Parse a .fpu directive. */
27985 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27987 const struct arm_option_fpu_value_table
*opt
;
27991 name
= input_line_pointer
;
27992 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27993 input_line_pointer
++;
27994 saved_char
= *input_line_pointer
;
27995 *input_line_pointer
= 0;
27997 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27998 if (streq (opt
->name
, name
))
28000 selected_fpu
= opt
->value
;
28001 #ifndef CPU_DEFAULT
28002 if (no_cpu_selected ())
28003 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28006 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28007 *input_line_pointer
= saved_char
;
28008 demand_empty_rest_of_line ();
28012 as_bad (_("unknown floating point format `%s'\n"), name
);
28013 *input_line_pointer
= saved_char
;
28014 ignore_rest_of_line ();
28017 /* Copy symbol information. */
28020 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
28022 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
28026 /* Given a symbolic attribute NAME, return the proper integer value.
28027 Returns -1 if the attribute is not known. */
28030 arm_convert_symbolic_attribute (const char *name
)
28032 static const struct
28037 attribute_table
[] =
28039 /* When you modify this table you should
28040 also modify the list in doc/c-arm.texi. */
28041 #define T(tag) {#tag, tag}
28042 T (Tag_CPU_raw_name
),
28045 T (Tag_CPU_arch_profile
),
28046 T (Tag_ARM_ISA_use
),
28047 T (Tag_THUMB_ISA_use
),
28051 T (Tag_Advanced_SIMD_arch
),
28052 T (Tag_PCS_config
),
28053 T (Tag_ABI_PCS_R9_use
),
28054 T (Tag_ABI_PCS_RW_data
),
28055 T (Tag_ABI_PCS_RO_data
),
28056 T (Tag_ABI_PCS_GOT_use
),
28057 T (Tag_ABI_PCS_wchar_t
),
28058 T (Tag_ABI_FP_rounding
),
28059 T (Tag_ABI_FP_denormal
),
28060 T (Tag_ABI_FP_exceptions
),
28061 T (Tag_ABI_FP_user_exceptions
),
28062 T (Tag_ABI_FP_number_model
),
28063 T (Tag_ABI_align_needed
),
28064 T (Tag_ABI_align8_needed
),
28065 T (Tag_ABI_align_preserved
),
28066 T (Tag_ABI_align8_preserved
),
28067 T (Tag_ABI_enum_size
),
28068 T (Tag_ABI_HardFP_use
),
28069 T (Tag_ABI_VFP_args
),
28070 T (Tag_ABI_WMMX_args
),
28071 T (Tag_ABI_optimization_goals
),
28072 T (Tag_ABI_FP_optimization_goals
),
28073 T (Tag_compatibility
),
28074 T (Tag_CPU_unaligned_access
),
28075 T (Tag_FP_HP_extension
),
28076 T (Tag_VFP_HP_extension
),
28077 T (Tag_ABI_FP_16bit_format
),
28078 T (Tag_MPextension_use
),
28080 T (Tag_nodefaults
),
28081 T (Tag_also_compatible_with
),
28082 T (Tag_conformance
),
28084 T (Tag_Virtualization_use
),
28085 T (Tag_DSP_extension
),
28086 /* We deliberately do not include Tag_MPextension_use_legacy. */
28094 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28095 if (streq (name
, attribute_table
[i
].name
))
28096 return attribute_table
[i
].tag
;
28101 /* Apply sym value for relocations only in the case that they are for
28102 local symbols in the same segment as the fixup and you have the
28103 respective architectural feature for blx and simple switches. */
28106 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28109 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28110 /* PR 17444: If the local symbol is in a different section then a reloc
28111 will always be generated for it, so applying the symbol value now
28112 will result in a double offset being stored in the relocation. */
28113 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28114 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28116 switch (fixP
->fx_r_type
)
28118 case BFD_RELOC_ARM_PCREL_BLX
:
28119 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28120 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28124 case BFD_RELOC_ARM_PCREL_CALL
:
28125 case BFD_RELOC_THUMB_PCREL_BLX
:
28126 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28137 #endif /* OBJ_ELF */