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Remove use of alloca.
[deliverable/binutils-gdb.git] / gas / config / tc-avr.c
1 /* tc-avr.c -- Assembler code for the ATMEL AVR
2
3 Copyright (C) 1999-2016 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "elf/avr.h"
29 #include "elf32-avr.h"
30
31 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
32 struct avr_property_record_link
33 {
34 struct avr_property_record record;
35 struct avr_property_record_link *next;
36 };
37
38 struct avr_opcodes_s
39 {
40 const char * name;
41 const char * constraints;
42 const char * opcode;
43 int insn_size; /* In words. */
44 int isa;
45 unsigned int bin_opcode;
46 };
47
48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
50
51 struct avr_opcodes_s avr_opcodes[] =
52 {
53 #include "opcode/avr.h"
54 {NULL, NULL, NULL, 0, 0, 0}
55 };
56
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "$";
60
61 const char *md_shortopts = "m:";
62 struct mcu_type_s
63 {
64 const char *name;
65 int isa;
66 int mach;
67 };
68
69 /* XXX - devices that don't seem to exist (renamed, replaced with larger
70 ones, or planned but never produced), left here for compatibility. */
71
72 static struct mcu_type_s mcu_types[] =
73 {
74 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
75 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
76 but set to AVR_ISA_AVR25 for some following version
77 of GCC (from 4.3) for backward compatibility. */
78 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
79 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
80 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
81 but set to AVR_ISA_AVR3_ALL for some following version
82 of GCC (from 4.3) for backward compatibility. */
83 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
84 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
85 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
86 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
87 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
88 but set to AVR_ISA_AVR51 for some following version
89 of GCC (from 4.3) for backward compatibility. */
90 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
91 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
92 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
93 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
94 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
95 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
96 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
97 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
98 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
99 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
100 {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
101 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
102 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
103 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
104 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
105 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
106 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
107 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
108 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
109 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
110 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
111 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
112 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
113 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
114 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
115 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
116 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
117 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
118 {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25},
119 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
120 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
121 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
122 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
123 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
124 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
125 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
126 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
127 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
128 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
129 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
130 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
131 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
132 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
133 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
134 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
135 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
136 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
137 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
138 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
139 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
140 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
141 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
142 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
143 {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25},
144 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
145 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
146 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
147 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
148 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
149 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
150 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
151 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
152 {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35},
153 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
154 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
155 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
156 {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35},
157 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
158 {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4},
159 {"atmega8a", AVR_ISA_M8, bfd_mach_avr4},
160 {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4},
161 {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4},
162 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
163 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
164 {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4},
165 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
166 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
167 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
168 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
169 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
170 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
171 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
172 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
173 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
174 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
175 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
176 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
177 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
178 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
179 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
180 {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5},
181 {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5},
182 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
183 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
184 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
185 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
186 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
187 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
188 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
189 {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5},
190 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
191 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
192 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
193 {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5},
194 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
195 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
196 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
197 {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5},
198 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
199 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
200 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
201 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
202 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
203 {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5},
204 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
205 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
206 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
207 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
208 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
209 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
210 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
211 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
212 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
213 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
214 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
215 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
216 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
217 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
218 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
219 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
220 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
221 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
222 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
223 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
224 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
225 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
226 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
227 {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5},
228 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
229 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
230 {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5},
231 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
232 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
233 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
234 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
235 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
236 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
237 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
238 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
239 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
240 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
241 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
242 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
243 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
244 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
245 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
246 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
247 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
248 {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
249 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
250 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
251 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
252 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
253 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
254 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
255 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
256 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
257 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
258 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
259 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
260 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
261 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
262 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
263 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
264 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
265 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
266 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
267 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
268 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
269 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
270 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
271 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
272 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
273 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
274 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
275 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
276 {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51},
277 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
278 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
279 {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51},
280 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
281 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
282 {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
283 {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
284 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
285 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
286 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
287 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
288 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
289 {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
290 {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
291 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
292 {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
293 {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
294 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
295 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
296 {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
297 {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
298 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
299 {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
300 {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
301 {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
302 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
303 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
304 {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
305 {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
306 {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
307 {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
308 {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
309 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
310 {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
311 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
312 {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
313 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
314 {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
315 {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
316 {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
317 {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
318 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
319 {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
320 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
321 {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
322 {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
323 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
324 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
325 {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
326 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
327 {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
328 {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
329 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
330 {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
331 {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
332 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
333 {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
334 {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
335 {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
336 {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
337 {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
338 {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
339 {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
340 {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
341 {NULL, 0, 0}
342 };
343
344
345 /* Current MCU type. */
346 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
347 static struct mcu_type_s specified_mcu;
348 static struct mcu_type_s * avr_mcu = & default_mcu;
349
350 /* AVR target-specific switches. */
351 struct avr_opt_s
352 {
353 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
354 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
355 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
356 int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not)
357 relocations for linker relaxation. */
358 };
359
360 static struct avr_opt_s avr_opt = { 0, 0, 0, 0 };
361
362 const char EXP_CHARS[] = "eE";
363 const char FLT_CHARS[] = "dD";
364
365 static void avr_set_arch (int);
366
367 /* The target specific pseudo-ops which we support. */
368 const pseudo_typeS md_pseudo_table[] =
369 {
370 {"arch", avr_set_arch, 0},
371 { NULL, NULL, 0}
372 };
373
374 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
375
376 #define EXP_MOD_NAME(i) exp_mod[i].name
377 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
378 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
379 #define HAVE_PM_P(i) exp_mod[i].have_pm
380
381 struct exp_mod_s
382 {
383 const char * name;
384 bfd_reloc_code_real_type reloc;
385 bfd_reloc_code_real_type neg_reloc;
386 int have_pm;
387 };
388
389 static struct exp_mod_s exp_mod[] =
390 {
391 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
392 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
393 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
394 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
395 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
396 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
397 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
398 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
399 };
400
401 /* A union used to store indicies into the exp_mod[] array
402 in a hash table which expects void * data types. */
403 typedef union
404 {
405 void * ptr;
406 int index;
407 } mod_index;
408
409 /* Opcode hash table. */
410 static struct hash_control *avr_hash;
411
412 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
413 static struct hash_control *avr_mod_hash;
414
415 #define OPTION_MMCU 'm'
416 enum options
417 {
418 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
419 OPTION_NO_SKIP_BUG,
420 OPTION_NO_WRAP,
421 OPTION_ISA_RMW,
422 OPTION_LINK_RELAX,
423 OPTION_NO_LINK_RELAX
424 };
425
426 struct option md_longopts[] =
427 {
428 { "mmcu", required_argument, NULL, OPTION_MMCU },
429 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
430 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
431 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
432 { "mrmw", no_argument, NULL, OPTION_ISA_RMW },
433 { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX },
434 { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX },
435 { NULL, no_argument, NULL, 0 }
436 };
437
438 size_t md_longopts_size = sizeof (md_longopts);
439
440 /* Display nicely formatted list of known MCU names. */
441
442 static void
443 show_mcu_list (FILE *stream)
444 {
445 int i, x;
446
447 fprintf (stream, _("Known MCU names:"));
448 x = 1000;
449
450 for (i = 0; mcu_types[i].name; i++)
451 {
452 int len = strlen (mcu_types[i].name);
453
454 x += len + 1;
455
456 if (x < 75)
457 fprintf (stream, " %s", mcu_types[i].name);
458 else
459 {
460 fprintf (stream, "\n %s", mcu_types[i].name);
461 x = len + 2;
462 }
463 }
464
465 fprintf (stream, "\n");
466 }
467
468 static inline char *
469 skip_space (char *s)
470 {
471 while (*s == ' ' || *s == '\t')
472 ++s;
473 return s;
474 }
475
476 /* Extract one word from FROM and copy it to TO. */
477
478 static char *
479 extract_word (char *from, char *to, int limit)
480 {
481 char *op_end;
482 int size = 0;
483
484 /* Drop leading whitespace. */
485 from = skip_space (from);
486 *to = 0;
487
488 /* Find the op code end. */
489 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
490 {
491 to[size++] = *op_end++;
492 if (size + 1 >= limit)
493 break;
494 }
495
496 to[size] = 0;
497 return op_end;
498 }
499
500 int
501 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
502 asection *seg ATTRIBUTE_UNUSED)
503 {
504 abort ();
505 return 0;
506 }
507
508 void
509 md_show_usage (FILE *stream)
510 {
511 fprintf (stream,
512 _("AVR Assembler options:\n"
513 " -mmcu=[avr-name] select microcontroller variant\n"
514 " [avr-name] can be:\n"
515 " avr1 - classic AVR core without data RAM\n"
516 " avr2 - classic AVR core with up to 8K program memory\n"
517 " avr25 - classic AVR core with up to 8K program memory\n"
518 " plus the MOVW instruction\n"
519 " avr3 - classic AVR core with up to 64K program memory\n"
520 " avr31 - classic AVR core with up to 128K program memory\n"
521 " avr35 - classic AVR core with up to 64K program memory\n"
522 " plus the MOVW instruction\n"
523 " avr4 - enhanced AVR core with up to 8K program memory\n"
524 " avr5 - enhanced AVR core with up to 64K program memory\n"
525 " avr51 - enhanced AVR core with up to 128K program memory\n"
526 " avr6 - enhanced AVR core with up to 256K program memory\n"
527 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
528 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
529 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
530 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
531 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
532 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
533 " avrtiny - AVR Tiny core with 16 gp registers\n"));
534 fprintf (stream,
535 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
536 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
537 " (default for avr4, avr5)\n"
538 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
539 " (default for avr3, avr5)\n"
540 " -mrmw accept Read-Modify-Write instructions\n"
541 " -mlink-relax generate relocations for linker relaxation (default)\n"
542 " -mno-link-relax don't generate relocations for linker relaxation.\n"
543 ));
544 show_mcu_list (stream);
545 }
546
547 static void
548 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
549 {
550 char str[20];
551
552 input_line_pointer = extract_word (input_line_pointer, str, 20);
553 md_parse_option (OPTION_MMCU, str);
554 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
555 }
556
557 int
558 md_parse_option (int c, char *arg)
559 {
560 switch (c)
561 {
562 case OPTION_MMCU:
563 {
564 int i;
565 char *s = xmalloc (strlen (arg) + 1);
566
567 {
568 char *t = s;
569 char *arg1 = arg;
570
571 do
572 *t = TOLOWER (*arg1++);
573 while (*t++);
574 }
575
576 for (i = 0; mcu_types[i].name; ++i)
577 if (strcmp (mcu_types[i].name, s) == 0)
578 break;
579
580 free (s);
581 if (!mcu_types[i].name)
582 {
583 show_mcu_list (stderr);
584 as_fatal (_("unknown MCU: %s\n"), arg);
585 }
586
587 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
588 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
589 as .arch ... in the asm output at the same time. */
590 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
591 {
592 specified_mcu.name = mcu_types[i].name;
593 specified_mcu.isa |= mcu_types[i].isa;
594 specified_mcu.mach = mcu_types[i].mach;
595 avr_mcu = &specified_mcu;
596 }
597 else
598 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
599 avr_mcu->name, mcu_types[i].name);
600 return 1;
601 }
602 case OPTION_ALL_OPCODES:
603 avr_opt.all_opcodes = 1;
604 return 1;
605 case OPTION_NO_SKIP_BUG:
606 avr_opt.no_skip_bug = 1;
607 return 1;
608 case OPTION_NO_WRAP:
609 avr_opt.no_wrap = 1;
610 return 1;
611 case OPTION_ISA_RMW:
612 specified_mcu.isa |= AVR_ISA_RMW;
613 return 1;
614 case OPTION_LINK_RELAX:
615 avr_opt.no_link_relax = 0;
616 return 1;
617 case OPTION_NO_LINK_RELAX:
618 avr_opt.no_link_relax = 1;
619 return 1;
620 }
621
622 return 0;
623 }
624
625 symbolS *
626 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
627 {
628 return NULL;
629 }
630
631 char *
632 md_atof (int type, char *litP, int *sizeP)
633 {
634 return ieee_md_atof (type, litP, sizeP, FALSE);
635 }
636
637 void
638 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
639 asection *sec ATTRIBUTE_UNUSED,
640 fragS *fragP ATTRIBUTE_UNUSED)
641 {
642 abort ();
643 }
644
645 void
646 md_begin (void)
647 {
648 unsigned int i;
649 struct avr_opcodes_s *opcode;
650
651 avr_hash = hash_new ();
652
653 /* Insert unique names into hash table. This hash table then provides a
654 quick index to the first opcode with a particular name in the opcode
655 table. */
656 for (opcode = avr_opcodes; opcode->name; opcode++)
657 hash_insert (avr_hash, opcode->name, (char *) opcode);
658
659 avr_mod_hash = hash_new ();
660
661 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
662 {
663 mod_index m;
664
665 m.index = i + 10;
666 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
667 }
668
669 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
670 linkrelax = !avr_opt.no_link_relax;
671 }
672
673 /* Resolve STR as a constant expression and return the result.
674 If result greater than MAX then error. */
675
676 static unsigned int
677 avr_get_constant (char *str, int max)
678 {
679 expressionS ex;
680
681 str = skip_space (str);
682 input_line_pointer = str;
683 expression (& ex);
684
685 if (ex.X_op != O_constant)
686 as_bad (_("constant value required"));
687
688 if (ex.X_add_number > max || ex.X_add_number < 0)
689 as_bad (_("number must be positive and less than %d"), max + 1);
690
691 return ex.X_add_number;
692 }
693
694 /* Parse for ldd/std offset. */
695
696 static void
697 avr_offset_expression (expressionS *exp)
698 {
699 char *str = input_line_pointer;
700 char *tmp;
701 char op[8];
702
703 tmp = str;
704 str = extract_word (str, op, sizeof (op));
705
706 input_line_pointer = tmp;
707 expression (exp);
708
709 /* Warn about expressions that fail to use lo8 (). */
710 if (exp->X_op == O_constant)
711 {
712 int x = exp->X_add_number;
713
714 if (x < -255 || x > 255)
715 as_warn (_("constant out of 8-bit range: %d"), x);
716 }
717 }
718
719 /* Parse ordinary expression. */
720
721 static char *
722 parse_exp (char *s, expressionS *op)
723 {
724 input_line_pointer = s;
725 expression (op);
726 if (op->X_op == O_absent)
727 as_bad (_("missing operand"));
728 return input_line_pointer;
729 }
730
731 /* Parse special expressions (needed for LDI command):
732 xx8 (address)
733 xx8 (-address)
734 pm_xx8 (address)
735 pm_xx8 (-address)
736 where xx is: hh, hi, lo. */
737
738 static bfd_reloc_code_real_type
739 avr_ldi_expression (expressionS *exp)
740 {
741 char *str = input_line_pointer;
742 char *tmp;
743 char op[8];
744 int mod;
745 int linker_stubs_should_be_generated = 0;
746
747 tmp = str;
748
749 str = extract_word (str, op, sizeof (op));
750
751 if (op[0])
752 {
753 mod_index m;
754
755 m.ptr = hash_find (avr_mod_hash, op);
756 mod = m.index;
757
758 if (mod)
759 {
760 int closes = 0;
761
762 mod -= 10;
763 str = skip_space (str);
764
765 if (*str == '(')
766 {
767 bfd_reloc_code_real_type reloc_to_return;
768 int neg_p = 0;
769
770 ++str;
771
772 if (strncmp ("pm(", str, 3) == 0
773 || strncmp ("gs(",str,3) == 0
774 || strncmp ("-(gs(",str,5) == 0
775 || strncmp ("-(pm(", str, 5) == 0)
776 {
777 if (HAVE_PM_P (mod))
778 {
779 ++mod;
780 ++closes;
781 }
782 else
783 as_bad (_("illegal expression"));
784
785 if (str[0] == 'g' || str[2] == 'g')
786 linker_stubs_should_be_generated = 1;
787
788 if (*str == '-')
789 {
790 neg_p = 1;
791 ++closes;
792 str += 5;
793 }
794 else
795 str += 3;
796 }
797
798 if (*str == '-' && *(str + 1) == '(')
799 {
800 neg_p ^= 1;
801 ++closes;
802 str += 2;
803 }
804
805 input_line_pointer = str;
806 expression (exp);
807
808 do
809 {
810 if (*input_line_pointer != ')')
811 {
812 as_bad (_("`)' required"));
813 break;
814 }
815 input_line_pointer++;
816 }
817 while (closes--);
818
819 reloc_to_return =
820 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
821 if (linker_stubs_should_be_generated)
822 {
823 switch (reloc_to_return)
824 {
825 case BFD_RELOC_AVR_LO8_LDI_PM:
826 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
827 break;
828 case BFD_RELOC_AVR_HI8_LDI_PM:
829 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
830 break;
831
832 default:
833 /* PR 5523: Do not generate a warning here,
834 legitimate code can trigger this case. */
835 break;
836 }
837 }
838 return reloc_to_return;
839 }
840 }
841 }
842
843 input_line_pointer = tmp;
844 expression (exp);
845
846 /* Warn about expressions that fail to use lo8 (). */
847 if (exp->X_op == O_constant)
848 {
849 int x = exp->X_add_number;
850
851 if (x < -255 || x > 255)
852 as_warn (_("constant out of 8-bit range: %d"), x);
853 }
854
855 return BFD_RELOC_AVR_LDI;
856 }
857
858 /* Parse one instruction operand.
859 Return operand bitmask. Also fixups can be generated. */
860
861 static unsigned int
862 avr_operand (struct avr_opcodes_s *opcode,
863 int where,
864 const char *op,
865 char **line)
866 {
867 expressionS op_expr;
868 unsigned int op_mask = 0;
869 char *str = skip_space (*line);
870
871 switch (*op)
872 {
873 /* Any register operand. */
874 case 'w':
875 case 'd':
876 case 'r':
877 case 'a':
878 case 'v':
879 {
880 char * old_str = str;
881 char *lower;
882 char r_name[20];
883
884 str = extract_word (str, r_name, sizeof (r_name));
885 for (lower = r_name; *lower; ++lower)
886 {
887 if (*lower >= 'A' && *lower <= 'Z')
888 *lower += 'a' - 'A';
889 }
890
891 if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0)
892 /* Single-digit register number, ie r0-r9. */
893 op_mask = r_name[1] - '0';
894 else if (r_name[0] == 'r' && ISDIGIT (r_name[1])
895 && ISDIGIT (r_name[2]) && r_name[3] == 0)
896 /* Double-digit register number, ie r10 - r32. */
897 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
898 else if (r_name[0] >= 'x' && r_name[0] <= 'z'
899 && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0)
900 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
901 op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26;
902 else if ((*op == 'v' || *op == 'w')
903 && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0)
904 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
905 op_mask = (r_name[0] - 'x') * 2 + 26;
906 else
907 {
908 /* Numeric or symbolic constant register number. */
909 op_mask = avr_get_constant (old_str, 31);
910 str = input_line_pointer;
911 }
912 }
913
914 if (avr_mcu->mach == bfd_mach_avrtiny)
915 {
916 if (op_mask < 16 || op_mask > 31)
917 {
918 as_bad (_("register name or number from 16 to 31 required"));
919 break;
920 }
921 }
922 else if (op_mask > 31)
923 {
924 as_bad (_("register name or number from 0 to 31 required"));
925 break;
926 }
927
928 switch (*op)
929 {
930 case 'a':
931 if (op_mask < 16 || op_mask > 23)
932 as_bad (_("register r16-r23 required"));
933 op_mask -= 16;
934 break;
935
936 case 'd':
937 if (op_mask < 16)
938 as_bad (_("register number above 15 required"));
939 op_mask -= 16;
940 break;
941
942 case 'v':
943 if (op_mask & 1)
944 as_bad (_("even register number required"));
945 op_mask >>= 1;
946 break;
947
948 case 'w':
949 if ((op_mask & 1) || op_mask < 24)
950 as_bad (_("register r24, r26, r28 or r30 required"));
951 op_mask = (op_mask - 24) >> 1;
952 break;
953 }
954 break;
955
956 case 'e':
957 {
958 char c;
959
960 if (*str == '-')
961 {
962 str = skip_space (str + 1);
963 op_mask = 0x1002;
964 }
965 c = TOLOWER (*str);
966 if (c == 'x')
967 op_mask |= 0x100c;
968 else if (c == 'y')
969 op_mask |= 0x8;
970 else if (c != 'z')
971 as_bad (_("pointer register (X, Y or Z) required"));
972
973 str = skip_space (str + 1);
974 if (*str == '+')
975 {
976 ++str;
977 if (op_mask & 2)
978 as_bad (_("cannot both predecrement and postincrement"));
979 op_mask |= 0x1001;
980 }
981
982 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
983 registers, no predecrement, no postincrement. */
984 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
985 && !(avr_mcu->isa & AVR_ISA_SRAM))
986 as_bad (_("addressing mode not supported"));
987 }
988 break;
989
990 case 'z':
991 if (*str == '-')
992 as_bad (_("can't predecrement"));
993
994 if (! (*str == 'z' || *str == 'Z'))
995 as_bad (_("pointer register Z required"));
996
997 str = skip_space (str + 1);
998
999 if (*str == '+')
1000 {
1001 ++str;
1002 const char *s;
1003 for (s = opcode->opcode; *s; ++s)
1004 {
1005 if (*s == '+')
1006 op_mask |= (1 << (15 - (s - opcode->opcode)));
1007 }
1008 }
1009
1010 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1011 if (!avr_opt.all_opcodes
1012 && (op_mask & 0x0001)
1013 && !(avr_mcu->isa & AVR_ISA_MOVW))
1014 as_bad (_("postincrement not supported"));
1015 break;
1016
1017 case 'b':
1018 {
1019 char c = TOLOWER (*str++);
1020
1021 if (c == 'y')
1022 op_mask |= 0x8;
1023 else if (c != 'z')
1024 as_bad (_("pointer register (Y or Z) required"));
1025 str = skip_space (str);
1026 if (*str++ == '+')
1027 {
1028 input_line_pointer = str;
1029 avr_offset_expression (& op_expr);
1030 str = input_line_pointer;
1031 fix_new_exp (frag_now, where, 3,
1032 &op_expr, FALSE, BFD_RELOC_AVR_6);
1033 }
1034 }
1035 break;
1036
1037 case 'h':
1038 str = parse_exp (str, &op_expr);
1039 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1040 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
1041 break;
1042
1043 case 'L':
1044 str = parse_exp (str, &op_expr);
1045 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1046 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
1047 break;
1048
1049 case 'l':
1050 str = parse_exp (str, &op_expr);
1051 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1052 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
1053 break;
1054
1055 case 'i':
1056 str = parse_exp (str, &op_expr);
1057 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
1058 &op_expr, FALSE, BFD_RELOC_16);
1059 break;
1060
1061 case 'j':
1062 str = parse_exp (str, &op_expr);
1063 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1064 &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
1065 break;
1066
1067 case 'M':
1068 {
1069 bfd_reloc_code_real_type r_type;
1070
1071 input_line_pointer = str;
1072 r_type = avr_ldi_expression (&op_expr);
1073 str = input_line_pointer;
1074 fix_new_exp (frag_now, where, 3,
1075 &op_expr, FALSE, r_type);
1076 }
1077 break;
1078
1079 case 'n':
1080 {
1081 unsigned int x;
1082
1083 x = ~avr_get_constant (str, 255);
1084 str = input_line_pointer;
1085 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
1086 }
1087 break;
1088
1089 case 'K':
1090 input_line_pointer = str;
1091 avr_offset_expression (& op_expr);
1092 str = input_line_pointer;
1093 fix_new_exp (frag_now, where, 3,
1094 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
1095 break;
1096
1097 case 'S':
1098 case 's':
1099 {
1100 unsigned int x;
1101
1102 x = avr_get_constant (str, 7);
1103 str = input_line_pointer;
1104 if (*op == 'S')
1105 x <<= 4;
1106 op_mask |= x;
1107 }
1108 break;
1109
1110 case 'P':
1111 str = parse_exp (str, &op_expr);
1112 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1113 &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
1114 break;
1115
1116 case 'p':
1117 str = parse_exp (str, &op_expr);
1118 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1119 &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
1120 break;
1121
1122 case 'E':
1123 {
1124 unsigned int x;
1125
1126 x = avr_get_constant (str, 15);
1127 str = input_line_pointer;
1128 op_mask |= (x << 4);
1129 }
1130 break;
1131
1132 case '?':
1133 break;
1134
1135 default:
1136 as_bad (_("unknown constraint `%c'"), *op);
1137 }
1138
1139 *line = str;
1140 return op_mask;
1141 }
1142
1143 /* Parse instruction operands.
1144 Return binary opcode. */
1145
1146 static unsigned int
1147 avr_operands (struct avr_opcodes_s *opcode, char **line)
1148 {
1149 const char *op = opcode->constraints;
1150 unsigned int bin = opcode->bin_opcode;
1151 char *frag = frag_more (opcode->insn_size * 2);
1152 char *str = *line;
1153 int where = frag - frag_now->fr_literal;
1154 static unsigned int prev = 0; /* Previous opcode. */
1155
1156 /* Opcode have operands. */
1157 if (*op)
1158 {
1159 unsigned int reg1 = 0;
1160 unsigned int reg2 = 0;
1161 int reg1_present = 0;
1162 int reg2_present = 0;
1163
1164 /* Parse first operand. */
1165 if (REGISTER_P (*op))
1166 reg1_present = 1;
1167 reg1 = avr_operand (opcode, where, op, &str);
1168 ++op;
1169
1170 /* Parse second operand. */
1171 if (*op)
1172 {
1173 if (*op == ',')
1174 ++op;
1175
1176 if (*op == '=')
1177 {
1178 reg2 = reg1;
1179 reg2_present = 1;
1180 }
1181 else
1182 {
1183 if (REGISTER_P (*op))
1184 reg2_present = 1;
1185
1186 str = skip_space (str);
1187 if (*str++ != ',')
1188 as_bad (_("`,' required"));
1189 str = skip_space (str);
1190
1191 reg2 = avr_operand (opcode, where, op, &str);
1192 }
1193
1194 if (reg1_present && reg2_present)
1195 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1196 else if (reg2_present)
1197 reg2 <<= 4;
1198 }
1199 if (reg1_present)
1200 reg1 <<= 4;
1201 bin |= reg1 | reg2;
1202 }
1203
1204 /* Detect undefined combinations (like ld r31,Z+). */
1205 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1206 as_warn (_("undefined combination of operands"));
1207
1208 if (opcode->insn_size == 2)
1209 {
1210 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1211 (AVR core bug, fixed in the newer devices). */
1212 if (!(avr_opt.no_skip_bug ||
1213 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1214 && AVR_SKIP_P (prev))
1215 as_warn (_("skipping two-word instruction"));
1216
1217 bfd_putl32 ((bfd_vma) bin, frag);
1218 }
1219 else
1220 bfd_putl16 ((bfd_vma) bin, frag);
1221
1222 prev = bin;
1223 *line = str;
1224 return bin;
1225 }
1226
1227 /* GAS will call this function for each section at the end of the assembly,
1228 to permit the CPU backend to adjust the alignment of a section. */
1229
1230 valueT
1231 md_section_align (asection *seg, valueT addr)
1232 {
1233 int align = bfd_get_section_alignment (stdoutput, seg);
1234 return ((addr + (1 << align) - 1) & (-1UL << align));
1235 }
1236
1237 /* If you define this macro, it should return the offset between the
1238 address of a PC relative fixup and the position from which the PC
1239 relative adjustment should be made. On many processors, the base
1240 of a PC relative instruction is the next instruction, so this
1241 macro would return the length of an instruction. */
1242
1243 long
1244 md_pcrel_from_section (fixS *fixp, segT sec)
1245 {
1246 if (fixp->fx_addsy != (symbolS *) NULL
1247 && (!S_IS_DEFINED (fixp->fx_addsy)
1248 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1249 return 0;
1250
1251 return fixp->fx_frag->fr_address + fixp->fx_where;
1252 }
1253
1254 static bfd_boolean
1255 relaxable_section (asection *sec)
1256 {
1257 return ((sec->flags & SEC_DEBUGGING) == 0
1258 && (sec->flags & SEC_CODE) != 0
1259 && (sec->flags & SEC_ALLOC) != 0);
1260 }
1261
1262 /* Does whatever the xtensa port does. */
1263 int
1264 avr_validate_fix_sub (fixS *fix)
1265 {
1266 segT add_symbol_segment, sub_symbol_segment;
1267
1268 /* The difference of two symbols should be resolved by the assembler when
1269 linkrelax is not set. If the linker may relax the section containing
1270 the symbols, then an Xtensa DIFF relocation must be generated so that
1271 the linker knows to adjust the difference value. */
1272 if (!linkrelax || fix->fx_addsy == NULL)
1273 return 0;
1274
1275 /* Make sure both symbols are in the same segment, and that segment is
1276 "normal" and relaxable. If the segment is not "normal", then the
1277 fix is not valid. If the segment is not "relaxable", then the fix
1278 should have been handled earlier. */
1279 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
1280 if (! SEG_NORMAL (add_symbol_segment) ||
1281 ! relaxable_section (add_symbol_segment))
1282 return 0;
1283
1284 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
1285 return (sub_symbol_segment == add_symbol_segment);
1286 }
1287
1288 /* TC_FORCE_RELOCATION hook */
1289
1290 /* If linkrelax is turned on, and the symbol to relocate
1291 against is in a relaxable segment, don't compute the value -
1292 generate a relocation instead. */
1293 int
1294 avr_force_relocation (fixS *fix)
1295 {
1296 if (linkrelax && fix->fx_addsy
1297 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
1298 return 1;
1299
1300 return generic_force_reloc (fix);
1301 }
1302
1303 /* GAS will call this for each fixup. It should store the correct
1304 value in the object file. */
1305
1306 void
1307 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1308 {
1309 unsigned char *where;
1310 unsigned long insn;
1311 long value = *valP;
1312
1313 if (fixP->fx_addsy == (symbolS *) NULL)
1314 fixP->fx_done = 1;
1315
1316 else if (fixP->fx_pcrel)
1317 {
1318 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1319
1320 if (s == seg || s == absolute_section)
1321 {
1322 value += S_GET_VALUE (fixP->fx_addsy);
1323 fixP->fx_done = 1;
1324 }
1325 }
1326 else if (linkrelax && fixP->fx_subsy)
1327 {
1328 /* For a subtraction relocation expression, generate one
1329 of the DIFF relocs, with the value being the difference.
1330 Note that a sym1 - sym2 expression is adjusted into a
1331 section_start_sym + sym4_offset_from_section_start - sym1
1332 expression. fixP->fx_addsy holds the section start symbol,
1333 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1334 holds sym1. Calculate the current difference and write value,
1335 but leave fx_offset as is - during relaxation,
1336 fx_offset - value gives sym1's value. */
1337
1338 switch (fixP->fx_r_type)
1339 {
1340 case BFD_RELOC_8:
1341 fixP->fx_r_type = BFD_RELOC_AVR_DIFF8;
1342 break;
1343 case BFD_RELOC_16:
1344 fixP->fx_r_type = BFD_RELOC_AVR_DIFF16;
1345 break;
1346 case BFD_RELOC_32:
1347 fixP->fx_r_type = BFD_RELOC_AVR_DIFF32;
1348 break;
1349 default:
1350 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1351 break;
1352 }
1353
1354 value = S_GET_VALUE (fixP->fx_addsy) +
1355 fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
1356 *valP = value;
1357
1358 fixP->fx_subsy = NULL;
1359 }
1360 /* We don't actually support subtracting a symbol. */
1361 if (fixP->fx_subsy != (symbolS *) NULL)
1362 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1363
1364 /* For the DIFF relocs, write the value into the object file while still
1365 keeping fx_done FALSE, as both the difference (recorded in the object file)
1366 and the sym offset (part of fixP) are needed at link relax time. */
1367 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1368 switch (fixP->fx_r_type)
1369 {
1370 default:
1371 fixP->fx_no_overflow = 1;
1372 break;
1373 case BFD_RELOC_AVR_7_PCREL:
1374 case BFD_RELOC_AVR_13_PCREL:
1375 case BFD_RELOC_32:
1376 case BFD_RELOC_16:
1377 break;
1378 case BFD_RELOC_AVR_DIFF8:
1379 *where = value;
1380 break;
1381 case BFD_RELOC_AVR_DIFF16:
1382 bfd_putl16 ((bfd_vma) value, where);
1383 break;
1384 case BFD_RELOC_AVR_DIFF32:
1385 bfd_putl32 ((bfd_vma) value, where);
1386 break;
1387 case BFD_RELOC_AVR_CALL:
1388 break;
1389 }
1390
1391 if (fixP->fx_done)
1392 {
1393 /* Fetch the instruction, insert the fully resolved operand
1394 value, and stuff the instruction back again. */
1395 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1396 insn = bfd_getl16 (where);
1397
1398 switch (fixP->fx_r_type)
1399 {
1400 case BFD_RELOC_AVR_7_PCREL:
1401 if (value & 1)
1402 as_bad_where (fixP->fx_file, fixP->fx_line,
1403 _("odd address operand: %ld"), value);
1404
1405 /* Instruction addresses are always right-shifted by 1. */
1406 value >>= 1;
1407 --value; /* Correct PC. */
1408
1409 if (value < -64 || value > 63)
1410 as_bad_where (fixP->fx_file, fixP->fx_line,
1411 _("operand out of range: %ld"), value);
1412 value = (value << 3) & 0x3f8;
1413 bfd_putl16 ((bfd_vma) (value | insn), where);
1414 break;
1415
1416 case BFD_RELOC_AVR_13_PCREL:
1417 if (value & 1)
1418 as_bad_where (fixP->fx_file, fixP->fx_line,
1419 _("odd address operand: %ld"), value);
1420
1421 /* Instruction addresses are always right-shifted by 1. */
1422 value >>= 1;
1423 --value; /* Correct PC. */
1424
1425 if (value < -2048 || value > 2047)
1426 {
1427 /* No wrap for devices with >8K of program memory. */
1428 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1429 as_bad_where (fixP->fx_file, fixP->fx_line,
1430 _("operand out of range: %ld"), value);
1431 }
1432
1433 value &= 0xfff;
1434 bfd_putl16 ((bfd_vma) (value | insn), where);
1435 break;
1436
1437 case BFD_RELOC_32:
1438 bfd_putl32 ((bfd_vma) value, where);
1439 break;
1440
1441 case BFD_RELOC_16:
1442 bfd_putl16 ((bfd_vma) value, where);
1443 break;
1444
1445 case BFD_RELOC_8:
1446 if (value > 255 || value < -128)
1447 as_warn_where (fixP->fx_file, fixP->fx_line,
1448 _("operand out of range: %ld"), value);
1449 *where = value;
1450 break;
1451
1452 case BFD_RELOC_AVR_16_PM:
1453 bfd_putl16 ((bfd_vma) (value >> 1), where);
1454 break;
1455
1456 case BFD_RELOC_AVR_LDI:
1457 if (value > 255)
1458 as_bad_where (fixP->fx_file, fixP->fx_line,
1459 _("operand out of range: %ld"), value);
1460 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1461 break;
1462
1463 case BFD_RELOC_AVR_LDS_STS_16:
1464 if ((value < 0x40) || (value > 0xBF))
1465 as_warn_where (fixP->fx_file, fixP->fx_line,
1466 _("operand out of range: 0x%lx"),
1467 (unsigned long)value);
1468 insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
1469 bfd_putl16 ((bfd_vma) insn, where);
1470 break;
1471
1472 case BFD_RELOC_AVR_6:
1473 if ((value > 63) || (value < 0))
1474 as_bad_where (fixP->fx_file, fixP->fx_line,
1475 _("operand out of range: %ld"), value);
1476 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
1477 | ((value & (1 << 5)) << 8)), where);
1478 break;
1479
1480 case BFD_RELOC_AVR_6_ADIW:
1481 if ((value > 63) || (value < 0))
1482 as_bad_where (fixP->fx_file, fixP->fx_line,
1483 _("operand out of range: %ld"), value);
1484 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1485 break;
1486
1487 case BFD_RELOC_AVR_LO8_LDI:
1488 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1489 break;
1490
1491 case BFD_RELOC_AVR_HI8_LDI:
1492 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1493 break;
1494
1495 case BFD_RELOC_AVR_MS8_LDI:
1496 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1497 break;
1498
1499 case BFD_RELOC_AVR_HH8_LDI:
1500 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1501 break;
1502
1503 case BFD_RELOC_AVR_LO8_LDI_NEG:
1504 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1505 break;
1506
1507 case BFD_RELOC_AVR_HI8_LDI_NEG:
1508 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1509 break;
1510
1511 case BFD_RELOC_AVR_MS8_LDI_NEG:
1512 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1513 break;
1514
1515 case BFD_RELOC_AVR_HH8_LDI_NEG:
1516 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1517 break;
1518
1519 case BFD_RELOC_AVR_LO8_LDI_PM:
1520 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1521 break;
1522
1523 case BFD_RELOC_AVR_HI8_LDI_PM:
1524 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1525 break;
1526
1527 case BFD_RELOC_AVR_HH8_LDI_PM:
1528 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1529 break;
1530
1531 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1532 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1533 break;
1534
1535 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1536 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1537 break;
1538
1539 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1540 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1541 break;
1542
1543 case BFD_RELOC_AVR_CALL:
1544 {
1545 unsigned long x;
1546
1547 x = bfd_getl16 (where);
1548 if (value & 1)
1549 as_bad_where (fixP->fx_file, fixP->fx_line,
1550 _("odd address operand: %ld"), value);
1551 value >>= 1;
1552 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1553 bfd_putl16 ((bfd_vma) x, where);
1554 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1555 }
1556 break;
1557
1558 case BFD_RELOC_AVR_8_LO:
1559 *where = 0xff & value;
1560 break;
1561
1562 case BFD_RELOC_AVR_8_HI:
1563 *where = 0xff & (value >> 8);
1564 break;
1565
1566 case BFD_RELOC_AVR_8_HLO:
1567 *where = 0xff & (value >> 16);
1568 break;
1569
1570 default:
1571 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1572 fixP->fx_line, fixP->fx_r_type);
1573 break;
1574
1575 case BFD_RELOC_AVR_PORT6:
1576 if (value > 63)
1577 as_bad_where (fixP->fx_file, fixP->fx_line,
1578 _("operand out of range: %ld"), value);
1579 bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where);
1580 break;
1581
1582 case BFD_RELOC_AVR_PORT5:
1583 if (value > 31)
1584 as_bad_where (fixP->fx_file, fixP->fx_line,
1585 _("operand out of range: %ld"), value);
1586 bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where);
1587 break;
1588 }
1589 }
1590 else
1591 {
1592 switch ((int) fixP->fx_r_type)
1593 {
1594 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1595 case -BFD_RELOC_AVR_HI8_LDI:
1596 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1597 case -BFD_RELOC_AVR_LO8_LDI:
1598 as_bad_where (fixP->fx_file, fixP->fx_line,
1599 _("only constant expression allowed"));
1600 fixP->fx_done = 1;
1601 break;
1602 default:
1603 break;
1604 }
1605 }
1606 }
1607
1608 /* GAS will call this to generate a reloc, passing the resulting reloc
1609 to `bfd_install_relocation'. This currently works poorly, as
1610 `bfd_install_relocation' often does the wrong thing, and instances of
1611 `tc_gen_reloc' have been written to work around the problems, which
1612 in turns makes it difficult to fix `bfd_install_relocation'. */
1613
1614 /* If while processing a fixup, a reloc really needs to be created
1615 then it is done here. */
1616
1617 arelent *
1618 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1619 fixS *fixp)
1620 {
1621 arelent *reloc;
1622 bfd_reloc_code_real_type code = fixp->fx_r_type;
1623
1624 if (fixp->fx_subsy != NULL)
1625 {
1626 as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
1627 return NULL;
1628 }
1629
1630 reloc = xmalloc (sizeof (arelent));
1631
1632 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1633 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1634
1635 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1636
1637 if ((fixp->fx_r_type == BFD_RELOC_32) && (fixp->fx_pcrel))
1638 {
1639 if (seg->use_rela_p)
1640 fixp->fx_offset -= md_pcrel_from_section (fixp, seg);
1641 else
1642 fixp->fx_offset = reloc->address;
1643
1644 code = BFD_RELOC_32_PCREL;
1645 }
1646
1647 reloc->addend = fixp->fx_offset;
1648
1649 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1650
1651 if (reloc->howto == (reloc_howto_type *) NULL)
1652 {
1653 as_bad_where (fixp->fx_file, fixp->fx_line,
1654 _("reloc %d not supported by object file format"),
1655 (int) fixp->fx_r_type);
1656 return NULL;
1657 }
1658
1659 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1660 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1661 reloc->address = fixp->fx_offset;
1662
1663
1664 return reloc;
1665 }
1666
1667 void
1668 md_assemble (char *str)
1669 {
1670 struct avr_opcodes_s *opcode;
1671 char op[11];
1672
1673 str = skip_space (extract_word (str, op, sizeof (op)));
1674
1675 if (!op[0])
1676 as_bad (_("can't find opcode "));
1677
1678 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1679
1680 if (opcode && !avr_opt.all_opcodes)
1681 {
1682 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1683 specified by the user. If not look for other instructions
1684 specifications with same mnemonic who's ISA bits matches.
1685
1686 This requires include/opcode/avr.h to have the instructions with
1687 same mnenomic to be specified in sequence. */
1688
1689 while ((opcode->isa & avr_mcu->isa) != opcode->isa)
1690 {
1691 opcode++;
1692
1693 if (opcode->name && strcmp(op, opcode->name))
1694 {
1695 as_bad (_("illegal opcode %s for mcu %s"),
1696 opcode->name, avr_mcu->name);
1697 return;
1698 }
1699 }
1700 }
1701
1702 if (opcode == NULL)
1703 {
1704 as_bad (_("unknown opcode `%s'"), op);
1705 return;
1706 }
1707
1708 /* Special case for opcodes with optional operands (lpm, elpm) -
1709 version with operands exists in avr_opcodes[] in the next entry. */
1710
1711 if (*str && *opcode->constraints == '?')
1712 ++opcode;
1713
1714 dwarf2_emit_insn (0);
1715
1716 /* We used to set input_line_pointer to the result of get_operands,
1717 but that is wrong. Our caller assumes we don't change it. */
1718 {
1719 char *t = input_line_pointer;
1720
1721 avr_operands (opcode, &str);
1722 if (*skip_space (str))
1723 as_bad (_("garbage at end of line"));
1724 input_line_pointer = t;
1725 }
1726 }
1727
1728 const exp_mod_data_t exp_mod_data[] =
1729 {
1730 /* Default, must be first. */
1731 { "", 0, BFD_RELOC_16, "" },
1732 /* Divides by 2 to get word address. Generate Stub. */
1733 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1734 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1735 /* The following are used together with avr-gcc's __memx address space
1736 in order to initialize a 24-bit pointer variable with a 24-bit address.
1737 For address in flash, hlo8 will contain the flash segment if the
1738 symbol is located in flash. If the symbol is located in RAM; hlo8
1739 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1740 addresses linearize address space. */
1741 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1742 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
1743 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1744 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
1745 /* End of list. */
1746 { NULL, 0, 0, NULL }
1747 };
1748
1749 /* Parse special CONS expression: pm (expression) or alternatively
1750 gs (expression). These are used for addressing program memory. Moreover,
1751 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1752
1753 const exp_mod_data_t *
1754 avr_parse_cons_expression (expressionS *exp, int nbytes)
1755 {
1756 const exp_mod_data_t *pexp = &exp_mod_data[0];
1757 char *tmp;
1758
1759 tmp = input_line_pointer = skip_space (input_line_pointer);
1760
1761 /* The first entry of exp_mod_data[] contains an entry if no
1762 expression modifier is present. Skip it. */
1763
1764 for (pexp++; pexp->name; pexp++)
1765 {
1766 int len = strlen (pexp->name);
1767
1768 if (nbytes == pexp->nbytes
1769 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
1770 {
1771 input_line_pointer = skip_space (input_line_pointer + len);
1772
1773 if (*input_line_pointer == '(')
1774 {
1775 input_line_pointer = skip_space (input_line_pointer + 1);
1776 expression (exp);
1777
1778 if (*input_line_pointer == ')')
1779 {
1780 ++input_line_pointer;
1781 return pexp;
1782 }
1783 else
1784 {
1785 as_bad (_("`)' required"));
1786 return &exp_mod_data[0];
1787 }
1788 }
1789
1790 input_line_pointer = tmp;
1791
1792 break;
1793 }
1794 }
1795
1796 expression (exp);
1797 return &exp_mod_data[0];
1798 }
1799
1800 void
1801 avr_cons_fix_new (fragS *frag,
1802 int where,
1803 int nbytes,
1804 expressionS *exp,
1805 const exp_mod_data_t *pexp_mod_data)
1806 {
1807 int bad = 0;
1808
1809 switch (pexp_mod_data->reloc)
1810 {
1811 default:
1812 if (nbytes == 1)
1813 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
1814 else if (nbytes == 2)
1815 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
1816 else if (nbytes == 4)
1817 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
1818 else
1819 bad = 1;
1820 break;
1821
1822 case BFD_RELOC_AVR_16_PM:
1823 case BFD_RELOC_AVR_8_LO:
1824 case BFD_RELOC_AVR_8_HI:
1825 case BFD_RELOC_AVR_8_HLO:
1826 if (nbytes == pexp_mod_data->nbytes)
1827 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
1828 else
1829 bad = 1;
1830 break;
1831 }
1832
1833 if (bad)
1834 as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
1835 }
1836
1837 static bfd_boolean
1838 mcu_has_3_byte_pc (void)
1839 {
1840 int mach = avr_mcu->mach;
1841
1842 return mach == bfd_mach_avr6
1843 || mach == bfd_mach_avrxmega6
1844 || mach == bfd_mach_avrxmega7;
1845 }
1846
1847 void
1848 tc_cfi_frame_initial_instructions (void)
1849 {
1850 /* AVR6 pushes 3 bytes for calls. */
1851 int return_size = (mcu_has_3_byte_pc () ? 3 : 2);
1852
1853 /* The CFA is the caller's stack location before the call insn. */
1854 /* Note that the stack pointer is dwarf register number 32. */
1855 cfi_add_CFA_def_cfa (32, return_size);
1856
1857 /* Note that AVR consistently uses post-decrement, which means that things
1858 do not line up the same way as for targers that use pre-decrement. */
1859 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
1860 }
1861
1862 bfd_boolean
1863 avr_allow_local_subtract (expressionS * left,
1864 expressionS * right,
1865 segT section)
1866 {
1867 /* If we are not in relaxation mode, subtraction is OK. */
1868 if (!linkrelax)
1869 return TRUE;
1870
1871 /* If the symbols are not in a code section then they are OK. */
1872 if ((section->flags & SEC_CODE) == 0)
1873 return TRUE;
1874
1875 if (left->X_add_symbol == right->X_add_symbol)
1876 return TRUE;
1877
1878 /* We have to assume that there may be instructions between the
1879 two symbols and that relaxation may increase the distance between
1880 them. */
1881 return FALSE;
1882 }
1883
1884 void
1885 avr_elf_final_processing (void)
1886 {
1887 if (linkrelax)
1888 elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED;
1889 }
1890
1891 /* Write out the header of a .avr.prop section into the area pointed to by
1892 DATA. The RECORD_COUNT will be placed in the header as the number of
1893 records that are to follow.
1894 The area DATA must be big enough the receive the header, which is
1895 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
1896
1897 static char *
1898 avr_output_property_section_header (char *data,
1899 unsigned int record_count)
1900 {
1901 char *orig_data = data;
1902
1903 md_number_to_chars (data, AVR_PROPERTY_RECORDS_VERSION, 1);
1904 data++;
1905 /* There's space for a single byte flags field, but right now there's
1906 nothing to go in here, so just set the value to zero. */
1907 md_number_to_chars (data, 0, 1);
1908 data++;
1909 md_number_to_chars (data, record_count, 2);
1910 data+=2;
1911
1912 gas_assert (data - orig_data == AVR_PROPERTY_SECTION_HEADER_SIZE);
1913
1914 return data;
1915 }
1916
1917 /* Return the number of bytes required to store RECORD into the .avr.prop
1918 section. The size returned is the compressed size that corresponds to
1919 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
1920
1921 static int
1922 avr_record_size (const struct avr_property_record *record)
1923 {
1924 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
1925 identifier. */
1926 int size = 5;
1927
1928 switch (record->type)
1929 {
1930 case RECORD_ORG:
1931 size += 0; /* No extra information. */
1932 break;
1933
1934 case RECORD_ORG_AND_FILL:
1935 size += 4; /* A 4-byte fill value. */
1936 break;
1937
1938 case RECORD_ALIGN:
1939 size += 4; /* A 4-byte alignment value. */
1940 break;
1941
1942 case RECORD_ALIGN_AND_FILL:
1943 size += 8; /* A 4-byte alignment, and 4-byte fill value. */
1944 break;
1945
1946 default:
1947 as_fatal (_("unknown record type %d (in %s)"),
1948 record->type, __PRETTY_FUNCTION__);
1949 }
1950
1951 return size;
1952 }
1953
1954 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
1955 to hold all of the .avr.prop content, FRAG_PTR points to the next
1956 writable location. The data area must be big enough to hold all of the
1957 records. The size of the data written out for this RECORD must match
1958 the size from AVR_RECORD_SIZE. */
1959
1960 static char *
1961 avr_output_property_record (char * const frag_base, char *frag_ptr,
1962 const struct avr_property_record *record)
1963 {
1964 fixS *fix;
1965 int where;
1966 char *init_frag_ptr = frag_ptr;
1967
1968 where = frag_ptr - frag_base;
1969 fix = fix_new (frag_now, where, 4,
1970 section_symbol (record->section),
1971 record->offset, FALSE, BFD_RELOC_32);
1972 fix->fx_file = "<internal>";
1973 fix->fx_line = 0;
1974 frag_ptr += 4;
1975
1976 md_number_to_chars (frag_ptr, (bfd_byte) record->type, 1);
1977 frag_ptr += 1;
1978
1979 /* Write out the rest of the data. */
1980 switch (record->type)
1981 {
1982 case RECORD_ORG:
1983 break;
1984
1985 case RECORD_ORG_AND_FILL:
1986 md_number_to_chars (frag_ptr, record->data.org.fill, 4);
1987 frag_ptr += 4;
1988 break;
1989
1990 case RECORD_ALIGN:
1991 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1992 frag_ptr += 4;
1993 break;
1994
1995 case RECORD_ALIGN_AND_FILL:
1996 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1997 md_number_to_chars (frag_ptr + 4, record->data.align.fill, 4);
1998 frag_ptr += 8;
1999 break;
2000
2001 default:
2002 as_fatal (_("unknown record type %d (in %s)"),
2003 record->type, __PRETTY_FUNCTION__);
2004 }
2005
2006 gas_assert (frag_ptr - init_frag_ptr == avr_record_size (record));
2007
2008 return frag_ptr;
2009 }
2010
2011 /* Create the section to hold the AVR property information. Return the
2012 section. */
2013
2014 static asection *
2015 avr_create_property_section (void)
2016 {
2017 asection *sec;
2018 flagword flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY);
2019 const char *section_name = AVR_PROPERTY_RECORD_SECTION_NAME;
2020
2021 sec = bfd_make_section (stdoutput, section_name);
2022 if (sec == NULL)
2023 as_fatal (_("Failed to create property section `%s'\n"), section_name);
2024 bfd_set_section_flags (stdoutput, sec, flags);
2025 sec->output_section = sec;
2026 return sec;
2027 }
2028
2029 /* This hook is called when alignment is performed, and allows us to
2030 capture the details of both .org and .align directives. */
2031
2032 void
2033 avr_handle_align (fragS *fragP)
2034 {
2035 if (linkrelax)
2036 {
2037 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2038 start of a section, and will be handled by the standard section
2039 alignment mechanism. */
2040 if ((fragP->fr_type == rs_align
2041 || fragP->fr_type == rs_align_code)
2042 && fragP->fr_offset > 0)
2043 {
2044 char *p = fragP->fr_literal + fragP->fr_fix;
2045
2046 fragP->tc_frag_data.is_align = TRUE;
2047 fragP->tc_frag_data.alignment = fragP->fr_offset;
2048 fragP->tc_frag_data.fill = *p;
2049 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2050 }
2051
2052 if (fragP->fr_type == rs_org && fragP->fr_offset > 0)
2053 {
2054 char *p = fragP->fr_literal + fragP->fr_fix;
2055
2056 fragP->tc_frag_data.is_org = TRUE;
2057 fragP->tc_frag_data.fill = *p;
2058 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2059 }
2060 }
2061 }
2062
2063 /* Return TRUE if this section is not one for which we need to record
2064 information in the avr property section. */
2065
2066 static bfd_boolean
2067 exclude_section_from_property_tables (segT sec)
2068 {
2069 /* Only generate property information for sections on which linker
2070 relaxation could be performed. */
2071 return !relaxable_section (sec);
2072 }
2073
2074 /* Create a property record for fragment FRAGP from section SEC and place
2075 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2076 into a linked list by the caller. */
2077
2078 static struct avr_property_record_link *
2079 create_record_for_frag (segT sec, fragS *fragP)
2080 {
2081 struct avr_property_record_link *prop_rec_link;
2082
2083 prop_rec_link = xmalloc (sizeof (struct avr_property_record_link));
2084 memset (prop_rec_link, 0, sizeof (*prop_rec_link));
2085 gas_assert (fragP->fr_next != NULL);
2086
2087 if (fragP->tc_frag_data.is_org)
2088 {
2089 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2090 prop_rec_link->record.section = sec;
2091
2092 if (fragP->tc_frag_data.has_fill)
2093 {
2094 prop_rec_link->record.data.org.fill = fragP->tc_frag_data.fill;
2095 prop_rec_link->record.type = RECORD_ORG_AND_FILL;
2096 }
2097 else
2098 prop_rec_link->record.type = RECORD_ORG;
2099 }
2100 else
2101 {
2102 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2103 prop_rec_link->record.section = sec;
2104
2105 gas_assert (fragP->tc_frag_data.is_align);
2106 if (fragP->tc_frag_data.has_fill)
2107 {
2108 prop_rec_link->record.data.align.fill = fragP->tc_frag_data.fill;
2109 prop_rec_link->record.type = RECORD_ALIGN_AND_FILL;
2110 }
2111 else
2112 prop_rec_link->record.type = RECORD_ALIGN;
2113 prop_rec_link->record.data.align.bytes = fragP->tc_frag_data.alignment;
2114 }
2115
2116 return prop_rec_link;
2117 }
2118
2119 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2120 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2121 the last list item created. */
2122
2123 static struct avr_property_record_link **
2124 append_records_for_section (segT sec,
2125 struct avr_property_record_link **next_ptr)
2126 {
2127 segment_info_type *seginfo = seg_info (sec);
2128 fragS *fragP;
2129
2130 if (seginfo && seginfo->frchainP)
2131 {
2132 for (fragP = seginfo->frchainP->frch_root;
2133 fragP;
2134 fragP = fragP->fr_next)
2135 {
2136 if (fragP->tc_frag_data.is_align
2137 || fragP->tc_frag_data.is_org)
2138 {
2139 /* Create a single new entry. */
2140 struct avr_property_record_link *new_link
2141 = create_record_for_frag (sec, fragP);
2142
2143 *next_ptr = new_link;
2144 next_ptr = &new_link->next;
2145 }
2146 }
2147 }
2148
2149 return next_ptr;
2150 }
2151
2152 /* Create the AVR property section and fill it with records of .org and
2153 .align directives that were used. The section is only created if it
2154 will actually have any content. */
2155
2156 static void
2157 avr_create_and_fill_property_section (void)
2158 {
2159 segT *seclist;
2160 asection *prop_sec;
2161 struct avr_property_record_link *r_list, **next_ptr;
2162 char *frag_ptr, *frag_base;
2163 bfd_size_type sec_size;
2164 struct avr_property_record_link *rec;
2165 unsigned int record_count;
2166
2167 /* First walk over all sections. For sections on which linker
2168 relaxation could be applied, extend the record list. The record list
2169 holds information that the linker will need to know. */
2170
2171 prop_sec = NULL;
2172 r_list = NULL;
2173 next_ptr = &r_list;
2174 for (seclist = &stdoutput->sections;
2175 seclist && *seclist;
2176 seclist = &(*seclist)->next)
2177 {
2178 segT sec = *seclist;
2179
2180 if (exclude_section_from_property_tables (sec))
2181 continue;
2182
2183 next_ptr = append_records_for_section (sec, next_ptr);
2184 }
2185
2186 /* Create property section and ensure the size is correct. We've already
2187 passed the point where gas could size this for us. */
2188 sec_size = AVR_PROPERTY_SECTION_HEADER_SIZE;
2189 record_count = 0;
2190 for (rec = r_list; rec != NULL; rec = rec->next)
2191 {
2192 record_count++;
2193 sec_size += avr_record_size (&rec->record);
2194 }
2195
2196 if (record_count == 0)
2197 return;
2198
2199 prop_sec = avr_create_property_section ();
2200 bfd_set_section_size (stdoutput, prop_sec, sec_size);
2201
2202 subseg_set (prop_sec, 0);
2203 frag_base = frag_more (sec_size);
2204
2205 frag_ptr =
2206 avr_output_property_section_header (frag_base, record_count);
2207
2208 for (rec = r_list; rec != NULL; rec = rec->next)
2209 frag_ptr = avr_output_property_record (frag_base, frag_ptr, &rec->record);
2210
2211 frag_wane (frag_now);
2212 frag_new (0);
2213 frag_wane (frag_now);
2214 }
2215
2216 /* We're using this hook to build up the AVR property section. It's called
2217 late in the assembly process which suits our needs. */
2218 void
2219 avr_post_relax_hook (void)
2220 {
2221 avr_create_and_fill_property_section ();
2222 }
GDB Binutils - Deliverables
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