1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
268 unsupported_with_intel_mnemonic
,
271 invalid_vsib_address
,
272 invalid_vector_register_set
,
273 unsupported_vector_index_register
,
274 unsupported_broadcast
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry
*base_reg
;
319 const reg_entry
*index_reg
;
320 unsigned int log2_scale_factor
;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry
*seg
[2];
326 /* Copied first memory operand string, for re-checking. */
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Prefer load or store in encoding. */
357 dir_encoding_default
= 0,
362 /* Prefer 8bit or 32bit displacement in encoding. */
365 disp_encoding_default
= 0,
370 /* Prefer the REX byte in encoding. */
371 bfd_boolean rex_encoding
;
373 /* Disable instruction size optimization. */
374 bfd_boolean no_optimize
;
376 /* How to encode vector instructions. */
379 vex_encoding_default
= 0,
386 const char *rep_prefix
;
389 const char *hle_prefix
;
391 /* Have BND prefix. */
392 const char *bnd_prefix
;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix
;
398 enum i386_error error
;
401 typedef struct _i386_insn i386_insn
;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable
[] =
414 { rne
, STRING_COMMA_LEN ("rn-sae") },
415 { rd
, STRING_COMMA_LEN ("rd-sae") },
416 { ru
, STRING_COMMA_LEN ("ru-sae") },
417 { rz
, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly
, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars
[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars
= "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars
= "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars
[] = "#/";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS
[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars
[256];
475 static char register_chars
[256];
476 static char operand_chars
[256];
477 static char identifier_chars
[256];
478 static char digit_chars
[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack
[32];
496 static char *save_stack_p
;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates
*current_templates
;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
510 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
512 /* Current operand we are working on. */
513 static int this_operand
= -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code
;
524 static unsigned int object_64bit
;
525 static unsigned int disallow_64bit_reloc
;
526 static int use_rela_relocations
= 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj
= 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared
= 0;
553 /* 1 for intel syntax,
555 static int intel_syntax
= 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic
= !SYSV386_COMPAT
;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg
= 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg
= 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix
= 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg
= 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix
= 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence
= 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
592 static enum check_kind
598 sse_check
, operand_check
= check_warning
;
601 1. Clear the REX_W bit with register operand if possible.
602 2. Above plus use 128bit vector instruction to clear the full vector
605 static int optimize
= 0;
608 1. Clear the REX_W bit with register operand if possible.
609 2. Above plus use 128bit vector instruction to clear the full vector
611 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
614 static int optimize_for_space
= 0;
616 /* Register prefix used for error message. */
617 static const char *register_prefix
= "%";
619 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
620 leave, push, and pop instructions so that gcc has the same stack
621 frame as in 32 bit mode. */
622 static char stackop_size
= '\0';
624 /* Non-zero to optimize code alignment. */
625 int optimize_align_code
= 1;
627 /* Non-zero to quieten some warnings. */
628 static int quiet_warnings
= 0;
631 static const char *cpu_arch_name
= NULL
;
632 static char *cpu_sub_arch_name
= NULL
;
634 /* CPU feature flags. */
635 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
637 /* If we have selected a cpu we are generating instructions for. */
638 static int cpu_arch_tune_set
= 0;
640 /* Cpu we are generating instructions for. */
641 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
643 /* CPU feature flags of cpu we are generating instructions for. */
644 static i386_cpu_flags cpu_arch_tune_flags
;
646 /* CPU instruction set architecture used. */
647 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
649 /* CPU feature flags of instruction set architecture used. */
650 i386_cpu_flags cpu_arch_isa_flags
;
652 /* If set, conditional jumps are not automatically promoted to handle
653 larger than a byte offset. */
654 static unsigned int no_cond_jump_promotion
= 0;
656 /* Encode SSE instructions with VEX prefix. */
657 static unsigned int sse2avx
;
659 /* Encode scalar AVX instructions with specific vector length. */
666 /* Encode scalar EVEX LIG instructions with specific vector length. */
674 /* Encode EVEX WIG instructions with specific evex.w. */
681 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
682 static enum rc_type evexrcig
= rne
;
684 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
685 static symbolS
*GOT_symbol
;
687 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
688 unsigned int x86_dwarf2_return_column
;
690 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
691 int x86_cie_data_alignment
;
693 /* Interface to relax_segment.
694 There are 3 major relax states for 386 jump insns because the
695 different types of jumps add different sizes to frags when we're
696 figuring out what sort of jump to choose to reach a given label. */
699 #define UNCOND_JUMP 0
701 #define COND_JUMP86 2
706 #define SMALL16 (SMALL | CODE16)
708 #define BIG16 (BIG | CODE16)
712 #define INLINE __inline__
718 #define ENCODE_RELAX_STATE(type, size) \
719 ((relax_substateT) (((type) << 2) | (size)))
720 #define TYPE_FROM_RELAX_STATE(s) \
722 #define DISP_SIZE_FROM_RELAX_STATE(s) \
723 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
725 /* This table is used by relax_frag to promote short jumps to long
726 ones where necessary. SMALL (short) jumps may be promoted to BIG
727 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
728 don't allow a short jump in a 32 bit code segment to be promoted to
729 a 16 bit offset jump because it's slower (requires data size
730 prefix), and doesn't work, unless the destination is in the bottom
731 64k of the code segment (The top 16 bits of eip are zeroed). */
733 const relax_typeS md_relax_table
[] =
736 1) most positive reach of this state,
737 2) most negative reach of this state,
738 3) how many bytes this mode will have in the variable part of the frag
739 4) which index into the table to try if we can't fit into this one. */
741 /* UNCOND_JUMP states. */
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
744 /* dword jmp adds 4 bytes to frag:
745 0 extra opcode bytes, 4 displacement bytes. */
747 /* word jmp adds 2 byte2 to frag:
748 0 extra opcode bytes, 2 displacement bytes. */
751 /* COND_JUMP states. */
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
754 /* dword conditionals adds 5 bytes to frag:
755 1 extra opcode byte, 4 displacement bytes. */
757 /* word conditionals add 3 bytes to frag:
758 1 extra opcode byte, 2 displacement bytes. */
761 /* COND_JUMP86 states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
764 /* dword conditionals adds 5 bytes to frag:
765 1 extra opcode byte, 4 displacement bytes. */
767 /* word conditionals add 4 bytes to frag:
768 1 displacement byte and a 3 byte long branch insn. */
772 static const arch_entry cpu_arch
[] =
774 /* Do not replace the first two entries - i386_target_format()
775 relies on them being there in this order. */
776 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
777 CPU_GENERIC32_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
779 CPU_GENERIC64_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
786 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
788 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
790 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
792 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
794 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
796 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
797 CPU_PENTIUMPRO_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
802 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
804 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
806 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
807 CPU_NOCONA_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
812 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 1 },
814 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
815 CPU_CORE2_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
817 CPU_COREI7_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
820 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
822 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
823 CPU_IAMCU_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
828 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
829 CPU_ATHLON_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
836 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
837 CPU_AMDFAM10_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
839 CPU_BDVER1_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
841 CPU_BDVER2_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
843 CPU_BDVER3_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
845 CPU_BDVER4_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
847 CPU_ZNVER1_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
849 CPU_ZNVER2_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
851 CPU_BTVER1_FLAGS
, 0 },
852 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
853 CPU_BTVER2_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
870 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
871 CPU_SSSE3_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_1_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
877 CPU_SSE4_2_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512F_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512CD_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512ER_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512PF_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512DQ_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512BW_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
895 CPU_AVX512VL_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
899 CPU_VMFUNC_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVE_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEOPT_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVEC_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
909 CPU_XSAVES_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
915 CPU_PCLMUL_FLAGS
, 1 },
916 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
917 CPU_FSGSBASE_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
919 CPU_RDRND_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
933 CPU_MOVBE_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
939 CPU_LZCNT_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
945 CPU_INVPCID_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
947 CPU_CLFLUSH_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
951 CPU_SYSCALL_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
953 CPU_RDTSCP_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOW_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
957 CPU_3DNOWA_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
959 CPU_PADLOCK_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
965 CPU_SSE4A_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
975 CPU_RDSEED_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
977 CPU_PRFCHW_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
985 CPU_CLFLUSHOPT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
987 CPU_PREFETCHWT1_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
992 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512IFMA_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512VBMI_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4FMAPS_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VBMI2_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_VNNI_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512_BITALG_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1009 CPU_CLZERO_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1011 CPU_MWAITX_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1013 CPU_OSPKE_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1015 CPU_RDPID_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1017 CPU_PTWRITE_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1021 CPU_SHSTK_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1023 CPU_GFNI_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1025 CPU_VAES_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1027 CPU_VPCLMULQDQ_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1029 CPU_WBNOINVD_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1031 CPU_PCONFIG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1033 CPU_WAITPKG_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1035 CPU_CLDEMOTE_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIRI_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1039 CPU_MOVDIR64B_FLAGS
, 0 },
1042 static const noarch_entry cpu_noarch
[] =
1044 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1045 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1046 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1047 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1048 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1050 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1052 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1055 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1071 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1072 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1073 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1074 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1075 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1076 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1080 /* Like s_lcomm_internal in gas/read.c but the alignment string
1081 is allowed to be optional. */
1084 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1091 && *input_line_pointer
== ',')
1093 align
= parse_align (needs_align
- 1);
1095 if (align
== (addressT
) -1)
1110 bss_alloc (symbolP
, size
, align
);
1115 pe_lcomm (int needs_align
)
1117 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1121 const pseudo_typeS md_pseudo_table
[] =
1123 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1124 {"align", s_align_bytes
, 0},
1126 {"align", s_align_ptwo
, 0},
1128 {"arch", set_cpu_arch
, 0},
1132 {"lcomm", pe_lcomm
, 1},
1134 {"ffloat", float_cons
, 'f'},
1135 {"dfloat", float_cons
, 'd'},
1136 {"tfloat", float_cons
, 'x'},
1138 {"slong", signed_cons
, 4},
1139 {"noopt", s_ignore
, 0},
1140 {"optim", s_ignore
, 0},
1141 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1142 {"code16", set_code_flag
, CODE_16BIT
},
1143 {"code32", set_code_flag
, CODE_32BIT
},
1145 {"code64", set_code_flag
, CODE_64BIT
},
1147 {"intel_syntax", set_intel_syntax
, 1},
1148 {"att_syntax", set_intel_syntax
, 0},
1149 {"intel_mnemonic", set_intel_mnemonic
, 1},
1150 {"att_mnemonic", set_intel_mnemonic
, 0},
1151 {"allow_index_reg", set_allow_index_reg
, 1},
1152 {"disallow_index_reg", set_allow_index_reg
, 0},
1153 {"sse_check", set_check
, 0},
1154 {"operand_check", set_check
, 1},
1155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1156 {"largecomm", handle_large_common
, 0},
1158 {"file", dwarf2_directive_file
, 0},
1159 {"loc", dwarf2_directive_loc
, 0},
1160 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1163 {"secrel32", pe_directive_secrel
, 0},
1168 /* For interface with expression (). */
1169 extern char *input_line_pointer
;
1171 /* Hash table for instruction mnemonic lookup. */
1172 static struct hash_control
*op_hash
;
1174 /* Hash table for register lookup. */
1175 static struct hash_control
*reg_hash
;
1177 /* Various efficient no-op patterns for aligning code labels.
1178 Note: Don't try to assemble the instructions in the comments.
1179 0L and 0w are not legal. */
1180 static const unsigned char f32_1
[] =
1182 static const unsigned char f32_2
[] =
1183 {0x66,0x90}; /* xchg %ax,%ax */
1184 static const unsigned char f32_3
[] =
1185 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1186 static const unsigned char f32_4
[] =
1187 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1188 static const unsigned char f32_6
[] =
1189 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1190 static const unsigned char f32_7
[] =
1191 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1192 static const unsigned char f16_3
[] =
1193 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1194 static const unsigned char f16_4
[] =
1195 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1196 static const unsigned char jump_disp8
[] =
1197 {0xeb}; /* jmp disp8 */
1198 static const unsigned char jump32_disp32
[] =
1199 {0xe9}; /* jmp disp32 */
1200 static const unsigned char jump16_disp32
[] =
1201 {0x66,0xe9}; /* jmp disp32 */
1202 /* 32-bit NOPs patterns. */
1203 static const unsigned char *const f32_patt
[] = {
1204 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1206 /* 16-bit NOPs patterns. */
1207 static const unsigned char *const f16_patt
[] = {
1208 f32_1
, f32_2
, f16_3
, f16_4
1210 /* nopl (%[re]ax) */
1211 static const unsigned char alt_3
[] =
1213 /* nopl 0(%[re]ax) */
1214 static const unsigned char alt_4
[] =
1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_5
[] =
1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_6
[] =
1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
1223 static const unsigned char alt_7
[] =
1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_8
[] =
1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_9
[] =
1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1232 static const unsigned char alt_10
[] =
1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 /* data16 nopw %cs:0L(%eax,%eax,1) */
1235 static const unsigned char alt_11
[] =
1236 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* 32-bit and 64-bit NOPs patterns. */
1238 static const unsigned char *const alt_patt
[] = {
1239 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1240 alt_9
, alt_10
, alt_11
1243 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1244 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1247 i386_output_nops (char *where
, const unsigned char *const *patt
,
1248 int count
, int max_single_nop_size
)
1251 /* Place the longer NOP first. */
1254 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1256 /* Use the smaller one if the requsted one isn't available. */
1259 max_single_nop_size
--;
1260 nops
= patt
[max_single_nop_size
- 1];
1263 last
= count
% max_single_nop_size
;
1266 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1267 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1271 nops
= patt
[last
- 1];
1274 /* Use the smaller one plus one-byte NOP if the needed one
1277 nops
= patt
[last
- 1];
1278 memcpy (where
+ offset
, nops
, last
);
1279 where
[offset
+ last
] = *patt
[0];
1282 memcpy (where
+ offset
, nops
, last
);
1287 fits_in_imm7 (offsetT num
)
1289 return (num
& 0x7f) == num
;
1293 fits_in_imm31 (offsetT num
)
1295 return (num
& 0x7fffffff) == num
;
1298 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1299 single NOP instruction LIMIT. */
1302 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1304 const unsigned char *const *patt
= NULL
;
1305 int max_single_nop_size
;
1306 /* Maximum number of NOPs before switching to jump over NOPs. */
1307 int max_number_of_nops
;
1309 switch (fragP
->fr_type
)
1318 /* We need to decide which NOP sequence to use for 32bit and
1319 64bit. When -mtune= is used:
1321 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1322 PROCESSOR_GENERIC32, f32_patt will be used.
1323 2. For the rest, alt_patt will be used.
1325 When -mtune= isn't used, alt_patt will be used if
1326 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1329 When -march= or .arch is used, we can't use anything beyond
1330 cpu_arch_isa_flags. */
1332 if (flag_code
== CODE_16BIT
)
1335 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1336 /* Limit number of NOPs to 2 in 16-bit mode. */
1337 max_number_of_nops
= 2;
1341 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1343 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1344 switch (cpu_arch_tune
)
1346 case PROCESSOR_UNKNOWN
:
1347 /* We use cpu_arch_isa_flags to check if we SHOULD
1348 optimize with nops. */
1349 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1354 case PROCESSOR_PENTIUM4
:
1355 case PROCESSOR_NOCONA
:
1356 case PROCESSOR_CORE
:
1357 case PROCESSOR_CORE2
:
1358 case PROCESSOR_COREI7
:
1359 case PROCESSOR_L1OM
:
1360 case PROCESSOR_K1OM
:
1361 case PROCESSOR_GENERIC64
:
1363 case PROCESSOR_ATHLON
:
1365 case PROCESSOR_AMDFAM10
:
1367 case PROCESSOR_ZNVER
:
1371 case PROCESSOR_I386
:
1372 case PROCESSOR_I486
:
1373 case PROCESSOR_PENTIUM
:
1374 case PROCESSOR_PENTIUMPRO
:
1375 case PROCESSOR_IAMCU
:
1376 case PROCESSOR_GENERIC32
:
1383 switch (fragP
->tc_frag_data
.tune
)
1385 case PROCESSOR_UNKNOWN
:
1386 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1387 PROCESSOR_UNKNOWN. */
1391 case PROCESSOR_I386
:
1392 case PROCESSOR_I486
:
1393 case PROCESSOR_PENTIUM
:
1394 case PROCESSOR_IAMCU
:
1396 case PROCESSOR_ATHLON
:
1398 case PROCESSOR_AMDFAM10
:
1400 case PROCESSOR_ZNVER
:
1402 case PROCESSOR_GENERIC32
:
1403 /* We use cpu_arch_isa_flags to check if we CAN optimize
1405 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1410 case PROCESSOR_PENTIUMPRO
:
1411 case PROCESSOR_PENTIUM4
:
1412 case PROCESSOR_NOCONA
:
1413 case PROCESSOR_CORE
:
1414 case PROCESSOR_CORE2
:
1415 case PROCESSOR_COREI7
:
1416 case PROCESSOR_L1OM
:
1417 case PROCESSOR_K1OM
:
1418 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1423 case PROCESSOR_GENERIC64
:
1429 if (patt
== f32_patt
)
1431 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1432 /* Limit number of NOPs to 2 for older processors. */
1433 max_number_of_nops
= 2;
1437 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1438 /* Limit number of NOPs to 7 for newer processors. */
1439 max_number_of_nops
= 7;
1444 limit
= max_single_nop_size
;
1446 if (fragP
->fr_type
== rs_fill_nop
)
1448 /* Output NOPs for .nop directive. */
1449 if (limit
> max_single_nop_size
)
1451 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1452 _("invalid single nop size: %d "
1453 "(expect within [0, %d])"),
1454 limit
, max_single_nop_size
);
1459 fragP
->fr_var
= count
;
1461 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1463 /* Generate jump over NOPs. */
1464 offsetT disp
= count
- 2;
1465 if (fits_in_imm7 (disp
))
1467 /* Use "jmp disp8" if possible. */
1469 where
[0] = jump_disp8
[0];
1475 unsigned int size_of_jump
;
1477 if (flag_code
== CODE_16BIT
)
1479 where
[0] = jump16_disp32
[0];
1480 where
[1] = jump16_disp32
[1];
1485 where
[0] = jump32_disp32
[0];
1489 count
-= size_of_jump
+ 4;
1490 if (!fits_in_imm31 (count
))
1492 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1493 _("jump over nop padding out of range"));
1497 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1498 where
+= size_of_jump
+ 4;
1502 /* Generate multiple NOPs. */
1503 i386_output_nops (where
, patt
, count
, limit
);
1507 operand_type_all_zero (const union i386_operand_type
*x
)
1509 switch (ARRAY_SIZE(x
->array
))
1520 return !x
->array
[0];
1527 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1529 switch (ARRAY_SIZE(x
->array
))
1547 operand_type_equal (const union i386_operand_type
*x
,
1548 const union i386_operand_type
*y
)
1550 switch (ARRAY_SIZE(x
->array
))
1553 if (x
->array
[2] != y
->array
[2])
1557 if (x
->array
[1] != y
->array
[1])
1561 return x
->array
[0] == y
->array
[0];
1569 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1571 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 cpu_flags_equal (const union i386_cpu_flags
*x
,
1594 const union i386_cpu_flags
*y
)
1596 switch (ARRAY_SIZE(x
->array
))
1599 if (x
->array
[3] != y
->array
[3])
1603 if (x
->array
[2] != y
->array
[2])
1607 if (x
->array
[1] != y
->array
[1])
1611 return x
->array
[0] == y
->array
[0];
1619 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1621 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1622 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1625 static INLINE i386_cpu_flags
1626 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1628 switch (ARRAY_SIZE (x
.array
))
1631 x
.array
[3] &= y
.array
[3];
1634 x
.array
[2] &= y
.array
[2];
1637 x
.array
[1] &= y
.array
[1];
1640 x
.array
[0] &= y
.array
[0];
1648 static INLINE i386_cpu_flags
1649 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1651 switch (ARRAY_SIZE (x
.array
))
1654 x
.array
[3] |= y
.array
[3];
1657 x
.array
[2] |= y
.array
[2];
1660 x
.array
[1] |= y
.array
[1];
1663 x
.array
[0] |= y
.array
[0];
1671 static INLINE i386_cpu_flags
1672 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1674 switch (ARRAY_SIZE (x
.array
))
1677 x
.array
[3] &= ~y
.array
[3];
1680 x
.array
[2] &= ~y
.array
[2];
1683 x
.array
[1] &= ~y
.array
[1];
1686 x
.array
[0] &= ~y
.array
[0];
1694 #define CPU_FLAGS_ARCH_MATCH 0x1
1695 #define CPU_FLAGS_64BIT_MATCH 0x2
1697 #define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1700 /* Return CPU flags match bits. */
1703 cpu_flags_match (const insn_template
*t
)
1705 i386_cpu_flags x
= t
->cpu_flags
;
1706 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1708 x
.bitfield
.cpu64
= 0;
1709 x
.bitfield
.cpuno64
= 0;
1711 if (cpu_flags_all_zero (&x
))
1713 /* This instruction is available on all archs. */
1714 match
|= CPU_FLAGS_ARCH_MATCH
;
1718 /* This instruction is available only on some archs. */
1719 i386_cpu_flags cpu
= cpu_arch_flags
;
1721 /* AVX512VL is no standalone feature - match it and then strip it. */
1722 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1724 x
.bitfield
.cpuavx512vl
= 0;
1726 cpu
= cpu_flags_and (x
, cpu
);
1727 if (!cpu_flags_all_zero (&cpu
))
1729 if (x
.bitfield
.cpuavx
)
1731 /* We need to check a few extra flags with AVX. */
1732 if (cpu
.bitfield
.cpuavx
1733 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1734 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1735 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1736 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1737 match
|= CPU_FLAGS_ARCH_MATCH
;
1739 else if (x
.bitfield
.cpuavx512f
)
1741 /* We need to check a few extra flags with AVX512F. */
1742 if (cpu
.bitfield
.cpuavx512f
1743 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1744 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1745 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1746 match
|= CPU_FLAGS_ARCH_MATCH
;
1749 match
|= CPU_FLAGS_ARCH_MATCH
;
1755 static INLINE i386_operand_type
1756 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1758 switch (ARRAY_SIZE (x
.array
))
1761 x
.array
[2] &= y
.array
[2];
1764 x
.array
[1] &= y
.array
[1];
1767 x
.array
[0] &= y
.array
[0];
1775 static INLINE i386_operand_type
1776 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1778 switch (ARRAY_SIZE (x
.array
))
1781 x
.array
[2] &= ~y
.array
[2];
1784 x
.array
[1] &= ~y
.array
[1];
1787 x
.array
[0] &= ~y
.array
[0];
1795 static INLINE i386_operand_type
1796 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1798 switch (ARRAY_SIZE (x
.array
))
1801 x
.array
[2] |= y
.array
[2];
1804 x
.array
[1] |= y
.array
[1];
1807 x
.array
[0] |= y
.array
[0];
1815 static INLINE i386_operand_type
1816 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1818 switch (ARRAY_SIZE (x
.array
))
1821 x
.array
[2] ^= y
.array
[2];
1824 x
.array
[1] ^= y
.array
[1];
1827 x
.array
[0] ^= y
.array
[0];
1835 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1836 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1837 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1838 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1839 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1840 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1841 static const i386_operand_type anydisp
1842 = OPERAND_TYPE_ANYDISP
;
1843 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1844 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1845 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1846 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1847 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1848 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1849 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1850 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1851 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1852 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1853 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1854 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1865 operand_type_check (i386_operand_type t
, enum operand_type c
)
1870 return t
.bitfield
.reg
;
1873 return (t
.bitfield
.imm8
1877 || t
.bitfield
.imm32s
1878 || t
.bitfield
.imm64
);
1881 return (t
.bitfield
.disp8
1882 || t
.bitfield
.disp16
1883 || t
.bitfield
.disp32
1884 || t
.bitfield
.disp32s
1885 || t
.bitfield
.disp64
);
1888 return (t
.bitfield
.disp8
1889 || t
.bitfield
.disp16
1890 || t
.bitfield
.disp32
1891 || t
.bitfield
.disp32s
1892 || t
.bitfield
.disp64
1893 || t
.bitfield
.baseindex
);
1902 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1903 between operand GIVEN and opeand WANTED for instruction template T. */
1906 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1909 return !((i
.types
[given
].bitfield
.byte
1910 && !t
->operand_types
[wanted
].bitfield
.byte
)
1911 || (i
.types
[given
].bitfield
.word
1912 && !t
->operand_types
[wanted
].bitfield
.word
)
1913 || (i
.types
[given
].bitfield
.dword
1914 && !t
->operand_types
[wanted
].bitfield
.dword
)
1915 || (i
.types
[given
].bitfield
.qword
1916 && !t
->operand_types
[wanted
].bitfield
.qword
)
1917 || (i
.types
[given
].bitfield
.tbyte
1918 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1921 /* Return 1 if there is no conflict in SIMD register between operand
1922 GIVEN and opeand WANTED for instruction template T. */
1925 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1928 return !((i
.types
[given
].bitfield
.xmmword
1929 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1930 || (i
.types
[given
].bitfield
.ymmword
1931 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1932 || (i
.types
[given
].bitfield
.zmmword
1933 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1936 /* Return 1 if there is no conflict in any size between operand GIVEN
1937 and opeand WANTED for instruction template T. */
1940 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1943 return (match_operand_size (t
, wanted
, given
)
1944 && !((i
.types
[given
].bitfield
.unspecified
1946 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1947 || (i
.types
[given
].bitfield
.fword
1948 && !t
->operand_types
[wanted
].bitfield
.fword
)
1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1953 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1954 && !t
->opcode_modifier
.broadcast
1955 && (t
->operand_types
[wanted
].bitfield
.byte
1956 || t
->operand_types
[wanted
].bitfield
.word
1957 || t
->operand_types
[wanted
].bitfield
.dword
1958 || t
->operand_types
[wanted
].bitfield
.qword
))
1959 ? (i
.types
[given
].bitfield
.xmmword
1960 || i
.types
[given
].bitfield
.ymmword
1961 || i
.types
[given
].bitfield
.zmmword
)
1962 : !match_simd_size(t
, wanted
, given
))));
1965 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1966 operands for instruction template T, and it has MATCH_REVERSE set if there
1967 is no size conflict on any operands for the template with operands reversed
1968 (and the template allows for reversing in the first place). */
1970 #define MATCH_STRAIGHT 1
1971 #define MATCH_REVERSE 2
1973 static INLINE
unsigned int
1974 operand_size_match (const insn_template
*t
)
1976 unsigned int j
, match
= MATCH_STRAIGHT
;
1978 /* Don't check jump instructions. */
1979 if (t
->opcode_modifier
.jump
1980 || t
->opcode_modifier
.jumpbyte
1981 || t
->opcode_modifier
.jumpdword
1982 || t
->opcode_modifier
.jumpintersegment
)
1985 /* Check memory and accumulator operand size. */
1986 for (j
= 0; j
< i
.operands
; j
++)
1988 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1989 && t
->operand_types
[j
].bitfield
.anysize
)
1992 if (t
->operand_types
[j
].bitfield
.reg
1993 && !match_operand_size (t
, j
, j
))
1999 if (t
->operand_types
[j
].bitfield
.regsimd
2000 && !match_simd_size (t
, j
, j
))
2006 if (t
->operand_types
[j
].bitfield
.acc
2007 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2013 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
, j
))
2020 if (!t
->opcode_modifier
.d
)
2024 i
.error
= operand_size_mismatch
;
2028 /* Check reverse. */
2029 gas_assert (i
.operands
== 2);
2031 for (j
= 0; j
< 2; j
++)
2033 if ((t
->operand_types
[j
].bitfield
.reg
2034 || t
->operand_types
[j
].bitfield
.acc
)
2035 && !match_operand_size (t
, j
, !j
))
2038 if (i
.types
[!j
].bitfield
.mem
2039 && !match_mem_size (t
, j
, !j
))
2043 return match
| MATCH_REVERSE
;
2047 operand_type_match (i386_operand_type overlap
,
2048 i386_operand_type given
)
2050 i386_operand_type temp
= overlap
;
2052 temp
.bitfield
.jumpabsolute
= 0;
2053 temp
.bitfield
.unspecified
= 0;
2054 temp
.bitfield
.byte
= 0;
2055 temp
.bitfield
.word
= 0;
2056 temp
.bitfield
.dword
= 0;
2057 temp
.bitfield
.fword
= 0;
2058 temp
.bitfield
.qword
= 0;
2059 temp
.bitfield
.tbyte
= 0;
2060 temp
.bitfield
.xmmword
= 0;
2061 temp
.bitfield
.ymmword
= 0;
2062 temp
.bitfield
.zmmword
= 0;
2063 if (operand_type_all_zero (&temp
))
2066 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2067 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2071 i
.error
= operand_type_mismatch
;
2075 /* If given types g0 and g1 are registers they must be of the same type
2076 unless the expected operand type register overlap is null.
2077 Memory operand size of certain SIMD instructions is also being checked
2081 operand_type_register_match (i386_operand_type g0
,
2082 i386_operand_type t0
,
2083 i386_operand_type g1
,
2084 i386_operand_type t1
)
2086 if (!g0
.bitfield
.reg
2087 && !g0
.bitfield
.regsimd
2088 && (!operand_type_check (g0
, anymem
)
2089 || g0
.bitfield
.unspecified
2090 || !t0
.bitfield
.regsimd
))
2093 if (!g1
.bitfield
.reg
2094 && !g1
.bitfield
.regsimd
2095 && (!operand_type_check (g1
, anymem
)
2096 || g1
.bitfield
.unspecified
2097 || !t1
.bitfield
.regsimd
))
2100 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2101 && g0
.bitfield
.word
== g1
.bitfield
.word
2102 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2103 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2104 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2105 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2106 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2109 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2110 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2111 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2112 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2113 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2114 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2115 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2118 i
.error
= register_type_mismatch
;
2123 static INLINE
unsigned int
2124 register_number (const reg_entry
*r
)
2126 unsigned int nr
= r
->reg_num
;
2128 if (r
->reg_flags
& RegRex
)
2131 if (r
->reg_flags
& RegVRex
)
2137 static INLINE
unsigned int
2138 mode_from_disp_size (i386_operand_type t
)
2140 if (t
.bitfield
.disp8
)
2142 else if (t
.bitfield
.disp16
2143 || t
.bitfield
.disp32
2144 || t
.bitfield
.disp32s
)
2151 fits_in_signed_byte (addressT num
)
2153 return num
+ 0x80 <= 0xff;
2157 fits_in_unsigned_byte (addressT num
)
2163 fits_in_unsigned_word (addressT num
)
2165 return num
<= 0xffff;
2169 fits_in_signed_word (addressT num
)
2171 return num
+ 0x8000 <= 0xffff;
2175 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2180 return num
+ 0x80000000 <= 0xffffffff;
2182 } /* fits_in_signed_long() */
2185 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2190 return num
<= 0xffffffff;
2192 } /* fits_in_unsigned_long() */
2195 fits_in_disp8 (offsetT num
)
2197 int shift
= i
.memshift
;
2203 mask
= (1 << shift
) - 1;
2205 /* Return 0 if NUM isn't properly aligned. */
2209 /* Check if NUM will fit in 8bit after shift. */
2210 return fits_in_signed_byte (num
>> shift
);
2214 fits_in_imm4 (offsetT num
)
2216 return (num
& 0xf) == num
;
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num
)
2222 i386_operand_type t
;
2224 operand_type_set (&t
, 0);
2225 t
.bitfield
.imm64
= 1;
2227 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2234 t
.bitfield
.imm1
= 1;
2235 t
.bitfield
.imm8
= 1;
2236 t
.bitfield
.imm8s
= 1;
2237 t
.bitfield
.imm16
= 1;
2238 t
.bitfield
.imm32
= 1;
2239 t
.bitfield
.imm32s
= 1;
2241 else if (fits_in_signed_byte (num
))
2243 t
.bitfield
.imm8
= 1;
2244 t
.bitfield
.imm8s
= 1;
2245 t
.bitfield
.imm16
= 1;
2246 t
.bitfield
.imm32
= 1;
2247 t
.bitfield
.imm32s
= 1;
2249 else if (fits_in_unsigned_byte (num
))
2251 t
.bitfield
.imm8
= 1;
2252 t
.bitfield
.imm16
= 1;
2253 t
.bitfield
.imm32
= 1;
2254 t
.bitfield
.imm32s
= 1;
2256 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2258 t
.bitfield
.imm16
= 1;
2259 t
.bitfield
.imm32
= 1;
2260 t
.bitfield
.imm32s
= 1;
2262 else if (fits_in_signed_long (num
))
2264 t
.bitfield
.imm32
= 1;
2265 t
.bitfield
.imm32s
= 1;
2267 else if (fits_in_unsigned_long (num
))
2268 t
.bitfield
.imm32
= 1;
2274 offset_in_range (offsetT val
, int size
)
2280 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2281 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2282 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2284 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code
!= CODE_64BIT
2292 || i
.prefix
[ADDR_PREFIX
])
2293 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2294 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2297 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2299 char buf1
[40], buf2
[40];
2301 sprint_value (buf1
, val
);
2302 sprint_value (buf2
, val
& mask
);
2303 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix
)
2329 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2332 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2333 && flag_code
== CODE_64BIT
)
2335 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2336 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2337 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2338 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2349 case DS_PREFIX_OPCODE
:
2352 case CS_PREFIX_OPCODE
:
2353 case ES_PREFIX_OPCODE
:
2354 case FS_PREFIX_OPCODE
:
2355 case GS_PREFIX_OPCODE
:
2356 case SS_PREFIX_OPCODE
:
2360 case REPNE_PREFIX_OPCODE
:
2361 case REPE_PREFIX_OPCODE
:
2366 case LOCK_PREFIX_OPCODE
:
2375 case ADDR_PREFIX_OPCODE
:
2379 case DATA_PREFIX_OPCODE
:
2383 if (i
.prefix
[q
] != 0)
2391 i
.prefix
[q
] |= prefix
;
2394 as_bad (_("same type of prefix used twice"));
2400 update_code_flag (int value
, int check
)
2402 PRINTF_LIKE ((*as_error
));
2404 flag_code
= (enum flag_code
) value
;
2405 if (flag_code
== CODE_64BIT
)
2407 cpu_arch_flags
.bitfield
.cpu64
= 1;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2412 cpu_arch_flags
.bitfield
.cpu64
= 0;
2413 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2415 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2418 as_error
= as_fatal
;
2421 (*as_error
) (_("64bit mode not supported on `%s'."),
2422 cpu_arch_name
? cpu_arch_name
: default_arch
);
2424 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2427 as_error
= as_fatal
;
2430 (*as_error
) (_("32bit mode not supported on `%s'."),
2431 cpu_arch_name
? cpu_arch_name
: default_arch
);
2433 stackop_size
= '\0';
2437 set_code_flag (int value
)
2439 update_code_flag (value
, 0);
2443 set_16bit_gcc_code_flag (int new_code_flag
)
2445 flag_code
= (enum flag_code
) new_code_flag
;
2446 if (flag_code
!= CODE_16BIT
)
2448 cpu_arch_flags
.bitfield
.cpu64
= 0;
2449 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2450 stackop_size
= LONG_MNEM_SUFFIX
;
2454 set_intel_syntax (int syntax_flag
)
2456 /* Find out if register prefixing is specified. */
2457 int ask_naked_reg
= 0;
2460 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2463 int e
= get_symbol_name (&string
);
2465 if (strcmp (string
, "prefix") == 0)
2467 else if (strcmp (string
, "noprefix") == 0)
2470 as_bad (_("bad argument to syntax directive."));
2471 (void) restore_line_pointer (e
);
2473 demand_empty_rest_of_line ();
2475 intel_syntax
= syntax_flag
;
2477 if (ask_naked_reg
== 0)
2478 allow_naked_reg
= (intel_syntax
2479 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2481 allow_naked_reg
= (ask_naked_reg
< 0);
2483 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2485 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2486 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2487 register_prefix
= allow_naked_reg
? "" : "%";
2491 set_intel_mnemonic (int mnemonic_flag
)
2493 intel_mnemonic
= mnemonic_flag
;
2497 set_allow_index_reg (int flag
)
2499 allow_index_reg
= flag
;
2503 set_check (int what
)
2505 enum check_kind
*kind
;
2510 kind
= &operand_check
;
2521 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2524 int e
= get_symbol_name (&string
);
2526 if (strcmp (string
, "none") == 0)
2528 else if (strcmp (string
, "warning") == 0)
2529 *kind
= check_warning
;
2530 else if (strcmp (string
, "error") == 0)
2531 *kind
= check_error
;
2533 as_bad (_("bad argument to %s_check directive."), str
);
2534 (void) restore_line_pointer (e
);
2537 as_bad (_("missing argument for %s_check directive"), str
);
2539 demand_empty_rest_of_line ();
2543 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2544 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2547 static const char *arch
;
2549 /* Intel LIOM is only supported on ELF. */
2555 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2556 use default_arch. */
2557 arch
= cpu_arch_name
;
2559 arch
= default_arch
;
2562 /* If we are targeting Intel MCU, we must enable it. */
2563 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2564 || new_flag
.bitfield
.cpuiamcu
)
2567 /* If we are targeting Intel L1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2569 || new_flag
.bitfield
.cpul1om
)
2572 /* If we are targeting Intel K1OM, we must enable it. */
2573 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2574 || new_flag
.bitfield
.cpuk1om
)
2577 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2582 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2586 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2589 int e
= get_symbol_name (&string
);
2591 i386_cpu_flags flags
;
2593 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2595 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2597 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2601 cpu_arch_name
= cpu_arch
[j
].name
;
2602 cpu_sub_arch_name
= NULL
;
2603 cpu_arch_flags
= cpu_arch
[j
].flags
;
2604 if (flag_code
== CODE_64BIT
)
2606 cpu_arch_flags
.bitfield
.cpu64
= 1;
2607 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2611 cpu_arch_flags
.bitfield
.cpu64
= 0;
2612 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2614 cpu_arch_isa
= cpu_arch
[j
].type
;
2615 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2616 if (!cpu_arch_tune_set
)
2618 cpu_arch_tune
= cpu_arch_isa
;
2619 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2624 flags
= cpu_flags_or (cpu_arch_flags
,
2627 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2629 if (cpu_sub_arch_name
)
2631 char *name
= cpu_sub_arch_name
;
2632 cpu_sub_arch_name
= concat (name
,
2634 (const char *) NULL
);
2638 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2639 cpu_arch_flags
= flags
;
2640 cpu_arch_isa_flags
= flags
;
2644 = cpu_flags_or (cpu_arch_isa_flags
,
2646 (void) restore_line_pointer (e
);
2647 demand_empty_rest_of_line ();
2652 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2654 /* Disable an ISA extension. */
2655 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2656 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2658 flags
= cpu_flags_and_not (cpu_arch_flags
,
2659 cpu_noarch
[j
].flags
);
2660 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2662 if (cpu_sub_arch_name
)
2664 char *name
= cpu_sub_arch_name
;
2665 cpu_sub_arch_name
= concat (name
, string
,
2666 (const char *) NULL
);
2670 cpu_sub_arch_name
= xstrdup (string
);
2671 cpu_arch_flags
= flags
;
2672 cpu_arch_isa_flags
= flags
;
2674 (void) restore_line_pointer (e
);
2675 demand_empty_rest_of_line ();
2679 j
= ARRAY_SIZE (cpu_arch
);
2682 if (j
>= ARRAY_SIZE (cpu_arch
))
2683 as_bad (_("no such architecture: `%s'"), string
);
2685 *input_line_pointer
= e
;
2688 as_bad (_("missing cpu architecture"));
2690 no_cond_jump_promotion
= 0;
2691 if (*input_line_pointer
== ','
2692 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2697 ++input_line_pointer
;
2698 e
= get_symbol_name (&string
);
2700 if (strcmp (string
, "nojumps") == 0)
2701 no_cond_jump_promotion
= 1;
2702 else if (strcmp (string
, "jumps") == 0)
2705 as_bad (_("no such architecture modifier: `%s'"), string
);
2707 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2713 enum bfd_architecture
2716 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2718 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2719 || flag_code
!= CODE_64BIT
)
2720 as_fatal (_("Intel L1OM is 64bit ELF only"));
2721 return bfd_arch_l1om
;
2723 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2725 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2726 || flag_code
!= CODE_64BIT
)
2727 as_fatal (_("Intel K1OM is 64bit ELF only"));
2728 return bfd_arch_k1om
;
2730 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2732 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2733 || flag_code
== CODE_64BIT
)
2734 as_fatal (_("Intel MCU is 32bit ELF only"));
2735 return bfd_arch_iamcu
;
2738 return bfd_arch_i386
;
2744 if (!strncmp (default_arch
, "x86_64", 6))
2746 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2748 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2749 || default_arch
[6] != '\0')
2750 as_fatal (_("Intel L1OM is 64bit ELF only"));
2751 return bfd_mach_l1om
;
2753 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2755 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2756 || default_arch
[6] != '\0')
2757 as_fatal (_("Intel K1OM is 64bit ELF only"));
2758 return bfd_mach_k1om
;
2760 else if (default_arch
[6] == '\0')
2761 return bfd_mach_x86_64
;
2763 return bfd_mach_x64_32
;
2765 else if (!strcmp (default_arch
, "i386")
2766 || !strcmp (default_arch
, "iamcu"))
2768 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2770 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2771 as_fatal (_("Intel MCU is 32bit ELF only"));
2772 return bfd_mach_i386_iamcu
;
2775 return bfd_mach_i386_i386
;
2778 as_fatal (_("unknown architecture"));
2784 const char *hash_err
;
2786 /* Support pseudo prefixes like {disp32}. */
2787 lex_type
['{'] = LEX_BEGIN_NAME
;
2789 /* Initialize op_hash hash table. */
2790 op_hash
= hash_new ();
2793 const insn_template
*optab
;
2794 templates
*core_optab
;
2796 /* Setup for loop. */
2798 core_optab
= XNEW (templates
);
2799 core_optab
->start
= optab
;
2804 if (optab
->name
== NULL
2805 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2807 /* different name --> ship out current template list;
2808 add to hash table; & begin anew. */
2809 core_optab
->end
= optab
;
2810 hash_err
= hash_insert (op_hash
,
2812 (void *) core_optab
);
2815 as_fatal (_("can't hash %s: %s"),
2819 if (optab
->name
== NULL
)
2821 core_optab
= XNEW (templates
);
2822 core_optab
->start
= optab
;
2827 /* Initialize reg_hash hash table. */
2828 reg_hash
= hash_new ();
2830 const reg_entry
*regtab
;
2831 unsigned int regtab_size
= i386_regtab_size
;
2833 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2835 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2837 as_fatal (_("can't hash %s: %s"),
2843 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2848 for (c
= 0; c
< 256; c
++)
2853 mnemonic_chars
[c
] = c
;
2854 register_chars
[c
] = c
;
2855 operand_chars
[c
] = c
;
2857 else if (ISLOWER (c
))
2859 mnemonic_chars
[c
] = c
;
2860 register_chars
[c
] = c
;
2861 operand_chars
[c
] = c
;
2863 else if (ISUPPER (c
))
2865 mnemonic_chars
[c
] = TOLOWER (c
);
2866 register_chars
[c
] = mnemonic_chars
[c
];
2867 operand_chars
[c
] = c
;
2869 else if (c
== '{' || c
== '}')
2871 mnemonic_chars
[c
] = c
;
2872 operand_chars
[c
] = c
;
2875 if (ISALPHA (c
) || ISDIGIT (c
))
2876 identifier_chars
[c
] = c
;
2879 identifier_chars
[c
] = c
;
2880 operand_chars
[c
] = c
;
2885 identifier_chars
['@'] = '@';
2888 identifier_chars
['?'] = '?';
2889 operand_chars
['?'] = '?';
2891 digit_chars
['-'] = '-';
2892 mnemonic_chars
['_'] = '_';
2893 mnemonic_chars
['-'] = '-';
2894 mnemonic_chars
['.'] = '.';
2895 identifier_chars
['_'] = '_';
2896 identifier_chars
['.'] = '.';
2898 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2899 operand_chars
[(unsigned char) *p
] = *p
;
2902 if (flag_code
== CODE_64BIT
)
2904 #if defined (OBJ_COFF) && defined (TE_PE)
2905 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2908 x86_dwarf2_return_column
= 16;
2910 x86_cie_data_alignment
= -8;
2914 x86_dwarf2_return_column
= 8;
2915 x86_cie_data_alignment
= -4;
2920 i386_print_statistics (FILE *file
)
2922 hash_print_statistics (file
, "i386 opcode", op_hash
);
2923 hash_print_statistics (file
, "i386 register", reg_hash
);
2928 /* Debugging routines for md_assemble. */
2929 static void pte (insn_template
*);
2930 static void pt (i386_operand_type
);
2931 static void pe (expressionS
*);
2932 static void ps (symbolS
*);
2935 pi (char *line
, i386_insn
*x
)
2939 fprintf (stdout
, "%s: template ", line
);
2941 fprintf (stdout
, " address: base %s index %s scale %x\n",
2942 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2943 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2944 x
->log2_scale_factor
);
2945 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2946 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2947 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2948 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2949 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2950 (x
->rex
& REX_W
) != 0,
2951 (x
->rex
& REX_R
) != 0,
2952 (x
->rex
& REX_X
) != 0,
2953 (x
->rex
& REX_B
) != 0);
2954 for (j
= 0; j
< x
->operands
; j
++)
2956 fprintf (stdout
, " #%d: ", j
+ 1);
2958 fprintf (stdout
, "\n");
2959 if (x
->types
[j
].bitfield
.reg
2960 || x
->types
[j
].bitfield
.regmmx
2961 || x
->types
[j
].bitfield
.regsimd
2962 || x
->types
[j
].bitfield
.sreg2
2963 || x
->types
[j
].bitfield
.sreg3
2964 || x
->types
[j
].bitfield
.control
2965 || x
->types
[j
].bitfield
.debug
2966 || x
->types
[j
].bitfield
.test
)
2967 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2968 if (operand_type_check (x
->types
[j
], imm
))
2970 if (operand_type_check (x
->types
[j
], disp
))
2971 pe (x
->op
[j
].disps
);
2976 pte (insn_template
*t
)
2979 fprintf (stdout
, " %d operands ", t
->operands
);
2980 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2981 if (t
->extension_opcode
!= None
)
2982 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2983 if (t
->opcode_modifier
.d
)
2984 fprintf (stdout
, "D");
2985 if (t
->opcode_modifier
.w
)
2986 fprintf (stdout
, "W");
2987 fprintf (stdout
, "\n");
2988 for (j
= 0; j
< t
->operands
; j
++)
2990 fprintf (stdout
, " #%d type ", j
+ 1);
2991 pt (t
->operand_types
[j
]);
2992 fprintf (stdout
, "\n");
2999 fprintf (stdout
, " operation %d\n", e
->X_op
);
3000 fprintf (stdout
, " add_number %ld (%lx)\n",
3001 (long) e
->X_add_number
, (long) e
->X_add_number
);
3002 if (e
->X_add_symbol
)
3004 fprintf (stdout
, " add_symbol ");
3005 ps (e
->X_add_symbol
);
3006 fprintf (stdout
, "\n");
3010 fprintf (stdout
, " op_symbol ");
3011 ps (e
->X_op_symbol
);
3012 fprintf (stdout
, "\n");
3019 fprintf (stdout
, "%s type %s%s",
3021 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3022 segment_name (S_GET_SEGMENT (s
)));
3025 static struct type_name
3027 i386_operand_type mask
;
3030 const type_names
[] =
3032 { OPERAND_TYPE_REG8
, "r8" },
3033 { OPERAND_TYPE_REG16
, "r16" },
3034 { OPERAND_TYPE_REG32
, "r32" },
3035 { OPERAND_TYPE_REG64
, "r64" },
3036 { OPERAND_TYPE_IMM8
, "i8" },
3037 { OPERAND_TYPE_IMM8
, "i8s" },
3038 { OPERAND_TYPE_IMM16
, "i16" },
3039 { OPERAND_TYPE_IMM32
, "i32" },
3040 { OPERAND_TYPE_IMM32S
, "i32s" },
3041 { OPERAND_TYPE_IMM64
, "i64" },
3042 { OPERAND_TYPE_IMM1
, "i1" },
3043 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3044 { OPERAND_TYPE_DISP8
, "d8" },
3045 { OPERAND_TYPE_DISP16
, "d16" },
3046 { OPERAND_TYPE_DISP32
, "d32" },
3047 { OPERAND_TYPE_DISP32S
, "d32s" },
3048 { OPERAND_TYPE_DISP64
, "d64" },
3049 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3050 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3051 { OPERAND_TYPE_CONTROL
, "control reg" },
3052 { OPERAND_TYPE_TEST
, "test reg" },
3053 { OPERAND_TYPE_DEBUG
, "debug reg" },
3054 { OPERAND_TYPE_FLOATREG
, "FReg" },
3055 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3056 { OPERAND_TYPE_SREG2
, "SReg2" },
3057 { OPERAND_TYPE_SREG3
, "SReg3" },
3058 { OPERAND_TYPE_ACC
, "Acc" },
3059 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3060 { OPERAND_TYPE_REGMMX
, "rMMX" },
3061 { OPERAND_TYPE_REGXMM
, "rXMM" },
3062 { OPERAND_TYPE_REGYMM
, "rYMM" },
3063 { OPERAND_TYPE_REGZMM
, "rZMM" },
3064 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3065 { OPERAND_TYPE_ESSEG
, "es" },
3069 pt (i386_operand_type t
)
3072 i386_operand_type a
;
3074 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3076 a
= operand_type_and (t
, type_names
[j
].mask
);
3077 if (!operand_type_all_zero (&a
))
3078 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3083 #endif /* DEBUG386 */
3085 static bfd_reloc_code_real_type
3086 reloc (unsigned int size
,
3089 bfd_reloc_code_real_type other
)
3091 if (other
!= NO_RELOC
)
3093 reloc_howto_type
*rel
;
3098 case BFD_RELOC_X86_64_GOT32
:
3099 return BFD_RELOC_X86_64_GOT64
;
3101 case BFD_RELOC_X86_64_GOTPLT64
:
3102 return BFD_RELOC_X86_64_GOTPLT64
;
3104 case BFD_RELOC_X86_64_PLTOFF64
:
3105 return BFD_RELOC_X86_64_PLTOFF64
;
3107 case BFD_RELOC_X86_64_GOTPC32
:
3108 other
= BFD_RELOC_X86_64_GOTPC64
;
3110 case BFD_RELOC_X86_64_GOTPCREL
:
3111 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3113 case BFD_RELOC_X86_64_TPOFF32
:
3114 other
= BFD_RELOC_X86_64_TPOFF64
;
3116 case BFD_RELOC_X86_64_DTPOFF32
:
3117 other
= BFD_RELOC_X86_64_DTPOFF64
;
3123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3124 if (other
== BFD_RELOC_SIZE32
)
3127 other
= BFD_RELOC_SIZE64
;
3130 as_bad (_("there are no pc-relative size relocations"));
3136 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3137 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3140 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3142 as_bad (_("unknown relocation (%u)"), other
);
3143 else if (size
!= bfd_get_reloc_size (rel
))
3144 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3145 bfd_get_reloc_size (rel
),
3147 else if (pcrel
&& !rel
->pc_relative
)
3148 as_bad (_("non-pc-relative relocation for pc-relative field"));
3149 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3151 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3153 as_bad (_("relocated field and relocation type differ in signedness"));
3162 as_bad (_("there are no unsigned pc-relative relocations"));
3165 case 1: return BFD_RELOC_8_PCREL
;
3166 case 2: return BFD_RELOC_16_PCREL
;
3167 case 4: return BFD_RELOC_32_PCREL
;
3168 case 8: return BFD_RELOC_64_PCREL
;
3170 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3177 case 4: return BFD_RELOC_X86_64_32S
;
3182 case 1: return BFD_RELOC_8
;
3183 case 2: return BFD_RELOC_16
;
3184 case 4: return BFD_RELOC_32
;
3185 case 8: return BFD_RELOC_64
;
3187 as_bad (_("cannot do %s %u byte relocation"),
3188 sign
> 0 ? "signed" : "unsigned", size
);
3194 /* Here we decide which fixups can be adjusted to make them relative to
3195 the beginning of the section instead of the symbol. Basically we need
3196 to make sure that the dynamic relocations are done correctly, so in
3197 some cases we force the original symbol to be used. */
3200 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3206 /* Don't adjust pc-relative references to merge sections in 64-bit
3208 if (use_rela_relocations
3209 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3213 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3214 and changed later by validate_fix. */
3215 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3216 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3219 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3220 for size relocations. */
3221 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3222 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3223 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3224 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3225 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3226 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3249 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3250 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3251 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3252 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3253 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3260 intel_float_operand (const char *mnemonic
)
3262 /* Note that the value returned is meaningful only for opcodes with (memory)
3263 operands, hence the code here is free to improperly handle opcodes that
3264 have no operands (for better performance and smaller code). */
3266 if (mnemonic
[0] != 'f')
3267 return 0; /* non-math */
3269 switch (mnemonic
[1])
3271 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3272 the fs segment override prefix not currently handled because no
3273 call path can make opcodes without operands get here */
3275 return 2 /* integer op */;
3277 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3278 return 3; /* fldcw/fldenv */
3281 if (mnemonic
[2] != 'o' /* fnop */)
3282 return 3; /* non-waiting control op */
3285 if (mnemonic
[2] == 's')
3286 return 3; /* frstor/frstpm */
3289 if (mnemonic
[2] == 'a')
3290 return 3; /* fsave */
3291 if (mnemonic
[2] == 't')
3293 switch (mnemonic
[3])
3295 case 'c': /* fstcw */
3296 case 'd': /* fstdw */
3297 case 'e': /* fstenv */
3298 case 's': /* fsts[gw] */
3304 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3305 return 0; /* fxsave/fxrstor are not really math ops */
3312 /* Build the VEX prefix. */
3315 build_vex_prefix (const insn_template
*t
)
3317 unsigned int register_specifier
;
3318 unsigned int implied_prefix
;
3319 unsigned int vector_length
;
3321 /* Check register specifier. */
3322 if (i
.vex
.register_specifier
)
3324 register_specifier
=
3325 ~register_number (i
.vex
.register_specifier
) & 0xf;
3326 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3329 register_specifier
= 0xf;
3331 /* Use 2-byte VEX prefix by swapping destination and source
3333 if (i
.vec_encoding
!= vex_encoding_vex3
3334 && i
.dir_encoding
== dir_encoding_default
3335 && i
.operands
== i
.reg_operands
3336 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3337 && i
.tm
.opcode_modifier
.load
3340 unsigned int xchg
= i
.operands
- 1;
3341 union i386_op temp_op
;
3342 i386_operand_type temp_type
;
3344 temp_type
= i
.types
[xchg
];
3345 i
.types
[xchg
] = i
.types
[0];
3346 i
.types
[0] = temp_type
;
3347 temp_op
= i
.op
[xchg
];
3348 i
.op
[xchg
] = i
.op
[0];
3351 gas_assert (i
.rm
.mode
== 3);
3355 i
.rm
.regmem
= i
.rm
.reg
;
3358 /* Use the next insn. */
3362 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3363 vector_length
= avxscalar
;
3364 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3370 /* Determine vector length from the last multi-length vector
3373 for (op
= t
->operands
; op
--;)
3374 if (t
->operand_types
[op
].bitfield
.xmmword
3375 && t
->operand_types
[op
].bitfield
.ymmword
3376 && i
.types
[op
].bitfield
.ymmword
)
3383 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3388 case DATA_PREFIX_OPCODE
:
3391 case REPE_PREFIX_OPCODE
:
3394 case REPNE_PREFIX_OPCODE
:
3401 /* Use 2-byte VEX prefix if possible. */
3402 if (i
.vec_encoding
!= vex_encoding_vex3
3403 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3404 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3405 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3407 /* 2-byte VEX prefix. */
3411 i
.vex
.bytes
[0] = 0xc5;
3413 /* Check the REX.R bit. */
3414 r
= (i
.rex
& REX_R
) ? 0 : 1;
3415 i
.vex
.bytes
[1] = (r
<< 7
3416 | register_specifier
<< 3
3417 | vector_length
<< 2
3422 /* 3-byte VEX prefix. */
3427 switch (i
.tm
.opcode_modifier
.vexopcode
)
3431 i
.vex
.bytes
[0] = 0xc4;
3435 i
.vex
.bytes
[0] = 0xc4;
3439 i
.vex
.bytes
[0] = 0xc4;
3443 i
.vex
.bytes
[0] = 0x8f;
3447 i
.vex
.bytes
[0] = 0x8f;
3451 i
.vex
.bytes
[0] = 0x8f;
3457 /* The high 3 bits of the second VEX byte are 1's compliment
3458 of RXB bits from REX. */
3459 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3461 /* Check the REX.W bit. */
3462 w
= (i
.rex
& REX_W
) ? 1 : 0;
3463 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3466 i
.vex
.bytes
[2] = (w
<< 7
3467 | register_specifier
<< 3
3468 | vector_length
<< 2
3473 static INLINE bfd_boolean
3474 is_evex_encoding (const insn_template
*t
)
3476 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3477 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3478 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3481 static INLINE bfd_boolean
3482 is_any_vex_encoding (const insn_template
*t
)
3484 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3485 || is_evex_encoding (t
);
3488 /* Build the EVEX prefix. */
3491 build_evex_prefix (void)
3493 unsigned int register_specifier
;
3494 unsigned int implied_prefix
;
3496 rex_byte vrex_used
= 0;
3498 /* Check register specifier. */
3499 if (i
.vex
.register_specifier
)
3501 gas_assert ((i
.vrex
& REX_X
) == 0);
3503 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3504 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3505 register_specifier
+= 8;
3506 /* The upper 16 registers are encoded in the fourth byte of the
3508 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3509 i
.vex
.bytes
[3] = 0x8;
3510 register_specifier
= ~register_specifier
& 0xf;
3514 register_specifier
= 0xf;
3516 /* Encode upper 16 vector index register in the fourth byte of
3518 if (!(i
.vrex
& REX_X
))
3519 i
.vex
.bytes
[3] = 0x8;
3524 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE
:
3532 case REPE_PREFIX_OPCODE
:
3535 case REPNE_PREFIX_OPCODE
:
3542 /* 4 byte EVEX prefix. */
3544 i
.vex
.bytes
[0] = 0x62;
3547 switch (i
.tm
.opcode_modifier
.vexopcode
)
3563 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3565 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3567 /* The fifth bit of the second EVEX byte is 1's compliment of the
3568 REX_R bit in VREX. */
3569 if (!(i
.vrex
& REX_R
))
3570 i
.vex
.bytes
[1] |= 0x10;
3574 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3576 /* When all operands are registers, the REX_X bit in REX is not
3577 used. We reuse it to encode the upper 16 registers, which is
3578 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3579 as 1's compliment. */
3580 if ((i
.vrex
& REX_B
))
3583 i
.vex
.bytes
[1] &= ~0x40;
3587 /* EVEX instructions shouldn't need the REX prefix. */
3588 i
.vrex
&= ~vrex_used
;
3589 gas_assert (i
.vrex
== 0);
3591 /* Check the REX.W bit. */
3592 w
= (i
.rex
& REX_W
) ? 1 : 0;
3593 if (i
.tm
.opcode_modifier
.vexw
)
3595 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3598 /* If w is not set it means we are dealing with WIG instruction. */
3601 if (evexwig
== evexw1
)
3605 /* Encode the U bit. */
3606 implied_prefix
|= 0x4;
3608 /* The third byte of the EVEX prefix. */
3609 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3611 /* The fourth byte of the EVEX prefix. */
3612 /* The zeroing-masking bit. */
3613 if (i
.mask
&& i
.mask
->zeroing
)
3614 i
.vex
.bytes
[3] |= 0x80;
3616 /* Don't always set the broadcast bit if there is no RC. */
3619 /* Encode the vector length. */
3620 unsigned int vec_length
;
3622 if (!i
.tm
.opcode_modifier
.evex
3623 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3627 /* Determine vector length from the last multi-length vector
3630 for (op
= i
.operands
; op
--;)
3631 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3632 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3633 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3635 if (i
.types
[op
].bitfield
.zmmword
)
3637 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3640 else if (i
.types
[op
].bitfield
.ymmword
)
3642 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3645 else if (i
.types
[op
].bitfield
.xmmword
)
3647 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3650 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3652 switch (i
.broadcast
->bytes
)
3655 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3658 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3661 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3670 if (op
>= MAX_OPERANDS
)
3674 switch (i
.tm
.opcode_modifier
.evex
)
3676 case EVEXLIG
: /* LL' is ignored */
3677 vec_length
= evexlig
<< 5;
3680 vec_length
= 0 << 5;
3683 vec_length
= 1 << 5;
3686 vec_length
= 2 << 5;
3692 i
.vex
.bytes
[3] |= vec_length
;
3693 /* Encode the broadcast bit. */
3695 i
.vex
.bytes
[3] |= 0x10;
3699 if (i
.rounding
->type
!= saeonly
)
3700 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3702 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3705 if (i
.mask
&& i
.mask
->mask
)
3706 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3710 process_immext (void)
3714 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3717 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3718 with an opcode suffix which is coded in the same place as an
3719 8-bit immediate field would be.
3720 Here we check those operands and remove them afterwards. */
3723 for (x
= 0; x
< i
.operands
; x
++)
3724 if (register_number (i
.op
[x
].regs
) != x
)
3725 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3726 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3732 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3734 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3735 suffix which is coded in the same place as an 8-bit immediate
3737 Here we check those operands and remove them afterwards. */
3740 if (i
.operands
!= 3)
3743 for (x
= 0; x
< 2; x
++)
3744 if (register_number (i
.op
[x
].regs
) != x
)
3745 goto bad_register_operand
;
3747 /* Check for third operand for mwaitx/monitorx insn. */
3748 if (register_number (i
.op
[x
].regs
)
3749 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3751 bad_register_operand
:
3752 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3753 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3760 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3761 which is coded in the same place as an 8-bit immediate field
3762 would be. Here we fake an 8-bit immediate operand from the
3763 opcode suffix stored in tm.extension_opcode.
3765 AVX instructions also use this encoding, for some of
3766 3 argument instructions. */
3768 gas_assert (i
.imm_operands
<= 1
3770 || (is_any_vex_encoding (&i
.tm
)
3771 && i
.operands
<= 4)));
3773 exp
= &im_expressions
[i
.imm_operands
++];
3774 i
.op
[i
.operands
].imms
= exp
;
3775 i
.types
[i
.operands
] = imm8
;
3777 exp
->X_op
= O_constant
;
3778 exp
->X_add_number
= i
.tm
.extension_opcode
;
3779 i
.tm
.extension_opcode
= None
;
3786 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3791 as_bad (_("invalid instruction `%s' after `%s'"),
3792 i
.tm
.name
, i
.hle_prefix
);
3795 if (i
.prefix
[LOCK_PREFIX
])
3797 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3801 case HLEPrefixRelease
:
3802 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3804 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3808 if (i
.mem_operands
== 0
3809 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3811 as_bad (_("memory destination needed for instruction `%s'"
3812 " after `xrelease'"), i
.tm
.name
);
3819 /* Try the shortest encoding by shortening operand size. */
3822 optimize_encoding (void)
3826 if (optimize_for_space
3827 && i
.reg_operands
== 1
3828 && i
.imm_operands
== 1
3829 && !i
.types
[1].bitfield
.byte
3830 && i
.op
[0].imms
->X_op
== O_constant
3831 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3832 && ((i
.tm
.base_opcode
== 0xa8
3833 && i
.tm
.extension_opcode
== None
)
3834 || (i
.tm
.base_opcode
== 0xf6
3835 && i
.tm
.extension_opcode
== 0x0)))
3838 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3840 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3841 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3843 i
.types
[1].bitfield
.byte
= 1;
3844 /* Ignore the suffix. */
3846 if (base_regnum
>= 4
3847 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3849 /* Handle SP, BP, SI and DI registers. */
3850 if (i
.types
[1].bitfield
.word
)
3852 else if (i
.types
[1].bitfield
.dword
)
3860 else if (flag_code
== CODE_64BIT
3861 && ((i
.types
[1].bitfield
.qword
3862 && i
.reg_operands
== 1
3863 && i
.imm_operands
== 1
3864 && i
.op
[0].imms
->X_op
== O_constant
3865 && ((i
.tm
.base_opcode
== 0xb0
3866 && i
.tm
.extension_opcode
== None
3867 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3868 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3869 && (((i
.tm
.base_opcode
== 0x24
3870 || i
.tm
.base_opcode
== 0xa8)
3871 && i
.tm
.extension_opcode
== None
)
3872 || (i
.tm
.base_opcode
== 0x80
3873 && i
.tm
.extension_opcode
== 0x4)
3874 || ((i
.tm
.base_opcode
== 0xf6
3875 || i
.tm
.base_opcode
== 0xc6)
3876 && i
.tm
.extension_opcode
== 0x0)))))
3877 || (i
.types
[0].bitfield
.qword
3878 && ((i
.reg_operands
== 2
3879 && i
.op
[0].regs
== i
.op
[1].regs
3880 && ((i
.tm
.base_opcode
== 0x30
3881 || i
.tm
.base_opcode
== 0x28)
3882 && i
.tm
.extension_opcode
== None
))
3883 || (i
.reg_operands
== 1
3885 && i
.tm
.base_opcode
== 0x30
3886 && i
.tm
.extension_opcode
== None
)))))
3889 andq $imm31, %r64 -> andl $imm31, %r32
3890 testq $imm31, %r64 -> testl $imm31, %r32
3891 xorq %r64, %r64 -> xorl %r32, %r32
3892 subq %r64, %r64 -> subl %r32, %r32
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3896 i
.tm
.opcode_modifier
.norex64
= 1;
3897 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3900 movq $imm31, %r64 -> movl $imm31, %r32
3901 movq $imm32, %r64 -> movl $imm32, %r32
3903 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3904 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3905 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3906 i
.types
[0].bitfield
.imm32
= 1;
3907 i
.types
[0].bitfield
.imm32s
= 0;
3908 i
.types
[0].bitfield
.imm64
= 0;
3909 i
.types
[1].bitfield
.dword
= 1;
3910 i
.types
[1].bitfield
.qword
= 0;
3911 if (i
.tm
.base_opcode
== 0xc6)
3914 movq $imm31, %r64 -> movl $imm31, %r32
3916 i
.tm
.base_opcode
= 0xb0;
3917 i
.tm
.extension_opcode
= None
;
3918 i
.tm
.opcode_modifier
.shortform
= 1;
3919 i
.tm
.opcode_modifier
.modrm
= 0;
3923 else if (optimize
> 1
3924 && i
.reg_operands
== 3
3925 && i
.op
[0].regs
== i
.op
[1].regs
3926 && !i
.types
[2].bitfield
.xmmword
3927 && (i
.tm
.opcode_modifier
.vex
3928 || ((!i
.mask
|| i
.mask
->zeroing
)
3930 && is_evex_encoding (&i
.tm
)
3931 && (i
.vec_encoding
!= vex_encoding_evex
3932 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3933 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3934 && i
.types
[2].bitfield
.ymmword
)
3935 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3936 && ((i
.tm
.base_opcode
== 0x55
3937 || i
.tm
.base_opcode
== 0x6655
3938 || i
.tm
.base_opcode
== 0x66df
3939 || i
.tm
.base_opcode
== 0x57
3940 || i
.tm
.base_opcode
== 0x6657
3941 || i
.tm
.base_opcode
== 0x66ef
3942 || i
.tm
.base_opcode
== 0x66f8
3943 || i
.tm
.base_opcode
== 0x66f9
3944 || i
.tm
.base_opcode
== 0x66fa
3945 || i
.tm
.base_opcode
== 0x66fb)
3946 && i
.tm
.extension_opcode
== None
))
3949 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3951 EVEX VOP %zmmM, %zmmM, %zmmN
3952 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3953 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3954 EVEX VOP %ymmM, %ymmM, %ymmN
3955 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3956 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3957 VEX VOP %ymmM, %ymmM, %ymmN
3958 -> VEX VOP %xmmM, %xmmM, %xmmN
3959 VOP, one of vpandn and vpxor:
3960 VEX VOP %ymmM, %ymmM, %ymmN
3961 -> VEX VOP %xmmM, %xmmM, %xmmN
3962 VOP, one of vpandnd and vpandnq:
3963 EVEX VOP %zmmM, %zmmM, %zmmN
3964 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3965 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3966 EVEX VOP %ymmM, %ymmM, %ymmN
3967 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3968 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3969 VOP, one of vpxord and vpxorq:
3970 EVEX VOP %zmmM, %zmmM, %zmmN
3971 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3972 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3973 EVEX VOP %ymmM, %ymmM, %ymmN
3974 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3975 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3977 if (is_evex_encoding (&i
.tm
))
3979 if (i
.vec_encoding
== vex_encoding_evex
)
3980 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3983 i
.tm
.opcode_modifier
.vex
= VEX128
;
3984 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3985 i
.tm
.opcode_modifier
.evex
= 0;
3989 i
.tm
.opcode_modifier
.vex
= VEX128
;
3991 if (i
.tm
.opcode_modifier
.vex
)
3992 for (j
= 0; j
< 3; j
++)
3994 i
.types
[j
].bitfield
.xmmword
= 1;
3995 i
.types
[j
].bitfield
.ymmword
= 0;
4000 /* This is the guts of the machine-dependent assembler. LINE points to a
4001 machine dependent instruction. This function is supposed to emit
4002 the frags/bytes it assembles to. */
4005 md_assemble (char *line
)
4008 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4009 const insn_template
*t
;
4011 /* Initialize globals. */
4012 memset (&i
, '\0', sizeof (i
));
4013 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4014 i
.reloc
[j
] = NO_RELOC
;
4015 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4016 memset (im_expressions
, '\0', sizeof (im_expressions
));
4017 save_stack_p
= save_stack
;
4019 /* First parse an instruction mnemonic & call i386_operand for the operands.
4020 We assume that the scrubber has arranged it so that line[0] is the valid
4021 start of a (possibly prefixed) mnemonic. */
4023 line
= parse_insn (line
, mnemonic
);
4026 mnem_suffix
= i
.suffix
;
4028 line
= parse_operands (line
, mnemonic
);
4030 xfree (i
.memop1_string
);
4031 i
.memop1_string
= NULL
;
4035 /* Now we've parsed the mnemonic into a set of templates, and have the
4036 operands at hand. */
4038 /* All intel opcodes have reversed operands except for "bound" and
4039 "enter". We also don't reverse intersegment "jmp" and "call"
4040 instructions with 2 immediate operands so that the immediate segment
4041 precedes the offset, as it does when in AT&T mode. */
4044 && (strcmp (mnemonic
, "bound") != 0)
4045 && (strcmp (mnemonic
, "invlpga") != 0)
4046 && !(operand_type_check (i
.types
[0], imm
)
4047 && operand_type_check (i
.types
[1], imm
)))
4050 /* The order of the immediates should be reversed
4051 for 2 immediates extrq and insertq instructions */
4052 if (i
.imm_operands
== 2
4053 && (strcmp (mnemonic
, "extrq") == 0
4054 || strcmp (mnemonic
, "insertq") == 0))
4055 swap_2_operands (0, 1);
4060 /* Don't optimize displacement for movabs since it only takes 64bit
4063 && i
.disp_encoding
!= disp_encoding_32bit
4064 && (flag_code
!= CODE_64BIT
4065 || strcmp (mnemonic
, "movabs") != 0))
4068 /* Next, we find a template that matches the given insn,
4069 making sure the overlap of the given operands types is consistent
4070 with the template operand types. */
4072 if (!(t
= match_template (mnem_suffix
)))
4075 if (sse_check
!= check_none
4076 && !i
.tm
.opcode_modifier
.noavx
4077 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4078 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4079 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4080 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4081 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4082 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4083 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4084 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4085 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4086 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4088 (sse_check
== check_warning
4090 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4093 /* Zap movzx and movsx suffix. The suffix has been set from
4094 "word ptr" or "byte ptr" on the source operand in Intel syntax
4095 or extracted from mnemonic in AT&T syntax. But we'll use
4096 the destination register to choose the suffix for encoding. */
4097 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4099 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4100 there is no suffix, the default will be byte extension. */
4101 if (i
.reg_operands
!= 2
4104 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4109 if (i
.tm
.opcode_modifier
.fwait
)
4110 if (!add_prefix (FWAIT_OPCODE
))
4113 /* Check if REP prefix is OK. */
4114 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4116 as_bad (_("invalid instruction `%s' after `%s'"),
4117 i
.tm
.name
, i
.rep_prefix
);
4121 /* Check for lock without a lockable instruction. Destination operand
4122 must be memory unless it is xchg (0x86). */
4123 if (i
.prefix
[LOCK_PREFIX
]
4124 && (!i
.tm
.opcode_modifier
.islockable
4125 || i
.mem_operands
== 0
4126 || (i
.tm
.base_opcode
!= 0x86
4127 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4129 as_bad (_("expecting lockable instruction after `lock'"));
4133 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4134 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4136 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4140 /* Check if HLE prefix is OK. */
4141 if (i
.hle_prefix
&& !check_hle ())
4144 /* Check BND prefix. */
4145 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4146 as_bad (_("expecting valid branch instruction after `bnd'"));
4148 /* Check NOTRACK prefix. */
4149 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4150 as_bad (_("expecting indirect branch instruction after `notrack'"));
4152 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4154 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4155 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4156 else if (flag_code
!= CODE_16BIT
4157 ? i
.prefix
[ADDR_PREFIX
]
4158 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4159 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4162 /* Insert BND prefix. */
4163 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4165 if (!i
.prefix
[BND_PREFIX
])
4166 add_prefix (BND_PREFIX_OPCODE
);
4167 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4169 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4170 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4174 /* Check string instruction segment overrides. */
4175 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4177 if (!check_string ())
4179 i
.disp_operands
= 0;
4182 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4183 optimize_encoding ();
4185 if (!process_suffix ())
4188 /* Update operand types. */
4189 for (j
= 0; j
< i
.operands
; j
++)
4190 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4192 /* Make still unresolved immediate matches conform to size of immediate
4193 given in i.suffix. */
4194 if (!finalize_imm ())
4197 if (i
.types
[0].bitfield
.imm1
)
4198 i
.imm_operands
= 0; /* kludge for shift insns. */
4200 /* We only need to check those implicit registers for instructions
4201 with 3 operands or less. */
4202 if (i
.operands
<= 3)
4203 for (j
= 0; j
< i
.operands
; j
++)
4204 if (i
.types
[j
].bitfield
.inoutportreg
4205 || i
.types
[j
].bitfield
.shiftcount
4206 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4209 /* ImmExt should be processed after SSE2AVX. */
4210 if (!i
.tm
.opcode_modifier
.sse2avx
4211 && i
.tm
.opcode_modifier
.immext
)
4214 /* For insns with operands there are more diddles to do to the opcode. */
4217 if (!process_operands ())
4220 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4222 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4223 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4226 if (is_any_vex_encoding (&i
.tm
))
4228 if (flag_code
== CODE_16BIT
)
4230 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4235 if (i
.tm
.opcode_modifier
.vex
)
4236 build_vex_prefix (t
);
4238 build_evex_prefix ();
4241 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4242 instructions may define INT_OPCODE as well, so avoid this corner
4243 case for those instructions that use MODRM. */
4244 if (i
.tm
.base_opcode
== INT_OPCODE
4245 && !i
.tm
.opcode_modifier
.modrm
4246 && i
.op
[0].imms
->X_add_number
== 3)
4248 i
.tm
.base_opcode
= INT3_OPCODE
;
4252 if ((i
.tm
.opcode_modifier
.jump
4253 || i
.tm
.opcode_modifier
.jumpbyte
4254 || i
.tm
.opcode_modifier
.jumpdword
)
4255 && i
.op
[0].disps
->X_op
== O_constant
)
4257 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4258 the absolute address given by the constant. Since ix86 jumps and
4259 calls are pc relative, we need to generate a reloc. */
4260 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4261 i
.op
[0].disps
->X_op
= O_symbol
;
4264 if (i
.tm
.opcode_modifier
.rex64
)
4267 /* For 8 bit registers we need an empty rex prefix. Also if the
4268 instruction already has a prefix, we need to convert old
4269 registers to new ones. */
4271 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4272 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4273 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4274 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4275 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4276 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4281 i
.rex
|= REX_OPCODE
;
4282 for (x
= 0; x
< 2; x
++)
4284 /* Look for 8 bit operand that uses old registers. */
4285 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4286 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4288 /* In case it is "hi" register, give up. */
4289 if (i
.op
[x
].regs
->reg_num
> 3)
4290 as_bad (_("can't encode register '%s%s' in an "
4291 "instruction requiring REX prefix."),
4292 register_prefix
, i
.op
[x
].regs
->reg_name
);
4294 /* Otherwise it is equivalent to the extended register.
4295 Since the encoding doesn't change this is merely
4296 cosmetic cleanup for debug output. */
4298 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4303 if (i
.rex
== 0 && i
.rex_encoding
)
4305 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4306 that uses legacy register. If it is "hi" register, don't add
4307 the REX_OPCODE byte. */
4309 for (x
= 0; x
< 2; x
++)
4310 if (i
.types
[x
].bitfield
.reg
4311 && i
.types
[x
].bitfield
.byte
4312 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4313 && i
.op
[x
].regs
->reg_num
> 3)
4315 i
.rex_encoding
= FALSE
;
4324 add_prefix (REX_OPCODE
| i
.rex
);
4326 /* We are ready to output the insn. */
4331 parse_insn (char *line
, char *mnemonic
)
4334 char *token_start
= l
;
4337 const insn_template
*t
;
4343 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4348 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4350 as_bad (_("no such instruction: `%s'"), token_start
);
4355 if (!is_space_char (*l
)
4356 && *l
!= END_OF_INSN
4358 || (*l
!= PREFIX_SEPARATOR
4361 as_bad (_("invalid character %s in mnemonic"),
4362 output_invalid (*l
));
4365 if (token_start
== l
)
4367 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4368 as_bad (_("expecting prefix; got nothing"));
4370 as_bad (_("expecting mnemonic; got nothing"));
4374 /* Look up instruction (or prefix) via hash table. */
4375 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4377 if (*l
!= END_OF_INSN
4378 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4379 && current_templates
4380 && current_templates
->start
->opcode_modifier
.isprefix
)
4382 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4384 as_bad ((flag_code
!= CODE_64BIT
4385 ? _("`%s' is only supported in 64-bit mode")
4386 : _("`%s' is not supported in 64-bit mode")),
4387 current_templates
->start
->name
);
4390 /* If we are in 16-bit mode, do not allow addr16 or data16.
4391 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4392 if ((current_templates
->start
->opcode_modifier
.size16
4393 || current_templates
->start
->opcode_modifier
.size32
)
4394 && flag_code
!= CODE_64BIT
4395 && (current_templates
->start
->opcode_modifier
.size32
4396 ^ (flag_code
== CODE_16BIT
)))
4398 as_bad (_("redundant %s prefix"),
4399 current_templates
->start
->name
);
4402 if (current_templates
->start
->opcode_length
== 0)
4404 /* Handle pseudo prefixes. */
4405 switch (current_templates
->start
->base_opcode
)
4409 i
.disp_encoding
= disp_encoding_8bit
;
4413 i
.disp_encoding
= disp_encoding_32bit
;
4417 i
.dir_encoding
= dir_encoding_load
;
4421 i
.dir_encoding
= dir_encoding_store
;
4425 i
.vec_encoding
= vex_encoding_vex2
;
4429 i
.vec_encoding
= vex_encoding_vex3
;
4433 i
.vec_encoding
= vex_encoding_evex
;
4437 i
.rex_encoding
= TRUE
;
4441 i
.no_optimize
= TRUE
;
4449 /* Add prefix, checking for repeated prefixes. */
4450 switch (add_prefix (current_templates
->start
->base_opcode
))
4455 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4456 i
.notrack_prefix
= current_templates
->start
->name
;
4459 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4460 i
.hle_prefix
= current_templates
->start
->name
;
4461 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4462 i
.bnd_prefix
= current_templates
->start
->name
;
4464 i
.rep_prefix
= current_templates
->start
->name
;
4470 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4477 if (!current_templates
)
4479 /* Check if we should swap operand or force 32bit displacement in
4481 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4482 i
.dir_encoding
= dir_encoding_store
;
4483 else if (mnem_p
- 3 == dot_p
4486 i
.disp_encoding
= disp_encoding_8bit
;
4487 else if (mnem_p
- 4 == dot_p
4491 i
.disp_encoding
= disp_encoding_32bit
;
4496 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4499 if (!current_templates
)
4502 /* See if we can get a match by trimming off a suffix. */
4505 case WORD_MNEM_SUFFIX
:
4506 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4507 i
.suffix
= SHORT_MNEM_SUFFIX
;
4510 case BYTE_MNEM_SUFFIX
:
4511 case QWORD_MNEM_SUFFIX
:
4512 i
.suffix
= mnem_p
[-1];
4514 current_templates
= (const templates
*) hash_find (op_hash
,
4517 case SHORT_MNEM_SUFFIX
:
4518 case LONG_MNEM_SUFFIX
:
4521 i
.suffix
= mnem_p
[-1];
4523 current_templates
= (const templates
*) hash_find (op_hash
,
4532 if (intel_float_operand (mnemonic
) == 1)
4533 i
.suffix
= SHORT_MNEM_SUFFIX
;
4535 i
.suffix
= LONG_MNEM_SUFFIX
;
4537 current_templates
= (const templates
*) hash_find (op_hash
,
4542 if (!current_templates
)
4544 as_bad (_("no such instruction: `%s'"), token_start
);
4549 if (current_templates
->start
->opcode_modifier
.jump
4550 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4552 /* Check for a branch hint. We allow ",pt" and ",pn" for
4553 predict taken and predict not taken respectively.
4554 I'm not sure that branch hints actually do anything on loop
4555 and jcxz insns (JumpByte) for current Pentium4 chips. They
4556 may work in the future and it doesn't hurt to accept them
4558 if (l
[0] == ',' && l
[1] == 'p')
4562 if (!add_prefix (DS_PREFIX_OPCODE
))
4566 else if (l
[2] == 'n')
4568 if (!add_prefix (CS_PREFIX_OPCODE
))
4574 /* Any other comma loses. */
4577 as_bad (_("invalid character %s in mnemonic"),
4578 output_invalid (*l
));
4582 /* Check if instruction is supported on specified architecture. */
4584 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4586 supported
|= cpu_flags_match (t
);
4587 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4589 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4590 as_warn (_("use .code16 to ensure correct addressing mode"));
4596 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4597 as_bad (flag_code
== CODE_64BIT
4598 ? _("`%s' is not supported in 64-bit mode")
4599 : _("`%s' is only supported in 64-bit mode"),
4600 current_templates
->start
->name
);
4602 as_bad (_("`%s' is not supported on `%s%s'"),
4603 current_templates
->start
->name
,
4604 cpu_arch_name
? cpu_arch_name
: default_arch
,
4605 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4611 parse_operands (char *l
, const char *mnemonic
)
4615 /* 1 if operand is pending after ','. */
4616 unsigned int expecting_operand
= 0;
4618 /* Non-zero if operand parens not balanced. */
4619 unsigned int paren_not_balanced
;
4621 while (*l
!= END_OF_INSN
)
4623 /* Skip optional white space before operand. */
4624 if (is_space_char (*l
))
4626 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4628 as_bad (_("invalid character %s before operand %d"),
4629 output_invalid (*l
),
4633 token_start
= l
; /* After white space. */
4634 paren_not_balanced
= 0;
4635 while (paren_not_balanced
|| *l
!= ',')
4637 if (*l
== END_OF_INSN
)
4639 if (paren_not_balanced
)
4642 as_bad (_("unbalanced parenthesis in operand %d."),
4645 as_bad (_("unbalanced brackets in operand %d."),
4650 break; /* we are done */
4652 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4654 as_bad (_("invalid character %s in operand %d"),
4655 output_invalid (*l
),
4662 ++paren_not_balanced
;
4664 --paren_not_balanced
;
4669 ++paren_not_balanced
;
4671 --paren_not_balanced
;
4675 if (l
!= token_start
)
4676 { /* Yes, we've read in another operand. */
4677 unsigned int operand_ok
;
4678 this_operand
= i
.operands
++;
4679 if (i
.operands
> MAX_OPERANDS
)
4681 as_bad (_("spurious operands; (%d operands/instruction max)"),
4685 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4686 /* Now parse operand adding info to 'i' as we go along. */
4687 END_STRING_AND_SAVE (l
);
4689 if (i
.mem_operands
> 1)
4691 as_bad (_("too many memory references for `%s'"),
4698 i386_intel_operand (token_start
,
4699 intel_float_operand (mnemonic
));
4701 operand_ok
= i386_att_operand (token_start
);
4703 RESTORE_END_STRING (l
);
4709 if (expecting_operand
)
4711 expecting_operand_after_comma
:
4712 as_bad (_("expecting operand after ','; got nothing"));
4717 as_bad (_("expecting operand before ','; got nothing"));
4722 /* Now *l must be either ',' or END_OF_INSN. */
4725 if (*++l
== END_OF_INSN
)
4727 /* Just skip it, if it's \n complain. */
4728 goto expecting_operand_after_comma
;
4730 expecting_operand
= 1;
4737 swap_2_operands (int xchg1
, int xchg2
)
4739 union i386_op temp_op
;
4740 i386_operand_type temp_type
;
4741 enum bfd_reloc_code_real temp_reloc
;
4743 temp_type
= i
.types
[xchg2
];
4744 i
.types
[xchg2
] = i
.types
[xchg1
];
4745 i
.types
[xchg1
] = temp_type
;
4746 temp_op
= i
.op
[xchg2
];
4747 i
.op
[xchg2
] = i
.op
[xchg1
];
4748 i
.op
[xchg1
] = temp_op
;
4749 temp_reloc
= i
.reloc
[xchg2
];
4750 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4751 i
.reloc
[xchg1
] = temp_reloc
;
4755 if (i
.mask
->operand
== xchg1
)
4756 i
.mask
->operand
= xchg2
;
4757 else if (i
.mask
->operand
== xchg2
)
4758 i
.mask
->operand
= xchg1
;
4762 if (i
.broadcast
->operand
== xchg1
)
4763 i
.broadcast
->operand
= xchg2
;
4764 else if (i
.broadcast
->operand
== xchg2
)
4765 i
.broadcast
->operand
= xchg1
;
4769 if (i
.rounding
->operand
== xchg1
)
4770 i
.rounding
->operand
= xchg2
;
4771 else if (i
.rounding
->operand
== xchg2
)
4772 i
.rounding
->operand
= xchg1
;
4777 swap_operands (void)
4783 swap_2_operands (1, i
.operands
- 2);
4787 swap_2_operands (0, i
.operands
- 1);
4793 if (i
.mem_operands
== 2)
4795 const seg_entry
*temp_seg
;
4796 temp_seg
= i
.seg
[0];
4797 i
.seg
[0] = i
.seg
[1];
4798 i
.seg
[1] = temp_seg
;
4802 /* Try to ensure constant immediates are represented in the smallest
4807 char guess_suffix
= 0;
4811 guess_suffix
= i
.suffix
;
4812 else if (i
.reg_operands
)
4814 /* Figure out a suffix from the last register operand specified.
4815 We can't do this properly yet, ie. excluding InOutPortReg,
4816 but the following works for instructions with immediates.
4817 In any case, we can't set i.suffix yet. */
4818 for (op
= i
.operands
; --op
>= 0;)
4819 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4821 guess_suffix
= BYTE_MNEM_SUFFIX
;
4824 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4826 guess_suffix
= WORD_MNEM_SUFFIX
;
4829 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4831 guess_suffix
= LONG_MNEM_SUFFIX
;
4834 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4836 guess_suffix
= QWORD_MNEM_SUFFIX
;
4840 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4841 guess_suffix
= WORD_MNEM_SUFFIX
;
4843 for (op
= i
.operands
; --op
>= 0;)
4844 if (operand_type_check (i
.types
[op
], imm
))
4846 switch (i
.op
[op
].imms
->X_op
)
4849 /* If a suffix is given, this operand may be shortened. */
4850 switch (guess_suffix
)
4852 case LONG_MNEM_SUFFIX
:
4853 i
.types
[op
].bitfield
.imm32
= 1;
4854 i
.types
[op
].bitfield
.imm64
= 1;
4856 case WORD_MNEM_SUFFIX
:
4857 i
.types
[op
].bitfield
.imm16
= 1;
4858 i
.types
[op
].bitfield
.imm32
= 1;
4859 i
.types
[op
].bitfield
.imm32s
= 1;
4860 i
.types
[op
].bitfield
.imm64
= 1;
4862 case BYTE_MNEM_SUFFIX
:
4863 i
.types
[op
].bitfield
.imm8
= 1;
4864 i
.types
[op
].bitfield
.imm8s
= 1;
4865 i
.types
[op
].bitfield
.imm16
= 1;
4866 i
.types
[op
].bitfield
.imm32
= 1;
4867 i
.types
[op
].bitfield
.imm32s
= 1;
4868 i
.types
[op
].bitfield
.imm64
= 1;
4872 /* If this operand is at most 16 bits, convert it
4873 to a signed 16 bit number before trying to see
4874 whether it will fit in an even smaller size.
4875 This allows a 16-bit operand such as $0xffe0 to
4876 be recognised as within Imm8S range. */
4877 if ((i
.types
[op
].bitfield
.imm16
)
4878 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4880 i
.op
[op
].imms
->X_add_number
=
4881 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4884 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4885 if ((i
.types
[op
].bitfield
.imm32
)
4886 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4889 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4890 ^ ((offsetT
) 1 << 31))
4891 - ((offsetT
) 1 << 31));
4895 = operand_type_or (i
.types
[op
],
4896 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4898 /* We must avoid matching of Imm32 templates when 64bit
4899 only immediate is available. */
4900 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4901 i
.types
[op
].bitfield
.imm32
= 0;
4908 /* Symbols and expressions. */
4910 /* Convert symbolic operand to proper sizes for matching, but don't
4911 prevent matching a set of insns that only supports sizes other
4912 than those matching the insn suffix. */
4914 i386_operand_type mask
, allowed
;
4915 const insn_template
*t
;
4917 operand_type_set (&mask
, 0);
4918 operand_type_set (&allowed
, 0);
4920 for (t
= current_templates
->start
;
4921 t
< current_templates
->end
;
4923 allowed
= operand_type_or (allowed
,
4924 t
->operand_types
[op
]);
4925 switch (guess_suffix
)
4927 case QWORD_MNEM_SUFFIX
:
4928 mask
.bitfield
.imm64
= 1;
4929 mask
.bitfield
.imm32s
= 1;
4931 case LONG_MNEM_SUFFIX
:
4932 mask
.bitfield
.imm32
= 1;
4934 case WORD_MNEM_SUFFIX
:
4935 mask
.bitfield
.imm16
= 1;
4937 case BYTE_MNEM_SUFFIX
:
4938 mask
.bitfield
.imm8
= 1;
4943 allowed
= operand_type_and (mask
, allowed
);
4944 if (!operand_type_all_zero (&allowed
))
4945 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4952 /* Try to use the smallest displacement type too. */
4954 optimize_disp (void)
4958 for (op
= i
.operands
; --op
>= 0;)
4959 if (operand_type_check (i
.types
[op
], disp
))
4961 if (i
.op
[op
].disps
->X_op
== O_constant
)
4963 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4965 if (i
.types
[op
].bitfield
.disp16
4966 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4968 /* If this operand is at most 16 bits, convert
4969 to a signed 16 bit number and don't use 64bit
4971 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4972 i
.types
[op
].bitfield
.disp64
= 0;
4975 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4976 if (i
.types
[op
].bitfield
.disp32
4977 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4979 /* If this operand is at most 32 bits, convert
4980 to a signed 32 bit number and don't use 64bit
4982 op_disp
&= (((offsetT
) 2 << 31) - 1);
4983 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4984 i
.types
[op
].bitfield
.disp64
= 0;
4987 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4989 i
.types
[op
].bitfield
.disp8
= 0;
4990 i
.types
[op
].bitfield
.disp16
= 0;
4991 i
.types
[op
].bitfield
.disp32
= 0;
4992 i
.types
[op
].bitfield
.disp32s
= 0;
4993 i
.types
[op
].bitfield
.disp64
= 0;
4997 else if (flag_code
== CODE_64BIT
)
4999 if (fits_in_signed_long (op_disp
))
5001 i
.types
[op
].bitfield
.disp64
= 0;
5002 i
.types
[op
].bitfield
.disp32s
= 1;
5004 if (i
.prefix
[ADDR_PREFIX
]
5005 && fits_in_unsigned_long (op_disp
))
5006 i
.types
[op
].bitfield
.disp32
= 1;
5008 if ((i
.types
[op
].bitfield
.disp32
5009 || i
.types
[op
].bitfield
.disp32s
5010 || i
.types
[op
].bitfield
.disp16
)
5011 && fits_in_disp8 (op_disp
))
5012 i
.types
[op
].bitfield
.disp8
= 1;
5014 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5015 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5017 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5018 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5019 i
.types
[op
].bitfield
.disp8
= 0;
5020 i
.types
[op
].bitfield
.disp16
= 0;
5021 i
.types
[op
].bitfield
.disp32
= 0;
5022 i
.types
[op
].bitfield
.disp32s
= 0;
5023 i
.types
[op
].bitfield
.disp64
= 0;
5026 /* We only support 64bit displacement on constants. */
5027 i
.types
[op
].bitfield
.disp64
= 0;
5031 /* Return 1 if there is a match in broadcast bytes between operand
5032 GIVEN and instruction template T. */
5035 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5037 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5038 && i
.types
[given
].bitfield
.byte
)
5039 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5040 && i
.types
[given
].bitfield
.word
)
5041 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5042 && i
.types
[given
].bitfield
.dword
)
5043 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5044 && i
.types
[given
].bitfield
.qword
));
5047 /* Check if operands are valid for the instruction. */
5050 check_VecOperands (const insn_template
*t
)
5054 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5056 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5057 any one operand are implicity requiring AVX512VL support if the actual
5058 operand size is YMMword or XMMword. Since this function runs after
5059 template matching, there's no need to check for YMMword/XMMword in
5061 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5062 if (!cpu_flags_all_zero (&cpu
)
5063 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5064 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5066 for (op
= 0; op
< t
->operands
; ++op
)
5068 if (t
->operand_types
[op
].bitfield
.zmmword
5069 && (i
.types
[op
].bitfield
.ymmword
5070 || i
.types
[op
].bitfield
.xmmword
))
5072 i
.error
= unsupported
;
5078 /* Without VSIB byte, we can't have a vector register for index. */
5079 if (!t
->opcode_modifier
.vecsib
5081 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5082 || i
.index_reg
->reg_type
.bitfield
.ymmword
5083 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5085 i
.error
= unsupported_vector_index_register
;
5089 /* Check if default mask is allowed. */
5090 if (t
->opcode_modifier
.nodefmask
5091 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5093 i
.error
= no_default_mask
;
5097 /* For VSIB byte, we need a vector register for index, and all vector
5098 registers must be distinct. */
5099 if (t
->opcode_modifier
.vecsib
)
5102 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5103 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5104 || (t
->opcode_modifier
.vecsib
== VecSIB256
5105 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5106 || (t
->opcode_modifier
.vecsib
== VecSIB512
5107 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5109 i
.error
= invalid_vsib_address
;
5113 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5114 if (i
.reg_operands
== 2 && !i
.mask
)
5116 gas_assert (i
.types
[0].bitfield
.regsimd
);
5117 gas_assert (i
.types
[0].bitfield
.xmmword
5118 || i
.types
[0].bitfield
.ymmword
);
5119 gas_assert (i
.types
[2].bitfield
.regsimd
);
5120 gas_assert (i
.types
[2].bitfield
.xmmword
5121 || i
.types
[2].bitfield
.ymmword
);
5122 if (operand_check
== check_none
)
5124 if (register_number (i
.op
[0].regs
)
5125 != register_number (i
.index_reg
)
5126 && register_number (i
.op
[2].regs
)
5127 != register_number (i
.index_reg
)
5128 && register_number (i
.op
[0].regs
)
5129 != register_number (i
.op
[2].regs
))
5131 if (operand_check
== check_error
)
5133 i
.error
= invalid_vector_register_set
;
5136 as_warn (_("mask, index, and destination registers should be distinct"));
5138 else if (i
.reg_operands
== 1 && i
.mask
)
5140 if (i
.types
[1].bitfield
.regsimd
5141 && (i
.types
[1].bitfield
.xmmword
5142 || i
.types
[1].bitfield
.ymmword
5143 || i
.types
[1].bitfield
.zmmword
)
5144 && (register_number (i
.op
[1].regs
)
5145 == register_number (i
.index_reg
)))
5147 if (operand_check
== check_error
)
5149 i
.error
= invalid_vector_register_set
;
5152 if (operand_check
!= check_none
)
5153 as_warn (_("index and destination registers should be distinct"));
5158 /* Check if broadcast is supported by the instruction and is applied
5159 to the memory operand. */
5162 i386_operand_type type
, overlap
;
5164 /* Check if specified broadcast is supported in this instruction,
5165 and its broadcast bytes match the memory operand. */
5166 op
= i
.broadcast
->operand
;
5167 if (!t
->opcode_modifier
.broadcast
5168 || !i
.types
[op
].bitfield
.mem
5169 || (!i
.types
[op
].bitfield
.unspecified
5170 && !match_broadcast_size (t
, op
)))
5173 i
.error
= unsupported_broadcast
;
5177 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5178 * i
.broadcast
->type
);
5179 operand_type_set (&type
, 0);
5180 switch (i
.broadcast
->bytes
)
5183 type
.bitfield
.word
= 1;
5186 type
.bitfield
.dword
= 1;
5189 type
.bitfield
.qword
= 1;
5192 type
.bitfield
.xmmword
= 1;
5195 type
.bitfield
.ymmword
= 1;
5198 type
.bitfield
.zmmword
= 1;
5204 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5205 if (operand_type_all_zero (&overlap
))
5208 if (t
->opcode_modifier
.checkregsize
)
5212 type
.bitfield
.baseindex
= 1;
5213 for (j
= 0; j
< i
.operands
; ++j
)
5216 && !operand_type_register_match(i
.types
[j
],
5217 t
->operand_types
[j
],
5219 t
->operand_types
[op
]))
5224 /* If broadcast is supported in this instruction, we need to check if
5225 operand of one-element size isn't specified without broadcast. */
5226 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5228 /* Find memory operand. */
5229 for (op
= 0; op
< i
.operands
; op
++)
5230 if (operand_type_check (i
.types
[op
], anymem
))
5232 gas_assert (op
< i
.operands
);
5233 /* Check size of the memory operand. */
5234 if (match_broadcast_size (t
, op
))
5236 i
.error
= broadcast_needed
;
5241 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5243 /* Check if requested masking is supported. */
5245 && (!t
->opcode_modifier
.masking
5247 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5249 i
.error
= unsupported_masking
;
5253 /* Check if masking is applied to dest operand. */
5254 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5256 i
.error
= mask_not_on_destination
;
5263 if ((i
.rounding
->type
!= saeonly
5264 && !t
->opcode_modifier
.staticrounding
)
5265 || (i
.rounding
->type
== saeonly
5266 && (t
->opcode_modifier
.staticrounding
5267 || !t
->opcode_modifier
.sae
)))
5269 i
.error
= unsupported_rc_sae
;
5272 /* If the instruction has several immediate operands and one of
5273 them is rounding, the rounding operand should be the last
5274 immediate operand. */
5275 if (i
.imm_operands
> 1
5276 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5278 i
.error
= rc_sae_operand_not_last_imm
;
5283 /* Check vector Disp8 operand. */
5284 if (t
->opcode_modifier
.disp8memshift
5285 && i
.disp_encoding
!= disp_encoding_32bit
)
5288 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5289 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5290 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5293 const i386_operand_type
*type
= NULL
;
5296 for (op
= 0; op
< i
.operands
; op
++)
5297 if (operand_type_check (i
.types
[op
], anymem
))
5299 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5300 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5301 else if (t
->operand_types
[op
].bitfield
.xmmword
5302 + t
->operand_types
[op
].bitfield
.ymmword
5303 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5304 type
= &t
->operand_types
[op
];
5305 else if (!i
.types
[op
].bitfield
.unspecified
)
5306 type
= &i
.types
[op
];
5308 else if (i
.types
[op
].bitfield
.regsimd
5309 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5311 if (i
.types
[op
].bitfield
.zmmword
)
5313 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5315 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5321 if (type
->bitfield
.zmmword
)
5323 else if (type
->bitfield
.ymmword
)
5325 else if (type
->bitfield
.xmmword
)
5329 /* For the check in fits_in_disp8(). */
5330 if (i
.memshift
== 0)
5334 for (op
= 0; op
< i
.operands
; op
++)
5335 if (operand_type_check (i
.types
[op
], disp
)
5336 && i
.op
[op
].disps
->X_op
== O_constant
)
5338 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5340 i
.types
[op
].bitfield
.disp8
= 1;
5343 i
.types
[op
].bitfield
.disp8
= 0;
5352 /* Check if operands are valid for the instruction. Update VEX
5356 VEX_check_operands (const insn_template
*t
)
5358 if (i
.vec_encoding
== vex_encoding_evex
)
5360 /* This instruction must be encoded with EVEX prefix. */
5361 if (!is_evex_encoding (t
))
5363 i
.error
= unsupported
;
5369 if (!t
->opcode_modifier
.vex
)
5371 /* This instruction template doesn't have VEX prefix. */
5372 if (i
.vec_encoding
!= vex_encoding_default
)
5374 i
.error
= unsupported
;
5380 /* Only check VEX_Imm4, which must be the first operand. */
5381 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5383 if (i
.op
[0].imms
->X_op
!= O_constant
5384 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5390 /* Turn off Imm8 so that update_imm won't complain. */
5391 i
.types
[0] = vec_imm4
;
5397 static const insn_template
*
5398 match_template (char mnem_suffix
)
5400 /* Points to template once we've found it. */
5401 const insn_template
*t
;
5402 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5403 i386_operand_type overlap4
;
5404 unsigned int found_reverse_match
;
5405 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5406 i386_operand_type operand_types
[MAX_OPERANDS
];
5407 int addr_prefix_disp
;
5409 unsigned int found_cpu_match
, size_match
;
5410 unsigned int check_register
;
5411 enum i386_error specific_error
= 0;
5413 #if MAX_OPERANDS != 5
5414 # error "MAX_OPERANDS must be 5."
5417 found_reverse_match
= 0;
5418 addr_prefix_disp
= -1;
5420 memset (&suffix_check
, 0, sizeof (suffix_check
));
5421 if (intel_syntax
&& i
.broadcast
)
5423 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5424 suffix_check
.no_bsuf
= 1;
5425 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5426 suffix_check
.no_wsuf
= 1;
5427 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5428 suffix_check
.no_ssuf
= 1;
5429 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5430 suffix_check
.no_lsuf
= 1;
5431 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5432 suffix_check
.no_qsuf
= 1;
5433 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5434 suffix_check
.no_ldsuf
= 1;
5436 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5439 switch (mnem_suffix
)
5441 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5442 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5443 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5444 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5445 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5449 /* Must have right number of operands. */
5450 i
.error
= number_of_operands_mismatch
;
5452 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5454 addr_prefix_disp
= -1;
5456 if (i
.operands
!= t
->operands
)
5459 /* Check processor support. */
5460 i
.error
= unsupported
;
5461 found_cpu_match
= (cpu_flags_match (t
)
5462 == CPU_FLAGS_PERFECT_MATCH
);
5463 if (!found_cpu_match
)
5466 /* Check AT&T mnemonic. */
5467 i
.error
= unsupported_with_intel_mnemonic
;
5468 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5471 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5472 i
.error
= unsupported_syntax
;
5473 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5474 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5475 || (intel64
&& t
->opcode_modifier
.amd64
)
5476 || (!intel64
&& t
->opcode_modifier
.intel64
))
5479 /* Check the suffix, except for some instructions in intel mode. */
5480 i
.error
= invalid_instruction_suffix
;
5481 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5482 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5483 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5484 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5485 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5486 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5487 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5489 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5490 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5491 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5492 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5493 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5494 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5495 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5498 size_match
= operand_size_match (t
);
5502 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5503 operand_types
[j
] = t
->operand_types
[j
];
5505 /* In general, don't allow 64-bit operands in 32-bit mode. */
5506 if (i
.suffix
== QWORD_MNEM_SUFFIX
5507 && flag_code
!= CODE_64BIT
5509 ? (!t
->opcode_modifier
.ignoresize
5510 && !t
->opcode_modifier
.broadcast
5511 && !intel_float_operand (t
->name
))
5512 : intel_float_operand (t
->name
) != 2)
5513 && ((!operand_types
[0].bitfield
.regmmx
5514 && !operand_types
[0].bitfield
.regsimd
)
5515 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5516 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5517 && (t
->base_opcode
!= 0x0fc7
5518 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5521 /* In general, don't allow 32-bit operands on pre-386. */
5522 else if (i
.suffix
== LONG_MNEM_SUFFIX
5523 && !cpu_arch_flags
.bitfield
.cpui386
5525 ? (!t
->opcode_modifier
.ignoresize
5526 && !intel_float_operand (t
->name
))
5527 : intel_float_operand (t
->name
) != 2)
5528 && ((!operand_types
[0].bitfield
.regmmx
5529 && !operand_types
[0].bitfield
.regsimd
)
5530 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5531 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5534 /* Do not verify operands when there are none. */
5538 /* We've found a match; break out of loop. */
5542 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5543 into Disp32/Disp16/Disp32 operand. */
5544 if (i
.prefix
[ADDR_PREFIX
] != 0)
5546 /* There should be only one Disp operand. */
5550 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5552 if (operand_types
[j
].bitfield
.disp16
)
5554 addr_prefix_disp
= j
;
5555 operand_types
[j
].bitfield
.disp32
= 1;
5556 operand_types
[j
].bitfield
.disp16
= 0;
5562 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5564 if (operand_types
[j
].bitfield
.disp32
)
5566 addr_prefix_disp
= j
;
5567 operand_types
[j
].bitfield
.disp32
= 0;
5568 operand_types
[j
].bitfield
.disp16
= 1;
5574 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5576 if (operand_types
[j
].bitfield
.disp64
)
5578 addr_prefix_disp
= j
;
5579 operand_types
[j
].bitfield
.disp64
= 0;
5580 operand_types
[j
].bitfield
.disp32
= 1;
5588 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5589 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5592 /* We check register size if needed. */
5593 if (t
->opcode_modifier
.checkregsize
)
5595 check_register
= (1 << t
->operands
) - 1;
5597 check_register
&= ~(1 << i
.broadcast
->operand
);
5602 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5603 switch (t
->operands
)
5606 if (!operand_type_match (overlap0
, i
.types
[0]))
5610 /* xchg %eax, %eax is a special case. It is an alias for nop
5611 only in 32bit mode and we can use opcode 0x90. In 64bit
5612 mode, we can't use 0x90 for xchg %eax, %eax since it should
5613 zero-extend %eax to %rax. */
5614 if (flag_code
== CODE_64BIT
5615 && t
->base_opcode
== 0x90
5616 && operand_type_equal (&i
.types
[0], &acc32
)
5617 && operand_type_equal (&i
.types
[1], &acc32
))
5619 /* xrelease mov %eax, <disp> is another special case. It must not
5620 match the accumulator-only encoding of mov. */
5621 if (flag_code
!= CODE_64BIT
5623 && t
->base_opcode
== 0xa0
5624 && i
.types
[0].bitfield
.acc
5625 && operand_type_check (i
.types
[1], anymem
))
5627 if (!(size_match
& MATCH_STRAIGHT
))
5629 /* If we want store form, we reverse direction of operands. */
5630 if (i
.dir_encoding
== dir_encoding_store
5631 && t
->opcode_modifier
.d
)
5636 /* If we want store form, we skip the current load. */
5637 if (i
.dir_encoding
== dir_encoding_store
5638 && i
.mem_operands
== 0
5639 && t
->opcode_modifier
.load
)
5644 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5645 if (!operand_type_match (overlap0
, i
.types
[0])
5646 || !operand_type_match (overlap1
, i
.types
[1])
5647 || ((check_register
& 3) == 3
5648 && !operand_type_register_match (i
.types
[0],
5653 /* Check if other direction is valid ... */
5654 if (!t
->opcode_modifier
.d
)
5658 if (!(size_match
& MATCH_REVERSE
))
5660 /* Try reversing direction of operands. */
5661 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5662 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5663 if (!operand_type_match (overlap0
, i
.types
[0])
5664 || !operand_type_match (overlap1
, i
.types
[1])
5666 && !operand_type_register_match (i
.types
[0],
5671 /* Does not match either direction. */
5674 /* found_reverse_match holds which of D or FloatR
5676 if (!t
->opcode_modifier
.d
)
5677 found_reverse_match
= 0;
5678 else if (operand_types
[0].bitfield
.tbyte
)
5679 found_reverse_match
= Opcode_FloatD
;
5681 found_reverse_match
= Opcode_D
;
5682 if (t
->opcode_modifier
.floatr
)
5683 found_reverse_match
|= Opcode_FloatR
;
5687 /* Found a forward 2 operand match here. */
5688 switch (t
->operands
)
5691 overlap4
= operand_type_and (i
.types
[4],
5695 overlap3
= operand_type_and (i
.types
[3],
5699 overlap2
= operand_type_and (i
.types
[2],
5704 switch (t
->operands
)
5707 if (!operand_type_match (overlap4
, i
.types
[4])
5708 || !operand_type_register_match (i
.types
[3],
5715 if (!operand_type_match (overlap3
, i
.types
[3])
5716 || ((check_register
& 0xa) == 0xa
5717 && !operand_type_register_match (i
.types
[1],
5721 || ((check_register
& 0xc) == 0xc
5722 && !operand_type_register_match (i
.types
[2],
5729 /* Here we make use of the fact that there are no
5730 reverse match 3 operand instructions. */
5731 if (!operand_type_match (overlap2
, i
.types
[2])
5732 || ((check_register
& 5) == 5
5733 && !operand_type_register_match (i
.types
[0],
5737 || ((check_register
& 6) == 6
5738 && !operand_type_register_match (i
.types
[1],
5746 /* Found either forward/reverse 2, 3 or 4 operand match here:
5747 slip through to break. */
5749 if (!found_cpu_match
)
5751 found_reverse_match
= 0;
5755 /* Check if vector and VEX operands are valid. */
5756 if (check_VecOperands (t
) || VEX_check_operands (t
))
5758 specific_error
= i
.error
;
5762 /* We've found a match; break out of loop. */
5766 if (t
== current_templates
->end
)
5768 /* We found no match. */
5769 const char *err_msg
;
5770 switch (specific_error
? specific_error
: i
.error
)
5774 case operand_size_mismatch
:
5775 err_msg
= _("operand size mismatch");
5777 case operand_type_mismatch
:
5778 err_msg
= _("operand type mismatch");
5780 case register_type_mismatch
:
5781 err_msg
= _("register type mismatch");
5783 case number_of_operands_mismatch
:
5784 err_msg
= _("number of operands mismatch");
5786 case invalid_instruction_suffix
:
5787 err_msg
= _("invalid instruction suffix");
5790 err_msg
= _("constant doesn't fit in 4 bits");
5792 case unsupported_with_intel_mnemonic
:
5793 err_msg
= _("unsupported with Intel mnemonic");
5795 case unsupported_syntax
:
5796 err_msg
= _("unsupported syntax");
5799 as_bad (_("unsupported instruction `%s'"),
5800 current_templates
->start
->name
);
5802 case invalid_vsib_address
:
5803 err_msg
= _("invalid VSIB address");
5805 case invalid_vector_register_set
:
5806 err_msg
= _("mask, index, and destination registers must be distinct");
5808 case unsupported_vector_index_register
:
5809 err_msg
= _("unsupported vector index register");
5811 case unsupported_broadcast
:
5812 err_msg
= _("unsupported broadcast");
5814 case broadcast_needed
:
5815 err_msg
= _("broadcast is needed for operand of such type");
5817 case unsupported_masking
:
5818 err_msg
= _("unsupported masking");
5820 case mask_not_on_destination
:
5821 err_msg
= _("mask not on destination operand");
5823 case no_default_mask
:
5824 err_msg
= _("default mask isn't allowed");
5826 case unsupported_rc_sae
:
5827 err_msg
= _("unsupported static rounding/sae");
5829 case rc_sae_operand_not_last_imm
:
5831 err_msg
= _("RC/SAE operand must precede immediate operands");
5833 err_msg
= _("RC/SAE operand must follow immediate operands");
5835 case invalid_register_operand
:
5836 err_msg
= _("invalid register operand");
5839 as_bad (_("%s for `%s'"), err_msg
,
5840 current_templates
->start
->name
);
5844 if (!quiet_warnings
)
5847 && (i
.types
[0].bitfield
.jumpabsolute
5848 != operand_types
[0].bitfield
.jumpabsolute
))
5850 as_warn (_("indirect %s without `*'"), t
->name
);
5853 if (t
->opcode_modifier
.isprefix
5854 && t
->opcode_modifier
.ignoresize
)
5856 /* Warn them that a data or address size prefix doesn't
5857 affect assembly of the next line of code. */
5858 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5862 /* Copy the template we found. */
5865 if (addr_prefix_disp
!= -1)
5866 i
.tm
.operand_types
[addr_prefix_disp
]
5867 = operand_types
[addr_prefix_disp
];
5869 if (found_reverse_match
)
5871 /* If we found a reverse match we must alter the opcode
5872 direction bit. found_reverse_match holds bits to change
5873 (different for int & float insns). */
5875 i
.tm
.base_opcode
^= found_reverse_match
;
5877 i
.tm
.operand_types
[0] = operand_types
[1];
5878 i
.tm
.operand_types
[1] = operand_types
[0];
5887 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5888 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5890 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5892 as_bad (_("`%s' operand %d must use `%ses' segment"),
5898 /* There's only ever one segment override allowed per instruction.
5899 This instruction possibly has a legal segment override on the
5900 second operand, so copy the segment to where non-string
5901 instructions store it, allowing common code. */
5902 i
.seg
[0] = i
.seg
[1];
5904 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5906 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5908 as_bad (_("`%s' operand %d must use `%ses' segment"),
5919 process_suffix (void)
5921 /* If matched instruction specifies an explicit instruction mnemonic
5923 if (i
.tm
.opcode_modifier
.size16
)
5924 i
.suffix
= WORD_MNEM_SUFFIX
;
5925 else if (i
.tm
.opcode_modifier
.size32
)
5926 i
.suffix
= LONG_MNEM_SUFFIX
;
5927 else if (i
.tm
.opcode_modifier
.size64
)
5928 i
.suffix
= QWORD_MNEM_SUFFIX
;
5929 else if (i
.reg_operands
)
5931 /* If there's no instruction mnemonic suffix we try to invent one
5932 based on register operands. */
5935 /* We take i.suffix from the last register operand specified,
5936 Destination register type is more significant than source
5937 register type. crc32 in SSE4.2 prefers source register
5939 if (i
.tm
.base_opcode
== 0xf20f38f1)
5941 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5942 i
.suffix
= WORD_MNEM_SUFFIX
;
5943 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5944 i
.suffix
= LONG_MNEM_SUFFIX
;
5945 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5946 i
.suffix
= QWORD_MNEM_SUFFIX
;
5948 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5950 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5951 i
.suffix
= BYTE_MNEM_SUFFIX
;
5958 if (i
.tm
.base_opcode
== 0xf20f38f1
5959 || i
.tm
.base_opcode
== 0xf20f38f0)
5961 /* We have to know the operand size for crc32. */
5962 as_bad (_("ambiguous memory operand size for `%s`"),
5967 for (op
= i
.operands
; --op
>= 0;)
5968 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5969 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5971 if (!i
.types
[op
].bitfield
.reg
)
5973 if (i
.types
[op
].bitfield
.byte
)
5974 i
.suffix
= BYTE_MNEM_SUFFIX
;
5975 else if (i
.types
[op
].bitfield
.word
)
5976 i
.suffix
= WORD_MNEM_SUFFIX
;
5977 else if (i
.types
[op
].bitfield
.dword
)
5978 i
.suffix
= LONG_MNEM_SUFFIX
;
5979 else if (i
.types
[op
].bitfield
.qword
)
5980 i
.suffix
= QWORD_MNEM_SUFFIX
;
5987 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5990 && i
.tm
.opcode_modifier
.ignoresize
5991 && i
.tm
.opcode_modifier
.no_bsuf
)
5993 else if (!check_byte_reg ())
5996 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5999 && i
.tm
.opcode_modifier
.ignoresize
6000 && i
.tm
.opcode_modifier
.no_lsuf
6001 && !i
.tm
.opcode_modifier
.todword
6002 && !i
.tm
.opcode_modifier
.toqword
)
6004 else if (!check_long_reg ())
6007 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6010 && i
.tm
.opcode_modifier
.ignoresize
6011 && i
.tm
.opcode_modifier
.no_qsuf
6012 && !i
.tm
.opcode_modifier
.todword
6013 && !i
.tm
.opcode_modifier
.toqword
)
6015 else if (!check_qword_reg ())
6018 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6021 && i
.tm
.opcode_modifier
.ignoresize
6022 && i
.tm
.opcode_modifier
.no_wsuf
)
6024 else if (!check_word_reg ())
6027 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6028 /* Do nothing if the instruction is going to ignore the prefix. */
6033 else if (i
.tm
.opcode_modifier
.defaultsize
6035 /* exclude fldenv/frstor/fsave/fstenv */
6036 && i
.tm
.opcode_modifier
.no_ssuf
)
6038 i
.suffix
= stackop_size
;
6040 else if (intel_syntax
6042 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6043 || i
.tm
.opcode_modifier
.jumpbyte
6044 || i
.tm
.opcode_modifier
.jumpintersegment
6045 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6046 && i
.tm
.extension_opcode
<= 3)))
6051 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6053 i
.suffix
= QWORD_MNEM_SUFFIX
;
6058 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6059 i
.suffix
= LONG_MNEM_SUFFIX
;
6062 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6063 i
.suffix
= WORD_MNEM_SUFFIX
;
6072 if (i
.tm
.opcode_modifier
.w
)
6074 as_bad (_("no instruction mnemonic suffix given and "
6075 "no register operands; can't size instruction"));
6081 unsigned int suffixes
;
6083 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6084 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6086 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6088 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6090 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6092 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6095 /* There are more than suffix matches. */
6096 if (i
.tm
.opcode_modifier
.w
6097 || ((suffixes
& (suffixes
- 1))
6098 && !i
.tm
.opcode_modifier
.defaultsize
6099 && !i
.tm
.opcode_modifier
.ignoresize
))
6101 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6107 /* Change the opcode based on the operand size given by i.suffix. */
6110 /* Size floating point instruction. */
6111 case LONG_MNEM_SUFFIX
:
6112 if (i
.tm
.opcode_modifier
.floatmf
)
6114 i
.tm
.base_opcode
^= 4;
6118 case WORD_MNEM_SUFFIX
:
6119 case QWORD_MNEM_SUFFIX
:
6120 /* It's not a byte, select word/dword operation. */
6121 if (i
.tm
.opcode_modifier
.w
)
6123 if (i
.tm
.opcode_modifier
.shortform
)
6124 i
.tm
.base_opcode
|= 8;
6126 i
.tm
.base_opcode
|= 1;
6129 case SHORT_MNEM_SUFFIX
:
6130 /* Now select between word & dword operations via the operand
6131 size prefix, except for instructions that will ignore this
6133 if (i
.reg_operands
> 0
6134 && i
.types
[0].bitfield
.reg
6135 && i
.tm
.opcode_modifier
.addrprefixopreg
6136 && (i
.tm
.opcode_modifier
.immext
6137 || i
.operands
== 1))
6139 /* The address size override prefix changes the size of the
6141 if ((flag_code
== CODE_32BIT
6142 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6143 || (flag_code
!= CODE_32BIT
6144 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6145 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6148 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6149 && !i
.tm
.opcode_modifier
.ignoresize
6150 && !i
.tm
.opcode_modifier
.floatmf
6151 && !i
.tm
.opcode_modifier
.vex
6152 && !i
.tm
.opcode_modifier
.vexopcode
6153 && !is_evex_encoding (&i
.tm
)
6154 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6155 || (flag_code
== CODE_64BIT
6156 && i
.tm
.opcode_modifier
.jumpbyte
)))
6158 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6160 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6161 prefix
= ADDR_PREFIX_OPCODE
;
6163 if (!add_prefix (prefix
))
6167 /* Set mode64 for an operand. */
6168 if (i
.suffix
== QWORD_MNEM_SUFFIX
6169 && flag_code
== CODE_64BIT
6170 && !i
.tm
.opcode_modifier
.norex64
6171 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6173 && ! (i
.operands
== 2
6174 && i
.tm
.base_opcode
== 0x90
6175 && i
.tm
.extension_opcode
== None
6176 && operand_type_equal (&i
.types
[0], &acc64
)
6177 && operand_type_equal (&i
.types
[1], &acc64
)))
6183 if (i
.reg_operands
!= 0
6185 && i
.tm
.opcode_modifier
.addrprefixopreg
6186 && !i
.tm
.opcode_modifier
.immext
)
6188 /* Check invalid register operand when the address size override
6189 prefix changes the size of register operands. */
6191 enum { need_word
, need_dword
, need_qword
} need
;
6193 if (flag_code
== CODE_32BIT
)
6194 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6197 if (i
.prefix
[ADDR_PREFIX
])
6200 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6203 for (op
= 0; op
< i
.operands
; op
++)
6204 if (i
.types
[op
].bitfield
.reg
6205 && ((need
== need_word
6206 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6207 || (need
== need_dword
6208 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6209 || (need
== need_qword
6210 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6212 as_bad (_("invalid register operand size for `%s'"),
6222 check_byte_reg (void)
6226 for (op
= i
.operands
; --op
>= 0;)
6228 /* Skip non-register operands. */
6229 if (!i
.types
[op
].bitfield
.reg
)
6232 /* If this is an eight bit register, it's OK. If it's the 16 or
6233 32 bit version of an eight bit register, we will just use the
6234 low portion, and that's OK too. */
6235 if (i
.types
[op
].bitfield
.byte
)
6238 /* I/O port address operands are OK too. */
6239 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6242 /* crc32 doesn't generate this warning. */
6243 if (i
.tm
.base_opcode
== 0xf20f38f0)
6246 if ((i
.types
[op
].bitfield
.word
6247 || i
.types
[op
].bitfield
.dword
6248 || i
.types
[op
].bitfield
.qword
)
6249 && i
.op
[op
].regs
->reg_num
< 4
6250 /* Prohibit these changes in 64bit mode, since the lowering
6251 would be more complicated. */
6252 && flag_code
!= CODE_64BIT
)
6254 #if REGISTER_WARNINGS
6255 if (!quiet_warnings
)
6256 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6258 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6259 ? REGNAM_AL
- REGNAM_AX
6260 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6262 i
.op
[op
].regs
->reg_name
,
6267 /* Any other register is bad. */
6268 if (i
.types
[op
].bitfield
.reg
6269 || i
.types
[op
].bitfield
.regmmx
6270 || i
.types
[op
].bitfield
.regsimd
6271 || i
.types
[op
].bitfield
.sreg2
6272 || i
.types
[op
].bitfield
.sreg3
6273 || i
.types
[op
].bitfield
.control
6274 || i
.types
[op
].bitfield
.debug
6275 || i
.types
[op
].bitfield
.test
)
6277 as_bad (_("`%s%s' not allowed with `%s%c'"),
6279 i
.op
[op
].regs
->reg_name
,
6289 check_long_reg (void)
6293 for (op
= i
.operands
; --op
>= 0;)
6294 /* Skip non-register operands. */
6295 if (!i
.types
[op
].bitfield
.reg
)
6297 /* Reject eight bit registers, except where the template requires
6298 them. (eg. movzb) */
6299 else if (i
.types
[op
].bitfield
.byte
6300 && (i
.tm
.operand_types
[op
].bitfield
.reg
6301 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6302 && (i
.tm
.operand_types
[op
].bitfield
.word
6303 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6305 as_bad (_("`%s%s' not allowed with `%s%c'"),
6307 i
.op
[op
].regs
->reg_name
,
6312 /* Warn if the e prefix on a general reg is missing. */
6313 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6314 && i
.types
[op
].bitfield
.word
6315 && (i
.tm
.operand_types
[op
].bitfield
.reg
6316 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6317 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6319 /* Prohibit these changes in the 64bit mode, since the
6320 lowering is more complicated. */
6321 if (flag_code
== CODE_64BIT
)
6323 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6324 register_prefix
, i
.op
[op
].regs
->reg_name
,
6328 #if REGISTER_WARNINGS
6329 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6331 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6332 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6335 /* Warn if the r prefix on a general reg is present. */
6336 else if (i
.types
[op
].bitfield
.qword
6337 && (i
.tm
.operand_types
[op
].bitfield
.reg
6338 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6339 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6342 && i
.tm
.opcode_modifier
.toqword
6343 && !i
.types
[0].bitfield
.regsimd
)
6345 /* Convert to QWORD. We want REX byte. */
6346 i
.suffix
= QWORD_MNEM_SUFFIX
;
6350 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6351 register_prefix
, i
.op
[op
].regs
->reg_name
,
6360 check_qword_reg (void)
6364 for (op
= i
.operands
; --op
>= 0; )
6365 /* Skip non-register operands. */
6366 if (!i
.types
[op
].bitfield
.reg
)
6368 /* Reject eight bit registers, except where the template requires
6369 them. (eg. movzb) */
6370 else if (i
.types
[op
].bitfield
.byte
6371 && (i
.tm
.operand_types
[op
].bitfield
.reg
6372 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6373 && (i
.tm
.operand_types
[op
].bitfield
.word
6374 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6376 as_bad (_("`%s%s' not allowed with `%s%c'"),
6378 i
.op
[op
].regs
->reg_name
,
6383 /* Warn if the r prefix on a general reg is missing. */
6384 else if ((i
.types
[op
].bitfield
.word
6385 || i
.types
[op
].bitfield
.dword
)
6386 && (i
.tm
.operand_types
[op
].bitfield
.reg
6387 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6388 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6390 /* Prohibit these changes in the 64bit mode, since the
6391 lowering is more complicated. */
6393 && i
.tm
.opcode_modifier
.todword
6394 && !i
.types
[0].bitfield
.regsimd
)
6396 /* Convert to DWORD. We don't want REX byte. */
6397 i
.suffix
= LONG_MNEM_SUFFIX
;
6401 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6402 register_prefix
, i
.op
[op
].regs
->reg_name
,
6411 check_word_reg (void)
6414 for (op
= i
.operands
; --op
>= 0;)
6415 /* Skip non-register operands. */
6416 if (!i
.types
[op
].bitfield
.reg
)
6418 /* Reject eight bit registers, except where the template requires
6419 them. (eg. movzb) */
6420 else if (i
.types
[op
].bitfield
.byte
6421 && (i
.tm
.operand_types
[op
].bitfield
.reg
6422 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6423 && (i
.tm
.operand_types
[op
].bitfield
.word
6424 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6426 as_bad (_("`%s%s' not allowed with `%s%c'"),
6428 i
.op
[op
].regs
->reg_name
,
6433 /* Warn if the e or r prefix on a general reg is present. */
6434 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6435 && (i
.types
[op
].bitfield
.dword
6436 || i
.types
[op
].bitfield
.qword
)
6437 && (i
.tm
.operand_types
[op
].bitfield
.reg
6438 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6439 && i
.tm
.operand_types
[op
].bitfield
.word
)
6441 /* Prohibit these changes in the 64bit mode, since the
6442 lowering is more complicated. */
6443 if (flag_code
== CODE_64BIT
)
6445 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6446 register_prefix
, i
.op
[op
].regs
->reg_name
,
6450 #if REGISTER_WARNINGS
6451 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6453 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6454 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6461 update_imm (unsigned int j
)
6463 i386_operand_type overlap
= i
.types
[j
];
6464 if ((overlap
.bitfield
.imm8
6465 || overlap
.bitfield
.imm8s
6466 || overlap
.bitfield
.imm16
6467 || overlap
.bitfield
.imm32
6468 || overlap
.bitfield
.imm32s
6469 || overlap
.bitfield
.imm64
)
6470 && !operand_type_equal (&overlap
, &imm8
)
6471 && !operand_type_equal (&overlap
, &imm8s
)
6472 && !operand_type_equal (&overlap
, &imm16
)
6473 && !operand_type_equal (&overlap
, &imm32
)
6474 && !operand_type_equal (&overlap
, &imm32s
)
6475 && !operand_type_equal (&overlap
, &imm64
))
6479 i386_operand_type temp
;
6481 operand_type_set (&temp
, 0);
6482 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6484 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6485 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6487 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6488 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6489 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6491 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6492 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6495 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6498 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6499 || operand_type_equal (&overlap
, &imm16_32
)
6500 || operand_type_equal (&overlap
, &imm16_32s
))
6502 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6507 if (!operand_type_equal (&overlap
, &imm8
)
6508 && !operand_type_equal (&overlap
, &imm8s
)
6509 && !operand_type_equal (&overlap
, &imm16
)
6510 && !operand_type_equal (&overlap
, &imm32
)
6511 && !operand_type_equal (&overlap
, &imm32s
)
6512 && !operand_type_equal (&overlap
, &imm64
))
6514 as_bad (_("no instruction mnemonic suffix given; "
6515 "can't determine immediate size"));
6519 i
.types
[j
] = overlap
;
6529 /* Update the first 2 immediate operands. */
6530 n
= i
.operands
> 2 ? 2 : i
.operands
;
6533 for (j
= 0; j
< n
; j
++)
6534 if (update_imm (j
) == 0)
6537 /* The 3rd operand can't be immediate operand. */
6538 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6545 process_operands (void)
6547 /* Default segment register this instruction will use for memory
6548 accesses. 0 means unknown. This is only for optimizing out
6549 unnecessary segment overrides. */
6550 const seg_entry
*default_seg
= 0;
6552 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6554 unsigned int dupl
= i
.operands
;
6555 unsigned int dest
= dupl
- 1;
6558 /* The destination must be an xmm register. */
6559 gas_assert (i
.reg_operands
6560 && MAX_OPERANDS
> dupl
6561 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6563 if (i
.tm
.operand_types
[0].bitfield
.acc
6564 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6566 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6568 /* Keep xmm0 for instructions with VEX prefix and 3
6570 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6571 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6576 /* We remove the first xmm0 and keep the number of
6577 operands unchanged, which in fact duplicates the
6579 for (j
= 1; j
< i
.operands
; j
++)
6581 i
.op
[j
- 1] = i
.op
[j
];
6582 i
.types
[j
- 1] = i
.types
[j
];
6583 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6587 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6589 gas_assert ((MAX_OPERANDS
- 1) > dupl
6590 && (i
.tm
.opcode_modifier
.vexsources
6593 /* Add the implicit xmm0 for instructions with VEX prefix
6595 for (j
= i
.operands
; j
> 0; j
--)
6597 i
.op
[j
] = i
.op
[j
- 1];
6598 i
.types
[j
] = i
.types
[j
- 1];
6599 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6602 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6603 i
.types
[0] = regxmm
;
6604 i
.tm
.operand_types
[0] = regxmm
;
6607 i
.reg_operands
+= 2;
6612 i
.op
[dupl
] = i
.op
[dest
];
6613 i
.types
[dupl
] = i
.types
[dest
];
6614 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6623 i
.op
[dupl
] = i
.op
[dest
];
6624 i
.types
[dupl
] = i
.types
[dest
];
6625 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6628 if (i
.tm
.opcode_modifier
.immext
)
6631 else if (i
.tm
.operand_types
[0].bitfield
.acc
6632 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6636 for (j
= 1; j
< i
.operands
; j
++)
6638 i
.op
[j
- 1] = i
.op
[j
];
6639 i
.types
[j
- 1] = i
.types
[j
];
6641 /* We need to adjust fields in i.tm since they are used by
6642 build_modrm_byte. */
6643 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6650 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6652 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6654 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6655 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6656 regnum
= register_number (i
.op
[1].regs
);
6657 first_reg_in_group
= regnum
& ~3;
6658 last_reg_in_group
= first_reg_in_group
+ 3;
6659 if (regnum
!= first_reg_in_group
)
6660 as_warn (_("source register `%s%s' implicitly denotes"
6661 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6662 register_prefix
, i
.op
[1].regs
->reg_name
,
6663 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6664 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6667 else if (i
.tm
.opcode_modifier
.regkludge
)
6669 /* The imul $imm, %reg instruction is converted into
6670 imul $imm, %reg, %reg, and the clr %reg instruction
6671 is converted into xor %reg, %reg. */
6673 unsigned int first_reg_op
;
6675 if (operand_type_check (i
.types
[0], reg
))
6679 /* Pretend we saw the extra register operand. */
6680 gas_assert (i
.reg_operands
== 1
6681 && i
.op
[first_reg_op
+ 1].regs
== 0);
6682 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6683 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6688 if (i
.tm
.opcode_modifier
.shortform
)
6690 if (i
.types
[0].bitfield
.sreg2
6691 || i
.types
[0].bitfield
.sreg3
)
6693 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6694 && i
.op
[0].regs
->reg_num
== 1)
6696 as_bad (_("you can't `pop %scs'"), register_prefix
);
6699 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6700 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6705 /* The register or float register operand is in operand
6709 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6710 || operand_type_check (i
.types
[0], reg
))
6714 /* Register goes in low 3 bits of opcode. */
6715 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6716 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6718 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6720 /* Warn about some common errors, but press on regardless.
6721 The first case can be generated by gcc (<= 2.8.1). */
6722 if (i
.operands
== 2)
6724 /* Reversed arguments on faddp, fsubp, etc. */
6725 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6726 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6727 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6731 /* Extraneous `l' suffix on fp insn. */
6732 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6733 register_prefix
, i
.op
[0].regs
->reg_name
);
6738 else if (i
.tm
.opcode_modifier
.modrm
)
6740 /* The opcode is completed (modulo i.tm.extension_opcode which
6741 must be put into the modrm byte). Now, we make the modrm and
6742 index base bytes based on all the info we've collected. */
6744 default_seg
= build_modrm_byte ();
6746 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6750 else if (i
.tm
.opcode_modifier
.isstring
)
6752 /* For the string instructions that allow a segment override
6753 on one of their operands, the default segment is ds. */
6757 if (i
.tm
.base_opcode
== 0x8d /* lea */
6760 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6762 /* If a segment was explicitly specified, and the specified segment
6763 is not the default, use an opcode prefix to select it. If we
6764 never figured out what the default segment is, then default_seg
6765 will be zero at this point, and the specified segment prefix will
6767 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6769 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6775 static const seg_entry
*
6776 build_modrm_byte (void)
6778 const seg_entry
*default_seg
= 0;
6779 unsigned int source
, dest
;
6782 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6785 unsigned int nds
, reg_slot
;
6788 dest
= i
.operands
- 1;
6791 /* There are 2 kinds of instructions:
6792 1. 5 operands: 4 register operands or 3 register operands
6793 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6794 VexW0 or VexW1. The destination must be either XMM, YMM or
6796 2. 4 operands: 4 register operands or 3 register operands
6797 plus 1 memory operand, with VexXDS. */
6798 gas_assert ((i
.reg_operands
== 4
6799 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6800 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6801 && i
.tm
.opcode_modifier
.vexw
6802 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6804 /* If VexW1 is set, the first non-immediate operand is the source and
6805 the second non-immediate one is encoded in the immediate operand. */
6806 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6808 source
= i
.imm_operands
;
6809 reg_slot
= i
.imm_operands
+ 1;
6813 source
= i
.imm_operands
+ 1;
6814 reg_slot
= i
.imm_operands
;
6817 if (i
.imm_operands
== 0)
6819 /* When there is no immediate operand, generate an 8bit
6820 immediate operand to encode the first operand. */
6821 exp
= &im_expressions
[i
.imm_operands
++];
6822 i
.op
[i
.operands
].imms
= exp
;
6823 i
.types
[i
.operands
] = imm8
;
6826 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6827 exp
->X_op
= O_constant
;
6828 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6829 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6833 unsigned int imm_slot
;
6835 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6837 if (i
.tm
.opcode_modifier
.immext
)
6839 /* When ImmExt is set, the immediate byte is the last
6841 imm_slot
= i
.operands
- 1;
6849 /* Turn on Imm8 so that output_imm will generate it. */
6850 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6853 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6854 i
.op
[imm_slot
].imms
->X_add_number
6855 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6856 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6859 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6860 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6865 /* i.reg_operands MUST be the number of real register operands;
6866 implicit registers do not count. If there are 3 register
6867 operands, it must be a instruction with VexNDS. For a
6868 instruction with VexNDD, the destination register is encoded
6869 in VEX prefix. If there are 4 register operands, it must be
6870 a instruction with VEX prefix and 3 sources. */
6871 if (i
.mem_operands
== 0
6872 && ((i
.reg_operands
== 2
6873 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6874 || (i
.reg_operands
== 3
6875 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6876 || (i
.reg_operands
== 4 && vex_3_sources
)))
6884 /* When there are 3 operands, one of them may be immediate,
6885 which may be the first or the last operand. Otherwise,
6886 the first operand must be shift count register (cl) or it
6887 is an instruction with VexNDS. */
6888 gas_assert (i
.imm_operands
== 1
6889 || (i
.imm_operands
== 0
6890 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6891 || i
.types
[0].bitfield
.shiftcount
)));
6892 if (operand_type_check (i
.types
[0], imm
)
6893 || i
.types
[0].bitfield
.shiftcount
)
6899 /* When there are 4 operands, the first two must be 8bit
6900 immediate operands. The source operand will be the 3rd
6903 For instructions with VexNDS, if the first operand
6904 an imm8, the source operand is the 2nd one. If the last
6905 operand is imm8, the source operand is the first one. */
6906 gas_assert ((i
.imm_operands
== 2
6907 && i
.types
[0].bitfield
.imm8
6908 && i
.types
[1].bitfield
.imm8
)
6909 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6910 && i
.imm_operands
== 1
6911 && (i
.types
[0].bitfield
.imm8
6912 || i
.types
[i
.operands
- 1].bitfield
.imm8
6914 if (i
.imm_operands
== 2)
6918 if (i
.types
[0].bitfield
.imm8
)
6925 if (is_evex_encoding (&i
.tm
))
6927 /* For EVEX instructions, when there are 5 operands, the
6928 first one must be immediate operand. If the second one
6929 is immediate operand, the source operand is the 3th
6930 one. If the last one is immediate operand, the source
6931 operand is the 2nd one. */
6932 gas_assert (i
.imm_operands
== 2
6933 && i
.tm
.opcode_modifier
.sae
6934 && operand_type_check (i
.types
[0], imm
));
6935 if (operand_type_check (i
.types
[1], imm
))
6937 else if (operand_type_check (i
.types
[4], imm
))
6951 /* RC/SAE operand could be between DEST and SRC. That happens
6952 when one operand is GPR and the other one is XMM/YMM/ZMM
6954 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6957 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6959 /* For instructions with VexNDS, the register-only source
6960 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6961 register. It is encoded in VEX prefix. We need to
6962 clear RegMem bit before calling operand_type_equal. */
6964 i386_operand_type op
;
6967 /* Check register-only source operand when two source
6968 operands are swapped. */
6969 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6970 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6978 op
= i
.tm
.operand_types
[vvvv
];
6979 op
.bitfield
.regmem
= 0;
6980 if ((dest
+ 1) >= i
.operands
6981 || ((!op
.bitfield
.reg
6982 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6983 && !op
.bitfield
.regsimd
6984 && !operand_type_equal (&op
, ®mask
)))
6986 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6992 /* One of the register operands will be encoded in the i.tm.reg
6993 field, the other in the combined i.tm.mode and i.tm.regmem
6994 fields. If no form of this instruction supports a memory
6995 destination operand, then we assume the source operand may
6996 sometimes be a memory operand and so we need to store the
6997 destination in the i.rm.reg field. */
6998 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6999 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7001 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7002 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7003 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7005 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7007 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7009 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7014 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7015 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7016 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7018 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7020 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7022 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7025 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7027 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7030 add_prefix (LOCK_PREFIX_OPCODE
);
7034 { /* If it's not 2 reg operands... */
7039 unsigned int fake_zero_displacement
= 0;
7042 for (op
= 0; op
< i
.operands
; op
++)
7043 if (operand_type_check (i
.types
[op
], anymem
))
7045 gas_assert (op
< i
.operands
);
7047 if (i
.tm
.opcode_modifier
.vecsib
)
7049 if (i
.index_reg
->reg_num
== RegEiz
7050 || i
.index_reg
->reg_num
== RegRiz
)
7053 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7056 i
.sib
.base
= NO_BASE_REGISTER
;
7057 i
.sib
.scale
= i
.log2_scale_factor
;
7058 i
.types
[op
].bitfield
.disp8
= 0;
7059 i
.types
[op
].bitfield
.disp16
= 0;
7060 i
.types
[op
].bitfield
.disp64
= 0;
7061 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7063 /* Must be 32 bit */
7064 i
.types
[op
].bitfield
.disp32
= 1;
7065 i
.types
[op
].bitfield
.disp32s
= 0;
7069 i
.types
[op
].bitfield
.disp32
= 0;
7070 i
.types
[op
].bitfield
.disp32s
= 1;
7073 i
.sib
.index
= i
.index_reg
->reg_num
;
7074 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7076 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7082 if (i
.base_reg
== 0)
7085 if (!i
.disp_operands
)
7086 fake_zero_displacement
= 1;
7087 if (i
.index_reg
== 0)
7089 i386_operand_type newdisp
;
7091 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7092 /* Operand is just <disp> */
7093 if (flag_code
== CODE_64BIT
)
7095 /* 64bit mode overwrites the 32bit absolute
7096 addressing by RIP relative addressing and
7097 absolute addressing is encoded by one of the
7098 redundant SIB forms. */
7099 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7100 i
.sib
.base
= NO_BASE_REGISTER
;
7101 i
.sib
.index
= NO_INDEX_REGISTER
;
7102 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7104 else if ((flag_code
== CODE_16BIT
)
7105 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7107 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7112 i
.rm
.regmem
= NO_BASE_REGISTER
;
7115 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7116 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7118 else if (!i
.tm
.opcode_modifier
.vecsib
)
7120 /* !i.base_reg && i.index_reg */
7121 if (i
.index_reg
->reg_num
== RegEiz
7122 || i
.index_reg
->reg_num
== RegRiz
)
7123 i
.sib
.index
= NO_INDEX_REGISTER
;
7125 i
.sib
.index
= i
.index_reg
->reg_num
;
7126 i
.sib
.base
= NO_BASE_REGISTER
;
7127 i
.sib
.scale
= i
.log2_scale_factor
;
7128 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7129 i
.types
[op
].bitfield
.disp8
= 0;
7130 i
.types
[op
].bitfield
.disp16
= 0;
7131 i
.types
[op
].bitfield
.disp64
= 0;
7132 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7134 /* Must be 32 bit */
7135 i
.types
[op
].bitfield
.disp32
= 1;
7136 i
.types
[op
].bitfield
.disp32s
= 0;
7140 i
.types
[op
].bitfield
.disp32
= 0;
7141 i
.types
[op
].bitfield
.disp32s
= 1;
7143 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7147 /* RIP addressing for 64bit mode. */
7148 else if (i
.base_reg
->reg_num
== RegRip
||
7149 i
.base_reg
->reg_num
== RegEip
)
7151 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7152 i
.rm
.regmem
= NO_BASE_REGISTER
;
7153 i
.types
[op
].bitfield
.disp8
= 0;
7154 i
.types
[op
].bitfield
.disp16
= 0;
7155 i
.types
[op
].bitfield
.disp32
= 0;
7156 i
.types
[op
].bitfield
.disp32s
= 1;
7157 i
.types
[op
].bitfield
.disp64
= 0;
7158 i
.flags
[op
] |= Operand_PCrel
;
7159 if (! i
.disp_operands
)
7160 fake_zero_displacement
= 1;
7162 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7164 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7165 switch (i
.base_reg
->reg_num
)
7168 if (i
.index_reg
== 0)
7170 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7171 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7175 if (i
.index_reg
== 0)
7178 if (operand_type_check (i
.types
[op
], disp
) == 0)
7180 /* fake (%bp) into 0(%bp) */
7181 i
.types
[op
].bitfield
.disp8
= 1;
7182 fake_zero_displacement
= 1;
7185 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7186 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7188 default: /* (%si) -> 4 or (%di) -> 5 */
7189 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7191 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7193 else /* i.base_reg and 32/64 bit mode */
7195 if (flag_code
== CODE_64BIT
7196 && operand_type_check (i
.types
[op
], disp
))
7198 i
.types
[op
].bitfield
.disp16
= 0;
7199 i
.types
[op
].bitfield
.disp64
= 0;
7200 if (i
.prefix
[ADDR_PREFIX
] == 0)
7202 i
.types
[op
].bitfield
.disp32
= 0;
7203 i
.types
[op
].bitfield
.disp32s
= 1;
7207 i
.types
[op
].bitfield
.disp32
= 1;
7208 i
.types
[op
].bitfield
.disp32s
= 0;
7212 if (!i
.tm
.opcode_modifier
.vecsib
)
7213 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7214 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7216 i
.sib
.base
= i
.base_reg
->reg_num
;
7217 /* x86-64 ignores REX prefix bit here to avoid decoder
7219 if (!(i
.base_reg
->reg_flags
& RegRex
)
7220 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7221 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7223 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7225 fake_zero_displacement
= 1;
7226 i
.types
[op
].bitfield
.disp8
= 1;
7228 i
.sib
.scale
= i
.log2_scale_factor
;
7229 if (i
.index_reg
== 0)
7231 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7232 /* <disp>(%esp) becomes two byte modrm with no index
7233 register. We've already stored the code for esp
7234 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7235 Any base register besides %esp will not use the
7236 extra modrm byte. */
7237 i
.sib
.index
= NO_INDEX_REGISTER
;
7239 else if (!i
.tm
.opcode_modifier
.vecsib
)
7241 if (i
.index_reg
->reg_num
== RegEiz
7242 || i
.index_reg
->reg_num
== RegRiz
)
7243 i
.sib
.index
= NO_INDEX_REGISTER
;
7245 i
.sib
.index
= i
.index_reg
->reg_num
;
7246 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7247 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7252 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7253 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7257 if (!fake_zero_displacement
7261 fake_zero_displacement
= 1;
7262 if (i
.disp_encoding
== disp_encoding_8bit
)
7263 i
.types
[op
].bitfield
.disp8
= 1;
7265 i
.types
[op
].bitfield
.disp32
= 1;
7267 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7271 if (fake_zero_displacement
)
7273 /* Fakes a zero displacement assuming that i.types[op]
7274 holds the correct displacement size. */
7277 gas_assert (i
.op
[op
].disps
== 0);
7278 exp
= &disp_expressions
[i
.disp_operands
++];
7279 i
.op
[op
].disps
= exp
;
7280 exp
->X_op
= O_constant
;
7281 exp
->X_add_number
= 0;
7282 exp
->X_add_symbol
= (symbolS
*) 0;
7283 exp
->X_op_symbol
= (symbolS
*) 0;
7291 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7293 if (operand_type_check (i
.types
[0], imm
))
7294 i
.vex
.register_specifier
= NULL
;
7297 /* VEX.vvvv encodes one of the sources when the first
7298 operand is not an immediate. */
7299 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7300 i
.vex
.register_specifier
= i
.op
[0].regs
;
7302 i
.vex
.register_specifier
= i
.op
[1].regs
;
7305 /* Destination is a XMM register encoded in the ModRM.reg
7307 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7308 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7311 /* ModRM.rm and VEX.B encodes the other source. */
7312 if (!i
.mem_operands
)
7316 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7317 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7319 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7321 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7325 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7327 i
.vex
.register_specifier
= i
.op
[2].regs
;
7328 if (!i
.mem_operands
)
7331 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7332 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7336 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7337 (if any) based on i.tm.extension_opcode. Again, we must be
7338 careful to make sure that segment/control/debug/test/MMX
7339 registers are coded into the i.rm.reg field. */
7340 else if (i
.reg_operands
)
7343 unsigned int vex_reg
= ~0;
7345 for (op
= 0; op
< i
.operands
; op
++)
7346 if (i
.types
[op
].bitfield
.reg
7347 || i
.types
[op
].bitfield
.regmmx
7348 || i
.types
[op
].bitfield
.regsimd
7349 || i
.types
[op
].bitfield
.regbnd
7350 || i
.types
[op
].bitfield
.regmask
7351 || i
.types
[op
].bitfield
.sreg2
7352 || i
.types
[op
].bitfield
.sreg3
7353 || i
.types
[op
].bitfield
.control
7354 || i
.types
[op
].bitfield
.debug
7355 || i
.types
[op
].bitfield
.test
)
7360 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7362 /* For instructions with VexNDS, the register-only
7363 source operand is encoded in VEX prefix. */
7364 gas_assert (mem
!= (unsigned int) ~0);
7369 gas_assert (op
< i
.operands
);
7373 /* Check register-only source operand when two source
7374 operands are swapped. */
7375 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7376 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7380 gas_assert (mem
== (vex_reg
+ 1)
7381 && op
< i
.operands
);
7386 gas_assert (vex_reg
< i
.operands
);
7390 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7392 /* For instructions with VexNDD, the register destination
7393 is encoded in VEX prefix. */
7394 if (i
.mem_operands
== 0)
7396 /* There is no memory operand. */
7397 gas_assert ((op
+ 2) == i
.operands
);
7402 /* There are only 2 non-immediate operands. */
7403 gas_assert (op
< i
.imm_operands
+ 2
7404 && i
.operands
== i
.imm_operands
+ 2);
7405 vex_reg
= i
.imm_operands
+ 1;
7409 gas_assert (op
< i
.operands
);
7411 if (vex_reg
!= (unsigned int) ~0)
7413 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7415 if ((!type
->bitfield
.reg
7416 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7417 && !type
->bitfield
.regsimd
7418 && !operand_type_equal (type
, ®mask
))
7421 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7424 /* Don't set OP operand twice. */
7427 /* If there is an extension opcode to put here, the
7428 register number must be put into the regmem field. */
7429 if (i
.tm
.extension_opcode
!= None
)
7431 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7432 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7434 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7439 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7440 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7442 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7447 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7448 must set it to 3 to indicate this is a register operand
7449 in the regmem field. */
7450 if (!i
.mem_operands
)
7454 /* Fill in i.rm.reg field with extension opcode (if any). */
7455 if (i
.tm
.extension_opcode
!= None
)
7456 i
.rm
.reg
= i
.tm
.extension_opcode
;
7462 output_branch (void)
7468 relax_substateT subtype
;
7472 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7473 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7476 if (i
.prefix
[DATA_PREFIX
] != 0)
7482 /* Pentium4 branch hints. */
7483 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7484 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7489 if (i
.prefix
[REX_PREFIX
] != 0)
7495 /* BND prefixed jump. */
7496 if (i
.prefix
[BND_PREFIX
] != 0)
7498 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7502 if (i
.prefixes
!= 0 && !intel_syntax
)
7503 as_warn (_("skipping prefixes on this instruction"));
7505 /* It's always a symbol; End frag & setup for relax.
7506 Make sure there is enough room in this frag for the largest
7507 instruction we may generate in md_convert_frag. This is 2
7508 bytes for the opcode and room for the prefix and largest
7510 frag_grow (prefix
+ 2 + 4);
7511 /* Prefix and 1 opcode byte go in fr_fix. */
7512 p
= frag_more (prefix
+ 1);
7513 if (i
.prefix
[DATA_PREFIX
] != 0)
7514 *p
++ = DATA_PREFIX_OPCODE
;
7515 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7516 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7517 *p
++ = i
.prefix
[SEG_PREFIX
];
7518 if (i
.prefix
[REX_PREFIX
] != 0)
7519 *p
++ = i
.prefix
[REX_PREFIX
];
7520 *p
= i
.tm
.base_opcode
;
7522 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7523 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7524 else if (cpu_arch_flags
.bitfield
.cpui386
)
7525 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7527 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7530 sym
= i
.op
[0].disps
->X_add_symbol
;
7531 off
= i
.op
[0].disps
->X_add_number
;
7533 if (i
.op
[0].disps
->X_op
!= O_constant
7534 && i
.op
[0].disps
->X_op
!= O_symbol
)
7536 /* Handle complex expressions. */
7537 sym
= make_expr_symbol (i
.op
[0].disps
);
7541 /* 1 possible extra opcode + 4 byte displacement go in var part.
7542 Pass reloc in fr_var. */
7543 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7547 /* Return TRUE iff PLT32 relocation should be used for branching to
7551 need_plt32_p (symbolS
*s
)
7553 /* PLT32 relocation is ELF only. */
7557 /* Since there is no need to prepare for PLT branch on x86-64, we
7558 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7559 be used as a marker for 32-bit PC-relative branches. */
7563 /* Weak or undefined symbol need PLT32 relocation. */
7564 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7567 /* Non-global symbol doesn't need PLT32 relocation. */
7568 if (! S_IS_EXTERNAL (s
))
7571 /* Other global symbols need PLT32 relocation. NB: Symbol with
7572 non-default visibilities are treated as normal global symbol
7573 so that PLT32 relocation can be used as a marker for 32-bit
7574 PC-relative branches. It is useful for linker relaxation. */
7585 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7587 if (i
.tm
.opcode_modifier
.jumpbyte
)
7589 /* This is a loop or jecxz type instruction. */
7591 if (i
.prefix
[ADDR_PREFIX
] != 0)
7593 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7596 /* Pentium4 branch hints. */
7597 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7598 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7600 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7609 if (flag_code
== CODE_16BIT
)
7612 if (i
.prefix
[DATA_PREFIX
] != 0)
7614 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7624 if (i
.prefix
[REX_PREFIX
] != 0)
7626 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7630 /* BND prefixed jump. */
7631 if (i
.prefix
[BND_PREFIX
] != 0)
7633 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7637 if (i
.prefixes
!= 0 && !intel_syntax
)
7638 as_warn (_("skipping prefixes on this instruction"));
7640 p
= frag_more (i
.tm
.opcode_length
+ size
);
7641 switch (i
.tm
.opcode_length
)
7644 *p
++ = i
.tm
.base_opcode
>> 8;
7647 *p
++ = i
.tm
.base_opcode
;
7653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7655 && jump_reloc
== NO_RELOC
7656 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7657 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7660 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7662 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7663 i
.op
[0].disps
, 1, jump_reloc
);
7665 /* All jumps handled here are signed, but don't use a signed limit
7666 check for 32 and 16 bit jumps as we want to allow wrap around at
7667 4G and 64k respectively. */
7669 fixP
->fx_signed
= 1;
7673 output_interseg_jump (void)
7681 if (flag_code
== CODE_16BIT
)
7685 if (i
.prefix
[DATA_PREFIX
] != 0)
7691 if (i
.prefix
[REX_PREFIX
] != 0)
7701 if (i
.prefixes
!= 0 && !intel_syntax
)
7702 as_warn (_("skipping prefixes on this instruction"));
7704 /* 1 opcode; 2 segment; offset */
7705 p
= frag_more (prefix
+ 1 + 2 + size
);
7707 if (i
.prefix
[DATA_PREFIX
] != 0)
7708 *p
++ = DATA_PREFIX_OPCODE
;
7710 if (i
.prefix
[REX_PREFIX
] != 0)
7711 *p
++ = i
.prefix
[REX_PREFIX
];
7713 *p
++ = i
.tm
.base_opcode
;
7714 if (i
.op
[1].imms
->X_op
== O_constant
)
7716 offsetT n
= i
.op
[1].imms
->X_add_number
;
7719 && !fits_in_unsigned_word (n
)
7720 && !fits_in_signed_word (n
))
7722 as_bad (_("16-bit jump out of range"));
7725 md_number_to_chars (p
, n
, size
);
7728 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7729 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7730 if (i
.op
[0].imms
->X_op
!= O_constant
)
7731 as_bad (_("can't handle non absolute segment in `%s'"),
7733 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7739 fragS
*insn_start_frag
;
7740 offsetT insn_start_off
;
7742 /* Tie dwarf2 debug info to the address at the start of the insn.
7743 We can't do this after the insn has been output as the current
7744 frag may have been closed off. eg. by frag_var. */
7745 dwarf2_emit_insn (0);
7747 insn_start_frag
= frag_now
;
7748 insn_start_off
= frag_now_fix ();
7751 if (i
.tm
.opcode_modifier
.jump
)
7753 else if (i
.tm
.opcode_modifier
.jumpbyte
7754 || i
.tm
.opcode_modifier
.jumpdword
)
7756 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7757 output_interseg_jump ();
7760 /* Output normal instructions here. */
7764 unsigned int prefix
;
7767 && i
.tm
.base_opcode
== 0xfae
7769 && i
.imm_operands
== 1
7770 && (i
.op
[0].imms
->X_add_number
== 0xe8
7771 || i
.op
[0].imms
->X_add_number
== 0xf0
7772 || i
.op
[0].imms
->X_add_number
== 0xf8))
7774 /* Encode lfence, mfence, and sfence as
7775 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7776 offsetT val
= 0x240483f0ULL
;
7778 md_number_to_chars (p
, val
, 5);
7782 /* Some processors fail on LOCK prefix. This options makes
7783 assembler ignore LOCK prefix and serves as a workaround. */
7784 if (omit_lock_prefix
)
7786 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7788 i
.prefix
[LOCK_PREFIX
] = 0;
7791 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7792 don't need the explicit prefix. */
7793 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7795 switch (i
.tm
.opcode_length
)
7798 if (i
.tm
.base_opcode
& 0xff000000)
7800 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7801 add_prefix (prefix
);
7805 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7807 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7808 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7809 || prefix
!= REPE_PREFIX_OPCODE
7810 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7811 add_prefix (prefix
);
7817 /* Check for pseudo prefixes. */
7818 as_bad_where (insn_start_frag
->fr_file
,
7819 insn_start_frag
->fr_line
,
7820 _("pseudo prefix without instruction"));
7826 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7827 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7828 R_X86_64_GOTTPOFF relocation so that linker can safely
7829 perform IE->LE optimization. */
7830 if (x86_elf_abi
== X86_64_X32_ABI
7832 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7833 && i
.prefix
[REX_PREFIX
] == 0)
7834 add_prefix (REX_OPCODE
);
7837 /* The prefix bytes. */
7838 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7840 FRAG_APPEND_1_CHAR (*q
);
7844 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7849 /* REX byte is encoded in VEX prefix. */
7853 FRAG_APPEND_1_CHAR (*q
);
7856 /* There should be no other prefixes for instructions
7861 /* For EVEX instructions i.vrex should become 0 after
7862 build_evex_prefix. For VEX instructions upper 16 registers
7863 aren't available, so VREX should be 0. */
7866 /* Now the VEX prefix. */
7867 p
= frag_more (i
.vex
.length
);
7868 for (j
= 0; j
< i
.vex
.length
; j
++)
7869 p
[j
] = i
.vex
.bytes
[j
];
7872 /* Now the opcode; be careful about word order here! */
7873 if (i
.tm
.opcode_length
== 1)
7875 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7879 switch (i
.tm
.opcode_length
)
7883 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7884 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7888 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7898 /* Put out high byte first: can't use md_number_to_chars! */
7899 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7900 *p
= i
.tm
.base_opcode
& 0xff;
7903 /* Now the modrm byte and sib byte (if present). */
7904 if (i
.tm
.opcode_modifier
.modrm
)
7906 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7909 /* If i.rm.regmem == ESP (4)
7910 && i.rm.mode != (Register mode)
7912 ==> need second modrm byte. */
7913 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7915 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7916 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7918 | i
.sib
.scale
<< 6));
7921 if (i
.disp_operands
)
7922 output_disp (insn_start_frag
, insn_start_off
);
7925 output_imm (insn_start_frag
, insn_start_off
);
7931 pi ("" /*line*/, &i
);
7933 #endif /* DEBUG386 */
7936 /* Return the size of the displacement operand N. */
7939 disp_size (unsigned int n
)
7943 if (i
.types
[n
].bitfield
.disp64
)
7945 else if (i
.types
[n
].bitfield
.disp8
)
7947 else if (i
.types
[n
].bitfield
.disp16
)
7952 /* Return the size of the immediate operand N. */
7955 imm_size (unsigned int n
)
7958 if (i
.types
[n
].bitfield
.imm64
)
7960 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7962 else if (i
.types
[n
].bitfield
.imm16
)
7968 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7973 for (n
= 0; n
< i
.operands
; n
++)
7975 if (operand_type_check (i
.types
[n
], disp
))
7977 if (i
.op
[n
].disps
->X_op
== O_constant
)
7979 int size
= disp_size (n
);
7980 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7982 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
7984 p
= frag_more (size
);
7985 md_number_to_chars (p
, val
, size
);
7989 enum bfd_reloc_code_real reloc_type
;
7990 int size
= disp_size (n
);
7991 int sign
= i
.types
[n
].bitfield
.disp32s
;
7992 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7995 /* We can't have 8 bit displacement here. */
7996 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7998 /* The PC relative address is computed relative
7999 to the instruction boundary, so in case immediate
8000 fields follows, we need to adjust the value. */
8001 if (pcrel
&& i
.imm_operands
)
8006 for (n1
= 0; n1
< i
.operands
; n1
++)
8007 if (operand_type_check (i
.types
[n1
], imm
))
8009 /* Only one immediate is allowed for PC
8010 relative address. */
8011 gas_assert (sz
== 0);
8013 i
.op
[n
].disps
->X_add_number
-= sz
;
8015 /* We should find the immediate. */
8016 gas_assert (sz
!= 0);
8019 p
= frag_more (size
);
8020 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8022 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8023 && (((reloc_type
== BFD_RELOC_32
8024 || reloc_type
== BFD_RELOC_X86_64_32S
8025 || (reloc_type
== BFD_RELOC_64
8027 && (i
.op
[n
].disps
->X_op
== O_symbol
8028 || (i
.op
[n
].disps
->X_op
== O_add
8029 && ((symbol_get_value_expression
8030 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8032 || reloc_type
== BFD_RELOC_32_PCREL
))
8036 if (insn_start_frag
== frag_now
)
8037 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8042 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8043 for (fr
= insn_start_frag
->fr_next
;
8044 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8046 add
+= p
- frag_now
->fr_literal
;
8051 reloc_type
= BFD_RELOC_386_GOTPC
;
8052 i
.op
[n
].imms
->X_add_number
+= add
;
8054 else if (reloc_type
== BFD_RELOC_64
)
8055 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8057 /* Don't do the adjustment for x86-64, as there
8058 the pcrel addressing is relative to the _next_
8059 insn, and that is taken care of in other code. */
8060 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8062 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8063 size
, i
.op
[n
].disps
, pcrel
,
8065 /* Check for "call/jmp *mem", "mov mem, %reg",
8066 "test %reg, mem" and "binop mem, %reg" where binop
8067 is one of adc, add, and, cmp, or, sbb, sub, xor
8068 instructions. Always generate R_386_GOT32X for
8069 "sym*GOT" operand in 32-bit mode. */
8070 if ((generate_relax_relocations
8073 && i
.rm
.regmem
== 5))
8075 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8076 && ((i
.operands
== 1
8077 && i
.tm
.base_opcode
== 0xff
8078 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8080 && (i
.tm
.base_opcode
== 0x8b
8081 || i
.tm
.base_opcode
== 0x85
8082 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8086 fixP
->fx_tcbit
= i
.rex
!= 0;
8088 && (i
.base_reg
->reg_num
== RegRip
8089 || i
.base_reg
->reg_num
== RegEip
))
8090 fixP
->fx_tcbit2
= 1;
8093 fixP
->fx_tcbit2
= 1;
8101 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8106 for (n
= 0; n
< i
.operands
; n
++)
8108 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8109 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8112 if (operand_type_check (i
.types
[n
], imm
))
8114 if (i
.op
[n
].imms
->X_op
== O_constant
)
8116 int size
= imm_size (n
);
8119 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8121 p
= frag_more (size
);
8122 md_number_to_chars (p
, val
, size
);
8126 /* Not absolute_section.
8127 Need a 32-bit fixup (don't support 8bit
8128 non-absolute imms). Try to support other
8130 enum bfd_reloc_code_real reloc_type
;
8131 int size
= imm_size (n
);
8134 if (i
.types
[n
].bitfield
.imm32s
8135 && (i
.suffix
== QWORD_MNEM_SUFFIX
8136 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8141 p
= frag_more (size
);
8142 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8144 /* This is tough to explain. We end up with this one if we
8145 * have operands that look like
8146 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8147 * obtain the absolute address of the GOT, and it is strongly
8148 * preferable from a performance point of view to avoid using
8149 * a runtime relocation for this. The actual sequence of
8150 * instructions often look something like:
8155 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8157 * The call and pop essentially return the absolute address
8158 * of the label .L66 and store it in %ebx. The linker itself
8159 * will ultimately change the first operand of the addl so
8160 * that %ebx points to the GOT, but to keep things simple, the
8161 * .o file must have this operand set so that it generates not
8162 * the absolute address of .L66, but the absolute address of
8163 * itself. This allows the linker itself simply treat a GOTPC
8164 * relocation as asking for a pcrel offset to the GOT to be
8165 * added in, and the addend of the relocation is stored in the
8166 * operand field for the instruction itself.
8168 * Our job here is to fix the operand so that it would add
8169 * the correct offset so that %ebx would point to itself. The
8170 * thing that is tricky is that .-.L66 will point to the
8171 * beginning of the instruction, so we need to further modify
8172 * the operand so that it will point to itself. There are
8173 * other cases where you have something like:
8175 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8177 * and here no correction would be required. Internally in
8178 * the assembler we treat operands of this form as not being
8179 * pcrel since the '.' is explicitly mentioned, and I wonder
8180 * whether it would simplify matters to do it this way. Who
8181 * knows. In earlier versions of the PIC patches, the
8182 * pcrel_adjust field was used to store the correction, but
8183 * since the expression is not pcrel, I felt it would be
8184 * confusing to do it this way. */
8186 if ((reloc_type
== BFD_RELOC_32
8187 || reloc_type
== BFD_RELOC_X86_64_32S
8188 || reloc_type
== BFD_RELOC_64
)
8190 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8191 && (i
.op
[n
].imms
->X_op
== O_symbol
8192 || (i
.op
[n
].imms
->X_op
== O_add
8193 && ((symbol_get_value_expression
8194 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8199 if (insn_start_frag
== frag_now
)
8200 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8205 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8206 for (fr
= insn_start_frag
->fr_next
;
8207 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8209 add
+= p
- frag_now
->fr_literal
;
8213 reloc_type
= BFD_RELOC_386_GOTPC
;
8215 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8217 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8218 i
.op
[n
].imms
->X_add_number
+= add
;
8220 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8221 i
.op
[n
].imms
, 0, reloc_type
);
8227 /* x86_cons_fix_new is called via the expression parsing code when a
8228 reloc is needed. We use this hook to get the correct .got reloc. */
8229 static int cons_sign
= -1;
8232 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8233 expressionS
*exp
, bfd_reloc_code_real_type r
)
8235 r
= reloc (len
, 0, cons_sign
, r
);
8238 if (exp
->X_op
== O_secrel
)
8240 exp
->X_op
= O_symbol
;
8241 r
= BFD_RELOC_32_SECREL
;
8245 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8248 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8249 purpose of the `.dc.a' internal pseudo-op. */
8252 x86_address_bytes (void)
8254 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8256 return stdoutput
->arch_info
->bits_per_address
/ 8;
8259 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8261 # define lex_got(reloc, adjust, types) NULL
8263 /* Parse operands of the form
8264 <symbol>@GOTOFF+<nnn>
8265 and similar .plt or .got references.
8267 If we find one, set up the correct relocation in RELOC and copy the
8268 input string, minus the `@GOTOFF' into a malloc'd buffer for
8269 parsing by the calling routine. Return this buffer, and if ADJUST
8270 is non-null set it to the length of the string we removed from the
8271 input line. Otherwise return NULL. */
8273 lex_got (enum bfd_reloc_code_real
*rel
,
8275 i386_operand_type
*types
)
8277 /* Some of the relocations depend on the size of what field is to
8278 be relocated. But in our callers i386_immediate and i386_displacement
8279 we don't yet know the operand size (this will be set by insn
8280 matching). Hence we record the word32 relocation here,
8281 and adjust the reloc according to the real size in reloc(). */
8282 static const struct {
8285 const enum bfd_reloc_code_real rel
[2];
8286 const i386_operand_type types64
;
8288 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8289 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8291 OPERAND_TYPE_IMM32_64
},
8293 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8294 BFD_RELOC_X86_64_PLTOFF64
},
8295 OPERAND_TYPE_IMM64
},
8296 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8297 BFD_RELOC_X86_64_PLT32
},
8298 OPERAND_TYPE_IMM32_32S_DISP32
},
8299 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8300 BFD_RELOC_X86_64_GOTPLT64
},
8301 OPERAND_TYPE_IMM64_DISP64
},
8302 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8303 BFD_RELOC_X86_64_GOTOFF64
},
8304 OPERAND_TYPE_IMM64_DISP64
},
8305 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8306 BFD_RELOC_X86_64_GOTPCREL
},
8307 OPERAND_TYPE_IMM32_32S_DISP32
},
8308 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8309 BFD_RELOC_X86_64_TLSGD
},
8310 OPERAND_TYPE_IMM32_32S_DISP32
},
8311 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8312 _dummy_first_bfd_reloc_code_real
},
8313 OPERAND_TYPE_NONE
},
8314 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8315 BFD_RELOC_X86_64_TLSLD
},
8316 OPERAND_TYPE_IMM32_32S_DISP32
},
8317 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8318 BFD_RELOC_X86_64_GOTTPOFF
},
8319 OPERAND_TYPE_IMM32_32S_DISP32
},
8320 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8321 BFD_RELOC_X86_64_TPOFF32
},
8322 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8323 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8324 _dummy_first_bfd_reloc_code_real
},
8325 OPERAND_TYPE_NONE
},
8326 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8327 BFD_RELOC_X86_64_DTPOFF32
},
8328 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8329 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8330 _dummy_first_bfd_reloc_code_real
},
8331 OPERAND_TYPE_NONE
},
8332 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8333 _dummy_first_bfd_reloc_code_real
},
8334 OPERAND_TYPE_NONE
},
8335 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8336 BFD_RELOC_X86_64_GOT32
},
8337 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8338 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8339 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8340 OPERAND_TYPE_IMM32_32S_DISP32
},
8341 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8342 BFD_RELOC_X86_64_TLSDESC_CALL
},
8343 OPERAND_TYPE_IMM32_32S_DISP32
},
8348 #if defined (OBJ_MAYBE_ELF)
8353 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8354 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8357 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8359 int len
= gotrel
[j
].len
;
8360 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8362 if (gotrel
[j
].rel
[object_64bit
] != 0)
8365 char *tmpbuf
, *past_reloc
;
8367 *rel
= gotrel
[j
].rel
[object_64bit
];
8371 if (flag_code
!= CODE_64BIT
)
8373 types
->bitfield
.imm32
= 1;
8374 types
->bitfield
.disp32
= 1;
8377 *types
= gotrel
[j
].types64
;
8380 if (j
!= 0 && GOT_symbol
== NULL
)
8381 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8383 /* The length of the first part of our input line. */
8384 first
= cp
- input_line_pointer
;
8386 /* The second part goes from after the reloc token until
8387 (and including) an end_of_line char or comma. */
8388 past_reloc
= cp
+ 1 + len
;
8390 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8392 second
= cp
+ 1 - past_reloc
;
8394 /* Allocate and copy string. The trailing NUL shouldn't
8395 be necessary, but be safe. */
8396 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8397 memcpy (tmpbuf
, input_line_pointer
, first
);
8398 if (second
!= 0 && *past_reloc
!= ' ')
8399 /* Replace the relocation token with ' ', so that
8400 errors like foo@GOTOFF1 will be detected. */
8401 tmpbuf
[first
++] = ' ';
8403 /* Increment length by 1 if the relocation token is
8408 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8409 tmpbuf
[first
+ second
] = '\0';
8413 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8414 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8419 /* Might be a symbol version string. Don't as_bad here. */
8428 /* Parse operands of the form
8429 <symbol>@SECREL32+<nnn>
8431 If we find one, set up the correct relocation in RELOC and copy the
8432 input string, minus the `@SECREL32' into a malloc'd buffer for
8433 parsing by the calling routine. Return this buffer, and if ADJUST
8434 is non-null set it to the length of the string we removed from the
8435 input line. Otherwise return NULL.
8437 This function is copied from the ELF version above adjusted for PE targets. */
8440 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8441 int *adjust ATTRIBUTE_UNUSED
,
8442 i386_operand_type
*types
)
8448 const enum bfd_reloc_code_real rel
[2];
8449 const i386_operand_type types64
;
8453 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8454 BFD_RELOC_32_SECREL
},
8455 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8461 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8462 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8465 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8467 int len
= gotrel
[j
].len
;
8469 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8471 if (gotrel
[j
].rel
[object_64bit
] != 0)
8474 char *tmpbuf
, *past_reloc
;
8476 *rel
= gotrel
[j
].rel
[object_64bit
];
8482 if (flag_code
!= CODE_64BIT
)
8484 types
->bitfield
.imm32
= 1;
8485 types
->bitfield
.disp32
= 1;
8488 *types
= gotrel
[j
].types64
;
8491 /* The length of the first part of our input line. */
8492 first
= cp
- input_line_pointer
;
8494 /* The second part goes from after the reloc token until
8495 (and including) an end_of_line char or comma. */
8496 past_reloc
= cp
+ 1 + len
;
8498 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8500 second
= cp
+ 1 - past_reloc
;
8502 /* Allocate and copy string. The trailing NUL shouldn't
8503 be necessary, but be safe. */
8504 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8505 memcpy (tmpbuf
, input_line_pointer
, first
);
8506 if (second
!= 0 && *past_reloc
!= ' ')
8507 /* Replace the relocation token with ' ', so that
8508 errors like foo@SECLREL321 will be detected. */
8509 tmpbuf
[first
++] = ' ';
8510 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8511 tmpbuf
[first
+ second
] = '\0';
8515 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8516 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8521 /* Might be a symbol version string. Don't as_bad here. */
8527 bfd_reloc_code_real_type
8528 x86_cons (expressionS
*exp
, int size
)
8530 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8532 intel_syntax
= -intel_syntax
;
8535 if (size
== 4 || (object_64bit
&& size
== 8))
8537 /* Handle @GOTOFF and the like in an expression. */
8539 char *gotfree_input_line
;
8542 save
= input_line_pointer
;
8543 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8544 if (gotfree_input_line
)
8545 input_line_pointer
= gotfree_input_line
;
8549 if (gotfree_input_line
)
8551 /* expression () has merrily parsed up to the end of line,
8552 or a comma - in the wrong buffer. Transfer how far
8553 input_line_pointer has moved to the right buffer. */
8554 input_line_pointer
= (save
8555 + (input_line_pointer
- gotfree_input_line
)
8557 free (gotfree_input_line
);
8558 if (exp
->X_op
== O_constant
8559 || exp
->X_op
== O_absent
8560 || exp
->X_op
== O_illegal
8561 || exp
->X_op
== O_register
8562 || exp
->X_op
== O_big
)
8564 char c
= *input_line_pointer
;
8565 *input_line_pointer
= 0;
8566 as_bad (_("missing or invalid expression `%s'"), save
);
8567 *input_line_pointer
= c
;
8574 intel_syntax
= -intel_syntax
;
8577 i386_intel_simplify (exp
);
8583 signed_cons (int size
)
8585 if (flag_code
== CODE_64BIT
)
8593 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8600 if (exp
.X_op
== O_symbol
)
8601 exp
.X_op
= O_secrel
;
8603 emit_expr (&exp
, 4);
8605 while (*input_line_pointer
++ == ',');
8607 input_line_pointer
--;
8608 demand_empty_rest_of_line ();
8612 /* Handle Vector operations. */
8615 check_VecOperations (char *op_string
, char *op_end
)
8617 const reg_entry
*mask
;
8622 && (op_end
== NULL
|| op_string
< op_end
))
8625 if (*op_string
== '{')
8629 /* Check broadcasts. */
8630 if (strncmp (op_string
, "1to", 3) == 0)
8635 goto duplicated_vec_op
;
8638 if (*op_string
== '8')
8640 else if (*op_string
== '4')
8642 else if (*op_string
== '2')
8644 else if (*op_string
== '1'
8645 && *(op_string
+1) == '6')
8652 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8657 broadcast_op
.type
= bcst_type
;
8658 broadcast_op
.operand
= this_operand
;
8659 broadcast_op
.bytes
= 0;
8660 i
.broadcast
= &broadcast_op
;
8662 /* Check masking operation. */
8663 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8665 /* k0 can't be used for write mask. */
8666 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8668 as_bad (_("`%s%s' can't be used for write mask"),
8669 register_prefix
, mask
->reg_name
);
8675 mask_op
.mask
= mask
;
8676 mask_op
.zeroing
= 0;
8677 mask_op
.operand
= this_operand
;
8683 goto duplicated_vec_op
;
8685 i
.mask
->mask
= mask
;
8687 /* Only "{z}" is allowed here. No need to check
8688 zeroing mask explicitly. */
8689 if (i
.mask
->operand
!= this_operand
)
8691 as_bad (_("invalid write mask `%s'"), saved
);
8698 /* Check zeroing-flag for masking operation. */
8699 else if (*op_string
== 'z')
8703 mask_op
.mask
= NULL
;
8704 mask_op
.zeroing
= 1;
8705 mask_op
.operand
= this_operand
;
8710 if (i
.mask
->zeroing
)
8713 as_bad (_("duplicated `%s'"), saved
);
8717 i
.mask
->zeroing
= 1;
8719 /* Only "{%k}" is allowed here. No need to check mask
8720 register explicitly. */
8721 if (i
.mask
->operand
!= this_operand
)
8723 as_bad (_("invalid zeroing-masking `%s'"),
8732 goto unknown_vec_op
;
8734 if (*op_string
!= '}')
8736 as_bad (_("missing `}' in `%s'"), saved
);
8741 /* Strip whitespace since the addition of pseudo prefixes
8742 changed how the scrubber treats '{'. */
8743 if (is_space_char (*op_string
))
8749 /* We don't know this one. */
8750 as_bad (_("unknown vector operation: `%s'"), saved
);
8754 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8756 as_bad (_("zeroing-masking only allowed with write mask"));
8764 i386_immediate (char *imm_start
)
8766 char *save_input_line_pointer
;
8767 char *gotfree_input_line
;
8770 i386_operand_type types
;
8772 operand_type_set (&types
, ~0);
8774 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8776 as_bad (_("at most %d immediate operands are allowed"),
8777 MAX_IMMEDIATE_OPERANDS
);
8781 exp
= &im_expressions
[i
.imm_operands
++];
8782 i
.op
[this_operand
].imms
= exp
;
8784 if (is_space_char (*imm_start
))
8787 save_input_line_pointer
= input_line_pointer
;
8788 input_line_pointer
= imm_start
;
8790 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8791 if (gotfree_input_line
)
8792 input_line_pointer
= gotfree_input_line
;
8794 exp_seg
= expression (exp
);
8798 /* Handle vector operations. */
8799 if (*input_line_pointer
== '{')
8801 input_line_pointer
= check_VecOperations (input_line_pointer
,
8803 if (input_line_pointer
== NULL
)
8807 if (*input_line_pointer
)
8808 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8810 input_line_pointer
= save_input_line_pointer
;
8811 if (gotfree_input_line
)
8813 free (gotfree_input_line
);
8815 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8816 exp
->X_op
= O_illegal
;
8819 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8823 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8824 i386_operand_type types
, const char *imm_start
)
8826 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8829 as_bad (_("missing or invalid immediate expression `%s'"),
8833 else if (exp
->X_op
== O_constant
)
8835 /* Size it properly later. */
8836 i
.types
[this_operand
].bitfield
.imm64
= 1;
8837 /* If not 64bit, sign extend val. */
8838 if (flag_code
!= CODE_64BIT
8839 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8841 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8843 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8844 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8845 && exp_seg
!= absolute_section
8846 && exp_seg
!= text_section
8847 && exp_seg
!= data_section
8848 && exp_seg
!= bss_section
8849 && exp_seg
!= undefined_section
8850 && !bfd_is_com_section (exp_seg
))
8852 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8856 else if (!intel_syntax
&& exp_seg
== reg_section
)
8859 as_bad (_("illegal immediate register operand %s"), imm_start
);
8864 /* This is an address. The size of the address will be
8865 determined later, depending on destination register,
8866 suffix, or the default for the section. */
8867 i
.types
[this_operand
].bitfield
.imm8
= 1;
8868 i
.types
[this_operand
].bitfield
.imm16
= 1;
8869 i
.types
[this_operand
].bitfield
.imm32
= 1;
8870 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8871 i
.types
[this_operand
].bitfield
.imm64
= 1;
8872 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8880 i386_scale (char *scale
)
8883 char *save
= input_line_pointer
;
8885 input_line_pointer
= scale
;
8886 val
= get_absolute_expression ();
8891 i
.log2_scale_factor
= 0;
8894 i
.log2_scale_factor
= 1;
8897 i
.log2_scale_factor
= 2;
8900 i
.log2_scale_factor
= 3;
8904 char sep
= *input_line_pointer
;
8906 *input_line_pointer
= '\0';
8907 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8909 *input_line_pointer
= sep
;
8910 input_line_pointer
= save
;
8914 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8916 as_warn (_("scale factor of %d without an index register"),
8917 1 << i
.log2_scale_factor
);
8918 i
.log2_scale_factor
= 0;
8920 scale
= input_line_pointer
;
8921 input_line_pointer
= save
;
8926 i386_displacement (char *disp_start
, char *disp_end
)
8930 char *save_input_line_pointer
;
8931 char *gotfree_input_line
;
8933 i386_operand_type bigdisp
, types
= anydisp
;
8936 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8938 as_bad (_("at most %d displacement operands are allowed"),
8939 MAX_MEMORY_OPERANDS
);
8943 operand_type_set (&bigdisp
, 0);
8944 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8945 || (!current_templates
->start
->opcode_modifier
.jump
8946 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8948 bigdisp
.bitfield
.disp32
= 1;
8949 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8950 if (flag_code
== CODE_64BIT
)
8954 bigdisp
.bitfield
.disp32s
= 1;
8955 bigdisp
.bitfield
.disp64
= 1;
8958 else if ((flag_code
== CODE_16BIT
) ^ override
)
8960 bigdisp
.bitfield
.disp32
= 0;
8961 bigdisp
.bitfield
.disp16
= 1;
8966 /* For PC-relative branches, the width of the displacement
8967 is dependent upon data size, not address size. */
8968 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8969 if (flag_code
== CODE_64BIT
)
8971 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8972 bigdisp
.bitfield
.disp16
= 1;
8975 bigdisp
.bitfield
.disp32
= 1;
8976 bigdisp
.bitfield
.disp32s
= 1;
8982 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8984 : LONG_MNEM_SUFFIX
));
8985 bigdisp
.bitfield
.disp32
= 1;
8986 if ((flag_code
== CODE_16BIT
) ^ override
)
8988 bigdisp
.bitfield
.disp32
= 0;
8989 bigdisp
.bitfield
.disp16
= 1;
8993 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8996 exp
= &disp_expressions
[i
.disp_operands
];
8997 i
.op
[this_operand
].disps
= exp
;
8999 save_input_line_pointer
= input_line_pointer
;
9000 input_line_pointer
= disp_start
;
9001 END_STRING_AND_SAVE (disp_end
);
9003 #ifndef GCC_ASM_O_HACK
9004 #define GCC_ASM_O_HACK 0
9007 END_STRING_AND_SAVE (disp_end
+ 1);
9008 if (i
.types
[this_operand
].bitfield
.baseIndex
9009 && displacement_string_end
[-1] == '+')
9011 /* This hack is to avoid a warning when using the "o"
9012 constraint within gcc asm statements.
9015 #define _set_tssldt_desc(n,addr,limit,type) \
9016 __asm__ __volatile__ ( \
9018 "movw %w1,2+%0\n\t" \
9020 "movb %b1,4+%0\n\t" \
9021 "movb %4,5+%0\n\t" \
9022 "movb $0,6+%0\n\t" \
9023 "movb %h1,7+%0\n\t" \
9025 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9027 This works great except that the output assembler ends
9028 up looking a bit weird if it turns out that there is
9029 no offset. You end up producing code that looks like:
9042 So here we provide the missing zero. */
9044 *displacement_string_end
= '0';
9047 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9048 if (gotfree_input_line
)
9049 input_line_pointer
= gotfree_input_line
;
9051 exp_seg
= expression (exp
);
9054 if (*input_line_pointer
)
9055 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9057 RESTORE_END_STRING (disp_end
+ 1);
9059 input_line_pointer
= save_input_line_pointer
;
9060 if (gotfree_input_line
)
9062 free (gotfree_input_line
);
9064 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9065 exp
->X_op
= O_illegal
;
9068 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9070 RESTORE_END_STRING (disp_end
);
9076 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9077 i386_operand_type types
, const char *disp_start
)
9079 i386_operand_type bigdisp
;
9082 /* We do this to make sure that the section symbol is in
9083 the symbol table. We will ultimately change the relocation
9084 to be relative to the beginning of the section. */
9085 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9086 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9087 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9089 if (exp
->X_op
!= O_symbol
)
9092 if (S_IS_LOCAL (exp
->X_add_symbol
)
9093 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9094 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9095 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9096 exp
->X_op
= O_subtract
;
9097 exp
->X_op_symbol
= GOT_symbol
;
9098 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9099 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9100 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9101 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9103 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9106 else if (exp
->X_op
== O_absent
9107 || exp
->X_op
== O_illegal
9108 || exp
->X_op
== O_big
)
9111 as_bad (_("missing or invalid displacement expression `%s'"),
9116 else if (flag_code
== CODE_64BIT
9117 && !i
.prefix
[ADDR_PREFIX
]
9118 && exp
->X_op
== O_constant
)
9120 /* Since displacement is signed extended to 64bit, don't allow
9121 disp32 and turn off disp32s if they are out of range. */
9122 i
.types
[this_operand
].bitfield
.disp32
= 0;
9123 if (!fits_in_signed_long (exp
->X_add_number
))
9125 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9126 if (i
.types
[this_operand
].bitfield
.baseindex
)
9128 as_bad (_("0x%lx out range of signed 32bit displacement"),
9129 (long) exp
->X_add_number
);
9135 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9136 else if (exp
->X_op
!= O_constant
9137 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9138 && exp_seg
!= absolute_section
9139 && exp_seg
!= text_section
9140 && exp_seg
!= data_section
9141 && exp_seg
!= bss_section
9142 && exp_seg
!= undefined_section
9143 && !bfd_is_com_section (exp_seg
))
9145 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9150 /* Check if this is a displacement only operand. */
9151 bigdisp
= i
.types
[this_operand
];
9152 bigdisp
.bitfield
.disp8
= 0;
9153 bigdisp
.bitfield
.disp16
= 0;
9154 bigdisp
.bitfield
.disp32
= 0;
9155 bigdisp
.bitfield
.disp32s
= 0;
9156 bigdisp
.bitfield
.disp64
= 0;
9157 if (operand_type_all_zero (&bigdisp
))
9158 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9164 /* Return the active addressing mode, taking address override and
9165 registers forming the address into consideration. Update the
9166 address override prefix if necessary. */
9168 static enum flag_code
9169 i386_addressing_mode (void)
9171 enum flag_code addr_mode
;
9173 if (i
.prefix
[ADDR_PREFIX
])
9174 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9177 addr_mode
= flag_code
;
9179 #if INFER_ADDR_PREFIX
9180 if (i
.mem_operands
== 0)
9182 /* Infer address prefix from the first memory operand. */
9183 const reg_entry
*addr_reg
= i
.base_reg
;
9185 if (addr_reg
== NULL
)
9186 addr_reg
= i
.index_reg
;
9190 if (addr_reg
->reg_num
== RegEip
9191 || addr_reg
->reg_num
== RegEiz
9192 || addr_reg
->reg_type
.bitfield
.dword
)
9193 addr_mode
= CODE_32BIT
;
9194 else if (flag_code
!= CODE_64BIT
9195 && addr_reg
->reg_type
.bitfield
.word
)
9196 addr_mode
= CODE_16BIT
;
9198 if (addr_mode
!= flag_code
)
9200 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9202 /* Change the size of any displacement too. At most one
9203 of Disp16 or Disp32 is set.
9204 FIXME. There doesn't seem to be any real need for
9205 separate Disp16 and Disp32 flags. The same goes for
9206 Imm16 and Imm32. Removing them would probably clean
9207 up the code quite a lot. */
9208 if (flag_code
!= CODE_64BIT
9209 && (i
.types
[this_operand
].bitfield
.disp16
9210 || i
.types
[this_operand
].bitfield
.disp32
))
9211 i
.types
[this_operand
]
9212 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9222 /* Make sure the memory operand we've been dealt is valid.
9223 Return 1 on success, 0 on a failure. */
9226 i386_index_check (const char *operand_string
)
9228 const char *kind
= "base/index";
9229 enum flag_code addr_mode
= i386_addressing_mode ();
9231 if (current_templates
->start
->opcode_modifier
.isstring
9232 && !current_templates
->start
->opcode_modifier
.immext
9233 && (current_templates
->end
[-1].opcode_modifier
.isstring
9236 /* Memory operands of string insns are special in that they only allow
9237 a single register (rDI, rSI, or rBX) as their memory address. */
9238 const reg_entry
*expected_reg
;
9239 static const char *di_si
[][2] =
9245 static const char *bx
[] = { "ebx", "bx", "rbx" };
9247 kind
= "string address";
9249 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9251 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9253 if (!type
.bitfield
.baseindex
9254 || ((!i
.mem_operands
!= !intel_syntax
)
9255 && current_templates
->end
[-1].operand_types
[1]
9256 .bitfield
.baseindex
))
9257 type
= current_templates
->end
[-1].operand_types
[1];
9258 expected_reg
= hash_find (reg_hash
,
9259 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9263 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9265 if (i
.base_reg
!= expected_reg
9267 || operand_type_check (i
.types
[this_operand
], disp
))
9269 /* The second memory operand must have the same size as
9273 && !((addr_mode
== CODE_64BIT
9274 && i
.base_reg
->reg_type
.bitfield
.qword
)
9275 || (addr_mode
== CODE_32BIT
9276 ? i
.base_reg
->reg_type
.bitfield
.dword
9277 : i
.base_reg
->reg_type
.bitfield
.word
)))
9280 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9282 intel_syntax
? '[' : '(',
9284 expected_reg
->reg_name
,
9285 intel_syntax
? ']' : ')');
9292 as_bad (_("`%s' is not a valid %s expression"),
9293 operand_string
, kind
);
9298 if (addr_mode
!= CODE_16BIT
)
9300 /* 32-bit/64-bit checks. */
9302 && (addr_mode
== CODE_64BIT
9303 ? !i
.base_reg
->reg_type
.bitfield
.qword
9304 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9306 || (i
.base_reg
->reg_num
9307 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9309 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9310 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9311 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9312 && ((addr_mode
== CODE_64BIT
9313 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9314 || i
.index_reg
->reg_num
== RegRiz
)
9315 : !(i
.index_reg
->reg_type
.bitfield
.dword
9316 || i
.index_reg
->reg_num
== RegEiz
))
9317 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9320 /* bndmk, bndldx, and bndstx have special restrictions. */
9321 if (current_templates
->start
->base_opcode
== 0xf30f1b
9322 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9324 /* They cannot use RIP-relative addressing. */
9325 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9327 as_bad (_("`%s' cannot be used here"), operand_string
);
9331 /* bndldx and bndstx ignore their scale factor. */
9332 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9333 && i
.log2_scale_factor
)
9334 as_warn (_("register scaling is being ignored here"));
9339 /* 16-bit checks. */
9341 && (!i
.base_reg
->reg_type
.bitfield
.word
9342 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9344 && (!i
.index_reg
->reg_type
.bitfield
.word
9345 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9347 && i
.base_reg
->reg_num
< 6
9348 && i
.index_reg
->reg_num
>= 6
9349 && i
.log2_scale_factor
== 0))))
9356 /* Handle vector immediates. */
9359 RC_SAE_immediate (const char *imm_start
)
9361 unsigned int match_found
, j
;
9362 const char *pstr
= imm_start
;
9370 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9372 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9376 rc_op
.type
= RC_NamesTable
[j
].type
;
9377 rc_op
.operand
= this_operand
;
9378 i
.rounding
= &rc_op
;
9382 as_bad (_("duplicated `%s'"), imm_start
);
9385 pstr
+= RC_NamesTable
[j
].len
;
9395 as_bad (_("Missing '}': '%s'"), imm_start
);
9398 /* RC/SAE immediate string should contain nothing more. */;
9401 as_bad (_("Junk after '}': '%s'"), imm_start
);
9405 exp
= &im_expressions
[i
.imm_operands
++];
9406 i
.op
[this_operand
].imms
= exp
;
9408 exp
->X_op
= O_constant
;
9409 exp
->X_add_number
= 0;
9410 exp
->X_add_symbol
= (symbolS
*) 0;
9411 exp
->X_op_symbol
= (symbolS
*) 0;
9413 i
.types
[this_operand
].bitfield
.imm8
= 1;
9417 /* Only string instructions can have a second memory operand, so
9418 reduce current_templates to just those if it contains any. */
9420 maybe_adjust_templates (void)
9422 const insn_template
*t
;
9424 gas_assert (i
.mem_operands
== 1);
9426 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9427 if (t
->opcode_modifier
.isstring
)
9430 if (t
< current_templates
->end
)
9432 static templates aux_templates
;
9433 bfd_boolean recheck
;
9435 aux_templates
.start
= t
;
9436 for (; t
< current_templates
->end
; ++t
)
9437 if (!t
->opcode_modifier
.isstring
)
9439 aux_templates
.end
= t
;
9441 /* Determine whether to re-check the first memory operand. */
9442 recheck
= (aux_templates
.start
!= current_templates
->start
9443 || t
!= current_templates
->end
);
9445 current_templates
= &aux_templates
;
9450 if (i
.memop1_string
!= NULL
9451 && i386_index_check (i
.memop1_string
) == 0)
9460 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9464 i386_att_operand (char *operand_string
)
9468 char *op_string
= operand_string
;
9470 if (is_space_char (*op_string
))
9473 /* We check for an absolute prefix (differentiating,
9474 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9475 if (*op_string
== ABSOLUTE_PREFIX
)
9478 if (is_space_char (*op_string
))
9480 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9483 /* Check if operand is a register. */
9484 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9486 i386_operand_type temp
;
9488 /* Check for a segment override by searching for ':' after a
9489 segment register. */
9491 if (is_space_char (*op_string
))
9493 if (*op_string
== ':'
9494 && (r
->reg_type
.bitfield
.sreg2
9495 || r
->reg_type
.bitfield
.sreg3
))
9500 i
.seg
[i
.mem_operands
] = &es
;
9503 i
.seg
[i
.mem_operands
] = &cs
;
9506 i
.seg
[i
.mem_operands
] = &ss
;
9509 i
.seg
[i
.mem_operands
] = &ds
;
9512 i
.seg
[i
.mem_operands
] = &fs
;
9515 i
.seg
[i
.mem_operands
] = &gs
;
9519 /* Skip the ':' and whitespace. */
9521 if (is_space_char (*op_string
))
9524 if (!is_digit_char (*op_string
)
9525 && !is_identifier_char (*op_string
)
9526 && *op_string
!= '('
9527 && *op_string
!= ABSOLUTE_PREFIX
)
9529 as_bad (_("bad memory operand `%s'"), op_string
);
9532 /* Handle case of %es:*foo. */
9533 if (*op_string
== ABSOLUTE_PREFIX
)
9536 if (is_space_char (*op_string
))
9538 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9540 goto do_memory_reference
;
9543 /* Handle vector operations. */
9544 if (*op_string
== '{')
9546 op_string
= check_VecOperations (op_string
, NULL
);
9547 if (op_string
== NULL
)
9553 as_bad (_("junk `%s' after register"), op_string
);
9557 temp
.bitfield
.baseindex
= 0;
9558 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9560 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9561 i
.op
[this_operand
].regs
= r
;
9564 else if (*op_string
== REGISTER_PREFIX
)
9566 as_bad (_("bad register name `%s'"), op_string
);
9569 else if (*op_string
== IMMEDIATE_PREFIX
)
9572 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9574 as_bad (_("immediate operand illegal with absolute jump"));
9577 if (!i386_immediate (op_string
))
9580 else if (RC_SAE_immediate (operand_string
))
9582 /* If it is a RC or SAE immediate, do nothing. */
9585 else if (is_digit_char (*op_string
)
9586 || is_identifier_char (*op_string
)
9587 || *op_string
== '"'
9588 || *op_string
== '(')
9590 /* This is a memory reference of some sort. */
9593 /* Start and end of displacement string expression (if found). */
9594 char *displacement_string_start
;
9595 char *displacement_string_end
;
9598 do_memory_reference
:
9599 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9601 if ((i
.mem_operands
== 1
9602 && !current_templates
->start
->opcode_modifier
.isstring
)
9603 || i
.mem_operands
== 2)
9605 as_bad (_("too many memory references for `%s'"),
9606 current_templates
->start
->name
);
9610 /* Check for base index form. We detect the base index form by
9611 looking for an ')' at the end of the operand, searching
9612 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9614 base_string
= op_string
+ strlen (op_string
);
9616 /* Handle vector operations. */
9617 vop_start
= strchr (op_string
, '{');
9618 if (vop_start
&& vop_start
< base_string
)
9620 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9622 base_string
= vop_start
;
9626 if (is_space_char (*base_string
))
9629 /* If we only have a displacement, set-up for it to be parsed later. */
9630 displacement_string_start
= op_string
;
9631 displacement_string_end
= base_string
+ 1;
9633 if (*base_string
== ')')
9636 unsigned int parens_balanced
= 1;
9637 /* We've already checked that the number of left & right ()'s are
9638 equal, so this loop will not be infinite. */
9642 if (*base_string
== ')')
9644 if (*base_string
== '(')
9647 while (parens_balanced
);
9649 temp_string
= base_string
;
9651 /* Skip past '(' and whitespace. */
9653 if (is_space_char (*base_string
))
9656 if (*base_string
== ','
9657 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9660 displacement_string_end
= temp_string
;
9662 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9666 base_string
= end_op
;
9667 if (is_space_char (*base_string
))
9671 /* There may be an index reg or scale factor here. */
9672 if (*base_string
== ',')
9675 if (is_space_char (*base_string
))
9678 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9681 base_string
= end_op
;
9682 if (is_space_char (*base_string
))
9684 if (*base_string
== ',')
9687 if (is_space_char (*base_string
))
9690 else if (*base_string
!= ')')
9692 as_bad (_("expecting `,' or `)' "
9693 "after index register in `%s'"),
9698 else if (*base_string
== REGISTER_PREFIX
)
9700 end_op
= strchr (base_string
, ',');
9703 as_bad (_("bad register name `%s'"), base_string
);
9707 /* Check for scale factor. */
9708 if (*base_string
!= ')')
9710 char *end_scale
= i386_scale (base_string
);
9715 base_string
= end_scale
;
9716 if (is_space_char (*base_string
))
9718 if (*base_string
!= ')')
9720 as_bad (_("expecting `)' "
9721 "after scale factor in `%s'"),
9726 else if (!i
.index_reg
)
9728 as_bad (_("expecting index register or scale factor "
9729 "after `,'; got '%c'"),
9734 else if (*base_string
!= ')')
9736 as_bad (_("expecting `,' or `)' "
9737 "after base register in `%s'"),
9742 else if (*base_string
== REGISTER_PREFIX
)
9744 end_op
= strchr (base_string
, ',');
9747 as_bad (_("bad register name `%s'"), base_string
);
9752 /* If there's an expression beginning the operand, parse it,
9753 assuming displacement_string_start and
9754 displacement_string_end are meaningful. */
9755 if (displacement_string_start
!= displacement_string_end
)
9757 if (!i386_displacement (displacement_string_start
,
9758 displacement_string_end
))
9762 /* Special case for (%dx) while doing input/output op. */
9764 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9766 && i
.log2_scale_factor
== 0
9767 && i
.seg
[i
.mem_operands
] == 0
9768 && !operand_type_check (i
.types
[this_operand
], disp
))
9770 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9774 if (i386_index_check (operand_string
) == 0)
9776 i
.types
[this_operand
].bitfield
.mem
= 1;
9777 if (i
.mem_operands
== 0)
9778 i
.memop1_string
= xstrdup (operand_string
);
9783 /* It's not a memory operand; argh! */
9784 as_bad (_("invalid char %s beginning operand %d `%s'"),
9785 output_invalid (*op_string
),
9790 return 1; /* Normal return. */
9793 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9794 that an rs_machine_dependent frag may reach. */
9797 i386_frag_max_var (fragS
*frag
)
9799 /* The only relaxable frags are for jumps.
9800 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9801 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9802 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9805 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9807 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9809 /* STT_GNU_IFUNC symbol must go through PLT. */
9810 if ((symbol_get_bfdsym (fr_symbol
)->flags
9811 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9814 if (!S_IS_EXTERNAL (fr_symbol
))
9815 /* Symbol may be weak or local. */
9816 return !S_IS_WEAK (fr_symbol
);
9818 /* Global symbols with non-default visibility can't be preempted. */
9819 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9822 if (fr_var
!= NO_RELOC
)
9823 switch ((enum bfd_reloc_code_real
) fr_var
)
9825 case BFD_RELOC_386_PLT32
:
9826 case BFD_RELOC_X86_64_PLT32
:
9827 /* Symbol with PLT relocation may be preempted. */
9833 /* Global symbols with default visibility in a shared library may be
9834 preempted by another definition. */
9839 /* md_estimate_size_before_relax()
9841 Called just before relax() for rs_machine_dependent frags. The x86
9842 assembler uses these frags to handle variable size jump
9845 Any symbol that is now undefined will not become defined.
9846 Return the correct fr_subtype in the frag.
9847 Return the initial "guess for variable size of frag" to caller.
9848 The guess is actually the growth beyond the fixed part. Whatever
9849 we do to grow the fixed or variable part contributes to our
9853 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9855 /* We've already got fragP->fr_subtype right; all we have to do is
9856 check for un-relaxable symbols. On an ELF system, we can't relax
9857 an externally visible symbol, because it may be overridden by a
9859 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9862 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9865 #if defined (OBJ_COFF) && defined (TE_PE)
9866 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9867 && S_IS_WEAK (fragP
->fr_symbol
))
9871 /* Symbol is undefined in this segment, or we need to keep a
9872 reloc so that weak symbols can be overridden. */
9873 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9874 enum bfd_reloc_code_real reloc_type
;
9875 unsigned char *opcode
;
9878 if (fragP
->fr_var
!= NO_RELOC
)
9879 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9881 reloc_type
= BFD_RELOC_16_PCREL
;
9882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9883 else if (need_plt32_p (fragP
->fr_symbol
))
9884 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9887 reloc_type
= BFD_RELOC_32_PCREL
;
9889 old_fr_fix
= fragP
->fr_fix
;
9890 opcode
= (unsigned char *) fragP
->fr_opcode
;
9892 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9895 /* Make jmp (0xeb) a (d)word displacement jump. */
9897 fragP
->fr_fix
+= size
;
9898 fix_new (fragP
, old_fr_fix
, size
,
9900 fragP
->fr_offset
, 1,
9906 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9908 /* Negate the condition, and branch past an
9909 unconditional jump. */
9912 /* Insert an unconditional jump. */
9914 /* We added two extra opcode bytes, and have a two byte
9916 fragP
->fr_fix
+= 2 + 2;
9917 fix_new (fragP
, old_fr_fix
+ 2, 2,
9919 fragP
->fr_offset
, 1,
9926 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9931 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9933 fragP
->fr_offset
, 1,
9935 fixP
->fx_signed
= 1;
9939 /* This changes the byte-displacement jump 0x7N
9940 to the (d)word-displacement jump 0x0f,0x8N. */
9941 opcode
[1] = opcode
[0] + 0x10;
9942 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9943 /* We've added an opcode byte. */
9944 fragP
->fr_fix
+= 1 + size
;
9945 fix_new (fragP
, old_fr_fix
+ 1, size
,
9947 fragP
->fr_offset
, 1,
9952 BAD_CASE (fragP
->fr_subtype
);
9956 return fragP
->fr_fix
- old_fr_fix
;
9959 /* Guess size depending on current relax state. Initially the relax
9960 state will correspond to a short jump and we return 1, because
9961 the variable part of the frag (the branch offset) is one byte
9962 long. However, we can relax a section more than once and in that
9963 case we must either set fr_subtype back to the unrelaxed state,
9964 or return the value for the appropriate branch. */
9965 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9968 /* Called after relax() is finished.
9970 In: Address of frag.
9971 fr_type == rs_machine_dependent.
9972 fr_subtype is what the address relaxed to.
9974 Out: Any fixSs and constants are set up.
9975 Caller will turn frag into a ".space 0". */
9978 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9981 unsigned char *opcode
;
9982 unsigned char *where_to_put_displacement
= NULL
;
9983 offsetT target_address
;
9984 offsetT opcode_address
;
9985 unsigned int extension
= 0;
9986 offsetT displacement_from_opcode_start
;
9988 opcode
= (unsigned char *) fragP
->fr_opcode
;
9990 /* Address we want to reach in file space. */
9991 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9993 /* Address opcode resides at in file space. */
9994 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9996 /* Displacement from opcode start to fill into instruction. */
9997 displacement_from_opcode_start
= target_address
- opcode_address
;
9999 if ((fragP
->fr_subtype
& BIG
) == 0)
10001 /* Don't have to change opcode. */
10002 extension
= 1; /* 1 opcode + 1 displacement */
10003 where_to_put_displacement
= &opcode
[1];
10007 if (no_cond_jump_promotion
10008 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10009 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10010 _("long jump required"));
10012 switch (fragP
->fr_subtype
)
10014 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10015 extension
= 4; /* 1 opcode + 4 displacement */
10017 where_to_put_displacement
= &opcode
[1];
10020 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10021 extension
= 2; /* 1 opcode + 2 displacement */
10023 where_to_put_displacement
= &opcode
[1];
10026 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10027 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10028 extension
= 5; /* 2 opcode + 4 displacement */
10029 opcode
[1] = opcode
[0] + 0x10;
10030 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10031 where_to_put_displacement
= &opcode
[2];
10034 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10035 extension
= 3; /* 2 opcode + 2 displacement */
10036 opcode
[1] = opcode
[0] + 0x10;
10037 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10038 where_to_put_displacement
= &opcode
[2];
10041 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10046 where_to_put_displacement
= &opcode
[3];
10050 BAD_CASE (fragP
->fr_subtype
);
10055 /* If size if less then four we are sure that the operand fits,
10056 but if it's 4, then it could be that the displacement is larger
10058 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10060 && ((addressT
) (displacement_from_opcode_start
- extension
10061 + ((addressT
) 1 << 31))
10062 > (((addressT
) 2 << 31) - 1)))
10064 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10065 _("jump target out of range"));
10066 /* Make us emit 0. */
10067 displacement_from_opcode_start
= extension
;
10069 /* Now put displacement after opcode. */
10070 md_number_to_chars ((char *) where_to_put_displacement
,
10071 (valueT
) (displacement_from_opcode_start
- extension
),
10072 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10073 fragP
->fr_fix
+= extension
;
10076 /* Apply a fixup (fixP) to segment data, once it has been determined
10077 by our caller that we have all the info we need to fix it up.
10079 Parameter valP is the pointer to the value of the bits.
10081 On the 386, immediates, displacements, and data pointers are all in
10082 the same (little-endian) format, so we don't need to care about which
10083 we are handling. */
10086 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10088 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10089 valueT value
= *valP
;
10091 #if !defined (TE_Mach)
10092 if (fixP
->fx_pcrel
)
10094 switch (fixP
->fx_r_type
)
10100 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10103 case BFD_RELOC_X86_64_32S
:
10104 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10107 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10110 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10115 if (fixP
->fx_addsy
!= NULL
10116 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10117 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10118 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10119 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10120 && !use_rela_relocations
)
10122 /* This is a hack. There should be a better way to handle this.
10123 This covers for the fact that bfd_install_relocation will
10124 subtract the current location (for partial_inplace, PC relative
10125 relocations); see more below. */
10129 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10132 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10134 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10137 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10139 if ((sym_seg
== seg
10140 || (symbol_section_p (fixP
->fx_addsy
)
10141 && sym_seg
!= absolute_section
))
10142 && !generic_force_reloc (fixP
))
10144 /* Yes, we add the values in twice. This is because
10145 bfd_install_relocation subtracts them out again. I think
10146 bfd_install_relocation is broken, but I don't dare change
10148 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10152 #if defined (OBJ_COFF) && defined (TE_PE)
10153 /* For some reason, the PE format does not store a
10154 section address offset for a PC relative symbol. */
10155 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10156 || S_IS_WEAK (fixP
->fx_addsy
))
10157 value
+= md_pcrel_from (fixP
);
10160 #if defined (OBJ_COFF) && defined (TE_PE)
10161 if (fixP
->fx_addsy
!= NULL
10162 && S_IS_WEAK (fixP
->fx_addsy
)
10163 /* PR 16858: Do not modify weak function references. */
10164 && ! fixP
->fx_pcrel
)
10166 #if !defined (TE_PEP)
10167 /* For x86 PE weak function symbols are neither PC-relative
10168 nor do they set S_IS_FUNCTION. So the only reliable way
10169 to detect them is to check the flags of their containing
10171 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10172 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10176 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10180 /* Fix a few things - the dynamic linker expects certain values here,
10181 and we must not disappoint it. */
10182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10183 if (IS_ELF
&& fixP
->fx_addsy
)
10184 switch (fixP
->fx_r_type
)
10186 case BFD_RELOC_386_PLT32
:
10187 case BFD_RELOC_X86_64_PLT32
:
10188 /* Make the jump instruction point to the address of the operand. At
10189 runtime we merely add the offset to the actual PLT entry. */
10193 case BFD_RELOC_386_TLS_GD
:
10194 case BFD_RELOC_386_TLS_LDM
:
10195 case BFD_RELOC_386_TLS_IE_32
:
10196 case BFD_RELOC_386_TLS_IE
:
10197 case BFD_RELOC_386_TLS_GOTIE
:
10198 case BFD_RELOC_386_TLS_GOTDESC
:
10199 case BFD_RELOC_X86_64_TLSGD
:
10200 case BFD_RELOC_X86_64_TLSLD
:
10201 case BFD_RELOC_X86_64_GOTTPOFF
:
10202 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10203 value
= 0; /* Fully resolved at runtime. No addend. */
10205 case BFD_RELOC_386_TLS_LE
:
10206 case BFD_RELOC_386_TLS_LDO_32
:
10207 case BFD_RELOC_386_TLS_LE_32
:
10208 case BFD_RELOC_X86_64_DTPOFF32
:
10209 case BFD_RELOC_X86_64_DTPOFF64
:
10210 case BFD_RELOC_X86_64_TPOFF32
:
10211 case BFD_RELOC_X86_64_TPOFF64
:
10212 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10215 case BFD_RELOC_386_TLS_DESC_CALL
:
10216 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10217 value
= 0; /* Fully resolved at runtime. No addend. */
10218 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10222 case BFD_RELOC_VTABLE_INHERIT
:
10223 case BFD_RELOC_VTABLE_ENTRY
:
10230 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10232 #endif /* !defined (TE_Mach) */
10234 /* Are we finished with this relocation now? */
10235 if (fixP
->fx_addsy
== NULL
)
10237 #if defined (OBJ_COFF) && defined (TE_PE)
10238 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10241 /* Remember value for tc_gen_reloc. */
10242 fixP
->fx_addnumber
= value
;
10243 /* Clear out the frag for now. */
10247 else if (use_rela_relocations
)
10249 fixP
->fx_no_overflow
= 1;
10250 /* Remember value for tc_gen_reloc. */
10251 fixP
->fx_addnumber
= value
;
10255 md_number_to_chars (p
, value
, fixP
->fx_size
);
10259 md_atof (int type
, char *litP
, int *sizeP
)
10261 /* This outputs the LITTLENUMs in REVERSE order;
10262 in accord with the bigendian 386. */
10263 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10266 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10269 output_invalid (int c
)
10272 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10275 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10276 "(0x%x)", (unsigned char) c
);
10277 return output_invalid_buf
;
10280 /* REG_STRING starts *before* REGISTER_PREFIX. */
10282 static const reg_entry
*
10283 parse_real_register (char *reg_string
, char **end_op
)
10285 char *s
= reg_string
;
10287 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10288 const reg_entry
*r
;
10290 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10291 if (*s
== REGISTER_PREFIX
)
10294 if (is_space_char (*s
))
10297 p
= reg_name_given
;
10298 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10300 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10301 return (const reg_entry
*) NULL
;
10305 /* For naked regs, make sure that we are not dealing with an identifier.
10306 This prevents confusing an identifier like `eax_var' with register
10308 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10309 return (const reg_entry
*) NULL
;
10313 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10315 /* Handle floating point regs, allowing spaces in the (i) part. */
10316 if (r
== i386_regtab
/* %st is first entry of table */)
10318 if (!cpu_arch_flags
.bitfield
.cpu8087
10319 && !cpu_arch_flags
.bitfield
.cpu287
10320 && !cpu_arch_flags
.bitfield
.cpu387
)
10321 return (const reg_entry
*) NULL
;
10323 if (is_space_char (*s
))
10328 if (is_space_char (*s
))
10330 if (*s
>= '0' && *s
<= '7')
10332 int fpr
= *s
- '0';
10334 if (is_space_char (*s
))
10339 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10344 /* We have "%st(" then garbage. */
10345 return (const reg_entry
*) NULL
;
10349 if (r
== NULL
|| allow_pseudo_reg
)
10352 if (operand_type_all_zero (&r
->reg_type
))
10353 return (const reg_entry
*) NULL
;
10355 if ((r
->reg_type
.bitfield
.dword
10356 || r
->reg_type
.bitfield
.sreg3
10357 || r
->reg_type
.bitfield
.control
10358 || r
->reg_type
.bitfield
.debug
10359 || r
->reg_type
.bitfield
.test
)
10360 && !cpu_arch_flags
.bitfield
.cpui386
)
10361 return (const reg_entry
*) NULL
;
10363 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10364 return (const reg_entry
*) NULL
;
10366 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10368 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10369 return (const reg_entry
*) NULL
;
10371 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10373 if (r
->reg_type
.bitfield
.ymmword
)
10374 return (const reg_entry
*) NULL
;
10376 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10377 return (const reg_entry
*) NULL
;
10381 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10382 return (const reg_entry
*) NULL
;
10384 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10385 if (!allow_index_reg
10386 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10387 return (const reg_entry
*) NULL
;
10389 /* Upper 16 vector registers are only available with VREX in 64bit
10390 mode, and require EVEX encoding. */
10391 if (r
->reg_flags
& RegVRex
)
10393 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10394 || flag_code
!= CODE_64BIT
)
10395 return (const reg_entry
*) NULL
;
10397 i
.vec_encoding
= vex_encoding_evex
;
10400 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10401 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10402 && flag_code
!= CODE_64BIT
)
10403 return (const reg_entry
*) NULL
;
10405 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10406 return (const reg_entry
*) NULL
;
10411 /* REG_STRING starts *before* REGISTER_PREFIX. */
10413 static const reg_entry
*
10414 parse_register (char *reg_string
, char **end_op
)
10416 const reg_entry
*r
;
10418 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10419 r
= parse_real_register (reg_string
, end_op
);
10424 char *save
= input_line_pointer
;
10428 input_line_pointer
= reg_string
;
10429 c
= get_symbol_name (®_string
);
10430 symbolP
= symbol_find (reg_string
);
10431 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10433 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10435 know (e
->X_op
== O_register
);
10436 know (e
->X_add_number
>= 0
10437 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10438 r
= i386_regtab
+ e
->X_add_number
;
10439 if ((r
->reg_flags
& RegVRex
))
10440 i
.vec_encoding
= vex_encoding_evex
;
10441 *end_op
= input_line_pointer
;
10443 *input_line_pointer
= c
;
10444 input_line_pointer
= save
;
10450 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10452 const reg_entry
*r
;
10453 char *end
= input_line_pointer
;
10456 r
= parse_register (name
, &input_line_pointer
);
10457 if (r
&& end
<= input_line_pointer
)
10459 *nextcharP
= *input_line_pointer
;
10460 *input_line_pointer
= 0;
10461 e
->X_op
= O_register
;
10462 e
->X_add_number
= r
- i386_regtab
;
10465 input_line_pointer
= end
;
10467 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10471 md_operand (expressionS
*e
)
10474 const reg_entry
*r
;
10476 switch (*input_line_pointer
)
10478 case REGISTER_PREFIX
:
10479 r
= parse_real_register (input_line_pointer
, &end
);
10482 e
->X_op
= O_register
;
10483 e
->X_add_number
= r
- i386_regtab
;
10484 input_line_pointer
= end
;
10489 gas_assert (intel_syntax
);
10490 end
= input_line_pointer
++;
10492 if (*input_line_pointer
== ']')
10494 ++input_line_pointer
;
10495 e
->X_op_symbol
= make_expr_symbol (e
);
10496 e
->X_add_symbol
= NULL
;
10497 e
->X_add_number
= 0;
10502 e
->X_op
= O_absent
;
10503 input_line_pointer
= end
;
10510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10511 const char *md_shortopts
= "kVQ:sqnO::";
10513 const char *md_shortopts
= "qnO::";
10516 #define OPTION_32 (OPTION_MD_BASE + 0)
10517 #define OPTION_64 (OPTION_MD_BASE + 1)
10518 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10519 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10520 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10521 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10522 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10523 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10524 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10525 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10526 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10527 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10528 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10529 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10530 #define OPTION_X32 (OPTION_MD_BASE + 14)
10531 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10532 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10533 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10534 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10535 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10536 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10537 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10538 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10539 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10540 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10542 struct option md_longopts
[] =
10544 {"32", no_argument
, NULL
, OPTION_32
},
10545 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10546 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10547 {"64", no_argument
, NULL
, OPTION_64
},
10549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10550 {"x32", no_argument
, NULL
, OPTION_X32
},
10551 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10553 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10554 {"march", required_argument
, NULL
, OPTION_MARCH
},
10555 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10556 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10557 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10558 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10559 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10560 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10561 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10562 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10563 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10564 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10565 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10566 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10567 # if defined (TE_PE) || defined (TE_PEP)
10568 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10570 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10571 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10572 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10573 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10574 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10575 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10576 {NULL
, no_argument
, NULL
, 0}
10578 size_t md_longopts_size
= sizeof (md_longopts
);
10581 md_parse_option (int c
, const char *arg
)
10584 char *arch
, *next
, *saved
;
10589 optimize_align_code
= 0;
10593 quiet_warnings
= 1;
10596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10597 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10598 should be emitted or not. FIXME: Not implemented. */
10602 /* -V: SVR4 argument to print version ID. */
10604 print_version_id ();
10607 /* -k: Ignore for FreeBSD compatibility. */
10612 /* -s: On i386 Solaris, this tells the native assembler to use
10613 .stab instead of .stab.excl. We always use .stab anyhow. */
10616 case OPTION_MSHARED
:
10620 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10621 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10624 const char **list
, **l
;
10626 list
= bfd_target_list ();
10627 for (l
= list
; *l
!= NULL
; l
++)
10628 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10629 || strcmp (*l
, "coff-x86-64") == 0
10630 || strcmp (*l
, "pe-x86-64") == 0
10631 || strcmp (*l
, "pei-x86-64") == 0
10632 || strcmp (*l
, "mach-o-x86-64") == 0)
10634 default_arch
= "x86_64";
10638 as_fatal (_("no compiled in support for x86_64"));
10644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10648 const char **list
, **l
;
10650 list
= bfd_target_list ();
10651 for (l
= list
; *l
!= NULL
; l
++)
10652 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10654 default_arch
= "x86_64:32";
10658 as_fatal (_("no compiled in support for 32bit x86_64"));
10662 as_fatal (_("32bit x86_64 is only supported for ELF"));
10667 default_arch
= "i386";
10670 case OPTION_DIVIDE
:
10671 #ifdef SVR4_COMMENT_CHARS
10676 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10678 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10682 i386_comment_chars
= n
;
10688 saved
= xstrdup (arg
);
10690 /* Allow -march=+nosse. */
10696 as_fatal (_("invalid -march= option: `%s'"), arg
);
10697 next
= strchr (arch
, '+');
10700 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10702 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10705 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10708 cpu_arch_name
= cpu_arch
[j
].name
;
10709 cpu_sub_arch_name
= NULL
;
10710 cpu_arch_flags
= cpu_arch
[j
].flags
;
10711 cpu_arch_isa
= cpu_arch
[j
].type
;
10712 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10713 if (!cpu_arch_tune_set
)
10715 cpu_arch_tune
= cpu_arch_isa
;
10716 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10720 else if (*cpu_arch
[j
].name
== '.'
10721 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10723 /* ISA extension. */
10724 i386_cpu_flags flags
;
10726 flags
= cpu_flags_or (cpu_arch_flags
,
10727 cpu_arch
[j
].flags
);
10729 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10731 if (cpu_sub_arch_name
)
10733 char *name
= cpu_sub_arch_name
;
10734 cpu_sub_arch_name
= concat (name
,
10736 (const char *) NULL
);
10740 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10741 cpu_arch_flags
= flags
;
10742 cpu_arch_isa_flags
= flags
;
10746 = cpu_flags_or (cpu_arch_isa_flags
,
10747 cpu_arch
[j
].flags
);
10752 if (j
>= ARRAY_SIZE (cpu_arch
))
10754 /* Disable an ISA extension. */
10755 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10756 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10758 i386_cpu_flags flags
;
10760 flags
= cpu_flags_and_not (cpu_arch_flags
,
10761 cpu_noarch
[j
].flags
);
10762 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10764 if (cpu_sub_arch_name
)
10766 char *name
= cpu_sub_arch_name
;
10767 cpu_sub_arch_name
= concat (arch
,
10768 (const char *) NULL
);
10772 cpu_sub_arch_name
= xstrdup (arch
);
10773 cpu_arch_flags
= flags
;
10774 cpu_arch_isa_flags
= flags
;
10779 if (j
>= ARRAY_SIZE (cpu_noarch
))
10780 j
= ARRAY_SIZE (cpu_arch
);
10783 if (j
>= ARRAY_SIZE (cpu_arch
))
10784 as_fatal (_("invalid -march= option: `%s'"), arg
);
10788 while (next
!= NULL
);
10794 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10795 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10797 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10799 cpu_arch_tune_set
= 1;
10800 cpu_arch_tune
= cpu_arch
[j
].type
;
10801 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10805 if (j
>= ARRAY_SIZE (cpu_arch
))
10806 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10809 case OPTION_MMNEMONIC
:
10810 if (strcasecmp (arg
, "att") == 0)
10811 intel_mnemonic
= 0;
10812 else if (strcasecmp (arg
, "intel") == 0)
10813 intel_mnemonic
= 1;
10815 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10818 case OPTION_MSYNTAX
:
10819 if (strcasecmp (arg
, "att") == 0)
10821 else if (strcasecmp (arg
, "intel") == 0)
10824 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10827 case OPTION_MINDEX_REG
:
10828 allow_index_reg
= 1;
10831 case OPTION_MNAKED_REG
:
10832 allow_naked_reg
= 1;
10835 case OPTION_MSSE2AVX
:
10839 case OPTION_MSSE_CHECK
:
10840 if (strcasecmp (arg
, "error") == 0)
10841 sse_check
= check_error
;
10842 else if (strcasecmp (arg
, "warning") == 0)
10843 sse_check
= check_warning
;
10844 else if (strcasecmp (arg
, "none") == 0)
10845 sse_check
= check_none
;
10847 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10850 case OPTION_MOPERAND_CHECK
:
10851 if (strcasecmp (arg
, "error") == 0)
10852 operand_check
= check_error
;
10853 else if (strcasecmp (arg
, "warning") == 0)
10854 operand_check
= check_warning
;
10855 else if (strcasecmp (arg
, "none") == 0)
10856 operand_check
= check_none
;
10858 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10861 case OPTION_MAVXSCALAR
:
10862 if (strcasecmp (arg
, "128") == 0)
10863 avxscalar
= vex128
;
10864 else if (strcasecmp (arg
, "256") == 0)
10865 avxscalar
= vex256
;
10867 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10870 case OPTION_MADD_BND_PREFIX
:
10871 add_bnd_prefix
= 1;
10874 case OPTION_MEVEXLIG
:
10875 if (strcmp (arg
, "128") == 0)
10876 evexlig
= evexl128
;
10877 else if (strcmp (arg
, "256") == 0)
10878 evexlig
= evexl256
;
10879 else if (strcmp (arg
, "512") == 0)
10880 evexlig
= evexl512
;
10882 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10885 case OPTION_MEVEXRCIG
:
10886 if (strcmp (arg
, "rne") == 0)
10888 else if (strcmp (arg
, "rd") == 0)
10890 else if (strcmp (arg
, "ru") == 0)
10892 else if (strcmp (arg
, "rz") == 0)
10895 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10898 case OPTION_MEVEXWIG
:
10899 if (strcmp (arg
, "0") == 0)
10901 else if (strcmp (arg
, "1") == 0)
10904 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10907 # if defined (TE_PE) || defined (TE_PEP)
10908 case OPTION_MBIG_OBJ
:
10913 case OPTION_MOMIT_LOCK_PREFIX
:
10914 if (strcasecmp (arg
, "yes") == 0)
10915 omit_lock_prefix
= 1;
10916 else if (strcasecmp (arg
, "no") == 0)
10917 omit_lock_prefix
= 0;
10919 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10922 case OPTION_MFENCE_AS_LOCK_ADD
:
10923 if (strcasecmp (arg
, "yes") == 0)
10925 else if (strcasecmp (arg
, "no") == 0)
10928 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10931 case OPTION_MRELAX_RELOCATIONS
:
10932 if (strcasecmp (arg
, "yes") == 0)
10933 generate_relax_relocations
= 1;
10934 else if (strcasecmp (arg
, "no") == 0)
10935 generate_relax_relocations
= 0;
10937 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10940 case OPTION_MAMD64
:
10944 case OPTION_MINTEL64
:
10952 /* Turn off -Os. */
10953 optimize_for_space
= 0;
10955 else if (*arg
== 's')
10957 optimize_for_space
= 1;
10958 /* Turn on all encoding optimizations. */
10963 optimize
= atoi (arg
);
10964 /* Turn off -Os. */
10965 optimize_for_space
= 0;
10975 #define MESSAGE_TEMPLATE \
10979 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10980 int *left_p
, const char *name
, int len
)
10982 int size
= sizeof (MESSAGE_TEMPLATE
);
10983 int left
= *left_p
;
10985 /* Reserve 2 spaces for ", " or ",\0" */
10988 /* Check if there is any room. */
10996 p
= mempcpy (p
, name
, len
);
11000 /* Output the current message now and start a new one. */
11003 fprintf (stream
, "%s\n", message
);
11005 left
= size
- (start
- message
) - len
- 2;
11007 gas_assert (left
>= 0);
11009 p
= mempcpy (p
, name
, len
);
11017 show_arch (FILE *stream
, int ext
, int check
)
11019 static char message
[] = MESSAGE_TEMPLATE
;
11020 char *start
= message
+ 27;
11022 int size
= sizeof (MESSAGE_TEMPLATE
);
11029 left
= size
- (start
- message
);
11030 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11032 /* Should it be skipped? */
11033 if (cpu_arch
[j
].skip
)
11036 name
= cpu_arch
[j
].name
;
11037 len
= cpu_arch
[j
].len
;
11040 /* It is an extension. Skip if we aren't asked to show it. */
11051 /* It is an processor. Skip if we show only extension. */
11054 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11056 /* It is an impossible processor - skip. */
11060 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11063 /* Display disabled extensions. */
11065 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11067 name
= cpu_noarch
[j
].name
;
11068 len
= cpu_noarch
[j
].len
;
11069 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11074 fprintf (stream
, "%s\n", message
);
11078 md_show_usage (FILE *stream
)
11080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11081 fprintf (stream
, _("\
11083 -V print assembler version number\n\
11086 fprintf (stream
, _("\
11087 -n Do not optimize code alignment\n\
11088 -q quieten some warnings\n"));
11089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11090 fprintf (stream
, _("\
11093 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11094 || defined (TE_PE) || defined (TE_PEP))
11095 fprintf (stream
, _("\
11096 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11098 #ifdef SVR4_COMMENT_CHARS
11099 fprintf (stream
, _("\
11100 --divide do not treat `/' as a comment character\n"));
11102 fprintf (stream
, _("\
11103 --divide ignored\n"));
11105 fprintf (stream
, _("\
11106 -march=CPU[,+EXTENSION...]\n\
11107 generate code for CPU and EXTENSION, CPU is one of:\n"));
11108 show_arch (stream
, 0, 1);
11109 fprintf (stream
, _("\
11110 EXTENSION is combination of:\n"));
11111 show_arch (stream
, 1, 0);
11112 fprintf (stream
, _("\
11113 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11114 show_arch (stream
, 0, 0);
11115 fprintf (stream
, _("\
11116 -msse2avx encode SSE instructions with VEX prefix\n"));
11117 fprintf (stream
, _("\
11118 -msse-check=[none|error|warning]\n\
11119 check SSE instructions\n"));
11120 fprintf (stream
, _("\
11121 -moperand-check=[none|error|warning]\n\
11122 check operand combinations for validity\n"));
11123 fprintf (stream
, _("\
11124 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11126 fprintf (stream
, _("\
11127 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11129 fprintf (stream
, _("\
11130 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11131 for EVEX.W bit ignored instructions\n"));
11132 fprintf (stream
, _("\
11133 -mevexrcig=[rne|rd|ru|rz]\n\
11134 encode EVEX instructions with specific EVEX.RC value\n\
11135 for SAE-only ignored instructions\n"));
11136 fprintf (stream
, _("\
11137 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11138 fprintf (stream
, _("\
11139 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11140 fprintf (stream
, _("\
11141 -mindex-reg support pseudo index registers\n"));
11142 fprintf (stream
, _("\
11143 -mnaked-reg don't require `%%' prefix for registers\n"));
11144 fprintf (stream
, _("\
11145 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11146 fprintf (stream
, _("\
11147 -mshared disable branch optimization for shared code\n"));
11148 # if defined (TE_PE) || defined (TE_PEP)
11149 fprintf (stream
, _("\
11150 -mbig-obj generate big object files\n"));
11152 fprintf (stream
, _("\
11153 -momit-lock-prefix=[no|yes]\n\
11154 strip all lock prefixes\n"));
11155 fprintf (stream
, _("\
11156 -mfence-as-lock-add=[no|yes]\n\
11157 encode lfence, mfence and sfence as\n\
11158 lock addl $0x0, (%%{re}sp)\n"));
11159 fprintf (stream
, _("\
11160 -mrelax-relocations=[no|yes]\n\
11161 generate relax relocations\n"));
11162 fprintf (stream
, _("\
11163 -mamd64 accept only AMD64 ISA\n"));
11164 fprintf (stream
, _("\
11165 -mintel64 accept only Intel64 ISA\n"));
11168 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11169 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11170 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11172 /* Pick the target format to use. */
11175 i386_target_format (void)
11177 if (!strncmp (default_arch
, "x86_64", 6))
11179 update_code_flag (CODE_64BIT
, 1);
11180 if (default_arch
[6] == '\0')
11181 x86_elf_abi
= X86_64_ABI
;
11183 x86_elf_abi
= X86_64_X32_ABI
;
11185 else if (!strcmp (default_arch
, "i386"))
11186 update_code_flag (CODE_32BIT
, 1);
11187 else if (!strcmp (default_arch
, "iamcu"))
11189 update_code_flag (CODE_32BIT
, 1);
11190 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11192 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11193 cpu_arch_name
= "iamcu";
11194 cpu_sub_arch_name
= NULL
;
11195 cpu_arch_flags
= iamcu_flags
;
11196 cpu_arch_isa
= PROCESSOR_IAMCU
;
11197 cpu_arch_isa_flags
= iamcu_flags
;
11198 if (!cpu_arch_tune_set
)
11200 cpu_arch_tune
= cpu_arch_isa
;
11201 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11204 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11205 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11209 as_fatal (_("unknown architecture"));
11211 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11212 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11213 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11214 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11216 switch (OUTPUT_FLAVOR
)
11218 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11219 case bfd_target_aout_flavour
:
11220 return AOUT_TARGET_FORMAT
;
11222 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11223 # if defined (TE_PE) || defined (TE_PEP)
11224 case bfd_target_coff_flavour
:
11225 if (flag_code
== CODE_64BIT
)
11226 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11229 # elif defined (TE_GO32)
11230 case bfd_target_coff_flavour
:
11231 return "coff-go32";
11233 case bfd_target_coff_flavour
:
11234 return "coff-i386";
11237 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11238 case bfd_target_elf_flavour
:
11240 const char *format
;
11242 switch (x86_elf_abi
)
11245 format
= ELF_TARGET_FORMAT
;
11248 use_rela_relocations
= 1;
11250 format
= ELF_TARGET_FORMAT64
;
11252 case X86_64_X32_ABI
:
11253 use_rela_relocations
= 1;
11255 disallow_64bit_reloc
= 1;
11256 format
= ELF_TARGET_FORMAT32
;
11259 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11261 if (x86_elf_abi
!= X86_64_ABI
)
11262 as_fatal (_("Intel L1OM is 64bit only"));
11263 return ELF_TARGET_L1OM_FORMAT
;
11265 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11267 if (x86_elf_abi
!= X86_64_ABI
)
11268 as_fatal (_("Intel K1OM is 64bit only"));
11269 return ELF_TARGET_K1OM_FORMAT
;
11271 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11273 if (x86_elf_abi
!= I386_ABI
)
11274 as_fatal (_("Intel MCU is 32bit only"));
11275 return ELF_TARGET_IAMCU_FORMAT
;
11281 #if defined (OBJ_MACH_O)
11282 case bfd_target_mach_o_flavour
:
11283 if (flag_code
== CODE_64BIT
)
11285 use_rela_relocations
= 1;
11287 return "mach-o-x86-64";
11290 return "mach-o-i386";
11298 #endif /* OBJ_MAYBE_ more than one */
11301 md_undefined_symbol (char *name
)
11303 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11304 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11305 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11306 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11310 if (symbol_find (name
))
11311 as_bad (_("GOT already in symbol table"));
11312 GOT_symbol
= symbol_new (name
, undefined_section
,
11313 (valueT
) 0, &zero_address_frag
);
11320 /* Round up a section size to the appropriate boundary. */
11323 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11325 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11326 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11328 /* For a.out, force the section size to be aligned. If we don't do
11329 this, BFD will align it for us, but it will not write out the
11330 final bytes of the section. This may be a bug in BFD, but it is
11331 easier to fix it here since that is how the other a.out targets
11335 align
= bfd_get_section_alignment (stdoutput
, segment
);
11336 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11343 /* On the i386, PC-relative offsets are relative to the start of the
11344 next instruction. That is, the address of the offset, plus its
11345 size, since the offset is always the last part of the insn. */
11348 md_pcrel_from (fixS
*fixP
)
11350 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11356 s_bss (int ignore ATTRIBUTE_UNUSED
)
11360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11362 obj_elf_section_change_hook ();
11364 temp
= get_absolute_expression ();
11365 subseg_set (bss_section
, (subsegT
) temp
);
11366 demand_empty_rest_of_line ();
11372 i386_validate_fix (fixS
*fixp
)
11374 if (fixp
->fx_subsy
)
11376 if (fixp
->fx_subsy
== GOT_symbol
)
11378 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11383 if (fixp
->fx_tcbit2
)
11384 fixp
->fx_r_type
= (fixp
->fx_tcbit
11385 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11386 : BFD_RELOC_X86_64_GOTPCRELX
);
11389 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11394 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11396 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11398 fixp
->fx_subsy
= 0;
11401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11402 else if (!object_64bit
)
11404 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11405 && fixp
->fx_tcbit2
)
11406 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11412 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11415 bfd_reloc_code_real_type code
;
11417 switch (fixp
->fx_r_type
)
11419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11420 case BFD_RELOC_SIZE32
:
11421 case BFD_RELOC_SIZE64
:
11422 if (S_IS_DEFINED (fixp
->fx_addsy
)
11423 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11425 /* Resolve size relocation against local symbol to size of
11426 the symbol plus addend. */
11427 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11428 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11429 && !fits_in_unsigned_long (value
))
11430 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11431 _("symbol size computation overflow"));
11432 fixp
->fx_addsy
= NULL
;
11433 fixp
->fx_subsy
= NULL
;
11434 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11438 /* Fall through. */
11440 case BFD_RELOC_X86_64_PLT32
:
11441 case BFD_RELOC_X86_64_GOT32
:
11442 case BFD_RELOC_X86_64_GOTPCREL
:
11443 case BFD_RELOC_X86_64_GOTPCRELX
:
11444 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11445 case BFD_RELOC_386_PLT32
:
11446 case BFD_RELOC_386_GOT32
:
11447 case BFD_RELOC_386_GOT32X
:
11448 case BFD_RELOC_386_GOTOFF
:
11449 case BFD_RELOC_386_GOTPC
:
11450 case BFD_RELOC_386_TLS_GD
:
11451 case BFD_RELOC_386_TLS_LDM
:
11452 case BFD_RELOC_386_TLS_LDO_32
:
11453 case BFD_RELOC_386_TLS_IE_32
:
11454 case BFD_RELOC_386_TLS_IE
:
11455 case BFD_RELOC_386_TLS_GOTIE
:
11456 case BFD_RELOC_386_TLS_LE_32
:
11457 case BFD_RELOC_386_TLS_LE
:
11458 case BFD_RELOC_386_TLS_GOTDESC
:
11459 case BFD_RELOC_386_TLS_DESC_CALL
:
11460 case BFD_RELOC_X86_64_TLSGD
:
11461 case BFD_RELOC_X86_64_TLSLD
:
11462 case BFD_RELOC_X86_64_DTPOFF32
:
11463 case BFD_RELOC_X86_64_DTPOFF64
:
11464 case BFD_RELOC_X86_64_GOTTPOFF
:
11465 case BFD_RELOC_X86_64_TPOFF32
:
11466 case BFD_RELOC_X86_64_TPOFF64
:
11467 case BFD_RELOC_X86_64_GOTOFF64
:
11468 case BFD_RELOC_X86_64_GOTPC32
:
11469 case BFD_RELOC_X86_64_GOT64
:
11470 case BFD_RELOC_X86_64_GOTPCREL64
:
11471 case BFD_RELOC_X86_64_GOTPC64
:
11472 case BFD_RELOC_X86_64_GOTPLT64
:
11473 case BFD_RELOC_X86_64_PLTOFF64
:
11474 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11475 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11476 case BFD_RELOC_RVA
:
11477 case BFD_RELOC_VTABLE_ENTRY
:
11478 case BFD_RELOC_VTABLE_INHERIT
:
11480 case BFD_RELOC_32_SECREL
:
11482 code
= fixp
->fx_r_type
;
11484 case BFD_RELOC_X86_64_32S
:
11485 if (!fixp
->fx_pcrel
)
11487 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11488 code
= fixp
->fx_r_type
;
11491 /* Fall through. */
11493 if (fixp
->fx_pcrel
)
11495 switch (fixp
->fx_size
)
11498 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11499 _("can not do %d byte pc-relative relocation"),
11501 code
= BFD_RELOC_32_PCREL
;
11503 case 1: code
= BFD_RELOC_8_PCREL
; break;
11504 case 2: code
= BFD_RELOC_16_PCREL
; break;
11505 case 4: code
= BFD_RELOC_32_PCREL
; break;
11507 case 8: code
= BFD_RELOC_64_PCREL
; break;
11513 switch (fixp
->fx_size
)
11516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11517 _("can not do %d byte relocation"),
11519 code
= BFD_RELOC_32
;
11521 case 1: code
= BFD_RELOC_8
; break;
11522 case 2: code
= BFD_RELOC_16
; break;
11523 case 4: code
= BFD_RELOC_32
; break;
11525 case 8: code
= BFD_RELOC_64
; break;
11532 if ((code
== BFD_RELOC_32
11533 || code
== BFD_RELOC_32_PCREL
11534 || code
== BFD_RELOC_X86_64_32S
)
11536 && fixp
->fx_addsy
== GOT_symbol
)
11539 code
= BFD_RELOC_386_GOTPC
;
11541 code
= BFD_RELOC_X86_64_GOTPC32
;
11543 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11545 && fixp
->fx_addsy
== GOT_symbol
)
11547 code
= BFD_RELOC_X86_64_GOTPC64
;
11550 rel
= XNEW (arelent
);
11551 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11552 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11554 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11556 if (!use_rela_relocations
)
11558 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11559 vtable entry to be used in the relocation's section offset. */
11560 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11561 rel
->address
= fixp
->fx_offset
;
11562 #if defined (OBJ_COFF) && defined (TE_PE)
11563 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11564 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11569 /* Use the rela in 64bit mode. */
11572 if (disallow_64bit_reloc
)
11575 case BFD_RELOC_X86_64_DTPOFF64
:
11576 case BFD_RELOC_X86_64_TPOFF64
:
11577 case BFD_RELOC_64_PCREL
:
11578 case BFD_RELOC_X86_64_GOTOFF64
:
11579 case BFD_RELOC_X86_64_GOT64
:
11580 case BFD_RELOC_X86_64_GOTPCREL64
:
11581 case BFD_RELOC_X86_64_GOTPC64
:
11582 case BFD_RELOC_X86_64_GOTPLT64
:
11583 case BFD_RELOC_X86_64_PLTOFF64
:
11584 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11585 _("cannot represent relocation type %s in x32 mode"),
11586 bfd_get_reloc_code_name (code
));
11592 if (!fixp
->fx_pcrel
)
11593 rel
->addend
= fixp
->fx_offset
;
11597 case BFD_RELOC_X86_64_PLT32
:
11598 case BFD_RELOC_X86_64_GOT32
:
11599 case BFD_RELOC_X86_64_GOTPCREL
:
11600 case BFD_RELOC_X86_64_GOTPCRELX
:
11601 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11602 case BFD_RELOC_X86_64_TLSGD
:
11603 case BFD_RELOC_X86_64_TLSLD
:
11604 case BFD_RELOC_X86_64_GOTTPOFF
:
11605 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11606 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11607 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11610 rel
->addend
= (section
->vma
11612 + fixp
->fx_addnumber
11613 + md_pcrel_from (fixp
));
11618 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11619 if (rel
->howto
== NULL
)
11621 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11622 _("cannot represent relocation type %s"),
11623 bfd_get_reloc_code_name (code
));
11624 /* Set howto to a garbage value so that we can keep going. */
11625 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11626 gas_assert (rel
->howto
!= NULL
);
11632 #include "tc-i386-intel.c"
11635 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11637 int saved_naked_reg
;
11638 char saved_register_dot
;
11640 saved_naked_reg
= allow_naked_reg
;
11641 allow_naked_reg
= 1;
11642 saved_register_dot
= register_chars
['.'];
11643 register_chars
['.'] = '.';
11644 allow_pseudo_reg
= 1;
11645 expression_and_evaluate (exp
);
11646 allow_pseudo_reg
= 0;
11647 register_chars
['.'] = saved_register_dot
;
11648 allow_naked_reg
= saved_naked_reg
;
11650 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11652 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11654 exp
->X_op
= O_constant
;
11655 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11656 .dw2_regnum
[flag_code
>> 1];
11659 exp
->X_op
= O_illegal
;
11664 tc_x86_frame_initial_instructions (void)
11666 static unsigned int sp_regno
[2];
11668 if (!sp_regno
[flag_code
>> 1])
11670 char *saved_input
= input_line_pointer
;
11671 char sp
[][4] = {"esp", "rsp"};
11674 input_line_pointer
= sp
[flag_code
>> 1];
11675 tc_x86_parse_to_dw2regnum (&exp
);
11676 gas_assert (exp
.X_op
== O_constant
);
11677 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11678 input_line_pointer
= saved_input
;
11681 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11682 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11686 x86_dwarf2_addr_size (void)
11688 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11689 if (x86_elf_abi
== X86_64_X32_ABI
)
11692 return bfd_arch_bits_per_address (stdoutput
) / 8;
11696 i386_elf_section_type (const char *str
, size_t len
)
11698 if (flag_code
== CODE_64BIT
11699 && len
== sizeof ("unwind") - 1
11700 && strncmp (str
, "unwind", 6) == 0)
11701 return SHT_X86_64_UNWIND
;
11708 i386_solaris_fix_up_eh_frame (segT sec
)
11710 if (flag_code
== CODE_64BIT
)
11711 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11717 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11721 exp
.X_op
= O_secrel
;
11722 exp
.X_add_symbol
= symbol
;
11723 exp
.X_add_number
= 0;
11724 emit_expr (&exp
, size
);
11728 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11729 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11732 x86_64_section_letter (int letter
, const char **ptr_msg
)
11734 if (flag_code
== CODE_64BIT
)
11737 return SHF_X86_64_LARGE
;
11739 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11742 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11747 x86_64_section_word (char *str
, size_t len
)
11749 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11750 return SHF_X86_64_LARGE
;
11756 handle_large_common (int small ATTRIBUTE_UNUSED
)
11758 if (flag_code
!= CODE_64BIT
)
11760 s_comm_internal (0, elf_common_parse
);
11761 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11765 static segT lbss_section
;
11766 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11767 asection
*saved_bss_section
= bss_section
;
11769 if (lbss_section
== NULL
)
11771 flagword applicable
;
11772 segT seg
= now_seg
;
11773 subsegT subseg
= now_subseg
;
11775 /* The .lbss section is for local .largecomm symbols. */
11776 lbss_section
= subseg_new (".lbss", 0);
11777 applicable
= bfd_applicable_section_flags (stdoutput
);
11778 bfd_set_section_flags (stdoutput
, lbss_section
,
11779 applicable
& SEC_ALLOC
);
11780 seg_info (lbss_section
)->bss
= 1;
11782 subseg_set (seg
, subseg
);
11785 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11786 bss_section
= lbss_section
;
11788 s_comm_internal (0, elf_common_parse
);
11790 elf_com_section_ptr
= saved_com_section_ptr
;
11791 bss_section
= saved_bss_section
;
11794 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */