1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* Types of condition jump used by macro-fusion. */
693 mf_jcc_jo
= 0, /* base opcode 0x70 */
694 mf_jcc_jc
, /* base opcode 0x72 */
695 mf_jcc_je
, /* base opcode 0x74 */
696 mf_jcc_jna
, /* base opcode 0x76 */
697 mf_jcc_js
, /* base opcode 0x78 */
698 mf_jcc_jp
, /* base opcode 0x7a */
699 mf_jcc_jl
, /* base opcode 0x7c */
700 mf_jcc_jle
, /* base opcode 0x7e */
703 /* Types of compare flag-modifying insntructions used by macro-fusion. */
706 mf_cmp_test_and
, /* test/cmp */
707 mf_cmp_alu_cmp
, /* add/sub/cmp */
708 mf_cmp_incdec
/* inc/dec */
711 /* The maximum padding size for fused jcc. CMP like instruction can
712 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
714 #define MAX_FUSED_JCC_PADDING_SIZE 20
716 /* The maximum number of prefixes added for an instruction. */
717 static unsigned int align_branch_prefix_size
= 5;
720 1. Clear the REX_W bit with register operand if possible.
721 2. Above plus use 128bit vector instruction to clear the full vector
724 static int optimize
= 0;
727 1. Clear the REX_W bit with register operand if possible.
728 2. Above plus use 128bit vector instruction to clear the full vector
730 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
733 static int optimize_for_space
= 0;
735 /* Register prefix used for error message. */
736 static const char *register_prefix
= "%";
738 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
739 leave, push, and pop instructions so that gcc has the same stack
740 frame as in 32 bit mode. */
741 static char stackop_size
= '\0';
743 /* Non-zero to optimize code alignment. */
744 int optimize_align_code
= 1;
746 /* Non-zero to quieten some warnings. */
747 static int quiet_warnings
= 0;
750 static const char *cpu_arch_name
= NULL
;
751 static char *cpu_sub_arch_name
= NULL
;
753 /* CPU feature flags. */
754 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
756 /* If we have selected a cpu we are generating instructions for. */
757 static int cpu_arch_tune_set
= 0;
759 /* Cpu we are generating instructions for. */
760 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
762 /* CPU feature flags of cpu we are generating instructions for. */
763 static i386_cpu_flags cpu_arch_tune_flags
;
765 /* CPU instruction set architecture used. */
766 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
768 /* CPU feature flags of instruction set architecture used. */
769 i386_cpu_flags cpu_arch_isa_flags
;
771 /* If set, conditional jumps are not automatically promoted to handle
772 larger than a byte offset. */
773 static unsigned int no_cond_jump_promotion
= 0;
775 /* Encode SSE instructions with VEX prefix. */
776 static unsigned int sse2avx
;
778 /* Encode scalar AVX instructions with specific vector length. */
785 /* Encode VEX WIG instructions with specific vex.w. */
792 /* Encode scalar EVEX LIG instructions with specific vector length. */
800 /* Encode EVEX WIG instructions with specific evex.w. */
807 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
808 static enum rc_type evexrcig
= rne
;
810 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
811 static symbolS
*GOT_symbol
;
813 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
814 unsigned int x86_dwarf2_return_column
;
816 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
817 int x86_cie_data_alignment
;
819 /* Interface to relax_segment.
820 There are 3 major relax states for 386 jump insns because the
821 different types of jumps add different sizes to frags when we're
822 figuring out what sort of jump to choose to reach a given label.
824 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
825 branches which are handled by md_estimate_size_before_relax() and
826 i386_generic_table_relax_frag(). */
829 #define UNCOND_JUMP 0
831 #define COND_JUMP86 2
832 #define BRANCH_PADDING 3
833 #define BRANCH_PREFIX 4
834 #define FUSED_JCC_PADDING 5
839 #define SMALL16 (SMALL | CODE16)
841 #define BIG16 (BIG | CODE16)
845 #define INLINE __inline__
851 #define ENCODE_RELAX_STATE(type, size) \
852 ((relax_substateT) (((type) << 2) | (size)))
853 #define TYPE_FROM_RELAX_STATE(s) \
855 #define DISP_SIZE_FROM_RELAX_STATE(s) \
856 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
858 /* This table is used by relax_frag to promote short jumps to long
859 ones where necessary. SMALL (short) jumps may be promoted to BIG
860 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
861 don't allow a short jump in a 32 bit code segment to be promoted to
862 a 16 bit offset jump because it's slower (requires data size
863 prefix), and doesn't work, unless the destination is in the bottom
864 64k of the code segment (The top 16 bits of eip are zeroed). */
866 const relax_typeS md_relax_table
[] =
869 1) most positive reach of this state,
870 2) most negative reach of this state,
871 3) how many bytes this mode will have in the variable part of the frag
872 4) which index into the table to try if we can't fit into this one. */
874 /* UNCOND_JUMP states. */
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
876 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
877 /* dword jmp adds 4 bytes to frag:
878 0 extra opcode bytes, 4 displacement bytes. */
880 /* word jmp adds 2 byte2 to frag:
881 0 extra opcode bytes, 2 displacement bytes. */
884 /* COND_JUMP states. */
885 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
886 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
887 /* dword conditionals adds 5 bytes to frag:
888 1 extra opcode byte, 4 displacement bytes. */
890 /* word conditionals add 3 bytes to frag:
891 1 extra opcode byte, 2 displacement bytes. */
894 /* COND_JUMP86 states. */
895 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
896 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
897 /* dword conditionals adds 5 bytes to frag:
898 1 extra opcode byte, 4 displacement bytes. */
900 /* word conditionals add 4 bytes to frag:
901 1 displacement byte and a 3 byte long branch insn. */
905 static const arch_entry cpu_arch
[] =
907 /* Do not replace the first two entries - i386_target_format()
908 relies on them being there in this order. */
909 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
910 CPU_GENERIC32_FLAGS
, 0 },
911 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
912 CPU_GENERIC64_FLAGS
, 0 },
913 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
921 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
923 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
925 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
927 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
929 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
930 CPU_PENTIUMPRO_FLAGS
, 0 },
931 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
933 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
935 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
937 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
939 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
940 CPU_NOCONA_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
943 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
945 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
946 CPU_CORE2_FLAGS
, 1 },
947 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
948 CPU_CORE2_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
950 CPU_COREI7_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
953 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
955 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
956 CPU_IAMCU_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
959 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
961 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
962 CPU_ATHLON_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
965 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
967 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
969 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
970 CPU_AMDFAM10_FLAGS
, 0 },
971 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
972 CPU_BDVER1_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
974 CPU_BDVER2_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
976 CPU_BDVER3_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
978 CPU_BDVER4_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
980 CPU_ZNVER1_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
982 CPU_ZNVER2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
984 CPU_BTVER1_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
986 CPU_BTVER2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1001 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1004 CPU_SSE2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1006 CPU_SSE3_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1010 CPU_SSSE3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1012 CPU_SSE4_1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4_2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1016 CPU_SSE4_2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512F_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512CD_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512ER_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512PF_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512DQ_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512BW_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1034 CPU_AVX512VL_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1038 CPU_VMFUNC_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1042 CPU_XSAVE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1044 CPU_XSAVEOPT_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1046 CPU_XSAVEC_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1048 CPU_XSAVES_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1052 CPU_PCLMUL_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1054 CPU_PCLMUL_FLAGS
, 1 },
1055 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1056 CPU_FSGSBASE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1058 CPU_RDRND_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1060 CPU_F16C_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1062 CPU_BMI2_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1066 CPU_FMA4_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1072 CPU_MOVBE_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1074 CPU_CX16_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1078 CPU_LZCNT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1080 CPU_POPCNT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1086 CPU_INVPCID_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1088 CPU_CLFLUSH_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1091 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1092 CPU_SYSCALL_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1094 CPU_RDTSCP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1096 CPU_3DNOW_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1098 CPU_3DNOWA_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1100 CPU_PADLOCK_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1102 CPU_SVME_FLAGS
, 1 },
1103 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1104 CPU_SVME_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1106 CPU_SSE4A_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1116 CPU_RDSEED_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1118 CPU_PRFCHW_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1120 CPU_SMAP_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1126 CPU_CLFLUSHOPT_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1128 CPU_PREFETCHWT1_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1131 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1132 CPU_CLWB_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1134 CPU_AVX512IFMA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1136 CPU_AVX512VBMI_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1138 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1140 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1142 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1144 CPU_AVX512_VBMI2_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1146 CPU_AVX512_VNNI_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1148 CPU_AVX512_BITALG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1150 CPU_CLZERO_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1152 CPU_MWAITX_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1154 CPU_OSPKE_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1156 CPU_RDPID_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1158 CPU_PTWRITE_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1162 CPU_SHSTK_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1164 CPU_GFNI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1166 CPU_VAES_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1168 CPU_VPCLMULQDQ_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1170 CPU_WBNOINVD_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1172 CPU_PCONFIG_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1174 CPU_WAITPKG_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1176 CPU_CLDEMOTE_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1178 CPU_MOVDIRI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1180 CPU_MOVDIR64B_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BF16_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1186 CPU_ENQCMD_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPRU_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1190 CPU_MCOMMIT_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1192 CPU_SEV_ES_FLAGS
, 0 },
1195 static const noarch_entry cpu_noarch
[] =
1197 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1198 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1199 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1200 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1201 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1202 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1203 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1204 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1205 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1206 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1207 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1208 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1209 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1210 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1211 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1212 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1213 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1214 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1215 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1216 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1217 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1218 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1219 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1220 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1221 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1222 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1223 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1224 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1225 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1226 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1227 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1228 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1229 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1230 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1231 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1232 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1233 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1234 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1235 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1239 /* Like s_lcomm_internal in gas/read.c but the alignment string
1240 is allowed to be optional. */
1243 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1250 && *input_line_pointer
== ',')
1252 align
= parse_align (needs_align
- 1);
1254 if (align
== (addressT
) -1)
1269 bss_alloc (symbolP
, size
, align
);
1274 pe_lcomm (int needs_align
)
1276 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1280 const pseudo_typeS md_pseudo_table
[] =
1282 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1283 {"align", s_align_bytes
, 0},
1285 {"align", s_align_ptwo
, 0},
1287 {"arch", set_cpu_arch
, 0},
1291 {"lcomm", pe_lcomm
, 1},
1293 {"ffloat", float_cons
, 'f'},
1294 {"dfloat", float_cons
, 'd'},
1295 {"tfloat", float_cons
, 'x'},
1297 {"slong", signed_cons
, 4},
1298 {"noopt", s_ignore
, 0},
1299 {"optim", s_ignore
, 0},
1300 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1301 {"code16", set_code_flag
, CODE_16BIT
},
1302 {"code32", set_code_flag
, CODE_32BIT
},
1304 {"code64", set_code_flag
, CODE_64BIT
},
1306 {"intel_syntax", set_intel_syntax
, 1},
1307 {"att_syntax", set_intel_syntax
, 0},
1308 {"intel_mnemonic", set_intel_mnemonic
, 1},
1309 {"att_mnemonic", set_intel_mnemonic
, 0},
1310 {"allow_index_reg", set_allow_index_reg
, 1},
1311 {"disallow_index_reg", set_allow_index_reg
, 0},
1312 {"sse_check", set_check
, 0},
1313 {"operand_check", set_check
, 1},
1314 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1315 {"largecomm", handle_large_common
, 0},
1317 {"file", dwarf2_directive_file
, 0},
1318 {"loc", dwarf2_directive_loc
, 0},
1319 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1322 {"secrel32", pe_directive_secrel
, 0},
1327 /* For interface with expression (). */
1328 extern char *input_line_pointer
;
1330 /* Hash table for instruction mnemonic lookup. */
1331 static struct hash_control
*op_hash
;
1333 /* Hash table for register lookup. */
1334 static struct hash_control
*reg_hash
;
1336 /* Various efficient no-op patterns for aligning code labels.
1337 Note: Don't try to assemble the instructions in the comments.
1338 0L and 0w are not legal. */
1339 static const unsigned char f32_1
[] =
1341 static const unsigned char f32_2
[] =
1342 {0x66,0x90}; /* xchg %ax,%ax */
1343 static const unsigned char f32_3
[] =
1344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1345 static const unsigned char f32_4
[] =
1346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1347 static const unsigned char f32_6
[] =
1348 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1349 static const unsigned char f32_7
[] =
1350 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1351 static const unsigned char f16_3
[] =
1352 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1353 static const unsigned char f16_4
[] =
1354 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1355 static const unsigned char jump_disp8
[] =
1356 {0xeb}; /* jmp disp8 */
1357 static const unsigned char jump32_disp32
[] =
1358 {0xe9}; /* jmp disp32 */
1359 static const unsigned char jump16_disp32
[] =
1360 {0x66,0xe9}; /* jmp disp32 */
1361 /* 32-bit NOPs patterns. */
1362 static const unsigned char *const f32_patt
[] = {
1363 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1365 /* 16-bit NOPs patterns. */
1366 static const unsigned char *const f16_patt
[] = {
1367 f32_1
, f32_2
, f16_3
, f16_4
1369 /* nopl (%[re]ax) */
1370 static const unsigned char alt_3
[] =
1372 /* nopl 0(%[re]ax) */
1373 static const unsigned char alt_4
[] =
1374 {0x0f,0x1f,0x40,0x00};
1375 /* nopl 0(%[re]ax,%[re]ax,1) */
1376 static const unsigned char alt_5
[] =
1377 {0x0f,0x1f,0x44,0x00,0x00};
1378 /* nopw 0(%[re]ax,%[re]ax,1) */
1379 static const unsigned char alt_6
[] =
1380 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1381 /* nopl 0L(%[re]ax) */
1382 static const unsigned char alt_7
[] =
1383 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1384 /* nopl 0L(%[re]ax,%[re]ax,1) */
1385 static const unsigned char alt_8
[] =
1386 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1387 /* nopw 0L(%[re]ax,%[re]ax,1) */
1388 static const unsigned char alt_9
[] =
1389 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1390 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1391 static const unsigned char alt_10
[] =
1392 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1393 /* data16 nopw %cs:0L(%eax,%eax,1) */
1394 static const unsigned char alt_11
[] =
1395 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1396 /* 32-bit and 64-bit NOPs patterns. */
1397 static const unsigned char *const alt_patt
[] = {
1398 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1399 alt_9
, alt_10
, alt_11
1402 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1403 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1406 i386_output_nops (char *where
, const unsigned char *const *patt
,
1407 int count
, int max_single_nop_size
)
1410 /* Place the longer NOP first. */
1413 const unsigned char *nops
;
1415 if (max_single_nop_size
< 1)
1417 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1418 max_single_nop_size
);
1422 nops
= patt
[max_single_nop_size
- 1];
1424 /* Use the smaller one if the requsted one isn't available. */
1427 max_single_nop_size
--;
1428 nops
= patt
[max_single_nop_size
- 1];
1431 last
= count
% max_single_nop_size
;
1434 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1435 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1439 nops
= patt
[last
- 1];
1442 /* Use the smaller one plus one-byte NOP if the needed one
1445 nops
= patt
[last
- 1];
1446 memcpy (where
+ offset
, nops
, last
);
1447 where
[offset
+ last
] = *patt
[0];
1450 memcpy (where
+ offset
, nops
, last
);
1455 fits_in_imm7 (offsetT num
)
1457 return (num
& 0x7f) == num
;
1461 fits_in_imm31 (offsetT num
)
1463 return (num
& 0x7fffffff) == num
;
1466 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1467 single NOP instruction LIMIT. */
1470 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1472 const unsigned char *const *patt
= NULL
;
1473 int max_single_nop_size
;
1474 /* Maximum number of NOPs before switching to jump over NOPs. */
1475 int max_number_of_nops
;
1477 switch (fragP
->fr_type
)
1482 case rs_machine_dependent
:
1483 /* Allow NOP padding for jumps and calls. */
1484 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1485 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1492 /* We need to decide which NOP sequence to use for 32bit and
1493 64bit. When -mtune= is used:
1495 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1496 PROCESSOR_GENERIC32, f32_patt will be used.
1497 2. For the rest, alt_patt will be used.
1499 When -mtune= isn't used, alt_patt will be used if
1500 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1503 When -march= or .arch is used, we can't use anything beyond
1504 cpu_arch_isa_flags. */
1506 if (flag_code
== CODE_16BIT
)
1509 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1510 /* Limit number of NOPs to 2 in 16-bit mode. */
1511 max_number_of_nops
= 2;
1515 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1517 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1518 switch (cpu_arch_tune
)
1520 case PROCESSOR_UNKNOWN
:
1521 /* We use cpu_arch_isa_flags to check if we SHOULD
1522 optimize with nops. */
1523 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1528 case PROCESSOR_PENTIUM4
:
1529 case PROCESSOR_NOCONA
:
1530 case PROCESSOR_CORE
:
1531 case PROCESSOR_CORE2
:
1532 case PROCESSOR_COREI7
:
1533 case PROCESSOR_L1OM
:
1534 case PROCESSOR_K1OM
:
1535 case PROCESSOR_GENERIC64
:
1537 case PROCESSOR_ATHLON
:
1539 case PROCESSOR_AMDFAM10
:
1541 case PROCESSOR_ZNVER
:
1545 case PROCESSOR_I386
:
1546 case PROCESSOR_I486
:
1547 case PROCESSOR_PENTIUM
:
1548 case PROCESSOR_PENTIUMPRO
:
1549 case PROCESSOR_IAMCU
:
1550 case PROCESSOR_GENERIC32
:
1557 switch (fragP
->tc_frag_data
.tune
)
1559 case PROCESSOR_UNKNOWN
:
1560 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1561 PROCESSOR_UNKNOWN. */
1565 case PROCESSOR_I386
:
1566 case PROCESSOR_I486
:
1567 case PROCESSOR_PENTIUM
:
1568 case PROCESSOR_IAMCU
:
1570 case PROCESSOR_ATHLON
:
1572 case PROCESSOR_AMDFAM10
:
1574 case PROCESSOR_ZNVER
:
1576 case PROCESSOR_GENERIC32
:
1577 /* We use cpu_arch_isa_flags to check if we CAN optimize
1579 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1584 case PROCESSOR_PENTIUMPRO
:
1585 case PROCESSOR_PENTIUM4
:
1586 case PROCESSOR_NOCONA
:
1587 case PROCESSOR_CORE
:
1588 case PROCESSOR_CORE2
:
1589 case PROCESSOR_COREI7
:
1590 case PROCESSOR_L1OM
:
1591 case PROCESSOR_K1OM
:
1592 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1597 case PROCESSOR_GENERIC64
:
1603 if (patt
== f32_patt
)
1605 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1606 /* Limit number of NOPs to 2 for older processors. */
1607 max_number_of_nops
= 2;
1611 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1612 /* Limit number of NOPs to 7 for newer processors. */
1613 max_number_of_nops
= 7;
1618 limit
= max_single_nop_size
;
1620 if (fragP
->fr_type
== rs_fill_nop
)
1622 /* Output NOPs for .nop directive. */
1623 if (limit
> max_single_nop_size
)
1625 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1626 _("invalid single nop size: %d "
1627 "(expect within [0, %d])"),
1628 limit
, max_single_nop_size
);
1632 else if (fragP
->fr_type
!= rs_machine_dependent
)
1633 fragP
->fr_var
= count
;
1635 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1637 /* Generate jump over NOPs. */
1638 offsetT disp
= count
- 2;
1639 if (fits_in_imm7 (disp
))
1641 /* Use "jmp disp8" if possible. */
1643 where
[0] = jump_disp8
[0];
1649 unsigned int size_of_jump
;
1651 if (flag_code
== CODE_16BIT
)
1653 where
[0] = jump16_disp32
[0];
1654 where
[1] = jump16_disp32
[1];
1659 where
[0] = jump32_disp32
[0];
1663 count
-= size_of_jump
+ 4;
1664 if (!fits_in_imm31 (count
))
1666 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1667 _("jump over nop padding out of range"));
1671 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1672 where
+= size_of_jump
+ 4;
1676 /* Generate multiple NOPs. */
1677 i386_output_nops (where
, patt
, count
, limit
);
1681 operand_type_all_zero (const union i386_operand_type
*x
)
1683 switch (ARRAY_SIZE(x
->array
))
1694 return !x
->array
[0];
1701 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1703 switch (ARRAY_SIZE(x
->array
))
1719 x
->bitfield
.class = ClassNone
;
1720 x
->bitfield
.instance
= InstanceNone
;
1724 operand_type_equal (const union i386_operand_type
*x
,
1725 const union i386_operand_type
*y
)
1727 switch (ARRAY_SIZE(x
->array
))
1730 if (x
->array
[2] != y
->array
[2])
1734 if (x
->array
[1] != y
->array
[1])
1738 return x
->array
[0] == y
->array
[0];
1746 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1748 switch (ARRAY_SIZE(x
->array
))
1763 return !x
->array
[0];
1770 cpu_flags_equal (const union i386_cpu_flags
*x
,
1771 const union i386_cpu_flags
*y
)
1773 switch (ARRAY_SIZE(x
->array
))
1776 if (x
->array
[3] != y
->array
[3])
1780 if (x
->array
[2] != y
->array
[2])
1784 if (x
->array
[1] != y
->array
[1])
1788 return x
->array
[0] == y
->array
[0];
1796 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1798 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1799 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1802 static INLINE i386_cpu_flags
1803 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[3] &= y
.array
[3];
1811 x
.array
[2] &= y
.array
[2];
1814 x
.array
[1] &= y
.array
[1];
1817 x
.array
[0] &= y
.array
[0];
1825 static INLINE i386_cpu_flags
1826 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1828 switch (ARRAY_SIZE (x
.array
))
1831 x
.array
[3] |= y
.array
[3];
1834 x
.array
[2] |= y
.array
[2];
1837 x
.array
[1] |= y
.array
[1];
1840 x
.array
[0] |= y
.array
[0];
1848 static INLINE i386_cpu_flags
1849 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1851 switch (ARRAY_SIZE (x
.array
))
1854 x
.array
[3] &= ~y
.array
[3];
1857 x
.array
[2] &= ~y
.array
[2];
1860 x
.array
[1] &= ~y
.array
[1];
1863 x
.array
[0] &= ~y
.array
[0];
1871 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1873 #define CPU_FLAGS_ARCH_MATCH 0x1
1874 #define CPU_FLAGS_64BIT_MATCH 0x2
1876 #define CPU_FLAGS_PERFECT_MATCH \
1877 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1879 /* Return CPU flags match bits. */
1882 cpu_flags_match (const insn_template
*t
)
1884 i386_cpu_flags x
= t
->cpu_flags
;
1885 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1887 x
.bitfield
.cpu64
= 0;
1888 x
.bitfield
.cpuno64
= 0;
1890 if (cpu_flags_all_zero (&x
))
1892 /* This instruction is available on all archs. */
1893 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 /* This instruction is available only on some archs. */
1898 i386_cpu_flags cpu
= cpu_arch_flags
;
1900 /* AVX512VL is no standalone feature - match it and then strip it. */
1901 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1903 x
.bitfield
.cpuavx512vl
= 0;
1905 cpu
= cpu_flags_and (x
, cpu
);
1906 if (!cpu_flags_all_zero (&cpu
))
1908 if (x
.bitfield
.cpuavx
)
1910 /* We need to check a few extra flags with AVX. */
1911 if (cpu
.bitfield
.cpuavx
1912 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1913 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1914 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1915 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1916 match
|= CPU_FLAGS_ARCH_MATCH
;
1918 else if (x
.bitfield
.cpuavx512f
)
1920 /* We need to check a few extra flags with AVX512F. */
1921 if (cpu
.bitfield
.cpuavx512f
1922 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1923 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1924 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1925 match
|= CPU_FLAGS_ARCH_MATCH
;
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1934 static INLINE i386_operand_type
1935 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1937 if (x
.bitfield
.class != y
.bitfield
.class)
1938 x
.bitfield
.class = ClassNone
;
1939 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1940 x
.bitfield
.instance
= InstanceNone
;
1942 switch (ARRAY_SIZE (x
.array
))
1945 x
.array
[2] &= y
.array
[2];
1948 x
.array
[1] &= y
.array
[1];
1951 x
.array
[0] &= y
.array
[0];
1959 static INLINE i386_operand_type
1960 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1962 gas_assert (y
.bitfield
.class == ClassNone
);
1963 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1965 switch (ARRAY_SIZE (x
.array
))
1968 x
.array
[2] &= ~y
.array
[2];
1971 x
.array
[1] &= ~y
.array
[1];
1974 x
.array
[0] &= ~y
.array
[0];
1982 static INLINE i386_operand_type
1983 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1985 gas_assert (x
.bitfield
.class == ClassNone
||
1986 y
.bitfield
.class == ClassNone
||
1987 x
.bitfield
.class == y
.bitfield
.class);
1988 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1989 y
.bitfield
.instance
== InstanceNone
||
1990 x
.bitfield
.instance
== y
.bitfield
.instance
);
1992 switch (ARRAY_SIZE (x
.array
))
1995 x
.array
[2] |= y
.array
[2];
1998 x
.array
[1] |= y
.array
[1];
2001 x
.array
[0] |= y
.array
[0];
2009 static INLINE i386_operand_type
2010 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2012 gas_assert (y
.bitfield
.class == ClassNone
);
2013 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2015 switch (ARRAY_SIZE (x
.array
))
2018 x
.array
[2] ^= y
.array
[2];
2021 x
.array
[1] ^= y
.array
[1];
2024 x
.array
[0] ^= y
.array
[0];
2032 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2033 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2034 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2035 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2036 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2037 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2038 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2039 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2040 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2041 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2042 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2043 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2044 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2045 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2046 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2047 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2048 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2059 operand_type_check (i386_operand_type t
, enum operand_type c
)
2064 return t
.bitfield
.class == Reg
;
2067 return (t
.bitfield
.imm8
2071 || t
.bitfield
.imm32s
2072 || t
.bitfield
.imm64
);
2075 return (t
.bitfield
.disp8
2076 || t
.bitfield
.disp16
2077 || t
.bitfield
.disp32
2078 || t
.bitfield
.disp32s
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp32s
2086 || t
.bitfield
.disp64
2087 || t
.bitfield
.baseindex
);
2096 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2097 between operand GIVEN and opeand WANTED for instruction template T. */
2100 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2103 return !((i
.types
[given
].bitfield
.byte
2104 && !t
->operand_types
[wanted
].bitfield
.byte
)
2105 || (i
.types
[given
].bitfield
.word
2106 && !t
->operand_types
[wanted
].bitfield
.word
)
2107 || (i
.types
[given
].bitfield
.dword
2108 && !t
->operand_types
[wanted
].bitfield
.dword
)
2109 || (i
.types
[given
].bitfield
.qword
2110 && !t
->operand_types
[wanted
].bitfield
.qword
)
2111 || (i
.types
[given
].bitfield
.tbyte
2112 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2115 /* Return 1 if there is no conflict in SIMD register between operand
2116 GIVEN and opeand WANTED for instruction template T. */
2119 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2122 return !((i
.types
[given
].bitfield
.xmmword
2123 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2124 || (i
.types
[given
].bitfield
.ymmword
2125 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2126 || (i
.types
[given
].bitfield
.zmmword
2127 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2130 /* Return 1 if there is no conflict in any size between operand GIVEN
2131 and opeand WANTED for instruction template T. */
2134 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2137 return (match_operand_size (t
, wanted
, given
)
2138 && !((i
.types
[given
].bitfield
.unspecified
2140 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2141 || (i
.types
[given
].bitfield
.fword
2142 && !t
->operand_types
[wanted
].bitfield
.fword
)
2143 /* For scalar opcode templates to allow register and memory
2144 operands at the same time, some special casing is needed
2145 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2146 down-conversion vpmov*. */
2147 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2148 && !t
->opcode_modifier
.broadcast
2149 && (t
->operand_types
[wanted
].bitfield
.byte
2150 || t
->operand_types
[wanted
].bitfield
.word
2151 || t
->operand_types
[wanted
].bitfield
.dword
2152 || t
->operand_types
[wanted
].bitfield
.qword
))
2153 ? (i
.types
[given
].bitfield
.xmmword
2154 || i
.types
[given
].bitfield
.ymmword
2155 || i
.types
[given
].bitfield
.zmmword
)
2156 : !match_simd_size(t
, wanted
, given
))));
2159 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2160 operands for instruction template T, and it has MATCH_REVERSE set if there
2161 is no size conflict on any operands for the template with operands reversed
2162 (and the template allows for reversing in the first place). */
2164 #define MATCH_STRAIGHT 1
2165 #define MATCH_REVERSE 2
2167 static INLINE
unsigned int
2168 operand_size_match (const insn_template
*t
)
2170 unsigned int j
, match
= MATCH_STRAIGHT
;
2172 /* Don't check non-absolute jump instructions. */
2173 if (t
->opcode_modifier
.jump
2174 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2177 /* Check memory and accumulator operand size. */
2178 for (j
= 0; j
< i
.operands
; j
++)
2180 if (i
.types
[j
].bitfield
.class != Reg
2181 && i
.types
[j
].bitfield
.class != RegSIMD
2182 && t
->opcode_modifier
.anysize
)
2185 if (t
->operand_types
[j
].bitfield
.class == Reg
2186 && !match_operand_size (t
, j
, j
))
2192 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2193 && !match_simd_size (t
, j
, j
))
2199 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2200 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2206 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2213 if (!t
->opcode_modifier
.d
)
2217 i
.error
= operand_size_mismatch
;
2221 /* Check reverse. */
2222 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2224 for (j
= 0; j
< i
.operands
; j
++)
2226 unsigned int given
= i
.operands
- j
- 1;
2228 if (t
->operand_types
[j
].bitfield
.class == Reg
2229 && !match_operand_size (t
, j
, given
))
2232 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2233 && !match_simd_size (t
, j
, given
))
2236 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2237 && (!match_operand_size (t
, j
, given
)
2238 || !match_simd_size (t
, j
, given
)))
2241 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2245 return match
| MATCH_REVERSE
;
2249 operand_type_match (i386_operand_type overlap
,
2250 i386_operand_type given
)
2252 i386_operand_type temp
= overlap
;
2254 temp
.bitfield
.unspecified
= 0;
2255 temp
.bitfield
.byte
= 0;
2256 temp
.bitfield
.word
= 0;
2257 temp
.bitfield
.dword
= 0;
2258 temp
.bitfield
.fword
= 0;
2259 temp
.bitfield
.qword
= 0;
2260 temp
.bitfield
.tbyte
= 0;
2261 temp
.bitfield
.xmmword
= 0;
2262 temp
.bitfield
.ymmword
= 0;
2263 temp
.bitfield
.zmmword
= 0;
2264 if (operand_type_all_zero (&temp
))
2267 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2271 i
.error
= operand_type_mismatch
;
2275 /* If given types g0 and g1 are registers they must be of the same type
2276 unless the expected operand type register overlap is null.
2277 Some Intel syntax memory operand size checking also happens here. */
2280 operand_type_register_match (i386_operand_type g0
,
2281 i386_operand_type t0
,
2282 i386_operand_type g1
,
2283 i386_operand_type t1
)
2285 if (g0
.bitfield
.class != Reg
2286 && g0
.bitfield
.class != RegSIMD
2287 && (!operand_type_check (g0
, anymem
)
2288 || g0
.bitfield
.unspecified
2289 || (t0
.bitfield
.class != Reg
2290 && t0
.bitfield
.class != RegSIMD
)))
2293 if (g1
.bitfield
.class != Reg
2294 && g1
.bitfield
.class != RegSIMD
2295 && (!operand_type_check (g1
, anymem
)
2296 || g1
.bitfield
.unspecified
2297 || (t1
.bitfield
.class != Reg
2298 && t1
.bitfield
.class != RegSIMD
)))
2301 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2302 && g0
.bitfield
.word
== g1
.bitfield
.word
2303 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2304 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2305 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2306 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2307 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2310 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2311 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2312 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2313 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2314 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2315 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2316 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2319 i
.error
= register_type_mismatch
;
2324 static INLINE
unsigned int
2325 register_number (const reg_entry
*r
)
2327 unsigned int nr
= r
->reg_num
;
2329 if (r
->reg_flags
& RegRex
)
2332 if (r
->reg_flags
& RegVRex
)
2338 static INLINE
unsigned int
2339 mode_from_disp_size (i386_operand_type t
)
2341 if (t
.bitfield
.disp8
)
2343 else if (t
.bitfield
.disp16
2344 || t
.bitfield
.disp32
2345 || t
.bitfield
.disp32s
)
2352 fits_in_signed_byte (addressT num
)
2354 return num
+ 0x80 <= 0xff;
2358 fits_in_unsigned_byte (addressT num
)
2364 fits_in_unsigned_word (addressT num
)
2366 return num
<= 0xffff;
2370 fits_in_signed_word (addressT num
)
2372 return num
+ 0x8000 <= 0xffff;
2376 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2381 return num
+ 0x80000000 <= 0xffffffff;
2383 } /* fits_in_signed_long() */
2386 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2391 return num
<= 0xffffffff;
2393 } /* fits_in_unsigned_long() */
2396 fits_in_disp8 (offsetT num
)
2398 int shift
= i
.memshift
;
2404 mask
= (1 << shift
) - 1;
2406 /* Return 0 if NUM isn't properly aligned. */
2410 /* Check if NUM will fit in 8bit after shift. */
2411 return fits_in_signed_byte (num
>> shift
);
2415 fits_in_imm4 (offsetT num
)
2417 return (num
& 0xf) == num
;
2420 static i386_operand_type
2421 smallest_imm_type (offsetT num
)
2423 i386_operand_type t
;
2425 operand_type_set (&t
, 0);
2426 t
.bitfield
.imm64
= 1;
2428 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2430 /* This code is disabled on the 486 because all the Imm1 forms
2431 in the opcode table are slower on the i486. They're the
2432 versions with the implicitly specified single-position
2433 displacement, which has another syntax if you really want to
2435 t
.bitfield
.imm1
= 1;
2436 t
.bitfield
.imm8
= 1;
2437 t
.bitfield
.imm8s
= 1;
2438 t
.bitfield
.imm16
= 1;
2439 t
.bitfield
.imm32
= 1;
2440 t
.bitfield
.imm32s
= 1;
2442 else if (fits_in_signed_byte (num
))
2444 t
.bitfield
.imm8
= 1;
2445 t
.bitfield
.imm8s
= 1;
2446 t
.bitfield
.imm16
= 1;
2447 t
.bitfield
.imm32
= 1;
2448 t
.bitfield
.imm32s
= 1;
2450 else if (fits_in_unsigned_byte (num
))
2452 t
.bitfield
.imm8
= 1;
2453 t
.bitfield
.imm16
= 1;
2454 t
.bitfield
.imm32
= 1;
2455 t
.bitfield
.imm32s
= 1;
2457 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2459 t
.bitfield
.imm16
= 1;
2460 t
.bitfield
.imm32
= 1;
2461 t
.bitfield
.imm32s
= 1;
2463 else if (fits_in_signed_long (num
))
2465 t
.bitfield
.imm32
= 1;
2466 t
.bitfield
.imm32s
= 1;
2468 else if (fits_in_unsigned_long (num
))
2469 t
.bitfield
.imm32
= 1;
2475 offset_in_range (offsetT val
, int size
)
2481 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2482 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2483 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2485 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2491 /* If BFD64, sign extend val for 32bit address mode. */
2492 if (flag_code
!= CODE_64BIT
2493 || i
.prefix
[ADDR_PREFIX
])
2494 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2495 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2498 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2500 char buf1
[40], buf2
[40];
2502 sprint_value (buf1
, val
);
2503 sprint_value (buf2
, val
& mask
);
2504 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2519 a. PREFIX_EXIST if attempting to add a prefix where one from the
2520 same class already exists.
2521 b. PREFIX_LOCK if lock prefix is added.
2522 c. PREFIX_REP if rep/repne prefix is added.
2523 d. PREFIX_DS if ds prefix is added.
2524 e. PREFIX_OTHER if other prefix is added.
2527 static enum PREFIX_GROUP
2528 add_prefix (unsigned int prefix
)
2530 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2533 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2534 && flag_code
== CODE_64BIT
)
2536 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2537 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2538 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2539 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2550 case DS_PREFIX_OPCODE
:
2553 case CS_PREFIX_OPCODE
:
2554 case ES_PREFIX_OPCODE
:
2555 case FS_PREFIX_OPCODE
:
2556 case GS_PREFIX_OPCODE
:
2557 case SS_PREFIX_OPCODE
:
2561 case REPNE_PREFIX_OPCODE
:
2562 case REPE_PREFIX_OPCODE
:
2567 case LOCK_PREFIX_OPCODE
:
2576 case ADDR_PREFIX_OPCODE
:
2580 case DATA_PREFIX_OPCODE
:
2584 if (i
.prefix
[q
] != 0)
2592 i
.prefix
[q
] |= prefix
;
2595 as_bad (_("same type of prefix used twice"));
2601 update_code_flag (int value
, int check
)
2603 PRINTF_LIKE ((*as_error
));
2605 flag_code
= (enum flag_code
) value
;
2606 if (flag_code
== CODE_64BIT
)
2608 cpu_arch_flags
.bitfield
.cpu64
= 1;
2609 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2613 cpu_arch_flags
.bitfield
.cpu64
= 0;
2614 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2616 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2619 as_error
= as_fatal
;
2622 (*as_error
) (_("64bit mode not supported on `%s'."),
2623 cpu_arch_name
? cpu_arch_name
: default_arch
);
2625 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2628 as_error
= as_fatal
;
2631 (*as_error
) (_("32bit mode not supported on `%s'."),
2632 cpu_arch_name
? cpu_arch_name
: default_arch
);
2634 stackop_size
= '\0';
2638 set_code_flag (int value
)
2640 update_code_flag (value
, 0);
2644 set_16bit_gcc_code_flag (int new_code_flag
)
2646 flag_code
= (enum flag_code
) new_code_flag
;
2647 if (flag_code
!= CODE_16BIT
)
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 stackop_size
= LONG_MNEM_SUFFIX
;
2655 set_intel_syntax (int syntax_flag
)
2657 /* Find out if register prefixing is specified. */
2658 int ask_naked_reg
= 0;
2661 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2664 int e
= get_symbol_name (&string
);
2666 if (strcmp (string
, "prefix") == 0)
2668 else if (strcmp (string
, "noprefix") == 0)
2671 as_bad (_("bad argument to syntax directive."));
2672 (void) restore_line_pointer (e
);
2674 demand_empty_rest_of_line ();
2676 intel_syntax
= syntax_flag
;
2678 if (ask_naked_reg
== 0)
2679 allow_naked_reg
= (intel_syntax
2680 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2682 allow_naked_reg
= (ask_naked_reg
< 0);
2684 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2686 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2687 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2688 register_prefix
= allow_naked_reg
? "" : "%";
2692 set_intel_mnemonic (int mnemonic_flag
)
2694 intel_mnemonic
= mnemonic_flag
;
2698 set_allow_index_reg (int flag
)
2700 allow_index_reg
= flag
;
2704 set_check (int what
)
2706 enum check_kind
*kind
;
2711 kind
= &operand_check
;
2722 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2725 int e
= get_symbol_name (&string
);
2727 if (strcmp (string
, "none") == 0)
2729 else if (strcmp (string
, "warning") == 0)
2730 *kind
= check_warning
;
2731 else if (strcmp (string
, "error") == 0)
2732 *kind
= check_error
;
2734 as_bad (_("bad argument to %s_check directive."), str
);
2735 (void) restore_line_pointer (e
);
2738 as_bad (_("missing argument for %s_check directive"), str
);
2740 demand_empty_rest_of_line ();
2744 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2745 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2747 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2748 static const char *arch
;
2750 /* Intel LIOM is only supported on ELF. */
2756 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2757 use default_arch. */
2758 arch
= cpu_arch_name
;
2760 arch
= default_arch
;
2763 /* If we are targeting Intel MCU, we must enable it. */
2764 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2765 || new_flag
.bitfield
.cpuiamcu
)
2768 /* If we are targeting Intel L1OM, we must enable it. */
2769 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2770 || new_flag
.bitfield
.cpul1om
)
2773 /* If we are targeting Intel K1OM, we must enable it. */
2774 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2775 || new_flag
.bitfield
.cpuk1om
)
2778 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2783 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2787 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2790 int e
= get_symbol_name (&string
);
2792 i386_cpu_flags flags
;
2794 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2796 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2798 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2802 cpu_arch_name
= cpu_arch
[j
].name
;
2803 cpu_sub_arch_name
= NULL
;
2804 cpu_arch_flags
= cpu_arch
[j
].flags
;
2805 if (flag_code
== CODE_64BIT
)
2807 cpu_arch_flags
.bitfield
.cpu64
= 1;
2808 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2812 cpu_arch_flags
.bitfield
.cpu64
= 0;
2813 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2815 cpu_arch_isa
= cpu_arch
[j
].type
;
2816 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2817 if (!cpu_arch_tune_set
)
2819 cpu_arch_tune
= cpu_arch_isa
;
2820 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2825 flags
= cpu_flags_or (cpu_arch_flags
,
2828 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2830 if (cpu_sub_arch_name
)
2832 char *name
= cpu_sub_arch_name
;
2833 cpu_sub_arch_name
= concat (name
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2845 = cpu_flags_or (cpu_arch_isa_flags
,
2847 (void) restore_line_pointer (e
);
2848 demand_empty_rest_of_line ();
2853 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2855 /* Disable an ISA extension. */
2856 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2857 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2859 flags
= cpu_flags_and_not (cpu_arch_flags
,
2860 cpu_noarch
[j
].flags
);
2861 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2863 if (cpu_sub_arch_name
)
2865 char *name
= cpu_sub_arch_name
;
2866 cpu_sub_arch_name
= concat (name
, string
,
2867 (const char *) NULL
);
2871 cpu_sub_arch_name
= xstrdup (string
);
2872 cpu_arch_flags
= flags
;
2873 cpu_arch_isa_flags
= flags
;
2875 (void) restore_line_pointer (e
);
2876 demand_empty_rest_of_line ();
2880 j
= ARRAY_SIZE (cpu_arch
);
2883 if (j
>= ARRAY_SIZE (cpu_arch
))
2884 as_bad (_("no such architecture: `%s'"), string
);
2886 *input_line_pointer
= e
;
2889 as_bad (_("missing cpu architecture"));
2891 no_cond_jump_promotion
= 0;
2892 if (*input_line_pointer
== ','
2893 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2898 ++input_line_pointer
;
2899 e
= get_symbol_name (&string
);
2901 if (strcmp (string
, "nojumps") == 0)
2902 no_cond_jump_promotion
= 1;
2903 else if (strcmp (string
, "jumps") == 0)
2906 as_bad (_("no such architecture modifier: `%s'"), string
);
2908 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2914 enum bfd_architecture
2917 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2919 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2920 || flag_code
!= CODE_64BIT
)
2921 as_fatal (_("Intel L1OM is 64bit ELF only"));
2922 return bfd_arch_l1om
;
2924 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2926 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2927 || flag_code
!= CODE_64BIT
)
2928 as_fatal (_("Intel K1OM is 64bit ELF only"));
2929 return bfd_arch_k1om
;
2931 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2933 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2934 || flag_code
== CODE_64BIT
)
2935 as_fatal (_("Intel MCU is 32bit ELF only"));
2936 return bfd_arch_iamcu
;
2939 return bfd_arch_i386
;
2945 if (!strncmp (default_arch
, "x86_64", 6))
2947 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2949 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2950 || default_arch
[6] != '\0')
2951 as_fatal (_("Intel L1OM is 64bit ELF only"));
2952 return bfd_mach_l1om
;
2954 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2956 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2957 || default_arch
[6] != '\0')
2958 as_fatal (_("Intel K1OM is 64bit ELF only"));
2959 return bfd_mach_k1om
;
2961 else if (default_arch
[6] == '\0')
2962 return bfd_mach_x86_64
;
2964 return bfd_mach_x64_32
;
2966 else if (!strcmp (default_arch
, "i386")
2967 || !strcmp (default_arch
, "iamcu"))
2969 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2971 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2972 as_fatal (_("Intel MCU is 32bit ELF only"));
2973 return bfd_mach_i386_iamcu
;
2976 return bfd_mach_i386_i386
;
2979 as_fatal (_("unknown architecture"));
2985 const char *hash_err
;
2987 /* Support pseudo prefixes like {disp32}. */
2988 lex_type
['{'] = LEX_BEGIN_NAME
;
2990 /* Initialize op_hash hash table. */
2991 op_hash
= hash_new ();
2994 const insn_template
*optab
;
2995 templates
*core_optab
;
2997 /* Setup for loop. */
2999 core_optab
= XNEW (templates
);
3000 core_optab
->start
= optab
;
3005 if (optab
->name
== NULL
3006 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3008 /* different name --> ship out current template list;
3009 add to hash table; & begin anew. */
3010 core_optab
->end
= optab
;
3011 hash_err
= hash_insert (op_hash
,
3013 (void *) core_optab
);
3016 as_fatal (_("can't hash %s: %s"),
3020 if (optab
->name
== NULL
)
3022 core_optab
= XNEW (templates
);
3023 core_optab
->start
= optab
;
3028 /* Initialize reg_hash hash table. */
3029 reg_hash
= hash_new ();
3031 const reg_entry
*regtab
;
3032 unsigned int regtab_size
= i386_regtab_size
;
3034 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3036 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3038 as_fatal (_("can't hash %s: %s"),
3044 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3049 for (c
= 0; c
< 256; c
++)
3054 mnemonic_chars
[c
] = c
;
3055 register_chars
[c
] = c
;
3056 operand_chars
[c
] = c
;
3058 else if (ISLOWER (c
))
3060 mnemonic_chars
[c
] = c
;
3061 register_chars
[c
] = c
;
3062 operand_chars
[c
] = c
;
3064 else if (ISUPPER (c
))
3066 mnemonic_chars
[c
] = TOLOWER (c
);
3067 register_chars
[c
] = mnemonic_chars
[c
];
3068 operand_chars
[c
] = c
;
3070 else if (c
== '{' || c
== '}')
3072 mnemonic_chars
[c
] = c
;
3073 operand_chars
[c
] = c
;
3076 if (ISALPHA (c
) || ISDIGIT (c
))
3077 identifier_chars
[c
] = c
;
3080 identifier_chars
[c
] = c
;
3081 operand_chars
[c
] = c
;
3086 identifier_chars
['@'] = '@';
3089 identifier_chars
['?'] = '?';
3090 operand_chars
['?'] = '?';
3092 digit_chars
['-'] = '-';
3093 mnemonic_chars
['_'] = '_';
3094 mnemonic_chars
['-'] = '-';
3095 mnemonic_chars
['.'] = '.';
3096 identifier_chars
['_'] = '_';
3097 identifier_chars
['.'] = '.';
3099 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3100 operand_chars
[(unsigned char) *p
] = *p
;
3103 if (flag_code
== CODE_64BIT
)
3105 #if defined (OBJ_COFF) && defined (TE_PE)
3106 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3109 x86_dwarf2_return_column
= 16;
3111 x86_cie_data_alignment
= -8;
3115 x86_dwarf2_return_column
= 8;
3116 x86_cie_data_alignment
= -4;
3119 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3120 can be turned into BRANCH_PREFIX frag. */
3121 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3126 i386_print_statistics (FILE *file
)
3128 hash_print_statistics (file
, "i386 opcode", op_hash
);
3129 hash_print_statistics (file
, "i386 register", reg_hash
);
3134 /* Debugging routines for md_assemble. */
3135 static void pte (insn_template
*);
3136 static void pt (i386_operand_type
);
3137 static void pe (expressionS
*);
3138 static void ps (symbolS
*);
3141 pi (const char *line
, i386_insn
*x
)
3145 fprintf (stdout
, "%s: template ", line
);
3147 fprintf (stdout
, " address: base %s index %s scale %x\n",
3148 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3149 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3150 x
->log2_scale_factor
);
3151 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3152 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3153 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3154 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3155 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3156 (x
->rex
& REX_W
) != 0,
3157 (x
->rex
& REX_R
) != 0,
3158 (x
->rex
& REX_X
) != 0,
3159 (x
->rex
& REX_B
) != 0);
3160 for (j
= 0; j
< x
->operands
; j
++)
3162 fprintf (stdout
, " #%d: ", j
+ 1);
3164 fprintf (stdout
, "\n");
3165 if (x
->types
[j
].bitfield
.class == Reg
3166 || x
->types
[j
].bitfield
.class == RegMMX
3167 || x
->types
[j
].bitfield
.class == RegSIMD
3168 || x
->types
[j
].bitfield
.class == SReg
3169 || x
->types
[j
].bitfield
.class == RegCR
3170 || x
->types
[j
].bitfield
.class == RegDR
3171 || x
->types
[j
].bitfield
.class == RegTR
)
3172 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3173 if (operand_type_check (x
->types
[j
], imm
))
3175 if (operand_type_check (x
->types
[j
], disp
))
3176 pe (x
->op
[j
].disps
);
3181 pte (insn_template
*t
)
3184 fprintf (stdout
, " %d operands ", t
->operands
);
3185 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3186 if (t
->extension_opcode
!= None
)
3187 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3188 if (t
->opcode_modifier
.d
)
3189 fprintf (stdout
, "D");
3190 if (t
->opcode_modifier
.w
)
3191 fprintf (stdout
, "W");
3192 fprintf (stdout
, "\n");
3193 for (j
= 0; j
< t
->operands
; j
++)
3195 fprintf (stdout
, " #%d type ", j
+ 1);
3196 pt (t
->operand_types
[j
]);
3197 fprintf (stdout
, "\n");
3204 fprintf (stdout
, " operation %d\n", e
->X_op
);
3205 fprintf (stdout
, " add_number %ld (%lx)\n",
3206 (long) e
->X_add_number
, (long) e
->X_add_number
);
3207 if (e
->X_add_symbol
)
3209 fprintf (stdout
, " add_symbol ");
3210 ps (e
->X_add_symbol
);
3211 fprintf (stdout
, "\n");
3215 fprintf (stdout
, " op_symbol ");
3216 ps (e
->X_op_symbol
);
3217 fprintf (stdout
, "\n");
3224 fprintf (stdout
, "%s type %s%s",
3226 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3227 segment_name (S_GET_SEGMENT (s
)));
3230 static struct type_name
3232 i386_operand_type mask
;
3235 const type_names
[] =
3237 { OPERAND_TYPE_REG8
, "r8" },
3238 { OPERAND_TYPE_REG16
, "r16" },
3239 { OPERAND_TYPE_REG32
, "r32" },
3240 { OPERAND_TYPE_REG64
, "r64" },
3241 { OPERAND_TYPE_ACC8
, "acc8" },
3242 { OPERAND_TYPE_ACC16
, "acc16" },
3243 { OPERAND_TYPE_ACC32
, "acc32" },
3244 { OPERAND_TYPE_ACC64
, "acc64" },
3245 { OPERAND_TYPE_IMM8
, "i8" },
3246 { OPERAND_TYPE_IMM8
, "i8s" },
3247 { OPERAND_TYPE_IMM16
, "i16" },
3248 { OPERAND_TYPE_IMM32
, "i32" },
3249 { OPERAND_TYPE_IMM32S
, "i32s" },
3250 { OPERAND_TYPE_IMM64
, "i64" },
3251 { OPERAND_TYPE_IMM1
, "i1" },
3252 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3253 { OPERAND_TYPE_DISP8
, "d8" },
3254 { OPERAND_TYPE_DISP16
, "d16" },
3255 { OPERAND_TYPE_DISP32
, "d32" },
3256 { OPERAND_TYPE_DISP32S
, "d32s" },
3257 { OPERAND_TYPE_DISP64
, "d64" },
3258 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3259 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3260 { OPERAND_TYPE_CONTROL
, "control reg" },
3261 { OPERAND_TYPE_TEST
, "test reg" },
3262 { OPERAND_TYPE_DEBUG
, "debug reg" },
3263 { OPERAND_TYPE_FLOATREG
, "FReg" },
3264 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3265 { OPERAND_TYPE_SREG
, "SReg" },
3266 { OPERAND_TYPE_REGMMX
, "rMMX" },
3267 { OPERAND_TYPE_REGXMM
, "rXMM" },
3268 { OPERAND_TYPE_REGYMM
, "rYMM" },
3269 { OPERAND_TYPE_REGZMM
, "rZMM" },
3270 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3274 pt (i386_operand_type t
)
3277 i386_operand_type a
;
3279 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3281 a
= operand_type_and (t
, type_names
[j
].mask
);
3282 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3283 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3288 #endif /* DEBUG386 */
3290 static bfd_reloc_code_real_type
3291 reloc (unsigned int size
,
3294 bfd_reloc_code_real_type other
)
3296 if (other
!= NO_RELOC
)
3298 reloc_howto_type
*rel
;
3303 case BFD_RELOC_X86_64_GOT32
:
3304 return BFD_RELOC_X86_64_GOT64
;
3306 case BFD_RELOC_X86_64_GOTPLT64
:
3307 return BFD_RELOC_X86_64_GOTPLT64
;
3309 case BFD_RELOC_X86_64_PLTOFF64
:
3310 return BFD_RELOC_X86_64_PLTOFF64
;
3312 case BFD_RELOC_X86_64_GOTPC32
:
3313 other
= BFD_RELOC_X86_64_GOTPC64
;
3315 case BFD_RELOC_X86_64_GOTPCREL
:
3316 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3318 case BFD_RELOC_X86_64_TPOFF32
:
3319 other
= BFD_RELOC_X86_64_TPOFF64
;
3321 case BFD_RELOC_X86_64_DTPOFF32
:
3322 other
= BFD_RELOC_X86_64_DTPOFF64
;
3328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3329 if (other
== BFD_RELOC_SIZE32
)
3332 other
= BFD_RELOC_SIZE64
;
3335 as_bad (_("there are no pc-relative size relocations"));
3341 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3342 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3345 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3347 as_bad (_("unknown relocation (%u)"), other
);
3348 else if (size
!= bfd_get_reloc_size (rel
))
3349 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3350 bfd_get_reloc_size (rel
),
3352 else if (pcrel
&& !rel
->pc_relative
)
3353 as_bad (_("non-pc-relative relocation for pc-relative field"));
3354 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3356 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3358 as_bad (_("relocated field and relocation type differ in signedness"));
3367 as_bad (_("there are no unsigned pc-relative relocations"));
3370 case 1: return BFD_RELOC_8_PCREL
;
3371 case 2: return BFD_RELOC_16_PCREL
;
3372 case 4: return BFD_RELOC_32_PCREL
;
3373 case 8: return BFD_RELOC_64_PCREL
;
3375 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3382 case 4: return BFD_RELOC_X86_64_32S
;
3387 case 1: return BFD_RELOC_8
;
3388 case 2: return BFD_RELOC_16
;
3389 case 4: return BFD_RELOC_32
;
3390 case 8: return BFD_RELOC_64
;
3392 as_bad (_("cannot do %s %u byte relocation"),
3393 sign
> 0 ? "signed" : "unsigned", size
);
3399 /* Here we decide which fixups can be adjusted to make them relative to
3400 the beginning of the section instead of the symbol. Basically we need
3401 to make sure that the dynamic relocations are done correctly, so in
3402 some cases we force the original symbol to be used. */
3405 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3411 /* Don't adjust pc-relative references to merge sections in 64-bit
3413 if (use_rela_relocations
3414 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3418 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3419 and changed later by validate_fix. */
3420 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3421 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3424 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3425 for size relocations. */
3426 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3427 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3428 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3429 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3430 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3431 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3432 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3433 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3434 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3435 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3436 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3437 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3438 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3439 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3440 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3441 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3442 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3443 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3444 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3445 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3446 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3447 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3448 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3449 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3455 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3456 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3463 intel_float_operand (const char *mnemonic
)
3465 /* Note that the value returned is meaningful only for opcodes with (memory)
3466 operands, hence the code here is free to improperly handle opcodes that
3467 have no operands (for better performance and smaller code). */
3469 if (mnemonic
[0] != 'f')
3470 return 0; /* non-math */
3472 switch (mnemonic
[1])
3474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3475 the fs segment override prefix not currently handled because no
3476 call path can make opcodes without operands get here */
3478 return 2 /* integer op */;
3480 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3481 return 3; /* fldcw/fldenv */
3484 if (mnemonic
[2] != 'o' /* fnop */)
3485 return 3; /* non-waiting control op */
3488 if (mnemonic
[2] == 's')
3489 return 3; /* frstor/frstpm */
3492 if (mnemonic
[2] == 'a')
3493 return 3; /* fsave */
3494 if (mnemonic
[2] == 't')
3496 switch (mnemonic
[3])
3498 case 'c': /* fstcw */
3499 case 'd': /* fstdw */
3500 case 'e': /* fstenv */
3501 case 's': /* fsts[gw] */
3507 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3508 return 0; /* fxsave/fxrstor are not really math ops */
3515 /* Build the VEX prefix. */
3518 build_vex_prefix (const insn_template
*t
)
3520 unsigned int register_specifier
;
3521 unsigned int implied_prefix
;
3522 unsigned int vector_length
;
3525 /* Check register specifier. */
3526 if (i
.vex
.register_specifier
)
3528 register_specifier
=
3529 ~register_number (i
.vex
.register_specifier
) & 0xf;
3530 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3533 register_specifier
= 0xf;
3535 /* Use 2-byte VEX prefix by swapping destination and source operand
3536 if there are more than 1 register operand. */
3537 if (i
.reg_operands
> 1
3538 && i
.vec_encoding
!= vex_encoding_vex3
3539 && i
.dir_encoding
== dir_encoding_default
3540 && i
.operands
== i
.reg_operands
3541 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3542 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3543 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3546 unsigned int xchg
= i
.operands
- 1;
3547 union i386_op temp_op
;
3548 i386_operand_type temp_type
;
3550 temp_type
= i
.types
[xchg
];
3551 i
.types
[xchg
] = i
.types
[0];
3552 i
.types
[0] = temp_type
;
3553 temp_op
= i
.op
[xchg
];
3554 i
.op
[xchg
] = i
.op
[0];
3557 gas_assert (i
.rm
.mode
== 3);
3561 i
.rm
.regmem
= i
.rm
.reg
;
3564 if (i
.tm
.opcode_modifier
.d
)
3565 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3566 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3567 else /* Use the next insn. */
3571 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3572 are no memory operands and at least 3 register ones. */
3573 if (i
.reg_operands
>= 3
3574 && i
.vec_encoding
!= vex_encoding_vex3
3575 && i
.reg_operands
== i
.operands
- i
.imm_operands
3576 && i
.tm
.opcode_modifier
.vex
3577 && i
.tm
.opcode_modifier
.commutative
3578 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3580 && i
.vex
.register_specifier
3581 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3583 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3588 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3589 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3590 &i
.types
[i
.operands
- 3]));
3591 gas_assert (i
.rm
.mode
== 3);
3593 temp_type
= i
.types
[xchg
];
3594 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3595 i
.types
[xchg
+ 1] = temp_type
;
3596 temp_op
= i
.op
[xchg
];
3597 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3598 i
.op
[xchg
+ 1] = temp_op
;
3601 xchg
= i
.rm
.regmem
| 8;
3602 i
.rm
.regmem
= ~register_specifier
& 0xf;
3603 gas_assert (!(i
.rm
.regmem
& 8));
3604 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3605 register_specifier
= ~xchg
& 0xf;
3608 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3609 vector_length
= avxscalar
;
3610 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3616 /* Determine vector length from the last multi-length vector
3619 for (op
= t
->operands
; op
--;)
3620 if (t
->operand_types
[op
].bitfield
.xmmword
3621 && t
->operand_types
[op
].bitfield
.ymmword
3622 && i
.types
[op
].bitfield
.ymmword
)
3629 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3634 case DATA_PREFIX_OPCODE
:
3637 case REPE_PREFIX_OPCODE
:
3640 case REPNE_PREFIX_OPCODE
:
3647 /* Check the REX.W bit and VEXW. */
3648 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3649 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3650 else if (i
.tm
.opcode_modifier
.vexw
)
3651 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3653 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3655 /* Use 2-byte VEX prefix if possible. */
3657 && i
.vec_encoding
!= vex_encoding_vex3
3658 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3659 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3661 /* 2-byte VEX prefix. */
3665 i
.vex
.bytes
[0] = 0xc5;
3667 /* Check the REX.R bit. */
3668 r
= (i
.rex
& REX_R
) ? 0 : 1;
3669 i
.vex
.bytes
[1] = (r
<< 7
3670 | register_specifier
<< 3
3671 | vector_length
<< 2
3676 /* 3-byte VEX prefix. */
3681 switch (i
.tm
.opcode_modifier
.vexopcode
)
3685 i
.vex
.bytes
[0] = 0xc4;
3689 i
.vex
.bytes
[0] = 0xc4;
3693 i
.vex
.bytes
[0] = 0xc4;
3697 i
.vex
.bytes
[0] = 0x8f;
3701 i
.vex
.bytes
[0] = 0x8f;
3705 i
.vex
.bytes
[0] = 0x8f;
3711 /* The high 3 bits of the second VEX byte are 1's compliment
3712 of RXB bits from REX. */
3713 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3715 i
.vex
.bytes
[2] = (w
<< 7
3716 | register_specifier
<< 3
3717 | vector_length
<< 2
3722 static INLINE bfd_boolean
3723 is_evex_encoding (const insn_template
*t
)
3725 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3726 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3727 || t
->opcode_modifier
.sae
;
3730 static INLINE bfd_boolean
3731 is_any_vex_encoding (const insn_template
*t
)
3733 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3734 || is_evex_encoding (t
);
3737 /* Build the EVEX prefix. */
3740 build_evex_prefix (void)
3742 unsigned int register_specifier
;
3743 unsigned int implied_prefix
;
3745 rex_byte vrex_used
= 0;
3747 /* Check register specifier. */
3748 if (i
.vex
.register_specifier
)
3750 gas_assert ((i
.vrex
& REX_X
) == 0);
3752 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3753 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3754 register_specifier
+= 8;
3755 /* The upper 16 registers are encoded in the fourth byte of the
3757 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3758 i
.vex
.bytes
[3] = 0x8;
3759 register_specifier
= ~register_specifier
& 0xf;
3763 register_specifier
= 0xf;
3765 /* Encode upper 16 vector index register in the fourth byte of
3767 if (!(i
.vrex
& REX_X
))
3768 i
.vex
.bytes
[3] = 0x8;
3773 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3778 case DATA_PREFIX_OPCODE
:
3781 case REPE_PREFIX_OPCODE
:
3784 case REPNE_PREFIX_OPCODE
:
3791 /* 4 byte EVEX prefix. */
3793 i
.vex
.bytes
[0] = 0x62;
3796 switch (i
.tm
.opcode_modifier
.vexopcode
)
3812 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3814 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3816 /* The fifth bit of the second EVEX byte is 1's compliment of the
3817 REX_R bit in VREX. */
3818 if (!(i
.vrex
& REX_R
))
3819 i
.vex
.bytes
[1] |= 0x10;
3823 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3825 /* When all operands are registers, the REX_X bit in REX is not
3826 used. We reuse it to encode the upper 16 registers, which is
3827 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3828 as 1's compliment. */
3829 if ((i
.vrex
& REX_B
))
3832 i
.vex
.bytes
[1] &= ~0x40;
3836 /* EVEX instructions shouldn't need the REX prefix. */
3837 i
.vrex
&= ~vrex_used
;
3838 gas_assert (i
.vrex
== 0);
3840 /* Check the REX.W bit and VEXW. */
3841 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3842 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3843 else if (i
.tm
.opcode_modifier
.vexw
)
3844 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3846 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3848 /* Encode the U bit. */
3849 implied_prefix
|= 0x4;
3851 /* The third byte of the EVEX prefix. */
3852 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3854 /* The fourth byte of the EVEX prefix. */
3855 /* The zeroing-masking bit. */
3856 if (i
.mask
&& i
.mask
->zeroing
)
3857 i
.vex
.bytes
[3] |= 0x80;
3859 /* Don't always set the broadcast bit if there is no RC. */
3862 /* Encode the vector length. */
3863 unsigned int vec_length
;
3865 if (!i
.tm
.opcode_modifier
.evex
3866 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3870 /* Determine vector length from the last multi-length vector
3873 for (op
= i
.operands
; op
--;)
3874 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3875 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3876 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3878 if (i
.types
[op
].bitfield
.zmmword
)
3880 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3883 else if (i
.types
[op
].bitfield
.ymmword
)
3885 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3888 else if (i
.types
[op
].bitfield
.xmmword
)
3890 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3893 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3895 switch (i
.broadcast
->bytes
)
3898 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3901 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3904 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3913 if (op
>= MAX_OPERANDS
)
3917 switch (i
.tm
.opcode_modifier
.evex
)
3919 case EVEXLIG
: /* LL' is ignored */
3920 vec_length
= evexlig
<< 5;
3923 vec_length
= 0 << 5;
3926 vec_length
= 1 << 5;
3929 vec_length
= 2 << 5;
3935 i
.vex
.bytes
[3] |= vec_length
;
3936 /* Encode the broadcast bit. */
3938 i
.vex
.bytes
[3] |= 0x10;
3942 if (i
.rounding
->type
!= saeonly
)
3943 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3945 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3948 if (i
.mask
&& i
.mask
->mask
)
3949 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3953 process_immext (void)
3957 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3958 which is coded in the same place as an 8-bit immediate field
3959 would be. Here we fake an 8-bit immediate operand from the
3960 opcode suffix stored in tm.extension_opcode.
3962 AVX instructions also use this encoding, for some of
3963 3 argument instructions. */
3965 gas_assert (i
.imm_operands
<= 1
3967 || (is_any_vex_encoding (&i
.tm
)
3968 && i
.operands
<= 4)));
3970 exp
= &im_expressions
[i
.imm_operands
++];
3971 i
.op
[i
.operands
].imms
= exp
;
3972 i
.types
[i
.operands
] = imm8
;
3974 exp
->X_op
= O_constant
;
3975 exp
->X_add_number
= i
.tm
.extension_opcode
;
3976 i
.tm
.extension_opcode
= None
;
3983 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3988 as_bad (_("invalid instruction `%s' after `%s'"),
3989 i
.tm
.name
, i
.hle_prefix
);
3992 if (i
.prefix
[LOCK_PREFIX
])
3994 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3998 case HLEPrefixRelease
:
3999 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4001 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4005 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4007 as_bad (_("memory destination needed for instruction `%s'"
4008 " after `xrelease'"), i
.tm
.name
);
4015 /* Try the shortest encoding by shortening operand size. */
4018 optimize_encoding (void)
4022 if (optimize_for_space
4023 && !is_any_vex_encoding (&i
.tm
)
4024 && i
.reg_operands
== 1
4025 && i
.imm_operands
== 1
4026 && !i
.types
[1].bitfield
.byte
4027 && i
.op
[0].imms
->X_op
== O_constant
4028 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4029 && (i
.tm
.base_opcode
== 0xa8
4030 || (i
.tm
.base_opcode
== 0xf6
4031 && i
.tm
.extension_opcode
== 0x0)))
4034 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4036 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4037 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4039 i
.types
[1].bitfield
.byte
= 1;
4040 /* Ignore the suffix. */
4042 /* Convert to byte registers. */
4043 if (i
.types
[1].bitfield
.word
)
4045 else if (i
.types
[1].bitfield
.dword
)
4049 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4054 else if (flag_code
== CODE_64BIT
4055 && !is_any_vex_encoding (&i
.tm
)
4056 && ((i
.types
[1].bitfield
.qword
4057 && i
.reg_operands
== 1
4058 && i
.imm_operands
== 1
4059 && i
.op
[0].imms
->X_op
== O_constant
4060 && ((i
.tm
.base_opcode
== 0xb8
4061 && i
.tm
.extension_opcode
== None
4062 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4063 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4064 && ((i
.tm
.base_opcode
== 0x24
4065 || i
.tm
.base_opcode
== 0xa8)
4066 || (i
.tm
.base_opcode
== 0x80
4067 && i
.tm
.extension_opcode
== 0x4)
4068 || ((i
.tm
.base_opcode
== 0xf6
4069 || (i
.tm
.base_opcode
| 1) == 0xc7)
4070 && i
.tm
.extension_opcode
== 0x0)))
4071 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4072 && i
.tm
.base_opcode
== 0x83
4073 && i
.tm
.extension_opcode
== 0x4)))
4074 || (i
.types
[0].bitfield
.qword
4075 && ((i
.reg_operands
== 2
4076 && i
.op
[0].regs
== i
.op
[1].regs
4077 && (i
.tm
.base_opcode
== 0x30
4078 || i
.tm
.base_opcode
== 0x28))
4079 || (i
.reg_operands
== 1
4081 && i
.tm
.base_opcode
== 0x30)))))
4084 andq $imm31, %r64 -> andl $imm31, %r32
4085 andq $imm7, %r64 -> andl $imm7, %r32
4086 testq $imm31, %r64 -> testl $imm31, %r32
4087 xorq %r64, %r64 -> xorl %r32, %r32
4088 subq %r64, %r64 -> subl %r32, %r32
4089 movq $imm31, %r64 -> movl $imm31, %r32
4090 movq $imm32, %r64 -> movl $imm32, %r32
4092 i
.tm
.opcode_modifier
.norex64
= 1;
4093 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4096 movq $imm31, %r64 -> movl $imm31, %r32
4097 movq $imm32, %r64 -> movl $imm32, %r32
4099 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4100 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4101 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4102 i
.types
[0].bitfield
.imm32
= 1;
4103 i
.types
[0].bitfield
.imm32s
= 0;
4104 i
.types
[0].bitfield
.imm64
= 0;
4105 i
.types
[1].bitfield
.dword
= 1;
4106 i
.types
[1].bitfield
.qword
= 0;
4107 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4110 movq $imm31, %r64 -> movl $imm31, %r32
4112 i
.tm
.base_opcode
= 0xb8;
4113 i
.tm
.extension_opcode
= None
;
4114 i
.tm
.opcode_modifier
.w
= 0;
4115 i
.tm
.opcode_modifier
.modrm
= 0;
4119 else if (optimize
> 1
4120 && !optimize_for_space
4121 && !is_any_vex_encoding (&i
.tm
)
4122 && i
.reg_operands
== 2
4123 && i
.op
[0].regs
== i
.op
[1].regs
4124 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4125 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4126 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4129 andb %rN, %rN -> testb %rN, %rN
4130 andw %rN, %rN -> testw %rN, %rN
4131 andq %rN, %rN -> testq %rN, %rN
4132 orb %rN, %rN -> testb %rN, %rN
4133 orw %rN, %rN -> testw %rN, %rN
4134 orq %rN, %rN -> testq %rN, %rN
4136 and outside of 64-bit mode
4138 andl %rN, %rN -> testl %rN, %rN
4139 orl %rN, %rN -> testl %rN, %rN
4141 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4143 else if (i
.reg_operands
== 3
4144 && i
.op
[0].regs
== i
.op
[1].regs
4145 && !i
.types
[2].bitfield
.xmmword
4146 && (i
.tm
.opcode_modifier
.vex
4147 || ((!i
.mask
|| i
.mask
->zeroing
)
4149 && is_evex_encoding (&i
.tm
)
4150 && (i
.vec_encoding
!= vex_encoding_evex
4151 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4152 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4153 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4154 && i
.types
[2].bitfield
.ymmword
))))
4155 && ((i
.tm
.base_opcode
== 0x55
4156 || i
.tm
.base_opcode
== 0x6655
4157 || i
.tm
.base_opcode
== 0x66df
4158 || i
.tm
.base_opcode
== 0x57
4159 || i
.tm
.base_opcode
== 0x6657
4160 || i
.tm
.base_opcode
== 0x66ef
4161 || i
.tm
.base_opcode
== 0x66f8
4162 || i
.tm
.base_opcode
== 0x66f9
4163 || i
.tm
.base_opcode
== 0x66fa
4164 || i
.tm
.base_opcode
== 0x66fb
4165 || i
.tm
.base_opcode
== 0x42
4166 || i
.tm
.base_opcode
== 0x6642
4167 || i
.tm
.base_opcode
== 0x47
4168 || i
.tm
.base_opcode
== 0x6647)
4169 && i
.tm
.extension_opcode
== None
))
4172 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4174 EVEX VOP %zmmM, %zmmM, %zmmN
4175 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4176 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4177 EVEX VOP %ymmM, %ymmM, %ymmN
4178 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4179 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4180 VEX VOP %ymmM, %ymmM, %ymmN
4181 -> VEX VOP %xmmM, %xmmM, %xmmN
4182 VOP, one of vpandn and vpxor:
4183 VEX VOP %ymmM, %ymmM, %ymmN
4184 -> VEX VOP %xmmM, %xmmM, %xmmN
4185 VOP, one of vpandnd and vpandnq:
4186 EVEX VOP %zmmM, %zmmM, %zmmN
4187 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4188 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4189 EVEX VOP %ymmM, %ymmM, %ymmN
4190 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4191 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4192 VOP, one of vpxord and vpxorq:
4193 EVEX VOP %zmmM, %zmmM, %zmmN
4194 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4195 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4196 EVEX VOP %ymmM, %ymmM, %ymmN
4197 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4198 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4199 VOP, one of kxord and kxorq:
4200 VEX VOP %kM, %kM, %kN
4201 -> VEX kxorw %kM, %kM, %kN
4202 VOP, one of kandnd and kandnq:
4203 VEX VOP %kM, %kM, %kN
4204 -> VEX kandnw %kM, %kM, %kN
4206 if (is_evex_encoding (&i
.tm
))
4208 if (i
.vec_encoding
!= vex_encoding_evex
)
4210 i
.tm
.opcode_modifier
.vex
= VEX128
;
4211 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4212 i
.tm
.opcode_modifier
.evex
= 0;
4214 else if (optimize
> 1)
4215 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4219 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4221 i
.tm
.base_opcode
&= 0xff;
4222 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4225 i
.tm
.opcode_modifier
.vex
= VEX128
;
4227 if (i
.tm
.opcode_modifier
.vex
)
4228 for (j
= 0; j
< 3; j
++)
4230 i
.types
[j
].bitfield
.xmmword
= 1;
4231 i
.types
[j
].bitfield
.ymmword
= 0;
4234 else if (i
.vec_encoding
!= vex_encoding_evex
4235 && !i
.types
[0].bitfield
.zmmword
4236 && !i
.types
[1].bitfield
.zmmword
4239 && is_evex_encoding (&i
.tm
)
4240 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4241 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4242 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4243 || (i
.tm
.base_opcode
& ~4) == 0x66db
4244 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4245 && i
.tm
.extension_opcode
== None
)
4248 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4249 vmovdqu32 and vmovdqu64:
4250 EVEX VOP %xmmM, %xmmN
4251 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4252 EVEX VOP %ymmM, %ymmN
4253 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4255 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4257 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4259 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4261 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4262 VOP, one of vpand, vpandn, vpor, vpxor:
4263 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4264 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4265 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4266 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4267 EVEX VOP{d,q} mem, %xmmM, %xmmN
4268 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4269 EVEX VOP{d,q} mem, %ymmM, %ymmN
4270 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4272 for (j
= 0; j
< i
.operands
; j
++)
4273 if (operand_type_check (i
.types
[j
], disp
)
4274 && i
.op
[j
].disps
->X_op
== O_constant
)
4276 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4277 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4278 bytes, we choose EVEX Disp8 over VEX Disp32. */
4279 int evex_disp8
, vex_disp8
;
4280 unsigned int memshift
= i
.memshift
;
4281 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4283 evex_disp8
= fits_in_disp8 (n
);
4285 vex_disp8
= fits_in_disp8 (n
);
4286 if (evex_disp8
!= vex_disp8
)
4288 i
.memshift
= memshift
;
4292 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4295 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4296 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4297 i
.tm
.opcode_modifier
.vex
4298 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4299 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4300 /* VPAND, VPOR, and VPXOR are commutative. */
4301 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4302 i
.tm
.opcode_modifier
.commutative
= 1;
4303 i
.tm
.opcode_modifier
.evex
= 0;
4304 i
.tm
.opcode_modifier
.masking
= 0;
4305 i
.tm
.opcode_modifier
.broadcast
= 0;
4306 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4309 i
.types
[j
].bitfield
.disp8
4310 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4314 /* This is the guts of the machine-dependent assembler. LINE points to a
4315 machine dependent instruction. This function is supposed to emit
4316 the frags/bytes it assembles to. */
4319 md_assemble (char *line
)
4322 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4323 const insn_template
*t
;
4325 /* Initialize globals. */
4326 memset (&i
, '\0', sizeof (i
));
4327 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4328 i
.reloc
[j
] = NO_RELOC
;
4329 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4330 memset (im_expressions
, '\0', sizeof (im_expressions
));
4331 save_stack_p
= save_stack
;
4333 /* First parse an instruction mnemonic & call i386_operand for the operands.
4334 We assume that the scrubber has arranged it so that line[0] is the valid
4335 start of a (possibly prefixed) mnemonic. */
4337 line
= parse_insn (line
, mnemonic
);
4340 mnem_suffix
= i
.suffix
;
4342 line
= parse_operands (line
, mnemonic
);
4344 xfree (i
.memop1_string
);
4345 i
.memop1_string
= NULL
;
4349 /* Now we've parsed the mnemonic into a set of templates, and have the
4350 operands at hand. */
4352 /* All Intel opcodes have reversed operands except for "bound", "enter",
4353 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4354 intersegment "jmp" and "call" instructions with 2 immediate operands so
4355 that the immediate segment precedes the offset, as it does when in AT&T
4359 && (strcmp (mnemonic
, "bound") != 0)
4360 && (strcmp (mnemonic
, "invlpga") != 0)
4361 && (strncmp (mnemonic
, "monitor", 7) != 0)
4362 && (strncmp (mnemonic
, "mwait", 5) != 0)
4363 && (strcmp (mnemonic
, "tpause") != 0)
4364 && (strcmp (mnemonic
, "umwait") != 0)
4365 && !(operand_type_check (i
.types
[0], imm
)
4366 && operand_type_check (i
.types
[1], imm
)))
4369 /* The order of the immediates should be reversed
4370 for 2 immediates extrq and insertq instructions */
4371 if (i
.imm_operands
== 2
4372 && (strcmp (mnemonic
, "extrq") == 0
4373 || strcmp (mnemonic
, "insertq") == 0))
4374 swap_2_operands (0, 1);
4379 /* Don't optimize displacement for movabs since it only takes 64bit
4382 && i
.disp_encoding
!= disp_encoding_32bit
4383 && (flag_code
!= CODE_64BIT
4384 || strcmp (mnemonic
, "movabs") != 0))
4387 /* Next, we find a template that matches the given insn,
4388 making sure the overlap of the given operands types is consistent
4389 with the template operand types. */
4391 if (!(t
= match_template (mnem_suffix
)))
4394 if (sse_check
!= check_none
4395 && !i
.tm
.opcode_modifier
.noavx
4396 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4397 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4398 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4399 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4400 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4401 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4402 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4403 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4404 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4405 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4406 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4407 || i
.tm
.cpu_flags
.bitfield
.cpusha
4408 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4410 (sse_check
== check_warning
4412 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4415 if (i
.tm
.opcode_modifier
.fwait
)
4416 if (!add_prefix (FWAIT_OPCODE
))
4419 /* Check if REP prefix is OK. */
4420 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4422 as_bad (_("invalid instruction `%s' after `%s'"),
4423 i
.tm
.name
, i
.rep_prefix
);
4427 /* Check for lock without a lockable instruction. Destination operand
4428 must be memory unless it is xchg (0x86). */
4429 if (i
.prefix
[LOCK_PREFIX
]
4430 && (!i
.tm
.opcode_modifier
.islockable
4431 || i
.mem_operands
== 0
4432 || (i
.tm
.base_opcode
!= 0x86
4433 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4435 as_bad (_("expecting lockable instruction after `lock'"));
4439 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4440 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4442 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4446 /* Check if HLE prefix is OK. */
4447 if (i
.hle_prefix
&& !check_hle ())
4450 /* Check BND prefix. */
4451 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4452 as_bad (_("expecting valid branch instruction after `bnd'"));
4454 /* Check NOTRACK prefix. */
4455 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4456 as_bad (_("expecting indirect branch instruction after `notrack'"));
4458 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4460 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4461 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4462 else if (flag_code
!= CODE_16BIT
4463 ? i
.prefix
[ADDR_PREFIX
]
4464 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4465 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4468 /* Insert BND prefix. */
4469 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4471 if (!i
.prefix
[BND_PREFIX
])
4472 add_prefix (BND_PREFIX_OPCODE
);
4473 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4475 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4476 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4480 /* Check string instruction segment overrides. */
4481 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4483 gas_assert (i
.mem_operands
);
4484 if (!check_string ())
4486 i
.disp_operands
= 0;
4489 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4490 optimize_encoding ();
4492 if (!process_suffix ())
4495 /* Update operand types. */
4496 for (j
= 0; j
< i
.operands
; j
++)
4497 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4499 /* Make still unresolved immediate matches conform to size of immediate
4500 given in i.suffix. */
4501 if (!finalize_imm ())
4504 if (i
.types
[0].bitfield
.imm1
)
4505 i
.imm_operands
= 0; /* kludge for shift insns. */
4507 /* We only need to check those implicit registers for instructions
4508 with 3 operands or less. */
4509 if (i
.operands
<= 3)
4510 for (j
= 0; j
< i
.operands
; j
++)
4511 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4512 && !i
.types
[j
].bitfield
.xmmword
)
4515 /* ImmExt should be processed after SSE2AVX. */
4516 if (!i
.tm
.opcode_modifier
.sse2avx
4517 && i
.tm
.opcode_modifier
.immext
)
4520 /* For insns with operands there are more diddles to do to the opcode. */
4523 if (!process_operands ())
4526 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4528 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4529 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4532 if (is_any_vex_encoding (&i
.tm
))
4534 if (!cpu_arch_flags
.bitfield
.cpui286
)
4536 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4541 if (i
.tm
.opcode_modifier
.vex
)
4542 build_vex_prefix (t
);
4544 build_evex_prefix ();
4547 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4548 instructions may define INT_OPCODE as well, so avoid this corner
4549 case for those instructions that use MODRM. */
4550 if (i
.tm
.base_opcode
== INT_OPCODE
4551 && !i
.tm
.opcode_modifier
.modrm
4552 && i
.op
[0].imms
->X_add_number
== 3)
4554 i
.tm
.base_opcode
= INT3_OPCODE
;
4558 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4559 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4560 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4561 && i
.op
[0].disps
->X_op
== O_constant
)
4563 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4564 the absolute address given by the constant. Since ix86 jumps and
4565 calls are pc relative, we need to generate a reloc. */
4566 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4567 i
.op
[0].disps
->X_op
= O_symbol
;
4570 /* For 8 bit registers we need an empty rex prefix. Also if the
4571 instruction already has a prefix, we need to convert old
4572 registers to new ones. */
4574 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4575 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4576 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4577 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4578 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4579 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4584 i
.rex
|= REX_OPCODE
;
4585 for (x
= 0; x
< 2; x
++)
4587 /* Look for 8 bit operand that uses old registers. */
4588 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4589 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4591 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4592 /* In case it is "hi" register, give up. */
4593 if (i
.op
[x
].regs
->reg_num
> 3)
4594 as_bad (_("can't encode register '%s%s' in an "
4595 "instruction requiring REX prefix."),
4596 register_prefix
, i
.op
[x
].regs
->reg_name
);
4598 /* Otherwise it is equivalent to the extended register.
4599 Since the encoding doesn't change this is merely
4600 cosmetic cleanup for debug output. */
4602 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4607 if (i
.rex
== 0 && i
.rex_encoding
)
4609 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4610 that uses legacy register. If it is "hi" register, don't add
4611 the REX_OPCODE byte. */
4613 for (x
= 0; x
< 2; x
++)
4614 if (i
.types
[x
].bitfield
.class == Reg
4615 && i
.types
[x
].bitfield
.byte
4616 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4617 && i
.op
[x
].regs
->reg_num
> 3)
4619 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4620 i
.rex_encoding
= FALSE
;
4629 add_prefix (REX_OPCODE
| i
.rex
);
4631 /* We are ready to output the insn. */
4634 last_insn
.seg
= now_seg
;
4636 if (i
.tm
.opcode_modifier
.isprefix
)
4638 last_insn
.kind
= last_insn_prefix
;
4639 last_insn
.name
= i
.tm
.name
;
4640 last_insn
.file
= as_where (&last_insn
.line
);
4643 last_insn
.kind
= last_insn_other
;
4647 parse_insn (char *line
, char *mnemonic
)
4650 char *token_start
= l
;
4653 const insn_template
*t
;
4659 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4664 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4666 as_bad (_("no such instruction: `%s'"), token_start
);
4671 if (!is_space_char (*l
)
4672 && *l
!= END_OF_INSN
4674 || (*l
!= PREFIX_SEPARATOR
4677 as_bad (_("invalid character %s in mnemonic"),
4678 output_invalid (*l
));
4681 if (token_start
== l
)
4683 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4684 as_bad (_("expecting prefix; got nothing"));
4686 as_bad (_("expecting mnemonic; got nothing"));
4690 /* Look up instruction (or prefix) via hash table. */
4691 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4693 if (*l
!= END_OF_INSN
4694 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4695 && current_templates
4696 && current_templates
->start
->opcode_modifier
.isprefix
)
4698 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4700 as_bad ((flag_code
!= CODE_64BIT
4701 ? _("`%s' is only supported in 64-bit mode")
4702 : _("`%s' is not supported in 64-bit mode")),
4703 current_templates
->start
->name
);
4706 /* If we are in 16-bit mode, do not allow addr16 or data16.
4707 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4708 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4709 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4710 && flag_code
!= CODE_64BIT
4711 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4712 ^ (flag_code
== CODE_16BIT
)))
4714 as_bad (_("redundant %s prefix"),
4715 current_templates
->start
->name
);
4718 if (current_templates
->start
->opcode_length
== 0)
4720 /* Handle pseudo prefixes. */
4721 switch (current_templates
->start
->base_opcode
)
4725 i
.disp_encoding
= disp_encoding_8bit
;
4729 i
.disp_encoding
= disp_encoding_32bit
;
4733 i
.dir_encoding
= dir_encoding_load
;
4737 i
.dir_encoding
= dir_encoding_store
;
4741 i
.vec_encoding
= vex_encoding_vex
;
4745 i
.vec_encoding
= vex_encoding_vex3
;
4749 i
.vec_encoding
= vex_encoding_evex
;
4753 i
.rex_encoding
= TRUE
;
4757 i
.no_optimize
= TRUE
;
4765 /* Add prefix, checking for repeated prefixes. */
4766 switch (add_prefix (current_templates
->start
->base_opcode
))
4771 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4772 i
.notrack_prefix
= current_templates
->start
->name
;
4775 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4776 i
.hle_prefix
= current_templates
->start
->name
;
4777 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4778 i
.bnd_prefix
= current_templates
->start
->name
;
4780 i
.rep_prefix
= current_templates
->start
->name
;
4786 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4793 if (!current_templates
)
4795 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4796 Check if we should swap operand or force 32bit displacement in
4798 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4799 i
.dir_encoding
= dir_encoding_swap
;
4800 else if (mnem_p
- 3 == dot_p
4803 i
.disp_encoding
= disp_encoding_8bit
;
4804 else if (mnem_p
- 4 == dot_p
4808 i
.disp_encoding
= disp_encoding_32bit
;
4813 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4816 if (!current_templates
)
4819 if (mnem_p
> mnemonic
)
4821 /* See if we can get a match by trimming off a suffix. */
4824 case WORD_MNEM_SUFFIX
:
4825 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4826 i
.suffix
= SHORT_MNEM_SUFFIX
;
4829 case BYTE_MNEM_SUFFIX
:
4830 case QWORD_MNEM_SUFFIX
:
4831 i
.suffix
= mnem_p
[-1];
4833 current_templates
= (const templates
*) hash_find (op_hash
,
4836 case SHORT_MNEM_SUFFIX
:
4837 case LONG_MNEM_SUFFIX
:
4840 i
.suffix
= mnem_p
[-1];
4842 current_templates
= (const templates
*) hash_find (op_hash
,
4851 if (intel_float_operand (mnemonic
) == 1)
4852 i
.suffix
= SHORT_MNEM_SUFFIX
;
4854 i
.suffix
= LONG_MNEM_SUFFIX
;
4856 current_templates
= (const templates
*) hash_find (op_hash
,
4863 if (!current_templates
)
4865 as_bad (_("no such instruction: `%s'"), token_start
);
4870 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4871 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4873 /* Check for a branch hint. We allow ",pt" and ",pn" for
4874 predict taken and predict not taken respectively.
4875 I'm not sure that branch hints actually do anything on loop
4876 and jcxz insns (JumpByte) for current Pentium4 chips. They
4877 may work in the future and it doesn't hurt to accept them
4879 if (l
[0] == ',' && l
[1] == 'p')
4883 if (!add_prefix (DS_PREFIX_OPCODE
))
4887 else if (l
[2] == 'n')
4889 if (!add_prefix (CS_PREFIX_OPCODE
))
4895 /* Any other comma loses. */
4898 as_bad (_("invalid character %s in mnemonic"),
4899 output_invalid (*l
));
4903 /* Check if instruction is supported on specified architecture. */
4905 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4907 supported
|= cpu_flags_match (t
);
4908 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4910 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4911 as_warn (_("use .code16 to ensure correct addressing mode"));
4917 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4918 as_bad (flag_code
== CODE_64BIT
4919 ? _("`%s' is not supported in 64-bit mode")
4920 : _("`%s' is only supported in 64-bit mode"),
4921 current_templates
->start
->name
);
4923 as_bad (_("`%s' is not supported on `%s%s'"),
4924 current_templates
->start
->name
,
4925 cpu_arch_name
? cpu_arch_name
: default_arch
,
4926 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4932 parse_operands (char *l
, const char *mnemonic
)
4936 /* 1 if operand is pending after ','. */
4937 unsigned int expecting_operand
= 0;
4939 /* Non-zero if operand parens not balanced. */
4940 unsigned int paren_not_balanced
;
4942 while (*l
!= END_OF_INSN
)
4944 /* Skip optional white space before operand. */
4945 if (is_space_char (*l
))
4947 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4949 as_bad (_("invalid character %s before operand %d"),
4950 output_invalid (*l
),
4954 token_start
= l
; /* After white space. */
4955 paren_not_balanced
= 0;
4956 while (paren_not_balanced
|| *l
!= ',')
4958 if (*l
== END_OF_INSN
)
4960 if (paren_not_balanced
)
4963 as_bad (_("unbalanced parenthesis in operand %d."),
4966 as_bad (_("unbalanced brackets in operand %d."),
4971 break; /* we are done */
4973 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4975 as_bad (_("invalid character %s in operand %d"),
4976 output_invalid (*l
),
4983 ++paren_not_balanced
;
4985 --paren_not_balanced
;
4990 ++paren_not_balanced
;
4992 --paren_not_balanced
;
4996 if (l
!= token_start
)
4997 { /* Yes, we've read in another operand. */
4998 unsigned int operand_ok
;
4999 this_operand
= i
.operands
++;
5000 if (i
.operands
> MAX_OPERANDS
)
5002 as_bad (_("spurious operands; (%d operands/instruction max)"),
5006 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5007 /* Now parse operand adding info to 'i' as we go along. */
5008 END_STRING_AND_SAVE (l
);
5010 if (i
.mem_operands
> 1)
5012 as_bad (_("too many memory references for `%s'"),
5019 i386_intel_operand (token_start
,
5020 intel_float_operand (mnemonic
));
5022 operand_ok
= i386_att_operand (token_start
);
5024 RESTORE_END_STRING (l
);
5030 if (expecting_operand
)
5032 expecting_operand_after_comma
:
5033 as_bad (_("expecting operand after ','; got nothing"));
5038 as_bad (_("expecting operand before ','; got nothing"));
5043 /* Now *l must be either ',' or END_OF_INSN. */
5046 if (*++l
== END_OF_INSN
)
5048 /* Just skip it, if it's \n complain. */
5049 goto expecting_operand_after_comma
;
5051 expecting_operand
= 1;
5058 swap_2_operands (int xchg1
, int xchg2
)
5060 union i386_op temp_op
;
5061 i386_operand_type temp_type
;
5062 unsigned int temp_flags
;
5063 enum bfd_reloc_code_real temp_reloc
;
5065 temp_type
= i
.types
[xchg2
];
5066 i
.types
[xchg2
] = i
.types
[xchg1
];
5067 i
.types
[xchg1
] = temp_type
;
5069 temp_flags
= i
.flags
[xchg2
];
5070 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5071 i
.flags
[xchg1
] = temp_flags
;
5073 temp_op
= i
.op
[xchg2
];
5074 i
.op
[xchg2
] = i
.op
[xchg1
];
5075 i
.op
[xchg1
] = temp_op
;
5077 temp_reloc
= i
.reloc
[xchg2
];
5078 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5079 i
.reloc
[xchg1
] = temp_reloc
;
5083 if (i
.mask
->operand
== xchg1
)
5084 i
.mask
->operand
= xchg2
;
5085 else if (i
.mask
->operand
== xchg2
)
5086 i
.mask
->operand
= xchg1
;
5090 if (i
.broadcast
->operand
== xchg1
)
5091 i
.broadcast
->operand
= xchg2
;
5092 else if (i
.broadcast
->operand
== xchg2
)
5093 i
.broadcast
->operand
= xchg1
;
5097 if (i
.rounding
->operand
== xchg1
)
5098 i
.rounding
->operand
= xchg2
;
5099 else if (i
.rounding
->operand
== xchg2
)
5100 i
.rounding
->operand
= xchg1
;
5105 swap_operands (void)
5111 swap_2_operands (1, i
.operands
- 2);
5115 swap_2_operands (0, i
.operands
- 1);
5121 if (i
.mem_operands
== 2)
5123 const seg_entry
*temp_seg
;
5124 temp_seg
= i
.seg
[0];
5125 i
.seg
[0] = i
.seg
[1];
5126 i
.seg
[1] = temp_seg
;
5130 /* Try to ensure constant immediates are represented in the smallest
5135 char guess_suffix
= 0;
5139 guess_suffix
= i
.suffix
;
5140 else if (i
.reg_operands
)
5142 /* Figure out a suffix from the last register operand specified.
5143 We can't do this properly yet, i.e. excluding special register
5144 instances, but the following works for instructions with
5145 immediates. In any case, we can't set i.suffix yet. */
5146 for (op
= i
.operands
; --op
>= 0;)
5147 if (i
.types
[op
].bitfield
.class != Reg
)
5149 else if (i
.types
[op
].bitfield
.byte
)
5151 guess_suffix
= BYTE_MNEM_SUFFIX
;
5154 else if (i
.types
[op
].bitfield
.word
)
5156 guess_suffix
= WORD_MNEM_SUFFIX
;
5159 else if (i
.types
[op
].bitfield
.dword
)
5161 guess_suffix
= LONG_MNEM_SUFFIX
;
5164 else if (i
.types
[op
].bitfield
.qword
)
5166 guess_suffix
= QWORD_MNEM_SUFFIX
;
5170 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5171 guess_suffix
= WORD_MNEM_SUFFIX
;
5173 for (op
= i
.operands
; --op
>= 0;)
5174 if (operand_type_check (i
.types
[op
], imm
))
5176 switch (i
.op
[op
].imms
->X_op
)
5179 /* If a suffix is given, this operand may be shortened. */
5180 switch (guess_suffix
)
5182 case LONG_MNEM_SUFFIX
:
5183 i
.types
[op
].bitfield
.imm32
= 1;
5184 i
.types
[op
].bitfield
.imm64
= 1;
5186 case WORD_MNEM_SUFFIX
:
5187 i
.types
[op
].bitfield
.imm16
= 1;
5188 i
.types
[op
].bitfield
.imm32
= 1;
5189 i
.types
[op
].bitfield
.imm32s
= 1;
5190 i
.types
[op
].bitfield
.imm64
= 1;
5192 case BYTE_MNEM_SUFFIX
:
5193 i
.types
[op
].bitfield
.imm8
= 1;
5194 i
.types
[op
].bitfield
.imm8s
= 1;
5195 i
.types
[op
].bitfield
.imm16
= 1;
5196 i
.types
[op
].bitfield
.imm32
= 1;
5197 i
.types
[op
].bitfield
.imm32s
= 1;
5198 i
.types
[op
].bitfield
.imm64
= 1;
5202 /* If this operand is at most 16 bits, convert it
5203 to a signed 16 bit number before trying to see
5204 whether it will fit in an even smaller size.
5205 This allows a 16-bit operand such as $0xffe0 to
5206 be recognised as within Imm8S range. */
5207 if ((i
.types
[op
].bitfield
.imm16
)
5208 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5210 i
.op
[op
].imms
->X_add_number
=
5211 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5214 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5215 if ((i
.types
[op
].bitfield
.imm32
)
5216 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5219 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5220 ^ ((offsetT
) 1 << 31))
5221 - ((offsetT
) 1 << 31));
5225 = operand_type_or (i
.types
[op
],
5226 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5228 /* We must avoid matching of Imm32 templates when 64bit
5229 only immediate is available. */
5230 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5231 i
.types
[op
].bitfield
.imm32
= 0;
5238 /* Symbols and expressions. */
5240 /* Convert symbolic operand to proper sizes for matching, but don't
5241 prevent matching a set of insns that only supports sizes other
5242 than those matching the insn suffix. */
5244 i386_operand_type mask
, allowed
;
5245 const insn_template
*t
;
5247 operand_type_set (&mask
, 0);
5248 operand_type_set (&allowed
, 0);
5250 for (t
= current_templates
->start
;
5251 t
< current_templates
->end
;
5254 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5255 allowed
= operand_type_and (allowed
, anyimm
);
5257 switch (guess_suffix
)
5259 case QWORD_MNEM_SUFFIX
:
5260 mask
.bitfield
.imm64
= 1;
5261 mask
.bitfield
.imm32s
= 1;
5263 case LONG_MNEM_SUFFIX
:
5264 mask
.bitfield
.imm32
= 1;
5266 case WORD_MNEM_SUFFIX
:
5267 mask
.bitfield
.imm16
= 1;
5269 case BYTE_MNEM_SUFFIX
:
5270 mask
.bitfield
.imm8
= 1;
5275 allowed
= operand_type_and (mask
, allowed
);
5276 if (!operand_type_all_zero (&allowed
))
5277 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5284 /* Try to use the smallest displacement type too. */
5286 optimize_disp (void)
5290 for (op
= i
.operands
; --op
>= 0;)
5291 if (operand_type_check (i
.types
[op
], disp
))
5293 if (i
.op
[op
].disps
->X_op
== O_constant
)
5295 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5297 if (i
.types
[op
].bitfield
.disp16
5298 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5300 /* If this operand is at most 16 bits, convert
5301 to a signed 16 bit number and don't use 64bit
5303 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5304 i
.types
[op
].bitfield
.disp64
= 0;
5307 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5308 if (i
.types
[op
].bitfield
.disp32
5309 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5311 /* If this operand is at most 32 bits, convert
5312 to a signed 32 bit number and don't use 64bit
5314 op_disp
&= (((offsetT
) 2 << 31) - 1);
5315 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5316 i
.types
[op
].bitfield
.disp64
= 0;
5319 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5321 i
.types
[op
].bitfield
.disp8
= 0;
5322 i
.types
[op
].bitfield
.disp16
= 0;
5323 i
.types
[op
].bitfield
.disp32
= 0;
5324 i
.types
[op
].bitfield
.disp32s
= 0;
5325 i
.types
[op
].bitfield
.disp64
= 0;
5329 else if (flag_code
== CODE_64BIT
)
5331 if (fits_in_signed_long (op_disp
))
5333 i
.types
[op
].bitfield
.disp64
= 0;
5334 i
.types
[op
].bitfield
.disp32s
= 1;
5336 if (i
.prefix
[ADDR_PREFIX
]
5337 && fits_in_unsigned_long (op_disp
))
5338 i
.types
[op
].bitfield
.disp32
= 1;
5340 if ((i
.types
[op
].bitfield
.disp32
5341 || i
.types
[op
].bitfield
.disp32s
5342 || i
.types
[op
].bitfield
.disp16
)
5343 && fits_in_disp8 (op_disp
))
5344 i
.types
[op
].bitfield
.disp8
= 1;
5346 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5347 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5349 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5350 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5351 i
.types
[op
].bitfield
.disp8
= 0;
5352 i
.types
[op
].bitfield
.disp16
= 0;
5353 i
.types
[op
].bitfield
.disp32
= 0;
5354 i
.types
[op
].bitfield
.disp32s
= 0;
5355 i
.types
[op
].bitfield
.disp64
= 0;
5358 /* We only support 64bit displacement on constants. */
5359 i
.types
[op
].bitfield
.disp64
= 0;
5363 /* Return 1 if there is a match in broadcast bytes between operand
5364 GIVEN and instruction template T. */
5367 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5369 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5370 && i
.types
[given
].bitfield
.byte
)
5371 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5372 && i
.types
[given
].bitfield
.word
)
5373 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5374 && i
.types
[given
].bitfield
.dword
)
5375 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5376 && i
.types
[given
].bitfield
.qword
));
5379 /* Check if operands are valid for the instruction. */
5382 check_VecOperands (const insn_template
*t
)
5387 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5388 any one operand are implicity requiring AVX512VL support if the actual
5389 operand size is YMMword or XMMword. Since this function runs after
5390 template matching, there's no need to check for YMMword/XMMword in
5392 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5393 if (!cpu_flags_all_zero (&cpu
)
5394 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5395 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5397 for (op
= 0; op
< t
->operands
; ++op
)
5399 if (t
->operand_types
[op
].bitfield
.zmmword
5400 && (i
.types
[op
].bitfield
.ymmword
5401 || i
.types
[op
].bitfield
.xmmword
))
5403 i
.error
= unsupported
;
5409 /* Without VSIB byte, we can't have a vector register for index. */
5410 if (!t
->opcode_modifier
.vecsib
5412 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5413 || i
.index_reg
->reg_type
.bitfield
.ymmword
5414 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5416 i
.error
= unsupported_vector_index_register
;
5420 /* Check if default mask is allowed. */
5421 if (t
->opcode_modifier
.nodefmask
5422 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5424 i
.error
= no_default_mask
;
5428 /* For VSIB byte, we need a vector register for index, and all vector
5429 registers must be distinct. */
5430 if (t
->opcode_modifier
.vecsib
)
5433 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5434 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5435 || (t
->opcode_modifier
.vecsib
== VecSIB256
5436 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5437 || (t
->opcode_modifier
.vecsib
== VecSIB512
5438 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5440 i
.error
= invalid_vsib_address
;
5444 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5445 if (i
.reg_operands
== 2 && !i
.mask
)
5447 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5448 gas_assert (i
.types
[0].bitfield
.xmmword
5449 || i
.types
[0].bitfield
.ymmword
);
5450 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5451 gas_assert (i
.types
[2].bitfield
.xmmword
5452 || i
.types
[2].bitfield
.ymmword
);
5453 if (operand_check
== check_none
)
5455 if (register_number (i
.op
[0].regs
)
5456 != register_number (i
.index_reg
)
5457 && register_number (i
.op
[2].regs
)
5458 != register_number (i
.index_reg
)
5459 && register_number (i
.op
[0].regs
)
5460 != register_number (i
.op
[2].regs
))
5462 if (operand_check
== check_error
)
5464 i
.error
= invalid_vector_register_set
;
5467 as_warn (_("mask, index, and destination registers should be distinct"));
5469 else if (i
.reg_operands
== 1 && i
.mask
)
5471 if (i
.types
[1].bitfield
.class == RegSIMD
5472 && (i
.types
[1].bitfield
.xmmword
5473 || i
.types
[1].bitfield
.ymmword
5474 || i
.types
[1].bitfield
.zmmword
)
5475 && (register_number (i
.op
[1].regs
)
5476 == register_number (i
.index_reg
)))
5478 if (operand_check
== check_error
)
5480 i
.error
= invalid_vector_register_set
;
5483 if (operand_check
!= check_none
)
5484 as_warn (_("index and destination registers should be distinct"));
5489 /* Check if broadcast is supported by the instruction and is applied
5490 to the memory operand. */
5493 i386_operand_type type
, overlap
;
5495 /* Check if specified broadcast is supported in this instruction,
5496 and its broadcast bytes match the memory operand. */
5497 op
= i
.broadcast
->operand
;
5498 if (!t
->opcode_modifier
.broadcast
5499 || !(i
.flags
[op
] & Operand_Mem
)
5500 || (!i
.types
[op
].bitfield
.unspecified
5501 && !match_broadcast_size (t
, op
)))
5504 i
.error
= unsupported_broadcast
;
5508 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5509 * i
.broadcast
->type
);
5510 operand_type_set (&type
, 0);
5511 switch (i
.broadcast
->bytes
)
5514 type
.bitfield
.word
= 1;
5517 type
.bitfield
.dword
= 1;
5520 type
.bitfield
.qword
= 1;
5523 type
.bitfield
.xmmword
= 1;
5526 type
.bitfield
.ymmword
= 1;
5529 type
.bitfield
.zmmword
= 1;
5535 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5536 if (operand_type_all_zero (&overlap
))
5539 if (t
->opcode_modifier
.checkregsize
)
5543 type
.bitfield
.baseindex
= 1;
5544 for (j
= 0; j
< i
.operands
; ++j
)
5547 && !operand_type_register_match(i
.types
[j
],
5548 t
->operand_types
[j
],
5550 t
->operand_types
[op
]))
5555 /* If broadcast is supported in this instruction, we need to check if
5556 operand of one-element size isn't specified without broadcast. */
5557 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5559 /* Find memory operand. */
5560 for (op
= 0; op
< i
.operands
; op
++)
5561 if (i
.flags
[op
] & Operand_Mem
)
5563 gas_assert (op
< i
.operands
);
5564 /* Check size of the memory operand. */
5565 if (match_broadcast_size (t
, op
))
5567 i
.error
= broadcast_needed
;
5572 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5574 /* Check if requested masking is supported. */
5577 switch (t
->opcode_modifier
.masking
)
5581 case MERGING_MASKING
:
5582 if (i
.mask
->zeroing
)
5585 i
.error
= unsupported_masking
;
5589 case DYNAMIC_MASKING
:
5590 /* Memory destinations allow only merging masking. */
5591 if (i
.mask
->zeroing
&& i
.mem_operands
)
5593 /* Find memory operand. */
5594 for (op
= 0; op
< i
.operands
; op
++)
5595 if (i
.flags
[op
] & Operand_Mem
)
5597 gas_assert (op
< i
.operands
);
5598 if (op
== i
.operands
- 1)
5600 i
.error
= unsupported_masking
;
5610 /* Check if masking is applied to dest operand. */
5611 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5613 i
.error
= mask_not_on_destination
;
5620 if (!t
->opcode_modifier
.sae
5621 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5623 i
.error
= unsupported_rc_sae
;
5626 /* If the instruction has several immediate operands and one of
5627 them is rounding, the rounding operand should be the last
5628 immediate operand. */
5629 if (i
.imm_operands
> 1
5630 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5632 i
.error
= rc_sae_operand_not_last_imm
;
5637 /* Check vector Disp8 operand. */
5638 if (t
->opcode_modifier
.disp8memshift
5639 && i
.disp_encoding
!= disp_encoding_32bit
)
5642 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5643 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5644 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5647 const i386_operand_type
*type
= NULL
;
5650 for (op
= 0; op
< i
.operands
; op
++)
5651 if (i
.flags
[op
] & Operand_Mem
)
5653 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5654 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5655 else if (t
->operand_types
[op
].bitfield
.xmmword
5656 + t
->operand_types
[op
].bitfield
.ymmword
5657 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5658 type
= &t
->operand_types
[op
];
5659 else if (!i
.types
[op
].bitfield
.unspecified
)
5660 type
= &i
.types
[op
];
5662 else if (i
.types
[op
].bitfield
.class == RegSIMD
5663 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5665 if (i
.types
[op
].bitfield
.zmmword
)
5667 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5669 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5675 if (type
->bitfield
.zmmword
)
5677 else if (type
->bitfield
.ymmword
)
5679 else if (type
->bitfield
.xmmword
)
5683 /* For the check in fits_in_disp8(). */
5684 if (i
.memshift
== 0)
5688 for (op
= 0; op
< i
.operands
; op
++)
5689 if (operand_type_check (i
.types
[op
], disp
)
5690 && i
.op
[op
].disps
->X_op
== O_constant
)
5692 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5694 i
.types
[op
].bitfield
.disp8
= 1;
5697 i
.types
[op
].bitfield
.disp8
= 0;
5706 /* Check if operands are valid for the instruction. Update VEX
5710 VEX_check_operands (const insn_template
*t
)
5712 if (i
.vec_encoding
== vex_encoding_evex
)
5714 /* This instruction must be encoded with EVEX prefix. */
5715 if (!is_evex_encoding (t
))
5717 i
.error
= unsupported
;
5723 if (!t
->opcode_modifier
.vex
)
5725 /* This instruction template doesn't have VEX prefix. */
5726 if (i
.vec_encoding
!= vex_encoding_default
)
5728 i
.error
= unsupported
;
5734 /* Check the special Imm4 cases; must be the first operand. */
5735 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5737 if (i
.op
[0].imms
->X_op
!= O_constant
5738 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5744 /* Turn off Imm<N> so that update_imm won't complain. */
5745 operand_type_set (&i
.types
[0], 0);
5751 static const insn_template
*
5752 match_template (char mnem_suffix
)
5754 /* Points to template once we've found it. */
5755 const insn_template
*t
;
5756 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5757 i386_operand_type overlap4
;
5758 unsigned int found_reverse_match
;
5759 i386_opcode_modifier suffix_check
;
5760 i386_operand_type operand_types
[MAX_OPERANDS
];
5761 int addr_prefix_disp
;
5762 unsigned int j
, size_match
, check_register
;
5763 enum i386_error specific_error
= 0;
5765 #if MAX_OPERANDS != 5
5766 # error "MAX_OPERANDS must be 5."
5769 found_reverse_match
= 0;
5770 addr_prefix_disp
= -1;
5772 /* Prepare for mnemonic suffix check. */
5773 memset (&suffix_check
, 0, sizeof (suffix_check
));
5774 switch (mnem_suffix
)
5776 case BYTE_MNEM_SUFFIX
:
5777 suffix_check
.no_bsuf
= 1;
5779 case WORD_MNEM_SUFFIX
:
5780 suffix_check
.no_wsuf
= 1;
5782 case SHORT_MNEM_SUFFIX
:
5783 suffix_check
.no_ssuf
= 1;
5785 case LONG_MNEM_SUFFIX
:
5786 suffix_check
.no_lsuf
= 1;
5788 case QWORD_MNEM_SUFFIX
:
5789 suffix_check
.no_qsuf
= 1;
5792 /* NB: In Intel syntax, normally we can check for memory operand
5793 size when there is no mnemonic suffix. But jmp and call have
5794 2 different encodings with Dword memory operand size, one with
5795 No_ldSuf and the other without. i.suffix is set to
5796 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5797 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5798 suffix_check
.no_ldsuf
= 1;
5801 /* Must have right number of operands. */
5802 i
.error
= number_of_operands_mismatch
;
5804 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5806 addr_prefix_disp
= -1;
5807 found_reverse_match
= 0;
5809 if (i
.operands
!= t
->operands
)
5812 /* Check processor support. */
5813 i
.error
= unsupported
;
5814 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5817 /* Check AT&T mnemonic. */
5818 i
.error
= unsupported_with_intel_mnemonic
;
5819 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5822 /* Check AT&T/Intel syntax. */
5823 i
.error
= unsupported_syntax
;
5824 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5825 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5828 /* Check Intel64/AMD64 ISA. */
5832 /* Default: Don't accept Intel64. */
5833 if (t
->opcode_modifier
.isa64
== INTEL64
)
5837 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5838 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5842 /* -mintel64: Don't accept AMD64. */
5843 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5848 /* Check the suffix. */
5849 i
.error
= invalid_instruction_suffix
;
5850 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5851 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5852 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5853 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5854 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5855 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5858 size_match
= operand_size_match (t
);
5862 /* This is intentionally not
5864 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5866 as the case of a missing * on the operand is accepted (perhaps with
5867 a warning, issued further down). */
5868 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5870 i
.error
= operand_type_mismatch
;
5874 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5875 operand_types
[j
] = t
->operand_types
[j
];
5877 /* In general, don't allow
5878 - 64-bit operands outside of 64-bit mode,
5879 - 32-bit operands on pre-386. */
5880 if (((i
.suffix
== QWORD_MNEM_SUFFIX
5881 && flag_code
!= CODE_64BIT
5882 && (t
->base_opcode
!= 0x0fc7
5883 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5884 || (i
.suffix
== LONG_MNEM_SUFFIX
5885 && !cpu_arch_flags
.bitfield
.cpui386
))
5887 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5888 && !t
->opcode_modifier
.broadcast
5889 && !intel_float_operand (t
->name
))
5890 : intel_float_operand (t
->name
) != 2)
5891 && ((operand_types
[0].bitfield
.class != RegMMX
5892 && operand_types
[0].bitfield
.class != RegSIMD
)
5893 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5894 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
)))
5897 /* Do not verify operands when there are none. */
5899 /* We've found a match; break out of loop. */
5902 if (!t
->opcode_modifier
.jump
5903 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5905 /* There should be only one Disp operand. */
5906 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5907 if (operand_type_check (operand_types
[j
], disp
))
5909 if (j
< MAX_OPERANDS
)
5911 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5913 addr_prefix_disp
= j
;
5915 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5916 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5920 override
= !override
;
5923 if (operand_types
[j
].bitfield
.disp32
5924 && operand_types
[j
].bitfield
.disp16
)
5926 operand_types
[j
].bitfield
.disp16
= override
;
5927 operand_types
[j
].bitfield
.disp32
= !override
;
5929 operand_types
[j
].bitfield
.disp32s
= 0;
5930 operand_types
[j
].bitfield
.disp64
= 0;
5934 if (operand_types
[j
].bitfield
.disp32s
5935 || operand_types
[j
].bitfield
.disp64
)
5937 operand_types
[j
].bitfield
.disp64
&= !override
;
5938 operand_types
[j
].bitfield
.disp32s
&= !override
;
5939 operand_types
[j
].bitfield
.disp32
= override
;
5941 operand_types
[j
].bitfield
.disp16
= 0;
5947 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5948 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5951 /* We check register size if needed. */
5952 if (t
->opcode_modifier
.checkregsize
)
5954 check_register
= (1 << t
->operands
) - 1;
5956 check_register
&= ~(1 << i
.broadcast
->operand
);
5961 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5962 switch (t
->operands
)
5965 if (!operand_type_match (overlap0
, i
.types
[0]))
5969 /* xchg %eax, %eax is a special case. It is an alias for nop
5970 only in 32bit mode and we can use opcode 0x90. In 64bit
5971 mode, we can't use 0x90 for xchg %eax, %eax since it should
5972 zero-extend %eax to %rax. */
5973 if (flag_code
== CODE_64BIT
5974 && t
->base_opcode
== 0x90
5975 && i
.types
[0].bitfield
.instance
== Accum
5976 && i
.types
[0].bitfield
.dword
5977 && i
.types
[1].bitfield
.instance
== Accum
5978 && i
.types
[1].bitfield
.dword
)
5980 /* xrelease mov %eax, <disp> is another special case. It must not
5981 match the accumulator-only encoding of mov. */
5982 if (flag_code
!= CODE_64BIT
5984 && t
->base_opcode
== 0xa0
5985 && i
.types
[0].bitfield
.instance
== Accum
5986 && (i
.flags
[1] & Operand_Mem
))
5991 if (!(size_match
& MATCH_STRAIGHT
))
5993 /* Reverse direction of operands if swapping is possible in the first
5994 place (operands need to be symmetric) and
5995 - the load form is requested, and the template is a store form,
5996 - the store form is requested, and the template is a load form,
5997 - the non-default (swapped) form is requested. */
5998 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5999 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6000 && !operand_type_all_zero (&overlap1
))
6001 switch (i
.dir_encoding
)
6003 case dir_encoding_load
:
6004 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6005 || t
->opcode_modifier
.regmem
)
6009 case dir_encoding_store
:
6010 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6011 && !t
->opcode_modifier
.regmem
)
6015 case dir_encoding_swap
:
6018 case dir_encoding_default
:
6021 /* If we want store form, we skip the current load. */
6022 if ((i
.dir_encoding
== dir_encoding_store
6023 || i
.dir_encoding
== dir_encoding_swap
)
6024 && i
.mem_operands
== 0
6025 && t
->opcode_modifier
.load
)
6030 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6031 if (!operand_type_match (overlap0
, i
.types
[0])
6032 || !operand_type_match (overlap1
, i
.types
[1])
6033 || ((check_register
& 3) == 3
6034 && !operand_type_register_match (i
.types
[0],
6039 /* Check if other direction is valid ... */
6040 if (!t
->opcode_modifier
.d
)
6044 if (!(size_match
& MATCH_REVERSE
))
6046 /* Try reversing direction of operands. */
6047 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6048 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6049 if (!operand_type_match (overlap0
, i
.types
[0])
6050 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6052 && !operand_type_register_match (i
.types
[0],
6053 operand_types
[i
.operands
- 1],
6054 i
.types
[i
.operands
- 1],
6057 /* Does not match either direction. */
6060 /* found_reverse_match holds which of D or FloatR
6062 if (!t
->opcode_modifier
.d
)
6063 found_reverse_match
= 0;
6064 else if (operand_types
[0].bitfield
.tbyte
)
6065 found_reverse_match
= Opcode_FloatD
;
6066 else if (operand_types
[0].bitfield
.xmmword
6067 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6068 || operand_types
[0].bitfield
.class == RegMMX
6069 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6070 || is_any_vex_encoding(t
))
6071 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6072 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6074 found_reverse_match
= Opcode_D
;
6075 if (t
->opcode_modifier
.floatr
)
6076 found_reverse_match
|= Opcode_FloatR
;
6080 /* Found a forward 2 operand match here. */
6081 switch (t
->operands
)
6084 overlap4
= operand_type_and (i
.types
[4],
6088 overlap3
= operand_type_and (i
.types
[3],
6092 overlap2
= operand_type_and (i
.types
[2],
6097 switch (t
->operands
)
6100 if (!operand_type_match (overlap4
, i
.types
[4])
6101 || !operand_type_register_match (i
.types
[3],
6108 if (!operand_type_match (overlap3
, i
.types
[3])
6109 || ((check_register
& 0xa) == 0xa
6110 && !operand_type_register_match (i
.types
[1],
6114 || ((check_register
& 0xc) == 0xc
6115 && !operand_type_register_match (i
.types
[2],
6122 /* Here we make use of the fact that there are no
6123 reverse match 3 operand instructions. */
6124 if (!operand_type_match (overlap2
, i
.types
[2])
6125 || ((check_register
& 5) == 5
6126 && !operand_type_register_match (i
.types
[0],
6130 || ((check_register
& 6) == 6
6131 && !operand_type_register_match (i
.types
[1],
6139 /* Found either forward/reverse 2, 3 or 4 operand match here:
6140 slip through to break. */
6143 /* Check if vector and VEX operands are valid. */
6144 if (check_VecOperands (t
) || VEX_check_operands (t
))
6146 specific_error
= i
.error
;
6150 /* We've found a match; break out of loop. */
6154 if (t
== current_templates
->end
)
6156 /* We found no match. */
6157 const char *err_msg
;
6158 switch (specific_error
? specific_error
: i
.error
)
6162 case operand_size_mismatch
:
6163 err_msg
= _("operand size mismatch");
6165 case operand_type_mismatch
:
6166 err_msg
= _("operand type mismatch");
6168 case register_type_mismatch
:
6169 err_msg
= _("register type mismatch");
6171 case number_of_operands_mismatch
:
6172 err_msg
= _("number of operands mismatch");
6174 case invalid_instruction_suffix
:
6175 err_msg
= _("invalid instruction suffix");
6178 err_msg
= _("constant doesn't fit in 4 bits");
6180 case unsupported_with_intel_mnemonic
:
6181 err_msg
= _("unsupported with Intel mnemonic");
6183 case unsupported_syntax
:
6184 err_msg
= _("unsupported syntax");
6187 as_bad (_("unsupported instruction `%s'"),
6188 current_templates
->start
->name
);
6190 case invalid_vsib_address
:
6191 err_msg
= _("invalid VSIB address");
6193 case invalid_vector_register_set
:
6194 err_msg
= _("mask, index, and destination registers must be distinct");
6196 case unsupported_vector_index_register
:
6197 err_msg
= _("unsupported vector index register");
6199 case unsupported_broadcast
:
6200 err_msg
= _("unsupported broadcast");
6202 case broadcast_needed
:
6203 err_msg
= _("broadcast is needed for operand of such type");
6205 case unsupported_masking
:
6206 err_msg
= _("unsupported masking");
6208 case mask_not_on_destination
:
6209 err_msg
= _("mask not on destination operand");
6211 case no_default_mask
:
6212 err_msg
= _("default mask isn't allowed");
6214 case unsupported_rc_sae
:
6215 err_msg
= _("unsupported static rounding/sae");
6217 case rc_sae_operand_not_last_imm
:
6219 err_msg
= _("RC/SAE operand must precede immediate operands");
6221 err_msg
= _("RC/SAE operand must follow immediate operands");
6223 case invalid_register_operand
:
6224 err_msg
= _("invalid register operand");
6227 as_bad (_("%s for `%s'"), err_msg
,
6228 current_templates
->start
->name
);
6232 if (!quiet_warnings
)
6235 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6236 as_warn (_("indirect %s without `*'"), t
->name
);
6238 if (t
->opcode_modifier
.isprefix
6239 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6241 /* Warn them that a data or address size prefix doesn't
6242 affect assembly of the next line of code. */
6243 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6247 /* Copy the template we found. */
6250 if (addr_prefix_disp
!= -1)
6251 i
.tm
.operand_types
[addr_prefix_disp
]
6252 = operand_types
[addr_prefix_disp
];
6254 if (found_reverse_match
)
6256 /* If we found a reverse match we must alter the opcode direction
6257 bit and clear/flip the regmem modifier one. found_reverse_match
6258 holds bits to change (different for int & float insns). */
6260 i
.tm
.base_opcode
^= found_reverse_match
;
6262 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6263 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6265 /* Certain SIMD insns have their load forms specified in the opcode
6266 table, and hence we need to _set_ RegMem instead of clearing it.
6267 We need to avoid setting the bit though on insns like KMOVW. */
6268 i
.tm
.opcode_modifier
.regmem
6269 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6270 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6271 && !i
.tm
.opcode_modifier
.regmem
;
6280 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6281 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6283 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6285 as_bad (_("`%s' operand %u must use `%ses' segment"),
6287 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6292 /* There's only ever one segment override allowed per instruction.
6293 This instruction possibly has a legal segment override on the
6294 second operand, so copy the segment to where non-string
6295 instructions store it, allowing common code. */
6296 i
.seg
[op
] = i
.seg
[1];
6302 process_suffix (void)
6304 /* If matched instruction specifies an explicit instruction mnemonic
6306 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6307 i
.suffix
= WORD_MNEM_SUFFIX
;
6308 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6309 i
.suffix
= LONG_MNEM_SUFFIX
;
6310 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6311 i
.suffix
= QWORD_MNEM_SUFFIX
;
6312 else if (i
.reg_operands
6313 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6314 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6316 unsigned int numop
= i
.operands
;
6318 /* movsx/movzx want only their source operand considered here, for the
6319 ambiguity checking below. The suffix will be replaced afterwards
6320 to represent the destination (register). */
6321 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6322 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6325 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6326 if (i
.tm
.base_opcode
== 0xf20f38f0
6327 && i
.tm
.operand_types
[1].bitfield
.qword
)
6330 /* If there's no instruction mnemonic suffix we try to invent one
6331 based on GPR operands. */
6334 /* We take i.suffix from the last register operand specified,
6335 Destination register type is more significant than source
6336 register type. crc32 in SSE4.2 prefers source register
6338 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6341 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6342 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6344 if (i
.types
[op
].bitfield
.class != Reg
)
6346 if (i
.types
[op
].bitfield
.byte
)
6347 i
.suffix
= BYTE_MNEM_SUFFIX
;
6348 else if (i
.types
[op
].bitfield
.word
)
6349 i
.suffix
= WORD_MNEM_SUFFIX
;
6350 else if (i
.types
[op
].bitfield
.dword
)
6351 i
.suffix
= LONG_MNEM_SUFFIX
;
6352 else if (i
.types
[op
].bitfield
.qword
)
6353 i
.suffix
= QWORD_MNEM_SUFFIX
;
6359 /* As an exception, movsx/movzx silently default to a byte source
6361 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6362 && !i
.suffix
&& !intel_syntax
)
6363 i
.suffix
= BYTE_MNEM_SUFFIX
;
6365 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6368 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6369 && i
.tm
.opcode_modifier
.no_bsuf
)
6371 else if (!check_byte_reg ())
6374 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6377 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6378 && i
.tm
.opcode_modifier
.no_lsuf
6379 && !i
.tm
.opcode_modifier
.todword
6380 && !i
.tm
.opcode_modifier
.toqword
)
6382 else if (!check_long_reg ())
6385 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6388 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6389 && i
.tm
.opcode_modifier
.no_qsuf
6390 && !i
.tm
.opcode_modifier
.todword
6391 && !i
.tm
.opcode_modifier
.toqword
)
6393 else if (!check_qword_reg ())
6396 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6399 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6400 && i
.tm
.opcode_modifier
.no_wsuf
)
6402 else if (!check_word_reg ())
6405 else if (intel_syntax
6406 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6407 /* Do nothing if the instruction is going to ignore the prefix. */
6412 /* Undo the movsx/movzx change done above. */
6415 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6418 i
.suffix
= stackop_size
;
6419 if (stackop_size
== LONG_MNEM_SUFFIX
)
6421 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6422 .code16gcc directive to support 16-bit mode with
6423 32-bit address. For IRET without a suffix, generate
6424 16-bit IRET (opcode 0xcf) to return from an interrupt
6426 if (i
.tm
.base_opcode
== 0xcf)
6428 i
.suffix
= WORD_MNEM_SUFFIX
;
6429 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6431 /* Warn about changed behavior for segment register push/pop. */
6432 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6433 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6438 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6439 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6440 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6441 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6442 && i
.tm
.extension_opcode
<= 3)))
6447 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6449 i
.suffix
= QWORD_MNEM_SUFFIX
;
6454 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6455 i
.suffix
= LONG_MNEM_SUFFIX
;
6458 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6459 i
.suffix
= WORD_MNEM_SUFFIX
;
6465 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6466 /* Also cover lret/retf/iret in 64-bit mode. */
6467 || (flag_code
== CODE_64BIT
6468 && !i
.tm
.opcode_modifier
.no_lsuf
6469 && !i
.tm
.opcode_modifier
.no_qsuf
))
6470 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6471 /* Accept FLDENV et al without suffix. */
6472 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6474 unsigned int suffixes
, evex
= 0;
6476 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6477 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6479 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6481 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6483 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6485 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6488 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6489 also suitable for AT&T syntax mode, it was requested that this be
6490 restricted to just Intel syntax. */
6491 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6495 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6497 if (is_evex_encoding (&i
.tm
)
6498 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6500 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6501 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6502 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6503 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6504 if (!i
.tm
.opcode_modifier
.evex
6505 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6506 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6509 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6510 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6511 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6514 /* Any properly sized operand disambiguates the insn. */
6515 if (i
.types
[op
].bitfield
.xmmword
6516 || i
.types
[op
].bitfield
.ymmword
6517 || i
.types
[op
].bitfield
.zmmword
)
6519 suffixes
&= ~(7 << 6);
6524 if ((i
.flags
[op
] & Operand_Mem
)
6525 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6527 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6529 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6531 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6533 if (is_evex_encoding (&i
.tm
))
6539 /* Are multiple suffixes / operand sizes allowed? */
6540 if (suffixes
& (suffixes
- 1))
6543 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6544 || operand_check
== check_error
))
6546 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6549 if (operand_check
== check_error
)
6551 as_bad (_("no instruction mnemonic suffix given and "
6552 "no register operands; can't size `%s'"), i
.tm
.name
);
6555 if (operand_check
== check_warning
)
6556 as_warn (_("%s; using default for `%s'"),
6558 ? _("ambiguous operand size")
6559 : _("no instruction mnemonic suffix given and "
6560 "no register operands"),
6563 if (i
.tm
.opcode_modifier
.floatmf
)
6564 i
.suffix
= SHORT_MNEM_SUFFIX
;
6565 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6566 || (i
.tm
.base_opcode
== 0x63
6567 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6568 /* handled below */;
6570 i
.tm
.opcode_modifier
.evex
= evex
;
6571 else if (flag_code
== CODE_16BIT
)
6572 i
.suffix
= WORD_MNEM_SUFFIX
;
6573 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6574 i
.suffix
= LONG_MNEM_SUFFIX
;
6576 i
.suffix
= QWORD_MNEM_SUFFIX
;
6580 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6581 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6583 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6584 In AT&T syntax, if there is no suffix (warned about above), the default
6585 will be byte extension. */
6586 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6587 i
.tm
.base_opcode
|= 1;
6589 /* For further processing, the suffix should represent the destination
6590 (register). This is already the case when one was used with
6591 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6592 no suffix to begin with. */
6593 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6595 if (i
.types
[1].bitfield
.word
)
6596 i
.suffix
= WORD_MNEM_SUFFIX
;
6597 else if (i
.types
[1].bitfield
.qword
)
6598 i
.suffix
= QWORD_MNEM_SUFFIX
;
6600 i
.suffix
= LONG_MNEM_SUFFIX
;
6602 i
.tm
.opcode_modifier
.w
= 0;
6606 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6607 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6608 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6610 /* Change the opcode based on the operand size given by i.suffix. */
6613 /* Size floating point instruction. */
6614 case LONG_MNEM_SUFFIX
:
6615 if (i
.tm
.opcode_modifier
.floatmf
)
6617 i
.tm
.base_opcode
^= 4;
6621 case WORD_MNEM_SUFFIX
:
6622 case QWORD_MNEM_SUFFIX
:
6623 /* It's not a byte, select word/dword operation. */
6624 if (i
.tm
.opcode_modifier
.w
)
6627 i
.tm
.base_opcode
|= 8;
6629 i
.tm
.base_opcode
|= 1;
6632 case SHORT_MNEM_SUFFIX
:
6633 /* Now select between word & dword operations via the operand
6634 size prefix, except for instructions that will ignore this
6636 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6637 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6638 && !i
.tm
.opcode_modifier
.floatmf
6639 && !is_any_vex_encoding (&i
.tm
)
6640 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6641 || (flag_code
== CODE_64BIT
6642 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6644 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6646 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6647 prefix
= ADDR_PREFIX_OPCODE
;
6649 if (!add_prefix (prefix
))
6653 /* Set mode64 for an operand. */
6654 if (i
.suffix
== QWORD_MNEM_SUFFIX
6655 && flag_code
== CODE_64BIT
6656 && !i
.tm
.opcode_modifier
.norex64
6657 && !i
.tm
.opcode_modifier
.vexw
6658 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6660 && ! (i
.operands
== 2
6661 && i
.tm
.base_opcode
== 0x90
6662 && i
.tm
.extension_opcode
== None
6663 && i
.types
[0].bitfield
.instance
== Accum
6664 && i
.types
[0].bitfield
.qword
6665 && i
.types
[1].bitfield
.instance
== Accum
6666 && i
.types
[1].bitfield
.qword
))
6672 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6674 gas_assert (!i
.suffix
);
6675 gas_assert (i
.reg_operands
);
6677 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6680 /* The address size override prefix changes the size of the
6682 if (flag_code
== CODE_64BIT
6683 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6685 as_bad (_("16-bit addressing unavailable for `%s'"),
6690 if ((flag_code
== CODE_32BIT
6691 ? i
.op
[0].regs
->reg_type
.bitfield
.word
6692 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
6693 && !add_prefix (ADDR_PREFIX_OPCODE
))
6698 /* Check invalid register operand when the address size override
6699 prefix changes the size of register operands. */
6701 enum { need_word
, need_dword
, need_qword
} need
;
6703 if (flag_code
== CODE_32BIT
)
6704 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6705 else if (i
.prefix
[ADDR_PREFIX
])
6708 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6710 for (op
= 0; op
< i
.operands
; op
++)
6712 if (i
.types
[op
].bitfield
.class != Reg
)
6718 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6722 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6726 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
6731 as_bad (_("invalid register operand size for `%s'"),
6742 check_byte_reg (void)
6746 for (op
= i
.operands
; --op
>= 0;)
6748 /* Skip non-register operands. */
6749 if (i
.types
[op
].bitfield
.class != Reg
)
6752 /* If this is an eight bit register, it's OK. If it's the 16 or
6753 32 bit version of an eight bit register, we will just use the
6754 low portion, and that's OK too. */
6755 if (i
.types
[op
].bitfield
.byte
)
6758 /* I/O port address operands are OK too. */
6759 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6760 && i
.tm
.operand_types
[op
].bitfield
.word
)
6763 /* crc32 only wants its source operand checked here. */
6764 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6767 /* Any other register is bad. */
6768 if (i
.types
[op
].bitfield
.class == Reg
6769 || i
.types
[op
].bitfield
.class == RegMMX
6770 || i
.types
[op
].bitfield
.class == RegSIMD
6771 || i
.types
[op
].bitfield
.class == SReg
6772 || i
.types
[op
].bitfield
.class == RegCR
6773 || i
.types
[op
].bitfield
.class == RegDR
6774 || i
.types
[op
].bitfield
.class == RegTR
)
6776 as_bad (_("`%s%s' not allowed with `%s%c'"),
6778 i
.op
[op
].regs
->reg_name
,
6788 check_long_reg (void)
6792 for (op
= i
.operands
; --op
>= 0;)
6793 /* Skip non-register operands. */
6794 if (i
.types
[op
].bitfield
.class != Reg
)
6796 /* Reject eight bit registers, except where the template requires
6797 them. (eg. movzb) */
6798 else if (i
.types
[op
].bitfield
.byte
6799 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6800 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6801 && (i
.tm
.operand_types
[op
].bitfield
.word
6802 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6804 as_bad (_("`%s%s' not allowed with `%s%c'"),
6806 i
.op
[op
].regs
->reg_name
,
6811 /* Error if the e prefix on a general reg is missing. */
6812 else if (i
.types
[op
].bitfield
.word
6813 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6814 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6815 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6817 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6818 register_prefix
, i
.op
[op
].regs
->reg_name
,
6822 /* Warn if the r prefix on a general reg is present. */
6823 else if (i
.types
[op
].bitfield
.qword
6824 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6825 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6826 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6829 && i
.tm
.opcode_modifier
.toqword
6830 && i
.types
[0].bitfield
.class != RegSIMD
)
6832 /* Convert to QWORD. We want REX byte. */
6833 i
.suffix
= QWORD_MNEM_SUFFIX
;
6837 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6838 register_prefix
, i
.op
[op
].regs
->reg_name
,
6847 check_qword_reg (void)
6851 for (op
= i
.operands
; --op
>= 0; )
6852 /* Skip non-register operands. */
6853 if (i
.types
[op
].bitfield
.class != Reg
)
6855 /* Reject eight bit registers, except where the template requires
6856 them. (eg. movzb) */
6857 else if (i
.types
[op
].bitfield
.byte
6858 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6859 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6860 && (i
.tm
.operand_types
[op
].bitfield
.word
6861 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6863 as_bad (_("`%s%s' not allowed with `%s%c'"),
6865 i
.op
[op
].regs
->reg_name
,
6870 /* Warn if the r prefix on a general reg is missing. */
6871 else if ((i
.types
[op
].bitfield
.word
6872 || i
.types
[op
].bitfield
.dword
)
6873 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6874 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6875 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6877 /* Prohibit these changes in the 64bit mode, since the
6878 lowering is more complicated. */
6880 && i
.tm
.opcode_modifier
.todword
6881 && i
.types
[0].bitfield
.class != RegSIMD
)
6883 /* Convert to DWORD. We don't want REX byte. */
6884 i
.suffix
= LONG_MNEM_SUFFIX
;
6888 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6889 register_prefix
, i
.op
[op
].regs
->reg_name
,
6898 check_word_reg (void)
6901 for (op
= i
.operands
; --op
>= 0;)
6902 /* Skip non-register operands. */
6903 if (i
.types
[op
].bitfield
.class != Reg
)
6905 /* Reject eight bit registers, except where the template requires
6906 them. (eg. movzb) */
6907 else if (i
.types
[op
].bitfield
.byte
6908 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6909 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6910 && (i
.tm
.operand_types
[op
].bitfield
.word
6911 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6913 as_bad (_("`%s%s' not allowed with `%s%c'"),
6915 i
.op
[op
].regs
->reg_name
,
6920 /* Error if the e or r prefix on a general reg is present. */
6921 else if ((i
.types
[op
].bitfield
.dword
6922 || i
.types
[op
].bitfield
.qword
)
6923 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6924 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6925 && i
.tm
.operand_types
[op
].bitfield
.word
)
6927 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6928 register_prefix
, i
.op
[op
].regs
->reg_name
,
6936 update_imm (unsigned int j
)
6938 i386_operand_type overlap
= i
.types
[j
];
6939 if ((overlap
.bitfield
.imm8
6940 || overlap
.bitfield
.imm8s
6941 || overlap
.bitfield
.imm16
6942 || overlap
.bitfield
.imm32
6943 || overlap
.bitfield
.imm32s
6944 || overlap
.bitfield
.imm64
)
6945 && !operand_type_equal (&overlap
, &imm8
)
6946 && !operand_type_equal (&overlap
, &imm8s
)
6947 && !operand_type_equal (&overlap
, &imm16
)
6948 && !operand_type_equal (&overlap
, &imm32
)
6949 && !operand_type_equal (&overlap
, &imm32s
)
6950 && !operand_type_equal (&overlap
, &imm64
))
6954 i386_operand_type temp
;
6956 operand_type_set (&temp
, 0);
6957 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6959 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6960 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6962 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6963 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6964 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6966 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6967 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6970 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6973 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6974 || operand_type_equal (&overlap
, &imm16_32
)
6975 || operand_type_equal (&overlap
, &imm16_32s
))
6977 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6982 if (!operand_type_equal (&overlap
, &imm8
)
6983 && !operand_type_equal (&overlap
, &imm8s
)
6984 && !operand_type_equal (&overlap
, &imm16
)
6985 && !operand_type_equal (&overlap
, &imm32
)
6986 && !operand_type_equal (&overlap
, &imm32s
)
6987 && !operand_type_equal (&overlap
, &imm64
))
6989 as_bad (_("no instruction mnemonic suffix given; "
6990 "can't determine immediate size"));
6994 i
.types
[j
] = overlap
;
7004 /* Update the first 2 immediate operands. */
7005 n
= i
.operands
> 2 ? 2 : i
.operands
;
7008 for (j
= 0; j
< n
; j
++)
7009 if (update_imm (j
) == 0)
7012 /* The 3rd operand can't be immediate operand. */
7013 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7020 process_operands (void)
7022 /* Default segment register this instruction will use for memory
7023 accesses. 0 means unknown. This is only for optimizing out
7024 unnecessary segment overrides. */
7025 const seg_entry
*default_seg
= 0;
7027 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7029 unsigned int dupl
= i
.operands
;
7030 unsigned int dest
= dupl
- 1;
7033 /* The destination must be an xmm register. */
7034 gas_assert (i
.reg_operands
7035 && MAX_OPERANDS
> dupl
7036 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7038 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7039 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7041 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7043 /* Keep xmm0 for instructions with VEX prefix and 3
7045 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7046 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7051 /* We remove the first xmm0 and keep the number of
7052 operands unchanged, which in fact duplicates the
7054 for (j
= 1; j
< i
.operands
; j
++)
7056 i
.op
[j
- 1] = i
.op
[j
];
7057 i
.types
[j
- 1] = i
.types
[j
];
7058 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7059 i
.flags
[j
- 1] = i
.flags
[j
];
7063 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7065 gas_assert ((MAX_OPERANDS
- 1) > dupl
7066 && (i
.tm
.opcode_modifier
.vexsources
7069 /* Add the implicit xmm0 for instructions with VEX prefix
7071 for (j
= i
.operands
; j
> 0; j
--)
7073 i
.op
[j
] = i
.op
[j
- 1];
7074 i
.types
[j
] = i
.types
[j
- 1];
7075 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7076 i
.flags
[j
] = i
.flags
[j
- 1];
7079 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7080 i
.types
[0] = regxmm
;
7081 i
.tm
.operand_types
[0] = regxmm
;
7084 i
.reg_operands
+= 2;
7089 i
.op
[dupl
] = i
.op
[dest
];
7090 i
.types
[dupl
] = i
.types
[dest
];
7091 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7092 i
.flags
[dupl
] = i
.flags
[dest
];
7101 i
.op
[dupl
] = i
.op
[dest
];
7102 i
.types
[dupl
] = i
.types
[dest
];
7103 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7104 i
.flags
[dupl
] = i
.flags
[dest
];
7107 if (i
.tm
.opcode_modifier
.immext
)
7110 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7111 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7115 for (j
= 1; j
< i
.operands
; j
++)
7117 i
.op
[j
- 1] = i
.op
[j
];
7118 i
.types
[j
- 1] = i
.types
[j
];
7120 /* We need to adjust fields in i.tm since they are used by
7121 build_modrm_byte. */
7122 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7124 i
.flags
[j
- 1] = i
.flags
[j
];
7131 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7133 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7135 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7136 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7137 regnum
= register_number (i
.op
[1].regs
);
7138 first_reg_in_group
= regnum
& ~3;
7139 last_reg_in_group
= first_reg_in_group
+ 3;
7140 if (regnum
!= first_reg_in_group
)
7141 as_warn (_("source register `%s%s' implicitly denotes"
7142 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7143 register_prefix
, i
.op
[1].regs
->reg_name
,
7144 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7145 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7148 else if (i
.tm
.opcode_modifier
.regkludge
)
7150 /* The imul $imm, %reg instruction is converted into
7151 imul $imm, %reg, %reg, and the clr %reg instruction
7152 is converted into xor %reg, %reg. */
7154 unsigned int first_reg_op
;
7156 if (operand_type_check (i
.types
[0], reg
))
7160 /* Pretend we saw the extra register operand. */
7161 gas_assert (i
.reg_operands
== 1
7162 && i
.op
[first_reg_op
+ 1].regs
== 0);
7163 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7164 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7169 if (i
.tm
.opcode_modifier
.modrm
)
7171 /* The opcode is completed (modulo i.tm.extension_opcode which
7172 must be put into the modrm byte). Now, we make the modrm and
7173 index base bytes based on all the info we've collected. */
7175 default_seg
= build_modrm_byte ();
7177 else if (i
.types
[0].bitfield
.class == SReg
)
7179 if (flag_code
!= CODE_64BIT
7180 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7181 && i
.op
[0].regs
->reg_num
== 1
7182 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7183 && i
.op
[0].regs
->reg_num
< 4)
7185 as_bad (_("you can't `%s %s%s'"),
7186 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7189 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7191 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7192 i
.tm
.opcode_length
= 2;
7194 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7196 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7200 else if (i
.tm
.opcode_modifier
.isstring
)
7202 /* For the string instructions that allow a segment override
7203 on one of their operands, the default segment is ds. */
7206 else if (i
.short_form
)
7208 /* The register or float register operand is in operand
7210 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7212 /* Register goes in low 3 bits of opcode. */
7213 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7214 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7216 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7218 /* Warn about some common errors, but press on regardless.
7219 The first case can be generated by gcc (<= 2.8.1). */
7220 if (i
.operands
== 2)
7222 /* Reversed arguments on faddp, fsubp, etc. */
7223 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7224 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7225 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7229 /* Extraneous `l' suffix on fp insn. */
7230 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7231 register_prefix
, i
.op
[0].regs
->reg_name
);
7236 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7237 && i
.tm
.base_opcode
== 0x8d /* lea */
7238 && !is_any_vex_encoding(&i
.tm
))
7240 if (!quiet_warnings
)
7241 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7245 i
.prefix
[SEG_PREFIX
] = 0;
7249 /* If a segment was explicitly specified, and the specified segment
7250 is neither the default nor the one already recorded from a prefix,
7251 use an opcode prefix to select it. If we never figured out what
7252 the default segment is, then default_seg will be zero at this
7253 point, and the specified segment prefix will always be used. */
7255 && i
.seg
[0] != default_seg
7256 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7258 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7264 static const seg_entry
*
7265 build_modrm_byte (void)
7267 const seg_entry
*default_seg
= 0;
7268 unsigned int source
, dest
;
7271 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7274 unsigned int nds
, reg_slot
;
7277 dest
= i
.operands
- 1;
7280 /* There are 2 kinds of instructions:
7281 1. 5 operands: 4 register operands or 3 register operands
7282 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7283 VexW0 or VexW1. The destination must be either XMM, YMM or
7285 2. 4 operands: 4 register operands or 3 register operands
7286 plus 1 memory operand, with VexXDS. */
7287 gas_assert ((i
.reg_operands
== 4
7288 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7289 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7290 && i
.tm
.opcode_modifier
.vexw
7291 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7293 /* If VexW1 is set, the first non-immediate operand is the source and
7294 the second non-immediate one is encoded in the immediate operand. */
7295 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7297 source
= i
.imm_operands
;
7298 reg_slot
= i
.imm_operands
+ 1;
7302 source
= i
.imm_operands
+ 1;
7303 reg_slot
= i
.imm_operands
;
7306 if (i
.imm_operands
== 0)
7308 /* When there is no immediate operand, generate an 8bit
7309 immediate operand to encode the first operand. */
7310 exp
= &im_expressions
[i
.imm_operands
++];
7311 i
.op
[i
.operands
].imms
= exp
;
7312 i
.types
[i
.operands
] = imm8
;
7315 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7316 exp
->X_op
= O_constant
;
7317 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7318 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7322 gas_assert (i
.imm_operands
== 1);
7323 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7324 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7326 /* Turn on Imm8 again so that output_imm will generate it. */
7327 i
.types
[0].bitfield
.imm8
= 1;
7329 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7330 i
.op
[0].imms
->X_add_number
7331 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7332 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7335 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7336 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7341 /* i.reg_operands MUST be the number of real register operands;
7342 implicit registers do not count. If there are 3 register
7343 operands, it must be a instruction with VexNDS. For a
7344 instruction with VexNDD, the destination register is encoded
7345 in VEX prefix. If there are 4 register operands, it must be
7346 a instruction with VEX prefix and 3 sources. */
7347 if (i
.mem_operands
== 0
7348 && ((i
.reg_operands
== 2
7349 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7350 || (i
.reg_operands
== 3
7351 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7352 || (i
.reg_operands
== 4 && vex_3_sources
)))
7360 /* When there are 3 operands, one of them may be immediate,
7361 which may be the first or the last operand. Otherwise,
7362 the first operand must be shift count register (cl) or it
7363 is an instruction with VexNDS. */
7364 gas_assert (i
.imm_operands
== 1
7365 || (i
.imm_operands
== 0
7366 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7367 || (i
.types
[0].bitfield
.instance
== RegC
7368 && i
.types
[0].bitfield
.byte
))));
7369 if (operand_type_check (i
.types
[0], imm
)
7370 || (i
.types
[0].bitfield
.instance
== RegC
7371 && i
.types
[0].bitfield
.byte
))
7377 /* When there are 4 operands, the first two must be 8bit
7378 immediate operands. The source operand will be the 3rd
7381 For instructions with VexNDS, if the first operand
7382 an imm8, the source operand is the 2nd one. If the last
7383 operand is imm8, the source operand is the first one. */
7384 gas_assert ((i
.imm_operands
== 2
7385 && i
.types
[0].bitfield
.imm8
7386 && i
.types
[1].bitfield
.imm8
)
7387 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7388 && i
.imm_operands
== 1
7389 && (i
.types
[0].bitfield
.imm8
7390 || i
.types
[i
.operands
- 1].bitfield
.imm8
7392 if (i
.imm_operands
== 2)
7396 if (i
.types
[0].bitfield
.imm8
)
7403 if (is_evex_encoding (&i
.tm
))
7405 /* For EVEX instructions, when there are 5 operands, the
7406 first one must be immediate operand. If the second one
7407 is immediate operand, the source operand is the 3th
7408 one. If the last one is immediate operand, the source
7409 operand is the 2nd one. */
7410 gas_assert (i
.imm_operands
== 2
7411 && i
.tm
.opcode_modifier
.sae
7412 && operand_type_check (i
.types
[0], imm
));
7413 if (operand_type_check (i
.types
[1], imm
))
7415 else if (operand_type_check (i
.types
[4], imm
))
7429 /* RC/SAE operand could be between DEST and SRC. That happens
7430 when one operand is GPR and the other one is XMM/YMM/ZMM
7432 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7435 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7437 /* For instructions with VexNDS, the register-only source
7438 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7439 register. It is encoded in VEX prefix. */
7441 i386_operand_type op
;
7444 /* Check register-only source operand when two source
7445 operands are swapped. */
7446 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7447 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7455 op
= i
.tm
.operand_types
[vvvv
];
7456 if ((dest
+ 1) >= i
.operands
7457 || ((op
.bitfield
.class != Reg
7458 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7459 && op
.bitfield
.class != RegSIMD
7460 && !operand_type_equal (&op
, ®mask
)))
7462 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7468 /* One of the register operands will be encoded in the i.rm.reg
7469 field, the other in the combined i.rm.mode and i.rm.regmem
7470 fields. If no form of this instruction supports a memory
7471 destination operand, then we assume the source operand may
7472 sometimes be a memory operand and so we need to store the
7473 destination in the i.rm.reg field. */
7474 if (!i
.tm
.opcode_modifier
.regmem
7475 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7477 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7478 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7479 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7480 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7481 i
.has_regmmx
= TRUE
;
7482 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7483 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7485 if (i
.types
[dest
].bitfield
.zmmword
7486 || i
.types
[source
].bitfield
.zmmword
)
7487 i
.has_regzmm
= TRUE
;
7488 else if (i
.types
[dest
].bitfield
.ymmword
7489 || i
.types
[source
].bitfield
.ymmword
)
7490 i
.has_regymm
= TRUE
;
7492 i
.has_regxmm
= TRUE
;
7494 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7496 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7498 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7500 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7505 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7506 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7507 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7509 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7511 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7513 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7516 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7518 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7521 add_prefix (LOCK_PREFIX_OPCODE
);
7525 { /* If it's not 2 reg operands... */
7530 unsigned int fake_zero_displacement
= 0;
7533 for (op
= 0; op
< i
.operands
; op
++)
7534 if (i
.flags
[op
] & Operand_Mem
)
7536 gas_assert (op
< i
.operands
);
7538 if (i
.tm
.opcode_modifier
.vecsib
)
7540 if (i
.index_reg
->reg_num
== RegIZ
)
7543 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7546 i
.sib
.base
= NO_BASE_REGISTER
;
7547 i
.sib
.scale
= i
.log2_scale_factor
;
7548 i
.types
[op
].bitfield
.disp8
= 0;
7549 i
.types
[op
].bitfield
.disp16
= 0;
7550 i
.types
[op
].bitfield
.disp64
= 0;
7551 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7553 /* Must be 32 bit */
7554 i
.types
[op
].bitfield
.disp32
= 1;
7555 i
.types
[op
].bitfield
.disp32s
= 0;
7559 i
.types
[op
].bitfield
.disp32
= 0;
7560 i
.types
[op
].bitfield
.disp32s
= 1;
7563 i
.sib
.index
= i
.index_reg
->reg_num
;
7564 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7566 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7572 if (i
.base_reg
== 0)
7575 if (!i
.disp_operands
)
7576 fake_zero_displacement
= 1;
7577 if (i
.index_reg
== 0)
7579 i386_operand_type newdisp
;
7581 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7582 /* Operand is just <disp> */
7583 if (flag_code
== CODE_64BIT
)
7585 /* 64bit mode overwrites the 32bit absolute
7586 addressing by RIP relative addressing and
7587 absolute addressing is encoded by one of the
7588 redundant SIB forms. */
7589 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7590 i
.sib
.base
= NO_BASE_REGISTER
;
7591 i
.sib
.index
= NO_INDEX_REGISTER
;
7592 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7594 else if ((flag_code
== CODE_16BIT
)
7595 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7597 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7602 i
.rm
.regmem
= NO_BASE_REGISTER
;
7605 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7606 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7608 else if (!i
.tm
.opcode_modifier
.vecsib
)
7610 /* !i.base_reg && i.index_reg */
7611 if (i
.index_reg
->reg_num
== RegIZ
)
7612 i
.sib
.index
= NO_INDEX_REGISTER
;
7614 i
.sib
.index
= i
.index_reg
->reg_num
;
7615 i
.sib
.base
= NO_BASE_REGISTER
;
7616 i
.sib
.scale
= i
.log2_scale_factor
;
7617 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7618 i
.types
[op
].bitfield
.disp8
= 0;
7619 i
.types
[op
].bitfield
.disp16
= 0;
7620 i
.types
[op
].bitfield
.disp64
= 0;
7621 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7623 /* Must be 32 bit */
7624 i
.types
[op
].bitfield
.disp32
= 1;
7625 i
.types
[op
].bitfield
.disp32s
= 0;
7629 i
.types
[op
].bitfield
.disp32
= 0;
7630 i
.types
[op
].bitfield
.disp32s
= 1;
7632 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7636 /* RIP addressing for 64bit mode. */
7637 else if (i
.base_reg
->reg_num
== RegIP
)
7639 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7640 i
.rm
.regmem
= NO_BASE_REGISTER
;
7641 i
.types
[op
].bitfield
.disp8
= 0;
7642 i
.types
[op
].bitfield
.disp16
= 0;
7643 i
.types
[op
].bitfield
.disp32
= 0;
7644 i
.types
[op
].bitfield
.disp32s
= 1;
7645 i
.types
[op
].bitfield
.disp64
= 0;
7646 i
.flags
[op
] |= Operand_PCrel
;
7647 if (! i
.disp_operands
)
7648 fake_zero_displacement
= 1;
7650 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7652 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7653 switch (i
.base_reg
->reg_num
)
7656 if (i
.index_reg
== 0)
7658 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7659 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7663 if (i
.index_reg
== 0)
7666 if (operand_type_check (i
.types
[op
], disp
) == 0)
7668 /* fake (%bp) into 0(%bp) */
7669 i
.types
[op
].bitfield
.disp8
= 1;
7670 fake_zero_displacement
= 1;
7673 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7674 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7676 default: /* (%si) -> 4 or (%di) -> 5 */
7677 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7679 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7681 else /* i.base_reg and 32/64 bit mode */
7683 if (flag_code
== CODE_64BIT
7684 && operand_type_check (i
.types
[op
], disp
))
7686 i
.types
[op
].bitfield
.disp16
= 0;
7687 i
.types
[op
].bitfield
.disp64
= 0;
7688 if (i
.prefix
[ADDR_PREFIX
] == 0)
7690 i
.types
[op
].bitfield
.disp32
= 0;
7691 i
.types
[op
].bitfield
.disp32s
= 1;
7695 i
.types
[op
].bitfield
.disp32
= 1;
7696 i
.types
[op
].bitfield
.disp32s
= 0;
7700 if (!i
.tm
.opcode_modifier
.vecsib
)
7701 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7702 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7704 i
.sib
.base
= i
.base_reg
->reg_num
;
7705 /* x86-64 ignores REX prefix bit here to avoid decoder
7707 if (!(i
.base_reg
->reg_flags
& RegRex
)
7708 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7709 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7711 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7713 fake_zero_displacement
= 1;
7714 i
.types
[op
].bitfield
.disp8
= 1;
7716 i
.sib
.scale
= i
.log2_scale_factor
;
7717 if (i
.index_reg
== 0)
7719 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7720 /* <disp>(%esp) becomes two byte modrm with no index
7721 register. We've already stored the code for esp
7722 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7723 Any base register besides %esp will not use the
7724 extra modrm byte. */
7725 i
.sib
.index
= NO_INDEX_REGISTER
;
7727 else if (!i
.tm
.opcode_modifier
.vecsib
)
7729 if (i
.index_reg
->reg_num
== RegIZ
)
7730 i
.sib
.index
= NO_INDEX_REGISTER
;
7732 i
.sib
.index
= i
.index_reg
->reg_num
;
7733 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7734 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7739 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7740 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7744 if (!fake_zero_displacement
7748 fake_zero_displacement
= 1;
7749 if (i
.disp_encoding
== disp_encoding_8bit
)
7750 i
.types
[op
].bitfield
.disp8
= 1;
7752 i
.types
[op
].bitfield
.disp32
= 1;
7754 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7758 if (fake_zero_displacement
)
7760 /* Fakes a zero displacement assuming that i.types[op]
7761 holds the correct displacement size. */
7764 gas_assert (i
.op
[op
].disps
== 0);
7765 exp
= &disp_expressions
[i
.disp_operands
++];
7766 i
.op
[op
].disps
= exp
;
7767 exp
->X_op
= O_constant
;
7768 exp
->X_add_number
= 0;
7769 exp
->X_add_symbol
= (symbolS
*) 0;
7770 exp
->X_op_symbol
= (symbolS
*) 0;
7778 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7780 if (operand_type_check (i
.types
[0], imm
))
7781 i
.vex
.register_specifier
= NULL
;
7784 /* VEX.vvvv encodes one of the sources when the first
7785 operand is not an immediate. */
7786 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7787 i
.vex
.register_specifier
= i
.op
[0].regs
;
7789 i
.vex
.register_specifier
= i
.op
[1].regs
;
7792 /* Destination is a XMM register encoded in the ModRM.reg
7794 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7795 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7798 /* ModRM.rm and VEX.B encodes the other source. */
7799 if (!i
.mem_operands
)
7803 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7804 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7806 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7808 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7812 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7814 i
.vex
.register_specifier
= i
.op
[2].regs
;
7815 if (!i
.mem_operands
)
7818 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7819 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7823 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7824 (if any) based on i.tm.extension_opcode. Again, we must be
7825 careful to make sure that segment/control/debug/test/MMX
7826 registers are coded into the i.rm.reg field. */
7827 else if (i
.reg_operands
)
7830 unsigned int vex_reg
= ~0;
7832 for (op
= 0; op
< i
.operands
; op
++)
7834 if (i
.types
[op
].bitfield
.class == Reg
7835 || i
.types
[op
].bitfield
.class == RegBND
7836 || i
.types
[op
].bitfield
.class == RegMask
7837 || i
.types
[op
].bitfield
.class == SReg
7838 || i
.types
[op
].bitfield
.class == RegCR
7839 || i
.types
[op
].bitfield
.class == RegDR
7840 || i
.types
[op
].bitfield
.class == RegTR
)
7842 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7844 if (i
.types
[op
].bitfield
.zmmword
)
7845 i
.has_regzmm
= TRUE
;
7846 else if (i
.types
[op
].bitfield
.ymmword
)
7847 i
.has_regymm
= TRUE
;
7849 i
.has_regxmm
= TRUE
;
7852 if (i
.types
[op
].bitfield
.class == RegMMX
)
7854 i
.has_regmmx
= TRUE
;
7861 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7863 /* For instructions with VexNDS, the register-only
7864 source operand is encoded in VEX prefix. */
7865 gas_assert (mem
!= (unsigned int) ~0);
7870 gas_assert (op
< i
.operands
);
7874 /* Check register-only source operand when two source
7875 operands are swapped. */
7876 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7877 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7881 gas_assert (mem
== (vex_reg
+ 1)
7882 && op
< i
.operands
);
7887 gas_assert (vex_reg
< i
.operands
);
7891 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7893 /* For instructions with VexNDD, the register destination
7894 is encoded in VEX prefix. */
7895 if (i
.mem_operands
== 0)
7897 /* There is no memory operand. */
7898 gas_assert ((op
+ 2) == i
.operands
);
7903 /* There are only 2 non-immediate operands. */
7904 gas_assert (op
< i
.imm_operands
+ 2
7905 && i
.operands
== i
.imm_operands
+ 2);
7906 vex_reg
= i
.imm_operands
+ 1;
7910 gas_assert (op
< i
.operands
);
7912 if (vex_reg
!= (unsigned int) ~0)
7914 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7916 if ((type
->bitfield
.class != Reg
7917 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7918 && type
->bitfield
.class != RegSIMD
7919 && !operand_type_equal (type
, ®mask
))
7922 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7925 /* Don't set OP operand twice. */
7928 /* If there is an extension opcode to put here, the
7929 register number must be put into the regmem field. */
7930 if (i
.tm
.extension_opcode
!= None
)
7932 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7933 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7935 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7940 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7941 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7943 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7948 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7949 must set it to 3 to indicate this is a register operand
7950 in the regmem field. */
7951 if (!i
.mem_operands
)
7955 /* Fill in i.rm.reg field with extension opcode (if any). */
7956 if (i
.tm
.extension_opcode
!= None
)
7957 i
.rm
.reg
= i
.tm
.extension_opcode
;
7963 flip_code16 (unsigned int code16
)
7965 gas_assert (i
.tm
.operands
== 1);
7967 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7968 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7969 || i
.tm
.operand_types
[0].bitfield
.disp32s
7970 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7975 output_branch (void)
7981 relax_substateT subtype
;
7985 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7986 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7989 if (i
.prefix
[DATA_PREFIX
] != 0)
7993 code16
^= flip_code16(code16
);
7995 /* Pentium4 branch hints. */
7996 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7997 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8002 if (i
.prefix
[REX_PREFIX
] != 0)
8008 /* BND prefixed jump. */
8009 if (i
.prefix
[BND_PREFIX
] != 0)
8015 if (i
.prefixes
!= 0)
8016 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8018 /* It's always a symbol; End frag & setup for relax.
8019 Make sure there is enough room in this frag for the largest
8020 instruction we may generate in md_convert_frag. This is 2
8021 bytes for the opcode and room for the prefix and largest
8023 frag_grow (prefix
+ 2 + 4);
8024 /* Prefix and 1 opcode byte go in fr_fix. */
8025 p
= frag_more (prefix
+ 1);
8026 if (i
.prefix
[DATA_PREFIX
] != 0)
8027 *p
++ = DATA_PREFIX_OPCODE
;
8028 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8029 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8030 *p
++ = i
.prefix
[SEG_PREFIX
];
8031 if (i
.prefix
[BND_PREFIX
] != 0)
8032 *p
++ = BND_PREFIX_OPCODE
;
8033 if (i
.prefix
[REX_PREFIX
] != 0)
8034 *p
++ = i
.prefix
[REX_PREFIX
];
8035 *p
= i
.tm
.base_opcode
;
8037 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8038 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8039 else if (cpu_arch_flags
.bitfield
.cpui386
)
8040 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8042 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8045 sym
= i
.op
[0].disps
->X_add_symbol
;
8046 off
= i
.op
[0].disps
->X_add_number
;
8048 if (i
.op
[0].disps
->X_op
!= O_constant
8049 && i
.op
[0].disps
->X_op
!= O_symbol
)
8051 /* Handle complex expressions. */
8052 sym
= make_expr_symbol (i
.op
[0].disps
);
8056 /* 1 possible extra opcode + 4 byte displacement go in var part.
8057 Pass reloc in fr_var. */
8058 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8061 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8062 /* Return TRUE iff PLT32 relocation should be used for branching to
8066 need_plt32_p (symbolS
*s
)
8068 /* PLT32 relocation is ELF only. */
8073 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8074 krtld support it. */
8078 /* Since there is no need to prepare for PLT branch on x86-64, we
8079 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8080 be used as a marker for 32-bit PC-relative branches. */
8084 /* Weak or undefined symbol need PLT32 relocation. */
8085 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8088 /* Non-global symbol doesn't need PLT32 relocation. */
8089 if (! S_IS_EXTERNAL (s
))
8092 /* Other global symbols need PLT32 relocation. NB: Symbol with
8093 non-default visibilities are treated as normal global symbol
8094 so that PLT32 relocation can be used as a marker for 32-bit
8095 PC-relative branches. It is useful for linker relaxation. */
8106 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8108 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8110 /* This is a loop or jecxz type instruction. */
8112 if (i
.prefix
[ADDR_PREFIX
] != 0)
8114 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8117 /* Pentium4 branch hints. */
8118 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8119 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8121 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8130 if (flag_code
== CODE_16BIT
)
8133 if (i
.prefix
[DATA_PREFIX
] != 0)
8135 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8137 code16
^= flip_code16(code16
);
8145 /* BND prefixed jump. */
8146 if (i
.prefix
[BND_PREFIX
] != 0)
8148 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8152 if (i
.prefix
[REX_PREFIX
] != 0)
8154 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8158 if (i
.prefixes
!= 0)
8159 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8161 p
= frag_more (i
.tm
.opcode_length
+ size
);
8162 switch (i
.tm
.opcode_length
)
8165 *p
++ = i
.tm
.base_opcode
>> 8;
8168 *p
++ = i
.tm
.base_opcode
;
8174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8176 && jump_reloc
== NO_RELOC
8177 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8178 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8181 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8183 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8184 i
.op
[0].disps
, 1, jump_reloc
);
8186 /* All jumps handled here are signed, but don't use a signed limit
8187 check for 32 and 16 bit jumps as we want to allow wrap around at
8188 4G and 64k respectively. */
8190 fixP
->fx_signed
= 1;
8194 output_interseg_jump (void)
8202 if (flag_code
== CODE_16BIT
)
8206 if (i
.prefix
[DATA_PREFIX
] != 0)
8213 gas_assert (!i
.prefix
[REX_PREFIX
]);
8219 if (i
.prefixes
!= 0)
8220 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8222 /* 1 opcode; 2 segment; offset */
8223 p
= frag_more (prefix
+ 1 + 2 + size
);
8225 if (i
.prefix
[DATA_PREFIX
] != 0)
8226 *p
++ = DATA_PREFIX_OPCODE
;
8228 if (i
.prefix
[REX_PREFIX
] != 0)
8229 *p
++ = i
.prefix
[REX_PREFIX
];
8231 *p
++ = i
.tm
.base_opcode
;
8232 if (i
.op
[1].imms
->X_op
== O_constant
)
8234 offsetT n
= i
.op
[1].imms
->X_add_number
;
8237 && !fits_in_unsigned_word (n
)
8238 && !fits_in_signed_word (n
))
8240 as_bad (_("16-bit jump out of range"));
8243 md_number_to_chars (p
, n
, size
);
8246 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8247 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8248 if (i
.op
[0].imms
->X_op
!= O_constant
)
8249 as_bad (_("can't handle non absolute segment in `%s'"),
8251 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8259 asection
*seg
= now_seg
;
8260 subsegT subseg
= now_subseg
;
8262 unsigned int alignment
, align_size_1
;
8263 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8264 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8265 unsigned int padding
;
8267 if (!IS_ELF
|| !x86_used_note
)
8270 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8272 /* The .note.gnu.property section layout:
8274 Field Length Contents
8277 n_descsz 4 The note descriptor size
8278 n_type 4 NT_GNU_PROPERTY_TYPE_0
8280 n_desc n_descsz The program property array
8284 /* Create the .note.gnu.property section. */
8285 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8286 bfd_set_section_flags (sec
,
8293 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8304 bfd_set_section_alignment (sec
, alignment
);
8305 elf_section_type (sec
) = SHT_NOTE
;
8307 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8309 isa_1_descsz_raw
= 4 + 4 + 4;
8310 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8311 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8313 feature_2_descsz_raw
= isa_1_descsz
;
8314 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8316 feature_2_descsz_raw
+= 4 + 4 + 4;
8317 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8318 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8321 descsz
= feature_2_descsz
;
8322 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8323 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8325 /* Write n_namsz. */
8326 md_number_to_chars (p
, (valueT
) 4, 4);
8328 /* Write n_descsz. */
8329 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8332 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8335 memcpy (p
+ 4 * 3, "GNU", 4);
8337 /* Write 4-byte type. */
8338 md_number_to_chars (p
+ 4 * 4,
8339 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8341 /* Write 4-byte data size. */
8342 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8344 /* Write 4-byte data. */
8345 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8347 /* Zero out paddings. */
8348 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8350 memset (p
+ 4 * 7, 0, padding
);
8352 /* Write 4-byte type. */
8353 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8354 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8356 /* Write 4-byte data size. */
8357 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8359 /* Write 4-byte data. */
8360 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8361 (valueT
) x86_feature_2_used
, 4);
8363 /* Zero out paddings. */
8364 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8366 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8368 /* We probably can't restore the current segment, for there likely
8371 subseg_set (seg
, subseg
);
8376 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8377 const char *frag_now_ptr
)
8379 unsigned int len
= 0;
8381 if (start_frag
!= frag_now
)
8383 const fragS
*fr
= start_frag
;
8388 } while (fr
&& fr
!= frag_now
);
8391 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8394 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8395 be macro-fused with conditional jumps.
8396 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8397 or is one of the following format:
8410 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8412 /* No RIP address. */
8413 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8416 /* No VEX/EVEX encoding. */
8417 if (is_any_vex_encoding (&i
.tm
))
8420 /* add, sub without add/sub m, imm. */
8421 if (i
.tm
.base_opcode
<= 5
8422 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8423 || ((i
.tm
.base_opcode
| 3) == 0x83
8424 && (i
.tm
.extension_opcode
== 0x5
8425 || i
.tm
.extension_opcode
== 0x0)))
8427 *mf_cmp_p
= mf_cmp_alu_cmp
;
8428 return !(i
.mem_operands
&& i
.imm_operands
);
8431 /* and without and m, imm. */
8432 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8433 || ((i
.tm
.base_opcode
| 3) == 0x83
8434 && i
.tm
.extension_opcode
== 0x4))
8436 *mf_cmp_p
= mf_cmp_test_and
;
8437 return !(i
.mem_operands
&& i
.imm_operands
);
8440 /* test without test m imm. */
8441 if ((i
.tm
.base_opcode
| 1) == 0x85
8442 || (i
.tm
.base_opcode
| 1) == 0xa9
8443 || ((i
.tm
.base_opcode
| 1) == 0xf7
8444 && i
.tm
.extension_opcode
== 0))
8446 *mf_cmp_p
= mf_cmp_test_and
;
8447 return !(i
.mem_operands
&& i
.imm_operands
);
8450 /* cmp without cmp m, imm. */
8451 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8452 || ((i
.tm
.base_opcode
| 3) == 0x83
8453 && (i
.tm
.extension_opcode
== 0x7)))
8455 *mf_cmp_p
= mf_cmp_alu_cmp
;
8456 return !(i
.mem_operands
&& i
.imm_operands
);
8459 /* inc, dec without inc/dec m. */
8460 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8461 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8462 || ((i
.tm
.base_opcode
| 1) == 0xff
8463 && i
.tm
.extension_opcode
<= 0x1))
8465 *mf_cmp_p
= mf_cmp_incdec
;
8466 return !i
.mem_operands
;
8472 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8475 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8477 /* NB: Don't work with COND_JUMP86 without i386. */
8478 if (!align_branch_power
8479 || now_seg
== absolute_section
8480 || !cpu_arch_flags
.bitfield
.cpui386
8481 || !(align_branch
& align_branch_fused_bit
))
8484 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8486 if (last_insn
.kind
== last_insn_other
8487 || last_insn
.seg
!= now_seg
)
8490 as_warn_where (last_insn
.file
, last_insn
.line
,
8491 _("`%s` skips -malign-branch-boundary on `%s`"),
8492 last_insn
.name
, i
.tm
.name
);
8498 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8501 add_branch_prefix_frag_p (void)
8503 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8504 to PadLock instructions since they include prefixes in opcode. */
8505 if (!align_branch_power
8506 || !align_branch_prefix_size
8507 || now_seg
== absolute_section
8508 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8509 || !cpu_arch_flags
.bitfield
.cpui386
)
8512 /* Don't add prefix if it is a prefix or there is no operand in case
8513 that segment prefix is special. */
8514 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8517 if (last_insn
.kind
== last_insn_other
8518 || last_insn
.seg
!= now_seg
)
8522 as_warn_where (last_insn
.file
, last_insn
.line
,
8523 _("`%s` skips -malign-branch-boundary on `%s`"),
8524 last_insn
.name
, i
.tm
.name
);
8529 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8532 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8533 enum mf_jcc_kind
*mf_jcc_p
)
8537 /* NB: Don't work with COND_JUMP86 without i386. */
8538 if (!align_branch_power
8539 || now_seg
== absolute_section
8540 || !cpu_arch_flags
.bitfield
.cpui386
)
8545 /* Check for jcc and direct jmp. */
8546 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8548 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8550 *branch_p
= align_branch_jmp
;
8551 add_padding
= align_branch
& align_branch_jmp_bit
;
8555 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8556 igore the lowest bit. */
8557 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8558 *branch_p
= align_branch_jcc
;
8559 if ((align_branch
& align_branch_jcc_bit
))
8563 else if (is_any_vex_encoding (&i
.tm
))
8565 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8568 *branch_p
= align_branch_ret
;
8569 if ((align_branch
& align_branch_ret_bit
))
8574 /* Check for indirect jmp, direct and indirect calls. */
8575 if (i
.tm
.base_opcode
== 0xe8)
8578 *branch_p
= align_branch_call
;
8579 if ((align_branch
& align_branch_call_bit
))
8582 else if (i
.tm
.base_opcode
== 0xff
8583 && (i
.tm
.extension_opcode
== 2
8584 || i
.tm
.extension_opcode
== 4))
8586 /* Indirect call and jmp. */
8587 *branch_p
= align_branch_indirect
;
8588 if ((align_branch
& align_branch_indirect_bit
))
8595 && (i
.op
[0].disps
->X_op
== O_symbol
8596 || (i
.op
[0].disps
->X_op
== O_subtract
8597 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8599 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8600 /* No padding to call to global or undefined tls_get_addr. */
8601 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8602 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8608 && last_insn
.kind
!= last_insn_other
8609 && last_insn
.seg
== now_seg
)
8612 as_warn_where (last_insn
.file
, last_insn
.line
,
8613 _("`%s` skips -malign-branch-boundary on `%s`"),
8614 last_insn
.name
, i
.tm
.name
);
8624 fragS
*insn_start_frag
;
8625 offsetT insn_start_off
;
8626 fragS
*fragP
= NULL
;
8627 enum align_branch_kind branch
= align_branch_none
;
8628 /* The initializer is arbitrary just to avoid uninitialized error.
8629 it's actually either assigned in add_branch_padding_frag_p
8630 or never be used. */
8631 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
8633 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8634 if (IS_ELF
&& x86_used_note
)
8636 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8637 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8638 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8639 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8640 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8641 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8642 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8643 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8644 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8645 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8646 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8647 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8648 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8649 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8650 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8651 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8652 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8653 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8654 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8655 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8656 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8657 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8658 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8659 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8660 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8661 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8662 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8663 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8664 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8665 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8666 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8667 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8668 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8669 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8670 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8671 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8672 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8673 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8674 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8675 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8676 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8677 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8678 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8679 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8680 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8681 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8682 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8683 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8684 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8685 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8687 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8688 || i
.tm
.cpu_flags
.bitfield
.cpu287
8689 || i
.tm
.cpu_flags
.bitfield
.cpu387
8690 || i
.tm
.cpu_flags
.bitfield
.cpu687
8691 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8692 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8694 || i
.tm
.base_opcode
== 0xf77 /* emms */
8695 || i
.tm
.base_opcode
== 0xf0e /* femms */
8696 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
8697 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
8698 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8700 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8702 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8704 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8705 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8706 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8707 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8708 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8709 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8710 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8711 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8712 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8716 /* Tie dwarf2 debug info to the address at the start of the insn.
8717 We can't do this after the insn has been output as the current
8718 frag may have been closed off. eg. by frag_var. */
8719 dwarf2_emit_insn (0);
8721 insn_start_frag
= frag_now
;
8722 insn_start_off
= frag_now_fix ();
8724 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
8727 /* Branch can be 8 bytes. Leave some room for prefixes. */
8728 unsigned int max_branch_padding_size
= 14;
8730 /* Align section to boundary. */
8731 record_alignment (now_seg
, align_branch_power
);
8733 /* Make room for padding. */
8734 frag_grow (max_branch_padding_size
);
8736 /* Start of the padding. */
8741 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8742 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8745 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
8746 fragP
->tc_frag_data
.branch_type
= branch
;
8747 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8751 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8753 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8754 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8756 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8757 output_interseg_jump ();
8760 /* Output normal instructions here. */
8764 unsigned int prefix
;
8765 enum mf_cmp_kind mf_cmp
;
8768 && (i
.tm
.base_opcode
== 0xfaee8
8769 || i
.tm
.base_opcode
== 0xfaef0
8770 || i
.tm
.base_opcode
== 0xfaef8))
8772 /* Encode lfence, mfence, and sfence as
8773 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8774 offsetT val
= 0x240483f0ULL
;
8776 md_number_to_chars (p
, val
, 5);
8780 /* Some processors fail on LOCK prefix. This options makes
8781 assembler ignore LOCK prefix and serves as a workaround. */
8782 if (omit_lock_prefix
)
8784 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8786 i
.prefix
[LOCK_PREFIX
] = 0;
8790 /* Skip if this is a branch. */
8792 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
8794 /* Make room for padding. */
8795 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8800 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8801 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8804 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
8805 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8806 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8808 else if (add_branch_prefix_frag_p ())
8810 unsigned int max_prefix_size
= align_branch_prefix_size
;
8812 /* Make room for padding. */
8813 frag_grow (max_prefix_size
);
8818 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8819 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8822 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8825 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8826 don't need the explicit prefix. */
8827 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8829 switch (i
.tm
.opcode_length
)
8832 if (i
.tm
.base_opcode
& 0xff000000)
8834 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8835 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8836 || prefix
!= REPE_PREFIX_OPCODE
8837 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8838 add_prefix (prefix
);
8842 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8844 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8845 add_prefix (prefix
);
8851 /* Check for pseudo prefixes. */
8852 as_bad_where (insn_start_frag
->fr_file
,
8853 insn_start_frag
->fr_line
,
8854 _("pseudo prefix without instruction"));
8860 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8861 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8862 R_X86_64_GOTTPOFF relocation so that linker can safely
8863 perform IE->LE optimization. A dummy REX_OPCODE prefix
8864 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8865 relocation for GDesc -> IE/LE optimization. */
8866 if (x86_elf_abi
== X86_64_X32_ABI
8868 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8869 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8870 && i
.prefix
[REX_PREFIX
] == 0)
8871 add_prefix (REX_OPCODE
);
8874 /* The prefix bytes. */
8875 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8877 FRAG_APPEND_1_CHAR (*q
);
8881 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8886 /* REX byte is encoded in VEX prefix. */
8890 FRAG_APPEND_1_CHAR (*q
);
8893 /* There should be no other prefixes for instructions
8898 /* For EVEX instructions i.vrex should become 0 after
8899 build_evex_prefix. For VEX instructions upper 16 registers
8900 aren't available, so VREX should be 0. */
8903 /* Now the VEX prefix. */
8904 p
= frag_more (i
.vex
.length
);
8905 for (j
= 0; j
< i
.vex
.length
; j
++)
8906 p
[j
] = i
.vex
.bytes
[j
];
8909 /* Now the opcode; be careful about word order here! */
8910 if (i
.tm
.opcode_length
== 1)
8912 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8916 switch (i
.tm
.opcode_length
)
8920 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8921 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8925 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8935 /* Put out high byte first: can't use md_number_to_chars! */
8936 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8937 *p
= i
.tm
.base_opcode
& 0xff;
8940 /* Now the modrm byte and sib byte (if present). */
8941 if (i
.tm
.opcode_modifier
.modrm
)
8943 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8946 /* If i.rm.regmem == ESP (4)
8947 && i.rm.mode != (Register mode)
8949 ==> need second modrm byte. */
8950 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8952 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8953 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8955 | i
.sib
.scale
<< 6));
8958 if (i
.disp_operands
)
8959 output_disp (insn_start_frag
, insn_start_off
);
8962 output_imm (insn_start_frag
, insn_start_off
);
8965 * frag_now_fix () returning plain abs_section_offset when we're in the
8966 * absolute section, and abs_section_offset not getting updated as data
8967 * gets added to the frag breaks the logic below.
8969 if (now_seg
!= absolute_section
)
8971 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8973 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8977 /* NB: Don't add prefix with GOTPC relocation since
8978 output_disp() above depends on the fixed encoding
8979 length. Can't add prefix with TLS relocation since
8980 it breaks TLS linker optimization. */
8981 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8982 /* Prefix count on the current instruction. */
8983 unsigned int count
= i
.vex
.length
;
8985 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8986 /* REX byte is encoded in VEX/EVEX prefix. */
8987 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8990 /* Count prefixes for extended opcode maps. */
8992 switch (i
.tm
.opcode_length
)
8995 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8998 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9010 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9019 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9022 /* Set the maximum prefix size in BRANCH_PREFIX
9024 if (fragP
->tc_frag_data
.max_bytes
> max
)
9025 fragP
->tc_frag_data
.max_bytes
= max
;
9026 if (fragP
->tc_frag_data
.max_bytes
> count
)
9027 fragP
->tc_frag_data
.max_bytes
-= count
;
9029 fragP
->tc_frag_data
.max_bytes
= 0;
9033 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9035 unsigned int max_prefix_size
;
9036 if (align_branch_prefix_size
> max
)
9037 max_prefix_size
= max
;
9039 max_prefix_size
= align_branch_prefix_size
;
9040 if (max_prefix_size
> count
)
9041 fragP
->tc_frag_data
.max_prefix_length
9042 = max_prefix_size
- count
;
9045 /* Use existing segment prefix if possible. Use CS
9046 segment prefix in 64-bit mode. In 32-bit mode, use SS
9047 segment prefix with ESP/EBP base register and use DS
9048 segment prefix without ESP/EBP base register. */
9049 if (i
.prefix
[SEG_PREFIX
])
9050 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9051 else if (flag_code
== CODE_64BIT
)
9052 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9054 && (i
.base_reg
->reg_num
== 4
9055 || i
.base_reg
->reg_num
== 5))
9056 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9058 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9063 /* NB: Don't work with COND_JUMP86 without i386. */
9064 if (align_branch_power
9065 && now_seg
!= absolute_section
9066 && cpu_arch_flags
.bitfield
.cpui386
)
9068 /* Terminate each frag so that we can add prefix and check for
9070 frag_wane (frag_now
);
9077 pi ("" /*line*/, &i
);
9079 #endif /* DEBUG386 */
9082 /* Return the size of the displacement operand N. */
9085 disp_size (unsigned int n
)
9089 if (i
.types
[n
].bitfield
.disp64
)
9091 else if (i
.types
[n
].bitfield
.disp8
)
9093 else if (i
.types
[n
].bitfield
.disp16
)
9098 /* Return the size of the immediate operand N. */
9101 imm_size (unsigned int n
)
9104 if (i
.types
[n
].bitfield
.imm64
)
9106 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9108 else if (i
.types
[n
].bitfield
.imm16
)
9114 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9119 for (n
= 0; n
< i
.operands
; n
++)
9121 if (operand_type_check (i
.types
[n
], disp
))
9123 if (i
.op
[n
].disps
->X_op
== O_constant
)
9125 int size
= disp_size (n
);
9126 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9128 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9130 p
= frag_more (size
);
9131 md_number_to_chars (p
, val
, size
);
9135 enum bfd_reloc_code_real reloc_type
;
9136 int size
= disp_size (n
);
9137 int sign
= i
.types
[n
].bitfield
.disp32s
;
9138 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9141 /* We can't have 8 bit displacement here. */
9142 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9144 /* The PC relative address is computed relative
9145 to the instruction boundary, so in case immediate
9146 fields follows, we need to adjust the value. */
9147 if (pcrel
&& i
.imm_operands
)
9152 for (n1
= 0; n1
< i
.operands
; n1
++)
9153 if (operand_type_check (i
.types
[n1
], imm
))
9155 /* Only one immediate is allowed for PC
9156 relative address. */
9157 gas_assert (sz
== 0);
9159 i
.op
[n
].disps
->X_add_number
-= sz
;
9161 /* We should find the immediate. */
9162 gas_assert (sz
!= 0);
9165 p
= frag_more (size
);
9166 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9168 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9169 && (((reloc_type
== BFD_RELOC_32
9170 || reloc_type
== BFD_RELOC_X86_64_32S
9171 || (reloc_type
== BFD_RELOC_64
9173 && (i
.op
[n
].disps
->X_op
== O_symbol
9174 || (i
.op
[n
].disps
->X_op
== O_add
9175 && ((symbol_get_value_expression
9176 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9178 || reloc_type
== BFD_RELOC_32_PCREL
))
9182 reloc_type
= BFD_RELOC_386_GOTPC
;
9183 i
.has_gotpc_tls_reloc
= TRUE
;
9184 i
.op
[n
].imms
->X_add_number
+=
9185 encoding_length (insn_start_frag
, insn_start_off
, p
);
9187 else if (reloc_type
== BFD_RELOC_64
)
9188 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9190 /* Don't do the adjustment for x86-64, as there
9191 the pcrel addressing is relative to the _next_
9192 insn, and that is taken care of in other code. */
9193 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9195 else if (align_branch_power
)
9199 case BFD_RELOC_386_TLS_GD
:
9200 case BFD_RELOC_386_TLS_LDM
:
9201 case BFD_RELOC_386_TLS_IE
:
9202 case BFD_RELOC_386_TLS_IE_32
:
9203 case BFD_RELOC_386_TLS_GOTIE
:
9204 case BFD_RELOC_386_TLS_GOTDESC
:
9205 case BFD_RELOC_386_TLS_DESC_CALL
:
9206 case BFD_RELOC_X86_64_TLSGD
:
9207 case BFD_RELOC_X86_64_TLSLD
:
9208 case BFD_RELOC_X86_64_GOTTPOFF
:
9209 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9210 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9211 i
.has_gotpc_tls_reloc
= TRUE
;
9216 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9217 size
, i
.op
[n
].disps
, pcrel
,
9219 /* Check for "call/jmp *mem", "mov mem, %reg",
9220 "test %reg, mem" and "binop mem, %reg" where binop
9221 is one of adc, add, and, cmp, or, sbb, sub, xor
9222 instructions without data prefix. Always generate
9223 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9224 if (i
.prefix
[DATA_PREFIX
] == 0
9225 && (generate_relax_relocations
9228 && i
.rm
.regmem
== 5))
9230 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9231 && !is_any_vex_encoding(&i
.tm
)
9232 && ((i
.operands
== 1
9233 && i
.tm
.base_opcode
== 0xff
9234 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9236 && (i
.tm
.base_opcode
== 0x8b
9237 || i
.tm
.base_opcode
== 0x85
9238 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9242 fixP
->fx_tcbit
= i
.rex
!= 0;
9244 && (i
.base_reg
->reg_num
== RegIP
))
9245 fixP
->fx_tcbit2
= 1;
9248 fixP
->fx_tcbit2
= 1;
9256 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9261 for (n
= 0; n
< i
.operands
; n
++)
9263 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9264 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9267 if (operand_type_check (i
.types
[n
], imm
))
9269 if (i
.op
[n
].imms
->X_op
== O_constant
)
9271 int size
= imm_size (n
);
9274 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9276 p
= frag_more (size
);
9277 md_number_to_chars (p
, val
, size
);
9281 /* Not absolute_section.
9282 Need a 32-bit fixup (don't support 8bit
9283 non-absolute imms). Try to support other
9285 enum bfd_reloc_code_real reloc_type
;
9286 int size
= imm_size (n
);
9289 if (i
.types
[n
].bitfield
.imm32s
9290 && (i
.suffix
== QWORD_MNEM_SUFFIX
9291 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9296 p
= frag_more (size
);
9297 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9299 /* This is tough to explain. We end up with this one if we
9300 * have operands that look like
9301 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9302 * obtain the absolute address of the GOT, and it is strongly
9303 * preferable from a performance point of view to avoid using
9304 * a runtime relocation for this. The actual sequence of
9305 * instructions often look something like:
9310 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9312 * The call and pop essentially return the absolute address
9313 * of the label .L66 and store it in %ebx. The linker itself
9314 * will ultimately change the first operand of the addl so
9315 * that %ebx points to the GOT, but to keep things simple, the
9316 * .o file must have this operand set so that it generates not
9317 * the absolute address of .L66, but the absolute address of
9318 * itself. This allows the linker itself simply treat a GOTPC
9319 * relocation as asking for a pcrel offset to the GOT to be
9320 * added in, and the addend of the relocation is stored in the
9321 * operand field for the instruction itself.
9323 * Our job here is to fix the operand so that it would add
9324 * the correct offset so that %ebx would point to itself. The
9325 * thing that is tricky is that .-.L66 will point to the
9326 * beginning of the instruction, so we need to further modify
9327 * the operand so that it will point to itself. There are
9328 * other cases where you have something like:
9330 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9332 * and here no correction would be required. Internally in
9333 * the assembler we treat operands of this form as not being
9334 * pcrel since the '.' is explicitly mentioned, and I wonder
9335 * whether it would simplify matters to do it this way. Who
9336 * knows. In earlier versions of the PIC patches, the
9337 * pcrel_adjust field was used to store the correction, but
9338 * since the expression is not pcrel, I felt it would be
9339 * confusing to do it this way. */
9341 if ((reloc_type
== BFD_RELOC_32
9342 || reloc_type
== BFD_RELOC_X86_64_32S
9343 || reloc_type
== BFD_RELOC_64
)
9345 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9346 && (i
.op
[n
].imms
->X_op
== O_symbol
9347 || (i
.op
[n
].imms
->X_op
== O_add
9348 && ((symbol_get_value_expression
9349 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9353 reloc_type
= BFD_RELOC_386_GOTPC
;
9355 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9357 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9358 i
.has_gotpc_tls_reloc
= TRUE
;
9359 i
.op
[n
].imms
->X_add_number
+=
9360 encoding_length (insn_start_frag
, insn_start_off
, p
);
9362 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9363 i
.op
[n
].imms
, 0, reloc_type
);
9369 /* x86_cons_fix_new is called via the expression parsing code when a
9370 reloc is needed. We use this hook to get the correct .got reloc. */
9371 static int cons_sign
= -1;
9374 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9375 expressionS
*exp
, bfd_reloc_code_real_type r
)
9377 r
= reloc (len
, 0, cons_sign
, r
);
9380 if (exp
->X_op
== O_secrel
)
9382 exp
->X_op
= O_symbol
;
9383 r
= BFD_RELOC_32_SECREL
;
9387 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9390 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9391 purpose of the `.dc.a' internal pseudo-op. */
9394 x86_address_bytes (void)
9396 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9398 return stdoutput
->arch_info
->bits_per_address
/ 8;
9401 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9403 # define lex_got(reloc, adjust, types) NULL
9405 /* Parse operands of the form
9406 <symbol>@GOTOFF+<nnn>
9407 and similar .plt or .got references.
9409 If we find one, set up the correct relocation in RELOC and copy the
9410 input string, minus the `@GOTOFF' into a malloc'd buffer for
9411 parsing by the calling routine. Return this buffer, and if ADJUST
9412 is non-null set it to the length of the string we removed from the
9413 input line. Otherwise return NULL. */
9415 lex_got (enum bfd_reloc_code_real
*rel
,
9417 i386_operand_type
*types
)
9419 /* Some of the relocations depend on the size of what field is to
9420 be relocated. But in our callers i386_immediate and i386_displacement
9421 we don't yet know the operand size (this will be set by insn
9422 matching). Hence we record the word32 relocation here,
9423 and adjust the reloc according to the real size in reloc(). */
9424 static const struct {
9427 const enum bfd_reloc_code_real rel
[2];
9428 const i386_operand_type types64
;
9430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9431 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9433 OPERAND_TYPE_IMM32_64
},
9435 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9436 BFD_RELOC_X86_64_PLTOFF64
},
9437 OPERAND_TYPE_IMM64
},
9438 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9439 BFD_RELOC_X86_64_PLT32
},
9440 OPERAND_TYPE_IMM32_32S_DISP32
},
9441 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9442 BFD_RELOC_X86_64_GOTPLT64
},
9443 OPERAND_TYPE_IMM64_DISP64
},
9444 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9445 BFD_RELOC_X86_64_GOTOFF64
},
9446 OPERAND_TYPE_IMM64_DISP64
},
9447 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9448 BFD_RELOC_X86_64_GOTPCREL
},
9449 OPERAND_TYPE_IMM32_32S_DISP32
},
9450 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9451 BFD_RELOC_X86_64_TLSGD
},
9452 OPERAND_TYPE_IMM32_32S_DISP32
},
9453 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9454 _dummy_first_bfd_reloc_code_real
},
9455 OPERAND_TYPE_NONE
},
9456 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9457 BFD_RELOC_X86_64_TLSLD
},
9458 OPERAND_TYPE_IMM32_32S_DISP32
},
9459 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9460 BFD_RELOC_X86_64_GOTTPOFF
},
9461 OPERAND_TYPE_IMM32_32S_DISP32
},
9462 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9463 BFD_RELOC_X86_64_TPOFF32
},
9464 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9465 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9466 _dummy_first_bfd_reloc_code_real
},
9467 OPERAND_TYPE_NONE
},
9468 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9469 BFD_RELOC_X86_64_DTPOFF32
},
9470 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9471 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9472 _dummy_first_bfd_reloc_code_real
},
9473 OPERAND_TYPE_NONE
},
9474 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9475 _dummy_first_bfd_reloc_code_real
},
9476 OPERAND_TYPE_NONE
},
9477 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9478 BFD_RELOC_X86_64_GOT32
},
9479 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9480 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9481 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9482 OPERAND_TYPE_IMM32_32S_DISP32
},
9483 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9484 BFD_RELOC_X86_64_TLSDESC_CALL
},
9485 OPERAND_TYPE_IMM32_32S_DISP32
},
9490 #if defined (OBJ_MAYBE_ELF)
9495 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9496 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9499 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9501 int len
= gotrel
[j
].len
;
9502 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9504 if (gotrel
[j
].rel
[object_64bit
] != 0)
9507 char *tmpbuf
, *past_reloc
;
9509 *rel
= gotrel
[j
].rel
[object_64bit
];
9513 if (flag_code
!= CODE_64BIT
)
9515 types
->bitfield
.imm32
= 1;
9516 types
->bitfield
.disp32
= 1;
9519 *types
= gotrel
[j
].types64
;
9522 if (j
!= 0 && GOT_symbol
== NULL
)
9523 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9525 /* The length of the first part of our input line. */
9526 first
= cp
- input_line_pointer
;
9528 /* The second part goes from after the reloc token until
9529 (and including) an end_of_line char or comma. */
9530 past_reloc
= cp
+ 1 + len
;
9532 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9534 second
= cp
+ 1 - past_reloc
;
9536 /* Allocate and copy string. The trailing NUL shouldn't
9537 be necessary, but be safe. */
9538 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9539 memcpy (tmpbuf
, input_line_pointer
, first
);
9540 if (second
!= 0 && *past_reloc
!= ' ')
9541 /* Replace the relocation token with ' ', so that
9542 errors like foo@GOTOFF1 will be detected. */
9543 tmpbuf
[first
++] = ' ';
9545 /* Increment length by 1 if the relocation token is
9550 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9551 tmpbuf
[first
+ second
] = '\0';
9555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9556 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9561 /* Might be a symbol version string. Don't as_bad here. */
9570 /* Parse operands of the form
9571 <symbol>@SECREL32+<nnn>
9573 If we find one, set up the correct relocation in RELOC and copy the
9574 input string, minus the `@SECREL32' into a malloc'd buffer for
9575 parsing by the calling routine. Return this buffer, and if ADJUST
9576 is non-null set it to the length of the string we removed from the
9577 input line. Otherwise return NULL.
9579 This function is copied from the ELF version above adjusted for PE targets. */
9582 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9583 int *adjust ATTRIBUTE_UNUSED
,
9584 i386_operand_type
*types
)
9590 const enum bfd_reloc_code_real rel
[2];
9591 const i386_operand_type types64
;
9595 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9596 BFD_RELOC_32_SECREL
},
9597 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9603 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9604 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9607 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9609 int len
= gotrel
[j
].len
;
9611 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9613 if (gotrel
[j
].rel
[object_64bit
] != 0)
9616 char *tmpbuf
, *past_reloc
;
9618 *rel
= gotrel
[j
].rel
[object_64bit
];
9624 if (flag_code
!= CODE_64BIT
)
9626 types
->bitfield
.imm32
= 1;
9627 types
->bitfield
.disp32
= 1;
9630 *types
= gotrel
[j
].types64
;
9633 /* The length of the first part of our input line. */
9634 first
= cp
- input_line_pointer
;
9636 /* The second part goes from after the reloc token until
9637 (and including) an end_of_line char or comma. */
9638 past_reloc
= cp
+ 1 + len
;
9640 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9642 second
= cp
+ 1 - past_reloc
;
9644 /* Allocate and copy string. The trailing NUL shouldn't
9645 be necessary, but be safe. */
9646 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9647 memcpy (tmpbuf
, input_line_pointer
, first
);
9648 if (second
!= 0 && *past_reloc
!= ' ')
9649 /* Replace the relocation token with ' ', so that
9650 errors like foo@SECLREL321 will be detected. */
9651 tmpbuf
[first
++] = ' ';
9652 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9653 tmpbuf
[first
+ second
] = '\0';
9657 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9658 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9663 /* Might be a symbol version string. Don't as_bad here. */
9669 bfd_reloc_code_real_type
9670 x86_cons (expressionS
*exp
, int size
)
9672 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9674 intel_syntax
= -intel_syntax
;
9677 if (size
== 4 || (object_64bit
&& size
== 8))
9679 /* Handle @GOTOFF and the like in an expression. */
9681 char *gotfree_input_line
;
9684 save
= input_line_pointer
;
9685 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9686 if (gotfree_input_line
)
9687 input_line_pointer
= gotfree_input_line
;
9691 if (gotfree_input_line
)
9693 /* expression () has merrily parsed up to the end of line,
9694 or a comma - in the wrong buffer. Transfer how far
9695 input_line_pointer has moved to the right buffer. */
9696 input_line_pointer
= (save
9697 + (input_line_pointer
- gotfree_input_line
)
9699 free (gotfree_input_line
);
9700 if (exp
->X_op
== O_constant
9701 || exp
->X_op
== O_absent
9702 || exp
->X_op
== O_illegal
9703 || exp
->X_op
== O_register
9704 || exp
->X_op
== O_big
)
9706 char c
= *input_line_pointer
;
9707 *input_line_pointer
= 0;
9708 as_bad (_("missing or invalid expression `%s'"), save
);
9709 *input_line_pointer
= c
;
9711 else if ((got_reloc
== BFD_RELOC_386_PLT32
9712 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9713 && exp
->X_op
!= O_symbol
)
9715 char c
= *input_line_pointer
;
9716 *input_line_pointer
= 0;
9717 as_bad (_("invalid PLT expression `%s'"), save
);
9718 *input_line_pointer
= c
;
9725 intel_syntax
= -intel_syntax
;
9728 i386_intel_simplify (exp
);
9734 signed_cons (int size
)
9736 if (flag_code
== CODE_64BIT
)
9744 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9751 if (exp
.X_op
== O_symbol
)
9752 exp
.X_op
= O_secrel
;
9754 emit_expr (&exp
, 4);
9756 while (*input_line_pointer
++ == ',');
9758 input_line_pointer
--;
9759 demand_empty_rest_of_line ();
9763 /* Handle Vector operations. */
9766 check_VecOperations (char *op_string
, char *op_end
)
9768 const reg_entry
*mask
;
9773 && (op_end
== NULL
|| op_string
< op_end
))
9776 if (*op_string
== '{')
9780 /* Check broadcasts. */
9781 if (strncmp (op_string
, "1to", 3) == 0)
9786 goto duplicated_vec_op
;
9789 if (*op_string
== '8')
9791 else if (*op_string
== '4')
9793 else if (*op_string
== '2')
9795 else if (*op_string
== '1'
9796 && *(op_string
+1) == '6')
9803 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9808 broadcast_op
.type
= bcst_type
;
9809 broadcast_op
.operand
= this_operand
;
9810 broadcast_op
.bytes
= 0;
9811 i
.broadcast
= &broadcast_op
;
9813 /* Check masking operation. */
9814 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9816 /* k0 can't be used for write mask. */
9817 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9819 as_bad (_("`%s%s' can't be used for write mask"),
9820 register_prefix
, mask
->reg_name
);
9826 mask_op
.mask
= mask
;
9827 mask_op
.zeroing
= 0;
9828 mask_op
.operand
= this_operand
;
9834 goto duplicated_vec_op
;
9836 i
.mask
->mask
= mask
;
9838 /* Only "{z}" is allowed here. No need to check
9839 zeroing mask explicitly. */
9840 if (i
.mask
->operand
!= this_operand
)
9842 as_bad (_("invalid write mask `%s'"), saved
);
9849 /* Check zeroing-flag for masking operation. */
9850 else if (*op_string
== 'z')
9854 mask_op
.mask
= NULL
;
9855 mask_op
.zeroing
= 1;
9856 mask_op
.operand
= this_operand
;
9861 if (i
.mask
->zeroing
)
9864 as_bad (_("duplicated `%s'"), saved
);
9868 i
.mask
->zeroing
= 1;
9870 /* Only "{%k}" is allowed here. No need to check mask
9871 register explicitly. */
9872 if (i
.mask
->operand
!= this_operand
)
9874 as_bad (_("invalid zeroing-masking `%s'"),
9883 goto unknown_vec_op
;
9885 if (*op_string
!= '}')
9887 as_bad (_("missing `}' in `%s'"), saved
);
9892 /* Strip whitespace since the addition of pseudo prefixes
9893 changed how the scrubber treats '{'. */
9894 if (is_space_char (*op_string
))
9900 /* We don't know this one. */
9901 as_bad (_("unknown vector operation: `%s'"), saved
);
9905 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9907 as_bad (_("zeroing-masking only allowed with write mask"));
9915 i386_immediate (char *imm_start
)
9917 char *save_input_line_pointer
;
9918 char *gotfree_input_line
;
9921 i386_operand_type types
;
9923 operand_type_set (&types
, ~0);
9925 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9927 as_bad (_("at most %d immediate operands are allowed"),
9928 MAX_IMMEDIATE_OPERANDS
);
9932 exp
= &im_expressions
[i
.imm_operands
++];
9933 i
.op
[this_operand
].imms
= exp
;
9935 if (is_space_char (*imm_start
))
9938 save_input_line_pointer
= input_line_pointer
;
9939 input_line_pointer
= imm_start
;
9941 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9942 if (gotfree_input_line
)
9943 input_line_pointer
= gotfree_input_line
;
9945 exp_seg
= expression (exp
);
9949 /* Handle vector operations. */
9950 if (*input_line_pointer
== '{')
9952 input_line_pointer
= check_VecOperations (input_line_pointer
,
9954 if (input_line_pointer
== NULL
)
9958 if (*input_line_pointer
)
9959 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9961 input_line_pointer
= save_input_line_pointer
;
9962 if (gotfree_input_line
)
9964 free (gotfree_input_line
);
9966 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9967 exp
->X_op
= O_illegal
;
9970 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9974 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9975 i386_operand_type types
, const char *imm_start
)
9977 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9980 as_bad (_("missing or invalid immediate expression `%s'"),
9984 else if (exp
->X_op
== O_constant
)
9986 /* Size it properly later. */
9987 i
.types
[this_operand
].bitfield
.imm64
= 1;
9988 /* If not 64bit, sign extend val. */
9989 if (flag_code
!= CODE_64BIT
9990 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9992 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9994 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9995 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9996 && exp_seg
!= absolute_section
9997 && exp_seg
!= text_section
9998 && exp_seg
!= data_section
9999 && exp_seg
!= bss_section
10000 && exp_seg
!= undefined_section
10001 && !bfd_is_com_section (exp_seg
))
10003 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10007 else if (!intel_syntax
&& exp_seg
== reg_section
)
10010 as_bad (_("illegal immediate register operand %s"), imm_start
);
10015 /* This is an address. The size of the address will be
10016 determined later, depending on destination register,
10017 suffix, or the default for the section. */
10018 i
.types
[this_operand
].bitfield
.imm8
= 1;
10019 i
.types
[this_operand
].bitfield
.imm16
= 1;
10020 i
.types
[this_operand
].bitfield
.imm32
= 1;
10021 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10022 i
.types
[this_operand
].bitfield
.imm64
= 1;
10023 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10031 i386_scale (char *scale
)
10034 char *save
= input_line_pointer
;
10036 input_line_pointer
= scale
;
10037 val
= get_absolute_expression ();
10042 i
.log2_scale_factor
= 0;
10045 i
.log2_scale_factor
= 1;
10048 i
.log2_scale_factor
= 2;
10051 i
.log2_scale_factor
= 3;
10055 char sep
= *input_line_pointer
;
10057 *input_line_pointer
= '\0';
10058 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10060 *input_line_pointer
= sep
;
10061 input_line_pointer
= save
;
10065 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10067 as_warn (_("scale factor of %d without an index register"),
10068 1 << i
.log2_scale_factor
);
10069 i
.log2_scale_factor
= 0;
10071 scale
= input_line_pointer
;
10072 input_line_pointer
= save
;
10077 i386_displacement (char *disp_start
, char *disp_end
)
10081 char *save_input_line_pointer
;
10082 char *gotfree_input_line
;
10084 i386_operand_type bigdisp
, types
= anydisp
;
10087 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10089 as_bad (_("at most %d displacement operands are allowed"),
10090 MAX_MEMORY_OPERANDS
);
10094 operand_type_set (&bigdisp
, 0);
10096 || i
.types
[this_operand
].bitfield
.baseindex
10097 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10098 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10100 i386_addressing_mode ();
10101 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10102 if (flag_code
== CODE_64BIT
)
10106 bigdisp
.bitfield
.disp32s
= 1;
10107 bigdisp
.bitfield
.disp64
= 1;
10110 bigdisp
.bitfield
.disp32
= 1;
10112 else if ((flag_code
== CODE_16BIT
) ^ override
)
10113 bigdisp
.bitfield
.disp16
= 1;
10115 bigdisp
.bitfield
.disp32
= 1;
10119 /* For PC-relative branches, the width of the displacement may be
10120 dependent upon data size, but is never dependent upon address size.
10121 Also make sure to not unintentionally match against a non-PC-relative
10122 branch template. */
10123 static templates aux_templates
;
10124 const insn_template
*t
= current_templates
->start
;
10125 bfd_boolean has_intel64
= FALSE
;
10127 aux_templates
.start
= t
;
10128 while (++t
< current_templates
->end
)
10130 if (t
->opcode_modifier
.jump
10131 != current_templates
->start
->opcode_modifier
.jump
)
10133 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10134 has_intel64
= TRUE
;
10136 if (t
< current_templates
->end
)
10138 aux_templates
.end
= t
;
10139 current_templates
= &aux_templates
;
10142 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10143 if (flag_code
== CODE_64BIT
)
10145 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10146 && (!intel64
|| !has_intel64
))
10147 bigdisp
.bitfield
.disp16
= 1;
10149 bigdisp
.bitfield
.disp32s
= 1;
10154 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10156 : LONG_MNEM_SUFFIX
));
10157 bigdisp
.bitfield
.disp32
= 1;
10158 if ((flag_code
== CODE_16BIT
) ^ override
)
10160 bigdisp
.bitfield
.disp32
= 0;
10161 bigdisp
.bitfield
.disp16
= 1;
10165 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10168 exp
= &disp_expressions
[i
.disp_operands
];
10169 i
.op
[this_operand
].disps
= exp
;
10171 save_input_line_pointer
= input_line_pointer
;
10172 input_line_pointer
= disp_start
;
10173 END_STRING_AND_SAVE (disp_end
);
10175 #ifndef GCC_ASM_O_HACK
10176 #define GCC_ASM_O_HACK 0
10179 END_STRING_AND_SAVE (disp_end
+ 1);
10180 if (i
.types
[this_operand
].bitfield
.baseIndex
10181 && displacement_string_end
[-1] == '+')
10183 /* This hack is to avoid a warning when using the "o"
10184 constraint within gcc asm statements.
10187 #define _set_tssldt_desc(n,addr,limit,type) \
10188 __asm__ __volatile__ ( \
10189 "movw %w2,%0\n\t" \
10190 "movw %w1,2+%0\n\t" \
10191 "rorl $16,%1\n\t" \
10192 "movb %b1,4+%0\n\t" \
10193 "movb %4,5+%0\n\t" \
10194 "movb $0,6+%0\n\t" \
10195 "movb %h1,7+%0\n\t" \
10197 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10199 This works great except that the output assembler ends
10200 up looking a bit weird if it turns out that there is
10201 no offset. You end up producing code that looks like:
10214 So here we provide the missing zero. */
10216 *displacement_string_end
= '0';
10219 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10220 if (gotfree_input_line
)
10221 input_line_pointer
= gotfree_input_line
;
10223 exp_seg
= expression (exp
);
10225 SKIP_WHITESPACE ();
10226 if (*input_line_pointer
)
10227 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10229 RESTORE_END_STRING (disp_end
+ 1);
10231 input_line_pointer
= save_input_line_pointer
;
10232 if (gotfree_input_line
)
10234 free (gotfree_input_line
);
10236 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10237 exp
->X_op
= O_illegal
;
10240 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10242 RESTORE_END_STRING (disp_end
);
10248 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10249 i386_operand_type types
, const char *disp_start
)
10251 i386_operand_type bigdisp
;
10254 /* We do this to make sure that the section symbol is in
10255 the symbol table. We will ultimately change the relocation
10256 to be relative to the beginning of the section. */
10257 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10258 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10259 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10261 if (exp
->X_op
!= O_symbol
)
10264 if (S_IS_LOCAL (exp
->X_add_symbol
)
10265 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10266 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10267 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10268 exp
->X_op
= O_subtract
;
10269 exp
->X_op_symbol
= GOT_symbol
;
10270 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10271 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10272 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10273 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10275 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10278 else if (exp
->X_op
== O_absent
10279 || exp
->X_op
== O_illegal
10280 || exp
->X_op
== O_big
)
10283 as_bad (_("missing or invalid displacement expression `%s'"),
10288 else if (flag_code
== CODE_64BIT
10289 && !i
.prefix
[ADDR_PREFIX
]
10290 && exp
->X_op
== O_constant
)
10292 /* Since displacement is signed extended to 64bit, don't allow
10293 disp32 and turn off disp32s if they are out of range. */
10294 i
.types
[this_operand
].bitfield
.disp32
= 0;
10295 if (!fits_in_signed_long (exp
->X_add_number
))
10297 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10298 if (i
.types
[this_operand
].bitfield
.baseindex
)
10300 as_bad (_("0x%lx out range of signed 32bit displacement"),
10301 (long) exp
->X_add_number
);
10307 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10308 else if (exp
->X_op
!= O_constant
10309 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10310 && exp_seg
!= absolute_section
10311 && exp_seg
!= text_section
10312 && exp_seg
!= data_section
10313 && exp_seg
!= bss_section
10314 && exp_seg
!= undefined_section
10315 && !bfd_is_com_section (exp_seg
))
10317 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10322 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10323 /* Constants get taken care of by optimize_disp(). */
10324 && exp
->X_op
!= O_constant
)
10325 i
.types
[this_operand
].bitfield
.disp8
= 1;
10327 /* Check if this is a displacement only operand. */
10328 bigdisp
= i
.types
[this_operand
];
10329 bigdisp
.bitfield
.disp8
= 0;
10330 bigdisp
.bitfield
.disp16
= 0;
10331 bigdisp
.bitfield
.disp32
= 0;
10332 bigdisp
.bitfield
.disp32s
= 0;
10333 bigdisp
.bitfield
.disp64
= 0;
10334 if (operand_type_all_zero (&bigdisp
))
10335 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10341 /* Return the active addressing mode, taking address override and
10342 registers forming the address into consideration. Update the
10343 address override prefix if necessary. */
10345 static enum flag_code
10346 i386_addressing_mode (void)
10348 enum flag_code addr_mode
;
10350 if (i
.prefix
[ADDR_PREFIX
])
10351 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10352 else if (flag_code
== CODE_16BIT
10353 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10354 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10355 from md_assemble() by "is not a valid base/index expression"
10356 when there is a base and/or index. */
10357 && !i
.types
[this_operand
].bitfield
.baseindex
)
10359 /* MPX insn memory operands with neither base nor index must be forced
10360 to use 32-bit addressing in 16-bit mode. */
10361 addr_mode
= CODE_32BIT
;
10362 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10364 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10365 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10369 addr_mode
= flag_code
;
10371 #if INFER_ADDR_PREFIX
10372 if (i
.mem_operands
== 0)
10374 /* Infer address prefix from the first memory operand. */
10375 const reg_entry
*addr_reg
= i
.base_reg
;
10377 if (addr_reg
== NULL
)
10378 addr_reg
= i
.index_reg
;
10382 if (addr_reg
->reg_type
.bitfield
.dword
)
10383 addr_mode
= CODE_32BIT
;
10384 else if (flag_code
!= CODE_64BIT
10385 && addr_reg
->reg_type
.bitfield
.word
)
10386 addr_mode
= CODE_16BIT
;
10388 if (addr_mode
!= flag_code
)
10390 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10392 /* Change the size of any displacement too. At most one
10393 of Disp16 or Disp32 is set.
10394 FIXME. There doesn't seem to be any real need for
10395 separate Disp16 and Disp32 flags. The same goes for
10396 Imm16 and Imm32. Removing them would probably clean
10397 up the code quite a lot. */
10398 if (flag_code
!= CODE_64BIT
10399 && (i
.types
[this_operand
].bitfield
.disp16
10400 || i
.types
[this_operand
].bitfield
.disp32
))
10401 i
.types
[this_operand
]
10402 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10412 /* Make sure the memory operand we've been dealt is valid.
10413 Return 1 on success, 0 on a failure. */
10416 i386_index_check (const char *operand_string
)
10418 const char *kind
= "base/index";
10419 enum flag_code addr_mode
= i386_addressing_mode ();
10421 if (current_templates
->start
->opcode_modifier
.isstring
10422 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10423 && (current_templates
->end
[-1].opcode_modifier
.isstring
10424 || i
.mem_operands
))
10426 /* Memory operands of string insns are special in that they only allow
10427 a single register (rDI, rSI, or rBX) as their memory address. */
10428 const reg_entry
*expected_reg
;
10429 static const char *di_si
[][2] =
10435 static const char *bx
[] = { "ebx", "bx", "rbx" };
10437 kind
= "string address";
10439 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10441 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10442 - IS_STRING_ES_OP0
;
10445 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10446 || ((!i
.mem_operands
!= !intel_syntax
)
10447 && current_templates
->end
[-1].operand_types
[1]
10448 .bitfield
.baseindex
))
10450 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10453 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10455 if (i
.base_reg
!= expected_reg
10457 || operand_type_check (i
.types
[this_operand
], disp
))
10459 /* The second memory operand must have the same size as
10463 && !((addr_mode
== CODE_64BIT
10464 && i
.base_reg
->reg_type
.bitfield
.qword
)
10465 || (addr_mode
== CODE_32BIT
10466 ? i
.base_reg
->reg_type
.bitfield
.dword
10467 : i
.base_reg
->reg_type
.bitfield
.word
)))
10470 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10472 intel_syntax
? '[' : '(',
10474 expected_reg
->reg_name
,
10475 intel_syntax
? ']' : ')');
10482 as_bad (_("`%s' is not a valid %s expression"),
10483 operand_string
, kind
);
10488 if (addr_mode
!= CODE_16BIT
)
10490 /* 32-bit/64-bit checks. */
10492 && ((addr_mode
== CODE_64BIT
10493 ? !i
.base_reg
->reg_type
.bitfield
.qword
10494 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10495 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10496 || i
.base_reg
->reg_num
== RegIZ
))
10498 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10499 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10500 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10501 && ((addr_mode
== CODE_64BIT
10502 ? !i
.index_reg
->reg_type
.bitfield
.qword
10503 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10504 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10507 /* bndmk, bndldx, and bndstx have special restrictions. */
10508 if (current_templates
->start
->base_opcode
== 0xf30f1b
10509 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10511 /* They cannot use RIP-relative addressing. */
10512 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10514 as_bad (_("`%s' cannot be used here"), operand_string
);
10518 /* bndldx and bndstx ignore their scale factor. */
10519 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10520 && i
.log2_scale_factor
)
10521 as_warn (_("register scaling is being ignored here"));
10526 /* 16-bit checks. */
10528 && (!i
.base_reg
->reg_type
.bitfield
.word
10529 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10531 && (!i
.index_reg
->reg_type
.bitfield
.word
10532 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10534 && i
.base_reg
->reg_num
< 6
10535 && i
.index_reg
->reg_num
>= 6
10536 && i
.log2_scale_factor
== 0))))
10543 /* Handle vector immediates. */
10546 RC_SAE_immediate (const char *imm_start
)
10548 unsigned int match_found
, j
;
10549 const char *pstr
= imm_start
;
10557 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10559 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10563 rc_op
.type
= RC_NamesTable
[j
].type
;
10564 rc_op
.operand
= this_operand
;
10565 i
.rounding
= &rc_op
;
10569 as_bad (_("duplicated `%s'"), imm_start
);
10572 pstr
+= RC_NamesTable
[j
].len
;
10580 if (*pstr
++ != '}')
10582 as_bad (_("Missing '}': '%s'"), imm_start
);
10585 /* RC/SAE immediate string should contain nothing more. */;
10588 as_bad (_("Junk after '}': '%s'"), imm_start
);
10592 exp
= &im_expressions
[i
.imm_operands
++];
10593 i
.op
[this_operand
].imms
= exp
;
10595 exp
->X_op
= O_constant
;
10596 exp
->X_add_number
= 0;
10597 exp
->X_add_symbol
= (symbolS
*) 0;
10598 exp
->X_op_symbol
= (symbolS
*) 0;
10600 i
.types
[this_operand
].bitfield
.imm8
= 1;
10604 /* Only string instructions can have a second memory operand, so
10605 reduce current_templates to just those if it contains any. */
10607 maybe_adjust_templates (void)
10609 const insn_template
*t
;
10611 gas_assert (i
.mem_operands
== 1);
10613 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10614 if (t
->opcode_modifier
.isstring
)
10617 if (t
< current_templates
->end
)
10619 static templates aux_templates
;
10620 bfd_boolean recheck
;
10622 aux_templates
.start
= t
;
10623 for (; t
< current_templates
->end
; ++t
)
10624 if (!t
->opcode_modifier
.isstring
)
10626 aux_templates
.end
= t
;
10628 /* Determine whether to re-check the first memory operand. */
10629 recheck
= (aux_templates
.start
!= current_templates
->start
10630 || t
!= current_templates
->end
);
10632 current_templates
= &aux_templates
;
10636 i
.mem_operands
= 0;
10637 if (i
.memop1_string
!= NULL
10638 && i386_index_check (i
.memop1_string
) == 0)
10640 i
.mem_operands
= 1;
10647 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10651 i386_att_operand (char *operand_string
)
10653 const reg_entry
*r
;
10655 char *op_string
= operand_string
;
10657 if (is_space_char (*op_string
))
10660 /* We check for an absolute prefix (differentiating,
10661 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10662 if (*op_string
== ABSOLUTE_PREFIX
)
10665 if (is_space_char (*op_string
))
10667 i
.jumpabsolute
= TRUE
;
10670 /* Check if operand is a register. */
10671 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10673 i386_operand_type temp
;
10675 /* Check for a segment override by searching for ':' after a
10676 segment register. */
10677 op_string
= end_op
;
10678 if (is_space_char (*op_string
))
10680 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10682 switch (r
->reg_num
)
10685 i
.seg
[i
.mem_operands
] = &es
;
10688 i
.seg
[i
.mem_operands
] = &cs
;
10691 i
.seg
[i
.mem_operands
] = &ss
;
10694 i
.seg
[i
.mem_operands
] = &ds
;
10697 i
.seg
[i
.mem_operands
] = &fs
;
10700 i
.seg
[i
.mem_operands
] = &gs
;
10704 /* Skip the ':' and whitespace. */
10706 if (is_space_char (*op_string
))
10709 if (!is_digit_char (*op_string
)
10710 && !is_identifier_char (*op_string
)
10711 && *op_string
!= '('
10712 && *op_string
!= ABSOLUTE_PREFIX
)
10714 as_bad (_("bad memory operand `%s'"), op_string
);
10717 /* Handle case of %es:*foo. */
10718 if (*op_string
== ABSOLUTE_PREFIX
)
10721 if (is_space_char (*op_string
))
10723 i
.jumpabsolute
= TRUE
;
10725 goto do_memory_reference
;
10728 /* Handle vector operations. */
10729 if (*op_string
== '{')
10731 op_string
= check_VecOperations (op_string
, NULL
);
10732 if (op_string
== NULL
)
10738 as_bad (_("junk `%s' after register"), op_string
);
10741 temp
= r
->reg_type
;
10742 temp
.bitfield
.baseindex
= 0;
10743 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10745 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10746 i
.op
[this_operand
].regs
= r
;
10749 else if (*op_string
== REGISTER_PREFIX
)
10751 as_bad (_("bad register name `%s'"), op_string
);
10754 else if (*op_string
== IMMEDIATE_PREFIX
)
10757 if (i
.jumpabsolute
)
10759 as_bad (_("immediate operand illegal with absolute jump"));
10762 if (!i386_immediate (op_string
))
10765 else if (RC_SAE_immediate (operand_string
))
10767 /* If it is a RC or SAE immediate, do nothing. */
10770 else if (is_digit_char (*op_string
)
10771 || is_identifier_char (*op_string
)
10772 || *op_string
== '"'
10773 || *op_string
== '(')
10775 /* This is a memory reference of some sort. */
10778 /* Start and end of displacement string expression (if found). */
10779 char *displacement_string_start
;
10780 char *displacement_string_end
;
10783 do_memory_reference
:
10784 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10786 if ((i
.mem_operands
== 1
10787 && !current_templates
->start
->opcode_modifier
.isstring
)
10788 || i
.mem_operands
== 2)
10790 as_bad (_("too many memory references for `%s'"),
10791 current_templates
->start
->name
);
10795 /* Check for base index form. We detect the base index form by
10796 looking for an ')' at the end of the operand, searching
10797 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10799 base_string
= op_string
+ strlen (op_string
);
10801 /* Handle vector operations. */
10802 vop_start
= strchr (op_string
, '{');
10803 if (vop_start
&& vop_start
< base_string
)
10805 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10807 base_string
= vop_start
;
10811 if (is_space_char (*base_string
))
10814 /* If we only have a displacement, set-up for it to be parsed later. */
10815 displacement_string_start
= op_string
;
10816 displacement_string_end
= base_string
+ 1;
10818 if (*base_string
== ')')
10821 unsigned int parens_balanced
= 1;
10822 /* We've already checked that the number of left & right ()'s are
10823 equal, so this loop will not be infinite. */
10827 if (*base_string
== ')')
10829 if (*base_string
== '(')
10832 while (parens_balanced
);
10834 temp_string
= base_string
;
10836 /* Skip past '(' and whitespace. */
10838 if (is_space_char (*base_string
))
10841 if (*base_string
== ','
10842 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10845 displacement_string_end
= temp_string
;
10847 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10851 base_string
= end_op
;
10852 if (is_space_char (*base_string
))
10856 /* There may be an index reg or scale factor here. */
10857 if (*base_string
== ',')
10860 if (is_space_char (*base_string
))
10863 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10866 base_string
= end_op
;
10867 if (is_space_char (*base_string
))
10869 if (*base_string
== ',')
10872 if (is_space_char (*base_string
))
10875 else if (*base_string
!= ')')
10877 as_bad (_("expecting `,' or `)' "
10878 "after index register in `%s'"),
10883 else if (*base_string
== REGISTER_PREFIX
)
10885 end_op
= strchr (base_string
, ',');
10888 as_bad (_("bad register name `%s'"), base_string
);
10892 /* Check for scale factor. */
10893 if (*base_string
!= ')')
10895 char *end_scale
= i386_scale (base_string
);
10900 base_string
= end_scale
;
10901 if (is_space_char (*base_string
))
10903 if (*base_string
!= ')')
10905 as_bad (_("expecting `)' "
10906 "after scale factor in `%s'"),
10911 else if (!i
.index_reg
)
10913 as_bad (_("expecting index register or scale factor "
10914 "after `,'; got '%c'"),
10919 else if (*base_string
!= ')')
10921 as_bad (_("expecting `,' or `)' "
10922 "after base register in `%s'"),
10927 else if (*base_string
== REGISTER_PREFIX
)
10929 end_op
= strchr (base_string
, ',');
10932 as_bad (_("bad register name `%s'"), base_string
);
10937 /* If there's an expression beginning the operand, parse it,
10938 assuming displacement_string_start and
10939 displacement_string_end are meaningful. */
10940 if (displacement_string_start
!= displacement_string_end
)
10942 if (!i386_displacement (displacement_string_start
,
10943 displacement_string_end
))
10947 /* Special case for (%dx) while doing input/output op. */
10949 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10950 && i
.base_reg
->reg_type
.bitfield
.word
10951 && i
.index_reg
== 0
10952 && i
.log2_scale_factor
== 0
10953 && i
.seg
[i
.mem_operands
] == 0
10954 && !operand_type_check (i
.types
[this_operand
], disp
))
10956 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10960 if (i386_index_check (operand_string
) == 0)
10962 i
.flags
[this_operand
] |= Operand_Mem
;
10963 if (i
.mem_operands
== 0)
10964 i
.memop1_string
= xstrdup (operand_string
);
10969 /* It's not a memory operand; argh! */
10970 as_bad (_("invalid char %s beginning operand %d `%s'"),
10971 output_invalid (*op_string
),
10976 return 1; /* Normal return. */
10979 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10980 that an rs_machine_dependent frag may reach. */
10983 i386_frag_max_var (fragS
*frag
)
10985 /* The only relaxable frags are for jumps.
10986 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10987 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10988 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10993 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10995 /* STT_GNU_IFUNC symbol must go through PLT. */
10996 if ((symbol_get_bfdsym (fr_symbol
)->flags
10997 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11000 if (!S_IS_EXTERNAL (fr_symbol
))
11001 /* Symbol may be weak or local. */
11002 return !S_IS_WEAK (fr_symbol
);
11004 /* Global symbols with non-default visibility can't be preempted. */
11005 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11008 if (fr_var
!= NO_RELOC
)
11009 switch ((enum bfd_reloc_code_real
) fr_var
)
11011 case BFD_RELOC_386_PLT32
:
11012 case BFD_RELOC_X86_64_PLT32
:
11013 /* Symbol with PLT relocation may be preempted. */
11019 /* Global symbols with default visibility in a shared library may be
11020 preempted by another definition. */
11025 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11026 Note also work for Skylake and Cascadelake.
11027 ---------------------------------------------------------------------
11028 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11029 | ------ | ----------- | ------- | -------- |
11031 | Jno | N | N | Y |
11032 | Jc/Jb | Y | N | Y |
11033 | Jae/Jnb | Y | N | Y |
11034 | Je/Jz | Y | Y | Y |
11035 | Jne/Jnz | Y | Y | Y |
11036 | Jna/Jbe | Y | N | Y |
11037 | Ja/Jnbe | Y | N | Y |
11039 | Jns | N | N | Y |
11040 | Jp/Jpe | N | N | Y |
11041 | Jnp/Jpo | N | N | Y |
11042 | Jl/Jnge | Y | Y | Y |
11043 | Jge/Jnl | Y | Y | Y |
11044 | Jle/Jng | Y | Y | Y |
11045 | Jg/Jnle | Y | Y | Y |
11046 --------------------------------------------------------------------- */
11048 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11050 if (mf_cmp
== mf_cmp_alu_cmp
)
11051 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11052 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11053 if (mf_cmp
== mf_cmp_incdec
)
11054 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11055 || mf_jcc
== mf_jcc_jle
);
11056 if (mf_cmp
== mf_cmp_test_and
)
11061 /* Return the next non-empty frag. */
11064 i386_next_non_empty_frag (fragS
*fragP
)
11066 /* There may be a frag with a ".fill 0" when there is no room in
11067 the current frag for frag_grow in output_insn. */
11068 for (fragP
= fragP
->fr_next
;
11070 && fragP
->fr_type
== rs_fill
11071 && fragP
->fr_fix
== 0);
11072 fragP
= fragP
->fr_next
)
11077 /* Return the next jcc frag after BRANCH_PADDING. */
11080 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11082 fragS
*branch_fragP
;
11086 if (pad_fragP
->fr_type
== rs_machine_dependent
11087 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11088 == BRANCH_PADDING
))
11090 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11091 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11093 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11094 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11095 pad_fragP
->tc_frag_data
.mf_type
))
11096 return branch_fragP
;
11102 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11105 i386_classify_machine_dependent_frag (fragS
*fragP
)
11109 fragS
*branch_fragP
;
11111 unsigned int max_prefix_length
;
11113 if (fragP
->tc_frag_data
.classified
)
11116 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11117 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11118 for (next_fragP
= fragP
;
11119 next_fragP
!= NULL
;
11120 next_fragP
= next_fragP
->fr_next
)
11122 next_fragP
->tc_frag_data
.classified
= 1;
11123 if (next_fragP
->fr_type
== rs_machine_dependent
)
11124 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11126 case BRANCH_PADDING
:
11127 /* The BRANCH_PADDING frag must be followed by a branch
11129 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11130 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11132 case FUSED_JCC_PADDING
:
11133 /* Check if this is a fused jcc:
11135 CMP like instruction
11139 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11140 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11141 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11144 /* The BRANCH_PADDING frag is merged with the
11145 FUSED_JCC_PADDING frag. */
11146 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11147 /* CMP like instruction size. */
11148 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11149 frag_wane (pad_fragP
);
11150 /* Skip to branch_fragP. */
11151 next_fragP
= branch_fragP
;
11153 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11155 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11157 next_fragP
->fr_subtype
11158 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11159 next_fragP
->tc_frag_data
.max_bytes
11160 = next_fragP
->tc_frag_data
.max_prefix_length
;
11161 /* This will be updated in the BRANCH_PREFIX scan. */
11162 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11165 frag_wane (next_fragP
);
11170 /* Stop if there is no BRANCH_PREFIX. */
11171 if (!align_branch_prefix_size
)
11174 /* Scan for BRANCH_PREFIX. */
11175 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11177 if (fragP
->fr_type
!= rs_machine_dependent
11178 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11182 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11183 COND_JUMP_PREFIX. */
11184 max_prefix_length
= 0;
11185 for (next_fragP
= fragP
;
11186 next_fragP
!= NULL
;
11187 next_fragP
= next_fragP
->fr_next
)
11189 if (next_fragP
->fr_type
== rs_fill
)
11190 /* Skip rs_fill frags. */
11192 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11193 /* Stop for all other frags. */
11196 /* rs_machine_dependent frags. */
11197 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11200 /* Count BRANCH_PREFIX frags. */
11201 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11203 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11204 frag_wane (next_fragP
);
11208 += next_fragP
->tc_frag_data
.max_bytes
;
11210 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11212 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11213 == FUSED_JCC_PADDING
))
11215 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11216 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11220 /* Stop for other rs_machine_dependent frags. */
11224 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11226 /* Skip to the next frag. */
11227 fragP
= next_fragP
;
11231 /* Compute padding size for
11234 CMP like instruction
11236 COND_JUMP/UNCOND_JUMP
11241 COND_JUMP/UNCOND_JUMP
11245 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11247 unsigned int offset
, size
, padding_size
;
11248 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11250 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11252 address
= fragP
->fr_address
;
11253 address
+= fragP
->fr_fix
;
11255 /* CMP like instrunction size. */
11256 size
= fragP
->tc_frag_data
.cmp_size
;
11258 /* The base size of the branch frag. */
11259 size
+= branch_fragP
->fr_fix
;
11261 /* Add opcode and displacement bytes for the rs_machine_dependent
11263 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11264 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11266 /* Check if branch is within boundary and doesn't end at the last
11268 offset
= address
& ((1U << align_branch_power
) - 1);
11269 if ((offset
+ size
) >= (1U << align_branch_power
))
11270 /* Padding needed to avoid crossing boundary. */
11271 padding_size
= (1U << align_branch_power
) - offset
;
11273 /* No padding needed. */
11276 /* The return value may be saved in tc_frag_data.length which is
11278 if (!fits_in_unsigned_byte (padding_size
))
11281 return padding_size
;
11284 /* i386_generic_table_relax_frag()
11286 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11287 grow/shrink padding to align branch frags. Hand others to
11291 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11293 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11294 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11296 long padding_size
= i386_branch_padding_size (fragP
, 0);
11297 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11299 /* When the BRANCH_PREFIX frag is used, the computed address
11300 must match the actual address and there should be no padding. */
11301 if (fragP
->tc_frag_data
.padding_address
11302 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11306 /* Update the padding size. */
11308 fragP
->tc_frag_data
.length
= padding_size
;
11312 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11314 fragS
*padding_fragP
, *next_fragP
;
11315 long padding_size
, left_size
, last_size
;
11317 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11318 if (!padding_fragP
)
11319 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11320 return (fragP
->tc_frag_data
.length
11321 - fragP
->tc_frag_data
.last_length
);
11323 /* Compute the relative address of the padding frag in the very
11324 first time where the BRANCH_PREFIX frag sizes are zero. */
11325 if (!fragP
->tc_frag_data
.padding_address
)
11326 fragP
->tc_frag_data
.padding_address
11327 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11329 /* First update the last length from the previous interation. */
11330 left_size
= fragP
->tc_frag_data
.prefix_length
;
11331 for (next_fragP
= fragP
;
11332 next_fragP
!= padding_fragP
;
11333 next_fragP
= next_fragP
->fr_next
)
11334 if (next_fragP
->fr_type
== rs_machine_dependent
11335 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11340 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11344 if (max
> left_size
)
11349 next_fragP
->tc_frag_data
.last_length
= size
;
11353 next_fragP
->tc_frag_data
.last_length
= 0;
11356 /* Check the padding size for the padding frag. */
11357 padding_size
= i386_branch_padding_size
11358 (padding_fragP
, (fragP
->fr_address
11359 + fragP
->tc_frag_data
.padding_address
));
11361 last_size
= fragP
->tc_frag_data
.prefix_length
;
11362 /* Check if there is change from the last interation. */
11363 if (padding_size
== last_size
)
11365 /* Update the expected address of the padding frag. */
11366 padding_fragP
->tc_frag_data
.padding_address
11367 = (fragP
->fr_address
+ padding_size
11368 + fragP
->tc_frag_data
.padding_address
);
11372 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11374 /* No padding if there is no sufficient room. Clear the
11375 expected address of the padding frag. */
11376 padding_fragP
->tc_frag_data
.padding_address
= 0;
11380 /* Store the expected address of the padding frag. */
11381 padding_fragP
->tc_frag_data
.padding_address
11382 = (fragP
->fr_address
+ padding_size
11383 + fragP
->tc_frag_data
.padding_address
);
11385 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11387 /* Update the length for the current interation. */
11388 left_size
= padding_size
;
11389 for (next_fragP
= fragP
;
11390 next_fragP
!= padding_fragP
;
11391 next_fragP
= next_fragP
->fr_next
)
11392 if (next_fragP
->fr_type
== rs_machine_dependent
11393 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11398 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11402 if (max
> left_size
)
11407 next_fragP
->tc_frag_data
.length
= size
;
11411 next_fragP
->tc_frag_data
.length
= 0;
11414 return (fragP
->tc_frag_data
.length
11415 - fragP
->tc_frag_data
.last_length
);
11417 return relax_frag (segment
, fragP
, stretch
);
11420 /* md_estimate_size_before_relax()
11422 Called just before relax() for rs_machine_dependent frags. The x86
11423 assembler uses these frags to handle variable size jump
11426 Any symbol that is now undefined will not become defined.
11427 Return the correct fr_subtype in the frag.
11428 Return the initial "guess for variable size of frag" to caller.
11429 The guess is actually the growth beyond the fixed part. Whatever
11430 we do to grow the fixed or variable part contributes to our
11434 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11436 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11437 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11438 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11440 i386_classify_machine_dependent_frag (fragP
);
11441 return fragP
->tc_frag_data
.length
;
11444 /* We've already got fragP->fr_subtype right; all we have to do is
11445 check for un-relaxable symbols. On an ELF system, we can't relax
11446 an externally visible symbol, because it may be overridden by a
11448 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11451 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11454 #if defined (OBJ_COFF) && defined (TE_PE)
11455 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11456 && S_IS_WEAK (fragP
->fr_symbol
))
11460 /* Symbol is undefined in this segment, or we need to keep a
11461 reloc so that weak symbols can be overridden. */
11462 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11463 enum bfd_reloc_code_real reloc_type
;
11464 unsigned char *opcode
;
11467 if (fragP
->fr_var
!= NO_RELOC
)
11468 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11469 else if (size
== 2)
11470 reloc_type
= BFD_RELOC_16_PCREL
;
11471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11472 else if (need_plt32_p (fragP
->fr_symbol
))
11473 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11476 reloc_type
= BFD_RELOC_32_PCREL
;
11478 old_fr_fix
= fragP
->fr_fix
;
11479 opcode
= (unsigned char *) fragP
->fr_opcode
;
11481 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11484 /* Make jmp (0xeb) a (d)word displacement jump. */
11486 fragP
->fr_fix
+= size
;
11487 fix_new (fragP
, old_fr_fix
, size
,
11489 fragP
->fr_offset
, 1,
11495 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11497 /* Negate the condition, and branch past an
11498 unconditional jump. */
11501 /* Insert an unconditional jump. */
11503 /* We added two extra opcode bytes, and have a two byte
11505 fragP
->fr_fix
+= 2 + 2;
11506 fix_new (fragP
, old_fr_fix
+ 2, 2,
11508 fragP
->fr_offset
, 1,
11512 /* Fall through. */
11515 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11519 fragP
->fr_fix
+= 1;
11520 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11522 fragP
->fr_offset
, 1,
11523 BFD_RELOC_8_PCREL
);
11524 fixP
->fx_signed
= 1;
11528 /* This changes the byte-displacement jump 0x7N
11529 to the (d)word-displacement jump 0x0f,0x8N. */
11530 opcode
[1] = opcode
[0] + 0x10;
11531 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11532 /* We've added an opcode byte. */
11533 fragP
->fr_fix
+= 1 + size
;
11534 fix_new (fragP
, old_fr_fix
+ 1, size
,
11536 fragP
->fr_offset
, 1,
11541 BAD_CASE (fragP
->fr_subtype
);
11545 return fragP
->fr_fix
- old_fr_fix
;
11548 /* Guess size depending on current relax state. Initially the relax
11549 state will correspond to a short jump and we return 1, because
11550 the variable part of the frag (the branch offset) is one byte
11551 long. However, we can relax a section more than once and in that
11552 case we must either set fr_subtype back to the unrelaxed state,
11553 or return the value for the appropriate branch. */
11554 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11557 /* Called after relax() is finished.
11559 In: Address of frag.
11560 fr_type == rs_machine_dependent.
11561 fr_subtype is what the address relaxed to.
11563 Out: Any fixSs and constants are set up.
11564 Caller will turn frag into a ".space 0". */
11567 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11570 unsigned char *opcode
;
11571 unsigned char *where_to_put_displacement
= NULL
;
11572 offsetT target_address
;
11573 offsetT opcode_address
;
11574 unsigned int extension
= 0;
11575 offsetT displacement_from_opcode_start
;
11577 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11578 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11579 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11581 /* Generate nop padding. */
11582 unsigned int size
= fragP
->tc_frag_data
.length
;
11585 if (size
> fragP
->tc_frag_data
.max_bytes
)
11591 const char *branch
= "branch";
11592 const char *prefix
= "";
11593 fragS
*padding_fragP
;
11594 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11597 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11598 switch (fragP
->tc_frag_data
.default_prefix
)
11603 case CS_PREFIX_OPCODE
:
11606 case DS_PREFIX_OPCODE
:
11609 case ES_PREFIX_OPCODE
:
11612 case FS_PREFIX_OPCODE
:
11615 case GS_PREFIX_OPCODE
:
11618 case SS_PREFIX_OPCODE
:
11623 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11624 "%s within %d-byte boundary\n");
11626 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11627 "align %s within %d-byte boundary\n");
11631 padding_fragP
= fragP
;
11632 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11633 "%s within %d-byte boundary\n");
11637 switch (padding_fragP
->tc_frag_data
.branch_type
)
11639 case align_branch_jcc
:
11642 case align_branch_fused
:
11643 branch
= "fused jcc";
11645 case align_branch_jmp
:
11648 case align_branch_call
:
11651 case align_branch_indirect
:
11652 branch
= "indiret branch";
11654 case align_branch_ret
:
11661 fprintf (stdout
, msg
,
11662 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11663 (long long) fragP
->fr_address
, branch
,
11664 1 << align_branch_power
);
11666 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11667 memset (fragP
->fr_opcode
,
11668 fragP
->tc_frag_data
.default_prefix
, size
);
11670 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11672 fragP
->fr_fix
+= size
;
11677 opcode
= (unsigned char *) fragP
->fr_opcode
;
11679 /* Address we want to reach in file space. */
11680 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11682 /* Address opcode resides at in file space. */
11683 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11685 /* Displacement from opcode start to fill into instruction. */
11686 displacement_from_opcode_start
= target_address
- opcode_address
;
11688 if ((fragP
->fr_subtype
& BIG
) == 0)
11690 /* Don't have to change opcode. */
11691 extension
= 1; /* 1 opcode + 1 displacement */
11692 where_to_put_displacement
= &opcode
[1];
11696 if (no_cond_jump_promotion
11697 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11698 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11699 _("long jump required"));
11701 switch (fragP
->fr_subtype
)
11703 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11704 extension
= 4; /* 1 opcode + 4 displacement */
11706 where_to_put_displacement
= &opcode
[1];
11709 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11710 extension
= 2; /* 1 opcode + 2 displacement */
11712 where_to_put_displacement
= &opcode
[1];
11715 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11716 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11717 extension
= 5; /* 2 opcode + 4 displacement */
11718 opcode
[1] = opcode
[0] + 0x10;
11719 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11720 where_to_put_displacement
= &opcode
[2];
11723 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11724 extension
= 3; /* 2 opcode + 2 displacement */
11725 opcode
[1] = opcode
[0] + 0x10;
11726 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11727 where_to_put_displacement
= &opcode
[2];
11730 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11735 where_to_put_displacement
= &opcode
[3];
11739 BAD_CASE (fragP
->fr_subtype
);
11744 /* If size if less then four we are sure that the operand fits,
11745 but if it's 4, then it could be that the displacement is larger
11747 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11749 && ((addressT
) (displacement_from_opcode_start
- extension
11750 + ((addressT
) 1 << 31))
11751 > (((addressT
) 2 << 31) - 1)))
11753 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11754 _("jump target out of range"));
11755 /* Make us emit 0. */
11756 displacement_from_opcode_start
= extension
;
11758 /* Now put displacement after opcode. */
11759 md_number_to_chars ((char *) where_to_put_displacement
,
11760 (valueT
) (displacement_from_opcode_start
- extension
),
11761 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11762 fragP
->fr_fix
+= extension
;
11765 /* Apply a fixup (fixP) to segment data, once it has been determined
11766 by our caller that we have all the info we need to fix it up.
11768 Parameter valP is the pointer to the value of the bits.
11770 On the 386, immediates, displacements, and data pointers are all in
11771 the same (little-endian) format, so we don't need to care about which
11772 we are handling. */
11775 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11777 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11778 valueT value
= *valP
;
11780 #if !defined (TE_Mach)
11781 if (fixP
->fx_pcrel
)
11783 switch (fixP
->fx_r_type
)
11789 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11792 case BFD_RELOC_X86_64_32S
:
11793 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11796 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11799 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11804 if (fixP
->fx_addsy
!= NULL
11805 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11806 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11807 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11808 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11809 && !use_rela_relocations
)
11811 /* This is a hack. There should be a better way to handle this.
11812 This covers for the fact that bfd_install_relocation will
11813 subtract the current location (for partial_inplace, PC relative
11814 relocations); see more below. */
11818 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11821 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11826 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11828 if ((sym_seg
== seg
11829 || (symbol_section_p (fixP
->fx_addsy
)
11830 && sym_seg
!= absolute_section
))
11831 && !generic_force_reloc (fixP
))
11833 /* Yes, we add the values in twice. This is because
11834 bfd_install_relocation subtracts them out again. I think
11835 bfd_install_relocation is broken, but I don't dare change
11837 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11841 #if defined (OBJ_COFF) && defined (TE_PE)
11842 /* For some reason, the PE format does not store a
11843 section address offset for a PC relative symbol. */
11844 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11845 || S_IS_WEAK (fixP
->fx_addsy
))
11846 value
+= md_pcrel_from (fixP
);
11849 #if defined (OBJ_COFF) && defined (TE_PE)
11850 if (fixP
->fx_addsy
!= NULL
11851 && S_IS_WEAK (fixP
->fx_addsy
)
11852 /* PR 16858: Do not modify weak function references. */
11853 && ! fixP
->fx_pcrel
)
11855 #if !defined (TE_PEP)
11856 /* For x86 PE weak function symbols are neither PC-relative
11857 nor do they set S_IS_FUNCTION. So the only reliable way
11858 to detect them is to check the flags of their containing
11860 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11861 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11865 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11869 /* Fix a few things - the dynamic linker expects certain values here,
11870 and we must not disappoint it. */
11871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11872 if (IS_ELF
&& fixP
->fx_addsy
)
11873 switch (fixP
->fx_r_type
)
11875 case BFD_RELOC_386_PLT32
:
11876 case BFD_RELOC_X86_64_PLT32
:
11877 /* Make the jump instruction point to the address of the operand.
11878 At runtime we merely add the offset to the actual PLT entry.
11879 NB: Subtract the offset size only for jump instructions. */
11880 if (fixP
->fx_pcrel
)
11884 case BFD_RELOC_386_TLS_GD
:
11885 case BFD_RELOC_386_TLS_LDM
:
11886 case BFD_RELOC_386_TLS_IE_32
:
11887 case BFD_RELOC_386_TLS_IE
:
11888 case BFD_RELOC_386_TLS_GOTIE
:
11889 case BFD_RELOC_386_TLS_GOTDESC
:
11890 case BFD_RELOC_X86_64_TLSGD
:
11891 case BFD_RELOC_X86_64_TLSLD
:
11892 case BFD_RELOC_X86_64_GOTTPOFF
:
11893 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11894 value
= 0; /* Fully resolved at runtime. No addend. */
11896 case BFD_RELOC_386_TLS_LE
:
11897 case BFD_RELOC_386_TLS_LDO_32
:
11898 case BFD_RELOC_386_TLS_LE_32
:
11899 case BFD_RELOC_X86_64_DTPOFF32
:
11900 case BFD_RELOC_X86_64_DTPOFF64
:
11901 case BFD_RELOC_X86_64_TPOFF32
:
11902 case BFD_RELOC_X86_64_TPOFF64
:
11903 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11906 case BFD_RELOC_386_TLS_DESC_CALL
:
11907 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11908 value
= 0; /* Fully resolved at runtime. No addend. */
11909 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11913 case BFD_RELOC_VTABLE_INHERIT
:
11914 case BFD_RELOC_VTABLE_ENTRY
:
11921 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11923 #endif /* !defined (TE_Mach) */
11925 /* Are we finished with this relocation now? */
11926 if (fixP
->fx_addsy
== NULL
)
11928 #if defined (OBJ_COFF) && defined (TE_PE)
11929 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11932 /* Remember value for tc_gen_reloc. */
11933 fixP
->fx_addnumber
= value
;
11934 /* Clear out the frag for now. */
11938 else if (use_rela_relocations
)
11940 fixP
->fx_no_overflow
= 1;
11941 /* Remember value for tc_gen_reloc. */
11942 fixP
->fx_addnumber
= value
;
11946 md_number_to_chars (p
, value
, fixP
->fx_size
);
11950 md_atof (int type
, char *litP
, int *sizeP
)
11952 /* This outputs the LITTLENUMs in REVERSE order;
11953 in accord with the bigendian 386. */
11954 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11957 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11960 output_invalid (int c
)
11963 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11966 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11967 "(0x%x)", (unsigned char) c
);
11968 return output_invalid_buf
;
11971 /* REG_STRING starts *before* REGISTER_PREFIX. */
11973 static const reg_entry
*
11974 parse_real_register (char *reg_string
, char **end_op
)
11976 char *s
= reg_string
;
11978 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11979 const reg_entry
*r
;
11981 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11982 if (*s
== REGISTER_PREFIX
)
11985 if (is_space_char (*s
))
11988 p
= reg_name_given
;
11989 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11991 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11992 return (const reg_entry
*) NULL
;
11996 /* For naked regs, make sure that we are not dealing with an identifier.
11997 This prevents confusing an identifier like `eax_var' with register
11999 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12000 return (const reg_entry
*) NULL
;
12004 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12006 /* Handle floating point regs, allowing spaces in the (i) part. */
12007 if (r
== i386_regtab
/* %st is first entry of table */)
12009 if (!cpu_arch_flags
.bitfield
.cpu8087
12010 && !cpu_arch_flags
.bitfield
.cpu287
12011 && !cpu_arch_flags
.bitfield
.cpu387
)
12012 return (const reg_entry
*) NULL
;
12014 if (is_space_char (*s
))
12019 if (is_space_char (*s
))
12021 if (*s
>= '0' && *s
<= '7')
12023 int fpr
= *s
- '0';
12025 if (is_space_char (*s
))
12030 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12035 /* We have "%st(" then garbage. */
12036 return (const reg_entry
*) NULL
;
12040 if (r
== NULL
|| allow_pseudo_reg
)
12043 if (operand_type_all_zero (&r
->reg_type
))
12044 return (const reg_entry
*) NULL
;
12046 if ((r
->reg_type
.bitfield
.dword
12047 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12048 || r
->reg_type
.bitfield
.class == RegCR
12049 || r
->reg_type
.bitfield
.class == RegDR
12050 || r
->reg_type
.bitfield
.class == RegTR
)
12051 && !cpu_arch_flags
.bitfield
.cpui386
)
12052 return (const reg_entry
*) NULL
;
12054 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12055 return (const reg_entry
*) NULL
;
12057 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12059 if (r
->reg_type
.bitfield
.zmmword
12060 || r
->reg_type
.bitfield
.class == RegMask
)
12061 return (const reg_entry
*) NULL
;
12063 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12065 if (r
->reg_type
.bitfield
.ymmword
)
12066 return (const reg_entry
*) NULL
;
12068 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12069 return (const reg_entry
*) NULL
;
12073 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12074 return (const reg_entry
*) NULL
;
12076 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12077 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12078 return (const reg_entry
*) NULL
;
12080 /* Upper 16 vector registers are only available with VREX in 64bit
12081 mode, and require EVEX encoding. */
12082 if (r
->reg_flags
& RegVRex
)
12084 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12085 || flag_code
!= CODE_64BIT
)
12086 return (const reg_entry
*) NULL
;
12088 i
.vec_encoding
= vex_encoding_evex
;
12091 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12092 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12093 && flag_code
!= CODE_64BIT
)
12094 return (const reg_entry
*) NULL
;
12096 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12098 return (const reg_entry
*) NULL
;
12103 /* REG_STRING starts *before* REGISTER_PREFIX. */
12105 static const reg_entry
*
12106 parse_register (char *reg_string
, char **end_op
)
12108 const reg_entry
*r
;
12110 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12111 r
= parse_real_register (reg_string
, end_op
);
12116 char *save
= input_line_pointer
;
12120 input_line_pointer
= reg_string
;
12121 c
= get_symbol_name (®_string
);
12122 symbolP
= symbol_find (reg_string
);
12123 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12125 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12127 know (e
->X_op
== O_register
);
12128 know (e
->X_add_number
>= 0
12129 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12130 r
= i386_regtab
+ e
->X_add_number
;
12131 if ((r
->reg_flags
& RegVRex
))
12132 i
.vec_encoding
= vex_encoding_evex
;
12133 *end_op
= input_line_pointer
;
12135 *input_line_pointer
= c
;
12136 input_line_pointer
= save
;
12142 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12144 const reg_entry
*r
;
12145 char *end
= input_line_pointer
;
12148 r
= parse_register (name
, &input_line_pointer
);
12149 if (r
&& end
<= input_line_pointer
)
12151 *nextcharP
= *input_line_pointer
;
12152 *input_line_pointer
= 0;
12153 e
->X_op
= O_register
;
12154 e
->X_add_number
= r
- i386_regtab
;
12157 input_line_pointer
= end
;
12159 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12163 md_operand (expressionS
*e
)
12166 const reg_entry
*r
;
12168 switch (*input_line_pointer
)
12170 case REGISTER_PREFIX
:
12171 r
= parse_real_register (input_line_pointer
, &end
);
12174 e
->X_op
= O_register
;
12175 e
->X_add_number
= r
- i386_regtab
;
12176 input_line_pointer
= end
;
12181 gas_assert (intel_syntax
);
12182 end
= input_line_pointer
++;
12184 if (*input_line_pointer
== ']')
12186 ++input_line_pointer
;
12187 e
->X_op_symbol
= make_expr_symbol (e
);
12188 e
->X_add_symbol
= NULL
;
12189 e
->X_add_number
= 0;
12194 e
->X_op
= O_absent
;
12195 input_line_pointer
= end
;
12202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12203 const char *md_shortopts
= "kVQ:sqnO::";
12205 const char *md_shortopts
= "qnO::";
12208 #define OPTION_32 (OPTION_MD_BASE + 0)
12209 #define OPTION_64 (OPTION_MD_BASE + 1)
12210 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12211 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12212 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12213 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12214 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12215 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12216 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12217 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12218 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12219 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12220 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12221 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12222 #define OPTION_X32 (OPTION_MD_BASE + 14)
12223 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12224 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12225 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12226 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12227 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12228 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12229 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12230 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12231 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12232 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12233 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12234 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12235 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12236 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12237 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12238 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12240 struct option md_longopts
[] =
12242 {"32", no_argument
, NULL
, OPTION_32
},
12243 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12244 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12245 {"64", no_argument
, NULL
, OPTION_64
},
12247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12248 {"x32", no_argument
, NULL
, OPTION_X32
},
12249 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12250 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12252 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12253 {"march", required_argument
, NULL
, OPTION_MARCH
},
12254 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12255 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12256 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12257 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12258 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12259 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12260 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12261 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12262 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12263 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12264 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12265 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12266 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12267 # if defined (TE_PE) || defined (TE_PEP)
12268 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12270 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12271 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12272 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12273 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12274 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12275 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12276 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12277 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12278 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12279 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12280 {NULL
, no_argument
, NULL
, 0}
12282 size_t md_longopts_size
= sizeof (md_longopts
);
12285 md_parse_option (int c
, const char *arg
)
12288 char *arch
, *next
, *saved
, *type
;
12293 optimize_align_code
= 0;
12297 quiet_warnings
= 1;
12300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12301 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12302 should be emitted or not. FIXME: Not implemented. */
12304 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12308 /* -V: SVR4 argument to print version ID. */
12310 print_version_id ();
12313 /* -k: Ignore for FreeBSD compatibility. */
12318 /* -s: On i386 Solaris, this tells the native assembler to use
12319 .stab instead of .stab.excl. We always use .stab anyhow. */
12322 case OPTION_MSHARED
:
12326 case OPTION_X86_USED_NOTE
:
12327 if (strcasecmp (arg
, "yes") == 0)
12329 else if (strcasecmp (arg
, "no") == 0)
12332 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12337 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12338 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12341 const char **list
, **l
;
12343 list
= bfd_target_list ();
12344 for (l
= list
; *l
!= NULL
; l
++)
12345 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12346 || strcmp (*l
, "coff-x86-64") == 0
12347 || strcmp (*l
, "pe-x86-64") == 0
12348 || strcmp (*l
, "pei-x86-64") == 0
12349 || strcmp (*l
, "mach-o-x86-64") == 0)
12351 default_arch
= "x86_64";
12355 as_fatal (_("no compiled in support for x86_64"));
12361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12365 const char **list
, **l
;
12367 list
= bfd_target_list ();
12368 for (l
= list
; *l
!= NULL
; l
++)
12369 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12371 default_arch
= "x86_64:32";
12375 as_fatal (_("no compiled in support for 32bit x86_64"));
12379 as_fatal (_("32bit x86_64 is only supported for ELF"));
12384 default_arch
= "i386";
12387 case OPTION_DIVIDE
:
12388 #ifdef SVR4_COMMENT_CHARS
12393 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12395 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12399 i386_comment_chars
= n
;
12405 saved
= xstrdup (arg
);
12407 /* Allow -march=+nosse. */
12413 as_fatal (_("invalid -march= option: `%s'"), arg
);
12414 next
= strchr (arch
, '+');
12417 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12419 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12422 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12425 cpu_arch_name
= cpu_arch
[j
].name
;
12426 cpu_sub_arch_name
= NULL
;
12427 cpu_arch_flags
= cpu_arch
[j
].flags
;
12428 cpu_arch_isa
= cpu_arch
[j
].type
;
12429 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12430 if (!cpu_arch_tune_set
)
12432 cpu_arch_tune
= cpu_arch_isa
;
12433 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12437 else if (*cpu_arch
[j
].name
== '.'
12438 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12440 /* ISA extension. */
12441 i386_cpu_flags flags
;
12443 flags
= cpu_flags_or (cpu_arch_flags
,
12444 cpu_arch
[j
].flags
);
12446 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12448 if (cpu_sub_arch_name
)
12450 char *name
= cpu_sub_arch_name
;
12451 cpu_sub_arch_name
= concat (name
,
12453 (const char *) NULL
);
12457 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12458 cpu_arch_flags
= flags
;
12459 cpu_arch_isa_flags
= flags
;
12463 = cpu_flags_or (cpu_arch_isa_flags
,
12464 cpu_arch
[j
].flags
);
12469 if (j
>= ARRAY_SIZE (cpu_arch
))
12471 /* Disable an ISA extension. */
12472 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12473 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12475 i386_cpu_flags flags
;
12477 flags
= cpu_flags_and_not (cpu_arch_flags
,
12478 cpu_noarch
[j
].flags
);
12479 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12481 if (cpu_sub_arch_name
)
12483 char *name
= cpu_sub_arch_name
;
12484 cpu_sub_arch_name
= concat (arch
,
12485 (const char *) NULL
);
12489 cpu_sub_arch_name
= xstrdup (arch
);
12490 cpu_arch_flags
= flags
;
12491 cpu_arch_isa_flags
= flags
;
12496 if (j
>= ARRAY_SIZE (cpu_noarch
))
12497 j
= ARRAY_SIZE (cpu_arch
);
12500 if (j
>= ARRAY_SIZE (cpu_arch
))
12501 as_fatal (_("invalid -march= option: `%s'"), arg
);
12505 while (next
!= NULL
);
12511 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12512 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12514 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12516 cpu_arch_tune_set
= 1;
12517 cpu_arch_tune
= cpu_arch
[j
].type
;
12518 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12522 if (j
>= ARRAY_SIZE (cpu_arch
))
12523 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12526 case OPTION_MMNEMONIC
:
12527 if (strcasecmp (arg
, "att") == 0)
12528 intel_mnemonic
= 0;
12529 else if (strcasecmp (arg
, "intel") == 0)
12530 intel_mnemonic
= 1;
12532 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12535 case OPTION_MSYNTAX
:
12536 if (strcasecmp (arg
, "att") == 0)
12538 else if (strcasecmp (arg
, "intel") == 0)
12541 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12544 case OPTION_MINDEX_REG
:
12545 allow_index_reg
= 1;
12548 case OPTION_MNAKED_REG
:
12549 allow_naked_reg
= 1;
12552 case OPTION_MSSE2AVX
:
12556 case OPTION_MSSE_CHECK
:
12557 if (strcasecmp (arg
, "error") == 0)
12558 sse_check
= check_error
;
12559 else if (strcasecmp (arg
, "warning") == 0)
12560 sse_check
= check_warning
;
12561 else if (strcasecmp (arg
, "none") == 0)
12562 sse_check
= check_none
;
12564 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12567 case OPTION_MOPERAND_CHECK
:
12568 if (strcasecmp (arg
, "error") == 0)
12569 operand_check
= check_error
;
12570 else if (strcasecmp (arg
, "warning") == 0)
12571 operand_check
= check_warning
;
12572 else if (strcasecmp (arg
, "none") == 0)
12573 operand_check
= check_none
;
12575 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12578 case OPTION_MAVXSCALAR
:
12579 if (strcasecmp (arg
, "128") == 0)
12580 avxscalar
= vex128
;
12581 else if (strcasecmp (arg
, "256") == 0)
12582 avxscalar
= vex256
;
12584 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12587 case OPTION_MVEXWIG
:
12588 if (strcmp (arg
, "0") == 0)
12590 else if (strcmp (arg
, "1") == 0)
12593 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12596 case OPTION_MADD_BND_PREFIX
:
12597 add_bnd_prefix
= 1;
12600 case OPTION_MEVEXLIG
:
12601 if (strcmp (arg
, "128") == 0)
12602 evexlig
= evexl128
;
12603 else if (strcmp (arg
, "256") == 0)
12604 evexlig
= evexl256
;
12605 else if (strcmp (arg
, "512") == 0)
12606 evexlig
= evexl512
;
12608 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12611 case OPTION_MEVEXRCIG
:
12612 if (strcmp (arg
, "rne") == 0)
12614 else if (strcmp (arg
, "rd") == 0)
12616 else if (strcmp (arg
, "ru") == 0)
12618 else if (strcmp (arg
, "rz") == 0)
12621 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12624 case OPTION_MEVEXWIG
:
12625 if (strcmp (arg
, "0") == 0)
12627 else if (strcmp (arg
, "1") == 0)
12630 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12633 # if defined (TE_PE) || defined (TE_PEP)
12634 case OPTION_MBIG_OBJ
:
12639 case OPTION_MOMIT_LOCK_PREFIX
:
12640 if (strcasecmp (arg
, "yes") == 0)
12641 omit_lock_prefix
= 1;
12642 else if (strcasecmp (arg
, "no") == 0)
12643 omit_lock_prefix
= 0;
12645 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12648 case OPTION_MFENCE_AS_LOCK_ADD
:
12649 if (strcasecmp (arg
, "yes") == 0)
12651 else if (strcasecmp (arg
, "no") == 0)
12654 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12657 case OPTION_MRELAX_RELOCATIONS
:
12658 if (strcasecmp (arg
, "yes") == 0)
12659 generate_relax_relocations
= 1;
12660 else if (strcasecmp (arg
, "no") == 0)
12661 generate_relax_relocations
= 0;
12663 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12666 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12669 long int align
= strtoul (arg
, &end
, 0);
12674 align_branch_power
= 0;
12677 else if (align
>= 16)
12680 for (align_power
= 0;
12682 align
>>= 1, align_power
++)
12684 /* Limit alignment power to 31. */
12685 if (align
== 1 && align_power
< 32)
12687 align_branch_power
= align_power
;
12692 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12696 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12699 int align
= strtoul (arg
, &end
, 0);
12700 /* Some processors only support 5 prefixes. */
12701 if (*end
== '\0' && align
>= 0 && align
< 6)
12703 align_branch_prefix_size
= align
;
12706 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12711 case OPTION_MALIGN_BRANCH
:
12713 saved
= xstrdup (arg
);
12717 next
= strchr (type
, '+');
12720 if (strcasecmp (type
, "jcc") == 0)
12721 align_branch
|= align_branch_jcc_bit
;
12722 else if (strcasecmp (type
, "fused") == 0)
12723 align_branch
|= align_branch_fused_bit
;
12724 else if (strcasecmp (type
, "jmp") == 0)
12725 align_branch
|= align_branch_jmp_bit
;
12726 else if (strcasecmp (type
, "call") == 0)
12727 align_branch
|= align_branch_call_bit
;
12728 else if (strcasecmp (type
, "ret") == 0)
12729 align_branch
|= align_branch_ret_bit
;
12730 else if (strcasecmp (type
, "indirect") == 0)
12731 align_branch
|= align_branch_indirect_bit
;
12733 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12736 while (next
!= NULL
);
12740 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12741 align_branch_power
= 5;
12742 align_branch_prefix_size
= 5;
12743 align_branch
= (align_branch_jcc_bit
12744 | align_branch_fused_bit
12745 | align_branch_jmp_bit
);
12748 case OPTION_MAMD64
:
12752 case OPTION_MINTEL64
:
12760 /* Turn off -Os. */
12761 optimize_for_space
= 0;
12763 else if (*arg
== 's')
12765 optimize_for_space
= 1;
12766 /* Turn on all encoding optimizations. */
12767 optimize
= INT_MAX
;
12771 optimize
= atoi (arg
);
12772 /* Turn off -Os. */
12773 optimize_for_space
= 0;
12783 #define MESSAGE_TEMPLATE \
12787 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12788 int *left_p
, const char *name
, int len
)
12790 int size
= sizeof (MESSAGE_TEMPLATE
);
12791 int left
= *left_p
;
12793 /* Reserve 2 spaces for ", " or ",\0" */
12796 /* Check if there is any room. */
12804 p
= mempcpy (p
, name
, len
);
12808 /* Output the current message now and start a new one. */
12811 fprintf (stream
, "%s\n", message
);
12813 left
= size
- (start
- message
) - len
- 2;
12815 gas_assert (left
>= 0);
12817 p
= mempcpy (p
, name
, len
);
12825 show_arch (FILE *stream
, int ext
, int check
)
12827 static char message
[] = MESSAGE_TEMPLATE
;
12828 char *start
= message
+ 27;
12830 int size
= sizeof (MESSAGE_TEMPLATE
);
12837 left
= size
- (start
- message
);
12838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12840 /* Should it be skipped? */
12841 if (cpu_arch
[j
].skip
)
12844 name
= cpu_arch
[j
].name
;
12845 len
= cpu_arch
[j
].len
;
12848 /* It is an extension. Skip if we aren't asked to show it. */
12859 /* It is an processor. Skip if we show only extension. */
12862 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12864 /* It is an impossible processor - skip. */
12868 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12871 /* Display disabled extensions. */
12873 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12875 name
= cpu_noarch
[j
].name
;
12876 len
= cpu_noarch
[j
].len
;
12877 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12882 fprintf (stream
, "%s\n", message
);
12886 md_show_usage (FILE *stream
)
12888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12889 fprintf (stream
, _("\
12890 -Qy, -Qn ignored\n\
12891 -V print assembler version number\n\
12894 fprintf (stream
, _("\
12895 -n Do not optimize code alignment\n\
12896 -q quieten some warnings\n"));
12897 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12898 fprintf (stream
, _("\
12901 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12902 || defined (TE_PE) || defined (TE_PEP))
12903 fprintf (stream
, _("\
12904 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12906 #ifdef SVR4_COMMENT_CHARS
12907 fprintf (stream
, _("\
12908 --divide do not treat `/' as a comment character\n"));
12910 fprintf (stream
, _("\
12911 --divide ignored\n"));
12913 fprintf (stream
, _("\
12914 -march=CPU[,+EXTENSION...]\n\
12915 generate code for CPU and EXTENSION, CPU is one of:\n"));
12916 show_arch (stream
, 0, 1);
12917 fprintf (stream
, _("\
12918 EXTENSION is combination of:\n"));
12919 show_arch (stream
, 1, 0);
12920 fprintf (stream
, _("\
12921 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12922 show_arch (stream
, 0, 0);
12923 fprintf (stream
, _("\
12924 -msse2avx encode SSE instructions with VEX prefix\n"));
12925 fprintf (stream
, _("\
12926 -msse-check=[none|error|warning] (default: warning)\n\
12927 check SSE instructions\n"));
12928 fprintf (stream
, _("\
12929 -moperand-check=[none|error|warning] (default: warning)\n\
12930 check operand combinations for validity\n"));
12931 fprintf (stream
, _("\
12932 -mavxscalar=[128|256] (default: 128)\n\
12933 encode scalar AVX instructions with specific vector\n\
12935 fprintf (stream
, _("\
12936 -mvexwig=[0|1] (default: 0)\n\
12937 encode VEX instructions with specific VEX.W value\n\
12938 for VEX.W bit ignored instructions\n"));
12939 fprintf (stream
, _("\
12940 -mevexlig=[128|256|512] (default: 128)\n\
12941 encode scalar EVEX instructions with specific vector\n\
12943 fprintf (stream
, _("\
12944 -mevexwig=[0|1] (default: 0)\n\
12945 encode EVEX instructions with specific EVEX.W value\n\
12946 for EVEX.W bit ignored instructions\n"));
12947 fprintf (stream
, _("\
12948 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12949 encode EVEX instructions with specific EVEX.RC value\n\
12950 for SAE-only ignored instructions\n"));
12951 fprintf (stream
, _("\
12952 -mmnemonic=[att|intel] "));
12953 if (SYSV386_COMPAT
)
12954 fprintf (stream
, _("(default: att)\n"));
12956 fprintf (stream
, _("(default: intel)\n"));
12957 fprintf (stream
, _("\
12958 use AT&T/Intel mnemonic\n"));
12959 fprintf (stream
, _("\
12960 -msyntax=[att|intel] (default: att)\n\
12961 use AT&T/Intel syntax\n"));
12962 fprintf (stream
, _("\
12963 -mindex-reg support pseudo index registers\n"));
12964 fprintf (stream
, _("\
12965 -mnaked-reg don't require `%%' prefix for registers\n"));
12966 fprintf (stream
, _("\
12967 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12969 fprintf (stream
, _("\
12970 -mshared disable branch optimization for shared code\n"));
12971 fprintf (stream
, _("\
12972 -mx86-used-note=[no|yes] "));
12973 if (DEFAULT_X86_USED_NOTE
)
12974 fprintf (stream
, _("(default: yes)\n"));
12976 fprintf (stream
, _("(default: no)\n"));
12977 fprintf (stream
, _("\
12978 generate x86 used ISA and feature properties\n"));
12980 #if defined (TE_PE) || defined (TE_PEP)
12981 fprintf (stream
, _("\
12982 -mbig-obj generate big object files\n"));
12984 fprintf (stream
, _("\
12985 -momit-lock-prefix=[no|yes] (default: no)\n\
12986 strip all lock prefixes\n"));
12987 fprintf (stream
, _("\
12988 -mfence-as-lock-add=[no|yes] (default: no)\n\
12989 encode lfence, mfence and sfence as\n\
12990 lock addl $0x0, (%%{re}sp)\n"));
12991 fprintf (stream
, _("\
12992 -mrelax-relocations=[no|yes] "));
12993 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12994 fprintf (stream
, _("(default: yes)\n"));
12996 fprintf (stream
, _("(default: no)\n"));
12997 fprintf (stream
, _("\
12998 generate relax relocations\n"));
12999 fprintf (stream
, _("\
13000 -malign-branch-boundary=NUM (default: 0)\n\
13001 align branches within NUM byte boundary\n"));
13002 fprintf (stream
, _("\
13003 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13004 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13006 specify types of branches to align\n"));
13007 fprintf (stream
, _("\
13008 -malign-branch-prefix-size=NUM (default: 5)\n\
13009 align branches with NUM prefixes per instruction\n"));
13010 fprintf (stream
, _("\
13011 -mbranches-within-32B-boundaries\n\
13012 align branches within 32 byte boundary\n"));
13013 fprintf (stream
, _("\
13014 -mamd64 accept only AMD64 ISA [default]\n"));
13015 fprintf (stream
, _("\
13016 -mintel64 accept only Intel64 ISA\n"));
13019 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13020 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13021 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13023 /* Pick the target format to use. */
13026 i386_target_format (void)
13028 if (!strncmp (default_arch
, "x86_64", 6))
13030 update_code_flag (CODE_64BIT
, 1);
13031 if (default_arch
[6] == '\0')
13032 x86_elf_abi
= X86_64_ABI
;
13034 x86_elf_abi
= X86_64_X32_ABI
;
13036 else if (!strcmp (default_arch
, "i386"))
13037 update_code_flag (CODE_32BIT
, 1);
13038 else if (!strcmp (default_arch
, "iamcu"))
13040 update_code_flag (CODE_32BIT
, 1);
13041 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13043 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13044 cpu_arch_name
= "iamcu";
13045 cpu_sub_arch_name
= NULL
;
13046 cpu_arch_flags
= iamcu_flags
;
13047 cpu_arch_isa
= PROCESSOR_IAMCU
;
13048 cpu_arch_isa_flags
= iamcu_flags
;
13049 if (!cpu_arch_tune_set
)
13051 cpu_arch_tune
= cpu_arch_isa
;
13052 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13055 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13056 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13060 as_fatal (_("unknown architecture"));
13062 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13063 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13064 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13065 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13067 switch (OUTPUT_FLAVOR
)
13069 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13070 case bfd_target_aout_flavour
:
13071 return AOUT_TARGET_FORMAT
;
13073 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13074 # if defined (TE_PE) || defined (TE_PEP)
13075 case bfd_target_coff_flavour
:
13076 if (flag_code
== CODE_64BIT
)
13077 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13080 # elif defined (TE_GO32)
13081 case bfd_target_coff_flavour
:
13082 return "coff-go32";
13084 case bfd_target_coff_flavour
:
13085 return "coff-i386";
13088 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13089 case bfd_target_elf_flavour
:
13091 const char *format
;
13093 switch (x86_elf_abi
)
13096 format
= ELF_TARGET_FORMAT
;
13098 tls_get_addr
= "___tls_get_addr";
13102 use_rela_relocations
= 1;
13105 tls_get_addr
= "__tls_get_addr";
13107 format
= ELF_TARGET_FORMAT64
;
13109 case X86_64_X32_ABI
:
13110 use_rela_relocations
= 1;
13113 tls_get_addr
= "__tls_get_addr";
13115 disallow_64bit_reloc
= 1;
13116 format
= ELF_TARGET_FORMAT32
;
13119 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13121 if (x86_elf_abi
!= X86_64_ABI
)
13122 as_fatal (_("Intel L1OM is 64bit only"));
13123 return ELF_TARGET_L1OM_FORMAT
;
13125 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13127 if (x86_elf_abi
!= X86_64_ABI
)
13128 as_fatal (_("Intel K1OM is 64bit only"));
13129 return ELF_TARGET_K1OM_FORMAT
;
13131 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13133 if (x86_elf_abi
!= I386_ABI
)
13134 as_fatal (_("Intel MCU is 32bit only"));
13135 return ELF_TARGET_IAMCU_FORMAT
;
13141 #if defined (OBJ_MACH_O)
13142 case bfd_target_mach_o_flavour
:
13143 if (flag_code
== CODE_64BIT
)
13145 use_rela_relocations
= 1;
13147 return "mach-o-x86-64";
13150 return "mach-o-i386";
13158 #endif /* OBJ_MAYBE_ more than one */
13161 md_undefined_symbol (char *name
)
13163 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13164 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13165 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13166 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13170 if (symbol_find (name
))
13171 as_bad (_("GOT already in symbol table"));
13172 GOT_symbol
= symbol_new (name
, undefined_section
,
13173 (valueT
) 0, &zero_address_frag
);
13180 /* Round up a section size to the appropriate boundary. */
13183 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13185 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13186 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13188 /* For a.out, force the section size to be aligned. If we don't do
13189 this, BFD will align it for us, but it will not write out the
13190 final bytes of the section. This may be a bug in BFD, but it is
13191 easier to fix it here since that is how the other a.out targets
13195 align
= bfd_section_alignment (segment
);
13196 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13203 /* On the i386, PC-relative offsets are relative to the start of the
13204 next instruction. That is, the address of the offset, plus its
13205 size, since the offset is always the last part of the insn. */
13208 md_pcrel_from (fixS
*fixP
)
13210 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13216 s_bss (int ignore ATTRIBUTE_UNUSED
)
13220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13222 obj_elf_section_change_hook ();
13224 temp
= get_absolute_expression ();
13225 subseg_set (bss_section
, (subsegT
) temp
);
13226 demand_empty_rest_of_line ();
13231 /* Remember constant directive. */
13234 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13236 if (last_insn
.kind
!= last_insn_directive
13237 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13239 last_insn
.seg
= now_seg
;
13240 last_insn
.kind
= last_insn_directive
;
13241 last_insn
.name
= "constant directive";
13242 last_insn
.file
= as_where (&last_insn
.line
);
13247 i386_validate_fix (fixS
*fixp
)
13249 if (fixp
->fx_subsy
)
13251 if (fixp
->fx_subsy
== GOT_symbol
)
13253 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13258 if (fixp
->fx_tcbit2
)
13259 fixp
->fx_r_type
= (fixp
->fx_tcbit
13260 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13261 : BFD_RELOC_X86_64_GOTPCRELX
);
13264 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13269 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13271 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13273 fixp
->fx_subsy
= 0;
13276 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13277 else if (!object_64bit
)
13279 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13280 && fixp
->fx_tcbit2
)
13281 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13287 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13290 bfd_reloc_code_real_type code
;
13292 switch (fixp
->fx_r_type
)
13294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13295 case BFD_RELOC_SIZE32
:
13296 case BFD_RELOC_SIZE64
:
13297 if (S_IS_DEFINED (fixp
->fx_addsy
)
13298 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13300 /* Resolve size relocation against local symbol to size of
13301 the symbol plus addend. */
13302 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13303 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13304 && !fits_in_unsigned_long (value
))
13305 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13306 _("symbol size computation overflow"));
13307 fixp
->fx_addsy
= NULL
;
13308 fixp
->fx_subsy
= NULL
;
13309 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13313 /* Fall through. */
13315 case BFD_RELOC_X86_64_PLT32
:
13316 case BFD_RELOC_X86_64_GOT32
:
13317 case BFD_RELOC_X86_64_GOTPCREL
:
13318 case BFD_RELOC_X86_64_GOTPCRELX
:
13319 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13320 case BFD_RELOC_386_PLT32
:
13321 case BFD_RELOC_386_GOT32
:
13322 case BFD_RELOC_386_GOT32X
:
13323 case BFD_RELOC_386_GOTOFF
:
13324 case BFD_RELOC_386_GOTPC
:
13325 case BFD_RELOC_386_TLS_GD
:
13326 case BFD_RELOC_386_TLS_LDM
:
13327 case BFD_RELOC_386_TLS_LDO_32
:
13328 case BFD_RELOC_386_TLS_IE_32
:
13329 case BFD_RELOC_386_TLS_IE
:
13330 case BFD_RELOC_386_TLS_GOTIE
:
13331 case BFD_RELOC_386_TLS_LE_32
:
13332 case BFD_RELOC_386_TLS_LE
:
13333 case BFD_RELOC_386_TLS_GOTDESC
:
13334 case BFD_RELOC_386_TLS_DESC_CALL
:
13335 case BFD_RELOC_X86_64_TLSGD
:
13336 case BFD_RELOC_X86_64_TLSLD
:
13337 case BFD_RELOC_X86_64_DTPOFF32
:
13338 case BFD_RELOC_X86_64_DTPOFF64
:
13339 case BFD_RELOC_X86_64_GOTTPOFF
:
13340 case BFD_RELOC_X86_64_TPOFF32
:
13341 case BFD_RELOC_X86_64_TPOFF64
:
13342 case BFD_RELOC_X86_64_GOTOFF64
:
13343 case BFD_RELOC_X86_64_GOTPC32
:
13344 case BFD_RELOC_X86_64_GOT64
:
13345 case BFD_RELOC_X86_64_GOTPCREL64
:
13346 case BFD_RELOC_X86_64_GOTPC64
:
13347 case BFD_RELOC_X86_64_GOTPLT64
:
13348 case BFD_RELOC_X86_64_PLTOFF64
:
13349 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13350 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13351 case BFD_RELOC_RVA
:
13352 case BFD_RELOC_VTABLE_ENTRY
:
13353 case BFD_RELOC_VTABLE_INHERIT
:
13355 case BFD_RELOC_32_SECREL
:
13357 code
= fixp
->fx_r_type
;
13359 case BFD_RELOC_X86_64_32S
:
13360 if (!fixp
->fx_pcrel
)
13362 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13363 code
= fixp
->fx_r_type
;
13366 /* Fall through. */
13368 if (fixp
->fx_pcrel
)
13370 switch (fixp
->fx_size
)
13373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13374 _("can not do %d byte pc-relative relocation"),
13376 code
= BFD_RELOC_32_PCREL
;
13378 case 1: code
= BFD_RELOC_8_PCREL
; break;
13379 case 2: code
= BFD_RELOC_16_PCREL
; break;
13380 case 4: code
= BFD_RELOC_32_PCREL
; break;
13382 case 8: code
= BFD_RELOC_64_PCREL
; break;
13388 switch (fixp
->fx_size
)
13391 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13392 _("can not do %d byte relocation"),
13394 code
= BFD_RELOC_32
;
13396 case 1: code
= BFD_RELOC_8
; break;
13397 case 2: code
= BFD_RELOC_16
; break;
13398 case 4: code
= BFD_RELOC_32
; break;
13400 case 8: code
= BFD_RELOC_64
; break;
13407 if ((code
== BFD_RELOC_32
13408 || code
== BFD_RELOC_32_PCREL
13409 || code
== BFD_RELOC_X86_64_32S
)
13411 && fixp
->fx_addsy
== GOT_symbol
)
13414 code
= BFD_RELOC_386_GOTPC
;
13416 code
= BFD_RELOC_X86_64_GOTPC32
;
13418 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13420 && fixp
->fx_addsy
== GOT_symbol
)
13422 code
= BFD_RELOC_X86_64_GOTPC64
;
13425 rel
= XNEW (arelent
);
13426 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13427 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13429 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13431 if (!use_rela_relocations
)
13433 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13434 vtable entry to be used in the relocation's section offset. */
13435 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13436 rel
->address
= fixp
->fx_offset
;
13437 #if defined (OBJ_COFF) && defined (TE_PE)
13438 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13439 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13444 /* Use the rela in 64bit mode. */
13447 if (disallow_64bit_reloc
)
13450 case BFD_RELOC_X86_64_DTPOFF64
:
13451 case BFD_RELOC_X86_64_TPOFF64
:
13452 case BFD_RELOC_64_PCREL
:
13453 case BFD_RELOC_X86_64_GOTOFF64
:
13454 case BFD_RELOC_X86_64_GOT64
:
13455 case BFD_RELOC_X86_64_GOTPCREL64
:
13456 case BFD_RELOC_X86_64_GOTPC64
:
13457 case BFD_RELOC_X86_64_GOTPLT64
:
13458 case BFD_RELOC_X86_64_PLTOFF64
:
13459 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13460 _("cannot represent relocation type %s in x32 mode"),
13461 bfd_get_reloc_code_name (code
));
13467 if (!fixp
->fx_pcrel
)
13468 rel
->addend
= fixp
->fx_offset
;
13472 case BFD_RELOC_X86_64_PLT32
:
13473 case BFD_RELOC_X86_64_GOT32
:
13474 case BFD_RELOC_X86_64_GOTPCREL
:
13475 case BFD_RELOC_X86_64_GOTPCRELX
:
13476 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13477 case BFD_RELOC_X86_64_TLSGD
:
13478 case BFD_RELOC_X86_64_TLSLD
:
13479 case BFD_RELOC_X86_64_GOTTPOFF
:
13480 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13481 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13482 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13485 rel
->addend
= (section
->vma
13487 + fixp
->fx_addnumber
13488 + md_pcrel_from (fixp
));
13493 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13494 if (rel
->howto
== NULL
)
13496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13497 _("cannot represent relocation type %s"),
13498 bfd_get_reloc_code_name (code
));
13499 /* Set howto to a garbage value so that we can keep going. */
13500 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13501 gas_assert (rel
->howto
!= NULL
);
13507 #include "tc-i386-intel.c"
13510 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13512 int saved_naked_reg
;
13513 char saved_register_dot
;
13515 saved_naked_reg
= allow_naked_reg
;
13516 allow_naked_reg
= 1;
13517 saved_register_dot
= register_chars
['.'];
13518 register_chars
['.'] = '.';
13519 allow_pseudo_reg
= 1;
13520 expression_and_evaluate (exp
);
13521 allow_pseudo_reg
= 0;
13522 register_chars
['.'] = saved_register_dot
;
13523 allow_naked_reg
= saved_naked_reg
;
13525 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13527 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13529 exp
->X_op
= O_constant
;
13530 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13531 .dw2_regnum
[flag_code
>> 1];
13534 exp
->X_op
= O_illegal
;
13539 tc_x86_frame_initial_instructions (void)
13541 static unsigned int sp_regno
[2];
13543 if (!sp_regno
[flag_code
>> 1])
13545 char *saved_input
= input_line_pointer
;
13546 char sp
[][4] = {"esp", "rsp"};
13549 input_line_pointer
= sp
[flag_code
>> 1];
13550 tc_x86_parse_to_dw2regnum (&exp
);
13551 gas_assert (exp
.X_op
== O_constant
);
13552 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13553 input_line_pointer
= saved_input
;
13556 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13557 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13561 x86_dwarf2_addr_size (void)
13563 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13564 if (x86_elf_abi
== X86_64_X32_ABI
)
13567 return bfd_arch_bits_per_address (stdoutput
) / 8;
13571 i386_elf_section_type (const char *str
, size_t len
)
13573 if (flag_code
== CODE_64BIT
13574 && len
== sizeof ("unwind") - 1
13575 && strncmp (str
, "unwind", 6) == 0)
13576 return SHT_X86_64_UNWIND
;
13583 i386_solaris_fix_up_eh_frame (segT sec
)
13585 if (flag_code
== CODE_64BIT
)
13586 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13592 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13596 exp
.X_op
= O_secrel
;
13597 exp
.X_add_symbol
= symbol
;
13598 exp
.X_add_number
= 0;
13599 emit_expr (&exp
, size
);
13603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13604 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13607 x86_64_section_letter (int letter
, const char **ptr_msg
)
13609 if (flag_code
== CODE_64BIT
)
13612 return SHF_X86_64_LARGE
;
13614 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13617 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13622 x86_64_section_word (char *str
, size_t len
)
13624 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13625 return SHF_X86_64_LARGE
;
13631 handle_large_common (int small ATTRIBUTE_UNUSED
)
13633 if (flag_code
!= CODE_64BIT
)
13635 s_comm_internal (0, elf_common_parse
);
13636 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13640 static segT lbss_section
;
13641 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13642 asection
*saved_bss_section
= bss_section
;
13644 if (lbss_section
== NULL
)
13646 flagword applicable
;
13647 segT seg
= now_seg
;
13648 subsegT subseg
= now_subseg
;
13650 /* The .lbss section is for local .largecomm symbols. */
13651 lbss_section
= subseg_new (".lbss", 0);
13652 applicable
= bfd_applicable_section_flags (stdoutput
);
13653 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13654 seg_info (lbss_section
)->bss
= 1;
13656 subseg_set (seg
, subseg
);
13659 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13660 bss_section
= lbss_section
;
13662 s_comm_internal (0, elf_common_parse
);
13664 elf_com_section_ptr
= saved_com_section_ptr
;
13665 bss_section
= saved_bss_section
;
13668 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */