1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_allow_index_reg (int);
62 static void set_cpu_arch (int);
64 static void pe_directive_secrel (int);
66 static void signed_cons (int);
67 static char *output_invalid (int c
);
68 static int i386_operand (char *);
69 static int i386_intel_operand (char *, int);
70 static const reg_entry
*parse_register (char *, char **);
71 static char *parse_insn (char *, char *);
72 static char *parse_operands (char *, const char *);
73 static void swap_operands (void);
74 static void swap_2_operands (int, int);
75 static void optimize_imm (void);
76 static void optimize_disp (void);
77 static int match_template (void);
78 static int check_string (void);
79 static int process_suffix (void);
80 static int check_byte_reg (void);
81 static int check_long_reg (void);
82 static int check_qword_reg (void);
83 static int check_word_reg (void);
84 static int finalize_imm (void);
85 static void process_drex (void);
86 static int process_operands (void);
87 static const seg_entry
*build_modrm_byte (void);
88 static void output_insn (void);
89 static void output_imm (fragS
*, offsetT
);
90 static void output_disp (fragS
*, offsetT
);
92 static void s_bss (int);
94 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
98 static const char *default_arch
= DEFAULT_ARCH
;
100 /* 'md_assemble ()' gathers together information and puts it into a
107 const reg_entry
*regs
;
112 /* TM holds the template for the insn were currently assembling. */
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
119 /* OPERANDS gives the number of given operands. */
120 unsigned int operands
;
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
125 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
127 /* TYPES [i] is the type (see above #defines) which tells us how to
128 use OP[i] for the corresponding operand. */
129 i386_operand_type types
[MAX_OPERANDS
];
131 /* Displacement expression, immediate expression, or register for each
133 union i386_op op
[MAX_OPERANDS
];
135 /* Flags for operands. */
136 unsigned int flags
[MAX_OPERANDS
];
137 #define Operand_PCrel 1
139 /* Relocation type for operand */
140 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry
*base_reg
;
145 const reg_entry
*index_reg
;
146 unsigned int log2_scale_factor
;
148 /* SEG gives the seg_entries of this insn. They are zero unless
149 explicit segment overrides are given. */
150 const seg_entry
*seg
[2];
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes
;
155 unsigned char prefix
[MAX_PREFIXES
];
157 /* RM and SIB are the modrm byte and the sib byte where the
158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
167 typedef struct _i386_insn i386_insn
;
169 /* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
171 const char extra_symbol_chars
[] = "*%-(["
180 #if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
182 && !defined (TE_GNU) \
183 && !defined (TE_LINUX) \
184 && !defined (TE_NETWARE) \
185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190 const char *i386_comment_chars
= "#/";
191 #define SVR4_COMMENT_CHARS 1
192 #define PREFIX_SEPARATOR '\\'
195 const char *i386_comment_chars
= "#";
196 #define PREFIX_SEPARATOR '/'
199 /* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
203 first line of the input file. This is because the compiler outputs
204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
206 '/' isn't otherwise defined. */
207 const char line_comment_chars
[] = "#/";
209 const char line_separator_chars
[] = ";";
211 /* Chars that can be used to separate mant from exp in floating point
213 const char EXP_CHARS
[] = "eE";
215 /* Chars that mean this number is a floating point constant
218 const char FLT_CHARS
[] = "fFdDxX";
220 /* Tables for lexical analysis. */
221 static char mnemonic_chars
[256];
222 static char register_chars
[256];
223 static char operand_chars
[256];
224 static char identifier_chars
[256];
225 static char digit_chars
[256];
227 /* Lexical macros. */
228 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229 #define is_operand_char(x) (operand_chars[(unsigned char) x])
230 #define is_register_char(x) (register_chars[(unsigned char) x])
231 #define is_space_char(x) ((x) == ' ')
232 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233 #define is_digit_char(x) (digit_chars[(unsigned char) x])
235 /* All non-digit non-letter characters that may occur in an operand. */
236 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
238 /* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
241 assembler instruction). */
242 static char save_stack
[32];
243 static char *save_stack_p
;
244 #define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246 #define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
249 /* The instruction we're assembling. */
252 /* Possible templates for current insn. */
253 static const templates
*current_templates
;
255 /* Per instruction expressionS buffers: max displacements & immediates. */
256 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
257 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
259 /* Current operand we are working on. */
260 static int this_operand
;
262 /* We support four different modes. FLAG_CODE variable is used to distinguish
269 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
271 static enum flag_code flag_code
;
272 static unsigned int object_64bit
;
273 static int use_rela_relocations
= 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names
[] =
283 /* 1 for intel syntax,
285 static int intel_syntax
= 0;
287 /* 1 if register prefix % not required. */
288 static int allow_naked_reg
= 0;
290 /* 1 if fake index register, eiz/riz, is allowed . */
291 static int allow_index_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
314 /* Bitwise NOT of cpu_arch_flags. */
315 static i386_cpu_flags cpu_arch_flags_not
;
317 /* If we have selected a cpu we are generating instructions for. */
318 static int cpu_arch_tune_set
= 0;
320 /* Cpu we are generating instructions for. */
321 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
323 /* CPU feature flags of cpu we are generating instructions for. */
324 static i386_cpu_flags cpu_arch_tune_flags
;
326 /* CPU instruction set architecture used. */
327 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
329 /* CPU feature flags of instruction set architecture used. */
330 static i386_cpu_flags cpu_arch_isa_flags
;
332 /* If set, conditional jumps are not automatically promoted to handle
333 larger than a byte offset. */
334 static unsigned int no_cond_jump_promotion
= 0;
336 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
337 static symbolS
*GOT_symbol
;
339 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
340 unsigned int x86_dwarf2_return_column
;
342 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
343 int x86_cie_data_alignment
;
345 /* Interface to relax_segment.
346 There are 3 major relax states for 386 jump insns because the
347 different types of jumps add different sizes to frags when we're
348 figuring out what sort of jump to choose to reach a given label. */
351 #define UNCOND_JUMP 0
353 #define COND_JUMP86 2
358 #define SMALL16 (SMALL | CODE16)
360 #define BIG16 (BIG | CODE16)
364 #define INLINE __inline__
370 #define ENCODE_RELAX_STATE(type, size) \
371 ((relax_substateT) (((type) << 2) | (size)))
372 #define TYPE_FROM_RELAX_STATE(s) \
374 #define DISP_SIZE_FROM_RELAX_STATE(s) \
375 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
377 /* This table is used by relax_frag to promote short jumps to long
378 ones where necessary. SMALL (short) jumps may be promoted to BIG
379 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
380 don't allow a short jump in a 32 bit code segment to be promoted to
381 a 16 bit offset jump because it's slower (requires data size
382 prefix), and doesn't work, unless the destination is in the bottom
383 64k of the code segment (The top 16 bits of eip are zeroed). */
385 const relax_typeS md_relax_table
[] =
388 1) most positive reach of this state,
389 2) most negative reach of this state,
390 3) how many bytes this mode will have in the variable part of the frag
391 4) which index into the table to try if we can't fit into this one. */
393 /* UNCOND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
396 /* dword jmp adds 4 bytes to frag:
397 0 extra opcode bytes, 4 displacement bytes. */
399 /* word jmp adds 2 byte2 to frag:
400 0 extra opcode bytes, 2 displacement bytes. */
403 /* COND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 3 bytes to frag:
410 1 extra opcode byte, 2 displacement bytes. */
413 /* COND_JUMP86 states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 4 bytes to frag:
420 1 displacement byte and a 3 byte long branch insn. */
424 static const arch_entry cpu_arch
[] =
426 {"generic32", PROCESSOR_GENERIC32
,
427 CPU_GENERIC32_FLAGS
},
428 {"generic64", PROCESSOR_GENERIC64
,
429 CPU_GENERIC64_FLAGS
},
430 {"i8086", PROCESSOR_UNKNOWN
,
432 {"i186", PROCESSOR_UNKNOWN
,
434 {"i286", PROCESSOR_UNKNOWN
,
436 {"i386", PROCESSOR_I386
,
438 {"i486", PROCESSOR_I486
,
440 {"i586", PROCESSOR_PENTIUM
,
442 {"i686", PROCESSOR_PENTIUMPRO
,
444 {"pentium", PROCESSOR_PENTIUM
,
446 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
448 {"pentiumii", PROCESSOR_PENTIUMPRO
,
450 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
452 {"pentium4", PROCESSOR_PENTIUM4
,
454 {"prescott", PROCESSOR_NOCONA
,
456 {"nocona", PROCESSOR_NOCONA
,
458 {"yonah", PROCESSOR_CORE
,
460 {"core", PROCESSOR_CORE
,
462 {"merom", PROCESSOR_CORE2
,
464 {"core2", PROCESSOR_CORE2
,
468 {"k6_2", PROCESSOR_K6
,
470 {"athlon", PROCESSOR_ATHLON
,
472 {"sledgehammer", PROCESSOR_K8
,
474 {"opteron", PROCESSOR_K8
,
478 {"amdfam10", PROCESSOR_AMDFAM10
,
479 CPU_AMDFAM10_FLAGS
},
480 {".mmx", PROCESSOR_UNKNOWN
,
482 {".sse", PROCESSOR_UNKNOWN
,
484 {".sse2", PROCESSOR_UNKNOWN
,
486 {".sse3", PROCESSOR_UNKNOWN
,
488 {".ssse3", PROCESSOR_UNKNOWN
,
490 {".sse4.1", PROCESSOR_UNKNOWN
,
492 {".sse4.2", PROCESSOR_UNKNOWN
,
494 {".sse4", PROCESSOR_UNKNOWN
,
496 {".3dnow", PROCESSOR_UNKNOWN
,
498 {".3dnowa", PROCESSOR_UNKNOWN
,
500 {".padlock", PROCESSOR_UNKNOWN
,
502 {".pacifica", PROCESSOR_UNKNOWN
,
504 {".svme", PROCESSOR_UNKNOWN
,
506 {".sse4a", PROCESSOR_UNKNOWN
,
508 {".abm", PROCESSOR_UNKNOWN
,
510 {".sse5", PROCESSOR_UNKNOWN
,
514 const pseudo_typeS md_pseudo_table
[] =
516 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
517 {"align", s_align_bytes
, 0},
519 {"align", s_align_ptwo
, 0},
521 {"arch", set_cpu_arch
, 0},
525 {"ffloat", float_cons
, 'f'},
526 {"dfloat", float_cons
, 'd'},
527 {"tfloat", float_cons
, 'x'},
529 {"slong", signed_cons
, 4},
530 {"noopt", s_ignore
, 0},
531 {"optim", s_ignore
, 0},
532 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
533 {"code16", set_code_flag
, CODE_16BIT
},
534 {"code32", set_code_flag
, CODE_32BIT
},
535 {"code64", set_code_flag
, CODE_64BIT
},
536 {"intel_syntax", set_intel_syntax
, 1},
537 {"att_syntax", set_intel_syntax
, 0},
538 {"allow_index_reg", set_allow_index_reg
, 1},
539 {"disallow_index_reg", set_allow_index_reg
, 0},
540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
541 {"largecomm", handle_large_common
, 0},
543 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
544 {"loc", dwarf2_directive_loc
, 0},
545 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
548 {"secrel32", pe_directive_secrel
, 0},
553 /* For interface with expression (). */
554 extern char *input_line_pointer
;
556 /* Hash table for instruction mnemonic lookup. */
557 static struct hash_control
*op_hash
;
559 /* Hash table for register lookup. */
560 static struct hash_control
*reg_hash
;
563 i386_align_code (fragS
*fragP
, int count
)
565 /* Various efficient no-op patterns for aligning code labels.
566 Note: Don't try to assemble the instructions in the comments.
567 0L and 0w are not legal. */
568 static const char f32_1
[] =
570 static const char f32_2
[] =
571 {0x66,0x90}; /* xchg %ax,%ax */
572 static const char f32_3
[] =
573 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
574 static const char f32_4
[] =
575 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_5
[] =
578 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_6
[] =
580 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
581 static const char f32_7
[] =
582 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_8
[] =
585 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_9
[] =
587 {0x89,0xf6, /* movl %esi,%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_10
[] =
590 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_11
[] =
593 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_12
[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
598 static const char f32_13
[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_14
[] =
602 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f16_3
[] =
605 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
606 static const char f16_4
[] =
607 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_5
[] =
610 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
611 static const char f16_6
[] =
612 {0x89,0xf6, /* mov %si,%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_7
[] =
615 {0x8d,0x74,0x00, /* lea 0(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char f16_8
[] =
618 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char jump_31
[] =
621 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
625 static const char *const f32_patt
[] = {
626 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
627 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
629 static const char *const f16_patt
[] = {
630 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
633 static const char alt_3
[] =
635 /* nopl 0(%[re]ax) */
636 static const char alt_4
[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5
[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6
[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7
[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8
[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9
[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10
[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11
[] =
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12
[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13
[] =
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14
[] =
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15
[] =
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11
[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12
[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
713 static const char alt_short_13
[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 static const char alt_short_14
[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15
[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt
[] = {
727 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
728 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
729 alt_short_14
, alt_short_15
731 static const char *const alt_long_patt
[] = {
732 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
733 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
734 alt_long_14
, alt_long_15
737 /* Only align for at least a positive non-zero boundary. */
738 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
744 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
745 PROCESSOR_GENERIC32, f32_patt will be used.
746 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
747 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
748 alt_long_patt will be used.
749 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
750 PROCESSOR_AMDFAM10, alt_short_patt will be used.
752 When -mtune= isn't used, alt_long_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
759 if (flag_code
== CODE_16BIT
)
763 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
765 /* Adjust jump offset. */
766 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
769 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
770 f16_patt
[count
- 1], count
);
774 const char *const *patt
= NULL
;
776 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
778 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
779 switch (cpu_arch_tune
)
781 case PROCESSOR_UNKNOWN
:
782 /* We use cpu_arch_isa_flags to check if we SHOULD
783 optimize for Cpu686. */
784 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
785 patt
= alt_long_patt
;
789 case PROCESSOR_PENTIUMPRO
:
790 case PROCESSOR_PENTIUM4
:
791 case PROCESSOR_NOCONA
:
793 case PROCESSOR_CORE2
:
794 case PROCESSOR_GENERIC64
:
795 patt
= alt_long_patt
;
798 case PROCESSOR_ATHLON
:
800 case PROCESSOR_AMDFAM10
:
801 patt
= alt_short_patt
;
805 case PROCESSOR_PENTIUM
:
806 case PROCESSOR_GENERIC32
:
813 switch (cpu_arch_tune
)
815 case PROCESSOR_UNKNOWN
:
816 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
817 PROCESSOR_UNKNOWN. */
823 case PROCESSOR_PENTIUM
:
825 case PROCESSOR_ATHLON
:
827 case PROCESSOR_AMDFAM10
:
828 case PROCESSOR_GENERIC32
:
829 /* We use cpu_arch_isa_flags to check if we CAN optimize
831 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
832 patt
= alt_short_patt
;
836 case PROCESSOR_PENTIUMPRO
:
837 case PROCESSOR_PENTIUM4
:
838 case PROCESSOR_NOCONA
:
840 case PROCESSOR_CORE2
:
841 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
842 patt
= alt_long_patt
;
846 case PROCESSOR_GENERIC64
:
847 patt
= alt_long_patt
;
852 if (patt
== f32_patt
)
854 /* If the padding is less than 15 bytes, we use the normal
855 ones. Otherwise, we use a jump instruction and adjust
858 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
859 patt
[count
- 1], count
);
862 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
864 /* Adjust jump offset. */
865 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
870 /* Maximum length of an instruction is 15 byte. If the
871 padding is greater than 15 bytes and we don't use jump,
872 we have to break it into smaller pieces. */
877 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
882 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
883 patt
[padding
- 1], padding
);
886 fragP
->fr_var
= count
;
890 uints_all_zero (const unsigned int *x
, unsigned int size
)
908 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
925 uints_equal (const unsigned int *x
, const unsigned int *y
,
937 return x
[0] == y
[0];
944 #define UINTS_ALL_ZERO(x) \
945 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
946 #define UINTS_SET(x, v) \
947 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
948 #define UINTS_CLEAR(x) \
949 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
950 #define UINTS_EQUAL(x, y) \
951 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
954 cpu_flags_check_cpu64 (i386_cpu_flags f
)
956 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
957 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
960 static INLINE i386_cpu_flags
961 cpu_flags_not (i386_cpu_flags x
)
963 switch (ARRAY_SIZE (x
.array
))
966 x
.array
[2] = ~x
.array
[2];
968 x
.array
[1] = ~x
.array
[1];
970 x
.array
[0] = ~x
.array
[0];
977 x
.bitfield
.unused
= 0;
983 static INLINE i386_cpu_flags
984 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
986 switch (ARRAY_SIZE (x
.array
))
989 x
.array
[2] &= y
.array
[2];
991 x
.array
[1] &= y
.array
[1];
993 x
.array
[0] &= y
.array
[0];
1001 static INLINE i386_cpu_flags
1002 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1004 switch (ARRAY_SIZE (x
.array
))
1007 x
.array
[2] |= y
.array
[2];
1009 x
.array
[1] |= y
.array
[1];
1011 x
.array
[0] |= y
.array
[0];
1020 cpu_flags_match (i386_cpu_flags x
)
1022 i386_cpu_flags
not = cpu_arch_flags_not
;
1024 not.bitfield
.cpu64
= 1;
1025 not.bitfield
.cpuno64
= 1;
1027 x
.bitfield
.cpu64
= 0;
1028 x
.bitfield
.cpuno64
= 0;
1030 not = cpu_flags_and (x
, not);
1031 return UINTS_ALL_ZERO (not);
1034 static INLINE i386_operand_type
1035 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1037 switch (ARRAY_SIZE (x
.array
))
1040 x
.array
[2] &= y
.array
[2];
1042 x
.array
[1] &= y
.array
[1];
1044 x
.array
[0] &= y
.array
[0];
1052 static INLINE i386_operand_type
1053 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1055 switch (ARRAY_SIZE (x
.array
))
1058 x
.array
[2] |= y
.array
[2];
1060 x
.array
[1] |= y
.array
[1];
1062 x
.array
[0] |= y
.array
[0];
1070 static INLINE i386_operand_type
1071 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1073 switch (ARRAY_SIZE (x
.array
))
1076 x
.array
[2] ^= y
.array
[2];
1078 x
.array
[1] ^= y
.array
[1];
1080 x
.array
[0] ^= y
.array
[0];
1088 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1089 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1090 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1091 static const i386_operand_type reg16_inoutportreg
1092 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1093 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1094 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1095 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1096 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1097 static const i386_operand_type anydisp
1098 = OPERAND_TYPE_ANYDISP
;
1099 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1100 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1101 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1102 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1103 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1104 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1105 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1106 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1107 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1108 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1119 operand_type_check (i386_operand_type t
, enum operand_type c
)
1124 return (t
.bitfield
.reg8
1127 || t
.bitfield
.reg64
);
1130 return (t
.bitfield
.imm8
1134 || t
.bitfield
.imm32s
1135 || t
.bitfield
.imm64
);
1138 return (t
.bitfield
.disp8
1139 || t
.bitfield
.disp16
1140 || t
.bitfield
.disp32
1141 || t
.bitfield
.disp32s
1142 || t
.bitfield
.disp64
);
1145 return (t
.bitfield
.disp8
1146 || t
.bitfield
.disp16
1147 || t
.bitfield
.disp32
1148 || t
.bitfield
.disp32s
1149 || t
.bitfield
.disp64
1150 || t
.bitfield
.baseindex
);
1158 operand_type_match (i386_operand_type overlap
,
1159 i386_operand_type given
)
1161 i386_operand_type temp
= overlap
;
1163 temp
.bitfield
.jumpabsolute
= 0;
1164 if (UINTS_ALL_ZERO (temp
))
1167 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1168 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1171 /* If given types r0 and r1 are registers they must be of the same type
1172 unless the expected operand type register overlap is null.
1173 Note that Acc in a template matches every size of reg. */
1176 operand_type_register_match (i386_operand_type m0
,
1177 i386_operand_type g0
,
1178 i386_operand_type t0
,
1179 i386_operand_type m1
,
1180 i386_operand_type g1
,
1181 i386_operand_type t1
)
1183 if (!operand_type_check (g0
, reg
))
1186 if (!operand_type_check (g1
, reg
))
1189 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1190 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1191 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1192 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1195 if (m0
.bitfield
.acc
)
1197 t0
.bitfield
.reg8
= 1;
1198 t0
.bitfield
.reg16
= 1;
1199 t0
.bitfield
.reg32
= 1;
1200 t0
.bitfield
.reg64
= 1;
1203 if (m1
.bitfield
.acc
)
1205 t1
.bitfield
.reg8
= 1;
1206 t1
.bitfield
.reg16
= 1;
1207 t1
.bitfield
.reg32
= 1;
1208 t1
.bitfield
.reg64
= 1;
1211 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1212 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1213 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1214 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1217 static INLINE
unsigned int
1218 mode_from_disp_size (i386_operand_type t
)
1220 if (t
.bitfield
.disp8
)
1222 else if (t
.bitfield
.disp16
1223 || t
.bitfield
.disp32
1224 || t
.bitfield
.disp32s
)
1231 fits_in_signed_byte (offsetT num
)
1233 return (num
>= -128) && (num
<= 127);
1237 fits_in_unsigned_byte (offsetT num
)
1239 return (num
& 0xff) == num
;
1243 fits_in_unsigned_word (offsetT num
)
1245 return (num
& 0xffff) == num
;
1249 fits_in_signed_word (offsetT num
)
1251 return (-32768 <= num
) && (num
<= 32767);
1255 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1260 return (!(((offsetT
) -1 << 31) & num
)
1261 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1263 } /* fits_in_signed_long() */
1266 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1271 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1273 } /* fits_in_unsigned_long() */
1275 static i386_operand_type
1276 smallest_imm_type (offsetT num
)
1278 i386_operand_type t
;
1281 t
.bitfield
.imm64
= 1;
1283 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1285 /* This code is disabled on the 486 because all the Imm1 forms
1286 in the opcode table are slower on the i486. They're the
1287 versions with the implicitly specified single-position
1288 displacement, which has another syntax if you really want to
1290 t
.bitfield
.imm1
= 1;
1291 t
.bitfield
.imm8
= 1;
1292 t
.bitfield
.imm8s
= 1;
1293 t
.bitfield
.imm16
= 1;
1294 t
.bitfield
.imm32
= 1;
1295 t
.bitfield
.imm32s
= 1;
1297 else if (fits_in_signed_byte (num
))
1299 t
.bitfield
.imm8
= 1;
1300 t
.bitfield
.imm8s
= 1;
1301 t
.bitfield
.imm16
= 1;
1302 t
.bitfield
.imm32
= 1;
1303 t
.bitfield
.imm32s
= 1;
1305 else if (fits_in_unsigned_byte (num
))
1307 t
.bitfield
.imm8
= 1;
1308 t
.bitfield
.imm16
= 1;
1309 t
.bitfield
.imm32
= 1;
1310 t
.bitfield
.imm32s
= 1;
1312 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1314 t
.bitfield
.imm16
= 1;
1315 t
.bitfield
.imm32
= 1;
1316 t
.bitfield
.imm32s
= 1;
1318 else if (fits_in_signed_long (num
))
1320 t
.bitfield
.imm32
= 1;
1321 t
.bitfield
.imm32s
= 1;
1323 else if (fits_in_unsigned_long (num
))
1324 t
.bitfield
.imm32
= 1;
1330 offset_in_range (offsetT val
, int size
)
1336 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1337 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1338 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1340 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1345 /* If BFD64, sign extend val. */
1346 if (!use_rela_relocations
)
1347 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1348 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1350 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1352 char buf1
[40], buf2
[40];
1354 sprint_value (buf1
, val
);
1355 sprint_value (buf2
, val
& mask
);
1356 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1361 /* Returns 0 if attempting to add a prefix where one from the same
1362 class already exists, 1 if non rep/repne added, 2 if rep/repne
1365 add_prefix (unsigned int prefix
)
1370 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1371 && flag_code
== CODE_64BIT
)
1373 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1374 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1375 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1386 case CS_PREFIX_OPCODE
:
1387 case DS_PREFIX_OPCODE
:
1388 case ES_PREFIX_OPCODE
:
1389 case FS_PREFIX_OPCODE
:
1390 case GS_PREFIX_OPCODE
:
1391 case SS_PREFIX_OPCODE
:
1395 case REPNE_PREFIX_OPCODE
:
1396 case REPE_PREFIX_OPCODE
:
1399 case LOCK_PREFIX_OPCODE
:
1407 case ADDR_PREFIX_OPCODE
:
1411 case DATA_PREFIX_OPCODE
:
1415 if (i
.prefix
[q
] != 0)
1423 i
.prefix
[q
] |= prefix
;
1426 as_bad (_("same type of prefix used twice"));
1432 set_code_flag (int value
)
1435 if (flag_code
== CODE_64BIT
)
1437 cpu_arch_flags
.bitfield
.cpu64
= 1;
1438 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1439 cpu_arch_flags_not
.bitfield
.cpu64
= 0;
1440 cpu_arch_flags_not
.bitfield
.cpuno64
= 1;
1444 cpu_arch_flags
.bitfield
.cpu64
= 0;
1445 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1446 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1447 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1449 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1451 as_bad (_("64bit mode not supported on this CPU."));
1453 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1455 as_bad (_("32bit mode not supported on this CPU."));
1457 stackop_size
= '\0';
1461 set_16bit_gcc_code_flag (int new_code_flag
)
1463 flag_code
= new_code_flag
;
1464 if (flag_code
!= CODE_16BIT
)
1466 cpu_arch_flags
.bitfield
.cpu64
= 0;
1467 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1468 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1469 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1470 stackop_size
= LONG_MNEM_SUFFIX
;
1474 set_intel_syntax (int syntax_flag
)
1476 /* Find out if register prefixing is specified. */
1477 int ask_naked_reg
= 0;
1480 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1482 char *string
= input_line_pointer
;
1483 int e
= get_symbol_end ();
1485 if (strcmp (string
, "prefix") == 0)
1487 else if (strcmp (string
, "noprefix") == 0)
1490 as_bad (_("bad argument to syntax directive."));
1491 *input_line_pointer
= e
;
1493 demand_empty_rest_of_line ();
1495 intel_syntax
= syntax_flag
;
1497 if (ask_naked_reg
== 0)
1498 allow_naked_reg
= (intel_syntax
1499 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1501 allow_naked_reg
= (ask_naked_reg
< 0);
1503 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1504 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1505 register_prefix
= allow_naked_reg
? "" : "%";
1509 set_allow_index_reg (int flag
)
1511 allow_index_reg
= flag
;
1515 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1519 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1521 char *string
= input_line_pointer
;
1522 int e
= get_symbol_end ();
1524 i386_cpu_flags flags
;
1526 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1528 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1532 cpu_arch_name
= cpu_arch
[i
].name
;
1533 cpu_sub_arch_name
= NULL
;
1534 cpu_arch_flags
= cpu_arch
[i
].flags
;
1535 if (flag_code
== CODE_64BIT
)
1537 cpu_arch_flags
.bitfield
.cpu64
= 1;
1538 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1542 cpu_arch_flags
.bitfield
.cpu64
= 0;
1543 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1545 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1546 cpu_arch_isa
= cpu_arch
[i
].type
;
1547 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1548 if (!cpu_arch_tune_set
)
1550 cpu_arch_tune
= cpu_arch_isa
;
1551 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1556 flags
= cpu_flags_or (cpu_arch_flags
,
1558 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1560 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1561 cpu_arch_flags
= flags
;
1562 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1564 *input_line_pointer
= e
;
1565 demand_empty_rest_of_line ();
1569 if (i
>= ARRAY_SIZE (cpu_arch
))
1570 as_bad (_("no such architecture: `%s'"), string
);
1572 *input_line_pointer
= e
;
1575 as_bad (_("missing cpu architecture"));
1577 no_cond_jump_promotion
= 0;
1578 if (*input_line_pointer
== ','
1579 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1581 char *string
= ++input_line_pointer
;
1582 int e
= get_symbol_end ();
1584 if (strcmp (string
, "nojumps") == 0)
1585 no_cond_jump_promotion
= 1;
1586 else if (strcmp (string
, "jumps") == 0)
1589 as_bad (_("no such architecture modifier: `%s'"), string
);
1591 *input_line_pointer
= e
;
1594 demand_empty_rest_of_line ();
1600 if (!strcmp (default_arch
, "x86_64"))
1601 return bfd_mach_x86_64
;
1602 else if (!strcmp (default_arch
, "i386"))
1603 return bfd_mach_i386_i386
;
1605 as_fatal (_("Unknown architecture"));
1611 const char *hash_err
;
1613 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1615 /* Initialize op_hash hash table. */
1616 op_hash
= hash_new ();
1619 const template *optab
;
1620 templates
*core_optab
;
1622 /* Setup for loop. */
1624 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1625 core_optab
->start
= optab
;
1630 if (optab
->name
== NULL
1631 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1633 /* different name --> ship out current template list;
1634 add to hash table; & begin anew. */
1635 core_optab
->end
= optab
;
1636 hash_err
= hash_insert (op_hash
,
1641 as_fatal (_("Internal Error: Can't hash %s: %s"),
1645 if (optab
->name
== NULL
)
1647 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1648 core_optab
->start
= optab
;
1653 /* Initialize reg_hash hash table. */
1654 reg_hash
= hash_new ();
1656 const reg_entry
*regtab
;
1657 unsigned int regtab_size
= i386_regtab_size
;
1659 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1661 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1663 as_fatal (_("Internal Error: Can't hash %s: %s"),
1669 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1674 for (c
= 0; c
< 256; c
++)
1679 mnemonic_chars
[c
] = c
;
1680 register_chars
[c
] = c
;
1681 operand_chars
[c
] = c
;
1683 else if (ISLOWER (c
))
1685 mnemonic_chars
[c
] = c
;
1686 register_chars
[c
] = c
;
1687 operand_chars
[c
] = c
;
1689 else if (ISUPPER (c
))
1691 mnemonic_chars
[c
] = TOLOWER (c
);
1692 register_chars
[c
] = mnemonic_chars
[c
];
1693 operand_chars
[c
] = c
;
1696 if (ISALPHA (c
) || ISDIGIT (c
))
1697 identifier_chars
[c
] = c
;
1700 identifier_chars
[c
] = c
;
1701 operand_chars
[c
] = c
;
1706 identifier_chars
['@'] = '@';
1709 identifier_chars
['?'] = '?';
1710 operand_chars
['?'] = '?';
1712 digit_chars
['-'] = '-';
1713 mnemonic_chars
['-'] = '-';
1714 mnemonic_chars
['.'] = '.';
1715 identifier_chars
['_'] = '_';
1716 identifier_chars
['.'] = '.';
1718 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1719 operand_chars
[(unsigned char) *p
] = *p
;
1722 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1725 record_alignment (text_section
, 2);
1726 record_alignment (data_section
, 2);
1727 record_alignment (bss_section
, 2);
1731 if (flag_code
== CODE_64BIT
)
1733 x86_dwarf2_return_column
= 16;
1734 x86_cie_data_alignment
= -8;
1738 x86_dwarf2_return_column
= 8;
1739 x86_cie_data_alignment
= -4;
1744 i386_print_statistics (FILE *file
)
1746 hash_print_statistics (file
, "i386 opcode", op_hash
);
1747 hash_print_statistics (file
, "i386 register", reg_hash
);
1752 /* Debugging routines for md_assemble. */
1753 static void pte (template *);
1754 static void pt (i386_operand_type
);
1755 static void pe (expressionS
*);
1756 static void ps (symbolS
*);
1759 pi (char *line
, i386_insn
*x
)
1763 fprintf (stdout
, "%s: template ", line
);
1765 fprintf (stdout
, " address: base %s index %s scale %x\n",
1766 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1767 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1768 x
->log2_scale_factor
);
1769 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1770 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1771 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1772 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1773 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1774 (x
->rex
& REX_W
) != 0,
1775 (x
->rex
& REX_R
) != 0,
1776 (x
->rex
& REX_X
) != 0,
1777 (x
->rex
& REX_B
) != 0);
1778 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
1779 x
->drex
.reg
, x
->drex
.rex
);
1780 for (i
= 0; i
< x
->operands
; i
++)
1782 fprintf (stdout
, " #%d: ", i
+ 1);
1784 fprintf (stdout
, "\n");
1785 if (x
->types
[i
].bitfield
.reg8
1786 || x
->types
[i
].bitfield
.reg16
1787 || x
->types
[i
].bitfield
.reg32
1788 || x
->types
[i
].bitfield
.reg64
1789 || x
->types
[i
].bitfield
.regmmx
1790 || x
->types
[i
].bitfield
.regxmm
1791 || x
->types
[i
].bitfield
.sreg2
1792 || x
->types
[i
].bitfield
.sreg3
1793 || x
->types
[i
].bitfield
.control
1794 || x
->types
[i
].bitfield
.debug
1795 || x
->types
[i
].bitfield
.test
)
1796 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1797 if (operand_type_check (x
->types
[i
], imm
))
1799 if (operand_type_check (x
->types
[i
], disp
))
1800 pe (x
->op
[i
].disps
);
1808 fprintf (stdout
, " %d operands ", t
->operands
);
1809 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1810 if (t
->extension_opcode
!= None
)
1811 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1812 if (t
->opcode_modifier
.d
)
1813 fprintf (stdout
, "D");
1814 if (t
->opcode_modifier
.w
)
1815 fprintf (stdout
, "W");
1816 fprintf (stdout
, "\n");
1817 for (i
= 0; i
< t
->operands
; i
++)
1819 fprintf (stdout
, " #%d type ", i
+ 1);
1820 pt (t
->operand_types
[i
]);
1821 fprintf (stdout
, "\n");
1828 fprintf (stdout
, " operation %d\n", e
->X_op
);
1829 fprintf (stdout
, " add_number %ld (%lx)\n",
1830 (long) e
->X_add_number
, (long) e
->X_add_number
);
1831 if (e
->X_add_symbol
)
1833 fprintf (stdout
, " add_symbol ");
1834 ps (e
->X_add_symbol
);
1835 fprintf (stdout
, "\n");
1839 fprintf (stdout
, " op_symbol ");
1840 ps (e
->X_op_symbol
);
1841 fprintf (stdout
, "\n");
1848 fprintf (stdout
, "%s type %s%s",
1850 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1851 segment_name (S_GET_SEGMENT (s
)));
1854 static struct type_name
1856 i386_operand_type mask
;
1859 const type_names
[] =
1861 { OPERAND_TYPE_REG8
, "r8" },
1862 { OPERAND_TYPE_REG16
, "r16" },
1863 { OPERAND_TYPE_REG32
, "r32" },
1864 { OPERAND_TYPE_REG64
, "r64" },
1865 { OPERAND_TYPE_IMM8
, "i8" },
1866 { OPERAND_TYPE_IMM8
, "i8s" },
1867 { OPERAND_TYPE_IMM16
, "i16" },
1868 { OPERAND_TYPE_IMM32
, "i32" },
1869 { OPERAND_TYPE_IMM32S
, "i32s" },
1870 { OPERAND_TYPE_IMM64
, "i64" },
1871 { OPERAND_TYPE_IMM1
, "i1" },
1872 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1873 { OPERAND_TYPE_DISP8
, "d8" },
1874 { OPERAND_TYPE_DISP16
, "d16" },
1875 { OPERAND_TYPE_DISP32
, "d32" },
1876 { OPERAND_TYPE_DISP32S
, "d32s" },
1877 { OPERAND_TYPE_DISP64
, "d64" },
1878 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1879 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1880 { OPERAND_TYPE_CONTROL
, "control reg" },
1881 { OPERAND_TYPE_TEST
, "test reg" },
1882 { OPERAND_TYPE_DEBUG
, "debug reg" },
1883 { OPERAND_TYPE_FLOATREG
, "FReg" },
1884 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1885 { OPERAND_TYPE_SREG2
, "SReg2" },
1886 { OPERAND_TYPE_SREG3
, "SReg3" },
1887 { OPERAND_TYPE_ACC
, "Acc" },
1888 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1889 { OPERAND_TYPE_REGMMX
, "rMMX" },
1890 { OPERAND_TYPE_REGXMM
, "rXMM" },
1891 { OPERAND_TYPE_ESSEG
, "es" },
1895 pt (i386_operand_type t
)
1898 i386_operand_type a
;
1900 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1902 a
= operand_type_and (t
, type_names
[j
].mask
);
1903 if (!UINTS_ALL_ZERO (a
))
1904 fprintf (stdout
, "%s, ", type_names
[j
].name
);
1909 #endif /* DEBUG386 */
1911 static bfd_reloc_code_real_type
1912 reloc (unsigned int size
,
1915 bfd_reloc_code_real_type other
)
1917 if (other
!= NO_RELOC
)
1919 reloc_howto_type
*reloc
;
1924 case BFD_RELOC_X86_64_GOT32
:
1925 return BFD_RELOC_X86_64_GOT64
;
1927 case BFD_RELOC_X86_64_PLTOFF64
:
1928 return BFD_RELOC_X86_64_PLTOFF64
;
1930 case BFD_RELOC_X86_64_GOTPC32
:
1931 other
= BFD_RELOC_X86_64_GOTPC64
;
1933 case BFD_RELOC_X86_64_GOTPCREL
:
1934 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1936 case BFD_RELOC_X86_64_TPOFF32
:
1937 other
= BFD_RELOC_X86_64_TPOFF64
;
1939 case BFD_RELOC_X86_64_DTPOFF32
:
1940 other
= BFD_RELOC_X86_64_DTPOFF64
;
1946 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1947 if (size
== 4 && flag_code
!= CODE_64BIT
)
1950 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1952 as_bad (_("unknown relocation (%u)"), other
);
1953 else if (size
!= bfd_get_reloc_size (reloc
))
1954 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1955 bfd_get_reloc_size (reloc
),
1957 else if (pcrel
&& !reloc
->pc_relative
)
1958 as_bad (_("non-pc-relative relocation for pc-relative field"));
1959 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1961 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1963 as_bad (_("relocated field and relocation type differ in signedness"));
1972 as_bad (_("there are no unsigned pc-relative relocations"));
1975 case 1: return BFD_RELOC_8_PCREL
;
1976 case 2: return BFD_RELOC_16_PCREL
;
1977 case 4: return BFD_RELOC_32_PCREL
;
1978 case 8: return BFD_RELOC_64_PCREL
;
1980 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1987 case 4: return BFD_RELOC_X86_64_32S
;
1992 case 1: return BFD_RELOC_8
;
1993 case 2: return BFD_RELOC_16
;
1994 case 4: return BFD_RELOC_32
;
1995 case 8: return BFD_RELOC_64
;
1997 as_bad (_("cannot do %s %u byte relocation"),
1998 sign
> 0 ? "signed" : "unsigned", size
);
2002 return BFD_RELOC_NONE
;
2005 /* Here we decide which fixups can be adjusted to make them relative to
2006 the beginning of the section instead of the symbol. Basically we need
2007 to make sure that the dynamic relocations are done correctly, so in
2008 some cases we force the original symbol to be used. */
2011 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2017 /* Don't adjust pc-relative references to merge sections in 64-bit
2019 if (use_rela_relocations
2020 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2024 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2025 and changed later by validate_fix. */
2026 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2027 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2030 /* adjust_reloc_syms doesn't know about the GOT. */
2031 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2032 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2033 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2034 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2035 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2036 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2037 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2038 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2040 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2042 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2043 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2056 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2057 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2058 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2065 intel_float_operand (const char *mnemonic
)
2067 /* Note that the value returned is meaningful only for opcodes with (memory)
2068 operands, hence the code here is free to improperly handle opcodes that
2069 have no operands (for better performance and smaller code). */
2071 if (mnemonic
[0] != 'f')
2072 return 0; /* non-math */
2074 switch (mnemonic
[1])
2076 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2077 the fs segment override prefix not currently handled because no
2078 call path can make opcodes without operands get here */
2080 return 2 /* integer op */;
2082 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2083 return 3; /* fldcw/fldenv */
2086 if (mnemonic
[2] != 'o' /* fnop */)
2087 return 3; /* non-waiting control op */
2090 if (mnemonic
[2] == 's')
2091 return 3; /* frstor/frstpm */
2094 if (mnemonic
[2] == 'a')
2095 return 3; /* fsave */
2096 if (mnemonic
[2] == 't')
2098 switch (mnemonic
[3])
2100 case 'c': /* fstcw */
2101 case 'd': /* fstdw */
2102 case 'e': /* fstenv */
2103 case 's': /* fsts[gw] */
2109 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2110 return 0; /* fxsave/fxrstor are not really math ops */
2117 /* This is the guts of the machine-dependent assembler. LINE points to a
2118 machine dependent instruction. This function is supposed to emit
2119 the frags/bytes it assembles to. */
2126 char mnemonic
[MAX_MNEM_SIZE
];
2128 /* Initialize globals. */
2129 memset (&i
, '\0', sizeof (i
));
2130 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2131 i
.reloc
[j
] = NO_RELOC
;
2132 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2133 memset (im_expressions
, '\0', sizeof (im_expressions
));
2134 save_stack_p
= save_stack
;
2136 /* First parse an instruction mnemonic & call i386_operand for the operands.
2137 We assume that the scrubber has arranged it so that line[0] is the valid
2138 start of a (possibly prefixed) mnemonic. */
2140 line
= parse_insn (line
, mnemonic
);
2144 line
= parse_operands (line
, mnemonic
);
2148 /* Now we've parsed the mnemonic into a set of templates, and have the
2149 operands at hand. */
2151 /* All intel opcodes have reversed operands except for "bound" and
2152 "enter". We also don't reverse intersegment "jmp" and "call"
2153 instructions with 2 immediate operands so that the immediate segment
2154 precedes the offset, as it does when in AT&T mode. */
2157 && (strcmp (mnemonic
, "bound") != 0)
2158 && (strcmp (mnemonic
, "invlpga") != 0)
2159 && !(operand_type_check (i
.types
[0], imm
)
2160 && operand_type_check (i
.types
[1], imm
)))
2163 /* The order of the immediates should be reversed
2164 for 2 immediates extrq and insertq instructions */
2165 if (i
.imm_operands
== 2
2166 && (strcmp (mnemonic
, "extrq") == 0
2167 || strcmp (mnemonic
, "insertq") == 0))
2168 swap_2_operands (0, 1);
2173 /* Don't optimize displacement for movabs since it only takes 64bit
2176 && (flag_code
!= CODE_64BIT
2177 || strcmp (mnemonic
, "movabs") != 0))
2180 /* Next, we find a template that matches the given insn,
2181 making sure the overlap of the given operands types is consistent
2182 with the template operand types. */
2184 if (!match_template ())
2189 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2191 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
2192 i
.tm
.base_opcode
^= Opcode_FloatR
;
2194 /* Zap movzx and movsx suffix. The suffix may have been set from
2195 "word ptr" or "byte ptr" on the source operand, but we'll use
2196 the suffix later to choose the destination register. */
2197 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2199 if (i
.reg_operands
< 2
2201 && (!i
.tm
.opcode_modifier
.no_bsuf
2202 || !i
.tm
.opcode_modifier
.no_wsuf
2203 || !i
.tm
.opcode_modifier
.no_lsuf
2204 || !i
.tm
.opcode_modifier
.no_ssuf
2205 || !i
.tm
.opcode_modifier
.no_xsuf
2206 || !i
.tm
.opcode_modifier
.no_qsuf
))
2207 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2213 if (i
.tm
.opcode_modifier
.fwait
)
2214 if (!add_prefix (FWAIT_OPCODE
))
2217 /* Check string instruction segment overrides. */
2218 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2220 if (!check_string ())
2224 if (!process_suffix ())
2227 /* Make still unresolved immediate matches conform to size of immediate
2228 given in i.suffix. */
2229 if (!finalize_imm ())
2232 if (i
.types
[0].bitfield
.imm1
)
2233 i
.imm_operands
= 0; /* kludge for shift insns. */
2235 for (j
= 0; j
< 3; j
++)
2236 if (i
.types
[j
].bitfield
.inoutportreg
2237 || i
.types
[j
].bitfield
.shiftcount
2238 || i
.types
[j
].bitfield
.acc
2239 || i
.types
[j
].bitfield
.floatacc
)
2242 if (i
.tm
.opcode_modifier
.immext
)
2246 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2248 /* Streaming SIMD extensions 3 Instructions have the fixed
2249 operands with an opcode suffix which is coded in the same
2250 place as an 8-bit immediate field would be. Here we check
2251 those operands and remove them afterwards. */
2254 for (x
= 0; x
< i
.operands
; x
++)
2255 if (i
.op
[x
].regs
->reg_num
!= x
)
2256 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2258 i
.op
[x
].regs
->reg_name
,
2264 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2265 opcode suffix which is coded in the same place as an 8-bit
2266 immediate field would be. Here we fake an 8-bit immediate
2267 operand from the opcode suffix stored in tm.extension_opcode.
2268 SSE5 also uses this encoding, for some of its 3 argument
2271 assert (i
.imm_operands
== 0
2273 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2274 && i
.operands
<= 3)));
2276 exp
= &im_expressions
[i
.imm_operands
++];
2277 i
.op
[i
.operands
].imms
= exp
;
2278 UINTS_CLEAR (i
.types
[i
.operands
]);
2279 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2281 exp
->X_op
= O_constant
;
2282 exp
->X_add_number
= i
.tm
.extension_opcode
;
2283 i
.tm
.extension_opcode
= None
;
2286 /* For insns with operands there are more diddles to do to the opcode. */
2289 if (!process_operands ())
2292 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2294 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2295 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2298 /* Handle conversion of 'int $3' --> special int3 insn. */
2299 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2301 i
.tm
.base_opcode
= INT3_OPCODE
;
2305 if ((i
.tm
.opcode_modifier
.jump
2306 || i
.tm
.opcode_modifier
.jumpbyte
2307 || i
.tm
.opcode_modifier
.jumpdword
)
2308 && i
.op
[0].disps
->X_op
== O_constant
)
2310 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2311 the absolute address given by the constant. Since ix86 jumps and
2312 calls are pc relative, we need to generate a reloc. */
2313 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2314 i
.op
[0].disps
->X_op
= O_symbol
;
2317 if (i
.tm
.opcode_modifier
.rex64
)
2320 /* For 8 bit registers we need an empty rex prefix. Also if the
2321 instruction already has a prefix, we need to convert old
2322 registers to new ones. */
2324 if ((i
.types
[0].bitfield
.reg8
2325 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2326 || (i
.types
[1].bitfield
.reg8
2327 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2328 || ((i
.types
[0].bitfield
.reg8
2329 || i
.types
[1].bitfield
.reg8
)
2334 i
.rex
|= REX_OPCODE
;
2335 for (x
= 0; x
< 2; x
++)
2337 /* Look for 8 bit operand that uses old registers. */
2338 if (i
.types
[x
].bitfield
.reg8
2339 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2341 /* In case it is "hi" register, give up. */
2342 if (i
.op
[x
].regs
->reg_num
> 3)
2343 as_bad (_("can't encode register '%s%s' in an "
2344 "instruction requiring REX prefix."),
2345 register_prefix
, i
.op
[x
].regs
->reg_name
);
2347 /* Otherwise it is equivalent to the extended register.
2348 Since the encoding doesn't change this is merely
2349 cosmetic cleanup for debug output. */
2351 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2356 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2358 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2363 else if (i
.rex
!= 0)
2364 add_prefix (REX_OPCODE
| i
.rex
);
2366 /* We are ready to output the insn. */
2371 parse_insn (char *line
, char *mnemonic
)
2374 char *token_start
= l
;
2379 /* Non-zero if we found a prefix only acceptable with string insns. */
2380 const char *expecting_string_instruction
= NULL
;
2385 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2388 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2390 as_bad (_("no such instruction: `%s'"), token_start
);
2395 if (!is_space_char (*l
)
2396 && *l
!= END_OF_INSN
2398 || (*l
!= PREFIX_SEPARATOR
2401 as_bad (_("invalid character %s in mnemonic"),
2402 output_invalid (*l
));
2405 if (token_start
== l
)
2407 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2408 as_bad (_("expecting prefix; got nothing"));
2410 as_bad (_("expecting mnemonic; got nothing"));
2414 /* Look up instruction (or prefix) via hash table. */
2415 current_templates
= hash_find (op_hash
, mnemonic
);
2417 if (*l
!= END_OF_INSN
2418 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2419 && current_templates
2420 && current_templates
->start
->opcode_modifier
.isprefix
)
2422 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2424 as_bad ((flag_code
!= CODE_64BIT
2425 ? _("`%s' is only supported in 64-bit mode")
2426 : _("`%s' is not supported in 64-bit mode")),
2427 current_templates
->start
->name
);
2430 /* If we are in 16-bit mode, do not allow addr16 or data16.
2431 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2432 if ((current_templates
->start
->opcode_modifier
.size16
2433 || current_templates
->start
->opcode_modifier
.size32
)
2434 && flag_code
!= CODE_64BIT
2435 && (current_templates
->start
->opcode_modifier
.size32
2436 ^ (flag_code
== CODE_16BIT
)))
2438 as_bad (_("redundant %s prefix"),
2439 current_templates
->start
->name
);
2442 /* Add prefix, checking for repeated prefixes. */
2443 switch (add_prefix (current_templates
->start
->base_opcode
))
2448 expecting_string_instruction
= current_templates
->start
->name
;
2451 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2458 if (!current_templates
)
2460 /* See if we can get a match by trimming off a suffix. */
2463 case WORD_MNEM_SUFFIX
:
2464 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2465 i
.suffix
= SHORT_MNEM_SUFFIX
;
2467 case BYTE_MNEM_SUFFIX
:
2468 case QWORD_MNEM_SUFFIX
:
2469 i
.suffix
= mnem_p
[-1];
2471 current_templates
= hash_find (op_hash
, mnemonic
);
2473 case SHORT_MNEM_SUFFIX
:
2474 case LONG_MNEM_SUFFIX
:
2477 i
.suffix
= mnem_p
[-1];
2479 current_templates
= hash_find (op_hash
, mnemonic
);
2487 if (intel_float_operand (mnemonic
) == 1)
2488 i
.suffix
= SHORT_MNEM_SUFFIX
;
2490 i
.suffix
= LONG_MNEM_SUFFIX
;
2492 current_templates
= hash_find (op_hash
, mnemonic
);
2496 if (!current_templates
)
2498 as_bad (_("no such instruction: `%s'"), token_start
);
2503 if (current_templates
->start
->opcode_modifier
.jump
2504 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2506 /* Check for a branch hint. We allow ",pt" and ",pn" for
2507 predict taken and predict not taken respectively.
2508 I'm not sure that branch hints actually do anything on loop
2509 and jcxz insns (JumpByte) for current Pentium4 chips. They
2510 may work in the future and it doesn't hurt to accept them
2512 if (l
[0] == ',' && l
[1] == 'p')
2516 if (!add_prefix (DS_PREFIX_OPCODE
))
2520 else if (l
[2] == 'n')
2522 if (!add_prefix (CS_PREFIX_OPCODE
))
2528 /* Any other comma loses. */
2531 as_bad (_("invalid character %s in mnemonic"),
2532 output_invalid (*l
));
2536 /* Check if instruction is supported on specified architecture. */
2538 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2540 if (cpu_flags_match (t
->cpu_flags
))
2542 if (cpu_flags_check_cpu64 (t
->cpu_flags
))
2545 if (!(supported
& 2))
2547 as_bad (flag_code
== CODE_64BIT
2548 ? _("`%s' is not supported in 64-bit mode")
2549 : _("`%s' is only supported in 64-bit mode"),
2550 current_templates
->start
->name
);
2553 if (!(supported
& 1))
2555 as_warn (_("`%s' is not supported on `%s%s'"),
2556 current_templates
->start
->name
,
2558 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2560 else if (!cpu_arch_flags
.bitfield
.cpui386
2561 && (flag_code
!= CODE_16BIT
))
2563 as_warn (_("use .code16 to ensure correct addressing mode"));
2566 /* Check for rep/repne without a string instruction. */
2567 if (expecting_string_instruction
)
2569 static templates override
;
2571 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2572 if (t
->opcode_modifier
.isstring
)
2574 if (t
>= current_templates
->end
)
2576 as_bad (_("expecting string instruction after `%s'"),
2577 expecting_string_instruction
);
2580 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2581 if (!t
->opcode_modifier
.isstring
)
2584 current_templates
= &override
;
2591 parse_operands (char *l
, const char *mnemonic
)
2595 /* 1 if operand is pending after ','. */
2596 unsigned int expecting_operand
= 0;
2598 /* Non-zero if operand parens not balanced. */
2599 unsigned int paren_not_balanced
;
2601 while (*l
!= END_OF_INSN
)
2603 /* Skip optional white space before operand. */
2604 if (is_space_char (*l
))
2606 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2608 as_bad (_("invalid character %s before operand %d"),
2609 output_invalid (*l
),
2613 token_start
= l
; /* after white space */
2614 paren_not_balanced
= 0;
2615 while (paren_not_balanced
|| *l
!= ',')
2617 if (*l
== END_OF_INSN
)
2619 if (paren_not_balanced
)
2622 as_bad (_("unbalanced parenthesis in operand %d."),
2625 as_bad (_("unbalanced brackets in operand %d."),
2630 break; /* we are done */
2632 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2634 as_bad (_("invalid character %s in operand %d"),
2635 output_invalid (*l
),
2642 ++paren_not_balanced
;
2644 --paren_not_balanced
;
2649 ++paren_not_balanced
;
2651 --paren_not_balanced
;
2655 if (l
!= token_start
)
2656 { /* Yes, we've read in another operand. */
2657 unsigned int operand_ok
;
2658 this_operand
= i
.operands
++;
2659 if (i
.operands
> MAX_OPERANDS
)
2661 as_bad (_("spurious operands; (%d operands/instruction max)"),
2665 /* Now parse operand adding info to 'i' as we go along. */
2666 END_STRING_AND_SAVE (l
);
2670 i386_intel_operand (token_start
,
2671 intel_float_operand (mnemonic
));
2673 operand_ok
= i386_operand (token_start
);
2675 RESTORE_END_STRING (l
);
2681 if (expecting_operand
)
2683 expecting_operand_after_comma
:
2684 as_bad (_("expecting operand after ','; got nothing"));
2689 as_bad (_("expecting operand before ','; got nothing"));
2694 /* Now *l must be either ',' or END_OF_INSN. */
2697 if (*++l
== END_OF_INSN
)
2699 /* Just skip it, if it's \n complain. */
2700 goto expecting_operand_after_comma
;
2702 expecting_operand
= 1;
2709 swap_2_operands (int xchg1
, int xchg2
)
2711 union i386_op temp_op
;
2712 i386_operand_type temp_type
;
2713 enum bfd_reloc_code_real temp_reloc
;
2715 temp_type
= i
.types
[xchg2
];
2716 i
.types
[xchg2
] = i
.types
[xchg1
];
2717 i
.types
[xchg1
] = temp_type
;
2718 temp_op
= i
.op
[xchg2
];
2719 i
.op
[xchg2
] = i
.op
[xchg1
];
2720 i
.op
[xchg1
] = temp_op
;
2721 temp_reloc
= i
.reloc
[xchg2
];
2722 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2723 i
.reloc
[xchg1
] = temp_reloc
;
2727 swap_operands (void)
2732 swap_2_operands (1, i
.operands
- 2);
2735 swap_2_operands (0, i
.operands
- 1);
2741 if (i
.mem_operands
== 2)
2743 const seg_entry
*temp_seg
;
2744 temp_seg
= i
.seg
[0];
2745 i
.seg
[0] = i
.seg
[1];
2746 i
.seg
[1] = temp_seg
;
2750 /* Try to ensure constant immediates are represented in the smallest
2755 char guess_suffix
= 0;
2759 guess_suffix
= i
.suffix
;
2760 else if (i
.reg_operands
)
2762 /* Figure out a suffix from the last register operand specified.
2763 We can't do this properly yet, ie. excluding InOutPortReg,
2764 but the following works for instructions with immediates.
2765 In any case, we can't set i.suffix yet. */
2766 for (op
= i
.operands
; --op
>= 0;)
2767 if (i
.types
[op
].bitfield
.reg8
)
2769 guess_suffix
= BYTE_MNEM_SUFFIX
;
2772 else if (i
.types
[op
].bitfield
.reg16
)
2774 guess_suffix
= WORD_MNEM_SUFFIX
;
2777 else if (i
.types
[op
].bitfield
.reg32
)
2779 guess_suffix
= LONG_MNEM_SUFFIX
;
2782 else if (i
.types
[op
].bitfield
.reg64
)
2784 guess_suffix
= QWORD_MNEM_SUFFIX
;
2788 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2789 guess_suffix
= WORD_MNEM_SUFFIX
;
2791 for (op
= i
.operands
; --op
>= 0;)
2792 if (operand_type_check (i
.types
[op
], imm
))
2794 switch (i
.op
[op
].imms
->X_op
)
2797 /* If a suffix is given, this operand may be shortened. */
2798 switch (guess_suffix
)
2800 case LONG_MNEM_SUFFIX
:
2801 i
.types
[op
].bitfield
.imm32
= 1;
2802 i
.types
[op
].bitfield
.imm64
= 1;
2804 case WORD_MNEM_SUFFIX
:
2805 i
.types
[op
].bitfield
.imm16
= 1;
2806 i
.types
[op
].bitfield
.imm32
= 1;
2807 i
.types
[op
].bitfield
.imm32s
= 1;
2808 i
.types
[op
].bitfield
.imm64
= 1;
2810 case BYTE_MNEM_SUFFIX
:
2811 i
.types
[op
].bitfield
.imm8
= 1;
2812 i
.types
[op
].bitfield
.imm8s
= 1;
2813 i
.types
[op
].bitfield
.imm16
= 1;
2814 i
.types
[op
].bitfield
.imm32
= 1;
2815 i
.types
[op
].bitfield
.imm32s
= 1;
2816 i
.types
[op
].bitfield
.imm64
= 1;
2820 /* If this operand is at most 16 bits, convert it
2821 to a signed 16 bit number before trying to see
2822 whether it will fit in an even smaller size.
2823 This allows a 16-bit operand such as $0xffe0 to
2824 be recognised as within Imm8S range. */
2825 if ((i
.types
[op
].bitfield
.imm16
)
2826 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2828 i
.op
[op
].imms
->X_add_number
=
2829 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2831 if ((i
.types
[op
].bitfield
.imm32
)
2832 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2835 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2836 ^ ((offsetT
) 1 << 31))
2837 - ((offsetT
) 1 << 31));
2840 = operand_type_or (i
.types
[op
],
2841 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2843 /* We must avoid matching of Imm32 templates when 64bit
2844 only immediate is available. */
2845 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2846 i
.types
[op
].bitfield
.imm32
= 0;
2853 /* Symbols and expressions. */
2855 /* Convert symbolic operand to proper sizes for matching, but don't
2856 prevent matching a set of insns that only supports sizes other
2857 than those matching the insn suffix. */
2859 i386_operand_type mask
, allowed
;
2863 UINTS_CLEAR (allowed
);
2865 for (t
= current_templates
->start
;
2866 t
< current_templates
->end
;
2868 allowed
= operand_type_or (allowed
,
2869 t
->operand_types
[op
]);
2870 switch (guess_suffix
)
2872 case QWORD_MNEM_SUFFIX
:
2873 mask
.bitfield
.imm64
= 1;
2874 mask
.bitfield
.imm32s
= 1;
2876 case LONG_MNEM_SUFFIX
:
2877 mask
.bitfield
.imm32
= 1;
2879 case WORD_MNEM_SUFFIX
:
2880 mask
.bitfield
.imm16
= 1;
2882 case BYTE_MNEM_SUFFIX
:
2883 mask
.bitfield
.imm8
= 1;
2888 allowed
= operand_type_and (mask
, allowed
);
2889 if (!UINTS_ALL_ZERO (allowed
))
2890 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2897 /* Try to use the smallest displacement type too. */
2899 optimize_disp (void)
2903 for (op
= i
.operands
; --op
>= 0;)
2904 if (operand_type_check (i
.types
[op
], disp
))
2906 if (i
.op
[op
].disps
->X_op
== O_constant
)
2908 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2910 if (i
.types
[op
].bitfield
.disp16
2911 && (disp
& ~(offsetT
) 0xffff) == 0)
2913 /* If this operand is at most 16 bits, convert
2914 to a signed 16 bit number and don't use 64bit
2916 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2917 i
.types
[op
].bitfield
.disp64
= 0;
2919 if (i
.types
[op
].bitfield
.disp32
2920 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2922 /* If this operand is at most 32 bits, convert
2923 to a signed 32 bit number and don't use 64bit
2925 disp
&= (((offsetT
) 2 << 31) - 1);
2926 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2927 i
.types
[op
].bitfield
.disp64
= 0;
2929 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
2931 i
.types
[op
].bitfield
.disp8
= 0;
2932 i
.types
[op
].bitfield
.disp16
= 0;
2933 i
.types
[op
].bitfield
.disp32
= 0;
2934 i
.types
[op
].bitfield
.disp32s
= 0;
2935 i
.types
[op
].bitfield
.disp64
= 0;
2939 else if (flag_code
== CODE_64BIT
)
2941 if (fits_in_signed_long (disp
))
2943 i
.types
[op
].bitfield
.disp64
= 0;
2944 i
.types
[op
].bitfield
.disp32s
= 1;
2946 if (fits_in_unsigned_long (disp
))
2947 i
.types
[op
].bitfield
.disp32
= 1;
2949 if ((i
.types
[op
].bitfield
.disp32
2950 || i
.types
[op
].bitfield
.disp32s
2951 || i
.types
[op
].bitfield
.disp16
)
2952 && fits_in_signed_byte (disp
))
2953 i
.types
[op
].bitfield
.disp8
= 1;
2955 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2956 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2958 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2959 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2960 i
.types
[op
].bitfield
.disp8
= 0;
2961 i
.types
[op
].bitfield
.disp16
= 0;
2962 i
.types
[op
].bitfield
.disp32
= 0;
2963 i
.types
[op
].bitfield
.disp32s
= 0;
2964 i
.types
[op
].bitfield
.disp64
= 0;
2967 /* We only support 64bit displacement on constants. */
2968 i
.types
[op
].bitfield
.disp64
= 0;
2973 match_template (void)
2975 /* Points to template once we've found it. */
2977 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
2978 unsigned int found_reverse_match
;
2979 i386_opcode_modifier suffix_check
;
2980 i386_operand_type operand_types
[MAX_OPERANDS
];
2981 int addr_prefix_disp
;
2983 i386_cpu_flags overlap
;
2985 #if MAX_OPERANDS != 4
2986 # error "MAX_OPERANDS must be 4."
2989 found_reverse_match
= 0;
2990 addr_prefix_disp
= -1;
2992 memset (&suffix_check
, 0, sizeof (suffix_check
));
2993 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2994 suffix_check
.no_bsuf
= 1;
2995 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2996 suffix_check
.no_wsuf
= 1;
2997 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
2998 suffix_check
.no_ssuf
= 1;
2999 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3000 suffix_check
.no_lsuf
= 1;
3001 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3002 suffix_check
.no_qsuf
= 1;
3003 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3004 suffix_check
.no_xsuf
= 1;
3006 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3008 addr_prefix_disp
= -1;
3010 /* Must have right number of operands. */
3011 if (i
.operands
!= t
->operands
)
3014 /* Check the suffix, except for some instructions in intel mode. */
3015 if (((t
->opcode_modifier
.no_bsuf
& suffix_check
.no_bsuf
)
3016 || (t
->opcode_modifier
.no_wsuf
& suffix_check
.no_wsuf
)
3017 || (t
->opcode_modifier
.no_lsuf
& suffix_check
.no_lsuf
)
3018 || (t
->opcode_modifier
.no_ssuf
& suffix_check
.no_ssuf
)
3019 || (t
->opcode_modifier
.no_qsuf
& suffix_check
.no_qsuf
)
3020 || (t
->opcode_modifier
.no_xsuf
& suffix_check
.no_xsuf
))
3021 && !(intel_syntax
&& t
->opcode_modifier
.ignoresize
))
3024 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3025 operand_types
[j
] = t
->operand_types
[j
];
3027 /* In general, don't allow 64-bit operands in 32-bit mode. */
3028 if (i
.suffix
== QWORD_MNEM_SUFFIX
3029 && flag_code
!= CODE_64BIT
3031 ? (!t
->opcode_modifier
.ignoresize
3032 && !intel_float_operand (t
->name
))
3033 : intel_float_operand (t
->name
) != 2)
3034 && ((!operand_types
[0].bitfield
.regmmx
3035 && !operand_types
[0].bitfield
.regxmm
)
3036 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3037 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3038 && (t
->base_opcode
!= 0x0fc7
3039 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3042 /* Do not verify operands when there are none. */
3045 overlap
= cpu_flags_and (t
->cpu_flags
, cpu_arch_flags_not
);
3048 if (!UINTS_ALL_ZERO (overlap
))
3050 /* We've found a match; break out of loop. */
3055 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3056 into Disp32/Disp16/Disp32 operand. */
3057 if (i
.prefix
[ADDR_PREFIX
] != 0)
3059 /* There should be only one Disp operand. */
3063 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3065 if (operand_types
[j
].bitfield
.disp16
)
3067 addr_prefix_disp
= j
;
3068 operand_types
[j
].bitfield
.disp32
= 1;
3069 operand_types
[j
].bitfield
.disp16
= 0;
3075 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3077 if (operand_types
[j
].bitfield
.disp32
)
3079 addr_prefix_disp
= j
;
3080 operand_types
[j
].bitfield
.disp32
= 0;
3081 operand_types
[j
].bitfield
.disp16
= 1;
3087 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3089 if (operand_types
[j
].bitfield
.disp64
)
3091 addr_prefix_disp
= j
;
3092 operand_types
[j
].bitfield
.disp64
= 0;
3093 operand_types
[j
].bitfield
.disp32
= 1;
3101 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3102 switch (t
->operands
)
3105 if (!operand_type_match (overlap0
, i
.types
[0]))
3109 /* xchg %eax, %eax is a special case. It is an aliase for nop
3110 only in 32bit mode and we can use opcode 0x90. In 64bit
3111 mode, we can't use 0x90 for xchg %eax, %eax since it should
3112 zero-extend %eax to %rax. */
3113 if (flag_code
== CODE_64BIT
3114 && t
->base_opcode
== 0x90
3115 && UINTS_EQUAL (i
.types
[0], acc32
)
3116 && UINTS_EQUAL (i
.types
[1], acc32
))
3120 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3121 if (!operand_type_match (overlap0
, i
.types
[0])
3122 || !operand_type_match (overlap1
, i
.types
[1])
3123 /* monitor in SSE3 is a very special case. The first
3124 register and the second register may have different
3125 sizes. The same applies to crc32 in SSE4.2. It is
3126 also true for invlpga, vmload, vmrun and vmsave in
3128 || !((t
->base_opcode
== 0x0f01
3129 && (t
->extension_opcode
== 0xc8
3130 || t
->extension_opcode
== 0xd8
3131 || t
->extension_opcode
== 0xda
3132 || t
->extension_opcode
== 0xdb
3133 || t
->extension_opcode
== 0xdf))
3134 || t
->base_opcode
== 0xf20f38f1
3135 || operand_type_register_match (overlap0
, i
.types
[0],
3137 overlap1
, i
.types
[1],
3140 /* Check if other direction is valid ... */
3141 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3144 /* Try reversing direction of operands. */
3145 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3146 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3147 if (!operand_type_match (overlap0
, i
.types
[0])
3148 || !operand_type_match (overlap1
, i
.types
[1])
3149 || !operand_type_register_match (overlap0
, i
.types
[0],
3151 overlap1
, i
.types
[1],
3154 /* Does not match either direction. */
3157 /* found_reverse_match holds which of D or FloatDR
3159 if (t
->opcode_modifier
.d
)
3160 found_reverse_match
= Opcode_D
;
3161 else if (t
->opcode_modifier
.floatd
)
3162 found_reverse_match
= Opcode_FloatD
;
3164 found_reverse_match
= 0;
3165 if (t
->opcode_modifier
.floatr
)
3166 found_reverse_match
|= Opcode_FloatR
;
3170 /* Found a forward 2 operand match here. */
3171 switch (t
->operands
)
3174 overlap3
= operand_type_and (i
.types
[3],
3177 overlap2
= operand_type_and (i
.types
[2],
3182 switch (t
->operands
)
3185 if (!operand_type_match (overlap3
, i
.types
[3])
3186 || !operand_type_register_match (overlap2
,
3194 /* Here we make use of the fact that there are no
3195 reverse match 3 operand instructions, and all 3
3196 operand instructions only need to be checked for
3197 register consistency between operands 2 and 3. */
3198 if (!operand_type_match (overlap2
, i
.types
[2])
3199 || !operand_type_register_match (overlap1
,
3209 /* Found either forward/reverse 2, 3 or 4 operand match here:
3210 slip through to break. */
3212 if (!UINTS_ALL_ZERO (overlap
))
3214 found_reverse_match
= 0;
3217 /* We've found a match; break out of loop. */
3221 if (t
== current_templates
->end
)
3223 /* We found no match. */
3224 as_bad (_("suffix or operands invalid for `%s'"),
3225 current_templates
->start
->name
);
3229 if (!quiet_warnings
)
3232 && (i
.types
[0].bitfield
.jumpabsolute
3233 != operand_types
[0].bitfield
.jumpabsolute
))
3235 as_warn (_("indirect %s without `*'"), t
->name
);
3238 if (t
->opcode_modifier
.isprefix
3239 && t
->opcode_modifier
.ignoresize
)
3241 /* Warn them that a data or address size prefix doesn't
3242 affect assembly of the next line of code. */
3243 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3247 /* Copy the template we found. */
3250 if (addr_prefix_disp
!= -1)
3251 i
.tm
.operand_types
[addr_prefix_disp
]
3252 = operand_types
[addr_prefix_disp
];
3254 if (found_reverse_match
)
3256 /* If we found a reverse match we must alter the opcode
3257 direction bit. found_reverse_match holds bits to change
3258 (different for int & float insns). */
3260 i
.tm
.base_opcode
^= found_reverse_match
;
3262 i
.tm
.operand_types
[0] = operand_types
[1];
3263 i
.tm
.operand_types
[1] = operand_types
[0];
3272 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3273 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3275 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3277 as_bad (_("`%s' operand %d must use `%%es' segment"),
3282 /* There's only ever one segment override allowed per instruction.
3283 This instruction possibly has a legal segment override on the
3284 second operand, so copy the segment to where non-string
3285 instructions store it, allowing common code. */
3286 i
.seg
[0] = i
.seg
[1];
3288 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3290 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3292 as_bad (_("`%s' operand %d must use `%%es' segment"),
3302 process_suffix (void)
3304 /* If matched instruction specifies an explicit instruction mnemonic
3306 if (i
.tm
.opcode_modifier
.size16
)
3307 i
.suffix
= WORD_MNEM_SUFFIX
;
3308 else if (i
.tm
.opcode_modifier
.size32
)
3309 i
.suffix
= LONG_MNEM_SUFFIX
;
3310 else if (i
.tm
.opcode_modifier
.size64
)
3311 i
.suffix
= QWORD_MNEM_SUFFIX
;
3312 else if (i
.reg_operands
)
3314 /* If there's no instruction mnemonic suffix we try to invent one
3315 based on register operands. */
3318 /* We take i.suffix from the last register operand specified,
3319 Destination register type is more significant than source
3320 register type. crc32 in SSE4.2 prefers source register
3322 if (i
.tm
.base_opcode
== 0xf20f38f1)
3324 if (i
.types
[0].bitfield
.reg16
)
3325 i
.suffix
= WORD_MNEM_SUFFIX
;
3326 else if (i
.types
[0].bitfield
.reg32
)
3327 i
.suffix
= LONG_MNEM_SUFFIX
;
3328 else if (i
.types
[0].bitfield
.reg64
)
3329 i
.suffix
= QWORD_MNEM_SUFFIX
;
3331 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3333 if (i
.types
[0].bitfield
.reg8
)
3334 i
.suffix
= BYTE_MNEM_SUFFIX
;
3341 if (i
.tm
.base_opcode
== 0xf20f38f1
3342 || i
.tm
.base_opcode
== 0xf20f38f0)
3344 /* We have to know the operand size for crc32. */
3345 as_bad (_("ambiguous memory operand size for `%s`"),
3350 for (op
= i
.operands
; --op
>= 0;)
3351 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3353 if (i
.types
[op
].bitfield
.reg8
)
3355 i
.suffix
= BYTE_MNEM_SUFFIX
;
3358 else if (i
.types
[op
].bitfield
.reg16
)
3360 i
.suffix
= WORD_MNEM_SUFFIX
;
3363 else if (i
.types
[op
].bitfield
.reg32
)
3365 i
.suffix
= LONG_MNEM_SUFFIX
;
3368 else if (i
.types
[op
].bitfield
.reg64
)
3370 i
.suffix
= QWORD_MNEM_SUFFIX
;
3376 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3378 if (!check_byte_reg ())
3381 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3383 if (!check_long_reg ())
3386 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3388 if (!check_qword_reg ())
3391 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3393 if (!check_word_reg ())
3396 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3397 /* Do nothing if the instruction is going to ignore the prefix. */
3402 else if (i
.tm
.opcode_modifier
.defaultsize
3404 /* exclude fldenv/frstor/fsave/fstenv */
3405 && i
.tm
.opcode_modifier
.no_ssuf
)
3407 i
.suffix
= stackop_size
;
3409 else if (intel_syntax
3411 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3412 || i
.tm
.opcode_modifier
.jumpbyte
3413 || i
.tm
.opcode_modifier
.jumpintersegment
3414 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3415 && i
.tm
.extension_opcode
<= 3)))
3420 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3422 i
.suffix
= QWORD_MNEM_SUFFIX
;
3426 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3427 i
.suffix
= LONG_MNEM_SUFFIX
;
3430 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3431 i
.suffix
= WORD_MNEM_SUFFIX
;
3440 if (i
.tm
.opcode_modifier
.w
)
3442 as_bad (_("no instruction mnemonic suffix given and "
3443 "no register operands; can't size instruction"));
3449 unsigned int suffixes
;
3451 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3452 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3454 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3456 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3458 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3460 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3463 /* There are more than suffix matches. */
3464 if (i
.tm
.opcode_modifier
.w
3465 || ((suffixes
& (suffixes
- 1))
3466 && !i
.tm
.opcode_modifier
.defaultsize
3467 && !i
.tm
.opcode_modifier
.ignoresize
))
3469 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3475 /* Change the opcode based on the operand size given by i.suffix;
3476 We don't need to change things for byte insns. */
3478 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
3480 /* It's not a byte, select word/dword operation. */
3481 if (i
.tm
.opcode_modifier
.w
)
3483 if (i
.tm
.opcode_modifier
.shortform
)
3484 i
.tm
.base_opcode
|= 8;
3486 i
.tm
.base_opcode
|= 1;
3489 /* Now select between word & dword operations via the operand
3490 size prefix, except for instructions that will ignore this
3492 if (i
.tm
.base_opcode
== 0x0f01
3493 && (i
.tm
.extension_opcode
== 0xc8
3494 || i
.tm
.extension_opcode
== 0xd8
3495 || i
.tm
.extension_opcode
== 0xda
3496 || i
.tm
.extension_opcode
== 0xdb
3497 || i
.tm
.extension_opcode
== 0xdf))
3499 /* monitor in SSE3 is a very special case. The default size
3500 of AX is the size of mode. The address size override
3501 prefix will change the size of AX. It is also true for
3502 invlpga, vmload, vmrun and vmsave in SVME. */
3503 if ((flag_code
== CODE_32BIT
3504 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3505 || (flag_code
!= CODE_32BIT
3506 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3507 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3510 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3511 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3512 && !i
.tm
.opcode_modifier
.ignoresize
3513 && !i
.tm
.opcode_modifier
.floatmf
3514 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3515 || (flag_code
== CODE_64BIT
3516 && i
.tm
.opcode_modifier
.jumpbyte
)))
3518 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3520 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3521 prefix
= ADDR_PREFIX_OPCODE
;
3523 if (!add_prefix (prefix
))
3527 /* Set mode64 for an operand. */
3528 if (i
.suffix
== QWORD_MNEM_SUFFIX
3529 && flag_code
== CODE_64BIT
3530 && !i
.tm
.opcode_modifier
.norex64
)
3532 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3533 need rex64. cmpxchg8b is also a special case. */
3534 if (! (i
.operands
== 2
3535 && i
.tm
.base_opcode
== 0x90
3536 && i
.tm
.extension_opcode
== None
3537 && UINTS_EQUAL (i
.types
[0], acc64
)
3538 && UINTS_EQUAL (i
.types
[1], acc64
))
3539 && ! (i
.operands
== 1
3540 && i
.tm
.base_opcode
== 0xfc7
3541 && i
.tm
.extension_opcode
== 1
3542 && !operand_type_check (i
.types
[0], reg
)
3543 && operand_type_check (i
.types
[0], anymem
)))
3547 /* Size floating point instruction. */
3548 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3549 if (i
.tm
.opcode_modifier
.floatmf
)
3550 i
.tm
.base_opcode
^= 4;
3557 check_byte_reg (void)
3561 for (op
= i
.operands
; --op
>= 0;)
3563 /* If this is an eight bit register, it's OK. If it's the 16 or
3564 32 bit version of an eight bit register, we will just use the
3565 low portion, and that's OK too. */
3566 if (i
.types
[op
].bitfield
.reg8
)
3569 /* movzx, movsx, pextrb and pinsrb should not generate this
3572 && (i
.tm
.base_opcode
== 0xfb7
3573 || i
.tm
.base_opcode
== 0xfb6
3574 || i
.tm
.base_opcode
== 0x63
3575 || i
.tm
.base_opcode
== 0xfbe
3576 || i
.tm
.base_opcode
== 0xfbf
3577 || i
.tm
.base_opcode
== 0x660f3a14
3578 || i
.tm
.base_opcode
== 0x660f3a20))
3581 /* crc32 doesn't generate this warning. */
3582 if (i
.tm
.base_opcode
== 0xf20f38f0)
3585 if ((i
.types
[op
].bitfield
.reg16
3586 || i
.types
[op
].bitfield
.reg32
3587 || i
.types
[op
].bitfield
.reg64
)
3588 && i
.op
[op
].regs
->reg_num
< 4)
3590 /* Prohibit these changes in the 64bit mode, since the
3591 lowering is more complicated. */
3592 if (flag_code
== CODE_64BIT
3593 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3595 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3596 register_prefix
, i
.op
[op
].regs
->reg_name
,
3600 #if REGISTER_WARNINGS
3602 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3605 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3606 ? REGNAM_AL
- REGNAM_AX
3607 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3609 i
.op
[op
].regs
->reg_name
,
3614 /* Any other register is bad. */
3615 if (i
.types
[op
].bitfield
.reg16
3616 || i
.types
[op
].bitfield
.reg32
3617 || i
.types
[op
].bitfield
.reg64
3618 || i
.types
[op
].bitfield
.regmmx
3619 || i
.types
[op
].bitfield
.regxmm
3620 || i
.types
[op
].bitfield
.sreg2
3621 || i
.types
[op
].bitfield
.sreg3
3622 || i
.types
[op
].bitfield
.control
3623 || i
.types
[op
].bitfield
.debug
3624 || i
.types
[op
].bitfield
.test
3625 || i
.types
[op
].bitfield
.floatreg
3626 || i
.types
[op
].bitfield
.floatacc
)
3628 as_bad (_("`%s%s' not allowed with `%s%c'"),
3630 i
.op
[op
].regs
->reg_name
,
3640 check_long_reg (void)
3644 for (op
= i
.operands
; --op
>= 0;)
3645 /* Reject eight bit registers, except where the template requires
3646 them. (eg. movzb) */
3647 if (i
.types
[op
].bitfield
.reg8
3648 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3649 || i
.tm
.operand_types
[op
].bitfield
.reg32
3650 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3652 as_bad (_("`%s%s' not allowed with `%s%c'"),
3654 i
.op
[op
].regs
->reg_name
,
3659 /* Warn if the e prefix on a general reg is missing. */
3660 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3661 && i
.types
[op
].bitfield
.reg16
3662 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3663 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3665 /* Prohibit these changes in the 64bit mode, since the
3666 lowering is more complicated. */
3667 if (flag_code
== CODE_64BIT
)
3669 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3670 register_prefix
, i
.op
[op
].regs
->reg_name
,
3674 #if REGISTER_WARNINGS
3676 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3678 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3680 i
.op
[op
].regs
->reg_name
,
3684 /* Warn if the r prefix on a general reg is missing. */
3685 else if (i
.types
[op
].bitfield
.reg64
3686 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3687 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3690 && i
.tm
.base_opcode
== 0xf30f2d
3691 && !i
.types
[0].bitfield
.regxmm
)
3693 /* cvtss2si converts DWORD memory to Reg64. We want
3695 i
.suffix
= QWORD_MNEM_SUFFIX
;
3699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3700 register_prefix
, i
.op
[op
].regs
->reg_name
,
3709 check_qword_reg (void)
3713 for (op
= i
.operands
; --op
>= 0; )
3714 /* Reject eight bit registers, except where the template requires
3715 them. (eg. movzb) */
3716 if (i
.types
[op
].bitfield
.reg8
3717 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3718 || i
.tm
.operand_types
[op
].bitfield
.reg32
3719 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3721 as_bad (_("`%s%s' not allowed with `%s%c'"),
3723 i
.op
[op
].regs
->reg_name
,
3728 /* Warn if the e prefix on a general reg is missing. */
3729 else if ((i
.types
[op
].bitfield
.reg16
3730 || i
.types
[op
].bitfield
.reg32
)
3731 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3732 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3734 /* Prohibit these changes in the 64bit mode, since the
3735 lowering is more complicated. */
3737 && i
.tm
.base_opcode
== 0xf20f2d
3738 && !i
.types
[0].bitfield
.regxmm
)
3740 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3742 i
.suffix
= LONG_MNEM_SUFFIX
;
3746 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3747 register_prefix
, i
.op
[op
].regs
->reg_name
,
3756 check_word_reg (void)
3759 for (op
= i
.operands
; --op
>= 0;)
3760 /* Reject eight bit registers, except where the template requires
3761 them. (eg. movzb) */
3762 if (i
.types
[op
].bitfield
.reg8
3763 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3764 || i
.tm
.operand_types
[op
].bitfield
.reg32
3765 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3767 as_bad (_("`%s%s' not allowed with `%s%c'"),
3769 i
.op
[op
].regs
->reg_name
,
3774 /* Warn if the e prefix on a general reg is present. */
3775 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3776 && i
.types
[op
].bitfield
.reg32
3777 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3778 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3780 /* Prohibit these changes in the 64bit mode, since the
3781 lowering is more complicated. */
3782 if (flag_code
== CODE_64BIT
)
3784 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3785 register_prefix
, i
.op
[op
].regs
->reg_name
,
3790 #if REGISTER_WARNINGS
3791 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3793 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3795 i
.op
[op
].regs
->reg_name
,
3803 update_imm (unsigned int j
)
3805 i386_operand_type overlap
;
3807 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3808 if ((overlap
.bitfield
.imm8
3809 || overlap
.bitfield
.imm8s
3810 || overlap
.bitfield
.imm16
3811 || overlap
.bitfield
.imm32
3812 || overlap
.bitfield
.imm32s
3813 || overlap
.bitfield
.imm64
)
3814 && !UINTS_EQUAL (overlap
, imm8
)
3815 && !UINTS_EQUAL (overlap
, imm8s
)
3816 && !UINTS_EQUAL (overlap
, imm16
)
3817 && !UINTS_EQUAL (overlap
, imm32
)
3818 && !UINTS_EQUAL (overlap
, imm32s
)
3819 && !UINTS_EQUAL (overlap
, imm64
))
3823 i386_operand_type temp
;
3826 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3828 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3829 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3831 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3832 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3833 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3835 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3836 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3839 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3842 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3843 || UINTS_EQUAL (overlap
, imm16_32
)
3844 || UINTS_EQUAL (overlap
, imm16_32s
))
3846 UINTS_CLEAR (overlap
);
3847 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3848 overlap
.bitfield
.imm16
= 1;
3850 overlap
.bitfield
.imm32s
= 1;
3852 if (!UINTS_EQUAL (overlap
, imm8
)
3853 && !UINTS_EQUAL (overlap
, imm8s
)
3854 && !UINTS_EQUAL (overlap
, imm16
)
3855 && !UINTS_EQUAL (overlap
, imm32
)
3856 && !UINTS_EQUAL (overlap
, imm32s
)
3857 && !UINTS_EQUAL (overlap
, imm64
))
3859 as_bad (_("no instruction mnemonic suffix given; "
3860 "can't determine immediate size"));
3864 i
.types
[j
] = overlap
;
3874 for (j
= 0; j
< 2; j
++)
3875 if (update_imm (j
) == 0)
3878 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3879 assert (operand_type_check (i
.types
[2], imm
) == 0);
3887 i
.drex
.modrm_reg
= None
;
3888 i
.drex
.modrm_regmem
= None
;
3890 /* SSE5 4 operand instructions must have the destination the same as
3891 one of the inputs. Figure out the destination register and cache
3892 it away in the drex field, and remember which fields to use for
3894 if (i
.tm
.opcode_modifier
.drex
3895 && i
.tm
.opcode_modifier
.drexv
3898 i
.tm
.extension_opcode
= None
;
3900 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3901 if (i
.types
[0].bitfield
.regxmm
!= 0
3902 && i
.types
[1].bitfield
.regxmm
!= 0
3903 && i
.types
[2].bitfield
.regxmm
!= 0
3904 && i
.types
[3].bitfield
.regxmm
!= 0
3905 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3906 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3908 /* Clear the arguments that are stored in drex. */
3909 UINTS_CLEAR (i
.types
[0]);
3910 UINTS_CLEAR (i
.types
[3]);
3911 i
.reg_operands
-= 2;
3913 /* There are two different ways to encode a 4 operand
3914 instruction with all registers that uses OC1 set to
3915 0 or 1. Favor setting OC1 to 0 since this mimics the
3916 actions of other SSE5 assemblers. Use modrm encoding 2
3917 for register/register. Include the high order bit that
3918 is normally stored in the REX byte in the register
3920 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3921 i
.drex
.modrm_reg
= 2;
3922 i
.drex
.modrm_regmem
= 1;
3923 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3924 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3927 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3928 else if (i
.types
[0].bitfield
.regxmm
!= 0
3929 && i
.types
[1].bitfield
.regxmm
!= 0
3930 && (i
.types
[2].bitfield
.regxmm
3931 || operand_type_check (i
.types
[2], anymem
))
3932 && i
.types
[3].bitfield
.regxmm
!= 0
3933 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3934 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3936 /* clear the arguments that are stored in drex */
3937 UINTS_CLEAR (i
.types
[0]);
3938 UINTS_CLEAR (i
.types
[3]);
3939 i
.reg_operands
-= 2;
3941 /* Specify the modrm encoding for memory addressing. Include
3942 the high order bit that is normally stored in the REX byte
3943 in the register field. */
3944 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
3945 i
.drex
.modrm_reg
= 1;
3946 i
.drex
.modrm_regmem
= 2;
3947 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3948 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3951 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3952 else if (i
.types
[0].bitfield
.regxmm
!= 0
3953 && operand_type_check (i
.types
[1], anymem
) != 0
3954 && i
.types
[2].bitfield
.regxmm
!= 0
3955 && i
.types
[3].bitfield
.regxmm
!= 0
3956 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
3957 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3959 /* Clear the arguments that are stored in drex. */
3960 UINTS_CLEAR (i
.types
[0]);
3961 UINTS_CLEAR (i
.types
[3]);
3962 i
.reg_operands
-= 2;
3964 /* Specify the modrm encoding for memory addressing. Include
3965 the high order bit that is normally stored in the REX byte
3966 in the register field. */
3967 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
3968 i
.drex
.modrm_reg
= 2;
3969 i
.drex
.modrm_regmem
= 1;
3970 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
3971 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
3974 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3975 else if (i
.types
[0].bitfield
.regxmm
!= 0
3976 && i
.types
[1].bitfield
.regxmm
!= 0
3977 && i
.types
[2].bitfield
.regxmm
!= 0
3978 && i
.types
[3].bitfield
.regxmm
!= 0
3979 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
3980 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
3982 /* clear the arguments that are stored in drex */
3983 UINTS_CLEAR (i
.types
[2]);
3984 UINTS_CLEAR (i
.types
[3]);
3985 i
.reg_operands
-= 2;
3987 /* There are two different ways to encode a 4 operand
3988 instruction with all registers that uses OC1 set to
3989 0 or 1. Favor setting OC1 to 0 since this mimics the
3990 actions of other SSE5 assemblers. Use modrm encoding
3991 2 for register/register. Include the high order bit that
3992 is normally stored in the REX byte in the register
3994 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
3995 i
.drex
.modrm_reg
= 1;
3996 i
.drex
.modrm_regmem
= 0;
3998 /* Remember the register, including the upper bits */
3999 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4000 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4003 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4004 else if (i
.types
[0].bitfield
.regxmm
!= 0
4005 && (i
.types
[1].bitfield
.regxmm
4006 || operand_type_check (i
.types
[1], anymem
))
4007 && i
.types
[2].bitfield
.regxmm
!= 0
4008 && i
.types
[3].bitfield
.regxmm
!= 0
4009 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4010 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4012 /* Clear the arguments that are stored in drex. */
4013 UINTS_CLEAR (i
.types
[2]);
4014 UINTS_CLEAR (i
.types
[3]);
4015 i
.reg_operands
-= 2;
4017 /* Specify the modrm encoding and remember the register
4018 including the bits normally stored in the REX byte. */
4019 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4020 i
.drex
.modrm_reg
= 0;
4021 i
.drex
.modrm_regmem
= 1;
4022 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4023 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4026 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4027 else if (operand_type_check (i
.types
[0], anymem
) != 0
4028 && i
.types
[1].bitfield
.regxmm
!= 0
4029 && i
.types
[2].bitfield
.regxmm
!= 0
4030 && i
.types
[3].bitfield
.regxmm
!= 0
4031 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4032 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4034 /* clear the arguments that are stored in drex */
4035 UINTS_CLEAR (i
.types
[2]);
4036 UINTS_CLEAR (i
.types
[3]);
4037 i
.reg_operands
-= 2;
4039 /* Specify the modrm encoding and remember the register
4040 including the bits normally stored in the REX byte. */
4041 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4042 i
.drex
.modrm_reg
= 1;
4043 i
.drex
.modrm_regmem
= 0;
4044 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4045 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4049 as_bad (_("Incorrect operands for the '%s' instruction"),
4053 /* SSE5 instructions with the DREX byte where the only memory operand
4054 is in the 2nd argument, and the first and last xmm register must
4055 match, and is encoded in the DREX byte. */
4056 else if (i
.tm
.opcode_modifier
.drex
4057 && !i
.tm
.opcode_modifier
.drexv
4060 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4061 if (i
.types
[0].bitfield
.regxmm
!= 0
4062 && (i
.types
[1].bitfield
.regxmm
4063 || operand_type_check(i
.types
[1], anymem
))
4064 && i
.types
[2].bitfield
.regxmm
!= 0
4065 && i
.types
[3].bitfield
.regxmm
!= 0
4066 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4067 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4069 /* clear the arguments that are stored in drex */
4070 UINTS_CLEAR (i
.types
[0]);
4071 UINTS_CLEAR (i
.types
[3]);
4072 i
.reg_operands
-= 2;
4074 /* Specify the modrm encoding and remember the register
4075 including the high bit normally stored in the REX
4077 i
.drex
.modrm_reg
= 2;
4078 i
.drex
.modrm_regmem
= 1;
4079 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4080 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4084 as_bad (_("Incorrect operands for the '%s' instruction"),
4088 /* SSE5 3 operand instructions that the result is a register, being
4089 either operand can be a memory operand, using OC0 to note which
4090 one is the memory. */
4091 else if (i
.tm
.opcode_modifier
.drex
4092 && i
.tm
.opcode_modifier
.drexv
4095 i
.tm
.extension_opcode
= None
;
4097 /* Case 1: 3 operand insn, src1 = register. */
4098 if (i
.types
[0].bitfield
.regxmm
!= 0
4099 && i
.types
[1].bitfield
.regxmm
!= 0
4100 && i
.types
[2].bitfield
.regxmm
!= 0)
4102 /* Clear the arguments that are stored in drex. */
4103 UINTS_CLEAR (i
.types
[2]);
4106 /* Specify the modrm encoding and remember the register
4107 including the high bit normally stored in the REX byte. */
4108 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4109 i
.drex
.modrm_reg
= 1;
4110 i
.drex
.modrm_regmem
= 0;
4111 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4112 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4115 /* Case 2: 3 operand insn, src1 = memory. */
4116 else if (operand_type_check (i
.types
[0], anymem
) != 0
4117 && i
.types
[1].bitfield
.regxmm
!= 0
4118 && i
.types
[2].bitfield
.regxmm
!= 0)
4120 /* Clear the arguments that are stored in drex. */
4121 UINTS_CLEAR (i
.types
[2]);
4124 /* Specify the modrm encoding and remember the register
4125 including the high bit normally stored in the REX
4127 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4128 i
.drex
.modrm_reg
= 1;
4129 i
.drex
.modrm_regmem
= 0;
4130 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4131 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4134 /* Case 3: 3 operand insn, src2 = memory. */
4135 else if (i
.types
[0].bitfield
.regxmm
!= 0
4136 && operand_type_check (i
.types
[1], anymem
) != 0
4137 && i
.types
[2].bitfield
.regxmm
!= 0)
4139 /* Clear the arguments that are stored in drex. */
4140 UINTS_CLEAR (i
.types
[2]);
4143 /* Specify the modrm encoding and remember the register
4144 including the high bit normally stored in the REX byte. */
4145 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4146 i
.drex
.modrm_reg
= 0;
4147 i
.drex
.modrm_regmem
= 1;
4148 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4149 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4153 as_bad (_("Incorrect operands for the '%s' instruction"),
4157 /* SSE5 4 operand instructions that are the comparison instructions
4158 where the first operand is the immediate value of the comparison
4160 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4162 /* Case 1: 4 operand insn, src1 = reg/memory. */
4163 if (operand_type_check (i
.types
[0], imm
) != 0
4164 && (i
.types
[1].bitfield
.regxmm
4165 || operand_type_check (i
.types
[1], anymem
))
4166 && i
.types
[2].bitfield
.regxmm
!= 0
4167 && i
.types
[3].bitfield
.regxmm
!= 0)
4169 /* clear the arguments that are stored in drex */
4170 UINTS_CLEAR (i
.types
[3]);
4173 /* Specify the modrm encoding and remember the register
4174 including the high bit normally stored in the REX byte. */
4175 i
.drex
.modrm_reg
= 2;
4176 i
.drex
.modrm_regmem
= 1;
4177 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4178 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4181 /* Case 2: 3 operand insn with ImmExt that places the
4182 opcode_extension as an immediate argument. This is used for
4183 all of the varients of comparison that supplies the appropriate
4184 value as part of the instruction. */
4185 else if ((i
.types
[0].bitfield
.regxmm
4186 || operand_type_check (i
.types
[0], anymem
))
4187 && i
.types
[1].bitfield
.regxmm
!= 0
4188 && i
.types
[2].bitfield
.regxmm
!= 0
4189 && operand_type_check (i
.types
[3], imm
) != 0)
4191 /* clear the arguments that are stored in drex */
4192 UINTS_CLEAR (i
.types
[2]);
4195 /* Specify the modrm encoding and remember the register
4196 including the high bit normally stored in the REX byte. */
4197 i
.drex
.modrm_reg
= 1;
4198 i
.drex
.modrm_regmem
= 0;
4199 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4200 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4204 as_bad (_("Incorrect operands for the '%s' instruction"),
4208 else if (i
.tm
.opcode_modifier
.drex
4209 || i
.tm
.opcode_modifier
.drexv
4210 || i
.tm
.opcode_modifier
.drexc
)
4211 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4215 process_operands (void)
4217 /* Default segment register this instruction will use for memory
4218 accesses. 0 means unknown. This is only for optimizing out
4219 unnecessary segment overrides. */
4220 const seg_entry
*default_seg
= 0;
4222 /* Handle all of the DREX munging that SSE5 needs. */
4223 if (i
.tm
.opcode_modifier
.drex
4224 || i
.tm
.opcode_modifier
.drexv
4225 || i
.tm
.opcode_modifier
.drexc
)
4228 /* The imul $imm, %reg instruction is converted into
4229 imul $imm, %reg, %reg, and the clr %reg instruction
4230 is converted into xor %reg, %reg. */
4231 if (i
.tm
.opcode_modifier
.regkludge
)
4233 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
4235 /* The first operand in instruction blendvpd, blendvps and
4236 pblendvb in SSE4.1 is implicit and must be xmm0. */
4237 assert (i
.operands
== 3
4238 && i
.reg_operands
>= 2
4239 && UINTS_EQUAL (i
.types
[0], regxmm
));
4240 if (i
.op
[0].regs
->reg_num
!= 0)
4243 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4244 i
.tm
.name
, register_prefix
);
4246 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4247 i
.tm
.name
, register_prefix
);
4252 i
.types
[0] = i
.types
[1];
4253 i
.types
[1] = i
.types
[2];
4257 /* We need to adjust fields in i.tm since they are used by
4258 build_modrm_byte. */
4259 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
4260 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
4265 unsigned int first_reg_op
;
4267 if (operand_type_check (i
.types
[0], reg
))
4271 /* Pretend we saw the extra register operand. */
4272 assert (i
.reg_operands
== 1
4273 && i
.op
[first_reg_op
+ 1].regs
== 0);
4274 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4275 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4281 if (i
.tm
.opcode_modifier
.shortform
)
4283 if (i
.types
[0].bitfield
.sreg2
4284 || i
.types
[0].bitfield
.sreg3
)
4286 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4287 && i
.op
[0].regs
->reg_num
== 1)
4289 as_bad (_("you can't `pop %%cs'"));
4292 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4293 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4298 /* The register or float register operand is in operand
4302 if (i
.types
[0].bitfield
.floatreg
4303 || operand_type_check (i
.types
[0], reg
))
4307 /* Register goes in low 3 bits of opcode. */
4308 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4309 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4311 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4313 /* Warn about some common errors, but press on regardless.
4314 The first case can be generated by gcc (<= 2.8.1). */
4315 if (i
.operands
== 2)
4317 /* Reversed arguments on faddp, fsubp, etc. */
4318 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4319 register_prefix
, i
.op
[1].regs
->reg_name
,
4320 register_prefix
, i
.op
[0].regs
->reg_name
);
4324 /* Extraneous `l' suffix on fp insn. */
4325 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4326 register_prefix
, i
.op
[0].regs
->reg_name
);
4331 else if (i
.tm
.opcode_modifier
.modrm
)
4333 /* The opcode is completed (modulo i.tm.extension_opcode which
4334 must be put into the modrm byte). Now, we make the modrm and
4335 index base bytes based on all the info we've collected. */
4337 default_seg
= build_modrm_byte ();
4339 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4343 else if (i
.tm
.opcode_modifier
.isstring
)
4345 /* For the string instructions that allow a segment override
4346 on one of their operands, the default segment is ds. */
4350 if (i
.tm
.base_opcode
== 0x8d /* lea */
4353 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4355 /* If a segment was explicitly specified, and the specified segment
4356 is not the default, use an opcode prefix to select it. If we
4357 never figured out what the default segment is, then default_seg
4358 will be zero at this point, and the specified segment prefix will
4360 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4362 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4368 static const seg_entry
*
4369 build_modrm_byte (void)
4371 const seg_entry
*default_seg
= 0;
4373 /* SSE5 4 operand instructions are encoded in such a way that one of
4374 the inputs must match the destination register. Process_drex hides
4375 the 3rd argument in the drex field, so that by the time we get
4376 here, it looks to GAS as if this is a 2 operand instruction. */
4377 if ((i
.tm
.opcode_modifier
.drex
4378 || i
.tm
.opcode_modifier
.drexv
4379 || i
.tm
.opcode_modifier
.drexc
)
4380 && i
.reg_operands
== 2)
4382 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
4383 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
4385 i
.rm
.reg
= reg
->reg_num
;
4386 i
.rm
.regmem
= regmem
->reg_num
;
4388 if ((reg
->reg_flags
& RegRex
) != 0)
4390 if ((regmem
->reg_flags
& RegRex
) != 0)
4394 /* i.reg_operands MUST be the number of real register operands;
4395 implicit registers do not count. */
4396 else if (i
.reg_operands
== 2)
4398 unsigned int source
, dest
;
4406 /* When there are 3 operands, one of them may be immediate,
4407 which may be the first or the last operand. Otherwise,
4408 the first operand must be shift count register (cl). */
4409 assert (i
.imm_operands
== 1
4410 || (i
.imm_operands
== 0
4411 && i
.types
[0].bitfield
.shiftcount
));
4412 if (operand_type_check (i
.types
[0], imm
)
4413 || i
.types
[0].bitfield
.shiftcount
)
4419 /* When there are 4 operands, the first two must be immediate
4420 operands. The source operand will be the 3rd one. */
4421 assert (i
.imm_operands
== 2
4422 && operand_type_check (i
.types
[0], imm
)
4423 && operand_type_check (i
.types
[1], imm
));
4433 /* One of the register operands will be encoded in the i.tm.reg
4434 field, the other in the combined i.tm.mode and i.tm.regmem
4435 fields. If no form of this instruction supports a memory
4436 destination operand, then we assume the source operand may
4437 sometimes be a memory operand and so we need to store the
4438 destination in the i.rm.reg field. */
4439 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4440 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4442 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4443 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4444 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4446 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4451 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4452 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4453 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4455 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4458 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4460 if (!i
.types
[0].bitfield
.control
4461 && !i
.types
[1].bitfield
.control
)
4463 i
.rex
&= ~(REX_R
| REX_B
);
4464 add_prefix (LOCK_PREFIX_OPCODE
);
4468 { /* If it's not 2 reg operands... */
4471 unsigned int fake_zero_displacement
= 0;
4474 /* This has been precalculated for SSE5 instructions
4475 that have a DREX field earlier in process_drex. */
4476 if (i
.tm
.opcode_modifier
.drex
4477 || i
.tm
.opcode_modifier
.drexv
4478 || i
.tm
.opcode_modifier
.drexc
)
4479 op
= i
.drex
.modrm_regmem
;
4482 for (op
= 0; op
< i
.operands
; op
++)
4483 if (operand_type_check (i
.types
[op
], anymem
))
4485 assert (op
< i
.operands
);
4490 if (i
.base_reg
== 0)
4493 if (!i
.disp_operands
)
4494 fake_zero_displacement
= 1;
4495 if (i
.index_reg
== 0)
4497 /* Operand is just <disp> */
4498 if (flag_code
== CODE_64BIT
)
4500 /* 64bit mode overwrites the 32bit absolute
4501 addressing by RIP relative addressing and
4502 absolute addressing is encoded by one of the
4503 redundant SIB forms. */
4504 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4505 i
.sib
.base
= NO_BASE_REGISTER
;
4506 i
.sib
.index
= NO_INDEX_REGISTER
;
4507 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4508 ? disp32s
: disp32
);
4510 else if ((flag_code
== CODE_16BIT
)
4511 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4513 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4514 i
.types
[op
] = disp16
;
4518 i
.rm
.regmem
= NO_BASE_REGISTER
;
4519 i
.types
[op
] = disp32
;
4522 else /* !i.base_reg && i.index_reg */
4524 if (i
.index_reg
->reg_num
== RegEiz
4525 || i
.index_reg
->reg_num
== RegRiz
)
4526 i
.sib
.index
= NO_INDEX_REGISTER
;
4528 i
.sib
.index
= i
.index_reg
->reg_num
;
4529 i
.sib
.base
= NO_BASE_REGISTER
;
4530 i
.sib
.scale
= i
.log2_scale_factor
;
4531 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4532 i
.types
[op
].bitfield
.disp8
= 0;
4533 i
.types
[op
].bitfield
.disp16
= 0;
4534 i
.types
[op
].bitfield
.disp64
= 0;
4535 if (flag_code
!= CODE_64BIT
)
4537 /* Must be 32 bit */
4538 i
.types
[op
].bitfield
.disp32
= 1;
4539 i
.types
[op
].bitfield
.disp32s
= 0;
4543 i
.types
[op
].bitfield
.disp32
= 0;
4544 i
.types
[op
].bitfield
.disp32s
= 1;
4546 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4550 /* RIP addressing for 64bit mode. */
4551 else if (i
.base_reg
->reg_num
== RegRip
)
4553 i
.rm
.regmem
= NO_BASE_REGISTER
;
4554 i
.types
[op
].bitfield
.disp8
= 0;
4555 i
.types
[op
].bitfield
.disp16
= 0;
4556 i
.types
[op
].bitfield
.disp32
= 0;
4557 i
.types
[op
].bitfield
.disp32s
= 1;
4558 i
.types
[op
].bitfield
.disp64
= 0;
4559 i
.flags
[op
] |= Operand_PCrel
;
4560 if (! i
.disp_operands
)
4561 fake_zero_displacement
= 1;
4563 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4565 switch (i
.base_reg
->reg_num
)
4568 if (i
.index_reg
== 0)
4570 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4571 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4575 if (i
.index_reg
== 0)
4578 if (operand_type_check (i
.types
[op
], disp
) == 0)
4580 /* fake (%bp) into 0(%bp) */
4581 i
.types
[op
].bitfield
.disp8
= 1;
4582 fake_zero_displacement
= 1;
4585 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4586 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4588 default: /* (%si) -> 4 or (%di) -> 5 */
4589 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4591 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4593 else /* i.base_reg and 32/64 bit mode */
4595 if (flag_code
== CODE_64BIT
4596 && operand_type_check (i
.types
[op
], disp
))
4598 i386_operand_type temp
;
4600 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4602 if (i
.prefix
[ADDR_PREFIX
] == 0)
4603 i
.types
[op
].bitfield
.disp32s
= 1;
4605 i
.types
[op
].bitfield
.disp32
= 1;
4608 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4609 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4611 i
.sib
.base
= i
.base_reg
->reg_num
;
4612 /* x86-64 ignores REX prefix bit here to avoid decoder
4614 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4617 if (i
.disp_operands
== 0)
4619 fake_zero_displacement
= 1;
4620 i
.types
[op
].bitfield
.disp8
= 1;
4623 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4627 i
.sib
.scale
= i
.log2_scale_factor
;
4628 if (i
.index_reg
== 0)
4630 /* <disp>(%esp) becomes two byte modrm with no index
4631 register. We've already stored the code for esp
4632 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4633 Any base register besides %esp will not use the
4634 extra modrm byte. */
4635 i
.sib
.index
= NO_INDEX_REGISTER
;
4639 if (i
.index_reg
->reg_num
== RegEiz
4640 || i
.index_reg
->reg_num
== RegRiz
)
4641 i
.sib
.index
= NO_INDEX_REGISTER
;
4643 i
.sib
.index
= i
.index_reg
->reg_num
;
4644 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4645 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4650 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4651 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4654 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4657 if (fake_zero_displacement
)
4659 /* Fakes a zero displacement assuming that i.types[op]
4660 holds the correct displacement size. */
4663 assert (i
.op
[op
].disps
== 0);
4664 exp
= &disp_expressions
[i
.disp_operands
++];
4665 i
.op
[op
].disps
= exp
;
4666 exp
->X_op
= O_constant
;
4667 exp
->X_add_number
= 0;
4668 exp
->X_add_symbol
= (symbolS
*) 0;
4669 exp
->X_op_symbol
= (symbolS
*) 0;
4673 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4674 (if any) based on i.tm.extension_opcode. Again, we must be
4675 careful to make sure that segment/control/debug/test/MMX
4676 registers are coded into the i.rm.reg field. */
4681 /* This has been precalculated for SSE5 instructions
4682 that have a DREX field earlier in process_drex. */
4683 if (i
.tm
.opcode_modifier
.drex
4684 || i
.tm
.opcode_modifier
.drexv
4685 || i
.tm
.opcode_modifier
.drexc
)
4687 op
= i
.drex
.modrm_reg
;
4688 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4689 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4694 for (op
= 0; op
< i
.operands
; op
++)
4695 if (i
.types
[op
].bitfield
.reg8
4696 || i
.types
[op
].bitfield
.reg16
4697 || i
.types
[op
].bitfield
.reg32
4698 || i
.types
[op
].bitfield
.reg64
4699 || i
.types
[op
].bitfield
.regmmx
4700 || i
.types
[op
].bitfield
.regxmm
4701 || i
.types
[op
].bitfield
.sreg2
4702 || i
.types
[op
].bitfield
.sreg3
4703 || i
.types
[op
].bitfield
.control
4704 || i
.types
[op
].bitfield
.debug
4705 || i
.types
[op
].bitfield
.test
)
4708 assert (op
< i
.operands
);
4710 /* If there is an extension opcode to put here, the
4711 register number must be put into the regmem field. */
4712 if (i
.tm
.extension_opcode
!= None
)
4714 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4715 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4720 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4721 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4726 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4727 must set it to 3 to indicate this is a register operand
4728 in the regmem field. */
4729 if (!i
.mem_operands
)
4733 /* Fill in i.rm.reg field with extension opcode (if any). */
4734 if (i
.tm
.extension_opcode
!= None
4735 && !(i
.tm
.opcode_modifier
.drex
4736 || i
.tm
.opcode_modifier
.drexv
4737 || i
.tm
.opcode_modifier
.drexc
))
4738 i
.rm
.reg
= i
.tm
.extension_opcode
;
4744 output_branch (void)
4749 relax_substateT subtype
;
4754 if (flag_code
== CODE_16BIT
)
4758 if (i
.prefix
[DATA_PREFIX
] != 0)
4764 /* Pentium4 branch hints. */
4765 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4766 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4771 if (i
.prefix
[REX_PREFIX
] != 0)
4777 if (i
.prefixes
!= 0 && !intel_syntax
)
4778 as_warn (_("skipping prefixes on this instruction"));
4780 /* It's always a symbol; End frag & setup for relax.
4781 Make sure there is enough room in this frag for the largest
4782 instruction we may generate in md_convert_frag. This is 2
4783 bytes for the opcode and room for the prefix and largest
4785 frag_grow (prefix
+ 2 + 4);
4786 /* Prefix and 1 opcode byte go in fr_fix. */
4787 p
= frag_more (prefix
+ 1);
4788 if (i
.prefix
[DATA_PREFIX
] != 0)
4789 *p
++ = DATA_PREFIX_OPCODE
;
4790 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4791 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4792 *p
++ = i
.prefix
[SEG_PREFIX
];
4793 if (i
.prefix
[REX_PREFIX
] != 0)
4794 *p
++ = i
.prefix
[REX_PREFIX
];
4795 *p
= i
.tm
.base_opcode
;
4797 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4798 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4799 else if (cpu_arch_flags
.bitfield
.cpui386
)
4800 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4802 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4805 sym
= i
.op
[0].disps
->X_add_symbol
;
4806 off
= i
.op
[0].disps
->X_add_number
;
4808 if (i
.op
[0].disps
->X_op
!= O_constant
4809 && i
.op
[0].disps
->X_op
!= O_symbol
)
4811 /* Handle complex expressions. */
4812 sym
= make_expr_symbol (i
.op
[0].disps
);
4816 /* 1 possible extra opcode + 4 byte displacement go in var part.
4817 Pass reloc in fr_var. */
4818 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4828 if (i
.tm
.opcode_modifier
.jumpbyte
)
4830 /* This is a loop or jecxz type instruction. */
4832 if (i
.prefix
[ADDR_PREFIX
] != 0)
4834 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4837 /* Pentium4 branch hints. */
4838 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4839 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4841 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4850 if (flag_code
== CODE_16BIT
)
4853 if (i
.prefix
[DATA_PREFIX
] != 0)
4855 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4865 if (i
.prefix
[REX_PREFIX
] != 0)
4867 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4871 if (i
.prefixes
!= 0 && !intel_syntax
)
4872 as_warn (_("skipping prefixes on this instruction"));
4874 p
= frag_more (1 + size
);
4875 *p
++ = i
.tm
.base_opcode
;
4877 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4878 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4880 /* All jumps handled here are signed, but don't use a signed limit
4881 check for 32 and 16 bit jumps as we want to allow wrap around at
4882 4G and 64k respectively. */
4884 fixP
->fx_signed
= 1;
4888 output_interseg_jump (void)
4896 if (flag_code
== CODE_16BIT
)
4900 if (i
.prefix
[DATA_PREFIX
] != 0)
4906 if (i
.prefix
[REX_PREFIX
] != 0)
4916 if (i
.prefixes
!= 0 && !intel_syntax
)
4917 as_warn (_("skipping prefixes on this instruction"));
4919 /* 1 opcode; 2 segment; offset */
4920 p
= frag_more (prefix
+ 1 + 2 + size
);
4922 if (i
.prefix
[DATA_PREFIX
] != 0)
4923 *p
++ = DATA_PREFIX_OPCODE
;
4925 if (i
.prefix
[REX_PREFIX
] != 0)
4926 *p
++ = i
.prefix
[REX_PREFIX
];
4928 *p
++ = i
.tm
.base_opcode
;
4929 if (i
.op
[1].imms
->X_op
== O_constant
)
4931 offsetT n
= i
.op
[1].imms
->X_add_number
;
4934 && !fits_in_unsigned_word (n
)
4935 && !fits_in_signed_word (n
))
4937 as_bad (_("16-bit jump out of range"));
4940 md_number_to_chars (p
, n
, size
);
4943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4944 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4945 if (i
.op
[0].imms
->X_op
!= O_constant
)
4946 as_bad (_("can't handle non absolute segment in `%s'"),
4948 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4954 fragS
*insn_start_frag
;
4955 offsetT insn_start_off
;
4957 /* Tie dwarf2 debug info to the address at the start of the insn.
4958 We can't do this after the insn has been output as the current
4959 frag may have been closed off. eg. by frag_var. */
4960 dwarf2_emit_insn (0);
4962 insn_start_frag
= frag_now
;
4963 insn_start_off
= frag_now_fix ();
4966 if (i
.tm
.opcode_modifier
.jump
)
4968 else if (i
.tm
.opcode_modifier
.jumpbyte
4969 || i
.tm
.opcode_modifier
.jumpdword
)
4971 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
4972 output_interseg_jump ();
4975 /* Output normal instructions here. */
4978 unsigned int prefix
;
4981 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4982 SSE4 and SSE5 instructions have 3 bytes. We may use one
4983 more higher byte to specify a prefix the instruction
4984 requires. Exclude instructions which are in both SSE4.2
4986 opc_3b
= (i
.tm
.cpu_flags
.bitfield
.cpussse3
4987 || i
.tm
.cpu_flags
.bitfield
.cpusse5
4988 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4989 || (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4990 && !i
.tm
.cpu_flags
.bitfield
.cpuabm
));
4993 if (i
.tm
.base_opcode
& 0xff000000)
4995 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
4999 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5001 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5002 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5005 if (prefix
!= REPE_PREFIX_OPCODE
5006 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
5007 add_prefix (prefix
);
5010 add_prefix (prefix
);
5013 /* The prefix bytes. */
5015 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
5021 md_number_to_chars (p
, (valueT
) *q
, 1);
5025 /* Now the opcode; be careful about word order here! */
5026 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
5028 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5035 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5040 /* Put out high byte first: can't use md_number_to_chars! */
5041 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5042 *p
= i
.tm
.base_opcode
& 0xff;
5044 /* On SSE5, encode the OC1 bit in the DREX field if this
5045 encoding has multiple formats. */
5046 if (i
.tm
.opcode_modifier
.drex
5047 && i
.tm
.opcode_modifier
.drexv
5048 && DREX_OC1 (i
.tm
.extension_opcode
))
5049 *p
|= DREX_OC1_MASK
;
5052 /* Now the modrm byte and sib byte (if present). */
5053 if (i
.tm
.opcode_modifier
.modrm
)
5056 md_number_to_chars (p
,
5057 (valueT
) (i
.rm
.regmem
<< 0
5061 /* If i.rm.regmem == ESP (4)
5062 && i.rm.mode != (Register mode)
5064 ==> need second modrm byte. */
5065 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5067 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5070 md_number_to_chars (p
,
5071 (valueT
) (i
.sib
.base
<< 0
5073 | i
.sib
.scale
<< 6),
5078 /* Write the DREX byte if needed. */
5079 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5082 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5084 /* Encode the OC0 bit if this encoding has multiple
5086 if ((i
.tm
.opcode_modifier
.drex
5087 || i
.tm
.opcode_modifier
.drexv
)
5088 && DREX_OC0 (i
.tm
.extension_opcode
))
5089 *p
|= DREX_OC0_MASK
;
5092 if (i
.disp_operands
)
5093 output_disp (insn_start_frag
, insn_start_off
);
5096 output_imm (insn_start_frag
, insn_start_off
);
5102 pi ("" /*line*/, &i
);
5104 #endif /* DEBUG386 */
5107 /* Return the size of the displacement operand N. */
5110 disp_size (unsigned int n
)
5113 if (i
.types
[n
].bitfield
.disp64
)
5115 else if (i
.types
[n
].bitfield
.disp8
)
5117 else if (i
.types
[n
].bitfield
.disp16
)
5122 /* Return the size of the immediate operand N. */
5125 imm_size (unsigned int n
)
5128 if (i
.types
[n
].bitfield
.imm64
)
5130 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5132 else if (i
.types
[n
].bitfield
.imm16
)
5138 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5143 for (n
= 0; n
< i
.operands
; n
++)
5145 if (operand_type_check (i
.types
[n
], disp
))
5147 if (i
.op
[n
].disps
->X_op
== O_constant
)
5149 int size
= disp_size (n
);
5152 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5154 p
= frag_more (size
);
5155 md_number_to_chars (p
, val
, size
);
5159 enum bfd_reloc_code_real reloc_type
;
5160 int size
= disp_size (n
);
5161 int sign
= i
.types
[n
].bitfield
.disp32s
;
5162 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5164 /* We can't have 8 bit displacement here. */
5165 assert (!i
.types
[n
].bitfield
.disp8
);
5167 /* The PC relative address is computed relative
5168 to the instruction boundary, so in case immediate
5169 fields follows, we need to adjust the value. */
5170 if (pcrel
&& i
.imm_operands
)
5175 for (n1
= 0; n1
< i
.operands
; n1
++)
5176 if (operand_type_check (i
.types
[n1
], imm
))
5178 /* Only one immediate is allowed for PC
5179 relative address. */
5182 i
.op
[n
].disps
->X_add_number
-= sz
;
5184 /* We should find the immediate. */
5188 p
= frag_more (size
);
5189 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5191 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5192 && (((reloc_type
== BFD_RELOC_32
5193 || reloc_type
== BFD_RELOC_X86_64_32S
5194 || (reloc_type
== BFD_RELOC_64
5196 && (i
.op
[n
].disps
->X_op
== O_symbol
5197 || (i
.op
[n
].disps
->X_op
== O_add
5198 && ((symbol_get_value_expression
5199 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5201 || reloc_type
== BFD_RELOC_32_PCREL
))
5205 if (insn_start_frag
== frag_now
)
5206 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5211 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5212 for (fr
= insn_start_frag
->fr_next
;
5213 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5215 add
+= p
- frag_now
->fr_literal
;
5220 reloc_type
= BFD_RELOC_386_GOTPC
;
5221 i
.op
[n
].imms
->X_add_number
+= add
;
5223 else if (reloc_type
== BFD_RELOC_64
)
5224 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5226 /* Don't do the adjustment for x86-64, as there
5227 the pcrel addressing is relative to the _next_
5228 insn, and that is taken care of in other code. */
5229 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5231 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5232 i
.op
[n
].disps
, pcrel
, reloc_type
);
5239 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5244 for (n
= 0; n
< i
.operands
; n
++)
5246 if (operand_type_check (i
.types
[n
], imm
))
5248 if (i
.op
[n
].imms
->X_op
== O_constant
)
5250 int size
= imm_size (n
);
5253 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5255 p
= frag_more (size
);
5256 md_number_to_chars (p
, val
, size
);
5260 /* Not absolute_section.
5261 Need a 32-bit fixup (don't support 8bit
5262 non-absolute imms). Try to support other
5264 enum bfd_reloc_code_real reloc_type
;
5265 int size
= imm_size (n
);
5268 if (i
.types
[n
].bitfield
.imm32s
5269 && (i
.suffix
== QWORD_MNEM_SUFFIX
5270 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5275 p
= frag_more (size
);
5276 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5278 /* This is tough to explain. We end up with this one if we
5279 * have operands that look like
5280 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5281 * obtain the absolute address of the GOT, and it is strongly
5282 * preferable from a performance point of view to avoid using
5283 * a runtime relocation for this. The actual sequence of
5284 * instructions often look something like:
5289 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5291 * The call and pop essentially return the absolute address
5292 * of the label .L66 and store it in %ebx. The linker itself
5293 * will ultimately change the first operand of the addl so
5294 * that %ebx points to the GOT, but to keep things simple, the
5295 * .o file must have this operand set so that it generates not
5296 * the absolute address of .L66, but the absolute address of
5297 * itself. This allows the linker itself simply treat a GOTPC
5298 * relocation as asking for a pcrel offset to the GOT to be
5299 * added in, and the addend of the relocation is stored in the
5300 * operand field for the instruction itself.
5302 * Our job here is to fix the operand so that it would add
5303 * the correct offset so that %ebx would point to itself. The
5304 * thing that is tricky is that .-.L66 will point to the
5305 * beginning of the instruction, so we need to further modify
5306 * the operand so that it will point to itself. There are
5307 * other cases where you have something like:
5309 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5311 * and here no correction would be required. Internally in
5312 * the assembler we treat operands of this form as not being
5313 * pcrel since the '.' is explicitly mentioned, and I wonder
5314 * whether it would simplify matters to do it this way. Who
5315 * knows. In earlier versions of the PIC patches, the
5316 * pcrel_adjust field was used to store the correction, but
5317 * since the expression is not pcrel, I felt it would be
5318 * confusing to do it this way. */
5320 if ((reloc_type
== BFD_RELOC_32
5321 || reloc_type
== BFD_RELOC_X86_64_32S
5322 || reloc_type
== BFD_RELOC_64
)
5324 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5325 && (i
.op
[n
].imms
->X_op
== O_symbol
5326 || (i
.op
[n
].imms
->X_op
== O_add
5327 && ((symbol_get_value_expression
5328 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5333 if (insn_start_frag
== frag_now
)
5334 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5339 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5340 for (fr
= insn_start_frag
->fr_next
;
5341 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5343 add
+= p
- frag_now
->fr_literal
;
5347 reloc_type
= BFD_RELOC_386_GOTPC
;
5349 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5351 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5352 i
.op
[n
].imms
->X_add_number
+= add
;
5354 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5355 i
.op
[n
].imms
, 0, reloc_type
);
5361 /* x86_cons_fix_new is called via the expression parsing code when a
5362 reloc is needed. We use this hook to get the correct .got reloc. */
5363 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5364 static int cons_sign
= -1;
5367 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5370 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5372 got_reloc
= NO_RELOC
;
5375 if (exp
->X_op
== O_secrel
)
5377 exp
->X_op
= O_symbol
;
5378 r
= BFD_RELOC_32_SECREL
;
5382 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5385 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5386 # define lex_got(reloc, adjust, types) NULL
5388 /* Parse operands of the form
5389 <symbol>@GOTOFF+<nnn>
5390 and similar .plt or .got references.
5392 If we find one, set up the correct relocation in RELOC and copy the
5393 input string, minus the `@GOTOFF' into a malloc'd buffer for
5394 parsing by the calling routine. Return this buffer, and if ADJUST
5395 is non-null set it to the length of the string we removed from the
5396 input line. Otherwise return NULL. */
5398 lex_got (enum bfd_reloc_code_real
*reloc
,
5400 i386_operand_type
*types
)
5402 /* Some of the relocations depend on the size of what field is to
5403 be relocated. But in our callers i386_immediate and i386_displacement
5404 we don't yet know the operand size (this will be set by insn
5405 matching). Hence we record the word32 relocation here,
5406 and adjust the reloc according to the real size in reloc(). */
5407 static const struct {
5409 const enum bfd_reloc_code_real rel
[2];
5410 const i386_operand_type types64
;
5413 BFD_RELOC_X86_64_PLTOFF64
},
5414 OPERAND_TYPE_IMM64
},
5415 { "PLT", { BFD_RELOC_386_PLT32
,
5416 BFD_RELOC_X86_64_PLT32
},
5417 OPERAND_TYPE_IMM32_32S_DISP32
},
5419 BFD_RELOC_X86_64_GOTPLT64
},
5420 OPERAND_TYPE_IMM64_DISP64
},
5421 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5422 BFD_RELOC_X86_64_GOTOFF64
},
5423 OPERAND_TYPE_IMM64_DISP64
},
5425 BFD_RELOC_X86_64_GOTPCREL
},
5426 OPERAND_TYPE_IMM32_32S_DISP32
},
5427 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5428 BFD_RELOC_X86_64_TLSGD
},
5429 OPERAND_TYPE_IMM32_32S_DISP32
},
5430 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5432 OPERAND_TYPE_NONE
},
5434 BFD_RELOC_X86_64_TLSLD
},
5435 OPERAND_TYPE_IMM32_32S_DISP32
},
5436 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5437 BFD_RELOC_X86_64_GOTTPOFF
},
5438 OPERAND_TYPE_IMM32_32S_DISP32
},
5439 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5440 BFD_RELOC_X86_64_TPOFF32
},
5441 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5442 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5444 OPERAND_TYPE_NONE
},
5445 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5446 BFD_RELOC_X86_64_DTPOFF32
},
5448 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5449 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5451 OPERAND_TYPE_NONE
},
5452 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5454 OPERAND_TYPE_NONE
},
5455 { "GOT", { BFD_RELOC_386_GOT32
,
5456 BFD_RELOC_X86_64_GOT32
},
5457 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5458 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5459 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5460 OPERAND_TYPE_IMM32_32S_DISP32
},
5461 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5462 BFD_RELOC_X86_64_TLSDESC_CALL
},
5463 OPERAND_TYPE_IMM32_32S_DISP32
},
5471 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5472 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5475 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
5479 len
= strlen (gotrel
[j
].str
);
5480 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5482 if (gotrel
[j
].rel
[object_64bit
] != 0)
5485 char *tmpbuf
, *past_reloc
;
5487 *reloc
= gotrel
[j
].rel
[object_64bit
];
5493 if (flag_code
!= CODE_64BIT
)
5495 types
->bitfield
.imm32
= 1;
5496 types
->bitfield
.disp32
= 1;
5499 *types
= gotrel
[j
].types64
;
5502 if (GOT_symbol
== NULL
)
5503 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5505 /* The length of the first part of our input line. */
5506 first
= cp
- input_line_pointer
;
5508 /* The second part goes from after the reloc token until
5509 (and including) an end_of_line char or comma. */
5510 past_reloc
= cp
+ 1 + len
;
5512 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5514 second
= cp
+ 1 - past_reloc
;
5516 /* Allocate and copy string. The trailing NUL shouldn't
5517 be necessary, but be safe. */
5518 tmpbuf
= xmalloc (first
+ second
+ 2);
5519 memcpy (tmpbuf
, input_line_pointer
, first
);
5520 if (second
!= 0 && *past_reloc
!= ' ')
5521 /* Replace the relocation token with ' ', so that
5522 errors like foo@GOTOFF1 will be detected. */
5523 tmpbuf
[first
++] = ' ';
5524 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5525 tmpbuf
[first
+ second
] = '\0';
5529 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5530 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5535 /* Might be a symbol version string. Don't as_bad here. */
5540 x86_cons (expressionS
*exp
, int size
)
5542 if (size
== 4 || (object_64bit
&& size
== 8))
5544 /* Handle @GOTOFF and the like in an expression. */
5546 char *gotfree_input_line
;
5549 save
= input_line_pointer
;
5550 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5551 if (gotfree_input_line
)
5552 input_line_pointer
= gotfree_input_line
;
5556 if (gotfree_input_line
)
5558 /* expression () has merrily parsed up to the end of line,
5559 or a comma - in the wrong buffer. Transfer how far
5560 input_line_pointer has moved to the right buffer. */
5561 input_line_pointer
= (save
5562 + (input_line_pointer
- gotfree_input_line
)
5564 free (gotfree_input_line
);
5565 if (exp
->X_op
== O_constant
5566 || exp
->X_op
== O_absent
5567 || exp
->X_op
== O_illegal
5568 || exp
->X_op
== O_register
5569 || exp
->X_op
== O_big
)
5571 char c
= *input_line_pointer
;
5572 *input_line_pointer
= 0;
5573 as_bad (_("missing or invalid expression `%s'"), save
);
5574 *input_line_pointer
= c
;
5583 static void signed_cons (int size
)
5585 if (flag_code
== CODE_64BIT
)
5593 pe_directive_secrel (dummy
)
5594 int dummy ATTRIBUTE_UNUSED
;
5601 if (exp
.X_op
== O_symbol
)
5602 exp
.X_op
= O_secrel
;
5604 emit_expr (&exp
, 4);
5606 while (*input_line_pointer
++ == ',');
5608 input_line_pointer
--;
5609 demand_empty_rest_of_line ();
5614 i386_immediate (char *imm_start
)
5616 char *save_input_line_pointer
;
5617 char *gotfree_input_line
;
5620 i386_operand_type types
;
5622 UINTS_SET (types
, ~0);
5624 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5626 as_bad (_("at most %d immediate operands are allowed"),
5627 MAX_IMMEDIATE_OPERANDS
);
5631 exp
= &im_expressions
[i
.imm_operands
++];
5632 i
.op
[this_operand
].imms
= exp
;
5634 if (is_space_char (*imm_start
))
5637 save_input_line_pointer
= input_line_pointer
;
5638 input_line_pointer
= imm_start
;
5640 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5641 if (gotfree_input_line
)
5642 input_line_pointer
= gotfree_input_line
;
5644 exp_seg
= expression (exp
);
5647 if (*input_line_pointer
)
5648 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5650 input_line_pointer
= save_input_line_pointer
;
5651 if (gotfree_input_line
)
5652 free (gotfree_input_line
);
5654 if (exp
->X_op
== O_absent
5655 || exp
->X_op
== O_illegal
5656 || exp
->X_op
== O_big
5657 || (gotfree_input_line
5658 && (exp
->X_op
== O_constant
5659 || exp
->X_op
== O_register
)))
5661 as_bad (_("missing or invalid immediate expression `%s'"),
5665 else if (exp
->X_op
== O_constant
)
5667 /* Size it properly later. */
5668 i
.types
[this_operand
].bitfield
.imm64
= 1;
5669 /* If BFD64, sign extend val. */
5670 if (!use_rela_relocations
5671 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5673 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5675 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5676 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5677 && exp_seg
!= absolute_section
5678 && exp_seg
!= text_section
5679 && exp_seg
!= data_section
5680 && exp_seg
!= bss_section
5681 && exp_seg
!= undefined_section
5682 && !bfd_is_com_section (exp_seg
))
5684 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5688 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5690 as_bad (_("illegal immediate register operand %s"), imm_start
);
5695 /* This is an address. The size of the address will be
5696 determined later, depending on destination register,
5697 suffix, or the default for the section. */
5698 i
.types
[this_operand
].bitfield
.imm8
= 1;
5699 i
.types
[this_operand
].bitfield
.imm16
= 1;
5700 i
.types
[this_operand
].bitfield
.imm32
= 1;
5701 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5702 i
.types
[this_operand
].bitfield
.imm64
= 1;
5703 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5711 i386_scale (char *scale
)
5714 char *save
= input_line_pointer
;
5716 input_line_pointer
= scale
;
5717 val
= get_absolute_expression ();
5722 i
.log2_scale_factor
= 0;
5725 i
.log2_scale_factor
= 1;
5728 i
.log2_scale_factor
= 2;
5731 i
.log2_scale_factor
= 3;
5735 char sep
= *input_line_pointer
;
5737 *input_line_pointer
= '\0';
5738 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5740 *input_line_pointer
= sep
;
5741 input_line_pointer
= save
;
5745 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5747 as_warn (_("scale factor of %d without an index register"),
5748 1 << i
.log2_scale_factor
);
5749 i
.log2_scale_factor
= 0;
5751 scale
= input_line_pointer
;
5752 input_line_pointer
= save
;
5757 i386_displacement (char *disp_start
, char *disp_end
)
5761 char *save_input_line_pointer
;
5762 char *gotfree_input_line
;
5764 i386_operand_type bigdisp
, types
= anydisp
;
5767 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5769 as_bad (_("at most %d displacement operands are allowed"),
5770 MAX_MEMORY_OPERANDS
);
5774 UINTS_CLEAR (bigdisp
);
5775 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5776 || (!current_templates
->start
->opcode_modifier
.jump
5777 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5779 bigdisp
.bitfield
.disp32
= 1;
5780 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5781 if (flag_code
== CODE_64BIT
)
5785 bigdisp
.bitfield
.disp32s
= 1;
5786 bigdisp
.bitfield
.disp64
= 1;
5789 else if ((flag_code
== CODE_16BIT
) ^ override
)
5791 bigdisp
.bitfield
.disp32
= 0;
5792 bigdisp
.bitfield
.disp16
= 1;
5797 /* For PC-relative branches, the width of the displacement
5798 is dependent upon data size, not address size. */
5799 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5800 if (flag_code
== CODE_64BIT
)
5802 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5803 bigdisp
.bitfield
.disp16
= 1;
5806 bigdisp
.bitfield
.disp32
= 1;
5807 bigdisp
.bitfield
.disp32s
= 1;
5813 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5815 : LONG_MNEM_SUFFIX
));
5816 bigdisp
.bitfield
.disp32
= 1;
5817 if ((flag_code
== CODE_16BIT
) ^ override
)
5819 bigdisp
.bitfield
.disp32
= 0;
5820 bigdisp
.bitfield
.disp16
= 1;
5824 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5827 exp
= &disp_expressions
[i
.disp_operands
];
5828 i
.op
[this_operand
].disps
= exp
;
5830 save_input_line_pointer
= input_line_pointer
;
5831 input_line_pointer
= disp_start
;
5832 END_STRING_AND_SAVE (disp_end
);
5834 #ifndef GCC_ASM_O_HACK
5835 #define GCC_ASM_O_HACK 0
5838 END_STRING_AND_SAVE (disp_end
+ 1);
5839 if (i
.types
[this_operand
].bitfield
.baseIndex
5840 && displacement_string_end
[-1] == '+')
5842 /* This hack is to avoid a warning when using the "o"
5843 constraint within gcc asm statements.
5846 #define _set_tssldt_desc(n,addr,limit,type) \
5847 __asm__ __volatile__ ( \
5849 "movw %w1,2+%0\n\t" \
5851 "movb %b1,4+%0\n\t" \
5852 "movb %4,5+%0\n\t" \
5853 "movb $0,6+%0\n\t" \
5854 "movb %h1,7+%0\n\t" \
5856 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5858 This works great except that the output assembler ends
5859 up looking a bit weird if it turns out that there is
5860 no offset. You end up producing code that looks like:
5873 So here we provide the missing zero. */
5875 *displacement_string_end
= '0';
5878 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5879 if (gotfree_input_line
)
5880 input_line_pointer
= gotfree_input_line
;
5882 exp_seg
= expression (exp
);
5885 if (*input_line_pointer
)
5886 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5888 RESTORE_END_STRING (disp_end
+ 1);
5890 input_line_pointer
= save_input_line_pointer
;
5891 if (gotfree_input_line
)
5892 free (gotfree_input_line
);
5895 /* We do this to make sure that the section symbol is in
5896 the symbol table. We will ultimately change the relocation
5897 to be relative to the beginning of the section. */
5898 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5899 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5900 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5902 if (exp
->X_op
!= O_symbol
)
5905 if (S_IS_LOCAL (exp
->X_add_symbol
)
5906 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5907 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5908 exp
->X_op
= O_subtract
;
5909 exp
->X_op_symbol
= GOT_symbol
;
5910 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
5911 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
5912 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5913 i
.reloc
[this_operand
] = BFD_RELOC_64
;
5915 i
.reloc
[this_operand
] = BFD_RELOC_32
;
5918 else if (exp
->X_op
== O_absent
5919 || exp
->X_op
== O_illegal
5920 || exp
->X_op
== O_big
5921 || (gotfree_input_line
5922 && (exp
->X_op
== O_constant
5923 || exp
->X_op
== O_register
)))
5926 as_bad (_("missing or invalid displacement expression `%s'"),
5931 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5932 else if (exp
->X_op
!= O_constant
5933 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
5934 && exp_seg
!= absolute_section
5935 && exp_seg
!= text_section
5936 && exp_seg
!= data_section
5937 && exp_seg
!= bss_section
5938 && exp_seg
!= undefined_section
5939 && !bfd_is_com_section (exp_seg
))
5941 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5946 RESTORE_END_STRING (disp_end
);
5948 /* Check if this is a displacement only operand. */
5949 bigdisp
= i
.types
[this_operand
];
5950 bigdisp
.bitfield
.disp8
= 0;
5951 bigdisp
.bitfield
.disp16
= 0;
5952 bigdisp
.bitfield
.disp32
= 0;
5953 bigdisp
.bitfield
.disp32s
= 0;
5954 bigdisp
.bitfield
.disp64
= 0;
5955 if (UINTS_ALL_ZERO (bigdisp
))
5956 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5962 /* Make sure the memory operand we've been dealt is valid.
5963 Return 1 on success, 0 on a failure. */
5966 i386_index_check (const char *operand_string
)
5969 #if INFER_ADDR_PREFIX
5975 if (flag_code
== CODE_64BIT
)
5978 && ((i
.prefix
[ADDR_PREFIX
] == 0
5979 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
5980 || (i
.prefix
[ADDR_PREFIX
]
5981 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
5983 || i
.base_reg
->reg_num
!= RegRip
))
5985 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
5986 || (i
.prefix
[ADDR_PREFIX
] == 0
5987 && i
.index_reg
->reg_num
!= RegRiz
5988 && !i
.index_reg
->reg_type
.bitfield
.reg64
5990 || (i
.prefix
[ADDR_PREFIX
]
5991 && i
.index_reg
->reg_num
!= RegEiz
5992 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
5997 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6001 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6002 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6004 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6005 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6007 && i
.base_reg
->reg_num
< 6
6008 && i
.index_reg
->reg_num
>= 6
6009 && i
.log2_scale_factor
== 0))))
6016 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6018 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6019 && i
.index_reg
->reg_num
!= RegEiz
)
6020 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6026 #if INFER_ADDR_PREFIX
6027 if (i
.prefix
[ADDR_PREFIX
] == 0)
6029 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6031 /* Change the size of any displacement too. At most one of
6032 Disp16 or Disp32 is set.
6033 FIXME. There doesn't seem to be any real need for separate
6034 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6035 Removing them would probably clean up the code quite a lot. */
6036 if (flag_code
!= CODE_64BIT
6037 && (i
.types
[this_operand
].bitfield
.disp16
6038 || i
.types
[this_operand
].bitfield
.disp32
))
6039 i
.types
[this_operand
]
6040 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6045 as_bad (_("`%s' is not a valid base/index expression"),
6049 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6051 flag_code_names
[flag_code
]);
6056 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6060 i386_operand (char *operand_string
)
6064 char *op_string
= operand_string
;
6066 if (is_space_char (*op_string
))
6069 /* We check for an absolute prefix (differentiating,
6070 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6071 if (*op_string
== ABSOLUTE_PREFIX
)
6074 if (is_space_char (*op_string
))
6076 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6079 /* Check if operand is a register. */
6080 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6082 i386_operand_type temp
;
6084 /* Check for a segment override by searching for ':' after a
6085 segment register. */
6087 if (is_space_char (*op_string
))
6089 if (*op_string
== ':'
6090 && (r
->reg_type
.bitfield
.sreg2
6091 || r
->reg_type
.bitfield
.sreg3
))
6096 i
.seg
[i
.mem_operands
] = &es
;
6099 i
.seg
[i
.mem_operands
] = &cs
;
6102 i
.seg
[i
.mem_operands
] = &ss
;
6105 i
.seg
[i
.mem_operands
] = &ds
;
6108 i
.seg
[i
.mem_operands
] = &fs
;
6111 i
.seg
[i
.mem_operands
] = &gs
;
6115 /* Skip the ':' and whitespace. */
6117 if (is_space_char (*op_string
))
6120 if (!is_digit_char (*op_string
)
6121 && !is_identifier_char (*op_string
)
6122 && *op_string
!= '('
6123 && *op_string
!= ABSOLUTE_PREFIX
)
6125 as_bad (_("bad memory operand `%s'"), op_string
);
6128 /* Handle case of %es:*foo. */
6129 if (*op_string
== ABSOLUTE_PREFIX
)
6132 if (is_space_char (*op_string
))
6134 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6136 goto do_memory_reference
;
6140 as_bad (_("junk `%s' after register"), op_string
);
6144 temp
.bitfield
.baseindex
= 0;
6145 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6147 i
.op
[this_operand
].regs
= r
;
6150 else if (*op_string
== REGISTER_PREFIX
)
6152 as_bad (_("bad register name `%s'"), op_string
);
6155 else if (*op_string
== IMMEDIATE_PREFIX
)
6158 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6160 as_bad (_("immediate operand illegal with absolute jump"));
6163 if (!i386_immediate (op_string
))
6166 else if (is_digit_char (*op_string
)
6167 || is_identifier_char (*op_string
)
6168 || *op_string
== '(')
6170 /* This is a memory reference of some sort. */
6173 /* Start and end of displacement string expression (if found). */
6174 char *displacement_string_start
;
6175 char *displacement_string_end
;
6177 do_memory_reference
:
6178 if ((i
.mem_operands
== 1
6179 && !current_templates
->start
->opcode_modifier
.isstring
)
6180 || i
.mem_operands
== 2)
6182 as_bad (_("too many memory references for `%s'"),
6183 current_templates
->start
->name
);
6187 /* Check for base index form. We detect the base index form by
6188 looking for an ')' at the end of the operand, searching
6189 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6191 base_string
= op_string
+ strlen (op_string
);
6194 if (is_space_char (*base_string
))
6197 /* If we only have a displacement, set-up for it to be parsed later. */
6198 displacement_string_start
= op_string
;
6199 displacement_string_end
= base_string
+ 1;
6201 if (*base_string
== ')')
6204 unsigned int parens_balanced
= 1;
6205 /* We've already checked that the number of left & right ()'s are
6206 equal, so this loop will not be infinite. */
6210 if (*base_string
== ')')
6212 if (*base_string
== '(')
6215 while (parens_balanced
);
6217 temp_string
= base_string
;
6219 /* Skip past '(' and whitespace. */
6221 if (is_space_char (*base_string
))
6224 if (*base_string
== ','
6225 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6228 displacement_string_end
= temp_string
;
6230 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6234 base_string
= end_op
;
6235 if (is_space_char (*base_string
))
6239 /* There may be an index reg or scale factor here. */
6240 if (*base_string
== ',')
6243 if (is_space_char (*base_string
))
6246 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6249 base_string
= end_op
;
6250 if (is_space_char (*base_string
))
6252 if (*base_string
== ',')
6255 if (is_space_char (*base_string
))
6258 else if (*base_string
!= ')')
6260 as_bad (_("expecting `,' or `)' "
6261 "after index register in `%s'"),
6266 else if (*base_string
== REGISTER_PREFIX
)
6268 as_bad (_("bad register name `%s'"), base_string
);
6272 /* Check for scale factor. */
6273 if (*base_string
!= ')')
6275 char *end_scale
= i386_scale (base_string
);
6280 base_string
= end_scale
;
6281 if (is_space_char (*base_string
))
6283 if (*base_string
!= ')')
6285 as_bad (_("expecting `)' "
6286 "after scale factor in `%s'"),
6291 else if (!i
.index_reg
)
6293 as_bad (_("expecting index register or scale factor "
6294 "after `,'; got '%c'"),
6299 else if (*base_string
!= ')')
6301 as_bad (_("expecting `,' or `)' "
6302 "after base register in `%s'"),
6307 else if (*base_string
== REGISTER_PREFIX
)
6309 as_bad (_("bad register name `%s'"), base_string
);
6314 /* If there's an expression beginning the operand, parse it,
6315 assuming displacement_string_start and
6316 displacement_string_end are meaningful. */
6317 if (displacement_string_start
!= displacement_string_end
)
6319 if (!i386_displacement (displacement_string_start
,
6320 displacement_string_end
))
6324 /* Special case for (%dx) while doing input/output op. */
6326 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
6328 && i
.log2_scale_factor
== 0
6329 && i
.seg
[i
.mem_operands
] == 0
6330 && !operand_type_check (i
.types
[this_operand
], disp
))
6332 UINTS_CLEAR (i
.types
[this_operand
]);
6333 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
6337 if (i386_index_check (operand_string
) == 0)
6343 /* It's not a memory operand; argh! */
6344 as_bad (_("invalid char %s beginning operand %d `%s'"),
6345 output_invalid (*op_string
),
6350 return 1; /* Normal return. */
6353 /* md_estimate_size_before_relax()
6355 Called just before relax() for rs_machine_dependent frags. The x86
6356 assembler uses these frags to handle variable size jump
6359 Any symbol that is now undefined will not become defined.
6360 Return the correct fr_subtype in the frag.
6361 Return the initial "guess for variable size of frag" to caller.
6362 The guess is actually the growth beyond the fixed part. Whatever
6363 we do to grow the fixed or variable part contributes to our
6367 md_estimate_size_before_relax (fragP
, segment
)
6371 /* We've already got fragP->fr_subtype right; all we have to do is
6372 check for un-relaxable symbols. On an ELF system, we can't relax
6373 an externally visible symbol, because it may be overridden by a
6375 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6378 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6379 || S_IS_WEAK (fragP
->fr_symbol
)))
6383 /* Symbol is undefined in this segment, or we need to keep a
6384 reloc so that weak symbols can be overridden. */
6385 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6386 enum bfd_reloc_code_real reloc_type
;
6387 unsigned char *opcode
;
6390 if (fragP
->fr_var
!= NO_RELOC
)
6391 reloc_type
= fragP
->fr_var
;
6393 reloc_type
= BFD_RELOC_16_PCREL
;
6395 reloc_type
= BFD_RELOC_32_PCREL
;
6397 old_fr_fix
= fragP
->fr_fix
;
6398 opcode
= (unsigned char *) fragP
->fr_opcode
;
6400 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6403 /* Make jmp (0xeb) a (d)word displacement jump. */
6405 fragP
->fr_fix
+= size
;
6406 fix_new (fragP
, old_fr_fix
, size
,
6408 fragP
->fr_offset
, 1,
6414 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6416 /* Negate the condition, and branch past an
6417 unconditional jump. */
6420 /* Insert an unconditional jump. */
6422 /* We added two extra opcode bytes, and have a two byte
6424 fragP
->fr_fix
+= 2 + 2;
6425 fix_new (fragP
, old_fr_fix
+ 2, 2,
6427 fragP
->fr_offset
, 1,
6434 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6439 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6441 fragP
->fr_offset
, 1,
6443 fixP
->fx_signed
= 1;
6447 /* This changes the byte-displacement jump 0x7N
6448 to the (d)word-displacement jump 0x0f,0x8N. */
6449 opcode
[1] = opcode
[0] + 0x10;
6450 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6451 /* We've added an opcode byte. */
6452 fragP
->fr_fix
+= 1 + size
;
6453 fix_new (fragP
, old_fr_fix
+ 1, size
,
6455 fragP
->fr_offset
, 1,
6460 BAD_CASE (fragP
->fr_subtype
);
6464 return fragP
->fr_fix
- old_fr_fix
;
6467 /* Guess size depending on current relax state. Initially the relax
6468 state will correspond to a short jump and we return 1, because
6469 the variable part of the frag (the branch offset) is one byte
6470 long. However, we can relax a section more than once and in that
6471 case we must either set fr_subtype back to the unrelaxed state,
6472 or return the value for the appropriate branch. */
6473 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6476 /* Called after relax() is finished.
6478 In: Address of frag.
6479 fr_type == rs_machine_dependent.
6480 fr_subtype is what the address relaxed to.
6482 Out: Any fixSs and constants are set up.
6483 Caller will turn frag into a ".space 0". */
6486 md_convert_frag (abfd
, sec
, fragP
)
6487 bfd
*abfd ATTRIBUTE_UNUSED
;
6488 segT sec ATTRIBUTE_UNUSED
;
6491 unsigned char *opcode
;
6492 unsigned char *where_to_put_displacement
= NULL
;
6493 offsetT target_address
;
6494 offsetT opcode_address
;
6495 unsigned int extension
= 0;
6496 offsetT displacement_from_opcode_start
;
6498 opcode
= (unsigned char *) fragP
->fr_opcode
;
6500 /* Address we want to reach in file space. */
6501 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6503 /* Address opcode resides at in file space. */
6504 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6506 /* Displacement from opcode start to fill into instruction. */
6507 displacement_from_opcode_start
= target_address
- opcode_address
;
6509 if ((fragP
->fr_subtype
& BIG
) == 0)
6511 /* Don't have to change opcode. */
6512 extension
= 1; /* 1 opcode + 1 displacement */
6513 where_to_put_displacement
= &opcode
[1];
6517 if (no_cond_jump_promotion
6518 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6519 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6520 _("long jump required"));
6522 switch (fragP
->fr_subtype
)
6524 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6525 extension
= 4; /* 1 opcode + 4 displacement */
6527 where_to_put_displacement
= &opcode
[1];
6530 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6531 extension
= 2; /* 1 opcode + 2 displacement */
6533 where_to_put_displacement
= &opcode
[1];
6536 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6537 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6538 extension
= 5; /* 2 opcode + 4 displacement */
6539 opcode
[1] = opcode
[0] + 0x10;
6540 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6541 where_to_put_displacement
= &opcode
[2];
6544 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6545 extension
= 3; /* 2 opcode + 2 displacement */
6546 opcode
[1] = opcode
[0] + 0x10;
6547 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6548 where_to_put_displacement
= &opcode
[2];
6551 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6556 where_to_put_displacement
= &opcode
[3];
6560 BAD_CASE (fragP
->fr_subtype
);
6565 /* If size if less then four we are sure that the operand fits,
6566 but if it's 4, then it could be that the displacement is larger
6568 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6570 && ((addressT
) (displacement_from_opcode_start
- extension
6571 + ((addressT
) 1 << 31))
6572 > (((addressT
) 2 << 31) - 1)))
6574 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6575 _("jump target out of range"));
6576 /* Make us emit 0. */
6577 displacement_from_opcode_start
= extension
;
6579 /* Now put displacement after opcode. */
6580 md_number_to_chars ((char *) where_to_put_displacement
,
6581 (valueT
) (displacement_from_opcode_start
- extension
),
6582 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6583 fragP
->fr_fix
+= extension
;
6586 /* Size of byte displacement jmp. */
6587 int md_short_jump_size
= 2;
6589 /* Size of dword displacement jmp. */
6590 int md_long_jump_size
= 5;
6593 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
6595 addressT from_addr
, to_addr
;
6596 fragS
*frag ATTRIBUTE_UNUSED
;
6597 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
6601 offset
= to_addr
- (from_addr
+ 2);
6602 /* Opcode for byte-disp jump. */
6603 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
6604 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
6608 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
6610 addressT from_addr
, to_addr
;
6611 fragS
*frag ATTRIBUTE_UNUSED
;
6612 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
6616 offset
= to_addr
- (from_addr
+ 5);
6617 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
6618 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
6621 /* Apply a fixup (fixS) to segment data, once it has been determined
6622 by our caller that we have all the info we need to fix it up.
6624 On the 386, immediates, displacements, and data pointers are all in
6625 the same (little-endian) format, so we don't need to care about which
6629 md_apply_fix (fixP
, valP
, seg
)
6630 /* The fix we're to put in. */
6632 /* Pointer to the value of the bits. */
6634 /* Segment fix is from. */
6635 segT seg ATTRIBUTE_UNUSED
;
6637 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6638 valueT value
= *valP
;
6640 #if !defined (TE_Mach)
6643 switch (fixP
->fx_r_type
)
6649 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6652 case BFD_RELOC_X86_64_32S
:
6653 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6656 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6659 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6664 if (fixP
->fx_addsy
!= NULL
6665 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6666 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6667 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6668 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6669 && !use_rela_relocations
)
6671 /* This is a hack. There should be a better way to handle this.
6672 This covers for the fact that bfd_install_relocation will
6673 subtract the current location (for partial_inplace, PC relative
6674 relocations); see more below. */
6678 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6681 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6683 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6686 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6689 || (symbol_section_p (fixP
->fx_addsy
)
6690 && sym_seg
!= absolute_section
))
6691 && !generic_force_reloc (fixP
))
6693 /* Yes, we add the values in twice. This is because
6694 bfd_install_relocation subtracts them out again. I think
6695 bfd_install_relocation is broken, but I don't dare change
6697 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6701 #if defined (OBJ_COFF) && defined (TE_PE)
6702 /* For some reason, the PE format does not store a
6703 section address offset for a PC relative symbol. */
6704 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6705 || S_IS_WEAK (fixP
->fx_addsy
))
6706 value
+= md_pcrel_from (fixP
);
6710 /* Fix a few things - the dynamic linker expects certain values here,
6711 and we must not disappoint it. */
6712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6713 if (IS_ELF
&& fixP
->fx_addsy
)
6714 switch (fixP
->fx_r_type
)
6716 case BFD_RELOC_386_PLT32
:
6717 case BFD_RELOC_X86_64_PLT32
:
6718 /* Make the jump instruction point to the address of the operand. At
6719 runtime we merely add the offset to the actual PLT entry. */
6723 case BFD_RELOC_386_TLS_GD
:
6724 case BFD_RELOC_386_TLS_LDM
:
6725 case BFD_RELOC_386_TLS_IE_32
:
6726 case BFD_RELOC_386_TLS_IE
:
6727 case BFD_RELOC_386_TLS_GOTIE
:
6728 case BFD_RELOC_386_TLS_GOTDESC
:
6729 case BFD_RELOC_X86_64_TLSGD
:
6730 case BFD_RELOC_X86_64_TLSLD
:
6731 case BFD_RELOC_X86_64_GOTTPOFF
:
6732 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6733 value
= 0; /* Fully resolved at runtime. No addend. */
6735 case BFD_RELOC_386_TLS_LE
:
6736 case BFD_RELOC_386_TLS_LDO_32
:
6737 case BFD_RELOC_386_TLS_LE_32
:
6738 case BFD_RELOC_X86_64_DTPOFF32
:
6739 case BFD_RELOC_X86_64_DTPOFF64
:
6740 case BFD_RELOC_X86_64_TPOFF32
:
6741 case BFD_RELOC_X86_64_TPOFF64
:
6742 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6745 case BFD_RELOC_386_TLS_DESC_CALL
:
6746 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6747 value
= 0; /* Fully resolved at runtime. No addend. */
6748 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6752 case BFD_RELOC_386_GOT32
:
6753 case BFD_RELOC_X86_64_GOT32
:
6754 value
= 0; /* Fully resolved at runtime. No addend. */
6757 case BFD_RELOC_VTABLE_INHERIT
:
6758 case BFD_RELOC_VTABLE_ENTRY
:
6765 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6767 #endif /* !defined (TE_Mach) */
6769 /* Are we finished with this relocation now? */
6770 if (fixP
->fx_addsy
== NULL
)
6772 else if (use_rela_relocations
)
6774 fixP
->fx_no_overflow
= 1;
6775 /* Remember value for tc_gen_reloc. */
6776 fixP
->fx_addnumber
= value
;
6780 md_number_to_chars (p
, value
, fixP
->fx_size
);
6783 #define MAX_LITTLENUMS 6
6785 /* Turn the string pointed to by litP into a floating point constant
6786 of type TYPE, and emit the appropriate bytes. The number of
6787 LITTLENUMS emitted is stored in *SIZEP. An error message is
6788 returned, or NULL on OK. */
6791 md_atof (type
, litP
, sizeP
)
6797 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
6798 LITTLENUM_TYPE
*wordP
;
6820 return _("Bad call to md_atof ()");
6822 t
= atof_ieee (input_line_pointer
, type
, words
);
6824 input_line_pointer
= t
;
6826 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
6827 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6828 the bigendian 386. */
6829 for (wordP
= words
+ prec
- 1; prec
--;)
6831 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
6832 litP
+= sizeof (LITTLENUM_TYPE
);
6837 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6840 output_invalid (int c
)
6843 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6846 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6847 "(0x%x)", (unsigned char) c
);
6848 return output_invalid_buf
;
6851 /* REG_STRING starts *before* REGISTER_PREFIX. */
6853 static const reg_entry
*
6854 parse_real_register (char *reg_string
, char **end_op
)
6856 char *s
= reg_string
;
6858 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6861 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6862 if (*s
== REGISTER_PREFIX
)
6865 if (is_space_char (*s
))
6869 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6871 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6872 return (const reg_entry
*) NULL
;
6876 /* For naked regs, make sure that we are not dealing with an identifier.
6877 This prevents confusing an identifier like `eax_var' with register
6879 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6880 return (const reg_entry
*) NULL
;
6884 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6886 /* Handle floating point regs, allowing spaces in the (i) part. */
6887 if (r
== i386_regtab
/* %st is first entry of table */)
6889 if (is_space_char (*s
))
6894 if (is_space_char (*s
))
6896 if (*s
>= '0' && *s
<= '7')
6900 if (is_space_char (*s
))
6905 r
= hash_find (reg_hash
, "st(0)");
6910 /* We have "%st(" then garbage. */
6911 return (const reg_entry
*) NULL
;
6915 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6918 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
6919 return (const reg_entry
*) NULL
;
6922 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6923 || r
->reg_type
.bitfield
.reg64
)
6924 && (!cpu_arch_flags
.bitfield
.cpulm
6925 || !UINTS_EQUAL (r
->reg_type
, control
))
6926 && flag_code
!= CODE_64BIT
)
6927 return (const reg_entry
*) NULL
;
6932 /* REG_STRING starts *before* REGISTER_PREFIX. */
6934 static const reg_entry
*
6935 parse_register (char *reg_string
, char **end_op
)
6939 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6940 r
= parse_real_register (reg_string
, end_op
);
6945 char *save
= input_line_pointer
;
6949 input_line_pointer
= reg_string
;
6950 c
= get_symbol_end ();
6951 symbolP
= symbol_find (reg_string
);
6952 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6954 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6956 know (e
->X_op
== O_register
);
6957 know (e
->X_add_number
>= 0
6958 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6959 r
= i386_regtab
+ e
->X_add_number
;
6960 *end_op
= input_line_pointer
;
6962 *input_line_pointer
= c
;
6963 input_line_pointer
= save
;
6969 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6972 char *end
= input_line_pointer
;
6975 r
= parse_register (name
, &input_line_pointer
);
6976 if (r
&& end
<= input_line_pointer
)
6978 *nextcharP
= *input_line_pointer
;
6979 *input_line_pointer
= 0;
6980 e
->X_op
= O_register
;
6981 e
->X_add_number
= r
- i386_regtab
;
6984 input_line_pointer
= end
;
6990 md_operand (expressionS
*e
)
6992 if (*input_line_pointer
== REGISTER_PREFIX
)
6995 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
6999 e
->X_op
= O_register
;
7000 e
->X_add_number
= r
- i386_regtab
;
7001 input_line_pointer
= end
;
7007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7008 const char *md_shortopts
= "kVQ:sqn";
7010 const char *md_shortopts
= "qn";
7013 #define OPTION_32 (OPTION_MD_BASE + 0)
7014 #define OPTION_64 (OPTION_MD_BASE + 1)
7015 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7016 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7017 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7019 struct option md_longopts
[] =
7021 {"32", no_argument
, NULL
, OPTION_32
},
7022 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7023 {"64", no_argument
, NULL
, OPTION_64
},
7025 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7026 {"march", required_argument
, NULL
, OPTION_MARCH
},
7027 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7028 {NULL
, no_argument
, NULL
, 0}
7030 size_t md_longopts_size
= sizeof (md_longopts
);
7033 md_parse_option (int c
, char *arg
)
7040 optimize_align_code
= 0;
7047 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7048 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7049 should be emitted or not. FIXME: Not implemented. */
7053 /* -V: SVR4 argument to print version ID. */
7055 print_version_id ();
7058 /* -k: Ignore for FreeBSD compatibility. */
7063 /* -s: On i386 Solaris, this tells the native assembler to use
7064 .stab instead of .stab.excl. We always use .stab anyhow. */
7067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7070 const char **list
, **l
;
7072 list
= bfd_target_list ();
7073 for (l
= list
; *l
!= NULL
; l
++)
7074 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7075 || strcmp (*l
, "coff-x86-64") == 0
7076 || strcmp (*l
, "pe-x86-64") == 0
7077 || strcmp (*l
, "pei-x86-64") == 0)
7079 default_arch
= "x86_64";
7083 as_fatal (_("No compiled in support for x86_64"));
7090 default_arch
= "i386";
7094 #ifdef SVR4_COMMENT_CHARS
7099 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7101 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7105 i386_comment_chars
= n
;
7112 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7113 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7115 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7117 cpu_arch_isa
= cpu_arch
[i
].type
;
7118 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7119 if (!cpu_arch_tune_set
)
7121 cpu_arch_tune
= cpu_arch_isa
;
7122 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7127 if (i
>= ARRAY_SIZE (cpu_arch
))
7128 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7133 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7134 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7136 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7138 cpu_arch_tune_set
= 1;
7139 cpu_arch_tune
= cpu_arch
[i
].type
;
7140 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7144 if (i
>= ARRAY_SIZE (cpu_arch
))
7145 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7155 md_show_usage (stream
)
7158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7159 fprintf (stream
, _("\
7161 -V print assembler version number\n\
7164 fprintf (stream
, _("\
7165 -n Do not optimize code alignment\n\
7166 -q quieten some warnings\n"));
7167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7168 fprintf (stream
, _("\
7171 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7172 fprintf (stream
, _("\
7173 --32/--64 generate 32bit/64bit code\n"));
7175 #ifdef SVR4_COMMENT_CHARS
7176 fprintf (stream
, _("\
7177 --divide do not treat `/' as a comment character\n"));
7179 fprintf (stream
, _("\
7180 --divide ignored\n"));
7182 fprintf (stream
, _("\
7183 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7184 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7185 core, core2, k6, athlon, k8, generic32, generic64\n"));
7189 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7190 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7192 /* Pick the target format to use. */
7195 i386_target_format (void)
7197 if (!strcmp (default_arch
, "x86_64"))
7199 set_code_flag (CODE_64BIT
);
7200 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7202 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7203 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7204 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7205 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7206 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7207 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7208 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
7209 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7210 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
7211 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7212 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7214 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7216 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7217 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7218 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7219 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7220 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7221 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7222 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
7223 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7224 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
7225 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7226 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7229 else if (!strcmp (default_arch
, "i386"))
7231 set_code_flag (CODE_32BIT
);
7232 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7234 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7235 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7236 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7238 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7240 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7241 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7242 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7246 as_fatal (_("Unknown architecture"));
7247 switch (OUTPUT_FLAVOR
)
7250 case bfd_target_coff_flavour
:
7251 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
7254 #ifdef OBJ_MAYBE_AOUT
7255 case bfd_target_aout_flavour
:
7256 return AOUT_TARGET_FORMAT
;
7258 #ifdef OBJ_MAYBE_COFF
7259 case bfd_target_coff_flavour
:
7262 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7263 case bfd_target_elf_flavour
:
7265 if (flag_code
== CODE_64BIT
)
7268 use_rela_relocations
= 1;
7270 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7279 #endif /* OBJ_MAYBE_ more than one */
7281 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7283 i386_elf_emit_arch_note (void)
7285 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7288 asection
*seg
= now_seg
;
7289 subsegT subseg
= now_subseg
;
7290 Elf_Internal_Note i_note
;
7291 Elf_External_Note e_note
;
7292 asection
*note_secp
;
7295 /* Create the .note section. */
7296 note_secp
= subseg_new (".note", 0);
7297 bfd_set_section_flags (stdoutput
,
7299 SEC_HAS_CONTENTS
| SEC_READONLY
);
7301 /* Process the arch string. */
7302 len
= strlen (cpu_arch_name
);
7304 i_note
.namesz
= len
+ 1;
7306 i_note
.type
= NT_ARCH
;
7307 p
= frag_more (sizeof (e_note
.namesz
));
7308 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
7309 p
= frag_more (sizeof (e_note
.descsz
));
7310 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
7311 p
= frag_more (sizeof (e_note
.type
));
7312 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
7313 p
= frag_more (len
+ 1);
7314 strcpy (p
, cpu_arch_name
);
7316 frag_align (2, 0, 0);
7318 subseg_set (seg
, subseg
);
7324 md_undefined_symbol (name
)
7327 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
7328 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
7329 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
7330 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
7334 if (symbol_find (name
))
7335 as_bad (_("GOT already in symbol table"));
7336 GOT_symbol
= symbol_new (name
, undefined_section
,
7337 (valueT
) 0, &zero_address_frag
);
7344 /* Round up a section size to the appropriate boundary. */
7347 md_section_align (segment
, size
)
7348 segT segment ATTRIBUTE_UNUSED
;
7351 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7352 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
7354 /* For a.out, force the section size to be aligned. If we don't do
7355 this, BFD will align it for us, but it will not write out the
7356 final bytes of the section. This may be a bug in BFD, but it is
7357 easier to fix it here since that is how the other a.out targets
7361 align
= bfd_get_section_alignment (stdoutput
, segment
);
7362 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7369 /* On the i386, PC-relative offsets are relative to the start of the
7370 next instruction. That is, the address of the offset, plus its
7371 size, since the offset is always the last part of the insn. */
7374 md_pcrel_from (fixS
*fixP
)
7376 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7382 s_bss (int ignore ATTRIBUTE_UNUSED
)
7386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7388 obj_elf_section_change_hook ();
7390 temp
= get_absolute_expression ();
7391 subseg_set (bss_section
, (subsegT
) temp
);
7392 demand_empty_rest_of_line ();
7398 i386_validate_fix (fixS
*fixp
)
7400 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
7402 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
7406 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
7411 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
7413 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
7420 tc_gen_reloc (section
, fixp
)
7421 asection
*section ATTRIBUTE_UNUSED
;
7425 bfd_reloc_code_real_type code
;
7427 switch (fixp
->fx_r_type
)
7429 case BFD_RELOC_X86_64_PLT32
:
7430 case BFD_RELOC_X86_64_GOT32
:
7431 case BFD_RELOC_X86_64_GOTPCREL
:
7432 case BFD_RELOC_386_PLT32
:
7433 case BFD_RELOC_386_GOT32
:
7434 case BFD_RELOC_386_GOTOFF
:
7435 case BFD_RELOC_386_GOTPC
:
7436 case BFD_RELOC_386_TLS_GD
:
7437 case BFD_RELOC_386_TLS_LDM
:
7438 case BFD_RELOC_386_TLS_LDO_32
:
7439 case BFD_RELOC_386_TLS_IE_32
:
7440 case BFD_RELOC_386_TLS_IE
:
7441 case BFD_RELOC_386_TLS_GOTIE
:
7442 case BFD_RELOC_386_TLS_LE_32
:
7443 case BFD_RELOC_386_TLS_LE
:
7444 case BFD_RELOC_386_TLS_GOTDESC
:
7445 case BFD_RELOC_386_TLS_DESC_CALL
:
7446 case BFD_RELOC_X86_64_TLSGD
:
7447 case BFD_RELOC_X86_64_TLSLD
:
7448 case BFD_RELOC_X86_64_DTPOFF32
:
7449 case BFD_RELOC_X86_64_DTPOFF64
:
7450 case BFD_RELOC_X86_64_GOTTPOFF
:
7451 case BFD_RELOC_X86_64_TPOFF32
:
7452 case BFD_RELOC_X86_64_TPOFF64
:
7453 case BFD_RELOC_X86_64_GOTOFF64
:
7454 case BFD_RELOC_X86_64_GOTPC32
:
7455 case BFD_RELOC_X86_64_GOT64
:
7456 case BFD_RELOC_X86_64_GOTPCREL64
:
7457 case BFD_RELOC_X86_64_GOTPC64
:
7458 case BFD_RELOC_X86_64_GOTPLT64
:
7459 case BFD_RELOC_X86_64_PLTOFF64
:
7460 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7461 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7463 case BFD_RELOC_VTABLE_ENTRY
:
7464 case BFD_RELOC_VTABLE_INHERIT
:
7466 case BFD_RELOC_32_SECREL
:
7468 code
= fixp
->fx_r_type
;
7470 case BFD_RELOC_X86_64_32S
:
7471 if (!fixp
->fx_pcrel
)
7473 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7474 code
= fixp
->fx_r_type
;
7480 switch (fixp
->fx_size
)
7483 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7484 _("can not do %d byte pc-relative relocation"),
7486 code
= BFD_RELOC_32_PCREL
;
7488 case 1: code
= BFD_RELOC_8_PCREL
; break;
7489 case 2: code
= BFD_RELOC_16_PCREL
; break;
7490 case 4: code
= BFD_RELOC_32_PCREL
; break;
7492 case 8: code
= BFD_RELOC_64_PCREL
; break;
7498 switch (fixp
->fx_size
)
7501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7502 _("can not do %d byte relocation"),
7504 code
= BFD_RELOC_32
;
7506 case 1: code
= BFD_RELOC_8
; break;
7507 case 2: code
= BFD_RELOC_16
; break;
7508 case 4: code
= BFD_RELOC_32
; break;
7510 case 8: code
= BFD_RELOC_64
; break;
7517 if ((code
== BFD_RELOC_32
7518 || code
== BFD_RELOC_32_PCREL
7519 || code
== BFD_RELOC_X86_64_32S
)
7521 && fixp
->fx_addsy
== GOT_symbol
)
7524 code
= BFD_RELOC_386_GOTPC
;
7526 code
= BFD_RELOC_X86_64_GOTPC32
;
7528 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7530 && fixp
->fx_addsy
== GOT_symbol
)
7532 code
= BFD_RELOC_X86_64_GOTPC64
;
7535 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7536 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7537 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7539 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7541 if (!use_rela_relocations
)
7543 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7544 vtable entry to be used in the relocation's section offset. */
7545 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7546 rel
->address
= fixp
->fx_offset
;
7550 /* Use the rela in 64bit mode. */
7553 if (!fixp
->fx_pcrel
)
7554 rel
->addend
= fixp
->fx_offset
;
7558 case BFD_RELOC_X86_64_PLT32
:
7559 case BFD_RELOC_X86_64_GOT32
:
7560 case BFD_RELOC_X86_64_GOTPCREL
:
7561 case BFD_RELOC_X86_64_TLSGD
:
7562 case BFD_RELOC_X86_64_TLSLD
:
7563 case BFD_RELOC_X86_64_GOTTPOFF
:
7564 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7565 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7566 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7569 rel
->addend
= (section
->vma
7571 + fixp
->fx_addnumber
7572 + md_pcrel_from (fixp
));
7577 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7578 if (rel
->howto
== NULL
)
7580 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7581 _("cannot represent relocation type %s"),
7582 bfd_get_reloc_code_name (code
));
7583 /* Set howto to a garbage value so that we can keep going. */
7584 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7585 assert (rel
->howto
!= NULL
);
7592 /* Parse operands using Intel syntax. This implements a recursive descent
7593 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7596 FIXME: We do not recognize the full operand grammar defined in the MASM
7597 documentation. In particular, all the structure/union and
7598 high-level macro operands are missing.
7600 Uppercase words are terminals, lower case words are non-terminals.
7601 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7602 bars '|' denote choices. Most grammar productions are implemented in
7603 functions called 'intel_<production>'.
7605 Initial production is 'expr'.
7611 binOp & | AND | \| | OR | ^ | XOR
7613 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7615 constant digits [[ radixOverride ]]
7617 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7655 => expr expr cmpOp e04
7658 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7659 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7661 hexdigit a | b | c | d | e | f
7662 | A | B | C | D | E | F
7668 mulOp * | / | % | MOD | << | SHL | >> | SHR
7672 register specialRegister
7676 segmentRegister CS | DS | ES | FS | GS | SS
7678 specialRegister CR0 | CR2 | CR3 | CR4
7679 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7680 | TR3 | TR4 | TR5 | TR6 | TR7
7682 We simplify the grammar in obvious places (e.g., register parsing is
7683 done by calling parse_register) and eliminate immediate left recursion
7684 to implement a recursive-descent parser.
7688 expr' cmpOp e04 expr'
7739 /* Parsing structure for the intel syntax parser. Used to implement the
7740 semantic actions for the operand grammar. */
7741 struct intel_parser_s
7743 char *op_string
; /* The string being parsed. */
7744 int got_a_float
; /* Whether the operand is a float. */
7745 int op_modifier
; /* Operand modifier. */
7746 int is_mem
; /* 1 if operand is memory reference. */
7747 int in_offset
; /* >=1 if parsing operand of offset. */
7748 int in_bracket
; /* >=1 if parsing operand in brackets. */
7749 const reg_entry
*reg
; /* Last register reference found. */
7750 char *disp
; /* Displacement string being built. */
7751 char *next_operand
; /* Resume point when splitting operands. */
7754 static struct intel_parser_s intel_parser
;
7756 /* Token structure for parsing intel syntax. */
7759 int code
; /* Token code. */
7760 const reg_entry
*reg
; /* Register entry for register tokens. */
7761 char *str
; /* String representation. */
7764 static struct intel_token cur_token
, prev_token
;
7766 /* Token codes for the intel parser. Since T_SHORT is already used
7767 by COFF, undefine it first to prevent a warning. */
7786 /* Prototypes for intel parser functions. */
7787 static int intel_match_token (int);
7788 static void intel_putback_token (void);
7789 static void intel_get_token (void);
7790 static int intel_expr (void);
7791 static int intel_e04 (void);
7792 static int intel_e05 (void);
7793 static int intel_e06 (void);
7794 static int intel_e09 (void);
7795 static int intel_e10 (void);
7796 static int intel_e11 (void);
7799 i386_intel_operand (char *operand_string
, int got_a_float
)
7804 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7805 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7809 /* Initialize token holders. */
7810 cur_token
.code
= prev_token
.code
= T_NIL
;
7811 cur_token
.reg
= prev_token
.reg
= NULL
;
7812 cur_token
.str
= prev_token
.str
= NULL
;
7814 /* Initialize parser structure. */
7815 intel_parser
.got_a_float
= got_a_float
;
7816 intel_parser
.op_modifier
= 0;
7817 intel_parser
.is_mem
= 0;
7818 intel_parser
.in_offset
= 0;
7819 intel_parser
.in_bracket
= 0;
7820 intel_parser
.reg
= NULL
;
7821 intel_parser
.disp
[0] = '\0';
7822 intel_parser
.next_operand
= NULL
;
7824 /* Read the first token and start the parser. */
7826 ret
= intel_expr ();
7831 if (cur_token
.code
!= T_NIL
)
7833 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7834 current_templates
->start
->name
, cur_token
.str
);
7837 /* If we found a memory reference, hand it over to i386_displacement
7838 to fill in the rest of the operand fields. */
7839 else if (intel_parser
.is_mem
)
7841 if ((i
.mem_operands
== 1
7842 && !current_templates
->start
->opcode_modifier
.isstring
)
7843 || i
.mem_operands
== 2)
7845 as_bad (_("too many memory references for '%s'"),
7846 current_templates
->start
->name
);
7851 char *s
= intel_parser
.disp
;
7854 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7855 /* See the comments in intel_bracket_expr. */
7856 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7858 /* Add the displacement expression. */
7860 ret
= i386_displacement (s
, s
+ strlen (s
));
7863 /* Swap base and index in 16-bit memory operands like
7864 [si+bx]. Since i386_index_check is also used in AT&T
7865 mode we have to do that here. */
7868 && i
.base_reg
->reg_type
.bitfield
.reg16
7869 && i
.index_reg
->reg_type
.bitfield
.reg16
7870 && i
.base_reg
->reg_num
>= 6
7871 && i
.index_reg
->reg_num
< 6)
7873 const reg_entry
*base
= i
.index_reg
;
7875 i
.index_reg
= i
.base_reg
;
7878 ret
= i386_index_check (operand_string
);
7883 /* Constant and OFFSET expressions are handled by i386_immediate. */
7884 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7885 || intel_parser
.reg
== NULL
)
7886 ret
= i386_immediate (intel_parser
.disp
);
7888 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7890 if (!ret
|| !intel_parser
.next_operand
)
7892 intel_parser
.op_string
= intel_parser
.next_operand
;
7893 this_operand
= i
.operands
++;
7897 free (intel_parser
.disp
);
7902 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7906 expr' cmpOp e04 expr'
7911 /* XXX Implement the comparison operators. */
7912 return intel_e04 ();
7929 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7930 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7932 if (cur_token
.code
== '+')
7934 else if (cur_token
.code
== '-')
7935 nregs
= NUM_ADDRESS_REGS
;
7939 strcat (intel_parser
.disp
, cur_token
.str
);
7940 intel_match_token (cur_token
.code
);
7951 int nregs
= ~NUM_ADDRESS_REGS
;
7958 if (cur_token
.code
== '&'
7959 || cur_token
.code
== '|'
7960 || cur_token
.code
== '^')
7964 str
[0] = cur_token
.code
;
7966 strcat (intel_parser
.disp
, str
);
7971 intel_match_token (cur_token
.code
);
7976 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7977 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
7988 int nregs
= ~NUM_ADDRESS_REGS
;
7995 if (cur_token
.code
== '*'
7996 || cur_token
.code
== '/'
7997 || cur_token
.code
== '%')
8001 str
[0] = cur_token
.code
;
8003 strcat (intel_parser
.disp
, str
);
8005 else if (cur_token
.code
== T_SHL
)
8006 strcat (intel_parser
.disp
, "<<");
8007 else if (cur_token
.code
== T_SHR
)
8008 strcat (intel_parser
.disp
, ">>");
8012 intel_match_token (cur_token
.code
);
8017 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8018 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8036 int nregs
= ~NUM_ADDRESS_REGS
;
8041 /* Don't consume constants here. */
8042 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8044 /* Need to look one token ahead - if the next token
8045 is a constant, the current token is its sign. */
8048 intel_match_token (cur_token
.code
);
8049 next_code
= cur_token
.code
;
8050 intel_putback_token ();
8051 if (next_code
== T_CONST
)
8055 /* e09 OFFSET e09 */
8056 if (cur_token
.code
== T_OFFSET
)
8059 ++intel_parser
.in_offset
;
8063 else if (cur_token
.code
== T_SHORT
)
8064 intel_parser
.op_modifier
|= 1 << T_SHORT
;
8067 else if (cur_token
.code
== '+')
8068 strcat (intel_parser
.disp
, "+");
8073 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
8079 str
[0] = cur_token
.code
;
8081 strcat (intel_parser
.disp
, str
);
8088 intel_match_token (cur_token
.code
);
8096 /* e09' PTR e10 e09' */
8097 if (cur_token
.code
== T_PTR
)
8101 if (prev_token
.code
== T_BYTE
)
8102 suffix
= BYTE_MNEM_SUFFIX
;
8104 else if (prev_token
.code
== T_WORD
)
8106 if (current_templates
->start
->name
[0] == 'l'
8107 && current_templates
->start
->name
[2] == 's'
8108 && current_templates
->start
->name
[3] == 0)
8109 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8110 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
8111 suffix
= SHORT_MNEM_SUFFIX
;
8113 suffix
= WORD_MNEM_SUFFIX
;
8116 else if (prev_token
.code
== T_DWORD
)
8118 if (current_templates
->start
->name
[0] == 'l'
8119 && current_templates
->start
->name
[2] == 's'
8120 && current_templates
->start
->name
[3] == 0)
8121 suffix
= WORD_MNEM_SUFFIX
;
8122 else if (flag_code
== CODE_16BIT
8123 && (current_templates
->start
->opcode_modifier
.jump
8124 || current_templates
->start
->opcode_modifier
.jumpdword
))
8125 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8126 else if (intel_parser
.got_a_float
== 1) /* "f..." */
8127 suffix
= SHORT_MNEM_SUFFIX
;
8129 suffix
= LONG_MNEM_SUFFIX
;
8132 else if (prev_token
.code
== T_FWORD
)
8134 if (current_templates
->start
->name
[0] == 'l'
8135 && current_templates
->start
->name
[2] == 's'
8136 && current_templates
->start
->name
[3] == 0)
8137 suffix
= LONG_MNEM_SUFFIX
;
8138 else if (!intel_parser
.got_a_float
)
8140 if (flag_code
== CODE_16BIT
)
8141 add_prefix (DATA_PREFIX_OPCODE
);
8142 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8145 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8148 else if (prev_token
.code
== T_QWORD
)
8150 if (intel_parser
.got_a_float
== 1) /* "f..." */
8151 suffix
= LONG_MNEM_SUFFIX
;
8153 suffix
= QWORD_MNEM_SUFFIX
;
8156 else if (prev_token
.code
== T_TBYTE
)
8158 if (intel_parser
.got_a_float
== 1)
8159 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8161 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8164 else if (prev_token
.code
== T_XMMWORD
)
8166 /* XXX ignored for now, but accepted since gcc uses it */
8172 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
8176 /* Operands for jump/call using 'ptr' notation denote absolute
8178 if (current_templates
->start
->opcode_modifier
.jump
8179 || current_templates
->start
->opcode_modifier
.jumpdword
)
8180 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8182 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
8186 else if (i
.suffix
!= suffix
)
8188 as_bad (_("Conflicting operand modifiers"));
8194 /* e09' : e10 e09' */
8195 else if (cur_token
.code
== ':')
8197 if (prev_token
.code
!= T_REG
)
8199 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8200 segment/group identifier (which we don't have), using comma
8201 as the operand separator there is even less consistent, since
8202 there all branches only have a single operand. */
8203 if (this_operand
!= 0
8204 || intel_parser
.in_offset
8205 || intel_parser
.in_bracket
8206 || (!current_templates
->start
->opcode_modifier
.jump
8207 && !current_templates
->start
->opcode_modifier
.jumpdword
8208 && !current_templates
->start
->opcode_modifier
.jumpintersegment
8209 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
8210 return intel_match_token (T_NIL
);
8211 /* Remember the start of the 2nd operand and terminate 1st
8213 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8214 another expression), but it gets at least the simplest case
8215 (a plain number or symbol on the left side) right. */
8216 intel_parser
.next_operand
= intel_parser
.op_string
;
8217 *--intel_parser
.op_string
= '\0';
8218 return intel_match_token (':');
8226 intel_match_token (cur_token
.code
);
8232 --intel_parser
.in_offset
;
8235 if (NUM_ADDRESS_REGS
> nregs
)
8237 as_bad (_("Invalid operand to `OFFSET'"));
8240 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
8243 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8244 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
8249 intel_bracket_expr (void)
8251 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
8252 const char *start
= intel_parser
.op_string
;
8255 if (i
.op
[this_operand
].regs
)
8256 return intel_match_token (T_NIL
);
8258 intel_match_token ('[');
8260 /* Mark as a memory operand only if it's not already known to be an
8261 offset expression. If it's an offset expression, we need to keep
8263 if (!intel_parser
.in_offset
)
8265 ++intel_parser
.in_bracket
;
8267 /* Operands for jump/call inside brackets denote absolute addresses. */
8268 if (current_templates
->start
->opcode_modifier
.jump
8269 || current_templates
->start
->opcode_modifier
.jumpdword
)
8270 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8272 /* Unfortunately gas always diverged from MASM in a respect that can't
8273 be easily fixed without risking to break code sequences likely to be
8274 encountered (the testsuite even check for this): MASM doesn't consider
8275 an expression inside brackets unconditionally as a memory reference.
8276 When that is e.g. a constant, an offset expression, or the sum of the
8277 two, this is still taken as a constant load. gas, however, always
8278 treated these as memory references. As a compromise, we'll try to make
8279 offset expressions inside brackets work the MASM way (since that's
8280 less likely to be found in real world code), but make constants alone
8281 continue to work the traditional gas way. In either case, issue a
8283 intel_parser
.op_modifier
&= ~was_offset
;
8286 strcat (intel_parser
.disp
, "[");
8288 /* Add a '+' to the displacement string if necessary. */
8289 if (*intel_parser
.disp
!= '\0'
8290 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
8291 strcat (intel_parser
.disp
, "+");
8294 && (len
= intel_parser
.op_string
- start
- 1,
8295 intel_match_token (']')))
8297 /* Preserve brackets when the operand is an offset expression. */
8298 if (intel_parser
.in_offset
)
8299 strcat (intel_parser
.disp
, "]");
8302 --intel_parser
.in_bracket
;
8303 if (i
.base_reg
|| i
.index_reg
)
8304 intel_parser
.is_mem
= 1;
8305 if (!intel_parser
.is_mem
)
8307 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8308 /* Defer the warning until all of the operand was parsed. */
8309 intel_parser
.is_mem
= -1;
8310 else if (!quiet_warnings
)
8311 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8312 len
, start
, len
, start
);
8315 intel_parser
.op_modifier
|= was_offset
;
8332 while (cur_token
.code
== '[')
8334 if (!intel_bracket_expr ())
8359 switch (cur_token
.code
)
8363 intel_match_token ('(');
8364 strcat (intel_parser
.disp
, "(");
8366 if (intel_expr () && intel_match_token (')'))
8368 strcat (intel_parser
.disp
, ")");
8375 return intel_bracket_expr ();
8380 strcat (intel_parser
.disp
, cur_token
.str
);
8381 intel_match_token (cur_token
.code
);
8383 /* Mark as a memory operand only if it's not already known to be an
8384 offset expression. */
8385 if (!intel_parser
.in_offset
)
8386 intel_parser
.is_mem
= 1;
8393 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
8395 intel_match_token (T_REG
);
8397 /* Check for segment change. */
8398 if (cur_token
.code
== ':')
8400 if (!reg
->reg_type
.bitfield
.sreg2
8401 && !reg
->reg_type
.bitfield
.sreg3
)
8403 as_bad (_("`%s' is not a valid segment register"),
8407 else if (i
.seg
[i
.mem_operands
])
8408 as_warn (_("Extra segment override ignored"));
8411 if (!intel_parser
.in_offset
)
8412 intel_parser
.is_mem
= 1;
8413 switch (reg
->reg_num
)
8416 i
.seg
[i
.mem_operands
] = &es
;
8419 i
.seg
[i
.mem_operands
] = &cs
;
8422 i
.seg
[i
.mem_operands
] = &ss
;
8425 i
.seg
[i
.mem_operands
] = &ds
;
8428 i
.seg
[i
.mem_operands
] = &fs
;
8431 i
.seg
[i
.mem_operands
] = &gs
;
8437 /* Not a segment register. Check for register scaling. */
8438 else if (cur_token
.code
== '*')
8440 if (!intel_parser
.in_bracket
)
8442 as_bad (_("Register scaling only allowed in memory operands"));
8446 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8447 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8448 else if (i
.index_reg
)
8449 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8451 /* What follows must be a valid scale. */
8452 intel_match_token ('*');
8454 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8456 /* Set the scale after setting the register (otherwise,
8457 i386_scale will complain) */
8458 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8460 char *str
, sign
= cur_token
.code
;
8461 intel_match_token (cur_token
.code
);
8462 if (cur_token
.code
!= T_CONST
)
8464 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8468 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8469 strcpy (str
+ 1, cur_token
.str
);
8471 if (!i386_scale (str
))
8475 else if (!i386_scale (cur_token
.str
))
8477 intel_match_token (cur_token
.code
);
8480 /* No scaling. If this is a memory operand, the register is either a
8481 base register (first occurrence) or an index register (second
8483 else if (intel_parser
.in_bracket
)
8488 else if (!i
.index_reg
)
8492 as_bad (_("Too many register references in memory operand"));
8496 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8499 /* It's neither base nor index. */
8500 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8502 i386_operand_type temp
= reg
->reg_type
;
8503 temp
.bitfield
.baseindex
= 0;
8504 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8506 i
.op
[this_operand
].regs
= reg
;
8511 as_bad (_("Invalid use of register"));
8515 /* Since registers are not part of the displacement string (except
8516 when we're parsing offset operands), we may need to remove any
8517 preceding '+' from the displacement string. */
8518 if (*intel_parser
.disp
!= '\0'
8519 && !intel_parser
.in_offset
)
8521 char *s
= intel_parser
.disp
;
8522 s
+= strlen (s
) - 1;
8545 intel_match_token (cur_token
.code
);
8547 if (cur_token
.code
== T_PTR
)
8550 /* It must have been an identifier. */
8551 intel_putback_token ();
8552 cur_token
.code
= T_ID
;
8558 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8562 /* The identifier represents a memory reference only if it's not
8563 preceded by an offset modifier and if it's not an equate. */
8564 symbolP
= symbol_find(cur_token
.str
);
8565 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8566 intel_parser
.is_mem
= 1;
8574 char *save_str
, sign
= 0;
8576 /* Allow constants that start with `+' or `-'. */
8577 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8579 sign
= cur_token
.code
;
8580 intel_match_token (cur_token
.code
);
8581 if (cur_token
.code
!= T_CONST
)
8583 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8589 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8590 strcpy (save_str
+ !!sign
, cur_token
.str
);
8594 /* Get the next token to check for register scaling. */
8595 intel_match_token (cur_token
.code
);
8597 /* Check if this constant is a scaling factor for an
8599 if (cur_token
.code
== '*')
8601 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8603 const reg_entry
*reg
= cur_token
.reg
;
8605 if (!intel_parser
.in_bracket
)
8607 as_bad (_("Register scaling only allowed "
8608 "in memory operands"));
8612 /* Disallow things like [1*si].
8613 sp and esp are invalid as index. */
8614 if (reg
->reg_type
.bitfield
.reg16
)
8615 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8616 else if (i
.index_reg
)
8617 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8619 /* The constant is followed by `* reg', so it must be
8622 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8624 /* Set the scale after setting the register (otherwise,
8625 i386_scale will complain) */
8626 if (!i386_scale (save_str
))
8628 intel_match_token (T_REG
);
8630 /* Since registers are not part of the displacement
8631 string, we may need to remove any preceding '+' from
8632 the displacement string. */
8633 if (*intel_parser
.disp
!= '\0')
8635 char *s
= intel_parser
.disp
;
8636 s
+= strlen (s
) - 1;
8646 /* The constant was not used for register scaling. Since we have
8647 already consumed the token following `*' we now need to put it
8648 back in the stream. */
8649 intel_putback_token ();
8652 /* Add the constant to the displacement string. */
8653 strcat (intel_parser
.disp
, save_str
);
8660 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8664 /* Match the given token against cur_token. If they match, read the next
8665 token from the operand string. */
8667 intel_match_token (int code
)
8669 if (cur_token
.code
== code
)
8676 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8681 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8683 intel_get_token (void)
8686 const reg_entry
*reg
;
8687 struct intel_token new_token
;
8689 new_token
.code
= T_NIL
;
8690 new_token
.reg
= NULL
;
8691 new_token
.str
= NULL
;
8693 /* Free the memory allocated to the previous token and move
8694 cur_token to prev_token. */
8696 free (prev_token
.str
);
8698 prev_token
= cur_token
;
8700 /* Skip whitespace. */
8701 while (is_space_char (*intel_parser
.op_string
))
8702 intel_parser
.op_string
++;
8704 /* Return an empty token if we find nothing else on the line. */
8705 if (*intel_parser
.op_string
== '\0')
8707 cur_token
= new_token
;
8711 /* The new token cannot be larger than the remainder of the operand
8713 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8714 new_token
.str
[0] = '\0';
8716 if (strchr ("0123456789", *intel_parser
.op_string
))
8718 char *p
= new_token
.str
;
8719 char *q
= intel_parser
.op_string
;
8720 new_token
.code
= T_CONST
;
8722 /* Allow any kind of identifier char to encompass floating point and
8723 hexadecimal numbers. */
8724 while (is_identifier_char (*q
))
8728 /* Recognize special symbol names [0-9][bf]. */
8729 if (strlen (intel_parser
.op_string
) == 2
8730 && (intel_parser
.op_string
[1] == 'b'
8731 || intel_parser
.op_string
[1] == 'f'))
8732 new_token
.code
= T_ID
;
8735 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8737 size_t len
= end_op
- intel_parser
.op_string
;
8739 new_token
.code
= T_REG
;
8740 new_token
.reg
= reg
;
8742 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8743 new_token
.str
[len
] = '\0';
8746 else if (is_identifier_char (*intel_parser
.op_string
))
8748 char *p
= new_token
.str
;
8749 char *q
= intel_parser
.op_string
;
8751 /* A '.' or '$' followed by an identifier char is an identifier.
8752 Otherwise, it's operator '.' followed by an expression. */
8753 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8755 new_token
.code
= '.';
8756 new_token
.str
[0] = '.';
8757 new_token
.str
[1] = '\0';
8761 while (is_identifier_char (*q
) || *q
== '@')
8765 if (strcasecmp (new_token
.str
, "NOT") == 0)
8766 new_token
.code
= '~';
8768 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8769 new_token
.code
= '%';
8771 else if (strcasecmp (new_token
.str
, "AND") == 0)
8772 new_token
.code
= '&';
8774 else if (strcasecmp (new_token
.str
, "OR") == 0)
8775 new_token
.code
= '|';
8777 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8778 new_token
.code
= '^';
8780 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8781 new_token
.code
= T_SHL
;
8783 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8784 new_token
.code
= T_SHR
;
8786 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8787 new_token
.code
= T_BYTE
;
8789 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8790 new_token
.code
= T_WORD
;
8792 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8793 new_token
.code
= T_DWORD
;
8795 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8796 new_token
.code
= T_FWORD
;
8798 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8799 new_token
.code
= T_QWORD
;
8801 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8802 /* XXX remove (gcc still uses it) */
8803 || strcasecmp (new_token
.str
, "XWORD") == 0)
8804 new_token
.code
= T_TBYTE
;
8806 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8807 || strcasecmp (new_token
.str
, "OWORD") == 0)
8808 new_token
.code
= T_XMMWORD
;
8810 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8811 new_token
.code
= T_PTR
;
8813 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8814 new_token
.code
= T_SHORT
;
8816 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8818 new_token
.code
= T_OFFSET
;
8820 /* ??? This is not mentioned in the MASM grammar but gcc
8821 makes use of it with -mintel-syntax. OFFSET may be
8822 followed by FLAT: */
8823 if (strncasecmp (q
, " FLAT:", 6) == 0)
8824 strcat (new_token
.str
, " FLAT:");
8827 /* ??? This is not mentioned in the MASM grammar. */
8828 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8830 new_token
.code
= T_OFFSET
;
8832 strcat (new_token
.str
, ":");
8834 as_bad (_("`:' expected"));
8838 new_token
.code
= T_ID
;
8842 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8844 new_token
.code
= *intel_parser
.op_string
;
8845 new_token
.str
[0] = *intel_parser
.op_string
;
8846 new_token
.str
[1] = '\0';
8849 else if (strchr ("<>", *intel_parser
.op_string
)
8850 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8852 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8853 new_token
.str
[0] = *intel_parser
.op_string
;
8854 new_token
.str
[1] = *intel_parser
.op_string
;
8855 new_token
.str
[2] = '\0';
8859 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8861 intel_parser
.op_string
+= strlen (new_token
.str
);
8862 cur_token
= new_token
;
8865 /* Put cur_token back into the token stream and make cur_token point to
8868 intel_putback_token (void)
8870 if (cur_token
.code
!= T_NIL
)
8872 intel_parser
.op_string
-= strlen (cur_token
.str
);
8873 free (cur_token
.str
);
8875 cur_token
= prev_token
;
8877 /* Forget prev_token. */
8878 prev_token
.code
= T_NIL
;
8879 prev_token
.reg
= NULL
;
8880 prev_token
.str
= NULL
;
8884 tc_x86_regname_to_dw2regnum (char *regname
)
8886 unsigned int regnum
;
8887 unsigned int regnames_count
;
8888 static const char *const regnames_32
[] =
8890 "eax", "ecx", "edx", "ebx",
8891 "esp", "ebp", "esi", "edi",
8892 "eip", "eflags", NULL
,
8893 "st0", "st1", "st2", "st3",
8894 "st4", "st5", "st6", "st7",
8896 "xmm0", "xmm1", "xmm2", "xmm3",
8897 "xmm4", "xmm5", "xmm6", "xmm7",
8898 "mm0", "mm1", "mm2", "mm3",
8899 "mm4", "mm5", "mm6", "mm7",
8900 "fcw", "fsw", "mxcsr",
8901 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8904 static const char *const regnames_64
[] =
8906 "rax", "rdx", "rcx", "rbx",
8907 "rsi", "rdi", "rbp", "rsp",
8908 "r8", "r9", "r10", "r11",
8909 "r12", "r13", "r14", "r15",
8911 "xmm0", "xmm1", "xmm2", "xmm3",
8912 "xmm4", "xmm5", "xmm6", "xmm7",
8913 "xmm8", "xmm9", "xmm10", "xmm11",
8914 "xmm12", "xmm13", "xmm14", "xmm15",
8915 "st0", "st1", "st2", "st3",
8916 "st4", "st5", "st6", "st7",
8917 "mm0", "mm1", "mm2", "mm3",
8918 "mm4", "mm5", "mm6", "mm7",
8920 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8921 "fs.base", "gs.base", NULL
, NULL
,
8923 "mxcsr", "fcw", "fsw"
8925 const char *const *regnames
;
8927 if (flag_code
== CODE_64BIT
)
8929 regnames
= regnames_64
;
8930 regnames_count
= ARRAY_SIZE (regnames_64
);
8934 regnames
= regnames_32
;
8935 regnames_count
= ARRAY_SIZE (regnames_32
);
8938 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
8939 if (regnames
[regnum
] != NULL
8940 && strcmp (regname
, regnames
[regnum
]) == 0)
8947 tc_x86_frame_initial_instructions (void)
8949 static unsigned int sp_regno
;
8952 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
8955 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
8956 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8960 i386_elf_section_type (const char *str
, size_t len
)
8962 if (flag_code
== CODE_64BIT
8963 && len
== sizeof ("unwind") - 1
8964 && strncmp (str
, "unwind", 6) == 0)
8965 return SHT_X86_64_UNWIND
;
8972 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8976 expr
.X_op
= O_secrel
;
8977 expr
.X_add_symbol
= symbol
;
8978 expr
.X_add_number
= 0;
8979 emit_expr (&expr
, size
);
8983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8984 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8987 x86_64_section_letter (int letter
, char **ptr_msg
)
8989 if (flag_code
== CODE_64BIT
)
8992 return SHF_X86_64_LARGE
;
8994 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8997 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9002 x86_64_section_word (char *str
, size_t len
)
9004 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9005 return SHF_X86_64_LARGE
;
9011 handle_large_common (int small ATTRIBUTE_UNUSED
)
9013 if (flag_code
!= CODE_64BIT
)
9015 s_comm_internal (0, elf_common_parse
);
9016 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9020 static segT lbss_section
;
9021 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9022 asection
*saved_bss_section
= bss_section
;
9024 if (lbss_section
== NULL
)
9026 flagword applicable
;
9028 subsegT subseg
= now_subseg
;
9030 /* The .lbss section is for local .largecomm symbols. */
9031 lbss_section
= subseg_new (".lbss", 0);
9032 applicable
= bfd_applicable_section_flags (stdoutput
);
9033 bfd_set_section_flags (stdoutput
, lbss_section
,
9034 applicable
& SEC_ALLOC
);
9035 seg_info (lbss_section
)->bss
= 1;
9037 subseg_set (seg
, subseg
);
9040 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9041 bss_section
= lbss_section
;
9043 s_comm_internal (0, elf_common_parse
);
9045 elf_com_section_ptr
= saved_com_section_ptr
;
9046 bss_section
= saved_bss_section
;
9049 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */