1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
847 CPU_BTVER1_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
849 CPU_BTVER2_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
867 CPU_SSSE3_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
869 CPU_SSE4_1_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_2_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
879 CPU_AVX512F_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512CD_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512ER_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512PF_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512DQ_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512BW_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512VL_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
895 CPU_VMFUNC_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
899 CPU_XSAVE_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVEOPT_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEC_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVES_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
909 CPU_PCLMUL_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 1 },
912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
913 CPU_FSGSBASE_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
915 CPU_RDRND_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
929 CPU_MOVBE_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
935 CPU_LZCNT_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
941 CPU_INVPCID_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
943 CPU_CLFLUSH_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
947 CPU_SYSCALL_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
949 CPU_RDTSCP_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
951 CPU_3DNOW_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOWA_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
955 CPU_PADLOCK_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
961 CPU_SSE4A_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
971 CPU_RDSEED_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
973 CPU_PRFCHW_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
981 CPU_CLFLUSHOPT_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
983 CPU_PREFETCHWT1_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
989 CPU_AVX512IFMA_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512VBMI_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512_4FMAPS_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4VNNIW_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VBMI2_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VNNI_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_BITALG_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1005 CPU_CLZERO_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1007 CPU_MWAITX_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1009 CPU_OSPKE_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1011 CPU_RDPID_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1013 CPU_PTWRITE_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1017 CPU_SHSTK_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1019 CPU_GFNI_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1021 CPU_VAES_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1023 CPU_VPCLMULQDQ_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1025 CPU_WBNOINVD_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1027 CPU_PCONFIG_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1029 CPU_WAITPKG_FLAGS
, 0 },
1032 static const noarch_entry cpu_noarch
[] =
1034 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1035 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1036 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1037 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1038 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1039 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1040 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1041 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1042 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1043 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1044 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1045 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1046 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1047 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1048 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1049 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1050 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1051 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1052 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1053 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1063 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1064 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1068 /* Like s_lcomm_internal in gas/read.c but the alignment string
1069 is allowed to be optional. */
1072 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1079 && *input_line_pointer
== ',')
1081 align
= parse_align (needs_align
- 1);
1083 if (align
== (addressT
) -1)
1098 bss_alloc (symbolP
, size
, align
);
1103 pe_lcomm (int needs_align
)
1105 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1109 const pseudo_typeS md_pseudo_table
[] =
1111 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1112 {"align", s_align_bytes
, 0},
1114 {"align", s_align_ptwo
, 0},
1116 {"arch", set_cpu_arch
, 0},
1120 {"lcomm", pe_lcomm
, 1},
1122 {"ffloat", float_cons
, 'f'},
1123 {"dfloat", float_cons
, 'd'},
1124 {"tfloat", float_cons
, 'x'},
1126 {"slong", signed_cons
, 4},
1127 {"noopt", s_ignore
, 0},
1128 {"optim", s_ignore
, 0},
1129 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1130 {"code16", set_code_flag
, CODE_16BIT
},
1131 {"code32", set_code_flag
, CODE_32BIT
},
1133 {"code64", set_code_flag
, CODE_64BIT
},
1135 {"intel_syntax", set_intel_syntax
, 1},
1136 {"att_syntax", set_intel_syntax
, 0},
1137 {"intel_mnemonic", set_intel_mnemonic
, 1},
1138 {"att_mnemonic", set_intel_mnemonic
, 0},
1139 {"allow_index_reg", set_allow_index_reg
, 1},
1140 {"disallow_index_reg", set_allow_index_reg
, 0},
1141 {"sse_check", set_check
, 0},
1142 {"operand_check", set_check
, 1},
1143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1144 {"largecomm", handle_large_common
, 0},
1146 {"file", dwarf2_directive_file
, 0},
1147 {"loc", dwarf2_directive_loc
, 0},
1148 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1151 {"secrel32", pe_directive_secrel
, 0},
1156 /* For interface with expression (). */
1157 extern char *input_line_pointer
;
1159 /* Hash table for instruction mnemonic lookup. */
1160 static struct hash_control
*op_hash
;
1162 /* Hash table for register lookup. */
1163 static struct hash_control
*reg_hash
;
1165 /* Various efficient no-op patterns for aligning code labels.
1166 Note: Don't try to assemble the instructions in the comments.
1167 0L and 0w are not legal. */
1168 static const unsigned char f32_1
[] =
1170 static const unsigned char f32_2
[] =
1171 {0x66,0x90}; /* xchg %ax,%ax */
1172 static const unsigned char f32_3
[] =
1173 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1174 static const unsigned char f32_4
[] =
1175 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1176 static const unsigned char f32_6
[] =
1177 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1178 static const unsigned char f32_7
[] =
1179 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1180 static const unsigned char f16_3
[] =
1181 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1182 static const unsigned char f16_4
[] =
1183 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1184 static const unsigned char jump_disp8
[] =
1185 {0xeb}; /* jmp disp8 */
1186 static const unsigned char jump32_disp32
[] =
1187 {0xe9}; /* jmp disp32 */
1188 static const unsigned char jump16_disp32
[] =
1189 {0x66,0xe9}; /* jmp disp32 */
1190 /* 32-bit NOPs patterns. */
1191 static const unsigned char *const f32_patt
[] = {
1192 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1194 /* 16-bit NOPs patterns. */
1195 static const unsigned char *const f16_patt
[] = {
1196 f32_1
, f32_2
, f16_3
, f16_4
1198 /* nopl (%[re]ax) */
1199 static const unsigned char alt_3
[] =
1201 /* nopl 0(%[re]ax) */
1202 static const unsigned char alt_4
[] =
1203 {0x0f,0x1f,0x40,0x00};
1204 /* nopl 0(%[re]ax,%[re]ax,1) */
1205 static const unsigned char alt_5
[] =
1206 {0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopw 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_6
[] =
1209 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopl 0L(%[re]ax) */
1211 static const unsigned char alt_7
[] =
1212 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1213 /* nopl 0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_8
[] =
1215 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_9
[] =
1218 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_10
[] =
1221 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* data16 nopw %cs:0L(%eax,%eax,1) */
1223 static const unsigned char alt_11
[] =
1224 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* 32-bit and 64-bit NOPs patterns. */
1226 static const unsigned char *const alt_patt
[] = {
1227 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1228 alt_9
, alt_10
, alt_11
1231 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1232 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1235 i386_output_nops (char *where
, const unsigned char *const *patt
,
1236 int count
, int max_single_nop_size
)
1239 /* Place the longer NOP first. */
1242 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1244 /* Use the smaller one if the requsted one isn't available. */
1247 max_single_nop_size
--;
1248 nops
= patt
[max_single_nop_size
- 1];
1251 last
= count
% max_single_nop_size
;
1254 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1255 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1259 nops
= patt
[last
- 1];
1262 /* Use the smaller one plus one-byte NOP if the needed one
1265 nops
= patt
[last
- 1];
1266 memcpy (where
+ offset
, nops
, last
);
1267 where
[offset
+ last
] = *patt
[0];
1270 memcpy (where
+ offset
, nops
, last
);
1275 fits_in_imm7 (offsetT num
)
1277 return (num
& 0x7f) == num
;
1281 fits_in_imm31 (offsetT num
)
1283 return (num
& 0x7fffffff) == num
;
1286 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1287 single NOP instruction LIMIT. */
1290 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1292 const unsigned char *const *patt
= NULL
;
1293 int max_single_nop_size
;
1294 /* Maximum number of NOPs before switching to jump over NOPs. */
1295 int max_number_of_nops
;
1297 switch (fragP
->fr_type
)
1306 /* We need to decide which NOP sequence to use for 32bit and
1307 64bit. When -mtune= is used:
1309 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1310 PROCESSOR_GENERIC32, f32_patt will be used.
1311 2. For the rest, alt_patt will be used.
1313 When -mtune= isn't used, alt_patt will be used if
1314 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1317 When -march= or .arch is used, we can't use anything beyond
1318 cpu_arch_isa_flags. */
1320 if (flag_code
== CODE_16BIT
)
1323 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1324 /* Limit number of NOPs to 2 in 16-bit mode. */
1325 max_number_of_nops
= 2;
1329 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1331 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1332 switch (cpu_arch_tune
)
1334 case PROCESSOR_UNKNOWN
:
1335 /* We use cpu_arch_isa_flags to check if we SHOULD
1336 optimize with nops. */
1337 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1342 case PROCESSOR_PENTIUM4
:
1343 case PROCESSOR_NOCONA
:
1344 case PROCESSOR_CORE
:
1345 case PROCESSOR_CORE2
:
1346 case PROCESSOR_COREI7
:
1347 case PROCESSOR_L1OM
:
1348 case PROCESSOR_K1OM
:
1349 case PROCESSOR_GENERIC64
:
1351 case PROCESSOR_ATHLON
:
1353 case PROCESSOR_AMDFAM10
:
1355 case PROCESSOR_ZNVER
:
1359 case PROCESSOR_I386
:
1360 case PROCESSOR_I486
:
1361 case PROCESSOR_PENTIUM
:
1362 case PROCESSOR_PENTIUMPRO
:
1363 case PROCESSOR_IAMCU
:
1364 case PROCESSOR_GENERIC32
:
1371 switch (fragP
->tc_frag_data
.tune
)
1373 case PROCESSOR_UNKNOWN
:
1374 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1375 PROCESSOR_UNKNOWN. */
1379 case PROCESSOR_I386
:
1380 case PROCESSOR_I486
:
1381 case PROCESSOR_PENTIUM
:
1382 case PROCESSOR_IAMCU
:
1384 case PROCESSOR_ATHLON
:
1386 case PROCESSOR_AMDFAM10
:
1388 case PROCESSOR_ZNVER
:
1390 case PROCESSOR_GENERIC32
:
1391 /* We use cpu_arch_isa_flags to check if we CAN optimize
1393 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1398 case PROCESSOR_PENTIUMPRO
:
1399 case PROCESSOR_PENTIUM4
:
1400 case PROCESSOR_NOCONA
:
1401 case PROCESSOR_CORE
:
1402 case PROCESSOR_CORE2
:
1403 case PROCESSOR_COREI7
:
1404 case PROCESSOR_L1OM
:
1405 case PROCESSOR_K1OM
:
1406 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1411 case PROCESSOR_GENERIC64
:
1417 if (patt
== f32_patt
)
1419 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1420 /* Limit number of NOPs to 2 for older processors. */
1421 max_number_of_nops
= 2;
1425 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1426 /* Limit number of NOPs to 7 for newer processors. */
1427 max_number_of_nops
= 7;
1432 limit
= max_single_nop_size
;
1434 if (fragP
->fr_type
== rs_fill_nop
)
1436 /* Output NOPs for .nop directive. */
1437 if (limit
> max_single_nop_size
)
1439 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1440 _("invalid single nop size: %d "
1441 "(expect within [0, %d])"),
1442 limit
, max_single_nop_size
);
1447 fragP
->fr_var
= count
;
1449 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1451 /* Generate jump over NOPs. */
1452 offsetT disp
= count
- 2;
1453 if (fits_in_imm7 (disp
))
1455 /* Use "jmp disp8" if possible. */
1457 where
[0] = jump_disp8
[0];
1463 unsigned int size_of_jump
;
1465 if (flag_code
== CODE_16BIT
)
1467 where
[0] = jump16_disp32
[0];
1468 where
[1] = jump16_disp32
[1];
1473 where
[0] = jump32_disp32
[0];
1477 count
-= size_of_jump
+ 4;
1478 if (!fits_in_imm31 (count
))
1480 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1481 _("jump over nop padding out of range"));
1485 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1486 where
+= size_of_jump
+ 4;
1490 /* Generate multiple NOPs. */
1491 i386_output_nops (where
, patt
, count
, limit
);
1495 operand_type_all_zero (const union i386_operand_type
*x
)
1497 switch (ARRAY_SIZE(x
->array
))
1508 return !x
->array
[0];
1515 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1517 switch (ARRAY_SIZE(x
->array
))
1535 operand_type_equal (const union i386_operand_type
*x
,
1536 const union i386_operand_type
*y
)
1538 switch (ARRAY_SIZE(x
->array
))
1541 if (x
->array
[2] != y
->array
[2])
1545 if (x
->array
[1] != y
->array
[1])
1549 return x
->array
[0] == y
->array
[0];
1557 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1559 switch (ARRAY_SIZE(x
->array
))
1574 return !x
->array
[0];
1581 cpu_flags_equal (const union i386_cpu_flags
*x
,
1582 const union i386_cpu_flags
*y
)
1584 switch (ARRAY_SIZE(x
->array
))
1587 if (x
->array
[3] != y
->array
[3])
1591 if (x
->array
[2] != y
->array
[2])
1595 if (x
->array
[1] != y
->array
[1])
1599 return x
->array
[0] == y
->array
[0];
1607 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1609 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1610 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1613 static INLINE i386_cpu_flags
1614 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1616 switch (ARRAY_SIZE (x
.array
))
1619 x
.array
[3] &= y
.array
[3];
1622 x
.array
[2] &= y
.array
[2];
1625 x
.array
[1] &= y
.array
[1];
1628 x
.array
[0] &= y
.array
[0];
1636 static INLINE i386_cpu_flags
1637 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1639 switch (ARRAY_SIZE (x
.array
))
1642 x
.array
[3] |= y
.array
[3];
1645 x
.array
[2] |= y
.array
[2];
1648 x
.array
[1] |= y
.array
[1];
1651 x
.array
[0] |= y
.array
[0];
1659 static INLINE i386_cpu_flags
1660 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1662 switch (ARRAY_SIZE (x
.array
))
1665 x
.array
[3] &= ~y
.array
[3];
1668 x
.array
[2] &= ~y
.array
[2];
1671 x
.array
[1] &= ~y
.array
[1];
1674 x
.array
[0] &= ~y
.array
[0];
1682 #define CPU_FLAGS_ARCH_MATCH 0x1
1683 #define CPU_FLAGS_64BIT_MATCH 0x2
1685 #define CPU_FLAGS_PERFECT_MATCH \
1686 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1688 /* Return CPU flags match bits. */
1691 cpu_flags_match (const insn_template
*t
)
1693 i386_cpu_flags x
= t
->cpu_flags
;
1694 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1696 x
.bitfield
.cpu64
= 0;
1697 x
.bitfield
.cpuno64
= 0;
1699 if (cpu_flags_all_zero (&x
))
1701 /* This instruction is available on all archs. */
1702 match
|= CPU_FLAGS_ARCH_MATCH
;
1706 /* This instruction is available only on some archs. */
1707 i386_cpu_flags cpu
= cpu_arch_flags
;
1709 /* AVX512VL is no standalone feature - match it and then strip it. */
1710 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1712 x
.bitfield
.cpuavx512vl
= 0;
1714 cpu
= cpu_flags_and (x
, cpu
);
1715 if (!cpu_flags_all_zero (&cpu
))
1717 if (x
.bitfield
.cpuavx
)
1719 /* We need to check a few extra flags with AVX. */
1720 if (cpu
.bitfield
.cpuavx
1721 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1722 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1723 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1724 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1725 match
|= CPU_FLAGS_ARCH_MATCH
;
1727 else if (x
.bitfield
.cpuavx512f
)
1729 /* We need to check a few extra flags with AVX512F. */
1730 if (cpu
.bitfield
.cpuavx512f
1731 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1732 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1733 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1734 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 match
|= CPU_FLAGS_ARCH_MATCH
;
1743 static INLINE i386_operand_type
1744 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1746 switch (ARRAY_SIZE (x
.array
))
1749 x
.array
[2] &= y
.array
[2];
1752 x
.array
[1] &= y
.array
[1];
1755 x
.array
[0] &= y
.array
[0];
1763 static INLINE i386_operand_type
1764 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1766 switch (ARRAY_SIZE (x
.array
))
1769 x
.array
[2] &= ~y
.array
[2];
1772 x
.array
[1] &= ~y
.array
[1];
1775 x
.array
[0] &= ~y
.array
[0];
1783 static INLINE i386_operand_type
1784 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1786 switch (ARRAY_SIZE (x
.array
))
1789 x
.array
[2] |= y
.array
[2];
1792 x
.array
[1] |= y
.array
[1];
1795 x
.array
[0] |= y
.array
[0];
1803 static INLINE i386_operand_type
1804 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1806 switch (ARRAY_SIZE (x
.array
))
1809 x
.array
[2] ^= y
.array
[2];
1812 x
.array
[1] ^= y
.array
[1];
1815 x
.array
[0] ^= y
.array
[0];
1823 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1824 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1825 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1826 static const i386_operand_type inoutportreg
1827 = OPERAND_TYPE_INOUTPORTREG
;
1828 static const i386_operand_type reg16_inoutportreg
1829 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1830 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1831 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1832 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1833 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1834 static const i386_operand_type anydisp
1835 = OPERAND_TYPE_ANYDISP
;
1836 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1837 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1838 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1839 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1840 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1841 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1842 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1843 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1844 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1845 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1846 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1847 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1858 operand_type_check (i386_operand_type t
, enum operand_type c
)
1863 return t
.bitfield
.reg
;
1866 return (t
.bitfield
.imm8
1870 || t
.bitfield
.imm32s
1871 || t
.bitfield
.imm64
);
1874 return (t
.bitfield
.disp8
1875 || t
.bitfield
.disp16
1876 || t
.bitfield
.disp32
1877 || t
.bitfield
.disp32s
1878 || t
.bitfield
.disp64
);
1881 return (t
.bitfield
.disp8
1882 || t
.bitfield
.disp16
1883 || t
.bitfield
.disp32
1884 || t
.bitfield
.disp32s
1885 || t
.bitfield
.disp64
1886 || t
.bitfield
.baseindex
);
1895 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1896 operand J for instruction template T. */
1899 match_reg_size (const insn_template
*t
, unsigned int j
)
1901 return !((i
.types
[j
].bitfield
.byte
1902 && !t
->operand_types
[j
].bitfield
.byte
)
1903 || (i
.types
[j
].bitfield
.word
1904 && !t
->operand_types
[j
].bitfield
.word
)
1905 || (i
.types
[j
].bitfield
.dword
1906 && !t
->operand_types
[j
].bitfield
.dword
)
1907 || (i
.types
[j
].bitfield
.qword
1908 && !t
->operand_types
[j
].bitfield
.qword
)
1909 || (i
.types
[j
].bitfield
.tbyte
1910 && !t
->operand_types
[j
].bitfield
.tbyte
));
1913 /* Return 1 if there is no conflict in SIMD register on
1914 operand J for instruction template T. */
1917 match_simd_size (const insn_template
*t
, unsigned int j
)
1919 return !((i
.types
[j
].bitfield
.xmmword
1920 && !t
->operand_types
[j
].bitfield
.xmmword
)
1921 || (i
.types
[j
].bitfield
.ymmword
1922 && !t
->operand_types
[j
].bitfield
.ymmword
)
1923 || (i
.types
[j
].bitfield
.zmmword
1924 && !t
->operand_types
[j
].bitfield
.zmmword
));
1927 /* Return 1 if there is no conflict in any size on operand J for
1928 instruction template T. */
1931 match_mem_size (const insn_template
*t
, unsigned int j
)
1933 return (match_reg_size (t
, j
)
1934 && !((i
.types
[j
].bitfield
.unspecified
1936 && !t
->operand_types
[j
].bitfield
.unspecified
)
1937 || (i
.types
[j
].bitfield
.fword
1938 && !t
->operand_types
[j
].bitfield
.fword
)
1939 /* For scalar opcode templates to allow register and memory
1940 operands at the same time, some special casing is needed
1941 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1942 down-conversion vpmov*. */
1943 || ((t
->operand_types
[j
].bitfield
.regsimd
1944 && !t
->opcode_modifier
.broadcast
1945 && (t
->operand_types
[j
].bitfield
.byte
1946 || t
->operand_types
[j
].bitfield
.word
1947 || t
->operand_types
[j
].bitfield
.dword
1948 || t
->operand_types
[j
].bitfield
.qword
))
1949 ? (i
.types
[j
].bitfield
.xmmword
1950 || i
.types
[j
].bitfield
.ymmword
1951 || i
.types
[j
].bitfield
.zmmword
)
1952 : !match_simd_size(t
, j
))));
1955 /* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1959 operand_size_match (const insn_template
*t
)
1964 /* Don't check jump instructions. */
1965 if (t
->opcode_modifier
.jump
1966 || t
->opcode_modifier
.jumpbyte
1967 || t
->opcode_modifier
.jumpdword
1968 || t
->opcode_modifier
.jumpintersegment
)
1971 /* Check memory and accumulator operand size. */
1972 for (j
= 0; j
< i
.operands
; j
++)
1974 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1975 && t
->operand_types
[j
].bitfield
.anysize
)
1978 if (t
->operand_types
[j
].bitfield
.reg
1979 && !match_reg_size (t
, j
))
1985 if (t
->operand_types
[j
].bitfield
.regsimd
1986 && !match_simd_size (t
, j
))
1992 if (t
->operand_types
[j
].bitfield
.acc
1993 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
1999 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2008 else if (!t
->opcode_modifier
.d
)
2011 i
.error
= operand_size_mismatch
;
2015 /* Check reverse. */
2016 gas_assert (i
.operands
== 2);
2019 for (j
= 0; j
< 2; j
++)
2021 if ((t
->operand_types
[j
].bitfield
.reg
2022 || t
->operand_types
[j
].bitfield
.acc
)
2023 && !match_reg_size (t
, j
? 0 : 1))
2026 if (i
.types
[j
].bitfield
.mem
2027 && !match_mem_size (t
, j
? 0 : 1))
2035 operand_type_match (i386_operand_type overlap
,
2036 i386_operand_type given
)
2038 i386_operand_type temp
= overlap
;
2040 temp
.bitfield
.jumpabsolute
= 0;
2041 temp
.bitfield
.unspecified
= 0;
2042 temp
.bitfield
.byte
= 0;
2043 temp
.bitfield
.word
= 0;
2044 temp
.bitfield
.dword
= 0;
2045 temp
.bitfield
.fword
= 0;
2046 temp
.bitfield
.qword
= 0;
2047 temp
.bitfield
.tbyte
= 0;
2048 temp
.bitfield
.xmmword
= 0;
2049 temp
.bitfield
.ymmword
= 0;
2050 temp
.bitfield
.zmmword
= 0;
2051 if (operand_type_all_zero (&temp
))
2054 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2055 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2059 i
.error
= operand_type_mismatch
;
2063 /* If given types g0 and g1 are registers they must be of the same type
2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2069 operand_type_register_match (i386_operand_type g0
,
2070 i386_operand_type t0
,
2071 i386_operand_type g1
,
2072 i386_operand_type t1
)
2074 if (!g0
.bitfield
.reg
2075 && !g0
.bitfield
.regsimd
2076 && (!operand_type_check (g0
, anymem
)
2077 || g0
.bitfield
.unspecified
2078 || !t0
.bitfield
.regsimd
))
2081 if (!g1
.bitfield
.reg
2082 && !g1
.bitfield
.regsimd
2083 && (!operand_type_check (g1
, anymem
)
2084 || g1
.bitfield
.unspecified
2085 || !t1
.bitfield
.regsimd
))
2088 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2089 && g0
.bitfield
.word
== g1
.bitfield
.word
2090 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2091 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2092 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2093 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2094 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2097 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2098 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2099 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2100 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2101 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2102 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2103 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2106 i
.error
= register_type_mismatch
;
2111 static INLINE
unsigned int
2112 register_number (const reg_entry
*r
)
2114 unsigned int nr
= r
->reg_num
;
2116 if (r
->reg_flags
& RegRex
)
2119 if (r
->reg_flags
& RegVRex
)
2125 static INLINE
unsigned int
2126 mode_from_disp_size (i386_operand_type t
)
2128 if (t
.bitfield
.disp8
)
2130 else if (t
.bitfield
.disp16
2131 || t
.bitfield
.disp32
2132 || t
.bitfield
.disp32s
)
2139 fits_in_signed_byte (addressT num
)
2141 return num
+ 0x80 <= 0xff;
2145 fits_in_unsigned_byte (addressT num
)
2151 fits_in_unsigned_word (addressT num
)
2153 return num
<= 0xffff;
2157 fits_in_signed_word (addressT num
)
2159 return num
+ 0x8000 <= 0xffff;
2163 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2168 return num
+ 0x80000000 <= 0xffffffff;
2170 } /* fits_in_signed_long() */
2173 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2178 return num
<= 0xffffffff;
2180 } /* fits_in_unsigned_long() */
2183 fits_in_disp8 (offsetT num
)
2185 int shift
= i
.memshift
;
2191 mask
= (1 << shift
) - 1;
2193 /* Return 0 if NUM isn't properly aligned. */
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num
>> shift
);
2202 fits_in_imm4 (offsetT num
)
2204 return (num
& 0xf) == num
;
2207 static i386_operand_type
2208 smallest_imm_type (offsetT num
)
2210 i386_operand_type t
;
2212 operand_type_set (&t
, 0);
2213 t
.bitfield
.imm64
= 1;
2215 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2217 /* This code is disabled on the 486 because all the Imm1 forms
2218 in the opcode table are slower on the i486. They're the
2219 versions with the implicitly specified single-position
2220 displacement, which has another syntax if you really want to
2222 t
.bitfield
.imm1
= 1;
2223 t
.bitfield
.imm8
= 1;
2224 t
.bitfield
.imm8s
= 1;
2225 t
.bitfield
.imm16
= 1;
2226 t
.bitfield
.imm32
= 1;
2227 t
.bitfield
.imm32s
= 1;
2229 else if (fits_in_signed_byte (num
))
2231 t
.bitfield
.imm8
= 1;
2232 t
.bitfield
.imm8s
= 1;
2233 t
.bitfield
.imm16
= 1;
2234 t
.bitfield
.imm32
= 1;
2235 t
.bitfield
.imm32s
= 1;
2237 else if (fits_in_unsigned_byte (num
))
2239 t
.bitfield
.imm8
= 1;
2240 t
.bitfield
.imm16
= 1;
2241 t
.bitfield
.imm32
= 1;
2242 t
.bitfield
.imm32s
= 1;
2244 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2246 t
.bitfield
.imm16
= 1;
2247 t
.bitfield
.imm32
= 1;
2248 t
.bitfield
.imm32s
= 1;
2250 else if (fits_in_signed_long (num
))
2252 t
.bitfield
.imm32
= 1;
2253 t
.bitfield
.imm32s
= 1;
2255 else if (fits_in_unsigned_long (num
))
2256 t
.bitfield
.imm32
= 1;
2262 offset_in_range (offsetT val
, int size
)
2268 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2269 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2270 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2272 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2278 /* If BFD64, sign extend val for 32bit address mode. */
2279 if (flag_code
!= CODE_64BIT
2280 || i
.prefix
[ADDR_PREFIX
])
2281 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2282 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2285 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2287 char buf1
[40], buf2
[40];
2289 sprint_value (buf1
, val
);
2290 sprint_value (buf2
, val
& mask
);
2291 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2306 a. PREFIX_EXIST if attempting to add a prefix where one from the
2307 same class already exists.
2308 b. PREFIX_LOCK if lock prefix is added.
2309 c. PREFIX_REP if rep/repne prefix is added.
2310 d. PREFIX_DS if ds prefix is added.
2311 e. PREFIX_OTHER if other prefix is added.
2314 static enum PREFIX_GROUP
2315 add_prefix (unsigned int prefix
)
2317 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2320 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2321 && flag_code
== CODE_64BIT
)
2323 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2324 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2325 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2336 case DS_PREFIX_OPCODE
:
2339 case CS_PREFIX_OPCODE
:
2340 case ES_PREFIX_OPCODE
:
2341 case FS_PREFIX_OPCODE
:
2342 case GS_PREFIX_OPCODE
:
2343 case SS_PREFIX_OPCODE
:
2347 case REPNE_PREFIX_OPCODE
:
2348 case REPE_PREFIX_OPCODE
:
2353 case LOCK_PREFIX_OPCODE
:
2362 case ADDR_PREFIX_OPCODE
:
2366 case DATA_PREFIX_OPCODE
:
2370 if (i
.prefix
[q
] != 0)
2378 i
.prefix
[q
] |= prefix
;
2381 as_bad (_("same type of prefix used twice"));
2387 update_code_flag (int value
, int check
)
2389 PRINTF_LIKE ((*as_error
));
2391 flag_code
= (enum flag_code
) value
;
2392 if (flag_code
== CODE_64BIT
)
2394 cpu_arch_flags
.bitfield
.cpu64
= 1;
2395 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2399 cpu_arch_flags
.bitfield
.cpu64
= 0;
2400 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2402 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2405 as_error
= as_fatal
;
2408 (*as_error
) (_("64bit mode not supported on `%s'."),
2409 cpu_arch_name
? cpu_arch_name
: default_arch
);
2411 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2414 as_error
= as_fatal
;
2417 (*as_error
) (_("32bit mode not supported on `%s'."),
2418 cpu_arch_name
? cpu_arch_name
: default_arch
);
2420 stackop_size
= '\0';
2424 set_code_flag (int value
)
2426 update_code_flag (value
, 0);
2430 set_16bit_gcc_code_flag (int new_code_flag
)
2432 flag_code
= (enum flag_code
) new_code_flag
;
2433 if (flag_code
!= CODE_16BIT
)
2435 cpu_arch_flags
.bitfield
.cpu64
= 0;
2436 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2437 stackop_size
= LONG_MNEM_SUFFIX
;
2441 set_intel_syntax (int syntax_flag
)
2443 /* Find out if register prefixing is specified. */
2444 int ask_naked_reg
= 0;
2447 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2450 int e
= get_symbol_name (&string
);
2452 if (strcmp (string
, "prefix") == 0)
2454 else if (strcmp (string
, "noprefix") == 0)
2457 as_bad (_("bad argument to syntax directive."));
2458 (void) restore_line_pointer (e
);
2460 demand_empty_rest_of_line ();
2462 intel_syntax
= syntax_flag
;
2464 if (ask_naked_reg
== 0)
2465 allow_naked_reg
= (intel_syntax
2466 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2468 allow_naked_reg
= (ask_naked_reg
< 0);
2470 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2472 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2473 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2474 register_prefix
= allow_naked_reg
? "" : "%";
2478 set_intel_mnemonic (int mnemonic_flag
)
2480 intel_mnemonic
= mnemonic_flag
;
2484 set_allow_index_reg (int flag
)
2486 allow_index_reg
= flag
;
2490 set_check (int what
)
2492 enum check_kind
*kind
;
2497 kind
= &operand_check
;
2508 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2511 int e
= get_symbol_name (&string
);
2513 if (strcmp (string
, "none") == 0)
2515 else if (strcmp (string
, "warning") == 0)
2516 *kind
= check_warning
;
2517 else if (strcmp (string
, "error") == 0)
2518 *kind
= check_error
;
2520 as_bad (_("bad argument to %s_check directive."), str
);
2521 (void) restore_line_pointer (e
);
2524 as_bad (_("missing argument for %s_check directive"), str
);
2526 demand_empty_rest_of_line ();
2530 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2531 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2533 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2534 static const char *arch
;
2536 /* Intel LIOM is only supported on ELF. */
2542 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2543 use default_arch. */
2544 arch
= cpu_arch_name
;
2546 arch
= default_arch
;
2549 /* If we are targeting Intel MCU, we must enable it. */
2550 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2551 || new_flag
.bitfield
.cpuiamcu
)
2554 /* If we are targeting Intel L1OM, we must enable it. */
2555 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2556 || new_flag
.bitfield
.cpul1om
)
2559 /* If we are targeting Intel K1OM, we must enable it. */
2560 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2561 || new_flag
.bitfield
.cpuk1om
)
2564 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2569 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2573 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2576 int e
= get_symbol_name (&string
);
2578 i386_cpu_flags flags
;
2580 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2582 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2584 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2588 cpu_arch_name
= cpu_arch
[j
].name
;
2589 cpu_sub_arch_name
= NULL
;
2590 cpu_arch_flags
= cpu_arch
[j
].flags
;
2591 if (flag_code
== CODE_64BIT
)
2593 cpu_arch_flags
.bitfield
.cpu64
= 1;
2594 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2598 cpu_arch_flags
.bitfield
.cpu64
= 0;
2599 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2601 cpu_arch_isa
= cpu_arch
[j
].type
;
2602 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2603 if (!cpu_arch_tune_set
)
2605 cpu_arch_tune
= cpu_arch_isa
;
2606 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2611 flags
= cpu_flags_or (cpu_arch_flags
,
2614 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2616 if (cpu_sub_arch_name
)
2618 char *name
= cpu_sub_arch_name
;
2619 cpu_sub_arch_name
= concat (name
,
2621 (const char *) NULL
);
2625 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2626 cpu_arch_flags
= flags
;
2627 cpu_arch_isa_flags
= flags
;
2631 = cpu_flags_or (cpu_arch_isa_flags
,
2633 (void) restore_line_pointer (e
);
2634 demand_empty_rest_of_line ();
2639 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2641 /* Disable an ISA extension. */
2642 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2643 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2645 flags
= cpu_flags_and_not (cpu_arch_flags
,
2646 cpu_noarch
[j
].flags
);
2647 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2649 if (cpu_sub_arch_name
)
2651 char *name
= cpu_sub_arch_name
;
2652 cpu_sub_arch_name
= concat (name
, string
,
2653 (const char *) NULL
);
2657 cpu_sub_arch_name
= xstrdup (string
);
2658 cpu_arch_flags
= flags
;
2659 cpu_arch_isa_flags
= flags
;
2661 (void) restore_line_pointer (e
);
2662 demand_empty_rest_of_line ();
2666 j
= ARRAY_SIZE (cpu_arch
);
2669 if (j
>= ARRAY_SIZE (cpu_arch
))
2670 as_bad (_("no such architecture: `%s'"), string
);
2672 *input_line_pointer
= e
;
2675 as_bad (_("missing cpu architecture"));
2677 no_cond_jump_promotion
= 0;
2678 if (*input_line_pointer
== ','
2679 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2684 ++input_line_pointer
;
2685 e
= get_symbol_name (&string
);
2687 if (strcmp (string
, "nojumps") == 0)
2688 no_cond_jump_promotion
= 1;
2689 else if (strcmp (string
, "jumps") == 0)
2692 as_bad (_("no such architecture modifier: `%s'"), string
);
2694 (void) restore_line_pointer (e
);
2697 demand_empty_rest_of_line ();
2700 enum bfd_architecture
2703 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2705 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2706 || flag_code
!= CODE_64BIT
)
2707 as_fatal (_("Intel L1OM is 64bit ELF only"));
2708 return bfd_arch_l1om
;
2710 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2712 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2713 || flag_code
!= CODE_64BIT
)
2714 as_fatal (_("Intel K1OM is 64bit ELF only"));
2715 return bfd_arch_k1om
;
2717 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2719 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2720 || flag_code
== CODE_64BIT
)
2721 as_fatal (_("Intel MCU is 32bit ELF only"));
2722 return bfd_arch_iamcu
;
2725 return bfd_arch_i386
;
2731 if (!strncmp (default_arch
, "x86_64", 6))
2733 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2735 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2736 || default_arch
[6] != '\0')
2737 as_fatal (_("Intel L1OM is 64bit ELF only"));
2738 return bfd_mach_l1om
;
2740 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2742 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2743 || default_arch
[6] != '\0')
2744 as_fatal (_("Intel K1OM is 64bit ELF only"));
2745 return bfd_mach_k1om
;
2747 else if (default_arch
[6] == '\0')
2748 return bfd_mach_x86_64
;
2750 return bfd_mach_x64_32
;
2752 else if (!strcmp (default_arch
, "i386")
2753 || !strcmp (default_arch
, "iamcu"))
2755 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2757 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2758 as_fatal (_("Intel MCU is 32bit ELF only"));
2759 return bfd_mach_i386_iamcu
;
2762 return bfd_mach_i386_i386
;
2765 as_fatal (_("unknown architecture"));
2771 const char *hash_err
;
2773 /* Support pseudo prefixes like {disp32}. */
2774 lex_type
['{'] = LEX_BEGIN_NAME
;
2776 /* Initialize op_hash hash table. */
2777 op_hash
= hash_new ();
2780 const insn_template
*optab
;
2781 templates
*core_optab
;
2783 /* Setup for loop. */
2785 core_optab
= XNEW (templates
);
2786 core_optab
->start
= optab
;
2791 if (optab
->name
== NULL
2792 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2794 /* different name --> ship out current template list;
2795 add to hash table; & begin anew. */
2796 core_optab
->end
= optab
;
2797 hash_err
= hash_insert (op_hash
,
2799 (void *) core_optab
);
2802 as_fatal (_("can't hash %s: %s"),
2806 if (optab
->name
== NULL
)
2808 core_optab
= XNEW (templates
);
2809 core_optab
->start
= optab
;
2814 /* Initialize reg_hash hash table. */
2815 reg_hash
= hash_new ();
2817 const reg_entry
*regtab
;
2818 unsigned int regtab_size
= i386_regtab_size
;
2820 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2822 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2824 as_fatal (_("can't hash %s: %s"),
2830 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2835 for (c
= 0; c
< 256; c
++)
2840 mnemonic_chars
[c
] = c
;
2841 register_chars
[c
] = c
;
2842 operand_chars
[c
] = c
;
2844 else if (ISLOWER (c
))
2846 mnemonic_chars
[c
] = c
;
2847 register_chars
[c
] = c
;
2848 operand_chars
[c
] = c
;
2850 else if (ISUPPER (c
))
2852 mnemonic_chars
[c
] = TOLOWER (c
);
2853 register_chars
[c
] = mnemonic_chars
[c
];
2854 operand_chars
[c
] = c
;
2856 else if (c
== '{' || c
== '}')
2858 mnemonic_chars
[c
] = c
;
2859 operand_chars
[c
] = c
;
2862 if (ISALPHA (c
) || ISDIGIT (c
))
2863 identifier_chars
[c
] = c
;
2866 identifier_chars
[c
] = c
;
2867 operand_chars
[c
] = c
;
2872 identifier_chars
['@'] = '@';
2875 identifier_chars
['?'] = '?';
2876 operand_chars
['?'] = '?';
2878 digit_chars
['-'] = '-';
2879 mnemonic_chars
['_'] = '_';
2880 mnemonic_chars
['-'] = '-';
2881 mnemonic_chars
['.'] = '.';
2882 identifier_chars
['_'] = '_';
2883 identifier_chars
['.'] = '.';
2885 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2886 operand_chars
[(unsigned char) *p
] = *p
;
2889 if (flag_code
== CODE_64BIT
)
2891 #if defined (OBJ_COFF) && defined (TE_PE)
2892 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2895 x86_dwarf2_return_column
= 16;
2897 x86_cie_data_alignment
= -8;
2901 x86_dwarf2_return_column
= 8;
2902 x86_cie_data_alignment
= -4;
2907 i386_print_statistics (FILE *file
)
2909 hash_print_statistics (file
, "i386 opcode", op_hash
);
2910 hash_print_statistics (file
, "i386 register", reg_hash
);
2915 /* Debugging routines for md_assemble. */
2916 static void pte (insn_template
*);
2917 static void pt (i386_operand_type
);
2918 static void pe (expressionS
*);
2919 static void ps (symbolS
*);
2922 pi (char *line
, i386_insn
*x
)
2926 fprintf (stdout
, "%s: template ", line
);
2928 fprintf (stdout
, " address: base %s index %s scale %x\n",
2929 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2930 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2931 x
->log2_scale_factor
);
2932 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2933 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2934 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2935 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2936 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2937 (x
->rex
& REX_W
) != 0,
2938 (x
->rex
& REX_R
) != 0,
2939 (x
->rex
& REX_X
) != 0,
2940 (x
->rex
& REX_B
) != 0);
2941 for (j
= 0; j
< x
->operands
; j
++)
2943 fprintf (stdout
, " #%d: ", j
+ 1);
2945 fprintf (stdout
, "\n");
2946 if (x
->types
[j
].bitfield
.reg
2947 || x
->types
[j
].bitfield
.regmmx
2948 || x
->types
[j
].bitfield
.regsimd
2949 || x
->types
[j
].bitfield
.sreg2
2950 || x
->types
[j
].bitfield
.sreg3
2951 || x
->types
[j
].bitfield
.control
2952 || x
->types
[j
].bitfield
.debug
2953 || x
->types
[j
].bitfield
.test
)
2954 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2955 if (operand_type_check (x
->types
[j
], imm
))
2957 if (operand_type_check (x
->types
[j
], disp
))
2958 pe (x
->op
[j
].disps
);
2963 pte (insn_template
*t
)
2966 fprintf (stdout
, " %d operands ", t
->operands
);
2967 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2968 if (t
->extension_opcode
!= None
)
2969 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2970 if (t
->opcode_modifier
.d
)
2971 fprintf (stdout
, "D");
2972 if (t
->opcode_modifier
.w
)
2973 fprintf (stdout
, "W");
2974 fprintf (stdout
, "\n");
2975 for (j
= 0; j
< t
->operands
; j
++)
2977 fprintf (stdout
, " #%d type ", j
+ 1);
2978 pt (t
->operand_types
[j
]);
2979 fprintf (stdout
, "\n");
2986 fprintf (stdout
, " operation %d\n", e
->X_op
);
2987 fprintf (stdout
, " add_number %ld (%lx)\n",
2988 (long) e
->X_add_number
, (long) e
->X_add_number
);
2989 if (e
->X_add_symbol
)
2991 fprintf (stdout
, " add_symbol ");
2992 ps (e
->X_add_symbol
);
2993 fprintf (stdout
, "\n");
2997 fprintf (stdout
, " op_symbol ");
2998 ps (e
->X_op_symbol
);
2999 fprintf (stdout
, "\n");
3006 fprintf (stdout
, "%s type %s%s",
3008 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3009 segment_name (S_GET_SEGMENT (s
)));
3012 static struct type_name
3014 i386_operand_type mask
;
3017 const type_names
[] =
3019 { OPERAND_TYPE_REG8
, "r8" },
3020 { OPERAND_TYPE_REG16
, "r16" },
3021 { OPERAND_TYPE_REG32
, "r32" },
3022 { OPERAND_TYPE_REG64
, "r64" },
3023 { OPERAND_TYPE_IMM8
, "i8" },
3024 { OPERAND_TYPE_IMM8
, "i8s" },
3025 { OPERAND_TYPE_IMM16
, "i16" },
3026 { OPERAND_TYPE_IMM32
, "i32" },
3027 { OPERAND_TYPE_IMM32S
, "i32s" },
3028 { OPERAND_TYPE_IMM64
, "i64" },
3029 { OPERAND_TYPE_IMM1
, "i1" },
3030 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3031 { OPERAND_TYPE_DISP8
, "d8" },
3032 { OPERAND_TYPE_DISP16
, "d16" },
3033 { OPERAND_TYPE_DISP32
, "d32" },
3034 { OPERAND_TYPE_DISP32S
, "d32s" },
3035 { OPERAND_TYPE_DISP64
, "d64" },
3036 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3037 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3038 { OPERAND_TYPE_CONTROL
, "control reg" },
3039 { OPERAND_TYPE_TEST
, "test reg" },
3040 { OPERAND_TYPE_DEBUG
, "debug reg" },
3041 { OPERAND_TYPE_FLOATREG
, "FReg" },
3042 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3043 { OPERAND_TYPE_SREG2
, "SReg2" },
3044 { OPERAND_TYPE_SREG3
, "SReg3" },
3045 { OPERAND_TYPE_ACC
, "Acc" },
3046 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3047 { OPERAND_TYPE_REGMMX
, "rMMX" },
3048 { OPERAND_TYPE_REGXMM
, "rXMM" },
3049 { OPERAND_TYPE_REGYMM
, "rYMM" },
3050 { OPERAND_TYPE_REGZMM
, "rZMM" },
3051 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3052 { OPERAND_TYPE_ESSEG
, "es" },
3056 pt (i386_operand_type t
)
3059 i386_operand_type a
;
3061 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3063 a
= operand_type_and (t
, type_names
[j
].mask
);
3064 if (!operand_type_all_zero (&a
))
3065 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3070 #endif /* DEBUG386 */
3072 static bfd_reloc_code_real_type
3073 reloc (unsigned int size
,
3076 bfd_reloc_code_real_type other
)
3078 if (other
!= NO_RELOC
)
3080 reloc_howto_type
*rel
;
3085 case BFD_RELOC_X86_64_GOT32
:
3086 return BFD_RELOC_X86_64_GOT64
;
3088 case BFD_RELOC_X86_64_GOTPLT64
:
3089 return BFD_RELOC_X86_64_GOTPLT64
;
3091 case BFD_RELOC_X86_64_PLTOFF64
:
3092 return BFD_RELOC_X86_64_PLTOFF64
;
3094 case BFD_RELOC_X86_64_GOTPC32
:
3095 other
= BFD_RELOC_X86_64_GOTPC64
;
3097 case BFD_RELOC_X86_64_GOTPCREL
:
3098 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3100 case BFD_RELOC_X86_64_TPOFF32
:
3101 other
= BFD_RELOC_X86_64_TPOFF64
;
3103 case BFD_RELOC_X86_64_DTPOFF32
:
3104 other
= BFD_RELOC_X86_64_DTPOFF64
;
3110 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3111 if (other
== BFD_RELOC_SIZE32
)
3114 other
= BFD_RELOC_SIZE64
;
3117 as_bad (_("there are no pc-relative size relocations"));
3123 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3124 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3127 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3129 as_bad (_("unknown relocation (%u)"), other
);
3130 else if (size
!= bfd_get_reloc_size (rel
))
3131 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3132 bfd_get_reloc_size (rel
),
3134 else if (pcrel
&& !rel
->pc_relative
)
3135 as_bad (_("non-pc-relative relocation for pc-relative field"));
3136 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3138 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3140 as_bad (_("relocated field and relocation type differ in signedness"));
3149 as_bad (_("there are no unsigned pc-relative relocations"));
3152 case 1: return BFD_RELOC_8_PCREL
;
3153 case 2: return BFD_RELOC_16_PCREL
;
3154 case 4: return BFD_RELOC_32_PCREL
;
3155 case 8: return BFD_RELOC_64_PCREL
;
3157 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3164 case 4: return BFD_RELOC_X86_64_32S
;
3169 case 1: return BFD_RELOC_8
;
3170 case 2: return BFD_RELOC_16
;
3171 case 4: return BFD_RELOC_32
;
3172 case 8: return BFD_RELOC_64
;
3174 as_bad (_("cannot do %s %u byte relocation"),
3175 sign
> 0 ? "signed" : "unsigned", size
);
3181 /* Here we decide which fixups can be adjusted to make them relative to
3182 the beginning of the section instead of the symbol. Basically we need
3183 to make sure that the dynamic relocations are done correctly, so in
3184 some cases we force the original symbol to be used. */
3187 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3193 /* Don't adjust pc-relative references to merge sections in 64-bit
3195 if (use_rela_relocations
3196 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3200 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3201 and changed later by validate_fix. */
3202 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3203 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3206 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3207 for size relocations. */
3208 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3209 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3210 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3211 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3212 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3213 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3214 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3215 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3216 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3217 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3218 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3219 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3220 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3221 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3222 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3223 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3224 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3225 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3226 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3227 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3228 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3229 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3230 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3231 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3232 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3239 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3240 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3247 intel_float_operand (const char *mnemonic
)
3249 /* Note that the value returned is meaningful only for opcodes with (memory)
3250 operands, hence the code here is free to improperly handle opcodes that
3251 have no operands (for better performance and smaller code). */
3253 if (mnemonic
[0] != 'f')
3254 return 0; /* non-math */
3256 switch (mnemonic
[1])
3258 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3259 the fs segment override prefix not currently handled because no
3260 call path can make opcodes without operands get here */
3262 return 2 /* integer op */;
3264 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3265 return 3; /* fldcw/fldenv */
3268 if (mnemonic
[2] != 'o' /* fnop */)
3269 return 3; /* non-waiting control op */
3272 if (mnemonic
[2] == 's')
3273 return 3; /* frstor/frstpm */
3276 if (mnemonic
[2] == 'a')
3277 return 3; /* fsave */
3278 if (mnemonic
[2] == 't')
3280 switch (mnemonic
[3])
3282 case 'c': /* fstcw */
3283 case 'd': /* fstdw */
3284 case 'e': /* fstenv */
3285 case 's': /* fsts[gw] */
3291 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3292 return 0; /* fxsave/fxrstor are not really math ops */
3299 /* Build the VEX prefix. */
3302 build_vex_prefix (const insn_template
*t
)
3304 unsigned int register_specifier
;
3305 unsigned int implied_prefix
;
3306 unsigned int vector_length
;
3308 /* Check register specifier. */
3309 if (i
.vex
.register_specifier
)
3311 register_specifier
=
3312 ~register_number (i
.vex
.register_specifier
) & 0xf;
3313 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3316 register_specifier
= 0xf;
3318 /* Use 2-byte VEX prefix by swapping destination and source
3320 if (i
.vec_encoding
!= vex_encoding_vex3
3321 && i
.dir_encoding
== dir_encoding_default
3322 && i
.operands
== i
.reg_operands
3323 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3324 && i
.tm
.opcode_modifier
.load
3327 unsigned int xchg
= i
.operands
- 1;
3328 union i386_op temp_op
;
3329 i386_operand_type temp_type
;
3331 temp_type
= i
.types
[xchg
];
3332 i
.types
[xchg
] = i
.types
[0];
3333 i
.types
[0] = temp_type
;
3334 temp_op
= i
.op
[xchg
];
3335 i
.op
[xchg
] = i
.op
[0];
3338 gas_assert (i
.rm
.mode
== 3);
3342 i
.rm
.regmem
= i
.rm
.reg
;
3345 /* Use the next insn. */
3349 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3350 vector_length
= avxscalar
;
3351 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3358 for (op
= 0; op
< t
->operands
; ++op
)
3359 if (t
->operand_types
[op
].bitfield
.xmmword
3360 && t
->operand_types
[op
].bitfield
.ymmword
3361 && i
.types
[op
].bitfield
.ymmword
)
3368 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3373 case DATA_PREFIX_OPCODE
:
3376 case REPE_PREFIX_OPCODE
:
3379 case REPNE_PREFIX_OPCODE
:
3386 /* Use 2-byte VEX prefix if possible. */
3387 if (i
.vec_encoding
!= vex_encoding_vex3
3388 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3389 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3390 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3392 /* 2-byte VEX prefix. */
3396 i
.vex
.bytes
[0] = 0xc5;
3398 /* Check the REX.R bit. */
3399 r
= (i
.rex
& REX_R
) ? 0 : 1;
3400 i
.vex
.bytes
[1] = (r
<< 7
3401 | register_specifier
<< 3
3402 | vector_length
<< 2
3407 /* 3-byte VEX prefix. */
3412 switch (i
.tm
.opcode_modifier
.vexopcode
)
3416 i
.vex
.bytes
[0] = 0xc4;
3420 i
.vex
.bytes
[0] = 0xc4;
3424 i
.vex
.bytes
[0] = 0xc4;
3428 i
.vex
.bytes
[0] = 0x8f;
3432 i
.vex
.bytes
[0] = 0x8f;
3436 i
.vex
.bytes
[0] = 0x8f;
3442 /* The high 3 bits of the second VEX byte are 1's compliment
3443 of RXB bits from REX. */
3444 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3446 /* Check the REX.W bit. */
3447 w
= (i
.rex
& REX_W
) ? 1 : 0;
3448 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3451 i
.vex
.bytes
[2] = (w
<< 7
3452 | register_specifier
<< 3
3453 | vector_length
<< 2
3458 static INLINE bfd_boolean
3459 is_evex_encoding (const insn_template
*t
)
3461 return t
->opcode_modifier
.evex
3462 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3463 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3466 /* Build the EVEX prefix. */
3469 build_evex_prefix (void)
3471 unsigned int register_specifier
;
3472 unsigned int implied_prefix
;
3474 rex_byte vrex_used
= 0;
3476 /* Check register specifier. */
3477 if (i
.vex
.register_specifier
)
3479 gas_assert ((i
.vrex
& REX_X
) == 0);
3481 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3482 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3483 register_specifier
+= 8;
3484 /* The upper 16 registers are encoded in the fourth byte of the
3486 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3487 i
.vex
.bytes
[3] = 0x8;
3488 register_specifier
= ~register_specifier
& 0xf;
3492 register_specifier
= 0xf;
3494 /* Encode upper 16 vector index register in the fourth byte of
3496 if (!(i
.vrex
& REX_X
))
3497 i
.vex
.bytes
[3] = 0x8;
3502 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3507 case DATA_PREFIX_OPCODE
:
3510 case REPE_PREFIX_OPCODE
:
3513 case REPNE_PREFIX_OPCODE
:
3520 /* 4 byte EVEX prefix. */
3522 i
.vex
.bytes
[0] = 0x62;
3525 switch (i
.tm
.opcode_modifier
.vexopcode
)
3541 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3543 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3545 /* The fifth bit of the second EVEX byte is 1's compliment of the
3546 REX_R bit in VREX. */
3547 if (!(i
.vrex
& REX_R
))
3548 i
.vex
.bytes
[1] |= 0x10;
3552 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3554 /* When all operands are registers, the REX_X bit in REX is not
3555 used. We reuse it to encode the upper 16 registers, which is
3556 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3557 as 1's compliment. */
3558 if ((i
.vrex
& REX_B
))
3561 i
.vex
.bytes
[1] &= ~0x40;
3565 /* EVEX instructions shouldn't need the REX prefix. */
3566 i
.vrex
&= ~vrex_used
;
3567 gas_assert (i
.vrex
== 0);
3569 /* Check the REX.W bit. */
3570 w
= (i
.rex
& REX_W
) ? 1 : 0;
3571 if (i
.tm
.opcode_modifier
.vexw
)
3573 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3576 /* If w is not set it means we are dealing with WIG instruction. */
3579 if (evexwig
== evexw1
)
3583 /* Encode the U bit. */
3584 implied_prefix
|= 0x4;
3586 /* The third byte of the EVEX prefix. */
3587 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3589 /* The fourth byte of the EVEX prefix. */
3590 /* The zeroing-masking bit. */
3591 if (i
.mask
&& i
.mask
->zeroing
)
3592 i
.vex
.bytes
[3] |= 0x80;
3594 /* Don't always set the broadcast bit if there is no RC. */
3597 /* Encode the vector length. */
3598 unsigned int vec_length
;
3600 if (!i
.tm
.opcode_modifier
.evex
3601 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3606 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3607 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3608 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3609 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3611 if (i
.types
[op
].bitfield
.zmmword
)
3612 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3613 else if (i
.types
[op
].bitfield
.ymmword
)
3614 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3615 else if (i
.types
[op
].bitfield
.xmmword
)
3616 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3623 switch (i
.tm
.opcode_modifier
.evex
)
3625 case EVEXLIG
: /* LL' is ignored */
3626 vec_length
= evexlig
<< 5;
3629 vec_length
= 0 << 5;
3632 vec_length
= 1 << 5;
3635 vec_length
= 2 << 5;
3641 i
.vex
.bytes
[3] |= vec_length
;
3642 /* Encode the broadcast bit. */
3644 i
.vex
.bytes
[3] |= 0x10;
3648 if (i
.rounding
->type
!= saeonly
)
3649 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3651 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3654 if (i
.mask
&& i
.mask
->mask
)
3655 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3659 process_immext (void)
3663 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3666 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3667 with an opcode suffix which is coded in the same place as an
3668 8-bit immediate field would be.
3669 Here we check those operands and remove them afterwards. */
3672 for (x
= 0; x
< i
.operands
; x
++)
3673 if (register_number (i
.op
[x
].regs
) != x
)
3674 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3675 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3681 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3683 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3684 suffix which is coded in the same place as an 8-bit immediate
3686 Here we check those operands and remove them afterwards. */
3689 if (i
.operands
!= 3)
3692 for (x
= 0; x
< 2; x
++)
3693 if (register_number (i
.op
[x
].regs
) != x
)
3694 goto bad_register_operand
;
3696 /* Check for third operand for mwaitx/monitorx insn. */
3697 if (register_number (i
.op
[x
].regs
)
3698 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3700 bad_register_operand
:
3701 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3702 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3709 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3710 which is coded in the same place as an 8-bit immediate field
3711 would be. Here we fake an 8-bit immediate operand from the
3712 opcode suffix stored in tm.extension_opcode.
3714 AVX instructions also use this encoding, for some of
3715 3 argument instructions. */
3717 gas_assert (i
.imm_operands
<= 1
3719 || ((i
.tm
.opcode_modifier
.vex
3720 || i
.tm
.opcode_modifier
.vexopcode
3721 || is_evex_encoding (&i
.tm
))
3722 && i
.operands
<= 4)));
3724 exp
= &im_expressions
[i
.imm_operands
++];
3725 i
.op
[i
.operands
].imms
= exp
;
3726 i
.types
[i
.operands
] = imm8
;
3728 exp
->X_op
= O_constant
;
3729 exp
->X_add_number
= i
.tm
.extension_opcode
;
3730 i
.tm
.extension_opcode
= None
;
3737 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3742 as_bad (_("invalid instruction `%s' after `%s'"),
3743 i
.tm
.name
, i
.hle_prefix
);
3746 if (i
.prefix
[LOCK_PREFIX
])
3748 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3752 case HLEPrefixRelease
:
3753 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3755 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3759 if (i
.mem_operands
== 0
3760 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3762 as_bad (_("memory destination needed for instruction `%s'"
3763 " after `xrelease'"), i
.tm
.name
);
3770 /* Try the shortest encoding by shortening operand size. */
3773 optimize_encoding (void)
3777 if (optimize_for_space
3778 && i
.reg_operands
== 1
3779 && i
.imm_operands
== 1
3780 && !i
.types
[1].bitfield
.byte
3781 && i
.op
[0].imms
->X_op
== O_constant
3782 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3783 && ((i
.tm
.base_opcode
== 0xa8
3784 && i
.tm
.extension_opcode
== None
)
3785 || (i
.tm
.base_opcode
== 0xf6
3786 && i
.tm
.extension_opcode
== 0x0)))
3789 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3791 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3792 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3794 i
.types
[1].bitfield
.byte
= 1;
3795 /* Ignore the suffix. */
3797 if (base_regnum
>= 4
3798 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3800 /* Handle SP, BP, SI and DI registers. */
3801 if (i
.types
[1].bitfield
.word
)
3803 else if (i
.types
[1].bitfield
.dword
)
3811 else if (flag_code
== CODE_64BIT
3812 && ((i
.types
[1].bitfield
.qword
3813 && i
.reg_operands
== 1
3814 && i
.imm_operands
== 1
3815 && i
.op
[0].imms
->X_op
== O_constant
3816 && ((i
.tm
.base_opcode
== 0xb0
3817 && i
.tm
.extension_opcode
== None
3818 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3819 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3820 && (((i
.tm
.base_opcode
== 0x24
3821 || i
.tm
.base_opcode
== 0xa8)
3822 && i
.tm
.extension_opcode
== None
)
3823 || (i
.tm
.base_opcode
== 0x80
3824 && i
.tm
.extension_opcode
== 0x4)
3825 || ((i
.tm
.base_opcode
== 0xf6
3826 || i
.tm
.base_opcode
== 0xc6)
3827 && i
.tm
.extension_opcode
== 0x0)))))
3828 || (i
.types
[0].bitfield
.qword
3829 && ((i
.reg_operands
== 2
3830 && i
.op
[0].regs
== i
.op
[1].regs
3831 && ((i
.tm
.base_opcode
== 0x30
3832 || i
.tm
.base_opcode
== 0x28)
3833 && i
.tm
.extension_opcode
== None
))
3834 || (i
.reg_operands
== 1
3836 && i
.tm
.base_opcode
== 0x30
3837 && i
.tm
.extension_opcode
== None
)))))
3840 andq $imm31, %r64 -> andl $imm31, %r32
3841 testq $imm31, %r64 -> testl $imm31, %r32
3842 xorq %r64, %r64 -> xorl %r32, %r32
3843 subq %r64, %r64 -> subl %r32, %r32
3844 movq $imm31, %r64 -> movl $imm31, %r32
3845 movq $imm32, %r64 -> movl $imm32, %r32
3847 i
.tm
.opcode_modifier
.norex64
= 1;
3848 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3851 movq $imm31, %r64 -> movl $imm31, %r32
3852 movq $imm32, %r64 -> movl $imm32, %r32
3854 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3855 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3856 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3857 i
.types
[0].bitfield
.imm32
= 1;
3858 i
.types
[0].bitfield
.imm32s
= 0;
3859 i
.types
[0].bitfield
.imm64
= 0;
3860 i
.types
[1].bitfield
.dword
= 1;
3861 i
.types
[1].bitfield
.qword
= 0;
3862 if (i
.tm
.base_opcode
== 0xc6)
3865 movq $imm31, %r64 -> movl $imm31, %r32
3867 i
.tm
.base_opcode
= 0xb0;
3868 i
.tm
.extension_opcode
= None
;
3869 i
.tm
.opcode_modifier
.shortform
= 1;
3870 i
.tm
.opcode_modifier
.modrm
= 0;
3874 else if (optimize
> 1
3875 && i
.reg_operands
== 3
3876 && i
.op
[0].regs
== i
.op
[1].regs
3877 && !i
.types
[2].bitfield
.xmmword
3878 && (i
.tm
.opcode_modifier
.vex
3881 && is_evex_encoding (&i
.tm
)
3882 && (i
.vec_encoding
!= vex_encoding_evex
3883 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3884 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3885 && ((i
.tm
.base_opcode
== 0x55
3886 || i
.tm
.base_opcode
== 0x6655
3887 || i
.tm
.base_opcode
== 0x66df
3888 || i
.tm
.base_opcode
== 0x57
3889 || i
.tm
.base_opcode
== 0x6657
3890 || i
.tm
.base_opcode
== 0x66ef
3891 || i
.tm
.base_opcode
== 0x66f8
3892 || i
.tm
.base_opcode
== 0x66f9
3893 || i
.tm
.base_opcode
== 0x66fa
3894 || i
.tm
.base_opcode
== 0x66fb)
3895 && i
.tm
.extension_opcode
== None
))
3898 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3900 EVEX VOP %zmmM, %zmmM, %zmmN
3901 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3902 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3903 EVEX VOP %ymmM, %ymmM, %ymmN
3904 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3905 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3906 VEX VOP %ymmM, %ymmM, %ymmN
3907 -> VEX VOP %xmmM, %xmmM, %xmmN
3908 VOP, one of vpandn and vpxor:
3909 VEX VOP %ymmM, %ymmM, %ymmN
3910 -> VEX VOP %xmmM, %xmmM, %xmmN
3911 VOP, one of vpandnd and vpandnq:
3912 EVEX VOP %zmmM, %zmmM, %zmmN
3913 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3914 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3915 EVEX VOP %ymmM, %ymmM, %ymmN
3916 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3917 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3918 VOP, one of vpxord and vpxorq:
3919 EVEX VOP %zmmM, %zmmM, %zmmN
3920 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3921 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3922 EVEX VOP %ymmM, %ymmM, %ymmN
3923 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3926 if (is_evex_encoding (&i
.tm
))
3928 if (i
.vec_encoding
== vex_encoding_evex
)
3929 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3932 i
.tm
.opcode_modifier
.vex
= VEX128
;
3933 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3934 i
.tm
.opcode_modifier
.evex
= 0;
3938 i
.tm
.opcode_modifier
.vex
= VEX128
;
3940 if (i
.tm
.opcode_modifier
.vex
)
3941 for (j
= 0; j
< 3; j
++)
3943 i
.types
[j
].bitfield
.xmmword
= 1;
3944 i
.types
[j
].bitfield
.ymmword
= 0;
3949 /* This is the guts of the machine-dependent assembler. LINE points to a
3950 machine dependent instruction. This function is supposed to emit
3951 the frags/bytes it assembles to. */
3954 md_assemble (char *line
)
3957 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3958 const insn_template
*t
;
3960 /* Initialize globals. */
3961 memset (&i
, '\0', sizeof (i
));
3962 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3963 i
.reloc
[j
] = NO_RELOC
;
3964 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3965 memset (im_expressions
, '\0', sizeof (im_expressions
));
3966 save_stack_p
= save_stack
;
3968 /* First parse an instruction mnemonic & call i386_operand for the operands.
3969 We assume that the scrubber has arranged it so that line[0] is the valid
3970 start of a (possibly prefixed) mnemonic. */
3972 line
= parse_insn (line
, mnemonic
);
3975 mnem_suffix
= i
.suffix
;
3977 line
= parse_operands (line
, mnemonic
);
3979 xfree (i
.memop1_string
);
3980 i
.memop1_string
= NULL
;
3984 /* Now we've parsed the mnemonic into a set of templates, and have the
3985 operands at hand. */
3987 /* All intel opcodes have reversed operands except for "bound" and
3988 "enter". We also don't reverse intersegment "jmp" and "call"
3989 instructions with 2 immediate operands so that the immediate segment
3990 precedes the offset, as it does when in AT&T mode. */
3993 && (strcmp (mnemonic
, "bound") != 0)
3994 && (strcmp (mnemonic
, "invlpga") != 0)
3995 && !(operand_type_check (i
.types
[0], imm
)
3996 && operand_type_check (i
.types
[1], imm
)))
3999 /* The order of the immediates should be reversed
4000 for 2 immediates extrq and insertq instructions */
4001 if (i
.imm_operands
== 2
4002 && (strcmp (mnemonic
, "extrq") == 0
4003 || strcmp (mnemonic
, "insertq") == 0))
4004 swap_2_operands (0, 1);
4009 /* Don't optimize displacement for movabs since it only takes 64bit
4012 && i
.disp_encoding
!= disp_encoding_32bit
4013 && (flag_code
!= CODE_64BIT
4014 || strcmp (mnemonic
, "movabs") != 0))
4017 /* Next, we find a template that matches the given insn,
4018 making sure the overlap of the given operands types is consistent
4019 with the template operand types. */
4021 if (!(t
= match_template (mnem_suffix
)))
4024 if (sse_check
!= check_none
4025 && !i
.tm
.opcode_modifier
.noavx
4026 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4027 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4028 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4029 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4030 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4031 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4032 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4033 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4034 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4035 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4037 (sse_check
== check_warning
4039 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4042 /* Zap movzx and movsx suffix. The suffix has been set from
4043 "word ptr" or "byte ptr" on the source operand in Intel syntax
4044 or extracted from mnemonic in AT&T syntax. But we'll use
4045 the destination register to choose the suffix for encoding. */
4046 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4048 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4049 there is no suffix, the default will be byte extension. */
4050 if (i
.reg_operands
!= 2
4053 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4058 if (i
.tm
.opcode_modifier
.fwait
)
4059 if (!add_prefix (FWAIT_OPCODE
))
4062 /* Check if REP prefix is OK. */
4063 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4065 as_bad (_("invalid instruction `%s' after `%s'"),
4066 i
.tm
.name
, i
.rep_prefix
);
4070 /* Check for lock without a lockable instruction. Destination operand
4071 must be memory unless it is xchg (0x86). */
4072 if (i
.prefix
[LOCK_PREFIX
]
4073 && (!i
.tm
.opcode_modifier
.islockable
4074 || i
.mem_operands
== 0
4075 || (i
.tm
.base_opcode
!= 0x86
4076 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4078 as_bad (_("expecting lockable instruction after `lock'"));
4082 /* Check if HLE prefix is OK. */
4083 if (i
.hle_prefix
&& !check_hle ())
4086 /* Check BND prefix. */
4087 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4088 as_bad (_("expecting valid branch instruction after `bnd'"));
4090 /* Check NOTRACK prefix. */
4091 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4092 as_bad (_("expecting indirect branch instruction after `notrack'"));
4094 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4096 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4097 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4098 else if (flag_code
!= CODE_16BIT
4099 ? i
.prefix
[ADDR_PREFIX
]
4100 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4101 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4104 /* Insert BND prefix. */
4106 && i
.tm
.opcode_modifier
.bndprefixok
4107 && !i
.prefix
[BND_PREFIX
])
4108 add_prefix (BND_PREFIX_OPCODE
);
4110 /* Check string instruction segment overrides. */
4111 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4113 if (!check_string ())
4115 i
.disp_operands
= 0;
4118 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4119 optimize_encoding ();
4121 if (!process_suffix ())
4124 /* Update operand types. */
4125 for (j
= 0; j
< i
.operands
; j
++)
4126 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4128 /* Make still unresolved immediate matches conform to size of immediate
4129 given in i.suffix. */
4130 if (!finalize_imm ())
4133 if (i
.types
[0].bitfield
.imm1
)
4134 i
.imm_operands
= 0; /* kludge for shift insns. */
4136 /* We only need to check those implicit registers for instructions
4137 with 3 operands or less. */
4138 if (i
.operands
<= 3)
4139 for (j
= 0; j
< i
.operands
; j
++)
4140 if (i
.types
[j
].bitfield
.inoutportreg
4141 || i
.types
[j
].bitfield
.shiftcount
4142 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4145 /* ImmExt should be processed after SSE2AVX. */
4146 if (!i
.tm
.opcode_modifier
.sse2avx
4147 && i
.tm
.opcode_modifier
.immext
)
4150 /* For insns with operands there are more diddles to do to the opcode. */
4153 if (!process_operands ())
4156 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4158 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4159 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4162 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4163 || is_evex_encoding (&i
.tm
))
4165 if (flag_code
== CODE_16BIT
)
4167 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4172 if (i
.tm
.opcode_modifier
.vex
)
4173 build_vex_prefix (t
);
4175 build_evex_prefix ();
4178 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4179 instructions may define INT_OPCODE as well, so avoid this corner
4180 case for those instructions that use MODRM. */
4181 if (i
.tm
.base_opcode
== INT_OPCODE
4182 && !i
.tm
.opcode_modifier
.modrm
4183 && i
.op
[0].imms
->X_add_number
== 3)
4185 i
.tm
.base_opcode
= INT3_OPCODE
;
4189 if ((i
.tm
.opcode_modifier
.jump
4190 || i
.tm
.opcode_modifier
.jumpbyte
4191 || i
.tm
.opcode_modifier
.jumpdword
)
4192 && i
.op
[0].disps
->X_op
== O_constant
)
4194 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4195 the absolute address given by the constant. Since ix86 jumps and
4196 calls are pc relative, we need to generate a reloc. */
4197 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4198 i
.op
[0].disps
->X_op
= O_symbol
;
4201 if (i
.tm
.opcode_modifier
.rex64
)
4204 /* For 8 bit registers we need an empty rex prefix. Also if the
4205 instruction already has a prefix, we need to convert old
4206 registers to new ones. */
4208 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4209 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4210 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4211 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4212 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4213 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4218 i
.rex
|= REX_OPCODE
;
4219 for (x
= 0; x
< 2; x
++)
4221 /* Look for 8 bit operand that uses old registers. */
4222 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4223 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4225 /* In case it is "hi" register, give up. */
4226 if (i
.op
[x
].regs
->reg_num
> 3)
4227 as_bad (_("can't encode register '%s%s' in an "
4228 "instruction requiring REX prefix."),
4229 register_prefix
, i
.op
[x
].regs
->reg_name
);
4231 /* Otherwise it is equivalent to the extended register.
4232 Since the encoding doesn't change this is merely
4233 cosmetic cleanup for debug output. */
4235 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4240 if (i
.rex
== 0 && i
.rex_encoding
)
4242 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4243 that uses legacy register. If it is "hi" register, don't add
4244 the REX_OPCODE byte. */
4246 for (x
= 0; x
< 2; x
++)
4247 if (i
.types
[x
].bitfield
.reg
4248 && i
.types
[x
].bitfield
.byte
4249 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4250 && i
.op
[x
].regs
->reg_num
> 3)
4252 i
.rex_encoding
= FALSE
;
4261 add_prefix (REX_OPCODE
| i
.rex
);
4263 /* We are ready to output the insn. */
4268 parse_insn (char *line
, char *mnemonic
)
4271 char *token_start
= l
;
4274 const insn_template
*t
;
4280 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4285 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4287 as_bad (_("no such instruction: `%s'"), token_start
);
4292 if (!is_space_char (*l
)
4293 && *l
!= END_OF_INSN
4295 || (*l
!= PREFIX_SEPARATOR
4298 as_bad (_("invalid character %s in mnemonic"),
4299 output_invalid (*l
));
4302 if (token_start
== l
)
4304 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4305 as_bad (_("expecting prefix; got nothing"));
4307 as_bad (_("expecting mnemonic; got nothing"));
4311 /* Look up instruction (or prefix) via hash table. */
4312 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4314 if (*l
!= END_OF_INSN
4315 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4316 && current_templates
4317 && current_templates
->start
->opcode_modifier
.isprefix
)
4319 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4321 as_bad ((flag_code
!= CODE_64BIT
4322 ? _("`%s' is only supported in 64-bit mode")
4323 : _("`%s' is not supported in 64-bit mode")),
4324 current_templates
->start
->name
);
4327 /* If we are in 16-bit mode, do not allow addr16 or data16.
4328 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4329 if ((current_templates
->start
->opcode_modifier
.size16
4330 || current_templates
->start
->opcode_modifier
.size32
)
4331 && flag_code
!= CODE_64BIT
4332 && (current_templates
->start
->opcode_modifier
.size32
4333 ^ (flag_code
== CODE_16BIT
)))
4335 as_bad (_("redundant %s prefix"),
4336 current_templates
->start
->name
);
4339 if (current_templates
->start
->opcode_length
== 0)
4341 /* Handle pseudo prefixes. */
4342 switch (current_templates
->start
->base_opcode
)
4346 i
.disp_encoding
= disp_encoding_8bit
;
4350 i
.disp_encoding
= disp_encoding_32bit
;
4354 i
.dir_encoding
= dir_encoding_load
;
4358 i
.dir_encoding
= dir_encoding_store
;
4362 i
.vec_encoding
= vex_encoding_vex2
;
4366 i
.vec_encoding
= vex_encoding_vex3
;
4370 i
.vec_encoding
= vex_encoding_evex
;
4374 i
.rex_encoding
= TRUE
;
4378 i
.no_optimize
= TRUE
;
4386 /* Add prefix, checking for repeated prefixes. */
4387 switch (add_prefix (current_templates
->start
->base_opcode
))
4392 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4393 i
.notrack_prefix
= current_templates
->start
->name
;
4396 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4397 i
.hle_prefix
= current_templates
->start
->name
;
4398 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4399 i
.bnd_prefix
= current_templates
->start
->name
;
4401 i
.rep_prefix
= current_templates
->start
->name
;
4407 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4414 if (!current_templates
)
4416 /* Check if we should swap operand or force 32bit displacement in
4418 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4419 i
.dir_encoding
= dir_encoding_store
;
4420 else if (mnem_p
- 3 == dot_p
4423 i
.disp_encoding
= disp_encoding_8bit
;
4424 else if (mnem_p
- 4 == dot_p
4428 i
.disp_encoding
= disp_encoding_32bit
;
4433 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4436 if (!current_templates
)
4439 /* See if we can get a match by trimming off a suffix. */
4442 case WORD_MNEM_SUFFIX
:
4443 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4444 i
.suffix
= SHORT_MNEM_SUFFIX
;
4447 case BYTE_MNEM_SUFFIX
:
4448 case QWORD_MNEM_SUFFIX
:
4449 i
.suffix
= mnem_p
[-1];
4451 current_templates
= (const templates
*) hash_find (op_hash
,
4454 case SHORT_MNEM_SUFFIX
:
4455 case LONG_MNEM_SUFFIX
:
4458 i
.suffix
= mnem_p
[-1];
4460 current_templates
= (const templates
*) hash_find (op_hash
,
4469 if (intel_float_operand (mnemonic
) == 1)
4470 i
.suffix
= SHORT_MNEM_SUFFIX
;
4472 i
.suffix
= LONG_MNEM_SUFFIX
;
4474 current_templates
= (const templates
*) hash_find (op_hash
,
4479 if (!current_templates
)
4481 as_bad (_("no such instruction: `%s'"), token_start
);
4486 if (current_templates
->start
->opcode_modifier
.jump
4487 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4489 /* Check for a branch hint. We allow ",pt" and ",pn" for
4490 predict taken and predict not taken respectively.
4491 I'm not sure that branch hints actually do anything on loop
4492 and jcxz insns (JumpByte) for current Pentium4 chips. They
4493 may work in the future and it doesn't hurt to accept them
4495 if (l
[0] == ',' && l
[1] == 'p')
4499 if (!add_prefix (DS_PREFIX_OPCODE
))
4503 else if (l
[2] == 'n')
4505 if (!add_prefix (CS_PREFIX_OPCODE
))
4511 /* Any other comma loses. */
4514 as_bad (_("invalid character %s in mnemonic"),
4515 output_invalid (*l
));
4519 /* Check if instruction is supported on specified architecture. */
4521 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4523 supported
|= cpu_flags_match (t
);
4524 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4526 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4527 as_warn (_("use .code16 to ensure correct addressing mode"));
4533 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4534 as_bad (flag_code
== CODE_64BIT
4535 ? _("`%s' is not supported in 64-bit mode")
4536 : _("`%s' is only supported in 64-bit mode"),
4537 current_templates
->start
->name
);
4539 as_bad (_("`%s' is not supported on `%s%s'"),
4540 current_templates
->start
->name
,
4541 cpu_arch_name
? cpu_arch_name
: default_arch
,
4542 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4548 parse_operands (char *l
, const char *mnemonic
)
4552 /* 1 if operand is pending after ','. */
4553 unsigned int expecting_operand
= 0;
4555 /* Non-zero if operand parens not balanced. */
4556 unsigned int paren_not_balanced
;
4558 while (*l
!= END_OF_INSN
)
4560 /* Skip optional white space before operand. */
4561 if (is_space_char (*l
))
4563 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4565 as_bad (_("invalid character %s before operand %d"),
4566 output_invalid (*l
),
4570 token_start
= l
; /* After white space. */
4571 paren_not_balanced
= 0;
4572 while (paren_not_balanced
|| *l
!= ',')
4574 if (*l
== END_OF_INSN
)
4576 if (paren_not_balanced
)
4579 as_bad (_("unbalanced parenthesis in operand %d."),
4582 as_bad (_("unbalanced brackets in operand %d."),
4587 break; /* we are done */
4589 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4591 as_bad (_("invalid character %s in operand %d"),
4592 output_invalid (*l
),
4599 ++paren_not_balanced
;
4601 --paren_not_balanced
;
4606 ++paren_not_balanced
;
4608 --paren_not_balanced
;
4612 if (l
!= token_start
)
4613 { /* Yes, we've read in another operand. */
4614 unsigned int operand_ok
;
4615 this_operand
= i
.operands
++;
4616 if (i
.operands
> MAX_OPERANDS
)
4618 as_bad (_("spurious operands; (%d operands/instruction max)"),
4622 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4623 /* Now parse operand adding info to 'i' as we go along. */
4624 END_STRING_AND_SAVE (l
);
4628 i386_intel_operand (token_start
,
4629 intel_float_operand (mnemonic
));
4631 operand_ok
= i386_att_operand (token_start
);
4633 RESTORE_END_STRING (l
);
4639 if (expecting_operand
)
4641 expecting_operand_after_comma
:
4642 as_bad (_("expecting operand after ','; got nothing"));
4647 as_bad (_("expecting operand before ','; got nothing"));
4652 /* Now *l must be either ',' or END_OF_INSN. */
4655 if (*++l
== END_OF_INSN
)
4657 /* Just skip it, if it's \n complain. */
4658 goto expecting_operand_after_comma
;
4660 expecting_operand
= 1;
4667 swap_2_operands (int xchg1
, int xchg2
)
4669 union i386_op temp_op
;
4670 i386_operand_type temp_type
;
4671 enum bfd_reloc_code_real temp_reloc
;
4673 temp_type
= i
.types
[xchg2
];
4674 i
.types
[xchg2
] = i
.types
[xchg1
];
4675 i
.types
[xchg1
] = temp_type
;
4676 temp_op
= i
.op
[xchg2
];
4677 i
.op
[xchg2
] = i
.op
[xchg1
];
4678 i
.op
[xchg1
] = temp_op
;
4679 temp_reloc
= i
.reloc
[xchg2
];
4680 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4681 i
.reloc
[xchg1
] = temp_reloc
;
4685 if (i
.mask
->operand
== xchg1
)
4686 i
.mask
->operand
= xchg2
;
4687 else if (i
.mask
->operand
== xchg2
)
4688 i
.mask
->operand
= xchg1
;
4692 if (i
.broadcast
->operand
== xchg1
)
4693 i
.broadcast
->operand
= xchg2
;
4694 else if (i
.broadcast
->operand
== xchg2
)
4695 i
.broadcast
->operand
= xchg1
;
4699 if (i
.rounding
->operand
== xchg1
)
4700 i
.rounding
->operand
= xchg2
;
4701 else if (i
.rounding
->operand
== xchg2
)
4702 i
.rounding
->operand
= xchg1
;
4707 swap_operands (void)
4713 swap_2_operands (1, i
.operands
- 2);
4717 swap_2_operands (0, i
.operands
- 1);
4723 if (i
.mem_operands
== 2)
4725 const seg_entry
*temp_seg
;
4726 temp_seg
= i
.seg
[0];
4727 i
.seg
[0] = i
.seg
[1];
4728 i
.seg
[1] = temp_seg
;
4732 /* Try to ensure constant immediates are represented in the smallest
4737 char guess_suffix
= 0;
4741 guess_suffix
= i
.suffix
;
4742 else if (i
.reg_operands
)
4744 /* Figure out a suffix from the last register operand specified.
4745 We can't do this properly yet, ie. excluding InOutPortReg,
4746 but the following works for instructions with immediates.
4747 In any case, we can't set i.suffix yet. */
4748 for (op
= i
.operands
; --op
>= 0;)
4749 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4751 guess_suffix
= BYTE_MNEM_SUFFIX
;
4754 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4756 guess_suffix
= WORD_MNEM_SUFFIX
;
4759 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4761 guess_suffix
= LONG_MNEM_SUFFIX
;
4764 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4766 guess_suffix
= QWORD_MNEM_SUFFIX
;
4770 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4771 guess_suffix
= WORD_MNEM_SUFFIX
;
4773 for (op
= i
.operands
; --op
>= 0;)
4774 if (operand_type_check (i
.types
[op
], imm
))
4776 switch (i
.op
[op
].imms
->X_op
)
4779 /* If a suffix is given, this operand may be shortened. */
4780 switch (guess_suffix
)
4782 case LONG_MNEM_SUFFIX
:
4783 i
.types
[op
].bitfield
.imm32
= 1;
4784 i
.types
[op
].bitfield
.imm64
= 1;
4786 case WORD_MNEM_SUFFIX
:
4787 i
.types
[op
].bitfield
.imm16
= 1;
4788 i
.types
[op
].bitfield
.imm32
= 1;
4789 i
.types
[op
].bitfield
.imm32s
= 1;
4790 i
.types
[op
].bitfield
.imm64
= 1;
4792 case BYTE_MNEM_SUFFIX
:
4793 i
.types
[op
].bitfield
.imm8
= 1;
4794 i
.types
[op
].bitfield
.imm8s
= 1;
4795 i
.types
[op
].bitfield
.imm16
= 1;
4796 i
.types
[op
].bitfield
.imm32
= 1;
4797 i
.types
[op
].bitfield
.imm32s
= 1;
4798 i
.types
[op
].bitfield
.imm64
= 1;
4802 /* If this operand is at most 16 bits, convert it
4803 to a signed 16 bit number before trying to see
4804 whether it will fit in an even smaller size.
4805 This allows a 16-bit operand such as $0xffe0 to
4806 be recognised as within Imm8S range. */
4807 if ((i
.types
[op
].bitfield
.imm16
)
4808 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4810 i
.op
[op
].imms
->X_add_number
=
4811 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4814 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4815 if ((i
.types
[op
].bitfield
.imm32
)
4816 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4819 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4820 ^ ((offsetT
) 1 << 31))
4821 - ((offsetT
) 1 << 31));
4825 = operand_type_or (i
.types
[op
],
4826 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4828 /* We must avoid matching of Imm32 templates when 64bit
4829 only immediate is available. */
4830 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4831 i
.types
[op
].bitfield
.imm32
= 0;
4838 /* Symbols and expressions. */
4840 /* Convert symbolic operand to proper sizes for matching, but don't
4841 prevent matching a set of insns that only supports sizes other
4842 than those matching the insn suffix. */
4844 i386_operand_type mask
, allowed
;
4845 const insn_template
*t
;
4847 operand_type_set (&mask
, 0);
4848 operand_type_set (&allowed
, 0);
4850 for (t
= current_templates
->start
;
4851 t
< current_templates
->end
;
4853 allowed
= operand_type_or (allowed
,
4854 t
->operand_types
[op
]);
4855 switch (guess_suffix
)
4857 case QWORD_MNEM_SUFFIX
:
4858 mask
.bitfield
.imm64
= 1;
4859 mask
.bitfield
.imm32s
= 1;
4861 case LONG_MNEM_SUFFIX
:
4862 mask
.bitfield
.imm32
= 1;
4864 case WORD_MNEM_SUFFIX
:
4865 mask
.bitfield
.imm16
= 1;
4867 case BYTE_MNEM_SUFFIX
:
4868 mask
.bitfield
.imm8
= 1;
4873 allowed
= operand_type_and (mask
, allowed
);
4874 if (!operand_type_all_zero (&allowed
))
4875 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4882 /* Try to use the smallest displacement type too. */
4884 optimize_disp (void)
4888 for (op
= i
.operands
; --op
>= 0;)
4889 if (operand_type_check (i
.types
[op
], disp
))
4891 if (i
.op
[op
].disps
->X_op
== O_constant
)
4893 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4895 if (i
.types
[op
].bitfield
.disp16
4896 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4898 /* If this operand is at most 16 bits, convert
4899 to a signed 16 bit number and don't use 64bit
4901 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4902 i
.types
[op
].bitfield
.disp64
= 0;
4905 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4906 if (i
.types
[op
].bitfield
.disp32
4907 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4909 /* If this operand is at most 32 bits, convert
4910 to a signed 32 bit number and don't use 64bit
4912 op_disp
&= (((offsetT
) 2 << 31) - 1);
4913 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4914 i
.types
[op
].bitfield
.disp64
= 0;
4917 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4919 i
.types
[op
].bitfield
.disp8
= 0;
4920 i
.types
[op
].bitfield
.disp16
= 0;
4921 i
.types
[op
].bitfield
.disp32
= 0;
4922 i
.types
[op
].bitfield
.disp32s
= 0;
4923 i
.types
[op
].bitfield
.disp64
= 0;
4927 else if (flag_code
== CODE_64BIT
)
4929 if (fits_in_signed_long (op_disp
))
4931 i
.types
[op
].bitfield
.disp64
= 0;
4932 i
.types
[op
].bitfield
.disp32s
= 1;
4934 if (i
.prefix
[ADDR_PREFIX
]
4935 && fits_in_unsigned_long (op_disp
))
4936 i
.types
[op
].bitfield
.disp32
= 1;
4938 if ((i
.types
[op
].bitfield
.disp32
4939 || i
.types
[op
].bitfield
.disp32s
4940 || i
.types
[op
].bitfield
.disp16
)
4941 && fits_in_disp8 (op_disp
))
4942 i
.types
[op
].bitfield
.disp8
= 1;
4944 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4945 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4947 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4948 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4949 i
.types
[op
].bitfield
.disp8
= 0;
4950 i
.types
[op
].bitfield
.disp16
= 0;
4951 i
.types
[op
].bitfield
.disp32
= 0;
4952 i
.types
[op
].bitfield
.disp32s
= 0;
4953 i
.types
[op
].bitfield
.disp64
= 0;
4956 /* We only support 64bit displacement on constants. */
4957 i
.types
[op
].bitfield
.disp64
= 0;
4961 /* Check if operands are valid for the instruction. */
4964 check_VecOperands (const insn_template
*t
)
4968 /* Without VSIB byte, we can't have a vector register for index. */
4969 if (!t
->opcode_modifier
.vecsib
4971 && (i
.index_reg
->reg_type
.bitfield
.xmmword
4972 || i
.index_reg
->reg_type
.bitfield
.ymmword
4973 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
4975 i
.error
= unsupported_vector_index_register
;
4979 /* Check if default mask is allowed. */
4980 if (t
->opcode_modifier
.nodefmask
4981 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4983 i
.error
= no_default_mask
;
4987 /* For VSIB byte, we need a vector register for index, and all vector
4988 registers must be distinct. */
4989 if (t
->opcode_modifier
.vecsib
)
4992 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4993 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
4994 || (t
->opcode_modifier
.vecsib
== VecSIB256
4995 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
4996 || (t
->opcode_modifier
.vecsib
== VecSIB512
4997 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
4999 i
.error
= invalid_vsib_address
;
5003 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5004 if (i
.reg_operands
== 2 && !i
.mask
)
5006 gas_assert (i
.types
[0].bitfield
.regsimd
);
5007 gas_assert (i
.types
[0].bitfield
.xmmword
5008 || i
.types
[0].bitfield
.ymmword
);
5009 gas_assert (i
.types
[2].bitfield
.regsimd
);
5010 gas_assert (i
.types
[2].bitfield
.xmmword
5011 || i
.types
[2].bitfield
.ymmword
);
5012 if (operand_check
== check_none
)
5014 if (register_number (i
.op
[0].regs
)
5015 != register_number (i
.index_reg
)
5016 && register_number (i
.op
[2].regs
)
5017 != register_number (i
.index_reg
)
5018 && register_number (i
.op
[0].regs
)
5019 != register_number (i
.op
[2].regs
))
5021 if (operand_check
== check_error
)
5023 i
.error
= invalid_vector_register_set
;
5026 as_warn (_("mask, index, and destination registers should be distinct"));
5028 else if (i
.reg_operands
== 1 && i
.mask
)
5030 if (i
.types
[1].bitfield
.regsimd
5031 && (i
.types
[1].bitfield
.xmmword
5032 || i
.types
[1].bitfield
.ymmword
5033 || i
.types
[1].bitfield
.zmmword
)
5034 && (register_number (i
.op
[1].regs
)
5035 == register_number (i
.index_reg
)))
5037 if (operand_check
== check_error
)
5039 i
.error
= invalid_vector_register_set
;
5042 if (operand_check
!= check_none
)
5043 as_warn (_("index and destination registers should be distinct"));
5048 /* Check if broadcast is supported by the instruction and is applied
5049 to the memory operand. */
5052 i386_operand_type type
, overlap
;
5054 /* Check if specified broadcast is supported in this instruction,
5055 and it's applied to memory operand of DWORD or QWORD type. */
5056 op
= i
.broadcast
->operand
;
5057 if (!t
->opcode_modifier
.broadcast
5058 || !i
.types
[op
].bitfield
.mem
5059 || (!i
.types
[op
].bitfield
.unspecified
5060 && (t
->operand_types
[op
].bitfield
.dword
5061 ? !i
.types
[op
].bitfield
.dword
5062 : !i
.types
[op
].bitfield
.qword
)))
5065 i
.error
= unsupported_broadcast
;
5069 operand_type_set (&type
, 0);
5070 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5073 type
.bitfield
.qword
= 1;
5076 type
.bitfield
.xmmword
= 1;
5079 type
.bitfield
.ymmword
= 1;
5082 type
.bitfield
.zmmword
= 1;
5088 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5089 if (operand_type_all_zero (&overlap
))
5092 if (t
->opcode_modifier
.checkregsize
)
5096 for (j
= 0; j
< i
.operands
; ++j
)
5099 && !operand_type_register_match(i
.types
[j
],
5100 t
->operand_types
[j
],
5102 t
->operand_types
[op
]))
5107 /* If broadcast is supported in this instruction, we need to check if
5108 operand of one-element size isn't specified without broadcast. */
5109 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5111 /* Find memory operand. */
5112 for (op
= 0; op
< i
.operands
; op
++)
5113 if (operand_type_check (i
.types
[op
], anymem
))
5115 gas_assert (op
< i
.operands
);
5116 /* Check size of the memory operand. */
5117 if (t
->operand_types
[op
].bitfield
.dword
5118 ? i
.types
[op
].bitfield
.dword
5119 : i
.types
[op
].bitfield
.qword
)
5121 i
.error
= broadcast_needed
;
5126 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5128 /* Check if requested masking is supported. */
5130 && (!t
->opcode_modifier
.masking
5132 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5134 i
.error
= unsupported_masking
;
5138 /* Check if masking is applied to dest operand. */
5139 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5141 i
.error
= mask_not_on_destination
;
5148 if ((i
.rounding
->type
!= saeonly
5149 && !t
->opcode_modifier
.staticrounding
)
5150 || (i
.rounding
->type
== saeonly
5151 && (t
->opcode_modifier
.staticrounding
5152 || !t
->opcode_modifier
.sae
)))
5154 i
.error
= unsupported_rc_sae
;
5157 /* If the instruction has several immediate operands and one of
5158 them is rounding, the rounding operand should be the last
5159 immediate operand. */
5160 if (i
.imm_operands
> 1
5161 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5163 i
.error
= rc_sae_operand_not_last_imm
;
5168 /* Check vector Disp8 operand. */
5169 if (t
->opcode_modifier
.disp8memshift
5170 && i
.disp_encoding
!= disp_encoding_32bit
)
5173 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5175 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5177 for (op
= 0; op
< i
.operands
; op
++)
5178 if (operand_type_check (i
.types
[op
], disp
)
5179 && i
.op
[op
].disps
->X_op
== O_constant
)
5181 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5183 i
.types
[op
].bitfield
.disp8
= 1;
5186 i
.types
[op
].bitfield
.disp8
= 0;
5195 /* Check if operands are valid for the instruction. Update VEX
5199 VEX_check_operands (const insn_template
*t
)
5201 if (i
.vec_encoding
== vex_encoding_evex
)
5203 /* This instruction must be encoded with EVEX prefix. */
5204 if (!is_evex_encoding (t
))
5206 i
.error
= unsupported
;
5212 if (!t
->opcode_modifier
.vex
)
5214 /* This instruction template doesn't have VEX prefix. */
5215 if (i
.vec_encoding
!= vex_encoding_default
)
5217 i
.error
= unsupported
;
5223 /* Only check VEX_Imm4, which must be the first operand. */
5224 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5226 if (i
.op
[0].imms
->X_op
!= O_constant
5227 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5233 /* Turn off Imm8 so that update_imm won't complain. */
5234 i
.types
[0] = vec_imm4
;
5240 static const insn_template
*
5241 match_template (char mnem_suffix
)
5243 /* Points to template once we've found it. */
5244 const insn_template
*t
;
5245 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5246 i386_operand_type overlap4
;
5247 unsigned int found_reverse_match
;
5248 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5249 i386_operand_type operand_types
[MAX_OPERANDS
];
5250 int addr_prefix_disp
;
5252 unsigned int found_cpu_match
;
5253 unsigned int check_register
;
5254 enum i386_error specific_error
= 0;
5256 #if MAX_OPERANDS != 5
5257 # error "MAX_OPERANDS must be 5."
5260 found_reverse_match
= 0;
5261 addr_prefix_disp
= -1;
5263 memset (&suffix_check
, 0, sizeof (suffix_check
));
5264 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5265 suffix_check
.no_bsuf
= 1;
5266 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5267 suffix_check
.no_wsuf
= 1;
5268 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5269 suffix_check
.no_ssuf
= 1;
5270 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5271 suffix_check
.no_lsuf
= 1;
5272 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5273 suffix_check
.no_qsuf
= 1;
5274 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5275 suffix_check
.no_ldsuf
= 1;
5277 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5280 switch (mnem_suffix
)
5282 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5283 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5284 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5285 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5286 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5290 /* Must have right number of operands. */
5291 i
.error
= number_of_operands_mismatch
;
5293 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5295 addr_prefix_disp
= -1;
5297 if (i
.operands
!= t
->operands
)
5300 /* Check processor support. */
5301 i
.error
= unsupported
;
5302 found_cpu_match
= (cpu_flags_match (t
)
5303 == CPU_FLAGS_PERFECT_MATCH
);
5304 if (!found_cpu_match
)
5307 /* Check AT&T mnemonic. */
5308 i
.error
= unsupported_with_intel_mnemonic
;
5309 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5312 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5313 i
.error
= unsupported_syntax
;
5314 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5315 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5316 || (intel64
&& t
->opcode_modifier
.amd64
)
5317 || (!intel64
&& t
->opcode_modifier
.intel64
))
5320 /* Check the suffix, except for some instructions in intel mode. */
5321 i
.error
= invalid_instruction_suffix
;
5322 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5323 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5324 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5325 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5326 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5327 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5328 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5330 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5331 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5332 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5333 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5334 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5335 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5336 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5339 if (!operand_size_match (t
))
5342 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5343 operand_types
[j
] = t
->operand_types
[j
];
5345 /* In general, don't allow 64-bit operands in 32-bit mode. */
5346 if (i
.suffix
== QWORD_MNEM_SUFFIX
5347 && flag_code
!= CODE_64BIT
5349 ? (!t
->opcode_modifier
.ignoresize
5350 && !intel_float_operand (t
->name
))
5351 : intel_float_operand (t
->name
) != 2)
5352 && ((!operand_types
[0].bitfield
.regmmx
5353 && !operand_types
[0].bitfield
.regsimd
)
5354 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5355 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5356 && (t
->base_opcode
!= 0x0fc7
5357 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5360 /* In general, don't allow 32-bit operands on pre-386. */
5361 else if (i
.suffix
== LONG_MNEM_SUFFIX
5362 && !cpu_arch_flags
.bitfield
.cpui386
5364 ? (!t
->opcode_modifier
.ignoresize
5365 && !intel_float_operand (t
->name
))
5366 : intel_float_operand (t
->name
) != 2)
5367 && ((!operand_types
[0].bitfield
.regmmx
5368 && !operand_types
[0].bitfield
.regsimd
)
5369 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5370 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5373 /* Do not verify operands when there are none. */
5377 /* We've found a match; break out of loop. */
5381 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5382 into Disp32/Disp16/Disp32 operand. */
5383 if (i
.prefix
[ADDR_PREFIX
] != 0)
5385 /* There should be only one Disp operand. */
5389 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5391 if (operand_types
[j
].bitfield
.disp16
)
5393 addr_prefix_disp
= j
;
5394 operand_types
[j
].bitfield
.disp32
= 1;
5395 operand_types
[j
].bitfield
.disp16
= 0;
5401 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5403 if (operand_types
[j
].bitfield
.disp32
)
5405 addr_prefix_disp
= j
;
5406 operand_types
[j
].bitfield
.disp32
= 0;
5407 operand_types
[j
].bitfield
.disp16
= 1;
5413 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5415 if (operand_types
[j
].bitfield
.disp64
)
5417 addr_prefix_disp
= j
;
5418 operand_types
[j
].bitfield
.disp64
= 0;
5419 operand_types
[j
].bitfield
.disp32
= 1;
5427 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5428 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5431 /* We check register size if needed. */
5432 check_register
= t
->opcode_modifier
.checkregsize
;
5433 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5434 switch (t
->operands
)
5437 if (!operand_type_match (overlap0
, i
.types
[0]))
5441 /* xchg %eax, %eax is a special case. It is an alias for nop
5442 only in 32bit mode and we can use opcode 0x90. In 64bit
5443 mode, we can't use 0x90 for xchg %eax, %eax since it should
5444 zero-extend %eax to %rax. */
5445 if (flag_code
== CODE_64BIT
5446 && t
->base_opcode
== 0x90
5447 && operand_type_equal (&i
.types
[0], &acc32
)
5448 && operand_type_equal (&i
.types
[1], &acc32
))
5450 /* xrelease mov %eax, <disp> is another special case. It must not
5451 match the accumulator-only encoding of mov. */
5452 if (flag_code
!= CODE_64BIT
5454 && t
->base_opcode
== 0xa0
5455 && i
.types
[0].bitfield
.acc
5456 && operand_type_check (i
.types
[1], anymem
))
5458 /* If we want store form, we reverse direction of operands. */
5459 if (i
.dir_encoding
== dir_encoding_store
5460 && t
->opcode_modifier
.d
)
5465 /* If we want store form, we skip the current load. */
5466 if (i
.dir_encoding
== dir_encoding_store
5467 && i
.mem_operands
== 0
5468 && t
->opcode_modifier
.load
)
5473 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5474 if (!operand_type_match (overlap0
, i
.types
[0])
5475 || !operand_type_match (overlap1
, i
.types
[1])
5477 && !operand_type_register_match (i
.types
[0],
5482 /* Check if other direction is valid ... */
5483 if (!t
->opcode_modifier
.d
)
5487 /* Try reversing direction of operands. */
5488 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5489 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5490 if (!operand_type_match (overlap0
, i
.types
[0])
5491 || !operand_type_match (overlap1
, i
.types
[1])
5493 && !operand_type_register_match (i
.types
[0],
5498 /* Does not match either direction. */
5501 /* found_reverse_match holds which of D or FloatR
5503 if (!t
->opcode_modifier
.d
)
5504 found_reverse_match
= 0;
5505 else if (operand_types
[0].bitfield
.tbyte
)
5506 found_reverse_match
= Opcode_FloatD
;
5508 found_reverse_match
= Opcode_D
;
5509 if (t
->opcode_modifier
.floatr
)
5510 found_reverse_match
|= Opcode_FloatR
;
5514 /* Found a forward 2 operand match here. */
5515 switch (t
->operands
)
5518 overlap4
= operand_type_and (i
.types
[4],
5522 overlap3
= operand_type_and (i
.types
[3],
5526 overlap2
= operand_type_and (i
.types
[2],
5531 switch (t
->operands
)
5534 if (!operand_type_match (overlap4
, i
.types
[4])
5535 || !operand_type_register_match (i
.types
[3],
5542 if (!operand_type_match (overlap3
, i
.types
[3])
5544 && (!operand_type_register_match (i
.types
[1],
5548 || !operand_type_register_match (i
.types
[2],
5551 operand_types
[3]))))
5555 /* Here we make use of the fact that there are no
5556 reverse match 3 operand instructions. */
5557 if (!operand_type_match (overlap2
, i
.types
[2])
5559 && (!operand_type_register_match (i
.types
[0],
5563 || !operand_type_register_match (i
.types
[1],
5566 operand_types
[2]))))
5571 /* Found either forward/reverse 2, 3 or 4 operand match here:
5572 slip through to break. */
5574 if (!found_cpu_match
)
5576 found_reverse_match
= 0;
5580 /* Check if vector and VEX operands are valid. */
5581 if (check_VecOperands (t
) || VEX_check_operands (t
))
5583 specific_error
= i
.error
;
5587 /* We've found a match; break out of loop. */
5591 if (t
== current_templates
->end
)
5593 /* We found no match. */
5594 const char *err_msg
;
5595 switch (specific_error
? specific_error
: i
.error
)
5599 case operand_size_mismatch
:
5600 err_msg
= _("operand size mismatch");
5602 case operand_type_mismatch
:
5603 err_msg
= _("operand type mismatch");
5605 case register_type_mismatch
:
5606 err_msg
= _("register type mismatch");
5608 case number_of_operands_mismatch
:
5609 err_msg
= _("number of operands mismatch");
5611 case invalid_instruction_suffix
:
5612 err_msg
= _("invalid instruction suffix");
5615 err_msg
= _("constant doesn't fit in 4 bits");
5617 case unsupported_with_intel_mnemonic
:
5618 err_msg
= _("unsupported with Intel mnemonic");
5620 case unsupported_syntax
:
5621 err_msg
= _("unsupported syntax");
5624 as_bad (_("unsupported instruction `%s'"),
5625 current_templates
->start
->name
);
5627 case invalid_vsib_address
:
5628 err_msg
= _("invalid VSIB address");
5630 case invalid_vector_register_set
:
5631 err_msg
= _("mask, index, and destination registers must be distinct");
5633 case unsupported_vector_index_register
:
5634 err_msg
= _("unsupported vector index register");
5636 case unsupported_broadcast
:
5637 err_msg
= _("unsupported broadcast");
5639 case broadcast_not_on_src_operand
:
5640 err_msg
= _("broadcast not on source memory operand");
5642 case broadcast_needed
:
5643 err_msg
= _("broadcast is needed for operand of such type");
5645 case unsupported_masking
:
5646 err_msg
= _("unsupported masking");
5648 case mask_not_on_destination
:
5649 err_msg
= _("mask not on destination operand");
5651 case no_default_mask
:
5652 err_msg
= _("default mask isn't allowed");
5654 case unsupported_rc_sae
:
5655 err_msg
= _("unsupported static rounding/sae");
5657 case rc_sae_operand_not_last_imm
:
5659 err_msg
= _("RC/SAE operand must precede immediate operands");
5661 err_msg
= _("RC/SAE operand must follow immediate operands");
5663 case invalid_register_operand
:
5664 err_msg
= _("invalid register operand");
5667 as_bad (_("%s for `%s'"), err_msg
,
5668 current_templates
->start
->name
);
5672 if (!quiet_warnings
)
5675 && (i
.types
[0].bitfield
.jumpabsolute
5676 != operand_types
[0].bitfield
.jumpabsolute
))
5678 as_warn (_("indirect %s without `*'"), t
->name
);
5681 if (t
->opcode_modifier
.isprefix
5682 && t
->opcode_modifier
.ignoresize
)
5684 /* Warn them that a data or address size prefix doesn't
5685 affect assembly of the next line of code. */
5686 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5690 /* Copy the template we found. */
5693 if (addr_prefix_disp
!= -1)
5694 i
.tm
.operand_types
[addr_prefix_disp
]
5695 = operand_types
[addr_prefix_disp
];
5697 if (found_reverse_match
)
5699 /* If we found a reverse match we must alter the opcode
5700 direction bit. found_reverse_match holds bits to change
5701 (different for int & float insns). */
5703 i
.tm
.base_opcode
^= found_reverse_match
;
5705 i
.tm
.operand_types
[0] = operand_types
[1];
5706 i
.tm
.operand_types
[1] = operand_types
[0];
5715 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5716 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5718 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5720 as_bad (_("`%s' operand %d must use `%ses' segment"),
5726 /* There's only ever one segment override allowed per instruction.
5727 This instruction possibly has a legal segment override on the
5728 second operand, so copy the segment to where non-string
5729 instructions store it, allowing common code. */
5730 i
.seg
[0] = i
.seg
[1];
5732 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5734 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5736 as_bad (_("`%s' operand %d must use `%ses' segment"),
5747 process_suffix (void)
5749 /* If matched instruction specifies an explicit instruction mnemonic
5751 if (i
.tm
.opcode_modifier
.size16
)
5752 i
.suffix
= WORD_MNEM_SUFFIX
;
5753 else if (i
.tm
.opcode_modifier
.size32
)
5754 i
.suffix
= LONG_MNEM_SUFFIX
;
5755 else if (i
.tm
.opcode_modifier
.size64
)
5756 i
.suffix
= QWORD_MNEM_SUFFIX
;
5757 else if (i
.reg_operands
)
5759 /* If there's no instruction mnemonic suffix we try to invent one
5760 based on register operands. */
5763 /* We take i.suffix from the last register operand specified,
5764 Destination register type is more significant than source
5765 register type. crc32 in SSE4.2 prefers source register
5767 if (i
.tm
.base_opcode
== 0xf20f38f1)
5769 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5770 i
.suffix
= WORD_MNEM_SUFFIX
;
5771 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5772 i
.suffix
= LONG_MNEM_SUFFIX
;
5773 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5774 i
.suffix
= QWORD_MNEM_SUFFIX
;
5776 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5778 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5779 i
.suffix
= BYTE_MNEM_SUFFIX
;
5786 if (i
.tm
.base_opcode
== 0xf20f38f1
5787 || i
.tm
.base_opcode
== 0xf20f38f0)
5789 /* We have to know the operand size for crc32. */
5790 as_bad (_("ambiguous memory operand size for `%s`"),
5795 for (op
= i
.operands
; --op
>= 0;)
5796 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5797 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5799 if (!i
.types
[op
].bitfield
.reg
)
5801 if (i
.types
[op
].bitfield
.byte
)
5802 i
.suffix
= BYTE_MNEM_SUFFIX
;
5803 else if (i
.types
[op
].bitfield
.word
)
5804 i
.suffix
= WORD_MNEM_SUFFIX
;
5805 else if (i
.types
[op
].bitfield
.dword
)
5806 i
.suffix
= LONG_MNEM_SUFFIX
;
5807 else if (i
.types
[op
].bitfield
.qword
)
5808 i
.suffix
= QWORD_MNEM_SUFFIX
;
5815 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5818 && i
.tm
.opcode_modifier
.ignoresize
5819 && i
.tm
.opcode_modifier
.no_bsuf
)
5821 else if (!check_byte_reg ())
5824 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5827 && i
.tm
.opcode_modifier
.ignoresize
5828 && i
.tm
.opcode_modifier
.no_lsuf
5829 && !i
.tm
.opcode_modifier
.todword
5830 && !i
.tm
.opcode_modifier
.toqword
)
5832 else if (!check_long_reg ())
5835 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5838 && i
.tm
.opcode_modifier
.ignoresize
5839 && i
.tm
.opcode_modifier
.no_qsuf
5840 && !i
.tm
.opcode_modifier
.todword
5841 && !i
.tm
.opcode_modifier
.toqword
)
5843 else if (!check_qword_reg ())
5846 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5849 && i
.tm
.opcode_modifier
.ignoresize
5850 && i
.tm
.opcode_modifier
.no_wsuf
)
5852 else if (!check_word_reg ())
5855 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5856 /* Do nothing if the instruction is going to ignore the prefix. */
5861 else if (i
.tm
.opcode_modifier
.defaultsize
5863 /* exclude fldenv/frstor/fsave/fstenv */
5864 && i
.tm
.opcode_modifier
.no_ssuf
)
5866 i
.suffix
= stackop_size
;
5868 else if (intel_syntax
5870 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5871 || i
.tm
.opcode_modifier
.jumpbyte
5872 || i
.tm
.opcode_modifier
.jumpintersegment
5873 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5874 && i
.tm
.extension_opcode
<= 3)))
5879 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5881 i
.suffix
= QWORD_MNEM_SUFFIX
;
5886 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5887 i
.suffix
= LONG_MNEM_SUFFIX
;
5890 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5891 i
.suffix
= WORD_MNEM_SUFFIX
;
5900 if (i
.tm
.opcode_modifier
.w
)
5902 as_bad (_("no instruction mnemonic suffix given and "
5903 "no register operands; can't size instruction"));
5909 unsigned int suffixes
;
5911 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5912 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5914 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5916 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5918 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5920 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5923 /* There are more than suffix matches. */
5924 if (i
.tm
.opcode_modifier
.w
5925 || ((suffixes
& (suffixes
- 1))
5926 && !i
.tm
.opcode_modifier
.defaultsize
5927 && !i
.tm
.opcode_modifier
.ignoresize
))
5929 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5935 /* Change the opcode based on the operand size given by i.suffix. */
5938 /* Size floating point instruction. */
5939 case LONG_MNEM_SUFFIX
:
5940 if (i
.tm
.opcode_modifier
.floatmf
)
5942 i
.tm
.base_opcode
^= 4;
5946 case WORD_MNEM_SUFFIX
:
5947 case QWORD_MNEM_SUFFIX
:
5948 /* It's not a byte, select word/dword operation. */
5949 if (i
.tm
.opcode_modifier
.w
)
5951 if (i
.tm
.opcode_modifier
.shortform
)
5952 i
.tm
.base_opcode
|= 8;
5954 i
.tm
.base_opcode
|= 1;
5957 case SHORT_MNEM_SUFFIX
:
5958 /* Now select between word & dword operations via the operand
5959 size prefix, except for instructions that will ignore this
5961 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5963 /* The address size override prefix changes the size of the
5965 if ((flag_code
== CODE_32BIT
5966 && i
.op
->regs
[0].reg_type
.bitfield
.word
)
5967 || (flag_code
!= CODE_32BIT
5968 && i
.op
->regs
[0].reg_type
.bitfield
.dword
))
5969 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5972 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5973 && !i
.tm
.opcode_modifier
.ignoresize
5974 && !i
.tm
.opcode_modifier
.floatmf
5975 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5976 || (flag_code
== CODE_64BIT
5977 && i
.tm
.opcode_modifier
.jumpbyte
)))
5979 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5981 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5982 prefix
= ADDR_PREFIX_OPCODE
;
5984 if (!add_prefix (prefix
))
5988 /* Set mode64 for an operand. */
5989 if (i
.suffix
== QWORD_MNEM_SUFFIX
5990 && flag_code
== CODE_64BIT
5991 && !i
.tm
.opcode_modifier
.norex64
5992 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5994 && ! (i
.operands
== 2
5995 && i
.tm
.base_opcode
== 0x90
5996 && i
.tm
.extension_opcode
== None
5997 && operand_type_equal (&i
.types
[0], &acc64
)
5998 && operand_type_equal (&i
.types
[1], &acc64
)))
6008 check_byte_reg (void)
6012 for (op
= i
.operands
; --op
>= 0;)
6014 /* Skip non-register operands. */
6015 if (!i
.types
[op
].bitfield
.reg
)
6018 /* If this is an eight bit register, it's OK. If it's the 16 or
6019 32 bit version of an eight bit register, we will just use the
6020 low portion, and that's OK too. */
6021 if (i
.types
[op
].bitfield
.byte
)
6024 /* I/O port address operands are OK too. */
6025 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6028 /* crc32 doesn't generate this warning. */
6029 if (i
.tm
.base_opcode
== 0xf20f38f0)
6032 if ((i
.types
[op
].bitfield
.word
6033 || i
.types
[op
].bitfield
.dword
6034 || i
.types
[op
].bitfield
.qword
)
6035 && i
.op
[op
].regs
->reg_num
< 4
6036 /* Prohibit these changes in 64bit mode, since the lowering
6037 would be more complicated. */
6038 && flag_code
!= CODE_64BIT
)
6040 #if REGISTER_WARNINGS
6041 if (!quiet_warnings
)
6042 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6044 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6045 ? REGNAM_AL
- REGNAM_AX
6046 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6048 i
.op
[op
].regs
->reg_name
,
6053 /* Any other register is bad. */
6054 if (i
.types
[op
].bitfield
.reg
6055 || i
.types
[op
].bitfield
.regmmx
6056 || i
.types
[op
].bitfield
.regsimd
6057 || i
.types
[op
].bitfield
.sreg2
6058 || i
.types
[op
].bitfield
.sreg3
6059 || i
.types
[op
].bitfield
.control
6060 || i
.types
[op
].bitfield
.debug
6061 || i
.types
[op
].bitfield
.test
)
6063 as_bad (_("`%s%s' not allowed with `%s%c'"),
6065 i
.op
[op
].regs
->reg_name
,
6075 check_long_reg (void)
6079 for (op
= i
.operands
; --op
>= 0;)
6080 /* Skip non-register operands. */
6081 if (!i
.types
[op
].bitfield
.reg
)
6083 /* Reject eight bit registers, except where the template requires
6084 them. (eg. movzb) */
6085 else if (i
.types
[op
].bitfield
.byte
6086 && (i
.tm
.operand_types
[op
].bitfield
.reg
6087 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6088 && (i
.tm
.operand_types
[op
].bitfield
.word
6089 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6091 as_bad (_("`%s%s' not allowed with `%s%c'"),
6093 i
.op
[op
].regs
->reg_name
,
6098 /* Warn if the e prefix on a general reg is missing. */
6099 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6100 && i
.types
[op
].bitfield
.word
6101 && (i
.tm
.operand_types
[op
].bitfield
.reg
6102 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6103 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6105 /* Prohibit these changes in the 64bit mode, since the
6106 lowering is more complicated. */
6107 if (flag_code
== CODE_64BIT
)
6109 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6110 register_prefix
, i
.op
[op
].regs
->reg_name
,
6114 #if REGISTER_WARNINGS
6115 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6117 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6118 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6121 /* Warn if the r prefix on a general reg is present. */
6122 else if (i
.types
[op
].bitfield
.qword
6123 && (i
.tm
.operand_types
[op
].bitfield
.reg
6124 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6125 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6128 && i
.tm
.opcode_modifier
.toqword
6129 && !i
.types
[0].bitfield
.regsimd
)
6131 /* Convert to QWORD. We want REX byte. */
6132 i
.suffix
= QWORD_MNEM_SUFFIX
;
6136 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6137 register_prefix
, i
.op
[op
].regs
->reg_name
,
6146 check_qword_reg (void)
6150 for (op
= i
.operands
; --op
>= 0; )
6151 /* Skip non-register operands. */
6152 if (!i
.types
[op
].bitfield
.reg
)
6154 /* Reject eight bit registers, except where the template requires
6155 them. (eg. movzb) */
6156 else if (i
.types
[op
].bitfield
.byte
6157 && (i
.tm
.operand_types
[op
].bitfield
.reg
6158 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6159 && (i
.tm
.operand_types
[op
].bitfield
.word
6160 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6162 as_bad (_("`%s%s' not allowed with `%s%c'"),
6164 i
.op
[op
].regs
->reg_name
,
6169 /* Warn if the r prefix on a general reg is missing. */
6170 else if ((i
.types
[op
].bitfield
.word
6171 || i
.types
[op
].bitfield
.dword
)
6172 && (i
.tm
.operand_types
[op
].bitfield
.reg
6173 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6174 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6176 /* Prohibit these changes in the 64bit mode, since the
6177 lowering is more complicated. */
6179 && i
.tm
.opcode_modifier
.todword
6180 && !i
.types
[0].bitfield
.regsimd
)
6182 /* Convert to DWORD. We don't want REX byte. */
6183 i
.suffix
= LONG_MNEM_SUFFIX
;
6187 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6188 register_prefix
, i
.op
[op
].regs
->reg_name
,
6197 check_word_reg (void)
6200 for (op
= i
.operands
; --op
>= 0;)
6201 /* Skip non-register operands. */
6202 if (!i
.types
[op
].bitfield
.reg
)
6204 /* Reject eight bit registers, except where the template requires
6205 them. (eg. movzb) */
6206 else if (i
.types
[op
].bitfield
.byte
6207 && (i
.tm
.operand_types
[op
].bitfield
.reg
6208 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6209 && (i
.tm
.operand_types
[op
].bitfield
.word
6210 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6212 as_bad (_("`%s%s' not allowed with `%s%c'"),
6214 i
.op
[op
].regs
->reg_name
,
6219 /* Warn if the e or r prefix on a general reg is present. */
6220 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6221 && (i
.types
[op
].bitfield
.dword
6222 || i
.types
[op
].bitfield
.qword
)
6223 && (i
.tm
.operand_types
[op
].bitfield
.reg
6224 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6225 && i
.tm
.operand_types
[op
].bitfield
.word
)
6227 /* Prohibit these changes in the 64bit mode, since the
6228 lowering is more complicated. */
6229 if (flag_code
== CODE_64BIT
)
6231 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6232 register_prefix
, i
.op
[op
].regs
->reg_name
,
6236 #if REGISTER_WARNINGS
6237 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6239 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6240 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6247 update_imm (unsigned int j
)
6249 i386_operand_type overlap
= i
.types
[j
];
6250 if ((overlap
.bitfield
.imm8
6251 || overlap
.bitfield
.imm8s
6252 || overlap
.bitfield
.imm16
6253 || overlap
.bitfield
.imm32
6254 || overlap
.bitfield
.imm32s
6255 || overlap
.bitfield
.imm64
)
6256 && !operand_type_equal (&overlap
, &imm8
)
6257 && !operand_type_equal (&overlap
, &imm8s
)
6258 && !operand_type_equal (&overlap
, &imm16
)
6259 && !operand_type_equal (&overlap
, &imm32
)
6260 && !operand_type_equal (&overlap
, &imm32s
)
6261 && !operand_type_equal (&overlap
, &imm64
))
6265 i386_operand_type temp
;
6267 operand_type_set (&temp
, 0);
6268 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6270 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6271 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6273 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6274 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6275 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6277 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6278 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6281 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6284 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6285 || operand_type_equal (&overlap
, &imm16_32
)
6286 || operand_type_equal (&overlap
, &imm16_32s
))
6288 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6293 if (!operand_type_equal (&overlap
, &imm8
)
6294 && !operand_type_equal (&overlap
, &imm8s
)
6295 && !operand_type_equal (&overlap
, &imm16
)
6296 && !operand_type_equal (&overlap
, &imm32
)
6297 && !operand_type_equal (&overlap
, &imm32s
)
6298 && !operand_type_equal (&overlap
, &imm64
))
6300 as_bad (_("no instruction mnemonic suffix given; "
6301 "can't determine immediate size"));
6305 i
.types
[j
] = overlap
;
6315 /* Update the first 2 immediate operands. */
6316 n
= i
.operands
> 2 ? 2 : i
.operands
;
6319 for (j
= 0; j
< n
; j
++)
6320 if (update_imm (j
) == 0)
6323 /* The 3rd operand can't be immediate operand. */
6324 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6331 process_operands (void)
6333 /* Default segment register this instruction will use for memory
6334 accesses. 0 means unknown. This is only for optimizing out
6335 unnecessary segment overrides. */
6336 const seg_entry
*default_seg
= 0;
6338 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6340 unsigned int dupl
= i
.operands
;
6341 unsigned int dest
= dupl
- 1;
6344 /* The destination must be an xmm register. */
6345 gas_assert (i
.reg_operands
6346 && MAX_OPERANDS
> dupl
6347 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6349 if (i
.tm
.operand_types
[0].bitfield
.acc
6350 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6352 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6354 /* Keep xmm0 for instructions with VEX prefix and 3
6356 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6357 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6362 /* We remove the first xmm0 and keep the number of
6363 operands unchanged, which in fact duplicates the
6365 for (j
= 1; j
< i
.operands
; j
++)
6367 i
.op
[j
- 1] = i
.op
[j
];
6368 i
.types
[j
- 1] = i
.types
[j
];
6369 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6373 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6375 gas_assert ((MAX_OPERANDS
- 1) > dupl
6376 && (i
.tm
.opcode_modifier
.vexsources
6379 /* Add the implicit xmm0 for instructions with VEX prefix
6381 for (j
= i
.operands
; j
> 0; j
--)
6383 i
.op
[j
] = i
.op
[j
- 1];
6384 i
.types
[j
] = i
.types
[j
- 1];
6385 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6388 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6389 i
.types
[0] = regxmm
;
6390 i
.tm
.operand_types
[0] = regxmm
;
6393 i
.reg_operands
+= 2;
6398 i
.op
[dupl
] = i
.op
[dest
];
6399 i
.types
[dupl
] = i
.types
[dest
];
6400 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6409 i
.op
[dupl
] = i
.op
[dest
];
6410 i
.types
[dupl
] = i
.types
[dest
];
6411 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6414 if (i
.tm
.opcode_modifier
.immext
)
6417 else if (i
.tm
.operand_types
[0].bitfield
.acc
6418 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6422 for (j
= 1; j
< i
.operands
; j
++)
6424 i
.op
[j
- 1] = i
.op
[j
];
6425 i
.types
[j
- 1] = i
.types
[j
];
6427 /* We need to adjust fields in i.tm since they are used by
6428 build_modrm_byte. */
6429 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6436 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6438 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6440 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6441 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6442 regnum
= register_number (i
.op
[1].regs
);
6443 first_reg_in_group
= regnum
& ~3;
6444 last_reg_in_group
= first_reg_in_group
+ 3;
6445 if (regnum
!= first_reg_in_group
)
6446 as_warn (_("source register `%s%s' implicitly denotes"
6447 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6448 register_prefix
, i
.op
[1].regs
->reg_name
,
6449 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6450 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6453 else if (i
.tm
.opcode_modifier
.regkludge
)
6455 /* The imul $imm, %reg instruction is converted into
6456 imul $imm, %reg, %reg, and the clr %reg instruction
6457 is converted into xor %reg, %reg. */
6459 unsigned int first_reg_op
;
6461 if (operand_type_check (i
.types
[0], reg
))
6465 /* Pretend we saw the extra register operand. */
6466 gas_assert (i
.reg_operands
== 1
6467 && i
.op
[first_reg_op
+ 1].regs
== 0);
6468 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6469 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6474 if (i
.tm
.opcode_modifier
.shortform
)
6476 if (i
.types
[0].bitfield
.sreg2
6477 || i
.types
[0].bitfield
.sreg3
)
6479 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6480 && i
.op
[0].regs
->reg_num
== 1)
6482 as_bad (_("you can't `pop %scs'"), register_prefix
);
6485 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6486 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6491 /* The register or float register operand is in operand
6495 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6496 || operand_type_check (i
.types
[0], reg
))
6500 /* Register goes in low 3 bits of opcode. */
6501 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6502 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6504 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6506 /* Warn about some common errors, but press on regardless.
6507 The first case can be generated by gcc (<= 2.8.1). */
6508 if (i
.operands
== 2)
6510 /* Reversed arguments on faddp, fsubp, etc. */
6511 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6512 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6513 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6517 /* Extraneous `l' suffix on fp insn. */
6518 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6519 register_prefix
, i
.op
[0].regs
->reg_name
);
6524 else if (i
.tm
.opcode_modifier
.modrm
)
6526 /* The opcode is completed (modulo i.tm.extension_opcode which
6527 must be put into the modrm byte). Now, we make the modrm and
6528 index base bytes based on all the info we've collected. */
6530 default_seg
= build_modrm_byte ();
6532 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6536 else if (i
.tm
.opcode_modifier
.isstring
)
6538 /* For the string instructions that allow a segment override
6539 on one of their operands, the default segment is ds. */
6543 if (i
.tm
.base_opcode
== 0x8d /* lea */
6546 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6548 /* If a segment was explicitly specified, and the specified segment
6549 is not the default, use an opcode prefix to select it. If we
6550 never figured out what the default segment is, then default_seg
6551 will be zero at this point, and the specified segment prefix will
6553 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6555 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6561 static const seg_entry
*
6562 build_modrm_byte (void)
6564 const seg_entry
*default_seg
= 0;
6565 unsigned int source
, dest
;
6568 /* The first operand of instructions with VEX prefix and 3 sources
6569 must be VEX_Imm4. */
6570 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6573 unsigned int nds
, reg_slot
;
6576 if (i
.tm
.opcode_modifier
.veximmext
6577 && i
.tm
.opcode_modifier
.immext
)
6579 dest
= i
.operands
- 2;
6580 gas_assert (dest
== 3);
6583 dest
= i
.operands
- 1;
6586 /* There are 2 kinds of instructions:
6587 1. 5 operands: 4 register operands or 3 register operands
6588 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6589 VexW0 or VexW1. The destination must be either XMM, YMM or
6591 2. 4 operands: 4 register operands or 3 register operands
6592 plus 1 memory operand, VexXDS, and VexImmExt */
6593 gas_assert ((i
.reg_operands
== 4
6594 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6595 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6596 && (i
.tm
.opcode_modifier
.veximmext
6597 || (i
.imm_operands
== 1
6598 && i
.types
[0].bitfield
.vec_imm4
6599 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6600 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6601 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
)));
6603 if (i
.imm_operands
== 0)
6605 /* When there is no immediate operand, generate an 8bit
6606 immediate operand to encode the first operand. */
6607 exp
= &im_expressions
[i
.imm_operands
++];
6608 i
.op
[i
.operands
].imms
= exp
;
6609 i
.types
[i
.operands
] = imm8
;
6611 /* If VexW1 is set, the first operand is the source and
6612 the second operand is encoded in the immediate operand. */
6613 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6624 /* FMA swaps REG and NDS. */
6625 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6633 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6634 exp
->X_op
= O_constant
;
6635 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6636 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6640 unsigned int imm_slot
;
6642 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6644 /* If VexW0 is set, the third operand is the source and
6645 the second operand is encoded in the immediate
6652 /* VexW1 is set, the second operand is the source and
6653 the third operand is encoded in the immediate
6659 if (i
.tm
.opcode_modifier
.immext
)
6661 /* When ImmExt is set, the immediate byte is the last
6663 imm_slot
= i
.operands
- 1;
6671 /* Turn on Imm8 so that output_imm will generate it. */
6672 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6675 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6676 i
.op
[imm_slot
].imms
->X_add_number
6677 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6678 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6681 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6682 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6687 /* i.reg_operands MUST be the number of real register operands;
6688 implicit registers do not count. If there are 3 register
6689 operands, it must be a instruction with VexNDS. For a
6690 instruction with VexNDD, the destination register is encoded
6691 in VEX prefix. If there are 4 register operands, it must be
6692 a instruction with VEX prefix and 3 sources. */
6693 if (i
.mem_operands
== 0
6694 && ((i
.reg_operands
== 2
6695 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6696 || (i
.reg_operands
== 3
6697 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6698 || (i
.reg_operands
== 4 && vex_3_sources
)))
6706 /* When there are 3 operands, one of them may be immediate,
6707 which may be the first or the last operand. Otherwise,
6708 the first operand must be shift count register (cl) or it
6709 is an instruction with VexNDS. */
6710 gas_assert (i
.imm_operands
== 1
6711 || (i
.imm_operands
== 0
6712 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6713 || i
.types
[0].bitfield
.shiftcount
)));
6714 if (operand_type_check (i
.types
[0], imm
)
6715 || i
.types
[0].bitfield
.shiftcount
)
6721 /* When there are 4 operands, the first two must be 8bit
6722 immediate operands. The source operand will be the 3rd
6725 For instructions with VexNDS, if the first operand
6726 an imm8, the source operand is the 2nd one. If the last
6727 operand is imm8, the source operand is the first one. */
6728 gas_assert ((i
.imm_operands
== 2
6729 && i
.types
[0].bitfield
.imm8
6730 && i
.types
[1].bitfield
.imm8
)
6731 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6732 && i
.imm_operands
== 1
6733 && (i
.types
[0].bitfield
.imm8
6734 || i
.types
[i
.operands
- 1].bitfield
.imm8
6736 if (i
.imm_operands
== 2)
6740 if (i
.types
[0].bitfield
.imm8
)
6747 if (is_evex_encoding (&i
.tm
))
6749 /* For EVEX instructions, when there are 5 operands, the
6750 first one must be immediate operand. If the second one
6751 is immediate operand, the source operand is the 3th
6752 one. If the last one is immediate operand, the source
6753 operand is the 2nd one. */
6754 gas_assert (i
.imm_operands
== 2
6755 && i
.tm
.opcode_modifier
.sae
6756 && operand_type_check (i
.types
[0], imm
));
6757 if (operand_type_check (i
.types
[1], imm
))
6759 else if (operand_type_check (i
.types
[4], imm
))
6773 /* RC/SAE operand could be between DEST and SRC. That happens
6774 when one operand is GPR and the other one is XMM/YMM/ZMM
6776 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6779 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6781 /* For instructions with VexNDS, the register-only source
6782 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6783 register. It is encoded in VEX prefix. We need to
6784 clear RegMem bit before calling operand_type_equal. */
6786 i386_operand_type op
;
6789 /* Check register-only source operand when two source
6790 operands are swapped. */
6791 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6792 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6800 op
= i
.tm
.operand_types
[vvvv
];
6801 op
.bitfield
.regmem
= 0;
6802 if ((dest
+ 1) >= i
.operands
6803 || ((!op
.bitfield
.reg
6804 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6805 && !op
.bitfield
.regsimd
6806 && !operand_type_equal (&op
, ®mask
)))
6808 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6814 /* One of the register operands will be encoded in the i.tm.reg
6815 field, the other in the combined i.tm.mode and i.tm.regmem
6816 fields. If no form of this instruction supports a memory
6817 destination operand, then we assume the source operand may
6818 sometimes be a memory operand and so we need to store the
6819 destination in the i.rm.reg field. */
6820 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6821 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6823 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6824 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6825 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6827 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6829 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6831 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6836 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6837 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6838 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6840 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6842 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6844 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6847 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6849 if (!i
.types
[0].bitfield
.control
6850 && !i
.types
[1].bitfield
.control
)
6852 i
.rex
&= ~(REX_R
| REX_B
);
6853 add_prefix (LOCK_PREFIX_OPCODE
);
6857 { /* If it's not 2 reg operands... */
6862 unsigned int fake_zero_displacement
= 0;
6865 for (op
= 0; op
< i
.operands
; op
++)
6866 if (operand_type_check (i
.types
[op
], anymem
))
6868 gas_assert (op
< i
.operands
);
6870 if (i
.tm
.opcode_modifier
.vecsib
)
6872 if (i
.index_reg
->reg_num
== RegEiz
6873 || i
.index_reg
->reg_num
== RegRiz
)
6876 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6879 i
.sib
.base
= NO_BASE_REGISTER
;
6880 i
.sib
.scale
= i
.log2_scale_factor
;
6881 i
.types
[op
].bitfield
.disp8
= 0;
6882 i
.types
[op
].bitfield
.disp16
= 0;
6883 i
.types
[op
].bitfield
.disp64
= 0;
6884 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6886 /* Must be 32 bit */
6887 i
.types
[op
].bitfield
.disp32
= 1;
6888 i
.types
[op
].bitfield
.disp32s
= 0;
6892 i
.types
[op
].bitfield
.disp32
= 0;
6893 i
.types
[op
].bitfield
.disp32s
= 1;
6896 i
.sib
.index
= i
.index_reg
->reg_num
;
6897 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6899 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6905 if (i
.base_reg
== 0)
6908 if (!i
.disp_operands
)
6909 fake_zero_displacement
= 1;
6910 if (i
.index_reg
== 0)
6912 i386_operand_type newdisp
;
6914 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6915 /* Operand is just <disp> */
6916 if (flag_code
== CODE_64BIT
)
6918 /* 64bit mode overwrites the 32bit absolute
6919 addressing by RIP relative addressing and
6920 absolute addressing is encoded by one of the
6921 redundant SIB forms. */
6922 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6923 i
.sib
.base
= NO_BASE_REGISTER
;
6924 i
.sib
.index
= NO_INDEX_REGISTER
;
6925 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6927 else if ((flag_code
== CODE_16BIT
)
6928 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6930 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6935 i
.rm
.regmem
= NO_BASE_REGISTER
;
6938 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6939 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6941 else if (!i
.tm
.opcode_modifier
.vecsib
)
6943 /* !i.base_reg && i.index_reg */
6944 if (i
.index_reg
->reg_num
== RegEiz
6945 || i
.index_reg
->reg_num
== RegRiz
)
6946 i
.sib
.index
= NO_INDEX_REGISTER
;
6948 i
.sib
.index
= i
.index_reg
->reg_num
;
6949 i
.sib
.base
= NO_BASE_REGISTER
;
6950 i
.sib
.scale
= i
.log2_scale_factor
;
6951 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6952 i
.types
[op
].bitfield
.disp8
= 0;
6953 i
.types
[op
].bitfield
.disp16
= 0;
6954 i
.types
[op
].bitfield
.disp64
= 0;
6955 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6957 /* Must be 32 bit */
6958 i
.types
[op
].bitfield
.disp32
= 1;
6959 i
.types
[op
].bitfield
.disp32s
= 0;
6963 i
.types
[op
].bitfield
.disp32
= 0;
6964 i
.types
[op
].bitfield
.disp32s
= 1;
6966 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6970 /* RIP addressing for 64bit mode. */
6971 else if (i
.base_reg
->reg_num
== RegRip
||
6972 i
.base_reg
->reg_num
== RegEip
)
6974 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6975 i
.rm
.regmem
= NO_BASE_REGISTER
;
6976 i
.types
[op
].bitfield
.disp8
= 0;
6977 i
.types
[op
].bitfield
.disp16
= 0;
6978 i
.types
[op
].bitfield
.disp32
= 0;
6979 i
.types
[op
].bitfield
.disp32s
= 1;
6980 i
.types
[op
].bitfield
.disp64
= 0;
6981 i
.flags
[op
] |= Operand_PCrel
;
6982 if (! i
.disp_operands
)
6983 fake_zero_displacement
= 1;
6985 else if (i
.base_reg
->reg_type
.bitfield
.word
)
6987 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6988 switch (i
.base_reg
->reg_num
)
6991 if (i
.index_reg
== 0)
6993 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6994 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6998 if (i
.index_reg
== 0)
7001 if (operand_type_check (i
.types
[op
], disp
) == 0)
7003 /* fake (%bp) into 0(%bp) */
7004 i
.types
[op
].bitfield
.disp8
= 1;
7005 fake_zero_displacement
= 1;
7008 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7009 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7011 default: /* (%si) -> 4 or (%di) -> 5 */
7012 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7014 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7016 else /* i.base_reg and 32/64 bit mode */
7018 if (flag_code
== CODE_64BIT
7019 && operand_type_check (i
.types
[op
], disp
))
7021 i
.types
[op
].bitfield
.disp16
= 0;
7022 i
.types
[op
].bitfield
.disp64
= 0;
7023 if (i
.prefix
[ADDR_PREFIX
] == 0)
7025 i
.types
[op
].bitfield
.disp32
= 0;
7026 i
.types
[op
].bitfield
.disp32s
= 1;
7030 i
.types
[op
].bitfield
.disp32
= 1;
7031 i
.types
[op
].bitfield
.disp32s
= 0;
7035 if (!i
.tm
.opcode_modifier
.vecsib
)
7036 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7037 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7039 i
.sib
.base
= i
.base_reg
->reg_num
;
7040 /* x86-64 ignores REX prefix bit here to avoid decoder
7042 if (!(i
.base_reg
->reg_flags
& RegRex
)
7043 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7044 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7046 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7048 fake_zero_displacement
= 1;
7049 i
.types
[op
].bitfield
.disp8
= 1;
7051 i
.sib
.scale
= i
.log2_scale_factor
;
7052 if (i
.index_reg
== 0)
7054 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7055 /* <disp>(%esp) becomes two byte modrm with no index
7056 register. We've already stored the code for esp
7057 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7058 Any base register besides %esp will not use the
7059 extra modrm byte. */
7060 i
.sib
.index
= NO_INDEX_REGISTER
;
7062 else if (!i
.tm
.opcode_modifier
.vecsib
)
7064 if (i
.index_reg
->reg_num
== RegEiz
7065 || i
.index_reg
->reg_num
== RegRiz
)
7066 i
.sib
.index
= NO_INDEX_REGISTER
;
7068 i
.sib
.index
= i
.index_reg
->reg_num
;
7069 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7070 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7075 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7076 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7080 if (!fake_zero_displacement
7084 fake_zero_displacement
= 1;
7085 if (i
.disp_encoding
== disp_encoding_8bit
)
7086 i
.types
[op
].bitfield
.disp8
= 1;
7088 i
.types
[op
].bitfield
.disp32
= 1;
7090 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7094 if (fake_zero_displacement
)
7096 /* Fakes a zero displacement assuming that i.types[op]
7097 holds the correct displacement size. */
7100 gas_assert (i
.op
[op
].disps
== 0);
7101 exp
= &disp_expressions
[i
.disp_operands
++];
7102 i
.op
[op
].disps
= exp
;
7103 exp
->X_op
= O_constant
;
7104 exp
->X_add_number
= 0;
7105 exp
->X_add_symbol
= (symbolS
*) 0;
7106 exp
->X_op_symbol
= (symbolS
*) 0;
7114 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7116 if (operand_type_check (i
.types
[0], imm
))
7117 i
.vex
.register_specifier
= NULL
;
7120 /* VEX.vvvv encodes one of the sources when the first
7121 operand is not an immediate. */
7122 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7123 i
.vex
.register_specifier
= i
.op
[0].regs
;
7125 i
.vex
.register_specifier
= i
.op
[1].regs
;
7128 /* Destination is a XMM register encoded in the ModRM.reg
7130 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7131 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7134 /* ModRM.rm and VEX.B encodes the other source. */
7135 if (!i
.mem_operands
)
7139 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7140 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7142 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7144 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7148 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7150 i
.vex
.register_specifier
= i
.op
[2].regs
;
7151 if (!i
.mem_operands
)
7154 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7155 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7159 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7160 (if any) based on i.tm.extension_opcode. Again, we must be
7161 careful to make sure that segment/control/debug/test/MMX
7162 registers are coded into the i.rm.reg field. */
7163 else if (i
.reg_operands
)
7166 unsigned int vex_reg
= ~0;
7168 for (op
= 0; op
< i
.operands
; op
++)
7169 if (i
.types
[op
].bitfield
.reg
7170 || i
.types
[op
].bitfield
.regmmx
7171 || i
.types
[op
].bitfield
.regsimd
7172 || i
.types
[op
].bitfield
.regbnd
7173 || i
.types
[op
].bitfield
.regmask
7174 || i
.types
[op
].bitfield
.sreg2
7175 || i
.types
[op
].bitfield
.sreg3
7176 || i
.types
[op
].bitfield
.control
7177 || i
.types
[op
].bitfield
.debug
7178 || i
.types
[op
].bitfield
.test
)
7183 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7185 /* For instructions with VexNDS, the register-only
7186 source operand is encoded in VEX prefix. */
7187 gas_assert (mem
!= (unsigned int) ~0);
7192 gas_assert (op
< i
.operands
);
7196 /* Check register-only source operand when two source
7197 operands are swapped. */
7198 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7199 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7203 gas_assert (mem
== (vex_reg
+ 1)
7204 && op
< i
.operands
);
7209 gas_assert (vex_reg
< i
.operands
);
7213 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7215 /* For instructions with VexNDD, the register destination
7216 is encoded in VEX prefix. */
7217 if (i
.mem_operands
== 0)
7219 /* There is no memory operand. */
7220 gas_assert ((op
+ 2) == i
.operands
);
7225 /* There are only 2 non-immediate operands. */
7226 gas_assert (op
< i
.imm_operands
+ 2
7227 && i
.operands
== i
.imm_operands
+ 2);
7228 vex_reg
= i
.imm_operands
+ 1;
7232 gas_assert (op
< i
.operands
);
7234 if (vex_reg
!= (unsigned int) ~0)
7236 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7238 if ((!type
->bitfield
.reg
7239 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7240 && !type
->bitfield
.regsimd
7241 && !operand_type_equal (type
, ®mask
))
7244 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7247 /* Don't set OP operand twice. */
7250 /* If there is an extension opcode to put here, the
7251 register number must be put into the regmem field. */
7252 if (i
.tm
.extension_opcode
!= None
)
7254 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7255 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7257 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7262 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7263 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7265 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7270 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7271 must set it to 3 to indicate this is a register operand
7272 in the regmem field. */
7273 if (!i
.mem_operands
)
7277 /* Fill in i.rm.reg field with extension opcode (if any). */
7278 if (i
.tm
.extension_opcode
!= None
)
7279 i
.rm
.reg
= i
.tm
.extension_opcode
;
7285 output_branch (void)
7291 relax_substateT subtype
;
7295 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7296 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7299 if (i
.prefix
[DATA_PREFIX
] != 0)
7305 /* Pentium4 branch hints. */
7306 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7307 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7312 if (i
.prefix
[REX_PREFIX
] != 0)
7318 /* BND prefixed jump. */
7319 if (i
.prefix
[BND_PREFIX
] != 0)
7321 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7325 if (i
.prefixes
!= 0 && !intel_syntax
)
7326 as_warn (_("skipping prefixes on this instruction"));
7328 /* It's always a symbol; End frag & setup for relax.
7329 Make sure there is enough room in this frag for the largest
7330 instruction we may generate in md_convert_frag. This is 2
7331 bytes for the opcode and room for the prefix and largest
7333 frag_grow (prefix
+ 2 + 4);
7334 /* Prefix and 1 opcode byte go in fr_fix. */
7335 p
= frag_more (prefix
+ 1);
7336 if (i
.prefix
[DATA_PREFIX
] != 0)
7337 *p
++ = DATA_PREFIX_OPCODE
;
7338 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7339 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7340 *p
++ = i
.prefix
[SEG_PREFIX
];
7341 if (i
.prefix
[REX_PREFIX
] != 0)
7342 *p
++ = i
.prefix
[REX_PREFIX
];
7343 *p
= i
.tm
.base_opcode
;
7345 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7346 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7347 else if (cpu_arch_flags
.bitfield
.cpui386
)
7348 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7350 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7353 sym
= i
.op
[0].disps
->X_add_symbol
;
7354 off
= i
.op
[0].disps
->X_add_number
;
7356 if (i
.op
[0].disps
->X_op
!= O_constant
7357 && i
.op
[0].disps
->X_op
!= O_symbol
)
7359 /* Handle complex expressions. */
7360 sym
= make_expr_symbol (i
.op
[0].disps
);
7364 /* 1 possible extra opcode + 4 byte displacement go in var part.
7365 Pass reloc in fr_var. */
7366 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7370 /* Return TRUE iff PLT32 relocation should be used for branching to
7374 need_plt32_p (symbolS
*s
)
7376 /* PLT32 relocation is ELF only. */
7380 /* Since there is no need to prepare for PLT branch on x86-64, we
7381 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7382 be used as a marker for 32-bit PC-relative branches. */
7386 /* Weak or undefined symbol need PLT32 relocation. */
7387 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7390 /* Non-global symbol doesn't need PLT32 relocation. */
7391 if (! S_IS_EXTERNAL (s
))
7394 /* Other global symbols need PLT32 relocation. NB: Symbol with
7395 non-default visibilities are treated as normal global symbol
7396 so that PLT32 relocation can be used as a marker for 32-bit
7397 PC-relative branches. It is useful for linker relaxation. */
7408 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7410 if (i
.tm
.opcode_modifier
.jumpbyte
)
7412 /* This is a loop or jecxz type instruction. */
7414 if (i
.prefix
[ADDR_PREFIX
] != 0)
7416 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7419 /* Pentium4 branch hints. */
7420 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7421 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7423 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7432 if (flag_code
== CODE_16BIT
)
7435 if (i
.prefix
[DATA_PREFIX
] != 0)
7437 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7447 if (i
.prefix
[REX_PREFIX
] != 0)
7449 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7453 /* BND prefixed jump. */
7454 if (i
.prefix
[BND_PREFIX
] != 0)
7456 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7460 if (i
.prefixes
!= 0 && !intel_syntax
)
7461 as_warn (_("skipping prefixes on this instruction"));
7463 p
= frag_more (i
.tm
.opcode_length
+ size
);
7464 switch (i
.tm
.opcode_length
)
7467 *p
++ = i
.tm
.base_opcode
>> 8;
7470 *p
++ = i
.tm
.base_opcode
;
7476 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7478 && jump_reloc
== NO_RELOC
7479 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7480 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7483 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7485 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7486 i
.op
[0].disps
, 1, jump_reloc
);
7488 /* All jumps handled here are signed, but don't use a signed limit
7489 check for 32 and 16 bit jumps as we want to allow wrap around at
7490 4G and 64k respectively. */
7492 fixP
->fx_signed
= 1;
7496 output_interseg_jump (void)
7504 if (flag_code
== CODE_16BIT
)
7508 if (i
.prefix
[DATA_PREFIX
] != 0)
7514 if (i
.prefix
[REX_PREFIX
] != 0)
7524 if (i
.prefixes
!= 0 && !intel_syntax
)
7525 as_warn (_("skipping prefixes on this instruction"));
7527 /* 1 opcode; 2 segment; offset */
7528 p
= frag_more (prefix
+ 1 + 2 + size
);
7530 if (i
.prefix
[DATA_PREFIX
] != 0)
7531 *p
++ = DATA_PREFIX_OPCODE
;
7533 if (i
.prefix
[REX_PREFIX
] != 0)
7534 *p
++ = i
.prefix
[REX_PREFIX
];
7536 *p
++ = i
.tm
.base_opcode
;
7537 if (i
.op
[1].imms
->X_op
== O_constant
)
7539 offsetT n
= i
.op
[1].imms
->X_add_number
;
7542 && !fits_in_unsigned_word (n
)
7543 && !fits_in_signed_word (n
))
7545 as_bad (_("16-bit jump out of range"));
7548 md_number_to_chars (p
, n
, size
);
7551 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7552 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7553 if (i
.op
[0].imms
->X_op
!= O_constant
)
7554 as_bad (_("can't handle non absolute segment in `%s'"),
7556 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7562 fragS
*insn_start_frag
;
7563 offsetT insn_start_off
;
7565 /* Tie dwarf2 debug info to the address at the start of the insn.
7566 We can't do this after the insn has been output as the current
7567 frag may have been closed off. eg. by frag_var. */
7568 dwarf2_emit_insn (0);
7570 insn_start_frag
= frag_now
;
7571 insn_start_off
= frag_now_fix ();
7574 if (i
.tm
.opcode_modifier
.jump
)
7576 else if (i
.tm
.opcode_modifier
.jumpbyte
7577 || i
.tm
.opcode_modifier
.jumpdword
)
7579 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7580 output_interseg_jump ();
7583 /* Output normal instructions here. */
7587 unsigned int prefix
;
7590 && i
.tm
.base_opcode
== 0xfae
7592 && i
.imm_operands
== 1
7593 && (i
.op
[0].imms
->X_add_number
== 0xe8
7594 || i
.op
[0].imms
->X_add_number
== 0xf0
7595 || i
.op
[0].imms
->X_add_number
== 0xf8))
7597 /* Encode lfence, mfence, and sfence as
7598 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7599 offsetT val
= 0x240483f0ULL
;
7601 md_number_to_chars (p
, val
, 5);
7605 /* Some processors fail on LOCK prefix. This options makes
7606 assembler ignore LOCK prefix and serves as a workaround. */
7607 if (omit_lock_prefix
)
7609 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7611 i
.prefix
[LOCK_PREFIX
] = 0;
7614 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7615 don't need the explicit prefix. */
7616 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7618 switch (i
.tm
.opcode_length
)
7621 if (i
.tm
.base_opcode
& 0xff000000)
7623 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7628 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7630 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7631 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7634 if (prefix
!= REPE_PREFIX_OPCODE
7635 || (i
.prefix
[REP_PREFIX
]
7636 != REPE_PREFIX_OPCODE
))
7637 add_prefix (prefix
);
7640 add_prefix (prefix
);
7646 /* Check for pseudo prefixes. */
7647 as_bad_where (insn_start_frag
->fr_file
,
7648 insn_start_frag
->fr_line
,
7649 _("pseudo prefix without instruction"));
7655 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7656 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7657 R_X86_64_GOTTPOFF relocation so that linker can safely
7658 perform IE->LE optimization. */
7659 if (x86_elf_abi
== X86_64_X32_ABI
7661 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7662 && i
.prefix
[REX_PREFIX
] == 0)
7663 add_prefix (REX_OPCODE
);
7666 /* The prefix bytes. */
7667 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7669 FRAG_APPEND_1_CHAR (*q
);
7673 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7678 /* REX byte is encoded in VEX prefix. */
7682 FRAG_APPEND_1_CHAR (*q
);
7685 /* There should be no other prefixes for instructions
7690 /* For EVEX instructions i.vrex should become 0 after
7691 build_evex_prefix. For VEX instructions upper 16 registers
7692 aren't available, so VREX should be 0. */
7695 /* Now the VEX prefix. */
7696 p
= frag_more (i
.vex
.length
);
7697 for (j
= 0; j
< i
.vex
.length
; j
++)
7698 p
[j
] = i
.vex
.bytes
[j
];
7701 /* Now the opcode; be careful about word order here! */
7702 if (i
.tm
.opcode_length
== 1)
7704 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7708 switch (i
.tm
.opcode_length
)
7712 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7713 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7717 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7727 /* Put out high byte first: can't use md_number_to_chars! */
7728 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7729 *p
= i
.tm
.base_opcode
& 0xff;
7732 /* Now the modrm byte and sib byte (if present). */
7733 if (i
.tm
.opcode_modifier
.modrm
)
7735 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7738 /* If i.rm.regmem == ESP (4)
7739 && i.rm.mode != (Register mode)
7741 ==> need second modrm byte. */
7742 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7744 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7745 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7747 | i
.sib
.scale
<< 6));
7750 if (i
.disp_operands
)
7751 output_disp (insn_start_frag
, insn_start_off
);
7754 output_imm (insn_start_frag
, insn_start_off
);
7760 pi ("" /*line*/, &i
);
7762 #endif /* DEBUG386 */
7765 /* Return the size of the displacement operand N. */
7768 disp_size (unsigned int n
)
7772 if (i
.types
[n
].bitfield
.disp64
)
7774 else if (i
.types
[n
].bitfield
.disp8
)
7776 else if (i
.types
[n
].bitfield
.disp16
)
7781 /* Return the size of the immediate operand N. */
7784 imm_size (unsigned int n
)
7787 if (i
.types
[n
].bitfield
.imm64
)
7789 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7791 else if (i
.types
[n
].bitfield
.imm16
)
7797 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7802 for (n
= 0; n
< i
.operands
; n
++)
7804 if (operand_type_check (i
.types
[n
], disp
))
7806 if (i
.op
[n
].disps
->X_op
== O_constant
)
7808 int size
= disp_size (n
);
7809 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7811 val
= offset_in_range (val
>> i
.memshift
, size
);
7812 p
= frag_more (size
);
7813 md_number_to_chars (p
, val
, size
);
7817 enum bfd_reloc_code_real reloc_type
;
7818 int size
= disp_size (n
);
7819 int sign
= i
.types
[n
].bitfield
.disp32s
;
7820 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7823 /* We can't have 8 bit displacement here. */
7824 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7826 /* The PC relative address is computed relative
7827 to the instruction boundary, so in case immediate
7828 fields follows, we need to adjust the value. */
7829 if (pcrel
&& i
.imm_operands
)
7834 for (n1
= 0; n1
< i
.operands
; n1
++)
7835 if (operand_type_check (i
.types
[n1
], imm
))
7837 /* Only one immediate is allowed for PC
7838 relative address. */
7839 gas_assert (sz
== 0);
7841 i
.op
[n
].disps
->X_add_number
-= sz
;
7843 /* We should find the immediate. */
7844 gas_assert (sz
!= 0);
7847 p
= frag_more (size
);
7848 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7850 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7851 && (((reloc_type
== BFD_RELOC_32
7852 || reloc_type
== BFD_RELOC_X86_64_32S
7853 || (reloc_type
== BFD_RELOC_64
7855 && (i
.op
[n
].disps
->X_op
== O_symbol
7856 || (i
.op
[n
].disps
->X_op
== O_add
7857 && ((symbol_get_value_expression
7858 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7860 || reloc_type
== BFD_RELOC_32_PCREL
))
7864 if (insn_start_frag
== frag_now
)
7865 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7870 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7871 for (fr
= insn_start_frag
->fr_next
;
7872 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7874 add
+= p
- frag_now
->fr_literal
;
7879 reloc_type
= BFD_RELOC_386_GOTPC
;
7880 i
.op
[n
].imms
->X_add_number
+= add
;
7882 else if (reloc_type
== BFD_RELOC_64
)
7883 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7885 /* Don't do the adjustment for x86-64, as there
7886 the pcrel addressing is relative to the _next_
7887 insn, and that is taken care of in other code. */
7888 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7890 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7891 size
, i
.op
[n
].disps
, pcrel
,
7893 /* Check for "call/jmp *mem", "mov mem, %reg",
7894 "test %reg, mem" and "binop mem, %reg" where binop
7895 is one of adc, add, and, cmp, or, sbb, sub, xor
7896 instructions. Always generate R_386_GOT32X for
7897 "sym*GOT" operand in 32-bit mode. */
7898 if ((generate_relax_relocations
7901 && i
.rm
.regmem
== 5))
7903 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7904 && ((i
.operands
== 1
7905 && i
.tm
.base_opcode
== 0xff
7906 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7908 && (i
.tm
.base_opcode
== 0x8b
7909 || i
.tm
.base_opcode
== 0x85
7910 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7914 fixP
->fx_tcbit
= i
.rex
!= 0;
7916 && (i
.base_reg
->reg_num
== RegRip
7917 || i
.base_reg
->reg_num
== RegEip
))
7918 fixP
->fx_tcbit2
= 1;
7921 fixP
->fx_tcbit2
= 1;
7929 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7934 for (n
= 0; n
< i
.operands
; n
++)
7936 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7937 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7940 if (operand_type_check (i
.types
[n
], imm
))
7942 if (i
.op
[n
].imms
->X_op
== O_constant
)
7944 int size
= imm_size (n
);
7947 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7949 p
= frag_more (size
);
7950 md_number_to_chars (p
, val
, size
);
7954 /* Not absolute_section.
7955 Need a 32-bit fixup (don't support 8bit
7956 non-absolute imms). Try to support other
7958 enum bfd_reloc_code_real reloc_type
;
7959 int size
= imm_size (n
);
7962 if (i
.types
[n
].bitfield
.imm32s
7963 && (i
.suffix
== QWORD_MNEM_SUFFIX
7964 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7969 p
= frag_more (size
);
7970 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7972 /* This is tough to explain. We end up with this one if we
7973 * have operands that look like
7974 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7975 * obtain the absolute address of the GOT, and it is strongly
7976 * preferable from a performance point of view to avoid using
7977 * a runtime relocation for this. The actual sequence of
7978 * instructions often look something like:
7983 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7985 * The call and pop essentially return the absolute address
7986 * of the label .L66 and store it in %ebx. The linker itself
7987 * will ultimately change the first operand of the addl so
7988 * that %ebx points to the GOT, but to keep things simple, the
7989 * .o file must have this operand set so that it generates not
7990 * the absolute address of .L66, but the absolute address of
7991 * itself. This allows the linker itself simply treat a GOTPC
7992 * relocation as asking for a pcrel offset to the GOT to be
7993 * added in, and the addend of the relocation is stored in the
7994 * operand field for the instruction itself.
7996 * Our job here is to fix the operand so that it would add
7997 * the correct offset so that %ebx would point to itself. The
7998 * thing that is tricky is that .-.L66 will point to the
7999 * beginning of the instruction, so we need to further modify
8000 * the operand so that it will point to itself. There are
8001 * other cases where you have something like:
8003 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8005 * and here no correction would be required. Internally in
8006 * the assembler we treat operands of this form as not being
8007 * pcrel since the '.' is explicitly mentioned, and I wonder
8008 * whether it would simplify matters to do it this way. Who
8009 * knows. In earlier versions of the PIC patches, the
8010 * pcrel_adjust field was used to store the correction, but
8011 * since the expression is not pcrel, I felt it would be
8012 * confusing to do it this way. */
8014 if ((reloc_type
== BFD_RELOC_32
8015 || reloc_type
== BFD_RELOC_X86_64_32S
8016 || reloc_type
== BFD_RELOC_64
)
8018 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8019 && (i
.op
[n
].imms
->X_op
== O_symbol
8020 || (i
.op
[n
].imms
->X_op
== O_add
8021 && ((symbol_get_value_expression
8022 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8027 if (insn_start_frag
== frag_now
)
8028 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8033 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8034 for (fr
= insn_start_frag
->fr_next
;
8035 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8037 add
+= p
- frag_now
->fr_literal
;
8041 reloc_type
= BFD_RELOC_386_GOTPC
;
8043 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8045 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8046 i
.op
[n
].imms
->X_add_number
+= add
;
8048 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8049 i
.op
[n
].imms
, 0, reloc_type
);
8055 /* x86_cons_fix_new is called via the expression parsing code when a
8056 reloc is needed. We use this hook to get the correct .got reloc. */
8057 static int cons_sign
= -1;
8060 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8061 expressionS
*exp
, bfd_reloc_code_real_type r
)
8063 r
= reloc (len
, 0, cons_sign
, r
);
8066 if (exp
->X_op
== O_secrel
)
8068 exp
->X_op
= O_symbol
;
8069 r
= BFD_RELOC_32_SECREL
;
8073 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8076 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8077 purpose of the `.dc.a' internal pseudo-op. */
8080 x86_address_bytes (void)
8082 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8084 return stdoutput
->arch_info
->bits_per_address
/ 8;
8087 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8089 # define lex_got(reloc, adjust, types) NULL
8091 /* Parse operands of the form
8092 <symbol>@GOTOFF+<nnn>
8093 and similar .plt or .got references.
8095 If we find one, set up the correct relocation in RELOC and copy the
8096 input string, minus the `@GOTOFF' into a malloc'd buffer for
8097 parsing by the calling routine. Return this buffer, and if ADJUST
8098 is non-null set it to the length of the string we removed from the
8099 input line. Otherwise return NULL. */
8101 lex_got (enum bfd_reloc_code_real
*rel
,
8103 i386_operand_type
*types
)
8105 /* Some of the relocations depend on the size of what field is to
8106 be relocated. But in our callers i386_immediate and i386_displacement
8107 we don't yet know the operand size (this will be set by insn
8108 matching). Hence we record the word32 relocation here,
8109 and adjust the reloc according to the real size in reloc(). */
8110 static const struct {
8113 const enum bfd_reloc_code_real rel
[2];
8114 const i386_operand_type types64
;
8116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8117 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8119 OPERAND_TYPE_IMM32_64
},
8121 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8122 BFD_RELOC_X86_64_PLTOFF64
},
8123 OPERAND_TYPE_IMM64
},
8124 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8125 BFD_RELOC_X86_64_PLT32
},
8126 OPERAND_TYPE_IMM32_32S_DISP32
},
8127 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8128 BFD_RELOC_X86_64_GOTPLT64
},
8129 OPERAND_TYPE_IMM64_DISP64
},
8130 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8131 BFD_RELOC_X86_64_GOTOFF64
},
8132 OPERAND_TYPE_IMM64_DISP64
},
8133 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8134 BFD_RELOC_X86_64_GOTPCREL
},
8135 OPERAND_TYPE_IMM32_32S_DISP32
},
8136 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8137 BFD_RELOC_X86_64_TLSGD
},
8138 OPERAND_TYPE_IMM32_32S_DISP32
},
8139 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8140 _dummy_first_bfd_reloc_code_real
},
8141 OPERAND_TYPE_NONE
},
8142 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8143 BFD_RELOC_X86_64_TLSLD
},
8144 OPERAND_TYPE_IMM32_32S_DISP32
},
8145 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8146 BFD_RELOC_X86_64_GOTTPOFF
},
8147 OPERAND_TYPE_IMM32_32S_DISP32
},
8148 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8149 BFD_RELOC_X86_64_TPOFF32
},
8150 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8151 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8152 _dummy_first_bfd_reloc_code_real
},
8153 OPERAND_TYPE_NONE
},
8154 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8155 BFD_RELOC_X86_64_DTPOFF32
},
8156 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8157 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8158 _dummy_first_bfd_reloc_code_real
},
8159 OPERAND_TYPE_NONE
},
8160 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8161 _dummy_first_bfd_reloc_code_real
},
8162 OPERAND_TYPE_NONE
},
8163 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8164 BFD_RELOC_X86_64_GOT32
},
8165 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8166 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8167 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8168 OPERAND_TYPE_IMM32_32S_DISP32
},
8169 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8170 BFD_RELOC_X86_64_TLSDESC_CALL
},
8171 OPERAND_TYPE_IMM32_32S_DISP32
},
8176 #if defined (OBJ_MAYBE_ELF)
8181 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8182 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8185 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8187 int len
= gotrel
[j
].len
;
8188 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8190 if (gotrel
[j
].rel
[object_64bit
] != 0)
8193 char *tmpbuf
, *past_reloc
;
8195 *rel
= gotrel
[j
].rel
[object_64bit
];
8199 if (flag_code
!= CODE_64BIT
)
8201 types
->bitfield
.imm32
= 1;
8202 types
->bitfield
.disp32
= 1;
8205 *types
= gotrel
[j
].types64
;
8208 if (j
!= 0 && GOT_symbol
== NULL
)
8209 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8211 /* The length of the first part of our input line. */
8212 first
= cp
- input_line_pointer
;
8214 /* The second part goes from after the reloc token until
8215 (and including) an end_of_line char or comma. */
8216 past_reloc
= cp
+ 1 + len
;
8218 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8220 second
= cp
+ 1 - past_reloc
;
8222 /* Allocate and copy string. The trailing NUL shouldn't
8223 be necessary, but be safe. */
8224 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8225 memcpy (tmpbuf
, input_line_pointer
, first
);
8226 if (second
!= 0 && *past_reloc
!= ' ')
8227 /* Replace the relocation token with ' ', so that
8228 errors like foo@GOTOFF1 will be detected. */
8229 tmpbuf
[first
++] = ' ';
8231 /* Increment length by 1 if the relocation token is
8236 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8237 tmpbuf
[first
+ second
] = '\0';
8241 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8242 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8247 /* Might be a symbol version string. Don't as_bad here. */
8256 /* Parse operands of the form
8257 <symbol>@SECREL32+<nnn>
8259 If we find one, set up the correct relocation in RELOC and copy the
8260 input string, minus the `@SECREL32' into a malloc'd buffer for
8261 parsing by the calling routine. Return this buffer, and if ADJUST
8262 is non-null set it to the length of the string we removed from the
8263 input line. Otherwise return NULL.
8265 This function is copied from the ELF version above adjusted for PE targets. */
8268 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8269 int *adjust ATTRIBUTE_UNUSED
,
8270 i386_operand_type
*types
)
8276 const enum bfd_reloc_code_real rel
[2];
8277 const i386_operand_type types64
;
8281 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8282 BFD_RELOC_32_SECREL
},
8283 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8289 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8290 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8293 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8295 int len
= gotrel
[j
].len
;
8297 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8299 if (gotrel
[j
].rel
[object_64bit
] != 0)
8302 char *tmpbuf
, *past_reloc
;
8304 *rel
= gotrel
[j
].rel
[object_64bit
];
8310 if (flag_code
!= CODE_64BIT
)
8312 types
->bitfield
.imm32
= 1;
8313 types
->bitfield
.disp32
= 1;
8316 *types
= gotrel
[j
].types64
;
8319 /* The length of the first part of our input line. */
8320 first
= cp
- input_line_pointer
;
8322 /* The second part goes from after the reloc token until
8323 (and including) an end_of_line char or comma. */
8324 past_reloc
= cp
+ 1 + len
;
8326 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8328 second
= cp
+ 1 - past_reloc
;
8330 /* Allocate and copy string. The trailing NUL shouldn't
8331 be necessary, but be safe. */
8332 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8333 memcpy (tmpbuf
, input_line_pointer
, first
);
8334 if (second
!= 0 && *past_reloc
!= ' ')
8335 /* Replace the relocation token with ' ', so that
8336 errors like foo@SECLREL321 will be detected. */
8337 tmpbuf
[first
++] = ' ';
8338 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8339 tmpbuf
[first
+ second
] = '\0';
8343 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8344 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8349 /* Might be a symbol version string. Don't as_bad here. */
8355 bfd_reloc_code_real_type
8356 x86_cons (expressionS
*exp
, int size
)
8358 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8360 intel_syntax
= -intel_syntax
;
8363 if (size
== 4 || (object_64bit
&& size
== 8))
8365 /* Handle @GOTOFF and the like in an expression. */
8367 char *gotfree_input_line
;
8370 save
= input_line_pointer
;
8371 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8372 if (gotfree_input_line
)
8373 input_line_pointer
= gotfree_input_line
;
8377 if (gotfree_input_line
)
8379 /* expression () has merrily parsed up to the end of line,
8380 or a comma - in the wrong buffer. Transfer how far
8381 input_line_pointer has moved to the right buffer. */
8382 input_line_pointer
= (save
8383 + (input_line_pointer
- gotfree_input_line
)
8385 free (gotfree_input_line
);
8386 if (exp
->X_op
== O_constant
8387 || exp
->X_op
== O_absent
8388 || exp
->X_op
== O_illegal
8389 || exp
->X_op
== O_register
8390 || exp
->X_op
== O_big
)
8392 char c
= *input_line_pointer
;
8393 *input_line_pointer
= 0;
8394 as_bad (_("missing or invalid expression `%s'"), save
);
8395 *input_line_pointer
= c
;
8402 intel_syntax
= -intel_syntax
;
8405 i386_intel_simplify (exp
);
8411 signed_cons (int size
)
8413 if (flag_code
== CODE_64BIT
)
8421 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8428 if (exp
.X_op
== O_symbol
)
8429 exp
.X_op
= O_secrel
;
8431 emit_expr (&exp
, 4);
8433 while (*input_line_pointer
++ == ',');
8435 input_line_pointer
--;
8436 demand_empty_rest_of_line ();
8440 /* Handle Vector operations. */
8443 check_VecOperations (char *op_string
, char *op_end
)
8445 const reg_entry
*mask
;
8450 && (op_end
== NULL
|| op_string
< op_end
))
8453 if (*op_string
== '{')
8457 /* Check broadcasts. */
8458 if (strncmp (op_string
, "1to", 3) == 0)
8463 goto duplicated_vec_op
;
8466 if (*op_string
== '8')
8468 else if (*op_string
== '4')
8470 else if (*op_string
== '2')
8472 else if (*op_string
== '1'
8473 && *(op_string
+1) == '6')
8480 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8485 broadcast_op
.type
= bcst_type
;
8486 broadcast_op
.operand
= this_operand
;
8487 i
.broadcast
= &broadcast_op
;
8489 /* Check masking operation. */
8490 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8492 /* k0 can't be used for write mask. */
8493 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8495 as_bad (_("`%s%s' can't be used for write mask"),
8496 register_prefix
, mask
->reg_name
);
8502 mask_op
.mask
= mask
;
8503 mask_op
.zeroing
= 0;
8504 mask_op
.operand
= this_operand
;
8510 goto duplicated_vec_op
;
8512 i
.mask
->mask
= mask
;
8514 /* Only "{z}" is allowed here. No need to check
8515 zeroing mask explicitly. */
8516 if (i
.mask
->operand
!= this_operand
)
8518 as_bad (_("invalid write mask `%s'"), saved
);
8525 /* Check zeroing-flag for masking operation. */
8526 else if (*op_string
== 'z')
8530 mask_op
.mask
= NULL
;
8531 mask_op
.zeroing
= 1;
8532 mask_op
.operand
= this_operand
;
8537 if (i
.mask
->zeroing
)
8540 as_bad (_("duplicated `%s'"), saved
);
8544 i
.mask
->zeroing
= 1;
8546 /* Only "{%k}" is allowed here. No need to check mask
8547 register explicitly. */
8548 if (i
.mask
->operand
!= this_operand
)
8550 as_bad (_("invalid zeroing-masking `%s'"),
8559 goto unknown_vec_op
;
8561 if (*op_string
!= '}')
8563 as_bad (_("missing `}' in `%s'"), saved
);
8568 /* Strip whitespace since the addition of pseudo prefixes
8569 changed how the scrubber treats '{'. */
8570 if (is_space_char (*op_string
))
8576 /* We don't know this one. */
8577 as_bad (_("unknown vector operation: `%s'"), saved
);
8581 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8583 as_bad (_("zeroing-masking only allowed with write mask"));
8591 i386_immediate (char *imm_start
)
8593 char *save_input_line_pointer
;
8594 char *gotfree_input_line
;
8597 i386_operand_type types
;
8599 operand_type_set (&types
, ~0);
8601 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8603 as_bad (_("at most %d immediate operands are allowed"),
8604 MAX_IMMEDIATE_OPERANDS
);
8608 exp
= &im_expressions
[i
.imm_operands
++];
8609 i
.op
[this_operand
].imms
= exp
;
8611 if (is_space_char (*imm_start
))
8614 save_input_line_pointer
= input_line_pointer
;
8615 input_line_pointer
= imm_start
;
8617 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8618 if (gotfree_input_line
)
8619 input_line_pointer
= gotfree_input_line
;
8621 exp_seg
= expression (exp
);
8625 /* Handle vector operations. */
8626 if (*input_line_pointer
== '{')
8628 input_line_pointer
= check_VecOperations (input_line_pointer
,
8630 if (input_line_pointer
== NULL
)
8634 if (*input_line_pointer
)
8635 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8637 input_line_pointer
= save_input_line_pointer
;
8638 if (gotfree_input_line
)
8640 free (gotfree_input_line
);
8642 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8643 exp
->X_op
= O_illegal
;
8646 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8650 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8651 i386_operand_type types
, const char *imm_start
)
8653 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8656 as_bad (_("missing or invalid immediate expression `%s'"),
8660 else if (exp
->X_op
== O_constant
)
8662 /* Size it properly later. */
8663 i
.types
[this_operand
].bitfield
.imm64
= 1;
8664 /* If not 64bit, sign extend val. */
8665 if (flag_code
!= CODE_64BIT
8666 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8668 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8670 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8671 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8672 && exp_seg
!= absolute_section
8673 && exp_seg
!= text_section
8674 && exp_seg
!= data_section
8675 && exp_seg
!= bss_section
8676 && exp_seg
!= undefined_section
8677 && !bfd_is_com_section (exp_seg
))
8679 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8683 else if (!intel_syntax
&& exp_seg
== reg_section
)
8686 as_bad (_("illegal immediate register operand %s"), imm_start
);
8691 /* This is an address. The size of the address will be
8692 determined later, depending on destination register,
8693 suffix, or the default for the section. */
8694 i
.types
[this_operand
].bitfield
.imm8
= 1;
8695 i
.types
[this_operand
].bitfield
.imm16
= 1;
8696 i
.types
[this_operand
].bitfield
.imm32
= 1;
8697 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8698 i
.types
[this_operand
].bitfield
.imm64
= 1;
8699 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8707 i386_scale (char *scale
)
8710 char *save
= input_line_pointer
;
8712 input_line_pointer
= scale
;
8713 val
= get_absolute_expression ();
8718 i
.log2_scale_factor
= 0;
8721 i
.log2_scale_factor
= 1;
8724 i
.log2_scale_factor
= 2;
8727 i
.log2_scale_factor
= 3;
8731 char sep
= *input_line_pointer
;
8733 *input_line_pointer
= '\0';
8734 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8736 *input_line_pointer
= sep
;
8737 input_line_pointer
= save
;
8741 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8743 as_warn (_("scale factor of %d without an index register"),
8744 1 << i
.log2_scale_factor
);
8745 i
.log2_scale_factor
= 0;
8747 scale
= input_line_pointer
;
8748 input_line_pointer
= save
;
8753 i386_displacement (char *disp_start
, char *disp_end
)
8757 char *save_input_line_pointer
;
8758 char *gotfree_input_line
;
8760 i386_operand_type bigdisp
, types
= anydisp
;
8763 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8765 as_bad (_("at most %d displacement operands are allowed"),
8766 MAX_MEMORY_OPERANDS
);
8770 operand_type_set (&bigdisp
, 0);
8771 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8772 || (!current_templates
->start
->opcode_modifier
.jump
8773 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8775 bigdisp
.bitfield
.disp32
= 1;
8776 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8777 if (flag_code
== CODE_64BIT
)
8781 bigdisp
.bitfield
.disp32s
= 1;
8782 bigdisp
.bitfield
.disp64
= 1;
8785 else if ((flag_code
== CODE_16BIT
) ^ override
)
8787 bigdisp
.bitfield
.disp32
= 0;
8788 bigdisp
.bitfield
.disp16
= 1;
8793 /* For PC-relative branches, the width of the displacement
8794 is dependent upon data size, not address size. */
8795 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8796 if (flag_code
== CODE_64BIT
)
8798 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8799 bigdisp
.bitfield
.disp16
= 1;
8802 bigdisp
.bitfield
.disp32
= 1;
8803 bigdisp
.bitfield
.disp32s
= 1;
8809 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8811 : LONG_MNEM_SUFFIX
));
8812 bigdisp
.bitfield
.disp32
= 1;
8813 if ((flag_code
== CODE_16BIT
) ^ override
)
8815 bigdisp
.bitfield
.disp32
= 0;
8816 bigdisp
.bitfield
.disp16
= 1;
8820 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8823 exp
= &disp_expressions
[i
.disp_operands
];
8824 i
.op
[this_operand
].disps
= exp
;
8826 save_input_line_pointer
= input_line_pointer
;
8827 input_line_pointer
= disp_start
;
8828 END_STRING_AND_SAVE (disp_end
);
8830 #ifndef GCC_ASM_O_HACK
8831 #define GCC_ASM_O_HACK 0
8834 END_STRING_AND_SAVE (disp_end
+ 1);
8835 if (i
.types
[this_operand
].bitfield
.baseIndex
8836 && displacement_string_end
[-1] == '+')
8838 /* This hack is to avoid a warning when using the "o"
8839 constraint within gcc asm statements.
8842 #define _set_tssldt_desc(n,addr,limit,type) \
8843 __asm__ __volatile__ ( \
8845 "movw %w1,2+%0\n\t" \
8847 "movb %b1,4+%0\n\t" \
8848 "movb %4,5+%0\n\t" \
8849 "movb $0,6+%0\n\t" \
8850 "movb %h1,7+%0\n\t" \
8852 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8854 This works great except that the output assembler ends
8855 up looking a bit weird if it turns out that there is
8856 no offset. You end up producing code that looks like:
8869 So here we provide the missing zero. */
8871 *displacement_string_end
= '0';
8874 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8875 if (gotfree_input_line
)
8876 input_line_pointer
= gotfree_input_line
;
8878 exp_seg
= expression (exp
);
8881 if (*input_line_pointer
)
8882 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8884 RESTORE_END_STRING (disp_end
+ 1);
8886 input_line_pointer
= save_input_line_pointer
;
8887 if (gotfree_input_line
)
8889 free (gotfree_input_line
);
8891 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8892 exp
->X_op
= O_illegal
;
8895 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8897 RESTORE_END_STRING (disp_end
);
8903 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8904 i386_operand_type types
, const char *disp_start
)
8906 i386_operand_type bigdisp
;
8909 /* We do this to make sure that the section symbol is in
8910 the symbol table. We will ultimately change the relocation
8911 to be relative to the beginning of the section. */
8912 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8913 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8914 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8916 if (exp
->X_op
!= O_symbol
)
8919 if (S_IS_LOCAL (exp
->X_add_symbol
)
8920 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8921 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8922 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8923 exp
->X_op
= O_subtract
;
8924 exp
->X_op_symbol
= GOT_symbol
;
8925 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8926 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8927 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8928 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8930 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8933 else if (exp
->X_op
== O_absent
8934 || exp
->X_op
== O_illegal
8935 || exp
->X_op
== O_big
)
8938 as_bad (_("missing or invalid displacement expression `%s'"),
8943 else if (flag_code
== CODE_64BIT
8944 && !i
.prefix
[ADDR_PREFIX
]
8945 && exp
->X_op
== O_constant
)
8947 /* Since displacement is signed extended to 64bit, don't allow
8948 disp32 and turn off disp32s if they are out of range. */
8949 i
.types
[this_operand
].bitfield
.disp32
= 0;
8950 if (!fits_in_signed_long (exp
->X_add_number
))
8952 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8953 if (i
.types
[this_operand
].bitfield
.baseindex
)
8955 as_bad (_("0x%lx out range of signed 32bit displacement"),
8956 (long) exp
->X_add_number
);
8962 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8963 else if (exp
->X_op
!= O_constant
8964 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8965 && exp_seg
!= absolute_section
8966 && exp_seg
!= text_section
8967 && exp_seg
!= data_section
8968 && exp_seg
!= bss_section
8969 && exp_seg
!= undefined_section
8970 && !bfd_is_com_section (exp_seg
))
8972 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8977 /* Check if this is a displacement only operand. */
8978 bigdisp
= i
.types
[this_operand
];
8979 bigdisp
.bitfield
.disp8
= 0;
8980 bigdisp
.bitfield
.disp16
= 0;
8981 bigdisp
.bitfield
.disp32
= 0;
8982 bigdisp
.bitfield
.disp32s
= 0;
8983 bigdisp
.bitfield
.disp64
= 0;
8984 if (operand_type_all_zero (&bigdisp
))
8985 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8991 /* Return the active addressing mode, taking address override and
8992 registers forming the address into consideration. Update the
8993 address override prefix if necessary. */
8995 static enum flag_code
8996 i386_addressing_mode (void)
8998 enum flag_code addr_mode
;
9000 if (i
.prefix
[ADDR_PREFIX
])
9001 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9004 addr_mode
= flag_code
;
9006 #if INFER_ADDR_PREFIX
9007 if (i
.mem_operands
== 0)
9009 /* Infer address prefix from the first memory operand. */
9010 const reg_entry
*addr_reg
= i
.base_reg
;
9012 if (addr_reg
== NULL
)
9013 addr_reg
= i
.index_reg
;
9017 if (addr_reg
->reg_num
== RegEip
9018 || addr_reg
->reg_num
== RegEiz
9019 || addr_reg
->reg_type
.bitfield
.dword
)
9020 addr_mode
= CODE_32BIT
;
9021 else if (flag_code
!= CODE_64BIT
9022 && addr_reg
->reg_type
.bitfield
.word
)
9023 addr_mode
= CODE_16BIT
;
9025 if (addr_mode
!= flag_code
)
9027 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9029 /* Change the size of any displacement too. At most one
9030 of Disp16 or Disp32 is set.
9031 FIXME. There doesn't seem to be any real need for
9032 separate Disp16 and Disp32 flags. The same goes for
9033 Imm16 and Imm32. Removing them would probably clean
9034 up the code quite a lot. */
9035 if (flag_code
!= CODE_64BIT
9036 && (i
.types
[this_operand
].bitfield
.disp16
9037 || i
.types
[this_operand
].bitfield
.disp32
))
9038 i
.types
[this_operand
]
9039 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9049 /* Make sure the memory operand we've been dealt is valid.
9050 Return 1 on success, 0 on a failure. */
9053 i386_index_check (const char *operand_string
)
9055 const char *kind
= "base/index";
9056 enum flag_code addr_mode
= i386_addressing_mode ();
9058 if (current_templates
->start
->opcode_modifier
.isstring
9059 && !current_templates
->start
->opcode_modifier
.immext
9060 && (current_templates
->end
[-1].opcode_modifier
.isstring
9063 /* Memory operands of string insns are special in that they only allow
9064 a single register (rDI, rSI, or rBX) as their memory address. */
9065 const reg_entry
*expected_reg
;
9066 static const char *di_si
[][2] =
9072 static const char *bx
[] = { "ebx", "bx", "rbx" };
9074 kind
= "string address";
9076 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9078 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9080 if (!type
.bitfield
.baseindex
9081 || ((!i
.mem_operands
!= !intel_syntax
)
9082 && current_templates
->end
[-1].operand_types
[1]
9083 .bitfield
.baseindex
))
9084 type
= current_templates
->end
[-1].operand_types
[1];
9085 expected_reg
= hash_find (reg_hash
,
9086 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9090 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9092 if (i
.base_reg
!= expected_reg
9094 || operand_type_check (i
.types
[this_operand
], disp
))
9096 /* The second memory operand must have the same size as
9100 && !((addr_mode
== CODE_64BIT
9101 && i
.base_reg
->reg_type
.bitfield
.qword
)
9102 || (addr_mode
== CODE_32BIT
9103 ? i
.base_reg
->reg_type
.bitfield
.dword
9104 : i
.base_reg
->reg_type
.bitfield
.word
)))
9107 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9109 intel_syntax
? '[' : '(',
9111 expected_reg
->reg_name
,
9112 intel_syntax
? ']' : ')');
9119 as_bad (_("`%s' is not a valid %s expression"),
9120 operand_string
, kind
);
9125 if (addr_mode
!= CODE_16BIT
)
9127 /* 32-bit/64-bit checks. */
9129 && (addr_mode
== CODE_64BIT
9130 ? !i
.base_reg
->reg_type
.bitfield
.qword
9131 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9133 || (i
.base_reg
->reg_num
9134 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9136 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9137 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9138 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9139 && ((addr_mode
== CODE_64BIT
9140 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9141 || i
.index_reg
->reg_num
== RegRiz
)
9142 : !(i
.index_reg
->reg_type
.bitfield
.dword
9143 || i
.index_reg
->reg_num
== RegEiz
))
9144 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9147 /* bndmk, bndldx, and bndstx have special restrictions. */
9148 if (current_templates
->start
->base_opcode
== 0xf30f1b
9149 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9151 /* They cannot use RIP-relative addressing. */
9152 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9154 as_bad (_("`%s' cannot be used here"), operand_string
);
9158 /* bndldx and bndstx ignore their scale factor. */
9159 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9160 && i
.log2_scale_factor
)
9161 as_warn (_("register scaling is being ignored here"));
9166 /* 16-bit checks. */
9168 && (!i
.base_reg
->reg_type
.bitfield
.word
9169 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9171 && (!i
.index_reg
->reg_type
.bitfield
.word
9172 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9174 && i
.base_reg
->reg_num
< 6
9175 && i
.index_reg
->reg_num
>= 6
9176 && i
.log2_scale_factor
== 0))))
9183 /* Handle vector immediates. */
9186 RC_SAE_immediate (const char *imm_start
)
9188 unsigned int match_found
, j
;
9189 const char *pstr
= imm_start
;
9197 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9199 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9203 rc_op
.type
= RC_NamesTable
[j
].type
;
9204 rc_op
.operand
= this_operand
;
9205 i
.rounding
= &rc_op
;
9209 as_bad (_("duplicated `%s'"), imm_start
);
9212 pstr
+= RC_NamesTable
[j
].len
;
9222 as_bad (_("Missing '}': '%s'"), imm_start
);
9225 /* RC/SAE immediate string should contain nothing more. */;
9228 as_bad (_("Junk after '}': '%s'"), imm_start
);
9232 exp
= &im_expressions
[i
.imm_operands
++];
9233 i
.op
[this_operand
].imms
= exp
;
9235 exp
->X_op
= O_constant
;
9236 exp
->X_add_number
= 0;
9237 exp
->X_add_symbol
= (symbolS
*) 0;
9238 exp
->X_op_symbol
= (symbolS
*) 0;
9240 i
.types
[this_operand
].bitfield
.imm8
= 1;
9244 /* Only string instructions can have a second memory operand, so
9245 reduce current_templates to just those if it contains any. */
9247 maybe_adjust_templates (void)
9249 const insn_template
*t
;
9251 gas_assert (i
.mem_operands
== 1);
9253 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9254 if (t
->opcode_modifier
.isstring
)
9257 if (t
< current_templates
->end
)
9259 static templates aux_templates
;
9260 bfd_boolean recheck
;
9262 aux_templates
.start
= t
;
9263 for (; t
< current_templates
->end
; ++t
)
9264 if (!t
->opcode_modifier
.isstring
)
9266 aux_templates
.end
= t
;
9268 /* Determine whether to re-check the first memory operand. */
9269 recheck
= (aux_templates
.start
!= current_templates
->start
9270 || t
!= current_templates
->end
);
9272 current_templates
= &aux_templates
;
9277 if (i
.memop1_string
!= NULL
9278 && i386_index_check (i
.memop1_string
) == 0)
9287 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9291 i386_att_operand (char *operand_string
)
9295 char *op_string
= operand_string
;
9297 if (is_space_char (*op_string
))
9300 /* We check for an absolute prefix (differentiating,
9301 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9302 if (*op_string
== ABSOLUTE_PREFIX
)
9305 if (is_space_char (*op_string
))
9307 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9310 /* Check if operand is a register. */
9311 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9313 i386_operand_type temp
;
9315 /* Check for a segment override by searching for ':' after a
9316 segment register. */
9318 if (is_space_char (*op_string
))
9320 if (*op_string
== ':'
9321 && (r
->reg_type
.bitfield
.sreg2
9322 || r
->reg_type
.bitfield
.sreg3
))
9327 i
.seg
[i
.mem_operands
] = &es
;
9330 i
.seg
[i
.mem_operands
] = &cs
;
9333 i
.seg
[i
.mem_operands
] = &ss
;
9336 i
.seg
[i
.mem_operands
] = &ds
;
9339 i
.seg
[i
.mem_operands
] = &fs
;
9342 i
.seg
[i
.mem_operands
] = &gs
;
9346 /* Skip the ':' and whitespace. */
9348 if (is_space_char (*op_string
))
9351 if (!is_digit_char (*op_string
)
9352 && !is_identifier_char (*op_string
)
9353 && *op_string
!= '('
9354 && *op_string
!= ABSOLUTE_PREFIX
)
9356 as_bad (_("bad memory operand `%s'"), op_string
);
9359 /* Handle case of %es:*foo. */
9360 if (*op_string
== ABSOLUTE_PREFIX
)
9363 if (is_space_char (*op_string
))
9365 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9367 goto do_memory_reference
;
9370 /* Handle vector operations. */
9371 if (*op_string
== '{')
9373 op_string
= check_VecOperations (op_string
, NULL
);
9374 if (op_string
== NULL
)
9380 as_bad (_("junk `%s' after register"), op_string
);
9384 temp
.bitfield
.baseindex
= 0;
9385 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9387 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9388 i
.op
[this_operand
].regs
= r
;
9391 else if (*op_string
== REGISTER_PREFIX
)
9393 as_bad (_("bad register name `%s'"), op_string
);
9396 else if (*op_string
== IMMEDIATE_PREFIX
)
9399 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9401 as_bad (_("immediate operand illegal with absolute jump"));
9404 if (!i386_immediate (op_string
))
9407 else if (RC_SAE_immediate (operand_string
))
9409 /* If it is a RC or SAE immediate, do nothing. */
9412 else if (is_digit_char (*op_string
)
9413 || is_identifier_char (*op_string
)
9414 || *op_string
== '"'
9415 || *op_string
== '(')
9417 /* This is a memory reference of some sort. */
9420 /* Start and end of displacement string expression (if found). */
9421 char *displacement_string_start
;
9422 char *displacement_string_end
;
9425 do_memory_reference
:
9426 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9428 if ((i
.mem_operands
== 1
9429 && !current_templates
->start
->opcode_modifier
.isstring
)
9430 || i
.mem_operands
== 2)
9432 as_bad (_("too many memory references for `%s'"),
9433 current_templates
->start
->name
);
9437 /* Check for base index form. We detect the base index form by
9438 looking for an ')' at the end of the operand, searching
9439 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9441 base_string
= op_string
+ strlen (op_string
);
9443 /* Handle vector operations. */
9444 vop_start
= strchr (op_string
, '{');
9445 if (vop_start
&& vop_start
< base_string
)
9447 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9449 base_string
= vop_start
;
9453 if (is_space_char (*base_string
))
9456 /* If we only have a displacement, set-up for it to be parsed later. */
9457 displacement_string_start
= op_string
;
9458 displacement_string_end
= base_string
+ 1;
9460 if (*base_string
== ')')
9463 unsigned int parens_balanced
= 1;
9464 /* We've already checked that the number of left & right ()'s are
9465 equal, so this loop will not be infinite. */
9469 if (*base_string
== ')')
9471 if (*base_string
== '(')
9474 while (parens_balanced
);
9476 temp_string
= base_string
;
9478 /* Skip past '(' and whitespace. */
9480 if (is_space_char (*base_string
))
9483 if (*base_string
== ','
9484 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9487 displacement_string_end
= temp_string
;
9489 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9493 base_string
= end_op
;
9494 if (is_space_char (*base_string
))
9498 /* There may be an index reg or scale factor here. */
9499 if (*base_string
== ',')
9502 if (is_space_char (*base_string
))
9505 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9508 base_string
= end_op
;
9509 if (is_space_char (*base_string
))
9511 if (*base_string
== ',')
9514 if (is_space_char (*base_string
))
9517 else if (*base_string
!= ')')
9519 as_bad (_("expecting `,' or `)' "
9520 "after index register in `%s'"),
9525 else if (*base_string
== REGISTER_PREFIX
)
9527 end_op
= strchr (base_string
, ',');
9530 as_bad (_("bad register name `%s'"), base_string
);
9534 /* Check for scale factor. */
9535 if (*base_string
!= ')')
9537 char *end_scale
= i386_scale (base_string
);
9542 base_string
= end_scale
;
9543 if (is_space_char (*base_string
))
9545 if (*base_string
!= ')')
9547 as_bad (_("expecting `)' "
9548 "after scale factor in `%s'"),
9553 else if (!i
.index_reg
)
9555 as_bad (_("expecting index register or scale factor "
9556 "after `,'; got '%c'"),
9561 else if (*base_string
!= ')')
9563 as_bad (_("expecting `,' or `)' "
9564 "after base register in `%s'"),
9569 else if (*base_string
== REGISTER_PREFIX
)
9571 end_op
= strchr (base_string
, ',');
9574 as_bad (_("bad register name `%s'"), base_string
);
9579 /* If there's an expression beginning the operand, parse it,
9580 assuming displacement_string_start and
9581 displacement_string_end are meaningful. */
9582 if (displacement_string_start
!= displacement_string_end
)
9584 if (!i386_displacement (displacement_string_start
,
9585 displacement_string_end
))
9589 /* Special case for (%dx) while doing input/output op. */
9591 && operand_type_equal (&i
.base_reg
->reg_type
,
9592 ®16_inoutportreg
)
9594 && i
.log2_scale_factor
== 0
9595 && i
.seg
[i
.mem_operands
] == 0
9596 && !operand_type_check (i
.types
[this_operand
], disp
))
9598 i
.types
[this_operand
] = inoutportreg
;
9602 if (i386_index_check (operand_string
) == 0)
9604 i
.types
[this_operand
].bitfield
.mem
= 1;
9605 if (i
.mem_operands
== 0)
9606 i
.memop1_string
= xstrdup (operand_string
);
9611 /* It's not a memory operand; argh! */
9612 as_bad (_("invalid char %s beginning operand %d `%s'"),
9613 output_invalid (*op_string
),
9618 return 1; /* Normal return. */
9621 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9622 that an rs_machine_dependent frag may reach. */
9625 i386_frag_max_var (fragS
*frag
)
9627 /* The only relaxable frags are for jumps.
9628 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9629 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9630 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9633 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9635 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9637 /* STT_GNU_IFUNC symbol must go through PLT. */
9638 if ((symbol_get_bfdsym (fr_symbol
)->flags
9639 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9642 if (!S_IS_EXTERNAL (fr_symbol
))
9643 /* Symbol may be weak or local. */
9644 return !S_IS_WEAK (fr_symbol
);
9646 /* Global symbols with non-default visibility can't be preempted. */
9647 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9650 if (fr_var
!= NO_RELOC
)
9651 switch ((enum bfd_reloc_code_real
) fr_var
)
9653 case BFD_RELOC_386_PLT32
:
9654 case BFD_RELOC_X86_64_PLT32
:
9655 /* Symbol with PLT relocation may be preempted. */
9661 /* Global symbols with default visibility in a shared library may be
9662 preempted by another definition. */
9667 /* md_estimate_size_before_relax()
9669 Called just before relax() for rs_machine_dependent frags. The x86
9670 assembler uses these frags to handle variable size jump
9673 Any symbol that is now undefined will not become defined.
9674 Return the correct fr_subtype in the frag.
9675 Return the initial "guess for variable size of frag" to caller.
9676 The guess is actually the growth beyond the fixed part. Whatever
9677 we do to grow the fixed or variable part contributes to our
9681 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9683 /* We've already got fragP->fr_subtype right; all we have to do is
9684 check for un-relaxable symbols. On an ELF system, we can't relax
9685 an externally visible symbol, because it may be overridden by a
9687 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9690 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9693 #if defined (OBJ_COFF) && defined (TE_PE)
9694 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9695 && S_IS_WEAK (fragP
->fr_symbol
))
9699 /* Symbol is undefined in this segment, or we need to keep a
9700 reloc so that weak symbols can be overridden. */
9701 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9702 enum bfd_reloc_code_real reloc_type
;
9703 unsigned char *opcode
;
9706 if (fragP
->fr_var
!= NO_RELOC
)
9707 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9709 reloc_type
= BFD_RELOC_16_PCREL
;
9710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9711 else if (need_plt32_p (fragP
->fr_symbol
))
9712 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9715 reloc_type
= BFD_RELOC_32_PCREL
;
9717 old_fr_fix
= fragP
->fr_fix
;
9718 opcode
= (unsigned char *) fragP
->fr_opcode
;
9720 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9723 /* Make jmp (0xeb) a (d)word displacement jump. */
9725 fragP
->fr_fix
+= size
;
9726 fix_new (fragP
, old_fr_fix
, size
,
9728 fragP
->fr_offset
, 1,
9734 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9736 /* Negate the condition, and branch past an
9737 unconditional jump. */
9740 /* Insert an unconditional jump. */
9742 /* We added two extra opcode bytes, and have a two byte
9744 fragP
->fr_fix
+= 2 + 2;
9745 fix_new (fragP
, old_fr_fix
+ 2, 2,
9747 fragP
->fr_offset
, 1,
9754 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9759 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9761 fragP
->fr_offset
, 1,
9763 fixP
->fx_signed
= 1;
9767 /* This changes the byte-displacement jump 0x7N
9768 to the (d)word-displacement jump 0x0f,0x8N. */
9769 opcode
[1] = opcode
[0] + 0x10;
9770 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9771 /* We've added an opcode byte. */
9772 fragP
->fr_fix
+= 1 + size
;
9773 fix_new (fragP
, old_fr_fix
+ 1, size
,
9775 fragP
->fr_offset
, 1,
9780 BAD_CASE (fragP
->fr_subtype
);
9784 return fragP
->fr_fix
- old_fr_fix
;
9787 /* Guess size depending on current relax state. Initially the relax
9788 state will correspond to a short jump and we return 1, because
9789 the variable part of the frag (the branch offset) is one byte
9790 long. However, we can relax a section more than once and in that
9791 case we must either set fr_subtype back to the unrelaxed state,
9792 or return the value for the appropriate branch. */
9793 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9796 /* Called after relax() is finished.
9798 In: Address of frag.
9799 fr_type == rs_machine_dependent.
9800 fr_subtype is what the address relaxed to.
9802 Out: Any fixSs and constants are set up.
9803 Caller will turn frag into a ".space 0". */
9806 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9809 unsigned char *opcode
;
9810 unsigned char *where_to_put_displacement
= NULL
;
9811 offsetT target_address
;
9812 offsetT opcode_address
;
9813 unsigned int extension
= 0;
9814 offsetT displacement_from_opcode_start
;
9816 opcode
= (unsigned char *) fragP
->fr_opcode
;
9818 /* Address we want to reach in file space. */
9819 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9821 /* Address opcode resides at in file space. */
9822 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9824 /* Displacement from opcode start to fill into instruction. */
9825 displacement_from_opcode_start
= target_address
- opcode_address
;
9827 if ((fragP
->fr_subtype
& BIG
) == 0)
9829 /* Don't have to change opcode. */
9830 extension
= 1; /* 1 opcode + 1 displacement */
9831 where_to_put_displacement
= &opcode
[1];
9835 if (no_cond_jump_promotion
9836 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9837 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9838 _("long jump required"));
9840 switch (fragP
->fr_subtype
)
9842 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9843 extension
= 4; /* 1 opcode + 4 displacement */
9845 where_to_put_displacement
= &opcode
[1];
9848 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9849 extension
= 2; /* 1 opcode + 2 displacement */
9851 where_to_put_displacement
= &opcode
[1];
9854 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9855 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9856 extension
= 5; /* 2 opcode + 4 displacement */
9857 opcode
[1] = opcode
[0] + 0x10;
9858 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9859 where_to_put_displacement
= &opcode
[2];
9862 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9863 extension
= 3; /* 2 opcode + 2 displacement */
9864 opcode
[1] = opcode
[0] + 0x10;
9865 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9866 where_to_put_displacement
= &opcode
[2];
9869 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9874 where_to_put_displacement
= &opcode
[3];
9878 BAD_CASE (fragP
->fr_subtype
);
9883 /* If size if less then four we are sure that the operand fits,
9884 but if it's 4, then it could be that the displacement is larger
9886 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9888 && ((addressT
) (displacement_from_opcode_start
- extension
9889 + ((addressT
) 1 << 31))
9890 > (((addressT
) 2 << 31) - 1)))
9892 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9893 _("jump target out of range"));
9894 /* Make us emit 0. */
9895 displacement_from_opcode_start
= extension
;
9897 /* Now put displacement after opcode. */
9898 md_number_to_chars ((char *) where_to_put_displacement
,
9899 (valueT
) (displacement_from_opcode_start
- extension
),
9900 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9901 fragP
->fr_fix
+= extension
;
9904 /* Apply a fixup (fixP) to segment data, once it has been determined
9905 by our caller that we have all the info we need to fix it up.
9907 Parameter valP is the pointer to the value of the bits.
9909 On the 386, immediates, displacements, and data pointers are all in
9910 the same (little-endian) format, so we don't need to care about which
9914 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9916 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9917 valueT value
= *valP
;
9919 #if !defined (TE_Mach)
9922 switch (fixP
->fx_r_type
)
9928 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9931 case BFD_RELOC_X86_64_32S
:
9932 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9935 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9938 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9943 if (fixP
->fx_addsy
!= NULL
9944 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9945 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9946 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9947 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9948 && !use_rela_relocations
)
9950 /* This is a hack. There should be a better way to handle this.
9951 This covers for the fact that bfd_install_relocation will
9952 subtract the current location (for partial_inplace, PC relative
9953 relocations); see more below. */
9957 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9960 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9965 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9968 || (symbol_section_p (fixP
->fx_addsy
)
9969 && sym_seg
!= absolute_section
))
9970 && !generic_force_reloc (fixP
))
9972 /* Yes, we add the values in twice. This is because
9973 bfd_install_relocation subtracts them out again. I think
9974 bfd_install_relocation is broken, but I don't dare change
9976 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9980 #if defined (OBJ_COFF) && defined (TE_PE)
9981 /* For some reason, the PE format does not store a
9982 section address offset for a PC relative symbol. */
9983 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9984 || S_IS_WEAK (fixP
->fx_addsy
))
9985 value
+= md_pcrel_from (fixP
);
9988 #if defined (OBJ_COFF) && defined (TE_PE)
9989 if (fixP
->fx_addsy
!= NULL
9990 && S_IS_WEAK (fixP
->fx_addsy
)
9991 /* PR 16858: Do not modify weak function references. */
9992 && ! fixP
->fx_pcrel
)
9994 #if !defined (TE_PEP)
9995 /* For x86 PE weak function symbols are neither PC-relative
9996 nor do they set S_IS_FUNCTION. So the only reliable way
9997 to detect them is to check the flags of their containing
9999 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10000 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10004 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10008 /* Fix a few things - the dynamic linker expects certain values here,
10009 and we must not disappoint it. */
10010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10011 if (IS_ELF
&& fixP
->fx_addsy
)
10012 switch (fixP
->fx_r_type
)
10014 case BFD_RELOC_386_PLT32
:
10015 case BFD_RELOC_X86_64_PLT32
:
10016 /* Make the jump instruction point to the address of the operand. At
10017 runtime we merely add the offset to the actual PLT entry. */
10021 case BFD_RELOC_386_TLS_GD
:
10022 case BFD_RELOC_386_TLS_LDM
:
10023 case BFD_RELOC_386_TLS_IE_32
:
10024 case BFD_RELOC_386_TLS_IE
:
10025 case BFD_RELOC_386_TLS_GOTIE
:
10026 case BFD_RELOC_386_TLS_GOTDESC
:
10027 case BFD_RELOC_X86_64_TLSGD
:
10028 case BFD_RELOC_X86_64_TLSLD
:
10029 case BFD_RELOC_X86_64_GOTTPOFF
:
10030 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10031 value
= 0; /* Fully resolved at runtime. No addend. */
10033 case BFD_RELOC_386_TLS_LE
:
10034 case BFD_RELOC_386_TLS_LDO_32
:
10035 case BFD_RELOC_386_TLS_LE_32
:
10036 case BFD_RELOC_X86_64_DTPOFF32
:
10037 case BFD_RELOC_X86_64_DTPOFF64
:
10038 case BFD_RELOC_X86_64_TPOFF32
:
10039 case BFD_RELOC_X86_64_TPOFF64
:
10040 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10043 case BFD_RELOC_386_TLS_DESC_CALL
:
10044 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10045 value
= 0; /* Fully resolved at runtime. No addend. */
10046 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10050 case BFD_RELOC_VTABLE_INHERIT
:
10051 case BFD_RELOC_VTABLE_ENTRY
:
10058 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10060 #endif /* !defined (TE_Mach) */
10062 /* Are we finished with this relocation now? */
10063 if (fixP
->fx_addsy
== NULL
)
10065 #if defined (OBJ_COFF) && defined (TE_PE)
10066 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10069 /* Remember value for tc_gen_reloc. */
10070 fixP
->fx_addnumber
= value
;
10071 /* Clear out the frag for now. */
10075 else if (use_rela_relocations
)
10077 fixP
->fx_no_overflow
= 1;
10078 /* Remember value for tc_gen_reloc. */
10079 fixP
->fx_addnumber
= value
;
10083 md_number_to_chars (p
, value
, fixP
->fx_size
);
10087 md_atof (int type
, char *litP
, int *sizeP
)
10089 /* This outputs the LITTLENUMs in REVERSE order;
10090 in accord with the bigendian 386. */
10091 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10094 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10097 output_invalid (int c
)
10100 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10103 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10104 "(0x%x)", (unsigned char) c
);
10105 return output_invalid_buf
;
10108 /* REG_STRING starts *before* REGISTER_PREFIX. */
10110 static const reg_entry
*
10111 parse_real_register (char *reg_string
, char **end_op
)
10113 char *s
= reg_string
;
10115 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10116 const reg_entry
*r
;
10118 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10119 if (*s
== REGISTER_PREFIX
)
10122 if (is_space_char (*s
))
10125 p
= reg_name_given
;
10126 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10128 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10129 return (const reg_entry
*) NULL
;
10133 /* For naked regs, make sure that we are not dealing with an identifier.
10134 This prevents confusing an identifier like `eax_var' with register
10136 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10137 return (const reg_entry
*) NULL
;
10141 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10143 /* Handle floating point regs, allowing spaces in the (i) part. */
10144 if (r
== i386_regtab
/* %st is first entry of table */)
10146 if (is_space_char (*s
))
10151 if (is_space_char (*s
))
10153 if (*s
>= '0' && *s
<= '7')
10155 int fpr
= *s
- '0';
10157 if (is_space_char (*s
))
10162 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10167 /* We have "%st(" then garbage. */
10168 return (const reg_entry
*) NULL
;
10172 if (r
== NULL
|| allow_pseudo_reg
)
10175 if (operand_type_all_zero (&r
->reg_type
))
10176 return (const reg_entry
*) NULL
;
10178 if ((r
->reg_type
.bitfield
.dword
10179 || r
->reg_type
.bitfield
.sreg3
10180 || r
->reg_type
.bitfield
.control
10181 || r
->reg_type
.bitfield
.debug
10182 || r
->reg_type
.bitfield
.test
)
10183 && !cpu_arch_flags
.bitfield
.cpui386
)
10184 return (const reg_entry
*) NULL
;
10186 if (r
->reg_type
.bitfield
.tbyte
10187 && !cpu_arch_flags
.bitfield
.cpu8087
10188 && !cpu_arch_flags
.bitfield
.cpu287
10189 && !cpu_arch_flags
.bitfield
.cpu387
)
10190 return (const reg_entry
*) NULL
;
10192 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
10193 return (const reg_entry
*) NULL
;
10195 if (r
->reg_type
.bitfield
.xmmword
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
10196 return (const reg_entry
*) NULL
;
10198 if (r
->reg_type
.bitfield
.ymmword
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
10199 return (const reg_entry
*) NULL
;
10201 if (r
->reg_type
.bitfield
.zmmword
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
10202 return (const reg_entry
*) NULL
;
10204 if (r
->reg_type
.bitfield
.regmask
10205 && !cpu_arch_flags
.bitfield
.cpuregmask
)
10206 return (const reg_entry
*) NULL
;
10208 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10209 if (!allow_index_reg
10210 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10211 return (const reg_entry
*) NULL
;
10213 /* Upper 16 vector register is only available with VREX in 64bit
10215 if ((r
->reg_flags
& RegVRex
))
10217 if (i
.vec_encoding
== vex_encoding_default
)
10218 i
.vec_encoding
= vex_encoding_evex
;
10220 if (!cpu_arch_flags
.bitfield
.cpuvrex
10221 || i
.vec_encoding
!= vex_encoding_evex
10222 || flag_code
!= CODE_64BIT
)
10223 return (const reg_entry
*) NULL
;
10226 if (((r
->reg_flags
& (RegRex64
| RegRex
))
10227 || r
->reg_type
.bitfield
.qword
)
10228 && (!cpu_arch_flags
.bitfield
.cpulm
10229 || !operand_type_equal (&r
->reg_type
, &control
))
10230 && flag_code
!= CODE_64BIT
)
10231 return (const reg_entry
*) NULL
;
10233 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10234 return (const reg_entry
*) NULL
;
10239 /* REG_STRING starts *before* REGISTER_PREFIX. */
10241 static const reg_entry
*
10242 parse_register (char *reg_string
, char **end_op
)
10244 const reg_entry
*r
;
10246 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10247 r
= parse_real_register (reg_string
, end_op
);
10252 char *save
= input_line_pointer
;
10256 input_line_pointer
= reg_string
;
10257 c
= get_symbol_name (®_string
);
10258 symbolP
= symbol_find (reg_string
);
10259 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10261 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10263 know (e
->X_op
== O_register
);
10264 know (e
->X_add_number
>= 0
10265 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10266 r
= i386_regtab
+ e
->X_add_number
;
10267 if ((r
->reg_flags
& RegVRex
))
10268 i
.vec_encoding
= vex_encoding_evex
;
10269 *end_op
= input_line_pointer
;
10271 *input_line_pointer
= c
;
10272 input_line_pointer
= save
;
10278 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10280 const reg_entry
*r
;
10281 char *end
= input_line_pointer
;
10284 r
= parse_register (name
, &input_line_pointer
);
10285 if (r
&& end
<= input_line_pointer
)
10287 *nextcharP
= *input_line_pointer
;
10288 *input_line_pointer
= 0;
10289 e
->X_op
= O_register
;
10290 e
->X_add_number
= r
- i386_regtab
;
10293 input_line_pointer
= end
;
10295 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10299 md_operand (expressionS
*e
)
10302 const reg_entry
*r
;
10304 switch (*input_line_pointer
)
10306 case REGISTER_PREFIX
:
10307 r
= parse_real_register (input_line_pointer
, &end
);
10310 e
->X_op
= O_register
;
10311 e
->X_add_number
= r
- i386_regtab
;
10312 input_line_pointer
= end
;
10317 gas_assert (intel_syntax
);
10318 end
= input_line_pointer
++;
10320 if (*input_line_pointer
== ']')
10322 ++input_line_pointer
;
10323 e
->X_op_symbol
= make_expr_symbol (e
);
10324 e
->X_add_symbol
= NULL
;
10325 e
->X_add_number
= 0;
10330 e
->X_op
= O_absent
;
10331 input_line_pointer
= end
;
10338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10339 const char *md_shortopts
= "kVQ:sqnO::";
10341 const char *md_shortopts
= "qnO::";
10344 #define OPTION_32 (OPTION_MD_BASE + 0)
10345 #define OPTION_64 (OPTION_MD_BASE + 1)
10346 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10347 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10348 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10349 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10350 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10351 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10352 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10353 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10354 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10355 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10356 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10357 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10358 #define OPTION_X32 (OPTION_MD_BASE + 14)
10359 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10360 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10361 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10362 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10363 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10364 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10365 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10366 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10367 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10368 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10370 struct option md_longopts
[] =
10372 {"32", no_argument
, NULL
, OPTION_32
},
10373 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10374 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10375 {"64", no_argument
, NULL
, OPTION_64
},
10377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10378 {"x32", no_argument
, NULL
, OPTION_X32
},
10379 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10381 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10382 {"march", required_argument
, NULL
, OPTION_MARCH
},
10383 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10384 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10385 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10386 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10387 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10388 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10389 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10390 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10391 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10392 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10393 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10394 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10395 # if defined (TE_PE) || defined (TE_PEP)
10396 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10398 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10399 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10400 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10401 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10402 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10403 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10404 {NULL
, no_argument
, NULL
, 0}
10406 size_t md_longopts_size
= sizeof (md_longopts
);
10409 md_parse_option (int c
, const char *arg
)
10412 char *arch
, *next
, *saved
;
10417 optimize_align_code
= 0;
10421 quiet_warnings
= 1;
10424 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10425 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10426 should be emitted or not. FIXME: Not implemented. */
10430 /* -V: SVR4 argument to print version ID. */
10432 print_version_id ();
10435 /* -k: Ignore for FreeBSD compatibility. */
10440 /* -s: On i386 Solaris, this tells the native assembler to use
10441 .stab instead of .stab.excl. We always use .stab anyhow. */
10444 case OPTION_MSHARED
:
10448 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10449 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10452 const char **list
, **l
;
10454 list
= bfd_target_list ();
10455 for (l
= list
; *l
!= NULL
; l
++)
10456 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10457 || strcmp (*l
, "coff-x86-64") == 0
10458 || strcmp (*l
, "pe-x86-64") == 0
10459 || strcmp (*l
, "pei-x86-64") == 0
10460 || strcmp (*l
, "mach-o-x86-64") == 0)
10462 default_arch
= "x86_64";
10466 as_fatal (_("no compiled in support for x86_64"));
10472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10476 const char **list
, **l
;
10478 list
= bfd_target_list ();
10479 for (l
= list
; *l
!= NULL
; l
++)
10480 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10482 default_arch
= "x86_64:32";
10486 as_fatal (_("no compiled in support for 32bit x86_64"));
10490 as_fatal (_("32bit x86_64 is only supported for ELF"));
10495 default_arch
= "i386";
10498 case OPTION_DIVIDE
:
10499 #ifdef SVR4_COMMENT_CHARS
10504 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10506 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10510 i386_comment_chars
= n
;
10516 saved
= xstrdup (arg
);
10518 /* Allow -march=+nosse. */
10524 as_fatal (_("invalid -march= option: `%s'"), arg
);
10525 next
= strchr (arch
, '+');
10528 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10530 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10533 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10536 cpu_arch_name
= cpu_arch
[j
].name
;
10537 cpu_sub_arch_name
= NULL
;
10538 cpu_arch_flags
= cpu_arch
[j
].flags
;
10539 cpu_arch_isa
= cpu_arch
[j
].type
;
10540 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10541 if (!cpu_arch_tune_set
)
10543 cpu_arch_tune
= cpu_arch_isa
;
10544 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10548 else if (*cpu_arch
[j
].name
== '.'
10549 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10551 /* ISA extension. */
10552 i386_cpu_flags flags
;
10554 flags
= cpu_flags_or (cpu_arch_flags
,
10555 cpu_arch
[j
].flags
);
10557 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10559 if (cpu_sub_arch_name
)
10561 char *name
= cpu_sub_arch_name
;
10562 cpu_sub_arch_name
= concat (name
,
10564 (const char *) NULL
);
10568 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10569 cpu_arch_flags
= flags
;
10570 cpu_arch_isa_flags
= flags
;
10574 = cpu_flags_or (cpu_arch_isa_flags
,
10575 cpu_arch
[j
].flags
);
10580 if (j
>= ARRAY_SIZE (cpu_arch
))
10582 /* Disable an ISA extension. */
10583 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10584 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10586 i386_cpu_flags flags
;
10588 flags
= cpu_flags_and_not (cpu_arch_flags
,
10589 cpu_noarch
[j
].flags
);
10590 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10592 if (cpu_sub_arch_name
)
10594 char *name
= cpu_sub_arch_name
;
10595 cpu_sub_arch_name
= concat (arch
,
10596 (const char *) NULL
);
10600 cpu_sub_arch_name
= xstrdup (arch
);
10601 cpu_arch_flags
= flags
;
10602 cpu_arch_isa_flags
= flags
;
10607 if (j
>= ARRAY_SIZE (cpu_noarch
))
10608 j
= ARRAY_SIZE (cpu_arch
);
10611 if (j
>= ARRAY_SIZE (cpu_arch
))
10612 as_fatal (_("invalid -march= option: `%s'"), arg
);
10616 while (next
!= NULL
);
10622 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10623 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10625 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10627 cpu_arch_tune_set
= 1;
10628 cpu_arch_tune
= cpu_arch
[j
].type
;
10629 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10633 if (j
>= ARRAY_SIZE (cpu_arch
))
10634 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10637 case OPTION_MMNEMONIC
:
10638 if (strcasecmp (arg
, "att") == 0)
10639 intel_mnemonic
= 0;
10640 else if (strcasecmp (arg
, "intel") == 0)
10641 intel_mnemonic
= 1;
10643 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10646 case OPTION_MSYNTAX
:
10647 if (strcasecmp (arg
, "att") == 0)
10649 else if (strcasecmp (arg
, "intel") == 0)
10652 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10655 case OPTION_MINDEX_REG
:
10656 allow_index_reg
= 1;
10659 case OPTION_MNAKED_REG
:
10660 allow_naked_reg
= 1;
10663 case OPTION_MSSE2AVX
:
10667 case OPTION_MSSE_CHECK
:
10668 if (strcasecmp (arg
, "error") == 0)
10669 sse_check
= check_error
;
10670 else if (strcasecmp (arg
, "warning") == 0)
10671 sse_check
= check_warning
;
10672 else if (strcasecmp (arg
, "none") == 0)
10673 sse_check
= check_none
;
10675 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10678 case OPTION_MOPERAND_CHECK
:
10679 if (strcasecmp (arg
, "error") == 0)
10680 operand_check
= check_error
;
10681 else if (strcasecmp (arg
, "warning") == 0)
10682 operand_check
= check_warning
;
10683 else if (strcasecmp (arg
, "none") == 0)
10684 operand_check
= check_none
;
10686 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10689 case OPTION_MAVXSCALAR
:
10690 if (strcasecmp (arg
, "128") == 0)
10691 avxscalar
= vex128
;
10692 else if (strcasecmp (arg
, "256") == 0)
10693 avxscalar
= vex256
;
10695 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10698 case OPTION_MADD_BND_PREFIX
:
10699 add_bnd_prefix
= 1;
10702 case OPTION_MEVEXLIG
:
10703 if (strcmp (arg
, "128") == 0)
10704 evexlig
= evexl128
;
10705 else if (strcmp (arg
, "256") == 0)
10706 evexlig
= evexl256
;
10707 else if (strcmp (arg
, "512") == 0)
10708 evexlig
= evexl512
;
10710 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10713 case OPTION_MEVEXRCIG
:
10714 if (strcmp (arg
, "rne") == 0)
10716 else if (strcmp (arg
, "rd") == 0)
10718 else if (strcmp (arg
, "ru") == 0)
10720 else if (strcmp (arg
, "rz") == 0)
10723 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10726 case OPTION_MEVEXWIG
:
10727 if (strcmp (arg
, "0") == 0)
10729 else if (strcmp (arg
, "1") == 0)
10732 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10735 # if defined (TE_PE) || defined (TE_PEP)
10736 case OPTION_MBIG_OBJ
:
10741 case OPTION_MOMIT_LOCK_PREFIX
:
10742 if (strcasecmp (arg
, "yes") == 0)
10743 omit_lock_prefix
= 1;
10744 else if (strcasecmp (arg
, "no") == 0)
10745 omit_lock_prefix
= 0;
10747 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10750 case OPTION_MFENCE_AS_LOCK_ADD
:
10751 if (strcasecmp (arg
, "yes") == 0)
10753 else if (strcasecmp (arg
, "no") == 0)
10756 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10759 case OPTION_MRELAX_RELOCATIONS
:
10760 if (strcasecmp (arg
, "yes") == 0)
10761 generate_relax_relocations
= 1;
10762 else if (strcasecmp (arg
, "no") == 0)
10763 generate_relax_relocations
= 0;
10765 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10768 case OPTION_MAMD64
:
10772 case OPTION_MINTEL64
:
10780 /* Turn off -Os. */
10781 optimize_for_space
= 0;
10783 else if (*arg
== 's')
10785 optimize_for_space
= 1;
10786 /* Turn on all encoding optimizations. */
10791 optimize
= atoi (arg
);
10792 /* Turn off -Os. */
10793 optimize_for_space
= 0;
10803 #define MESSAGE_TEMPLATE \
10807 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10808 int *left_p
, const char *name
, int len
)
10810 int size
= sizeof (MESSAGE_TEMPLATE
);
10811 int left
= *left_p
;
10813 /* Reserve 2 spaces for ", " or ",\0" */
10816 /* Check if there is any room. */
10824 p
= mempcpy (p
, name
, len
);
10828 /* Output the current message now and start a new one. */
10831 fprintf (stream
, "%s\n", message
);
10833 left
= size
- (start
- message
) - len
- 2;
10835 gas_assert (left
>= 0);
10837 p
= mempcpy (p
, name
, len
);
10845 show_arch (FILE *stream
, int ext
, int check
)
10847 static char message
[] = MESSAGE_TEMPLATE
;
10848 char *start
= message
+ 27;
10850 int size
= sizeof (MESSAGE_TEMPLATE
);
10857 left
= size
- (start
- message
);
10858 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10860 /* Should it be skipped? */
10861 if (cpu_arch
[j
].skip
)
10864 name
= cpu_arch
[j
].name
;
10865 len
= cpu_arch
[j
].len
;
10868 /* It is an extension. Skip if we aren't asked to show it. */
10879 /* It is an processor. Skip if we show only extension. */
10882 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10884 /* It is an impossible processor - skip. */
10888 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10891 /* Display disabled extensions. */
10893 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10895 name
= cpu_noarch
[j
].name
;
10896 len
= cpu_noarch
[j
].len
;
10897 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10902 fprintf (stream
, "%s\n", message
);
10906 md_show_usage (FILE *stream
)
10908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10909 fprintf (stream
, _("\
10911 -V print assembler version number\n\
10914 fprintf (stream
, _("\
10915 -n Do not optimize code alignment\n\
10916 -q quieten some warnings\n"));
10917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10918 fprintf (stream
, _("\
10921 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10922 || defined (TE_PE) || defined (TE_PEP))
10923 fprintf (stream
, _("\
10924 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10926 #ifdef SVR4_COMMENT_CHARS
10927 fprintf (stream
, _("\
10928 --divide do not treat `/' as a comment character\n"));
10930 fprintf (stream
, _("\
10931 --divide ignored\n"));
10933 fprintf (stream
, _("\
10934 -march=CPU[,+EXTENSION...]\n\
10935 generate code for CPU and EXTENSION, CPU is one of:\n"));
10936 show_arch (stream
, 0, 1);
10937 fprintf (stream
, _("\
10938 EXTENSION is combination of:\n"));
10939 show_arch (stream
, 1, 0);
10940 fprintf (stream
, _("\
10941 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10942 show_arch (stream
, 0, 0);
10943 fprintf (stream
, _("\
10944 -msse2avx encode SSE instructions with VEX prefix\n"));
10945 fprintf (stream
, _("\
10946 -msse-check=[none|error|warning]\n\
10947 check SSE instructions\n"));
10948 fprintf (stream
, _("\
10949 -moperand-check=[none|error|warning]\n\
10950 check operand combinations for validity\n"));
10951 fprintf (stream
, _("\
10952 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10954 fprintf (stream
, _("\
10955 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10957 fprintf (stream
, _("\
10958 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10959 for EVEX.W bit ignored instructions\n"));
10960 fprintf (stream
, _("\
10961 -mevexrcig=[rne|rd|ru|rz]\n\
10962 encode EVEX instructions with specific EVEX.RC value\n\
10963 for SAE-only ignored instructions\n"));
10964 fprintf (stream
, _("\
10965 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10966 fprintf (stream
, _("\
10967 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10968 fprintf (stream
, _("\
10969 -mindex-reg support pseudo index registers\n"));
10970 fprintf (stream
, _("\
10971 -mnaked-reg don't require `%%' prefix for registers\n"));
10972 fprintf (stream
, _("\
10973 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10974 fprintf (stream
, _("\
10975 -mshared disable branch optimization for shared code\n"));
10976 # if defined (TE_PE) || defined (TE_PEP)
10977 fprintf (stream
, _("\
10978 -mbig-obj generate big object files\n"));
10980 fprintf (stream
, _("\
10981 -momit-lock-prefix=[no|yes]\n\
10982 strip all lock prefixes\n"));
10983 fprintf (stream
, _("\
10984 -mfence-as-lock-add=[no|yes]\n\
10985 encode lfence, mfence and sfence as\n\
10986 lock addl $0x0, (%%{re}sp)\n"));
10987 fprintf (stream
, _("\
10988 -mrelax-relocations=[no|yes]\n\
10989 generate relax relocations\n"));
10990 fprintf (stream
, _("\
10991 -mamd64 accept only AMD64 ISA\n"));
10992 fprintf (stream
, _("\
10993 -mintel64 accept only Intel64 ISA\n"));
10996 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10997 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10998 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11000 /* Pick the target format to use. */
11003 i386_target_format (void)
11005 if (!strncmp (default_arch
, "x86_64", 6))
11007 update_code_flag (CODE_64BIT
, 1);
11008 if (default_arch
[6] == '\0')
11009 x86_elf_abi
= X86_64_ABI
;
11011 x86_elf_abi
= X86_64_X32_ABI
;
11013 else if (!strcmp (default_arch
, "i386"))
11014 update_code_flag (CODE_32BIT
, 1);
11015 else if (!strcmp (default_arch
, "iamcu"))
11017 update_code_flag (CODE_32BIT
, 1);
11018 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11020 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11021 cpu_arch_name
= "iamcu";
11022 cpu_sub_arch_name
= NULL
;
11023 cpu_arch_flags
= iamcu_flags
;
11024 cpu_arch_isa
= PROCESSOR_IAMCU
;
11025 cpu_arch_isa_flags
= iamcu_flags
;
11026 if (!cpu_arch_tune_set
)
11028 cpu_arch_tune
= cpu_arch_isa
;
11029 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11032 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11033 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11037 as_fatal (_("unknown architecture"));
11039 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11040 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11041 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11042 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11044 switch (OUTPUT_FLAVOR
)
11046 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11047 case bfd_target_aout_flavour
:
11048 return AOUT_TARGET_FORMAT
;
11050 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11051 # if defined (TE_PE) || defined (TE_PEP)
11052 case bfd_target_coff_flavour
:
11053 if (flag_code
== CODE_64BIT
)
11054 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11057 # elif defined (TE_GO32)
11058 case bfd_target_coff_flavour
:
11059 return "coff-go32";
11061 case bfd_target_coff_flavour
:
11062 return "coff-i386";
11065 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11066 case bfd_target_elf_flavour
:
11068 const char *format
;
11070 switch (x86_elf_abi
)
11073 format
= ELF_TARGET_FORMAT
;
11076 use_rela_relocations
= 1;
11078 format
= ELF_TARGET_FORMAT64
;
11080 case X86_64_X32_ABI
:
11081 use_rela_relocations
= 1;
11083 disallow_64bit_reloc
= 1;
11084 format
= ELF_TARGET_FORMAT32
;
11087 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11089 if (x86_elf_abi
!= X86_64_ABI
)
11090 as_fatal (_("Intel L1OM is 64bit only"));
11091 return ELF_TARGET_L1OM_FORMAT
;
11093 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11095 if (x86_elf_abi
!= X86_64_ABI
)
11096 as_fatal (_("Intel K1OM is 64bit only"));
11097 return ELF_TARGET_K1OM_FORMAT
;
11099 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11101 if (x86_elf_abi
!= I386_ABI
)
11102 as_fatal (_("Intel MCU is 32bit only"));
11103 return ELF_TARGET_IAMCU_FORMAT
;
11109 #if defined (OBJ_MACH_O)
11110 case bfd_target_mach_o_flavour
:
11111 if (flag_code
== CODE_64BIT
)
11113 use_rela_relocations
= 1;
11115 return "mach-o-x86-64";
11118 return "mach-o-i386";
11126 #endif /* OBJ_MAYBE_ more than one */
11129 md_undefined_symbol (char *name
)
11131 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11132 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11133 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11134 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11138 if (symbol_find (name
))
11139 as_bad (_("GOT already in symbol table"));
11140 GOT_symbol
= symbol_new (name
, undefined_section
,
11141 (valueT
) 0, &zero_address_frag
);
11148 /* Round up a section size to the appropriate boundary. */
11151 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11153 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11154 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11156 /* For a.out, force the section size to be aligned. If we don't do
11157 this, BFD will align it for us, but it will not write out the
11158 final bytes of the section. This may be a bug in BFD, but it is
11159 easier to fix it here since that is how the other a.out targets
11163 align
= bfd_get_section_alignment (stdoutput
, segment
);
11164 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11171 /* On the i386, PC-relative offsets are relative to the start of the
11172 next instruction. That is, the address of the offset, plus its
11173 size, since the offset is always the last part of the insn. */
11176 md_pcrel_from (fixS
*fixP
)
11178 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11184 s_bss (int ignore ATTRIBUTE_UNUSED
)
11188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11190 obj_elf_section_change_hook ();
11192 temp
= get_absolute_expression ();
11193 subseg_set (bss_section
, (subsegT
) temp
);
11194 demand_empty_rest_of_line ();
11200 i386_validate_fix (fixS
*fixp
)
11202 if (fixp
->fx_subsy
)
11204 if (fixp
->fx_subsy
== GOT_symbol
)
11206 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11211 if (fixp
->fx_tcbit2
)
11212 fixp
->fx_r_type
= (fixp
->fx_tcbit
11213 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11214 : BFD_RELOC_X86_64_GOTPCRELX
);
11217 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11222 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11224 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11226 fixp
->fx_subsy
= 0;
11229 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11230 else if (!object_64bit
)
11232 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11233 && fixp
->fx_tcbit2
)
11234 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11240 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11243 bfd_reloc_code_real_type code
;
11245 switch (fixp
->fx_r_type
)
11247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11248 case BFD_RELOC_SIZE32
:
11249 case BFD_RELOC_SIZE64
:
11250 if (S_IS_DEFINED (fixp
->fx_addsy
)
11251 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11253 /* Resolve size relocation against local symbol to size of
11254 the symbol plus addend. */
11255 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11256 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11257 && !fits_in_unsigned_long (value
))
11258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11259 _("symbol size computation overflow"));
11260 fixp
->fx_addsy
= NULL
;
11261 fixp
->fx_subsy
= NULL
;
11262 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11266 /* Fall through. */
11268 case BFD_RELOC_X86_64_PLT32
:
11269 case BFD_RELOC_X86_64_GOT32
:
11270 case BFD_RELOC_X86_64_GOTPCREL
:
11271 case BFD_RELOC_X86_64_GOTPCRELX
:
11272 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11273 case BFD_RELOC_386_PLT32
:
11274 case BFD_RELOC_386_GOT32
:
11275 case BFD_RELOC_386_GOT32X
:
11276 case BFD_RELOC_386_GOTOFF
:
11277 case BFD_RELOC_386_GOTPC
:
11278 case BFD_RELOC_386_TLS_GD
:
11279 case BFD_RELOC_386_TLS_LDM
:
11280 case BFD_RELOC_386_TLS_LDO_32
:
11281 case BFD_RELOC_386_TLS_IE_32
:
11282 case BFD_RELOC_386_TLS_IE
:
11283 case BFD_RELOC_386_TLS_GOTIE
:
11284 case BFD_RELOC_386_TLS_LE_32
:
11285 case BFD_RELOC_386_TLS_LE
:
11286 case BFD_RELOC_386_TLS_GOTDESC
:
11287 case BFD_RELOC_386_TLS_DESC_CALL
:
11288 case BFD_RELOC_X86_64_TLSGD
:
11289 case BFD_RELOC_X86_64_TLSLD
:
11290 case BFD_RELOC_X86_64_DTPOFF32
:
11291 case BFD_RELOC_X86_64_DTPOFF64
:
11292 case BFD_RELOC_X86_64_GOTTPOFF
:
11293 case BFD_RELOC_X86_64_TPOFF32
:
11294 case BFD_RELOC_X86_64_TPOFF64
:
11295 case BFD_RELOC_X86_64_GOTOFF64
:
11296 case BFD_RELOC_X86_64_GOTPC32
:
11297 case BFD_RELOC_X86_64_GOT64
:
11298 case BFD_RELOC_X86_64_GOTPCREL64
:
11299 case BFD_RELOC_X86_64_GOTPC64
:
11300 case BFD_RELOC_X86_64_GOTPLT64
:
11301 case BFD_RELOC_X86_64_PLTOFF64
:
11302 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11303 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11304 case BFD_RELOC_RVA
:
11305 case BFD_RELOC_VTABLE_ENTRY
:
11306 case BFD_RELOC_VTABLE_INHERIT
:
11308 case BFD_RELOC_32_SECREL
:
11310 code
= fixp
->fx_r_type
;
11312 case BFD_RELOC_X86_64_32S
:
11313 if (!fixp
->fx_pcrel
)
11315 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11316 code
= fixp
->fx_r_type
;
11319 /* Fall through. */
11321 if (fixp
->fx_pcrel
)
11323 switch (fixp
->fx_size
)
11326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11327 _("can not do %d byte pc-relative relocation"),
11329 code
= BFD_RELOC_32_PCREL
;
11331 case 1: code
= BFD_RELOC_8_PCREL
; break;
11332 case 2: code
= BFD_RELOC_16_PCREL
; break;
11333 case 4: code
= BFD_RELOC_32_PCREL
; break;
11335 case 8: code
= BFD_RELOC_64_PCREL
; break;
11341 switch (fixp
->fx_size
)
11344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11345 _("can not do %d byte relocation"),
11347 code
= BFD_RELOC_32
;
11349 case 1: code
= BFD_RELOC_8
; break;
11350 case 2: code
= BFD_RELOC_16
; break;
11351 case 4: code
= BFD_RELOC_32
; break;
11353 case 8: code
= BFD_RELOC_64
; break;
11360 if ((code
== BFD_RELOC_32
11361 || code
== BFD_RELOC_32_PCREL
11362 || code
== BFD_RELOC_X86_64_32S
)
11364 && fixp
->fx_addsy
== GOT_symbol
)
11367 code
= BFD_RELOC_386_GOTPC
;
11369 code
= BFD_RELOC_X86_64_GOTPC32
;
11371 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11373 && fixp
->fx_addsy
== GOT_symbol
)
11375 code
= BFD_RELOC_X86_64_GOTPC64
;
11378 rel
= XNEW (arelent
);
11379 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11380 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11382 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11384 if (!use_rela_relocations
)
11386 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11387 vtable entry to be used in the relocation's section offset. */
11388 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11389 rel
->address
= fixp
->fx_offset
;
11390 #if defined (OBJ_COFF) && defined (TE_PE)
11391 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11392 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11397 /* Use the rela in 64bit mode. */
11400 if (disallow_64bit_reloc
)
11403 case BFD_RELOC_X86_64_DTPOFF64
:
11404 case BFD_RELOC_X86_64_TPOFF64
:
11405 case BFD_RELOC_64_PCREL
:
11406 case BFD_RELOC_X86_64_GOTOFF64
:
11407 case BFD_RELOC_X86_64_GOT64
:
11408 case BFD_RELOC_X86_64_GOTPCREL64
:
11409 case BFD_RELOC_X86_64_GOTPC64
:
11410 case BFD_RELOC_X86_64_GOTPLT64
:
11411 case BFD_RELOC_X86_64_PLTOFF64
:
11412 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11413 _("cannot represent relocation type %s in x32 mode"),
11414 bfd_get_reloc_code_name (code
));
11420 if (!fixp
->fx_pcrel
)
11421 rel
->addend
= fixp
->fx_offset
;
11425 case BFD_RELOC_X86_64_PLT32
:
11426 case BFD_RELOC_X86_64_GOT32
:
11427 case BFD_RELOC_X86_64_GOTPCREL
:
11428 case BFD_RELOC_X86_64_GOTPCRELX
:
11429 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11430 case BFD_RELOC_X86_64_TLSGD
:
11431 case BFD_RELOC_X86_64_TLSLD
:
11432 case BFD_RELOC_X86_64_GOTTPOFF
:
11433 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11434 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11435 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11438 rel
->addend
= (section
->vma
11440 + fixp
->fx_addnumber
11441 + md_pcrel_from (fixp
));
11446 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11447 if (rel
->howto
== NULL
)
11449 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11450 _("cannot represent relocation type %s"),
11451 bfd_get_reloc_code_name (code
));
11452 /* Set howto to a garbage value so that we can keep going. */
11453 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11454 gas_assert (rel
->howto
!= NULL
);
11460 #include "tc-i386-intel.c"
11463 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11465 int saved_naked_reg
;
11466 char saved_register_dot
;
11468 saved_naked_reg
= allow_naked_reg
;
11469 allow_naked_reg
= 1;
11470 saved_register_dot
= register_chars
['.'];
11471 register_chars
['.'] = '.';
11472 allow_pseudo_reg
= 1;
11473 expression_and_evaluate (exp
);
11474 allow_pseudo_reg
= 0;
11475 register_chars
['.'] = saved_register_dot
;
11476 allow_naked_reg
= saved_naked_reg
;
11478 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11480 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11482 exp
->X_op
= O_constant
;
11483 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11484 .dw2_regnum
[flag_code
>> 1];
11487 exp
->X_op
= O_illegal
;
11492 tc_x86_frame_initial_instructions (void)
11494 static unsigned int sp_regno
[2];
11496 if (!sp_regno
[flag_code
>> 1])
11498 char *saved_input
= input_line_pointer
;
11499 char sp
[][4] = {"esp", "rsp"};
11502 input_line_pointer
= sp
[flag_code
>> 1];
11503 tc_x86_parse_to_dw2regnum (&exp
);
11504 gas_assert (exp
.X_op
== O_constant
);
11505 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11506 input_line_pointer
= saved_input
;
11509 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11510 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11514 x86_dwarf2_addr_size (void)
11516 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11517 if (x86_elf_abi
== X86_64_X32_ABI
)
11520 return bfd_arch_bits_per_address (stdoutput
) / 8;
11524 i386_elf_section_type (const char *str
, size_t len
)
11526 if (flag_code
== CODE_64BIT
11527 && len
== sizeof ("unwind") - 1
11528 && strncmp (str
, "unwind", 6) == 0)
11529 return SHT_X86_64_UNWIND
;
11536 i386_solaris_fix_up_eh_frame (segT sec
)
11538 if (flag_code
== CODE_64BIT
)
11539 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11545 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11549 exp
.X_op
= O_secrel
;
11550 exp
.X_add_symbol
= symbol
;
11551 exp
.X_add_number
= 0;
11552 emit_expr (&exp
, size
);
11556 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11557 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11560 x86_64_section_letter (int letter
, const char **ptr_msg
)
11562 if (flag_code
== CODE_64BIT
)
11565 return SHF_X86_64_LARGE
;
11567 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11570 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11575 x86_64_section_word (char *str
, size_t len
)
11577 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11578 return SHF_X86_64_LARGE
;
11584 handle_large_common (int small ATTRIBUTE_UNUSED
)
11586 if (flag_code
!= CODE_64BIT
)
11588 s_comm_internal (0, elf_common_parse
);
11589 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11593 static segT lbss_section
;
11594 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11595 asection
*saved_bss_section
= bss_section
;
11597 if (lbss_section
== NULL
)
11599 flagword applicable
;
11600 segT seg
= now_seg
;
11601 subsegT subseg
= now_subseg
;
11603 /* The .lbss section is for local .largecomm symbols. */
11604 lbss_section
= subseg_new (".lbss", 0);
11605 applicable
= bfd_applicable_section_flags (stdoutput
);
11606 bfd_set_section_flags (stdoutput
, lbss_section
,
11607 applicable
& SEC_ALLOC
);
11608 seg_info (lbss_section
)->bss
= 1;
11610 subseg_set (seg
, subseg
);
11613 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11614 bss_section
= lbss_section
;
11616 s_comm_internal (0, elf_common_parse
);
11618 elf_com_section_ptr
= saved_com_section_ptr
;
11619 bss_section
= saved_bss_section
;
11622 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */