1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
42 #define DEFAULT_ARCH "i386"
47 #define INLINE __inline__
53 /* Prefixes will be emitted in the order defined below.
54 WAIT_PREFIX must be the first prefix since FWAIT is really is an
55 instruction, and so must come before any prefixes.
56 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
57 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
63 #define HLE_PREFIX REP_PREFIX
64 #define BND_PREFIX REP_PREFIX
66 #define REX_PREFIX 6 /* must come last. */
67 #define MAX_PREFIXES 7 /* max prefixes per opcode */
69 /* we define the syntax here (modulo base,index,scale syntax) */
70 #define REGISTER_PREFIX '%'
71 #define IMMEDIATE_PREFIX '$'
72 #define ABSOLUTE_PREFIX '*'
74 /* these are the instruction mnemonic suffixes in AT&T syntax or
75 memory operand size in Intel syntax. */
76 #define WORD_MNEM_SUFFIX 'w'
77 #define BYTE_MNEM_SUFFIX 'b'
78 #define SHORT_MNEM_SUFFIX 's'
79 #define LONG_MNEM_SUFFIX 'l'
80 #define QWORD_MNEM_SUFFIX 'q'
81 /* Intel Syntax. Use a non-ascii letter since since it never appears
83 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
85 #define END_OF_INSN '\0'
87 /* This matches the C -> StaticRounding alias in the opcode table. */
88 #define commutative staticrounding
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (unsigned int, unsigned int);
171 static enum flag_code
i386_addressing_mode (void);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (char);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const reg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 /* GNU_PROPERTY_X86_ISA_1_USED. */
194 static unsigned int x86_isa_1_used
;
195 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
196 static unsigned int x86_feature_2_used
;
197 /* Generate x86 used ISA and feature properties. */
198 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
201 static const char *default_arch
= DEFAULT_ARCH
;
203 /* parse_register() returns this when a register alias cannot be used. */
204 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
205 { Dw2Inval
, Dw2Inval
} };
207 static const reg_entry
*reg_eax
;
208 static const reg_entry
*reg_ds
;
209 static const reg_entry
*reg_es
;
210 static const reg_entry
*reg_ss
;
211 static const reg_entry
*reg_st0
;
212 static const reg_entry
*reg_k0
;
217 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
218 unsigned char bytes
[4];
220 /* Destination or source register specifier. */
221 const reg_entry
*register_specifier
;
224 /* 'md_assemble ()' gathers together information and puts it into a
231 const reg_entry
*regs
;
236 operand_size_mismatch
,
237 operand_type_mismatch
,
238 register_type_mismatch
,
239 number_of_operands_mismatch
,
240 invalid_instruction_suffix
,
242 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 rc_sae_operand_not_last_imm
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* Copied first memory operand string, for re-checking. */
309 /* PREFIX holds all the given prefix opcodes (usually null).
310 PREFIXES is the number of prefix opcodes. */
311 unsigned int prefixes
;
312 unsigned char prefix
[MAX_PREFIXES
];
314 /* Register is in low 3 bits of opcode. */
317 /* The operand to a branch insn indicates an absolute branch. */
320 /* Extended states. */
328 xstate_ymm
= 1 << 2 | xstate_xmm
,
330 xstate_zmm
= 1 << 3 | xstate_ymm
,
333 /* Use MASK state. */
337 /* Has GOTPC or TLS relocation. */
338 bool has_gotpc_tls_reloc
;
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes.
350 The struct describes masking, applied to OPERAND in the instruction.
351 REG is a pointer to the corresponding mask register. ZEROING tells
352 whether merging or zeroing mask is used. */
353 struct Mask_Operation
355 const reg_entry
*reg
;
356 unsigned int zeroing
;
357 /* The operand where this operation is associated. */
358 unsigned int operand
;
361 /* Rounding control and SAE attributes. */
374 unsigned int operand
;
377 /* Broadcasting attributes.
379 The struct describes broadcasting, applied to OPERAND. TYPE is
380 expresses the broadcast factor. */
381 struct Broadcast_Operation
383 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
386 /* Index of broadcasted operand. */
387 unsigned int operand
;
389 /* Number of bytes to broadcast. */
393 /* Compressed disp8*N attribute. */
394 unsigned int memshift
;
396 /* Prefer load or store in encoding. */
399 dir_encoding_default
= 0,
405 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
408 disp_encoding_default
= 0,
414 /* Prefer the REX byte in encoding. */
417 /* Disable instruction size optimization. */
420 /* How to encode vector instructions. */
423 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
478 && !defined (TE_GNU) \
479 && !defined (TE_LINUX) \
480 && !defined (TE_FreeBSD) \
481 && !defined (TE_DragonFly) \
482 && !defined (TE_NetBSD))
483 /* This array holds the chars that always start a comment. If the
484 pre-processor is disabled, these aren't very useful. The option
485 --divide will remove '/' from this list. */
486 const char *i386_comment_chars
= "#/";
487 #define SVR4_COMMENT_CHARS 1
488 #define PREFIX_SEPARATOR '\\'
491 const char *i386_comment_chars
= "#";
492 #define PREFIX_SEPARATOR '/'
495 /* This array holds the chars that only start a comment at the beginning of
496 a line. If the line seems to have the form '# 123 filename'
497 .line and .file directives will appear in the pre-processed output.
498 Note that input_file.c hand checks for '#' at the beginning of the
499 first line of the input file. This is because the compiler outputs
500 #NO_APP at the beginning of its output.
501 Also note that comments started like this one will always work if
502 '/' isn't otherwise defined. */
503 const char line_comment_chars
[] = "#/";
505 const char line_separator_chars
[] = ";";
507 /* Chars that can be used to separate mant from exp in floating point
509 const char EXP_CHARS
[] = "eE";
511 /* Chars that mean this number is a floating point constant
514 const char FLT_CHARS
[] = "fFdDxX";
516 /* Tables for lexical analysis. */
517 static char mnemonic_chars
[256];
518 static char register_chars
[256];
519 static char operand_chars
[256];
520 static char identifier_chars
[256];
521 static char digit_chars
[256];
523 /* Lexical macros. */
524 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
525 #define is_operand_char(x) (operand_chars[(unsigned char) x])
526 #define is_register_char(x) (register_chars[(unsigned char) x])
527 #define is_space_char(x) ((x) == ' ')
528 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
529 #define is_digit_char(x) (digit_chars[(unsigned char) x])
531 /* All non-digit non-letter characters that may occur in an operand. */
532 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
534 /* md_assemble() always leaves the strings it's passed unaltered. To
535 effect this we maintain a stack of saved characters that we've smashed
536 with '\0's (indicating end of strings for various sub-fields of the
537 assembler instruction). */
538 static char save_stack
[32];
539 static char *save_stack_p
;
540 #define END_STRING_AND_SAVE(s) \
541 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
542 #define RESTORE_END_STRING(s) \
543 do { *(s) = *--save_stack_p; } while (0)
545 /* The instruction we're assembling. */
548 /* Possible templates for current insn. */
549 static const templates
*current_templates
;
551 /* Per instruction expressionS buffers: max displacements & immediates. */
552 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
553 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
555 /* Current operand we are working on. */
556 static int this_operand
= -1;
558 /* We support four different modes. FLAG_CODE variable is used to distinguish
566 static enum flag_code flag_code
;
567 static unsigned int object_64bit
;
568 static unsigned int disallow_64bit_reloc
;
569 static int use_rela_relocations
= 0;
570 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
571 static const char *tls_get_addr
;
573 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
574 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
575 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
577 /* The ELF ABI to use. */
585 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
588 #if defined (TE_PE) || defined (TE_PEP)
589 /* Use big object file format. */
590 static int use_big_obj
= 0;
593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
594 /* 1 if generating code for a shared library. */
595 static int shared
= 0;
598 /* 1 for intel syntax,
600 static int intel_syntax
= 0;
602 static enum x86_64_isa
604 amd64
= 1, /* AMD64 ISA. */
605 intel64
/* Intel64 ISA. */
608 /* 1 for intel mnemonic,
609 0 if att mnemonic. */
610 static int intel_mnemonic
= !SYSV386_COMPAT
;
612 /* 1 if pseudo registers are permitted. */
613 static int allow_pseudo_reg
= 0;
615 /* 1 if register prefix % not required. */
616 static int allow_naked_reg
= 0;
618 /* 1 if the assembler should add BND prefix for all control-transferring
619 instructions supporting it, even if this prefix wasn't specified
621 static int add_bnd_prefix
= 0;
623 /* 1 if pseudo index register, eiz/riz, is allowed . */
624 static int allow_index_reg
= 0;
626 /* 1 if the assembler should ignore LOCK prefix, even if it was
627 specified explicitly. */
628 static int omit_lock_prefix
= 0;
630 /* 1 if the assembler should encode lfence, mfence, and sfence as
631 "lock addl $0, (%{re}sp)". */
632 static int avoid_fence
= 0;
634 /* 1 if lfence should be inserted after every load. */
635 static int lfence_after_load
= 0;
637 /* Non-zero if lfence should be inserted before indirect branch. */
638 static enum lfence_before_indirect_branch_kind
640 lfence_branch_none
= 0,
641 lfence_branch_register
,
642 lfence_branch_memory
,
645 lfence_before_indirect_branch
;
647 /* Non-zero if lfence should be inserted before ret. */
648 static enum lfence_before_ret_kind
650 lfence_before_ret_none
= 0,
651 lfence_before_ret_not
,
652 lfence_before_ret_or
,
653 lfence_before_ret_shl
657 /* Types of previous instruction is .byte or prefix. */
672 /* 1 if the assembler should generate relax relocations. */
674 static int generate_relax_relocations
675 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
677 static enum check_kind
683 sse_check
, operand_check
= check_warning
;
685 /* Non-zero if branches should be aligned within power of 2 boundary. */
686 static int align_branch_power
= 0;
688 /* Types of branches to align. */
689 enum align_branch_kind
691 align_branch_none
= 0,
692 align_branch_jcc
= 1,
693 align_branch_fused
= 2,
694 align_branch_jmp
= 3,
695 align_branch_call
= 4,
696 align_branch_indirect
= 5,
700 /* Type bits of branches to align. */
701 enum align_branch_bit
703 align_branch_jcc_bit
= 1 << align_branch_jcc
,
704 align_branch_fused_bit
= 1 << align_branch_fused
,
705 align_branch_jmp_bit
= 1 << align_branch_jmp
,
706 align_branch_call_bit
= 1 << align_branch_call
,
707 align_branch_indirect_bit
= 1 << align_branch_indirect
,
708 align_branch_ret_bit
= 1 << align_branch_ret
711 static unsigned int align_branch
= (align_branch_jcc_bit
712 | align_branch_fused_bit
713 | align_branch_jmp_bit
);
715 /* Types of condition jump used by macro-fusion. */
718 mf_jcc_jo
= 0, /* base opcode 0x70 */
719 mf_jcc_jc
, /* base opcode 0x72 */
720 mf_jcc_je
, /* base opcode 0x74 */
721 mf_jcc_jna
, /* base opcode 0x76 */
722 mf_jcc_js
, /* base opcode 0x78 */
723 mf_jcc_jp
, /* base opcode 0x7a */
724 mf_jcc_jl
, /* base opcode 0x7c */
725 mf_jcc_jle
, /* base opcode 0x7e */
728 /* Types of compare flag-modifying insntructions used by macro-fusion. */
731 mf_cmp_test_and
, /* test/cmp */
732 mf_cmp_alu_cmp
, /* add/sub/cmp */
733 mf_cmp_incdec
/* inc/dec */
736 /* The maximum padding size for fused jcc. CMP like instruction can
737 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
739 #define MAX_FUSED_JCC_PADDING_SIZE 20
741 /* The maximum number of prefixes added for an instruction. */
742 static unsigned int align_branch_prefix_size
= 5;
745 1. Clear the REX_W bit with register operand if possible.
746 2. Above plus use 128bit vector instruction to clear the full vector
749 static int optimize
= 0;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
755 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
758 static int optimize_for_space
= 0;
760 /* Register prefix used for error message. */
761 static const char *register_prefix
= "%";
763 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
764 leave, push, and pop instructions so that gcc has the same stack
765 frame as in 32 bit mode. */
766 static char stackop_size
= '\0';
768 /* Non-zero to optimize code alignment. */
769 int optimize_align_code
= 1;
771 /* Non-zero to quieten some warnings. */
772 static int quiet_warnings
= 0;
775 static const char *cpu_arch_name
= NULL
;
776 static char *cpu_sub_arch_name
= NULL
;
778 /* CPU feature flags. */
779 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
781 /* If we have selected a cpu we are generating instructions for. */
782 static int cpu_arch_tune_set
= 0;
784 /* Cpu we are generating instructions for. */
785 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
787 /* CPU feature flags of cpu we are generating instructions for. */
788 static i386_cpu_flags cpu_arch_tune_flags
;
790 /* CPU instruction set architecture used. */
791 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
793 /* CPU feature flags of instruction set architecture used. */
794 i386_cpu_flags cpu_arch_isa_flags
;
796 /* If set, conditional jumps are not automatically promoted to handle
797 larger than a byte offset. */
798 static unsigned int no_cond_jump_promotion
= 0;
800 /* Encode SSE instructions with VEX prefix. */
801 static unsigned int sse2avx
;
803 /* Encode scalar AVX instructions with specific vector length. */
810 /* Encode VEX WIG instructions with specific vex.w. */
817 /* Encode scalar EVEX LIG instructions with specific vector length. */
825 /* Encode EVEX WIG instructions with specific evex.w. */
832 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
833 static enum rc_type evexrcig
= rne
;
835 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
836 static symbolS
*GOT_symbol
;
838 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
839 unsigned int x86_dwarf2_return_column
;
841 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
842 int x86_cie_data_alignment
;
844 /* Interface to relax_segment.
845 There are 3 major relax states for 386 jump insns because the
846 different types of jumps add different sizes to frags when we're
847 figuring out what sort of jump to choose to reach a given label.
849 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
850 branches which are handled by md_estimate_size_before_relax() and
851 i386_generic_table_relax_frag(). */
854 #define UNCOND_JUMP 0
856 #define COND_JUMP86 2
857 #define BRANCH_PADDING 3
858 #define BRANCH_PREFIX 4
859 #define FUSED_JCC_PADDING 5
864 #define SMALL16 (SMALL | CODE16)
866 #define BIG16 (BIG | CODE16)
870 #define INLINE __inline__
876 #define ENCODE_RELAX_STATE(type, size) \
877 ((relax_substateT) (((type) << 2) | (size)))
878 #define TYPE_FROM_RELAX_STATE(s) \
880 #define DISP_SIZE_FROM_RELAX_STATE(s) \
881 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
883 /* This table is used by relax_frag to promote short jumps to long
884 ones where necessary. SMALL (short) jumps may be promoted to BIG
885 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
886 don't allow a short jump in a 32 bit code segment to be promoted to
887 a 16 bit offset jump because it's slower (requires data size
888 prefix), and doesn't work, unless the destination is in the bottom
889 64k of the code segment (The top 16 bits of eip are zeroed). */
891 const relax_typeS md_relax_table
[] =
894 1) most positive reach of this state,
895 2) most negative reach of this state,
896 3) how many bytes this mode will have in the variable part of the frag
897 4) which index into the table to try if we can't fit into this one. */
899 /* UNCOND_JUMP states. */
900 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
901 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
902 /* dword jmp adds 4 bytes to frag:
903 0 extra opcode bytes, 4 displacement bytes. */
905 /* word jmp adds 2 byte2 to frag:
906 0 extra opcode bytes, 2 displacement bytes. */
909 /* COND_JUMP states. */
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
911 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
912 /* dword conditionals adds 5 bytes to frag:
913 1 extra opcode byte, 4 displacement bytes. */
915 /* word conditionals add 3 bytes to frag:
916 1 extra opcode byte, 2 displacement bytes. */
919 /* COND_JUMP86 states. */
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
921 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
922 /* dword conditionals adds 5 bytes to frag:
923 1 extra opcode byte, 4 displacement bytes. */
925 /* word conditionals add 4 bytes to frag:
926 1 displacement byte and a 3 byte long branch insn. */
930 static const arch_entry cpu_arch
[] =
932 /* Do not replace the first two entries - i386_target_format()
933 relies on them being there in this order. */
934 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
935 CPU_GENERIC32_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
937 CPU_GENERIC64_FLAGS
, 0 },
938 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
946 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
948 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
950 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
952 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
954 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
955 CPU_PENTIUMPRO_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
958 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
960 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
962 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
964 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
965 CPU_NOCONA_FLAGS
, 0 },
966 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
968 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
970 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
971 CPU_CORE2_FLAGS
, 1 },
972 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
973 CPU_CORE2_FLAGS
, 0 },
974 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
975 CPU_COREI7_FLAGS
, 0 },
976 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
978 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
980 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
981 CPU_IAMCU_FLAGS
, 0 },
982 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
984 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
986 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
987 CPU_ATHLON_FLAGS
, 0 },
988 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
990 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
994 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
995 CPU_AMDFAM10_FLAGS
, 0 },
996 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
997 CPU_BDVER1_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
999 CPU_BDVER2_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1001 CPU_BDVER3_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1003 CPU_BDVER4_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1005 CPU_ZNVER1_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER2_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1009 CPU_ZNVER3_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1011 CPU_BTVER1_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1013 CPU_BTVER2_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1015 CPU_8087_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1023 CPU_CMOV_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1025 CPU_FXSR_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE2_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE3_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1035 CPU_SSE4A_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1037 CPU_SSSE3_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_1_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE4_2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX2_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512F_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512CD_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512ER_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512PF_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512DQ_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512BW_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512VL_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1065 CPU_VMFUNC_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1068 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVE_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEOPT_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVEC_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1075 CPU_XSAVES_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1078 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1081 CPU_PCLMUL_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1083 CPU_FSGSBASE_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1085 CPU_RDRND_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1087 CPU_F16C_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1089 CPU_BMI2_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1093 CPU_FMA4_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1099 CPU_MOVBE_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1101 CPU_CX16_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_LZCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1107 CPU_POPCNT_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1112 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1113 CPU_INVPCID_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1115 CPU_CLFLUSH_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1118 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1119 CPU_SYSCALL_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1121 CPU_RDTSCP_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOW_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1125 CPU_3DNOWA_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1127 CPU_PADLOCK_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 1 },
1130 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1131 CPU_SVME_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1133 CPU_SSE4A_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1142 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1143 CPU_RDSEED_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1145 CPU_PRFCHW_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1147 CPU_SMAP_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1153 CPU_CLFLUSHOPT_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1155 CPU_PREFETCHWT1_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1158 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1159 CPU_CLWB_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512IFMA_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512VBMI_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VBMI2_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_VNNI_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512_BITALG_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1177 CPU_AVX_VNNI_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1179 CPU_CLZERO_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1181 CPU_MWAITX_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1183 CPU_OSPKE_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1185 CPU_RDPID_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1187 CPU_PTWRITE_FLAGS
, 0 },
1188 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1190 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1191 CPU_SHSTK_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1193 CPU_GFNI_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1195 CPU_VAES_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1197 CPU_VPCLMULQDQ_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1199 CPU_WBNOINVD_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1201 CPU_PCONFIG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1203 CPU_WAITPKG_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1205 CPU_CLDEMOTE_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1207 CPU_AMX_INT8_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1209 CPU_AMX_BF16_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1211 CPU_AMX_TILE_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1213 CPU_MOVDIRI_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1215 CPU_MOVDIR64B_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1217 CPU_AVX512_BF16_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1219 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1222 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1223 CPU_ENQCMD_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1225 CPU_SERIALIZE_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1227 CPU_RDPRU_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1229 CPU_MCOMMIT_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1231 CPU_SEV_ES_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1233 CPU_TSXLDTRK_FLAGS
, 0 },
1234 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1236 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1237 CPU_WIDEKL_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1239 CPU_UINTR_FLAGS
, 0 },
1240 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1241 CPU_HRESET_FLAGS
, 0 },
1244 static const noarch_entry cpu_noarch
[] =
1246 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1247 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1248 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1249 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1250 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1251 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1252 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1255 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1256 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1257 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1258 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1259 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1260 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1279 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1280 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1282 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1283 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1284 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1285 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1288 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1289 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1290 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1291 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1292 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1293 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1294 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1295 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1296 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1300 /* Like s_lcomm_internal in gas/read.c but the alignment string
1301 is allowed to be optional. */
1304 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1311 && *input_line_pointer
== ',')
1313 align
= parse_align (needs_align
- 1);
1315 if (align
== (addressT
) -1)
1330 bss_alloc (symbolP
, size
, align
);
1335 pe_lcomm (int needs_align
)
1337 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1341 const pseudo_typeS md_pseudo_table
[] =
1343 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1344 {"align", s_align_bytes
, 0},
1346 {"align", s_align_ptwo
, 0},
1348 {"arch", set_cpu_arch
, 0},
1352 {"lcomm", pe_lcomm
, 1},
1354 {"ffloat", float_cons
, 'f'},
1355 {"dfloat", float_cons
, 'd'},
1356 {"tfloat", float_cons
, 'x'},
1358 {"slong", signed_cons
, 4},
1359 {"noopt", s_ignore
, 0},
1360 {"optim", s_ignore
, 0},
1361 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1362 {"code16", set_code_flag
, CODE_16BIT
},
1363 {"code32", set_code_flag
, CODE_32BIT
},
1365 {"code64", set_code_flag
, CODE_64BIT
},
1367 {"intel_syntax", set_intel_syntax
, 1},
1368 {"att_syntax", set_intel_syntax
, 0},
1369 {"intel_mnemonic", set_intel_mnemonic
, 1},
1370 {"att_mnemonic", set_intel_mnemonic
, 0},
1371 {"allow_index_reg", set_allow_index_reg
, 1},
1372 {"disallow_index_reg", set_allow_index_reg
, 0},
1373 {"sse_check", set_check
, 0},
1374 {"operand_check", set_check
, 1},
1375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1376 {"largecomm", handle_large_common
, 0},
1378 {"file", dwarf2_directive_file
, 0},
1379 {"loc", dwarf2_directive_loc
, 0},
1380 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1383 {"secrel32", pe_directive_secrel
, 0},
1388 /* For interface with expression (). */
1389 extern char *input_line_pointer
;
1391 /* Hash table for instruction mnemonic lookup. */
1392 static htab_t op_hash
;
1394 /* Hash table for register lookup. */
1395 static htab_t reg_hash
;
1397 /* Various efficient no-op patterns for aligning code labels.
1398 Note: Don't try to assemble the instructions in the comments.
1399 0L and 0w are not legal. */
1400 static const unsigned char f32_1
[] =
1402 static const unsigned char f32_2
[] =
1403 {0x66,0x90}; /* xchg %ax,%ax */
1404 static const unsigned char f32_3
[] =
1405 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1406 static const unsigned char f32_4
[] =
1407 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1408 static const unsigned char f32_6
[] =
1409 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1410 static const unsigned char f32_7
[] =
1411 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1412 static const unsigned char f16_3
[] =
1413 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1414 static const unsigned char f16_4
[] =
1415 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1416 static const unsigned char jump_disp8
[] =
1417 {0xeb}; /* jmp disp8 */
1418 static const unsigned char jump32_disp32
[] =
1419 {0xe9}; /* jmp disp32 */
1420 static const unsigned char jump16_disp32
[] =
1421 {0x66,0xe9}; /* jmp disp32 */
1422 /* 32-bit NOPs patterns. */
1423 static const unsigned char *const f32_patt
[] = {
1424 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1426 /* 16-bit NOPs patterns. */
1427 static const unsigned char *const f16_patt
[] = {
1428 f32_1
, f32_2
, f16_3
, f16_4
1430 /* nopl (%[re]ax) */
1431 static const unsigned char alt_3
[] =
1433 /* nopl 0(%[re]ax) */
1434 static const unsigned char alt_4
[] =
1435 {0x0f,0x1f,0x40,0x00};
1436 /* nopl 0(%[re]ax,%[re]ax,1) */
1437 static const unsigned char alt_5
[] =
1438 {0x0f,0x1f,0x44,0x00,0x00};
1439 /* nopw 0(%[re]ax,%[re]ax,1) */
1440 static const unsigned char alt_6
[] =
1441 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1442 /* nopl 0L(%[re]ax) */
1443 static const unsigned char alt_7
[] =
1444 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1445 /* nopl 0L(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_8
[] =
1447 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1448 /* nopw 0L(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_9
[] =
1450 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1451 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1452 static const unsigned char alt_10
[] =
1453 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1454 /* data16 nopw %cs:0L(%eax,%eax,1) */
1455 static const unsigned char alt_11
[] =
1456 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* 32-bit and 64-bit NOPs patterns. */
1458 static const unsigned char *const alt_patt
[] = {
1459 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1460 alt_9
, alt_10
, alt_11
1463 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1464 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1467 i386_output_nops (char *where
, const unsigned char *const *patt
,
1468 int count
, int max_single_nop_size
)
1471 /* Place the longer NOP first. */
1474 const unsigned char *nops
;
1476 if (max_single_nop_size
< 1)
1478 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1479 max_single_nop_size
);
1483 nops
= patt
[max_single_nop_size
- 1];
1485 /* Use the smaller one if the requsted one isn't available. */
1488 max_single_nop_size
--;
1489 nops
= patt
[max_single_nop_size
- 1];
1492 last
= count
% max_single_nop_size
;
1495 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1496 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1500 nops
= patt
[last
- 1];
1503 /* Use the smaller one plus one-byte NOP if the needed one
1506 nops
= patt
[last
- 1];
1507 memcpy (where
+ offset
, nops
, last
);
1508 where
[offset
+ last
] = *patt
[0];
1511 memcpy (where
+ offset
, nops
, last
);
1516 fits_in_imm7 (offsetT num
)
1518 return (num
& 0x7f) == num
;
1522 fits_in_imm31 (offsetT num
)
1524 return (num
& 0x7fffffff) == num
;
1527 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1528 single NOP instruction LIMIT. */
1531 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1533 const unsigned char *const *patt
= NULL
;
1534 int max_single_nop_size
;
1535 /* Maximum number of NOPs before switching to jump over NOPs. */
1536 int max_number_of_nops
;
1538 switch (fragP
->fr_type
)
1543 case rs_machine_dependent
:
1544 /* Allow NOP padding for jumps and calls. */
1545 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1546 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1553 /* We need to decide which NOP sequence to use for 32bit and
1554 64bit. When -mtune= is used:
1556 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1557 PROCESSOR_GENERIC32, f32_patt will be used.
1558 2. For the rest, alt_patt will be used.
1560 When -mtune= isn't used, alt_patt will be used if
1561 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1564 When -march= or .arch is used, we can't use anything beyond
1565 cpu_arch_isa_flags. */
1567 if (flag_code
== CODE_16BIT
)
1570 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1571 /* Limit number of NOPs to 2 in 16-bit mode. */
1572 max_number_of_nops
= 2;
1576 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1578 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1579 switch (cpu_arch_tune
)
1581 case PROCESSOR_UNKNOWN
:
1582 /* We use cpu_arch_isa_flags to check if we SHOULD
1583 optimize with nops. */
1584 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1589 case PROCESSOR_PENTIUM4
:
1590 case PROCESSOR_NOCONA
:
1591 case PROCESSOR_CORE
:
1592 case PROCESSOR_CORE2
:
1593 case PROCESSOR_COREI7
:
1594 case PROCESSOR_L1OM
:
1595 case PROCESSOR_K1OM
:
1596 case PROCESSOR_GENERIC64
:
1598 case PROCESSOR_ATHLON
:
1600 case PROCESSOR_AMDFAM10
:
1602 case PROCESSOR_ZNVER
:
1606 case PROCESSOR_I386
:
1607 case PROCESSOR_I486
:
1608 case PROCESSOR_PENTIUM
:
1609 case PROCESSOR_PENTIUMPRO
:
1610 case PROCESSOR_IAMCU
:
1611 case PROCESSOR_GENERIC32
:
1618 switch (fragP
->tc_frag_data
.tune
)
1620 case PROCESSOR_UNKNOWN
:
1621 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1622 PROCESSOR_UNKNOWN. */
1626 case PROCESSOR_I386
:
1627 case PROCESSOR_I486
:
1628 case PROCESSOR_PENTIUM
:
1629 case PROCESSOR_IAMCU
:
1631 case PROCESSOR_ATHLON
:
1633 case PROCESSOR_AMDFAM10
:
1635 case PROCESSOR_ZNVER
:
1637 case PROCESSOR_GENERIC32
:
1638 /* We use cpu_arch_isa_flags to check if we CAN optimize
1640 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1645 case PROCESSOR_PENTIUMPRO
:
1646 case PROCESSOR_PENTIUM4
:
1647 case PROCESSOR_NOCONA
:
1648 case PROCESSOR_CORE
:
1649 case PROCESSOR_CORE2
:
1650 case PROCESSOR_COREI7
:
1651 case PROCESSOR_L1OM
:
1652 case PROCESSOR_K1OM
:
1653 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1658 case PROCESSOR_GENERIC64
:
1664 if (patt
== f32_patt
)
1666 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1667 /* Limit number of NOPs to 2 for older processors. */
1668 max_number_of_nops
= 2;
1672 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1673 /* Limit number of NOPs to 7 for newer processors. */
1674 max_number_of_nops
= 7;
1679 limit
= max_single_nop_size
;
1681 if (fragP
->fr_type
== rs_fill_nop
)
1683 /* Output NOPs for .nop directive. */
1684 if (limit
> max_single_nop_size
)
1686 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1687 _("invalid single nop size: %d "
1688 "(expect within [0, %d])"),
1689 limit
, max_single_nop_size
);
1693 else if (fragP
->fr_type
!= rs_machine_dependent
)
1694 fragP
->fr_var
= count
;
1696 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1698 /* Generate jump over NOPs. */
1699 offsetT disp
= count
- 2;
1700 if (fits_in_imm7 (disp
))
1702 /* Use "jmp disp8" if possible. */
1704 where
[0] = jump_disp8
[0];
1710 unsigned int size_of_jump
;
1712 if (flag_code
== CODE_16BIT
)
1714 where
[0] = jump16_disp32
[0];
1715 where
[1] = jump16_disp32
[1];
1720 where
[0] = jump32_disp32
[0];
1724 count
-= size_of_jump
+ 4;
1725 if (!fits_in_imm31 (count
))
1727 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1728 _("jump over nop padding out of range"));
1732 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1733 where
+= size_of_jump
+ 4;
1737 /* Generate multiple NOPs. */
1738 i386_output_nops (where
, patt
, count
, limit
);
1742 operand_type_all_zero (const union i386_operand_type
*x
)
1744 switch (ARRAY_SIZE(x
->array
))
1755 return !x
->array
[0];
1762 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1764 switch (ARRAY_SIZE(x
->array
))
1780 x
->bitfield
.class = ClassNone
;
1781 x
->bitfield
.instance
= InstanceNone
;
1785 operand_type_equal (const union i386_operand_type
*x
,
1786 const union i386_operand_type
*y
)
1788 switch (ARRAY_SIZE(x
->array
))
1791 if (x
->array
[2] != y
->array
[2])
1795 if (x
->array
[1] != y
->array
[1])
1799 return x
->array
[0] == y
->array
[0];
1807 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1809 switch (ARRAY_SIZE(x
->array
))
1824 return !x
->array
[0];
1831 cpu_flags_equal (const union i386_cpu_flags
*x
,
1832 const union i386_cpu_flags
*y
)
1834 switch (ARRAY_SIZE(x
->array
))
1837 if (x
->array
[3] != y
->array
[3])
1841 if (x
->array
[2] != y
->array
[2])
1845 if (x
->array
[1] != y
->array
[1])
1849 return x
->array
[0] == y
->array
[0];
1857 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1859 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1860 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1863 static INLINE i386_cpu_flags
1864 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1866 switch (ARRAY_SIZE (x
.array
))
1869 x
.array
[3] &= y
.array
[3];
1872 x
.array
[2] &= y
.array
[2];
1875 x
.array
[1] &= y
.array
[1];
1878 x
.array
[0] &= y
.array
[0];
1886 static INLINE i386_cpu_flags
1887 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[3] |= y
.array
[3];
1895 x
.array
[2] |= y
.array
[2];
1898 x
.array
[1] |= y
.array
[1];
1901 x
.array
[0] |= y
.array
[0];
1909 static INLINE i386_cpu_flags
1910 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[3] &= ~y
.array
[3];
1918 x
.array
[2] &= ~y
.array
[2];
1921 x
.array
[1] &= ~y
.array
[1];
1924 x
.array
[0] &= ~y
.array
[0];
1932 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1934 #define CPU_FLAGS_ARCH_MATCH 0x1
1935 #define CPU_FLAGS_64BIT_MATCH 0x2
1937 #define CPU_FLAGS_PERFECT_MATCH \
1938 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1940 /* Return CPU flags match bits. */
1943 cpu_flags_match (const insn_template
*t
)
1945 i386_cpu_flags x
= t
->cpu_flags
;
1946 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1948 x
.bitfield
.cpu64
= 0;
1949 x
.bitfield
.cpuno64
= 0;
1951 if (cpu_flags_all_zero (&x
))
1953 /* This instruction is available on all archs. */
1954 match
|= CPU_FLAGS_ARCH_MATCH
;
1958 /* This instruction is available only on some archs. */
1959 i386_cpu_flags cpu
= cpu_arch_flags
;
1961 /* AVX512VL is no standalone feature - match it and then strip it. */
1962 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1964 x
.bitfield
.cpuavx512vl
= 0;
1966 cpu
= cpu_flags_and (x
, cpu
);
1967 if (!cpu_flags_all_zero (&cpu
))
1969 if (x
.bitfield
.cpuavx
)
1971 /* We need to check a few extra flags with AVX. */
1972 if (cpu
.bitfield
.cpuavx
1973 && (!t
->opcode_modifier
.sse2avx
1974 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1975 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1976 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1977 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1978 match
|= CPU_FLAGS_ARCH_MATCH
;
1980 else if (x
.bitfield
.cpuavx512f
)
1982 /* We need to check a few extra flags with AVX512F. */
1983 if (cpu
.bitfield
.cpuavx512f
1984 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1985 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1986 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1990 match
|= CPU_FLAGS_ARCH_MATCH
;
1996 static INLINE i386_operand_type
1997 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1999 if (x
.bitfield
.class != y
.bitfield
.class)
2000 x
.bitfield
.class = ClassNone
;
2001 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2002 x
.bitfield
.instance
= InstanceNone
;
2004 switch (ARRAY_SIZE (x
.array
))
2007 x
.array
[2] &= y
.array
[2];
2010 x
.array
[1] &= y
.array
[1];
2013 x
.array
[0] &= y
.array
[0];
2021 static INLINE i386_operand_type
2022 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2024 gas_assert (y
.bitfield
.class == ClassNone
);
2025 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2027 switch (ARRAY_SIZE (x
.array
))
2030 x
.array
[2] &= ~y
.array
[2];
2033 x
.array
[1] &= ~y
.array
[1];
2036 x
.array
[0] &= ~y
.array
[0];
2044 static INLINE i386_operand_type
2045 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2047 gas_assert (x
.bitfield
.class == ClassNone
||
2048 y
.bitfield
.class == ClassNone
||
2049 x
.bitfield
.class == y
.bitfield
.class);
2050 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2051 y
.bitfield
.instance
== InstanceNone
||
2052 x
.bitfield
.instance
== y
.bitfield
.instance
);
2054 switch (ARRAY_SIZE (x
.array
))
2057 x
.array
[2] |= y
.array
[2];
2060 x
.array
[1] |= y
.array
[1];
2063 x
.array
[0] |= y
.array
[0];
2071 static INLINE i386_operand_type
2072 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2074 gas_assert (y
.bitfield
.class == ClassNone
);
2075 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2077 switch (ARRAY_SIZE (x
.array
))
2080 x
.array
[2] ^= y
.array
[2];
2083 x
.array
[1] ^= y
.array
[1];
2086 x
.array
[0] ^= y
.array
[0];
2094 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2095 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2096 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2097 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2098 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2099 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2100 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2101 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2102 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2103 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2104 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2105 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2106 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2107 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2108 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2109 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2110 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2121 operand_type_check (i386_operand_type t
, enum operand_type c
)
2126 return t
.bitfield
.class == Reg
;
2129 return (t
.bitfield
.imm8
2133 || t
.bitfield
.imm32s
2134 || t
.bitfield
.imm64
);
2137 return (t
.bitfield
.disp8
2138 || t
.bitfield
.disp16
2139 || t
.bitfield
.disp32
2140 || t
.bitfield
.disp32s
2141 || t
.bitfield
.disp64
);
2144 return (t
.bitfield
.disp8
2145 || t
.bitfield
.disp16
2146 || t
.bitfield
.disp32
2147 || t
.bitfield
.disp32s
2148 || t
.bitfield
.disp64
2149 || t
.bitfield
.baseindex
);
2158 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2159 between operand GIVEN and opeand WANTED for instruction template T. */
2162 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2165 return !((i
.types
[given
].bitfield
.byte
2166 && !t
->operand_types
[wanted
].bitfield
.byte
)
2167 || (i
.types
[given
].bitfield
.word
2168 && !t
->operand_types
[wanted
].bitfield
.word
)
2169 || (i
.types
[given
].bitfield
.dword
2170 && !t
->operand_types
[wanted
].bitfield
.dword
)
2171 || (i
.types
[given
].bitfield
.qword
2172 && !t
->operand_types
[wanted
].bitfield
.qword
)
2173 || (i
.types
[given
].bitfield
.tbyte
2174 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2177 /* Return 1 if there is no conflict in SIMD register between operand
2178 GIVEN and opeand WANTED for instruction template T. */
2181 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2184 return !((i
.types
[given
].bitfield
.xmmword
2185 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2186 || (i
.types
[given
].bitfield
.ymmword
2187 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2188 || (i
.types
[given
].bitfield
.zmmword
2189 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2190 || (i
.types
[given
].bitfield
.tmmword
2191 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2194 /* Return 1 if there is no conflict in any size between operand GIVEN
2195 and opeand WANTED for instruction template T. */
2198 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2201 return (match_operand_size (t
, wanted
, given
)
2202 && !((i
.types
[given
].bitfield
.unspecified
2203 && !i
.broadcast
.type
2204 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2205 || (i
.types
[given
].bitfield
.fword
2206 && !t
->operand_types
[wanted
].bitfield
.fword
)
2207 /* For scalar opcode templates to allow register and memory
2208 operands at the same time, some special casing is needed
2209 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2210 down-conversion vpmov*. */
2211 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2212 && t
->operand_types
[wanted
].bitfield
.byte
2213 + t
->operand_types
[wanted
].bitfield
.word
2214 + t
->operand_types
[wanted
].bitfield
.dword
2215 + t
->operand_types
[wanted
].bitfield
.qword
2216 > !!t
->opcode_modifier
.broadcast
)
2217 ? (i
.types
[given
].bitfield
.xmmword
2218 || i
.types
[given
].bitfield
.ymmword
2219 || i
.types
[given
].bitfield
.zmmword
)
2220 : !match_simd_size(t
, wanted
, given
))));
2223 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2224 operands for instruction template T, and it has MATCH_REVERSE set if there
2225 is no size conflict on any operands for the template with operands reversed
2226 (and the template allows for reversing in the first place). */
2228 #define MATCH_STRAIGHT 1
2229 #define MATCH_REVERSE 2
2231 static INLINE
unsigned int
2232 operand_size_match (const insn_template
*t
)
2234 unsigned int j
, match
= MATCH_STRAIGHT
;
2236 /* Don't check non-absolute jump instructions. */
2237 if (t
->opcode_modifier
.jump
2238 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2241 /* Check memory and accumulator operand size. */
2242 for (j
= 0; j
< i
.operands
; j
++)
2244 if (i
.types
[j
].bitfield
.class != Reg
2245 && i
.types
[j
].bitfield
.class != RegSIMD
2246 && t
->opcode_modifier
.anysize
)
2249 if (t
->operand_types
[j
].bitfield
.class == Reg
2250 && !match_operand_size (t
, j
, j
))
2256 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2257 && !match_simd_size (t
, j
, j
))
2263 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2264 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2270 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2277 if (!t
->opcode_modifier
.d
)
2281 i
.error
= operand_size_mismatch
;
2285 /* Check reverse. */
2286 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2288 for (j
= 0; j
< i
.operands
; j
++)
2290 unsigned int given
= i
.operands
- j
- 1;
2292 if (t
->operand_types
[j
].bitfield
.class == Reg
2293 && !match_operand_size (t
, j
, given
))
2296 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2297 && !match_simd_size (t
, j
, given
))
2300 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2301 && (!match_operand_size (t
, j
, given
)
2302 || !match_simd_size (t
, j
, given
)))
2305 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2309 return match
| MATCH_REVERSE
;
2313 operand_type_match (i386_operand_type overlap
,
2314 i386_operand_type given
)
2316 i386_operand_type temp
= overlap
;
2318 temp
.bitfield
.unspecified
= 0;
2319 temp
.bitfield
.byte
= 0;
2320 temp
.bitfield
.word
= 0;
2321 temp
.bitfield
.dword
= 0;
2322 temp
.bitfield
.fword
= 0;
2323 temp
.bitfield
.qword
= 0;
2324 temp
.bitfield
.tbyte
= 0;
2325 temp
.bitfield
.xmmword
= 0;
2326 temp
.bitfield
.ymmword
= 0;
2327 temp
.bitfield
.zmmword
= 0;
2328 temp
.bitfield
.tmmword
= 0;
2329 if (operand_type_all_zero (&temp
))
2332 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2336 i
.error
= operand_type_mismatch
;
2340 /* If given types g0 and g1 are registers they must be of the same type
2341 unless the expected operand type register overlap is null.
2342 Some Intel syntax memory operand size checking also happens here. */
2345 operand_type_register_match (i386_operand_type g0
,
2346 i386_operand_type t0
,
2347 i386_operand_type g1
,
2348 i386_operand_type t1
)
2350 if (g0
.bitfield
.class != Reg
2351 && g0
.bitfield
.class != RegSIMD
2352 && (!operand_type_check (g0
, anymem
)
2353 || g0
.bitfield
.unspecified
2354 || (t0
.bitfield
.class != Reg
2355 && t0
.bitfield
.class != RegSIMD
)))
2358 if (g1
.bitfield
.class != Reg
2359 && g1
.bitfield
.class != RegSIMD
2360 && (!operand_type_check (g1
, anymem
)
2361 || g1
.bitfield
.unspecified
2362 || (t1
.bitfield
.class != Reg
2363 && t1
.bitfield
.class != RegSIMD
)))
2366 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2367 && g0
.bitfield
.word
== g1
.bitfield
.word
2368 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2369 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2370 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2371 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2372 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2375 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2376 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2377 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2378 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2379 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2380 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2381 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2384 i
.error
= register_type_mismatch
;
2389 static INLINE
unsigned int
2390 register_number (const reg_entry
*r
)
2392 unsigned int nr
= r
->reg_num
;
2394 if (r
->reg_flags
& RegRex
)
2397 if (r
->reg_flags
& RegVRex
)
2403 static INLINE
unsigned int
2404 mode_from_disp_size (i386_operand_type t
)
2406 if (t
.bitfield
.disp8
)
2408 else if (t
.bitfield
.disp16
2409 || t
.bitfield
.disp32
2410 || t
.bitfield
.disp32s
)
2417 fits_in_signed_byte (addressT num
)
2419 return num
+ 0x80 <= 0xff;
2423 fits_in_unsigned_byte (addressT num
)
2429 fits_in_unsigned_word (addressT num
)
2431 return num
<= 0xffff;
2435 fits_in_signed_word (addressT num
)
2437 return num
+ 0x8000 <= 0xffff;
2441 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2446 return num
+ 0x80000000 <= 0xffffffff;
2448 } /* fits_in_signed_long() */
2451 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2456 return num
<= 0xffffffff;
2458 } /* fits_in_unsigned_long() */
2461 fits_in_disp8 (offsetT num
)
2463 int shift
= i
.memshift
;
2469 mask
= (1 << shift
) - 1;
2471 /* Return 0 if NUM isn't properly aligned. */
2475 /* Check if NUM will fit in 8bit after shift. */
2476 return fits_in_signed_byte (num
>> shift
);
2480 fits_in_imm4 (offsetT num
)
2482 return (num
& 0xf) == num
;
2485 static i386_operand_type
2486 smallest_imm_type (offsetT num
)
2488 i386_operand_type t
;
2490 operand_type_set (&t
, 0);
2491 t
.bitfield
.imm64
= 1;
2493 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2495 /* This code is disabled on the 486 because all the Imm1 forms
2496 in the opcode table are slower on the i486. They're the
2497 versions with the implicitly specified single-position
2498 displacement, which has another syntax if you really want to
2500 t
.bitfield
.imm1
= 1;
2501 t
.bitfield
.imm8
= 1;
2502 t
.bitfield
.imm8s
= 1;
2503 t
.bitfield
.imm16
= 1;
2504 t
.bitfield
.imm32
= 1;
2505 t
.bitfield
.imm32s
= 1;
2507 else if (fits_in_signed_byte (num
))
2509 t
.bitfield
.imm8
= 1;
2510 t
.bitfield
.imm8s
= 1;
2511 t
.bitfield
.imm16
= 1;
2512 t
.bitfield
.imm32
= 1;
2513 t
.bitfield
.imm32s
= 1;
2515 else if (fits_in_unsigned_byte (num
))
2517 t
.bitfield
.imm8
= 1;
2518 t
.bitfield
.imm16
= 1;
2519 t
.bitfield
.imm32
= 1;
2520 t
.bitfield
.imm32s
= 1;
2522 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2524 t
.bitfield
.imm16
= 1;
2525 t
.bitfield
.imm32
= 1;
2526 t
.bitfield
.imm32s
= 1;
2528 else if (fits_in_signed_long (num
))
2530 t
.bitfield
.imm32
= 1;
2531 t
.bitfield
.imm32s
= 1;
2533 else if (fits_in_unsigned_long (num
))
2534 t
.bitfield
.imm32
= 1;
2540 offset_in_range (offsetT val
, int size
)
2546 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2547 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2548 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2550 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2555 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2557 char buf1
[40], buf2
[40];
2559 bfd_sprintf_vma (stdoutput
, buf1
, val
);
2560 bfd_sprintf_vma (stdoutput
, buf2
, val
& mask
);
2561 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2576 a. PREFIX_EXIST if attempting to add a prefix where one from the
2577 same class already exists.
2578 b. PREFIX_LOCK if lock prefix is added.
2579 c. PREFIX_REP if rep/repne prefix is added.
2580 d. PREFIX_DS if ds prefix is added.
2581 e. PREFIX_OTHER if other prefix is added.
2584 static enum PREFIX_GROUP
2585 add_prefix (unsigned int prefix
)
2587 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2590 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2591 && flag_code
== CODE_64BIT
)
2593 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2594 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2595 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2596 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2607 case DS_PREFIX_OPCODE
:
2610 case CS_PREFIX_OPCODE
:
2611 case ES_PREFIX_OPCODE
:
2612 case FS_PREFIX_OPCODE
:
2613 case GS_PREFIX_OPCODE
:
2614 case SS_PREFIX_OPCODE
:
2618 case REPNE_PREFIX_OPCODE
:
2619 case REPE_PREFIX_OPCODE
:
2624 case LOCK_PREFIX_OPCODE
:
2633 case ADDR_PREFIX_OPCODE
:
2637 case DATA_PREFIX_OPCODE
:
2641 if (i
.prefix
[q
] != 0)
2649 i
.prefix
[q
] |= prefix
;
2652 as_bad (_("same type of prefix used twice"));
2658 update_code_flag (int value
, int check
)
2660 PRINTF_LIKE ((*as_error
));
2662 flag_code
= (enum flag_code
) value
;
2663 if (flag_code
== CODE_64BIT
)
2665 cpu_arch_flags
.bitfield
.cpu64
= 1;
2666 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2670 cpu_arch_flags
.bitfield
.cpu64
= 0;
2671 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2673 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2676 as_error
= as_fatal
;
2679 (*as_error
) (_("64bit mode not supported on `%s'."),
2680 cpu_arch_name
? cpu_arch_name
: default_arch
);
2682 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2685 as_error
= as_fatal
;
2688 (*as_error
) (_("32bit mode not supported on `%s'."),
2689 cpu_arch_name
? cpu_arch_name
: default_arch
);
2691 stackop_size
= '\0';
2695 set_code_flag (int value
)
2697 update_code_flag (value
, 0);
2701 set_16bit_gcc_code_flag (int new_code_flag
)
2703 flag_code
= (enum flag_code
) new_code_flag
;
2704 if (flag_code
!= CODE_16BIT
)
2706 cpu_arch_flags
.bitfield
.cpu64
= 0;
2707 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2708 stackop_size
= LONG_MNEM_SUFFIX
;
2712 set_intel_syntax (int syntax_flag
)
2714 /* Find out if register prefixing is specified. */
2715 int ask_naked_reg
= 0;
2718 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2721 int e
= get_symbol_name (&string
);
2723 if (strcmp (string
, "prefix") == 0)
2725 else if (strcmp (string
, "noprefix") == 0)
2728 as_bad (_("bad argument to syntax directive."));
2729 (void) restore_line_pointer (e
);
2731 demand_empty_rest_of_line ();
2733 intel_syntax
= syntax_flag
;
2735 if (ask_naked_reg
== 0)
2736 allow_naked_reg
= (intel_syntax
2737 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2739 allow_naked_reg
= (ask_naked_reg
< 0);
2741 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2743 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2744 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2745 register_prefix
= allow_naked_reg
? "" : "%";
2749 set_intel_mnemonic (int mnemonic_flag
)
2751 intel_mnemonic
= mnemonic_flag
;
2755 set_allow_index_reg (int flag
)
2757 allow_index_reg
= flag
;
2761 set_check (int what
)
2763 enum check_kind
*kind
;
2768 kind
= &operand_check
;
2779 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2782 int e
= get_symbol_name (&string
);
2784 if (strcmp (string
, "none") == 0)
2786 else if (strcmp (string
, "warning") == 0)
2787 *kind
= check_warning
;
2788 else if (strcmp (string
, "error") == 0)
2789 *kind
= check_error
;
2791 as_bad (_("bad argument to %s_check directive."), str
);
2792 (void) restore_line_pointer (e
);
2795 as_bad (_("missing argument for %s_check directive"), str
);
2797 demand_empty_rest_of_line ();
2801 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2802 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2805 static const char *arch
;
2807 /* Intel LIOM is only supported on ELF. */
2813 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2814 use default_arch. */
2815 arch
= cpu_arch_name
;
2817 arch
= default_arch
;
2820 /* If we are targeting Intel MCU, we must enable it. */
2821 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2822 || new_flag
.bitfield
.cpuiamcu
)
2825 /* If we are targeting Intel L1OM, we must enable it. */
2826 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2827 || new_flag
.bitfield
.cpul1om
)
2830 /* If we are targeting Intel K1OM, we must enable it. */
2831 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2832 || new_flag
.bitfield
.cpuk1om
)
2835 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2840 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2844 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2847 int e
= get_symbol_name (&string
);
2849 i386_cpu_flags flags
;
2851 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2853 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2855 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2859 cpu_arch_name
= cpu_arch
[j
].name
;
2860 cpu_sub_arch_name
= NULL
;
2861 cpu_arch_flags
= cpu_arch
[j
].flags
;
2862 if (flag_code
== CODE_64BIT
)
2864 cpu_arch_flags
.bitfield
.cpu64
= 1;
2865 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2869 cpu_arch_flags
.bitfield
.cpu64
= 0;
2870 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2872 cpu_arch_isa
= cpu_arch
[j
].type
;
2873 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2874 if (!cpu_arch_tune_set
)
2876 cpu_arch_tune
= cpu_arch_isa
;
2877 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2882 flags
= cpu_flags_or (cpu_arch_flags
,
2885 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2887 if (cpu_sub_arch_name
)
2889 char *name
= cpu_sub_arch_name
;
2890 cpu_sub_arch_name
= concat (name
,
2892 (const char *) NULL
);
2896 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2897 cpu_arch_flags
= flags
;
2898 cpu_arch_isa_flags
= flags
;
2902 = cpu_flags_or (cpu_arch_isa_flags
,
2904 (void) restore_line_pointer (e
);
2905 demand_empty_rest_of_line ();
2910 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2912 /* Disable an ISA extension. */
2913 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2914 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2916 flags
= cpu_flags_and_not (cpu_arch_flags
,
2917 cpu_noarch
[j
].flags
);
2918 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2920 if (cpu_sub_arch_name
)
2922 char *name
= cpu_sub_arch_name
;
2923 cpu_sub_arch_name
= concat (name
, string
,
2924 (const char *) NULL
);
2928 cpu_sub_arch_name
= xstrdup (string
);
2929 cpu_arch_flags
= flags
;
2930 cpu_arch_isa_flags
= flags
;
2932 (void) restore_line_pointer (e
);
2933 demand_empty_rest_of_line ();
2937 j
= ARRAY_SIZE (cpu_arch
);
2940 if (j
>= ARRAY_SIZE (cpu_arch
))
2941 as_bad (_("no such architecture: `%s'"), string
);
2943 *input_line_pointer
= e
;
2946 as_bad (_("missing cpu architecture"));
2948 no_cond_jump_promotion
= 0;
2949 if (*input_line_pointer
== ','
2950 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2955 ++input_line_pointer
;
2956 e
= get_symbol_name (&string
);
2958 if (strcmp (string
, "nojumps") == 0)
2959 no_cond_jump_promotion
= 1;
2960 else if (strcmp (string
, "jumps") == 0)
2963 as_bad (_("no such architecture modifier: `%s'"), string
);
2965 (void) restore_line_pointer (e
);
2968 demand_empty_rest_of_line ();
2971 enum bfd_architecture
2974 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2976 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2977 || flag_code
!= CODE_64BIT
)
2978 as_fatal (_("Intel L1OM is 64bit ELF only"));
2979 return bfd_arch_l1om
;
2981 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2983 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2984 || flag_code
!= CODE_64BIT
)
2985 as_fatal (_("Intel K1OM is 64bit ELF only"));
2986 return bfd_arch_k1om
;
2988 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2990 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2991 || flag_code
== CODE_64BIT
)
2992 as_fatal (_("Intel MCU is 32bit ELF only"));
2993 return bfd_arch_iamcu
;
2996 return bfd_arch_i386
;
3002 if (startswith (default_arch
, "x86_64"))
3004 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3006 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3007 || default_arch
[6] != '\0')
3008 as_fatal (_("Intel L1OM is 64bit ELF only"));
3009 return bfd_mach_l1om
;
3011 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3013 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3014 || default_arch
[6] != '\0')
3015 as_fatal (_("Intel K1OM is 64bit ELF only"));
3016 return bfd_mach_k1om
;
3018 else if (default_arch
[6] == '\0')
3019 return bfd_mach_x86_64
;
3021 return bfd_mach_x64_32
;
3023 else if (!strcmp (default_arch
, "i386")
3024 || !strcmp (default_arch
, "iamcu"))
3026 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3028 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3029 as_fatal (_("Intel MCU is 32bit ELF only"));
3030 return bfd_mach_i386_iamcu
;
3033 return bfd_mach_i386_i386
;
3036 as_fatal (_("unknown architecture"));
3042 /* Support pseudo prefixes like {disp32}. */
3043 lex_type
['{'] = LEX_BEGIN_NAME
;
3045 /* Initialize op_hash hash table. */
3046 op_hash
= str_htab_create ();
3049 const insn_template
*optab
;
3050 templates
*core_optab
;
3052 /* Setup for loop. */
3054 core_optab
= XNEW (templates
);
3055 core_optab
->start
= optab
;
3060 if (optab
->name
== NULL
3061 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3063 /* different name --> ship out current template list;
3064 add to hash table; & begin anew. */
3065 core_optab
->end
= optab
;
3066 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3067 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3069 if (optab
->name
== NULL
)
3071 core_optab
= XNEW (templates
);
3072 core_optab
->start
= optab
;
3077 /* Initialize reg_hash hash table. */
3078 reg_hash
= str_htab_create ();
3080 const reg_entry
*regtab
;
3081 unsigned int regtab_size
= i386_regtab_size
;
3083 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3085 switch (regtab
->reg_type
.bitfield
.class)
3088 if (regtab
->reg_type
.bitfield
.dword
)
3090 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3093 else if (regtab
->reg_type
.bitfield
.tbyte
)
3095 /* There's no point inserting st(<N>) in the hash table, as
3096 parentheses aren't included in register_chars[] anyway. */
3097 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3104 switch (regtab
->reg_num
)
3106 case 0: reg_es
= regtab
; break;
3107 case 2: reg_ss
= regtab
; break;
3108 case 3: reg_ds
= regtab
; break;
3113 if (!regtab
->reg_num
)
3118 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3119 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3123 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3128 for (c
= 0; c
< 256; c
++)
3133 mnemonic_chars
[c
] = c
;
3134 register_chars
[c
] = c
;
3135 operand_chars
[c
] = c
;
3137 else if (ISLOWER (c
))
3139 mnemonic_chars
[c
] = c
;
3140 register_chars
[c
] = c
;
3141 operand_chars
[c
] = c
;
3143 else if (ISUPPER (c
))
3145 mnemonic_chars
[c
] = TOLOWER (c
);
3146 register_chars
[c
] = mnemonic_chars
[c
];
3147 operand_chars
[c
] = c
;
3149 else if (c
== '{' || c
== '}')
3151 mnemonic_chars
[c
] = c
;
3152 operand_chars
[c
] = c
;
3154 #ifdef SVR4_COMMENT_CHARS
3155 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3156 operand_chars
[c
] = c
;
3159 if (ISALPHA (c
) || ISDIGIT (c
))
3160 identifier_chars
[c
] = c
;
3163 identifier_chars
[c
] = c
;
3164 operand_chars
[c
] = c
;
3169 identifier_chars
['@'] = '@';
3172 identifier_chars
['?'] = '?';
3173 operand_chars
['?'] = '?';
3175 digit_chars
['-'] = '-';
3176 mnemonic_chars
['_'] = '_';
3177 mnemonic_chars
['-'] = '-';
3178 mnemonic_chars
['.'] = '.';
3179 identifier_chars
['_'] = '_';
3180 identifier_chars
['.'] = '.';
3182 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3183 operand_chars
[(unsigned char) *p
] = *p
;
3186 if (flag_code
== CODE_64BIT
)
3188 #if defined (OBJ_COFF) && defined (TE_PE)
3189 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3192 x86_dwarf2_return_column
= 16;
3194 x86_cie_data_alignment
= -8;
3198 x86_dwarf2_return_column
= 8;
3199 x86_cie_data_alignment
= -4;
3202 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3203 can be turned into BRANCH_PREFIX frag. */
3204 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3209 i386_print_statistics (FILE *file
)
3211 htab_print_statistics (file
, "i386 opcode", op_hash
);
3212 htab_print_statistics (file
, "i386 register", reg_hash
);
3217 /* Debugging routines for md_assemble. */
3218 static void pte (insn_template
*);
3219 static void pt (i386_operand_type
);
3220 static void pe (expressionS
*);
3221 static void ps (symbolS
*);
3224 pi (const char *line
, i386_insn
*x
)
3228 fprintf (stdout
, "%s: template ", line
);
3230 fprintf (stdout
, " address: base %s index %s scale %x\n",
3231 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3232 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3233 x
->log2_scale_factor
);
3234 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3235 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3236 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3237 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3238 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3239 (x
->rex
& REX_W
) != 0,
3240 (x
->rex
& REX_R
) != 0,
3241 (x
->rex
& REX_X
) != 0,
3242 (x
->rex
& REX_B
) != 0);
3243 for (j
= 0; j
< x
->operands
; j
++)
3245 fprintf (stdout
, " #%d: ", j
+ 1);
3247 fprintf (stdout
, "\n");
3248 if (x
->types
[j
].bitfield
.class == Reg
3249 || x
->types
[j
].bitfield
.class == RegMMX
3250 || x
->types
[j
].bitfield
.class == RegSIMD
3251 || x
->types
[j
].bitfield
.class == RegMask
3252 || x
->types
[j
].bitfield
.class == SReg
3253 || x
->types
[j
].bitfield
.class == RegCR
3254 || x
->types
[j
].bitfield
.class == RegDR
3255 || x
->types
[j
].bitfield
.class == RegTR
3256 || x
->types
[j
].bitfield
.class == RegBND
)
3257 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3258 if (operand_type_check (x
->types
[j
], imm
))
3260 if (operand_type_check (x
->types
[j
], disp
))
3261 pe (x
->op
[j
].disps
);
3266 pte (insn_template
*t
)
3268 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3269 static const char *const opc_spc
[] = {
3270 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3271 "XOP08", "XOP09", "XOP0A",
3275 fprintf (stdout
, " %d operands ", t
->operands
);
3276 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3277 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3278 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3279 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3280 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3281 if (t
->extension_opcode
!= None
)
3282 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3283 if (t
->opcode_modifier
.d
)
3284 fprintf (stdout
, "D");
3285 if (t
->opcode_modifier
.w
)
3286 fprintf (stdout
, "W");
3287 fprintf (stdout
, "\n");
3288 for (j
= 0; j
< t
->operands
; j
++)
3290 fprintf (stdout
, " #%d type ", j
+ 1);
3291 pt (t
->operand_types
[j
]);
3292 fprintf (stdout
, "\n");
3299 fprintf (stdout
, " operation %d\n", e
->X_op
);
3300 fprintf (stdout
, " add_number %" BFD_VMA_FMT
"d (%" BFD_VMA_FMT
"x)\n",
3301 e
->X_add_number
, e
->X_add_number
);
3302 if (e
->X_add_symbol
)
3304 fprintf (stdout
, " add_symbol ");
3305 ps (e
->X_add_symbol
);
3306 fprintf (stdout
, "\n");
3310 fprintf (stdout
, " op_symbol ");
3311 ps (e
->X_op_symbol
);
3312 fprintf (stdout
, "\n");
3319 fprintf (stdout
, "%s type %s%s",
3321 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3322 segment_name (S_GET_SEGMENT (s
)));
3325 static struct type_name
3327 i386_operand_type mask
;
3330 const type_names
[] =
3332 { OPERAND_TYPE_REG8
, "r8" },
3333 { OPERAND_TYPE_REG16
, "r16" },
3334 { OPERAND_TYPE_REG32
, "r32" },
3335 { OPERAND_TYPE_REG64
, "r64" },
3336 { OPERAND_TYPE_ACC8
, "acc8" },
3337 { OPERAND_TYPE_ACC16
, "acc16" },
3338 { OPERAND_TYPE_ACC32
, "acc32" },
3339 { OPERAND_TYPE_ACC64
, "acc64" },
3340 { OPERAND_TYPE_IMM8
, "i8" },
3341 { OPERAND_TYPE_IMM8
, "i8s" },
3342 { OPERAND_TYPE_IMM16
, "i16" },
3343 { OPERAND_TYPE_IMM32
, "i32" },
3344 { OPERAND_TYPE_IMM32S
, "i32s" },
3345 { OPERAND_TYPE_IMM64
, "i64" },
3346 { OPERAND_TYPE_IMM1
, "i1" },
3347 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3348 { OPERAND_TYPE_DISP8
, "d8" },
3349 { OPERAND_TYPE_DISP16
, "d16" },
3350 { OPERAND_TYPE_DISP32
, "d32" },
3351 { OPERAND_TYPE_DISP32S
, "d32s" },
3352 { OPERAND_TYPE_DISP64
, "d64" },
3353 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3354 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3355 { OPERAND_TYPE_CONTROL
, "control reg" },
3356 { OPERAND_TYPE_TEST
, "test reg" },
3357 { OPERAND_TYPE_DEBUG
, "debug reg" },
3358 { OPERAND_TYPE_FLOATREG
, "FReg" },
3359 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3360 { OPERAND_TYPE_SREG
, "SReg" },
3361 { OPERAND_TYPE_REGMMX
, "rMMX" },
3362 { OPERAND_TYPE_REGXMM
, "rXMM" },
3363 { OPERAND_TYPE_REGYMM
, "rYMM" },
3364 { OPERAND_TYPE_REGZMM
, "rZMM" },
3365 { OPERAND_TYPE_REGTMM
, "rTMM" },
3366 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3370 pt (i386_operand_type t
)
3373 i386_operand_type a
;
3375 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3377 a
= operand_type_and (t
, type_names
[j
].mask
);
3378 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3379 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3384 #endif /* DEBUG386 */
3386 static bfd_reloc_code_real_type
3387 reloc (unsigned int size
,
3390 bfd_reloc_code_real_type other
)
3392 if (other
!= NO_RELOC
)
3394 reloc_howto_type
*rel
;
3399 case BFD_RELOC_X86_64_GOT32
:
3400 return BFD_RELOC_X86_64_GOT64
;
3402 case BFD_RELOC_X86_64_GOTPLT64
:
3403 return BFD_RELOC_X86_64_GOTPLT64
;
3405 case BFD_RELOC_X86_64_PLTOFF64
:
3406 return BFD_RELOC_X86_64_PLTOFF64
;
3408 case BFD_RELOC_X86_64_GOTPC32
:
3409 other
= BFD_RELOC_X86_64_GOTPC64
;
3411 case BFD_RELOC_X86_64_GOTPCREL
:
3412 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3414 case BFD_RELOC_X86_64_TPOFF32
:
3415 other
= BFD_RELOC_X86_64_TPOFF64
;
3417 case BFD_RELOC_X86_64_DTPOFF32
:
3418 other
= BFD_RELOC_X86_64_DTPOFF64
;
3424 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3425 if (other
== BFD_RELOC_SIZE32
)
3428 other
= BFD_RELOC_SIZE64
;
3431 as_bad (_("there are no pc-relative size relocations"));
3437 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3438 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3441 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3443 as_bad (_("unknown relocation (%u)"), other
);
3444 else if (size
!= bfd_get_reloc_size (rel
))
3445 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3446 bfd_get_reloc_size (rel
),
3448 else if (pcrel
&& !rel
->pc_relative
)
3449 as_bad (_("non-pc-relative relocation for pc-relative field"));
3450 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3452 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3454 as_bad (_("relocated field and relocation type differ in signedness"));
3463 as_bad (_("there are no unsigned pc-relative relocations"));
3466 case 1: return BFD_RELOC_8_PCREL
;
3467 case 2: return BFD_RELOC_16_PCREL
;
3468 case 4: return BFD_RELOC_32_PCREL
;
3469 case 8: return BFD_RELOC_64_PCREL
;
3471 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3478 case 4: return BFD_RELOC_X86_64_32S
;
3483 case 1: return BFD_RELOC_8
;
3484 case 2: return BFD_RELOC_16
;
3485 case 4: return BFD_RELOC_32
;
3486 case 8: return BFD_RELOC_64
;
3488 as_bad (_("cannot do %s %u byte relocation"),
3489 sign
> 0 ? "signed" : "unsigned", size
);
3495 /* Here we decide which fixups can be adjusted to make them relative to
3496 the beginning of the section instead of the symbol. Basically we need
3497 to make sure that the dynamic relocations are done correctly, so in
3498 some cases we force the original symbol to be used. */
3501 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3507 /* Don't adjust pc-relative references to merge sections in 64-bit
3509 if (use_rela_relocations
3510 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3514 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3515 and changed later by validate_fix. */
3516 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3517 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3520 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3521 for size relocations. */
3522 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3523 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3524 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3525 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3526 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3527 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3528 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3529 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3530 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3531 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3532 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3533 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3534 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3535 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3536 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3537 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3538 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3539 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3540 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3541 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3542 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3543 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3544 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3545 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3546 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3547 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3548 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3549 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3550 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3551 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3552 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3559 want_disp32 (const insn_template
*t
)
3561 return flag_code
!= CODE_64BIT
3562 || i
.prefix
[ADDR_PREFIX
]
3563 || (t
->base_opcode
== 0x8d
3564 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
3565 && (!i
.types
[1].bitfield
.qword
3566 || t
->opcode_modifier
.size
== SIZE32
));
3570 intel_float_operand (const char *mnemonic
)
3572 /* Note that the value returned is meaningful only for opcodes with (memory)
3573 operands, hence the code here is free to improperly handle opcodes that
3574 have no operands (for better performance and smaller code). */
3576 if (mnemonic
[0] != 'f')
3577 return 0; /* non-math */
3579 switch (mnemonic
[1])
3581 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3582 the fs segment override prefix not currently handled because no
3583 call path can make opcodes without operands get here */
3585 return 2 /* integer op */;
3587 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3588 return 3; /* fldcw/fldenv */
3591 if (mnemonic
[2] != 'o' /* fnop */)
3592 return 3; /* non-waiting control op */
3595 if (mnemonic
[2] == 's')
3596 return 3; /* frstor/frstpm */
3599 if (mnemonic
[2] == 'a')
3600 return 3; /* fsave */
3601 if (mnemonic
[2] == 't')
3603 switch (mnemonic
[3])
3605 case 'c': /* fstcw */
3606 case 'd': /* fstdw */
3607 case 'e': /* fstenv */
3608 case 's': /* fsts[gw] */
3614 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3615 return 0; /* fxsave/fxrstor are not really math ops */
3623 install_template (const insn_template
*t
)
3629 /* Note that for pseudo prefixes this produces a length of 1. But for them
3630 the length isn't interesting at all. */
3631 for (l
= 1; l
< 4; ++l
)
3632 if (!(t
->base_opcode
>> (8 * l
)))
3635 i
.opcode_length
= l
;
3638 /* Build the VEX prefix. */
3641 build_vex_prefix (const insn_template
*t
)
3643 unsigned int register_specifier
;
3644 unsigned int vector_length
;
3647 /* Check register specifier. */
3648 if (i
.vex
.register_specifier
)
3650 register_specifier
=
3651 ~register_number (i
.vex
.register_specifier
) & 0xf;
3652 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3655 register_specifier
= 0xf;
3657 /* Use 2-byte VEX prefix by swapping destination and source operand
3658 if there are more than 1 register operand. */
3659 if (i
.reg_operands
> 1
3660 && i
.vec_encoding
!= vex_encoding_vex3
3661 && i
.dir_encoding
== dir_encoding_default
3662 && i
.operands
== i
.reg_operands
3663 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3664 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3665 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3668 unsigned int xchg
= i
.operands
- 1;
3669 union i386_op temp_op
;
3670 i386_operand_type temp_type
;
3672 temp_type
= i
.types
[xchg
];
3673 i
.types
[xchg
] = i
.types
[0];
3674 i
.types
[0] = temp_type
;
3675 temp_op
= i
.op
[xchg
];
3676 i
.op
[xchg
] = i
.op
[0];
3679 gas_assert (i
.rm
.mode
== 3);
3683 i
.rm
.regmem
= i
.rm
.reg
;
3686 if (i
.tm
.opcode_modifier
.d
)
3687 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3688 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3689 else /* Use the next insn. */
3690 install_template (&t
[1]);
3693 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3694 are no memory operands and at least 3 register ones. */
3695 if (i
.reg_operands
>= 3
3696 && i
.vec_encoding
!= vex_encoding_vex3
3697 && i
.reg_operands
== i
.operands
- i
.imm_operands
3698 && i
.tm
.opcode_modifier
.vex
3699 && i
.tm
.opcode_modifier
.commutative
3700 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3702 && i
.vex
.register_specifier
3703 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3705 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3706 union i386_op temp_op
;
3707 i386_operand_type temp_type
;
3709 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3710 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3711 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3712 &i
.types
[i
.operands
- 3]));
3713 gas_assert (i
.rm
.mode
== 3);
3715 temp_type
= i
.types
[xchg
];
3716 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3717 i
.types
[xchg
+ 1] = temp_type
;
3718 temp_op
= i
.op
[xchg
];
3719 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3720 i
.op
[xchg
+ 1] = temp_op
;
3723 xchg
= i
.rm
.regmem
| 8;
3724 i
.rm
.regmem
= ~register_specifier
& 0xf;
3725 gas_assert (!(i
.rm
.regmem
& 8));
3726 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3727 register_specifier
= ~xchg
& 0xf;
3730 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3731 vector_length
= avxscalar
;
3732 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3738 /* Determine vector length from the last multi-length vector
3741 for (op
= t
->operands
; op
--;)
3742 if (t
->operand_types
[op
].bitfield
.xmmword
3743 && t
->operand_types
[op
].bitfield
.ymmword
3744 && i
.types
[op
].bitfield
.ymmword
)
3751 /* Check the REX.W bit and VEXW. */
3752 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3753 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3754 else if (i
.tm
.opcode_modifier
.vexw
)
3755 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3757 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3759 /* Use 2-byte VEX prefix if possible. */
3761 && i
.vec_encoding
!= vex_encoding_vex3
3762 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3763 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3765 /* 2-byte VEX prefix. */
3769 i
.vex
.bytes
[0] = 0xc5;
3771 /* Check the REX.R bit. */
3772 r
= (i
.rex
& REX_R
) ? 0 : 1;
3773 i
.vex
.bytes
[1] = (r
<< 7
3774 | register_specifier
<< 3
3775 | vector_length
<< 2
3776 | i
.tm
.opcode_modifier
.opcodeprefix
);
3780 /* 3-byte VEX prefix. */
3783 switch (i
.tm
.opcode_modifier
.opcodespace
)
3788 i
.vex
.bytes
[0] = 0xc4;
3793 i
.vex
.bytes
[0] = 0x8f;
3799 /* The high 3 bits of the second VEX byte are 1's compliment
3800 of RXB bits from REX. */
3801 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3803 i
.vex
.bytes
[2] = (w
<< 7
3804 | register_specifier
<< 3
3805 | vector_length
<< 2
3806 | i
.tm
.opcode_modifier
.opcodeprefix
);
3811 is_evex_encoding (const insn_template
*t
)
3813 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3814 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3815 || t
->opcode_modifier
.sae
;
3819 is_any_vex_encoding (const insn_template
*t
)
3821 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3824 /* Build the EVEX prefix. */
3827 build_evex_prefix (void)
3829 unsigned int register_specifier
, w
;
3830 rex_byte vrex_used
= 0;
3832 /* Check register specifier. */
3833 if (i
.vex
.register_specifier
)
3835 gas_assert ((i
.vrex
& REX_X
) == 0);
3837 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3838 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3839 register_specifier
+= 8;
3840 /* The upper 16 registers are encoded in the fourth byte of the
3842 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3843 i
.vex
.bytes
[3] = 0x8;
3844 register_specifier
= ~register_specifier
& 0xf;
3848 register_specifier
= 0xf;
3850 /* Encode upper 16 vector index register in the fourth byte of
3852 if (!(i
.vrex
& REX_X
))
3853 i
.vex
.bytes
[3] = 0x8;
3858 /* 4 byte EVEX prefix. */
3860 i
.vex
.bytes
[0] = 0x62;
3862 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3864 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3865 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3866 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3868 /* The fifth bit of the second EVEX byte is 1's compliment of the
3869 REX_R bit in VREX. */
3870 if (!(i
.vrex
& REX_R
))
3871 i
.vex
.bytes
[1] |= 0x10;
3875 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3877 /* When all operands are registers, the REX_X bit in REX is not
3878 used. We reuse it to encode the upper 16 registers, which is
3879 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3880 as 1's compliment. */
3881 if ((i
.vrex
& REX_B
))
3884 i
.vex
.bytes
[1] &= ~0x40;
3888 /* EVEX instructions shouldn't need the REX prefix. */
3889 i
.vrex
&= ~vrex_used
;
3890 gas_assert (i
.vrex
== 0);
3892 /* Check the REX.W bit and VEXW. */
3893 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3894 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3895 else if (i
.tm
.opcode_modifier
.vexw
)
3896 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3898 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3900 /* The third byte of the EVEX prefix. */
3901 i
.vex
.bytes
[2] = ((w
<< 7)
3902 | (register_specifier
<< 3)
3903 | 4 /* Encode the U bit. */
3904 | i
.tm
.opcode_modifier
.opcodeprefix
);
3906 /* The fourth byte of the EVEX prefix. */
3907 /* The zeroing-masking bit. */
3908 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3909 i
.vex
.bytes
[3] |= 0x80;
3911 /* Don't always set the broadcast bit if there is no RC. */
3912 if (i
.rounding
.type
== rc_none
)
3914 /* Encode the vector length. */
3915 unsigned int vec_length
;
3917 if (!i
.tm
.opcode_modifier
.evex
3918 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3922 /* Determine vector length from the last multi-length vector
3924 for (op
= i
.operands
; op
--;)
3925 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3926 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3927 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3929 if (i
.types
[op
].bitfield
.zmmword
)
3931 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3934 else if (i
.types
[op
].bitfield
.ymmword
)
3936 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3939 else if (i
.types
[op
].bitfield
.xmmword
)
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3944 else if (i
.broadcast
.type
&& op
== i
.broadcast
.operand
)
3946 switch (i
.broadcast
.bytes
)
3949 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3952 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3955 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3964 if (op
>= MAX_OPERANDS
)
3968 switch (i
.tm
.opcode_modifier
.evex
)
3970 case EVEXLIG
: /* LL' is ignored */
3971 vec_length
= evexlig
<< 5;
3974 vec_length
= 0 << 5;
3977 vec_length
= 1 << 5;
3980 vec_length
= 2 << 5;
3986 i
.vex
.bytes
[3] |= vec_length
;
3987 /* Encode the broadcast bit. */
3988 if (i
.broadcast
.type
)
3989 i
.vex
.bytes
[3] |= 0x10;
3991 else if (i
.rounding
.type
!= saeonly
)
3992 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3994 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3997 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4001 process_immext (void)
4005 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4006 which is coded in the same place as an 8-bit immediate field
4007 would be. Here we fake an 8-bit immediate operand from the
4008 opcode suffix stored in tm.extension_opcode.
4010 AVX instructions also use this encoding, for some of
4011 3 argument instructions. */
4013 gas_assert (i
.imm_operands
<= 1
4015 || (is_any_vex_encoding (&i
.tm
)
4016 && i
.operands
<= 4)));
4018 exp
= &im_expressions
[i
.imm_operands
++];
4019 i
.op
[i
.operands
].imms
= exp
;
4020 i
.types
[i
.operands
] = imm8
;
4022 exp
->X_op
= O_constant
;
4023 exp
->X_add_number
= i
.tm
.extension_opcode
;
4024 i
.tm
.extension_opcode
= None
;
4031 switch (i
.tm
.opcode_modifier
.prefixok
)
4039 as_bad (_("invalid instruction `%s' after `%s'"),
4040 i
.tm
.name
, i
.hle_prefix
);
4043 if (i
.prefix
[LOCK_PREFIX
])
4045 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4049 case PrefixHLERelease
:
4050 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4052 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4056 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4058 as_bad (_("memory destination needed for instruction `%s'"
4059 " after `xrelease'"), i
.tm
.name
);
4066 /* Try the shortest encoding by shortening operand size. */
4069 optimize_encoding (void)
4073 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4074 && i
.tm
.base_opcode
== 0x8d)
4077 lea symbol, %rN -> mov $symbol, %rN
4078 lea (%rM), %rN -> mov %rM, %rN
4079 lea (,%rM,1), %rN -> mov %rM, %rN
4081 and in 32-bit mode for 16-bit addressing
4083 lea (%rM), %rN -> movzx %rM, %rN
4085 and in 64-bit mode zap 32-bit addressing in favor of using a
4086 32-bit (or less) destination.
4088 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4090 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4091 i
.tm
.opcode_modifier
.size
= SIZE32
;
4092 i
.prefix
[ADDR_PREFIX
] = 0;
4095 if (!i
.index_reg
&& !i
.base_reg
)
4098 lea symbol, %rN -> mov $symbol, %rN
4100 if (flag_code
== CODE_64BIT
)
4102 /* Don't transform a relocation to a 16-bit one. */
4104 && i
.op
[0].disps
->X_op
!= O_constant
4105 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4108 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4109 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4111 i
.tm
.base_opcode
= 0xb8;
4112 i
.tm
.opcode_modifier
.modrm
= 0;
4113 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4114 i
.types
[0].bitfield
.imm32
= 1;
4117 i
.tm
.opcode_modifier
.size
= SIZE16
;
4118 i
.types
[0].bitfield
.imm16
= 1;
4123 /* Subject to further optimization below. */
4124 i
.tm
.base_opcode
= 0xc7;
4125 i
.tm
.extension_opcode
= 0;
4126 i
.types
[0].bitfield
.imm32s
= 1;
4127 i
.types
[0].bitfield
.baseindex
= 0;
4130 /* Outside of 64-bit mode address and operand sizes have to match if
4131 a relocation is involved, as otherwise we wouldn't (currently) or
4132 even couldn't express the relocation correctly. */
4133 else if (i
.op
[0].disps
4134 && i
.op
[0].disps
->X_op
!= O_constant
4135 && ((!i
.prefix
[ADDR_PREFIX
])
4136 != (flag_code
== CODE_32BIT
4137 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4138 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4142 i
.tm
.base_opcode
= 0xb8;
4143 i
.tm
.opcode_modifier
.modrm
= 0;
4144 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4145 i
.types
[0].bitfield
.imm32
= 1;
4147 i
.types
[0].bitfield
.imm16
= 1;
4150 && i
.op
[0].disps
->X_op
== O_constant
4151 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4152 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4154 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4155 i
.op
[0].disps
->X_add_number
&= 0xffff;
4158 i
.tm
.operand_types
[0] = i
.types
[0];
4162 i
.op
[0].imms
= &im_expressions
[0];
4163 i
.op
[0].imms
->X_op
= O_absent
;
4166 else if (i
.op
[0].disps
4167 && (i
.op
[0].disps
->X_op
!= O_constant
4168 || i
.op
[0].disps
->X_add_number
))
4173 lea (%rM), %rN -> mov %rM, %rN
4174 lea (,%rM,1), %rN -> mov %rM, %rN
4175 lea (%rM), %rN -> movzx %rM, %rN
4177 const reg_entry
*addr_reg
;
4179 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4180 addr_reg
= i
.base_reg
;
4181 else if (!i
.base_reg
4182 && i
.index_reg
->reg_num
!= RegIZ
4183 && !i
.log2_scale_factor
)
4184 addr_reg
= i
.index_reg
;
4188 if (addr_reg
->reg_type
.bitfield
.word
4189 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4191 if (flag_code
!= CODE_32BIT
)
4193 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4194 i
.tm
.base_opcode
= 0xb7;
4197 i
.tm
.base_opcode
= 0x8b;
4199 if (addr_reg
->reg_type
.bitfield
.dword
4200 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4201 i
.tm
.opcode_modifier
.size
= SIZE32
;
4203 i
.op
[0].regs
= addr_reg
;
4208 i
.disp_operands
= 0;
4209 i
.prefix
[ADDR_PREFIX
] = 0;
4210 i
.prefix
[SEG_PREFIX
] = 0;
4214 if (optimize_for_space
4215 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4216 && i
.reg_operands
== 1
4217 && i
.imm_operands
== 1
4218 && !i
.types
[1].bitfield
.byte
4219 && i
.op
[0].imms
->X_op
== O_constant
4220 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4221 && (i
.tm
.base_opcode
== 0xa8
4222 || (i
.tm
.base_opcode
== 0xf6
4223 && i
.tm
.extension_opcode
== 0x0)))
4226 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4228 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4229 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4231 i
.types
[1].bitfield
.byte
= 1;
4232 /* Ignore the suffix. */
4234 /* Convert to byte registers. */
4235 if (i
.types
[1].bitfield
.word
)
4237 else if (i
.types
[1].bitfield
.dword
)
4241 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4246 else if (flag_code
== CODE_64BIT
4247 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4248 && ((i
.types
[1].bitfield
.qword
4249 && i
.reg_operands
== 1
4250 && i
.imm_operands
== 1
4251 && i
.op
[0].imms
->X_op
== O_constant
4252 && ((i
.tm
.base_opcode
== 0xb8
4253 && i
.tm
.extension_opcode
== None
4254 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4255 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4256 && ((i
.tm
.base_opcode
== 0x24
4257 || i
.tm
.base_opcode
== 0xa8)
4258 || (i
.tm
.base_opcode
== 0x80
4259 && i
.tm
.extension_opcode
== 0x4)
4260 || ((i
.tm
.base_opcode
== 0xf6
4261 || (i
.tm
.base_opcode
| 1) == 0xc7)
4262 && i
.tm
.extension_opcode
== 0x0)))
4263 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4264 && i
.tm
.base_opcode
== 0x83
4265 && i
.tm
.extension_opcode
== 0x4)))
4266 || (i
.types
[0].bitfield
.qword
4267 && ((i
.reg_operands
== 2
4268 && i
.op
[0].regs
== i
.op
[1].regs
4269 && (i
.tm
.base_opcode
== 0x30
4270 || i
.tm
.base_opcode
== 0x28))
4271 || (i
.reg_operands
== 1
4273 && i
.tm
.base_opcode
== 0x30)))))
4276 andq $imm31, %r64 -> andl $imm31, %r32
4277 andq $imm7, %r64 -> andl $imm7, %r32
4278 testq $imm31, %r64 -> testl $imm31, %r32
4279 xorq %r64, %r64 -> xorl %r32, %r32
4280 subq %r64, %r64 -> subl %r32, %r32
4281 movq $imm31, %r64 -> movl $imm31, %r32
4282 movq $imm32, %r64 -> movl $imm32, %r32
4284 i
.tm
.opcode_modifier
.norex64
= 1;
4285 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4288 movq $imm31, %r64 -> movl $imm31, %r32
4289 movq $imm32, %r64 -> movl $imm32, %r32
4291 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4292 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4293 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4294 i
.types
[0].bitfield
.imm32
= 1;
4295 i
.types
[0].bitfield
.imm32s
= 0;
4296 i
.types
[0].bitfield
.imm64
= 0;
4297 i
.types
[1].bitfield
.dword
= 1;
4298 i
.types
[1].bitfield
.qword
= 0;
4299 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4302 movq $imm31, %r64 -> movl $imm31, %r32
4304 i
.tm
.base_opcode
= 0xb8;
4305 i
.tm
.extension_opcode
= None
;
4306 i
.tm
.opcode_modifier
.w
= 0;
4307 i
.tm
.opcode_modifier
.modrm
= 0;
4311 else if (optimize
> 1
4312 && !optimize_for_space
4313 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4314 && i
.reg_operands
== 2
4315 && i
.op
[0].regs
== i
.op
[1].regs
4316 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4317 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4318 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4321 andb %rN, %rN -> testb %rN, %rN
4322 andw %rN, %rN -> testw %rN, %rN
4323 andq %rN, %rN -> testq %rN, %rN
4324 orb %rN, %rN -> testb %rN, %rN
4325 orw %rN, %rN -> testw %rN, %rN
4326 orq %rN, %rN -> testq %rN, %rN
4328 and outside of 64-bit mode
4330 andl %rN, %rN -> testl %rN, %rN
4331 orl %rN, %rN -> testl %rN, %rN
4333 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4335 else if (i
.reg_operands
== 3
4336 && i
.op
[0].regs
== i
.op
[1].regs
4337 && !i
.types
[2].bitfield
.xmmword
4338 && (i
.tm
.opcode_modifier
.vex
4339 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4340 && i
.rounding
.type
== rc_none
4341 && is_evex_encoding (&i
.tm
)
4342 && (i
.vec_encoding
!= vex_encoding_evex
4343 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4344 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4345 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4346 && i
.types
[2].bitfield
.ymmword
))))
4347 && ((i
.tm
.base_opcode
== 0x55
4348 || i
.tm
.base_opcode
== 0x57
4349 || i
.tm
.base_opcode
== 0xdf
4350 || i
.tm
.base_opcode
== 0xef
4351 || i
.tm
.base_opcode
== 0xf8
4352 || i
.tm
.base_opcode
== 0xf9
4353 || i
.tm
.base_opcode
== 0xfa
4354 || i
.tm
.base_opcode
== 0xfb
4355 || i
.tm
.base_opcode
== 0x42
4356 || i
.tm
.base_opcode
== 0x47)
4357 && i
.tm
.extension_opcode
== None
))
4360 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4362 EVEX VOP %zmmM, %zmmM, %zmmN
4363 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4364 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4365 EVEX VOP %ymmM, %ymmM, %ymmN
4366 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4367 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4368 VEX VOP %ymmM, %ymmM, %ymmN
4369 -> VEX VOP %xmmM, %xmmM, %xmmN
4370 VOP, one of vpandn and vpxor:
4371 VEX VOP %ymmM, %ymmM, %ymmN
4372 -> VEX VOP %xmmM, %xmmM, %xmmN
4373 VOP, one of vpandnd and vpandnq:
4374 EVEX VOP %zmmM, %zmmM, %zmmN
4375 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4376 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4377 EVEX VOP %ymmM, %ymmM, %ymmN
4378 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4379 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4380 VOP, one of vpxord and vpxorq:
4381 EVEX VOP %zmmM, %zmmM, %zmmN
4382 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4383 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4384 EVEX VOP %ymmM, %ymmM, %ymmN
4385 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4386 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4387 VOP, one of kxord and kxorq:
4388 VEX VOP %kM, %kM, %kN
4389 -> VEX kxorw %kM, %kM, %kN
4390 VOP, one of kandnd and kandnq:
4391 VEX VOP %kM, %kM, %kN
4392 -> VEX kandnw %kM, %kM, %kN
4394 if (is_evex_encoding (&i
.tm
))
4396 if (i
.vec_encoding
!= vex_encoding_evex
)
4398 i
.tm
.opcode_modifier
.vex
= VEX128
;
4399 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4400 i
.tm
.opcode_modifier
.evex
= 0;
4402 else if (optimize
> 1)
4403 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4407 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4409 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4410 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4413 i
.tm
.opcode_modifier
.vex
= VEX128
;
4415 if (i
.tm
.opcode_modifier
.vex
)
4416 for (j
= 0; j
< 3; j
++)
4418 i
.types
[j
].bitfield
.xmmword
= 1;
4419 i
.types
[j
].bitfield
.ymmword
= 0;
4422 else if (i
.vec_encoding
!= vex_encoding_evex
4423 && !i
.types
[0].bitfield
.zmmword
4424 && !i
.types
[1].bitfield
.zmmword
4426 && !i
.broadcast
.type
4427 && is_evex_encoding (&i
.tm
)
4428 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4429 || (i
.tm
.base_opcode
& ~4) == 0xdb
4430 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4431 && i
.tm
.extension_opcode
== None
)
4434 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4435 vmovdqu32 and vmovdqu64:
4436 EVEX VOP %xmmM, %xmmN
4437 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4438 EVEX VOP %ymmM, %ymmN
4439 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4441 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4443 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4445 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4447 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4448 VOP, one of vpand, vpandn, vpor, vpxor:
4449 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4450 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4451 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4452 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4453 EVEX VOP{d,q} mem, %xmmM, %xmmN
4454 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4455 EVEX VOP{d,q} mem, %ymmM, %ymmN
4456 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4458 for (j
= 0; j
< i
.operands
; j
++)
4459 if (operand_type_check (i
.types
[j
], disp
)
4460 && i
.op
[j
].disps
->X_op
== O_constant
)
4462 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4463 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4464 bytes, we choose EVEX Disp8 over VEX Disp32. */
4465 int evex_disp8
, vex_disp8
;
4466 unsigned int memshift
= i
.memshift
;
4467 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4469 evex_disp8
= fits_in_disp8 (n
);
4471 vex_disp8
= fits_in_disp8 (n
);
4472 if (evex_disp8
!= vex_disp8
)
4474 i
.memshift
= memshift
;
4478 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4481 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4482 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4483 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4484 i
.tm
.opcode_modifier
.vex
4485 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4486 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4487 /* VPAND, VPOR, and VPXOR are commutative. */
4488 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4489 i
.tm
.opcode_modifier
.commutative
= 1;
4490 i
.tm
.opcode_modifier
.evex
= 0;
4491 i
.tm
.opcode_modifier
.masking
= 0;
4492 i
.tm
.opcode_modifier
.broadcast
= 0;
4493 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4496 i
.types
[j
].bitfield
.disp8
4497 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4501 /* Return non-zero for load instruction. */
4507 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4508 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4512 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4513 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4514 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4515 if (i
.tm
.opcode_modifier
.anysize
)
4519 if (strcmp (i
.tm
.name
, "pop") == 0)
4523 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4526 if (i
.tm
.base_opcode
== 0x9d
4527 || i
.tm
.base_opcode
== 0x61)
4530 /* movs, cmps, lods, scas. */
4531 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4535 if (base_opcode
== 0x6f
4536 || i
.tm
.base_opcode
== 0xd7)
4538 /* NB: For AMD-specific insns with implicit memory operands,
4539 they're intentionally not covered. */
4542 /* No memory operand. */
4543 if (!i
.mem_operands
)
4549 if (i
.tm
.base_opcode
== 0xae
4550 && i
.tm
.opcode_modifier
.vex
4551 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4552 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4553 && i
.tm
.extension_opcode
== 2)
4556 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4558 /* test, not, neg, mul, imul, div, idiv. */
4559 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4560 && i
.tm
.extension_opcode
!= 1)
4564 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4567 /* add, or, adc, sbb, and, sub, xor, cmp. */
4568 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4571 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4572 if ((base_opcode
== 0xc1
4573 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4574 && i
.tm
.extension_opcode
!= 6)
4577 /* Check for x87 instructions. */
4578 if (base_opcode
>= 0xd8 && base_opcode
<= 0xdf)
4580 /* Skip fst, fstp, fstenv, fstcw. */
4581 if (i
.tm
.base_opcode
== 0xd9
4582 && (i
.tm
.extension_opcode
== 2
4583 || i
.tm
.extension_opcode
== 3
4584 || i
.tm
.extension_opcode
== 6
4585 || i
.tm
.extension_opcode
== 7))
4588 /* Skip fisttp, fist, fistp, fstp. */
4589 if (i
.tm
.base_opcode
== 0xdb
4590 && (i
.tm
.extension_opcode
== 1
4591 || i
.tm
.extension_opcode
== 2
4592 || i
.tm
.extension_opcode
== 3
4593 || i
.tm
.extension_opcode
== 7))
4596 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4597 if (i
.tm
.base_opcode
== 0xdd
4598 && (i
.tm
.extension_opcode
== 1
4599 || i
.tm
.extension_opcode
== 2
4600 || i
.tm
.extension_opcode
== 3
4601 || i
.tm
.extension_opcode
== 6
4602 || i
.tm
.extension_opcode
== 7))
4605 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4606 if (i
.tm
.base_opcode
== 0xdf
4607 && (i
.tm
.extension_opcode
== 1
4608 || i
.tm
.extension_opcode
== 2
4609 || i
.tm
.extension_opcode
== 3
4610 || i
.tm
.extension_opcode
== 6
4611 || i
.tm
.extension_opcode
== 7))
4617 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4619 /* bt, bts, btr, btc. */
4620 if (i
.tm
.base_opcode
== 0xba
4621 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4624 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4625 if (i
.tm
.base_opcode
== 0xc7
4626 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4627 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4628 || i
.tm
.extension_opcode
== 6))
4631 /* fxrstor, ldmxcsr, xrstor. */
4632 if (i
.tm
.base_opcode
== 0xae
4633 && (i
.tm
.extension_opcode
== 1
4634 || i
.tm
.extension_opcode
== 2
4635 || i
.tm
.extension_opcode
== 5))
4638 /* lgdt, lidt, lmsw. */
4639 if (i
.tm
.base_opcode
== 0x01
4640 && (i
.tm
.extension_opcode
== 2
4641 || i
.tm
.extension_opcode
== 3
4642 || i
.tm
.extension_opcode
== 6))
4646 dest
= i
.operands
- 1;
4648 /* Check fake imm8 operand and 3 source operands. */
4649 if ((i
.tm
.opcode_modifier
.immext
4650 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4651 && i
.types
[dest
].bitfield
.imm8
)
4654 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4655 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4656 && (base_opcode
== 0x1
4657 || base_opcode
== 0x9
4658 || base_opcode
== 0x11
4659 || base_opcode
== 0x19
4660 || base_opcode
== 0x21
4661 || base_opcode
== 0x29
4662 || base_opcode
== 0x31
4663 || base_opcode
== 0x39
4664 || (base_opcode
| 2) == 0x87))
4668 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4669 && base_opcode
== 0xc1)
4672 /* Check for load instruction. */
4673 return (i
.types
[dest
].bitfield
.class != ClassNone
4674 || i
.types
[dest
].bitfield
.instance
== Accum
);
4677 /* Output lfence, 0xfaee8, after instruction. */
4680 insert_lfence_after (void)
4682 if (lfence_after_load
&& load_insn_p ())
4684 /* There are also two REP string instructions that require
4685 special treatment. Specifically, the compare string (CMPS)
4686 and scan string (SCAS) instructions set EFLAGS in a manner
4687 that depends on the data being compared/scanned. When used
4688 with a REP prefix, the number of iterations may therefore
4689 vary depending on this data. If the data is a program secret
4690 chosen by the adversary using an LVI method,
4691 then this data-dependent behavior may leak some aspect
4693 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4694 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4695 && i
.prefix
[REP_PREFIX
])
4697 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4700 char *p
= frag_more (3);
4707 /* Output lfence, 0xfaee8, before instruction. */
4710 insert_lfence_before (void)
4714 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4717 if (i
.tm
.base_opcode
== 0xff
4718 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4720 /* Insert lfence before indirect branch if needed. */
4722 if (lfence_before_indirect_branch
== lfence_branch_none
)
4725 if (i
.operands
!= 1)
4728 if (i
.reg_operands
== 1)
4730 /* Indirect branch via register. Don't insert lfence with
4731 -mlfence-after-load=yes. */
4732 if (lfence_after_load
4733 || lfence_before_indirect_branch
== lfence_branch_memory
)
4736 else if (i
.mem_operands
== 1
4737 && lfence_before_indirect_branch
!= lfence_branch_register
)
4739 as_warn (_("indirect `%s` with memory operand should be avoided"),
4746 if (last_insn
.kind
!= last_insn_other
4747 && last_insn
.seg
== now_seg
)
4749 as_warn_where (last_insn
.file
, last_insn
.line
,
4750 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4751 last_insn
.name
, i
.tm
.name
);
4762 /* Output or/not/shl and lfence before near ret. */
4763 if (lfence_before_ret
!= lfence_before_ret_none
4764 && (i
.tm
.base_opcode
== 0xc2
4765 || i
.tm
.base_opcode
== 0xc3))
4767 if (last_insn
.kind
!= last_insn_other
4768 && last_insn
.seg
== now_seg
)
4770 as_warn_where (last_insn
.file
, last_insn
.line
,
4771 _("`%s` skips -mlfence-before-ret on `%s`"),
4772 last_insn
.name
, i
.tm
.name
);
4776 /* Near ret ingore operand size override under CPU64. */
4777 char prefix
= flag_code
== CODE_64BIT
4779 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4781 if (lfence_before_ret
== lfence_before_ret_not
)
4783 /* not: 0xf71424, may add prefix
4784 for operand size override or 64-bit code. */
4785 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4799 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4802 if (lfence_before_ret
== lfence_before_ret_or
)
4804 /* or: 0x830c2400, may add prefix
4805 for operand size override or 64-bit code. */
4811 /* shl: 0xc1242400, may add prefix
4812 for operand size override or 64-bit code. */
4827 /* This is the guts of the machine-dependent assembler. LINE points to a
4828 machine dependent instruction. This function is supposed to emit
4829 the frags/bytes it assembles to. */
4832 md_assemble (char *line
)
4835 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4836 const insn_template
*t
;
4838 /* Initialize globals. */
4839 memset (&i
, '\0', sizeof (i
));
4840 i
.rounding
.type
= rc_none
;
4841 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4842 i
.reloc
[j
] = NO_RELOC
;
4843 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4844 memset (im_expressions
, '\0', sizeof (im_expressions
));
4845 save_stack_p
= save_stack
;
4847 /* First parse an instruction mnemonic & call i386_operand for the operands.
4848 We assume that the scrubber has arranged it so that line[0] is the valid
4849 start of a (possibly prefixed) mnemonic. */
4851 line
= parse_insn (line
, mnemonic
);
4854 mnem_suffix
= i
.suffix
;
4856 line
= parse_operands (line
, mnemonic
);
4858 xfree (i
.memop1_string
);
4859 i
.memop1_string
= NULL
;
4863 /* Now we've parsed the mnemonic into a set of templates, and have the
4864 operands at hand. */
4866 /* All Intel opcodes have reversed operands except for "bound", "enter",
4867 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4868 "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
4869 and "call" instructions with 2 immediate operands so that the immediate
4870 segment precedes the offset consistently in Intel and AT&T modes. */
4873 && (strcmp (mnemonic
, "bound") != 0)
4874 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4875 && !startswith (mnemonic
, "monitor")
4876 && !startswith (mnemonic
, "mwait")
4877 && (strcmp (mnemonic
, "pvalidate") != 0)
4878 && !startswith (mnemonic
, "rmp")
4879 && (strcmp (mnemonic
, "tpause") != 0)
4880 && (strcmp (mnemonic
, "umwait") != 0)
4881 && !(operand_type_check (i
.types
[0], imm
)
4882 && operand_type_check (i
.types
[1], imm
)))
4885 /* The order of the immediates should be reversed
4886 for 2 immediates extrq and insertq instructions */
4887 if (i
.imm_operands
== 2
4888 && (strcmp (mnemonic
, "extrq") == 0
4889 || strcmp (mnemonic
, "insertq") == 0))
4890 swap_2_operands (0, 1);
4895 if (i
.disp_operands
&& !want_disp32 (current_templates
->start
))
4897 for (j
= 0; j
< i
.operands
; ++j
)
4899 const expressionS
*exp
= i
.op
[j
].disps
;
4901 if (!operand_type_check (i
.types
[j
], disp
))
4904 if (exp
->X_op
!= O_constant
)
4907 /* Since displacement is signed extended to 64bit, don't allow
4908 disp32 and turn off disp32s if they are out of range. */
4909 i
.types
[j
].bitfield
.disp32
= 0;
4910 if (fits_in_signed_long (exp
->X_add_number
))
4913 i
.types
[j
].bitfield
.disp32s
= 0;
4914 if (i
.types
[j
].bitfield
.baseindex
)
4916 as_bad (_("0x%" BFD_VMA_FMT
"x out of range of signed 32bit displacement"),
4923 /* Don't optimize displacement for movabs since it only takes 64bit
4926 && i
.disp_encoding
!= disp_encoding_32bit
4927 && (flag_code
!= CODE_64BIT
4928 || strcmp (mnemonic
, "movabs") != 0))
4931 /* Next, we find a template that matches the given insn,
4932 making sure the overlap of the given operands types is consistent
4933 with the template operand types. */
4935 if (!(t
= match_template (mnem_suffix
)))
4938 if (sse_check
!= check_none
4939 && !i
.tm
.opcode_modifier
.noavx
4940 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4941 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4942 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4943 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4944 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4945 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4946 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4947 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4948 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4949 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4950 || i
.tm
.cpu_flags
.bitfield
.cpusha
4951 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4953 (sse_check
== check_warning
4955 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4958 if (i
.tm
.opcode_modifier
.fwait
)
4959 if (!add_prefix (FWAIT_OPCODE
))
4962 /* Check if REP prefix is OK. */
4963 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4965 as_bad (_("invalid instruction `%s' after `%s'"),
4966 i
.tm
.name
, i
.rep_prefix
);
4970 /* Check for lock without a lockable instruction. Destination operand
4971 must be memory unless it is xchg (0x86). */
4972 if (i
.prefix
[LOCK_PREFIX
]
4973 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4974 || i
.mem_operands
== 0
4975 || (i
.tm
.base_opcode
!= 0x86
4976 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4978 as_bad (_("expecting lockable instruction after `lock'"));
4982 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4983 if (i
.prefix
[DATA_PREFIX
]
4984 && (is_any_vex_encoding (&i
.tm
)
4985 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4986 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4988 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4992 /* Check if HLE prefix is OK. */
4993 if (i
.hle_prefix
&& !check_hle ())
4996 /* Check BND prefix. */
4997 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4998 as_bad (_("expecting valid branch instruction after `bnd'"));
5000 /* Check NOTRACK prefix. */
5001 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5002 as_bad (_("expecting indirect branch instruction after `notrack'"));
5004 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5006 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5007 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5008 else if (flag_code
!= CODE_16BIT
5009 ? i
.prefix
[ADDR_PREFIX
]
5010 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5011 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5014 /* Insert BND prefix. */
5015 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5017 if (!i
.prefix
[BND_PREFIX
])
5018 add_prefix (BND_PREFIX_OPCODE
);
5019 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5021 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5022 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5026 /* Check string instruction segment overrides. */
5027 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5029 gas_assert (i
.mem_operands
);
5030 if (!check_string ())
5032 i
.disp_operands
= 0;
5035 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5036 optimize_encoding ();
5038 if (!process_suffix ())
5041 /* Update operand types and check extended states. */
5042 for (j
= 0; j
< i
.operands
; j
++)
5044 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5045 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5050 i
.xstate
|= xstate_mmx
;
5053 i
.xstate
|= xstate_mask
;
5056 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5057 i
.xstate
|= xstate_tmm
;
5058 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5059 i
.xstate
|= xstate_zmm
;
5060 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5061 i
.xstate
|= xstate_ymm
;
5062 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5063 i
.xstate
|= xstate_xmm
;
5068 /* Make still unresolved immediate matches conform to size of immediate
5069 given in i.suffix. */
5070 if (!finalize_imm ())
5073 if (i
.types
[0].bitfield
.imm1
)
5074 i
.imm_operands
= 0; /* kludge for shift insns. */
5076 /* We only need to check those implicit registers for instructions
5077 with 3 operands or less. */
5078 if (i
.operands
<= 3)
5079 for (j
= 0; j
< i
.operands
; j
++)
5080 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
5081 && !i
.types
[j
].bitfield
.xmmword
)
5084 /* For insns with operands there are more diddles to do to the opcode. */
5087 if (!process_operands ())
5090 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5092 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5093 as_warn (_("translating to `%sp'"), i
.tm
.name
);
5096 if (is_any_vex_encoding (&i
.tm
))
5098 if (!cpu_arch_flags
.bitfield
.cpui286
)
5100 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5105 /* Check for explicit REX prefix. */
5106 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5108 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
5112 if (i
.tm
.opcode_modifier
.vex
)
5113 build_vex_prefix (t
);
5115 build_evex_prefix ();
5117 /* The individual REX.RXBW bits got consumed. */
5118 i
.rex
&= REX_OPCODE
;
5121 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
5122 instructions may define INT_OPCODE as well, so avoid this corner
5123 case for those instructions that use MODRM. */
5124 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
5125 && i
.tm
.base_opcode
== INT_OPCODE
5126 && !i
.tm
.opcode_modifier
.modrm
5127 && i
.op
[0].imms
->X_add_number
== 3)
5129 i
.tm
.base_opcode
= INT3_OPCODE
;
5133 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5134 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5135 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5136 && i
.op
[0].disps
->X_op
== O_constant
)
5138 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5139 the absolute address given by the constant. Since ix86 jumps and
5140 calls are pc relative, we need to generate a reloc. */
5141 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5142 i
.op
[0].disps
->X_op
= O_symbol
;
5145 /* For 8 bit registers we need an empty rex prefix. Also if the
5146 instruction already has a prefix, we need to convert old
5147 registers to new ones. */
5149 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5150 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5151 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5152 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5153 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5154 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5159 i
.rex
|= REX_OPCODE
;
5160 for (x
= 0; x
< 2; x
++)
5162 /* Look for 8 bit operand that uses old registers. */
5163 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5164 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5166 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5167 /* In case it is "hi" register, give up. */
5168 if (i
.op
[x
].regs
->reg_num
> 3)
5169 as_bad (_("can't encode register '%s%s' in an "
5170 "instruction requiring REX prefix."),
5171 register_prefix
, i
.op
[x
].regs
->reg_name
);
5173 /* Otherwise it is equivalent to the extended register.
5174 Since the encoding doesn't change this is merely
5175 cosmetic cleanup for debug output. */
5177 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5182 if (i
.rex
== 0 && i
.rex_encoding
)
5184 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5185 that uses legacy register. If it is "hi" register, don't add
5186 the REX_OPCODE byte. */
5188 for (x
= 0; x
< 2; x
++)
5189 if (i
.types
[x
].bitfield
.class == Reg
5190 && i
.types
[x
].bitfield
.byte
5191 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5192 && i
.op
[x
].regs
->reg_num
> 3)
5194 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5195 i
.rex_encoding
= false;
5204 add_prefix (REX_OPCODE
| i
.rex
);
5206 insert_lfence_before ();
5208 /* We are ready to output the insn. */
5211 insert_lfence_after ();
5213 last_insn
.seg
= now_seg
;
5215 if (i
.tm
.opcode_modifier
.isprefix
)
5217 last_insn
.kind
= last_insn_prefix
;
5218 last_insn
.name
= i
.tm
.name
;
5219 last_insn
.file
= as_where (&last_insn
.line
);
5222 last_insn
.kind
= last_insn_other
;
5226 parse_insn (char *line
, char *mnemonic
)
5229 char *token_start
= l
;
5232 const insn_template
*t
;
5238 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5243 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5245 as_bad (_("no such instruction: `%s'"), token_start
);
5250 if (!is_space_char (*l
)
5251 && *l
!= END_OF_INSN
5253 || (*l
!= PREFIX_SEPARATOR
5256 as_bad (_("invalid character %s in mnemonic"),
5257 output_invalid (*l
));
5260 if (token_start
== l
)
5262 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5263 as_bad (_("expecting prefix; got nothing"));
5265 as_bad (_("expecting mnemonic; got nothing"));
5269 /* Look up instruction (or prefix) via hash table. */
5270 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5272 if (*l
!= END_OF_INSN
5273 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5274 && current_templates
5275 && current_templates
->start
->opcode_modifier
.isprefix
)
5277 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5279 as_bad ((flag_code
!= CODE_64BIT
5280 ? _("`%s' is only supported in 64-bit mode")
5281 : _("`%s' is not supported in 64-bit mode")),
5282 current_templates
->start
->name
);
5285 /* If we are in 16-bit mode, do not allow addr16 or data16.
5286 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5287 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5288 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5289 && flag_code
!= CODE_64BIT
5290 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5291 ^ (flag_code
== CODE_16BIT
)))
5293 as_bad (_("redundant %s prefix"),
5294 current_templates
->start
->name
);
5298 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5300 /* Handle pseudo prefixes. */
5301 switch (current_templates
->start
->extension_opcode
)
5305 i
.disp_encoding
= disp_encoding_8bit
;
5309 i
.disp_encoding
= disp_encoding_16bit
;
5313 i
.disp_encoding
= disp_encoding_32bit
;
5317 i
.dir_encoding
= dir_encoding_load
;
5321 i
.dir_encoding
= dir_encoding_store
;
5325 i
.vec_encoding
= vex_encoding_vex
;
5329 i
.vec_encoding
= vex_encoding_vex3
;
5333 i
.vec_encoding
= vex_encoding_evex
;
5337 i
.rex_encoding
= true;
5339 case Prefix_NoOptimize
:
5341 i
.no_optimize
= true;
5349 /* Add prefix, checking for repeated prefixes. */
5350 switch (add_prefix (current_templates
->start
->base_opcode
))
5355 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5356 i
.notrack_prefix
= current_templates
->start
->name
;
5359 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5360 i
.hle_prefix
= current_templates
->start
->name
;
5361 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5362 i
.bnd_prefix
= current_templates
->start
->name
;
5364 i
.rep_prefix
= current_templates
->start
->name
;
5370 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5377 if (!current_templates
)
5379 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5380 Check if we should swap operand or force 32bit displacement in
5382 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5383 i
.dir_encoding
= dir_encoding_swap
;
5384 else if (mnem_p
- 3 == dot_p
5387 i
.disp_encoding
= disp_encoding_8bit
;
5388 else if (mnem_p
- 4 == dot_p
5392 i
.disp_encoding
= disp_encoding_32bit
;
5397 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5400 if (!current_templates
)
5403 if (mnem_p
> mnemonic
)
5405 /* See if we can get a match by trimming off a suffix. */
5408 case WORD_MNEM_SUFFIX
:
5409 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5410 i
.suffix
= SHORT_MNEM_SUFFIX
;
5413 case BYTE_MNEM_SUFFIX
:
5414 case QWORD_MNEM_SUFFIX
:
5415 i
.suffix
= mnem_p
[-1];
5418 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5420 case SHORT_MNEM_SUFFIX
:
5421 case LONG_MNEM_SUFFIX
:
5424 i
.suffix
= mnem_p
[-1];
5427 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5435 if (intel_float_operand (mnemonic
) == 1)
5436 i
.suffix
= SHORT_MNEM_SUFFIX
;
5438 i
.suffix
= LONG_MNEM_SUFFIX
;
5441 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5447 if (!current_templates
)
5449 as_bad (_("no such instruction: `%s'"), token_start
);
5454 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5455 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5457 /* Check for a branch hint. We allow ",pt" and ",pn" for
5458 predict taken and predict not taken respectively.
5459 I'm not sure that branch hints actually do anything on loop
5460 and jcxz insns (JumpByte) for current Pentium4 chips. They
5461 may work in the future and it doesn't hurt to accept them
5463 if (l
[0] == ',' && l
[1] == 'p')
5467 if (!add_prefix (DS_PREFIX_OPCODE
))
5471 else if (l
[2] == 'n')
5473 if (!add_prefix (CS_PREFIX_OPCODE
))
5479 /* Any other comma loses. */
5482 as_bad (_("invalid character %s in mnemonic"),
5483 output_invalid (*l
));
5487 /* Check if instruction is supported on specified architecture. */
5489 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5491 supported
|= cpu_flags_match (t
);
5492 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5494 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5495 as_warn (_("use .code16 to ensure correct addressing mode"));
5501 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5502 as_bad (flag_code
== CODE_64BIT
5503 ? _("`%s' is not supported in 64-bit mode")
5504 : _("`%s' is only supported in 64-bit mode"),
5505 current_templates
->start
->name
);
5507 as_bad (_("`%s' is not supported on `%s%s'"),
5508 current_templates
->start
->name
,
5509 cpu_arch_name
? cpu_arch_name
: default_arch
,
5510 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5516 parse_operands (char *l
, const char *mnemonic
)
5520 /* 1 if operand is pending after ','. */
5521 unsigned int expecting_operand
= 0;
5523 /* Non-zero if operand parens not balanced. */
5524 unsigned int paren_not_balanced
;
5526 while (*l
!= END_OF_INSN
)
5528 /* Skip optional white space before operand. */
5529 if (is_space_char (*l
))
5531 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5533 as_bad (_("invalid character %s before operand %d"),
5534 output_invalid (*l
),
5538 token_start
= l
; /* After white space. */
5539 paren_not_balanced
= 0;
5540 while (paren_not_balanced
|| *l
!= ',')
5542 if (*l
== END_OF_INSN
)
5544 if (paren_not_balanced
)
5547 as_bad (_("unbalanced parenthesis in operand %d."),
5550 as_bad (_("unbalanced brackets in operand %d."),
5555 break; /* we are done */
5557 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5559 as_bad (_("invalid character %s in operand %d"),
5560 output_invalid (*l
),
5567 ++paren_not_balanced
;
5569 --paren_not_balanced
;
5574 ++paren_not_balanced
;
5576 --paren_not_balanced
;
5580 if (l
!= token_start
)
5581 { /* Yes, we've read in another operand. */
5582 unsigned int operand_ok
;
5583 this_operand
= i
.operands
++;
5584 if (i
.operands
> MAX_OPERANDS
)
5586 as_bad (_("spurious operands; (%d operands/instruction max)"),
5590 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5591 /* Now parse operand adding info to 'i' as we go along. */
5592 END_STRING_AND_SAVE (l
);
5594 if (i
.mem_operands
> 1)
5596 as_bad (_("too many memory references for `%s'"),
5603 i386_intel_operand (token_start
,
5604 intel_float_operand (mnemonic
));
5606 operand_ok
= i386_att_operand (token_start
);
5608 RESTORE_END_STRING (l
);
5614 if (expecting_operand
)
5616 expecting_operand_after_comma
:
5617 as_bad (_("expecting operand after ','; got nothing"));
5622 as_bad (_("expecting operand before ','; got nothing"));
5627 /* Now *l must be either ',' or END_OF_INSN. */
5630 if (*++l
== END_OF_INSN
)
5632 /* Just skip it, if it's \n complain. */
5633 goto expecting_operand_after_comma
;
5635 expecting_operand
= 1;
5642 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5644 union i386_op temp_op
;
5645 i386_operand_type temp_type
;
5646 unsigned int temp_flags
;
5647 enum bfd_reloc_code_real temp_reloc
;
5649 temp_type
= i
.types
[xchg2
];
5650 i
.types
[xchg2
] = i
.types
[xchg1
];
5651 i
.types
[xchg1
] = temp_type
;
5653 temp_flags
= i
.flags
[xchg2
];
5654 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5655 i
.flags
[xchg1
] = temp_flags
;
5657 temp_op
= i
.op
[xchg2
];
5658 i
.op
[xchg2
] = i
.op
[xchg1
];
5659 i
.op
[xchg1
] = temp_op
;
5661 temp_reloc
= i
.reloc
[xchg2
];
5662 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5663 i
.reloc
[xchg1
] = temp_reloc
;
5667 if (i
.mask
.operand
== xchg1
)
5668 i
.mask
.operand
= xchg2
;
5669 else if (i
.mask
.operand
== xchg2
)
5670 i
.mask
.operand
= xchg1
;
5672 if (i
.broadcast
.type
)
5674 if (i
.broadcast
.operand
== xchg1
)
5675 i
.broadcast
.operand
= xchg2
;
5676 else if (i
.broadcast
.operand
== xchg2
)
5677 i
.broadcast
.operand
= xchg1
;
5679 if (i
.rounding
.type
!= rc_none
)
5681 if (i
.rounding
.operand
== xchg1
)
5682 i
.rounding
.operand
= xchg2
;
5683 else if (i
.rounding
.operand
== xchg2
)
5684 i
.rounding
.operand
= xchg1
;
5689 swap_operands (void)
5695 swap_2_operands (1, i
.operands
- 2);
5699 swap_2_operands (0, i
.operands
- 1);
5705 if (i
.mem_operands
== 2)
5707 const reg_entry
*temp_seg
;
5708 temp_seg
= i
.seg
[0];
5709 i
.seg
[0] = i
.seg
[1];
5710 i
.seg
[1] = temp_seg
;
5714 /* Try to ensure constant immediates are represented in the smallest
5719 char guess_suffix
= 0;
5723 guess_suffix
= i
.suffix
;
5724 else if (i
.reg_operands
)
5726 /* Figure out a suffix from the last register operand specified.
5727 We can't do this properly yet, i.e. excluding special register
5728 instances, but the following works for instructions with
5729 immediates. In any case, we can't set i.suffix yet. */
5730 for (op
= i
.operands
; --op
>= 0;)
5731 if (i
.types
[op
].bitfield
.class != Reg
)
5733 else if (i
.types
[op
].bitfield
.byte
)
5735 guess_suffix
= BYTE_MNEM_SUFFIX
;
5738 else if (i
.types
[op
].bitfield
.word
)
5740 guess_suffix
= WORD_MNEM_SUFFIX
;
5743 else if (i
.types
[op
].bitfield
.dword
)
5745 guess_suffix
= LONG_MNEM_SUFFIX
;
5748 else if (i
.types
[op
].bitfield
.qword
)
5750 guess_suffix
= QWORD_MNEM_SUFFIX
;
5754 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5755 guess_suffix
= WORD_MNEM_SUFFIX
;
5757 for (op
= i
.operands
; --op
>= 0;)
5758 if (operand_type_check (i
.types
[op
], imm
))
5760 switch (i
.op
[op
].imms
->X_op
)
5763 /* If a suffix is given, this operand may be shortened. */
5764 switch (guess_suffix
)
5766 case LONG_MNEM_SUFFIX
:
5767 i
.types
[op
].bitfield
.imm32
= 1;
5768 i
.types
[op
].bitfield
.imm64
= 1;
5770 case WORD_MNEM_SUFFIX
:
5771 i
.types
[op
].bitfield
.imm16
= 1;
5772 i
.types
[op
].bitfield
.imm32
= 1;
5773 i
.types
[op
].bitfield
.imm32s
= 1;
5774 i
.types
[op
].bitfield
.imm64
= 1;
5776 case BYTE_MNEM_SUFFIX
:
5777 i
.types
[op
].bitfield
.imm8
= 1;
5778 i
.types
[op
].bitfield
.imm8s
= 1;
5779 i
.types
[op
].bitfield
.imm16
= 1;
5780 i
.types
[op
].bitfield
.imm32
= 1;
5781 i
.types
[op
].bitfield
.imm32s
= 1;
5782 i
.types
[op
].bitfield
.imm64
= 1;
5786 /* If this operand is at most 16 bits, convert it
5787 to a signed 16 bit number before trying to see
5788 whether it will fit in an even smaller size.
5789 This allows a 16-bit operand such as $0xffe0 to
5790 be recognised as within Imm8S range. */
5791 if ((i
.types
[op
].bitfield
.imm16
)
5792 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5794 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5795 ^ 0x8000) - 0x8000);
5798 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5799 if ((i
.types
[op
].bitfield
.imm32
)
5800 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5803 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5804 ^ ((offsetT
) 1 << 31))
5805 - ((offsetT
) 1 << 31));
5809 = operand_type_or (i
.types
[op
],
5810 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5812 /* We must avoid matching of Imm32 templates when 64bit
5813 only immediate is available. */
5814 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5815 i
.types
[op
].bitfield
.imm32
= 0;
5822 /* Symbols and expressions. */
5824 /* Convert symbolic operand to proper sizes for matching, but don't
5825 prevent matching a set of insns that only supports sizes other
5826 than those matching the insn suffix. */
5828 i386_operand_type mask
, allowed
;
5829 const insn_template
*t
= current_templates
->start
;
5831 operand_type_set (&mask
, 0);
5832 allowed
= t
->operand_types
[op
];
5834 while (++t
< current_templates
->end
)
5836 allowed
= operand_type_and (allowed
, anyimm
);
5837 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5839 switch (guess_suffix
)
5841 case QWORD_MNEM_SUFFIX
:
5842 mask
.bitfield
.imm64
= 1;
5843 mask
.bitfield
.imm32s
= 1;
5845 case LONG_MNEM_SUFFIX
:
5846 mask
.bitfield
.imm32
= 1;
5848 case WORD_MNEM_SUFFIX
:
5849 mask
.bitfield
.imm16
= 1;
5851 case BYTE_MNEM_SUFFIX
:
5852 mask
.bitfield
.imm8
= 1;
5857 allowed
= operand_type_and (mask
, allowed
);
5858 if (!operand_type_all_zero (&allowed
))
5859 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5866 /* Try to use the smallest displacement type too. */
5868 optimize_disp (void)
5872 for (op
= i
.operands
; --op
>= 0;)
5873 if (operand_type_check (i
.types
[op
], disp
))
5875 if (i
.op
[op
].disps
->X_op
== O_constant
)
5877 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5879 if (i
.types
[op
].bitfield
.disp16
5880 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5882 /* If this operand is at most 16 bits, convert
5883 to a signed 16 bit number and don't use 64bit
5885 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5886 i
.types
[op
].bitfield
.disp64
= 0;
5888 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5890 i
.types
[op
].bitfield
.disp8
= 0;
5891 i
.types
[op
].bitfield
.disp16
= 0;
5892 i
.types
[op
].bitfield
.disp32
= 0;
5893 i
.types
[op
].bitfield
.disp32s
= 0;
5894 i
.types
[op
].bitfield
.disp64
= 0;
5899 else if (flag_code
== CODE_64BIT
)
5901 if (want_disp32 (current_templates
->start
)
5902 && fits_in_unsigned_long (op_disp
))
5903 i
.types
[op
].bitfield
.disp32
= 1;
5905 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5906 if (i
.types
[op
].bitfield
.disp32
5907 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5909 /* If this operand is at most 32 bits, convert
5910 to a signed 32 bit number and don't use 64bit
5912 op_disp
&= (((offsetT
) 2 << 31) - 1);
5913 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5914 i
.types
[op
].bitfield
.disp64
= 0;
5917 if (fits_in_signed_long (op_disp
))
5919 i
.types
[op
].bitfield
.disp64
= 0;
5920 i
.types
[op
].bitfield
.disp32s
= 1;
5924 if ((i
.types
[op
].bitfield
.disp32
5925 || i
.types
[op
].bitfield
.disp32s
5926 || i
.types
[op
].bitfield
.disp16
)
5927 && fits_in_disp8 (op_disp
))
5928 i
.types
[op
].bitfield
.disp8
= 1;
5930 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5931 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5933 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5934 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5935 i
.types
[op
].bitfield
.disp8
= 0;
5936 i
.types
[op
].bitfield
.disp16
= 0;
5937 i
.types
[op
].bitfield
.disp32
= 0;
5938 i
.types
[op
].bitfield
.disp32s
= 0;
5939 i
.types
[op
].bitfield
.disp64
= 0;
5942 /* We only support 64bit displacement on constants. */
5943 i
.types
[op
].bitfield
.disp64
= 0;
5947 /* Return 1 if there is a match in broadcast bytes between operand
5948 GIVEN and instruction template T. */
5951 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5953 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5954 && i
.types
[given
].bitfield
.byte
)
5955 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5956 && i
.types
[given
].bitfield
.word
)
5957 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5958 && i
.types
[given
].bitfield
.dword
)
5959 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5960 && i
.types
[given
].bitfield
.qword
));
5963 /* Check if operands are valid for the instruction. */
5966 check_VecOperands (const insn_template
*t
)
5971 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5972 any one operand are implicity requiring AVX512VL support if the actual
5973 operand size is YMMword or XMMword. Since this function runs after
5974 template matching, there's no need to check for YMMword/XMMword in
5976 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5977 if (!cpu_flags_all_zero (&cpu
)
5978 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5979 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5981 for (op
= 0; op
< t
->operands
; ++op
)
5983 if (t
->operand_types
[op
].bitfield
.zmmword
5984 && (i
.types
[op
].bitfield
.ymmword
5985 || i
.types
[op
].bitfield
.xmmword
))
5987 i
.error
= unsupported
;
5993 /* Without VSIB byte, we can't have a vector register for index. */
5994 if (!t
->opcode_modifier
.sib
5996 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5997 || i
.index_reg
->reg_type
.bitfield
.ymmword
5998 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6000 i
.error
= unsupported_vector_index_register
;
6004 /* Check if default mask is allowed. */
6005 if (t
->opcode_modifier
.nodefmask
6006 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6008 i
.error
= no_default_mask
;
6012 /* For VSIB byte, we need a vector register for index, and all vector
6013 registers must be distinct. */
6014 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6017 || !((t
->opcode_modifier
.sib
== VECSIB128
6018 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6019 || (t
->opcode_modifier
.sib
== VECSIB256
6020 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6021 || (t
->opcode_modifier
.sib
== VECSIB512
6022 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6024 i
.error
= invalid_vsib_address
;
6028 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6029 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6031 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6032 gas_assert (i
.types
[0].bitfield
.xmmword
6033 || i
.types
[0].bitfield
.ymmword
);
6034 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6035 gas_assert (i
.types
[2].bitfield
.xmmword
6036 || i
.types
[2].bitfield
.ymmword
);
6037 if (operand_check
== check_none
)
6039 if (register_number (i
.op
[0].regs
)
6040 != register_number (i
.index_reg
)
6041 && register_number (i
.op
[2].regs
)
6042 != register_number (i
.index_reg
)
6043 && register_number (i
.op
[0].regs
)
6044 != register_number (i
.op
[2].regs
))
6046 if (operand_check
== check_error
)
6048 i
.error
= invalid_vector_register_set
;
6051 as_warn (_("mask, index, and destination registers should be distinct"));
6053 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6055 if (i
.types
[1].bitfield
.class == RegSIMD
6056 && (i
.types
[1].bitfield
.xmmword
6057 || i
.types
[1].bitfield
.ymmword
6058 || i
.types
[1].bitfield
.zmmword
)
6059 && (register_number (i
.op
[1].regs
)
6060 == register_number (i
.index_reg
)))
6062 if (operand_check
== check_error
)
6064 i
.error
= invalid_vector_register_set
;
6067 if (operand_check
!= check_none
)
6068 as_warn (_("index and destination registers should be distinct"));
6073 /* For AMX instructions with three tmmword operands, all tmmword operand must be
6075 if (t
->operand_types
[0].bitfield
.tmmword
6076 && i
.reg_operands
== 3)
6078 if (register_number (i
.op
[0].regs
)
6079 == register_number (i
.op
[1].regs
)
6080 || register_number (i
.op
[0].regs
)
6081 == register_number (i
.op
[2].regs
)
6082 || register_number (i
.op
[1].regs
)
6083 == register_number (i
.op
[2].regs
))
6085 i
.error
= invalid_tmm_register_set
;
6090 /* Check if broadcast is supported by the instruction and is applied
6091 to the memory operand. */
6092 if (i
.broadcast
.type
)
6094 i386_operand_type type
, overlap
;
6096 /* Check if specified broadcast is supported in this instruction,
6097 and its broadcast bytes match the memory operand. */
6098 op
= i
.broadcast
.operand
;
6099 if (!t
->opcode_modifier
.broadcast
6100 || !(i
.flags
[op
] & Operand_Mem
)
6101 || (!i
.types
[op
].bitfield
.unspecified
6102 && !match_broadcast_size (t
, op
)))
6105 i
.error
= unsupported_broadcast
;
6109 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6110 * i
.broadcast
.type
);
6111 operand_type_set (&type
, 0);
6112 switch (i
.broadcast
.bytes
)
6115 type
.bitfield
.word
= 1;
6118 type
.bitfield
.dword
= 1;
6121 type
.bitfield
.qword
= 1;
6124 type
.bitfield
.xmmword
= 1;
6127 type
.bitfield
.ymmword
= 1;
6130 type
.bitfield
.zmmword
= 1;
6136 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6137 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6138 && t
->operand_types
[op
].bitfield
.byte
6139 + t
->operand_types
[op
].bitfield
.word
6140 + t
->operand_types
[op
].bitfield
.dword
6141 + t
->operand_types
[op
].bitfield
.qword
> 1)
6143 overlap
.bitfield
.xmmword
= 0;
6144 overlap
.bitfield
.ymmword
= 0;
6145 overlap
.bitfield
.zmmword
= 0;
6147 if (operand_type_all_zero (&overlap
))
6150 if (t
->opcode_modifier
.checkregsize
)
6154 type
.bitfield
.baseindex
= 1;
6155 for (j
= 0; j
< i
.operands
; ++j
)
6158 && !operand_type_register_match(i
.types
[j
],
6159 t
->operand_types
[j
],
6161 t
->operand_types
[op
]))
6166 /* If broadcast is supported in this instruction, we need to check if
6167 operand of one-element size isn't specified without broadcast. */
6168 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6170 /* Find memory operand. */
6171 for (op
= 0; op
< i
.operands
; op
++)
6172 if (i
.flags
[op
] & Operand_Mem
)
6174 gas_assert (op
< i
.operands
);
6175 /* Check size of the memory operand. */
6176 if (match_broadcast_size (t
, op
))
6178 i
.error
= broadcast_needed
;
6183 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6185 /* Check if requested masking is supported. */
6188 switch (t
->opcode_modifier
.masking
)
6192 case MERGING_MASKING
:
6196 i
.error
= unsupported_masking
;
6200 case DYNAMIC_MASKING
:
6201 /* Memory destinations allow only merging masking. */
6202 if (i
.mask
.zeroing
&& i
.mem_operands
)
6204 /* Find memory operand. */
6205 for (op
= 0; op
< i
.operands
; op
++)
6206 if (i
.flags
[op
] & Operand_Mem
)
6208 gas_assert (op
< i
.operands
);
6209 if (op
== i
.operands
- 1)
6211 i
.error
= unsupported_masking
;
6221 /* Check if masking is applied to dest operand. */
6222 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6224 i
.error
= mask_not_on_destination
;
6229 if (i
.rounding
.type
!= rc_none
)
6231 if (!t
->opcode_modifier
.sae
6232 || (i
.rounding
.type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6234 i
.error
= unsupported_rc_sae
;
6237 /* If the instruction has several immediate operands and one of
6238 them is rounding, the rounding operand should be the last
6239 immediate operand. */
6240 if (i
.imm_operands
> 1
6241 && i
.rounding
.operand
!= i
.imm_operands
- 1)
6243 i
.error
= rc_sae_operand_not_last_imm
;
6248 /* Check the special Imm4 cases; must be the first operand. */
6249 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6251 if (i
.op
[0].imms
->X_op
!= O_constant
6252 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6258 /* Turn off Imm<N> so that update_imm won't complain. */
6259 operand_type_set (&i
.types
[0], 0);
6262 /* Check vector Disp8 operand. */
6263 if (t
->opcode_modifier
.disp8memshift
6264 && i
.disp_encoding
!= disp_encoding_32bit
)
6266 if (i
.broadcast
.type
)
6267 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6268 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6269 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6272 const i386_operand_type
*type
= NULL
;
6275 for (op
= 0; op
< i
.operands
; op
++)
6276 if (i
.flags
[op
] & Operand_Mem
)
6278 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6279 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6280 else if (t
->operand_types
[op
].bitfield
.xmmword
6281 + t
->operand_types
[op
].bitfield
.ymmword
6282 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6283 type
= &t
->operand_types
[op
];
6284 else if (!i
.types
[op
].bitfield
.unspecified
)
6285 type
= &i
.types
[op
];
6287 else if (i
.types
[op
].bitfield
.class == RegSIMD
6288 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6290 if (i
.types
[op
].bitfield
.zmmword
)
6292 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6294 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6300 if (type
->bitfield
.zmmword
)
6302 else if (type
->bitfield
.ymmword
)
6304 else if (type
->bitfield
.xmmword
)
6308 /* For the check in fits_in_disp8(). */
6309 if (i
.memshift
== 0)
6313 for (op
= 0; op
< i
.operands
; op
++)
6314 if (operand_type_check (i
.types
[op
], disp
)
6315 && i
.op
[op
].disps
->X_op
== O_constant
)
6317 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6319 i
.types
[op
].bitfield
.disp8
= 1;
6322 i
.types
[op
].bitfield
.disp8
= 0;
6331 /* Check if encoding requirements are met by the instruction. */
6334 VEX_check_encoding (const insn_template
*t
)
6336 if (i
.vec_encoding
== vex_encoding_error
)
6338 i
.error
= unsupported
;
6342 if (i
.vec_encoding
== vex_encoding_evex
)
6344 /* This instruction must be encoded with EVEX prefix. */
6345 if (!is_evex_encoding (t
))
6347 i
.error
= unsupported
;
6353 if (!t
->opcode_modifier
.vex
)
6355 /* This instruction template doesn't have VEX prefix. */
6356 if (i
.vec_encoding
!= vex_encoding_default
)
6358 i
.error
= unsupported
;
6367 static const insn_template
*
6368 match_template (char mnem_suffix
)
6370 /* Points to template once we've found it. */
6371 const insn_template
*t
;
6372 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6373 i386_operand_type overlap4
;
6374 unsigned int found_reverse_match
;
6375 i386_opcode_modifier suffix_check
;
6376 i386_operand_type operand_types
[MAX_OPERANDS
];
6377 int addr_prefix_disp
;
6378 unsigned int j
, size_match
, check_register
;
6379 enum i386_error specific_error
= 0;
6381 #if MAX_OPERANDS != 5
6382 # error "MAX_OPERANDS must be 5."
6385 found_reverse_match
= 0;
6386 addr_prefix_disp
= -1;
6388 /* Prepare for mnemonic suffix check. */
6389 memset (&suffix_check
, 0, sizeof (suffix_check
));
6390 switch (mnem_suffix
)
6392 case BYTE_MNEM_SUFFIX
:
6393 suffix_check
.no_bsuf
= 1;
6395 case WORD_MNEM_SUFFIX
:
6396 suffix_check
.no_wsuf
= 1;
6398 case SHORT_MNEM_SUFFIX
:
6399 suffix_check
.no_ssuf
= 1;
6401 case LONG_MNEM_SUFFIX
:
6402 suffix_check
.no_lsuf
= 1;
6404 case QWORD_MNEM_SUFFIX
:
6405 suffix_check
.no_qsuf
= 1;
6408 /* NB: In Intel syntax, normally we can check for memory operand
6409 size when there is no mnemonic suffix. But jmp and call have
6410 2 different encodings with Dword memory operand size, one with
6411 No_ldSuf and the other without. i.suffix is set to
6412 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6413 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6414 suffix_check
.no_ldsuf
= 1;
6417 /* Must have right number of operands. */
6418 i
.error
= number_of_operands_mismatch
;
6420 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6422 addr_prefix_disp
= -1;
6423 found_reverse_match
= 0;
6425 if (i
.operands
!= t
->operands
)
6428 /* Check processor support. */
6429 i
.error
= unsupported
;
6430 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6433 /* Check Pseudo Prefix. */
6434 i
.error
= unsupported
;
6435 if (t
->opcode_modifier
.pseudovexprefix
6436 && !(i
.vec_encoding
== vex_encoding_vex
6437 || i
.vec_encoding
== vex_encoding_vex3
))
6440 /* Check AT&T mnemonic. */
6441 i
.error
= unsupported_with_intel_mnemonic
;
6442 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6445 /* Check AT&T/Intel syntax. */
6446 i
.error
= unsupported_syntax
;
6447 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6448 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6451 /* Check Intel64/AMD64 ISA. */
6455 /* Default: Don't accept Intel64. */
6456 if (t
->opcode_modifier
.isa64
== INTEL64
)
6460 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6461 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6465 /* -mintel64: Don't accept AMD64. */
6466 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6471 /* Check the suffix. */
6472 i
.error
= invalid_instruction_suffix
;
6473 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6474 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6475 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6476 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6477 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6478 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6481 size_match
= operand_size_match (t
);
6485 /* This is intentionally not
6487 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6489 as the case of a missing * on the operand is accepted (perhaps with
6490 a warning, issued further down). */
6491 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6493 i
.error
= operand_type_mismatch
;
6497 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6498 operand_types
[j
] = t
->operand_types
[j
];
6500 /* In general, don't allow
6501 - 64-bit operands outside of 64-bit mode,
6502 - 32-bit operands on pre-386. */
6503 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6504 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6505 && flag_code
!= CODE_64BIT
6506 && !(t
->opcode_modifier
.opcodespace
== SPACE_0F
6507 && t
->base_opcode
== 0xc7
6508 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6509 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6510 || (i
.suffix
== LONG_MNEM_SUFFIX
6511 && !cpu_arch_flags
.bitfield
.cpui386
))
6513 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6514 && !intel_float_operand (t
->name
))
6515 : intel_float_operand (t
->name
) != 2)
6516 && (t
->operands
== i
.imm_operands
6517 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6518 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6519 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6520 || (operand_types
[j
].bitfield
.class != RegMMX
6521 && operand_types
[j
].bitfield
.class != RegSIMD
6522 && operand_types
[j
].bitfield
.class != RegMask
))
6523 && !t
->opcode_modifier
.sib
)
6526 /* Do not verify operands when there are none. */
6529 if (VEX_check_encoding (t
))
6531 specific_error
= i
.error
;
6535 /* We've found a match; break out of loop. */
6539 if (!t
->opcode_modifier
.jump
6540 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6542 /* There should be only one Disp operand. */
6543 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6544 if (operand_type_check (operand_types
[j
], disp
))
6546 if (j
< MAX_OPERANDS
)
6548 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6550 addr_prefix_disp
= j
;
6552 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6553 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6557 override
= !override
;
6560 if (operand_types
[j
].bitfield
.disp32
6561 && operand_types
[j
].bitfield
.disp16
)
6563 operand_types
[j
].bitfield
.disp16
= override
;
6564 operand_types
[j
].bitfield
.disp32
= !override
;
6566 operand_types
[j
].bitfield
.disp32s
= 0;
6567 operand_types
[j
].bitfield
.disp64
= 0;
6571 if (operand_types
[j
].bitfield
.disp32s
6572 || operand_types
[j
].bitfield
.disp64
)
6574 operand_types
[j
].bitfield
.disp64
&= !override
;
6575 operand_types
[j
].bitfield
.disp32s
&= !override
;
6576 operand_types
[j
].bitfield
.disp32
= override
;
6578 operand_types
[j
].bitfield
.disp16
= 0;
6584 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6585 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6586 && t
->base_opcode
== 0xa0
6587 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6590 /* We check register size if needed. */
6591 if (t
->opcode_modifier
.checkregsize
)
6593 check_register
= (1 << t
->operands
) - 1;
6594 if (i
.broadcast
.type
)
6595 check_register
&= ~(1 << i
.broadcast
.operand
);
6600 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6601 switch (t
->operands
)
6604 if (!operand_type_match (overlap0
, i
.types
[0]))
6608 /* xchg %eax, %eax is a special case. It is an alias for nop
6609 only in 32bit mode and we can use opcode 0x90. In 64bit
6610 mode, we can't use 0x90 for xchg %eax, %eax since it should
6611 zero-extend %eax to %rax. */
6612 if (flag_code
== CODE_64BIT
6613 && t
->base_opcode
== 0x90
6614 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6615 && i
.types
[0].bitfield
.instance
== Accum
6616 && i
.types
[0].bitfield
.dword
6617 && i
.types
[1].bitfield
.instance
== Accum
6618 && i
.types
[1].bitfield
.dword
)
6620 /* xrelease mov %eax, <disp> is another special case. It must not
6621 match the accumulator-only encoding of mov. */
6622 if (flag_code
!= CODE_64BIT
6624 && t
->base_opcode
== 0xa0
6625 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6626 && i
.types
[0].bitfield
.instance
== Accum
6627 && (i
.flags
[1] & Operand_Mem
))
6632 if (!(size_match
& MATCH_STRAIGHT
))
6634 /* Reverse direction of operands if swapping is possible in the first
6635 place (operands need to be symmetric) and
6636 - the load form is requested, and the template is a store form,
6637 - the store form is requested, and the template is a load form,
6638 - the non-default (swapped) form is requested. */
6639 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6640 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6641 && !operand_type_all_zero (&overlap1
))
6642 switch (i
.dir_encoding
)
6644 case dir_encoding_load
:
6645 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6646 || t
->opcode_modifier
.regmem
)
6650 case dir_encoding_store
:
6651 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6652 && !t
->opcode_modifier
.regmem
)
6656 case dir_encoding_swap
:
6659 case dir_encoding_default
:
6662 /* If we want store form, we skip the current load. */
6663 if ((i
.dir_encoding
== dir_encoding_store
6664 || i
.dir_encoding
== dir_encoding_swap
)
6665 && i
.mem_operands
== 0
6666 && t
->opcode_modifier
.load
)
6671 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6672 if (!operand_type_match (overlap0
, i
.types
[0])
6673 || !operand_type_match (overlap1
, i
.types
[1])
6674 || ((check_register
& 3) == 3
6675 && !operand_type_register_match (i
.types
[0],
6680 /* Check if other direction is valid ... */
6681 if (!t
->opcode_modifier
.d
)
6685 if (!(size_match
& MATCH_REVERSE
))
6687 /* Try reversing direction of operands. */
6688 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6689 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6690 if (!operand_type_match (overlap0
, i
.types
[0])
6691 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6693 && !operand_type_register_match (i
.types
[0],
6694 operand_types
[i
.operands
- 1],
6695 i
.types
[i
.operands
- 1],
6698 /* Does not match either direction. */
6701 /* found_reverse_match holds which of D or FloatR
6703 if (!t
->opcode_modifier
.d
)
6704 found_reverse_match
= 0;
6705 else if (operand_types
[0].bitfield
.tbyte
)
6706 found_reverse_match
= Opcode_FloatD
;
6707 else if (operand_types
[0].bitfield
.xmmword
6708 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6709 || operand_types
[0].bitfield
.class == RegMMX
6710 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6711 || is_any_vex_encoding(t
))
6712 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6713 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6715 found_reverse_match
= Opcode_D
;
6716 if (t
->opcode_modifier
.floatr
)
6717 found_reverse_match
|= Opcode_FloatR
;
6721 /* Found a forward 2 operand match here. */
6722 switch (t
->operands
)
6725 overlap4
= operand_type_and (i
.types
[4],
6729 overlap3
= operand_type_and (i
.types
[3],
6733 overlap2
= operand_type_and (i
.types
[2],
6738 switch (t
->operands
)
6741 if (!operand_type_match (overlap4
, i
.types
[4])
6742 || !operand_type_register_match (i
.types
[3],
6749 if (!operand_type_match (overlap3
, i
.types
[3])
6750 || ((check_register
& 0xa) == 0xa
6751 && !operand_type_register_match (i
.types
[1],
6755 || ((check_register
& 0xc) == 0xc
6756 && !operand_type_register_match (i
.types
[2],
6763 /* Here we make use of the fact that there are no
6764 reverse match 3 operand instructions. */
6765 if (!operand_type_match (overlap2
, i
.types
[2])
6766 || ((check_register
& 5) == 5
6767 && !operand_type_register_match (i
.types
[0],
6771 || ((check_register
& 6) == 6
6772 && !operand_type_register_match (i
.types
[1],
6780 /* Found either forward/reverse 2, 3 or 4 operand match here:
6781 slip through to break. */
6784 /* Check if vector operands are valid. */
6785 if (check_VecOperands (t
))
6787 specific_error
= i
.error
;
6791 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6792 if (VEX_check_encoding (t
))
6794 specific_error
= i
.error
;
6798 /* We've found a match; break out of loop. */
6802 if (t
== current_templates
->end
)
6804 /* We found no match. */
6805 const char *err_msg
;
6806 switch (specific_error
? specific_error
: i
.error
)
6810 case operand_size_mismatch
:
6811 err_msg
= _("operand size mismatch");
6813 case operand_type_mismatch
:
6814 err_msg
= _("operand type mismatch");
6816 case register_type_mismatch
:
6817 err_msg
= _("register type mismatch");
6819 case number_of_operands_mismatch
:
6820 err_msg
= _("number of operands mismatch");
6822 case invalid_instruction_suffix
:
6823 err_msg
= _("invalid instruction suffix");
6826 err_msg
= _("constant doesn't fit in 4 bits");
6828 case unsupported_with_intel_mnemonic
:
6829 err_msg
= _("unsupported with Intel mnemonic");
6831 case unsupported_syntax
:
6832 err_msg
= _("unsupported syntax");
6835 as_bad (_("unsupported instruction `%s'"),
6836 current_templates
->start
->name
);
6838 case invalid_sib_address
:
6839 err_msg
= _("invalid SIB address");
6841 case invalid_vsib_address
:
6842 err_msg
= _("invalid VSIB address");
6844 case invalid_vector_register_set
:
6845 err_msg
= _("mask, index, and destination registers must be distinct");
6847 case invalid_tmm_register_set
:
6848 err_msg
= _("all tmm registers must be distinct");
6850 case unsupported_vector_index_register
:
6851 err_msg
= _("unsupported vector index register");
6853 case unsupported_broadcast
:
6854 err_msg
= _("unsupported broadcast");
6856 case broadcast_needed
:
6857 err_msg
= _("broadcast is needed for operand of such type");
6859 case unsupported_masking
:
6860 err_msg
= _("unsupported masking");
6862 case mask_not_on_destination
:
6863 err_msg
= _("mask not on destination operand");
6865 case no_default_mask
:
6866 err_msg
= _("default mask isn't allowed");
6868 case unsupported_rc_sae
:
6869 err_msg
= _("unsupported static rounding/sae");
6871 case rc_sae_operand_not_last_imm
:
6873 err_msg
= _("RC/SAE operand must precede immediate operands");
6875 err_msg
= _("RC/SAE operand must follow immediate operands");
6877 case invalid_register_operand
:
6878 err_msg
= _("invalid register operand");
6881 as_bad (_("%s for `%s'"), err_msg
,
6882 current_templates
->start
->name
);
6886 if (!quiet_warnings
)
6889 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6890 as_warn (_("indirect %s without `*'"), t
->name
);
6892 if (t
->opcode_modifier
.isprefix
6893 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6895 /* Warn them that a data or address size prefix doesn't
6896 affect assembly of the next line of code. */
6897 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6901 /* Copy the template we found. */
6902 install_template (t
);
6904 if (addr_prefix_disp
!= -1)
6905 i
.tm
.operand_types
[addr_prefix_disp
]
6906 = operand_types
[addr_prefix_disp
];
6908 if (found_reverse_match
)
6910 /* If we found a reverse match we must alter the opcode direction
6911 bit and clear/flip the regmem modifier one. found_reverse_match
6912 holds bits to change (different for int & float insns). */
6914 i
.tm
.base_opcode
^= found_reverse_match
;
6916 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6917 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6919 /* Certain SIMD insns have their load forms specified in the opcode
6920 table, and hence we need to _set_ RegMem instead of clearing it.
6921 We need to avoid setting the bit though on insns like KMOVW. */
6922 i
.tm
.opcode_modifier
.regmem
6923 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6924 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6925 && !i
.tm
.opcode_modifier
.regmem
;
6934 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6935 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6937 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
6939 as_bad (_("`%s' operand %u must use `%ses' segment"),
6941 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6946 /* There's only ever one segment override allowed per instruction.
6947 This instruction possibly has a legal segment override on the
6948 second operand, so copy the segment to where non-string
6949 instructions store it, allowing common code. */
6950 i
.seg
[op
] = i
.seg
[1];
6956 process_suffix (void)
6958 bool is_crc32
= false, is_movx
= false;
6960 /* If matched instruction specifies an explicit instruction mnemonic
6962 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6963 i
.suffix
= WORD_MNEM_SUFFIX
;
6964 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6965 i
.suffix
= LONG_MNEM_SUFFIX
;
6966 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6967 i
.suffix
= QWORD_MNEM_SUFFIX
;
6968 else if (i
.reg_operands
6969 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6970 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6972 unsigned int numop
= i
.operands
;
6975 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
6976 && (i
.tm
.base_opcode
| 8) == 0xbe)
6977 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6978 && i
.tm
.base_opcode
== 0x63
6979 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
6982 is_crc32
= (i
.tm
.base_opcode
== 0xf0
6983 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
6984 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6986 /* movsx/movzx want only their source operand considered here, for the
6987 ambiguity checking below. The suffix will be replaced afterwards
6988 to represent the destination (register). */
6989 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
6992 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6993 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6996 /* If there's no instruction mnemonic suffix we try to invent one
6997 based on GPR operands. */
7000 /* We take i.suffix from the last register operand specified,
7001 Destination register type is more significant than source
7002 register type. crc32 in SSE4.2 prefers source register
7004 unsigned int op
= is_crc32
? 1 : i
.operands
;
7007 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7008 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7010 if (i
.types
[op
].bitfield
.class != Reg
)
7012 if (i
.types
[op
].bitfield
.byte
)
7013 i
.suffix
= BYTE_MNEM_SUFFIX
;
7014 else if (i
.types
[op
].bitfield
.word
)
7015 i
.suffix
= WORD_MNEM_SUFFIX
;
7016 else if (i
.types
[op
].bitfield
.dword
)
7017 i
.suffix
= LONG_MNEM_SUFFIX
;
7018 else if (i
.types
[op
].bitfield
.qword
)
7019 i
.suffix
= QWORD_MNEM_SUFFIX
;
7025 /* As an exception, movsx/movzx silently default to a byte source
7027 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7028 i
.suffix
= BYTE_MNEM_SUFFIX
;
7030 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7033 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7034 && i
.tm
.opcode_modifier
.no_bsuf
)
7036 else if (!check_byte_reg ())
7039 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7042 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7043 && i
.tm
.opcode_modifier
.no_lsuf
7044 && !i
.tm
.opcode_modifier
.todword
7045 && !i
.tm
.opcode_modifier
.toqword
)
7047 else if (!check_long_reg ())
7050 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7053 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7054 && i
.tm
.opcode_modifier
.no_qsuf
7055 && !i
.tm
.opcode_modifier
.todword
7056 && !i
.tm
.opcode_modifier
.toqword
)
7058 else if (!check_qword_reg ())
7061 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7064 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7065 && i
.tm
.opcode_modifier
.no_wsuf
)
7067 else if (!check_word_reg ())
7070 else if (intel_syntax
7071 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7072 /* Do nothing if the instruction is going to ignore the prefix. */
7077 /* Undo the movsx/movzx change done above. */
7080 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7083 i
.suffix
= stackop_size
;
7084 if (stackop_size
== LONG_MNEM_SUFFIX
)
7086 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7087 .code16gcc directive to support 16-bit mode with
7088 32-bit address. For IRET without a suffix, generate
7089 16-bit IRET (opcode 0xcf) to return from an interrupt
7091 if (i
.tm
.base_opcode
== 0xcf)
7093 i
.suffix
= WORD_MNEM_SUFFIX
;
7094 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7096 /* Warn about changed behavior for segment register push/pop. */
7097 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7098 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7103 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7104 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7105 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7106 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7107 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7108 && i
.tm
.extension_opcode
<= 3)))
7113 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7115 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7116 || i
.tm
.opcode_modifier
.no_lsuf
)
7117 i
.suffix
= QWORD_MNEM_SUFFIX
;
7122 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7123 i
.suffix
= LONG_MNEM_SUFFIX
;
7126 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7127 i
.suffix
= WORD_MNEM_SUFFIX
;
7133 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7134 /* Also cover lret/retf/iret in 64-bit mode. */
7135 || (flag_code
== CODE_64BIT
7136 && !i
.tm
.opcode_modifier
.no_lsuf
7137 && !i
.tm
.opcode_modifier
.no_qsuf
))
7138 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7139 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7140 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7141 /* Accept FLDENV et al without suffix. */
7142 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7144 unsigned int suffixes
, evex
= 0;
7146 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7147 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7149 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7151 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
7153 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7155 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7158 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7159 also suitable for AT&T syntax mode, it was requested that this be
7160 restricted to just Intel syntax. */
7161 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
.type
)
7165 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7167 if (is_evex_encoding (&i
.tm
)
7168 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7170 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7171 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7172 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7173 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7174 if (!i
.tm
.opcode_modifier
.evex
7175 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7176 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7179 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7180 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7181 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7184 /* Any properly sized operand disambiguates the insn. */
7185 if (i
.types
[op
].bitfield
.xmmword
7186 || i
.types
[op
].bitfield
.ymmword
7187 || i
.types
[op
].bitfield
.zmmword
)
7189 suffixes
&= ~(7 << 6);
7194 if ((i
.flags
[op
] & Operand_Mem
)
7195 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7197 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7199 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7201 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7203 if (is_evex_encoding (&i
.tm
))
7209 /* Are multiple suffixes / operand sizes allowed? */
7210 if (suffixes
& (suffixes
- 1))
7213 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7214 || operand_check
== check_error
))
7216 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7219 if (operand_check
== check_error
)
7221 as_bad (_("no instruction mnemonic suffix given and "
7222 "no register operands; can't size `%s'"), i
.tm
.name
);
7225 if (operand_check
== check_warning
)
7226 as_warn (_("%s; using default for `%s'"),
7228 ? _("ambiguous operand size")
7229 : _("no instruction mnemonic suffix given and "
7230 "no register operands"),
7233 if (i
.tm
.opcode_modifier
.floatmf
)
7234 i
.suffix
= SHORT_MNEM_SUFFIX
;
7236 /* handled below */;
7238 i
.tm
.opcode_modifier
.evex
= evex
;
7239 else if (flag_code
== CODE_16BIT
)
7240 i
.suffix
= WORD_MNEM_SUFFIX
;
7241 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7242 i
.suffix
= LONG_MNEM_SUFFIX
;
7244 i
.suffix
= QWORD_MNEM_SUFFIX
;
7250 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7251 In AT&T syntax, if there is no suffix (warned about above), the default
7252 will be byte extension. */
7253 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7254 i
.tm
.base_opcode
|= 1;
7256 /* For further processing, the suffix should represent the destination
7257 (register). This is already the case when one was used with
7258 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7259 no suffix to begin with. */
7260 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7262 if (i
.types
[1].bitfield
.word
)
7263 i
.suffix
= WORD_MNEM_SUFFIX
;
7264 else if (i
.types
[1].bitfield
.qword
)
7265 i
.suffix
= QWORD_MNEM_SUFFIX
;
7267 i
.suffix
= LONG_MNEM_SUFFIX
;
7269 i
.tm
.opcode_modifier
.w
= 0;
7273 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7274 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7275 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7277 /* Change the opcode based on the operand size given by i.suffix. */
7280 /* Size floating point instruction. */
7281 case LONG_MNEM_SUFFIX
:
7282 if (i
.tm
.opcode_modifier
.floatmf
)
7284 i
.tm
.base_opcode
^= 4;
7288 case WORD_MNEM_SUFFIX
:
7289 case QWORD_MNEM_SUFFIX
:
7290 /* It's not a byte, select word/dword operation. */
7291 if (i
.tm
.opcode_modifier
.w
)
7294 i
.tm
.base_opcode
|= 8;
7296 i
.tm
.base_opcode
|= 1;
7299 case SHORT_MNEM_SUFFIX
:
7300 /* Now select between word & dword operations via the operand
7301 size prefix, except for instructions that will ignore this
7303 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7304 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7305 && !i
.tm
.opcode_modifier
.floatmf
7306 && !is_any_vex_encoding (&i
.tm
)
7307 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7308 || (flag_code
== CODE_64BIT
7309 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7311 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7313 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7314 prefix
= ADDR_PREFIX_OPCODE
;
7316 if (!add_prefix (prefix
))
7320 /* Set mode64 for an operand. */
7321 if (i
.suffix
== QWORD_MNEM_SUFFIX
7322 && flag_code
== CODE_64BIT
7323 && !i
.tm
.opcode_modifier
.norex64
7324 && !i
.tm
.opcode_modifier
.vexw
7325 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7327 && ! (i
.operands
== 2
7328 && i
.tm
.base_opcode
== 0x90
7329 && i
.tm
.extension_opcode
== None
7330 && i
.types
[0].bitfield
.instance
== Accum
7331 && i
.types
[0].bitfield
.qword
7332 && i
.types
[1].bitfield
.instance
== Accum
7333 && i
.types
[1].bitfield
.qword
))
7339 /* Select word/dword/qword operation with explicit data sizing prefix
7340 when there are no suitable register operands. */
7341 if (i
.tm
.opcode_modifier
.w
7342 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7344 || (i
.reg_operands
== 1
7346 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7348 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7349 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7352 i
.tm
.base_opcode
|= 1;
7356 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7358 gas_assert (!i
.suffix
);
7359 gas_assert (i
.reg_operands
);
7361 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7364 /* The address size override prefix changes the size of the
7366 if (flag_code
== CODE_64BIT
7367 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7369 as_bad (_("16-bit addressing unavailable for `%s'"),
7374 if ((flag_code
== CODE_32BIT
7375 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7376 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7377 && !add_prefix (ADDR_PREFIX_OPCODE
))
7382 /* Check invalid register operand when the address size override
7383 prefix changes the size of register operands. */
7385 enum { need_word
, need_dword
, need_qword
} need
;
7387 /* Check the register operand for the address size prefix if
7388 the memory operand has no real registers, like symbol, DISP
7389 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7390 if (i
.mem_operands
== 1
7391 && i
.reg_operands
== 1
7393 && i
.types
[1].bitfield
.class == Reg
7394 && (flag_code
== CODE_32BIT
7395 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7396 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7397 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7398 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7399 || (x86_elf_abi
== X86_64_X32_ABI
7401 && i
.base_reg
->reg_num
== RegIP
7402 && i
.base_reg
->reg_type
.bitfield
.qword
))
7406 && !add_prefix (ADDR_PREFIX_OPCODE
))
7409 if (flag_code
== CODE_32BIT
)
7410 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7411 else if (i
.prefix
[ADDR_PREFIX
])
7414 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7416 for (op
= 0; op
< i
.operands
; op
++)
7418 if (i
.types
[op
].bitfield
.class != Reg
)
7424 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7428 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7432 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7437 as_bad (_("invalid register operand size for `%s'"),
7448 check_byte_reg (void)
7452 for (op
= i
.operands
; --op
>= 0;)
7454 /* Skip non-register operands. */
7455 if (i
.types
[op
].bitfield
.class != Reg
)
7458 /* If this is an eight bit register, it's OK. If it's the 16 or
7459 32 bit version of an eight bit register, we will just use the
7460 low portion, and that's OK too. */
7461 if (i
.types
[op
].bitfield
.byte
)
7464 /* I/O port address operands are OK too. */
7465 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7466 && i
.tm
.operand_types
[op
].bitfield
.word
)
7469 /* crc32 only wants its source operand checked here. */
7470 if (i
.tm
.base_opcode
== 0xf0
7471 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7472 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7476 /* Any other register is bad. */
7477 as_bad (_("`%s%s' not allowed with `%s%c'"),
7478 register_prefix
, i
.op
[op
].regs
->reg_name
,
7479 i
.tm
.name
, i
.suffix
);
7486 check_long_reg (void)
7490 for (op
= i
.operands
; --op
>= 0;)
7491 /* Skip non-register operands. */
7492 if (i
.types
[op
].bitfield
.class != Reg
)
7494 /* Reject eight bit registers, except where the template requires
7495 them. (eg. movzb) */
7496 else if (i
.types
[op
].bitfield
.byte
7497 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7498 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7499 && (i
.tm
.operand_types
[op
].bitfield
.word
7500 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7502 as_bad (_("`%s%s' not allowed with `%s%c'"),
7504 i
.op
[op
].regs
->reg_name
,
7509 /* Error if the e prefix on a general reg is missing. */
7510 else if (i
.types
[op
].bitfield
.word
7511 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7512 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7513 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7515 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7516 register_prefix
, i
.op
[op
].regs
->reg_name
,
7520 /* Warn if the r prefix on a general reg is present. */
7521 else if (i
.types
[op
].bitfield
.qword
7522 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7523 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7524 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7527 && i
.tm
.opcode_modifier
.toqword
7528 && i
.types
[0].bitfield
.class != RegSIMD
)
7530 /* Convert to QWORD. We want REX byte. */
7531 i
.suffix
= QWORD_MNEM_SUFFIX
;
7535 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7536 register_prefix
, i
.op
[op
].regs
->reg_name
,
7545 check_qword_reg (void)
7549 for (op
= i
.operands
; --op
>= 0; )
7550 /* Skip non-register operands. */
7551 if (i
.types
[op
].bitfield
.class != Reg
)
7553 /* Reject eight bit registers, except where the template requires
7554 them. (eg. movzb) */
7555 else if (i
.types
[op
].bitfield
.byte
7556 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7557 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7558 && (i
.tm
.operand_types
[op
].bitfield
.word
7559 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7561 as_bad (_("`%s%s' not allowed with `%s%c'"),
7563 i
.op
[op
].regs
->reg_name
,
7568 /* Warn if the r prefix on a general reg is missing. */
7569 else if ((i
.types
[op
].bitfield
.word
7570 || i
.types
[op
].bitfield
.dword
)
7571 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7572 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7573 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7575 /* Prohibit these changes in the 64bit mode, since the
7576 lowering is more complicated. */
7578 && i
.tm
.opcode_modifier
.todword
7579 && i
.types
[0].bitfield
.class != RegSIMD
)
7581 /* Convert to DWORD. We don't want REX byte. */
7582 i
.suffix
= LONG_MNEM_SUFFIX
;
7586 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7587 register_prefix
, i
.op
[op
].regs
->reg_name
,
7596 check_word_reg (void)
7599 for (op
= i
.operands
; --op
>= 0;)
7600 /* Skip non-register operands. */
7601 if (i
.types
[op
].bitfield
.class != Reg
)
7603 /* Reject eight bit registers, except where the template requires
7604 them. (eg. movzb) */
7605 else if (i
.types
[op
].bitfield
.byte
7606 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7607 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7608 && (i
.tm
.operand_types
[op
].bitfield
.word
7609 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7611 as_bad (_("`%s%s' not allowed with `%s%c'"),
7613 i
.op
[op
].regs
->reg_name
,
7618 /* Error if the e or r prefix on a general reg is present. */
7619 else if ((i
.types
[op
].bitfield
.dword
7620 || i
.types
[op
].bitfield
.qword
)
7621 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7622 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7623 && i
.tm
.operand_types
[op
].bitfield
.word
)
7625 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7626 register_prefix
, i
.op
[op
].regs
->reg_name
,
7634 update_imm (unsigned int j
)
7636 i386_operand_type overlap
= i
.types
[j
];
7637 if ((overlap
.bitfield
.imm8
7638 || overlap
.bitfield
.imm8s
7639 || overlap
.bitfield
.imm16
7640 || overlap
.bitfield
.imm32
7641 || overlap
.bitfield
.imm32s
7642 || overlap
.bitfield
.imm64
)
7643 && !operand_type_equal (&overlap
, &imm8
)
7644 && !operand_type_equal (&overlap
, &imm8s
)
7645 && !operand_type_equal (&overlap
, &imm16
)
7646 && !operand_type_equal (&overlap
, &imm32
)
7647 && !operand_type_equal (&overlap
, &imm32s
)
7648 && !operand_type_equal (&overlap
, &imm64
))
7652 i386_operand_type temp
;
7654 operand_type_set (&temp
, 0);
7655 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7657 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7658 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7660 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7661 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7662 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7664 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7665 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7668 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7671 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7672 || operand_type_equal (&overlap
, &imm16_32
)
7673 || operand_type_equal (&overlap
, &imm16_32s
))
7675 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7680 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7681 overlap
= operand_type_and (overlap
, imm32s
);
7682 else if (i
.prefix
[DATA_PREFIX
])
7683 overlap
= operand_type_and (overlap
,
7684 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7685 if (!operand_type_equal (&overlap
, &imm8
)
7686 && !operand_type_equal (&overlap
, &imm8s
)
7687 && !operand_type_equal (&overlap
, &imm16
)
7688 && !operand_type_equal (&overlap
, &imm32
)
7689 && !operand_type_equal (&overlap
, &imm32s
)
7690 && !operand_type_equal (&overlap
, &imm64
))
7692 as_bad (_("no instruction mnemonic suffix given; "
7693 "can't determine immediate size"));
7697 i
.types
[j
] = overlap
;
7707 /* Update the first 2 immediate operands. */
7708 n
= i
.operands
> 2 ? 2 : i
.operands
;
7711 for (j
= 0; j
< n
; j
++)
7712 if (update_imm (j
) == 0)
7715 /* The 3rd operand can't be immediate operand. */
7716 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7723 process_operands (void)
7725 /* Default segment register this instruction will use for memory
7726 accesses. 0 means unknown. This is only for optimizing out
7727 unnecessary segment overrides. */
7728 const reg_entry
*default_seg
= NULL
;
7730 if (i
.tm
.opcode_modifier
.sse2avx
)
7732 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7734 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7735 i
.prefix
[REX_PREFIX
] = 0;
7738 /* ImmExt should be processed after SSE2AVX. */
7739 else if (i
.tm
.opcode_modifier
.immext
)
7742 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7744 unsigned int dupl
= i
.operands
;
7745 unsigned int dest
= dupl
- 1;
7748 /* The destination must be an xmm register. */
7749 gas_assert (i
.reg_operands
7750 && MAX_OPERANDS
> dupl
7751 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7753 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7754 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7756 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7758 /* Keep xmm0 for instructions with VEX prefix and 3
7760 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7761 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7766 /* We remove the first xmm0 and keep the number of
7767 operands unchanged, which in fact duplicates the
7769 for (j
= 1; j
< i
.operands
; j
++)
7771 i
.op
[j
- 1] = i
.op
[j
];
7772 i
.types
[j
- 1] = i
.types
[j
];
7773 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7774 i
.flags
[j
- 1] = i
.flags
[j
];
7778 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7780 gas_assert ((MAX_OPERANDS
- 1) > dupl
7781 && (i
.tm
.opcode_modifier
.vexsources
7784 /* Add the implicit xmm0 for instructions with VEX prefix
7786 for (j
= i
.operands
; j
> 0; j
--)
7788 i
.op
[j
] = i
.op
[j
- 1];
7789 i
.types
[j
] = i
.types
[j
- 1];
7790 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7791 i
.flags
[j
] = i
.flags
[j
- 1];
7794 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7795 i
.types
[0] = regxmm
;
7796 i
.tm
.operand_types
[0] = regxmm
;
7799 i
.reg_operands
+= 2;
7804 i
.op
[dupl
] = i
.op
[dest
];
7805 i
.types
[dupl
] = i
.types
[dest
];
7806 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7807 i
.flags
[dupl
] = i
.flags
[dest
];
7816 i
.op
[dupl
] = i
.op
[dest
];
7817 i
.types
[dupl
] = i
.types
[dest
];
7818 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7819 i
.flags
[dupl
] = i
.flags
[dest
];
7822 if (i
.tm
.opcode_modifier
.immext
)
7825 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7826 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7830 for (j
= 1; j
< i
.operands
; j
++)
7832 i
.op
[j
- 1] = i
.op
[j
];
7833 i
.types
[j
- 1] = i
.types
[j
];
7835 /* We need to adjust fields in i.tm since they are used by
7836 build_modrm_byte. */
7837 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7839 i
.flags
[j
- 1] = i
.flags
[j
];
7846 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7848 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7850 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7851 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7852 regnum
= register_number (i
.op
[1].regs
);
7853 first_reg_in_group
= regnum
& ~3;
7854 last_reg_in_group
= first_reg_in_group
+ 3;
7855 if (regnum
!= first_reg_in_group
)
7856 as_warn (_("source register `%s%s' implicitly denotes"
7857 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7858 register_prefix
, i
.op
[1].regs
->reg_name
,
7859 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7860 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7863 else if (i
.tm
.opcode_modifier
.regkludge
)
7865 /* The imul $imm, %reg instruction is converted into
7866 imul $imm, %reg, %reg, and the clr %reg instruction
7867 is converted into xor %reg, %reg. */
7869 unsigned int first_reg_op
;
7871 if (operand_type_check (i
.types
[0], reg
))
7875 /* Pretend we saw the extra register operand. */
7876 gas_assert (i
.reg_operands
== 1
7877 && i
.op
[first_reg_op
+ 1].regs
== 0);
7878 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7879 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7884 if (i
.tm
.opcode_modifier
.modrm
)
7886 /* The opcode is completed (modulo i.tm.extension_opcode which
7887 must be put into the modrm byte). Now, we make the modrm and
7888 index base bytes based on all the info we've collected. */
7890 default_seg
= build_modrm_byte ();
7892 else if (i
.types
[0].bitfield
.class == SReg
)
7894 if (flag_code
!= CODE_64BIT
7895 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7896 && i
.op
[0].regs
->reg_num
== 1
7897 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
7898 && i
.op
[0].regs
->reg_num
< 4)
7900 as_bad (_("you can't `%s %s%s'"),
7901 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7904 if (i
.op
[0].regs
->reg_num
> 3
7905 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
7907 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
7908 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
7910 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7912 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7913 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
7915 default_seg
= reg_ds
;
7917 else if (i
.tm
.opcode_modifier
.isstring
)
7919 /* For the string instructions that allow a segment override
7920 on one of their operands, the default segment is ds. */
7921 default_seg
= reg_ds
;
7923 else if (i
.short_form
)
7925 /* The register or float register operand is in operand
7927 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7929 /* Register goes in low 3 bits of opcode. */
7930 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7931 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7933 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7935 /* Warn about some common errors, but press on regardless.
7936 The first case can be generated by gcc (<= 2.8.1). */
7937 if (i
.operands
== 2)
7939 /* Reversed arguments on faddp, fsubp, etc. */
7940 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7941 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7942 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7946 /* Extraneous `l' suffix on fp insn. */
7947 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7948 register_prefix
, i
.op
[0].regs
->reg_name
);
7953 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7954 && i
.tm
.base_opcode
== 0x8d /* lea */
7955 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7956 && !is_any_vex_encoding(&i
.tm
))
7958 if (!quiet_warnings
)
7959 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7963 i
.prefix
[SEG_PREFIX
] = 0;
7967 /* If a segment was explicitly specified, and the specified segment
7968 is neither the default nor the one already recorded from a prefix,
7969 use an opcode prefix to select it. If we never figured out what
7970 the default segment is, then default_seg will be zero at this
7971 point, and the specified segment prefix will always be used. */
7973 && i
.seg
[0] != default_seg
7974 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
7976 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
7982 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7985 if (r
->reg_flags
& RegRex
)
7987 if (i
.rex
& rex_bit
)
7988 as_bad (_("same type of prefix used twice"));
7991 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7993 gas_assert (i
.vex
.register_specifier
== r
);
7994 i
.vex
.register_specifier
+= 8;
7997 if (r
->reg_flags
& RegVRex
)
8001 static const reg_entry
*
8002 build_modrm_byte (void)
8004 const reg_entry
*default_seg
= NULL
;
8005 unsigned int source
, dest
;
8008 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8011 unsigned int nds
, reg_slot
;
8014 dest
= i
.operands
- 1;
8017 /* There are 2 kinds of instructions:
8018 1. 5 operands: 4 register operands or 3 register operands
8019 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8020 VexW0 or VexW1. The destination must be either XMM, YMM or
8022 2. 4 operands: 4 register operands or 3 register operands
8023 plus 1 memory operand, with VexXDS. */
8024 gas_assert ((i
.reg_operands
== 4
8025 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8026 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8027 && i
.tm
.opcode_modifier
.vexw
8028 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8030 /* If VexW1 is set, the first non-immediate operand is the source and
8031 the second non-immediate one is encoded in the immediate operand. */
8032 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8034 source
= i
.imm_operands
;
8035 reg_slot
= i
.imm_operands
+ 1;
8039 source
= i
.imm_operands
+ 1;
8040 reg_slot
= i
.imm_operands
;
8043 if (i
.imm_operands
== 0)
8045 /* When there is no immediate operand, generate an 8bit
8046 immediate operand to encode the first operand. */
8047 exp
= &im_expressions
[i
.imm_operands
++];
8048 i
.op
[i
.operands
].imms
= exp
;
8049 i
.types
[i
.operands
] = imm8
;
8052 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8053 exp
->X_op
= O_constant
;
8054 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8055 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8059 gas_assert (i
.imm_operands
== 1);
8060 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8061 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8063 /* Turn on Imm8 again so that output_imm will generate it. */
8064 i
.types
[0].bitfield
.imm8
= 1;
8066 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8067 i
.op
[0].imms
->X_add_number
8068 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8069 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8072 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8073 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8078 /* i.reg_operands MUST be the number of real register operands;
8079 implicit registers do not count. If there are 3 register
8080 operands, it must be a instruction with VexNDS. For a
8081 instruction with VexNDD, the destination register is encoded
8082 in VEX prefix. If there are 4 register operands, it must be
8083 a instruction with VEX prefix and 3 sources. */
8084 if (i
.mem_operands
== 0
8085 && ((i
.reg_operands
== 2
8086 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8087 || (i
.reg_operands
== 3
8088 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8089 || (i
.reg_operands
== 4 && vex_3_sources
)))
8097 /* When there are 3 operands, one of them may be immediate,
8098 which may be the first or the last operand. Otherwise,
8099 the first operand must be shift count register (cl) or it
8100 is an instruction with VexNDS. */
8101 gas_assert (i
.imm_operands
== 1
8102 || (i
.imm_operands
== 0
8103 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8104 || (i
.types
[0].bitfield
.instance
== RegC
8105 && i
.types
[0].bitfield
.byte
))));
8106 if (operand_type_check (i
.types
[0], imm
)
8107 || (i
.types
[0].bitfield
.instance
== RegC
8108 && i
.types
[0].bitfield
.byte
))
8114 /* When there are 4 operands, the first two must be 8bit
8115 immediate operands. The source operand will be the 3rd
8118 For instructions with VexNDS, if the first operand
8119 an imm8, the source operand is the 2nd one. If the last
8120 operand is imm8, the source operand is the first one. */
8121 gas_assert ((i
.imm_operands
== 2
8122 && i
.types
[0].bitfield
.imm8
8123 && i
.types
[1].bitfield
.imm8
)
8124 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8125 && i
.imm_operands
== 1
8126 && (i
.types
[0].bitfield
.imm8
8127 || i
.types
[i
.operands
- 1].bitfield
.imm8
8128 || i
.rounding
.type
!= rc_none
)));
8129 if (i
.imm_operands
== 2)
8133 if (i
.types
[0].bitfield
.imm8
)
8140 if (is_evex_encoding (&i
.tm
))
8142 /* For EVEX instructions, when there are 5 operands, the
8143 first one must be immediate operand. If the second one
8144 is immediate operand, the source operand is the 3th
8145 one. If the last one is immediate operand, the source
8146 operand is the 2nd one. */
8147 gas_assert (i
.imm_operands
== 2
8148 && i
.tm
.opcode_modifier
.sae
8149 && operand_type_check (i
.types
[0], imm
));
8150 if (operand_type_check (i
.types
[1], imm
))
8152 else if (operand_type_check (i
.types
[4], imm
))
8166 /* RC/SAE operand could be between DEST and SRC. That happens
8167 when one operand is GPR and the other one is XMM/YMM/ZMM
8169 if (i
.rounding
.type
!= rc_none
&& i
.rounding
.operand
== dest
)
8172 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8174 /* For instructions with VexNDS, the register-only source
8175 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8176 register. It is encoded in VEX prefix. */
8178 i386_operand_type op
;
8181 /* Swap two source operands if needed. */
8182 if (i
.tm
.opcode_modifier
.swapsources
)
8190 op
= i
.tm
.operand_types
[vvvv
];
8191 if ((dest
+ 1) >= i
.operands
8192 || ((op
.bitfield
.class != Reg
8193 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8194 && op
.bitfield
.class != RegSIMD
8195 && !operand_type_equal (&op
, ®mask
)))
8197 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8203 /* One of the register operands will be encoded in the i.rm.reg
8204 field, the other in the combined i.rm.mode and i.rm.regmem
8205 fields. If no form of this instruction supports a memory
8206 destination operand, then we assume the source operand may
8207 sometimes be a memory operand and so we need to store the
8208 destination in the i.rm.reg field. */
8209 if (!i
.tm
.opcode_modifier
.regmem
8210 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8212 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8213 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8214 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8215 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8219 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8220 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8221 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8222 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8224 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8226 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8229 add_prefix (LOCK_PREFIX_OPCODE
);
8233 { /* If it's not 2 reg operands... */
8238 unsigned int fake_zero_displacement
= 0;
8241 for (op
= 0; op
< i
.operands
; op
++)
8242 if (i
.flags
[op
] & Operand_Mem
)
8244 gas_assert (op
< i
.operands
);
8246 if (i
.tm
.opcode_modifier
.sib
)
8248 /* The index register of VSIB shouldn't be RegIZ. */
8249 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8250 && i
.index_reg
->reg_num
== RegIZ
)
8253 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8256 i
.sib
.base
= NO_BASE_REGISTER
;
8257 i
.sib
.scale
= i
.log2_scale_factor
;
8258 i
.types
[op
].bitfield
.disp8
= 0;
8259 i
.types
[op
].bitfield
.disp16
= 0;
8260 i
.types
[op
].bitfield
.disp64
= 0;
8261 if (want_disp32 (&i
.tm
))
8263 /* Must be 32 bit */
8264 i
.types
[op
].bitfield
.disp32
= 1;
8265 i
.types
[op
].bitfield
.disp32s
= 0;
8269 i
.types
[op
].bitfield
.disp32
= 0;
8270 i
.types
[op
].bitfield
.disp32s
= 1;
8274 /* Since the mandatory SIB always has index register, so
8275 the code logic remains unchanged. The non-mandatory SIB
8276 without index register is allowed and will be handled
8280 if (i
.index_reg
->reg_num
== RegIZ
)
8281 i
.sib
.index
= NO_INDEX_REGISTER
;
8283 i
.sib
.index
= i
.index_reg
->reg_num
;
8284 set_rex_vrex (i
.index_reg
, REX_X
, false);
8288 default_seg
= reg_ds
;
8290 if (i
.base_reg
== 0)
8293 if (!i
.disp_operands
)
8294 fake_zero_displacement
= 1;
8295 if (i
.index_reg
== 0)
8297 i386_operand_type newdisp
;
8299 /* Both check for VSIB and mandatory non-vector SIB. */
8300 gas_assert (!i
.tm
.opcode_modifier
.sib
8301 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8302 /* Operand is just <disp> */
8303 if (flag_code
== CODE_64BIT
)
8305 /* 64bit mode overwrites the 32bit absolute
8306 addressing by RIP relative addressing and
8307 absolute addressing is encoded by one of the
8308 redundant SIB forms. */
8309 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8310 i
.sib
.base
= NO_BASE_REGISTER
;
8311 i
.sib
.index
= NO_INDEX_REGISTER
;
8312 newdisp
= (want_disp32(&i
.tm
) ? disp32
: disp32s
);
8314 else if ((flag_code
== CODE_16BIT
)
8315 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8317 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8322 i
.rm
.regmem
= NO_BASE_REGISTER
;
8325 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8326 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8328 else if (!i
.tm
.opcode_modifier
.sib
)
8330 /* !i.base_reg && i.index_reg */
8331 if (i
.index_reg
->reg_num
== RegIZ
)
8332 i
.sib
.index
= NO_INDEX_REGISTER
;
8334 i
.sib
.index
= i
.index_reg
->reg_num
;
8335 i
.sib
.base
= NO_BASE_REGISTER
;
8336 i
.sib
.scale
= i
.log2_scale_factor
;
8337 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8338 i
.types
[op
].bitfield
.disp8
= 0;
8339 i
.types
[op
].bitfield
.disp16
= 0;
8340 i
.types
[op
].bitfield
.disp64
= 0;
8341 if (want_disp32 (&i
.tm
))
8343 /* Must be 32 bit */
8344 i
.types
[op
].bitfield
.disp32
= 1;
8345 i
.types
[op
].bitfield
.disp32s
= 0;
8349 i
.types
[op
].bitfield
.disp32
= 0;
8350 i
.types
[op
].bitfield
.disp32s
= 1;
8352 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8356 /* RIP addressing for 64bit mode. */
8357 else if (i
.base_reg
->reg_num
== RegIP
)
8359 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8360 i
.rm
.regmem
= NO_BASE_REGISTER
;
8361 i
.types
[op
].bitfield
.disp8
= 0;
8362 i
.types
[op
].bitfield
.disp16
= 0;
8363 i
.types
[op
].bitfield
.disp32
= 0;
8364 i
.types
[op
].bitfield
.disp32s
= 1;
8365 i
.types
[op
].bitfield
.disp64
= 0;
8366 i
.flags
[op
] |= Operand_PCrel
;
8367 if (! i
.disp_operands
)
8368 fake_zero_displacement
= 1;
8370 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8372 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8373 switch (i
.base_reg
->reg_num
)
8376 if (i
.index_reg
== 0)
8378 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8379 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8382 default_seg
= reg_ss
;
8383 if (i
.index_reg
== 0)
8386 if (operand_type_check (i
.types
[op
], disp
) == 0)
8388 /* fake (%bp) into 0(%bp) */
8389 if (i
.disp_encoding
== disp_encoding_16bit
)
8390 i
.types
[op
].bitfield
.disp16
= 1;
8392 i
.types
[op
].bitfield
.disp8
= 1;
8393 fake_zero_displacement
= 1;
8396 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8397 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8399 default: /* (%si) -> 4 or (%di) -> 5 */
8400 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8402 if (!fake_zero_displacement
8406 fake_zero_displacement
= 1;
8407 if (i
.disp_encoding
== disp_encoding_8bit
)
8408 i
.types
[op
].bitfield
.disp8
= 1;
8410 i
.types
[op
].bitfield
.disp16
= 1;
8412 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8414 else /* i.base_reg and 32/64 bit mode */
8416 if (operand_type_check (i
.types
[op
], disp
))
8418 i
.types
[op
].bitfield
.disp16
= 0;
8419 i
.types
[op
].bitfield
.disp64
= 0;
8420 if (!want_disp32 (&i
.tm
))
8422 i
.types
[op
].bitfield
.disp32
= 0;
8423 i
.types
[op
].bitfield
.disp32s
= 1;
8427 i
.types
[op
].bitfield
.disp32
= 1;
8428 i
.types
[op
].bitfield
.disp32s
= 0;
8432 if (!i
.tm
.opcode_modifier
.sib
)
8433 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8434 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8436 i
.sib
.base
= i
.base_reg
->reg_num
;
8437 /* x86-64 ignores REX prefix bit here to avoid decoder
8439 if (!(i
.base_reg
->reg_flags
& RegRex
)
8440 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8441 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8442 default_seg
= reg_ss
;
8443 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8445 fake_zero_displacement
= 1;
8446 if (i
.disp_encoding
== disp_encoding_32bit
)
8447 i
.types
[op
].bitfield
.disp32
= 1;
8449 i
.types
[op
].bitfield
.disp8
= 1;
8451 i
.sib
.scale
= i
.log2_scale_factor
;
8452 if (i
.index_reg
== 0)
8454 /* Only check for VSIB. */
8455 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8456 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8457 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8459 /* <disp>(%esp) becomes two byte modrm with no index
8460 register. We've already stored the code for esp
8461 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8462 Any base register besides %esp will not use the
8463 extra modrm byte. */
8464 i
.sib
.index
= NO_INDEX_REGISTER
;
8466 else if (!i
.tm
.opcode_modifier
.sib
)
8468 if (i
.index_reg
->reg_num
== RegIZ
)
8469 i
.sib
.index
= NO_INDEX_REGISTER
;
8471 i
.sib
.index
= i
.index_reg
->reg_num
;
8472 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8473 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8478 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8479 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8483 if (!fake_zero_displacement
8487 fake_zero_displacement
= 1;
8488 if (i
.disp_encoding
== disp_encoding_8bit
)
8489 i
.types
[op
].bitfield
.disp8
= 1;
8491 i
.types
[op
].bitfield
.disp32
= 1;
8493 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8497 if (fake_zero_displacement
)
8499 /* Fakes a zero displacement assuming that i.types[op]
8500 holds the correct displacement size. */
8503 gas_assert (i
.op
[op
].disps
== 0);
8504 exp
= &disp_expressions
[i
.disp_operands
++];
8505 i
.op
[op
].disps
= exp
;
8506 exp
->X_op
= O_constant
;
8507 exp
->X_add_number
= 0;
8508 exp
->X_add_symbol
= (symbolS
*) 0;
8509 exp
->X_op_symbol
= (symbolS
*) 0;
8517 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8519 if (operand_type_check (i
.types
[0], imm
))
8520 i
.vex
.register_specifier
= NULL
;
8523 /* VEX.vvvv encodes one of the sources when the first
8524 operand is not an immediate. */
8525 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8526 i
.vex
.register_specifier
= i
.op
[0].regs
;
8528 i
.vex
.register_specifier
= i
.op
[1].regs
;
8531 /* Destination is a XMM register encoded in the ModRM.reg
8533 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8534 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8537 /* ModRM.rm and VEX.B encodes the other source. */
8538 if (!i
.mem_operands
)
8542 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8543 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8545 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8547 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8551 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8553 i
.vex
.register_specifier
= i
.op
[2].regs
;
8554 if (!i
.mem_operands
)
8557 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8558 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8562 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8563 (if any) based on i.tm.extension_opcode. Again, we must be
8564 careful to make sure that segment/control/debug/test/MMX
8565 registers are coded into the i.rm.reg field. */
8566 else if (i
.reg_operands
)
8569 unsigned int vex_reg
= ~0;
8571 for (op
= 0; op
< i
.operands
; op
++)
8572 if (i
.types
[op
].bitfield
.class == Reg
8573 || i
.types
[op
].bitfield
.class == RegBND
8574 || i
.types
[op
].bitfield
.class == RegMask
8575 || i
.types
[op
].bitfield
.class == SReg
8576 || i
.types
[op
].bitfield
.class == RegCR
8577 || i
.types
[op
].bitfield
.class == RegDR
8578 || i
.types
[op
].bitfield
.class == RegTR
8579 || i
.types
[op
].bitfield
.class == RegSIMD
8580 || i
.types
[op
].bitfield
.class == RegMMX
)
8585 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8587 /* For instructions with VexNDS, the register-only
8588 source operand is encoded in VEX prefix. */
8589 gas_assert (mem
!= (unsigned int) ~0);
8594 gas_assert (op
< i
.operands
);
8598 /* Check register-only source operand when two source
8599 operands are swapped. */
8600 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8601 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8605 gas_assert (mem
== (vex_reg
+ 1)
8606 && op
< i
.operands
);
8611 gas_assert (vex_reg
< i
.operands
);
8615 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8617 /* For instructions with VexNDD, the register destination
8618 is encoded in VEX prefix. */
8619 if (i
.mem_operands
== 0)
8621 /* There is no memory operand. */
8622 gas_assert ((op
+ 2) == i
.operands
);
8627 /* There are only 2 non-immediate operands. */
8628 gas_assert (op
< i
.imm_operands
+ 2
8629 && i
.operands
== i
.imm_operands
+ 2);
8630 vex_reg
= i
.imm_operands
+ 1;
8634 gas_assert (op
< i
.operands
);
8636 if (vex_reg
!= (unsigned int) ~0)
8638 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8640 if ((type
->bitfield
.class != Reg
8641 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8642 && type
->bitfield
.class != RegSIMD
8643 && !operand_type_equal (type
, ®mask
))
8646 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8649 /* Don't set OP operand twice. */
8652 /* If there is an extension opcode to put here, the
8653 register number must be put into the regmem field. */
8654 if (i
.tm
.extension_opcode
!= None
)
8656 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8657 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8658 i
.tm
.opcode_modifier
.sse2avx
);
8662 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8663 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8664 i
.tm
.opcode_modifier
.sse2avx
);
8668 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8669 must set it to 3 to indicate this is a register operand
8670 in the regmem field. */
8671 if (!i
.mem_operands
)
8675 /* Fill in i.rm.reg field with extension opcode (if any). */
8676 if (i
.tm
.extension_opcode
!= None
)
8677 i
.rm
.reg
= i
.tm
.extension_opcode
;
8683 frag_opcode_byte (unsigned char byte
)
8685 if (now_seg
!= absolute_section
)
8686 FRAG_APPEND_1_CHAR (byte
);
8688 ++abs_section_offset
;
8692 flip_code16 (unsigned int code16
)
8694 gas_assert (i
.tm
.operands
== 1);
8696 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8697 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8698 || i
.tm
.operand_types
[0].bitfield
.disp32s
8699 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8704 output_branch (void)
8710 relax_substateT subtype
;
8714 if (now_seg
== absolute_section
)
8716 as_bad (_("relaxable branches not supported in absolute section"));
8720 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8721 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8724 if (i
.prefix
[DATA_PREFIX
] != 0)
8728 code16
^= flip_code16(code16
);
8730 /* Pentium4 branch hints. */
8731 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8732 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8737 if (i
.prefix
[REX_PREFIX
] != 0)
8743 /* BND prefixed jump. */
8744 if (i
.prefix
[BND_PREFIX
] != 0)
8750 if (i
.prefixes
!= 0)
8751 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8753 /* It's always a symbol; End frag & setup for relax.
8754 Make sure there is enough room in this frag for the largest
8755 instruction we may generate in md_convert_frag. This is 2
8756 bytes for the opcode and room for the prefix and largest
8758 frag_grow (prefix
+ 2 + 4);
8759 /* Prefix and 1 opcode byte go in fr_fix. */
8760 p
= frag_more (prefix
+ 1);
8761 if (i
.prefix
[DATA_PREFIX
] != 0)
8762 *p
++ = DATA_PREFIX_OPCODE
;
8763 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8764 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8765 *p
++ = i
.prefix
[SEG_PREFIX
];
8766 if (i
.prefix
[BND_PREFIX
] != 0)
8767 *p
++ = BND_PREFIX_OPCODE
;
8768 if (i
.prefix
[REX_PREFIX
] != 0)
8769 *p
++ = i
.prefix
[REX_PREFIX
];
8770 *p
= i
.tm
.base_opcode
;
8772 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8773 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8774 else if (cpu_arch_flags
.bitfield
.cpui386
)
8775 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8777 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8780 sym
= i
.op
[0].disps
->X_add_symbol
;
8781 off
= i
.op
[0].disps
->X_add_number
;
8783 if (i
.op
[0].disps
->X_op
!= O_constant
8784 && i
.op
[0].disps
->X_op
!= O_symbol
)
8786 /* Handle complex expressions. */
8787 sym
= make_expr_symbol (i
.op
[0].disps
);
8791 /* 1 possible extra opcode + 4 byte displacement go in var part.
8792 Pass reloc in fr_var. */
8793 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8797 /* Return TRUE iff PLT32 relocation should be used for branching to
8801 need_plt32_p (symbolS
*s
)
8803 /* PLT32 relocation is ELF only. */
8808 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8809 krtld support it. */
8813 /* Since there is no need to prepare for PLT branch on x86-64, we
8814 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8815 be used as a marker for 32-bit PC-relative branches. */
8822 /* Weak or undefined symbol need PLT32 relocation. */
8823 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8826 /* Non-global symbol doesn't need PLT32 relocation. */
8827 if (! S_IS_EXTERNAL (s
))
8830 /* Other global symbols need PLT32 relocation. NB: Symbol with
8831 non-default visibilities are treated as normal global symbol
8832 so that PLT32 relocation can be used as a marker for 32-bit
8833 PC-relative branches. It is useful for linker relaxation. */
8844 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8846 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8848 /* This is a loop or jecxz type instruction. */
8850 if (i
.prefix
[ADDR_PREFIX
] != 0)
8852 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8855 /* Pentium4 branch hints. */
8856 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8857 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8859 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8868 if (flag_code
== CODE_16BIT
)
8871 if (i
.prefix
[DATA_PREFIX
] != 0)
8873 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8875 code16
^= flip_code16(code16
);
8883 /* BND prefixed jump. */
8884 if (i
.prefix
[BND_PREFIX
] != 0)
8886 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8890 if (i
.prefix
[REX_PREFIX
] != 0)
8892 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8896 if (i
.prefixes
!= 0)
8897 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8899 if (now_seg
== absolute_section
)
8901 abs_section_offset
+= i
.opcode_length
+ size
;
8905 p
= frag_more (i
.opcode_length
+ size
);
8906 switch (i
.opcode_length
)
8909 *p
++ = i
.tm
.base_opcode
>> 8;
8912 *p
++ = i
.tm
.base_opcode
;
8918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8920 && jump_reloc
== NO_RELOC
8921 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8922 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8925 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8927 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8928 i
.op
[0].disps
, 1, jump_reloc
);
8930 /* All jumps handled here are signed, but don't unconditionally use a
8931 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8932 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8937 fixP
->fx_signed
= 1;
8941 if (i
.tm
.base_opcode
== 0xc7f8)
8942 fixP
->fx_signed
= 1;
8946 if (flag_code
== CODE_64BIT
)
8947 fixP
->fx_signed
= 1;
8953 output_interseg_jump (void)
8961 if (flag_code
== CODE_16BIT
)
8965 if (i
.prefix
[DATA_PREFIX
] != 0)
8972 gas_assert (!i
.prefix
[REX_PREFIX
]);
8978 if (i
.prefixes
!= 0)
8979 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8981 if (now_seg
== absolute_section
)
8983 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8987 /* 1 opcode; 2 segment; offset */
8988 p
= frag_more (prefix
+ 1 + 2 + size
);
8990 if (i
.prefix
[DATA_PREFIX
] != 0)
8991 *p
++ = DATA_PREFIX_OPCODE
;
8993 if (i
.prefix
[REX_PREFIX
] != 0)
8994 *p
++ = i
.prefix
[REX_PREFIX
];
8996 *p
++ = i
.tm
.base_opcode
;
8997 if (i
.op
[1].imms
->X_op
== O_constant
)
8999 offsetT n
= i
.op
[1].imms
->X_add_number
;
9002 && !fits_in_unsigned_word (n
)
9003 && !fits_in_signed_word (n
))
9005 as_bad (_("16-bit jump out of range"));
9008 md_number_to_chars (p
, n
, size
);
9011 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9012 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9015 if (i
.op
[0].imms
->X_op
== O_constant
)
9016 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9019 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9022 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9027 asection
*seg
= now_seg
;
9028 subsegT subseg
= now_subseg
;
9030 unsigned int alignment
, align_size_1
;
9031 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9032 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9033 unsigned int padding
;
9035 if (!IS_ELF
|| !x86_used_note
)
9038 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9040 /* The .note.gnu.property section layout:
9042 Field Length Contents
9045 n_descsz 4 The note descriptor size
9046 n_type 4 NT_GNU_PROPERTY_TYPE_0
9048 n_desc n_descsz The program property array
9052 /* Create the .note.gnu.property section. */
9053 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9054 bfd_set_section_flags (sec
,
9061 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9072 bfd_set_section_alignment (sec
, alignment
);
9073 elf_section_type (sec
) = SHT_NOTE
;
9075 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9077 isa_1_descsz_raw
= 4 + 4 + 4;
9078 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9079 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9081 feature_2_descsz_raw
= isa_1_descsz
;
9082 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9084 feature_2_descsz_raw
+= 4 + 4 + 4;
9085 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9086 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9089 descsz
= feature_2_descsz
;
9090 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9091 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9093 /* Write n_namsz. */
9094 md_number_to_chars (p
, (valueT
) 4, 4);
9096 /* Write n_descsz. */
9097 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9100 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9103 memcpy (p
+ 4 * 3, "GNU", 4);
9105 /* Write 4-byte type. */
9106 md_number_to_chars (p
+ 4 * 4,
9107 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9109 /* Write 4-byte data size. */
9110 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9112 /* Write 4-byte data. */
9113 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9115 /* Zero out paddings. */
9116 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9118 memset (p
+ 4 * 7, 0, padding
);
9120 /* Write 4-byte type. */
9121 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9122 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9124 /* Write 4-byte data size. */
9125 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9127 /* Write 4-byte data. */
9128 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9129 (valueT
) x86_feature_2_used
, 4);
9131 /* Zero out paddings. */
9132 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9134 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9136 /* We probably can't restore the current segment, for there likely
9139 subseg_set (seg
, subseg
);
9144 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9145 const char *frag_now_ptr
)
9147 unsigned int len
= 0;
9149 if (start_frag
!= frag_now
)
9151 const fragS
*fr
= start_frag
;
9156 } while (fr
&& fr
!= frag_now
);
9159 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9162 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9163 be macro-fused with conditional jumps.
9164 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9165 or is one of the following format:
9178 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9180 /* No RIP address. */
9181 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9184 /* No opcodes outside of base encoding space. */
9185 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9188 /* add, sub without add/sub m, imm. */
9189 if (i
.tm
.base_opcode
<= 5
9190 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9191 || ((i
.tm
.base_opcode
| 3) == 0x83
9192 && (i
.tm
.extension_opcode
== 0x5
9193 || i
.tm
.extension_opcode
== 0x0)))
9195 *mf_cmp_p
= mf_cmp_alu_cmp
;
9196 return !(i
.mem_operands
&& i
.imm_operands
);
9199 /* and without and m, imm. */
9200 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9201 || ((i
.tm
.base_opcode
| 3) == 0x83
9202 && i
.tm
.extension_opcode
== 0x4))
9204 *mf_cmp_p
= mf_cmp_test_and
;
9205 return !(i
.mem_operands
&& i
.imm_operands
);
9208 /* test without test m imm. */
9209 if ((i
.tm
.base_opcode
| 1) == 0x85
9210 || (i
.tm
.base_opcode
| 1) == 0xa9
9211 || ((i
.tm
.base_opcode
| 1) == 0xf7
9212 && i
.tm
.extension_opcode
== 0))
9214 *mf_cmp_p
= mf_cmp_test_and
;
9215 return !(i
.mem_operands
&& i
.imm_operands
);
9218 /* cmp without cmp m, imm. */
9219 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9220 || ((i
.tm
.base_opcode
| 3) == 0x83
9221 && (i
.tm
.extension_opcode
== 0x7)))
9223 *mf_cmp_p
= mf_cmp_alu_cmp
;
9224 return !(i
.mem_operands
&& i
.imm_operands
);
9227 /* inc, dec without inc/dec m. */
9228 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9229 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9230 || ((i
.tm
.base_opcode
| 1) == 0xff
9231 && i
.tm
.extension_opcode
<= 0x1))
9233 *mf_cmp_p
= mf_cmp_incdec
;
9234 return !i
.mem_operands
;
9240 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9243 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9245 /* NB: Don't work with COND_JUMP86 without i386. */
9246 if (!align_branch_power
9247 || now_seg
== absolute_section
9248 || !cpu_arch_flags
.bitfield
.cpui386
9249 || !(align_branch
& align_branch_fused_bit
))
9252 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9254 if (last_insn
.kind
== last_insn_other
9255 || last_insn
.seg
!= now_seg
)
9258 as_warn_where (last_insn
.file
, last_insn
.line
,
9259 _("`%s` skips -malign-branch-boundary on `%s`"),
9260 last_insn
.name
, i
.tm
.name
);
9266 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9269 add_branch_prefix_frag_p (void)
9271 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9272 to PadLock instructions since they include prefixes in opcode. */
9273 if (!align_branch_power
9274 || !align_branch_prefix_size
9275 || now_seg
== absolute_section
9276 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9277 || !cpu_arch_flags
.bitfield
.cpui386
)
9280 /* Don't add prefix if it is a prefix or there is no operand in case
9281 that segment prefix is special. */
9282 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9285 if (last_insn
.kind
== last_insn_other
9286 || last_insn
.seg
!= now_seg
)
9290 as_warn_where (last_insn
.file
, last_insn
.line
,
9291 _("`%s` skips -malign-branch-boundary on `%s`"),
9292 last_insn
.name
, i
.tm
.name
);
9297 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9300 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9301 enum mf_jcc_kind
*mf_jcc_p
)
9305 /* NB: Don't work with COND_JUMP86 without i386. */
9306 if (!align_branch_power
9307 || now_seg
== absolute_section
9308 || !cpu_arch_flags
.bitfield
.cpui386
9309 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9314 /* Check for jcc and direct jmp. */
9315 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9317 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9319 *branch_p
= align_branch_jmp
;
9320 add_padding
= align_branch
& align_branch_jmp_bit
;
9324 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9325 igore the lowest bit. */
9326 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9327 *branch_p
= align_branch_jcc
;
9328 if ((align_branch
& align_branch_jcc_bit
))
9332 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9335 *branch_p
= align_branch_ret
;
9336 if ((align_branch
& align_branch_ret_bit
))
9341 /* Check for indirect jmp, direct and indirect calls. */
9342 if (i
.tm
.base_opcode
== 0xe8)
9345 *branch_p
= align_branch_call
;
9346 if ((align_branch
& align_branch_call_bit
))
9349 else if (i
.tm
.base_opcode
== 0xff
9350 && (i
.tm
.extension_opcode
== 2
9351 || i
.tm
.extension_opcode
== 4))
9353 /* Indirect call and jmp. */
9354 *branch_p
= align_branch_indirect
;
9355 if ((align_branch
& align_branch_indirect_bit
))
9362 && (i
.op
[0].disps
->X_op
== O_symbol
9363 || (i
.op
[0].disps
->X_op
== O_subtract
9364 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9366 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9367 /* No padding to call to global or undefined tls_get_addr. */
9368 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9369 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9375 && last_insn
.kind
!= last_insn_other
9376 && last_insn
.seg
== now_seg
)
9379 as_warn_where (last_insn
.file
, last_insn
.line
,
9380 _("`%s` skips -malign-branch-boundary on `%s`"),
9381 last_insn
.name
, i
.tm
.name
);
9391 fragS
*insn_start_frag
;
9392 offsetT insn_start_off
;
9393 fragS
*fragP
= NULL
;
9394 enum align_branch_kind branch
= align_branch_none
;
9395 /* The initializer is arbitrary just to avoid uninitialized error.
9396 it's actually either assigned in add_branch_padding_frag_p
9397 or never be used. */
9398 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9401 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9403 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9404 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9405 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9407 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9408 || i
.tm
.cpu_flags
.bitfield
.cpu287
9409 || i
.tm
.cpu_flags
.bitfield
.cpu387
9410 || i
.tm
.cpu_flags
.bitfield
.cpu687
9411 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9412 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9414 if ((i
.xstate
& xstate_mmx
)
9415 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9416 && !is_any_vex_encoding (&i
.tm
)
9417 && (i
.tm
.base_opcode
== 0x77 /* emms */
9418 || i
.tm
.base_opcode
== 0x0e /* femms */)))
9419 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9423 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9424 i
.xstate
|= xstate_zmm
;
9425 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9426 i
.xstate
|= xstate_ymm
;
9427 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9428 i
.xstate
|= xstate_xmm
;
9431 /* vzeroall / vzeroupper */
9432 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9433 i
.xstate
|= xstate_ymm
;
9435 if ((i
.xstate
& xstate_xmm
)
9436 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9437 || (i
.tm
.base_opcode
== 0xae
9438 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9439 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9440 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9441 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9442 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9444 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9445 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9446 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9447 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9448 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9449 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9450 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9451 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9452 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9453 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9454 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9455 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9456 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9457 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9459 if (x86_feature_2_used
9460 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9461 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9462 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9463 && i
.tm
.base_opcode
== 0xc7
9464 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9465 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9466 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9467 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9468 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9469 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9470 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9471 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9472 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9473 /* LAHF-SAHF insns in 64-bit mode. */
9474 || (flag_code
== CODE_64BIT
9475 && (i
.tm
.base_opcode
| 1) == 0x9f
9476 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9477 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9478 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9479 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9480 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9481 CpuAVX512DQ, LPW, TBM and AMX. */
9482 || (i
.tm
.opcode_modifier
.vex
9483 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9484 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9485 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9486 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9487 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9488 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9489 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9490 || i
.tm
.cpu_flags
.bitfield
.cpufma
9491 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9492 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9493 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9494 || (x86_feature_2_used
9495 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9496 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9497 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9498 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9499 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9500 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9501 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9502 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9503 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9505 || (i
.tm
.opcode_modifier
.evex
9506 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9507 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9508 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9509 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9513 /* Tie dwarf2 debug info to the address at the start of the insn.
9514 We can't do this after the insn has been output as the current
9515 frag may have been closed off. eg. by frag_var. */
9516 dwarf2_emit_insn (0);
9518 insn_start_frag
= frag_now
;
9519 insn_start_off
= frag_now_fix ();
9521 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9524 /* Branch can be 8 bytes. Leave some room for prefixes. */
9525 unsigned int max_branch_padding_size
= 14;
9527 /* Align section to boundary. */
9528 record_alignment (now_seg
, align_branch_power
);
9530 /* Make room for padding. */
9531 frag_grow (max_branch_padding_size
);
9533 /* Start of the padding. */
9538 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9539 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9542 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9543 fragP
->tc_frag_data
.branch_type
= branch
;
9544 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9548 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9550 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9551 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9553 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9554 output_interseg_jump ();
9557 /* Output normal instructions here. */
9561 enum mf_cmp_kind mf_cmp
;
9564 && (i
.tm
.base_opcode
== 0xaee8
9565 || i
.tm
.base_opcode
== 0xaef0
9566 || i
.tm
.base_opcode
== 0xaef8))
9568 /* Encode lfence, mfence, and sfence as
9569 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9570 if (now_seg
!= absolute_section
)
9572 offsetT val
= 0x240483f0ULL
;
9575 md_number_to_chars (p
, val
, 5);
9578 abs_section_offset
+= 5;
9582 /* Some processors fail on LOCK prefix. This options makes
9583 assembler ignore LOCK prefix and serves as a workaround. */
9584 if (omit_lock_prefix
)
9586 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9587 && i
.tm
.opcode_modifier
.isprefix
)
9589 i
.prefix
[LOCK_PREFIX
] = 0;
9593 /* Skip if this is a branch. */
9595 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9597 /* Make room for padding. */
9598 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9603 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9604 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9607 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9608 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9609 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9611 else if (add_branch_prefix_frag_p ())
9613 unsigned int max_prefix_size
= align_branch_prefix_size
;
9615 /* Make room for padding. */
9616 frag_grow (max_prefix_size
);
9621 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9622 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9625 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9628 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9629 don't need the explicit prefix. */
9630 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9632 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9641 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9642 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9646 switch (i
.opcode_length
)
9651 /* Check for pseudo prefixes. */
9652 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9654 as_bad_where (insn_start_frag
->fr_file
,
9655 insn_start_frag
->fr_line
,
9656 _("pseudo prefix without instruction"));
9666 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9667 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9668 R_X86_64_GOTTPOFF relocation so that linker can safely
9669 perform IE->LE optimization. A dummy REX_OPCODE prefix
9670 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9671 relocation for GDesc -> IE/LE optimization. */
9672 if (x86_elf_abi
== X86_64_X32_ABI
9674 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9675 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9676 && i
.prefix
[REX_PREFIX
] == 0)
9677 add_prefix (REX_OPCODE
);
9680 /* The prefix bytes. */
9681 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9683 frag_opcode_byte (*q
);
9687 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9693 frag_opcode_byte (*q
);
9696 /* There should be no other prefixes for instructions
9701 /* For EVEX instructions i.vrex should become 0 after
9702 build_evex_prefix. For VEX instructions upper 16 registers
9703 aren't available, so VREX should be 0. */
9706 /* Now the VEX prefix. */
9707 if (now_seg
!= absolute_section
)
9709 p
= frag_more (i
.vex
.length
);
9710 for (j
= 0; j
< i
.vex
.length
; j
++)
9711 p
[j
] = i
.vex
.bytes
[j
];
9714 abs_section_offset
+= i
.vex
.length
;
9717 /* Now the opcode; be careful about word order here! */
9718 j
= i
.opcode_length
;
9720 switch (i
.tm
.opcode_modifier
.opcodespace
)
9735 if (now_seg
== absolute_section
)
9736 abs_section_offset
+= j
;
9739 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9745 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9748 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9749 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9753 switch (i
.opcode_length
)
9756 /* Put out high byte first: can't use md_number_to_chars! */
9757 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9760 *p
= i
.tm
.base_opcode
& 0xff;
9769 /* Now the modrm byte and sib byte (if present). */
9770 if (i
.tm
.opcode_modifier
.modrm
)
9772 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9774 | (i
.rm
.mode
<< 6));
9775 /* If i.rm.regmem == ESP (4)
9776 && i.rm.mode != (Register mode)
9778 ==> need second modrm byte. */
9779 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9781 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9782 frag_opcode_byte ((i
.sib
.base
<< 0)
9783 | (i
.sib
.index
<< 3)
9784 | (i
.sib
.scale
<< 6));
9787 if (i
.disp_operands
)
9788 output_disp (insn_start_frag
, insn_start_off
);
9791 output_imm (insn_start_frag
, insn_start_off
);
9794 * frag_now_fix () returning plain abs_section_offset when we're in the
9795 * absolute section, and abs_section_offset not getting updated as data
9796 * gets added to the frag breaks the logic below.
9798 if (now_seg
!= absolute_section
)
9800 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9802 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9806 /* NB: Don't add prefix with GOTPC relocation since
9807 output_disp() above depends on the fixed encoding
9808 length. Can't add prefix with TLS relocation since
9809 it breaks TLS linker optimization. */
9810 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9811 /* Prefix count on the current instruction. */
9812 unsigned int count
= i
.vex
.length
;
9814 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9815 /* REX byte is encoded in VEX/EVEX prefix. */
9816 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9819 /* Count prefixes for extended opcode maps. */
9821 switch (i
.tm
.opcode_modifier
.opcodespace
)
9836 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9839 /* Set the maximum prefix size in BRANCH_PREFIX
9841 if (fragP
->tc_frag_data
.max_bytes
> max
)
9842 fragP
->tc_frag_data
.max_bytes
= max
;
9843 if (fragP
->tc_frag_data
.max_bytes
> count
)
9844 fragP
->tc_frag_data
.max_bytes
-= count
;
9846 fragP
->tc_frag_data
.max_bytes
= 0;
9850 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9852 unsigned int max_prefix_size
;
9853 if (align_branch_prefix_size
> max
)
9854 max_prefix_size
= max
;
9856 max_prefix_size
= align_branch_prefix_size
;
9857 if (max_prefix_size
> count
)
9858 fragP
->tc_frag_data
.max_prefix_length
9859 = max_prefix_size
- count
;
9862 /* Use existing segment prefix if possible. Use CS
9863 segment prefix in 64-bit mode. In 32-bit mode, use SS
9864 segment prefix with ESP/EBP base register and use DS
9865 segment prefix without ESP/EBP base register. */
9866 if (i
.prefix
[SEG_PREFIX
])
9867 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9868 else if (flag_code
== CODE_64BIT
)
9869 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9871 && (i
.base_reg
->reg_num
== 4
9872 || i
.base_reg
->reg_num
== 5))
9873 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9875 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9880 /* NB: Don't work with COND_JUMP86 without i386. */
9881 if (align_branch_power
9882 && now_seg
!= absolute_section
9883 && cpu_arch_flags
.bitfield
.cpui386
)
9885 /* Terminate each frag so that we can add prefix and check for
9887 frag_wane (frag_now
);
9894 pi ("" /*line*/, &i
);
9896 #endif /* DEBUG386 */
9899 /* Return the size of the displacement operand N. */
9902 disp_size (unsigned int n
)
9906 if (i
.types
[n
].bitfield
.disp64
)
9908 else if (i
.types
[n
].bitfield
.disp8
)
9910 else if (i
.types
[n
].bitfield
.disp16
)
9915 /* Return the size of the immediate operand N. */
9918 imm_size (unsigned int n
)
9921 if (i
.types
[n
].bitfield
.imm64
)
9923 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9925 else if (i
.types
[n
].bitfield
.imm16
)
9931 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9936 for (n
= 0; n
< i
.operands
; n
++)
9938 if (operand_type_check (i
.types
[n
], disp
))
9940 int size
= disp_size (n
);
9942 if (now_seg
== absolute_section
)
9943 abs_section_offset
+= size
;
9944 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9946 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9948 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9950 p
= frag_more (size
);
9951 md_number_to_chars (p
, val
, size
);
9955 enum bfd_reloc_code_real reloc_type
;
9956 int sign
= i
.types
[n
].bitfield
.disp32s
;
9957 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9960 /* We can't have 8 bit displacement here. */
9961 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9963 /* The PC relative address is computed relative
9964 to the instruction boundary, so in case immediate
9965 fields follows, we need to adjust the value. */
9966 if (pcrel
&& i
.imm_operands
)
9971 for (n1
= 0; n1
< i
.operands
; n1
++)
9972 if (operand_type_check (i
.types
[n1
], imm
))
9974 /* Only one immediate is allowed for PC
9975 relative address. */
9976 gas_assert (sz
== 0);
9978 i
.op
[n
].disps
->X_add_number
-= sz
;
9980 /* We should find the immediate. */
9981 gas_assert (sz
!= 0);
9984 p
= frag_more (size
);
9985 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9987 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9988 && (((reloc_type
== BFD_RELOC_32
9989 || reloc_type
== BFD_RELOC_X86_64_32S
9990 || (reloc_type
== BFD_RELOC_64
9992 && (i
.op
[n
].disps
->X_op
== O_symbol
9993 || (i
.op
[n
].disps
->X_op
== O_add
9994 && ((symbol_get_value_expression
9995 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9997 || reloc_type
== BFD_RELOC_32_PCREL
))
10001 reloc_type
= BFD_RELOC_386_GOTPC
;
10002 i
.has_gotpc_tls_reloc
= true;
10003 i
.op
[n
].disps
->X_add_number
+=
10004 encoding_length (insn_start_frag
, insn_start_off
, p
);
10006 else if (reloc_type
== BFD_RELOC_64
)
10007 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10009 /* Don't do the adjustment for x86-64, as there
10010 the pcrel addressing is relative to the _next_
10011 insn, and that is taken care of in other code. */
10012 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10014 else if (align_branch_power
)
10016 switch (reloc_type
)
10018 case BFD_RELOC_386_TLS_GD
:
10019 case BFD_RELOC_386_TLS_LDM
:
10020 case BFD_RELOC_386_TLS_IE
:
10021 case BFD_RELOC_386_TLS_IE_32
:
10022 case BFD_RELOC_386_TLS_GOTIE
:
10023 case BFD_RELOC_386_TLS_GOTDESC
:
10024 case BFD_RELOC_386_TLS_DESC_CALL
:
10025 case BFD_RELOC_X86_64_TLSGD
:
10026 case BFD_RELOC_X86_64_TLSLD
:
10027 case BFD_RELOC_X86_64_GOTTPOFF
:
10028 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10029 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10030 i
.has_gotpc_tls_reloc
= true;
10035 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10036 size
, i
.op
[n
].disps
, pcrel
,
10039 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10040 && !i
.prefix
[ADDR_PREFIX
])
10041 fixP
->fx_signed
= 1;
10043 /* Check for "call/jmp *mem", "mov mem, %reg",
10044 "test %reg, mem" and "binop mem, %reg" where binop
10045 is one of adc, add, and, cmp, or, sbb, sub, xor
10046 instructions without data prefix. Always generate
10047 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10048 if (i
.prefix
[DATA_PREFIX
] == 0
10049 && (generate_relax_relocations
10052 && i
.rm
.regmem
== 5))
10054 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10055 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10056 && ((i
.operands
== 1
10057 && i
.tm
.base_opcode
== 0xff
10058 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10059 || (i
.operands
== 2
10060 && (i
.tm
.base_opcode
== 0x8b
10061 || i
.tm
.base_opcode
== 0x85
10062 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10066 fixP
->fx_tcbit
= i
.rex
!= 0;
10068 && (i
.base_reg
->reg_num
== RegIP
))
10069 fixP
->fx_tcbit2
= 1;
10072 fixP
->fx_tcbit2
= 1;
10080 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10085 for (n
= 0; n
< i
.operands
; n
++)
10087 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
10088 if (i
.rounding
.type
!= rc_none
&& n
== i
.rounding
.operand
)
10091 if (operand_type_check (i
.types
[n
], imm
))
10093 int size
= imm_size (n
);
10095 if (now_seg
== absolute_section
)
10096 abs_section_offset
+= size
;
10097 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10101 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10103 p
= frag_more (size
);
10104 md_number_to_chars (p
, val
, size
);
10108 /* Not absolute_section.
10109 Need a 32-bit fixup (don't support 8bit
10110 non-absolute imms). Try to support other
10112 enum bfd_reloc_code_real reloc_type
;
10115 if (i
.types
[n
].bitfield
.imm32s
10116 && (i
.suffix
== QWORD_MNEM_SUFFIX
10117 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10122 p
= frag_more (size
);
10123 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10125 /* This is tough to explain. We end up with this one if we
10126 * have operands that look like
10127 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10128 * obtain the absolute address of the GOT, and it is strongly
10129 * preferable from a performance point of view to avoid using
10130 * a runtime relocation for this. The actual sequence of
10131 * instructions often look something like:
10136 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10138 * The call and pop essentially return the absolute address
10139 * of the label .L66 and store it in %ebx. The linker itself
10140 * will ultimately change the first operand of the addl so
10141 * that %ebx points to the GOT, but to keep things simple, the
10142 * .o file must have this operand set so that it generates not
10143 * the absolute address of .L66, but the absolute address of
10144 * itself. This allows the linker itself simply treat a GOTPC
10145 * relocation as asking for a pcrel offset to the GOT to be
10146 * added in, and the addend of the relocation is stored in the
10147 * operand field for the instruction itself.
10149 * Our job here is to fix the operand so that it would add
10150 * the correct offset so that %ebx would point to itself. The
10151 * thing that is tricky is that .-.L66 will point to the
10152 * beginning of the instruction, so we need to further modify
10153 * the operand so that it will point to itself. There are
10154 * other cases where you have something like:
10156 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10158 * and here no correction would be required. Internally in
10159 * the assembler we treat operands of this form as not being
10160 * pcrel since the '.' is explicitly mentioned, and I wonder
10161 * whether it would simplify matters to do it this way. Who
10162 * knows. In earlier versions of the PIC patches, the
10163 * pcrel_adjust field was used to store the correction, but
10164 * since the expression is not pcrel, I felt it would be
10165 * confusing to do it this way. */
10167 if ((reloc_type
== BFD_RELOC_32
10168 || reloc_type
== BFD_RELOC_X86_64_32S
10169 || reloc_type
== BFD_RELOC_64
)
10171 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10172 && (i
.op
[n
].imms
->X_op
== O_symbol
10173 || (i
.op
[n
].imms
->X_op
== O_add
10174 && ((symbol_get_value_expression
10175 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10179 reloc_type
= BFD_RELOC_386_GOTPC
;
10180 else if (size
== 4)
10181 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10182 else if (size
== 8)
10183 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10184 i
.has_gotpc_tls_reloc
= true;
10185 i
.op
[n
].imms
->X_add_number
+=
10186 encoding_length (insn_start_frag
, insn_start_off
, p
);
10188 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10189 i
.op
[n
].imms
, 0, reloc_type
);
10195 /* x86_cons_fix_new is called via the expression parsing code when a
10196 reloc is needed. We use this hook to get the correct .got reloc. */
10197 static int cons_sign
= -1;
10200 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10201 expressionS
*exp
, bfd_reloc_code_real_type r
)
10203 r
= reloc (len
, 0, cons_sign
, r
);
10206 if (exp
->X_op
== O_secrel
)
10208 exp
->X_op
= O_symbol
;
10209 r
= BFD_RELOC_32_SECREL
;
10213 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10216 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10217 purpose of the `.dc.a' internal pseudo-op. */
10220 x86_address_bytes (void)
10222 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10224 return stdoutput
->arch_info
->bits_per_address
/ 8;
10227 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10228 || defined (LEX_AT)) && !defined (TE_PE)
10229 # define lex_got(reloc, adjust, types) NULL
10231 /* Parse operands of the form
10232 <symbol>@GOTOFF+<nnn>
10233 and similar .plt or .got references.
10235 If we find one, set up the correct relocation in RELOC and copy the
10236 input string, minus the `@GOTOFF' into a malloc'd buffer for
10237 parsing by the calling routine. Return this buffer, and if ADJUST
10238 is non-null set it to the length of the string we removed from the
10239 input line. Otherwise return NULL. */
10241 lex_got (enum bfd_reloc_code_real
*rel
,
10243 i386_operand_type
*types
)
10245 /* Some of the relocations depend on the size of what field is to
10246 be relocated. But in our callers i386_immediate and i386_displacement
10247 we don't yet know the operand size (this will be set by insn
10248 matching). Hence we record the word32 relocation here,
10249 and adjust the reloc according to the real size in reloc(). */
10250 static const struct {
10253 const enum bfd_reloc_code_real rel
[2];
10254 const i386_operand_type types64
;
10255 bool need_GOT_symbol
;
10258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10259 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10260 BFD_RELOC_SIZE32
},
10261 OPERAND_TYPE_IMM32_64
, false },
10263 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10264 BFD_RELOC_X86_64_PLTOFF64
},
10265 OPERAND_TYPE_IMM64
, true },
10266 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10267 BFD_RELOC_X86_64_PLT32
},
10268 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10269 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10270 BFD_RELOC_X86_64_GOTPLT64
},
10271 OPERAND_TYPE_IMM64_DISP64
, true },
10272 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10273 BFD_RELOC_X86_64_GOTOFF64
},
10274 OPERAND_TYPE_IMM64_DISP64
, true },
10275 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10276 BFD_RELOC_X86_64_GOTPCREL
},
10277 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10278 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10279 BFD_RELOC_X86_64_TLSGD
},
10280 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10281 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10282 _dummy_first_bfd_reloc_code_real
},
10283 OPERAND_TYPE_NONE
, true },
10284 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10285 BFD_RELOC_X86_64_TLSLD
},
10286 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10287 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10288 BFD_RELOC_X86_64_GOTTPOFF
},
10289 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10290 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10291 BFD_RELOC_X86_64_TPOFF32
},
10292 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10293 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10294 _dummy_first_bfd_reloc_code_real
},
10295 OPERAND_TYPE_NONE
, true },
10296 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10297 BFD_RELOC_X86_64_DTPOFF32
},
10298 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10299 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10300 _dummy_first_bfd_reloc_code_real
},
10301 OPERAND_TYPE_NONE
, true },
10302 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10303 _dummy_first_bfd_reloc_code_real
},
10304 OPERAND_TYPE_NONE
, true },
10305 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10306 BFD_RELOC_X86_64_GOT32
},
10307 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10308 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10309 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10310 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10311 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10312 BFD_RELOC_X86_64_TLSDESC_CALL
},
10313 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10315 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10316 BFD_RELOC_32_SECREL
},
10317 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10323 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10328 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10329 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10332 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10334 int len
= gotrel
[j
].len
;
10335 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10337 if (gotrel
[j
].rel
[object_64bit
] != 0)
10340 char *tmpbuf
, *past_reloc
;
10342 *rel
= gotrel
[j
].rel
[object_64bit
];
10346 if (flag_code
!= CODE_64BIT
)
10348 types
->bitfield
.imm32
= 1;
10349 types
->bitfield
.disp32
= 1;
10352 *types
= gotrel
[j
].types64
;
10355 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10356 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10358 /* The length of the first part of our input line. */
10359 first
= cp
- input_line_pointer
;
10361 /* The second part goes from after the reloc token until
10362 (and including) an end_of_line char or comma. */
10363 past_reloc
= cp
+ 1 + len
;
10365 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10367 second
= cp
+ 1 - past_reloc
;
10369 /* Allocate and copy string. The trailing NUL shouldn't
10370 be necessary, but be safe. */
10371 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10372 memcpy (tmpbuf
, input_line_pointer
, first
);
10373 if (second
!= 0 && *past_reloc
!= ' ')
10374 /* Replace the relocation token with ' ', so that
10375 errors like foo@GOTOFF1 will be detected. */
10376 tmpbuf
[first
++] = ' ';
10378 /* Increment length by 1 if the relocation token is
10383 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10384 tmpbuf
[first
+ second
] = '\0';
10388 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10389 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10394 /* Might be a symbol version string. Don't as_bad here. */
10399 bfd_reloc_code_real_type
10400 x86_cons (expressionS
*exp
, int size
)
10402 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10404 intel_syntax
= -intel_syntax
;
10407 if (size
== 4 || (object_64bit
&& size
== 8))
10409 /* Handle @GOTOFF and the like in an expression. */
10411 char *gotfree_input_line
;
10414 save
= input_line_pointer
;
10415 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10416 if (gotfree_input_line
)
10417 input_line_pointer
= gotfree_input_line
;
10421 if (gotfree_input_line
)
10423 /* expression () has merrily parsed up to the end of line,
10424 or a comma - in the wrong buffer. Transfer how far
10425 input_line_pointer has moved to the right buffer. */
10426 input_line_pointer
= (save
10427 + (input_line_pointer
- gotfree_input_line
)
10429 free (gotfree_input_line
);
10430 if (exp
->X_op
== O_constant
10431 || exp
->X_op
== O_absent
10432 || exp
->X_op
== O_illegal
10433 || exp
->X_op
== O_register
10434 || exp
->X_op
== O_big
)
10436 char c
= *input_line_pointer
;
10437 *input_line_pointer
= 0;
10438 as_bad (_("missing or invalid expression `%s'"), save
);
10439 *input_line_pointer
= c
;
10441 else if ((got_reloc
== BFD_RELOC_386_PLT32
10442 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10443 && exp
->X_op
!= O_symbol
)
10445 char c
= *input_line_pointer
;
10446 *input_line_pointer
= 0;
10447 as_bad (_("invalid PLT expression `%s'"), save
);
10448 *input_line_pointer
= c
;
10455 intel_syntax
= -intel_syntax
;
10458 i386_intel_simplify (exp
);
10464 signed_cons (int size
)
10466 if (flag_code
== CODE_64BIT
)
10474 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10481 if (exp
.X_op
== O_symbol
)
10482 exp
.X_op
= O_secrel
;
10484 emit_expr (&exp
, 4);
10486 while (*input_line_pointer
++ == ',');
10488 input_line_pointer
--;
10489 demand_empty_rest_of_line ();
10493 /* Handle Vector operations. */
10496 check_VecOperations (char *op_string
, char *op_end
)
10498 const reg_entry
*mask
;
10503 && (op_end
== NULL
|| op_string
< op_end
))
10506 if (*op_string
== '{')
10510 /* Check broadcasts. */
10511 if (startswith (op_string
, "1to"))
10513 unsigned int bcst_type
;
10515 if (i
.broadcast
.type
)
10516 goto duplicated_vec_op
;
10519 if (*op_string
== '8')
10521 else if (*op_string
== '4')
10523 else if (*op_string
== '2')
10525 else if (*op_string
== '1'
10526 && *(op_string
+1) == '6')
10533 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10538 i
.broadcast
.type
= bcst_type
;
10539 i
.broadcast
.operand
= this_operand
;
10541 /* Check masking operation. */
10542 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10544 if (mask
== &bad_reg
)
10547 /* k0 can't be used for write mask. */
10548 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10550 as_bad (_("`%s%s' can't be used for write mask"),
10551 register_prefix
, mask
->reg_name
);
10558 i
.mask
.operand
= this_operand
;
10560 else if (i
.mask
.reg
->reg_num
)
10561 goto duplicated_vec_op
;
10566 /* Only "{z}" is allowed here. No need to check
10567 zeroing mask explicitly. */
10568 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10570 as_bad (_("invalid write mask `%s'"), saved
);
10575 op_string
= end_op
;
10577 /* Check zeroing-flag for masking operation. */
10578 else if (*op_string
== 'z')
10582 i
.mask
.reg
= reg_k0
;
10583 i
.mask
.zeroing
= 1;
10584 i
.mask
.operand
= this_operand
;
10588 if (i
.mask
.zeroing
)
10591 as_bad (_("duplicated `%s'"), saved
);
10595 i
.mask
.zeroing
= 1;
10597 /* Only "{%k}" is allowed here. No need to check mask
10598 register explicitly. */
10599 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10601 as_bad (_("invalid zeroing-masking `%s'"),
10610 goto unknown_vec_op
;
10612 if (*op_string
!= '}')
10614 as_bad (_("missing `}' in `%s'"), saved
);
10619 /* Strip whitespace since the addition of pseudo prefixes
10620 changed how the scrubber treats '{'. */
10621 if (is_space_char (*op_string
))
10627 /* We don't know this one. */
10628 as_bad (_("unknown vector operation: `%s'"), saved
);
10632 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10634 as_bad (_("zeroing-masking only allowed with write mask"));
10642 i386_immediate (char *imm_start
)
10644 char *save_input_line_pointer
;
10645 char *gotfree_input_line
;
10648 i386_operand_type types
;
10650 operand_type_set (&types
, ~0);
10652 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10654 as_bad (_("at most %d immediate operands are allowed"),
10655 MAX_IMMEDIATE_OPERANDS
);
10659 exp
= &im_expressions
[i
.imm_operands
++];
10660 i
.op
[this_operand
].imms
= exp
;
10662 if (is_space_char (*imm_start
))
10665 save_input_line_pointer
= input_line_pointer
;
10666 input_line_pointer
= imm_start
;
10668 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10669 if (gotfree_input_line
)
10670 input_line_pointer
= gotfree_input_line
;
10672 exp_seg
= expression (exp
);
10674 SKIP_WHITESPACE ();
10676 /* Handle vector operations. */
10677 if (*input_line_pointer
== '{')
10679 input_line_pointer
= check_VecOperations (input_line_pointer
,
10681 if (input_line_pointer
== NULL
)
10685 if (*input_line_pointer
)
10686 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10688 input_line_pointer
= save_input_line_pointer
;
10689 if (gotfree_input_line
)
10691 free (gotfree_input_line
);
10693 if (exp
->X_op
== O_constant
)
10694 exp
->X_op
= O_illegal
;
10697 if (exp_seg
== reg_section
)
10699 as_bad (_("illegal immediate register operand %s"), imm_start
);
10703 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10707 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10708 i386_operand_type types
, const char *imm_start
)
10710 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10713 as_bad (_("missing or invalid immediate expression `%s'"),
10717 else if (exp
->X_op
== O_constant
)
10719 /* Size it properly later. */
10720 i
.types
[this_operand
].bitfield
.imm64
= 1;
10721 /* If not 64bit, sign extend val. */
10722 if (flag_code
!= CODE_64BIT
10723 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10725 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10727 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10728 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10729 && exp_seg
!= absolute_section
10730 && exp_seg
!= text_section
10731 && exp_seg
!= data_section
10732 && exp_seg
!= bss_section
10733 && exp_seg
!= undefined_section
10734 && !bfd_is_com_section (exp_seg
))
10736 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10742 /* This is an address. The size of the address will be
10743 determined later, depending on destination register,
10744 suffix, or the default for the section. */
10745 i
.types
[this_operand
].bitfield
.imm8
= 1;
10746 i
.types
[this_operand
].bitfield
.imm16
= 1;
10747 i
.types
[this_operand
].bitfield
.imm32
= 1;
10748 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10749 i
.types
[this_operand
].bitfield
.imm64
= 1;
10750 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10758 i386_scale (char *scale
)
10761 char *save
= input_line_pointer
;
10763 input_line_pointer
= scale
;
10764 val
= get_absolute_expression ();
10769 i
.log2_scale_factor
= 0;
10772 i
.log2_scale_factor
= 1;
10775 i
.log2_scale_factor
= 2;
10778 i
.log2_scale_factor
= 3;
10782 char sep
= *input_line_pointer
;
10784 *input_line_pointer
= '\0';
10785 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10787 *input_line_pointer
= sep
;
10788 input_line_pointer
= save
;
10792 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10794 as_warn (_("scale factor of %d without an index register"),
10795 1 << i
.log2_scale_factor
);
10796 i
.log2_scale_factor
= 0;
10798 scale
= input_line_pointer
;
10799 input_line_pointer
= save
;
10804 i386_displacement (char *disp_start
, char *disp_end
)
10808 char *save_input_line_pointer
;
10809 char *gotfree_input_line
;
10811 i386_operand_type bigdisp
, types
= anydisp
;
10814 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10816 as_bad (_("at most %d displacement operands are allowed"),
10817 MAX_MEMORY_OPERANDS
);
10821 operand_type_set (&bigdisp
, 0);
10823 || i
.types
[this_operand
].bitfield
.baseindex
10824 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10825 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10827 i386_addressing_mode ();
10828 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10829 if (flag_code
== CODE_64BIT
)
10833 bigdisp
.bitfield
.disp32s
= 1;
10834 bigdisp
.bitfield
.disp64
= 1;
10837 bigdisp
.bitfield
.disp32
= 1;
10839 else if ((flag_code
== CODE_16BIT
) ^ override
)
10840 bigdisp
.bitfield
.disp16
= 1;
10842 bigdisp
.bitfield
.disp32
= 1;
10846 /* For PC-relative branches, the width of the displacement may be
10847 dependent upon data size, but is never dependent upon address size.
10848 Also make sure to not unintentionally match against a non-PC-relative
10849 branch template. */
10850 static templates aux_templates
;
10851 const insn_template
*t
= current_templates
->start
;
10852 bool has_intel64
= false;
10854 aux_templates
.start
= t
;
10855 while (++t
< current_templates
->end
)
10857 if (t
->opcode_modifier
.jump
10858 != current_templates
->start
->opcode_modifier
.jump
)
10860 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10861 has_intel64
= true;
10863 if (t
< current_templates
->end
)
10865 aux_templates
.end
= t
;
10866 current_templates
= &aux_templates
;
10869 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10870 if (flag_code
== CODE_64BIT
)
10872 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10873 && (!intel64
|| !has_intel64
))
10874 bigdisp
.bitfield
.disp16
= 1;
10876 bigdisp
.bitfield
.disp32s
= 1;
10881 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10883 : LONG_MNEM_SUFFIX
));
10884 bigdisp
.bitfield
.disp32
= 1;
10885 if ((flag_code
== CODE_16BIT
) ^ override
)
10887 bigdisp
.bitfield
.disp32
= 0;
10888 bigdisp
.bitfield
.disp16
= 1;
10892 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10895 exp
= &disp_expressions
[i
.disp_operands
];
10896 i
.op
[this_operand
].disps
= exp
;
10898 save_input_line_pointer
= input_line_pointer
;
10899 input_line_pointer
= disp_start
;
10900 END_STRING_AND_SAVE (disp_end
);
10902 #ifndef GCC_ASM_O_HACK
10903 #define GCC_ASM_O_HACK 0
10906 END_STRING_AND_SAVE (disp_end
+ 1);
10907 if (i
.types
[this_operand
].bitfield
.baseIndex
10908 && displacement_string_end
[-1] == '+')
10910 /* This hack is to avoid a warning when using the "o"
10911 constraint within gcc asm statements.
10914 #define _set_tssldt_desc(n,addr,limit,type) \
10915 __asm__ __volatile__ ( \
10916 "movw %w2,%0\n\t" \
10917 "movw %w1,2+%0\n\t" \
10918 "rorl $16,%1\n\t" \
10919 "movb %b1,4+%0\n\t" \
10920 "movb %4,5+%0\n\t" \
10921 "movb $0,6+%0\n\t" \
10922 "movb %h1,7+%0\n\t" \
10924 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10926 This works great except that the output assembler ends
10927 up looking a bit weird if it turns out that there is
10928 no offset. You end up producing code that looks like:
10941 So here we provide the missing zero. */
10943 *displacement_string_end
= '0';
10946 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10947 if (gotfree_input_line
)
10948 input_line_pointer
= gotfree_input_line
;
10950 exp_seg
= expression (exp
);
10952 SKIP_WHITESPACE ();
10953 if (*input_line_pointer
)
10954 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10956 RESTORE_END_STRING (disp_end
+ 1);
10958 input_line_pointer
= save_input_line_pointer
;
10959 if (gotfree_input_line
)
10961 free (gotfree_input_line
);
10963 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10964 exp
->X_op
= O_illegal
;
10967 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10969 RESTORE_END_STRING (disp_end
);
10975 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10976 i386_operand_type types
, const char *disp_start
)
10978 i386_operand_type bigdisp
;
10981 /* We do this to make sure that the section symbol is in
10982 the symbol table. We will ultimately change the relocation
10983 to be relative to the beginning of the section. */
10984 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10985 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10986 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10988 if (exp
->X_op
!= O_symbol
)
10991 if (S_IS_LOCAL (exp
->X_add_symbol
)
10992 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10993 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10994 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10995 exp
->X_op
= O_subtract
;
10996 exp
->X_op_symbol
= GOT_symbol
;
10997 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10998 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10999 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11000 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11002 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11005 else if (exp
->X_op
== O_absent
11006 || exp
->X_op
== O_illegal
11007 || exp
->X_op
== O_big
)
11010 as_bad (_("missing or invalid displacement expression `%s'"),
11015 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11016 else if (exp
->X_op
!= O_constant
11017 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
11018 && exp_seg
!= absolute_section
11019 && exp_seg
!= text_section
11020 && exp_seg
!= data_section
11021 && exp_seg
!= bss_section
11022 && exp_seg
!= undefined_section
11023 && !bfd_is_com_section (exp_seg
))
11025 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11030 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
11031 /* Constants get taken care of by optimize_disp(). */
11032 && exp
->X_op
!= O_constant
)
11033 i
.types
[this_operand
].bitfield
.disp8
= 1;
11035 /* Check if this is a displacement only operand. */
11036 bigdisp
= i
.types
[this_operand
];
11037 bigdisp
.bitfield
.disp8
= 0;
11038 bigdisp
.bitfield
.disp16
= 0;
11039 bigdisp
.bitfield
.disp32
= 0;
11040 bigdisp
.bitfield
.disp32s
= 0;
11041 bigdisp
.bitfield
.disp64
= 0;
11042 if (operand_type_all_zero (&bigdisp
))
11043 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11049 /* Return the active addressing mode, taking address override and
11050 registers forming the address into consideration. Update the
11051 address override prefix if necessary. */
11053 static enum flag_code
11054 i386_addressing_mode (void)
11056 enum flag_code addr_mode
;
11058 if (i
.prefix
[ADDR_PREFIX
])
11059 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11060 else if (flag_code
== CODE_16BIT
11061 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11062 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11063 from md_assemble() by "is not a valid base/index expression"
11064 when there is a base and/or index. */
11065 && !i
.types
[this_operand
].bitfield
.baseindex
)
11067 /* MPX insn memory operands with neither base nor index must be forced
11068 to use 32-bit addressing in 16-bit mode. */
11069 addr_mode
= CODE_32BIT
;
11070 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11072 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11073 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11077 addr_mode
= flag_code
;
11079 #if INFER_ADDR_PREFIX
11080 if (i
.mem_operands
== 0)
11082 /* Infer address prefix from the first memory operand. */
11083 const reg_entry
*addr_reg
= i
.base_reg
;
11085 if (addr_reg
== NULL
)
11086 addr_reg
= i
.index_reg
;
11090 if (addr_reg
->reg_type
.bitfield
.dword
)
11091 addr_mode
= CODE_32BIT
;
11092 else if (flag_code
!= CODE_64BIT
11093 && addr_reg
->reg_type
.bitfield
.word
)
11094 addr_mode
= CODE_16BIT
;
11096 if (addr_mode
!= flag_code
)
11098 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11100 /* Change the size of any displacement too. At most one
11101 of Disp16 or Disp32 is set.
11102 FIXME. There doesn't seem to be any real need for
11103 separate Disp16 and Disp32 flags. The same goes for
11104 Imm16 and Imm32. Removing them would probably clean
11105 up the code quite a lot. */
11106 if (flag_code
!= CODE_64BIT
11107 && (i
.types
[this_operand
].bitfield
.disp16
11108 || i
.types
[this_operand
].bitfield
.disp32
))
11109 i
.types
[this_operand
]
11110 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11120 /* Make sure the memory operand we've been dealt is valid.
11121 Return 1 on success, 0 on a failure. */
11124 i386_index_check (const char *operand_string
)
11126 const char *kind
= "base/index";
11127 enum flag_code addr_mode
= i386_addressing_mode ();
11128 const insn_template
*t
= current_templates
->start
;
11130 if (t
->opcode_modifier
.isstring
11131 && !t
->cpu_flags
.bitfield
.cpupadlock
11132 && (current_templates
->end
[-1].opcode_modifier
.isstring
11133 || i
.mem_operands
))
11135 /* Memory operands of string insns are special in that they only allow
11136 a single register (rDI, rSI, or rBX) as their memory address. */
11137 const reg_entry
*expected_reg
;
11138 static const char *di_si
[][2] =
11144 static const char *bx
[] = { "ebx", "bx", "rbx" };
11146 kind
= "string address";
11148 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11150 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11151 - IS_STRING_ES_OP0
;
11154 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11155 || ((!i
.mem_operands
!= !intel_syntax
)
11156 && current_templates
->end
[-1].operand_types
[1]
11157 .bitfield
.baseindex
))
11160 = (const reg_entry
*) str_hash_find (reg_hash
,
11161 di_si
[addr_mode
][op
== es_op
]);
11165 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11167 if (i
.base_reg
!= expected_reg
11169 || operand_type_check (i
.types
[this_operand
], disp
))
11171 /* The second memory operand must have the same size as
11175 && !((addr_mode
== CODE_64BIT
11176 && i
.base_reg
->reg_type
.bitfield
.qword
)
11177 || (addr_mode
== CODE_32BIT
11178 ? i
.base_reg
->reg_type
.bitfield
.dword
11179 : i
.base_reg
->reg_type
.bitfield
.word
)))
11182 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11184 intel_syntax
? '[' : '(',
11186 expected_reg
->reg_name
,
11187 intel_syntax
? ']' : ')');
11194 as_bad (_("`%s' is not a valid %s expression"),
11195 operand_string
, kind
);
11200 if (addr_mode
!= CODE_16BIT
)
11202 /* 32-bit/64-bit checks. */
11203 if (i
.disp_encoding
== disp_encoding_16bit
)
11206 as_bad (_("invalid `%s' prefix"),
11207 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11212 && ((addr_mode
== CODE_64BIT
11213 ? !i
.base_reg
->reg_type
.bitfield
.qword
11214 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11215 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11216 || i
.base_reg
->reg_num
== RegIZ
))
11218 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11219 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11220 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11221 && ((addr_mode
== CODE_64BIT
11222 ? !i
.index_reg
->reg_type
.bitfield
.qword
11223 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11224 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11227 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11228 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11229 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11230 && t
->base_opcode
== 0x1b)
11231 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11232 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11233 && (t
->base_opcode
& ~1) == 0x1a)
11234 || t
->opcode_modifier
.sib
== SIBMEM
)
11236 /* They cannot use RIP-relative addressing. */
11237 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11239 as_bad (_("`%s' cannot be used here"), operand_string
);
11243 /* bndldx and bndstx ignore their scale factor. */
11244 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11245 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11246 && (t
->base_opcode
& ~1) == 0x1a
11247 && i
.log2_scale_factor
)
11248 as_warn (_("register scaling is being ignored here"));
11253 /* 16-bit checks. */
11254 if (i
.disp_encoding
== disp_encoding_32bit
)
11258 && (!i
.base_reg
->reg_type
.bitfield
.word
11259 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11261 && (!i
.index_reg
->reg_type
.bitfield
.word
11262 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11264 && i
.base_reg
->reg_num
< 6
11265 && i
.index_reg
->reg_num
>= 6
11266 && i
.log2_scale_factor
== 0))))
11273 /* Handle vector immediates. */
11276 RC_SAE_immediate (const char *imm_start
)
11278 unsigned int match_found
, j
;
11279 const char *pstr
= imm_start
;
11287 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11289 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11291 if (i
.rounding
.type
!= rc_none
)
11293 as_bad (_("duplicated `%s'"), imm_start
);
11297 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11298 i
.rounding
.operand
= this_operand
;
11300 pstr
+= RC_NamesTable
[j
].len
;
11308 if (*pstr
++ != '}')
11310 as_bad (_("Missing '}': '%s'"), imm_start
);
11313 /* RC/SAE immediate string should contain nothing more. */;
11316 as_bad (_("Junk after '}': '%s'"), imm_start
);
11320 exp
= &im_expressions
[i
.imm_operands
++];
11321 i
.op
[this_operand
].imms
= exp
;
11323 exp
->X_op
= O_constant
;
11324 exp
->X_add_number
= 0;
11325 exp
->X_add_symbol
= (symbolS
*) 0;
11326 exp
->X_op_symbol
= (symbolS
*) 0;
11328 i
.types
[this_operand
].bitfield
.imm8
= 1;
11332 /* Only string instructions can have a second memory operand, so
11333 reduce current_templates to just those if it contains any. */
11335 maybe_adjust_templates (void)
11337 const insn_template
*t
;
11339 gas_assert (i
.mem_operands
== 1);
11341 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11342 if (t
->opcode_modifier
.isstring
)
11345 if (t
< current_templates
->end
)
11347 static templates aux_templates
;
11350 aux_templates
.start
= t
;
11351 for (; t
< current_templates
->end
; ++t
)
11352 if (!t
->opcode_modifier
.isstring
)
11354 aux_templates
.end
= t
;
11356 /* Determine whether to re-check the first memory operand. */
11357 recheck
= (aux_templates
.start
!= current_templates
->start
11358 || t
!= current_templates
->end
);
11360 current_templates
= &aux_templates
;
11364 i
.mem_operands
= 0;
11365 if (i
.memop1_string
!= NULL
11366 && i386_index_check (i
.memop1_string
) == 0)
11368 i
.mem_operands
= 1;
11375 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11379 i386_att_operand (char *operand_string
)
11381 const reg_entry
*r
;
11383 char *op_string
= operand_string
;
11385 if (is_space_char (*op_string
))
11388 /* We check for an absolute prefix (differentiating,
11389 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11390 if (*op_string
== ABSOLUTE_PREFIX
)
11393 if (is_space_char (*op_string
))
11395 i
.jumpabsolute
= true;
11398 /* Check if operand is a register. */
11399 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11401 i386_operand_type temp
;
11406 /* Check for a segment override by searching for ':' after a
11407 segment register. */
11408 op_string
= end_op
;
11409 if (is_space_char (*op_string
))
11411 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11413 i
.seg
[i
.mem_operands
] = r
;
11415 /* Skip the ':' and whitespace. */
11417 if (is_space_char (*op_string
))
11420 if (!is_digit_char (*op_string
)
11421 && !is_identifier_char (*op_string
)
11422 && *op_string
!= '('
11423 && *op_string
!= ABSOLUTE_PREFIX
)
11425 as_bad (_("bad memory operand `%s'"), op_string
);
11428 /* Handle case of %es:*foo. */
11429 if (*op_string
== ABSOLUTE_PREFIX
)
11432 if (is_space_char (*op_string
))
11434 i
.jumpabsolute
= true;
11436 goto do_memory_reference
;
11439 /* Handle vector operations. */
11440 if (*op_string
== '{')
11442 op_string
= check_VecOperations (op_string
, NULL
);
11443 if (op_string
== NULL
)
11449 as_bad (_("junk `%s' after register"), op_string
);
11452 temp
= r
->reg_type
;
11453 temp
.bitfield
.baseindex
= 0;
11454 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11456 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11457 i
.op
[this_operand
].regs
= r
;
11460 else if (*op_string
== REGISTER_PREFIX
)
11462 as_bad (_("bad register name `%s'"), op_string
);
11465 else if (*op_string
== IMMEDIATE_PREFIX
)
11468 if (i
.jumpabsolute
)
11470 as_bad (_("immediate operand illegal with absolute jump"));
11473 if (!i386_immediate (op_string
))
11476 else if (RC_SAE_immediate (operand_string
))
11478 /* If it is a RC or SAE immediate, do nothing. */
11481 else if (is_digit_char (*op_string
)
11482 || is_identifier_char (*op_string
)
11483 || *op_string
== '"'
11484 || *op_string
== '(')
11486 /* This is a memory reference of some sort. */
11489 /* Start and end of displacement string expression (if found). */
11490 char *displacement_string_start
;
11491 char *displacement_string_end
;
11494 do_memory_reference
:
11495 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11497 if ((i
.mem_operands
== 1
11498 && !current_templates
->start
->opcode_modifier
.isstring
)
11499 || i
.mem_operands
== 2)
11501 as_bad (_("too many memory references for `%s'"),
11502 current_templates
->start
->name
);
11506 /* Check for base index form. We detect the base index form by
11507 looking for an ')' at the end of the operand, searching
11508 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11510 base_string
= op_string
+ strlen (op_string
);
11512 /* Handle vector operations. */
11513 vop_start
= strchr (op_string
, '{');
11514 if (vop_start
&& vop_start
< base_string
)
11516 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11518 base_string
= vop_start
;
11522 if (is_space_char (*base_string
))
11525 /* If we only have a displacement, set-up for it to be parsed later. */
11526 displacement_string_start
= op_string
;
11527 displacement_string_end
= base_string
+ 1;
11529 if (*base_string
== ')')
11532 unsigned int parens_balanced
= 1;
11533 /* We've already checked that the number of left & right ()'s are
11534 equal, so this loop will not be infinite. */
11538 if (*base_string
== ')')
11540 if (*base_string
== '(')
11543 while (parens_balanced
);
11545 temp_string
= base_string
;
11547 /* Skip past '(' and whitespace. */
11549 if (is_space_char (*base_string
))
11552 if (*base_string
== ','
11553 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11556 displacement_string_end
= temp_string
;
11558 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11562 if (i
.base_reg
== &bad_reg
)
11564 base_string
= end_op
;
11565 if (is_space_char (*base_string
))
11569 /* There may be an index reg or scale factor here. */
11570 if (*base_string
== ',')
11573 if (is_space_char (*base_string
))
11576 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11579 if (i
.index_reg
== &bad_reg
)
11581 base_string
= end_op
;
11582 if (is_space_char (*base_string
))
11584 if (*base_string
== ',')
11587 if (is_space_char (*base_string
))
11590 else if (*base_string
!= ')')
11592 as_bad (_("expecting `,' or `)' "
11593 "after index register in `%s'"),
11598 else if (*base_string
== REGISTER_PREFIX
)
11600 end_op
= strchr (base_string
, ',');
11603 as_bad (_("bad register name `%s'"), base_string
);
11607 /* Check for scale factor. */
11608 if (*base_string
!= ')')
11610 char *end_scale
= i386_scale (base_string
);
11615 base_string
= end_scale
;
11616 if (is_space_char (*base_string
))
11618 if (*base_string
!= ')')
11620 as_bad (_("expecting `)' "
11621 "after scale factor in `%s'"),
11626 else if (!i
.index_reg
)
11628 as_bad (_("expecting index register or scale factor "
11629 "after `,'; got '%c'"),
11634 else if (*base_string
!= ')')
11636 as_bad (_("expecting `,' or `)' "
11637 "after base register in `%s'"),
11642 else if (*base_string
== REGISTER_PREFIX
)
11644 end_op
= strchr (base_string
, ',');
11647 as_bad (_("bad register name `%s'"), base_string
);
11652 /* If there's an expression beginning the operand, parse it,
11653 assuming displacement_string_start and
11654 displacement_string_end are meaningful. */
11655 if (displacement_string_start
!= displacement_string_end
)
11657 if (!i386_displacement (displacement_string_start
,
11658 displacement_string_end
))
11662 /* Special case for (%dx) while doing input/output op. */
11664 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11665 && i
.base_reg
->reg_type
.bitfield
.word
11666 && i
.index_reg
== 0
11667 && i
.log2_scale_factor
== 0
11668 && i
.seg
[i
.mem_operands
] == 0
11669 && !operand_type_check (i
.types
[this_operand
], disp
))
11671 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11675 if (i386_index_check (operand_string
) == 0)
11677 i
.flags
[this_operand
] |= Operand_Mem
;
11678 if (i
.mem_operands
== 0)
11679 i
.memop1_string
= xstrdup (operand_string
);
11684 /* It's not a memory operand; argh! */
11685 as_bad (_("invalid char %s beginning operand %d `%s'"),
11686 output_invalid (*op_string
),
11691 return 1; /* Normal return. */
11694 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11695 that an rs_machine_dependent frag may reach. */
11698 i386_frag_max_var (fragS
*frag
)
11700 /* The only relaxable frags are for jumps.
11701 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11702 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11703 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11708 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11710 /* STT_GNU_IFUNC symbol must go through PLT. */
11711 if ((symbol_get_bfdsym (fr_symbol
)->flags
11712 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11715 if (!S_IS_EXTERNAL (fr_symbol
))
11716 /* Symbol may be weak or local. */
11717 return !S_IS_WEAK (fr_symbol
);
11719 /* Global symbols with non-default visibility can't be preempted. */
11720 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11723 if (fr_var
!= NO_RELOC
)
11724 switch ((enum bfd_reloc_code_real
) fr_var
)
11726 case BFD_RELOC_386_PLT32
:
11727 case BFD_RELOC_X86_64_PLT32
:
11728 /* Symbol with PLT relocation may be preempted. */
11734 /* Global symbols with default visibility in a shared library may be
11735 preempted by another definition. */
11740 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11741 Note also work for Skylake and Cascadelake.
11742 ---------------------------------------------------------------------
11743 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11744 | ------ | ----------- | ------- | -------- |
11746 | Jno | N | N | Y |
11747 | Jc/Jb | Y | N | Y |
11748 | Jae/Jnb | Y | N | Y |
11749 | Je/Jz | Y | Y | Y |
11750 | Jne/Jnz | Y | Y | Y |
11751 | Jna/Jbe | Y | N | Y |
11752 | Ja/Jnbe | Y | N | Y |
11754 | Jns | N | N | Y |
11755 | Jp/Jpe | N | N | Y |
11756 | Jnp/Jpo | N | N | Y |
11757 | Jl/Jnge | Y | Y | Y |
11758 | Jge/Jnl | Y | Y | Y |
11759 | Jle/Jng | Y | Y | Y |
11760 | Jg/Jnle | Y | Y | Y |
11761 --------------------------------------------------------------------- */
11763 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11765 if (mf_cmp
== mf_cmp_alu_cmp
)
11766 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11767 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11768 if (mf_cmp
== mf_cmp_incdec
)
11769 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11770 || mf_jcc
== mf_jcc_jle
);
11771 if (mf_cmp
== mf_cmp_test_and
)
11776 /* Return the next non-empty frag. */
11779 i386_next_non_empty_frag (fragS
*fragP
)
11781 /* There may be a frag with a ".fill 0" when there is no room in
11782 the current frag for frag_grow in output_insn. */
11783 for (fragP
= fragP
->fr_next
;
11785 && fragP
->fr_type
== rs_fill
11786 && fragP
->fr_fix
== 0);
11787 fragP
= fragP
->fr_next
)
11792 /* Return the next jcc frag after BRANCH_PADDING. */
11795 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11797 fragS
*branch_fragP
;
11801 if (pad_fragP
->fr_type
== rs_machine_dependent
11802 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11803 == BRANCH_PADDING
))
11805 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11806 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11808 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11809 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11810 pad_fragP
->tc_frag_data
.mf_type
))
11811 return branch_fragP
;
11817 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11820 i386_classify_machine_dependent_frag (fragS
*fragP
)
11824 fragS
*branch_fragP
;
11826 unsigned int max_prefix_length
;
11828 if (fragP
->tc_frag_data
.classified
)
11831 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11832 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11833 for (next_fragP
= fragP
;
11834 next_fragP
!= NULL
;
11835 next_fragP
= next_fragP
->fr_next
)
11837 next_fragP
->tc_frag_data
.classified
= 1;
11838 if (next_fragP
->fr_type
== rs_machine_dependent
)
11839 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11841 case BRANCH_PADDING
:
11842 /* The BRANCH_PADDING frag must be followed by a branch
11844 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11845 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11847 case FUSED_JCC_PADDING
:
11848 /* Check if this is a fused jcc:
11850 CMP like instruction
11854 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11855 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11856 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11859 /* The BRANCH_PADDING frag is merged with the
11860 FUSED_JCC_PADDING frag. */
11861 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11862 /* CMP like instruction size. */
11863 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11864 frag_wane (pad_fragP
);
11865 /* Skip to branch_fragP. */
11866 next_fragP
= branch_fragP
;
11868 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11870 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11872 next_fragP
->fr_subtype
11873 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11874 next_fragP
->tc_frag_data
.max_bytes
11875 = next_fragP
->tc_frag_data
.max_prefix_length
;
11876 /* This will be updated in the BRANCH_PREFIX scan. */
11877 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11880 frag_wane (next_fragP
);
11885 /* Stop if there is no BRANCH_PREFIX. */
11886 if (!align_branch_prefix_size
)
11889 /* Scan for BRANCH_PREFIX. */
11890 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11892 if (fragP
->fr_type
!= rs_machine_dependent
11893 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11897 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11898 COND_JUMP_PREFIX. */
11899 max_prefix_length
= 0;
11900 for (next_fragP
= fragP
;
11901 next_fragP
!= NULL
;
11902 next_fragP
= next_fragP
->fr_next
)
11904 if (next_fragP
->fr_type
== rs_fill
)
11905 /* Skip rs_fill frags. */
11907 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11908 /* Stop for all other frags. */
11911 /* rs_machine_dependent frags. */
11912 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11915 /* Count BRANCH_PREFIX frags. */
11916 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11918 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11919 frag_wane (next_fragP
);
11923 += next_fragP
->tc_frag_data
.max_bytes
;
11925 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11927 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11928 == FUSED_JCC_PADDING
))
11930 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11931 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11935 /* Stop for other rs_machine_dependent frags. */
11939 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11941 /* Skip to the next frag. */
11942 fragP
= next_fragP
;
11946 /* Compute padding size for
11949 CMP like instruction
11951 COND_JUMP/UNCOND_JUMP
11956 COND_JUMP/UNCOND_JUMP
11960 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11962 unsigned int offset
, size
, padding_size
;
11963 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11965 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11967 address
= fragP
->fr_address
;
11968 address
+= fragP
->fr_fix
;
11970 /* CMP like instrunction size. */
11971 size
= fragP
->tc_frag_data
.cmp_size
;
11973 /* The base size of the branch frag. */
11974 size
+= branch_fragP
->fr_fix
;
11976 /* Add opcode and displacement bytes for the rs_machine_dependent
11978 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11979 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11981 /* Check if branch is within boundary and doesn't end at the last
11983 offset
= address
& ((1U << align_branch_power
) - 1);
11984 if ((offset
+ size
) >= (1U << align_branch_power
))
11985 /* Padding needed to avoid crossing boundary. */
11986 padding_size
= (1U << align_branch_power
) - offset
;
11988 /* No padding needed. */
11991 /* The return value may be saved in tc_frag_data.length which is
11993 if (!fits_in_unsigned_byte (padding_size
))
11996 return padding_size
;
11999 /* i386_generic_table_relax_frag()
12001 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12002 grow/shrink padding to align branch frags. Hand others to
12006 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12008 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12009 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12011 long padding_size
= i386_branch_padding_size (fragP
, 0);
12012 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12014 /* When the BRANCH_PREFIX frag is used, the computed address
12015 must match the actual address and there should be no padding. */
12016 if (fragP
->tc_frag_data
.padding_address
12017 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12021 /* Update the padding size. */
12023 fragP
->tc_frag_data
.length
= padding_size
;
12027 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12029 fragS
*padding_fragP
, *next_fragP
;
12030 long padding_size
, left_size
, last_size
;
12032 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12033 if (!padding_fragP
)
12034 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12035 return (fragP
->tc_frag_data
.length
12036 - fragP
->tc_frag_data
.last_length
);
12038 /* Compute the relative address of the padding frag in the very
12039 first time where the BRANCH_PREFIX frag sizes are zero. */
12040 if (!fragP
->tc_frag_data
.padding_address
)
12041 fragP
->tc_frag_data
.padding_address
12042 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12044 /* First update the last length from the previous interation. */
12045 left_size
= fragP
->tc_frag_data
.prefix_length
;
12046 for (next_fragP
= fragP
;
12047 next_fragP
!= padding_fragP
;
12048 next_fragP
= next_fragP
->fr_next
)
12049 if (next_fragP
->fr_type
== rs_machine_dependent
12050 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12055 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12059 if (max
> left_size
)
12064 next_fragP
->tc_frag_data
.last_length
= size
;
12068 next_fragP
->tc_frag_data
.last_length
= 0;
12071 /* Check the padding size for the padding frag. */
12072 padding_size
= i386_branch_padding_size
12073 (padding_fragP
, (fragP
->fr_address
12074 + fragP
->tc_frag_data
.padding_address
));
12076 last_size
= fragP
->tc_frag_data
.prefix_length
;
12077 /* Check if there is change from the last interation. */
12078 if (padding_size
== last_size
)
12080 /* Update the expected address of the padding frag. */
12081 padding_fragP
->tc_frag_data
.padding_address
12082 = (fragP
->fr_address
+ padding_size
12083 + fragP
->tc_frag_data
.padding_address
);
12087 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12089 /* No padding if there is no sufficient room. Clear the
12090 expected address of the padding frag. */
12091 padding_fragP
->tc_frag_data
.padding_address
= 0;
12095 /* Store the expected address of the padding frag. */
12096 padding_fragP
->tc_frag_data
.padding_address
12097 = (fragP
->fr_address
+ padding_size
12098 + fragP
->tc_frag_data
.padding_address
);
12100 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12102 /* Update the length for the current interation. */
12103 left_size
= padding_size
;
12104 for (next_fragP
= fragP
;
12105 next_fragP
!= padding_fragP
;
12106 next_fragP
= next_fragP
->fr_next
)
12107 if (next_fragP
->fr_type
== rs_machine_dependent
12108 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12113 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12117 if (max
> left_size
)
12122 next_fragP
->tc_frag_data
.length
= size
;
12126 next_fragP
->tc_frag_data
.length
= 0;
12129 return (fragP
->tc_frag_data
.length
12130 - fragP
->tc_frag_data
.last_length
);
12132 return relax_frag (segment
, fragP
, stretch
);
12135 /* md_estimate_size_before_relax()
12137 Called just before relax() for rs_machine_dependent frags. The x86
12138 assembler uses these frags to handle variable size jump
12141 Any symbol that is now undefined will not become defined.
12142 Return the correct fr_subtype in the frag.
12143 Return the initial "guess for variable size of frag" to caller.
12144 The guess is actually the growth beyond the fixed part. Whatever
12145 we do to grow the fixed or variable part contributes to our
12149 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12151 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12152 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12153 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12155 i386_classify_machine_dependent_frag (fragP
);
12156 return fragP
->tc_frag_data
.length
;
12159 /* We've already got fragP->fr_subtype right; all we have to do is
12160 check for un-relaxable symbols. On an ELF system, we can't relax
12161 an externally visible symbol, because it may be overridden by a
12163 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12164 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12166 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12169 #if defined (OBJ_COFF) && defined (TE_PE)
12170 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12171 && S_IS_WEAK (fragP
->fr_symbol
))
12175 /* Symbol is undefined in this segment, or we need to keep a
12176 reloc so that weak symbols can be overridden. */
12177 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12178 enum bfd_reloc_code_real reloc_type
;
12179 unsigned char *opcode
;
12183 if (fragP
->fr_var
!= NO_RELOC
)
12184 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12185 else if (size
== 2)
12186 reloc_type
= BFD_RELOC_16_PCREL
;
12187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12188 else if (need_plt32_p (fragP
->fr_symbol
))
12189 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12192 reloc_type
= BFD_RELOC_32_PCREL
;
12194 old_fr_fix
= fragP
->fr_fix
;
12195 opcode
= (unsigned char *) fragP
->fr_opcode
;
12197 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12200 /* Make jmp (0xeb) a (d)word displacement jump. */
12202 fragP
->fr_fix
+= size
;
12203 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12205 fragP
->fr_offset
, 1,
12211 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12213 /* Negate the condition, and branch past an
12214 unconditional jump. */
12217 /* Insert an unconditional jump. */
12219 /* We added two extra opcode bytes, and have a two byte
12221 fragP
->fr_fix
+= 2 + 2;
12222 fix_new (fragP
, old_fr_fix
+ 2, 2,
12224 fragP
->fr_offset
, 1,
12228 /* Fall through. */
12231 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12233 fragP
->fr_fix
+= 1;
12234 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12236 fragP
->fr_offset
, 1,
12237 BFD_RELOC_8_PCREL
);
12238 fixP
->fx_signed
= 1;
12242 /* This changes the byte-displacement jump 0x7N
12243 to the (d)word-displacement jump 0x0f,0x8N. */
12244 opcode
[1] = opcode
[0] + 0x10;
12245 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12246 /* We've added an opcode byte. */
12247 fragP
->fr_fix
+= 1 + size
;
12248 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12250 fragP
->fr_offset
, 1,
12255 BAD_CASE (fragP
->fr_subtype
);
12259 /* All jumps handled here are signed, but don't unconditionally use a
12260 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12261 around at 4G (outside of 64-bit mode) and 64k. */
12262 if (size
== 4 && flag_code
== CODE_64BIT
)
12263 fixP
->fx_signed
= 1;
12266 return fragP
->fr_fix
- old_fr_fix
;
12269 /* Guess size depending on current relax state. Initially the relax
12270 state will correspond to a short jump and we return 1, because
12271 the variable part of the frag (the branch offset) is one byte
12272 long. However, we can relax a section more than once and in that
12273 case we must either set fr_subtype back to the unrelaxed state,
12274 or return the value for the appropriate branch. */
12275 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12278 /* Called after relax() is finished.
12280 In: Address of frag.
12281 fr_type == rs_machine_dependent.
12282 fr_subtype is what the address relaxed to.
12284 Out: Any fixSs and constants are set up.
12285 Caller will turn frag into a ".space 0". */
12288 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12291 unsigned char *opcode
;
12292 unsigned char *where_to_put_displacement
= NULL
;
12293 offsetT target_address
;
12294 offsetT opcode_address
;
12295 unsigned int extension
= 0;
12296 offsetT displacement_from_opcode_start
;
12298 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12299 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12300 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12302 /* Generate nop padding. */
12303 unsigned int size
= fragP
->tc_frag_data
.length
;
12306 if (size
> fragP
->tc_frag_data
.max_bytes
)
12312 const char *branch
= "branch";
12313 const char *prefix
= "";
12314 fragS
*padding_fragP
;
12315 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12318 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12319 switch (fragP
->tc_frag_data
.default_prefix
)
12324 case CS_PREFIX_OPCODE
:
12327 case DS_PREFIX_OPCODE
:
12330 case ES_PREFIX_OPCODE
:
12333 case FS_PREFIX_OPCODE
:
12336 case GS_PREFIX_OPCODE
:
12339 case SS_PREFIX_OPCODE
:
12344 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12345 "%s within %d-byte boundary\n");
12347 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12348 "align %s within %d-byte boundary\n");
12352 padding_fragP
= fragP
;
12353 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12354 "%s within %d-byte boundary\n");
12358 switch (padding_fragP
->tc_frag_data
.branch_type
)
12360 case align_branch_jcc
:
12363 case align_branch_fused
:
12364 branch
= "fused jcc";
12366 case align_branch_jmp
:
12369 case align_branch_call
:
12372 case align_branch_indirect
:
12373 branch
= "indiret branch";
12375 case align_branch_ret
:
12382 fprintf (stdout
, msg
,
12383 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12384 (long long) fragP
->fr_address
, branch
,
12385 1 << align_branch_power
);
12387 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12388 memset (fragP
->fr_opcode
,
12389 fragP
->tc_frag_data
.default_prefix
, size
);
12391 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12393 fragP
->fr_fix
+= size
;
12398 opcode
= (unsigned char *) fragP
->fr_opcode
;
12400 /* Address we want to reach in file space. */
12401 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12403 /* Address opcode resides at in file space. */
12404 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12406 /* Displacement from opcode start to fill into instruction. */
12407 displacement_from_opcode_start
= target_address
- opcode_address
;
12409 if ((fragP
->fr_subtype
& BIG
) == 0)
12411 /* Don't have to change opcode. */
12412 extension
= 1; /* 1 opcode + 1 displacement */
12413 where_to_put_displacement
= &opcode
[1];
12417 if (no_cond_jump_promotion
12418 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12419 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12420 _("long jump required"));
12422 switch (fragP
->fr_subtype
)
12424 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12425 extension
= 4; /* 1 opcode + 4 displacement */
12427 where_to_put_displacement
= &opcode
[1];
12430 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12431 extension
= 2; /* 1 opcode + 2 displacement */
12433 where_to_put_displacement
= &opcode
[1];
12436 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12437 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12438 extension
= 5; /* 2 opcode + 4 displacement */
12439 opcode
[1] = opcode
[0] + 0x10;
12440 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12441 where_to_put_displacement
= &opcode
[2];
12444 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12445 extension
= 3; /* 2 opcode + 2 displacement */
12446 opcode
[1] = opcode
[0] + 0x10;
12447 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12448 where_to_put_displacement
= &opcode
[2];
12451 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12456 where_to_put_displacement
= &opcode
[3];
12460 BAD_CASE (fragP
->fr_subtype
);
12465 /* If size if less then four we are sure that the operand fits,
12466 but if it's 4, then it could be that the displacement is larger
12468 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12470 && ((addressT
) (displacement_from_opcode_start
- extension
12471 + ((addressT
) 1 << 31))
12472 > (((addressT
) 2 << 31) - 1)))
12474 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12475 _("jump target out of range"));
12476 /* Make us emit 0. */
12477 displacement_from_opcode_start
= extension
;
12479 /* Now put displacement after opcode. */
12480 md_number_to_chars ((char *) where_to_put_displacement
,
12481 (valueT
) (displacement_from_opcode_start
- extension
),
12482 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12483 fragP
->fr_fix
+= extension
;
12486 /* Apply a fixup (fixP) to segment data, once it has been determined
12487 by our caller that we have all the info we need to fix it up.
12489 Parameter valP is the pointer to the value of the bits.
12491 On the 386, immediates, displacements, and data pointers are all in
12492 the same (little-endian) format, so we don't need to care about which
12493 we are handling. */
12496 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12498 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12499 valueT value
= *valP
;
12501 #if !defined (TE_Mach)
12502 if (fixP
->fx_pcrel
)
12504 switch (fixP
->fx_r_type
)
12510 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12513 case BFD_RELOC_X86_64_32S
:
12514 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12517 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12520 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12525 if (fixP
->fx_addsy
!= NULL
12526 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12527 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12528 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12529 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12530 && !use_rela_relocations
)
12532 /* This is a hack. There should be a better way to handle this.
12533 This covers for the fact that bfd_install_relocation will
12534 subtract the current location (for partial_inplace, PC relative
12535 relocations); see more below. */
12539 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12542 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12547 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12549 if ((sym_seg
== seg
12550 || (symbol_section_p (fixP
->fx_addsy
)
12551 && sym_seg
!= absolute_section
))
12552 && !generic_force_reloc (fixP
))
12554 /* Yes, we add the values in twice. This is because
12555 bfd_install_relocation subtracts them out again. I think
12556 bfd_install_relocation is broken, but I don't dare change
12558 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12562 #if defined (OBJ_COFF) && defined (TE_PE)
12563 /* For some reason, the PE format does not store a
12564 section address offset for a PC relative symbol. */
12565 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12566 || S_IS_WEAK (fixP
->fx_addsy
))
12567 value
+= md_pcrel_from (fixP
);
12570 #if defined (OBJ_COFF) && defined (TE_PE)
12571 if (fixP
->fx_addsy
!= NULL
12572 && S_IS_WEAK (fixP
->fx_addsy
)
12573 /* PR 16858: Do not modify weak function references. */
12574 && ! fixP
->fx_pcrel
)
12576 #if !defined (TE_PEP)
12577 /* For x86 PE weak function symbols are neither PC-relative
12578 nor do they set S_IS_FUNCTION. So the only reliable way
12579 to detect them is to check the flags of their containing
12581 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12582 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12586 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12590 /* Fix a few things - the dynamic linker expects certain values here,
12591 and we must not disappoint it. */
12592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12593 if (IS_ELF
&& fixP
->fx_addsy
)
12594 switch (fixP
->fx_r_type
)
12596 case BFD_RELOC_386_PLT32
:
12597 case BFD_RELOC_X86_64_PLT32
:
12598 /* Make the jump instruction point to the address of the operand.
12599 At runtime we merely add the offset to the actual PLT entry.
12600 NB: Subtract the offset size only for jump instructions. */
12601 if (fixP
->fx_pcrel
)
12605 case BFD_RELOC_386_TLS_GD
:
12606 case BFD_RELOC_386_TLS_LDM
:
12607 case BFD_RELOC_386_TLS_IE_32
:
12608 case BFD_RELOC_386_TLS_IE
:
12609 case BFD_RELOC_386_TLS_GOTIE
:
12610 case BFD_RELOC_386_TLS_GOTDESC
:
12611 case BFD_RELOC_X86_64_TLSGD
:
12612 case BFD_RELOC_X86_64_TLSLD
:
12613 case BFD_RELOC_X86_64_GOTTPOFF
:
12614 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12615 value
= 0; /* Fully resolved at runtime. No addend. */
12617 case BFD_RELOC_386_TLS_LE
:
12618 case BFD_RELOC_386_TLS_LDO_32
:
12619 case BFD_RELOC_386_TLS_LE_32
:
12620 case BFD_RELOC_X86_64_DTPOFF32
:
12621 case BFD_RELOC_X86_64_DTPOFF64
:
12622 case BFD_RELOC_X86_64_TPOFF32
:
12623 case BFD_RELOC_X86_64_TPOFF64
:
12624 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12627 case BFD_RELOC_386_TLS_DESC_CALL
:
12628 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12629 value
= 0; /* Fully resolved at runtime. No addend. */
12630 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12634 case BFD_RELOC_VTABLE_INHERIT
:
12635 case BFD_RELOC_VTABLE_ENTRY
:
12642 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12644 #endif /* !defined (TE_Mach) */
12646 /* Are we finished with this relocation now? */
12647 if (fixP
->fx_addsy
== NULL
)
12650 switch (fixP
->fx_r_type
)
12652 case BFD_RELOC_X86_64_32S
:
12653 fixP
->fx_signed
= 1;
12660 #if defined (OBJ_COFF) && defined (TE_PE)
12661 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12664 /* Remember value for tc_gen_reloc. */
12665 fixP
->fx_addnumber
= value
;
12666 /* Clear out the frag for now. */
12670 else if (use_rela_relocations
)
12672 fixP
->fx_no_overflow
= 1;
12673 /* Remember value for tc_gen_reloc. */
12674 fixP
->fx_addnumber
= value
;
12678 md_number_to_chars (p
, value
, fixP
->fx_size
);
12682 md_atof (int type
, char *litP
, int *sizeP
)
12684 /* This outputs the LITTLENUMs in REVERSE order;
12685 in accord with the bigendian 386. */
12686 return ieee_md_atof (type
, litP
, sizeP
, false);
12689 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12692 output_invalid (int c
)
12695 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12698 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12699 "(0x%x)", (unsigned char) c
);
12700 return output_invalid_buf
;
12703 /* Verify that @r can be used in the current context. */
12705 static bool check_register (const reg_entry
*r
)
12707 if (allow_pseudo_reg
)
12710 if (operand_type_all_zero (&r
->reg_type
))
12713 if ((r
->reg_type
.bitfield
.dword
12714 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12715 || r
->reg_type
.bitfield
.class == RegCR
12716 || r
->reg_type
.bitfield
.class == RegDR
)
12717 && !cpu_arch_flags
.bitfield
.cpui386
)
12720 if (r
->reg_type
.bitfield
.class == RegTR
12721 && (flag_code
== CODE_64BIT
12722 || !cpu_arch_flags
.bitfield
.cpui386
12723 || cpu_arch_isa_flags
.bitfield
.cpui586
12724 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12727 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12730 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12732 if (r
->reg_type
.bitfield
.zmmword
12733 || r
->reg_type
.bitfield
.class == RegMask
)
12736 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12738 if (r
->reg_type
.bitfield
.ymmword
)
12741 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12746 if (r
->reg_type
.bitfield
.tmmword
12747 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12748 || flag_code
!= CODE_64BIT
))
12751 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12754 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12755 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12758 /* Upper 16 vector registers are only available with VREX in 64bit
12759 mode, and require EVEX encoding. */
12760 if (r
->reg_flags
& RegVRex
)
12762 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12763 || flag_code
!= CODE_64BIT
)
12766 if (i
.vec_encoding
== vex_encoding_default
)
12767 i
.vec_encoding
= vex_encoding_evex
;
12768 else if (i
.vec_encoding
!= vex_encoding_evex
)
12769 i
.vec_encoding
= vex_encoding_error
;
12772 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12773 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12774 && flag_code
!= CODE_64BIT
)
12777 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12784 /* REG_STRING starts *before* REGISTER_PREFIX. */
12786 static const reg_entry
*
12787 parse_real_register (char *reg_string
, char **end_op
)
12789 char *s
= reg_string
;
12791 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12792 const reg_entry
*r
;
12794 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12795 if (*s
== REGISTER_PREFIX
)
12798 if (is_space_char (*s
))
12801 p
= reg_name_given
;
12802 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12804 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12805 return (const reg_entry
*) NULL
;
12809 /* For naked regs, make sure that we are not dealing with an identifier.
12810 This prevents confusing an identifier like `eax_var' with register
12812 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12813 return (const reg_entry
*) NULL
;
12817 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12819 /* Handle floating point regs, allowing spaces in the (i) part. */
12822 if (!cpu_arch_flags
.bitfield
.cpu8087
12823 && !cpu_arch_flags
.bitfield
.cpu287
12824 && !cpu_arch_flags
.bitfield
.cpu387
12825 && !allow_pseudo_reg
)
12826 return (const reg_entry
*) NULL
;
12828 if (is_space_char (*s
))
12833 if (is_space_char (*s
))
12835 if (*s
>= '0' && *s
<= '7')
12837 int fpr
= *s
- '0';
12839 if (is_space_char (*s
))
12844 know (r
[fpr
].reg_num
== fpr
);
12848 /* We have "%st(" then garbage. */
12849 return (const reg_entry
*) NULL
;
12853 return r
&& check_register (r
) ? r
: NULL
;
12856 /* REG_STRING starts *before* REGISTER_PREFIX. */
12858 static const reg_entry
*
12859 parse_register (char *reg_string
, char **end_op
)
12861 const reg_entry
*r
;
12863 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12864 r
= parse_real_register (reg_string
, end_op
);
12869 char *save
= input_line_pointer
;
12873 input_line_pointer
= reg_string
;
12874 c
= get_symbol_name (®_string
);
12875 symbolP
= symbol_find (reg_string
);
12876 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12878 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12880 know (e
->X_op
== O_register
);
12881 know (e
->X_add_number
>= 0
12882 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12883 r
= i386_regtab
+ e
->X_add_number
;
12884 if (!check_register (r
))
12886 as_bad (_("register '%s%s' cannot be used here"),
12887 register_prefix
, r
->reg_name
);
12890 *end_op
= input_line_pointer
;
12892 *input_line_pointer
= c
;
12893 input_line_pointer
= save
;
12899 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12901 const reg_entry
*r
;
12902 char *end
= input_line_pointer
;
12905 r
= parse_register (name
, &input_line_pointer
);
12906 if (r
&& end
<= input_line_pointer
)
12908 *nextcharP
= *input_line_pointer
;
12909 *input_line_pointer
= 0;
12912 e
->X_op
= O_register
;
12913 e
->X_add_number
= r
- i386_regtab
;
12916 e
->X_op
= O_illegal
;
12919 input_line_pointer
= end
;
12921 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12925 md_operand (expressionS
*e
)
12928 const reg_entry
*r
;
12930 switch (*input_line_pointer
)
12932 case REGISTER_PREFIX
:
12933 r
= parse_real_register (input_line_pointer
, &end
);
12936 e
->X_op
= O_register
;
12937 e
->X_add_number
= r
- i386_regtab
;
12938 input_line_pointer
= end
;
12943 gas_assert (intel_syntax
);
12944 end
= input_line_pointer
++;
12946 if (*input_line_pointer
== ']')
12948 ++input_line_pointer
;
12949 e
->X_op_symbol
= make_expr_symbol (e
);
12950 e
->X_add_symbol
= NULL
;
12951 e
->X_add_number
= 0;
12956 e
->X_op
= O_absent
;
12957 input_line_pointer
= end
;
12964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12965 const char *md_shortopts
= "kVQ:sqnO::";
12967 const char *md_shortopts
= "qnO::";
12970 #define OPTION_32 (OPTION_MD_BASE + 0)
12971 #define OPTION_64 (OPTION_MD_BASE + 1)
12972 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12973 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12974 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12975 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12976 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12977 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12978 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12979 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12980 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12981 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12982 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12983 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12984 #define OPTION_X32 (OPTION_MD_BASE + 14)
12985 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12986 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12987 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12988 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12989 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12990 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12991 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12992 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12993 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12994 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12995 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12996 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12997 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12998 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12999 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13000 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13001 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13002 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13003 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13005 struct option md_longopts
[] =
13007 {"32", no_argument
, NULL
, OPTION_32
},
13008 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13009 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13010 {"64", no_argument
, NULL
, OPTION_64
},
13012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13013 {"x32", no_argument
, NULL
, OPTION_X32
},
13014 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13015 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13017 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13018 {"march", required_argument
, NULL
, OPTION_MARCH
},
13019 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13020 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13021 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13022 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13023 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13024 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13025 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13026 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13027 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13028 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13029 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13030 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13031 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13032 # if defined (TE_PE) || defined (TE_PEP)
13033 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13035 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13036 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13037 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13038 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13039 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13040 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13041 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13042 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13043 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13044 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13045 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13046 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13047 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13048 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13049 {NULL
, no_argument
, NULL
, 0}
13051 size_t md_longopts_size
= sizeof (md_longopts
);
13054 md_parse_option (int c
, const char *arg
)
13057 char *arch
, *next
, *saved
, *type
;
13062 optimize_align_code
= 0;
13066 quiet_warnings
= 1;
13069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13070 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13071 should be emitted or not. FIXME: Not implemented. */
13073 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13077 /* -V: SVR4 argument to print version ID. */
13079 print_version_id ();
13082 /* -k: Ignore for FreeBSD compatibility. */
13087 /* -s: On i386 Solaris, this tells the native assembler to use
13088 .stab instead of .stab.excl. We always use .stab anyhow. */
13091 case OPTION_MSHARED
:
13095 case OPTION_X86_USED_NOTE
:
13096 if (strcasecmp (arg
, "yes") == 0)
13098 else if (strcasecmp (arg
, "no") == 0)
13101 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13106 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13107 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13110 const char **list
, **l
;
13112 list
= bfd_target_list ();
13113 for (l
= list
; *l
!= NULL
; l
++)
13114 if (startswith (*l
, "elf64-x86-64")
13115 || strcmp (*l
, "coff-x86-64") == 0
13116 || strcmp (*l
, "pe-x86-64") == 0
13117 || strcmp (*l
, "pei-x86-64") == 0
13118 || strcmp (*l
, "mach-o-x86-64") == 0)
13120 default_arch
= "x86_64";
13124 as_fatal (_("no compiled in support for x86_64"));
13130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13134 const char **list
, **l
;
13136 list
= bfd_target_list ();
13137 for (l
= list
; *l
!= NULL
; l
++)
13138 if (startswith (*l
, "elf32-x86-64"))
13140 default_arch
= "x86_64:32";
13144 as_fatal (_("no compiled in support for 32bit x86_64"));
13148 as_fatal (_("32bit x86_64 is only supported for ELF"));
13153 default_arch
= "i386";
13156 case OPTION_DIVIDE
:
13157 #ifdef SVR4_COMMENT_CHARS
13162 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13164 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13168 i386_comment_chars
= n
;
13174 saved
= xstrdup (arg
);
13176 /* Allow -march=+nosse. */
13182 as_fatal (_("invalid -march= option: `%s'"), arg
);
13183 next
= strchr (arch
, '+');
13186 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13188 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13191 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13194 cpu_arch_name
= cpu_arch
[j
].name
;
13195 cpu_sub_arch_name
= NULL
;
13196 cpu_arch_flags
= cpu_arch
[j
].flags
;
13197 cpu_arch_isa
= cpu_arch
[j
].type
;
13198 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13199 if (!cpu_arch_tune_set
)
13201 cpu_arch_tune
= cpu_arch_isa
;
13202 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13206 else if (*cpu_arch
[j
].name
== '.'
13207 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13209 /* ISA extension. */
13210 i386_cpu_flags flags
;
13212 flags
= cpu_flags_or (cpu_arch_flags
,
13213 cpu_arch
[j
].flags
);
13215 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13217 if (cpu_sub_arch_name
)
13219 char *name
= cpu_sub_arch_name
;
13220 cpu_sub_arch_name
= concat (name
,
13222 (const char *) NULL
);
13226 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13227 cpu_arch_flags
= flags
;
13228 cpu_arch_isa_flags
= flags
;
13232 = cpu_flags_or (cpu_arch_isa_flags
,
13233 cpu_arch
[j
].flags
);
13238 if (j
>= ARRAY_SIZE (cpu_arch
))
13240 /* Disable an ISA extension. */
13241 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13242 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13244 i386_cpu_flags flags
;
13246 flags
= cpu_flags_and_not (cpu_arch_flags
,
13247 cpu_noarch
[j
].flags
);
13248 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13250 if (cpu_sub_arch_name
)
13252 char *name
= cpu_sub_arch_name
;
13253 cpu_sub_arch_name
= concat (arch
,
13254 (const char *) NULL
);
13258 cpu_sub_arch_name
= xstrdup (arch
);
13259 cpu_arch_flags
= flags
;
13260 cpu_arch_isa_flags
= flags
;
13265 if (j
>= ARRAY_SIZE (cpu_noarch
))
13266 j
= ARRAY_SIZE (cpu_arch
);
13269 if (j
>= ARRAY_SIZE (cpu_arch
))
13270 as_fatal (_("invalid -march= option: `%s'"), arg
);
13274 while (next
!= NULL
);
13280 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13281 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13283 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13285 cpu_arch_tune_set
= 1;
13286 cpu_arch_tune
= cpu_arch
[j
].type
;
13287 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13291 if (j
>= ARRAY_SIZE (cpu_arch
))
13292 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13295 case OPTION_MMNEMONIC
:
13296 if (strcasecmp (arg
, "att") == 0)
13297 intel_mnemonic
= 0;
13298 else if (strcasecmp (arg
, "intel") == 0)
13299 intel_mnemonic
= 1;
13301 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13304 case OPTION_MSYNTAX
:
13305 if (strcasecmp (arg
, "att") == 0)
13307 else if (strcasecmp (arg
, "intel") == 0)
13310 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13313 case OPTION_MINDEX_REG
:
13314 allow_index_reg
= 1;
13317 case OPTION_MNAKED_REG
:
13318 allow_naked_reg
= 1;
13321 case OPTION_MSSE2AVX
:
13325 case OPTION_MSSE_CHECK
:
13326 if (strcasecmp (arg
, "error") == 0)
13327 sse_check
= check_error
;
13328 else if (strcasecmp (arg
, "warning") == 0)
13329 sse_check
= check_warning
;
13330 else if (strcasecmp (arg
, "none") == 0)
13331 sse_check
= check_none
;
13333 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13336 case OPTION_MOPERAND_CHECK
:
13337 if (strcasecmp (arg
, "error") == 0)
13338 operand_check
= check_error
;
13339 else if (strcasecmp (arg
, "warning") == 0)
13340 operand_check
= check_warning
;
13341 else if (strcasecmp (arg
, "none") == 0)
13342 operand_check
= check_none
;
13344 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13347 case OPTION_MAVXSCALAR
:
13348 if (strcasecmp (arg
, "128") == 0)
13349 avxscalar
= vex128
;
13350 else if (strcasecmp (arg
, "256") == 0)
13351 avxscalar
= vex256
;
13353 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13356 case OPTION_MVEXWIG
:
13357 if (strcmp (arg
, "0") == 0)
13359 else if (strcmp (arg
, "1") == 0)
13362 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13365 case OPTION_MADD_BND_PREFIX
:
13366 add_bnd_prefix
= 1;
13369 case OPTION_MEVEXLIG
:
13370 if (strcmp (arg
, "128") == 0)
13371 evexlig
= evexl128
;
13372 else if (strcmp (arg
, "256") == 0)
13373 evexlig
= evexl256
;
13374 else if (strcmp (arg
, "512") == 0)
13375 evexlig
= evexl512
;
13377 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13380 case OPTION_MEVEXRCIG
:
13381 if (strcmp (arg
, "rne") == 0)
13383 else if (strcmp (arg
, "rd") == 0)
13385 else if (strcmp (arg
, "ru") == 0)
13387 else if (strcmp (arg
, "rz") == 0)
13390 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13393 case OPTION_MEVEXWIG
:
13394 if (strcmp (arg
, "0") == 0)
13396 else if (strcmp (arg
, "1") == 0)
13399 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13402 # if defined (TE_PE) || defined (TE_PEP)
13403 case OPTION_MBIG_OBJ
:
13408 case OPTION_MOMIT_LOCK_PREFIX
:
13409 if (strcasecmp (arg
, "yes") == 0)
13410 omit_lock_prefix
= 1;
13411 else if (strcasecmp (arg
, "no") == 0)
13412 omit_lock_prefix
= 0;
13414 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13417 case OPTION_MFENCE_AS_LOCK_ADD
:
13418 if (strcasecmp (arg
, "yes") == 0)
13420 else if (strcasecmp (arg
, "no") == 0)
13423 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13426 case OPTION_MLFENCE_AFTER_LOAD
:
13427 if (strcasecmp (arg
, "yes") == 0)
13428 lfence_after_load
= 1;
13429 else if (strcasecmp (arg
, "no") == 0)
13430 lfence_after_load
= 0;
13432 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13435 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13436 if (strcasecmp (arg
, "all") == 0)
13438 lfence_before_indirect_branch
= lfence_branch_all
;
13439 if (lfence_before_ret
== lfence_before_ret_none
)
13440 lfence_before_ret
= lfence_before_ret_shl
;
13442 else if (strcasecmp (arg
, "memory") == 0)
13443 lfence_before_indirect_branch
= lfence_branch_memory
;
13444 else if (strcasecmp (arg
, "register") == 0)
13445 lfence_before_indirect_branch
= lfence_branch_register
;
13446 else if (strcasecmp (arg
, "none") == 0)
13447 lfence_before_indirect_branch
= lfence_branch_none
;
13449 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13453 case OPTION_MLFENCE_BEFORE_RET
:
13454 if (strcasecmp (arg
, "or") == 0)
13455 lfence_before_ret
= lfence_before_ret_or
;
13456 else if (strcasecmp (arg
, "not") == 0)
13457 lfence_before_ret
= lfence_before_ret_not
;
13458 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13459 lfence_before_ret
= lfence_before_ret_shl
;
13460 else if (strcasecmp (arg
, "none") == 0)
13461 lfence_before_ret
= lfence_before_ret_none
;
13463 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13467 case OPTION_MRELAX_RELOCATIONS
:
13468 if (strcasecmp (arg
, "yes") == 0)
13469 generate_relax_relocations
= 1;
13470 else if (strcasecmp (arg
, "no") == 0)
13471 generate_relax_relocations
= 0;
13473 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13476 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13479 long int align
= strtoul (arg
, &end
, 0);
13484 align_branch_power
= 0;
13487 else if (align
>= 16)
13490 for (align_power
= 0;
13492 align
>>= 1, align_power
++)
13494 /* Limit alignment power to 31. */
13495 if (align
== 1 && align_power
< 32)
13497 align_branch_power
= align_power
;
13502 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13506 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13509 int align
= strtoul (arg
, &end
, 0);
13510 /* Some processors only support 5 prefixes. */
13511 if (*end
== '\0' && align
>= 0 && align
< 6)
13513 align_branch_prefix_size
= align
;
13516 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13521 case OPTION_MALIGN_BRANCH
:
13523 saved
= xstrdup (arg
);
13527 next
= strchr (type
, '+');
13530 if (strcasecmp (type
, "jcc") == 0)
13531 align_branch
|= align_branch_jcc_bit
;
13532 else if (strcasecmp (type
, "fused") == 0)
13533 align_branch
|= align_branch_fused_bit
;
13534 else if (strcasecmp (type
, "jmp") == 0)
13535 align_branch
|= align_branch_jmp_bit
;
13536 else if (strcasecmp (type
, "call") == 0)
13537 align_branch
|= align_branch_call_bit
;
13538 else if (strcasecmp (type
, "ret") == 0)
13539 align_branch
|= align_branch_ret_bit
;
13540 else if (strcasecmp (type
, "indirect") == 0)
13541 align_branch
|= align_branch_indirect_bit
;
13543 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13546 while (next
!= NULL
);
13550 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13551 align_branch_power
= 5;
13552 align_branch_prefix_size
= 5;
13553 align_branch
= (align_branch_jcc_bit
13554 | align_branch_fused_bit
13555 | align_branch_jmp_bit
);
13558 case OPTION_MAMD64
:
13562 case OPTION_MINTEL64
:
13570 /* Turn off -Os. */
13571 optimize_for_space
= 0;
13573 else if (*arg
== 's')
13575 optimize_for_space
= 1;
13576 /* Turn on all encoding optimizations. */
13577 optimize
= INT_MAX
;
13581 optimize
= atoi (arg
);
13582 /* Turn off -Os. */
13583 optimize_for_space
= 0;
13593 #define MESSAGE_TEMPLATE \
13597 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13598 int *left_p
, const char *name
, int len
)
13600 int size
= sizeof (MESSAGE_TEMPLATE
);
13601 int left
= *left_p
;
13603 /* Reserve 2 spaces for ", " or ",\0" */
13606 /* Check if there is any room. */
13614 p
= mempcpy (p
, name
, len
);
13618 /* Output the current message now and start a new one. */
13621 fprintf (stream
, "%s\n", message
);
13623 left
= size
- (start
- message
) - len
- 2;
13625 gas_assert (left
>= 0);
13627 p
= mempcpy (p
, name
, len
);
13635 show_arch (FILE *stream
, int ext
, int check
)
13637 static char message
[] = MESSAGE_TEMPLATE
;
13638 char *start
= message
+ 27;
13640 int size
= sizeof (MESSAGE_TEMPLATE
);
13647 left
= size
- (start
- message
);
13648 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13650 /* Should it be skipped? */
13651 if (cpu_arch
[j
].skip
)
13654 name
= cpu_arch
[j
].name
;
13655 len
= cpu_arch
[j
].len
;
13658 /* It is an extension. Skip if we aren't asked to show it. */
13669 /* It is an processor. Skip if we show only extension. */
13672 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13674 /* It is an impossible processor - skip. */
13678 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13681 /* Display disabled extensions. */
13683 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13685 name
= cpu_noarch
[j
].name
;
13686 len
= cpu_noarch
[j
].len
;
13687 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13692 fprintf (stream
, "%s\n", message
);
13696 md_show_usage (FILE *stream
)
13698 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13699 fprintf (stream
, _("\
13700 -Qy, -Qn ignored\n\
13701 -V print assembler version number\n\
13704 fprintf (stream
, _("\
13705 -n Do not optimize code alignment\n\
13706 -q quieten some warnings\n"));
13707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13708 fprintf (stream
, _("\
13711 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13712 || defined (TE_PE) || defined (TE_PEP))
13713 fprintf (stream
, _("\
13714 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13716 #ifdef SVR4_COMMENT_CHARS
13717 fprintf (stream
, _("\
13718 --divide do not treat `/' as a comment character\n"));
13720 fprintf (stream
, _("\
13721 --divide ignored\n"));
13723 fprintf (stream
, _("\
13724 -march=CPU[,+EXTENSION...]\n\
13725 generate code for CPU and EXTENSION, CPU is one of:\n"));
13726 show_arch (stream
, 0, 1);
13727 fprintf (stream
, _("\
13728 EXTENSION is combination of:\n"));
13729 show_arch (stream
, 1, 0);
13730 fprintf (stream
, _("\
13731 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13732 show_arch (stream
, 0, 0);
13733 fprintf (stream
, _("\
13734 -msse2avx encode SSE instructions with VEX prefix\n"));
13735 fprintf (stream
, _("\
13736 -msse-check=[none|error|warning] (default: warning)\n\
13737 check SSE instructions\n"));
13738 fprintf (stream
, _("\
13739 -moperand-check=[none|error|warning] (default: warning)\n\
13740 check operand combinations for validity\n"));
13741 fprintf (stream
, _("\
13742 -mavxscalar=[128|256] (default: 128)\n\
13743 encode scalar AVX instructions with specific vector\n\
13745 fprintf (stream
, _("\
13746 -mvexwig=[0|1] (default: 0)\n\
13747 encode VEX instructions with specific VEX.W value\n\
13748 for VEX.W bit ignored instructions\n"));
13749 fprintf (stream
, _("\
13750 -mevexlig=[128|256|512] (default: 128)\n\
13751 encode scalar EVEX instructions with specific vector\n\
13753 fprintf (stream
, _("\
13754 -mevexwig=[0|1] (default: 0)\n\
13755 encode EVEX instructions with specific EVEX.W value\n\
13756 for EVEX.W bit ignored instructions\n"));
13757 fprintf (stream
, _("\
13758 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13759 encode EVEX instructions with specific EVEX.RC value\n\
13760 for SAE-only ignored instructions\n"));
13761 fprintf (stream
, _("\
13762 -mmnemonic=[att|intel] "));
13763 if (SYSV386_COMPAT
)
13764 fprintf (stream
, _("(default: att)\n"));
13766 fprintf (stream
, _("(default: intel)\n"));
13767 fprintf (stream
, _("\
13768 use AT&T/Intel mnemonic\n"));
13769 fprintf (stream
, _("\
13770 -msyntax=[att|intel] (default: att)\n\
13771 use AT&T/Intel syntax\n"));
13772 fprintf (stream
, _("\
13773 -mindex-reg support pseudo index registers\n"));
13774 fprintf (stream
, _("\
13775 -mnaked-reg don't require `%%' prefix for registers\n"));
13776 fprintf (stream
, _("\
13777 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13778 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13779 fprintf (stream
, _("\
13780 -mshared disable branch optimization for shared code\n"));
13781 fprintf (stream
, _("\
13782 -mx86-used-note=[no|yes] "));
13783 if (DEFAULT_X86_USED_NOTE
)
13784 fprintf (stream
, _("(default: yes)\n"));
13786 fprintf (stream
, _("(default: no)\n"));
13787 fprintf (stream
, _("\
13788 generate x86 used ISA and feature properties\n"));
13790 #if defined (TE_PE) || defined (TE_PEP)
13791 fprintf (stream
, _("\
13792 -mbig-obj generate big object files\n"));
13794 fprintf (stream
, _("\
13795 -momit-lock-prefix=[no|yes] (default: no)\n\
13796 strip all lock prefixes\n"));
13797 fprintf (stream
, _("\
13798 -mfence-as-lock-add=[no|yes] (default: no)\n\
13799 encode lfence, mfence and sfence as\n\
13800 lock addl $0x0, (%%{re}sp)\n"));
13801 fprintf (stream
, _("\
13802 -mrelax-relocations=[no|yes] "));
13803 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13804 fprintf (stream
, _("(default: yes)\n"));
13806 fprintf (stream
, _("(default: no)\n"));
13807 fprintf (stream
, _("\
13808 generate relax relocations\n"));
13809 fprintf (stream
, _("\
13810 -malign-branch-boundary=NUM (default: 0)\n\
13811 align branches within NUM byte boundary\n"));
13812 fprintf (stream
, _("\
13813 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13814 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13816 specify types of branches to align\n"));
13817 fprintf (stream
, _("\
13818 -malign-branch-prefix-size=NUM (default: 5)\n\
13819 align branches with NUM prefixes per instruction\n"));
13820 fprintf (stream
, _("\
13821 -mbranches-within-32B-boundaries\n\
13822 align branches within 32 byte boundary\n"));
13823 fprintf (stream
, _("\
13824 -mlfence-after-load=[no|yes] (default: no)\n\
13825 generate lfence after load\n"));
13826 fprintf (stream
, _("\
13827 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13828 generate lfence before indirect near branch\n"));
13829 fprintf (stream
, _("\
13830 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13831 generate lfence before ret\n"));
13832 fprintf (stream
, _("\
13833 -mamd64 accept only AMD64 ISA [default]\n"));
13834 fprintf (stream
, _("\
13835 -mintel64 accept only Intel64 ISA\n"));
13838 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13839 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13840 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13842 /* Pick the target format to use. */
13845 i386_target_format (void)
13847 if (startswith (default_arch
, "x86_64"))
13849 update_code_flag (CODE_64BIT
, 1);
13850 if (default_arch
[6] == '\0')
13851 x86_elf_abi
= X86_64_ABI
;
13853 x86_elf_abi
= X86_64_X32_ABI
;
13855 else if (!strcmp (default_arch
, "i386"))
13856 update_code_flag (CODE_32BIT
, 1);
13857 else if (!strcmp (default_arch
, "iamcu"))
13859 update_code_flag (CODE_32BIT
, 1);
13860 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13862 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13863 cpu_arch_name
= "iamcu";
13864 cpu_sub_arch_name
= NULL
;
13865 cpu_arch_flags
= iamcu_flags
;
13866 cpu_arch_isa
= PROCESSOR_IAMCU
;
13867 cpu_arch_isa_flags
= iamcu_flags
;
13868 if (!cpu_arch_tune_set
)
13870 cpu_arch_tune
= cpu_arch_isa
;
13871 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13874 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13875 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13879 as_fatal (_("unknown architecture"));
13881 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13882 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13883 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13884 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13886 switch (OUTPUT_FLAVOR
)
13888 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13889 case bfd_target_aout_flavour
:
13890 return AOUT_TARGET_FORMAT
;
13892 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13893 # if defined (TE_PE) || defined (TE_PEP)
13894 case bfd_target_coff_flavour
:
13895 if (flag_code
== CODE_64BIT
)
13898 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13900 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13901 # elif defined (TE_GO32)
13902 case bfd_target_coff_flavour
:
13903 return "coff-go32";
13905 case bfd_target_coff_flavour
:
13906 return "coff-i386";
13909 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13910 case bfd_target_elf_flavour
:
13912 const char *format
;
13914 switch (x86_elf_abi
)
13917 format
= ELF_TARGET_FORMAT
;
13919 tls_get_addr
= "___tls_get_addr";
13923 use_rela_relocations
= 1;
13926 tls_get_addr
= "__tls_get_addr";
13928 format
= ELF_TARGET_FORMAT64
;
13930 case X86_64_X32_ABI
:
13931 use_rela_relocations
= 1;
13934 tls_get_addr
= "__tls_get_addr";
13936 disallow_64bit_reloc
= 1;
13937 format
= ELF_TARGET_FORMAT32
;
13940 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13942 if (x86_elf_abi
!= X86_64_ABI
)
13943 as_fatal (_("Intel L1OM is 64bit only"));
13944 return ELF_TARGET_L1OM_FORMAT
;
13946 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13948 if (x86_elf_abi
!= X86_64_ABI
)
13949 as_fatal (_("Intel K1OM is 64bit only"));
13950 return ELF_TARGET_K1OM_FORMAT
;
13952 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13954 if (x86_elf_abi
!= I386_ABI
)
13955 as_fatal (_("Intel MCU is 32bit only"));
13956 return ELF_TARGET_IAMCU_FORMAT
;
13962 #if defined (OBJ_MACH_O)
13963 case bfd_target_mach_o_flavour
:
13964 if (flag_code
== CODE_64BIT
)
13966 use_rela_relocations
= 1;
13968 return "mach-o-x86-64";
13971 return "mach-o-i386";
13979 #endif /* OBJ_MAYBE_ more than one */
13982 md_undefined_symbol (char *name
)
13984 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13985 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13986 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13987 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13991 if (symbol_find (name
))
13992 as_bad (_("GOT already in symbol table"));
13993 GOT_symbol
= symbol_new (name
, undefined_section
,
13994 &zero_address_frag
, 0);
14001 /* Round up a section size to the appropriate boundary. */
14004 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14006 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14007 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14009 /* For a.out, force the section size to be aligned. If we don't do
14010 this, BFD will align it for us, but it will not write out the
14011 final bytes of the section. This may be a bug in BFD, but it is
14012 easier to fix it here since that is how the other a.out targets
14016 align
= bfd_section_alignment (segment
);
14017 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14024 /* On the i386, PC-relative offsets are relative to the start of the
14025 next instruction. That is, the address of the offset, plus its
14026 size, since the offset is always the last part of the insn. */
14029 md_pcrel_from (fixS
*fixP
)
14031 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14037 s_bss (int ignore ATTRIBUTE_UNUSED
)
14041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14043 obj_elf_section_change_hook ();
14045 temp
= get_absolute_expression ();
14046 subseg_set (bss_section
, (subsegT
) temp
);
14047 demand_empty_rest_of_line ();
14052 /* Remember constant directive. */
14055 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14057 if (last_insn
.kind
!= last_insn_directive
14058 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14060 last_insn
.seg
= now_seg
;
14061 last_insn
.kind
= last_insn_directive
;
14062 last_insn
.name
= "constant directive";
14063 last_insn
.file
= as_where (&last_insn
.line
);
14064 if (lfence_before_ret
!= lfence_before_ret_none
)
14066 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14067 as_warn (_("constant directive skips -mlfence-before-ret "
14068 "and -mlfence-before-indirect-branch"));
14070 as_warn (_("constant directive skips -mlfence-before-ret"));
14072 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14073 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14078 i386_validate_fix (fixS
*fixp
)
14080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14081 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14082 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14083 return IS_ELF
&& fixp
->fx_addsy
14084 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14085 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14088 if (fixp
->fx_subsy
)
14090 if (fixp
->fx_subsy
== GOT_symbol
)
14092 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14096 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14097 if (fixp
->fx_tcbit2
)
14098 fixp
->fx_r_type
= (fixp
->fx_tcbit
14099 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14100 : BFD_RELOC_X86_64_GOTPCRELX
);
14103 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14108 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14110 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14112 fixp
->fx_subsy
= 0;
14115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14118 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14119 to section. Since PLT32 relocation must be against symbols,
14120 turn such PLT32 relocation into PC32 relocation. */
14122 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14123 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14124 && symbol_section_p (fixp
->fx_addsy
))
14125 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14128 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14129 && fixp
->fx_tcbit2
)
14130 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14139 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14142 bfd_reloc_code_real_type code
;
14144 switch (fixp
->fx_r_type
)
14146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14149 case BFD_RELOC_SIZE32
:
14150 case BFD_RELOC_SIZE64
:
14152 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14153 && (!fixp
->fx_subsy
14154 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14155 sym
= fixp
->fx_addsy
;
14156 else if (fixp
->fx_subsy
14157 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14158 && (!fixp
->fx_addsy
14159 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14160 sym
= fixp
->fx_subsy
;
14163 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14165 /* Resolve size relocation against local symbol to size of
14166 the symbol plus addend. */
14167 valueT value
= S_GET_SIZE (sym
);
14169 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14170 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14171 if (sym
== fixp
->fx_subsy
)
14174 if (fixp
->fx_addsy
)
14175 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14177 else if (fixp
->fx_subsy
)
14178 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14179 value
+= fixp
->fx_offset
;
14180 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14182 && !fits_in_unsigned_long (value
))
14183 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14184 _("symbol size computation overflow"));
14185 fixp
->fx_addsy
= NULL
;
14186 fixp
->fx_subsy
= NULL
;
14187 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14190 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14193 "unsupported expression involving @size");
14197 /* Fall through. */
14199 case BFD_RELOC_X86_64_PLT32
:
14200 case BFD_RELOC_X86_64_GOT32
:
14201 case BFD_RELOC_X86_64_GOTPCREL
:
14202 case BFD_RELOC_X86_64_GOTPCRELX
:
14203 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14204 case BFD_RELOC_386_PLT32
:
14205 case BFD_RELOC_386_GOT32
:
14206 case BFD_RELOC_386_GOT32X
:
14207 case BFD_RELOC_386_GOTOFF
:
14208 case BFD_RELOC_386_GOTPC
:
14209 case BFD_RELOC_386_TLS_GD
:
14210 case BFD_RELOC_386_TLS_LDM
:
14211 case BFD_RELOC_386_TLS_LDO_32
:
14212 case BFD_RELOC_386_TLS_IE_32
:
14213 case BFD_RELOC_386_TLS_IE
:
14214 case BFD_RELOC_386_TLS_GOTIE
:
14215 case BFD_RELOC_386_TLS_LE_32
:
14216 case BFD_RELOC_386_TLS_LE
:
14217 case BFD_RELOC_386_TLS_GOTDESC
:
14218 case BFD_RELOC_386_TLS_DESC_CALL
:
14219 case BFD_RELOC_X86_64_TLSGD
:
14220 case BFD_RELOC_X86_64_TLSLD
:
14221 case BFD_RELOC_X86_64_DTPOFF32
:
14222 case BFD_RELOC_X86_64_DTPOFF64
:
14223 case BFD_RELOC_X86_64_GOTTPOFF
:
14224 case BFD_RELOC_X86_64_TPOFF32
:
14225 case BFD_RELOC_X86_64_TPOFF64
:
14226 case BFD_RELOC_X86_64_GOTOFF64
:
14227 case BFD_RELOC_X86_64_GOTPC32
:
14228 case BFD_RELOC_X86_64_GOT64
:
14229 case BFD_RELOC_X86_64_GOTPCREL64
:
14230 case BFD_RELOC_X86_64_GOTPC64
:
14231 case BFD_RELOC_X86_64_GOTPLT64
:
14232 case BFD_RELOC_X86_64_PLTOFF64
:
14233 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14234 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14235 case BFD_RELOC_RVA
:
14236 case BFD_RELOC_VTABLE_ENTRY
:
14237 case BFD_RELOC_VTABLE_INHERIT
:
14239 case BFD_RELOC_32_SECREL
:
14241 code
= fixp
->fx_r_type
;
14243 case BFD_RELOC_X86_64_32S
:
14244 if (!fixp
->fx_pcrel
)
14246 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14247 code
= fixp
->fx_r_type
;
14250 /* Fall through. */
14252 if (fixp
->fx_pcrel
)
14254 switch (fixp
->fx_size
)
14257 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14258 _("can not do %d byte pc-relative relocation"),
14260 code
= BFD_RELOC_32_PCREL
;
14262 case 1: code
= BFD_RELOC_8_PCREL
; break;
14263 case 2: code
= BFD_RELOC_16_PCREL
; break;
14264 case 4: code
= BFD_RELOC_32_PCREL
; break;
14266 case 8: code
= BFD_RELOC_64_PCREL
; break;
14272 switch (fixp
->fx_size
)
14275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14276 _("can not do %d byte relocation"),
14278 code
= BFD_RELOC_32
;
14280 case 1: code
= BFD_RELOC_8
; break;
14281 case 2: code
= BFD_RELOC_16
; break;
14282 case 4: code
= BFD_RELOC_32
; break;
14284 case 8: code
= BFD_RELOC_64
; break;
14291 if ((code
== BFD_RELOC_32
14292 || code
== BFD_RELOC_32_PCREL
14293 || code
== BFD_RELOC_X86_64_32S
)
14295 && fixp
->fx_addsy
== GOT_symbol
)
14298 code
= BFD_RELOC_386_GOTPC
;
14300 code
= BFD_RELOC_X86_64_GOTPC32
;
14302 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14304 && fixp
->fx_addsy
== GOT_symbol
)
14306 code
= BFD_RELOC_X86_64_GOTPC64
;
14309 rel
= XNEW (arelent
);
14310 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14311 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14313 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14315 if (!use_rela_relocations
)
14317 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14318 vtable entry to be used in the relocation's section offset. */
14319 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14320 rel
->address
= fixp
->fx_offset
;
14321 #if defined (OBJ_COFF) && defined (TE_PE)
14322 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14323 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14328 /* Use the rela in 64bit mode. */
14331 if (disallow_64bit_reloc
)
14334 case BFD_RELOC_X86_64_DTPOFF64
:
14335 case BFD_RELOC_X86_64_TPOFF64
:
14336 case BFD_RELOC_64_PCREL
:
14337 case BFD_RELOC_X86_64_GOTOFF64
:
14338 case BFD_RELOC_X86_64_GOT64
:
14339 case BFD_RELOC_X86_64_GOTPCREL64
:
14340 case BFD_RELOC_X86_64_GOTPC64
:
14341 case BFD_RELOC_X86_64_GOTPLT64
:
14342 case BFD_RELOC_X86_64_PLTOFF64
:
14343 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14344 _("cannot represent relocation type %s in x32 mode"),
14345 bfd_get_reloc_code_name (code
));
14351 if (!fixp
->fx_pcrel
)
14352 rel
->addend
= fixp
->fx_offset
;
14356 case BFD_RELOC_X86_64_PLT32
:
14357 case BFD_RELOC_X86_64_GOT32
:
14358 case BFD_RELOC_X86_64_GOTPCREL
:
14359 case BFD_RELOC_X86_64_GOTPCRELX
:
14360 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14361 case BFD_RELOC_X86_64_TLSGD
:
14362 case BFD_RELOC_X86_64_TLSLD
:
14363 case BFD_RELOC_X86_64_GOTTPOFF
:
14364 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14365 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14366 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14369 rel
->addend
= (section
->vma
14371 + fixp
->fx_addnumber
14372 + md_pcrel_from (fixp
));
14377 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14378 if (rel
->howto
== NULL
)
14380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14381 _("cannot represent relocation type %s"),
14382 bfd_get_reloc_code_name (code
));
14383 /* Set howto to a garbage value so that we can keep going. */
14384 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14385 gas_assert (rel
->howto
!= NULL
);
14391 #include "tc-i386-intel.c"
14394 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14396 int saved_naked_reg
;
14397 char saved_register_dot
;
14399 saved_naked_reg
= allow_naked_reg
;
14400 allow_naked_reg
= 1;
14401 saved_register_dot
= register_chars
['.'];
14402 register_chars
['.'] = '.';
14403 allow_pseudo_reg
= 1;
14404 expression_and_evaluate (exp
);
14405 allow_pseudo_reg
= 0;
14406 register_chars
['.'] = saved_register_dot
;
14407 allow_naked_reg
= saved_naked_reg
;
14409 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14411 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14413 exp
->X_op
= O_constant
;
14414 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14415 .dw2_regnum
[flag_code
>> 1];
14418 exp
->X_op
= O_illegal
;
14423 tc_x86_frame_initial_instructions (void)
14425 static unsigned int sp_regno
[2];
14427 if (!sp_regno
[flag_code
>> 1])
14429 char *saved_input
= input_line_pointer
;
14430 char sp
[][4] = {"esp", "rsp"};
14433 input_line_pointer
= sp
[flag_code
>> 1];
14434 tc_x86_parse_to_dw2regnum (&exp
);
14435 gas_assert (exp
.X_op
== O_constant
);
14436 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14437 input_line_pointer
= saved_input
;
14440 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14441 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14445 x86_dwarf2_addr_size (void)
14447 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14448 if (x86_elf_abi
== X86_64_X32_ABI
)
14451 return bfd_arch_bits_per_address (stdoutput
) / 8;
14455 i386_elf_section_type (const char *str
, size_t len
)
14457 if (flag_code
== CODE_64BIT
14458 && len
== sizeof ("unwind") - 1
14459 && startswith (str
, "unwind"))
14460 return SHT_X86_64_UNWIND
;
14467 i386_solaris_fix_up_eh_frame (segT sec
)
14469 if (flag_code
== CODE_64BIT
)
14470 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14476 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14480 exp
.X_op
= O_secrel
;
14481 exp
.X_add_symbol
= symbol
;
14482 exp
.X_add_number
= 0;
14483 emit_expr (&exp
, size
);
14487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14488 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14491 x86_64_section_letter (int letter
, const char **ptr_msg
)
14493 if (flag_code
== CODE_64BIT
)
14496 return SHF_X86_64_LARGE
;
14498 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14501 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14506 x86_64_section_word (char *str
, size_t len
)
14508 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14509 return SHF_X86_64_LARGE
;
14515 handle_large_common (int small ATTRIBUTE_UNUSED
)
14517 if (flag_code
!= CODE_64BIT
)
14519 s_comm_internal (0, elf_common_parse
);
14520 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14524 static segT lbss_section
;
14525 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14526 asection
*saved_bss_section
= bss_section
;
14528 if (lbss_section
== NULL
)
14530 flagword applicable
;
14531 segT seg
= now_seg
;
14532 subsegT subseg
= now_subseg
;
14534 /* The .lbss section is for local .largecomm symbols. */
14535 lbss_section
= subseg_new (".lbss", 0);
14536 applicable
= bfd_applicable_section_flags (stdoutput
);
14537 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14538 seg_info (lbss_section
)->bss
= 1;
14540 subseg_set (seg
, subseg
);
14543 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14544 bss_section
= lbss_section
;
14546 s_comm_internal (0, elf_common_parse
);
14548 elf_com_section_ptr
= saved_com_section_ptr
;
14549 bss_section
= saved_bss_section
;
14552 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */