1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* 1 if lfence should be inserted after every load. */
633 static int lfence_after_load
= 0;
635 /* Non-zero if lfence should be inserted before indirect branch. */
636 static enum lfence_before_indirect_branch_kind
638 lfence_branch_none
= 0,
639 lfence_branch_register
,
640 lfence_branch_memory
,
643 lfence_before_indirect_branch
;
645 /* Non-zero if lfence should be inserted before ret. */
646 static enum lfence_before_ret_kind
648 lfence_before_ret_none
= 0,
649 lfence_before_ret_not
,
654 /* Types of previous instruction is .byte or prefix. */
669 /* 1 if the assembler should generate relax relocations. */
671 static int generate_relax_relocations
672 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
674 static enum check_kind
680 sse_check
, operand_check
= check_warning
;
682 /* Non-zero if branches should be aligned within power of 2 boundary. */
683 static int align_branch_power
= 0;
685 /* Types of branches to align. */
686 enum align_branch_kind
688 align_branch_none
= 0,
689 align_branch_jcc
= 1,
690 align_branch_fused
= 2,
691 align_branch_jmp
= 3,
692 align_branch_call
= 4,
693 align_branch_indirect
= 5,
697 /* Type bits of branches to align. */
698 enum align_branch_bit
700 align_branch_jcc_bit
= 1 << align_branch_jcc
,
701 align_branch_fused_bit
= 1 << align_branch_fused
,
702 align_branch_jmp_bit
= 1 << align_branch_jmp
,
703 align_branch_call_bit
= 1 << align_branch_call
,
704 align_branch_indirect_bit
= 1 << align_branch_indirect
,
705 align_branch_ret_bit
= 1 << align_branch_ret
708 static unsigned int align_branch
= (align_branch_jcc_bit
709 | align_branch_fused_bit
710 | align_branch_jmp_bit
);
712 /* Types of condition jump used by macro-fusion. */
715 mf_jcc_jo
= 0, /* base opcode 0x70 */
716 mf_jcc_jc
, /* base opcode 0x72 */
717 mf_jcc_je
, /* base opcode 0x74 */
718 mf_jcc_jna
, /* base opcode 0x76 */
719 mf_jcc_js
, /* base opcode 0x78 */
720 mf_jcc_jp
, /* base opcode 0x7a */
721 mf_jcc_jl
, /* base opcode 0x7c */
722 mf_jcc_jle
, /* base opcode 0x7e */
725 /* Types of compare flag-modifying insntructions used by macro-fusion. */
728 mf_cmp_test_and
, /* test/cmp */
729 mf_cmp_alu_cmp
, /* add/sub/cmp */
730 mf_cmp_incdec
/* inc/dec */
733 /* The maximum padding size for fused jcc. CMP like instruction can
734 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
736 #define MAX_FUSED_JCC_PADDING_SIZE 20
738 /* The maximum number of prefixes added for an instruction. */
739 static unsigned int align_branch_prefix_size
= 5;
742 1. Clear the REX_W bit with register operand if possible.
743 2. Above plus use 128bit vector instruction to clear the full vector
746 static int optimize
= 0;
749 1. Clear the REX_W bit with register operand if possible.
750 2. Above plus use 128bit vector instruction to clear the full vector
752 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
755 static int optimize_for_space
= 0;
757 /* Register prefix used for error message. */
758 static const char *register_prefix
= "%";
760 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
761 leave, push, and pop instructions so that gcc has the same stack
762 frame as in 32 bit mode. */
763 static char stackop_size
= '\0';
765 /* Non-zero to optimize code alignment. */
766 int optimize_align_code
= 1;
768 /* Non-zero to quieten some warnings. */
769 static int quiet_warnings
= 0;
772 static const char *cpu_arch_name
= NULL
;
773 static char *cpu_sub_arch_name
= NULL
;
775 /* CPU feature flags. */
776 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
778 /* If we have selected a cpu we are generating instructions for. */
779 static int cpu_arch_tune_set
= 0;
781 /* Cpu we are generating instructions for. */
782 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
784 /* CPU feature flags of cpu we are generating instructions for. */
785 static i386_cpu_flags cpu_arch_tune_flags
;
787 /* CPU instruction set architecture used. */
788 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of instruction set architecture used. */
791 i386_cpu_flags cpu_arch_isa_flags
;
793 /* If set, conditional jumps are not automatically promoted to handle
794 larger than a byte offset. */
795 static unsigned int no_cond_jump_promotion
= 0;
797 /* Encode SSE instructions with VEX prefix. */
798 static unsigned int sse2avx
;
800 /* Encode scalar AVX instructions with specific vector length. */
807 /* Encode VEX WIG instructions with specific vex.w. */
814 /* Encode scalar EVEX LIG instructions with specific vector length. */
822 /* Encode EVEX WIG instructions with specific evex.w. */
829 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
830 static enum rc_type evexrcig
= rne
;
832 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
833 static symbolS
*GOT_symbol
;
835 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
836 unsigned int x86_dwarf2_return_column
;
838 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
839 int x86_cie_data_alignment
;
841 /* Interface to relax_segment.
842 There are 3 major relax states for 386 jump insns because the
843 different types of jumps add different sizes to frags when we're
844 figuring out what sort of jump to choose to reach a given label.
846 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
847 branches which are handled by md_estimate_size_before_relax() and
848 i386_generic_table_relax_frag(). */
851 #define UNCOND_JUMP 0
853 #define COND_JUMP86 2
854 #define BRANCH_PADDING 3
855 #define BRANCH_PREFIX 4
856 #define FUSED_JCC_PADDING 5
861 #define SMALL16 (SMALL | CODE16)
863 #define BIG16 (BIG | CODE16)
867 #define INLINE __inline__
873 #define ENCODE_RELAX_STATE(type, size) \
874 ((relax_substateT) (((type) << 2) | (size)))
875 #define TYPE_FROM_RELAX_STATE(s) \
877 #define DISP_SIZE_FROM_RELAX_STATE(s) \
878 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
880 /* This table is used by relax_frag to promote short jumps to long
881 ones where necessary. SMALL (short) jumps may be promoted to BIG
882 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
883 don't allow a short jump in a 32 bit code segment to be promoted to
884 a 16 bit offset jump because it's slower (requires data size
885 prefix), and doesn't work, unless the destination is in the bottom
886 64k of the code segment (The top 16 bits of eip are zeroed). */
888 const relax_typeS md_relax_table
[] =
891 1) most positive reach of this state,
892 2) most negative reach of this state,
893 3) how many bytes this mode will have in the variable part of the frag
894 4) which index into the table to try if we can't fit into this one. */
896 /* UNCOND_JUMP states. */
897 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
898 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
899 /* dword jmp adds 4 bytes to frag:
900 0 extra opcode bytes, 4 displacement bytes. */
902 /* word jmp adds 2 byte2 to frag:
903 0 extra opcode bytes, 2 displacement bytes. */
906 /* COND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
909 /* dword conditionals adds 5 bytes to frag:
910 1 extra opcode byte, 4 displacement bytes. */
912 /* word conditionals add 3 bytes to frag:
913 1 extra opcode byte, 2 displacement bytes. */
916 /* COND_JUMP86 states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
922 /* word conditionals add 4 bytes to frag:
923 1 displacement byte and a 3 byte long branch insn. */
927 static const arch_entry cpu_arch
[] =
929 /* Do not replace the first two entries - i386_target_format()
930 relies on them being there in this order. */
931 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
932 CPU_GENERIC32_FLAGS
, 0 },
933 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
934 CPU_GENERIC64_FLAGS
, 0 },
935 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
943 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
945 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
947 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
949 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
951 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
952 CPU_PENTIUMPRO_FLAGS
, 0 },
953 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
957 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
959 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
961 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
962 CPU_NOCONA_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
965 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
967 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
968 CPU_CORE2_FLAGS
, 1 },
969 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
970 CPU_CORE2_FLAGS
, 0 },
971 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
972 CPU_COREI7_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
975 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
977 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
978 CPU_IAMCU_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
981 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
983 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
984 CPU_ATHLON_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
987 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
989 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
991 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
992 CPU_AMDFAM10_FLAGS
, 0 },
993 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
994 CPU_BDVER1_FLAGS
, 0 },
995 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
996 CPU_BDVER2_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
998 CPU_BDVER3_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1000 CPU_BDVER4_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1002 CPU_ZNVER1_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1004 CPU_ZNVER2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1006 CPU_BTVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1008 CPU_BTVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1010 CPU_8087_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1018 CPU_CMOV_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1020 CPU_FXSR_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1026 CPU_SSE2_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1028 CPU_SSE3_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1030 CPU_SSE4A_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1032 CPU_SSSE3_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE4_1_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4_2_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE4_2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512F_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512CD_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512ER_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512PF_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512DQ_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512BW_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512VL_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1059 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1060 CPU_VMFUNC_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1064 CPU_XSAVE_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1066 CPU_XSAVEOPT_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1068 CPU_XSAVEC_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVES_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1074 CPU_PCLMUL_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1076 CPU_PCLMUL_FLAGS
, 1 },
1077 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1078 CPU_FSGSBASE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1080 CPU_RDRND_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1082 CPU_F16C_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1084 CPU_BMI2_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1088 CPU_FMA4_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1091 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1094 CPU_MOVBE_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1096 CPU_CX16_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1100 CPU_LZCNT_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1102 CPU_POPCNT_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1107 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1108 CPU_INVPCID_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1110 CPU_CLFLUSH_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1114 CPU_SYSCALL_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1116 CPU_RDTSCP_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1118 CPU_3DNOW_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1120 CPU_3DNOWA_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1122 CPU_PADLOCK_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1124 CPU_SVME_FLAGS
, 1 },
1125 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1126 CPU_SVME_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1128 CPU_SSE4A_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1131 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1133 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1135 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1138 CPU_RDSEED_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1140 CPU_PRFCHW_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1142 CPU_SMAP_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1148 CPU_CLFLUSHOPT_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1150 CPU_PREFETCHWT1_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1154 CPU_CLWB_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1156 CPU_AVX512IFMA_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1158 CPU_AVX512VBMI_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1160 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_VBMI2_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_VNNI_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_BITALG_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1172 CPU_CLZERO_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1174 CPU_MWAITX_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1176 CPU_OSPKE_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1178 CPU_RDPID_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1180 CPU_PTWRITE_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1183 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1184 CPU_SHSTK_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1186 CPU_GFNI_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1188 CPU_VAES_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1190 CPU_VPCLMULQDQ_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1192 CPU_WBNOINVD_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1194 CPU_PCONFIG_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1196 CPU_WAITPKG_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1198 CPU_CLDEMOTE_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1200 CPU_MOVDIRI_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1202 CPU_MOVDIR64B_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1204 CPU_AVX512_BF16_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1206 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1208 CPU_ENQCMD_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1210 CPU_SERIALIZE_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1212 CPU_RDPRU_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1214 CPU_MCOMMIT_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1216 CPU_SEV_ES_FLAGS
, 0 },
1219 static const noarch_entry cpu_noarch
[] =
1221 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1222 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1223 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1224 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1225 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1226 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1227 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1228 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1229 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1230 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1231 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1232 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1233 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1234 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1235 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1236 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1237 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1238 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1239 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1240 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1241 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1242 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1243 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1253 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1254 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1255 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1256 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1259 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1260 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1264 /* Like s_lcomm_internal in gas/read.c but the alignment string
1265 is allowed to be optional. */
1268 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1275 && *input_line_pointer
== ',')
1277 align
= parse_align (needs_align
- 1);
1279 if (align
== (addressT
) -1)
1294 bss_alloc (symbolP
, size
, align
);
1299 pe_lcomm (int needs_align
)
1301 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1305 const pseudo_typeS md_pseudo_table
[] =
1307 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1308 {"align", s_align_bytes
, 0},
1310 {"align", s_align_ptwo
, 0},
1312 {"arch", set_cpu_arch
, 0},
1316 {"lcomm", pe_lcomm
, 1},
1318 {"ffloat", float_cons
, 'f'},
1319 {"dfloat", float_cons
, 'd'},
1320 {"tfloat", float_cons
, 'x'},
1322 {"slong", signed_cons
, 4},
1323 {"noopt", s_ignore
, 0},
1324 {"optim", s_ignore
, 0},
1325 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1326 {"code16", set_code_flag
, CODE_16BIT
},
1327 {"code32", set_code_flag
, CODE_32BIT
},
1329 {"code64", set_code_flag
, CODE_64BIT
},
1331 {"intel_syntax", set_intel_syntax
, 1},
1332 {"att_syntax", set_intel_syntax
, 0},
1333 {"intel_mnemonic", set_intel_mnemonic
, 1},
1334 {"att_mnemonic", set_intel_mnemonic
, 0},
1335 {"allow_index_reg", set_allow_index_reg
, 1},
1336 {"disallow_index_reg", set_allow_index_reg
, 0},
1337 {"sse_check", set_check
, 0},
1338 {"operand_check", set_check
, 1},
1339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1340 {"largecomm", handle_large_common
, 0},
1342 {"file", dwarf2_directive_file
, 0},
1343 {"loc", dwarf2_directive_loc
, 0},
1344 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1347 {"secrel32", pe_directive_secrel
, 0},
1352 /* For interface with expression (). */
1353 extern char *input_line_pointer
;
1355 /* Hash table for instruction mnemonic lookup. */
1356 static struct hash_control
*op_hash
;
1358 /* Hash table for register lookup. */
1359 static struct hash_control
*reg_hash
;
1361 /* Various efficient no-op patterns for aligning code labels.
1362 Note: Don't try to assemble the instructions in the comments.
1363 0L and 0w are not legal. */
1364 static const unsigned char f32_1
[] =
1366 static const unsigned char f32_2
[] =
1367 {0x66,0x90}; /* xchg %ax,%ax */
1368 static const unsigned char f32_3
[] =
1369 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1370 static const unsigned char f32_4
[] =
1371 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1372 static const unsigned char f32_6
[] =
1373 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1374 static const unsigned char f32_7
[] =
1375 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1376 static const unsigned char f16_3
[] =
1377 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1378 static const unsigned char f16_4
[] =
1379 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1380 static const unsigned char jump_disp8
[] =
1381 {0xeb}; /* jmp disp8 */
1382 static const unsigned char jump32_disp32
[] =
1383 {0xe9}; /* jmp disp32 */
1384 static const unsigned char jump16_disp32
[] =
1385 {0x66,0xe9}; /* jmp disp32 */
1386 /* 32-bit NOPs patterns. */
1387 static const unsigned char *const f32_patt
[] = {
1388 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1390 /* 16-bit NOPs patterns. */
1391 static const unsigned char *const f16_patt
[] = {
1392 f32_1
, f32_2
, f16_3
, f16_4
1394 /* nopl (%[re]ax) */
1395 static const unsigned char alt_3
[] =
1397 /* nopl 0(%[re]ax) */
1398 static const unsigned char alt_4
[] =
1399 {0x0f,0x1f,0x40,0x00};
1400 /* nopl 0(%[re]ax,%[re]ax,1) */
1401 static const unsigned char alt_5
[] =
1402 {0x0f,0x1f,0x44,0x00,0x00};
1403 /* nopw 0(%[re]ax,%[re]ax,1) */
1404 static const unsigned char alt_6
[] =
1405 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1406 /* nopl 0L(%[re]ax) */
1407 static const unsigned char alt_7
[] =
1408 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1409 /* nopl 0L(%[re]ax,%[re]ax,1) */
1410 static const unsigned char alt_8
[] =
1411 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1412 /* nopw 0L(%[re]ax,%[re]ax,1) */
1413 static const unsigned char alt_9
[] =
1414 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1415 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1416 static const unsigned char alt_10
[] =
1417 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1418 /* data16 nopw %cs:0L(%eax,%eax,1) */
1419 static const unsigned char alt_11
[] =
1420 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1421 /* 32-bit and 64-bit NOPs patterns. */
1422 static const unsigned char *const alt_patt
[] = {
1423 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1424 alt_9
, alt_10
, alt_11
1427 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1428 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1431 i386_output_nops (char *where
, const unsigned char *const *patt
,
1432 int count
, int max_single_nop_size
)
1435 /* Place the longer NOP first. */
1438 const unsigned char *nops
;
1440 if (max_single_nop_size
< 1)
1442 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1443 max_single_nop_size
);
1447 nops
= patt
[max_single_nop_size
- 1];
1449 /* Use the smaller one if the requsted one isn't available. */
1452 max_single_nop_size
--;
1453 nops
= patt
[max_single_nop_size
- 1];
1456 last
= count
% max_single_nop_size
;
1459 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1460 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1464 nops
= patt
[last
- 1];
1467 /* Use the smaller one plus one-byte NOP if the needed one
1470 nops
= patt
[last
- 1];
1471 memcpy (where
+ offset
, nops
, last
);
1472 where
[offset
+ last
] = *patt
[0];
1475 memcpy (where
+ offset
, nops
, last
);
1480 fits_in_imm7 (offsetT num
)
1482 return (num
& 0x7f) == num
;
1486 fits_in_imm31 (offsetT num
)
1488 return (num
& 0x7fffffff) == num
;
1491 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1492 single NOP instruction LIMIT. */
1495 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1497 const unsigned char *const *patt
= NULL
;
1498 int max_single_nop_size
;
1499 /* Maximum number of NOPs before switching to jump over NOPs. */
1500 int max_number_of_nops
;
1502 switch (fragP
->fr_type
)
1507 case rs_machine_dependent
:
1508 /* Allow NOP padding for jumps and calls. */
1509 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1510 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1517 /* We need to decide which NOP sequence to use for 32bit and
1518 64bit. When -mtune= is used:
1520 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1521 PROCESSOR_GENERIC32, f32_patt will be used.
1522 2. For the rest, alt_patt will be used.
1524 When -mtune= isn't used, alt_patt will be used if
1525 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1528 When -march= or .arch is used, we can't use anything beyond
1529 cpu_arch_isa_flags. */
1531 if (flag_code
== CODE_16BIT
)
1534 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1535 /* Limit number of NOPs to 2 in 16-bit mode. */
1536 max_number_of_nops
= 2;
1540 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1542 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1543 switch (cpu_arch_tune
)
1545 case PROCESSOR_UNKNOWN
:
1546 /* We use cpu_arch_isa_flags to check if we SHOULD
1547 optimize with nops. */
1548 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1553 case PROCESSOR_PENTIUM4
:
1554 case PROCESSOR_NOCONA
:
1555 case PROCESSOR_CORE
:
1556 case PROCESSOR_CORE2
:
1557 case PROCESSOR_COREI7
:
1558 case PROCESSOR_L1OM
:
1559 case PROCESSOR_K1OM
:
1560 case PROCESSOR_GENERIC64
:
1562 case PROCESSOR_ATHLON
:
1564 case PROCESSOR_AMDFAM10
:
1566 case PROCESSOR_ZNVER
:
1570 case PROCESSOR_I386
:
1571 case PROCESSOR_I486
:
1572 case PROCESSOR_PENTIUM
:
1573 case PROCESSOR_PENTIUMPRO
:
1574 case PROCESSOR_IAMCU
:
1575 case PROCESSOR_GENERIC32
:
1582 switch (fragP
->tc_frag_data
.tune
)
1584 case PROCESSOR_UNKNOWN
:
1585 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1586 PROCESSOR_UNKNOWN. */
1590 case PROCESSOR_I386
:
1591 case PROCESSOR_I486
:
1592 case PROCESSOR_PENTIUM
:
1593 case PROCESSOR_IAMCU
:
1595 case PROCESSOR_ATHLON
:
1597 case PROCESSOR_AMDFAM10
:
1599 case PROCESSOR_ZNVER
:
1601 case PROCESSOR_GENERIC32
:
1602 /* We use cpu_arch_isa_flags to check if we CAN optimize
1604 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1609 case PROCESSOR_PENTIUMPRO
:
1610 case PROCESSOR_PENTIUM4
:
1611 case PROCESSOR_NOCONA
:
1612 case PROCESSOR_CORE
:
1613 case PROCESSOR_CORE2
:
1614 case PROCESSOR_COREI7
:
1615 case PROCESSOR_L1OM
:
1616 case PROCESSOR_K1OM
:
1617 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1622 case PROCESSOR_GENERIC64
:
1628 if (patt
== f32_patt
)
1630 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1631 /* Limit number of NOPs to 2 for older processors. */
1632 max_number_of_nops
= 2;
1636 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1637 /* Limit number of NOPs to 7 for newer processors. */
1638 max_number_of_nops
= 7;
1643 limit
= max_single_nop_size
;
1645 if (fragP
->fr_type
== rs_fill_nop
)
1647 /* Output NOPs for .nop directive. */
1648 if (limit
> max_single_nop_size
)
1650 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1651 _("invalid single nop size: %d "
1652 "(expect within [0, %d])"),
1653 limit
, max_single_nop_size
);
1657 else if (fragP
->fr_type
!= rs_machine_dependent
)
1658 fragP
->fr_var
= count
;
1660 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1662 /* Generate jump over NOPs. */
1663 offsetT disp
= count
- 2;
1664 if (fits_in_imm7 (disp
))
1666 /* Use "jmp disp8" if possible. */
1668 where
[0] = jump_disp8
[0];
1674 unsigned int size_of_jump
;
1676 if (flag_code
== CODE_16BIT
)
1678 where
[0] = jump16_disp32
[0];
1679 where
[1] = jump16_disp32
[1];
1684 where
[0] = jump32_disp32
[0];
1688 count
-= size_of_jump
+ 4;
1689 if (!fits_in_imm31 (count
))
1691 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1692 _("jump over nop padding out of range"));
1696 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1697 where
+= size_of_jump
+ 4;
1701 /* Generate multiple NOPs. */
1702 i386_output_nops (where
, patt
, count
, limit
);
1706 operand_type_all_zero (const union i386_operand_type
*x
)
1708 switch (ARRAY_SIZE(x
->array
))
1719 return !x
->array
[0];
1726 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1728 switch (ARRAY_SIZE(x
->array
))
1744 x
->bitfield
.class = ClassNone
;
1745 x
->bitfield
.instance
= InstanceNone
;
1749 operand_type_equal (const union i386_operand_type
*x
,
1750 const union i386_operand_type
*y
)
1752 switch (ARRAY_SIZE(x
->array
))
1755 if (x
->array
[2] != y
->array
[2])
1759 if (x
->array
[1] != y
->array
[1])
1763 return x
->array
[0] == y
->array
[0];
1771 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1773 switch (ARRAY_SIZE(x
->array
))
1788 return !x
->array
[0];
1795 cpu_flags_equal (const union i386_cpu_flags
*x
,
1796 const union i386_cpu_flags
*y
)
1798 switch (ARRAY_SIZE(x
->array
))
1801 if (x
->array
[3] != y
->array
[3])
1805 if (x
->array
[2] != y
->array
[2])
1809 if (x
->array
[1] != y
->array
[1])
1813 return x
->array
[0] == y
->array
[0];
1821 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1823 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1824 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1827 static INLINE i386_cpu_flags
1828 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1830 switch (ARRAY_SIZE (x
.array
))
1833 x
.array
[3] &= y
.array
[3];
1836 x
.array
[2] &= y
.array
[2];
1839 x
.array
[1] &= y
.array
[1];
1842 x
.array
[0] &= y
.array
[0];
1850 static INLINE i386_cpu_flags
1851 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1853 switch (ARRAY_SIZE (x
.array
))
1856 x
.array
[3] |= y
.array
[3];
1859 x
.array
[2] |= y
.array
[2];
1862 x
.array
[1] |= y
.array
[1];
1865 x
.array
[0] |= y
.array
[0];
1873 static INLINE i386_cpu_flags
1874 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1876 switch (ARRAY_SIZE (x
.array
))
1879 x
.array
[3] &= ~y
.array
[3];
1882 x
.array
[2] &= ~y
.array
[2];
1885 x
.array
[1] &= ~y
.array
[1];
1888 x
.array
[0] &= ~y
.array
[0];
1896 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1898 #define CPU_FLAGS_ARCH_MATCH 0x1
1899 #define CPU_FLAGS_64BIT_MATCH 0x2
1901 #define CPU_FLAGS_PERFECT_MATCH \
1902 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1904 /* Return CPU flags match bits. */
1907 cpu_flags_match (const insn_template
*t
)
1909 i386_cpu_flags x
= t
->cpu_flags
;
1910 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1912 x
.bitfield
.cpu64
= 0;
1913 x
.bitfield
.cpuno64
= 0;
1915 if (cpu_flags_all_zero (&x
))
1917 /* This instruction is available on all archs. */
1918 match
|= CPU_FLAGS_ARCH_MATCH
;
1922 /* This instruction is available only on some archs. */
1923 i386_cpu_flags cpu
= cpu_arch_flags
;
1925 /* AVX512VL is no standalone feature - match it and then strip it. */
1926 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1928 x
.bitfield
.cpuavx512vl
= 0;
1930 cpu
= cpu_flags_and (x
, cpu
);
1931 if (!cpu_flags_all_zero (&cpu
))
1933 if (x
.bitfield
.cpuavx
)
1935 /* We need to check a few extra flags with AVX. */
1936 if (cpu
.bitfield
.cpuavx
1937 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1938 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1939 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1940 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1941 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 else if (x
.bitfield
.cpuavx512f
)
1945 /* We need to check a few extra flags with AVX512F. */
1946 if (cpu
.bitfield
.cpuavx512f
1947 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1948 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1949 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1950 match
|= CPU_FLAGS_ARCH_MATCH
;
1953 match
|= CPU_FLAGS_ARCH_MATCH
;
1959 static INLINE i386_operand_type
1960 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1962 if (x
.bitfield
.class != y
.bitfield
.class)
1963 x
.bitfield
.class = ClassNone
;
1964 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1965 x
.bitfield
.instance
= InstanceNone
;
1967 switch (ARRAY_SIZE (x
.array
))
1970 x
.array
[2] &= y
.array
[2];
1973 x
.array
[1] &= y
.array
[1];
1976 x
.array
[0] &= y
.array
[0];
1984 static INLINE i386_operand_type
1985 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1987 gas_assert (y
.bitfield
.class == ClassNone
);
1988 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1990 switch (ARRAY_SIZE (x
.array
))
1993 x
.array
[2] &= ~y
.array
[2];
1996 x
.array
[1] &= ~y
.array
[1];
1999 x
.array
[0] &= ~y
.array
[0];
2007 static INLINE i386_operand_type
2008 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2010 gas_assert (x
.bitfield
.class == ClassNone
||
2011 y
.bitfield
.class == ClassNone
||
2012 x
.bitfield
.class == y
.bitfield
.class);
2013 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2014 y
.bitfield
.instance
== InstanceNone
||
2015 x
.bitfield
.instance
== y
.bitfield
.instance
);
2017 switch (ARRAY_SIZE (x
.array
))
2020 x
.array
[2] |= y
.array
[2];
2023 x
.array
[1] |= y
.array
[1];
2026 x
.array
[0] |= y
.array
[0];
2034 static INLINE i386_operand_type
2035 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2037 gas_assert (y
.bitfield
.class == ClassNone
);
2038 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2040 switch (ARRAY_SIZE (x
.array
))
2043 x
.array
[2] ^= y
.array
[2];
2046 x
.array
[1] ^= y
.array
[1];
2049 x
.array
[0] ^= y
.array
[0];
2057 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2058 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2059 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2060 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2061 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2062 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2063 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2064 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2065 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2066 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2067 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2068 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2069 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2070 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2071 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2072 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2073 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2084 operand_type_check (i386_operand_type t
, enum operand_type c
)
2089 return t
.bitfield
.class == Reg
;
2092 return (t
.bitfield
.imm8
2096 || t
.bitfield
.imm32s
2097 || t
.bitfield
.imm64
);
2100 return (t
.bitfield
.disp8
2101 || t
.bitfield
.disp16
2102 || t
.bitfield
.disp32
2103 || t
.bitfield
.disp32s
2104 || t
.bitfield
.disp64
);
2107 return (t
.bitfield
.disp8
2108 || t
.bitfield
.disp16
2109 || t
.bitfield
.disp32
2110 || t
.bitfield
.disp32s
2111 || t
.bitfield
.disp64
2112 || t
.bitfield
.baseindex
);
2121 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2122 between operand GIVEN and opeand WANTED for instruction template T. */
2125 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2128 return !((i
.types
[given
].bitfield
.byte
2129 && !t
->operand_types
[wanted
].bitfield
.byte
)
2130 || (i
.types
[given
].bitfield
.word
2131 && !t
->operand_types
[wanted
].bitfield
.word
)
2132 || (i
.types
[given
].bitfield
.dword
2133 && !t
->operand_types
[wanted
].bitfield
.dword
)
2134 || (i
.types
[given
].bitfield
.qword
2135 && !t
->operand_types
[wanted
].bitfield
.qword
)
2136 || (i
.types
[given
].bitfield
.tbyte
2137 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2140 /* Return 1 if there is no conflict in SIMD register between operand
2141 GIVEN and opeand WANTED for instruction template T. */
2144 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2147 return !((i
.types
[given
].bitfield
.xmmword
2148 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2149 || (i
.types
[given
].bitfield
.ymmword
2150 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2151 || (i
.types
[given
].bitfield
.zmmword
2152 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2155 /* Return 1 if there is no conflict in any size between operand GIVEN
2156 and opeand WANTED for instruction template T. */
2159 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2162 return (match_operand_size (t
, wanted
, given
)
2163 && !((i
.types
[given
].bitfield
.unspecified
2165 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2166 || (i
.types
[given
].bitfield
.fword
2167 && !t
->operand_types
[wanted
].bitfield
.fword
)
2168 /* For scalar opcode templates to allow register and memory
2169 operands at the same time, some special casing is needed
2170 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2171 down-conversion vpmov*. */
2172 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2173 && t
->operand_types
[wanted
].bitfield
.byte
2174 + t
->operand_types
[wanted
].bitfield
.word
2175 + t
->operand_types
[wanted
].bitfield
.dword
2176 + t
->operand_types
[wanted
].bitfield
.qword
2177 > !!t
->opcode_modifier
.broadcast
)
2178 ? (i
.types
[given
].bitfield
.xmmword
2179 || i
.types
[given
].bitfield
.ymmword
2180 || i
.types
[given
].bitfield
.zmmword
)
2181 : !match_simd_size(t
, wanted
, given
))));
2184 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2185 operands for instruction template T, and it has MATCH_REVERSE set if there
2186 is no size conflict on any operands for the template with operands reversed
2187 (and the template allows for reversing in the first place). */
2189 #define MATCH_STRAIGHT 1
2190 #define MATCH_REVERSE 2
2192 static INLINE
unsigned int
2193 operand_size_match (const insn_template
*t
)
2195 unsigned int j
, match
= MATCH_STRAIGHT
;
2197 /* Don't check non-absolute jump instructions. */
2198 if (t
->opcode_modifier
.jump
2199 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2202 /* Check memory and accumulator operand size. */
2203 for (j
= 0; j
< i
.operands
; j
++)
2205 if (i
.types
[j
].bitfield
.class != Reg
2206 && i
.types
[j
].bitfield
.class != RegSIMD
2207 && t
->opcode_modifier
.anysize
)
2210 if (t
->operand_types
[j
].bitfield
.class == Reg
2211 && !match_operand_size (t
, j
, j
))
2217 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2218 && !match_simd_size (t
, j
, j
))
2224 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2225 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2231 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2238 if (!t
->opcode_modifier
.d
)
2242 i
.error
= operand_size_mismatch
;
2246 /* Check reverse. */
2247 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2249 for (j
= 0; j
< i
.operands
; j
++)
2251 unsigned int given
= i
.operands
- j
- 1;
2253 if (t
->operand_types
[j
].bitfield
.class == Reg
2254 && !match_operand_size (t
, j
, given
))
2257 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2258 && !match_simd_size (t
, j
, given
))
2261 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2262 && (!match_operand_size (t
, j
, given
)
2263 || !match_simd_size (t
, j
, given
)))
2266 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2270 return match
| MATCH_REVERSE
;
2274 operand_type_match (i386_operand_type overlap
,
2275 i386_operand_type given
)
2277 i386_operand_type temp
= overlap
;
2279 temp
.bitfield
.unspecified
= 0;
2280 temp
.bitfield
.byte
= 0;
2281 temp
.bitfield
.word
= 0;
2282 temp
.bitfield
.dword
= 0;
2283 temp
.bitfield
.fword
= 0;
2284 temp
.bitfield
.qword
= 0;
2285 temp
.bitfield
.tbyte
= 0;
2286 temp
.bitfield
.xmmword
= 0;
2287 temp
.bitfield
.ymmword
= 0;
2288 temp
.bitfield
.zmmword
= 0;
2289 if (operand_type_all_zero (&temp
))
2292 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2296 i
.error
= operand_type_mismatch
;
2300 /* If given types g0 and g1 are registers they must be of the same type
2301 unless the expected operand type register overlap is null.
2302 Some Intel syntax memory operand size checking also happens here. */
2305 operand_type_register_match (i386_operand_type g0
,
2306 i386_operand_type t0
,
2307 i386_operand_type g1
,
2308 i386_operand_type t1
)
2310 if (g0
.bitfield
.class != Reg
2311 && g0
.bitfield
.class != RegSIMD
2312 && (!operand_type_check (g0
, anymem
)
2313 || g0
.bitfield
.unspecified
2314 || (t0
.bitfield
.class != Reg
2315 && t0
.bitfield
.class != RegSIMD
)))
2318 if (g1
.bitfield
.class != Reg
2319 && g1
.bitfield
.class != RegSIMD
2320 && (!operand_type_check (g1
, anymem
)
2321 || g1
.bitfield
.unspecified
2322 || (t1
.bitfield
.class != Reg
2323 && t1
.bitfield
.class != RegSIMD
)))
2326 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2327 && g0
.bitfield
.word
== g1
.bitfield
.word
2328 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2329 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2330 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2331 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2332 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2335 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2336 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2337 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2338 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2339 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2340 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2341 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2344 i
.error
= register_type_mismatch
;
2349 static INLINE
unsigned int
2350 register_number (const reg_entry
*r
)
2352 unsigned int nr
= r
->reg_num
;
2354 if (r
->reg_flags
& RegRex
)
2357 if (r
->reg_flags
& RegVRex
)
2363 static INLINE
unsigned int
2364 mode_from_disp_size (i386_operand_type t
)
2366 if (t
.bitfield
.disp8
)
2368 else if (t
.bitfield
.disp16
2369 || t
.bitfield
.disp32
2370 || t
.bitfield
.disp32s
)
2377 fits_in_signed_byte (addressT num
)
2379 return num
+ 0x80 <= 0xff;
2383 fits_in_unsigned_byte (addressT num
)
2389 fits_in_unsigned_word (addressT num
)
2391 return num
<= 0xffff;
2395 fits_in_signed_word (addressT num
)
2397 return num
+ 0x8000 <= 0xffff;
2401 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2406 return num
+ 0x80000000 <= 0xffffffff;
2408 } /* fits_in_signed_long() */
2411 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2416 return num
<= 0xffffffff;
2418 } /* fits_in_unsigned_long() */
2421 fits_in_disp8 (offsetT num
)
2423 int shift
= i
.memshift
;
2429 mask
= (1 << shift
) - 1;
2431 /* Return 0 if NUM isn't properly aligned. */
2435 /* Check if NUM will fit in 8bit after shift. */
2436 return fits_in_signed_byte (num
>> shift
);
2440 fits_in_imm4 (offsetT num
)
2442 return (num
& 0xf) == num
;
2445 static i386_operand_type
2446 smallest_imm_type (offsetT num
)
2448 i386_operand_type t
;
2450 operand_type_set (&t
, 0);
2451 t
.bitfield
.imm64
= 1;
2453 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2455 /* This code is disabled on the 486 because all the Imm1 forms
2456 in the opcode table are slower on the i486. They're the
2457 versions with the implicitly specified single-position
2458 displacement, which has another syntax if you really want to
2460 t
.bitfield
.imm1
= 1;
2461 t
.bitfield
.imm8
= 1;
2462 t
.bitfield
.imm8s
= 1;
2463 t
.bitfield
.imm16
= 1;
2464 t
.bitfield
.imm32
= 1;
2465 t
.bitfield
.imm32s
= 1;
2467 else if (fits_in_signed_byte (num
))
2469 t
.bitfield
.imm8
= 1;
2470 t
.bitfield
.imm8s
= 1;
2471 t
.bitfield
.imm16
= 1;
2472 t
.bitfield
.imm32
= 1;
2473 t
.bitfield
.imm32s
= 1;
2475 else if (fits_in_unsigned_byte (num
))
2477 t
.bitfield
.imm8
= 1;
2478 t
.bitfield
.imm16
= 1;
2479 t
.bitfield
.imm32
= 1;
2480 t
.bitfield
.imm32s
= 1;
2482 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2484 t
.bitfield
.imm16
= 1;
2485 t
.bitfield
.imm32
= 1;
2486 t
.bitfield
.imm32s
= 1;
2488 else if (fits_in_signed_long (num
))
2490 t
.bitfield
.imm32
= 1;
2491 t
.bitfield
.imm32s
= 1;
2493 else if (fits_in_unsigned_long (num
))
2494 t
.bitfield
.imm32
= 1;
2500 offset_in_range (offsetT val
, int size
)
2506 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2507 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2508 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2510 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2516 /* If BFD64, sign extend val for 32bit address mode. */
2517 if (flag_code
!= CODE_64BIT
2518 || i
.prefix
[ADDR_PREFIX
])
2519 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2520 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2523 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2525 char buf1
[40], buf2
[40];
2527 sprint_value (buf1
, val
);
2528 sprint_value (buf2
, val
& mask
);
2529 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2544 a. PREFIX_EXIST if attempting to add a prefix where one from the
2545 same class already exists.
2546 b. PREFIX_LOCK if lock prefix is added.
2547 c. PREFIX_REP if rep/repne prefix is added.
2548 d. PREFIX_DS if ds prefix is added.
2549 e. PREFIX_OTHER if other prefix is added.
2552 static enum PREFIX_GROUP
2553 add_prefix (unsigned int prefix
)
2555 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2558 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2559 && flag_code
== CODE_64BIT
)
2561 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2562 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2563 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2564 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2575 case DS_PREFIX_OPCODE
:
2578 case CS_PREFIX_OPCODE
:
2579 case ES_PREFIX_OPCODE
:
2580 case FS_PREFIX_OPCODE
:
2581 case GS_PREFIX_OPCODE
:
2582 case SS_PREFIX_OPCODE
:
2586 case REPNE_PREFIX_OPCODE
:
2587 case REPE_PREFIX_OPCODE
:
2592 case LOCK_PREFIX_OPCODE
:
2601 case ADDR_PREFIX_OPCODE
:
2605 case DATA_PREFIX_OPCODE
:
2609 if (i
.prefix
[q
] != 0)
2617 i
.prefix
[q
] |= prefix
;
2620 as_bad (_("same type of prefix used twice"));
2626 update_code_flag (int value
, int check
)
2628 PRINTF_LIKE ((*as_error
));
2630 flag_code
= (enum flag_code
) value
;
2631 if (flag_code
== CODE_64BIT
)
2633 cpu_arch_flags
.bitfield
.cpu64
= 1;
2634 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2638 cpu_arch_flags
.bitfield
.cpu64
= 0;
2639 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2641 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2644 as_error
= as_fatal
;
2647 (*as_error
) (_("64bit mode not supported on `%s'."),
2648 cpu_arch_name
? cpu_arch_name
: default_arch
);
2650 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2653 as_error
= as_fatal
;
2656 (*as_error
) (_("32bit mode not supported on `%s'."),
2657 cpu_arch_name
? cpu_arch_name
: default_arch
);
2659 stackop_size
= '\0';
2663 set_code_flag (int value
)
2665 update_code_flag (value
, 0);
2669 set_16bit_gcc_code_flag (int new_code_flag
)
2671 flag_code
= (enum flag_code
) new_code_flag
;
2672 if (flag_code
!= CODE_16BIT
)
2674 cpu_arch_flags
.bitfield
.cpu64
= 0;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2676 stackop_size
= LONG_MNEM_SUFFIX
;
2680 set_intel_syntax (int syntax_flag
)
2682 /* Find out if register prefixing is specified. */
2683 int ask_naked_reg
= 0;
2686 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2689 int e
= get_symbol_name (&string
);
2691 if (strcmp (string
, "prefix") == 0)
2693 else if (strcmp (string
, "noprefix") == 0)
2696 as_bad (_("bad argument to syntax directive."));
2697 (void) restore_line_pointer (e
);
2699 demand_empty_rest_of_line ();
2701 intel_syntax
= syntax_flag
;
2703 if (ask_naked_reg
== 0)
2704 allow_naked_reg
= (intel_syntax
2705 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2707 allow_naked_reg
= (ask_naked_reg
< 0);
2709 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2711 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2712 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2713 register_prefix
= allow_naked_reg
? "" : "%";
2717 set_intel_mnemonic (int mnemonic_flag
)
2719 intel_mnemonic
= mnemonic_flag
;
2723 set_allow_index_reg (int flag
)
2725 allow_index_reg
= flag
;
2729 set_check (int what
)
2731 enum check_kind
*kind
;
2736 kind
= &operand_check
;
2747 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2750 int e
= get_symbol_name (&string
);
2752 if (strcmp (string
, "none") == 0)
2754 else if (strcmp (string
, "warning") == 0)
2755 *kind
= check_warning
;
2756 else if (strcmp (string
, "error") == 0)
2757 *kind
= check_error
;
2759 as_bad (_("bad argument to %s_check directive."), str
);
2760 (void) restore_line_pointer (e
);
2763 as_bad (_("missing argument for %s_check directive"), str
);
2765 demand_empty_rest_of_line ();
2769 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2770 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2773 static const char *arch
;
2775 /* Intel LIOM is only supported on ELF. */
2781 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2782 use default_arch. */
2783 arch
= cpu_arch_name
;
2785 arch
= default_arch
;
2788 /* If we are targeting Intel MCU, we must enable it. */
2789 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2790 || new_flag
.bitfield
.cpuiamcu
)
2793 /* If we are targeting Intel L1OM, we must enable it. */
2794 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2795 || new_flag
.bitfield
.cpul1om
)
2798 /* If we are targeting Intel K1OM, we must enable it. */
2799 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2800 || new_flag
.bitfield
.cpuk1om
)
2803 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2808 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2812 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2815 int e
= get_symbol_name (&string
);
2817 i386_cpu_flags flags
;
2819 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2821 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2823 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2827 cpu_arch_name
= cpu_arch
[j
].name
;
2828 cpu_sub_arch_name
= NULL
;
2829 cpu_arch_flags
= cpu_arch
[j
].flags
;
2830 if (flag_code
== CODE_64BIT
)
2832 cpu_arch_flags
.bitfield
.cpu64
= 1;
2833 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2837 cpu_arch_flags
.bitfield
.cpu64
= 0;
2838 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2840 cpu_arch_isa
= cpu_arch
[j
].type
;
2841 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2842 if (!cpu_arch_tune_set
)
2844 cpu_arch_tune
= cpu_arch_isa
;
2845 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2850 flags
= cpu_flags_or (cpu_arch_flags
,
2853 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2855 if (cpu_sub_arch_name
)
2857 char *name
= cpu_sub_arch_name
;
2858 cpu_sub_arch_name
= concat (name
,
2860 (const char *) NULL
);
2864 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2865 cpu_arch_flags
= flags
;
2866 cpu_arch_isa_flags
= flags
;
2870 = cpu_flags_or (cpu_arch_isa_flags
,
2872 (void) restore_line_pointer (e
);
2873 demand_empty_rest_of_line ();
2878 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2880 /* Disable an ISA extension. */
2881 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2882 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2884 flags
= cpu_flags_and_not (cpu_arch_flags
,
2885 cpu_noarch
[j
].flags
);
2886 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2888 if (cpu_sub_arch_name
)
2890 char *name
= cpu_sub_arch_name
;
2891 cpu_sub_arch_name
= concat (name
, string
,
2892 (const char *) NULL
);
2896 cpu_sub_arch_name
= xstrdup (string
);
2897 cpu_arch_flags
= flags
;
2898 cpu_arch_isa_flags
= flags
;
2900 (void) restore_line_pointer (e
);
2901 demand_empty_rest_of_line ();
2905 j
= ARRAY_SIZE (cpu_arch
);
2908 if (j
>= ARRAY_SIZE (cpu_arch
))
2909 as_bad (_("no such architecture: `%s'"), string
);
2911 *input_line_pointer
= e
;
2914 as_bad (_("missing cpu architecture"));
2916 no_cond_jump_promotion
= 0;
2917 if (*input_line_pointer
== ','
2918 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2923 ++input_line_pointer
;
2924 e
= get_symbol_name (&string
);
2926 if (strcmp (string
, "nojumps") == 0)
2927 no_cond_jump_promotion
= 1;
2928 else if (strcmp (string
, "jumps") == 0)
2931 as_bad (_("no such architecture modifier: `%s'"), string
);
2933 (void) restore_line_pointer (e
);
2936 demand_empty_rest_of_line ();
2939 enum bfd_architecture
2942 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2944 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2945 || flag_code
!= CODE_64BIT
)
2946 as_fatal (_("Intel L1OM is 64bit ELF only"));
2947 return bfd_arch_l1om
;
2949 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2951 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2952 || flag_code
!= CODE_64BIT
)
2953 as_fatal (_("Intel K1OM is 64bit ELF only"));
2954 return bfd_arch_k1om
;
2956 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2958 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2959 || flag_code
== CODE_64BIT
)
2960 as_fatal (_("Intel MCU is 32bit ELF only"));
2961 return bfd_arch_iamcu
;
2964 return bfd_arch_i386
;
2970 if (!strncmp (default_arch
, "x86_64", 6))
2972 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2974 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2975 || default_arch
[6] != '\0')
2976 as_fatal (_("Intel L1OM is 64bit ELF only"));
2977 return bfd_mach_l1om
;
2979 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2981 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2982 || default_arch
[6] != '\0')
2983 as_fatal (_("Intel K1OM is 64bit ELF only"));
2984 return bfd_mach_k1om
;
2986 else if (default_arch
[6] == '\0')
2987 return bfd_mach_x86_64
;
2989 return bfd_mach_x64_32
;
2991 else if (!strcmp (default_arch
, "i386")
2992 || !strcmp (default_arch
, "iamcu"))
2994 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2996 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2997 as_fatal (_("Intel MCU is 32bit ELF only"));
2998 return bfd_mach_i386_iamcu
;
3001 return bfd_mach_i386_i386
;
3004 as_fatal (_("unknown architecture"));
3010 const char *hash_err
;
3012 /* Support pseudo prefixes like {disp32}. */
3013 lex_type
['{'] = LEX_BEGIN_NAME
;
3015 /* Initialize op_hash hash table. */
3016 op_hash
= hash_new ();
3019 const insn_template
*optab
;
3020 templates
*core_optab
;
3022 /* Setup for loop. */
3024 core_optab
= XNEW (templates
);
3025 core_optab
->start
= optab
;
3030 if (optab
->name
== NULL
3031 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3033 /* different name --> ship out current template list;
3034 add to hash table; & begin anew. */
3035 core_optab
->end
= optab
;
3036 hash_err
= hash_insert (op_hash
,
3038 (void *) core_optab
);
3041 as_fatal (_("can't hash %s: %s"),
3045 if (optab
->name
== NULL
)
3047 core_optab
= XNEW (templates
);
3048 core_optab
->start
= optab
;
3053 /* Initialize reg_hash hash table. */
3054 reg_hash
= hash_new ();
3056 const reg_entry
*regtab
;
3057 unsigned int regtab_size
= i386_regtab_size
;
3059 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3061 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3063 as_fatal (_("can't hash %s: %s"),
3069 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3074 for (c
= 0; c
< 256; c
++)
3079 mnemonic_chars
[c
] = c
;
3080 register_chars
[c
] = c
;
3081 operand_chars
[c
] = c
;
3083 else if (ISLOWER (c
))
3085 mnemonic_chars
[c
] = c
;
3086 register_chars
[c
] = c
;
3087 operand_chars
[c
] = c
;
3089 else if (ISUPPER (c
))
3091 mnemonic_chars
[c
] = TOLOWER (c
);
3092 register_chars
[c
] = mnemonic_chars
[c
];
3093 operand_chars
[c
] = c
;
3095 else if (c
== '{' || c
== '}')
3097 mnemonic_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3101 if (ISALPHA (c
) || ISDIGIT (c
))
3102 identifier_chars
[c
] = c
;
3105 identifier_chars
[c
] = c
;
3106 operand_chars
[c
] = c
;
3111 identifier_chars
['@'] = '@';
3114 identifier_chars
['?'] = '?';
3115 operand_chars
['?'] = '?';
3117 digit_chars
['-'] = '-';
3118 mnemonic_chars
['_'] = '_';
3119 mnemonic_chars
['-'] = '-';
3120 mnemonic_chars
['.'] = '.';
3121 identifier_chars
['_'] = '_';
3122 identifier_chars
['.'] = '.';
3124 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3125 operand_chars
[(unsigned char) *p
] = *p
;
3128 if (flag_code
== CODE_64BIT
)
3130 #if defined (OBJ_COFF) && defined (TE_PE)
3131 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3134 x86_dwarf2_return_column
= 16;
3136 x86_cie_data_alignment
= -8;
3140 x86_dwarf2_return_column
= 8;
3141 x86_cie_data_alignment
= -4;
3144 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3145 can be turned into BRANCH_PREFIX frag. */
3146 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3151 i386_print_statistics (FILE *file
)
3153 hash_print_statistics (file
, "i386 opcode", op_hash
);
3154 hash_print_statistics (file
, "i386 register", reg_hash
);
3159 /* Debugging routines for md_assemble. */
3160 static void pte (insn_template
*);
3161 static void pt (i386_operand_type
);
3162 static void pe (expressionS
*);
3163 static void ps (symbolS
*);
3166 pi (const char *line
, i386_insn
*x
)
3170 fprintf (stdout
, "%s: template ", line
);
3172 fprintf (stdout
, " address: base %s index %s scale %x\n",
3173 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3174 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3175 x
->log2_scale_factor
);
3176 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3177 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3178 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3179 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3180 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3181 (x
->rex
& REX_W
) != 0,
3182 (x
->rex
& REX_R
) != 0,
3183 (x
->rex
& REX_X
) != 0,
3184 (x
->rex
& REX_B
) != 0);
3185 for (j
= 0; j
< x
->operands
; j
++)
3187 fprintf (stdout
, " #%d: ", j
+ 1);
3189 fprintf (stdout
, "\n");
3190 if (x
->types
[j
].bitfield
.class == Reg
3191 || x
->types
[j
].bitfield
.class == RegMMX
3192 || x
->types
[j
].bitfield
.class == RegSIMD
3193 || x
->types
[j
].bitfield
.class == SReg
3194 || x
->types
[j
].bitfield
.class == RegCR
3195 || x
->types
[j
].bitfield
.class == RegDR
3196 || x
->types
[j
].bitfield
.class == RegTR
)
3197 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3198 if (operand_type_check (x
->types
[j
], imm
))
3200 if (operand_type_check (x
->types
[j
], disp
))
3201 pe (x
->op
[j
].disps
);
3206 pte (insn_template
*t
)
3209 fprintf (stdout
, " %d operands ", t
->operands
);
3210 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3211 if (t
->extension_opcode
!= None
)
3212 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3213 if (t
->opcode_modifier
.d
)
3214 fprintf (stdout
, "D");
3215 if (t
->opcode_modifier
.w
)
3216 fprintf (stdout
, "W");
3217 fprintf (stdout
, "\n");
3218 for (j
= 0; j
< t
->operands
; j
++)
3220 fprintf (stdout
, " #%d type ", j
+ 1);
3221 pt (t
->operand_types
[j
]);
3222 fprintf (stdout
, "\n");
3229 fprintf (stdout
, " operation %d\n", e
->X_op
);
3230 fprintf (stdout
, " add_number %ld (%lx)\n",
3231 (long) e
->X_add_number
, (long) e
->X_add_number
);
3232 if (e
->X_add_symbol
)
3234 fprintf (stdout
, " add_symbol ");
3235 ps (e
->X_add_symbol
);
3236 fprintf (stdout
, "\n");
3240 fprintf (stdout
, " op_symbol ");
3241 ps (e
->X_op_symbol
);
3242 fprintf (stdout
, "\n");
3249 fprintf (stdout
, "%s type %s%s",
3251 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3252 segment_name (S_GET_SEGMENT (s
)));
3255 static struct type_name
3257 i386_operand_type mask
;
3260 const type_names
[] =
3262 { OPERAND_TYPE_REG8
, "r8" },
3263 { OPERAND_TYPE_REG16
, "r16" },
3264 { OPERAND_TYPE_REG32
, "r32" },
3265 { OPERAND_TYPE_REG64
, "r64" },
3266 { OPERAND_TYPE_ACC8
, "acc8" },
3267 { OPERAND_TYPE_ACC16
, "acc16" },
3268 { OPERAND_TYPE_ACC32
, "acc32" },
3269 { OPERAND_TYPE_ACC64
, "acc64" },
3270 { OPERAND_TYPE_IMM8
, "i8" },
3271 { OPERAND_TYPE_IMM8
, "i8s" },
3272 { OPERAND_TYPE_IMM16
, "i16" },
3273 { OPERAND_TYPE_IMM32
, "i32" },
3274 { OPERAND_TYPE_IMM32S
, "i32s" },
3275 { OPERAND_TYPE_IMM64
, "i64" },
3276 { OPERAND_TYPE_IMM1
, "i1" },
3277 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3278 { OPERAND_TYPE_DISP8
, "d8" },
3279 { OPERAND_TYPE_DISP16
, "d16" },
3280 { OPERAND_TYPE_DISP32
, "d32" },
3281 { OPERAND_TYPE_DISP32S
, "d32s" },
3282 { OPERAND_TYPE_DISP64
, "d64" },
3283 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3284 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3285 { OPERAND_TYPE_CONTROL
, "control reg" },
3286 { OPERAND_TYPE_TEST
, "test reg" },
3287 { OPERAND_TYPE_DEBUG
, "debug reg" },
3288 { OPERAND_TYPE_FLOATREG
, "FReg" },
3289 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3290 { OPERAND_TYPE_SREG
, "SReg" },
3291 { OPERAND_TYPE_REGMMX
, "rMMX" },
3292 { OPERAND_TYPE_REGXMM
, "rXMM" },
3293 { OPERAND_TYPE_REGYMM
, "rYMM" },
3294 { OPERAND_TYPE_REGZMM
, "rZMM" },
3295 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3299 pt (i386_operand_type t
)
3302 i386_operand_type a
;
3304 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3306 a
= operand_type_and (t
, type_names
[j
].mask
);
3307 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3308 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3313 #endif /* DEBUG386 */
3315 static bfd_reloc_code_real_type
3316 reloc (unsigned int size
,
3319 bfd_reloc_code_real_type other
)
3321 if (other
!= NO_RELOC
)
3323 reloc_howto_type
*rel
;
3328 case BFD_RELOC_X86_64_GOT32
:
3329 return BFD_RELOC_X86_64_GOT64
;
3331 case BFD_RELOC_X86_64_GOTPLT64
:
3332 return BFD_RELOC_X86_64_GOTPLT64
;
3334 case BFD_RELOC_X86_64_PLTOFF64
:
3335 return BFD_RELOC_X86_64_PLTOFF64
;
3337 case BFD_RELOC_X86_64_GOTPC32
:
3338 other
= BFD_RELOC_X86_64_GOTPC64
;
3340 case BFD_RELOC_X86_64_GOTPCREL
:
3341 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3343 case BFD_RELOC_X86_64_TPOFF32
:
3344 other
= BFD_RELOC_X86_64_TPOFF64
;
3346 case BFD_RELOC_X86_64_DTPOFF32
:
3347 other
= BFD_RELOC_X86_64_DTPOFF64
;
3353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3354 if (other
== BFD_RELOC_SIZE32
)
3357 other
= BFD_RELOC_SIZE64
;
3360 as_bad (_("there are no pc-relative size relocations"));
3366 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3367 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3370 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3372 as_bad (_("unknown relocation (%u)"), other
);
3373 else if (size
!= bfd_get_reloc_size (rel
))
3374 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3375 bfd_get_reloc_size (rel
),
3377 else if (pcrel
&& !rel
->pc_relative
)
3378 as_bad (_("non-pc-relative relocation for pc-relative field"));
3379 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3381 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3383 as_bad (_("relocated field and relocation type differ in signedness"));
3392 as_bad (_("there are no unsigned pc-relative relocations"));
3395 case 1: return BFD_RELOC_8_PCREL
;
3396 case 2: return BFD_RELOC_16_PCREL
;
3397 case 4: return BFD_RELOC_32_PCREL
;
3398 case 8: return BFD_RELOC_64_PCREL
;
3400 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3407 case 4: return BFD_RELOC_X86_64_32S
;
3412 case 1: return BFD_RELOC_8
;
3413 case 2: return BFD_RELOC_16
;
3414 case 4: return BFD_RELOC_32
;
3415 case 8: return BFD_RELOC_64
;
3417 as_bad (_("cannot do %s %u byte relocation"),
3418 sign
> 0 ? "signed" : "unsigned", size
);
3424 /* Here we decide which fixups can be adjusted to make them relative to
3425 the beginning of the section instead of the symbol. Basically we need
3426 to make sure that the dynamic relocations are done correctly, so in
3427 some cases we force the original symbol to be used. */
3430 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3436 /* Don't adjust pc-relative references to merge sections in 64-bit
3438 if (use_rela_relocations
3439 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3443 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3444 and changed later by validate_fix. */
3445 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3446 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3449 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3450 for size relocations. */
3451 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3452 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3453 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3454 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3455 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3456 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3457 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3458 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3459 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3461 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3466 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3467 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3468 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3469 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3480 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3481 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3488 intel_float_operand (const char *mnemonic
)
3490 /* Note that the value returned is meaningful only for opcodes with (memory)
3491 operands, hence the code here is free to improperly handle opcodes that
3492 have no operands (for better performance and smaller code). */
3494 if (mnemonic
[0] != 'f')
3495 return 0; /* non-math */
3497 switch (mnemonic
[1])
3499 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3500 the fs segment override prefix not currently handled because no
3501 call path can make opcodes without operands get here */
3503 return 2 /* integer op */;
3505 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3506 return 3; /* fldcw/fldenv */
3509 if (mnemonic
[2] != 'o' /* fnop */)
3510 return 3; /* non-waiting control op */
3513 if (mnemonic
[2] == 's')
3514 return 3; /* frstor/frstpm */
3517 if (mnemonic
[2] == 'a')
3518 return 3; /* fsave */
3519 if (mnemonic
[2] == 't')
3521 switch (mnemonic
[3])
3523 case 'c': /* fstcw */
3524 case 'd': /* fstdw */
3525 case 'e': /* fstenv */
3526 case 's': /* fsts[gw] */
3532 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3533 return 0; /* fxsave/fxrstor are not really math ops */
3540 /* Build the VEX prefix. */
3543 build_vex_prefix (const insn_template
*t
)
3545 unsigned int register_specifier
;
3546 unsigned int implied_prefix
;
3547 unsigned int vector_length
;
3550 /* Check register specifier. */
3551 if (i
.vex
.register_specifier
)
3553 register_specifier
=
3554 ~register_number (i
.vex
.register_specifier
) & 0xf;
3555 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3558 register_specifier
= 0xf;
3560 /* Use 2-byte VEX prefix by swapping destination and source operand
3561 if there are more than 1 register operand. */
3562 if (i
.reg_operands
> 1
3563 && i
.vec_encoding
!= vex_encoding_vex3
3564 && i
.dir_encoding
== dir_encoding_default
3565 && i
.operands
== i
.reg_operands
3566 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3567 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3568 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3571 unsigned int xchg
= i
.operands
- 1;
3572 union i386_op temp_op
;
3573 i386_operand_type temp_type
;
3575 temp_type
= i
.types
[xchg
];
3576 i
.types
[xchg
] = i
.types
[0];
3577 i
.types
[0] = temp_type
;
3578 temp_op
= i
.op
[xchg
];
3579 i
.op
[xchg
] = i
.op
[0];
3582 gas_assert (i
.rm
.mode
== 3);
3586 i
.rm
.regmem
= i
.rm
.reg
;
3589 if (i
.tm
.opcode_modifier
.d
)
3590 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3591 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3592 else /* Use the next insn. */
3596 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3597 are no memory operands and at least 3 register ones. */
3598 if (i
.reg_operands
>= 3
3599 && i
.vec_encoding
!= vex_encoding_vex3
3600 && i
.reg_operands
== i
.operands
- i
.imm_operands
3601 && i
.tm
.opcode_modifier
.vex
3602 && i
.tm
.opcode_modifier
.commutative
3603 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3605 && i
.vex
.register_specifier
3606 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3608 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3609 union i386_op temp_op
;
3610 i386_operand_type temp_type
;
3612 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3613 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3614 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3615 &i
.types
[i
.operands
- 3]));
3616 gas_assert (i
.rm
.mode
== 3);
3618 temp_type
= i
.types
[xchg
];
3619 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3620 i
.types
[xchg
+ 1] = temp_type
;
3621 temp_op
= i
.op
[xchg
];
3622 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3623 i
.op
[xchg
+ 1] = temp_op
;
3626 xchg
= i
.rm
.regmem
| 8;
3627 i
.rm
.regmem
= ~register_specifier
& 0xf;
3628 gas_assert (!(i
.rm
.regmem
& 8));
3629 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3630 register_specifier
= ~xchg
& 0xf;
3633 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3634 vector_length
= avxscalar
;
3635 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3641 /* Determine vector length from the last multi-length vector
3644 for (op
= t
->operands
; op
--;)
3645 if (t
->operand_types
[op
].bitfield
.xmmword
3646 && t
->operand_types
[op
].bitfield
.ymmword
3647 && i
.types
[op
].bitfield
.ymmword
)
3654 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3659 case DATA_PREFIX_OPCODE
:
3662 case REPE_PREFIX_OPCODE
:
3665 case REPNE_PREFIX_OPCODE
:
3672 /* Check the REX.W bit and VEXW. */
3673 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3674 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3675 else if (i
.tm
.opcode_modifier
.vexw
)
3676 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3678 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3680 /* Use 2-byte VEX prefix if possible. */
3682 && i
.vec_encoding
!= vex_encoding_vex3
3683 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3684 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3686 /* 2-byte VEX prefix. */
3690 i
.vex
.bytes
[0] = 0xc5;
3692 /* Check the REX.R bit. */
3693 r
= (i
.rex
& REX_R
) ? 0 : 1;
3694 i
.vex
.bytes
[1] = (r
<< 7
3695 | register_specifier
<< 3
3696 | vector_length
<< 2
3701 /* 3-byte VEX prefix. */
3706 switch (i
.tm
.opcode_modifier
.vexopcode
)
3710 i
.vex
.bytes
[0] = 0xc4;
3714 i
.vex
.bytes
[0] = 0xc4;
3718 i
.vex
.bytes
[0] = 0xc4;
3722 i
.vex
.bytes
[0] = 0x8f;
3726 i
.vex
.bytes
[0] = 0x8f;
3730 i
.vex
.bytes
[0] = 0x8f;
3736 /* The high 3 bits of the second VEX byte are 1's compliment
3737 of RXB bits from REX. */
3738 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3740 i
.vex
.bytes
[2] = (w
<< 7
3741 | register_specifier
<< 3
3742 | vector_length
<< 2
3747 static INLINE bfd_boolean
3748 is_evex_encoding (const insn_template
*t
)
3750 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3751 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3752 || t
->opcode_modifier
.sae
;
3755 static INLINE bfd_boolean
3756 is_any_vex_encoding (const insn_template
*t
)
3758 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3759 || is_evex_encoding (t
);
3762 /* Build the EVEX prefix. */
3765 build_evex_prefix (void)
3767 unsigned int register_specifier
;
3768 unsigned int implied_prefix
;
3770 rex_byte vrex_used
= 0;
3772 /* Check register specifier. */
3773 if (i
.vex
.register_specifier
)
3775 gas_assert ((i
.vrex
& REX_X
) == 0);
3777 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3778 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3779 register_specifier
+= 8;
3780 /* The upper 16 registers are encoded in the fourth byte of the
3782 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3783 i
.vex
.bytes
[3] = 0x8;
3784 register_specifier
= ~register_specifier
& 0xf;
3788 register_specifier
= 0xf;
3790 /* Encode upper 16 vector index register in the fourth byte of
3792 if (!(i
.vrex
& REX_X
))
3793 i
.vex
.bytes
[3] = 0x8;
3798 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3803 case DATA_PREFIX_OPCODE
:
3806 case REPE_PREFIX_OPCODE
:
3809 case REPNE_PREFIX_OPCODE
:
3816 /* 4 byte EVEX prefix. */
3818 i
.vex
.bytes
[0] = 0x62;
3821 switch (i
.tm
.opcode_modifier
.vexopcode
)
3837 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3839 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3841 /* The fifth bit of the second EVEX byte is 1's compliment of the
3842 REX_R bit in VREX. */
3843 if (!(i
.vrex
& REX_R
))
3844 i
.vex
.bytes
[1] |= 0x10;
3848 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3850 /* When all operands are registers, the REX_X bit in REX is not
3851 used. We reuse it to encode the upper 16 registers, which is
3852 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3853 as 1's compliment. */
3854 if ((i
.vrex
& REX_B
))
3857 i
.vex
.bytes
[1] &= ~0x40;
3861 /* EVEX instructions shouldn't need the REX prefix. */
3862 i
.vrex
&= ~vrex_used
;
3863 gas_assert (i
.vrex
== 0);
3865 /* Check the REX.W bit and VEXW. */
3866 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3867 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3868 else if (i
.tm
.opcode_modifier
.vexw
)
3869 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3871 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3873 /* Encode the U bit. */
3874 implied_prefix
|= 0x4;
3876 /* The third byte of the EVEX prefix. */
3877 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3879 /* The fourth byte of the EVEX prefix. */
3880 /* The zeroing-masking bit. */
3881 if (i
.mask
&& i
.mask
->zeroing
)
3882 i
.vex
.bytes
[3] |= 0x80;
3884 /* Don't always set the broadcast bit if there is no RC. */
3887 /* Encode the vector length. */
3888 unsigned int vec_length
;
3890 if (!i
.tm
.opcode_modifier
.evex
3891 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3895 /* Determine vector length from the last multi-length vector
3898 for (op
= i
.operands
; op
--;)
3899 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3900 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3901 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3903 if (i
.types
[op
].bitfield
.zmmword
)
3905 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3908 else if (i
.types
[op
].bitfield
.ymmword
)
3910 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3913 else if (i
.types
[op
].bitfield
.xmmword
)
3915 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3918 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3920 switch (i
.broadcast
->bytes
)
3923 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3926 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3929 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3938 if (op
>= MAX_OPERANDS
)
3942 switch (i
.tm
.opcode_modifier
.evex
)
3944 case EVEXLIG
: /* LL' is ignored */
3945 vec_length
= evexlig
<< 5;
3948 vec_length
= 0 << 5;
3951 vec_length
= 1 << 5;
3954 vec_length
= 2 << 5;
3960 i
.vex
.bytes
[3] |= vec_length
;
3961 /* Encode the broadcast bit. */
3963 i
.vex
.bytes
[3] |= 0x10;
3967 if (i
.rounding
->type
!= saeonly
)
3968 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3970 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3973 if (i
.mask
&& i
.mask
->mask
)
3974 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3978 process_immext (void)
3982 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3983 which is coded in the same place as an 8-bit immediate field
3984 would be. Here we fake an 8-bit immediate operand from the
3985 opcode suffix stored in tm.extension_opcode.
3987 AVX instructions also use this encoding, for some of
3988 3 argument instructions. */
3990 gas_assert (i
.imm_operands
<= 1
3992 || (is_any_vex_encoding (&i
.tm
)
3993 && i
.operands
<= 4)));
3995 exp
= &im_expressions
[i
.imm_operands
++];
3996 i
.op
[i
.operands
].imms
= exp
;
3997 i
.types
[i
.operands
] = imm8
;
3999 exp
->X_op
= O_constant
;
4000 exp
->X_add_number
= i
.tm
.extension_opcode
;
4001 i
.tm
.extension_opcode
= None
;
4008 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4013 as_bad (_("invalid instruction `%s' after `%s'"),
4014 i
.tm
.name
, i
.hle_prefix
);
4017 if (i
.prefix
[LOCK_PREFIX
])
4019 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4023 case HLEPrefixRelease
:
4024 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4026 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4030 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4032 as_bad (_("memory destination needed for instruction `%s'"
4033 " after `xrelease'"), i
.tm
.name
);
4040 /* Try the shortest encoding by shortening operand size. */
4043 optimize_encoding (void)
4047 if (optimize_for_space
4048 && !is_any_vex_encoding (&i
.tm
)
4049 && i
.reg_operands
== 1
4050 && i
.imm_operands
== 1
4051 && !i
.types
[1].bitfield
.byte
4052 && i
.op
[0].imms
->X_op
== O_constant
4053 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4054 && (i
.tm
.base_opcode
== 0xa8
4055 || (i
.tm
.base_opcode
== 0xf6
4056 && i
.tm
.extension_opcode
== 0x0)))
4059 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4061 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4062 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4064 i
.types
[1].bitfield
.byte
= 1;
4065 /* Ignore the suffix. */
4067 /* Convert to byte registers. */
4068 if (i
.types
[1].bitfield
.word
)
4070 else if (i
.types
[1].bitfield
.dword
)
4074 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4079 else if (flag_code
== CODE_64BIT
4080 && !is_any_vex_encoding (&i
.tm
)
4081 && ((i
.types
[1].bitfield
.qword
4082 && i
.reg_operands
== 1
4083 && i
.imm_operands
== 1
4084 && i
.op
[0].imms
->X_op
== O_constant
4085 && ((i
.tm
.base_opcode
== 0xb8
4086 && i
.tm
.extension_opcode
== None
4087 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4088 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4089 && ((i
.tm
.base_opcode
== 0x24
4090 || i
.tm
.base_opcode
== 0xa8)
4091 || (i
.tm
.base_opcode
== 0x80
4092 && i
.tm
.extension_opcode
== 0x4)
4093 || ((i
.tm
.base_opcode
== 0xf6
4094 || (i
.tm
.base_opcode
| 1) == 0xc7)
4095 && i
.tm
.extension_opcode
== 0x0)))
4096 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4097 && i
.tm
.base_opcode
== 0x83
4098 && i
.tm
.extension_opcode
== 0x4)))
4099 || (i
.types
[0].bitfield
.qword
4100 && ((i
.reg_operands
== 2
4101 && i
.op
[0].regs
== i
.op
[1].regs
4102 && (i
.tm
.base_opcode
== 0x30
4103 || i
.tm
.base_opcode
== 0x28))
4104 || (i
.reg_operands
== 1
4106 && i
.tm
.base_opcode
== 0x30)))))
4109 andq $imm31, %r64 -> andl $imm31, %r32
4110 andq $imm7, %r64 -> andl $imm7, %r32
4111 testq $imm31, %r64 -> testl $imm31, %r32
4112 xorq %r64, %r64 -> xorl %r32, %r32
4113 subq %r64, %r64 -> subl %r32, %r32
4114 movq $imm31, %r64 -> movl $imm31, %r32
4115 movq $imm32, %r64 -> movl $imm32, %r32
4117 i
.tm
.opcode_modifier
.norex64
= 1;
4118 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4121 movq $imm31, %r64 -> movl $imm31, %r32
4122 movq $imm32, %r64 -> movl $imm32, %r32
4124 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4125 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4126 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4127 i
.types
[0].bitfield
.imm32
= 1;
4128 i
.types
[0].bitfield
.imm32s
= 0;
4129 i
.types
[0].bitfield
.imm64
= 0;
4130 i
.types
[1].bitfield
.dword
= 1;
4131 i
.types
[1].bitfield
.qword
= 0;
4132 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4135 movq $imm31, %r64 -> movl $imm31, %r32
4137 i
.tm
.base_opcode
= 0xb8;
4138 i
.tm
.extension_opcode
= None
;
4139 i
.tm
.opcode_modifier
.w
= 0;
4140 i
.tm
.opcode_modifier
.modrm
= 0;
4144 else if (optimize
> 1
4145 && !optimize_for_space
4146 && !is_any_vex_encoding (&i
.tm
)
4147 && i
.reg_operands
== 2
4148 && i
.op
[0].regs
== i
.op
[1].regs
4149 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4150 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4151 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4154 andb %rN, %rN -> testb %rN, %rN
4155 andw %rN, %rN -> testw %rN, %rN
4156 andq %rN, %rN -> testq %rN, %rN
4157 orb %rN, %rN -> testb %rN, %rN
4158 orw %rN, %rN -> testw %rN, %rN
4159 orq %rN, %rN -> testq %rN, %rN
4161 and outside of 64-bit mode
4163 andl %rN, %rN -> testl %rN, %rN
4164 orl %rN, %rN -> testl %rN, %rN
4166 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4168 else if (i
.reg_operands
== 3
4169 && i
.op
[0].regs
== i
.op
[1].regs
4170 && !i
.types
[2].bitfield
.xmmword
4171 && (i
.tm
.opcode_modifier
.vex
4172 || ((!i
.mask
|| i
.mask
->zeroing
)
4174 && is_evex_encoding (&i
.tm
)
4175 && (i
.vec_encoding
!= vex_encoding_evex
4176 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4177 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4178 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4179 && i
.types
[2].bitfield
.ymmword
))))
4180 && ((i
.tm
.base_opcode
== 0x55
4181 || i
.tm
.base_opcode
== 0x6655
4182 || i
.tm
.base_opcode
== 0x66df
4183 || i
.tm
.base_opcode
== 0x57
4184 || i
.tm
.base_opcode
== 0x6657
4185 || i
.tm
.base_opcode
== 0x66ef
4186 || i
.tm
.base_opcode
== 0x66f8
4187 || i
.tm
.base_opcode
== 0x66f9
4188 || i
.tm
.base_opcode
== 0x66fa
4189 || i
.tm
.base_opcode
== 0x66fb
4190 || i
.tm
.base_opcode
== 0x42
4191 || i
.tm
.base_opcode
== 0x6642
4192 || i
.tm
.base_opcode
== 0x47
4193 || i
.tm
.base_opcode
== 0x6647)
4194 && i
.tm
.extension_opcode
== None
))
4197 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4199 EVEX VOP %zmmM, %zmmM, %zmmN
4200 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4201 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4202 EVEX VOP %ymmM, %ymmM, %ymmN
4203 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4204 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4205 VEX VOP %ymmM, %ymmM, %ymmN
4206 -> VEX VOP %xmmM, %xmmM, %xmmN
4207 VOP, one of vpandn and vpxor:
4208 VEX VOP %ymmM, %ymmM, %ymmN
4209 -> VEX VOP %xmmM, %xmmM, %xmmN
4210 VOP, one of vpandnd and vpandnq:
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VOP, one of vpxord and vpxorq:
4218 EVEX VOP %zmmM, %zmmM, %zmmN
4219 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4220 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4221 EVEX VOP %ymmM, %ymmM, %ymmN
4222 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4223 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4224 VOP, one of kxord and kxorq:
4225 VEX VOP %kM, %kM, %kN
4226 -> VEX kxorw %kM, %kM, %kN
4227 VOP, one of kandnd and kandnq:
4228 VEX VOP %kM, %kM, %kN
4229 -> VEX kandnw %kM, %kM, %kN
4231 if (is_evex_encoding (&i
.tm
))
4233 if (i
.vec_encoding
!= vex_encoding_evex
)
4235 i
.tm
.opcode_modifier
.vex
= VEX128
;
4236 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4237 i
.tm
.opcode_modifier
.evex
= 0;
4239 else if (optimize
> 1)
4240 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4244 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4246 i
.tm
.base_opcode
&= 0xff;
4247 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4250 i
.tm
.opcode_modifier
.vex
= VEX128
;
4252 if (i
.tm
.opcode_modifier
.vex
)
4253 for (j
= 0; j
< 3; j
++)
4255 i
.types
[j
].bitfield
.xmmword
= 1;
4256 i
.types
[j
].bitfield
.ymmword
= 0;
4259 else if (i
.vec_encoding
!= vex_encoding_evex
4260 && !i
.types
[0].bitfield
.zmmword
4261 && !i
.types
[1].bitfield
.zmmword
4264 && is_evex_encoding (&i
.tm
)
4265 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4266 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4267 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4268 || (i
.tm
.base_opcode
& ~4) == 0x66db
4269 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4270 && i
.tm
.extension_opcode
== None
)
4273 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4274 vmovdqu32 and vmovdqu64:
4275 EVEX VOP %xmmM, %xmmN
4276 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4277 EVEX VOP %ymmM, %ymmN
4278 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4280 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4282 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4284 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4286 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4287 VOP, one of vpand, vpandn, vpor, vpxor:
4288 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4289 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4290 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4291 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4292 EVEX VOP{d,q} mem, %xmmM, %xmmN
4293 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4294 EVEX VOP{d,q} mem, %ymmM, %ymmN
4295 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4297 for (j
= 0; j
< i
.operands
; j
++)
4298 if (operand_type_check (i
.types
[j
], disp
)
4299 && i
.op
[j
].disps
->X_op
== O_constant
)
4301 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4302 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4303 bytes, we choose EVEX Disp8 over VEX Disp32. */
4304 int evex_disp8
, vex_disp8
;
4305 unsigned int memshift
= i
.memshift
;
4306 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4308 evex_disp8
= fits_in_disp8 (n
);
4310 vex_disp8
= fits_in_disp8 (n
);
4311 if (evex_disp8
!= vex_disp8
)
4313 i
.memshift
= memshift
;
4317 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4320 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4321 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4322 i
.tm
.opcode_modifier
.vex
4323 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4324 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4325 /* VPAND, VPOR, and VPXOR are commutative. */
4326 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4327 i
.tm
.opcode_modifier
.commutative
= 1;
4328 i
.tm
.opcode_modifier
.evex
= 0;
4329 i
.tm
.opcode_modifier
.masking
= 0;
4330 i
.tm
.opcode_modifier
.broadcast
= 0;
4331 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4334 i
.types
[j
].bitfield
.disp8
4335 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4339 /* Return non-zero for load instruction. */
4345 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4346 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4351 if (i
.tm
.base_opcode
== 0x8d)
4355 if ((i
.tm
.base_opcode
& ~7) == 0x58
4356 || (i
.tm
.base_opcode
== 0x8f && i
.tm
.extension_opcode
== 0))
4359 /* movs, cmps, lods, scas. */
4360 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4364 if (base_opcode
== 0x6f)
4368 /* No memory operand. */
4369 if (!i
.mem_operands
)
4375 if (i
.tm
.base_opcode
== 0xae
4376 && i
.tm
.opcode_modifier
.vex
4377 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4378 && i
.tm
.extension_opcode
== 2)
4383 /* test, not, neg, mul, imul, div, idiv. */
4384 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4385 && i
.tm
.extension_opcode
!= 1)
4389 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4392 /* add, or, adc, sbb, and, sub, xor, cmp. */
4393 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4396 /* bt, bts, btr, btc. */
4397 if (i
.tm
.base_opcode
== 0xfba
4398 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4401 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4402 if ((base_opcode
== 0xc1
4403 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4404 && i
.tm
.extension_opcode
!= 6)
4407 /* cmpxchg8b, cmpxchg16b, xrstors. */
4408 if (i
.tm
.base_opcode
== 0xfc7
4409 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4412 /* fxrstor, ldmxcsr, xrstor. */
4413 if (i
.tm
.base_opcode
== 0xfae
4414 && (i
.tm
.extension_opcode
== 1
4415 || i
.tm
.extension_opcode
== 2
4416 || i
.tm
.extension_opcode
== 5))
4419 /* lgdt, lidt, lmsw. */
4420 if (i
.tm
.base_opcode
== 0xf01
4421 && (i
.tm
.extension_opcode
== 2
4422 || i
.tm
.extension_opcode
== 3
4423 || i
.tm
.extension_opcode
== 6))
4427 if (i
.tm
.base_opcode
== 0xfc7
4428 && i
.tm
.extension_opcode
== 6)
4431 /* Check for x87 instructions. */
4432 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4434 /* Skip fst, fstp, fstenv, fstcw. */
4435 if (i
.tm
.base_opcode
== 0xd9
4436 && (i
.tm
.extension_opcode
== 2
4437 || i
.tm
.extension_opcode
== 3
4438 || i
.tm
.extension_opcode
== 6
4439 || i
.tm
.extension_opcode
== 7))
4442 /* Skip fisttp, fist, fistp, fstp. */
4443 if (i
.tm
.base_opcode
== 0xdb
4444 && (i
.tm
.extension_opcode
== 1
4445 || i
.tm
.extension_opcode
== 2
4446 || i
.tm
.extension_opcode
== 3
4447 || i
.tm
.extension_opcode
== 7))
4450 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4451 if (i
.tm
.base_opcode
== 0xdd
4452 && (i
.tm
.extension_opcode
== 1
4453 || i
.tm
.extension_opcode
== 2
4454 || i
.tm
.extension_opcode
== 3
4455 || i
.tm
.extension_opcode
== 6
4456 || i
.tm
.extension_opcode
== 7))
4459 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4460 if (i
.tm
.base_opcode
== 0xdf
4461 && (i
.tm
.extension_opcode
== 1
4462 || i
.tm
.extension_opcode
== 2
4463 || i
.tm
.extension_opcode
== 3
4464 || i
.tm
.extension_opcode
== 6
4465 || i
.tm
.extension_opcode
== 7))
4472 dest
= i
.operands
- 1;
4474 /* Check fake imm8 operand and 3 source operands. */
4475 if ((i
.tm
.opcode_modifier
.immext
4476 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4477 && i
.types
[dest
].bitfield
.imm8
)
4480 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4482 && (base_opcode
== 0x1
4483 || base_opcode
== 0x9
4484 || base_opcode
== 0x11
4485 || base_opcode
== 0x19
4486 || base_opcode
== 0x21
4487 || base_opcode
== 0x29
4488 || base_opcode
== 0x31
4489 || base_opcode
== 0x39
4490 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4491 || base_opcode
== 0xfc1))
4494 /* Check for load instruction. */
4495 return (i
.types
[dest
].bitfield
.class != ClassNone
4496 || i
.types
[dest
].bitfield
.instance
== Accum
);
4499 /* Output lfence, 0xfaee8, after instruction. */
4502 insert_lfence_after (void)
4504 if (lfence_after_load
&& load_insn_p ())
4506 char *p
= frag_more (3);
4513 /* Output lfence, 0xfaee8, before instruction. */
4516 insert_lfence_before (void)
4520 if (is_any_vex_encoding (&i
.tm
))
4523 if (i
.tm
.base_opcode
== 0xff
4524 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4526 /* Insert lfence before indirect branch if needed. */
4528 if (lfence_before_indirect_branch
== lfence_branch_none
)
4531 if (i
.operands
!= 1)
4534 if (i
.reg_operands
== 1)
4536 /* Indirect branch via register. Don't insert lfence with
4537 -mlfence-after-load=yes. */
4538 if (lfence_after_load
4539 || lfence_before_indirect_branch
== lfence_branch_memory
)
4542 else if (i
.mem_operands
== 1
4543 && lfence_before_indirect_branch
!= lfence_branch_register
)
4545 as_warn (_("indirect `%s` with memory operand should be avoided"),
4552 if (last_insn
.kind
!= last_insn_other
4553 && last_insn
.seg
== now_seg
)
4555 as_warn_where (last_insn
.file
, last_insn
.line
,
4556 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4557 last_insn
.name
, i
.tm
.name
);
4568 /* Output or/not and lfence before ret. */
4569 if (lfence_before_ret
!= lfence_before_ret_none
4570 && (i
.tm
.base_opcode
== 0xc2
4571 || i
.tm
.base_opcode
== 0xc3
4572 || i
.tm
.base_opcode
== 0xca
4573 || i
.tm
.base_opcode
== 0xcb))
4575 if (last_insn
.kind
!= last_insn_other
4576 && last_insn
.seg
== now_seg
)
4578 as_warn_where (last_insn
.file
, last_insn
.line
,
4579 _("`%s` skips -mlfence-before-ret on `%s`"),
4580 last_insn
.name
, i
.tm
.name
);
4583 if (lfence_before_ret
== lfence_before_ret_or
)
4585 /* orl: 0x830c2400. */
4586 p
= frag_more ((flag_code
== CODE_64BIT
? 1 : 0) + 4 + 3);
4587 if (flag_code
== CODE_64BIT
)
4596 p
= frag_more ((flag_code
== CODE_64BIT
? 2 : 0) + 6 + 3);
4597 /* notl: 0xf71424. */
4598 if (flag_code
== CODE_64BIT
)
4603 /* notl: 0xf71424. */
4604 if (flag_code
== CODE_64BIT
)
4616 /* This is the guts of the machine-dependent assembler. LINE points to a
4617 machine dependent instruction. This function is supposed to emit
4618 the frags/bytes it assembles to. */
4621 md_assemble (char *line
)
4624 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4625 const insn_template
*t
;
4627 /* Initialize globals. */
4628 memset (&i
, '\0', sizeof (i
));
4629 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4630 i
.reloc
[j
] = NO_RELOC
;
4631 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4632 memset (im_expressions
, '\0', sizeof (im_expressions
));
4633 save_stack_p
= save_stack
;
4635 /* First parse an instruction mnemonic & call i386_operand for the operands.
4636 We assume that the scrubber has arranged it so that line[0] is the valid
4637 start of a (possibly prefixed) mnemonic. */
4639 line
= parse_insn (line
, mnemonic
);
4642 mnem_suffix
= i
.suffix
;
4644 line
= parse_operands (line
, mnemonic
);
4646 xfree (i
.memop1_string
);
4647 i
.memop1_string
= NULL
;
4651 /* Now we've parsed the mnemonic into a set of templates, and have the
4652 operands at hand. */
4654 /* All Intel opcodes have reversed operands except for "bound", "enter",
4655 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4656 intersegment "jmp" and "call" instructions with 2 immediate operands so
4657 that the immediate segment precedes the offset, as it does when in AT&T
4661 && (strcmp (mnemonic
, "bound") != 0)
4662 && (strcmp (mnemonic
, "invlpga") != 0)
4663 && (strncmp (mnemonic
, "monitor", 7) != 0)
4664 && (strncmp (mnemonic
, "mwait", 5) != 0)
4665 && (strcmp (mnemonic
, "tpause") != 0)
4666 && (strcmp (mnemonic
, "umwait") != 0)
4667 && !(operand_type_check (i
.types
[0], imm
)
4668 && operand_type_check (i
.types
[1], imm
)))
4671 /* The order of the immediates should be reversed
4672 for 2 immediates extrq and insertq instructions */
4673 if (i
.imm_operands
== 2
4674 && (strcmp (mnemonic
, "extrq") == 0
4675 || strcmp (mnemonic
, "insertq") == 0))
4676 swap_2_operands (0, 1);
4681 /* Don't optimize displacement for movabs since it only takes 64bit
4684 && i
.disp_encoding
!= disp_encoding_32bit
4685 && (flag_code
!= CODE_64BIT
4686 || strcmp (mnemonic
, "movabs") != 0))
4689 /* Next, we find a template that matches the given insn,
4690 making sure the overlap of the given operands types is consistent
4691 with the template operand types. */
4693 if (!(t
= match_template (mnem_suffix
)))
4696 if (sse_check
!= check_none
4697 && !i
.tm
.opcode_modifier
.noavx
4698 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4699 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4700 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4701 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4702 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4703 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4704 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4705 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4706 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4707 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4708 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4709 || i
.tm
.cpu_flags
.bitfield
.cpusha
4710 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4712 (sse_check
== check_warning
4714 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4717 if (i
.tm
.opcode_modifier
.fwait
)
4718 if (!add_prefix (FWAIT_OPCODE
))
4721 /* Check if REP prefix is OK. */
4722 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4724 as_bad (_("invalid instruction `%s' after `%s'"),
4725 i
.tm
.name
, i
.rep_prefix
);
4729 /* Check for lock without a lockable instruction. Destination operand
4730 must be memory unless it is xchg (0x86). */
4731 if (i
.prefix
[LOCK_PREFIX
]
4732 && (!i
.tm
.opcode_modifier
.islockable
4733 || i
.mem_operands
== 0
4734 || (i
.tm
.base_opcode
!= 0x86
4735 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4737 as_bad (_("expecting lockable instruction after `lock'"));
4741 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4742 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4744 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4748 /* Check if HLE prefix is OK. */
4749 if (i
.hle_prefix
&& !check_hle ())
4752 /* Check BND prefix. */
4753 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4754 as_bad (_("expecting valid branch instruction after `bnd'"));
4756 /* Check NOTRACK prefix. */
4757 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4758 as_bad (_("expecting indirect branch instruction after `notrack'"));
4760 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4762 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4763 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4764 else if (flag_code
!= CODE_16BIT
4765 ? i
.prefix
[ADDR_PREFIX
]
4766 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4767 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4770 /* Insert BND prefix. */
4771 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4773 if (!i
.prefix
[BND_PREFIX
])
4774 add_prefix (BND_PREFIX_OPCODE
);
4775 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4777 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4778 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4782 /* Check string instruction segment overrides. */
4783 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4785 gas_assert (i
.mem_operands
);
4786 if (!check_string ())
4788 i
.disp_operands
= 0;
4791 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4792 optimize_encoding ();
4794 if (!process_suffix ())
4797 /* Update operand types. */
4798 for (j
= 0; j
< i
.operands
; j
++)
4799 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4801 /* Make still unresolved immediate matches conform to size of immediate
4802 given in i.suffix. */
4803 if (!finalize_imm ())
4806 if (i
.types
[0].bitfield
.imm1
)
4807 i
.imm_operands
= 0; /* kludge for shift insns. */
4809 /* We only need to check those implicit registers for instructions
4810 with 3 operands or less. */
4811 if (i
.operands
<= 3)
4812 for (j
= 0; j
< i
.operands
; j
++)
4813 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4814 && !i
.types
[j
].bitfield
.xmmword
)
4817 /* ImmExt should be processed after SSE2AVX. */
4818 if (!i
.tm
.opcode_modifier
.sse2avx
4819 && i
.tm
.opcode_modifier
.immext
)
4822 /* For insns with operands there are more diddles to do to the opcode. */
4825 if (!process_operands ())
4828 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4830 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4831 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4834 if (is_any_vex_encoding (&i
.tm
))
4836 if (!cpu_arch_flags
.bitfield
.cpui286
)
4838 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4843 if (i
.tm
.opcode_modifier
.vex
)
4844 build_vex_prefix (t
);
4846 build_evex_prefix ();
4849 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4850 instructions may define INT_OPCODE as well, so avoid this corner
4851 case for those instructions that use MODRM. */
4852 if (i
.tm
.base_opcode
== INT_OPCODE
4853 && !i
.tm
.opcode_modifier
.modrm
4854 && i
.op
[0].imms
->X_add_number
== 3)
4856 i
.tm
.base_opcode
= INT3_OPCODE
;
4860 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4861 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4862 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4863 && i
.op
[0].disps
->X_op
== O_constant
)
4865 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4866 the absolute address given by the constant. Since ix86 jumps and
4867 calls are pc relative, we need to generate a reloc. */
4868 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4869 i
.op
[0].disps
->X_op
= O_symbol
;
4872 /* For 8 bit registers we need an empty rex prefix. Also if the
4873 instruction already has a prefix, we need to convert old
4874 registers to new ones. */
4876 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4877 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4878 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4879 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4880 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4881 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4886 i
.rex
|= REX_OPCODE
;
4887 for (x
= 0; x
< 2; x
++)
4889 /* Look for 8 bit operand that uses old registers. */
4890 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4891 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4893 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4894 /* In case it is "hi" register, give up. */
4895 if (i
.op
[x
].regs
->reg_num
> 3)
4896 as_bad (_("can't encode register '%s%s' in an "
4897 "instruction requiring REX prefix."),
4898 register_prefix
, i
.op
[x
].regs
->reg_name
);
4900 /* Otherwise it is equivalent to the extended register.
4901 Since the encoding doesn't change this is merely
4902 cosmetic cleanup for debug output. */
4904 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4909 if (i
.rex
== 0 && i
.rex_encoding
)
4911 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4912 that uses legacy register. If it is "hi" register, don't add
4913 the REX_OPCODE byte. */
4915 for (x
= 0; x
< 2; x
++)
4916 if (i
.types
[x
].bitfield
.class == Reg
4917 && i
.types
[x
].bitfield
.byte
4918 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4919 && i
.op
[x
].regs
->reg_num
> 3)
4921 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4922 i
.rex_encoding
= FALSE
;
4931 add_prefix (REX_OPCODE
| i
.rex
);
4933 insert_lfence_before ();
4935 /* We are ready to output the insn. */
4938 insert_lfence_after ();
4940 last_insn
.seg
= now_seg
;
4942 if (i
.tm
.opcode_modifier
.isprefix
)
4944 last_insn
.kind
= last_insn_prefix
;
4945 last_insn
.name
= i
.tm
.name
;
4946 last_insn
.file
= as_where (&last_insn
.line
);
4949 last_insn
.kind
= last_insn_other
;
4953 parse_insn (char *line
, char *mnemonic
)
4956 char *token_start
= l
;
4959 const insn_template
*t
;
4965 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4970 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4972 as_bad (_("no such instruction: `%s'"), token_start
);
4977 if (!is_space_char (*l
)
4978 && *l
!= END_OF_INSN
4980 || (*l
!= PREFIX_SEPARATOR
4983 as_bad (_("invalid character %s in mnemonic"),
4984 output_invalid (*l
));
4987 if (token_start
== l
)
4989 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4990 as_bad (_("expecting prefix; got nothing"));
4992 as_bad (_("expecting mnemonic; got nothing"));
4996 /* Look up instruction (or prefix) via hash table. */
4997 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4999 if (*l
!= END_OF_INSN
5000 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5001 && current_templates
5002 && current_templates
->start
->opcode_modifier
.isprefix
)
5004 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5006 as_bad ((flag_code
!= CODE_64BIT
5007 ? _("`%s' is only supported in 64-bit mode")
5008 : _("`%s' is not supported in 64-bit mode")),
5009 current_templates
->start
->name
);
5012 /* If we are in 16-bit mode, do not allow addr16 or data16.
5013 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5014 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5015 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5016 && flag_code
!= CODE_64BIT
5017 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5018 ^ (flag_code
== CODE_16BIT
)))
5020 as_bad (_("redundant %s prefix"),
5021 current_templates
->start
->name
);
5024 if (current_templates
->start
->opcode_length
== 0)
5026 /* Handle pseudo prefixes. */
5027 switch (current_templates
->start
->base_opcode
)
5031 i
.disp_encoding
= disp_encoding_8bit
;
5035 i
.disp_encoding
= disp_encoding_32bit
;
5039 i
.dir_encoding
= dir_encoding_load
;
5043 i
.dir_encoding
= dir_encoding_store
;
5047 i
.vec_encoding
= vex_encoding_vex
;
5051 i
.vec_encoding
= vex_encoding_vex3
;
5055 i
.vec_encoding
= vex_encoding_evex
;
5059 i
.rex_encoding
= TRUE
;
5063 i
.no_optimize
= TRUE
;
5071 /* Add prefix, checking for repeated prefixes. */
5072 switch (add_prefix (current_templates
->start
->base_opcode
))
5077 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5078 i
.notrack_prefix
= current_templates
->start
->name
;
5081 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5082 i
.hle_prefix
= current_templates
->start
->name
;
5083 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5084 i
.bnd_prefix
= current_templates
->start
->name
;
5086 i
.rep_prefix
= current_templates
->start
->name
;
5092 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5099 if (!current_templates
)
5101 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5102 Check if we should swap operand or force 32bit displacement in
5104 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5105 i
.dir_encoding
= dir_encoding_swap
;
5106 else if (mnem_p
- 3 == dot_p
5109 i
.disp_encoding
= disp_encoding_8bit
;
5110 else if (mnem_p
- 4 == dot_p
5114 i
.disp_encoding
= disp_encoding_32bit
;
5119 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5122 if (!current_templates
)
5125 if (mnem_p
> mnemonic
)
5127 /* See if we can get a match by trimming off a suffix. */
5130 case WORD_MNEM_SUFFIX
:
5131 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5132 i
.suffix
= SHORT_MNEM_SUFFIX
;
5135 case BYTE_MNEM_SUFFIX
:
5136 case QWORD_MNEM_SUFFIX
:
5137 i
.suffix
= mnem_p
[-1];
5139 current_templates
= (const templates
*) hash_find (op_hash
,
5142 case SHORT_MNEM_SUFFIX
:
5143 case LONG_MNEM_SUFFIX
:
5146 i
.suffix
= mnem_p
[-1];
5148 current_templates
= (const templates
*) hash_find (op_hash
,
5157 if (intel_float_operand (mnemonic
) == 1)
5158 i
.suffix
= SHORT_MNEM_SUFFIX
;
5160 i
.suffix
= LONG_MNEM_SUFFIX
;
5162 current_templates
= (const templates
*) hash_find (op_hash
,
5169 if (!current_templates
)
5171 as_bad (_("no such instruction: `%s'"), token_start
);
5176 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5177 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5179 /* Check for a branch hint. We allow ",pt" and ",pn" for
5180 predict taken and predict not taken respectively.
5181 I'm not sure that branch hints actually do anything on loop
5182 and jcxz insns (JumpByte) for current Pentium4 chips. They
5183 may work in the future and it doesn't hurt to accept them
5185 if (l
[0] == ',' && l
[1] == 'p')
5189 if (!add_prefix (DS_PREFIX_OPCODE
))
5193 else if (l
[2] == 'n')
5195 if (!add_prefix (CS_PREFIX_OPCODE
))
5201 /* Any other comma loses. */
5204 as_bad (_("invalid character %s in mnemonic"),
5205 output_invalid (*l
));
5209 /* Check if instruction is supported on specified architecture. */
5211 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5213 supported
|= cpu_flags_match (t
);
5214 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5216 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5217 as_warn (_("use .code16 to ensure correct addressing mode"));
5223 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5224 as_bad (flag_code
== CODE_64BIT
5225 ? _("`%s' is not supported in 64-bit mode")
5226 : _("`%s' is only supported in 64-bit mode"),
5227 current_templates
->start
->name
);
5229 as_bad (_("`%s' is not supported on `%s%s'"),
5230 current_templates
->start
->name
,
5231 cpu_arch_name
? cpu_arch_name
: default_arch
,
5232 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5238 parse_operands (char *l
, const char *mnemonic
)
5242 /* 1 if operand is pending after ','. */
5243 unsigned int expecting_operand
= 0;
5245 /* Non-zero if operand parens not balanced. */
5246 unsigned int paren_not_balanced
;
5248 while (*l
!= END_OF_INSN
)
5250 /* Skip optional white space before operand. */
5251 if (is_space_char (*l
))
5253 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5255 as_bad (_("invalid character %s before operand %d"),
5256 output_invalid (*l
),
5260 token_start
= l
; /* After white space. */
5261 paren_not_balanced
= 0;
5262 while (paren_not_balanced
|| *l
!= ',')
5264 if (*l
== END_OF_INSN
)
5266 if (paren_not_balanced
)
5269 as_bad (_("unbalanced parenthesis in operand %d."),
5272 as_bad (_("unbalanced brackets in operand %d."),
5277 break; /* we are done */
5279 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5281 as_bad (_("invalid character %s in operand %d"),
5282 output_invalid (*l
),
5289 ++paren_not_balanced
;
5291 --paren_not_balanced
;
5296 ++paren_not_balanced
;
5298 --paren_not_balanced
;
5302 if (l
!= token_start
)
5303 { /* Yes, we've read in another operand. */
5304 unsigned int operand_ok
;
5305 this_operand
= i
.operands
++;
5306 if (i
.operands
> MAX_OPERANDS
)
5308 as_bad (_("spurious operands; (%d operands/instruction max)"),
5312 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5313 /* Now parse operand adding info to 'i' as we go along. */
5314 END_STRING_AND_SAVE (l
);
5316 if (i
.mem_operands
> 1)
5318 as_bad (_("too many memory references for `%s'"),
5325 i386_intel_operand (token_start
,
5326 intel_float_operand (mnemonic
));
5328 operand_ok
= i386_att_operand (token_start
);
5330 RESTORE_END_STRING (l
);
5336 if (expecting_operand
)
5338 expecting_operand_after_comma
:
5339 as_bad (_("expecting operand after ','; got nothing"));
5344 as_bad (_("expecting operand before ','; got nothing"));
5349 /* Now *l must be either ',' or END_OF_INSN. */
5352 if (*++l
== END_OF_INSN
)
5354 /* Just skip it, if it's \n complain. */
5355 goto expecting_operand_after_comma
;
5357 expecting_operand
= 1;
5364 swap_2_operands (int xchg1
, int xchg2
)
5366 union i386_op temp_op
;
5367 i386_operand_type temp_type
;
5368 unsigned int temp_flags
;
5369 enum bfd_reloc_code_real temp_reloc
;
5371 temp_type
= i
.types
[xchg2
];
5372 i
.types
[xchg2
] = i
.types
[xchg1
];
5373 i
.types
[xchg1
] = temp_type
;
5375 temp_flags
= i
.flags
[xchg2
];
5376 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5377 i
.flags
[xchg1
] = temp_flags
;
5379 temp_op
= i
.op
[xchg2
];
5380 i
.op
[xchg2
] = i
.op
[xchg1
];
5381 i
.op
[xchg1
] = temp_op
;
5383 temp_reloc
= i
.reloc
[xchg2
];
5384 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5385 i
.reloc
[xchg1
] = temp_reloc
;
5389 if (i
.mask
->operand
== xchg1
)
5390 i
.mask
->operand
= xchg2
;
5391 else if (i
.mask
->operand
== xchg2
)
5392 i
.mask
->operand
= xchg1
;
5396 if (i
.broadcast
->operand
== xchg1
)
5397 i
.broadcast
->operand
= xchg2
;
5398 else if (i
.broadcast
->operand
== xchg2
)
5399 i
.broadcast
->operand
= xchg1
;
5403 if (i
.rounding
->operand
== xchg1
)
5404 i
.rounding
->operand
= xchg2
;
5405 else if (i
.rounding
->operand
== xchg2
)
5406 i
.rounding
->operand
= xchg1
;
5411 swap_operands (void)
5417 swap_2_operands (1, i
.operands
- 2);
5421 swap_2_operands (0, i
.operands
- 1);
5427 if (i
.mem_operands
== 2)
5429 const seg_entry
*temp_seg
;
5430 temp_seg
= i
.seg
[0];
5431 i
.seg
[0] = i
.seg
[1];
5432 i
.seg
[1] = temp_seg
;
5436 /* Try to ensure constant immediates are represented in the smallest
5441 char guess_suffix
= 0;
5445 guess_suffix
= i
.suffix
;
5446 else if (i
.reg_operands
)
5448 /* Figure out a suffix from the last register operand specified.
5449 We can't do this properly yet, i.e. excluding special register
5450 instances, but the following works for instructions with
5451 immediates. In any case, we can't set i.suffix yet. */
5452 for (op
= i
.operands
; --op
>= 0;)
5453 if (i
.types
[op
].bitfield
.class != Reg
)
5455 else if (i
.types
[op
].bitfield
.byte
)
5457 guess_suffix
= BYTE_MNEM_SUFFIX
;
5460 else if (i
.types
[op
].bitfield
.word
)
5462 guess_suffix
= WORD_MNEM_SUFFIX
;
5465 else if (i
.types
[op
].bitfield
.dword
)
5467 guess_suffix
= LONG_MNEM_SUFFIX
;
5470 else if (i
.types
[op
].bitfield
.qword
)
5472 guess_suffix
= QWORD_MNEM_SUFFIX
;
5476 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5477 guess_suffix
= WORD_MNEM_SUFFIX
;
5479 for (op
= i
.operands
; --op
>= 0;)
5480 if (operand_type_check (i
.types
[op
], imm
))
5482 switch (i
.op
[op
].imms
->X_op
)
5485 /* If a suffix is given, this operand may be shortened. */
5486 switch (guess_suffix
)
5488 case LONG_MNEM_SUFFIX
:
5489 i
.types
[op
].bitfield
.imm32
= 1;
5490 i
.types
[op
].bitfield
.imm64
= 1;
5492 case WORD_MNEM_SUFFIX
:
5493 i
.types
[op
].bitfield
.imm16
= 1;
5494 i
.types
[op
].bitfield
.imm32
= 1;
5495 i
.types
[op
].bitfield
.imm32s
= 1;
5496 i
.types
[op
].bitfield
.imm64
= 1;
5498 case BYTE_MNEM_SUFFIX
:
5499 i
.types
[op
].bitfield
.imm8
= 1;
5500 i
.types
[op
].bitfield
.imm8s
= 1;
5501 i
.types
[op
].bitfield
.imm16
= 1;
5502 i
.types
[op
].bitfield
.imm32
= 1;
5503 i
.types
[op
].bitfield
.imm32s
= 1;
5504 i
.types
[op
].bitfield
.imm64
= 1;
5508 /* If this operand is at most 16 bits, convert it
5509 to a signed 16 bit number before trying to see
5510 whether it will fit in an even smaller size.
5511 This allows a 16-bit operand such as $0xffe0 to
5512 be recognised as within Imm8S range. */
5513 if ((i
.types
[op
].bitfield
.imm16
)
5514 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5516 i
.op
[op
].imms
->X_add_number
=
5517 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5520 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5521 if ((i
.types
[op
].bitfield
.imm32
)
5522 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5525 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5526 ^ ((offsetT
) 1 << 31))
5527 - ((offsetT
) 1 << 31));
5531 = operand_type_or (i
.types
[op
],
5532 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5534 /* We must avoid matching of Imm32 templates when 64bit
5535 only immediate is available. */
5536 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5537 i
.types
[op
].bitfield
.imm32
= 0;
5544 /* Symbols and expressions. */
5546 /* Convert symbolic operand to proper sizes for matching, but don't
5547 prevent matching a set of insns that only supports sizes other
5548 than those matching the insn suffix. */
5550 i386_operand_type mask
, allowed
;
5551 const insn_template
*t
;
5553 operand_type_set (&mask
, 0);
5554 operand_type_set (&allowed
, 0);
5556 for (t
= current_templates
->start
;
5557 t
< current_templates
->end
;
5560 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5561 allowed
= operand_type_and (allowed
, anyimm
);
5563 switch (guess_suffix
)
5565 case QWORD_MNEM_SUFFIX
:
5566 mask
.bitfield
.imm64
= 1;
5567 mask
.bitfield
.imm32s
= 1;
5569 case LONG_MNEM_SUFFIX
:
5570 mask
.bitfield
.imm32
= 1;
5572 case WORD_MNEM_SUFFIX
:
5573 mask
.bitfield
.imm16
= 1;
5575 case BYTE_MNEM_SUFFIX
:
5576 mask
.bitfield
.imm8
= 1;
5581 allowed
= operand_type_and (mask
, allowed
);
5582 if (!operand_type_all_zero (&allowed
))
5583 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5590 /* Try to use the smallest displacement type too. */
5592 optimize_disp (void)
5596 for (op
= i
.operands
; --op
>= 0;)
5597 if (operand_type_check (i
.types
[op
], disp
))
5599 if (i
.op
[op
].disps
->X_op
== O_constant
)
5601 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5603 if (i
.types
[op
].bitfield
.disp16
5604 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5606 /* If this operand is at most 16 bits, convert
5607 to a signed 16 bit number and don't use 64bit
5609 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5610 i
.types
[op
].bitfield
.disp64
= 0;
5613 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5614 if (i
.types
[op
].bitfield
.disp32
5615 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5617 /* If this operand is at most 32 bits, convert
5618 to a signed 32 bit number and don't use 64bit
5620 op_disp
&= (((offsetT
) 2 << 31) - 1);
5621 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5622 i
.types
[op
].bitfield
.disp64
= 0;
5625 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5627 i
.types
[op
].bitfield
.disp8
= 0;
5628 i
.types
[op
].bitfield
.disp16
= 0;
5629 i
.types
[op
].bitfield
.disp32
= 0;
5630 i
.types
[op
].bitfield
.disp32s
= 0;
5631 i
.types
[op
].bitfield
.disp64
= 0;
5635 else if (flag_code
== CODE_64BIT
)
5637 if (fits_in_signed_long (op_disp
))
5639 i
.types
[op
].bitfield
.disp64
= 0;
5640 i
.types
[op
].bitfield
.disp32s
= 1;
5642 if (i
.prefix
[ADDR_PREFIX
]
5643 && fits_in_unsigned_long (op_disp
))
5644 i
.types
[op
].bitfield
.disp32
= 1;
5646 if ((i
.types
[op
].bitfield
.disp32
5647 || i
.types
[op
].bitfield
.disp32s
5648 || i
.types
[op
].bitfield
.disp16
)
5649 && fits_in_disp8 (op_disp
))
5650 i
.types
[op
].bitfield
.disp8
= 1;
5652 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5653 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5655 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5656 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5657 i
.types
[op
].bitfield
.disp8
= 0;
5658 i
.types
[op
].bitfield
.disp16
= 0;
5659 i
.types
[op
].bitfield
.disp32
= 0;
5660 i
.types
[op
].bitfield
.disp32s
= 0;
5661 i
.types
[op
].bitfield
.disp64
= 0;
5664 /* We only support 64bit displacement on constants. */
5665 i
.types
[op
].bitfield
.disp64
= 0;
5669 /* Return 1 if there is a match in broadcast bytes between operand
5670 GIVEN and instruction template T. */
5673 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5675 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5676 && i
.types
[given
].bitfield
.byte
)
5677 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5678 && i
.types
[given
].bitfield
.word
)
5679 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5680 && i
.types
[given
].bitfield
.dword
)
5681 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5682 && i
.types
[given
].bitfield
.qword
));
5685 /* Check if operands are valid for the instruction. */
5688 check_VecOperands (const insn_template
*t
)
5693 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5694 any one operand are implicity requiring AVX512VL support if the actual
5695 operand size is YMMword or XMMword. Since this function runs after
5696 template matching, there's no need to check for YMMword/XMMword in
5698 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5699 if (!cpu_flags_all_zero (&cpu
)
5700 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5701 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5703 for (op
= 0; op
< t
->operands
; ++op
)
5705 if (t
->operand_types
[op
].bitfield
.zmmword
5706 && (i
.types
[op
].bitfield
.ymmword
5707 || i
.types
[op
].bitfield
.xmmword
))
5709 i
.error
= unsupported
;
5715 /* Without VSIB byte, we can't have a vector register for index. */
5716 if (!t
->opcode_modifier
.vecsib
5718 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5719 || i
.index_reg
->reg_type
.bitfield
.ymmword
5720 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5722 i
.error
= unsupported_vector_index_register
;
5726 /* Check if default mask is allowed. */
5727 if (t
->opcode_modifier
.nodefmask
5728 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5730 i
.error
= no_default_mask
;
5734 /* For VSIB byte, we need a vector register for index, and all vector
5735 registers must be distinct. */
5736 if (t
->opcode_modifier
.vecsib
)
5739 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5740 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5741 || (t
->opcode_modifier
.vecsib
== VecSIB256
5742 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5743 || (t
->opcode_modifier
.vecsib
== VecSIB512
5744 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5746 i
.error
= invalid_vsib_address
;
5750 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5751 if (i
.reg_operands
== 2 && !i
.mask
)
5753 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5754 gas_assert (i
.types
[0].bitfield
.xmmword
5755 || i
.types
[0].bitfield
.ymmword
);
5756 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5757 gas_assert (i
.types
[2].bitfield
.xmmword
5758 || i
.types
[2].bitfield
.ymmword
);
5759 if (operand_check
== check_none
)
5761 if (register_number (i
.op
[0].regs
)
5762 != register_number (i
.index_reg
)
5763 && register_number (i
.op
[2].regs
)
5764 != register_number (i
.index_reg
)
5765 && register_number (i
.op
[0].regs
)
5766 != register_number (i
.op
[2].regs
))
5768 if (operand_check
== check_error
)
5770 i
.error
= invalid_vector_register_set
;
5773 as_warn (_("mask, index, and destination registers should be distinct"));
5775 else if (i
.reg_operands
== 1 && i
.mask
)
5777 if (i
.types
[1].bitfield
.class == RegSIMD
5778 && (i
.types
[1].bitfield
.xmmword
5779 || i
.types
[1].bitfield
.ymmword
5780 || i
.types
[1].bitfield
.zmmword
)
5781 && (register_number (i
.op
[1].regs
)
5782 == register_number (i
.index_reg
)))
5784 if (operand_check
== check_error
)
5786 i
.error
= invalid_vector_register_set
;
5789 if (operand_check
!= check_none
)
5790 as_warn (_("index and destination registers should be distinct"));
5795 /* Check if broadcast is supported by the instruction and is applied
5796 to the memory operand. */
5799 i386_operand_type type
, overlap
;
5801 /* Check if specified broadcast is supported in this instruction,
5802 and its broadcast bytes match the memory operand. */
5803 op
= i
.broadcast
->operand
;
5804 if (!t
->opcode_modifier
.broadcast
5805 || !(i
.flags
[op
] & Operand_Mem
)
5806 || (!i
.types
[op
].bitfield
.unspecified
5807 && !match_broadcast_size (t
, op
)))
5810 i
.error
= unsupported_broadcast
;
5814 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5815 * i
.broadcast
->type
);
5816 operand_type_set (&type
, 0);
5817 switch (i
.broadcast
->bytes
)
5820 type
.bitfield
.word
= 1;
5823 type
.bitfield
.dword
= 1;
5826 type
.bitfield
.qword
= 1;
5829 type
.bitfield
.xmmword
= 1;
5832 type
.bitfield
.ymmword
= 1;
5835 type
.bitfield
.zmmword
= 1;
5841 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5842 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5843 && t
->operand_types
[op
].bitfield
.byte
5844 + t
->operand_types
[op
].bitfield
.word
5845 + t
->operand_types
[op
].bitfield
.dword
5846 + t
->operand_types
[op
].bitfield
.qword
> 1)
5848 overlap
.bitfield
.xmmword
= 0;
5849 overlap
.bitfield
.ymmword
= 0;
5850 overlap
.bitfield
.zmmword
= 0;
5852 if (operand_type_all_zero (&overlap
))
5855 if (t
->opcode_modifier
.checkregsize
)
5859 type
.bitfield
.baseindex
= 1;
5860 for (j
= 0; j
< i
.operands
; ++j
)
5863 && !operand_type_register_match(i
.types
[j
],
5864 t
->operand_types
[j
],
5866 t
->operand_types
[op
]))
5871 /* If broadcast is supported in this instruction, we need to check if
5872 operand of one-element size isn't specified without broadcast. */
5873 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5875 /* Find memory operand. */
5876 for (op
= 0; op
< i
.operands
; op
++)
5877 if (i
.flags
[op
] & Operand_Mem
)
5879 gas_assert (op
< i
.operands
);
5880 /* Check size of the memory operand. */
5881 if (match_broadcast_size (t
, op
))
5883 i
.error
= broadcast_needed
;
5888 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5890 /* Check if requested masking is supported. */
5893 switch (t
->opcode_modifier
.masking
)
5897 case MERGING_MASKING
:
5898 if (i
.mask
->zeroing
)
5901 i
.error
= unsupported_masking
;
5905 case DYNAMIC_MASKING
:
5906 /* Memory destinations allow only merging masking. */
5907 if (i
.mask
->zeroing
&& i
.mem_operands
)
5909 /* Find memory operand. */
5910 for (op
= 0; op
< i
.operands
; op
++)
5911 if (i
.flags
[op
] & Operand_Mem
)
5913 gas_assert (op
< i
.operands
);
5914 if (op
== i
.operands
- 1)
5916 i
.error
= unsupported_masking
;
5926 /* Check if masking is applied to dest operand. */
5927 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5929 i
.error
= mask_not_on_destination
;
5936 if (!t
->opcode_modifier
.sae
5937 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5939 i
.error
= unsupported_rc_sae
;
5942 /* If the instruction has several immediate operands and one of
5943 them is rounding, the rounding operand should be the last
5944 immediate operand. */
5945 if (i
.imm_operands
> 1
5946 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5948 i
.error
= rc_sae_operand_not_last_imm
;
5953 /* Check vector Disp8 operand. */
5954 if (t
->opcode_modifier
.disp8memshift
5955 && i
.disp_encoding
!= disp_encoding_32bit
)
5958 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5959 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5960 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5963 const i386_operand_type
*type
= NULL
;
5966 for (op
= 0; op
< i
.operands
; op
++)
5967 if (i
.flags
[op
] & Operand_Mem
)
5969 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5970 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5971 else if (t
->operand_types
[op
].bitfield
.xmmword
5972 + t
->operand_types
[op
].bitfield
.ymmword
5973 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5974 type
= &t
->operand_types
[op
];
5975 else if (!i
.types
[op
].bitfield
.unspecified
)
5976 type
= &i
.types
[op
];
5978 else if (i
.types
[op
].bitfield
.class == RegSIMD
5979 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5981 if (i
.types
[op
].bitfield
.zmmword
)
5983 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5985 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5991 if (type
->bitfield
.zmmword
)
5993 else if (type
->bitfield
.ymmword
)
5995 else if (type
->bitfield
.xmmword
)
5999 /* For the check in fits_in_disp8(). */
6000 if (i
.memshift
== 0)
6004 for (op
= 0; op
< i
.operands
; op
++)
6005 if (operand_type_check (i
.types
[op
], disp
)
6006 && i
.op
[op
].disps
->X_op
== O_constant
)
6008 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6010 i
.types
[op
].bitfield
.disp8
= 1;
6013 i
.types
[op
].bitfield
.disp8
= 0;
6022 /* Check if operands are valid for the instruction. Update VEX
6026 VEX_check_operands (const insn_template
*t
)
6028 if (i
.vec_encoding
== vex_encoding_evex
)
6030 /* This instruction must be encoded with EVEX prefix. */
6031 if (!is_evex_encoding (t
))
6033 i
.error
= unsupported
;
6039 if (!t
->opcode_modifier
.vex
)
6041 /* This instruction template doesn't have VEX prefix. */
6042 if (i
.vec_encoding
!= vex_encoding_default
)
6044 i
.error
= unsupported
;
6050 /* Check the special Imm4 cases; must be the first operand. */
6051 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6053 if (i
.op
[0].imms
->X_op
!= O_constant
6054 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6060 /* Turn off Imm<N> so that update_imm won't complain. */
6061 operand_type_set (&i
.types
[0], 0);
6067 static const insn_template
*
6068 match_template (char mnem_suffix
)
6070 /* Points to template once we've found it. */
6071 const insn_template
*t
;
6072 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6073 i386_operand_type overlap4
;
6074 unsigned int found_reverse_match
;
6075 i386_opcode_modifier suffix_check
;
6076 i386_operand_type operand_types
[MAX_OPERANDS
];
6077 int addr_prefix_disp
;
6078 unsigned int j
, size_match
, check_register
;
6079 enum i386_error specific_error
= 0;
6081 #if MAX_OPERANDS != 5
6082 # error "MAX_OPERANDS must be 5."
6085 found_reverse_match
= 0;
6086 addr_prefix_disp
= -1;
6088 /* Prepare for mnemonic suffix check. */
6089 memset (&suffix_check
, 0, sizeof (suffix_check
));
6090 switch (mnem_suffix
)
6092 case BYTE_MNEM_SUFFIX
:
6093 suffix_check
.no_bsuf
= 1;
6095 case WORD_MNEM_SUFFIX
:
6096 suffix_check
.no_wsuf
= 1;
6098 case SHORT_MNEM_SUFFIX
:
6099 suffix_check
.no_ssuf
= 1;
6101 case LONG_MNEM_SUFFIX
:
6102 suffix_check
.no_lsuf
= 1;
6104 case QWORD_MNEM_SUFFIX
:
6105 suffix_check
.no_qsuf
= 1;
6108 /* NB: In Intel syntax, normally we can check for memory operand
6109 size when there is no mnemonic suffix. But jmp and call have
6110 2 different encodings with Dword memory operand size, one with
6111 No_ldSuf and the other without. i.suffix is set to
6112 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6113 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6114 suffix_check
.no_ldsuf
= 1;
6117 /* Must have right number of operands. */
6118 i
.error
= number_of_operands_mismatch
;
6120 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6122 addr_prefix_disp
= -1;
6123 found_reverse_match
= 0;
6125 if (i
.operands
!= t
->operands
)
6128 /* Check processor support. */
6129 i
.error
= unsupported
;
6130 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6133 /* Check AT&T mnemonic. */
6134 i
.error
= unsupported_with_intel_mnemonic
;
6135 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6138 /* Check AT&T/Intel syntax. */
6139 i
.error
= unsupported_syntax
;
6140 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6141 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6144 /* Check Intel64/AMD64 ISA. */
6148 /* Default: Don't accept Intel64. */
6149 if (t
->opcode_modifier
.isa64
== INTEL64
)
6153 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6154 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6158 /* -mintel64: Don't accept AMD64. */
6159 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6164 /* Check the suffix. */
6165 i
.error
= invalid_instruction_suffix
;
6166 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6167 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6168 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6169 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6170 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6171 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6174 size_match
= operand_size_match (t
);
6178 /* This is intentionally not
6180 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6182 as the case of a missing * on the operand is accepted (perhaps with
6183 a warning, issued further down). */
6184 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6186 i
.error
= operand_type_mismatch
;
6190 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6191 operand_types
[j
] = t
->operand_types
[j
];
6193 /* In general, don't allow
6194 - 64-bit operands outside of 64-bit mode,
6195 - 32-bit operands on pre-386. */
6196 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6197 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6198 && flag_code
!= CODE_64BIT
6199 && (t
->base_opcode
!= 0x0fc7
6200 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6201 || (i
.suffix
== LONG_MNEM_SUFFIX
6202 && !cpu_arch_flags
.bitfield
.cpui386
))
6204 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6205 && !intel_float_operand (t
->name
))
6206 : intel_float_operand (t
->name
) != 2)
6207 && (t
->operands
== i
.imm_operands
6208 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6209 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6210 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6211 || (operand_types
[j
].bitfield
.class != RegMMX
6212 && operand_types
[j
].bitfield
.class != RegSIMD
6213 && operand_types
[j
].bitfield
.class != RegMask
))
6214 && !t
->opcode_modifier
.vecsib
)
6217 /* Do not verify operands when there are none. */
6219 /* We've found a match; break out of loop. */
6222 if (!t
->opcode_modifier
.jump
6223 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6225 /* There should be only one Disp operand. */
6226 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6227 if (operand_type_check (operand_types
[j
], disp
))
6229 if (j
< MAX_OPERANDS
)
6231 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6233 addr_prefix_disp
= j
;
6235 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6236 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6240 override
= !override
;
6243 if (operand_types
[j
].bitfield
.disp32
6244 && operand_types
[j
].bitfield
.disp16
)
6246 operand_types
[j
].bitfield
.disp16
= override
;
6247 operand_types
[j
].bitfield
.disp32
= !override
;
6249 operand_types
[j
].bitfield
.disp32s
= 0;
6250 operand_types
[j
].bitfield
.disp64
= 0;
6254 if (operand_types
[j
].bitfield
.disp32s
6255 || operand_types
[j
].bitfield
.disp64
)
6257 operand_types
[j
].bitfield
.disp64
&= !override
;
6258 operand_types
[j
].bitfield
.disp32s
&= !override
;
6259 operand_types
[j
].bitfield
.disp32
= override
;
6261 operand_types
[j
].bitfield
.disp16
= 0;
6267 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6268 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6271 /* We check register size if needed. */
6272 if (t
->opcode_modifier
.checkregsize
)
6274 check_register
= (1 << t
->operands
) - 1;
6276 check_register
&= ~(1 << i
.broadcast
->operand
);
6281 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6282 switch (t
->operands
)
6285 if (!operand_type_match (overlap0
, i
.types
[0]))
6289 /* xchg %eax, %eax is a special case. It is an alias for nop
6290 only in 32bit mode and we can use opcode 0x90. In 64bit
6291 mode, we can't use 0x90 for xchg %eax, %eax since it should
6292 zero-extend %eax to %rax. */
6293 if (flag_code
== CODE_64BIT
6294 && t
->base_opcode
== 0x90
6295 && i
.types
[0].bitfield
.instance
== Accum
6296 && i
.types
[0].bitfield
.dword
6297 && i
.types
[1].bitfield
.instance
== Accum
6298 && i
.types
[1].bitfield
.dword
)
6300 /* xrelease mov %eax, <disp> is another special case. It must not
6301 match the accumulator-only encoding of mov. */
6302 if (flag_code
!= CODE_64BIT
6304 && t
->base_opcode
== 0xa0
6305 && i
.types
[0].bitfield
.instance
== Accum
6306 && (i
.flags
[1] & Operand_Mem
))
6311 if (!(size_match
& MATCH_STRAIGHT
))
6313 /* Reverse direction of operands if swapping is possible in the first
6314 place (operands need to be symmetric) and
6315 - the load form is requested, and the template is a store form,
6316 - the store form is requested, and the template is a load form,
6317 - the non-default (swapped) form is requested. */
6318 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6319 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6320 && !operand_type_all_zero (&overlap1
))
6321 switch (i
.dir_encoding
)
6323 case dir_encoding_load
:
6324 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6325 || t
->opcode_modifier
.regmem
)
6329 case dir_encoding_store
:
6330 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6331 && !t
->opcode_modifier
.regmem
)
6335 case dir_encoding_swap
:
6338 case dir_encoding_default
:
6341 /* If we want store form, we skip the current load. */
6342 if ((i
.dir_encoding
== dir_encoding_store
6343 || i
.dir_encoding
== dir_encoding_swap
)
6344 && i
.mem_operands
== 0
6345 && t
->opcode_modifier
.load
)
6350 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6351 if (!operand_type_match (overlap0
, i
.types
[0])
6352 || !operand_type_match (overlap1
, i
.types
[1])
6353 || ((check_register
& 3) == 3
6354 && !operand_type_register_match (i
.types
[0],
6359 /* Check if other direction is valid ... */
6360 if (!t
->opcode_modifier
.d
)
6364 if (!(size_match
& MATCH_REVERSE
))
6366 /* Try reversing direction of operands. */
6367 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6368 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6369 if (!operand_type_match (overlap0
, i
.types
[0])
6370 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6372 && !operand_type_register_match (i
.types
[0],
6373 operand_types
[i
.operands
- 1],
6374 i
.types
[i
.operands
- 1],
6377 /* Does not match either direction. */
6380 /* found_reverse_match holds which of D or FloatR
6382 if (!t
->opcode_modifier
.d
)
6383 found_reverse_match
= 0;
6384 else if (operand_types
[0].bitfield
.tbyte
)
6385 found_reverse_match
= Opcode_FloatD
;
6386 else if (operand_types
[0].bitfield
.xmmword
6387 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6388 || operand_types
[0].bitfield
.class == RegMMX
6389 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6390 || is_any_vex_encoding(t
))
6391 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6392 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6394 found_reverse_match
= Opcode_D
;
6395 if (t
->opcode_modifier
.floatr
)
6396 found_reverse_match
|= Opcode_FloatR
;
6400 /* Found a forward 2 operand match here. */
6401 switch (t
->operands
)
6404 overlap4
= operand_type_and (i
.types
[4],
6408 overlap3
= operand_type_and (i
.types
[3],
6412 overlap2
= operand_type_and (i
.types
[2],
6417 switch (t
->operands
)
6420 if (!operand_type_match (overlap4
, i
.types
[4])
6421 || !operand_type_register_match (i
.types
[3],
6428 if (!operand_type_match (overlap3
, i
.types
[3])
6429 || ((check_register
& 0xa) == 0xa
6430 && !operand_type_register_match (i
.types
[1],
6434 || ((check_register
& 0xc) == 0xc
6435 && !operand_type_register_match (i
.types
[2],
6442 /* Here we make use of the fact that there are no
6443 reverse match 3 operand instructions. */
6444 if (!operand_type_match (overlap2
, i
.types
[2])
6445 || ((check_register
& 5) == 5
6446 && !operand_type_register_match (i
.types
[0],
6450 || ((check_register
& 6) == 6
6451 && !operand_type_register_match (i
.types
[1],
6459 /* Found either forward/reverse 2, 3 or 4 operand match here:
6460 slip through to break. */
6463 /* Check if vector and VEX operands are valid. */
6464 if (check_VecOperands (t
) || VEX_check_operands (t
))
6466 specific_error
= i
.error
;
6470 /* We've found a match; break out of loop. */
6474 if (t
== current_templates
->end
)
6476 /* We found no match. */
6477 const char *err_msg
;
6478 switch (specific_error
? specific_error
: i
.error
)
6482 case operand_size_mismatch
:
6483 err_msg
= _("operand size mismatch");
6485 case operand_type_mismatch
:
6486 err_msg
= _("operand type mismatch");
6488 case register_type_mismatch
:
6489 err_msg
= _("register type mismatch");
6491 case number_of_operands_mismatch
:
6492 err_msg
= _("number of operands mismatch");
6494 case invalid_instruction_suffix
:
6495 err_msg
= _("invalid instruction suffix");
6498 err_msg
= _("constant doesn't fit in 4 bits");
6500 case unsupported_with_intel_mnemonic
:
6501 err_msg
= _("unsupported with Intel mnemonic");
6503 case unsupported_syntax
:
6504 err_msg
= _("unsupported syntax");
6507 as_bad (_("unsupported instruction `%s'"),
6508 current_templates
->start
->name
);
6510 case invalid_vsib_address
:
6511 err_msg
= _("invalid VSIB address");
6513 case invalid_vector_register_set
:
6514 err_msg
= _("mask, index, and destination registers must be distinct");
6516 case unsupported_vector_index_register
:
6517 err_msg
= _("unsupported vector index register");
6519 case unsupported_broadcast
:
6520 err_msg
= _("unsupported broadcast");
6522 case broadcast_needed
:
6523 err_msg
= _("broadcast is needed for operand of such type");
6525 case unsupported_masking
:
6526 err_msg
= _("unsupported masking");
6528 case mask_not_on_destination
:
6529 err_msg
= _("mask not on destination operand");
6531 case no_default_mask
:
6532 err_msg
= _("default mask isn't allowed");
6534 case unsupported_rc_sae
:
6535 err_msg
= _("unsupported static rounding/sae");
6537 case rc_sae_operand_not_last_imm
:
6539 err_msg
= _("RC/SAE operand must precede immediate operands");
6541 err_msg
= _("RC/SAE operand must follow immediate operands");
6543 case invalid_register_operand
:
6544 err_msg
= _("invalid register operand");
6547 as_bad (_("%s for `%s'"), err_msg
,
6548 current_templates
->start
->name
);
6552 if (!quiet_warnings
)
6555 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6556 as_warn (_("indirect %s without `*'"), t
->name
);
6558 if (t
->opcode_modifier
.isprefix
6559 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6561 /* Warn them that a data or address size prefix doesn't
6562 affect assembly of the next line of code. */
6563 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6567 /* Copy the template we found. */
6570 if (addr_prefix_disp
!= -1)
6571 i
.tm
.operand_types
[addr_prefix_disp
]
6572 = operand_types
[addr_prefix_disp
];
6574 if (found_reverse_match
)
6576 /* If we found a reverse match we must alter the opcode direction
6577 bit and clear/flip the regmem modifier one. found_reverse_match
6578 holds bits to change (different for int & float insns). */
6580 i
.tm
.base_opcode
^= found_reverse_match
;
6582 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6583 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6585 /* Certain SIMD insns have their load forms specified in the opcode
6586 table, and hence we need to _set_ RegMem instead of clearing it.
6587 We need to avoid setting the bit though on insns like KMOVW. */
6588 i
.tm
.opcode_modifier
.regmem
6589 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6590 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6591 && !i
.tm
.opcode_modifier
.regmem
;
6600 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6601 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6603 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6605 as_bad (_("`%s' operand %u must use `%ses' segment"),
6607 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6612 /* There's only ever one segment override allowed per instruction.
6613 This instruction possibly has a legal segment override on the
6614 second operand, so copy the segment to where non-string
6615 instructions store it, allowing common code. */
6616 i
.seg
[op
] = i
.seg
[1];
6622 process_suffix (void)
6624 /* If matched instruction specifies an explicit instruction mnemonic
6626 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6627 i
.suffix
= WORD_MNEM_SUFFIX
;
6628 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6629 i
.suffix
= LONG_MNEM_SUFFIX
;
6630 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6631 i
.suffix
= QWORD_MNEM_SUFFIX
;
6632 else if (i
.reg_operands
6633 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6634 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6636 unsigned int numop
= i
.operands
;
6638 /* movsx/movzx want only their source operand considered here, for the
6639 ambiguity checking below. The suffix will be replaced afterwards
6640 to represent the destination (register). */
6641 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6642 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6645 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6646 if (i
.tm
.base_opcode
== 0xf20f38f0
6647 && i
.tm
.operand_types
[1].bitfield
.qword
)
6650 /* If there's no instruction mnemonic suffix we try to invent one
6651 based on GPR operands. */
6654 /* We take i.suffix from the last register operand specified,
6655 Destination register type is more significant than source
6656 register type. crc32 in SSE4.2 prefers source register
6658 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6661 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6662 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6664 if (i
.types
[op
].bitfield
.class != Reg
)
6666 if (i
.types
[op
].bitfield
.byte
)
6667 i
.suffix
= BYTE_MNEM_SUFFIX
;
6668 else if (i
.types
[op
].bitfield
.word
)
6669 i
.suffix
= WORD_MNEM_SUFFIX
;
6670 else if (i
.types
[op
].bitfield
.dword
)
6671 i
.suffix
= LONG_MNEM_SUFFIX
;
6672 else if (i
.types
[op
].bitfield
.qword
)
6673 i
.suffix
= QWORD_MNEM_SUFFIX
;
6679 /* As an exception, movsx/movzx silently default to a byte source
6681 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6682 && !i
.suffix
&& !intel_syntax
)
6683 i
.suffix
= BYTE_MNEM_SUFFIX
;
6685 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6688 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6689 && i
.tm
.opcode_modifier
.no_bsuf
)
6691 else if (!check_byte_reg ())
6694 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6697 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6698 && i
.tm
.opcode_modifier
.no_lsuf
6699 && !i
.tm
.opcode_modifier
.todword
6700 && !i
.tm
.opcode_modifier
.toqword
)
6702 else if (!check_long_reg ())
6705 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6708 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6709 && i
.tm
.opcode_modifier
.no_qsuf
6710 && !i
.tm
.opcode_modifier
.todword
6711 && !i
.tm
.opcode_modifier
.toqword
)
6713 else if (!check_qword_reg ())
6716 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6719 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6720 && i
.tm
.opcode_modifier
.no_wsuf
)
6722 else if (!check_word_reg ())
6725 else if (intel_syntax
6726 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6727 /* Do nothing if the instruction is going to ignore the prefix. */
6732 /* Undo the movsx/movzx change done above. */
6735 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6738 i
.suffix
= stackop_size
;
6739 if (stackop_size
== LONG_MNEM_SUFFIX
)
6741 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6742 .code16gcc directive to support 16-bit mode with
6743 32-bit address. For IRET without a suffix, generate
6744 16-bit IRET (opcode 0xcf) to return from an interrupt
6746 if (i
.tm
.base_opcode
== 0xcf)
6748 i
.suffix
= WORD_MNEM_SUFFIX
;
6749 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6751 /* Warn about changed behavior for segment register push/pop. */
6752 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6753 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6758 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6759 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6760 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6761 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6762 && i
.tm
.extension_opcode
<= 3)))
6767 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6769 i
.suffix
= QWORD_MNEM_SUFFIX
;
6774 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6775 i
.suffix
= LONG_MNEM_SUFFIX
;
6778 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6779 i
.suffix
= WORD_MNEM_SUFFIX
;
6785 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6786 /* Also cover lret/retf/iret in 64-bit mode. */
6787 || (flag_code
== CODE_64BIT
6788 && !i
.tm
.opcode_modifier
.no_lsuf
6789 && !i
.tm
.opcode_modifier
.no_qsuf
))
6790 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6791 /* Accept FLDENV et al without suffix. */
6792 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6794 unsigned int suffixes
, evex
= 0;
6796 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6797 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6799 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6801 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6803 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6805 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6808 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6809 also suitable for AT&T syntax mode, it was requested that this be
6810 restricted to just Intel syntax. */
6811 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6815 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6817 if (is_evex_encoding (&i
.tm
)
6818 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6820 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6821 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6822 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6823 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6824 if (!i
.tm
.opcode_modifier
.evex
6825 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6826 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6829 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6830 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6831 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6834 /* Any properly sized operand disambiguates the insn. */
6835 if (i
.types
[op
].bitfield
.xmmword
6836 || i
.types
[op
].bitfield
.ymmword
6837 || i
.types
[op
].bitfield
.zmmword
)
6839 suffixes
&= ~(7 << 6);
6844 if ((i
.flags
[op
] & Operand_Mem
)
6845 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6847 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6849 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6851 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6853 if (is_evex_encoding (&i
.tm
))
6859 /* Are multiple suffixes / operand sizes allowed? */
6860 if (suffixes
& (suffixes
- 1))
6863 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6864 || operand_check
== check_error
))
6866 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6869 if (operand_check
== check_error
)
6871 as_bad (_("no instruction mnemonic suffix given and "
6872 "no register operands; can't size `%s'"), i
.tm
.name
);
6875 if (operand_check
== check_warning
)
6876 as_warn (_("%s; using default for `%s'"),
6878 ? _("ambiguous operand size")
6879 : _("no instruction mnemonic suffix given and "
6880 "no register operands"),
6883 if (i
.tm
.opcode_modifier
.floatmf
)
6884 i
.suffix
= SHORT_MNEM_SUFFIX
;
6885 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6886 || (i
.tm
.base_opcode
== 0x63
6887 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6888 /* handled below */;
6890 i
.tm
.opcode_modifier
.evex
= evex
;
6891 else if (flag_code
== CODE_16BIT
)
6892 i
.suffix
= WORD_MNEM_SUFFIX
;
6893 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6894 i
.suffix
= LONG_MNEM_SUFFIX
;
6896 i
.suffix
= QWORD_MNEM_SUFFIX
;
6900 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6901 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6903 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6904 In AT&T syntax, if there is no suffix (warned about above), the default
6905 will be byte extension. */
6906 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6907 i
.tm
.base_opcode
|= 1;
6909 /* For further processing, the suffix should represent the destination
6910 (register). This is already the case when one was used with
6911 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6912 no suffix to begin with. */
6913 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6915 if (i
.types
[1].bitfield
.word
)
6916 i
.suffix
= WORD_MNEM_SUFFIX
;
6917 else if (i
.types
[1].bitfield
.qword
)
6918 i
.suffix
= QWORD_MNEM_SUFFIX
;
6920 i
.suffix
= LONG_MNEM_SUFFIX
;
6922 i
.tm
.opcode_modifier
.w
= 0;
6926 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6927 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6928 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6930 /* Change the opcode based on the operand size given by i.suffix. */
6933 /* Size floating point instruction. */
6934 case LONG_MNEM_SUFFIX
:
6935 if (i
.tm
.opcode_modifier
.floatmf
)
6937 i
.tm
.base_opcode
^= 4;
6941 case WORD_MNEM_SUFFIX
:
6942 case QWORD_MNEM_SUFFIX
:
6943 /* It's not a byte, select word/dword operation. */
6944 if (i
.tm
.opcode_modifier
.w
)
6947 i
.tm
.base_opcode
|= 8;
6949 i
.tm
.base_opcode
|= 1;
6952 case SHORT_MNEM_SUFFIX
:
6953 /* Now select between word & dword operations via the operand
6954 size prefix, except for instructions that will ignore this
6956 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6957 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6958 && !i
.tm
.opcode_modifier
.floatmf
6959 && !is_any_vex_encoding (&i
.tm
)
6960 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6961 || (flag_code
== CODE_64BIT
6962 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6964 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6966 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6967 prefix
= ADDR_PREFIX_OPCODE
;
6969 if (!add_prefix (prefix
))
6973 /* Set mode64 for an operand. */
6974 if (i
.suffix
== QWORD_MNEM_SUFFIX
6975 && flag_code
== CODE_64BIT
6976 && !i
.tm
.opcode_modifier
.norex64
6977 && !i
.tm
.opcode_modifier
.vexw
6978 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6980 && ! (i
.operands
== 2
6981 && i
.tm
.base_opcode
== 0x90
6982 && i
.tm
.extension_opcode
== None
6983 && i
.types
[0].bitfield
.instance
== Accum
6984 && i
.types
[0].bitfield
.qword
6985 && i
.types
[1].bitfield
.instance
== Accum
6986 && i
.types
[1].bitfield
.qword
))
6992 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6994 gas_assert (!i
.suffix
);
6995 gas_assert (i
.reg_operands
);
6997 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7000 /* The address size override prefix changes the size of the
7002 if (flag_code
== CODE_64BIT
7003 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7005 as_bad (_("16-bit addressing unavailable for `%s'"),
7010 if ((flag_code
== CODE_32BIT
7011 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7012 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7013 && !add_prefix (ADDR_PREFIX_OPCODE
))
7018 /* Check invalid register operand when the address size override
7019 prefix changes the size of register operands. */
7021 enum { need_word
, need_dword
, need_qword
} need
;
7023 if (flag_code
== CODE_32BIT
)
7024 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7025 else if (i
.prefix
[ADDR_PREFIX
])
7028 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7030 for (op
= 0; op
< i
.operands
; op
++)
7032 if (i
.types
[op
].bitfield
.class != Reg
)
7038 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7042 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7046 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7051 as_bad (_("invalid register operand size for `%s'"),
7062 check_byte_reg (void)
7066 for (op
= i
.operands
; --op
>= 0;)
7068 /* Skip non-register operands. */
7069 if (i
.types
[op
].bitfield
.class != Reg
)
7072 /* If this is an eight bit register, it's OK. If it's the 16 or
7073 32 bit version of an eight bit register, we will just use the
7074 low portion, and that's OK too. */
7075 if (i
.types
[op
].bitfield
.byte
)
7078 /* I/O port address operands are OK too. */
7079 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7080 && i
.tm
.operand_types
[op
].bitfield
.word
)
7083 /* crc32 only wants its source operand checked here. */
7084 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7087 /* Any other register is bad. */
7088 if (i
.types
[op
].bitfield
.class == Reg
7089 || i
.types
[op
].bitfield
.class == RegMMX
7090 || i
.types
[op
].bitfield
.class == RegSIMD
7091 || i
.types
[op
].bitfield
.class == SReg
7092 || i
.types
[op
].bitfield
.class == RegCR
7093 || i
.types
[op
].bitfield
.class == RegDR
7094 || i
.types
[op
].bitfield
.class == RegTR
)
7096 as_bad (_("`%s%s' not allowed with `%s%c'"),
7098 i
.op
[op
].regs
->reg_name
,
7108 check_long_reg (void)
7112 for (op
= i
.operands
; --op
>= 0;)
7113 /* Skip non-register operands. */
7114 if (i
.types
[op
].bitfield
.class != Reg
)
7116 /* Reject eight bit registers, except where the template requires
7117 them. (eg. movzb) */
7118 else if (i
.types
[op
].bitfield
.byte
7119 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7120 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7121 && (i
.tm
.operand_types
[op
].bitfield
.word
7122 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7124 as_bad (_("`%s%s' not allowed with `%s%c'"),
7126 i
.op
[op
].regs
->reg_name
,
7131 /* Error if the e prefix on a general reg is missing. */
7132 else if (i
.types
[op
].bitfield
.word
7133 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7134 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7135 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7137 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7138 register_prefix
, i
.op
[op
].regs
->reg_name
,
7142 /* Warn if the r prefix on a general reg is present. */
7143 else if (i
.types
[op
].bitfield
.qword
7144 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7145 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7146 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7149 && i
.tm
.opcode_modifier
.toqword
7150 && i
.types
[0].bitfield
.class != RegSIMD
)
7152 /* Convert to QWORD. We want REX byte. */
7153 i
.suffix
= QWORD_MNEM_SUFFIX
;
7157 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7158 register_prefix
, i
.op
[op
].regs
->reg_name
,
7167 check_qword_reg (void)
7171 for (op
= i
.operands
; --op
>= 0; )
7172 /* Skip non-register operands. */
7173 if (i
.types
[op
].bitfield
.class != Reg
)
7175 /* Reject eight bit registers, except where the template requires
7176 them. (eg. movzb) */
7177 else if (i
.types
[op
].bitfield
.byte
7178 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7179 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7180 && (i
.tm
.operand_types
[op
].bitfield
.word
7181 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7183 as_bad (_("`%s%s' not allowed with `%s%c'"),
7185 i
.op
[op
].regs
->reg_name
,
7190 /* Warn if the r prefix on a general reg is missing. */
7191 else if ((i
.types
[op
].bitfield
.word
7192 || i
.types
[op
].bitfield
.dword
)
7193 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7194 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7195 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7197 /* Prohibit these changes in the 64bit mode, since the
7198 lowering is more complicated. */
7200 && i
.tm
.opcode_modifier
.todword
7201 && i
.types
[0].bitfield
.class != RegSIMD
)
7203 /* Convert to DWORD. We don't want REX byte. */
7204 i
.suffix
= LONG_MNEM_SUFFIX
;
7208 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7209 register_prefix
, i
.op
[op
].regs
->reg_name
,
7218 check_word_reg (void)
7221 for (op
= i
.operands
; --op
>= 0;)
7222 /* Skip non-register operands. */
7223 if (i
.types
[op
].bitfield
.class != Reg
)
7225 /* Reject eight bit registers, except where the template requires
7226 them. (eg. movzb) */
7227 else if (i
.types
[op
].bitfield
.byte
7228 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7229 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7230 && (i
.tm
.operand_types
[op
].bitfield
.word
7231 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7233 as_bad (_("`%s%s' not allowed with `%s%c'"),
7235 i
.op
[op
].regs
->reg_name
,
7240 /* Error if the e or r prefix on a general reg is present. */
7241 else if ((i
.types
[op
].bitfield
.dword
7242 || i
.types
[op
].bitfield
.qword
)
7243 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7244 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7245 && i
.tm
.operand_types
[op
].bitfield
.word
)
7247 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7248 register_prefix
, i
.op
[op
].regs
->reg_name
,
7256 update_imm (unsigned int j
)
7258 i386_operand_type overlap
= i
.types
[j
];
7259 if ((overlap
.bitfield
.imm8
7260 || overlap
.bitfield
.imm8s
7261 || overlap
.bitfield
.imm16
7262 || overlap
.bitfield
.imm32
7263 || overlap
.bitfield
.imm32s
7264 || overlap
.bitfield
.imm64
)
7265 && !operand_type_equal (&overlap
, &imm8
)
7266 && !operand_type_equal (&overlap
, &imm8s
)
7267 && !operand_type_equal (&overlap
, &imm16
)
7268 && !operand_type_equal (&overlap
, &imm32
)
7269 && !operand_type_equal (&overlap
, &imm32s
)
7270 && !operand_type_equal (&overlap
, &imm64
))
7274 i386_operand_type temp
;
7276 operand_type_set (&temp
, 0);
7277 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7279 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7280 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7282 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7283 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7284 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7286 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7287 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7290 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7293 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7294 || operand_type_equal (&overlap
, &imm16_32
)
7295 || operand_type_equal (&overlap
, &imm16_32s
))
7297 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7302 if (!operand_type_equal (&overlap
, &imm8
)
7303 && !operand_type_equal (&overlap
, &imm8s
)
7304 && !operand_type_equal (&overlap
, &imm16
)
7305 && !operand_type_equal (&overlap
, &imm32
)
7306 && !operand_type_equal (&overlap
, &imm32s
)
7307 && !operand_type_equal (&overlap
, &imm64
))
7309 as_bad (_("no instruction mnemonic suffix given; "
7310 "can't determine immediate size"));
7314 i
.types
[j
] = overlap
;
7324 /* Update the first 2 immediate operands. */
7325 n
= i
.operands
> 2 ? 2 : i
.operands
;
7328 for (j
= 0; j
< n
; j
++)
7329 if (update_imm (j
) == 0)
7332 /* The 3rd operand can't be immediate operand. */
7333 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7340 process_operands (void)
7342 /* Default segment register this instruction will use for memory
7343 accesses. 0 means unknown. This is only for optimizing out
7344 unnecessary segment overrides. */
7345 const seg_entry
*default_seg
= 0;
7347 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7349 unsigned int dupl
= i
.operands
;
7350 unsigned int dest
= dupl
- 1;
7353 /* The destination must be an xmm register. */
7354 gas_assert (i
.reg_operands
7355 && MAX_OPERANDS
> dupl
7356 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7358 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7359 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7361 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7363 /* Keep xmm0 for instructions with VEX prefix and 3
7365 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7366 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7371 /* We remove the first xmm0 and keep the number of
7372 operands unchanged, which in fact duplicates the
7374 for (j
= 1; j
< i
.operands
; j
++)
7376 i
.op
[j
- 1] = i
.op
[j
];
7377 i
.types
[j
- 1] = i
.types
[j
];
7378 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7379 i
.flags
[j
- 1] = i
.flags
[j
];
7383 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7385 gas_assert ((MAX_OPERANDS
- 1) > dupl
7386 && (i
.tm
.opcode_modifier
.vexsources
7389 /* Add the implicit xmm0 for instructions with VEX prefix
7391 for (j
= i
.operands
; j
> 0; j
--)
7393 i
.op
[j
] = i
.op
[j
- 1];
7394 i
.types
[j
] = i
.types
[j
- 1];
7395 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7396 i
.flags
[j
] = i
.flags
[j
- 1];
7399 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7400 i
.types
[0] = regxmm
;
7401 i
.tm
.operand_types
[0] = regxmm
;
7404 i
.reg_operands
+= 2;
7409 i
.op
[dupl
] = i
.op
[dest
];
7410 i
.types
[dupl
] = i
.types
[dest
];
7411 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7412 i
.flags
[dupl
] = i
.flags
[dest
];
7421 i
.op
[dupl
] = i
.op
[dest
];
7422 i
.types
[dupl
] = i
.types
[dest
];
7423 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7424 i
.flags
[dupl
] = i
.flags
[dest
];
7427 if (i
.tm
.opcode_modifier
.immext
)
7430 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7431 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7435 for (j
= 1; j
< i
.operands
; j
++)
7437 i
.op
[j
- 1] = i
.op
[j
];
7438 i
.types
[j
- 1] = i
.types
[j
];
7440 /* We need to adjust fields in i.tm since they are used by
7441 build_modrm_byte. */
7442 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7444 i
.flags
[j
- 1] = i
.flags
[j
];
7451 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7453 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7455 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7456 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7457 regnum
= register_number (i
.op
[1].regs
);
7458 first_reg_in_group
= regnum
& ~3;
7459 last_reg_in_group
= first_reg_in_group
+ 3;
7460 if (regnum
!= first_reg_in_group
)
7461 as_warn (_("source register `%s%s' implicitly denotes"
7462 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7463 register_prefix
, i
.op
[1].regs
->reg_name
,
7464 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7465 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7468 else if (i
.tm
.opcode_modifier
.regkludge
)
7470 /* The imul $imm, %reg instruction is converted into
7471 imul $imm, %reg, %reg, and the clr %reg instruction
7472 is converted into xor %reg, %reg. */
7474 unsigned int first_reg_op
;
7476 if (operand_type_check (i
.types
[0], reg
))
7480 /* Pretend we saw the extra register operand. */
7481 gas_assert (i
.reg_operands
== 1
7482 && i
.op
[first_reg_op
+ 1].regs
== 0);
7483 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7484 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7489 if (i
.tm
.opcode_modifier
.modrm
)
7491 /* The opcode is completed (modulo i.tm.extension_opcode which
7492 must be put into the modrm byte). Now, we make the modrm and
7493 index base bytes based on all the info we've collected. */
7495 default_seg
= build_modrm_byte ();
7497 else if (i
.types
[0].bitfield
.class == SReg
)
7499 if (flag_code
!= CODE_64BIT
7500 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7501 && i
.op
[0].regs
->reg_num
== 1
7502 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7503 && i
.op
[0].regs
->reg_num
< 4)
7505 as_bad (_("you can't `%s %s%s'"),
7506 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7509 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7511 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7512 i
.tm
.opcode_length
= 2;
7514 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7516 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7520 else if (i
.tm
.opcode_modifier
.isstring
)
7522 /* For the string instructions that allow a segment override
7523 on one of their operands, the default segment is ds. */
7526 else if (i
.short_form
)
7528 /* The register or float register operand is in operand
7530 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7532 /* Register goes in low 3 bits of opcode. */
7533 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7534 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7536 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7538 /* Warn about some common errors, but press on regardless.
7539 The first case can be generated by gcc (<= 2.8.1). */
7540 if (i
.operands
== 2)
7542 /* Reversed arguments on faddp, fsubp, etc. */
7543 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7544 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7545 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7549 /* Extraneous `l' suffix on fp insn. */
7550 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7551 register_prefix
, i
.op
[0].regs
->reg_name
);
7556 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7557 && i
.tm
.base_opcode
== 0x8d /* lea */
7558 && !is_any_vex_encoding(&i
.tm
))
7560 if (!quiet_warnings
)
7561 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7565 i
.prefix
[SEG_PREFIX
] = 0;
7569 /* If a segment was explicitly specified, and the specified segment
7570 is neither the default nor the one already recorded from a prefix,
7571 use an opcode prefix to select it. If we never figured out what
7572 the default segment is, then default_seg will be zero at this
7573 point, and the specified segment prefix will always be used. */
7575 && i
.seg
[0] != default_seg
7576 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7578 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7584 static const seg_entry
*
7585 build_modrm_byte (void)
7587 const seg_entry
*default_seg
= 0;
7588 unsigned int source
, dest
;
7591 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7594 unsigned int nds
, reg_slot
;
7597 dest
= i
.operands
- 1;
7600 /* There are 2 kinds of instructions:
7601 1. 5 operands: 4 register operands or 3 register operands
7602 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7603 VexW0 or VexW1. The destination must be either XMM, YMM or
7605 2. 4 operands: 4 register operands or 3 register operands
7606 plus 1 memory operand, with VexXDS. */
7607 gas_assert ((i
.reg_operands
== 4
7608 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7609 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7610 && i
.tm
.opcode_modifier
.vexw
7611 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7613 /* If VexW1 is set, the first non-immediate operand is the source and
7614 the second non-immediate one is encoded in the immediate operand. */
7615 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7617 source
= i
.imm_operands
;
7618 reg_slot
= i
.imm_operands
+ 1;
7622 source
= i
.imm_operands
+ 1;
7623 reg_slot
= i
.imm_operands
;
7626 if (i
.imm_operands
== 0)
7628 /* When there is no immediate operand, generate an 8bit
7629 immediate operand to encode the first operand. */
7630 exp
= &im_expressions
[i
.imm_operands
++];
7631 i
.op
[i
.operands
].imms
= exp
;
7632 i
.types
[i
.operands
] = imm8
;
7635 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7636 exp
->X_op
= O_constant
;
7637 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7638 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7642 gas_assert (i
.imm_operands
== 1);
7643 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7644 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7646 /* Turn on Imm8 again so that output_imm will generate it. */
7647 i
.types
[0].bitfield
.imm8
= 1;
7649 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7650 i
.op
[0].imms
->X_add_number
7651 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7652 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7655 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7656 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7661 /* i.reg_operands MUST be the number of real register operands;
7662 implicit registers do not count. If there are 3 register
7663 operands, it must be a instruction with VexNDS. For a
7664 instruction with VexNDD, the destination register is encoded
7665 in VEX prefix. If there are 4 register operands, it must be
7666 a instruction with VEX prefix and 3 sources. */
7667 if (i
.mem_operands
== 0
7668 && ((i
.reg_operands
== 2
7669 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7670 || (i
.reg_operands
== 3
7671 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7672 || (i
.reg_operands
== 4 && vex_3_sources
)))
7680 /* When there are 3 operands, one of them may be immediate,
7681 which may be the first or the last operand. Otherwise,
7682 the first operand must be shift count register (cl) or it
7683 is an instruction with VexNDS. */
7684 gas_assert (i
.imm_operands
== 1
7685 || (i
.imm_operands
== 0
7686 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7687 || (i
.types
[0].bitfield
.instance
== RegC
7688 && i
.types
[0].bitfield
.byte
))));
7689 if (operand_type_check (i
.types
[0], imm
)
7690 || (i
.types
[0].bitfield
.instance
== RegC
7691 && i
.types
[0].bitfield
.byte
))
7697 /* When there are 4 operands, the first two must be 8bit
7698 immediate operands. The source operand will be the 3rd
7701 For instructions with VexNDS, if the first operand
7702 an imm8, the source operand is the 2nd one. If the last
7703 operand is imm8, the source operand is the first one. */
7704 gas_assert ((i
.imm_operands
== 2
7705 && i
.types
[0].bitfield
.imm8
7706 && i
.types
[1].bitfield
.imm8
)
7707 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7708 && i
.imm_operands
== 1
7709 && (i
.types
[0].bitfield
.imm8
7710 || i
.types
[i
.operands
- 1].bitfield
.imm8
7712 if (i
.imm_operands
== 2)
7716 if (i
.types
[0].bitfield
.imm8
)
7723 if (is_evex_encoding (&i
.tm
))
7725 /* For EVEX instructions, when there are 5 operands, the
7726 first one must be immediate operand. If the second one
7727 is immediate operand, the source operand is the 3th
7728 one. If the last one is immediate operand, the source
7729 operand is the 2nd one. */
7730 gas_assert (i
.imm_operands
== 2
7731 && i
.tm
.opcode_modifier
.sae
7732 && operand_type_check (i
.types
[0], imm
));
7733 if (operand_type_check (i
.types
[1], imm
))
7735 else if (operand_type_check (i
.types
[4], imm
))
7749 /* RC/SAE operand could be between DEST and SRC. That happens
7750 when one operand is GPR and the other one is XMM/YMM/ZMM
7752 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7755 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7757 /* For instructions with VexNDS, the register-only source
7758 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7759 register. It is encoded in VEX prefix. */
7761 i386_operand_type op
;
7764 /* Check register-only source operand when two source
7765 operands are swapped. */
7766 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7767 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7775 op
= i
.tm
.operand_types
[vvvv
];
7776 if ((dest
+ 1) >= i
.operands
7777 || ((op
.bitfield
.class != Reg
7778 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7779 && op
.bitfield
.class != RegSIMD
7780 && !operand_type_equal (&op
, ®mask
)))
7782 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7788 /* One of the register operands will be encoded in the i.rm.reg
7789 field, the other in the combined i.rm.mode and i.rm.regmem
7790 fields. If no form of this instruction supports a memory
7791 destination operand, then we assume the source operand may
7792 sometimes be a memory operand and so we need to store the
7793 destination in the i.rm.reg field. */
7794 if (!i
.tm
.opcode_modifier
.regmem
7795 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7797 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7798 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7799 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7800 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7801 i
.has_regmmx
= TRUE
;
7802 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7803 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7805 if (i
.types
[dest
].bitfield
.zmmword
7806 || i
.types
[source
].bitfield
.zmmword
)
7807 i
.has_regzmm
= TRUE
;
7808 else if (i
.types
[dest
].bitfield
.ymmword
7809 || i
.types
[source
].bitfield
.ymmword
)
7810 i
.has_regymm
= TRUE
;
7812 i
.has_regxmm
= TRUE
;
7814 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7816 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7818 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7820 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7825 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7826 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7827 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7829 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7831 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7833 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7836 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7838 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7841 add_prefix (LOCK_PREFIX_OPCODE
);
7845 { /* If it's not 2 reg operands... */
7850 unsigned int fake_zero_displacement
= 0;
7853 for (op
= 0; op
< i
.operands
; op
++)
7854 if (i
.flags
[op
] & Operand_Mem
)
7856 gas_assert (op
< i
.operands
);
7858 if (i
.tm
.opcode_modifier
.vecsib
)
7860 if (i
.index_reg
->reg_num
== RegIZ
)
7863 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7866 i
.sib
.base
= NO_BASE_REGISTER
;
7867 i
.sib
.scale
= i
.log2_scale_factor
;
7868 i
.types
[op
].bitfield
.disp8
= 0;
7869 i
.types
[op
].bitfield
.disp16
= 0;
7870 i
.types
[op
].bitfield
.disp64
= 0;
7871 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7873 /* Must be 32 bit */
7874 i
.types
[op
].bitfield
.disp32
= 1;
7875 i
.types
[op
].bitfield
.disp32s
= 0;
7879 i
.types
[op
].bitfield
.disp32
= 0;
7880 i
.types
[op
].bitfield
.disp32s
= 1;
7883 i
.sib
.index
= i
.index_reg
->reg_num
;
7884 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7886 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7892 if (i
.base_reg
== 0)
7895 if (!i
.disp_operands
)
7896 fake_zero_displacement
= 1;
7897 if (i
.index_reg
== 0)
7899 i386_operand_type newdisp
;
7901 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7902 /* Operand is just <disp> */
7903 if (flag_code
== CODE_64BIT
)
7905 /* 64bit mode overwrites the 32bit absolute
7906 addressing by RIP relative addressing and
7907 absolute addressing is encoded by one of the
7908 redundant SIB forms. */
7909 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7910 i
.sib
.base
= NO_BASE_REGISTER
;
7911 i
.sib
.index
= NO_INDEX_REGISTER
;
7912 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7914 else if ((flag_code
== CODE_16BIT
)
7915 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7917 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7922 i
.rm
.regmem
= NO_BASE_REGISTER
;
7925 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7926 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7928 else if (!i
.tm
.opcode_modifier
.vecsib
)
7930 /* !i.base_reg && i.index_reg */
7931 if (i
.index_reg
->reg_num
== RegIZ
)
7932 i
.sib
.index
= NO_INDEX_REGISTER
;
7934 i
.sib
.index
= i
.index_reg
->reg_num
;
7935 i
.sib
.base
= NO_BASE_REGISTER
;
7936 i
.sib
.scale
= i
.log2_scale_factor
;
7937 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7938 i
.types
[op
].bitfield
.disp8
= 0;
7939 i
.types
[op
].bitfield
.disp16
= 0;
7940 i
.types
[op
].bitfield
.disp64
= 0;
7941 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7943 /* Must be 32 bit */
7944 i
.types
[op
].bitfield
.disp32
= 1;
7945 i
.types
[op
].bitfield
.disp32s
= 0;
7949 i
.types
[op
].bitfield
.disp32
= 0;
7950 i
.types
[op
].bitfield
.disp32s
= 1;
7952 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7956 /* RIP addressing for 64bit mode. */
7957 else if (i
.base_reg
->reg_num
== RegIP
)
7959 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7960 i
.rm
.regmem
= NO_BASE_REGISTER
;
7961 i
.types
[op
].bitfield
.disp8
= 0;
7962 i
.types
[op
].bitfield
.disp16
= 0;
7963 i
.types
[op
].bitfield
.disp32
= 0;
7964 i
.types
[op
].bitfield
.disp32s
= 1;
7965 i
.types
[op
].bitfield
.disp64
= 0;
7966 i
.flags
[op
] |= Operand_PCrel
;
7967 if (! i
.disp_operands
)
7968 fake_zero_displacement
= 1;
7970 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7972 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7973 switch (i
.base_reg
->reg_num
)
7976 if (i
.index_reg
== 0)
7978 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7979 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7983 if (i
.index_reg
== 0)
7986 if (operand_type_check (i
.types
[op
], disp
) == 0)
7988 /* fake (%bp) into 0(%bp) */
7989 i
.types
[op
].bitfield
.disp8
= 1;
7990 fake_zero_displacement
= 1;
7993 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7994 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7996 default: /* (%si) -> 4 or (%di) -> 5 */
7997 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7999 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8001 else /* i.base_reg and 32/64 bit mode */
8003 if (flag_code
== CODE_64BIT
8004 && operand_type_check (i
.types
[op
], disp
))
8006 i
.types
[op
].bitfield
.disp16
= 0;
8007 i
.types
[op
].bitfield
.disp64
= 0;
8008 if (i
.prefix
[ADDR_PREFIX
] == 0)
8010 i
.types
[op
].bitfield
.disp32
= 0;
8011 i
.types
[op
].bitfield
.disp32s
= 1;
8015 i
.types
[op
].bitfield
.disp32
= 1;
8016 i
.types
[op
].bitfield
.disp32s
= 0;
8020 if (!i
.tm
.opcode_modifier
.vecsib
)
8021 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8022 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8024 i
.sib
.base
= i
.base_reg
->reg_num
;
8025 /* x86-64 ignores REX prefix bit here to avoid decoder
8027 if (!(i
.base_reg
->reg_flags
& RegRex
)
8028 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8029 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8031 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8033 fake_zero_displacement
= 1;
8034 i
.types
[op
].bitfield
.disp8
= 1;
8036 i
.sib
.scale
= i
.log2_scale_factor
;
8037 if (i
.index_reg
== 0)
8039 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8040 /* <disp>(%esp) becomes two byte modrm with no index
8041 register. We've already stored the code for esp
8042 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8043 Any base register besides %esp will not use the
8044 extra modrm byte. */
8045 i
.sib
.index
= NO_INDEX_REGISTER
;
8047 else if (!i
.tm
.opcode_modifier
.vecsib
)
8049 if (i
.index_reg
->reg_num
== RegIZ
)
8050 i
.sib
.index
= NO_INDEX_REGISTER
;
8052 i
.sib
.index
= i
.index_reg
->reg_num
;
8053 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8054 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8059 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8060 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8064 if (!fake_zero_displacement
8068 fake_zero_displacement
= 1;
8069 if (i
.disp_encoding
== disp_encoding_8bit
)
8070 i
.types
[op
].bitfield
.disp8
= 1;
8072 i
.types
[op
].bitfield
.disp32
= 1;
8074 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8078 if (fake_zero_displacement
)
8080 /* Fakes a zero displacement assuming that i.types[op]
8081 holds the correct displacement size. */
8084 gas_assert (i
.op
[op
].disps
== 0);
8085 exp
= &disp_expressions
[i
.disp_operands
++];
8086 i
.op
[op
].disps
= exp
;
8087 exp
->X_op
= O_constant
;
8088 exp
->X_add_number
= 0;
8089 exp
->X_add_symbol
= (symbolS
*) 0;
8090 exp
->X_op_symbol
= (symbolS
*) 0;
8098 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8100 if (operand_type_check (i
.types
[0], imm
))
8101 i
.vex
.register_specifier
= NULL
;
8104 /* VEX.vvvv encodes one of the sources when the first
8105 operand is not an immediate. */
8106 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8107 i
.vex
.register_specifier
= i
.op
[0].regs
;
8109 i
.vex
.register_specifier
= i
.op
[1].regs
;
8112 /* Destination is a XMM register encoded in the ModRM.reg
8114 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8115 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8118 /* ModRM.rm and VEX.B encodes the other source. */
8119 if (!i
.mem_operands
)
8123 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8124 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8126 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8128 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8132 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8134 i
.vex
.register_specifier
= i
.op
[2].regs
;
8135 if (!i
.mem_operands
)
8138 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8139 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8143 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8144 (if any) based on i.tm.extension_opcode. Again, we must be
8145 careful to make sure that segment/control/debug/test/MMX
8146 registers are coded into the i.rm.reg field. */
8147 else if (i
.reg_operands
)
8150 unsigned int vex_reg
= ~0;
8152 for (op
= 0; op
< i
.operands
; op
++)
8154 if (i
.types
[op
].bitfield
.class == Reg
8155 || i
.types
[op
].bitfield
.class == RegBND
8156 || i
.types
[op
].bitfield
.class == RegMask
8157 || i
.types
[op
].bitfield
.class == SReg
8158 || i
.types
[op
].bitfield
.class == RegCR
8159 || i
.types
[op
].bitfield
.class == RegDR
8160 || i
.types
[op
].bitfield
.class == RegTR
)
8162 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8164 if (i
.types
[op
].bitfield
.zmmword
)
8165 i
.has_regzmm
= TRUE
;
8166 else if (i
.types
[op
].bitfield
.ymmword
)
8167 i
.has_regymm
= TRUE
;
8169 i
.has_regxmm
= TRUE
;
8172 if (i
.types
[op
].bitfield
.class == RegMMX
)
8174 i
.has_regmmx
= TRUE
;
8181 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8183 /* For instructions with VexNDS, the register-only
8184 source operand is encoded in VEX prefix. */
8185 gas_assert (mem
!= (unsigned int) ~0);
8190 gas_assert (op
< i
.operands
);
8194 /* Check register-only source operand when two source
8195 operands are swapped. */
8196 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8197 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8201 gas_assert (mem
== (vex_reg
+ 1)
8202 && op
< i
.operands
);
8207 gas_assert (vex_reg
< i
.operands
);
8211 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8213 /* For instructions with VexNDD, the register destination
8214 is encoded in VEX prefix. */
8215 if (i
.mem_operands
== 0)
8217 /* There is no memory operand. */
8218 gas_assert ((op
+ 2) == i
.operands
);
8223 /* There are only 2 non-immediate operands. */
8224 gas_assert (op
< i
.imm_operands
+ 2
8225 && i
.operands
== i
.imm_operands
+ 2);
8226 vex_reg
= i
.imm_operands
+ 1;
8230 gas_assert (op
< i
.operands
);
8232 if (vex_reg
!= (unsigned int) ~0)
8234 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8236 if ((type
->bitfield
.class != Reg
8237 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8238 && type
->bitfield
.class != RegSIMD
8239 && !operand_type_equal (type
, ®mask
))
8242 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8245 /* Don't set OP operand twice. */
8248 /* If there is an extension opcode to put here, the
8249 register number must be put into the regmem field. */
8250 if (i
.tm
.extension_opcode
!= None
)
8252 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8253 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8255 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8260 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8261 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8263 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8268 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8269 must set it to 3 to indicate this is a register operand
8270 in the regmem field. */
8271 if (!i
.mem_operands
)
8275 /* Fill in i.rm.reg field with extension opcode (if any). */
8276 if (i
.tm
.extension_opcode
!= None
)
8277 i
.rm
.reg
= i
.tm
.extension_opcode
;
8283 flip_code16 (unsigned int code16
)
8285 gas_assert (i
.tm
.operands
== 1);
8287 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8288 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8289 || i
.tm
.operand_types
[0].bitfield
.disp32s
8290 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8295 output_branch (void)
8301 relax_substateT subtype
;
8305 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8306 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8309 if (i
.prefix
[DATA_PREFIX
] != 0)
8313 code16
^= flip_code16(code16
);
8315 /* Pentium4 branch hints. */
8316 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8317 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8322 if (i
.prefix
[REX_PREFIX
] != 0)
8328 /* BND prefixed jump. */
8329 if (i
.prefix
[BND_PREFIX
] != 0)
8335 if (i
.prefixes
!= 0)
8336 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8338 /* It's always a symbol; End frag & setup for relax.
8339 Make sure there is enough room in this frag for the largest
8340 instruction we may generate in md_convert_frag. This is 2
8341 bytes for the opcode and room for the prefix and largest
8343 frag_grow (prefix
+ 2 + 4);
8344 /* Prefix and 1 opcode byte go in fr_fix. */
8345 p
= frag_more (prefix
+ 1);
8346 if (i
.prefix
[DATA_PREFIX
] != 0)
8347 *p
++ = DATA_PREFIX_OPCODE
;
8348 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8349 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8350 *p
++ = i
.prefix
[SEG_PREFIX
];
8351 if (i
.prefix
[BND_PREFIX
] != 0)
8352 *p
++ = BND_PREFIX_OPCODE
;
8353 if (i
.prefix
[REX_PREFIX
] != 0)
8354 *p
++ = i
.prefix
[REX_PREFIX
];
8355 *p
= i
.tm
.base_opcode
;
8357 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8358 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8359 else if (cpu_arch_flags
.bitfield
.cpui386
)
8360 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8362 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8365 sym
= i
.op
[0].disps
->X_add_symbol
;
8366 off
= i
.op
[0].disps
->X_add_number
;
8368 if (i
.op
[0].disps
->X_op
!= O_constant
8369 && i
.op
[0].disps
->X_op
!= O_symbol
)
8371 /* Handle complex expressions. */
8372 sym
= make_expr_symbol (i
.op
[0].disps
);
8376 /* 1 possible extra opcode + 4 byte displacement go in var part.
8377 Pass reloc in fr_var. */
8378 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8382 /* Return TRUE iff PLT32 relocation should be used for branching to
8386 need_plt32_p (symbolS
*s
)
8388 /* PLT32 relocation is ELF only. */
8393 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8394 krtld support it. */
8398 /* Since there is no need to prepare for PLT branch on x86-64, we
8399 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8400 be used as a marker for 32-bit PC-relative branches. */
8404 /* Weak or undefined symbol need PLT32 relocation. */
8405 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8408 /* Non-global symbol doesn't need PLT32 relocation. */
8409 if (! S_IS_EXTERNAL (s
))
8412 /* Other global symbols need PLT32 relocation. NB: Symbol with
8413 non-default visibilities are treated as normal global symbol
8414 so that PLT32 relocation can be used as a marker for 32-bit
8415 PC-relative branches. It is useful for linker relaxation. */
8426 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8428 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8430 /* This is a loop or jecxz type instruction. */
8432 if (i
.prefix
[ADDR_PREFIX
] != 0)
8434 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8437 /* Pentium4 branch hints. */
8438 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8439 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8441 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8450 if (flag_code
== CODE_16BIT
)
8453 if (i
.prefix
[DATA_PREFIX
] != 0)
8455 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8457 code16
^= flip_code16(code16
);
8465 /* BND prefixed jump. */
8466 if (i
.prefix
[BND_PREFIX
] != 0)
8468 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8472 if (i
.prefix
[REX_PREFIX
] != 0)
8474 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8478 if (i
.prefixes
!= 0)
8479 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8481 p
= frag_more (i
.tm
.opcode_length
+ size
);
8482 switch (i
.tm
.opcode_length
)
8485 *p
++ = i
.tm
.base_opcode
>> 8;
8488 *p
++ = i
.tm
.base_opcode
;
8494 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8496 && jump_reloc
== NO_RELOC
8497 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8498 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8501 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8503 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8504 i
.op
[0].disps
, 1, jump_reloc
);
8506 /* All jumps handled here are signed, but don't use a signed limit
8507 check for 32 and 16 bit jumps as we want to allow wrap around at
8508 4G and 64k respectively. */
8510 fixP
->fx_signed
= 1;
8514 output_interseg_jump (void)
8522 if (flag_code
== CODE_16BIT
)
8526 if (i
.prefix
[DATA_PREFIX
] != 0)
8533 gas_assert (!i
.prefix
[REX_PREFIX
]);
8539 if (i
.prefixes
!= 0)
8540 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8542 /* 1 opcode; 2 segment; offset */
8543 p
= frag_more (prefix
+ 1 + 2 + size
);
8545 if (i
.prefix
[DATA_PREFIX
] != 0)
8546 *p
++ = DATA_PREFIX_OPCODE
;
8548 if (i
.prefix
[REX_PREFIX
] != 0)
8549 *p
++ = i
.prefix
[REX_PREFIX
];
8551 *p
++ = i
.tm
.base_opcode
;
8552 if (i
.op
[1].imms
->X_op
== O_constant
)
8554 offsetT n
= i
.op
[1].imms
->X_add_number
;
8557 && !fits_in_unsigned_word (n
)
8558 && !fits_in_signed_word (n
))
8560 as_bad (_("16-bit jump out of range"));
8563 md_number_to_chars (p
, n
, size
);
8566 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8567 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8568 if (i
.op
[0].imms
->X_op
!= O_constant
)
8569 as_bad (_("can't handle non absolute segment in `%s'"),
8571 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8579 asection
*seg
= now_seg
;
8580 subsegT subseg
= now_subseg
;
8582 unsigned int alignment
, align_size_1
;
8583 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8584 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8585 unsigned int padding
;
8587 if (!IS_ELF
|| !x86_used_note
)
8590 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8592 /* The .note.gnu.property section layout:
8594 Field Length Contents
8597 n_descsz 4 The note descriptor size
8598 n_type 4 NT_GNU_PROPERTY_TYPE_0
8600 n_desc n_descsz The program property array
8604 /* Create the .note.gnu.property section. */
8605 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8606 bfd_set_section_flags (sec
,
8613 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8624 bfd_set_section_alignment (sec
, alignment
);
8625 elf_section_type (sec
) = SHT_NOTE
;
8627 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8629 isa_1_descsz_raw
= 4 + 4 + 4;
8630 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8631 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8633 feature_2_descsz_raw
= isa_1_descsz
;
8634 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8636 feature_2_descsz_raw
+= 4 + 4 + 4;
8637 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8638 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8641 descsz
= feature_2_descsz
;
8642 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8643 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8645 /* Write n_namsz. */
8646 md_number_to_chars (p
, (valueT
) 4, 4);
8648 /* Write n_descsz. */
8649 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8652 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8655 memcpy (p
+ 4 * 3, "GNU", 4);
8657 /* Write 4-byte type. */
8658 md_number_to_chars (p
+ 4 * 4,
8659 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8661 /* Write 4-byte data size. */
8662 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8664 /* Write 4-byte data. */
8665 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8667 /* Zero out paddings. */
8668 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8670 memset (p
+ 4 * 7, 0, padding
);
8672 /* Write 4-byte type. */
8673 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8674 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8676 /* Write 4-byte data size. */
8677 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8679 /* Write 4-byte data. */
8680 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8681 (valueT
) x86_feature_2_used
, 4);
8683 /* Zero out paddings. */
8684 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8686 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8688 /* We probably can't restore the current segment, for there likely
8691 subseg_set (seg
, subseg
);
8696 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8697 const char *frag_now_ptr
)
8699 unsigned int len
= 0;
8701 if (start_frag
!= frag_now
)
8703 const fragS
*fr
= start_frag
;
8708 } while (fr
&& fr
!= frag_now
);
8711 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8714 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8715 be macro-fused with conditional jumps.
8716 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8717 or is one of the following format:
8730 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8732 /* No RIP address. */
8733 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8736 /* No VEX/EVEX encoding. */
8737 if (is_any_vex_encoding (&i
.tm
))
8740 /* add, sub without add/sub m, imm. */
8741 if (i
.tm
.base_opcode
<= 5
8742 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8743 || ((i
.tm
.base_opcode
| 3) == 0x83
8744 && (i
.tm
.extension_opcode
== 0x5
8745 || i
.tm
.extension_opcode
== 0x0)))
8747 *mf_cmp_p
= mf_cmp_alu_cmp
;
8748 return !(i
.mem_operands
&& i
.imm_operands
);
8751 /* and without and m, imm. */
8752 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8753 || ((i
.tm
.base_opcode
| 3) == 0x83
8754 && i
.tm
.extension_opcode
== 0x4))
8756 *mf_cmp_p
= mf_cmp_test_and
;
8757 return !(i
.mem_operands
&& i
.imm_operands
);
8760 /* test without test m imm. */
8761 if ((i
.tm
.base_opcode
| 1) == 0x85
8762 || (i
.tm
.base_opcode
| 1) == 0xa9
8763 || ((i
.tm
.base_opcode
| 1) == 0xf7
8764 && i
.tm
.extension_opcode
== 0))
8766 *mf_cmp_p
= mf_cmp_test_and
;
8767 return !(i
.mem_operands
&& i
.imm_operands
);
8770 /* cmp without cmp m, imm. */
8771 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8772 || ((i
.tm
.base_opcode
| 3) == 0x83
8773 && (i
.tm
.extension_opcode
== 0x7)))
8775 *mf_cmp_p
= mf_cmp_alu_cmp
;
8776 return !(i
.mem_operands
&& i
.imm_operands
);
8779 /* inc, dec without inc/dec m. */
8780 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8781 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8782 || ((i
.tm
.base_opcode
| 1) == 0xff
8783 && i
.tm
.extension_opcode
<= 0x1))
8785 *mf_cmp_p
= mf_cmp_incdec
;
8786 return !i
.mem_operands
;
8792 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8795 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8797 /* NB: Don't work with COND_JUMP86 without i386. */
8798 if (!align_branch_power
8799 || now_seg
== absolute_section
8800 || !cpu_arch_flags
.bitfield
.cpui386
8801 || !(align_branch
& align_branch_fused_bit
))
8804 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8806 if (last_insn
.kind
== last_insn_other
8807 || last_insn
.seg
!= now_seg
)
8810 as_warn_where (last_insn
.file
, last_insn
.line
,
8811 _("`%s` skips -malign-branch-boundary on `%s`"),
8812 last_insn
.name
, i
.tm
.name
);
8818 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8821 add_branch_prefix_frag_p (void)
8823 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8824 to PadLock instructions since they include prefixes in opcode. */
8825 if (!align_branch_power
8826 || !align_branch_prefix_size
8827 || now_seg
== absolute_section
8828 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8829 || !cpu_arch_flags
.bitfield
.cpui386
)
8832 /* Don't add prefix if it is a prefix or there is no operand in case
8833 that segment prefix is special. */
8834 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8837 if (last_insn
.kind
== last_insn_other
8838 || last_insn
.seg
!= now_seg
)
8842 as_warn_where (last_insn
.file
, last_insn
.line
,
8843 _("`%s` skips -malign-branch-boundary on `%s`"),
8844 last_insn
.name
, i
.tm
.name
);
8849 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8852 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8853 enum mf_jcc_kind
*mf_jcc_p
)
8857 /* NB: Don't work with COND_JUMP86 without i386. */
8858 if (!align_branch_power
8859 || now_seg
== absolute_section
8860 || !cpu_arch_flags
.bitfield
.cpui386
)
8865 /* Check for jcc and direct jmp. */
8866 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8868 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8870 *branch_p
= align_branch_jmp
;
8871 add_padding
= align_branch
& align_branch_jmp_bit
;
8875 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8876 igore the lowest bit. */
8877 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8878 *branch_p
= align_branch_jcc
;
8879 if ((align_branch
& align_branch_jcc_bit
))
8883 else if (is_any_vex_encoding (&i
.tm
))
8885 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8888 *branch_p
= align_branch_ret
;
8889 if ((align_branch
& align_branch_ret_bit
))
8894 /* Check for indirect jmp, direct and indirect calls. */
8895 if (i
.tm
.base_opcode
== 0xe8)
8898 *branch_p
= align_branch_call
;
8899 if ((align_branch
& align_branch_call_bit
))
8902 else if (i
.tm
.base_opcode
== 0xff
8903 && (i
.tm
.extension_opcode
== 2
8904 || i
.tm
.extension_opcode
== 4))
8906 /* Indirect call and jmp. */
8907 *branch_p
= align_branch_indirect
;
8908 if ((align_branch
& align_branch_indirect_bit
))
8915 && (i
.op
[0].disps
->X_op
== O_symbol
8916 || (i
.op
[0].disps
->X_op
== O_subtract
8917 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8919 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8920 /* No padding to call to global or undefined tls_get_addr. */
8921 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8922 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8928 && last_insn
.kind
!= last_insn_other
8929 && last_insn
.seg
== now_seg
)
8932 as_warn_where (last_insn
.file
, last_insn
.line
,
8933 _("`%s` skips -malign-branch-boundary on `%s`"),
8934 last_insn
.name
, i
.tm
.name
);
8944 fragS
*insn_start_frag
;
8945 offsetT insn_start_off
;
8946 fragS
*fragP
= NULL
;
8947 enum align_branch_kind branch
= align_branch_none
;
8948 /* The initializer is arbitrary just to avoid uninitialized error.
8949 it's actually either assigned in add_branch_padding_frag_p
8950 or never be used. */
8951 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
8953 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8954 if (IS_ELF
&& x86_used_note
)
8956 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8957 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8958 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8959 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8960 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8961 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8962 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8963 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8964 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8965 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8966 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8967 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8968 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8969 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8970 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8971 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8972 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8973 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8974 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8975 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8976 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8977 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8978 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8979 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8980 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8981 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8982 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8983 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8984 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8985 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8986 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8987 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8988 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8989 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8990 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8991 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8992 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8993 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8994 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8995 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8996 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8997 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8998 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8999 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9000 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9001 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9002 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9003 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9004 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9005 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9007 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9008 || i
.tm
.cpu_flags
.bitfield
.cpu287
9009 || i
.tm
.cpu_flags
.bitfield
.cpu387
9010 || i
.tm
.cpu_flags
.bitfield
.cpu687
9011 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9012 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9014 || i
.tm
.base_opcode
== 0xf77 /* emms */
9015 || i
.tm
.base_opcode
== 0xf0e /* femms */
9016 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9017 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9018 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9020 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9022 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9024 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9025 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9026 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9027 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9028 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9029 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9030 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9031 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9032 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9036 /* Tie dwarf2 debug info to the address at the start of the insn.
9037 We can't do this after the insn has been output as the current
9038 frag may have been closed off. eg. by frag_var. */
9039 dwarf2_emit_insn (0);
9041 insn_start_frag
= frag_now
;
9042 insn_start_off
= frag_now_fix ();
9044 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9047 /* Branch can be 8 bytes. Leave some room for prefixes. */
9048 unsigned int max_branch_padding_size
= 14;
9050 /* Align section to boundary. */
9051 record_alignment (now_seg
, align_branch_power
);
9053 /* Make room for padding. */
9054 frag_grow (max_branch_padding_size
);
9056 /* Start of the padding. */
9061 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9062 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9065 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9066 fragP
->tc_frag_data
.branch_type
= branch
;
9067 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9071 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9073 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9074 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9076 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9077 output_interseg_jump ();
9080 /* Output normal instructions here. */
9084 unsigned int prefix
;
9085 enum mf_cmp_kind mf_cmp
;
9088 && (i
.tm
.base_opcode
== 0xfaee8
9089 || i
.tm
.base_opcode
== 0xfaef0
9090 || i
.tm
.base_opcode
== 0xfaef8))
9092 /* Encode lfence, mfence, and sfence as
9093 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9094 offsetT val
= 0x240483f0ULL
;
9096 md_number_to_chars (p
, val
, 5);
9100 /* Some processors fail on LOCK prefix. This options makes
9101 assembler ignore LOCK prefix and serves as a workaround. */
9102 if (omit_lock_prefix
)
9104 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9106 i
.prefix
[LOCK_PREFIX
] = 0;
9110 /* Skip if this is a branch. */
9112 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9114 /* Make room for padding. */
9115 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9120 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9121 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9124 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9125 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9126 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9128 else if (add_branch_prefix_frag_p ())
9130 unsigned int max_prefix_size
= align_branch_prefix_size
;
9132 /* Make room for padding. */
9133 frag_grow (max_prefix_size
);
9138 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9139 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9142 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9145 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9146 don't need the explicit prefix. */
9147 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9149 switch (i
.tm
.opcode_length
)
9152 if (i
.tm
.base_opcode
& 0xff000000)
9154 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9155 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9156 || prefix
!= REPE_PREFIX_OPCODE
9157 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9158 add_prefix (prefix
);
9162 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9164 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9165 add_prefix (prefix
);
9171 /* Check for pseudo prefixes. */
9172 as_bad_where (insn_start_frag
->fr_file
,
9173 insn_start_frag
->fr_line
,
9174 _("pseudo prefix without instruction"));
9180 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9181 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9182 R_X86_64_GOTTPOFF relocation so that linker can safely
9183 perform IE->LE optimization. A dummy REX_OPCODE prefix
9184 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9185 relocation for GDesc -> IE/LE optimization. */
9186 if (x86_elf_abi
== X86_64_X32_ABI
9188 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9189 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9190 && i
.prefix
[REX_PREFIX
] == 0)
9191 add_prefix (REX_OPCODE
);
9194 /* The prefix bytes. */
9195 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9197 FRAG_APPEND_1_CHAR (*q
);
9201 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9206 /* REX byte is encoded in VEX prefix. */
9210 FRAG_APPEND_1_CHAR (*q
);
9213 /* There should be no other prefixes for instructions
9218 /* For EVEX instructions i.vrex should become 0 after
9219 build_evex_prefix. For VEX instructions upper 16 registers
9220 aren't available, so VREX should be 0. */
9223 /* Now the VEX prefix. */
9224 p
= frag_more (i
.vex
.length
);
9225 for (j
= 0; j
< i
.vex
.length
; j
++)
9226 p
[j
] = i
.vex
.bytes
[j
];
9229 /* Now the opcode; be careful about word order here! */
9230 if (i
.tm
.opcode_length
== 1)
9232 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9236 switch (i
.tm
.opcode_length
)
9240 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9241 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9245 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9255 /* Put out high byte first: can't use md_number_to_chars! */
9256 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9257 *p
= i
.tm
.base_opcode
& 0xff;
9260 /* Now the modrm byte and sib byte (if present). */
9261 if (i
.tm
.opcode_modifier
.modrm
)
9263 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9266 /* If i.rm.regmem == ESP (4)
9267 && i.rm.mode != (Register mode)
9269 ==> need second modrm byte. */
9270 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9272 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9273 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9275 | i
.sib
.scale
<< 6));
9278 if (i
.disp_operands
)
9279 output_disp (insn_start_frag
, insn_start_off
);
9282 output_imm (insn_start_frag
, insn_start_off
);
9285 * frag_now_fix () returning plain abs_section_offset when we're in the
9286 * absolute section, and abs_section_offset not getting updated as data
9287 * gets added to the frag breaks the logic below.
9289 if (now_seg
!= absolute_section
)
9291 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9293 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9297 /* NB: Don't add prefix with GOTPC relocation since
9298 output_disp() above depends on the fixed encoding
9299 length. Can't add prefix with TLS relocation since
9300 it breaks TLS linker optimization. */
9301 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9302 /* Prefix count on the current instruction. */
9303 unsigned int count
= i
.vex
.length
;
9305 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9306 /* REX byte is encoded in VEX/EVEX prefix. */
9307 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9310 /* Count prefixes for extended opcode maps. */
9312 switch (i
.tm
.opcode_length
)
9315 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9318 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9330 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9339 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9342 /* Set the maximum prefix size in BRANCH_PREFIX
9344 if (fragP
->tc_frag_data
.max_bytes
> max
)
9345 fragP
->tc_frag_data
.max_bytes
= max
;
9346 if (fragP
->tc_frag_data
.max_bytes
> count
)
9347 fragP
->tc_frag_data
.max_bytes
-= count
;
9349 fragP
->tc_frag_data
.max_bytes
= 0;
9353 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9355 unsigned int max_prefix_size
;
9356 if (align_branch_prefix_size
> max
)
9357 max_prefix_size
= max
;
9359 max_prefix_size
= align_branch_prefix_size
;
9360 if (max_prefix_size
> count
)
9361 fragP
->tc_frag_data
.max_prefix_length
9362 = max_prefix_size
- count
;
9365 /* Use existing segment prefix if possible. Use CS
9366 segment prefix in 64-bit mode. In 32-bit mode, use SS
9367 segment prefix with ESP/EBP base register and use DS
9368 segment prefix without ESP/EBP base register. */
9369 if (i
.prefix
[SEG_PREFIX
])
9370 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9371 else if (flag_code
== CODE_64BIT
)
9372 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9374 && (i
.base_reg
->reg_num
== 4
9375 || i
.base_reg
->reg_num
== 5))
9376 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9378 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9383 /* NB: Don't work with COND_JUMP86 without i386. */
9384 if (align_branch_power
9385 && now_seg
!= absolute_section
9386 && cpu_arch_flags
.bitfield
.cpui386
)
9388 /* Terminate each frag so that we can add prefix and check for
9390 frag_wane (frag_now
);
9397 pi ("" /*line*/, &i
);
9399 #endif /* DEBUG386 */
9402 /* Return the size of the displacement operand N. */
9405 disp_size (unsigned int n
)
9409 if (i
.types
[n
].bitfield
.disp64
)
9411 else if (i
.types
[n
].bitfield
.disp8
)
9413 else if (i
.types
[n
].bitfield
.disp16
)
9418 /* Return the size of the immediate operand N. */
9421 imm_size (unsigned int n
)
9424 if (i
.types
[n
].bitfield
.imm64
)
9426 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9428 else if (i
.types
[n
].bitfield
.imm16
)
9434 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9439 for (n
= 0; n
< i
.operands
; n
++)
9441 if (operand_type_check (i
.types
[n
], disp
))
9443 if (i
.op
[n
].disps
->X_op
== O_constant
)
9445 int size
= disp_size (n
);
9446 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9448 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9450 p
= frag_more (size
);
9451 md_number_to_chars (p
, val
, size
);
9455 enum bfd_reloc_code_real reloc_type
;
9456 int size
= disp_size (n
);
9457 int sign
= i
.types
[n
].bitfield
.disp32s
;
9458 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9461 /* We can't have 8 bit displacement here. */
9462 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9464 /* The PC relative address is computed relative
9465 to the instruction boundary, so in case immediate
9466 fields follows, we need to adjust the value. */
9467 if (pcrel
&& i
.imm_operands
)
9472 for (n1
= 0; n1
< i
.operands
; n1
++)
9473 if (operand_type_check (i
.types
[n1
], imm
))
9475 /* Only one immediate is allowed for PC
9476 relative address. */
9477 gas_assert (sz
== 0);
9479 i
.op
[n
].disps
->X_add_number
-= sz
;
9481 /* We should find the immediate. */
9482 gas_assert (sz
!= 0);
9485 p
= frag_more (size
);
9486 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9488 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9489 && (((reloc_type
== BFD_RELOC_32
9490 || reloc_type
== BFD_RELOC_X86_64_32S
9491 || (reloc_type
== BFD_RELOC_64
9493 && (i
.op
[n
].disps
->X_op
== O_symbol
9494 || (i
.op
[n
].disps
->X_op
== O_add
9495 && ((symbol_get_value_expression
9496 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9498 || reloc_type
== BFD_RELOC_32_PCREL
))
9502 reloc_type
= BFD_RELOC_386_GOTPC
;
9503 i
.has_gotpc_tls_reloc
= TRUE
;
9504 i
.op
[n
].imms
->X_add_number
+=
9505 encoding_length (insn_start_frag
, insn_start_off
, p
);
9507 else if (reloc_type
== BFD_RELOC_64
)
9508 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9510 /* Don't do the adjustment for x86-64, as there
9511 the pcrel addressing is relative to the _next_
9512 insn, and that is taken care of in other code. */
9513 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9515 else if (align_branch_power
)
9519 case BFD_RELOC_386_TLS_GD
:
9520 case BFD_RELOC_386_TLS_LDM
:
9521 case BFD_RELOC_386_TLS_IE
:
9522 case BFD_RELOC_386_TLS_IE_32
:
9523 case BFD_RELOC_386_TLS_GOTIE
:
9524 case BFD_RELOC_386_TLS_GOTDESC
:
9525 case BFD_RELOC_386_TLS_DESC_CALL
:
9526 case BFD_RELOC_X86_64_TLSGD
:
9527 case BFD_RELOC_X86_64_TLSLD
:
9528 case BFD_RELOC_X86_64_GOTTPOFF
:
9529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9530 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9531 i
.has_gotpc_tls_reloc
= TRUE
;
9536 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9537 size
, i
.op
[n
].disps
, pcrel
,
9539 /* Check for "call/jmp *mem", "mov mem, %reg",
9540 "test %reg, mem" and "binop mem, %reg" where binop
9541 is one of adc, add, and, cmp, or, sbb, sub, xor
9542 instructions without data prefix. Always generate
9543 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9544 if (i
.prefix
[DATA_PREFIX
] == 0
9545 && (generate_relax_relocations
9548 && i
.rm
.regmem
== 5))
9550 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9551 && !is_any_vex_encoding(&i
.tm
)
9552 && ((i
.operands
== 1
9553 && i
.tm
.base_opcode
== 0xff
9554 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9556 && (i
.tm
.base_opcode
== 0x8b
9557 || i
.tm
.base_opcode
== 0x85
9558 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9562 fixP
->fx_tcbit
= i
.rex
!= 0;
9564 && (i
.base_reg
->reg_num
== RegIP
))
9565 fixP
->fx_tcbit2
= 1;
9568 fixP
->fx_tcbit2
= 1;
9576 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9581 for (n
= 0; n
< i
.operands
; n
++)
9583 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9584 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9587 if (operand_type_check (i
.types
[n
], imm
))
9589 if (i
.op
[n
].imms
->X_op
== O_constant
)
9591 int size
= imm_size (n
);
9594 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9596 p
= frag_more (size
);
9597 md_number_to_chars (p
, val
, size
);
9601 /* Not absolute_section.
9602 Need a 32-bit fixup (don't support 8bit
9603 non-absolute imms). Try to support other
9605 enum bfd_reloc_code_real reloc_type
;
9606 int size
= imm_size (n
);
9609 if (i
.types
[n
].bitfield
.imm32s
9610 && (i
.suffix
== QWORD_MNEM_SUFFIX
9611 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9616 p
= frag_more (size
);
9617 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9619 /* This is tough to explain. We end up with this one if we
9620 * have operands that look like
9621 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9622 * obtain the absolute address of the GOT, and it is strongly
9623 * preferable from a performance point of view to avoid using
9624 * a runtime relocation for this. The actual sequence of
9625 * instructions often look something like:
9630 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9632 * The call and pop essentially return the absolute address
9633 * of the label .L66 and store it in %ebx. The linker itself
9634 * will ultimately change the first operand of the addl so
9635 * that %ebx points to the GOT, but to keep things simple, the
9636 * .o file must have this operand set so that it generates not
9637 * the absolute address of .L66, but the absolute address of
9638 * itself. This allows the linker itself simply treat a GOTPC
9639 * relocation as asking for a pcrel offset to the GOT to be
9640 * added in, and the addend of the relocation is stored in the
9641 * operand field for the instruction itself.
9643 * Our job here is to fix the operand so that it would add
9644 * the correct offset so that %ebx would point to itself. The
9645 * thing that is tricky is that .-.L66 will point to the
9646 * beginning of the instruction, so we need to further modify
9647 * the operand so that it will point to itself. There are
9648 * other cases where you have something like:
9650 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9652 * and here no correction would be required. Internally in
9653 * the assembler we treat operands of this form as not being
9654 * pcrel since the '.' is explicitly mentioned, and I wonder
9655 * whether it would simplify matters to do it this way. Who
9656 * knows. In earlier versions of the PIC patches, the
9657 * pcrel_adjust field was used to store the correction, but
9658 * since the expression is not pcrel, I felt it would be
9659 * confusing to do it this way. */
9661 if ((reloc_type
== BFD_RELOC_32
9662 || reloc_type
== BFD_RELOC_X86_64_32S
9663 || reloc_type
== BFD_RELOC_64
)
9665 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9666 && (i
.op
[n
].imms
->X_op
== O_symbol
9667 || (i
.op
[n
].imms
->X_op
== O_add
9668 && ((symbol_get_value_expression
9669 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9673 reloc_type
= BFD_RELOC_386_GOTPC
;
9675 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9677 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9678 i
.has_gotpc_tls_reloc
= TRUE
;
9679 i
.op
[n
].imms
->X_add_number
+=
9680 encoding_length (insn_start_frag
, insn_start_off
, p
);
9682 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9683 i
.op
[n
].imms
, 0, reloc_type
);
9689 /* x86_cons_fix_new is called via the expression parsing code when a
9690 reloc is needed. We use this hook to get the correct .got reloc. */
9691 static int cons_sign
= -1;
9694 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9695 expressionS
*exp
, bfd_reloc_code_real_type r
)
9697 r
= reloc (len
, 0, cons_sign
, r
);
9700 if (exp
->X_op
== O_secrel
)
9702 exp
->X_op
= O_symbol
;
9703 r
= BFD_RELOC_32_SECREL
;
9707 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9710 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9711 purpose of the `.dc.a' internal pseudo-op. */
9714 x86_address_bytes (void)
9716 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9718 return stdoutput
->arch_info
->bits_per_address
/ 8;
9721 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9723 # define lex_got(reloc, adjust, types) NULL
9725 /* Parse operands of the form
9726 <symbol>@GOTOFF+<nnn>
9727 and similar .plt or .got references.
9729 If we find one, set up the correct relocation in RELOC and copy the
9730 input string, minus the `@GOTOFF' into a malloc'd buffer for
9731 parsing by the calling routine. Return this buffer, and if ADJUST
9732 is non-null set it to the length of the string we removed from the
9733 input line. Otherwise return NULL. */
9735 lex_got (enum bfd_reloc_code_real
*rel
,
9737 i386_operand_type
*types
)
9739 /* Some of the relocations depend on the size of what field is to
9740 be relocated. But in our callers i386_immediate and i386_displacement
9741 we don't yet know the operand size (this will be set by insn
9742 matching). Hence we record the word32 relocation here,
9743 and adjust the reloc according to the real size in reloc(). */
9744 static const struct {
9747 const enum bfd_reloc_code_real rel
[2];
9748 const i386_operand_type types64
;
9750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9751 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9753 OPERAND_TYPE_IMM32_64
},
9755 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9756 BFD_RELOC_X86_64_PLTOFF64
},
9757 OPERAND_TYPE_IMM64
},
9758 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9759 BFD_RELOC_X86_64_PLT32
},
9760 OPERAND_TYPE_IMM32_32S_DISP32
},
9761 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9762 BFD_RELOC_X86_64_GOTPLT64
},
9763 OPERAND_TYPE_IMM64_DISP64
},
9764 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9765 BFD_RELOC_X86_64_GOTOFF64
},
9766 OPERAND_TYPE_IMM64_DISP64
},
9767 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9768 BFD_RELOC_X86_64_GOTPCREL
},
9769 OPERAND_TYPE_IMM32_32S_DISP32
},
9770 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9771 BFD_RELOC_X86_64_TLSGD
},
9772 OPERAND_TYPE_IMM32_32S_DISP32
},
9773 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9774 _dummy_first_bfd_reloc_code_real
},
9775 OPERAND_TYPE_NONE
},
9776 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9777 BFD_RELOC_X86_64_TLSLD
},
9778 OPERAND_TYPE_IMM32_32S_DISP32
},
9779 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9780 BFD_RELOC_X86_64_GOTTPOFF
},
9781 OPERAND_TYPE_IMM32_32S_DISP32
},
9782 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9783 BFD_RELOC_X86_64_TPOFF32
},
9784 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9785 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9786 _dummy_first_bfd_reloc_code_real
},
9787 OPERAND_TYPE_NONE
},
9788 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9789 BFD_RELOC_X86_64_DTPOFF32
},
9790 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9791 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9792 _dummy_first_bfd_reloc_code_real
},
9793 OPERAND_TYPE_NONE
},
9794 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9795 _dummy_first_bfd_reloc_code_real
},
9796 OPERAND_TYPE_NONE
},
9797 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9798 BFD_RELOC_X86_64_GOT32
},
9799 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9800 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9801 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9802 OPERAND_TYPE_IMM32_32S_DISP32
},
9803 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9804 BFD_RELOC_X86_64_TLSDESC_CALL
},
9805 OPERAND_TYPE_IMM32_32S_DISP32
},
9810 #if defined (OBJ_MAYBE_ELF)
9815 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9816 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9819 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9821 int len
= gotrel
[j
].len
;
9822 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9824 if (gotrel
[j
].rel
[object_64bit
] != 0)
9827 char *tmpbuf
, *past_reloc
;
9829 *rel
= gotrel
[j
].rel
[object_64bit
];
9833 if (flag_code
!= CODE_64BIT
)
9835 types
->bitfield
.imm32
= 1;
9836 types
->bitfield
.disp32
= 1;
9839 *types
= gotrel
[j
].types64
;
9842 if (j
!= 0 && GOT_symbol
== NULL
)
9843 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9845 /* The length of the first part of our input line. */
9846 first
= cp
- input_line_pointer
;
9848 /* The second part goes from after the reloc token until
9849 (and including) an end_of_line char or comma. */
9850 past_reloc
= cp
+ 1 + len
;
9852 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9854 second
= cp
+ 1 - past_reloc
;
9856 /* Allocate and copy string. The trailing NUL shouldn't
9857 be necessary, but be safe. */
9858 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9859 memcpy (tmpbuf
, input_line_pointer
, first
);
9860 if (second
!= 0 && *past_reloc
!= ' ')
9861 /* Replace the relocation token with ' ', so that
9862 errors like foo@GOTOFF1 will be detected. */
9863 tmpbuf
[first
++] = ' ';
9865 /* Increment length by 1 if the relocation token is
9870 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9871 tmpbuf
[first
+ second
] = '\0';
9875 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9876 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9881 /* Might be a symbol version string. Don't as_bad here. */
9890 /* Parse operands of the form
9891 <symbol>@SECREL32+<nnn>
9893 If we find one, set up the correct relocation in RELOC and copy the
9894 input string, minus the `@SECREL32' into a malloc'd buffer for
9895 parsing by the calling routine. Return this buffer, and if ADJUST
9896 is non-null set it to the length of the string we removed from the
9897 input line. Otherwise return NULL.
9899 This function is copied from the ELF version above adjusted for PE targets. */
9902 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9903 int *adjust ATTRIBUTE_UNUSED
,
9904 i386_operand_type
*types
)
9910 const enum bfd_reloc_code_real rel
[2];
9911 const i386_operand_type types64
;
9915 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9916 BFD_RELOC_32_SECREL
},
9917 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9923 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9924 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9927 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9929 int len
= gotrel
[j
].len
;
9931 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9933 if (gotrel
[j
].rel
[object_64bit
] != 0)
9936 char *tmpbuf
, *past_reloc
;
9938 *rel
= gotrel
[j
].rel
[object_64bit
];
9944 if (flag_code
!= CODE_64BIT
)
9946 types
->bitfield
.imm32
= 1;
9947 types
->bitfield
.disp32
= 1;
9950 *types
= gotrel
[j
].types64
;
9953 /* The length of the first part of our input line. */
9954 first
= cp
- input_line_pointer
;
9956 /* The second part goes from after the reloc token until
9957 (and including) an end_of_line char or comma. */
9958 past_reloc
= cp
+ 1 + len
;
9960 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9962 second
= cp
+ 1 - past_reloc
;
9964 /* Allocate and copy string. The trailing NUL shouldn't
9965 be necessary, but be safe. */
9966 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9967 memcpy (tmpbuf
, input_line_pointer
, first
);
9968 if (second
!= 0 && *past_reloc
!= ' ')
9969 /* Replace the relocation token with ' ', so that
9970 errors like foo@SECLREL321 will be detected. */
9971 tmpbuf
[first
++] = ' ';
9972 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9973 tmpbuf
[first
+ second
] = '\0';
9977 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9978 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9983 /* Might be a symbol version string. Don't as_bad here. */
9989 bfd_reloc_code_real_type
9990 x86_cons (expressionS
*exp
, int size
)
9992 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9994 intel_syntax
= -intel_syntax
;
9997 if (size
== 4 || (object_64bit
&& size
== 8))
9999 /* Handle @GOTOFF and the like in an expression. */
10001 char *gotfree_input_line
;
10004 save
= input_line_pointer
;
10005 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10006 if (gotfree_input_line
)
10007 input_line_pointer
= gotfree_input_line
;
10011 if (gotfree_input_line
)
10013 /* expression () has merrily parsed up to the end of line,
10014 or a comma - in the wrong buffer. Transfer how far
10015 input_line_pointer has moved to the right buffer. */
10016 input_line_pointer
= (save
10017 + (input_line_pointer
- gotfree_input_line
)
10019 free (gotfree_input_line
);
10020 if (exp
->X_op
== O_constant
10021 || exp
->X_op
== O_absent
10022 || exp
->X_op
== O_illegal
10023 || exp
->X_op
== O_register
10024 || exp
->X_op
== O_big
)
10026 char c
= *input_line_pointer
;
10027 *input_line_pointer
= 0;
10028 as_bad (_("missing or invalid expression `%s'"), save
);
10029 *input_line_pointer
= c
;
10031 else if ((got_reloc
== BFD_RELOC_386_PLT32
10032 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10033 && exp
->X_op
!= O_symbol
)
10035 char c
= *input_line_pointer
;
10036 *input_line_pointer
= 0;
10037 as_bad (_("invalid PLT expression `%s'"), save
);
10038 *input_line_pointer
= c
;
10045 intel_syntax
= -intel_syntax
;
10048 i386_intel_simplify (exp
);
10054 signed_cons (int size
)
10056 if (flag_code
== CODE_64BIT
)
10064 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10071 if (exp
.X_op
== O_symbol
)
10072 exp
.X_op
= O_secrel
;
10074 emit_expr (&exp
, 4);
10076 while (*input_line_pointer
++ == ',');
10078 input_line_pointer
--;
10079 demand_empty_rest_of_line ();
10083 /* Handle Vector operations. */
10086 check_VecOperations (char *op_string
, char *op_end
)
10088 const reg_entry
*mask
;
10093 && (op_end
== NULL
|| op_string
< op_end
))
10096 if (*op_string
== '{')
10100 /* Check broadcasts. */
10101 if (strncmp (op_string
, "1to", 3) == 0)
10106 goto duplicated_vec_op
;
10109 if (*op_string
== '8')
10111 else if (*op_string
== '4')
10113 else if (*op_string
== '2')
10115 else if (*op_string
== '1'
10116 && *(op_string
+1) == '6')
10123 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10128 broadcast_op
.type
= bcst_type
;
10129 broadcast_op
.operand
= this_operand
;
10130 broadcast_op
.bytes
= 0;
10131 i
.broadcast
= &broadcast_op
;
10133 /* Check masking operation. */
10134 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10136 /* k0 can't be used for write mask. */
10137 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10139 as_bad (_("`%s%s' can't be used for write mask"),
10140 register_prefix
, mask
->reg_name
);
10146 mask_op
.mask
= mask
;
10147 mask_op
.zeroing
= 0;
10148 mask_op
.operand
= this_operand
;
10154 goto duplicated_vec_op
;
10156 i
.mask
->mask
= mask
;
10158 /* Only "{z}" is allowed here. No need to check
10159 zeroing mask explicitly. */
10160 if (i
.mask
->operand
!= this_operand
)
10162 as_bad (_("invalid write mask `%s'"), saved
);
10167 op_string
= end_op
;
10169 /* Check zeroing-flag for masking operation. */
10170 else if (*op_string
== 'z')
10174 mask_op
.mask
= NULL
;
10175 mask_op
.zeroing
= 1;
10176 mask_op
.operand
= this_operand
;
10181 if (i
.mask
->zeroing
)
10184 as_bad (_("duplicated `%s'"), saved
);
10188 i
.mask
->zeroing
= 1;
10190 /* Only "{%k}" is allowed here. No need to check mask
10191 register explicitly. */
10192 if (i
.mask
->operand
!= this_operand
)
10194 as_bad (_("invalid zeroing-masking `%s'"),
10203 goto unknown_vec_op
;
10205 if (*op_string
!= '}')
10207 as_bad (_("missing `}' in `%s'"), saved
);
10212 /* Strip whitespace since the addition of pseudo prefixes
10213 changed how the scrubber treats '{'. */
10214 if (is_space_char (*op_string
))
10220 /* We don't know this one. */
10221 as_bad (_("unknown vector operation: `%s'"), saved
);
10225 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10227 as_bad (_("zeroing-masking only allowed with write mask"));
10235 i386_immediate (char *imm_start
)
10237 char *save_input_line_pointer
;
10238 char *gotfree_input_line
;
10241 i386_operand_type types
;
10243 operand_type_set (&types
, ~0);
10245 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10247 as_bad (_("at most %d immediate operands are allowed"),
10248 MAX_IMMEDIATE_OPERANDS
);
10252 exp
= &im_expressions
[i
.imm_operands
++];
10253 i
.op
[this_operand
].imms
= exp
;
10255 if (is_space_char (*imm_start
))
10258 save_input_line_pointer
= input_line_pointer
;
10259 input_line_pointer
= imm_start
;
10261 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10262 if (gotfree_input_line
)
10263 input_line_pointer
= gotfree_input_line
;
10265 exp_seg
= expression (exp
);
10267 SKIP_WHITESPACE ();
10269 /* Handle vector operations. */
10270 if (*input_line_pointer
== '{')
10272 input_line_pointer
= check_VecOperations (input_line_pointer
,
10274 if (input_line_pointer
== NULL
)
10278 if (*input_line_pointer
)
10279 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10281 input_line_pointer
= save_input_line_pointer
;
10282 if (gotfree_input_line
)
10284 free (gotfree_input_line
);
10286 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10287 exp
->X_op
= O_illegal
;
10290 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10294 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10295 i386_operand_type types
, const char *imm_start
)
10297 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10300 as_bad (_("missing or invalid immediate expression `%s'"),
10304 else if (exp
->X_op
== O_constant
)
10306 /* Size it properly later. */
10307 i
.types
[this_operand
].bitfield
.imm64
= 1;
10308 /* If not 64bit, sign extend val. */
10309 if (flag_code
!= CODE_64BIT
10310 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10312 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10314 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10315 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10316 && exp_seg
!= absolute_section
10317 && exp_seg
!= text_section
10318 && exp_seg
!= data_section
10319 && exp_seg
!= bss_section
10320 && exp_seg
!= undefined_section
10321 && !bfd_is_com_section (exp_seg
))
10323 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10327 else if (!intel_syntax
&& exp_seg
== reg_section
)
10330 as_bad (_("illegal immediate register operand %s"), imm_start
);
10335 /* This is an address. The size of the address will be
10336 determined later, depending on destination register,
10337 suffix, or the default for the section. */
10338 i
.types
[this_operand
].bitfield
.imm8
= 1;
10339 i
.types
[this_operand
].bitfield
.imm16
= 1;
10340 i
.types
[this_operand
].bitfield
.imm32
= 1;
10341 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10342 i
.types
[this_operand
].bitfield
.imm64
= 1;
10343 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10351 i386_scale (char *scale
)
10354 char *save
= input_line_pointer
;
10356 input_line_pointer
= scale
;
10357 val
= get_absolute_expression ();
10362 i
.log2_scale_factor
= 0;
10365 i
.log2_scale_factor
= 1;
10368 i
.log2_scale_factor
= 2;
10371 i
.log2_scale_factor
= 3;
10375 char sep
= *input_line_pointer
;
10377 *input_line_pointer
= '\0';
10378 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10380 *input_line_pointer
= sep
;
10381 input_line_pointer
= save
;
10385 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10387 as_warn (_("scale factor of %d without an index register"),
10388 1 << i
.log2_scale_factor
);
10389 i
.log2_scale_factor
= 0;
10391 scale
= input_line_pointer
;
10392 input_line_pointer
= save
;
10397 i386_displacement (char *disp_start
, char *disp_end
)
10401 char *save_input_line_pointer
;
10402 char *gotfree_input_line
;
10404 i386_operand_type bigdisp
, types
= anydisp
;
10407 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10409 as_bad (_("at most %d displacement operands are allowed"),
10410 MAX_MEMORY_OPERANDS
);
10414 operand_type_set (&bigdisp
, 0);
10416 || i
.types
[this_operand
].bitfield
.baseindex
10417 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10418 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10420 i386_addressing_mode ();
10421 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10422 if (flag_code
== CODE_64BIT
)
10426 bigdisp
.bitfield
.disp32s
= 1;
10427 bigdisp
.bitfield
.disp64
= 1;
10430 bigdisp
.bitfield
.disp32
= 1;
10432 else if ((flag_code
== CODE_16BIT
) ^ override
)
10433 bigdisp
.bitfield
.disp16
= 1;
10435 bigdisp
.bitfield
.disp32
= 1;
10439 /* For PC-relative branches, the width of the displacement may be
10440 dependent upon data size, but is never dependent upon address size.
10441 Also make sure to not unintentionally match against a non-PC-relative
10442 branch template. */
10443 static templates aux_templates
;
10444 const insn_template
*t
= current_templates
->start
;
10445 bfd_boolean has_intel64
= FALSE
;
10447 aux_templates
.start
= t
;
10448 while (++t
< current_templates
->end
)
10450 if (t
->opcode_modifier
.jump
10451 != current_templates
->start
->opcode_modifier
.jump
)
10453 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10454 has_intel64
= TRUE
;
10456 if (t
< current_templates
->end
)
10458 aux_templates
.end
= t
;
10459 current_templates
= &aux_templates
;
10462 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10463 if (flag_code
== CODE_64BIT
)
10465 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10466 && (!intel64
|| !has_intel64
))
10467 bigdisp
.bitfield
.disp16
= 1;
10469 bigdisp
.bitfield
.disp32s
= 1;
10474 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10476 : LONG_MNEM_SUFFIX
));
10477 bigdisp
.bitfield
.disp32
= 1;
10478 if ((flag_code
== CODE_16BIT
) ^ override
)
10480 bigdisp
.bitfield
.disp32
= 0;
10481 bigdisp
.bitfield
.disp16
= 1;
10485 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10488 exp
= &disp_expressions
[i
.disp_operands
];
10489 i
.op
[this_operand
].disps
= exp
;
10491 save_input_line_pointer
= input_line_pointer
;
10492 input_line_pointer
= disp_start
;
10493 END_STRING_AND_SAVE (disp_end
);
10495 #ifndef GCC_ASM_O_HACK
10496 #define GCC_ASM_O_HACK 0
10499 END_STRING_AND_SAVE (disp_end
+ 1);
10500 if (i
.types
[this_operand
].bitfield
.baseIndex
10501 && displacement_string_end
[-1] == '+')
10503 /* This hack is to avoid a warning when using the "o"
10504 constraint within gcc asm statements.
10507 #define _set_tssldt_desc(n,addr,limit,type) \
10508 __asm__ __volatile__ ( \
10509 "movw %w2,%0\n\t" \
10510 "movw %w1,2+%0\n\t" \
10511 "rorl $16,%1\n\t" \
10512 "movb %b1,4+%0\n\t" \
10513 "movb %4,5+%0\n\t" \
10514 "movb $0,6+%0\n\t" \
10515 "movb %h1,7+%0\n\t" \
10517 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10519 This works great except that the output assembler ends
10520 up looking a bit weird if it turns out that there is
10521 no offset. You end up producing code that looks like:
10534 So here we provide the missing zero. */
10536 *displacement_string_end
= '0';
10539 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10540 if (gotfree_input_line
)
10541 input_line_pointer
= gotfree_input_line
;
10543 exp_seg
= expression (exp
);
10545 SKIP_WHITESPACE ();
10546 if (*input_line_pointer
)
10547 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10549 RESTORE_END_STRING (disp_end
+ 1);
10551 input_line_pointer
= save_input_line_pointer
;
10552 if (gotfree_input_line
)
10554 free (gotfree_input_line
);
10556 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10557 exp
->X_op
= O_illegal
;
10560 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10562 RESTORE_END_STRING (disp_end
);
10568 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10569 i386_operand_type types
, const char *disp_start
)
10571 i386_operand_type bigdisp
;
10574 /* We do this to make sure that the section symbol is in
10575 the symbol table. We will ultimately change the relocation
10576 to be relative to the beginning of the section. */
10577 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10578 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10579 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10581 if (exp
->X_op
!= O_symbol
)
10584 if (S_IS_LOCAL (exp
->X_add_symbol
)
10585 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10586 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10587 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10588 exp
->X_op
= O_subtract
;
10589 exp
->X_op_symbol
= GOT_symbol
;
10590 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10591 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10592 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10593 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10595 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10598 else if (exp
->X_op
== O_absent
10599 || exp
->X_op
== O_illegal
10600 || exp
->X_op
== O_big
)
10603 as_bad (_("missing or invalid displacement expression `%s'"),
10608 else if (flag_code
== CODE_64BIT
10609 && !i
.prefix
[ADDR_PREFIX
]
10610 && exp
->X_op
== O_constant
)
10612 /* Since displacement is signed extended to 64bit, don't allow
10613 disp32 and turn off disp32s if they are out of range. */
10614 i
.types
[this_operand
].bitfield
.disp32
= 0;
10615 if (!fits_in_signed_long (exp
->X_add_number
))
10617 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10618 if (i
.types
[this_operand
].bitfield
.baseindex
)
10620 as_bad (_("0x%lx out range of signed 32bit displacement"),
10621 (long) exp
->X_add_number
);
10627 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10628 else if (exp
->X_op
!= O_constant
10629 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10630 && exp_seg
!= absolute_section
10631 && exp_seg
!= text_section
10632 && exp_seg
!= data_section
10633 && exp_seg
!= bss_section
10634 && exp_seg
!= undefined_section
10635 && !bfd_is_com_section (exp_seg
))
10637 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10642 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10643 /* Constants get taken care of by optimize_disp(). */
10644 && exp
->X_op
!= O_constant
)
10645 i
.types
[this_operand
].bitfield
.disp8
= 1;
10647 /* Check if this is a displacement only operand. */
10648 bigdisp
= i
.types
[this_operand
];
10649 bigdisp
.bitfield
.disp8
= 0;
10650 bigdisp
.bitfield
.disp16
= 0;
10651 bigdisp
.bitfield
.disp32
= 0;
10652 bigdisp
.bitfield
.disp32s
= 0;
10653 bigdisp
.bitfield
.disp64
= 0;
10654 if (operand_type_all_zero (&bigdisp
))
10655 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10661 /* Return the active addressing mode, taking address override and
10662 registers forming the address into consideration. Update the
10663 address override prefix if necessary. */
10665 static enum flag_code
10666 i386_addressing_mode (void)
10668 enum flag_code addr_mode
;
10670 if (i
.prefix
[ADDR_PREFIX
])
10671 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10672 else if (flag_code
== CODE_16BIT
10673 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10674 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10675 from md_assemble() by "is not a valid base/index expression"
10676 when there is a base and/or index. */
10677 && !i
.types
[this_operand
].bitfield
.baseindex
)
10679 /* MPX insn memory operands with neither base nor index must be forced
10680 to use 32-bit addressing in 16-bit mode. */
10681 addr_mode
= CODE_32BIT
;
10682 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10684 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10685 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10689 addr_mode
= flag_code
;
10691 #if INFER_ADDR_PREFIX
10692 if (i
.mem_operands
== 0)
10694 /* Infer address prefix from the first memory operand. */
10695 const reg_entry
*addr_reg
= i
.base_reg
;
10697 if (addr_reg
== NULL
)
10698 addr_reg
= i
.index_reg
;
10702 if (addr_reg
->reg_type
.bitfield
.dword
)
10703 addr_mode
= CODE_32BIT
;
10704 else if (flag_code
!= CODE_64BIT
10705 && addr_reg
->reg_type
.bitfield
.word
)
10706 addr_mode
= CODE_16BIT
;
10708 if (addr_mode
!= flag_code
)
10710 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10712 /* Change the size of any displacement too. At most one
10713 of Disp16 or Disp32 is set.
10714 FIXME. There doesn't seem to be any real need for
10715 separate Disp16 and Disp32 flags. The same goes for
10716 Imm16 and Imm32. Removing them would probably clean
10717 up the code quite a lot. */
10718 if (flag_code
!= CODE_64BIT
10719 && (i
.types
[this_operand
].bitfield
.disp16
10720 || i
.types
[this_operand
].bitfield
.disp32
))
10721 i
.types
[this_operand
]
10722 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10732 /* Make sure the memory operand we've been dealt is valid.
10733 Return 1 on success, 0 on a failure. */
10736 i386_index_check (const char *operand_string
)
10738 const char *kind
= "base/index";
10739 enum flag_code addr_mode
= i386_addressing_mode ();
10741 if (current_templates
->start
->opcode_modifier
.isstring
10742 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10743 && (current_templates
->end
[-1].opcode_modifier
.isstring
10744 || i
.mem_operands
))
10746 /* Memory operands of string insns are special in that they only allow
10747 a single register (rDI, rSI, or rBX) as their memory address. */
10748 const reg_entry
*expected_reg
;
10749 static const char *di_si
[][2] =
10755 static const char *bx
[] = { "ebx", "bx", "rbx" };
10757 kind
= "string address";
10759 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10761 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10762 - IS_STRING_ES_OP0
;
10765 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10766 || ((!i
.mem_operands
!= !intel_syntax
)
10767 && current_templates
->end
[-1].operand_types
[1]
10768 .bitfield
.baseindex
))
10770 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10773 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10775 if (i
.base_reg
!= expected_reg
10777 || operand_type_check (i
.types
[this_operand
], disp
))
10779 /* The second memory operand must have the same size as
10783 && !((addr_mode
== CODE_64BIT
10784 && i
.base_reg
->reg_type
.bitfield
.qword
)
10785 || (addr_mode
== CODE_32BIT
10786 ? i
.base_reg
->reg_type
.bitfield
.dword
10787 : i
.base_reg
->reg_type
.bitfield
.word
)))
10790 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10792 intel_syntax
? '[' : '(',
10794 expected_reg
->reg_name
,
10795 intel_syntax
? ']' : ')');
10802 as_bad (_("`%s' is not a valid %s expression"),
10803 operand_string
, kind
);
10808 if (addr_mode
!= CODE_16BIT
)
10810 /* 32-bit/64-bit checks. */
10812 && ((addr_mode
== CODE_64BIT
10813 ? !i
.base_reg
->reg_type
.bitfield
.qword
10814 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10815 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10816 || i
.base_reg
->reg_num
== RegIZ
))
10818 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10819 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10820 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10821 && ((addr_mode
== CODE_64BIT
10822 ? !i
.index_reg
->reg_type
.bitfield
.qword
10823 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10824 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10827 /* bndmk, bndldx, and bndstx have special restrictions. */
10828 if (current_templates
->start
->base_opcode
== 0xf30f1b
10829 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10831 /* They cannot use RIP-relative addressing. */
10832 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10834 as_bad (_("`%s' cannot be used here"), operand_string
);
10838 /* bndldx and bndstx ignore their scale factor. */
10839 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10840 && i
.log2_scale_factor
)
10841 as_warn (_("register scaling is being ignored here"));
10846 /* 16-bit checks. */
10848 && (!i
.base_reg
->reg_type
.bitfield
.word
10849 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10851 && (!i
.index_reg
->reg_type
.bitfield
.word
10852 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10854 && i
.base_reg
->reg_num
< 6
10855 && i
.index_reg
->reg_num
>= 6
10856 && i
.log2_scale_factor
== 0))))
10863 /* Handle vector immediates. */
10866 RC_SAE_immediate (const char *imm_start
)
10868 unsigned int match_found
, j
;
10869 const char *pstr
= imm_start
;
10877 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10879 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10883 rc_op
.type
= RC_NamesTable
[j
].type
;
10884 rc_op
.operand
= this_operand
;
10885 i
.rounding
= &rc_op
;
10889 as_bad (_("duplicated `%s'"), imm_start
);
10892 pstr
+= RC_NamesTable
[j
].len
;
10900 if (*pstr
++ != '}')
10902 as_bad (_("Missing '}': '%s'"), imm_start
);
10905 /* RC/SAE immediate string should contain nothing more. */;
10908 as_bad (_("Junk after '}': '%s'"), imm_start
);
10912 exp
= &im_expressions
[i
.imm_operands
++];
10913 i
.op
[this_operand
].imms
= exp
;
10915 exp
->X_op
= O_constant
;
10916 exp
->X_add_number
= 0;
10917 exp
->X_add_symbol
= (symbolS
*) 0;
10918 exp
->X_op_symbol
= (symbolS
*) 0;
10920 i
.types
[this_operand
].bitfield
.imm8
= 1;
10924 /* Only string instructions can have a second memory operand, so
10925 reduce current_templates to just those if it contains any. */
10927 maybe_adjust_templates (void)
10929 const insn_template
*t
;
10931 gas_assert (i
.mem_operands
== 1);
10933 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10934 if (t
->opcode_modifier
.isstring
)
10937 if (t
< current_templates
->end
)
10939 static templates aux_templates
;
10940 bfd_boolean recheck
;
10942 aux_templates
.start
= t
;
10943 for (; t
< current_templates
->end
; ++t
)
10944 if (!t
->opcode_modifier
.isstring
)
10946 aux_templates
.end
= t
;
10948 /* Determine whether to re-check the first memory operand. */
10949 recheck
= (aux_templates
.start
!= current_templates
->start
10950 || t
!= current_templates
->end
);
10952 current_templates
= &aux_templates
;
10956 i
.mem_operands
= 0;
10957 if (i
.memop1_string
!= NULL
10958 && i386_index_check (i
.memop1_string
) == 0)
10960 i
.mem_operands
= 1;
10967 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10971 i386_att_operand (char *operand_string
)
10973 const reg_entry
*r
;
10975 char *op_string
= operand_string
;
10977 if (is_space_char (*op_string
))
10980 /* We check for an absolute prefix (differentiating,
10981 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10982 if (*op_string
== ABSOLUTE_PREFIX
)
10985 if (is_space_char (*op_string
))
10987 i
.jumpabsolute
= TRUE
;
10990 /* Check if operand is a register. */
10991 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10993 i386_operand_type temp
;
10995 /* Check for a segment override by searching for ':' after a
10996 segment register. */
10997 op_string
= end_op
;
10998 if (is_space_char (*op_string
))
11000 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11002 switch (r
->reg_num
)
11005 i
.seg
[i
.mem_operands
] = &es
;
11008 i
.seg
[i
.mem_operands
] = &cs
;
11011 i
.seg
[i
.mem_operands
] = &ss
;
11014 i
.seg
[i
.mem_operands
] = &ds
;
11017 i
.seg
[i
.mem_operands
] = &fs
;
11020 i
.seg
[i
.mem_operands
] = &gs
;
11024 /* Skip the ':' and whitespace. */
11026 if (is_space_char (*op_string
))
11029 if (!is_digit_char (*op_string
)
11030 && !is_identifier_char (*op_string
)
11031 && *op_string
!= '('
11032 && *op_string
!= ABSOLUTE_PREFIX
)
11034 as_bad (_("bad memory operand `%s'"), op_string
);
11037 /* Handle case of %es:*foo. */
11038 if (*op_string
== ABSOLUTE_PREFIX
)
11041 if (is_space_char (*op_string
))
11043 i
.jumpabsolute
= TRUE
;
11045 goto do_memory_reference
;
11048 /* Handle vector operations. */
11049 if (*op_string
== '{')
11051 op_string
= check_VecOperations (op_string
, NULL
);
11052 if (op_string
== NULL
)
11058 as_bad (_("junk `%s' after register"), op_string
);
11061 temp
= r
->reg_type
;
11062 temp
.bitfield
.baseindex
= 0;
11063 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11065 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11066 i
.op
[this_operand
].regs
= r
;
11069 else if (*op_string
== REGISTER_PREFIX
)
11071 as_bad (_("bad register name `%s'"), op_string
);
11074 else if (*op_string
== IMMEDIATE_PREFIX
)
11077 if (i
.jumpabsolute
)
11079 as_bad (_("immediate operand illegal with absolute jump"));
11082 if (!i386_immediate (op_string
))
11085 else if (RC_SAE_immediate (operand_string
))
11087 /* If it is a RC or SAE immediate, do nothing. */
11090 else if (is_digit_char (*op_string
)
11091 || is_identifier_char (*op_string
)
11092 || *op_string
== '"'
11093 || *op_string
== '(')
11095 /* This is a memory reference of some sort. */
11098 /* Start and end of displacement string expression (if found). */
11099 char *displacement_string_start
;
11100 char *displacement_string_end
;
11103 do_memory_reference
:
11104 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11106 if ((i
.mem_operands
== 1
11107 && !current_templates
->start
->opcode_modifier
.isstring
)
11108 || i
.mem_operands
== 2)
11110 as_bad (_("too many memory references for `%s'"),
11111 current_templates
->start
->name
);
11115 /* Check for base index form. We detect the base index form by
11116 looking for an ')' at the end of the operand, searching
11117 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11119 base_string
= op_string
+ strlen (op_string
);
11121 /* Handle vector operations. */
11122 vop_start
= strchr (op_string
, '{');
11123 if (vop_start
&& vop_start
< base_string
)
11125 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11127 base_string
= vop_start
;
11131 if (is_space_char (*base_string
))
11134 /* If we only have a displacement, set-up for it to be parsed later. */
11135 displacement_string_start
= op_string
;
11136 displacement_string_end
= base_string
+ 1;
11138 if (*base_string
== ')')
11141 unsigned int parens_balanced
= 1;
11142 /* We've already checked that the number of left & right ()'s are
11143 equal, so this loop will not be infinite. */
11147 if (*base_string
== ')')
11149 if (*base_string
== '(')
11152 while (parens_balanced
);
11154 temp_string
= base_string
;
11156 /* Skip past '(' and whitespace. */
11158 if (is_space_char (*base_string
))
11161 if (*base_string
== ','
11162 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11165 displacement_string_end
= temp_string
;
11167 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11171 base_string
= end_op
;
11172 if (is_space_char (*base_string
))
11176 /* There may be an index reg or scale factor here. */
11177 if (*base_string
== ',')
11180 if (is_space_char (*base_string
))
11183 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11186 base_string
= end_op
;
11187 if (is_space_char (*base_string
))
11189 if (*base_string
== ',')
11192 if (is_space_char (*base_string
))
11195 else if (*base_string
!= ')')
11197 as_bad (_("expecting `,' or `)' "
11198 "after index register in `%s'"),
11203 else if (*base_string
== REGISTER_PREFIX
)
11205 end_op
= strchr (base_string
, ',');
11208 as_bad (_("bad register name `%s'"), base_string
);
11212 /* Check for scale factor. */
11213 if (*base_string
!= ')')
11215 char *end_scale
= i386_scale (base_string
);
11220 base_string
= end_scale
;
11221 if (is_space_char (*base_string
))
11223 if (*base_string
!= ')')
11225 as_bad (_("expecting `)' "
11226 "after scale factor in `%s'"),
11231 else if (!i
.index_reg
)
11233 as_bad (_("expecting index register or scale factor "
11234 "after `,'; got '%c'"),
11239 else if (*base_string
!= ')')
11241 as_bad (_("expecting `,' or `)' "
11242 "after base register in `%s'"),
11247 else if (*base_string
== REGISTER_PREFIX
)
11249 end_op
= strchr (base_string
, ',');
11252 as_bad (_("bad register name `%s'"), base_string
);
11257 /* If there's an expression beginning the operand, parse it,
11258 assuming displacement_string_start and
11259 displacement_string_end are meaningful. */
11260 if (displacement_string_start
!= displacement_string_end
)
11262 if (!i386_displacement (displacement_string_start
,
11263 displacement_string_end
))
11267 /* Special case for (%dx) while doing input/output op. */
11269 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11270 && i
.base_reg
->reg_type
.bitfield
.word
11271 && i
.index_reg
== 0
11272 && i
.log2_scale_factor
== 0
11273 && i
.seg
[i
.mem_operands
] == 0
11274 && !operand_type_check (i
.types
[this_operand
], disp
))
11276 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11280 if (i386_index_check (operand_string
) == 0)
11282 i
.flags
[this_operand
] |= Operand_Mem
;
11283 if (i
.mem_operands
== 0)
11284 i
.memop1_string
= xstrdup (operand_string
);
11289 /* It's not a memory operand; argh! */
11290 as_bad (_("invalid char %s beginning operand %d `%s'"),
11291 output_invalid (*op_string
),
11296 return 1; /* Normal return. */
11299 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11300 that an rs_machine_dependent frag may reach. */
11303 i386_frag_max_var (fragS
*frag
)
11305 /* The only relaxable frags are for jumps.
11306 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11307 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11308 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11311 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11313 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11315 /* STT_GNU_IFUNC symbol must go through PLT. */
11316 if ((symbol_get_bfdsym (fr_symbol
)->flags
11317 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11320 if (!S_IS_EXTERNAL (fr_symbol
))
11321 /* Symbol may be weak or local. */
11322 return !S_IS_WEAK (fr_symbol
);
11324 /* Global symbols with non-default visibility can't be preempted. */
11325 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11328 if (fr_var
!= NO_RELOC
)
11329 switch ((enum bfd_reloc_code_real
) fr_var
)
11331 case BFD_RELOC_386_PLT32
:
11332 case BFD_RELOC_X86_64_PLT32
:
11333 /* Symbol with PLT relocation may be preempted. */
11339 /* Global symbols with default visibility in a shared library may be
11340 preempted by another definition. */
11345 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11346 Note also work for Skylake and Cascadelake.
11347 ---------------------------------------------------------------------
11348 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11349 | ------ | ----------- | ------- | -------- |
11351 | Jno | N | N | Y |
11352 | Jc/Jb | Y | N | Y |
11353 | Jae/Jnb | Y | N | Y |
11354 | Je/Jz | Y | Y | Y |
11355 | Jne/Jnz | Y | Y | Y |
11356 | Jna/Jbe | Y | N | Y |
11357 | Ja/Jnbe | Y | N | Y |
11359 | Jns | N | N | Y |
11360 | Jp/Jpe | N | N | Y |
11361 | Jnp/Jpo | N | N | Y |
11362 | Jl/Jnge | Y | Y | Y |
11363 | Jge/Jnl | Y | Y | Y |
11364 | Jle/Jng | Y | Y | Y |
11365 | Jg/Jnle | Y | Y | Y |
11366 --------------------------------------------------------------------- */
11368 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11370 if (mf_cmp
== mf_cmp_alu_cmp
)
11371 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11372 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11373 if (mf_cmp
== mf_cmp_incdec
)
11374 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11375 || mf_jcc
== mf_jcc_jle
);
11376 if (mf_cmp
== mf_cmp_test_and
)
11381 /* Return the next non-empty frag. */
11384 i386_next_non_empty_frag (fragS
*fragP
)
11386 /* There may be a frag with a ".fill 0" when there is no room in
11387 the current frag for frag_grow in output_insn. */
11388 for (fragP
= fragP
->fr_next
;
11390 && fragP
->fr_type
== rs_fill
11391 && fragP
->fr_fix
== 0);
11392 fragP
= fragP
->fr_next
)
11397 /* Return the next jcc frag after BRANCH_PADDING. */
11400 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11402 fragS
*branch_fragP
;
11406 if (pad_fragP
->fr_type
== rs_machine_dependent
11407 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11408 == BRANCH_PADDING
))
11410 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11411 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11413 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11414 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11415 pad_fragP
->tc_frag_data
.mf_type
))
11416 return branch_fragP
;
11422 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11425 i386_classify_machine_dependent_frag (fragS
*fragP
)
11429 fragS
*branch_fragP
;
11431 unsigned int max_prefix_length
;
11433 if (fragP
->tc_frag_data
.classified
)
11436 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11437 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11438 for (next_fragP
= fragP
;
11439 next_fragP
!= NULL
;
11440 next_fragP
= next_fragP
->fr_next
)
11442 next_fragP
->tc_frag_data
.classified
= 1;
11443 if (next_fragP
->fr_type
== rs_machine_dependent
)
11444 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11446 case BRANCH_PADDING
:
11447 /* The BRANCH_PADDING frag must be followed by a branch
11449 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11450 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11452 case FUSED_JCC_PADDING
:
11453 /* Check if this is a fused jcc:
11455 CMP like instruction
11459 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11460 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11461 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11464 /* The BRANCH_PADDING frag is merged with the
11465 FUSED_JCC_PADDING frag. */
11466 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11467 /* CMP like instruction size. */
11468 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11469 frag_wane (pad_fragP
);
11470 /* Skip to branch_fragP. */
11471 next_fragP
= branch_fragP
;
11473 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11475 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11477 next_fragP
->fr_subtype
11478 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11479 next_fragP
->tc_frag_data
.max_bytes
11480 = next_fragP
->tc_frag_data
.max_prefix_length
;
11481 /* This will be updated in the BRANCH_PREFIX scan. */
11482 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11485 frag_wane (next_fragP
);
11490 /* Stop if there is no BRANCH_PREFIX. */
11491 if (!align_branch_prefix_size
)
11494 /* Scan for BRANCH_PREFIX. */
11495 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11497 if (fragP
->fr_type
!= rs_machine_dependent
11498 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11502 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11503 COND_JUMP_PREFIX. */
11504 max_prefix_length
= 0;
11505 for (next_fragP
= fragP
;
11506 next_fragP
!= NULL
;
11507 next_fragP
= next_fragP
->fr_next
)
11509 if (next_fragP
->fr_type
== rs_fill
)
11510 /* Skip rs_fill frags. */
11512 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11513 /* Stop for all other frags. */
11516 /* rs_machine_dependent frags. */
11517 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11520 /* Count BRANCH_PREFIX frags. */
11521 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11523 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11524 frag_wane (next_fragP
);
11528 += next_fragP
->tc_frag_data
.max_bytes
;
11530 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11532 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11533 == FUSED_JCC_PADDING
))
11535 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11536 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11540 /* Stop for other rs_machine_dependent frags. */
11544 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11546 /* Skip to the next frag. */
11547 fragP
= next_fragP
;
11551 /* Compute padding size for
11554 CMP like instruction
11556 COND_JUMP/UNCOND_JUMP
11561 COND_JUMP/UNCOND_JUMP
11565 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11567 unsigned int offset
, size
, padding_size
;
11568 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11570 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11572 address
= fragP
->fr_address
;
11573 address
+= fragP
->fr_fix
;
11575 /* CMP like instrunction size. */
11576 size
= fragP
->tc_frag_data
.cmp_size
;
11578 /* The base size of the branch frag. */
11579 size
+= branch_fragP
->fr_fix
;
11581 /* Add opcode and displacement bytes for the rs_machine_dependent
11583 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11584 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11586 /* Check if branch is within boundary and doesn't end at the last
11588 offset
= address
& ((1U << align_branch_power
) - 1);
11589 if ((offset
+ size
) >= (1U << align_branch_power
))
11590 /* Padding needed to avoid crossing boundary. */
11591 padding_size
= (1U << align_branch_power
) - offset
;
11593 /* No padding needed. */
11596 /* The return value may be saved in tc_frag_data.length which is
11598 if (!fits_in_unsigned_byte (padding_size
))
11601 return padding_size
;
11604 /* i386_generic_table_relax_frag()
11606 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11607 grow/shrink padding to align branch frags. Hand others to
11611 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11613 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11614 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11616 long padding_size
= i386_branch_padding_size (fragP
, 0);
11617 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11619 /* When the BRANCH_PREFIX frag is used, the computed address
11620 must match the actual address and there should be no padding. */
11621 if (fragP
->tc_frag_data
.padding_address
11622 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11626 /* Update the padding size. */
11628 fragP
->tc_frag_data
.length
= padding_size
;
11632 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11634 fragS
*padding_fragP
, *next_fragP
;
11635 long padding_size
, left_size
, last_size
;
11637 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11638 if (!padding_fragP
)
11639 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11640 return (fragP
->tc_frag_data
.length
11641 - fragP
->tc_frag_data
.last_length
);
11643 /* Compute the relative address of the padding frag in the very
11644 first time where the BRANCH_PREFIX frag sizes are zero. */
11645 if (!fragP
->tc_frag_data
.padding_address
)
11646 fragP
->tc_frag_data
.padding_address
11647 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11649 /* First update the last length from the previous interation. */
11650 left_size
= fragP
->tc_frag_data
.prefix_length
;
11651 for (next_fragP
= fragP
;
11652 next_fragP
!= padding_fragP
;
11653 next_fragP
= next_fragP
->fr_next
)
11654 if (next_fragP
->fr_type
== rs_machine_dependent
11655 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11660 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11664 if (max
> left_size
)
11669 next_fragP
->tc_frag_data
.last_length
= size
;
11673 next_fragP
->tc_frag_data
.last_length
= 0;
11676 /* Check the padding size for the padding frag. */
11677 padding_size
= i386_branch_padding_size
11678 (padding_fragP
, (fragP
->fr_address
11679 + fragP
->tc_frag_data
.padding_address
));
11681 last_size
= fragP
->tc_frag_data
.prefix_length
;
11682 /* Check if there is change from the last interation. */
11683 if (padding_size
== last_size
)
11685 /* Update the expected address of the padding frag. */
11686 padding_fragP
->tc_frag_data
.padding_address
11687 = (fragP
->fr_address
+ padding_size
11688 + fragP
->tc_frag_data
.padding_address
);
11692 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11694 /* No padding if there is no sufficient room. Clear the
11695 expected address of the padding frag. */
11696 padding_fragP
->tc_frag_data
.padding_address
= 0;
11700 /* Store the expected address of the padding frag. */
11701 padding_fragP
->tc_frag_data
.padding_address
11702 = (fragP
->fr_address
+ padding_size
11703 + fragP
->tc_frag_data
.padding_address
);
11705 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11707 /* Update the length for the current interation. */
11708 left_size
= padding_size
;
11709 for (next_fragP
= fragP
;
11710 next_fragP
!= padding_fragP
;
11711 next_fragP
= next_fragP
->fr_next
)
11712 if (next_fragP
->fr_type
== rs_machine_dependent
11713 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11718 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11722 if (max
> left_size
)
11727 next_fragP
->tc_frag_data
.length
= size
;
11731 next_fragP
->tc_frag_data
.length
= 0;
11734 return (fragP
->tc_frag_data
.length
11735 - fragP
->tc_frag_data
.last_length
);
11737 return relax_frag (segment
, fragP
, stretch
);
11740 /* md_estimate_size_before_relax()
11742 Called just before relax() for rs_machine_dependent frags. The x86
11743 assembler uses these frags to handle variable size jump
11746 Any symbol that is now undefined will not become defined.
11747 Return the correct fr_subtype in the frag.
11748 Return the initial "guess for variable size of frag" to caller.
11749 The guess is actually the growth beyond the fixed part. Whatever
11750 we do to grow the fixed or variable part contributes to our
11754 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11756 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11757 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11758 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11760 i386_classify_machine_dependent_frag (fragP
);
11761 return fragP
->tc_frag_data
.length
;
11764 /* We've already got fragP->fr_subtype right; all we have to do is
11765 check for un-relaxable symbols. On an ELF system, we can't relax
11766 an externally visible symbol, because it may be overridden by a
11768 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11771 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11774 #if defined (OBJ_COFF) && defined (TE_PE)
11775 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11776 && S_IS_WEAK (fragP
->fr_symbol
))
11780 /* Symbol is undefined in this segment, or we need to keep a
11781 reloc so that weak symbols can be overridden. */
11782 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11783 enum bfd_reloc_code_real reloc_type
;
11784 unsigned char *opcode
;
11787 if (fragP
->fr_var
!= NO_RELOC
)
11788 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11789 else if (size
== 2)
11790 reloc_type
= BFD_RELOC_16_PCREL
;
11791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11792 else if (need_plt32_p (fragP
->fr_symbol
))
11793 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11796 reloc_type
= BFD_RELOC_32_PCREL
;
11798 old_fr_fix
= fragP
->fr_fix
;
11799 opcode
= (unsigned char *) fragP
->fr_opcode
;
11801 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11804 /* Make jmp (0xeb) a (d)word displacement jump. */
11806 fragP
->fr_fix
+= size
;
11807 fix_new (fragP
, old_fr_fix
, size
,
11809 fragP
->fr_offset
, 1,
11815 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11817 /* Negate the condition, and branch past an
11818 unconditional jump. */
11821 /* Insert an unconditional jump. */
11823 /* We added two extra opcode bytes, and have a two byte
11825 fragP
->fr_fix
+= 2 + 2;
11826 fix_new (fragP
, old_fr_fix
+ 2, 2,
11828 fragP
->fr_offset
, 1,
11832 /* Fall through. */
11835 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11839 fragP
->fr_fix
+= 1;
11840 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11842 fragP
->fr_offset
, 1,
11843 BFD_RELOC_8_PCREL
);
11844 fixP
->fx_signed
= 1;
11848 /* This changes the byte-displacement jump 0x7N
11849 to the (d)word-displacement jump 0x0f,0x8N. */
11850 opcode
[1] = opcode
[0] + 0x10;
11851 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11852 /* We've added an opcode byte. */
11853 fragP
->fr_fix
+= 1 + size
;
11854 fix_new (fragP
, old_fr_fix
+ 1, size
,
11856 fragP
->fr_offset
, 1,
11861 BAD_CASE (fragP
->fr_subtype
);
11865 return fragP
->fr_fix
- old_fr_fix
;
11868 /* Guess size depending on current relax state. Initially the relax
11869 state will correspond to a short jump and we return 1, because
11870 the variable part of the frag (the branch offset) is one byte
11871 long. However, we can relax a section more than once and in that
11872 case we must either set fr_subtype back to the unrelaxed state,
11873 or return the value for the appropriate branch. */
11874 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11877 /* Called after relax() is finished.
11879 In: Address of frag.
11880 fr_type == rs_machine_dependent.
11881 fr_subtype is what the address relaxed to.
11883 Out: Any fixSs and constants are set up.
11884 Caller will turn frag into a ".space 0". */
11887 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11890 unsigned char *opcode
;
11891 unsigned char *where_to_put_displacement
= NULL
;
11892 offsetT target_address
;
11893 offsetT opcode_address
;
11894 unsigned int extension
= 0;
11895 offsetT displacement_from_opcode_start
;
11897 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11898 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11899 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11901 /* Generate nop padding. */
11902 unsigned int size
= fragP
->tc_frag_data
.length
;
11905 if (size
> fragP
->tc_frag_data
.max_bytes
)
11911 const char *branch
= "branch";
11912 const char *prefix
= "";
11913 fragS
*padding_fragP
;
11914 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11917 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11918 switch (fragP
->tc_frag_data
.default_prefix
)
11923 case CS_PREFIX_OPCODE
:
11926 case DS_PREFIX_OPCODE
:
11929 case ES_PREFIX_OPCODE
:
11932 case FS_PREFIX_OPCODE
:
11935 case GS_PREFIX_OPCODE
:
11938 case SS_PREFIX_OPCODE
:
11943 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11944 "%s within %d-byte boundary\n");
11946 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11947 "align %s within %d-byte boundary\n");
11951 padding_fragP
= fragP
;
11952 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11953 "%s within %d-byte boundary\n");
11957 switch (padding_fragP
->tc_frag_data
.branch_type
)
11959 case align_branch_jcc
:
11962 case align_branch_fused
:
11963 branch
= "fused jcc";
11965 case align_branch_jmp
:
11968 case align_branch_call
:
11971 case align_branch_indirect
:
11972 branch
= "indiret branch";
11974 case align_branch_ret
:
11981 fprintf (stdout
, msg
,
11982 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11983 (long long) fragP
->fr_address
, branch
,
11984 1 << align_branch_power
);
11986 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11987 memset (fragP
->fr_opcode
,
11988 fragP
->tc_frag_data
.default_prefix
, size
);
11990 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11992 fragP
->fr_fix
+= size
;
11997 opcode
= (unsigned char *) fragP
->fr_opcode
;
11999 /* Address we want to reach in file space. */
12000 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12002 /* Address opcode resides at in file space. */
12003 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12005 /* Displacement from opcode start to fill into instruction. */
12006 displacement_from_opcode_start
= target_address
- opcode_address
;
12008 if ((fragP
->fr_subtype
& BIG
) == 0)
12010 /* Don't have to change opcode. */
12011 extension
= 1; /* 1 opcode + 1 displacement */
12012 where_to_put_displacement
= &opcode
[1];
12016 if (no_cond_jump_promotion
12017 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12018 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12019 _("long jump required"));
12021 switch (fragP
->fr_subtype
)
12023 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12024 extension
= 4; /* 1 opcode + 4 displacement */
12026 where_to_put_displacement
= &opcode
[1];
12029 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12030 extension
= 2; /* 1 opcode + 2 displacement */
12032 where_to_put_displacement
= &opcode
[1];
12035 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12036 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12037 extension
= 5; /* 2 opcode + 4 displacement */
12038 opcode
[1] = opcode
[0] + 0x10;
12039 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12040 where_to_put_displacement
= &opcode
[2];
12043 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12044 extension
= 3; /* 2 opcode + 2 displacement */
12045 opcode
[1] = opcode
[0] + 0x10;
12046 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12047 where_to_put_displacement
= &opcode
[2];
12050 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12055 where_to_put_displacement
= &opcode
[3];
12059 BAD_CASE (fragP
->fr_subtype
);
12064 /* If size if less then four we are sure that the operand fits,
12065 but if it's 4, then it could be that the displacement is larger
12067 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12069 && ((addressT
) (displacement_from_opcode_start
- extension
12070 + ((addressT
) 1 << 31))
12071 > (((addressT
) 2 << 31) - 1)))
12073 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12074 _("jump target out of range"));
12075 /* Make us emit 0. */
12076 displacement_from_opcode_start
= extension
;
12078 /* Now put displacement after opcode. */
12079 md_number_to_chars ((char *) where_to_put_displacement
,
12080 (valueT
) (displacement_from_opcode_start
- extension
),
12081 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12082 fragP
->fr_fix
+= extension
;
12085 /* Apply a fixup (fixP) to segment data, once it has been determined
12086 by our caller that we have all the info we need to fix it up.
12088 Parameter valP is the pointer to the value of the bits.
12090 On the 386, immediates, displacements, and data pointers are all in
12091 the same (little-endian) format, so we don't need to care about which
12092 we are handling. */
12095 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12097 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12098 valueT value
= *valP
;
12100 #if !defined (TE_Mach)
12101 if (fixP
->fx_pcrel
)
12103 switch (fixP
->fx_r_type
)
12109 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12112 case BFD_RELOC_X86_64_32S
:
12113 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12116 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12119 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12124 if (fixP
->fx_addsy
!= NULL
12125 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12126 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12127 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12128 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12129 && !use_rela_relocations
)
12131 /* This is a hack. There should be a better way to handle this.
12132 This covers for the fact that bfd_install_relocation will
12133 subtract the current location (for partial_inplace, PC relative
12134 relocations); see more below. */
12138 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12141 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12146 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12148 if ((sym_seg
== seg
12149 || (symbol_section_p (fixP
->fx_addsy
)
12150 && sym_seg
!= absolute_section
))
12151 && !generic_force_reloc (fixP
))
12153 /* Yes, we add the values in twice. This is because
12154 bfd_install_relocation subtracts them out again. I think
12155 bfd_install_relocation is broken, but I don't dare change
12157 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12161 #if defined (OBJ_COFF) && defined (TE_PE)
12162 /* For some reason, the PE format does not store a
12163 section address offset for a PC relative symbol. */
12164 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12165 || S_IS_WEAK (fixP
->fx_addsy
))
12166 value
+= md_pcrel_from (fixP
);
12169 #if defined (OBJ_COFF) && defined (TE_PE)
12170 if (fixP
->fx_addsy
!= NULL
12171 && S_IS_WEAK (fixP
->fx_addsy
)
12172 /* PR 16858: Do not modify weak function references. */
12173 && ! fixP
->fx_pcrel
)
12175 #if !defined (TE_PEP)
12176 /* For x86 PE weak function symbols are neither PC-relative
12177 nor do they set S_IS_FUNCTION. So the only reliable way
12178 to detect them is to check the flags of their containing
12180 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12181 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12185 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12189 /* Fix a few things - the dynamic linker expects certain values here,
12190 and we must not disappoint it. */
12191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12192 if (IS_ELF
&& fixP
->fx_addsy
)
12193 switch (fixP
->fx_r_type
)
12195 case BFD_RELOC_386_PLT32
:
12196 case BFD_RELOC_X86_64_PLT32
:
12197 /* Make the jump instruction point to the address of the operand.
12198 At runtime we merely add the offset to the actual PLT entry.
12199 NB: Subtract the offset size only for jump instructions. */
12200 if (fixP
->fx_pcrel
)
12204 case BFD_RELOC_386_TLS_GD
:
12205 case BFD_RELOC_386_TLS_LDM
:
12206 case BFD_RELOC_386_TLS_IE_32
:
12207 case BFD_RELOC_386_TLS_IE
:
12208 case BFD_RELOC_386_TLS_GOTIE
:
12209 case BFD_RELOC_386_TLS_GOTDESC
:
12210 case BFD_RELOC_X86_64_TLSGD
:
12211 case BFD_RELOC_X86_64_TLSLD
:
12212 case BFD_RELOC_X86_64_GOTTPOFF
:
12213 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12214 value
= 0; /* Fully resolved at runtime. No addend. */
12216 case BFD_RELOC_386_TLS_LE
:
12217 case BFD_RELOC_386_TLS_LDO_32
:
12218 case BFD_RELOC_386_TLS_LE_32
:
12219 case BFD_RELOC_X86_64_DTPOFF32
:
12220 case BFD_RELOC_X86_64_DTPOFF64
:
12221 case BFD_RELOC_X86_64_TPOFF32
:
12222 case BFD_RELOC_X86_64_TPOFF64
:
12223 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12226 case BFD_RELOC_386_TLS_DESC_CALL
:
12227 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12228 value
= 0; /* Fully resolved at runtime. No addend. */
12229 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12233 case BFD_RELOC_VTABLE_INHERIT
:
12234 case BFD_RELOC_VTABLE_ENTRY
:
12241 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12243 #endif /* !defined (TE_Mach) */
12245 /* Are we finished with this relocation now? */
12246 if (fixP
->fx_addsy
== NULL
)
12248 #if defined (OBJ_COFF) && defined (TE_PE)
12249 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12252 /* Remember value for tc_gen_reloc. */
12253 fixP
->fx_addnumber
= value
;
12254 /* Clear out the frag for now. */
12258 else if (use_rela_relocations
)
12260 fixP
->fx_no_overflow
= 1;
12261 /* Remember value for tc_gen_reloc. */
12262 fixP
->fx_addnumber
= value
;
12266 md_number_to_chars (p
, value
, fixP
->fx_size
);
12270 md_atof (int type
, char *litP
, int *sizeP
)
12272 /* This outputs the LITTLENUMs in REVERSE order;
12273 in accord with the bigendian 386. */
12274 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12277 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12280 output_invalid (int c
)
12283 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12286 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12287 "(0x%x)", (unsigned char) c
);
12288 return output_invalid_buf
;
12291 /* REG_STRING starts *before* REGISTER_PREFIX. */
12293 static const reg_entry
*
12294 parse_real_register (char *reg_string
, char **end_op
)
12296 char *s
= reg_string
;
12298 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12299 const reg_entry
*r
;
12301 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12302 if (*s
== REGISTER_PREFIX
)
12305 if (is_space_char (*s
))
12308 p
= reg_name_given
;
12309 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12311 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12312 return (const reg_entry
*) NULL
;
12316 /* For naked regs, make sure that we are not dealing with an identifier.
12317 This prevents confusing an identifier like `eax_var' with register
12319 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12320 return (const reg_entry
*) NULL
;
12324 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12326 /* Handle floating point regs, allowing spaces in the (i) part. */
12327 if (r
== i386_regtab
/* %st is first entry of table */)
12329 if (!cpu_arch_flags
.bitfield
.cpu8087
12330 && !cpu_arch_flags
.bitfield
.cpu287
12331 && !cpu_arch_flags
.bitfield
.cpu387
)
12332 return (const reg_entry
*) NULL
;
12334 if (is_space_char (*s
))
12339 if (is_space_char (*s
))
12341 if (*s
>= '0' && *s
<= '7')
12343 int fpr
= *s
- '0';
12345 if (is_space_char (*s
))
12350 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12355 /* We have "%st(" then garbage. */
12356 return (const reg_entry
*) NULL
;
12360 if (r
== NULL
|| allow_pseudo_reg
)
12363 if (operand_type_all_zero (&r
->reg_type
))
12364 return (const reg_entry
*) NULL
;
12366 if ((r
->reg_type
.bitfield
.dword
12367 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12368 || r
->reg_type
.bitfield
.class == RegCR
12369 || r
->reg_type
.bitfield
.class == RegDR
12370 || r
->reg_type
.bitfield
.class == RegTR
)
12371 && !cpu_arch_flags
.bitfield
.cpui386
)
12372 return (const reg_entry
*) NULL
;
12374 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12375 return (const reg_entry
*) NULL
;
12377 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12379 if (r
->reg_type
.bitfield
.zmmword
12380 || r
->reg_type
.bitfield
.class == RegMask
)
12381 return (const reg_entry
*) NULL
;
12383 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12385 if (r
->reg_type
.bitfield
.ymmword
)
12386 return (const reg_entry
*) NULL
;
12388 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12389 return (const reg_entry
*) NULL
;
12393 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12394 return (const reg_entry
*) NULL
;
12396 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12397 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12398 return (const reg_entry
*) NULL
;
12400 /* Upper 16 vector registers are only available with VREX in 64bit
12401 mode, and require EVEX encoding. */
12402 if (r
->reg_flags
& RegVRex
)
12404 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12405 || flag_code
!= CODE_64BIT
)
12406 return (const reg_entry
*) NULL
;
12408 i
.vec_encoding
= vex_encoding_evex
;
12411 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12412 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12413 && flag_code
!= CODE_64BIT
)
12414 return (const reg_entry
*) NULL
;
12416 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12418 return (const reg_entry
*) NULL
;
12423 /* REG_STRING starts *before* REGISTER_PREFIX. */
12425 static const reg_entry
*
12426 parse_register (char *reg_string
, char **end_op
)
12428 const reg_entry
*r
;
12430 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12431 r
= parse_real_register (reg_string
, end_op
);
12436 char *save
= input_line_pointer
;
12440 input_line_pointer
= reg_string
;
12441 c
= get_symbol_name (®_string
);
12442 symbolP
= symbol_find (reg_string
);
12443 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12445 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12447 know (e
->X_op
== O_register
);
12448 know (e
->X_add_number
>= 0
12449 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12450 r
= i386_regtab
+ e
->X_add_number
;
12451 if ((r
->reg_flags
& RegVRex
))
12452 i
.vec_encoding
= vex_encoding_evex
;
12453 *end_op
= input_line_pointer
;
12455 *input_line_pointer
= c
;
12456 input_line_pointer
= save
;
12462 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12464 const reg_entry
*r
;
12465 char *end
= input_line_pointer
;
12468 r
= parse_register (name
, &input_line_pointer
);
12469 if (r
&& end
<= input_line_pointer
)
12471 *nextcharP
= *input_line_pointer
;
12472 *input_line_pointer
= 0;
12473 e
->X_op
= O_register
;
12474 e
->X_add_number
= r
- i386_regtab
;
12477 input_line_pointer
= end
;
12479 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12483 md_operand (expressionS
*e
)
12486 const reg_entry
*r
;
12488 switch (*input_line_pointer
)
12490 case REGISTER_PREFIX
:
12491 r
= parse_real_register (input_line_pointer
, &end
);
12494 e
->X_op
= O_register
;
12495 e
->X_add_number
= r
- i386_regtab
;
12496 input_line_pointer
= end
;
12501 gas_assert (intel_syntax
);
12502 end
= input_line_pointer
++;
12504 if (*input_line_pointer
== ']')
12506 ++input_line_pointer
;
12507 e
->X_op_symbol
= make_expr_symbol (e
);
12508 e
->X_add_symbol
= NULL
;
12509 e
->X_add_number
= 0;
12514 e
->X_op
= O_absent
;
12515 input_line_pointer
= end
;
12522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12523 const char *md_shortopts
= "kVQ:sqnO::";
12525 const char *md_shortopts
= "qnO::";
12528 #define OPTION_32 (OPTION_MD_BASE + 0)
12529 #define OPTION_64 (OPTION_MD_BASE + 1)
12530 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12531 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12532 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12533 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12534 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12535 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12536 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12537 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12538 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12539 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12540 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12541 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12542 #define OPTION_X32 (OPTION_MD_BASE + 14)
12543 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12544 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12545 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12546 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12547 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12548 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12549 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12550 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12551 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12552 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12553 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12554 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12555 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12556 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12557 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12558 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12559 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12560 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12561 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12563 struct option md_longopts
[] =
12565 {"32", no_argument
, NULL
, OPTION_32
},
12566 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12568 {"64", no_argument
, NULL
, OPTION_64
},
12570 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12571 {"x32", no_argument
, NULL
, OPTION_X32
},
12572 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12573 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12575 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12576 {"march", required_argument
, NULL
, OPTION_MARCH
},
12577 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12578 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12579 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12580 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12581 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12582 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12583 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12584 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12585 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12586 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12587 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12588 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12589 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12590 # if defined (TE_PE) || defined (TE_PEP)
12591 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12593 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12594 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12595 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12596 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12597 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12598 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12599 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12600 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12601 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12602 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12603 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12604 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12605 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12606 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12607 {NULL
, no_argument
, NULL
, 0}
12609 size_t md_longopts_size
= sizeof (md_longopts
);
12612 md_parse_option (int c
, const char *arg
)
12615 char *arch
, *next
, *saved
, *type
;
12620 optimize_align_code
= 0;
12624 quiet_warnings
= 1;
12627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12628 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12629 should be emitted or not. FIXME: Not implemented. */
12631 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12635 /* -V: SVR4 argument to print version ID. */
12637 print_version_id ();
12640 /* -k: Ignore for FreeBSD compatibility. */
12645 /* -s: On i386 Solaris, this tells the native assembler to use
12646 .stab instead of .stab.excl. We always use .stab anyhow. */
12649 case OPTION_MSHARED
:
12653 case OPTION_X86_USED_NOTE
:
12654 if (strcasecmp (arg
, "yes") == 0)
12656 else if (strcasecmp (arg
, "no") == 0)
12659 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12664 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12665 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12668 const char **list
, **l
;
12670 list
= bfd_target_list ();
12671 for (l
= list
; *l
!= NULL
; l
++)
12672 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12673 || strcmp (*l
, "coff-x86-64") == 0
12674 || strcmp (*l
, "pe-x86-64") == 0
12675 || strcmp (*l
, "pei-x86-64") == 0
12676 || strcmp (*l
, "mach-o-x86-64") == 0)
12678 default_arch
= "x86_64";
12682 as_fatal (_("no compiled in support for x86_64"));
12688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12692 const char **list
, **l
;
12694 list
= bfd_target_list ();
12695 for (l
= list
; *l
!= NULL
; l
++)
12696 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12698 default_arch
= "x86_64:32";
12702 as_fatal (_("no compiled in support for 32bit x86_64"));
12706 as_fatal (_("32bit x86_64 is only supported for ELF"));
12711 default_arch
= "i386";
12714 case OPTION_DIVIDE
:
12715 #ifdef SVR4_COMMENT_CHARS
12720 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12722 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12726 i386_comment_chars
= n
;
12732 saved
= xstrdup (arg
);
12734 /* Allow -march=+nosse. */
12740 as_fatal (_("invalid -march= option: `%s'"), arg
);
12741 next
= strchr (arch
, '+');
12744 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12746 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12749 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12752 cpu_arch_name
= cpu_arch
[j
].name
;
12753 cpu_sub_arch_name
= NULL
;
12754 cpu_arch_flags
= cpu_arch
[j
].flags
;
12755 cpu_arch_isa
= cpu_arch
[j
].type
;
12756 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12757 if (!cpu_arch_tune_set
)
12759 cpu_arch_tune
= cpu_arch_isa
;
12760 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12764 else if (*cpu_arch
[j
].name
== '.'
12765 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12767 /* ISA extension. */
12768 i386_cpu_flags flags
;
12770 flags
= cpu_flags_or (cpu_arch_flags
,
12771 cpu_arch
[j
].flags
);
12773 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12775 if (cpu_sub_arch_name
)
12777 char *name
= cpu_sub_arch_name
;
12778 cpu_sub_arch_name
= concat (name
,
12780 (const char *) NULL
);
12784 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12785 cpu_arch_flags
= flags
;
12786 cpu_arch_isa_flags
= flags
;
12790 = cpu_flags_or (cpu_arch_isa_flags
,
12791 cpu_arch
[j
].flags
);
12796 if (j
>= ARRAY_SIZE (cpu_arch
))
12798 /* Disable an ISA extension. */
12799 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12800 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12802 i386_cpu_flags flags
;
12804 flags
= cpu_flags_and_not (cpu_arch_flags
,
12805 cpu_noarch
[j
].flags
);
12806 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12808 if (cpu_sub_arch_name
)
12810 char *name
= cpu_sub_arch_name
;
12811 cpu_sub_arch_name
= concat (arch
,
12812 (const char *) NULL
);
12816 cpu_sub_arch_name
= xstrdup (arch
);
12817 cpu_arch_flags
= flags
;
12818 cpu_arch_isa_flags
= flags
;
12823 if (j
>= ARRAY_SIZE (cpu_noarch
))
12824 j
= ARRAY_SIZE (cpu_arch
);
12827 if (j
>= ARRAY_SIZE (cpu_arch
))
12828 as_fatal (_("invalid -march= option: `%s'"), arg
);
12832 while (next
!= NULL
);
12838 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12839 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12841 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12843 cpu_arch_tune_set
= 1;
12844 cpu_arch_tune
= cpu_arch
[j
].type
;
12845 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12849 if (j
>= ARRAY_SIZE (cpu_arch
))
12850 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12853 case OPTION_MMNEMONIC
:
12854 if (strcasecmp (arg
, "att") == 0)
12855 intel_mnemonic
= 0;
12856 else if (strcasecmp (arg
, "intel") == 0)
12857 intel_mnemonic
= 1;
12859 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12862 case OPTION_MSYNTAX
:
12863 if (strcasecmp (arg
, "att") == 0)
12865 else if (strcasecmp (arg
, "intel") == 0)
12868 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12871 case OPTION_MINDEX_REG
:
12872 allow_index_reg
= 1;
12875 case OPTION_MNAKED_REG
:
12876 allow_naked_reg
= 1;
12879 case OPTION_MSSE2AVX
:
12883 case OPTION_MSSE_CHECK
:
12884 if (strcasecmp (arg
, "error") == 0)
12885 sse_check
= check_error
;
12886 else if (strcasecmp (arg
, "warning") == 0)
12887 sse_check
= check_warning
;
12888 else if (strcasecmp (arg
, "none") == 0)
12889 sse_check
= check_none
;
12891 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12894 case OPTION_MOPERAND_CHECK
:
12895 if (strcasecmp (arg
, "error") == 0)
12896 operand_check
= check_error
;
12897 else if (strcasecmp (arg
, "warning") == 0)
12898 operand_check
= check_warning
;
12899 else if (strcasecmp (arg
, "none") == 0)
12900 operand_check
= check_none
;
12902 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12905 case OPTION_MAVXSCALAR
:
12906 if (strcasecmp (arg
, "128") == 0)
12907 avxscalar
= vex128
;
12908 else if (strcasecmp (arg
, "256") == 0)
12909 avxscalar
= vex256
;
12911 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12914 case OPTION_MVEXWIG
:
12915 if (strcmp (arg
, "0") == 0)
12917 else if (strcmp (arg
, "1") == 0)
12920 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12923 case OPTION_MADD_BND_PREFIX
:
12924 add_bnd_prefix
= 1;
12927 case OPTION_MEVEXLIG
:
12928 if (strcmp (arg
, "128") == 0)
12929 evexlig
= evexl128
;
12930 else if (strcmp (arg
, "256") == 0)
12931 evexlig
= evexl256
;
12932 else if (strcmp (arg
, "512") == 0)
12933 evexlig
= evexl512
;
12935 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12938 case OPTION_MEVEXRCIG
:
12939 if (strcmp (arg
, "rne") == 0)
12941 else if (strcmp (arg
, "rd") == 0)
12943 else if (strcmp (arg
, "ru") == 0)
12945 else if (strcmp (arg
, "rz") == 0)
12948 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12951 case OPTION_MEVEXWIG
:
12952 if (strcmp (arg
, "0") == 0)
12954 else if (strcmp (arg
, "1") == 0)
12957 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12960 # if defined (TE_PE) || defined (TE_PEP)
12961 case OPTION_MBIG_OBJ
:
12966 case OPTION_MOMIT_LOCK_PREFIX
:
12967 if (strcasecmp (arg
, "yes") == 0)
12968 omit_lock_prefix
= 1;
12969 else if (strcasecmp (arg
, "no") == 0)
12970 omit_lock_prefix
= 0;
12972 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12975 case OPTION_MFENCE_AS_LOCK_ADD
:
12976 if (strcasecmp (arg
, "yes") == 0)
12978 else if (strcasecmp (arg
, "no") == 0)
12981 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12984 case OPTION_MLFENCE_AFTER_LOAD
:
12985 if (strcasecmp (arg
, "yes") == 0)
12986 lfence_after_load
= 1;
12987 else if (strcasecmp (arg
, "no") == 0)
12988 lfence_after_load
= 0;
12990 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
12993 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
12994 if (strcasecmp (arg
, "all") == 0)
12995 lfence_before_indirect_branch
= lfence_branch_all
;
12996 else if (strcasecmp (arg
, "memory") == 0)
12997 lfence_before_indirect_branch
= lfence_branch_memory
;
12998 else if (strcasecmp (arg
, "register") == 0)
12999 lfence_before_indirect_branch
= lfence_branch_register
;
13000 else if (strcasecmp (arg
, "none") == 0)
13001 lfence_before_indirect_branch
= lfence_branch_none
;
13003 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13007 case OPTION_MLFENCE_BEFORE_RET
:
13008 if (strcasecmp (arg
, "or") == 0)
13009 lfence_before_ret
= lfence_before_ret_or
;
13010 else if (strcasecmp (arg
, "not") == 0)
13011 lfence_before_ret
= lfence_before_ret_not
;
13012 else if (strcasecmp (arg
, "none") == 0)
13013 lfence_before_ret
= lfence_before_ret_none
;
13015 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13019 case OPTION_MRELAX_RELOCATIONS
:
13020 if (strcasecmp (arg
, "yes") == 0)
13021 generate_relax_relocations
= 1;
13022 else if (strcasecmp (arg
, "no") == 0)
13023 generate_relax_relocations
= 0;
13025 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13028 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13031 long int align
= strtoul (arg
, &end
, 0);
13036 align_branch_power
= 0;
13039 else if (align
>= 16)
13042 for (align_power
= 0;
13044 align
>>= 1, align_power
++)
13046 /* Limit alignment power to 31. */
13047 if (align
== 1 && align_power
< 32)
13049 align_branch_power
= align_power
;
13054 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13058 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13061 int align
= strtoul (arg
, &end
, 0);
13062 /* Some processors only support 5 prefixes. */
13063 if (*end
== '\0' && align
>= 0 && align
< 6)
13065 align_branch_prefix_size
= align
;
13068 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13073 case OPTION_MALIGN_BRANCH
:
13075 saved
= xstrdup (arg
);
13079 next
= strchr (type
, '+');
13082 if (strcasecmp (type
, "jcc") == 0)
13083 align_branch
|= align_branch_jcc_bit
;
13084 else if (strcasecmp (type
, "fused") == 0)
13085 align_branch
|= align_branch_fused_bit
;
13086 else if (strcasecmp (type
, "jmp") == 0)
13087 align_branch
|= align_branch_jmp_bit
;
13088 else if (strcasecmp (type
, "call") == 0)
13089 align_branch
|= align_branch_call_bit
;
13090 else if (strcasecmp (type
, "ret") == 0)
13091 align_branch
|= align_branch_ret_bit
;
13092 else if (strcasecmp (type
, "indirect") == 0)
13093 align_branch
|= align_branch_indirect_bit
;
13095 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13098 while (next
!= NULL
);
13102 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13103 align_branch_power
= 5;
13104 align_branch_prefix_size
= 5;
13105 align_branch
= (align_branch_jcc_bit
13106 | align_branch_fused_bit
13107 | align_branch_jmp_bit
);
13110 case OPTION_MAMD64
:
13114 case OPTION_MINTEL64
:
13122 /* Turn off -Os. */
13123 optimize_for_space
= 0;
13125 else if (*arg
== 's')
13127 optimize_for_space
= 1;
13128 /* Turn on all encoding optimizations. */
13129 optimize
= INT_MAX
;
13133 optimize
= atoi (arg
);
13134 /* Turn off -Os. */
13135 optimize_for_space
= 0;
13145 #define MESSAGE_TEMPLATE \
13149 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13150 int *left_p
, const char *name
, int len
)
13152 int size
= sizeof (MESSAGE_TEMPLATE
);
13153 int left
= *left_p
;
13155 /* Reserve 2 spaces for ", " or ",\0" */
13158 /* Check if there is any room. */
13166 p
= mempcpy (p
, name
, len
);
13170 /* Output the current message now and start a new one. */
13173 fprintf (stream
, "%s\n", message
);
13175 left
= size
- (start
- message
) - len
- 2;
13177 gas_assert (left
>= 0);
13179 p
= mempcpy (p
, name
, len
);
13187 show_arch (FILE *stream
, int ext
, int check
)
13189 static char message
[] = MESSAGE_TEMPLATE
;
13190 char *start
= message
+ 27;
13192 int size
= sizeof (MESSAGE_TEMPLATE
);
13199 left
= size
- (start
- message
);
13200 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13202 /* Should it be skipped? */
13203 if (cpu_arch
[j
].skip
)
13206 name
= cpu_arch
[j
].name
;
13207 len
= cpu_arch
[j
].len
;
13210 /* It is an extension. Skip if we aren't asked to show it. */
13221 /* It is an processor. Skip if we show only extension. */
13224 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13226 /* It is an impossible processor - skip. */
13230 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13233 /* Display disabled extensions. */
13235 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13237 name
= cpu_noarch
[j
].name
;
13238 len
= cpu_noarch
[j
].len
;
13239 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13244 fprintf (stream
, "%s\n", message
);
13248 md_show_usage (FILE *stream
)
13250 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13251 fprintf (stream
, _("\
13252 -Qy, -Qn ignored\n\
13253 -V print assembler version number\n\
13256 fprintf (stream
, _("\
13257 -n Do not optimize code alignment\n\
13258 -q quieten some warnings\n"));
13259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13260 fprintf (stream
, _("\
13263 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13264 || defined (TE_PE) || defined (TE_PEP))
13265 fprintf (stream
, _("\
13266 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13268 #ifdef SVR4_COMMENT_CHARS
13269 fprintf (stream
, _("\
13270 --divide do not treat `/' as a comment character\n"));
13272 fprintf (stream
, _("\
13273 --divide ignored\n"));
13275 fprintf (stream
, _("\
13276 -march=CPU[,+EXTENSION...]\n\
13277 generate code for CPU and EXTENSION, CPU is one of:\n"));
13278 show_arch (stream
, 0, 1);
13279 fprintf (stream
, _("\
13280 EXTENSION is combination of:\n"));
13281 show_arch (stream
, 1, 0);
13282 fprintf (stream
, _("\
13283 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13284 show_arch (stream
, 0, 0);
13285 fprintf (stream
, _("\
13286 -msse2avx encode SSE instructions with VEX prefix\n"));
13287 fprintf (stream
, _("\
13288 -msse-check=[none|error|warning] (default: warning)\n\
13289 check SSE instructions\n"));
13290 fprintf (stream
, _("\
13291 -moperand-check=[none|error|warning] (default: warning)\n\
13292 check operand combinations for validity\n"));
13293 fprintf (stream
, _("\
13294 -mavxscalar=[128|256] (default: 128)\n\
13295 encode scalar AVX instructions with specific vector\n\
13297 fprintf (stream
, _("\
13298 -mvexwig=[0|1] (default: 0)\n\
13299 encode VEX instructions with specific VEX.W value\n\
13300 for VEX.W bit ignored instructions\n"));
13301 fprintf (stream
, _("\
13302 -mevexlig=[128|256|512] (default: 128)\n\
13303 encode scalar EVEX instructions with specific vector\n\
13305 fprintf (stream
, _("\
13306 -mevexwig=[0|1] (default: 0)\n\
13307 encode EVEX instructions with specific EVEX.W value\n\
13308 for EVEX.W bit ignored instructions\n"));
13309 fprintf (stream
, _("\
13310 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13311 encode EVEX instructions with specific EVEX.RC value\n\
13312 for SAE-only ignored instructions\n"));
13313 fprintf (stream
, _("\
13314 -mmnemonic=[att|intel] "));
13315 if (SYSV386_COMPAT
)
13316 fprintf (stream
, _("(default: att)\n"));
13318 fprintf (stream
, _("(default: intel)\n"));
13319 fprintf (stream
, _("\
13320 use AT&T/Intel mnemonic\n"));
13321 fprintf (stream
, _("\
13322 -msyntax=[att|intel] (default: att)\n\
13323 use AT&T/Intel syntax\n"));
13324 fprintf (stream
, _("\
13325 -mindex-reg support pseudo index registers\n"));
13326 fprintf (stream
, _("\
13327 -mnaked-reg don't require `%%' prefix for registers\n"));
13328 fprintf (stream
, _("\
13329 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13331 fprintf (stream
, _("\
13332 -mshared disable branch optimization for shared code\n"));
13333 fprintf (stream
, _("\
13334 -mx86-used-note=[no|yes] "));
13335 if (DEFAULT_X86_USED_NOTE
)
13336 fprintf (stream
, _("(default: yes)\n"));
13338 fprintf (stream
, _("(default: no)\n"));
13339 fprintf (stream
, _("\
13340 generate x86 used ISA and feature properties\n"));
13342 #if defined (TE_PE) || defined (TE_PEP)
13343 fprintf (stream
, _("\
13344 -mbig-obj generate big object files\n"));
13346 fprintf (stream
, _("\
13347 -momit-lock-prefix=[no|yes] (default: no)\n\
13348 strip all lock prefixes\n"));
13349 fprintf (stream
, _("\
13350 -mfence-as-lock-add=[no|yes] (default: no)\n\
13351 encode lfence, mfence and sfence as\n\
13352 lock addl $0x0, (%%{re}sp)\n"));
13353 fprintf (stream
, _("\
13354 -mrelax-relocations=[no|yes] "));
13355 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13356 fprintf (stream
, _("(default: yes)\n"));
13358 fprintf (stream
, _("(default: no)\n"));
13359 fprintf (stream
, _("\
13360 generate relax relocations\n"));
13361 fprintf (stream
, _("\
13362 -malign-branch-boundary=NUM (default: 0)\n\
13363 align branches within NUM byte boundary\n"));
13364 fprintf (stream
, _("\
13365 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13366 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13368 specify types of branches to align\n"));
13369 fprintf (stream
, _("\
13370 -malign-branch-prefix-size=NUM (default: 5)\n\
13371 align branches with NUM prefixes per instruction\n"));
13372 fprintf (stream
, _("\
13373 -mbranches-within-32B-boundaries\n\
13374 align branches within 32 byte boundary\n"));
13375 fprintf (stream
, _("\
13376 -mlfence-after-load=[no|yes] (default: no)\n\
13377 generate lfence after load\n"));
13378 fprintf (stream
, _("\
13379 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13380 generate lfence before indirect near branch\n"));
13381 fprintf (stream
, _("\
13382 -mlfence-before-ret=[none|or|not] (default: none)\n\
13383 generate lfence before ret\n"));
13384 fprintf (stream
, _("\
13385 -mamd64 accept only AMD64 ISA [default]\n"));
13386 fprintf (stream
, _("\
13387 -mintel64 accept only Intel64 ISA\n"));
13390 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13391 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13392 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13394 /* Pick the target format to use. */
13397 i386_target_format (void)
13399 if (!strncmp (default_arch
, "x86_64", 6))
13401 update_code_flag (CODE_64BIT
, 1);
13402 if (default_arch
[6] == '\0')
13403 x86_elf_abi
= X86_64_ABI
;
13405 x86_elf_abi
= X86_64_X32_ABI
;
13407 else if (!strcmp (default_arch
, "i386"))
13408 update_code_flag (CODE_32BIT
, 1);
13409 else if (!strcmp (default_arch
, "iamcu"))
13411 update_code_flag (CODE_32BIT
, 1);
13412 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13414 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13415 cpu_arch_name
= "iamcu";
13416 cpu_sub_arch_name
= NULL
;
13417 cpu_arch_flags
= iamcu_flags
;
13418 cpu_arch_isa
= PROCESSOR_IAMCU
;
13419 cpu_arch_isa_flags
= iamcu_flags
;
13420 if (!cpu_arch_tune_set
)
13422 cpu_arch_tune
= cpu_arch_isa
;
13423 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13426 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13427 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13431 as_fatal (_("unknown architecture"));
13433 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13434 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13435 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13436 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13438 switch (OUTPUT_FLAVOR
)
13440 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13441 case bfd_target_aout_flavour
:
13442 return AOUT_TARGET_FORMAT
;
13444 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13445 # if defined (TE_PE) || defined (TE_PEP)
13446 case bfd_target_coff_flavour
:
13447 if (flag_code
== CODE_64BIT
)
13448 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13451 # elif defined (TE_GO32)
13452 case bfd_target_coff_flavour
:
13453 return "coff-go32";
13455 case bfd_target_coff_flavour
:
13456 return "coff-i386";
13459 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13460 case bfd_target_elf_flavour
:
13462 const char *format
;
13464 switch (x86_elf_abi
)
13467 format
= ELF_TARGET_FORMAT
;
13469 tls_get_addr
= "___tls_get_addr";
13473 use_rela_relocations
= 1;
13476 tls_get_addr
= "__tls_get_addr";
13478 format
= ELF_TARGET_FORMAT64
;
13480 case X86_64_X32_ABI
:
13481 use_rela_relocations
= 1;
13484 tls_get_addr
= "__tls_get_addr";
13486 disallow_64bit_reloc
= 1;
13487 format
= ELF_TARGET_FORMAT32
;
13490 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13492 if (x86_elf_abi
!= X86_64_ABI
)
13493 as_fatal (_("Intel L1OM is 64bit only"));
13494 return ELF_TARGET_L1OM_FORMAT
;
13496 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13498 if (x86_elf_abi
!= X86_64_ABI
)
13499 as_fatal (_("Intel K1OM is 64bit only"));
13500 return ELF_TARGET_K1OM_FORMAT
;
13502 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13504 if (x86_elf_abi
!= I386_ABI
)
13505 as_fatal (_("Intel MCU is 32bit only"));
13506 return ELF_TARGET_IAMCU_FORMAT
;
13512 #if defined (OBJ_MACH_O)
13513 case bfd_target_mach_o_flavour
:
13514 if (flag_code
== CODE_64BIT
)
13516 use_rela_relocations
= 1;
13518 return "mach-o-x86-64";
13521 return "mach-o-i386";
13529 #endif /* OBJ_MAYBE_ more than one */
13532 md_undefined_symbol (char *name
)
13534 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13535 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13536 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13537 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13541 if (symbol_find (name
))
13542 as_bad (_("GOT already in symbol table"));
13543 GOT_symbol
= symbol_new (name
, undefined_section
,
13544 (valueT
) 0, &zero_address_frag
);
13551 /* Round up a section size to the appropriate boundary. */
13554 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13556 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13557 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13559 /* For a.out, force the section size to be aligned. If we don't do
13560 this, BFD will align it for us, but it will not write out the
13561 final bytes of the section. This may be a bug in BFD, but it is
13562 easier to fix it here since that is how the other a.out targets
13566 align
= bfd_section_alignment (segment
);
13567 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13574 /* On the i386, PC-relative offsets are relative to the start of the
13575 next instruction. That is, the address of the offset, plus its
13576 size, since the offset is always the last part of the insn. */
13579 md_pcrel_from (fixS
*fixP
)
13581 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13587 s_bss (int ignore ATTRIBUTE_UNUSED
)
13591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13593 obj_elf_section_change_hook ();
13595 temp
= get_absolute_expression ();
13596 subseg_set (bss_section
, (subsegT
) temp
);
13597 demand_empty_rest_of_line ();
13602 /* Remember constant directive. */
13605 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13607 if (last_insn
.kind
!= last_insn_directive
13608 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13610 last_insn
.seg
= now_seg
;
13611 last_insn
.kind
= last_insn_directive
;
13612 last_insn
.name
= "constant directive";
13613 last_insn
.file
= as_where (&last_insn
.line
);
13614 if (lfence_before_ret
!= lfence_before_ret_none
)
13616 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13617 as_warn (_("constant directive skips -mlfence-before-ret "
13618 "and -mlfence-before-indirect-branch"));
13620 as_warn (_("constant directive skips -mlfence-before-ret"));
13622 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13623 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13628 i386_validate_fix (fixS
*fixp
)
13630 if (fixp
->fx_subsy
)
13632 if (fixp
->fx_subsy
== GOT_symbol
)
13634 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13639 if (fixp
->fx_tcbit2
)
13640 fixp
->fx_r_type
= (fixp
->fx_tcbit
13641 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13642 : BFD_RELOC_X86_64_GOTPCRELX
);
13645 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13650 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13652 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13654 fixp
->fx_subsy
= 0;
13657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13658 else if (!object_64bit
)
13660 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13661 && fixp
->fx_tcbit2
)
13662 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13668 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13671 bfd_reloc_code_real_type code
;
13673 switch (fixp
->fx_r_type
)
13675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13676 case BFD_RELOC_SIZE32
:
13677 case BFD_RELOC_SIZE64
:
13678 if (S_IS_DEFINED (fixp
->fx_addsy
)
13679 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13681 /* Resolve size relocation against local symbol to size of
13682 the symbol plus addend. */
13683 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13684 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13685 && !fits_in_unsigned_long (value
))
13686 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13687 _("symbol size computation overflow"));
13688 fixp
->fx_addsy
= NULL
;
13689 fixp
->fx_subsy
= NULL
;
13690 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13694 /* Fall through. */
13696 case BFD_RELOC_X86_64_PLT32
:
13697 case BFD_RELOC_X86_64_GOT32
:
13698 case BFD_RELOC_X86_64_GOTPCREL
:
13699 case BFD_RELOC_X86_64_GOTPCRELX
:
13700 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13701 case BFD_RELOC_386_PLT32
:
13702 case BFD_RELOC_386_GOT32
:
13703 case BFD_RELOC_386_GOT32X
:
13704 case BFD_RELOC_386_GOTOFF
:
13705 case BFD_RELOC_386_GOTPC
:
13706 case BFD_RELOC_386_TLS_GD
:
13707 case BFD_RELOC_386_TLS_LDM
:
13708 case BFD_RELOC_386_TLS_LDO_32
:
13709 case BFD_RELOC_386_TLS_IE_32
:
13710 case BFD_RELOC_386_TLS_IE
:
13711 case BFD_RELOC_386_TLS_GOTIE
:
13712 case BFD_RELOC_386_TLS_LE_32
:
13713 case BFD_RELOC_386_TLS_LE
:
13714 case BFD_RELOC_386_TLS_GOTDESC
:
13715 case BFD_RELOC_386_TLS_DESC_CALL
:
13716 case BFD_RELOC_X86_64_TLSGD
:
13717 case BFD_RELOC_X86_64_TLSLD
:
13718 case BFD_RELOC_X86_64_DTPOFF32
:
13719 case BFD_RELOC_X86_64_DTPOFF64
:
13720 case BFD_RELOC_X86_64_GOTTPOFF
:
13721 case BFD_RELOC_X86_64_TPOFF32
:
13722 case BFD_RELOC_X86_64_TPOFF64
:
13723 case BFD_RELOC_X86_64_GOTOFF64
:
13724 case BFD_RELOC_X86_64_GOTPC32
:
13725 case BFD_RELOC_X86_64_GOT64
:
13726 case BFD_RELOC_X86_64_GOTPCREL64
:
13727 case BFD_RELOC_X86_64_GOTPC64
:
13728 case BFD_RELOC_X86_64_GOTPLT64
:
13729 case BFD_RELOC_X86_64_PLTOFF64
:
13730 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13731 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13732 case BFD_RELOC_RVA
:
13733 case BFD_RELOC_VTABLE_ENTRY
:
13734 case BFD_RELOC_VTABLE_INHERIT
:
13736 case BFD_RELOC_32_SECREL
:
13738 code
= fixp
->fx_r_type
;
13740 case BFD_RELOC_X86_64_32S
:
13741 if (!fixp
->fx_pcrel
)
13743 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13744 code
= fixp
->fx_r_type
;
13747 /* Fall through. */
13749 if (fixp
->fx_pcrel
)
13751 switch (fixp
->fx_size
)
13754 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13755 _("can not do %d byte pc-relative relocation"),
13757 code
= BFD_RELOC_32_PCREL
;
13759 case 1: code
= BFD_RELOC_8_PCREL
; break;
13760 case 2: code
= BFD_RELOC_16_PCREL
; break;
13761 case 4: code
= BFD_RELOC_32_PCREL
; break;
13763 case 8: code
= BFD_RELOC_64_PCREL
; break;
13769 switch (fixp
->fx_size
)
13772 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13773 _("can not do %d byte relocation"),
13775 code
= BFD_RELOC_32
;
13777 case 1: code
= BFD_RELOC_8
; break;
13778 case 2: code
= BFD_RELOC_16
; break;
13779 case 4: code
= BFD_RELOC_32
; break;
13781 case 8: code
= BFD_RELOC_64
; break;
13788 if ((code
== BFD_RELOC_32
13789 || code
== BFD_RELOC_32_PCREL
13790 || code
== BFD_RELOC_X86_64_32S
)
13792 && fixp
->fx_addsy
== GOT_symbol
)
13795 code
= BFD_RELOC_386_GOTPC
;
13797 code
= BFD_RELOC_X86_64_GOTPC32
;
13799 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13801 && fixp
->fx_addsy
== GOT_symbol
)
13803 code
= BFD_RELOC_X86_64_GOTPC64
;
13806 rel
= XNEW (arelent
);
13807 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13808 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13810 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13812 if (!use_rela_relocations
)
13814 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13815 vtable entry to be used in the relocation's section offset. */
13816 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13817 rel
->address
= fixp
->fx_offset
;
13818 #if defined (OBJ_COFF) && defined (TE_PE)
13819 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13820 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13825 /* Use the rela in 64bit mode. */
13828 if (disallow_64bit_reloc
)
13831 case BFD_RELOC_X86_64_DTPOFF64
:
13832 case BFD_RELOC_X86_64_TPOFF64
:
13833 case BFD_RELOC_64_PCREL
:
13834 case BFD_RELOC_X86_64_GOTOFF64
:
13835 case BFD_RELOC_X86_64_GOT64
:
13836 case BFD_RELOC_X86_64_GOTPCREL64
:
13837 case BFD_RELOC_X86_64_GOTPC64
:
13838 case BFD_RELOC_X86_64_GOTPLT64
:
13839 case BFD_RELOC_X86_64_PLTOFF64
:
13840 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13841 _("cannot represent relocation type %s in x32 mode"),
13842 bfd_get_reloc_code_name (code
));
13848 if (!fixp
->fx_pcrel
)
13849 rel
->addend
= fixp
->fx_offset
;
13853 case BFD_RELOC_X86_64_PLT32
:
13854 case BFD_RELOC_X86_64_GOT32
:
13855 case BFD_RELOC_X86_64_GOTPCREL
:
13856 case BFD_RELOC_X86_64_GOTPCRELX
:
13857 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13858 case BFD_RELOC_X86_64_TLSGD
:
13859 case BFD_RELOC_X86_64_TLSLD
:
13860 case BFD_RELOC_X86_64_GOTTPOFF
:
13861 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13862 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13863 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13866 rel
->addend
= (section
->vma
13868 + fixp
->fx_addnumber
13869 + md_pcrel_from (fixp
));
13874 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13875 if (rel
->howto
== NULL
)
13877 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13878 _("cannot represent relocation type %s"),
13879 bfd_get_reloc_code_name (code
));
13880 /* Set howto to a garbage value so that we can keep going. */
13881 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13882 gas_assert (rel
->howto
!= NULL
);
13888 #include "tc-i386-intel.c"
13891 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13893 int saved_naked_reg
;
13894 char saved_register_dot
;
13896 saved_naked_reg
= allow_naked_reg
;
13897 allow_naked_reg
= 1;
13898 saved_register_dot
= register_chars
['.'];
13899 register_chars
['.'] = '.';
13900 allow_pseudo_reg
= 1;
13901 expression_and_evaluate (exp
);
13902 allow_pseudo_reg
= 0;
13903 register_chars
['.'] = saved_register_dot
;
13904 allow_naked_reg
= saved_naked_reg
;
13906 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13908 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13910 exp
->X_op
= O_constant
;
13911 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13912 .dw2_regnum
[flag_code
>> 1];
13915 exp
->X_op
= O_illegal
;
13920 tc_x86_frame_initial_instructions (void)
13922 static unsigned int sp_regno
[2];
13924 if (!sp_regno
[flag_code
>> 1])
13926 char *saved_input
= input_line_pointer
;
13927 char sp
[][4] = {"esp", "rsp"};
13930 input_line_pointer
= sp
[flag_code
>> 1];
13931 tc_x86_parse_to_dw2regnum (&exp
);
13932 gas_assert (exp
.X_op
== O_constant
);
13933 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13934 input_line_pointer
= saved_input
;
13937 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13938 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13942 x86_dwarf2_addr_size (void)
13944 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13945 if (x86_elf_abi
== X86_64_X32_ABI
)
13948 return bfd_arch_bits_per_address (stdoutput
) / 8;
13952 i386_elf_section_type (const char *str
, size_t len
)
13954 if (flag_code
== CODE_64BIT
13955 && len
== sizeof ("unwind") - 1
13956 && strncmp (str
, "unwind", 6) == 0)
13957 return SHT_X86_64_UNWIND
;
13964 i386_solaris_fix_up_eh_frame (segT sec
)
13966 if (flag_code
== CODE_64BIT
)
13967 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13973 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13977 exp
.X_op
= O_secrel
;
13978 exp
.X_add_symbol
= symbol
;
13979 exp
.X_add_number
= 0;
13980 emit_expr (&exp
, size
);
13984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13985 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13988 x86_64_section_letter (int letter
, const char **ptr_msg
)
13990 if (flag_code
== CODE_64BIT
)
13993 return SHF_X86_64_LARGE
;
13995 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13998 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14003 x86_64_section_word (char *str
, size_t len
)
14005 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14006 return SHF_X86_64_LARGE
;
14012 handle_large_common (int small ATTRIBUTE_UNUSED
)
14014 if (flag_code
!= CODE_64BIT
)
14016 s_comm_internal (0, elf_common_parse
);
14017 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14021 static segT lbss_section
;
14022 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14023 asection
*saved_bss_section
= bss_section
;
14025 if (lbss_section
== NULL
)
14027 flagword applicable
;
14028 segT seg
= now_seg
;
14029 subsegT subseg
= now_subseg
;
14031 /* The .lbss section is for local .largecomm symbols. */
14032 lbss_section
= subseg_new (".lbss", 0);
14033 applicable
= bfd_applicable_section_flags (stdoutput
);
14034 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14035 seg_info (lbss_section
)->bss
= 1;
14037 subseg_set (seg
, subseg
);
14040 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14041 bss_section
= lbss_section
;
14043 s_comm_internal (0, elf_common_parse
);
14045 elf_com_section_ptr
= saved_com_section_ptr
;
14046 bss_section
= saved_bss_section
;
14049 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */