1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
268 unsupported_with_intel_mnemonic
,
271 invalid_vsib_address
,
272 invalid_vector_register_set
,
273 unsupported_vector_index_register
,
274 unsupported_broadcast
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry
*base_reg
;
319 const reg_entry
*index_reg
;
320 unsigned int log2_scale_factor
;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry
*seg
[2];
326 /* Copied first memory operand string, for re-checking. */
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Prefer load or store in encoding. */
357 dir_encoding_default
= 0,
362 /* Prefer 8bit or 32bit displacement in encoding. */
365 disp_encoding_default
= 0,
370 /* Prefer the REX byte in encoding. */
371 bfd_boolean rex_encoding
;
373 /* Disable instruction size optimization. */
374 bfd_boolean no_optimize
;
376 /* How to encode vector instructions. */
379 vex_encoding_default
= 0,
386 const char *rep_prefix
;
389 const char *hle_prefix
;
391 /* Have BND prefix. */
392 const char *bnd_prefix
;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix
;
398 enum i386_error error
;
401 typedef struct _i386_insn i386_insn
;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable
[] =
414 { rne
, STRING_COMMA_LEN ("rn-sae") },
415 { rd
, STRING_COMMA_LEN ("rd-sae") },
416 { ru
, STRING_COMMA_LEN ("ru-sae") },
417 { rz
, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly
, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars
[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars
= "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars
= "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars
[] = "#/";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS
[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars
[256];
475 static char register_chars
[256];
476 static char operand_chars
[256];
477 static char identifier_chars
[256];
478 static char digit_chars
[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack
[32];
496 static char *save_stack_p
;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates
*current_templates
;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
510 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
512 /* Current operand we are working on. */
513 static int this_operand
= -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code
;
524 static unsigned int object_64bit
;
525 static unsigned int disallow_64bit_reloc
;
526 static int use_rela_relocations
= 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj
= 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared
= 0;
553 /* 1 for intel syntax,
555 static int intel_syntax
= 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic
= !SYSV386_COMPAT
;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg
= 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg
= 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix
= 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg
= 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix
= 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence
= 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
592 static enum check_kind
598 sse_check
, operand_check
= check_warning
;
601 1. Clear the REX_W bit with register operand if possible.
602 2. Above plus use 128bit vector instruction to clear the full vector
605 static int optimize
= 0;
608 1. Clear the REX_W bit with register operand if possible.
609 2. Above plus use 128bit vector instruction to clear the full vector
611 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
614 static int optimize_for_space
= 0;
616 /* Register prefix used for error message. */
617 static const char *register_prefix
= "%";
619 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
620 leave, push, and pop instructions so that gcc has the same stack
621 frame as in 32 bit mode. */
622 static char stackop_size
= '\0';
624 /* Non-zero to optimize code alignment. */
625 int optimize_align_code
= 1;
627 /* Non-zero to quieten some warnings. */
628 static int quiet_warnings
= 0;
631 static const char *cpu_arch_name
= NULL
;
632 static char *cpu_sub_arch_name
= NULL
;
634 /* CPU feature flags. */
635 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
637 /* If we have selected a cpu we are generating instructions for. */
638 static int cpu_arch_tune_set
= 0;
640 /* Cpu we are generating instructions for. */
641 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
643 /* CPU feature flags of cpu we are generating instructions for. */
644 static i386_cpu_flags cpu_arch_tune_flags
;
646 /* CPU instruction set architecture used. */
647 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
649 /* CPU feature flags of instruction set architecture used. */
650 i386_cpu_flags cpu_arch_isa_flags
;
652 /* If set, conditional jumps are not automatically promoted to handle
653 larger than a byte offset. */
654 static unsigned int no_cond_jump_promotion
= 0;
656 /* Encode SSE instructions with VEX prefix. */
657 static unsigned int sse2avx
;
659 /* Encode scalar AVX instructions with specific vector length. */
666 /* Encode scalar EVEX LIG instructions with specific vector length. */
674 /* Encode EVEX WIG instructions with specific evex.w. */
681 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
682 static enum rc_type evexrcig
= rne
;
684 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
685 static symbolS
*GOT_symbol
;
687 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
688 unsigned int x86_dwarf2_return_column
;
690 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
691 int x86_cie_data_alignment
;
693 /* Interface to relax_segment.
694 There are 3 major relax states for 386 jump insns because the
695 different types of jumps add different sizes to frags when we're
696 figuring out what sort of jump to choose to reach a given label. */
699 #define UNCOND_JUMP 0
701 #define COND_JUMP86 2
706 #define SMALL16 (SMALL | CODE16)
708 #define BIG16 (BIG | CODE16)
712 #define INLINE __inline__
718 #define ENCODE_RELAX_STATE(type, size) \
719 ((relax_substateT) (((type) << 2) | (size)))
720 #define TYPE_FROM_RELAX_STATE(s) \
722 #define DISP_SIZE_FROM_RELAX_STATE(s) \
723 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
725 /* This table is used by relax_frag to promote short jumps to long
726 ones where necessary. SMALL (short) jumps may be promoted to BIG
727 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
728 don't allow a short jump in a 32 bit code segment to be promoted to
729 a 16 bit offset jump because it's slower (requires data size
730 prefix), and doesn't work, unless the destination is in the bottom
731 64k of the code segment (The top 16 bits of eip are zeroed). */
733 const relax_typeS md_relax_table
[] =
736 1) most positive reach of this state,
737 2) most negative reach of this state,
738 3) how many bytes this mode will have in the variable part of the frag
739 4) which index into the table to try if we can't fit into this one. */
741 /* UNCOND_JUMP states. */
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
744 /* dword jmp adds 4 bytes to frag:
745 0 extra opcode bytes, 4 displacement bytes. */
747 /* word jmp adds 2 byte2 to frag:
748 0 extra opcode bytes, 2 displacement bytes. */
751 /* COND_JUMP states. */
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
754 /* dword conditionals adds 5 bytes to frag:
755 1 extra opcode byte, 4 displacement bytes. */
757 /* word conditionals add 3 bytes to frag:
758 1 extra opcode byte, 2 displacement bytes. */
761 /* COND_JUMP86 states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
764 /* dword conditionals adds 5 bytes to frag:
765 1 extra opcode byte, 4 displacement bytes. */
767 /* word conditionals add 4 bytes to frag:
768 1 displacement byte and a 3 byte long branch insn. */
772 static const arch_entry cpu_arch
[] =
774 /* Do not replace the first two entries - i386_target_format()
775 relies on them being there in this order. */
776 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
777 CPU_GENERIC32_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
779 CPU_GENERIC64_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
786 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
788 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
790 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
792 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
794 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
796 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
797 CPU_PENTIUMPRO_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
802 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
804 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
806 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
807 CPU_NOCONA_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
812 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 1 },
814 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
815 CPU_CORE2_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
817 CPU_COREI7_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
820 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
822 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
823 CPU_IAMCU_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
828 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
829 CPU_ATHLON_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
836 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
837 CPU_AMDFAM10_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
839 CPU_BDVER1_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
841 CPU_BDVER2_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
843 CPU_BDVER3_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
845 CPU_BDVER4_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
847 CPU_ZNVER1_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
849 CPU_ZNVER2_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
851 CPU_BTVER1_FLAGS
, 0 },
852 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
853 CPU_BTVER2_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
870 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
871 CPU_SSSE3_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_1_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
877 CPU_SSE4_2_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512F_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512CD_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512ER_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512PF_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512DQ_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512BW_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
895 CPU_AVX512VL_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
899 CPU_VMFUNC_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVE_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEOPT_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVEC_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
909 CPU_XSAVES_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
915 CPU_PCLMUL_FLAGS
, 1 },
916 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
917 CPU_FSGSBASE_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
919 CPU_RDRND_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
933 CPU_MOVBE_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
939 CPU_LZCNT_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
945 CPU_INVPCID_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
947 CPU_CLFLUSH_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
951 CPU_SYSCALL_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
953 CPU_RDTSCP_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOW_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
957 CPU_3DNOWA_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
959 CPU_PADLOCK_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
965 CPU_SSE4A_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
975 CPU_RDSEED_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
977 CPU_PRFCHW_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
985 CPU_CLFLUSHOPT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
987 CPU_PREFETCHWT1_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
992 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512IFMA_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512VBMI_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4FMAPS_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VBMI2_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_VNNI_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512_BITALG_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1009 CPU_CLZERO_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1011 CPU_MWAITX_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1013 CPU_OSPKE_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1015 CPU_RDPID_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1017 CPU_PTWRITE_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1021 CPU_SHSTK_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1023 CPU_GFNI_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1025 CPU_VAES_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1027 CPU_VPCLMULQDQ_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1029 CPU_WBNOINVD_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1031 CPU_PCONFIG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1033 CPU_WAITPKG_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1035 CPU_CLDEMOTE_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIRI_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1039 CPU_MOVDIR64B_FLAGS
, 0 },
1042 static const noarch_entry cpu_noarch
[] =
1044 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1045 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1046 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1047 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1048 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1050 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1052 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1055 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1071 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1072 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1073 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1074 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1075 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1076 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1080 /* Like s_lcomm_internal in gas/read.c but the alignment string
1081 is allowed to be optional. */
1084 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1091 && *input_line_pointer
== ',')
1093 align
= parse_align (needs_align
- 1);
1095 if (align
== (addressT
) -1)
1110 bss_alloc (symbolP
, size
, align
);
1115 pe_lcomm (int needs_align
)
1117 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1121 const pseudo_typeS md_pseudo_table
[] =
1123 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1124 {"align", s_align_bytes
, 0},
1126 {"align", s_align_ptwo
, 0},
1128 {"arch", set_cpu_arch
, 0},
1132 {"lcomm", pe_lcomm
, 1},
1134 {"ffloat", float_cons
, 'f'},
1135 {"dfloat", float_cons
, 'd'},
1136 {"tfloat", float_cons
, 'x'},
1138 {"slong", signed_cons
, 4},
1139 {"noopt", s_ignore
, 0},
1140 {"optim", s_ignore
, 0},
1141 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1142 {"code16", set_code_flag
, CODE_16BIT
},
1143 {"code32", set_code_flag
, CODE_32BIT
},
1145 {"code64", set_code_flag
, CODE_64BIT
},
1147 {"intel_syntax", set_intel_syntax
, 1},
1148 {"att_syntax", set_intel_syntax
, 0},
1149 {"intel_mnemonic", set_intel_mnemonic
, 1},
1150 {"att_mnemonic", set_intel_mnemonic
, 0},
1151 {"allow_index_reg", set_allow_index_reg
, 1},
1152 {"disallow_index_reg", set_allow_index_reg
, 0},
1153 {"sse_check", set_check
, 0},
1154 {"operand_check", set_check
, 1},
1155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1156 {"largecomm", handle_large_common
, 0},
1158 {"file", dwarf2_directive_file
, 0},
1159 {"loc", dwarf2_directive_loc
, 0},
1160 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1163 {"secrel32", pe_directive_secrel
, 0},
1168 /* For interface with expression (). */
1169 extern char *input_line_pointer
;
1171 /* Hash table for instruction mnemonic lookup. */
1172 static struct hash_control
*op_hash
;
1174 /* Hash table for register lookup. */
1175 static struct hash_control
*reg_hash
;
1177 /* Various efficient no-op patterns for aligning code labels.
1178 Note: Don't try to assemble the instructions in the comments.
1179 0L and 0w are not legal. */
1180 static const unsigned char f32_1
[] =
1182 static const unsigned char f32_2
[] =
1183 {0x66,0x90}; /* xchg %ax,%ax */
1184 static const unsigned char f32_3
[] =
1185 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1186 static const unsigned char f32_4
[] =
1187 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1188 static const unsigned char f32_6
[] =
1189 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1190 static const unsigned char f32_7
[] =
1191 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1192 static const unsigned char f16_3
[] =
1193 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1194 static const unsigned char f16_4
[] =
1195 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1196 static const unsigned char jump_disp8
[] =
1197 {0xeb}; /* jmp disp8 */
1198 static const unsigned char jump32_disp32
[] =
1199 {0xe9}; /* jmp disp32 */
1200 static const unsigned char jump16_disp32
[] =
1201 {0x66,0xe9}; /* jmp disp32 */
1202 /* 32-bit NOPs patterns. */
1203 static const unsigned char *const f32_patt
[] = {
1204 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1206 /* 16-bit NOPs patterns. */
1207 static const unsigned char *const f16_patt
[] = {
1208 f32_1
, f32_2
, f16_3
, f16_4
1210 /* nopl (%[re]ax) */
1211 static const unsigned char alt_3
[] =
1213 /* nopl 0(%[re]ax) */
1214 static const unsigned char alt_4
[] =
1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_5
[] =
1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_6
[] =
1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
1223 static const unsigned char alt_7
[] =
1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_8
[] =
1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_9
[] =
1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1232 static const unsigned char alt_10
[] =
1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 /* data16 nopw %cs:0L(%eax,%eax,1) */
1235 static const unsigned char alt_11
[] =
1236 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* 32-bit and 64-bit NOPs patterns. */
1238 static const unsigned char *const alt_patt
[] = {
1239 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1240 alt_9
, alt_10
, alt_11
1243 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1244 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1247 i386_output_nops (char *where
, const unsigned char *const *patt
,
1248 int count
, int max_single_nop_size
)
1251 /* Place the longer NOP first. */
1254 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1256 /* Use the smaller one if the requsted one isn't available. */
1259 max_single_nop_size
--;
1260 nops
= patt
[max_single_nop_size
- 1];
1263 last
= count
% max_single_nop_size
;
1266 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1267 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1271 nops
= patt
[last
- 1];
1274 /* Use the smaller one plus one-byte NOP if the needed one
1277 nops
= patt
[last
- 1];
1278 memcpy (where
+ offset
, nops
, last
);
1279 where
[offset
+ last
] = *patt
[0];
1282 memcpy (where
+ offset
, nops
, last
);
1287 fits_in_imm7 (offsetT num
)
1289 return (num
& 0x7f) == num
;
1293 fits_in_imm31 (offsetT num
)
1295 return (num
& 0x7fffffff) == num
;
1298 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1299 single NOP instruction LIMIT. */
1302 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1304 const unsigned char *const *patt
= NULL
;
1305 int max_single_nop_size
;
1306 /* Maximum number of NOPs before switching to jump over NOPs. */
1307 int max_number_of_nops
;
1309 switch (fragP
->fr_type
)
1318 /* We need to decide which NOP sequence to use for 32bit and
1319 64bit. When -mtune= is used:
1321 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1322 PROCESSOR_GENERIC32, f32_patt will be used.
1323 2. For the rest, alt_patt will be used.
1325 When -mtune= isn't used, alt_patt will be used if
1326 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1329 When -march= or .arch is used, we can't use anything beyond
1330 cpu_arch_isa_flags. */
1332 if (flag_code
== CODE_16BIT
)
1335 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1336 /* Limit number of NOPs to 2 in 16-bit mode. */
1337 max_number_of_nops
= 2;
1341 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1343 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1344 switch (cpu_arch_tune
)
1346 case PROCESSOR_UNKNOWN
:
1347 /* We use cpu_arch_isa_flags to check if we SHOULD
1348 optimize with nops. */
1349 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1354 case PROCESSOR_PENTIUM4
:
1355 case PROCESSOR_NOCONA
:
1356 case PROCESSOR_CORE
:
1357 case PROCESSOR_CORE2
:
1358 case PROCESSOR_COREI7
:
1359 case PROCESSOR_L1OM
:
1360 case PROCESSOR_K1OM
:
1361 case PROCESSOR_GENERIC64
:
1363 case PROCESSOR_ATHLON
:
1365 case PROCESSOR_AMDFAM10
:
1367 case PROCESSOR_ZNVER
:
1371 case PROCESSOR_I386
:
1372 case PROCESSOR_I486
:
1373 case PROCESSOR_PENTIUM
:
1374 case PROCESSOR_PENTIUMPRO
:
1375 case PROCESSOR_IAMCU
:
1376 case PROCESSOR_GENERIC32
:
1383 switch (fragP
->tc_frag_data
.tune
)
1385 case PROCESSOR_UNKNOWN
:
1386 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1387 PROCESSOR_UNKNOWN. */
1391 case PROCESSOR_I386
:
1392 case PROCESSOR_I486
:
1393 case PROCESSOR_PENTIUM
:
1394 case PROCESSOR_IAMCU
:
1396 case PROCESSOR_ATHLON
:
1398 case PROCESSOR_AMDFAM10
:
1400 case PROCESSOR_ZNVER
:
1402 case PROCESSOR_GENERIC32
:
1403 /* We use cpu_arch_isa_flags to check if we CAN optimize
1405 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1410 case PROCESSOR_PENTIUMPRO
:
1411 case PROCESSOR_PENTIUM4
:
1412 case PROCESSOR_NOCONA
:
1413 case PROCESSOR_CORE
:
1414 case PROCESSOR_CORE2
:
1415 case PROCESSOR_COREI7
:
1416 case PROCESSOR_L1OM
:
1417 case PROCESSOR_K1OM
:
1418 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1423 case PROCESSOR_GENERIC64
:
1429 if (patt
== f32_patt
)
1431 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1432 /* Limit number of NOPs to 2 for older processors. */
1433 max_number_of_nops
= 2;
1437 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1438 /* Limit number of NOPs to 7 for newer processors. */
1439 max_number_of_nops
= 7;
1444 limit
= max_single_nop_size
;
1446 if (fragP
->fr_type
== rs_fill_nop
)
1448 /* Output NOPs for .nop directive. */
1449 if (limit
> max_single_nop_size
)
1451 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1452 _("invalid single nop size: %d "
1453 "(expect within [0, %d])"),
1454 limit
, max_single_nop_size
);
1459 fragP
->fr_var
= count
;
1461 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1463 /* Generate jump over NOPs. */
1464 offsetT disp
= count
- 2;
1465 if (fits_in_imm7 (disp
))
1467 /* Use "jmp disp8" if possible. */
1469 where
[0] = jump_disp8
[0];
1475 unsigned int size_of_jump
;
1477 if (flag_code
== CODE_16BIT
)
1479 where
[0] = jump16_disp32
[0];
1480 where
[1] = jump16_disp32
[1];
1485 where
[0] = jump32_disp32
[0];
1489 count
-= size_of_jump
+ 4;
1490 if (!fits_in_imm31 (count
))
1492 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1493 _("jump over nop padding out of range"));
1497 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1498 where
+= size_of_jump
+ 4;
1502 /* Generate multiple NOPs. */
1503 i386_output_nops (where
, patt
, count
, limit
);
1507 operand_type_all_zero (const union i386_operand_type
*x
)
1509 switch (ARRAY_SIZE(x
->array
))
1520 return !x
->array
[0];
1527 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1529 switch (ARRAY_SIZE(x
->array
))
1547 operand_type_equal (const union i386_operand_type
*x
,
1548 const union i386_operand_type
*y
)
1550 switch (ARRAY_SIZE(x
->array
))
1553 if (x
->array
[2] != y
->array
[2])
1557 if (x
->array
[1] != y
->array
[1])
1561 return x
->array
[0] == y
->array
[0];
1569 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1571 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 cpu_flags_equal (const union i386_cpu_flags
*x
,
1594 const union i386_cpu_flags
*y
)
1596 switch (ARRAY_SIZE(x
->array
))
1599 if (x
->array
[3] != y
->array
[3])
1603 if (x
->array
[2] != y
->array
[2])
1607 if (x
->array
[1] != y
->array
[1])
1611 return x
->array
[0] == y
->array
[0];
1619 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1621 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1622 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1625 static INLINE i386_cpu_flags
1626 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1628 switch (ARRAY_SIZE (x
.array
))
1631 x
.array
[3] &= y
.array
[3];
1634 x
.array
[2] &= y
.array
[2];
1637 x
.array
[1] &= y
.array
[1];
1640 x
.array
[0] &= y
.array
[0];
1648 static INLINE i386_cpu_flags
1649 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1651 switch (ARRAY_SIZE (x
.array
))
1654 x
.array
[3] |= y
.array
[3];
1657 x
.array
[2] |= y
.array
[2];
1660 x
.array
[1] |= y
.array
[1];
1663 x
.array
[0] |= y
.array
[0];
1671 static INLINE i386_cpu_flags
1672 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1674 switch (ARRAY_SIZE (x
.array
))
1677 x
.array
[3] &= ~y
.array
[3];
1680 x
.array
[2] &= ~y
.array
[2];
1683 x
.array
[1] &= ~y
.array
[1];
1686 x
.array
[0] &= ~y
.array
[0];
1694 #define CPU_FLAGS_ARCH_MATCH 0x1
1695 #define CPU_FLAGS_64BIT_MATCH 0x2
1697 #define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1700 /* Return CPU flags match bits. */
1703 cpu_flags_match (const insn_template
*t
)
1705 i386_cpu_flags x
= t
->cpu_flags
;
1706 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1708 x
.bitfield
.cpu64
= 0;
1709 x
.bitfield
.cpuno64
= 0;
1711 if (cpu_flags_all_zero (&x
))
1713 /* This instruction is available on all archs. */
1714 match
|= CPU_FLAGS_ARCH_MATCH
;
1718 /* This instruction is available only on some archs. */
1719 i386_cpu_flags cpu
= cpu_arch_flags
;
1721 /* AVX512VL is no standalone feature - match it and then strip it. */
1722 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1724 x
.bitfield
.cpuavx512vl
= 0;
1726 cpu
= cpu_flags_and (x
, cpu
);
1727 if (!cpu_flags_all_zero (&cpu
))
1729 if (x
.bitfield
.cpuavx
)
1731 /* We need to check a few extra flags with AVX. */
1732 if (cpu
.bitfield
.cpuavx
1733 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1734 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1735 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1736 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1737 match
|= CPU_FLAGS_ARCH_MATCH
;
1739 else if (x
.bitfield
.cpuavx512f
)
1741 /* We need to check a few extra flags with AVX512F. */
1742 if (cpu
.bitfield
.cpuavx512f
1743 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1744 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1745 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1746 match
|= CPU_FLAGS_ARCH_MATCH
;
1749 match
|= CPU_FLAGS_ARCH_MATCH
;
1755 static INLINE i386_operand_type
1756 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1758 switch (ARRAY_SIZE (x
.array
))
1761 x
.array
[2] &= y
.array
[2];
1764 x
.array
[1] &= y
.array
[1];
1767 x
.array
[0] &= y
.array
[0];
1775 static INLINE i386_operand_type
1776 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1778 switch (ARRAY_SIZE (x
.array
))
1781 x
.array
[2] &= ~y
.array
[2];
1784 x
.array
[1] &= ~y
.array
[1];
1787 x
.array
[0] &= ~y
.array
[0];
1795 static INLINE i386_operand_type
1796 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1798 switch (ARRAY_SIZE (x
.array
))
1801 x
.array
[2] |= y
.array
[2];
1804 x
.array
[1] |= y
.array
[1];
1807 x
.array
[0] |= y
.array
[0];
1815 static INLINE i386_operand_type
1816 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1818 switch (ARRAY_SIZE (x
.array
))
1821 x
.array
[2] ^= y
.array
[2];
1824 x
.array
[1] ^= y
.array
[1];
1827 x
.array
[0] ^= y
.array
[0];
1835 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1836 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1837 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1838 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1839 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1840 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1841 static const i386_operand_type anydisp
1842 = OPERAND_TYPE_ANYDISP
;
1843 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1844 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1845 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1846 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1847 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1848 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1849 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1850 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1851 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1852 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1853 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1854 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1865 operand_type_check (i386_operand_type t
, enum operand_type c
)
1870 return t
.bitfield
.reg
;
1873 return (t
.bitfield
.imm8
1877 || t
.bitfield
.imm32s
1878 || t
.bitfield
.imm64
);
1881 return (t
.bitfield
.disp8
1882 || t
.bitfield
.disp16
1883 || t
.bitfield
.disp32
1884 || t
.bitfield
.disp32s
1885 || t
.bitfield
.disp64
);
1888 return (t
.bitfield
.disp8
1889 || t
.bitfield
.disp16
1890 || t
.bitfield
.disp32
1891 || t
.bitfield
.disp32s
1892 || t
.bitfield
.disp64
1893 || t
.bitfield
.baseindex
);
1902 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1903 between operand GIVEN and opeand WANTED for instruction template T. */
1906 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1909 return !((i
.types
[given
].bitfield
.byte
1910 && !t
->operand_types
[wanted
].bitfield
.byte
)
1911 || (i
.types
[given
].bitfield
.word
1912 && !t
->operand_types
[wanted
].bitfield
.word
)
1913 || (i
.types
[given
].bitfield
.dword
1914 && !t
->operand_types
[wanted
].bitfield
.dword
)
1915 || (i
.types
[given
].bitfield
.qword
1916 && !t
->operand_types
[wanted
].bitfield
.qword
)
1917 || (i
.types
[given
].bitfield
.tbyte
1918 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1921 /* Return 1 if there is no conflict in SIMD register between operand
1922 GIVEN and opeand WANTED for instruction template T. */
1925 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1928 return !((i
.types
[given
].bitfield
.xmmword
1929 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1930 || (i
.types
[given
].bitfield
.ymmword
1931 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1932 || (i
.types
[given
].bitfield
.zmmword
1933 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1936 /* Return 1 if there is no conflict in any size between operand GIVEN
1937 and opeand WANTED for instruction template T. */
1940 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1943 return (match_operand_size (t
, wanted
, given
)
1944 && !((i
.types
[given
].bitfield
.unspecified
1946 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1947 || (i
.types
[given
].bitfield
.fword
1948 && !t
->operand_types
[wanted
].bitfield
.fword
)
1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1953 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1954 && !t
->opcode_modifier
.broadcast
1955 && (t
->operand_types
[wanted
].bitfield
.byte
1956 || t
->operand_types
[wanted
].bitfield
.word
1957 || t
->operand_types
[wanted
].bitfield
.dword
1958 || t
->operand_types
[wanted
].bitfield
.qword
))
1959 ? (i
.types
[given
].bitfield
.xmmword
1960 || i
.types
[given
].bitfield
.ymmword
1961 || i
.types
[given
].bitfield
.zmmword
)
1962 : !match_simd_size(t
, wanted
, given
))));
1965 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1966 operands for instruction template T, and it has MATCH_REVERSE set if there
1967 is no size conflict on any operands for the template with operands reversed
1968 (and the template allows for reversing in the first place). */
1970 #define MATCH_STRAIGHT 1
1971 #define MATCH_REVERSE 2
1973 static INLINE
unsigned int
1974 operand_size_match (const insn_template
*t
)
1976 unsigned int j
, match
= MATCH_STRAIGHT
;
1978 /* Don't check jump instructions. */
1979 if (t
->opcode_modifier
.jump
1980 || t
->opcode_modifier
.jumpbyte
1981 || t
->opcode_modifier
.jumpdword
1982 || t
->opcode_modifier
.jumpintersegment
)
1985 /* Check memory and accumulator operand size. */
1986 for (j
= 0; j
< i
.operands
; j
++)
1988 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1989 && t
->operand_types
[j
].bitfield
.anysize
)
1992 if (t
->operand_types
[j
].bitfield
.reg
1993 && !match_operand_size (t
, j
, j
))
1999 if (t
->operand_types
[j
].bitfield
.regsimd
2000 && !match_simd_size (t
, j
, j
))
2006 if (t
->operand_types
[j
].bitfield
.acc
2007 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2013 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
, j
))
2020 if (!t
->opcode_modifier
.d
)
2024 i
.error
= operand_size_mismatch
;
2028 /* Check reverse. */
2029 gas_assert (i
.operands
== 2);
2031 for (j
= 0; j
< 2; j
++)
2033 if ((t
->operand_types
[j
].bitfield
.reg
2034 || t
->operand_types
[j
].bitfield
.acc
)
2035 && !match_operand_size (t
, j
, !j
))
2038 if (i
.types
[!j
].bitfield
.mem
2039 && !match_mem_size (t
, j
, !j
))
2043 return match
| MATCH_REVERSE
;
2047 operand_type_match (i386_operand_type overlap
,
2048 i386_operand_type given
)
2050 i386_operand_type temp
= overlap
;
2052 temp
.bitfield
.jumpabsolute
= 0;
2053 temp
.bitfield
.unspecified
= 0;
2054 temp
.bitfield
.byte
= 0;
2055 temp
.bitfield
.word
= 0;
2056 temp
.bitfield
.dword
= 0;
2057 temp
.bitfield
.fword
= 0;
2058 temp
.bitfield
.qword
= 0;
2059 temp
.bitfield
.tbyte
= 0;
2060 temp
.bitfield
.xmmword
= 0;
2061 temp
.bitfield
.ymmword
= 0;
2062 temp
.bitfield
.zmmword
= 0;
2063 if (operand_type_all_zero (&temp
))
2066 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2067 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2071 i
.error
= operand_type_mismatch
;
2075 /* If given types g0 and g1 are registers they must be of the same type
2076 unless the expected operand type register overlap is null.
2077 Memory operand size of certain SIMD instructions is also being checked
2081 operand_type_register_match (i386_operand_type g0
,
2082 i386_operand_type t0
,
2083 i386_operand_type g1
,
2084 i386_operand_type t1
)
2086 if (!g0
.bitfield
.reg
2087 && !g0
.bitfield
.regsimd
2088 && (!operand_type_check (g0
, anymem
)
2089 || g0
.bitfield
.unspecified
2090 || !t0
.bitfield
.regsimd
))
2093 if (!g1
.bitfield
.reg
2094 && !g1
.bitfield
.regsimd
2095 && (!operand_type_check (g1
, anymem
)
2096 || g1
.bitfield
.unspecified
2097 || !t1
.bitfield
.regsimd
))
2100 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2101 && g0
.bitfield
.word
== g1
.bitfield
.word
2102 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2103 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2104 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2105 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2106 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2109 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2110 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2111 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2112 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2113 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2114 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2115 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2118 i
.error
= register_type_mismatch
;
2123 static INLINE
unsigned int
2124 register_number (const reg_entry
*r
)
2126 unsigned int nr
= r
->reg_num
;
2128 if (r
->reg_flags
& RegRex
)
2131 if (r
->reg_flags
& RegVRex
)
2137 static INLINE
unsigned int
2138 mode_from_disp_size (i386_operand_type t
)
2140 if (t
.bitfield
.disp8
)
2142 else if (t
.bitfield
.disp16
2143 || t
.bitfield
.disp32
2144 || t
.bitfield
.disp32s
)
2151 fits_in_signed_byte (addressT num
)
2153 return num
+ 0x80 <= 0xff;
2157 fits_in_unsigned_byte (addressT num
)
2163 fits_in_unsigned_word (addressT num
)
2165 return num
<= 0xffff;
2169 fits_in_signed_word (addressT num
)
2171 return num
+ 0x8000 <= 0xffff;
2175 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2180 return num
+ 0x80000000 <= 0xffffffff;
2182 } /* fits_in_signed_long() */
2185 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2190 return num
<= 0xffffffff;
2192 } /* fits_in_unsigned_long() */
2195 fits_in_disp8 (offsetT num
)
2197 int shift
= i
.memshift
;
2203 mask
= (1 << shift
) - 1;
2205 /* Return 0 if NUM isn't properly aligned. */
2209 /* Check if NUM will fit in 8bit after shift. */
2210 return fits_in_signed_byte (num
>> shift
);
2214 fits_in_imm4 (offsetT num
)
2216 return (num
& 0xf) == num
;
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num
)
2222 i386_operand_type t
;
2224 operand_type_set (&t
, 0);
2225 t
.bitfield
.imm64
= 1;
2227 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2234 t
.bitfield
.imm1
= 1;
2235 t
.bitfield
.imm8
= 1;
2236 t
.bitfield
.imm8s
= 1;
2237 t
.bitfield
.imm16
= 1;
2238 t
.bitfield
.imm32
= 1;
2239 t
.bitfield
.imm32s
= 1;
2241 else if (fits_in_signed_byte (num
))
2243 t
.bitfield
.imm8
= 1;
2244 t
.bitfield
.imm8s
= 1;
2245 t
.bitfield
.imm16
= 1;
2246 t
.bitfield
.imm32
= 1;
2247 t
.bitfield
.imm32s
= 1;
2249 else if (fits_in_unsigned_byte (num
))
2251 t
.bitfield
.imm8
= 1;
2252 t
.bitfield
.imm16
= 1;
2253 t
.bitfield
.imm32
= 1;
2254 t
.bitfield
.imm32s
= 1;
2256 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2258 t
.bitfield
.imm16
= 1;
2259 t
.bitfield
.imm32
= 1;
2260 t
.bitfield
.imm32s
= 1;
2262 else if (fits_in_signed_long (num
))
2264 t
.bitfield
.imm32
= 1;
2265 t
.bitfield
.imm32s
= 1;
2267 else if (fits_in_unsigned_long (num
))
2268 t
.bitfield
.imm32
= 1;
2274 offset_in_range (offsetT val
, int size
)
2280 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2281 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2282 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2284 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code
!= CODE_64BIT
2292 || i
.prefix
[ADDR_PREFIX
])
2293 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2294 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2297 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2299 char buf1
[40], buf2
[40];
2301 sprint_value (buf1
, val
);
2302 sprint_value (buf2
, val
& mask
);
2303 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix
)
2329 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2332 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2333 && flag_code
== CODE_64BIT
)
2335 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2336 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2337 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2338 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2349 case DS_PREFIX_OPCODE
:
2352 case CS_PREFIX_OPCODE
:
2353 case ES_PREFIX_OPCODE
:
2354 case FS_PREFIX_OPCODE
:
2355 case GS_PREFIX_OPCODE
:
2356 case SS_PREFIX_OPCODE
:
2360 case REPNE_PREFIX_OPCODE
:
2361 case REPE_PREFIX_OPCODE
:
2366 case LOCK_PREFIX_OPCODE
:
2375 case ADDR_PREFIX_OPCODE
:
2379 case DATA_PREFIX_OPCODE
:
2383 if (i
.prefix
[q
] != 0)
2391 i
.prefix
[q
] |= prefix
;
2394 as_bad (_("same type of prefix used twice"));
2400 update_code_flag (int value
, int check
)
2402 PRINTF_LIKE ((*as_error
));
2404 flag_code
= (enum flag_code
) value
;
2405 if (flag_code
== CODE_64BIT
)
2407 cpu_arch_flags
.bitfield
.cpu64
= 1;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2412 cpu_arch_flags
.bitfield
.cpu64
= 0;
2413 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2415 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2418 as_error
= as_fatal
;
2421 (*as_error
) (_("64bit mode not supported on `%s'."),
2422 cpu_arch_name
? cpu_arch_name
: default_arch
);
2424 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2427 as_error
= as_fatal
;
2430 (*as_error
) (_("32bit mode not supported on `%s'."),
2431 cpu_arch_name
? cpu_arch_name
: default_arch
);
2433 stackop_size
= '\0';
2437 set_code_flag (int value
)
2439 update_code_flag (value
, 0);
2443 set_16bit_gcc_code_flag (int new_code_flag
)
2445 flag_code
= (enum flag_code
) new_code_flag
;
2446 if (flag_code
!= CODE_16BIT
)
2448 cpu_arch_flags
.bitfield
.cpu64
= 0;
2449 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2450 stackop_size
= LONG_MNEM_SUFFIX
;
2454 set_intel_syntax (int syntax_flag
)
2456 /* Find out if register prefixing is specified. */
2457 int ask_naked_reg
= 0;
2460 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2463 int e
= get_symbol_name (&string
);
2465 if (strcmp (string
, "prefix") == 0)
2467 else if (strcmp (string
, "noprefix") == 0)
2470 as_bad (_("bad argument to syntax directive."));
2471 (void) restore_line_pointer (e
);
2473 demand_empty_rest_of_line ();
2475 intel_syntax
= syntax_flag
;
2477 if (ask_naked_reg
== 0)
2478 allow_naked_reg
= (intel_syntax
2479 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2481 allow_naked_reg
= (ask_naked_reg
< 0);
2483 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2485 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2486 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2487 register_prefix
= allow_naked_reg
? "" : "%";
2491 set_intel_mnemonic (int mnemonic_flag
)
2493 intel_mnemonic
= mnemonic_flag
;
2497 set_allow_index_reg (int flag
)
2499 allow_index_reg
= flag
;
2503 set_check (int what
)
2505 enum check_kind
*kind
;
2510 kind
= &operand_check
;
2521 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2524 int e
= get_symbol_name (&string
);
2526 if (strcmp (string
, "none") == 0)
2528 else if (strcmp (string
, "warning") == 0)
2529 *kind
= check_warning
;
2530 else if (strcmp (string
, "error") == 0)
2531 *kind
= check_error
;
2533 as_bad (_("bad argument to %s_check directive."), str
);
2534 (void) restore_line_pointer (e
);
2537 as_bad (_("missing argument for %s_check directive"), str
);
2539 demand_empty_rest_of_line ();
2543 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2544 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2547 static const char *arch
;
2549 /* Intel LIOM is only supported on ELF. */
2555 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2556 use default_arch. */
2557 arch
= cpu_arch_name
;
2559 arch
= default_arch
;
2562 /* If we are targeting Intel MCU, we must enable it. */
2563 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2564 || new_flag
.bitfield
.cpuiamcu
)
2567 /* If we are targeting Intel L1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2569 || new_flag
.bitfield
.cpul1om
)
2572 /* If we are targeting Intel K1OM, we must enable it. */
2573 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2574 || new_flag
.bitfield
.cpuk1om
)
2577 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2582 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2586 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2589 int e
= get_symbol_name (&string
);
2591 i386_cpu_flags flags
;
2593 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2595 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2597 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2601 cpu_arch_name
= cpu_arch
[j
].name
;
2602 cpu_sub_arch_name
= NULL
;
2603 cpu_arch_flags
= cpu_arch
[j
].flags
;
2604 if (flag_code
== CODE_64BIT
)
2606 cpu_arch_flags
.bitfield
.cpu64
= 1;
2607 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2611 cpu_arch_flags
.bitfield
.cpu64
= 0;
2612 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2614 cpu_arch_isa
= cpu_arch
[j
].type
;
2615 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2616 if (!cpu_arch_tune_set
)
2618 cpu_arch_tune
= cpu_arch_isa
;
2619 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2624 flags
= cpu_flags_or (cpu_arch_flags
,
2627 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2629 if (cpu_sub_arch_name
)
2631 char *name
= cpu_sub_arch_name
;
2632 cpu_sub_arch_name
= concat (name
,
2634 (const char *) NULL
);
2638 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2639 cpu_arch_flags
= flags
;
2640 cpu_arch_isa_flags
= flags
;
2644 = cpu_flags_or (cpu_arch_isa_flags
,
2646 (void) restore_line_pointer (e
);
2647 demand_empty_rest_of_line ();
2652 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2654 /* Disable an ISA extension. */
2655 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2656 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2658 flags
= cpu_flags_and_not (cpu_arch_flags
,
2659 cpu_noarch
[j
].flags
);
2660 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2662 if (cpu_sub_arch_name
)
2664 char *name
= cpu_sub_arch_name
;
2665 cpu_sub_arch_name
= concat (name
, string
,
2666 (const char *) NULL
);
2670 cpu_sub_arch_name
= xstrdup (string
);
2671 cpu_arch_flags
= flags
;
2672 cpu_arch_isa_flags
= flags
;
2674 (void) restore_line_pointer (e
);
2675 demand_empty_rest_of_line ();
2679 j
= ARRAY_SIZE (cpu_arch
);
2682 if (j
>= ARRAY_SIZE (cpu_arch
))
2683 as_bad (_("no such architecture: `%s'"), string
);
2685 *input_line_pointer
= e
;
2688 as_bad (_("missing cpu architecture"));
2690 no_cond_jump_promotion
= 0;
2691 if (*input_line_pointer
== ','
2692 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2697 ++input_line_pointer
;
2698 e
= get_symbol_name (&string
);
2700 if (strcmp (string
, "nojumps") == 0)
2701 no_cond_jump_promotion
= 1;
2702 else if (strcmp (string
, "jumps") == 0)
2705 as_bad (_("no such architecture modifier: `%s'"), string
);
2707 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2713 enum bfd_architecture
2716 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2718 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2719 || flag_code
!= CODE_64BIT
)
2720 as_fatal (_("Intel L1OM is 64bit ELF only"));
2721 return bfd_arch_l1om
;
2723 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2725 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2726 || flag_code
!= CODE_64BIT
)
2727 as_fatal (_("Intel K1OM is 64bit ELF only"));
2728 return bfd_arch_k1om
;
2730 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2732 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2733 || flag_code
== CODE_64BIT
)
2734 as_fatal (_("Intel MCU is 32bit ELF only"));
2735 return bfd_arch_iamcu
;
2738 return bfd_arch_i386
;
2744 if (!strncmp (default_arch
, "x86_64", 6))
2746 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2748 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2749 || default_arch
[6] != '\0')
2750 as_fatal (_("Intel L1OM is 64bit ELF only"));
2751 return bfd_mach_l1om
;
2753 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2755 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2756 || default_arch
[6] != '\0')
2757 as_fatal (_("Intel K1OM is 64bit ELF only"));
2758 return bfd_mach_k1om
;
2760 else if (default_arch
[6] == '\0')
2761 return bfd_mach_x86_64
;
2763 return bfd_mach_x64_32
;
2765 else if (!strcmp (default_arch
, "i386")
2766 || !strcmp (default_arch
, "iamcu"))
2768 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2770 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2771 as_fatal (_("Intel MCU is 32bit ELF only"));
2772 return bfd_mach_i386_iamcu
;
2775 return bfd_mach_i386_i386
;
2778 as_fatal (_("unknown architecture"));
2784 const char *hash_err
;
2786 /* Support pseudo prefixes like {disp32}. */
2787 lex_type
['{'] = LEX_BEGIN_NAME
;
2789 /* Initialize op_hash hash table. */
2790 op_hash
= hash_new ();
2793 const insn_template
*optab
;
2794 templates
*core_optab
;
2796 /* Setup for loop. */
2798 core_optab
= XNEW (templates
);
2799 core_optab
->start
= optab
;
2804 if (optab
->name
== NULL
2805 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2807 /* different name --> ship out current template list;
2808 add to hash table; & begin anew. */
2809 core_optab
->end
= optab
;
2810 hash_err
= hash_insert (op_hash
,
2812 (void *) core_optab
);
2815 as_fatal (_("can't hash %s: %s"),
2819 if (optab
->name
== NULL
)
2821 core_optab
= XNEW (templates
);
2822 core_optab
->start
= optab
;
2827 /* Initialize reg_hash hash table. */
2828 reg_hash
= hash_new ();
2830 const reg_entry
*regtab
;
2831 unsigned int regtab_size
= i386_regtab_size
;
2833 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2835 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2837 as_fatal (_("can't hash %s: %s"),
2843 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2848 for (c
= 0; c
< 256; c
++)
2853 mnemonic_chars
[c
] = c
;
2854 register_chars
[c
] = c
;
2855 operand_chars
[c
] = c
;
2857 else if (ISLOWER (c
))
2859 mnemonic_chars
[c
] = c
;
2860 register_chars
[c
] = c
;
2861 operand_chars
[c
] = c
;
2863 else if (ISUPPER (c
))
2865 mnemonic_chars
[c
] = TOLOWER (c
);
2866 register_chars
[c
] = mnemonic_chars
[c
];
2867 operand_chars
[c
] = c
;
2869 else if (c
== '{' || c
== '}')
2871 mnemonic_chars
[c
] = c
;
2872 operand_chars
[c
] = c
;
2875 if (ISALPHA (c
) || ISDIGIT (c
))
2876 identifier_chars
[c
] = c
;
2879 identifier_chars
[c
] = c
;
2880 operand_chars
[c
] = c
;
2885 identifier_chars
['@'] = '@';
2888 identifier_chars
['?'] = '?';
2889 operand_chars
['?'] = '?';
2891 digit_chars
['-'] = '-';
2892 mnemonic_chars
['_'] = '_';
2893 mnemonic_chars
['-'] = '-';
2894 mnemonic_chars
['.'] = '.';
2895 identifier_chars
['_'] = '_';
2896 identifier_chars
['.'] = '.';
2898 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2899 operand_chars
[(unsigned char) *p
] = *p
;
2902 if (flag_code
== CODE_64BIT
)
2904 #if defined (OBJ_COFF) && defined (TE_PE)
2905 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2908 x86_dwarf2_return_column
= 16;
2910 x86_cie_data_alignment
= -8;
2914 x86_dwarf2_return_column
= 8;
2915 x86_cie_data_alignment
= -4;
2920 i386_print_statistics (FILE *file
)
2922 hash_print_statistics (file
, "i386 opcode", op_hash
);
2923 hash_print_statistics (file
, "i386 register", reg_hash
);
2928 /* Debugging routines for md_assemble. */
2929 static void pte (insn_template
*);
2930 static void pt (i386_operand_type
);
2931 static void pe (expressionS
*);
2932 static void ps (symbolS
*);
2935 pi (char *line
, i386_insn
*x
)
2939 fprintf (stdout
, "%s: template ", line
);
2941 fprintf (stdout
, " address: base %s index %s scale %x\n",
2942 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2943 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2944 x
->log2_scale_factor
);
2945 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2946 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2947 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2948 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2949 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2950 (x
->rex
& REX_W
) != 0,
2951 (x
->rex
& REX_R
) != 0,
2952 (x
->rex
& REX_X
) != 0,
2953 (x
->rex
& REX_B
) != 0);
2954 for (j
= 0; j
< x
->operands
; j
++)
2956 fprintf (stdout
, " #%d: ", j
+ 1);
2958 fprintf (stdout
, "\n");
2959 if (x
->types
[j
].bitfield
.reg
2960 || x
->types
[j
].bitfield
.regmmx
2961 || x
->types
[j
].bitfield
.regsimd
2962 || x
->types
[j
].bitfield
.sreg2
2963 || x
->types
[j
].bitfield
.sreg3
2964 || x
->types
[j
].bitfield
.control
2965 || x
->types
[j
].bitfield
.debug
2966 || x
->types
[j
].bitfield
.test
)
2967 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2968 if (operand_type_check (x
->types
[j
], imm
))
2970 if (operand_type_check (x
->types
[j
], disp
))
2971 pe (x
->op
[j
].disps
);
2976 pte (insn_template
*t
)
2979 fprintf (stdout
, " %d operands ", t
->operands
);
2980 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2981 if (t
->extension_opcode
!= None
)
2982 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2983 if (t
->opcode_modifier
.d
)
2984 fprintf (stdout
, "D");
2985 if (t
->opcode_modifier
.w
)
2986 fprintf (stdout
, "W");
2987 fprintf (stdout
, "\n");
2988 for (j
= 0; j
< t
->operands
; j
++)
2990 fprintf (stdout
, " #%d type ", j
+ 1);
2991 pt (t
->operand_types
[j
]);
2992 fprintf (stdout
, "\n");
2999 fprintf (stdout
, " operation %d\n", e
->X_op
);
3000 fprintf (stdout
, " add_number %ld (%lx)\n",
3001 (long) e
->X_add_number
, (long) e
->X_add_number
);
3002 if (e
->X_add_symbol
)
3004 fprintf (stdout
, " add_symbol ");
3005 ps (e
->X_add_symbol
);
3006 fprintf (stdout
, "\n");
3010 fprintf (stdout
, " op_symbol ");
3011 ps (e
->X_op_symbol
);
3012 fprintf (stdout
, "\n");
3019 fprintf (stdout
, "%s type %s%s",
3021 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3022 segment_name (S_GET_SEGMENT (s
)));
3025 static struct type_name
3027 i386_operand_type mask
;
3030 const type_names
[] =
3032 { OPERAND_TYPE_REG8
, "r8" },
3033 { OPERAND_TYPE_REG16
, "r16" },
3034 { OPERAND_TYPE_REG32
, "r32" },
3035 { OPERAND_TYPE_REG64
, "r64" },
3036 { OPERAND_TYPE_IMM8
, "i8" },
3037 { OPERAND_TYPE_IMM8
, "i8s" },
3038 { OPERAND_TYPE_IMM16
, "i16" },
3039 { OPERAND_TYPE_IMM32
, "i32" },
3040 { OPERAND_TYPE_IMM32S
, "i32s" },
3041 { OPERAND_TYPE_IMM64
, "i64" },
3042 { OPERAND_TYPE_IMM1
, "i1" },
3043 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3044 { OPERAND_TYPE_DISP8
, "d8" },
3045 { OPERAND_TYPE_DISP16
, "d16" },
3046 { OPERAND_TYPE_DISP32
, "d32" },
3047 { OPERAND_TYPE_DISP32S
, "d32s" },
3048 { OPERAND_TYPE_DISP64
, "d64" },
3049 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3050 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3051 { OPERAND_TYPE_CONTROL
, "control reg" },
3052 { OPERAND_TYPE_TEST
, "test reg" },
3053 { OPERAND_TYPE_DEBUG
, "debug reg" },
3054 { OPERAND_TYPE_FLOATREG
, "FReg" },
3055 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3056 { OPERAND_TYPE_SREG2
, "SReg2" },
3057 { OPERAND_TYPE_SREG3
, "SReg3" },
3058 { OPERAND_TYPE_ACC
, "Acc" },
3059 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3060 { OPERAND_TYPE_REGMMX
, "rMMX" },
3061 { OPERAND_TYPE_REGXMM
, "rXMM" },
3062 { OPERAND_TYPE_REGYMM
, "rYMM" },
3063 { OPERAND_TYPE_REGZMM
, "rZMM" },
3064 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3065 { OPERAND_TYPE_ESSEG
, "es" },
3069 pt (i386_operand_type t
)
3072 i386_operand_type a
;
3074 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3076 a
= operand_type_and (t
, type_names
[j
].mask
);
3077 if (!operand_type_all_zero (&a
))
3078 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3083 #endif /* DEBUG386 */
3085 static bfd_reloc_code_real_type
3086 reloc (unsigned int size
,
3089 bfd_reloc_code_real_type other
)
3091 if (other
!= NO_RELOC
)
3093 reloc_howto_type
*rel
;
3098 case BFD_RELOC_X86_64_GOT32
:
3099 return BFD_RELOC_X86_64_GOT64
;
3101 case BFD_RELOC_X86_64_GOTPLT64
:
3102 return BFD_RELOC_X86_64_GOTPLT64
;
3104 case BFD_RELOC_X86_64_PLTOFF64
:
3105 return BFD_RELOC_X86_64_PLTOFF64
;
3107 case BFD_RELOC_X86_64_GOTPC32
:
3108 other
= BFD_RELOC_X86_64_GOTPC64
;
3110 case BFD_RELOC_X86_64_GOTPCREL
:
3111 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3113 case BFD_RELOC_X86_64_TPOFF32
:
3114 other
= BFD_RELOC_X86_64_TPOFF64
;
3116 case BFD_RELOC_X86_64_DTPOFF32
:
3117 other
= BFD_RELOC_X86_64_DTPOFF64
;
3123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3124 if (other
== BFD_RELOC_SIZE32
)
3127 other
= BFD_RELOC_SIZE64
;
3130 as_bad (_("there are no pc-relative size relocations"));
3136 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3137 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3140 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3142 as_bad (_("unknown relocation (%u)"), other
);
3143 else if (size
!= bfd_get_reloc_size (rel
))
3144 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3145 bfd_get_reloc_size (rel
),
3147 else if (pcrel
&& !rel
->pc_relative
)
3148 as_bad (_("non-pc-relative relocation for pc-relative field"));
3149 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3151 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3153 as_bad (_("relocated field and relocation type differ in signedness"));
3162 as_bad (_("there are no unsigned pc-relative relocations"));
3165 case 1: return BFD_RELOC_8_PCREL
;
3166 case 2: return BFD_RELOC_16_PCREL
;
3167 case 4: return BFD_RELOC_32_PCREL
;
3168 case 8: return BFD_RELOC_64_PCREL
;
3170 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3177 case 4: return BFD_RELOC_X86_64_32S
;
3182 case 1: return BFD_RELOC_8
;
3183 case 2: return BFD_RELOC_16
;
3184 case 4: return BFD_RELOC_32
;
3185 case 8: return BFD_RELOC_64
;
3187 as_bad (_("cannot do %s %u byte relocation"),
3188 sign
> 0 ? "signed" : "unsigned", size
);
3194 /* Here we decide which fixups can be adjusted to make them relative to
3195 the beginning of the section instead of the symbol. Basically we need
3196 to make sure that the dynamic relocations are done correctly, so in
3197 some cases we force the original symbol to be used. */
3200 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3206 /* Don't adjust pc-relative references to merge sections in 64-bit
3208 if (use_rela_relocations
3209 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3213 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3214 and changed later by validate_fix. */
3215 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3216 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3219 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3220 for size relocations. */
3221 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3222 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3223 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3224 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3225 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3226 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3249 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3250 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3251 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3252 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3253 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3260 intel_float_operand (const char *mnemonic
)
3262 /* Note that the value returned is meaningful only for opcodes with (memory)
3263 operands, hence the code here is free to improperly handle opcodes that
3264 have no operands (for better performance and smaller code). */
3266 if (mnemonic
[0] != 'f')
3267 return 0; /* non-math */
3269 switch (mnemonic
[1])
3271 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3272 the fs segment override prefix not currently handled because no
3273 call path can make opcodes without operands get here */
3275 return 2 /* integer op */;
3277 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3278 return 3; /* fldcw/fldenv */
3281 if (mnemonic
[2] != 'o' /* fnop */)
3282 return 3; /* non-waiting control op */
3285 if (mnemonic
[2] == 's')
3286 return 3; /* frstor/frstpm */
3289 if (mnemonic
[2] == 'a')
3290 return 3; /* fsave */
3291 if (mnemonic
[2] == 't')
3293 switch (mnemonic
[3])
3295 case 'c': /* fstcw */
3296 case 'd': /* fstdw */
3297 case 'e': /* fstenv */
3298 case 's': /* fsts[gw] */
3304 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3305 return 0; /* fxsave/fxrstor are not really math ops */
3312 /* Build the VEX prefix. */
3315 build_vex_prefix (const insn_template
*t
)
3317 unsigned int register_specifier
;
3318 unsigned int implied_prefix
;
3319 unsigned int vector_length
;
3321 /* Check register specifier. */
3322 if (i
.vex
.register_specifier
)
3324 register_specifier
=
3325 ~register_number (i
.vex
.register_specifier
) & 0xf;
3326 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3329 register_specifier
= 0xf;
3331 /* Use 2-byte VEX prefix by swapping destination and source
3333 if (i
.vec_encoding
!= vex_encoding_vex3
3334 && i
.dir_encoding
== dir_encoding_default
3335 && i
.operands
== i
.reg_operands
3336 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3337 && i
.tm
.opcode_modifier
.load
3340 unsigned int xchg
= i
.operands
- 1;
3341 union i386_op temp_op
;
3342 i386_operand_type temp_type
;
3344 temp_type
= i
.types
[xchg
];
3345 i
.types
[xchg
] = i
.types
[0];
3346 i
.types
[0] = temp_type
;
3347 temp_op
= i
.op
[xchg
];
3348 i
.op
[xchg
] = i
.op
[0];
3351 gas_assert (i
.rm
.mode
== 3);
3355 i
.rm
.regmem
= i
.rm
.reg
;
3358 /* Use the next insn. */
3362 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3363 vector_length
= avxscalar
;
3364 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3370 /* Determine vector length from the last multi-length vector
3373 for (op
= t
->operands
; op
--;)
3374 if (t
->operand_types
[op
].bitfield
.xmmword
3375 && t
->operand_types
[op
].bitfield
.ymmword
3376 && i
.types
[op
].bitfield
.ymmword
)
3383 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3388 case DATA_PREFIX_OPCODE
:
3391 case REPE_PREFIX_OPCODE
:
3394 case REPNE_PREFIX_OPCODE
:
3401 /* Use 2-byte VEX prefix if possible. */
3402 if (i
.vec_encoding
!= vex_encoding_vex3
3403 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3404 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3405 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3407 /* 2-byte VEX prefix. */
3411 i
.vex
.bytes
[0] = 0xc5;
3413 /* Check the REX.R bit. */
3414 r
= (i
.rex
& REX_R
) ? 0 : 1;
3415 i
.vex
.bytes
[1] = (r
<< 7
3416 | register_specifier
<< 3
3417 | vector_length
<< 2
3422 /* 3-byte VEX prefix. */
3427 switch (i
.tm
.opcode_modifier
.vexopcode
)
3431 i
.vex
.bytes
[0] = 0xc4;
3435 i
.vex
.bytes
[0] = 0xc4;
3439 i
.vex
.bytes
[0] = 0xc4;
3443 i
.vex
.bytes
[0] = 0x8f;
3447 i
.vex
.bytes
[0] = 0x8f;
3451 i
.vex
.bytes
[0] = 0x8f;
3457 /* The high 3 bits of the second VEX byte are 1's compliment
3458 of RXB bits from REX. */
3459 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3461 /* Check the REX.W bit. */
3462 w
= (i
.rex
& REX_W
) ? 1 : 0;
3463 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3466 i
.vex
.bytes
[2] = (w
<< 7
3467 | register_specifier
<< 3
3468 | vector_length
<< 2
3473 static INLINE bfd_boolean
3474 is_evex_encoding (const insn_template
*t
)
3476 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3477 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3478 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3481 /* Build the EVEX prefix. */
3484 build_evex_prefix (void)
3486 unsigned int register_specifier
;
3487 unsigned int implied_prefix
;
3489 rex_byte vrex_used
= 0;
3491 /* Check register specifier. */
3492 if (i
.vex
.register_specifier
)
3494 gas_assert ((i
.vrex
& REX_X
) == 0);
3496 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3497 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3498 register_specifier
+= 8;
3499 /* The upper 16 registers are encoded in the fourth byte of the
3501 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3502 i
.vex
.bytes
[3] = 0x8;
3503 register_specifier
= ~register_specifier
& 0xf;
3507 register_specifier
= 0xf;
3509 /* Encode upper 16 vector index register in the fourth byte of
3511 if (!(i
.vrex
& REX_X
))
3512 i
.vex
.bytes
[3] = 0x8;
3517 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3522 case DATA_PREFIX_OPCODE
:
3525 case REPE_PREFIX_OPCODE
:
3528 case REPNE_PREFIX_OPCODE
:
3535 /* 4 byte EVEX prefix. */
3537 i
.vex
.bytes
[0] = 0x62;
3540 switch (i
.tm
.opcode_modifier
.vexopcode
)
3556 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3558 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3560 /* The fifth bit of the second EVEX byte is 1's compliment of the
3561 REX_R bit in VREX. */
3562 if (!(i
.vrex
& REX_R
))
3563 i
.vex
.bytes
[1] |= 0x10;
3567 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3569 /* When all operands are registers, the REX_X bit in REX is not
3570 used. We reuse it to encode the upper 16 registers, which is
3571 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3572 as 1's compliment. */
3573 if ((i
.vrex
& REX_B
))
3576 i
.vex
.bytes
[1] &= ~0x40;
3580 /* EVEX instructions shouldn't need the REX prefix. */
3581 i
.vrex
&= ~vrex_used
;
3582 gas_assert (i
.vrex
== 0);
3584 /* Check the REX.W bit. */
3585 w
= (i
.rex
& REX_W
) ? 1 : 0;
3586 if (i
.tm
.opcode_modifier
.vexw
)
3588 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3591 /* If w is not set it means we are dealing with WIG instruction. */
3594 if (evexwig
== evexw1
)
3598 /* Encode the U bit. */
3599 implied_prefix
|= 0x4;
3601 /* The third byte of the EVEX prefix. */
3602 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3604 /* The fourth byte of the EVEX prefix. */
3605 /* The zeroing-masking bit. */
3606 if (i
.mask
&& i
.mask
->zeroing
)
3607 i
.vex
.bytes
[3] |= 0x80;
3609 /* Don't always set the broadcast bit if there is no RC. */
3612 /* Encode the vector length. */
3613 unsigned int vec_length
;
3615 if (!i
.tm
.opcode_modifier
.evex
3616 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3620 /* Determine vector length from the last multi-length vector
3623 for (op
= i
.operands
; op
--;)
3624 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3625 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3626 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3628 if (i
.types
[op
].bitfield
.zmmword
)
3630 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3633 else if (i
.types
[op
].bitfield
.ymmword
)
3635 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3638 else if (i
.types
[op
].bitfield
.xmmword
)
3640 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3643 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3645 switch (i
.broadcast
->bytes
)
3648 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3651 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3654 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3663 if (op
>= MAX_OPERANDS
)
3667 switch (i
.tm
.opcode_modifier
.evex
)
3669 case EVEXLIG
: /* LL' is ignored */
3670 vec_length
= evexlig
<< 5;
3673 vec_length
= 0 << 5;
3676 vec_length
= 1 << 5;
3679 vec_length
= 2 << 5;
3685 i
.vex
.bytes
[3] |= vec_length
;
3686 /* Encode the broadcast bit. */
3688 i
.vex
.bytes
[3] |= 0x10;
3692 if (i
.rounding
->type
!= saeonly
)
3693 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3695 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3698 if (i
.mask
&& i
.mask
->mask
)
3699 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3703 process_immext (void)
3707 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3710 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3711 with an opcode suffix which is coded in the same place as an
3712 8-bit immediate field would be.
3713 Here we check those operands and remove them afterwards. */
3716 for (x
= 0; x
< i
.operands
; x
++)
3717 if (register_number (i
.op
[x
].regs
) != x
)
3718 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3719 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3725 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3727 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3728 suffix which is coded in the same place as an 8-bit immediate
3730 Here we check those operands and remove them afterwards. */
3733 if (i
.operands
!= 3)
3736 for (x
= 0; x
< 2; x
++)
3737 if (register_number (i
.op
[x
].regs
) != x
)
3738 goto bad_register_operand
;
3740 /* Check for third operand for mwaitx/monitorx insn. */
3741 if (register_number (i
.op
[x
].regs
)
3742 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3744 bad_register_operand
:
3745 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3746 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3753 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3754 which is coded in the same place as an 8-bit immediate field
3755 would be. Here we fake an 8-bit immediate operand from the
3756 opcode suffix stored in tm.extension_opcode.
3758 AVX instructions also use this encoding, for some of
3759 3 argument instructions. */
3761 gas_assert (i
.imm_operands
<= 1
3763 || ((i
.tm
.opcode_modifier
.vex
3764 || i
.tm
.opcode_modifier
.vexopcode
3765 || is_evex_encoding (&i
.tm
))
3766 && i
.operands
<= 4)));
3768 exp
= &im_expressions
[i
.imm_operands
++];
3769 i
.op
[i
.operands
].imms
= exp
;
3770 i
.types
[i
.operands
] = imm8
;
3772 exp
->X_op
= O_constant
;
3773 exp
->X_add_number
= i
.tm
.extension_opcode
;
3774 i
.tm
.extension_opcode
= None
;
3781 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3786 as_bad (_("invalid instruction `%s' after `%s'"),
3787 i
.tm
.name
, i
.hle_prefix
);
3790 if (i
.prefix
[LOCK_PREFIX
])
3792 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3796 case HLEPrefixRelease
:
3797 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3799 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3803 if (i
.mem_operands
== 0
3804 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3806 as_bad (_("memory destination needed for instruction `%s'"
3807 " after `xrelease'"), i
.tm
.name
);
3814 /* Try the shortest encoding by shortening operand size. */
3817 optimize_encoding (void)
3821 if (optimize_for_space
3822 && i
.reg_operands
== 1
3823 && i
.imm_operands
== 1
3824 && !i
.types
[1].bitfield
.byte
3825 && i
.op
[0].imms
->X_op
== O_constant
3826 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3827 && ((i
.tm
.base_opcode
== 0xa8
3828 && i
.tm
.extension_opcode
== None
)
3829 || (i
.tm
.base_opcode
== 0xf6
3830 && i
.tm
.extension_opcode
== 0x0)))
3833 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3835 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3836 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3838 i
.types
[1].bitfield
.byte
= 1;
3839 /* Ignore the suffix. */
3841 if (base_regnum
>= 4
3842 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3844 /* Handle SP, BP, SI and DI registers. */
3845 if (i
.types
[1].bitfield
.word
)
3847 else if (i
.types
[1].bitfield
.dword
)
3855 else if (flag_code
== CODE_64BIT
3856 && ((i
.types
[1].bitfield
.qword
3857 && i
.reg_operands
== 1
3858 && i
.imm_operands
== 1
3859 && i
.op
[0].imms
->X_op
== O_constant
3860 && ((i
.tm
.base_opcode
== 0xb0
3861 && i
.tm
.extension_opcode
== None
3862 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3863 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3864 && (((i
.tm
.base_opcode
== 0x24
3865 || i
.tm
.base_opcode
== 0xa8)
3866 && i
.tm
.extension_opcode
== None
)
3867 || (i
.tm
.base_opcode
== 0x80
3868 && i
.tm
.extension_opcode
== 0x4)
3869 || ((i
.tm
.base_opcode
== 0xf6
3870 || i
.tm
.base_opcode
== 0xc6)
3871 && i
.tm
.extension_opcode
== 0x0)))))
3872 || (i
.types
[0].bitfield
.qword
3873 && ((i
.reg_operands
== 2
3874 && i
.op
[0].regs
== i
.op
[1].regs
3875 && ((i
.tm
.base_opcode
== 0x30
3876 || i
.tm
.base_opcode
== 0x28)
3877 && i
.tm
.extension_opcode
== None
))
3878 || (i
.reg_operands
== 1
3880 && i
.tm
.base_opcode
== 0x30
3881 && i
.tm
.extension_opcode
== None
)))))
3884 andq $imm31, %r64 -> andl $imm31, %r32
3885 testq $imm31, %r64 -> testl $imm31, %r32
3886 xorq %r64, %r64 -> xorl %r32, %r32
3887 subq %r64, %r64 -> subl %r32, %r32
3888 movq $imm31, %r64 -> movl $imm31, %r32
3889 movq $imm32, %r64 -> movl $imm32, %r32
3891 i
.tm
.opcode_modifier
.norex64
= 1;
3892 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3895 movq $imm31, %r64 -> movl $imm31, %r32
3896 movq $imm32, %r64 -> movl $imm32, %r32
3898 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3899 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3900 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3901 i
.types
[0].bitfield
.imm32
= 1;
3902 i
.types
[0].bitfield
.imm32s
= 0;
3903 i
.types
[0].bitfield
.imm64
= 0;
3904 i
.types
[1].bitfield
.dword
= 1;
3905 i
.types
[1].bitfield
.qword
= 0;
3906 if (i
.tm
.base_opcode
== 0xc6)
3909 movq $imm31, %r64 -> movl $imm31, %r32
3911 i
.tm
.base_opcode
= 0xb0;
3912 i
.tm
.extension_opcode
= None
;
3913 i
.tm
.opcode_modifier
.shortform
= 1;
3914 i
.tm
.opcode_modifier
.modrm
= 0;
3918 else if (optimize
> 1
3919 && i
.reg_operands
== 3
3920 && i
.op
[0].regs
== i
.op
[1].regs
3921 && !i
.types
[2].bitfield
.xmmword
3922 && (i
.tm
.opcode_modifier
.vex
3923 || ((!i
.mask
|| i
.mask
->zeroing
)
3925 && is_evex_encoding (&i
.tm
)
3926 && (i
.vec_encoding
!= vex_encoding_evex
3927 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3928 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3929 && i
.types
[2].bitfield
.ymmword
)
3930 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3931 && ((i
.tm
.base_opcode
== 0x55
3932 || i
.tm
.base_opcode
== 0x6655
3933 || i
.tm
.base_opcode
== 0x66df
3934 || i
.tm
.base_opcode
== 0x57
3935 || i
.tm
.base_opcode
== 0x6657
3936 || i
.tm
.base_opcode
== 0x66ef
3937 || i
.tm
.base_opcode
== 0x66f8
3938 || i
.tm
.base_opcode
== 0x66f9
3939 || i
.tm
.base_opcode
== 0x66fa
3940 || i
.tm
.base_opcode
== 0x66fb)
3941 && i
.tm
.extension_opcode
== None
))
3944 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3946 EVEX VOP %zmmM, %zmmM, %zmmN
3947 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3948 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3949 EVEX VOP %ymmM, %ymmM, %ymmN
3950 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3951 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3952 VEX VOP %ymmM, %ymmM, %ymmN
3953 -> VEX VOP %xmmM, %xmmM, %xmmN
3954 VOP, one of vpandn and vpxor:
3955 VEX VOP %ymmM, %ymmM, %ymmN
3956 -> VEX VOP %xmmM, %xmmM, %xmmN
3957 VOP, one of vpandnd and vpandnq:
3958 EVEX VOP %zmmM, %zmmM, %zmmN
3959 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3960 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3961 EVEX VOP %ymmM, %ymmM, %ymmN
3962 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3963 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3964 VOP, one of vpxord and vpxorq:
3965 EVEX VOP %zmmM, %zmmM, %zmmN
3966 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3967 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3968 EVEX VOP %ymmM, %ymmM, %ymmN
3969 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3970 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3972 if (is_evex_encoding (&i
.tm
))
3974 if (i
.vec_encoding
== vex_encoding_evex
)
3975 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3978 i
.tm
.opcode_modifier
.vex
= VEX128
;
3979 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3980 i
.tm
.opcode_modifier
.evex
= 0;
3984 i
.tm
.opcode_modifier
.vex
= VEX128
;
3986 if (i
.tm
.opcode_modifier
.vex
)
3987 for (j
= 0; j
< 3; j
++)
3989 i
.types
[j
].bitfield
.xmmword
= 1;
3990 i
.types
[j
].bitfield
.ymmword
= 0;
3995 /* This is the guts of the machine-dependent assembler. LINE points to a
3996 machine dependent instruction. This function is supposed to emit
3997 the frags/bytes it assembles to. */
4000 md_assemble (char *line
)
4003 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4004 const insn_template
*t
;
4006 /* Initialize globals. */
4007 memset (&i
, '\0', sizeof (i
));
4008 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4009 i
.reloc
[j
] = NO_RELOC
;
4010 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4011 memset (im_expressions
, '\0', sizeof (im_expressions
));
4012 save_stack_p
= save_stack
;
4014 /* First parse an instruction mnemonic & call i386_operand for the operands.
4015 We assume that the scrubber has arranged it so that line[0] is the valid
4016 start of a (possibly prefixed) mnemonic. */
4018 line
= parse_insn (line
, mnemonic
);
4021 mnem_suffix
= i
.suffix
;
4023 line
= parse_operands (line
, mnemonic
);
4025 xfree (i
.memop1_string
);
4026 i
.memop1_string
= NULL
;
4030 /* Now we've parsed the mnemonic into a set of templates, and have the
4031 operands at hand. */
4033 /* All intel opcodes have reversed operands except for "bound" and
4034 "enter". We also don't reverse intersegment "jmp" and "call"
4035 instructions with 2 immediate operands so that the immediate segment
4036 precedes the offset, as it does when in AT&T mode. */
4039 && (strcmp (mnemonic
, "bound") != 0)
4040 && (strcmp (mnemonic
, "invlpga") != 0)
4041 && !(operand_type_check (i
.types
[0], imm
)
4042 && operand_type_check (i
.types
[1], imm
)))
4045 /* The order of the immediates should be reversed
4046 for 2 immediates extrq and insertq instructions */
4047 if (i
.imm_operands
== 2
4048 && (strcmp (mnemonic
, "extrq") == 0
4049 || strcmp (mnemonic
, "insertq") == 0))
4050 swap_2_operands (0, 1);
4055 /* Don't optimize displacement for movabs since it only takes 64bit
4058 && i
.disp_encoding
!= disp_encoding_32bit
4059 && (flag_code
!= CODE_64BIT
4060 || strcmp (mnemonic
, "movabs") != 0))
4063 /* Next, we find a template that matches the given insn,
4064 making sure the overlap of the given operands types is consistent
4065 with the template operand types. */
4067 if (!(t
= match_template (mnem_suffix
)))
4070 if (sse_check
!= check_none
4071 && !i
.tm
.opcode_modifier
.noavx
4072 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4073 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4074 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4075 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4076 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4077 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4078 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4079 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4080 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4081 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4083 (sse_check
== check_warning
4085 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4088 /* Zap movzx and movsx suffix. The suffix has been set from
4089 "word ptr" or "byte ptr" on the source operand in Intel syntax
4090 or extracted from mnemonic in AT&T syntax. But we'll use
4091 the destination register to choose the suffix for encoding. */
4092 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4094 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4095 there is no suffix, the default will be byte extension. */
4096 if (i
.reg_operands
!= 2
4099 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4104 if (i
.tm
.opcode_modifier
.fwait
)
4105 if (!add_prefix (FWAIT_OPCODE
))
4108 /* Check if REP prefix is OK. */
4109 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4111 as_bad (_("invalid instruction `%s' after `%s'"),
4112 i
.tm
.name
, i
.rep_prefix
);
4116 /* Check for lock without a lockable instruction. Destination operand
4117 must be memory unless it is xchg (0x86). */
4118 if (i
.prefix
[LOCK_PREFIX
]
4119 && (!i
.tm
.opcode_modifier
.islockable
4120 || i
.mem_operands
== 0
4121 || (i
.tm
.base_opcode
!= 0x86
4122 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4124 as_bad (_("expecting lockable instruction after `lock'"));
4128 /* Check if HLE prefix is OK. */
4129 if (i
.hle_prefix
&& !check_hle ())
4132 /* Check BND prefix. */
4133 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4134 as_bad (_("expecting valid branch instruction after `bnd'"));
4136 /* Check NOTRACK prefix. */
4137 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4138 as_bad (_("expecting indirect branch instruction after `notrack'"));
4140 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4142 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4143 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4144 else if (flag_code
!= CODE_16BIT
4145 ? i
.prefix
[ADDR_PREFIX
]
4146 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4147 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4150 /* Insert BND prefix. */
4151 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4153 if (!i
.prefix
[BND_PREFIX
])
4154 add_prefix (BND_PREFIX_OPCODE
);
4155 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4157 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4158 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4162 /* Check string instruction segment overrides. */
4163 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4165 if (!check_string ())
4167 i
.disp_operands
= 0;
4170 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4171 optimize_encoding ();
4173 if (!process_suffix ())
4176 /* Update operand types. */
4177 for (j
= 0; j
< i
.operands
; j
++)
4178 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4180 /* Make still unresolved immediate matches conform to size of immediate
4181 given in i.suffix. */
4182 if (!finalize_imm ())
4185 if (i
.types
[0].bitfield
.imm1
)
4186 i
.imm_operands
= 0; /* kludge for shift insns. */
4188 /* We only need to check those implicit registers for instructions
4189 with 3 operands or less. */
4190 if (i
.operands
<= 3)
4191 for (j
= 0; j
< i
.operands
; j
++)
4192 if (i
.types
[j
].bitfield
.inoutportreg
4193 || i
.types
[j
].bitfield
.shiftcount
4194 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4197 /* ImmExt should be processed after SSE2AVX. */
4198 if (!i
.tm
.opcode_modifier
.sse2avx
4199 && i
.tm
.opcode_modifier
.immext
)
4202 /* For insns with operands there are more diddles to do to the opcode. */
4205 if (!process_operands ())
4208 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4210 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4211 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4214 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4215 || is_evex_encoding (&i
.tm
))
4217 if (flag_code
== CODE_16BIT
)
4219 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4224 if (i
.tm
.opcode_modifier
.vex
)
4225 build_vex_prefix (t
);
4227 build_evex_prefix ();
4230 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4231 instructions may define INT_OPCODE as well, so avoid this corner
4232 case for those instructions that use MODRM. */
4233 if (i
.tm
.base_opcode
== INT_OPCODE
4234 && !i
.tm
.opcode_modifier
.modrm
4235 && i
.op
[0].imms
->X_add_number
== 3)
4237 i
.tm
.base_opcode
= INT3_OPCODE
;
4241 if ((i
.tm
.opcode_modifier
.jump
4242 || i
.tm
.opcode_modifier
.jumpbyte
4243 || i
.tm
.opcode_modifier
.jumpdword
)
4244 && i
.op
[0].disps
->X_op
== O_constant
)
4246 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4247 the absolute address given by the constant. Since ix86 jumps and
4248 calls are pc relative, we need to generate a reloc. */
4249 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4250 i
.op
[0].disps
->X_op
= O_symbol
;
4253 if (i
.tm
.opcode_modifier
.rex64
)
4256 /* For 8 bit registers we need an empty rex prefix. Also if the
4257 instruction already has a prefix, we need to convert old
4258 registers to new ones. */
4260 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4261 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4262 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4263 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4264 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4265 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4270 i
.rex
|= REX_OPCODE
;
4271 for (x
= 0; x
< 2; x
++)
4273 /* Look for 8 bit operand that uses old registers. */
4274 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4275 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4277 /* In case it is "hi" register, give up. */
4278 if (i
.op
[x
].regs
->reg_num
> 3)
4279 as_bad (_("can't encode register '%s%s' in an "
4280 "instruction requiring REX prefix."),
4281 register_prefix
, i
.op
[x
].regs
->reg_name
);
4283 /* Otherwise it is equivalent to the extended register.
4284 Since the encoding doesn't change this is merely
4285 cosmetic cleanup for debug output. */
4287 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4292 if (i
.rex
== 0 && i
.rex_encoding
)
4294 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4295 that uses legacy register. If it is "hi" register, don't add
4296 the REX_OPCODE byte. */
4298 for (x
= 0; x
< 2; x
++)
4299 if (i
.types
[x
].bitfield
.reg
4300 && i
.types
[x
].bitfield
.byte
4301 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4302 && i
.op
[x
].regs
->reg_num
> 3)
4304 i
.rex_encoding
= FALSE
;
4313 add_prefix (REX_OPCODE
| i
.rex
);
4315 /* We are ready to output the insn. */
4320 parse_insn (char *line
, char *mnemonic
)
4323 char *token_start
= l
;
4326 const insn_template
*t
;
4332 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4337 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4339 as_bad (_("no such instruction: `%s'"), token_start
);
4344 if (!is_space_char (*l
)
4345 && *l
!= END_OF_INSN
4347 || (*l
!= PREFIX_SEPARATOR
4350 as_bad (_("invalid character %s in mnemonic"),
4351 output_invalid (*l
));
4354 if (token_start
== l
)
4356 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4357 as_bad (_("expecting prefix; got nothing"));
4359 as_bad (_("expecting mnemonic; got nothing"));
4363 /* Look up instruction (or prefix) via hash table. */
4364 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4366 if (*l
!= END_OF_INSN
4367 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4368 && current_templates
4369 && current_templates
->start
->opcode_modifier
.isprefix
)
4371 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4373 as_bad ((flag_code
!= CODE_64BIT
4374 ? _("`%s' is only supported in 64-bit mode")
4375 : _("`%s' is not supported in 64-bit mode")),
4376 current_templates
->start
->name
);
4379 /* If we are in 16-bit mode, do not allow addr16 or data16.
4380 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4381 if ((current_templates
->start
->opcode_modifier
.size16
4382 || current_templates
->start
->opcode_modifier
.size32
)
4383 && flag_code
!= CODE_64BIT
4384 && (current_templates
->start
->opcode_modifier
.size32
4385 ^ (flag_code
== CODE_16BIT
)))
4387 as_bad (_("redundant %s prefix"),
4388 current_templates
->start
->name
);
4391 if (current_templates
->start
->opcode_length
== 0)
4393 /* Handle pseudo prefixes. */
4394 switch (current_templates
->start
->base_opcode
)
4398 i
.disp_encoding
= disp_encoding_8bit
;
4402 i
.disp_encoding
= disp_encoding_32bit
;
4406 i
.dir_encoding
= dir_encoding_load
;
4410 i
.dir_encoding
= dir_encoding_store
;
4414 i
.vec_encoding
= vex_encoding_vex2
;
4418 i
.vec_encoding
= vex_encoding_vex3
;
4422 i
.vec_encoding
= vex_encoding_evex
;
4426 i
.rex_encoding
= TRUE
;
4430 i
.no_optimize
= TRUE
;
4438 /* Add prefix, checking for repeated prefixes. */
4439 switch (add_prefix (current_templates
->start
->base_opcode
))
4444 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4445 i
.notrack_prefix
= current_templates
->start
->name
;
4448 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4449 i
.hle_prefix
= current_templates
->start
->name
;
4450 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4451 i
.bnd_prefix
= current_templates
->start
->name
;
4453 i
.rep_prefix
= current_templates
->start
->name
;
4459 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4466 if (!current_templates
)
4468 /* Check if we should swap operand or force 32bit displacement in
4470 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4471 i
.dir_encoding
= dir_encoding_store
;
4472 else if (mnem_p
- 3 == dot_p
4475 i
.disp_encoding
= disp_encoding_8bit
;
4476 else if (mnem_p
- 4 == dot_p
4480 i
.disp_encoding
= disp_encoding_32bit
;
4485 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4488 if (!current_templates
)
4491 /* See if we can get a match by trimming off a suffix. */
4494 case WORD_MNEM_SUFFIX
:
4495 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4496 i
.suffix
= SHORT_MNEM_SUFFIX
;
4499 case BYTE_MNEM_SUFFIX
:
4500 case QWORD_MNEM_SUFFIX
:
4501 i
.suffix
= mnem_p
[-1];
4503 current_templates
= (const templates
*) hash_find (op_hash
,
4506 case SHORT_MNEM_SUFFIX
:
4507 case LONG_MNEM_SUFFIX
:
4510 i
.suffix
= mnem_p
[-1];
4512 current_templates
= (const templates
*) hash_find (op_hash
,
4521 if (intel_float_operand (mnemonic
) == 1)
4522 i
.suffix
= SHORT_MNEM_SUFFIX
;
4524 i
.suffix
= LONG_MNEM_SUFFIX
;
4526 current_templates
= (const templates
*) hash_find (op_hash
,
4531 if (!current_templates
)
4533 as_bad (_("no such instruction: `%s'"), token_start
);
4538 if (current_templates
->start
->opcode_modifier
.jump
4539 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4541 /* Check for a branch hint. We allow ",pt" and ",pn" for
4542 predict taken and predict not taken respectively.
4543 I'm not sure that branch hints actually do anything on loop
4544 and jcxz insns (JumpByte) for current Pentium4 chips. They
4545 may work in the future and it doesn't hurt to accept them
4547 if (l
[0] == ',' && l
[1] == 'p')
4551 if (!add_prefix (DS_PREFIX_OPCODE
))
4555 else if (l
[2] == 'n')
4557 if (!add_prefix (CS_PREFIX_OPCODE
))
4563 /* Any other comma loses. */
4566 as_bad (_("invalid character %s in mnemonic"),
4567 output_invalid (*l
));
4571 /* Check if instruction is supported on specified architecture. */
4573 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4575 supported
|= cpu_flags_match (t
);
4576 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4578 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4579 as_warn (_("use .code16 to ensure correct addressing mode"));
4585 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4586 as_bad (flag_code
== CODE_64BIT
4587 ? _("`%s' is not supported in 64-bit mode")
4588 : _("`%s' is only supported in 64-bit mode"),
4589 current_templates
->start
->name
);
4591 as_bad (_("`%s' is not supported on `%s%s'"),
4592 current_templates
->start
->name
,
4593 cpu_arch_name
? cpu_arch_name
: default_arch
,
4594 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4600 parse_operands (char *l
, const char *mnemonic
)
4604 /* 1 if operand is pending after ','. */
4605 unsigned int expecting_operand
= 0;
4607 /* Non-zero if operand parens not balanced. */
4608 unsigned int paren_not_balanced
;
4610 while (*l
!= END_OF_INSN
)
4612 /* Skip optional white space before operand. */
4613 if (is_space_char (*l
))
4615 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4617 as_bad (_("invalid character %s before operand %d"),
4618 output_invalid (*l
),
4622 token_start
= l
; /* After white space. */
4623 paren_not_balanced
= 0;
4624 while (paren_not_balanced
|| *l
!= ',')
4626 if (*l
== END_OF_INSN
)
4628 if (paren_not_balanced
)
4631 as_bad (_("unbalanced parenthesis in operand %d."),
4634 as_bad (_("unbalanced brackets in operand %d."),
4639 break; /* we are done */
4641 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4643 as_bad (_("invalid character %s in operand %d"),
4644 output_invalid (*l
),
4651 ++paren_not_balanced
;
4653 --paren_not_balanced
;
4658 ++paren_not_balanced
;
4660 --paren_not_balanced
;
4664 if (l
!= token_start
)
4665 { /* Yes, we've read in another operand. */
4666 unsigned int operand_ok
;
4667 this_operand
= i
.operands
++;
4668 if (i
.operands
> MAX_OPERANDS
)
4670 as_bad (_("spurious operands; (%d operands/instruction max)"),
4674 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4675 /* Now parse operand adding info to 'i' as we go along. */
4676 END_STRING_AND_SAVE (l
);
4678 if (i
.mem_operands
> 1)
4680 as_bad (_("too many memory references for `%s'"),
4687 i386_intel_operand (token_start
,
4688 intel_float_operand (mnemonic
));
4690 operand_ok
= i386_att_operand (token_start
);
4692 RESTORE_END_STRING (l
);
4698 if (expecting_operand
)
4700 expecting_operand_after_comma
:
4701 as_bad (_("expecting operand after ','; got nothing"));
4706 as_bad (_("expecting operand before ','; got nothing"));
4711 /* Now *l must be either ',' or END_OF_INSN. */
4714 if (*++l
== END_OF_INSN
)
4716 /* Just skip it, if it's \n complain. */
4717 goto expecting_operand_after_comma
;
4719 expecting_operand
= 1;
4726 swap_2_operands (int xchg1
, int xchg2
)
4728 union i386_op temp_op
;
4729 i386_operand_type temp_type
;
4730 enum bfd_reloc_code_real temp_reloc
;
4732 temp_type
= i
.types
[xchg2
];
4733 i
.types
[xchg2
] = i
.types
[xchg1
];
4734 i
.types
[xchg1
] = temp_type
;
4735 temp_op
= i
.op
[xchg2
];
4736 i
.op
[xchg2
] = i
.op
[xchg1
];
4737 i
.op
[xchg1
] = temp_op
;
4738 temp_reloc
= i
.reloc
[xchg2
];
4739 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4740 i
.reloc
[xchg1
] = temp_reloc
;
4744 if (i
.mask
->operand
== xchg1
)
4745 i
.mask
->operand
= xchg2
;
4746 else if (i
.mask
->operand
== xchg2
)
4747 i
.mask
->operand
= xchg1
;
4751 if (i
.broadcast
->operand
== xchg1
)
4752 i
.broadcast
->operand
= xchg2
;
4753 else if (i
.broadcast
->operand
== xchg2
)
4754 i
.broadcast
->operand
= xchg1
;
4758 if (i
.rounding
->operand
== xchg1
)
4759 i
.rounding
->operand
= xchg2
;
4760 else if (i
.rounding
->operand
== xchg2
)
4761 i
.rounding
->operand
= xchg1
;
4766 swap_operands (void)
4772 swap_2_operands (1, i
.operands
- 2);
4776 swap_2_operands (0, i
.operands
- 1);
4782 if (i
.mem_operands
== 2)
4784 const seg_entry
*temp_seg
;
4785 temp_seg
= i
.seg
[0];
4786 i
.seg
[0] = i
.seg
[1];
4787 i
.seg
[1] = temp_seg
;
4791 /* Try to ensure constant immediates are represented in the smallest
4796 char guess_suffix
= 0;
4800 guess_suffix
= i
.suffix
;
4801 else if (i
.reg_operands
)
4803 /* Figure out a suffix from the last register operand specified.
4804 We can't do this properly yet, ie. excluding InOutPortReg,
4805 but the following works for instructions with immediates.
4806 In any case, we can't set i.suffix yet. */
4807 for (op
= i
.operands
; --op
>= 0;)
4808 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4810 guess_suffix
= BYTE_MNEM_SUFFIX
;
4813 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4815 guess_suffix
= WORD_MNEM_SUFFIX
;
4818 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4820 guess_suffix
= LONG_MNEM_SUFFIX
;
4823 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4825 guess_suffix
= QWORD_MNEM_SUFFIX
;
4829 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4830 guess_suffix
= WORD_MNEM_SUFFIX
;
4832 for (op
= i
.operands
; --op
>= 0;)
4833 if (operand_type_check (i
.types
[op
], imm
))
4835 switch (i
.op
[op
].imms
->X_op
)
4838 /* If a suffix is given, this operand may be shortened. */
4839 switch (guess_suffix
)
4841 case LONG_MNEM_SUFFIX
:
4842 i
.types
[op
].bitfield
.imm32
= 1;
4843 i
.types
[op
].bitfield
.imm64
= 1;
4845 case WORD_MNEM_SUFFIX
:
4846 i
.types
[op
].bitfield
.imm16
= 1;
4847 i
.types
[op
].bitfield
.imm32
= 1;
4848 i
.types
[op
].bitfield
.imm32s
= 1;
4849 i
.types
[op
].bitfield
.imm64
= 1;
4851 case BYTE_MNEM_SUFFIX
:
4852 i
.types
[op
].bitfield
.imm8
= 1;
4853 i
.types
[op
].bitfield
.imm8s
= 1;
4854 i
.types
[op
].bitfield
.imm16
= 1;
4855 i
.types
[op
].bitfield
.imm32
= 1;
4856 i
.types
[op
].bitfield
.imm32s
= 1;
4857 i
.types
[op
].bitfield
.imm64
= 1;
4861 /* If this operand is at most 16 bits, convert it
4862 to a signed 16 bit number before trying to see
4863 whether it will fit in an even smaller size.
4864 This allows a 16-bit operand such as $0xffe0 to
4865 be recognised as within Imm8S range. */
4866 if ((i
.types
[op
].bitfield
.imm16
)
4867 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4869 i
.op
[op
].imms
->X_add_number
=
4870 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4873 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4874 if ((i
.types
[op
].bitfield
.imm32
)
4875 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4878 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4879 ^ ((offsetT
) 1 << 31))
4880 - ((offsetT
) 1 << 31));
4884 = operand_type_or (i
.types
[op
],
4885 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4887 /* We must avoid matching of Imm32 templates when 64bit
4888 only immediate is available. */
4889 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4890 i
.types
[op
].bitfield
.imm32
= 0;
4897 /* Symbols and expressions. */
4899 /* Convert symbolic operand to proper sizes for matching, but don't
4900 prevent matching a set of insns that only supports sizes other
4901 than those matching the insn suffix. */
4903 i386_operand_type mask
, allowed
;
4904 const insn_template
*t
;
4906 operand_type_set (&mask
, 0);
4907 operand_type_set (&allowed
, 0);
4909 for (t
= current_templates
->start
;
4910 t
< current_templates
->end
;
4912 allowed
= operand_type_or (allowed
,
4913 t
->operand_types
[op
]);
4914 switch (guess_suffix
)
4916 case QWORD_MNEM_SUFFIX
:
4917 mask
.bitfield
.imm64
= 1;
4918 mask
.bitfield
.imm32s
= 1;
4920 case LONG_MNEM_SUFFIX
:
4921 mask
.bitfield
.imm32
= 1;
4923 case WORD_MNEM_SUFFIX
:
4924 mask
.bitfield
.imm16
= 1;
4926 case BYTE_MNEM_SUFFIX
:
4927 mask
.bitfield
.imm8
= 1;
4932 allowed
= operand_type_and (mask
, allowed
);
4933 if (!operand_type_all_zero (&allowed
))
4934 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4941 /* Try to use the smallest displacement type too. */
4943 optimize_disp (void)
4947 for (op
= i
.operands
; --op
>= 0;)
4948 if (operand_type_check (i
.types
[op
], disp
))
4950 if (i
.op
[op
].disps
->X_op
== O_constant
)
4952 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4954 if (i
.types
[op
].bitfield
.disp16
4955 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4957 /* If this operand is at most 16 bits, convert
4958 to a signed 16 bit number and don't use 64bit
4960 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4961 i
.types
[op
].bitfield
.disp64
= 0;
4964 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4965 if (i
.types
[op
].bitfield
.disp32
4966 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4968 /* If this operand is at most 32 bits, convert
4969 to a signed 32 bit number and don't use 64bit
4971 op_disp
&= (((offsetT
) 2 << 31) - 1);
4972 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4973 i
.types
[op
].bitfield
.disp64
= 0;
4976 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4978 i
.types
[op
].bitfield
.disp8
= 0;
4979 i
.types
[op
].bitfield
.disp16
= 0;
4980 i
.types
[op
].bitfield
.disp32
= 0;
4981 i
.types
[op
].bitfield
.disp32s
= 0;
4982 i
.types
[op
].bitfield
.disp64
= 0;
4986 else if (flag_code
== CODE_64BIT
)
4988 if (fits_in_signed_long (op_disp
))
4990 i
.types
[op
].bitfield
.disp64
= 0;
4991 i
.types
[op
].bitfield
.disp32s
= 1;
4993 if (i
.prefix
[ADDR_PREFIX
]
4994 && fits_in_unsigned_long (op_disp
))
4995 i
.types
[op
].bitfield
.disp32
= 1;
4997 if ((i
.types
[op
].bitfield
.disp32
4998 || i
.types
[op
].bitfield
.disp32s
4999 || i
.types
[op
].bitfield
.disp16
)
5000 && fits_in_disp8 (op_disp
))
5001 i
.types
[op
].bitfield
.disp8
= 1;
5003 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5004 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5006 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5007 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5008 i
.types
[op
].bitfield
.disp8
= 0;
5009 i
.types
[op
].bitfield
.disp16
= 0;
5010 i
.types
[op
].bitfield
.disp32
= 0;
5011 i
.types
[op
].bitfield
.disp32s
= 0;
5012 i
.types
[op
].bitfield
.disp64
= 0;
5015 /* We only support 64bit displacement on constants. */
5016 i
.types
[op
].bitfield
.disp64
= 0;
5020 /* Return 1 if there is a match in broadcast bytes between operand
5021 GIVEN and instruction template T. */
5024 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5026 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5027 && i
.types
[given
].bitfield
.byte
)
5028 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5029 && i
.types
[given
].bitfield
.word
)
5030 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5031 && i
.types
[given
].bitfield
.dword
)
5032 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5033 && i
.types
[given
].bitfield
.qword
));
5036 /* Check if operands are valid for the instruction. */
5039 check_VecOperands (const insn_template
*t
)
5043 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5045 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5046 any one operand are implicity requiring AVX512VL support if the actual
5047 operand size is YMMword or XMMword. Since this function runs after
5048 template matching, there's no need to check for YMMword/XMMword in
5050 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5051 if (!cpu_flags_all_zero (&cpu
)
5052 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5053 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5055 for (op
= 0; op
< t
->operands
; ++op
)
5057 if (t
->operand_types
[op
].bitfield
.zmmword
5058 && (i
.types
[op
].bitfield
.ymmword
5059 || i
.types
[op
].bitfield
.xmmword
))
5061 i
.error
= unsupported
;
5067 /* Without VSIB byte, we can't have a vector register for index. */
5068 if (!t
->opcode_modifier
.vecsib
5070 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5071 || i
.index_reg
->reg_type
.bitfield
.ymmword
5072 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5074 i
.error
= unsupported_vector_index_register
;
5078 /* Check if default mask is allowed. */
5079 if (t
->opcode_modifier
.nodefmask
5080 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5082 i
.error
= no_default_mask
;
5086 /* For VSIB byte, we need a vector register for index, and all vector
5087 registers must be distinct. */
5088 if (t
->opcode_modifier
.vecsib
)
5091 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5092 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5093 || (t
->opcode_modifier
.vecsib
== VecSIB256
5094 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5095 || (t
->opcode_modifier
.vecsib
== VecSIB512
5096 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5098 i
.error
= invalid_vsib_address
;
5102 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5103 if (i
.reg_operands
== 2 && !i
.mask
)
5105 gas_assert (i
.types
[0].bitfield
.regsimd
);
5106 gas_assert (i
.types
[0].bitfield
.xmmword
5107 || i
.types
[0].bitfield
.ymmword
);
5108 gas_assert (i
.types
[2].bitfield
.regsimd
);
5109 gas_assert (i
.types
[2].bitfield
.xmmword
5110 || i
.types
[2].bitfield
.ymmword
);
5111 if (operand_check
== check_none
)
5113 if (register_number (i
.op
[0].regs
)
5114 != register_number (i
.index_reg
)
5115 && register_number (i
.op
[2].regs
)
5116 != register_number (i
.index_reg
)
5117 && register_number (i
.op
[0].regs
)
5118 != register_number (i
.op
[2].regs
))
5120 if (operand_check
== check_error
)
5122 i
.error
= invalid_vector_register_set
;
5125 as_warn (_("mask, index, and destination registers should be distinct"));
5127 else if (i
.reg_operands
== 1 && i
.mask
)
5129 if (i
.types
[1].bitfield
.regsimd
5130 && (i
.types
[1].bitfield
.xmmword
5131 || i
.types
[1].bitfield
.ymmword
5132 || i
.types
[1].bitfield
.zmmword
)
5133 && (register_number (i
.op
[1].regs
)
5134 == register_number (i
.index_reg
)))
5136 if (operand_check
== check_error
)
5138 i
.error
= invalid_vector_register_set
;
5141 if (operand_check
!= check_none
)
5142 as_warn (_("index and destination registers should be distinct"));
5147 /* Check if broadcast is supported by the instruction and is applied
5148 to the memory operand. */
5151 i386_operand_type type
, overlap
;
5153 /* Check if specified broadcast is supported in this instruction,
5154 and its broadcast bytes match the memory operand. */
5155 op
= i
.broadcast
->operand
;
5156 if (!t
->opcode_modifier
.broadcast
5157 || !i
.types
[op
].bitfield
.mem
5158 || (!i
.types
[op
].bitfield
.unspecified
5159 && !match_broadcast_size (t
, op
)))
5162 i
.error
= unsupported_broadcast
;
5166 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5167 * i
.broadcast
->type
);
5168 operand_type_set (&type
, 0);
5169 switch (i
.broadcast
->bytes
)
5172 type
.bitfield
.word
= 1;
5175 type
.bitfield
.dword
= 1;
5178 type
.bitfield
.qword
= 1;
5181 type
.bitfield
.xmmword
= 1;
5184 type
.bitfield
.ymmword
= 1;
5187 type
.bitfield
.zmmword
= 1;
5193 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5194 if (operand_type_all_zero (&overlap
))
5197 if (t
->opcode_modifier
.checkregsize
)
5201 type
.bitfield
.baseindex
= 1;
5202 for (j
= 0; j
< i
.operands
; ++j
)
5205 && !operand_type_register_match(i
.types
[j
],
5206 t
->operand_types
[j
],
5208 t
->operand_types
[op
]))
5213 /* If broadcast is supported in this instruction, we need to check if
5214 operand of one-element size isn't specified without broadcast. */
5215 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5217 /* Find memory operand. */
5218 for (op
= 0; op
< i
.operands
; op
++)
5219 if (operand_type_check (i
.types
[op
], anymem
))
5221 gas_assert (op
< i
.operands
);
5222 /* Check size of the memory operand. */
5223 if (match_broadcast_size (t
, op
))
5225 i
.error
= broadcast_needed
;
5230 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5232 /* Check if requested masking is supported. */
5234 && (!t
->opcode_modifier
.masking
5236 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5238 i
.error
= unsupported_masking
;
5242 /* Check if masking is applied to dest operand. */
5243 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5245 i
.error
= mask_not_on_destination
;
5252 if ((i
.rounding
->type
!= saeonly
5253 && !t
->opcode_modifier
.staticrounding
)
5254 || (i
.rounding
->type
== saeonly
5255 && (t
->opcode_modifier
.staticrounding
5256 || !t
->opcode_modifier
.sae
)))
5258 i
.error
= unsupported_rc_sae
;
5261 /* If the instruction has several immediate operands and one of
5262 them is rounding, the rounding operand should be the last
5263 immediate operand. */
5264 if (i
.imm_operands
> 1
5265 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5267 i
.error
= rc_sae_operand_not_last_imm
;
5272 /* Check vector Disp8 operand. */
5273 if (t
->opcode_modifier
.disp8memshift
5274 && i
.disp_encoding
!= disp_encoding_32bit
)
5277 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5278 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5279 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5282 const i386_operand_type
*type
= NULL
;
5285 for (op
= 0; op
< i
.operands
; op
++)
5286 if (operand_type_check (i
.types
[op
], anymem
))
5288 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5289 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5290 else if (t
->operand_types
[op
].bitfield
.xmmword
5291 + t
->operand_types
[op
].bitfield
.ymmword
5292 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5293 type
= &t
->operand_types
[op
];
5294 else if (!i
.types
[op
].bitfield
.unspecified
)
5295 type
= &i
.types
[op
];
5297 else if (i
.types
[op
].bitfield
.regsimd
5298 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5300 if (i
.types
[op
].bitfield
.zmmword
)
5302 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5304 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5310 if (type
->bitfield
.zmmword
)
5312 else if (type
->bitfield
.ymmword
)
5314 else if (type
->bitfield
.xmmword
)
5318 /* For the check in fits_in_disp8(). */
5319 if (i
.memshift
== 0)
5323 for (op
= 0; op
< i
.operands
; op
++)
5324 if (operand_type_check (i
.types
[op
], disp
)
5325 && i
.op
[op
].disps
->X_op
== O_constant
)
5327 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5329 i
.types
[op
].bitfield
.disp8
= 1;
5332 i
.types
[op
].bitfield
.disp8
= 0;
5341 /* Check if operands are valid for the instruction. Update VEX
5345 VEX_check_operands (const insn_template
*t
)
5347 if (i
.vec_encoding
== vex_encoding_evex
)
5349 /* This instruction must be encoded with EVEX prefix. */
5350 if (!is_evex_encoding (t
))
5352 i
.error
= unsupported
;
5358 if (!t
->opcode_modifier
.vex
)
5360 /* This instruction template doesn't have VEX prefix. */
5361 if (i
.vec_encoding
!= vex_encoding_default
)
5363 i
.error
= unsupported
;
5369 /* Only check VEX_Imm4, which must be the first operand. */
5370 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5372 if (i
.op
[0].imms
->X_op
!= O_constant
5373 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5379 /* Turn off Imm8 so that update_imm won't complain. */
5380 i
.types
[0] = vec_imm4
;
5386 static const insn_template
*
5387 match_template (char mnem_suffix
)
5389 /* Points to template once we've found it. */
5390 const insn_template
*t
;
5391 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5392 i386_operand_type overlap4
;
5393 unsigned int found_reverse_match
;
5394 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5395 i386_operand_type operand_types
[MAX_OPERANDS
];
5396 int addr_prefix_disp
;
5398 unsigned int found_cpu_match
, size_match
;
5399 unsigned int check_register
;
5400 enum i386_error specific_error
= 0;
5402 #if MAX_OPERANDS != 5
5403 # error "MAX_OPERANDS must be 5."
5406 found_reverse_match
= 0;
5407 addr_prefix_disp
= -1;
5409 memset (&suffix_check
, 0, sizeof (suffix_check
));
5410 if (intel_syntax
&& i
.broadcast
)
5412 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5413 suffix_check
.no_bsuf
= 1;
5414 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5415 suffix_check
.no_wsuf
= 1;
5416 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5417 suffix_check
.no_ssuf
= 1;
5418 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5419 suffix_check
.no_lsuf
= 1;
5420 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5421 suffix_check
.no_qsuf
= 1;
5422 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5423 suffix_check
.no_ldsuf
= 1;
5425 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5428 switch (mnem_suffix
)
5430 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5431 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5432 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5433 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5434 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5438 /* Must have right number of operands. */
5439 i
.error
= number_of_operands_mismatch
;
5441 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5443 addr_prefix_disp
= -1;
5445 if (i
.operands
!= t
->operands
)
5448 /* Check processor support. */
5449 i
.error
= unsupported
;
5450 found_cpu_match
= (cpu_flags_match (t
)
5451 == CPU_FLAGS_PERFECT_MATCH
);
5452 if (!found_cpu_match
)
5455 /* Check AT&T mnemonic. */
5456 i
.error
= unsupported_with_intel_mnemonic
;
5457 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5460 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5461 i
.error
= unsupported_syntax
;
5462 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5463 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5464 || (intel64
&& t
->opcode_modifier
.amd64
)
5465 || (!intel64
&& t
->opcode_modifier
.intel64
))
5468 /* Check the suffix, except for some instructions in intel mode. */
5469 i
.error
= invalid_instruction_suffix
;
5470 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5471 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5472 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5473 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5474 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5475 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5476 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5478 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5479 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5480 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5481 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5482 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5483 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5484 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5487 size_match
= operand_size_match (t
);
5491 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5492 operand_types
[j
] = t
->operand_types
[j
];
5494 /* In general, don't allow 64-bit operands in 32-bit mode. */
5495 if (i
.suffix
== QWORD_MNEM_SUFFIX
5496 && flag_code
!= CODE_64BIT
5498 ? (!t
->opcode_modifier
.ignoresize
5499 && !t
->opcode_modifier
.broadcast
5500 && !intel_float_operand (t
->name
))
5501 : intel_float_operand (t
->name
) != 2)
5502 && ((!operand_types
[0].bitfield
.regmmx
5503 && !operand_types
[0].bitfield
.regsimd
)
5504 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5505 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5506 && (t
->base_opcode
!= 0x0fc7
5507 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5510 /* In general, don't allow 32-bit operands on pre-386. */
5511 else if (i
.suffix
== LONG_MNEM_SUFFIX
5512 && !cpu_arch_flags
.bitfield
.cpui386
5514 ? (!t
->opcode_modifier
.ignoresize
5515 && !intel_float_operand (t
->name
))
5516 : intel_float_operand (t
->name
) != 2)
5517 && ((!operand_types
[0].bitfield
.regmmx
5518 && !operand_types
[0].bitfield
.regsimd
)
5519 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5520 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5523 /* Do not verify operands when there are none. */
5527 /* We've found a match; break out of loop. */
5531 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5532 into Disp32/Disp16/Disp32 operand. */
5533 if (i
.prefix
[ADDR_PREFIX
] != 0)
5535 /* There should be only one Disp operand. */
5539 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5541 if (operand_types
[j
].bitfield
.disp16
)
5543 addr_prefix_disp
= j
;
5544 operand_types
[j
].bitfield
.disp32
= 1;
5545 operand_types
[j
].bitfield
.disp16
= 0;
5551 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5553 if (operand_types
[j
].bitfield
.disp32
)
5555 addr_prefix_disp
= j
;
5556 operand_types
[j
].bitfield
.disp32
= 0;
5557 operand_types
[j
].bitfield
.disp16
= 1;
5563 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5565 if (operand_types
[j
].bitfield
.disp64
)
5567 addr_prefix_disp
= j
;
5568 operand_types
[j
].bitfield
.disp64
= 0;
5569 operand_types
[j
].bitfield
.disp32
= 1;
5577 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5578 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5581 /* We check register size if needed. */
5582 if (t
->opcode_modifier
.checkregsize
)
5584 check_register
= (1 << t
->operands
) - 1;
5586 check_register
&= ~(1 << i
.broadcast
->operand
);
5591 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5592 switch (t
->operands
)
5595 if (!operand_type_match (overlap0
, i
.types
[0]))
5599 /* xchg %eax, %eax is a special case. It is an alias for nop
5600 only in 32bit mode and we can use opcode 0x90. In 64bit
5601 mode, we can't use 0x90 for xchg %eax, %eax since it should
5602 zero-extend %eax to %rax. */
5603 if (flag_code
== CODE_64BIT
5604 && t
->base_opcode
== 0x90
5605 && operand_type_equal (&i
.types
[0], &acc32
)
5606 && operand_type_equal (&i
.types
[1], &acc32
))
5608 /* xrelease mov %eax, <disp> is another special case. It must not
5609 match the accumulator-only encoding of mov. */
5610 if (flag_code
!= CODE_64BIT
5612 && t
->base_opcode
== 0xa0
5613 && i
.types
[0].bitfield
.acc
5614 && operand_type_check (i
.types
[1], anymem
))
5616 if (!(size_match
& MATCH_STRAIGHT
))
5618 /* If we want store form, we reverse direction of operands. */
5619 if (i
.dir_encoding
== dir_encoding_store
5620 && t
->opcode_modifier
.d
)
5625 /* If we want store form, we skip the current load. */
5626 if (i
.dir_encoding
== dir_encoding_store
5627 && i
.mem_operands
== 0
5628 && t
->opcode_modifier
.load
)
5633 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5634 if (!operand_type_match (overlap0
, i
.types
[0])
5635 || !operand_type_match (overlap1
, i
.types
[1])
5636 || ((check_register
& 3) == 3
5637 && !operand_type_register_match (i
.types
[0],
5642 /* Check if other direction is valid ... */
5643 if (!t
->opcode_modifier
.d
)
5647 if (!(size_match
& MATCH_REVERSE
))
5649 /* Try reversing direction of operands. */
5650 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5651 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5652 if (!operand_type_match (overlap0
, i
.types
[0])
5653 || !operand_type_match (overlap1
, i
.types
[1])
5655 && !operand_type_register_match (i
.types
[0],
5660 /* Does not match either direction. */
5663 /* found_reverse_match holds which of D or FloatR
5665 if (!t
->opcode_modifier
.d
)
5666 found_reverse_match
= 0;
5667 else if (operand_types
[0].bitfield
.tbyte
)
5668 found_reverse_match
= Opcode_FloatD
;
5670 found_reverse_match
= Opcode_D
;
5671 if (t
->opcode_modifier
.floatr
)
5672 found_reverse_match
|= Opcode_FloatR
;
5676 /* Found a forward 2 operand match here. */
5677 switch (t
->operands
)
5680 overlap4
= operand_type_and (i
.types
[4],
5684 overlap3
= operand_type_and (i
.types
[3],
5688 overlap2
= operand_type_and (i
.types
[2],
5693 switch (t
->operands
)
5696 if (!operand_type_match (overlap4
, i
.types
[4])
5697 || !operand_type_register_match (i
.types
[3],
5704 if (!operand_type_match (overlap3
, i
.types
[3])
5705 || ((check_register
& 0xa) == 0xa
5706 && !operand_type_register_match (i
.types
[1],
5710 || ((check_register
& 0xc) == 0xc
5711 && !operand_type_register_match (i
.types
[2],
5718 /* Here we make use of the fact that there are no
5719 reverse match 3 operand instructions. */
5720 if (!operand_type_match (overlap2
, i
.types
[2])
5721 || ((check_register
& 5) == 5
5722 && !operand_type_register_match (i
.types
[0],
5726 || ((check_register
& 6) == 6
5727 && !operand_type_register_match (i
.types
[1],
5735 /* Found either forward/reverse 2, 3 or 4 operand match here:
5736 slip through to break. */
5738 if (!found_cpu_match
)
5740 found_reverse_match
= 0;
5744 /* Check if vector and VEX operands are valid. */
5745 if (check_VecOperands (t
) || VEX_check_operands (t
))
5747 specific_error
= i
.error
;
5751 /* We've found a match; break out of loop. */
5755 if (t
== current_templates
->end
)
5757 /* We found no match. */
5758 const char *err_msg
;
5759 switch (specific_error
? specific_error
: i
.error
)
5763 case operand_size_mismatch
:
5764 err_msg
= _("operand size mismatch");
5766 case operand_type_mismatch
:
5767 err_msg
= _("operand type mismatch");
5769 case register_type_mismatch
:
5770 err_msg
= _("register type mismatch");
5772 case number_of_operands_mismatch
:
5773 err_msg
= _("number of operands mismatch");
5775 case invalid_instruction_suffix
:
5776 err_msg
= _("invalid instruction suffix");
5779 err_msg
= _("constant doesn't fit in 4 bits");
5781 case unsupported_with_intel_mnemonic
:
5782 err_msg
= _("unsupported with Intel mnemonic");
5784 case unsupported_syntax
:
5785 err_msg
= _("unsupported syntax");
5788 as_bad (_("unsupported instruction `%s'"),
5789 current_templates
->start
->name
);
5791 case invalid_vsib_address
:
5792 err_msg
= _("invalid VSIB address");
5794 case invalid_vector_register_set
:
5795 err_msg
= _("mask, index, and destination registers must be distinct");
5797 case unsupported_vector_index_register
:
5798 err_msg
= _("unsupported vector index register");
5800 case unsupported_broadcast
:
5801 err_msg
= _("unsupported broadcast");
5803 case broadcast_needed
:
5804 err_msg
= _("broadcast is needed for operand of such type");
5806 case unsupported_masking
:
5807 err_msg
= _("unsupported masking");
5809 case mask_not_on_destination
:
5810 err_msg
= _("mask not on destination operand");
5812 case no_default_mask
:
5813 err_msg
= _("default mask isn't allowed");
5815 case unsupported_rc_sae
:
5816 err_msg
= _("unsupported static rounding/sae");
5818 case rc_sae_operand_not_last_imm
:
5820 err_msg
= _("RC/SAE operand must precede immediate operands");
5822 err_msg
= _("RC/SAE operand must follow immediate operands");
5824 case invalid_register_operand
:
5825 err_msg
= _("invalid register operand");
5828 as_bad (_("%s for `%s'"), err_msg
,
5829 current_templates
->start
->name
);
5833 if (!quiet_warnings
)
5836 && (i
.types
[0].bitfield
.jumpabsolute
5837 != operand_types
[0].bitfield
.jumpabsolute
))
5839 as_warn (_("indirect %s without `*'"), t
->name
);
5842 if (t
->opcode_modifier
.isprefix
5843 && t
->opcode_modifier
.ignoresize
)
5845 /* Warn them that a data or address size prefix doesn't
5846 affect assembly of the next line of code. */
5847 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5851 /* Copy the template we found. */
5854 if (addr_prefix_disp
!= -1)
5855 i
.tm
.operand_types
[addr_prefix_disp
]
5856 = operand_types
[addr_prefix_disp
];
5858 if (found_reverse_match
)
5860 /* If we found a reverse match we must alter the opcode
5861 direction bit. found_reverse_match holds bits to change
5862 (different for int & float insns). */
5864 i
.tm
.base_opcode
^= found_reverse_match
;
5866 i
.tm
.operand_types
[0] = operand_types
[1];
5867 i
.tm
.operand_types
[1] = operand_types
[0];
5876 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5877 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5879 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5881 as_bad (_("`%s' operand %d must use `%ses' segment"),
5887 /* There's only ever one segment override allowed per instruction.
5888 This instruction possibly has a legal segment override on the
5889 second operand, so copy the segment to where non-string
5890 instructions store it, allowing common code. */
5891 i
.seg
[0] = i
.seg
[1];
5893 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5895 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5897 as_bad (_("`%s' operand %d must use `%ses' segment"),
5908 process_suffix (void)
5910 /* If matched instruction specifies an explicit instruction mnemonic
5912 if (i
.tm
.opcode_modifier
.size16
)
5913 i
.suffix
= WORD_MNEM_SUFFIX
;
5914 else if (i
.tm
.opcode_modifier
.size32
)
5915 i
.suffix
= LONG_MNEM_SUFFIX
;
5916 else if (i
.tm
.opcode_modifier
.size64
)
5917 i
.suffix
= QWORD_MNEM_SUFFIX
;
5918 else if (i
.reg_operands
)
5920 /* If there's no instruction mnemonic suffix we try to invent one
5921 based on register operands. */
5924 /* We take i.suffix from the last register operand specified,
5925 Destination register type is more significant than source
5926 register type. crc32 in SSE4.2 prefers source register
5928 if (i
.tm
.base_opcode
== 0xf20f38f1)
5930 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5931 i
.suffix
= WORD_MNEM_SUFFIX
;
5932 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5933 i
.suffix
= LONG_MNEM_SUFFIX
;
5934 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5935 i
.suffix
= QWORD_MNEM_SUFFIX
;
5937 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5939 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5940 i
.suffix
= BYTE_MNEM_SUFFIX
;
5947 if (i
.tm
.base_opcode
== 0xf20f38f1
5948 || i
.tm
.base_opcode
== 0xf20f38f0)
5950 /* We have to know the operand size for crc32. */
5951 as_bad (_("ambiguous memory operand size for `%s`"),
5956 for (op
= i
.operands
; --op
>= 0;)
5957 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5958 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5960 if (!i
.types
[op
].bitfield
.reg
)
5962 if (i
.types
[op
].bitfield
.byte
)
5963 i
.suffix
= BYTE_MNEM_SUFFIX
;
5964 else if (i
.types
[op
].bitfield
.word
)
5965 i
.suffix
= WORD_MNEM_SUFFIX
;
5966 else if (i
.types
[op
].bitfield
.dword
)
5967 i
.suffix
= LONG_MNEM_SUFFIX
;
5968 else if (i
.types
[op
].bitfield
.qword
)
5969 i
.suffix
= QWORD_MNEM_SUFFIX
;
5976 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5979 && i
.tm
.opcode_modifier
.ignoresize
5980 && i
.tm
.opcode_modifier
.no_bsuf
)
5982 else if (!check_byte_reg ())
5985 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5988 && i
.tm
.opcode_modifier
.ignoresize
5989 && i
.tm
.opcode_modifier
.no_lsuf
5990 && !i
.tm
.opcode_modifier
.todword
5991 && !i
.tm
.opcode_modifier
.toqword
)
5993 else if (!check_long_reg ())
5996 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5999 && i
.tm
.opcode_modifier
.ignoresize
6000 && i
.tm
.opcode_modifier
.no_qsuf
6001 && !i
.tm
.opcode_modifier
.todword
6002 && !i
.tm
.opcode_modifier
.toqword
)
6004 else if (!check_qword_reg ())
6007 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6010 && i
.tm
.opcode_modifier
.ignoresize
6011 && i
.tm
.opcode_modifier
.no_wsuf
)
6013 else if (!check_word_reg ())
6016 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6017 /* Do nothing if the instruction is going to ignore the prefix. */
6022 else if (i
.tm
.opcode_modifier
.defaultsize
6024 /* exclude fldenv/frstor/fsave/fstenv */
6025 && i
.tm
.opcode_modifier
.no_ssuf
)
6027 i
.suffix
= stackop_size
;
6029 else if (intel_syntax
6031 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6032 || i
.tm
.opcode_modifier
.jumpbyte
6033 || i
.tm
.opcode_modifier
.jumpintersegment
6034 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6035 && i
.tm
.extension_opcode
<= 3)))
6040 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6042 i
.suffix
= QWORD_MNEM_SUFFIX
;
6047 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6048 i
.suffix
= LONG_MNEM_SUFFIX
;
6051 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6052 i
.suffix
= WORD_MNEM_SUFFIX
;
6061 if (i
.tm
.opcode_modifier
.w
)
6063 as_bad (_("no instruction mnemonic suffix given and "
6064 "no register operands; can't size instruction"));
6070 unsigned int suffixes
;
6072 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6073 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6075 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6077 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6079 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6081 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6084 /* There are more than suffix matches. */
6085 if (i
.tm
.opcode_modifier
.w
6086 || ((suffixes
& (suffixes
- 1))
6087 && !i
.tm
.opcode_modifier
.defaultsize
6088 && !i
.tm
.opcode_modifier
.ignoresize
))
6090 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6096 /* Change the opcode based on the operand size given by i.suffix. */
6099 /* Size floating point instruction. */
6100 case LONG_MNEM_SUFFIX
:
6101 if (i
.tm
.opcode_modifier
.floatmf
)
6103 i
.tm
.base_opcode
^= 4;
6107 case WORD_MNEM_SUFFIX
:
6108 case QWORD_MNEM_SUFFIX
:
6109 /* It's not a byte, select word/dword operation. */
6110 if (i
.tm
.opcode_modifier
.w
)
6112 if (i
.tm
.opcode_modifier
.shortform
)
6113 i
.tm
.base_opcode
|= 8;
6115 i
.tm
.base_opcode
|= 1;
6118 case SHORT_MNEM_SUFFIX
:
6119 /* Now select between word & dword operations via the operand
6120 size prefix, except for instructions that will ignore this
6122 if (i
.reg_operands
> 0
6123 && i
.types
[0].bitfield
.reg
6124 && i
.tm
.opcode_modifier
.addrprefixopreg
6125 && (i
.tm
.opcode_modifier
.immext
6126 || i
.operands
== 1))
6128 /* The address size override prefix changes the size of the
6130 if ((flag_code
== CODE_32BIT
6131 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6132 || (flag_code
!= CODE_32BIT
6133 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6134 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6137 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6138 && !i
.tm
.opcode_modifier
.ignoresize
6139 && !i
.tm
.opcode_modifier
.floatmf
6140 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6141 || (flag_code
== CODE_64BIT
6142 && i
.tm
.opcode_modifier
.jumpbyte
)))
6144 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6146 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6147 prefix
= ADDR_PREFIX_OPCODE
;
6149 if (!add_prefix (prefix
))
6153 /* Set mode64 for an operand. */
6154 if (i
.suffix
== QWORD_MNEM_SUFFIX
6155 && flag_code
== CODE_64BIT
6156 && !i
.tm
.opcode_modifier
.norex64
6157 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6159 && ! (i
.operands
== 2
6160 && i
.tm
.base_opcode
== 0x90
6161 && i
.tm
.extension_opcode
== None
6162 && operand_type_equal (&i
.types
[0], &acc64
)
6163 && operand_type_equal (&i
.types
[1], &acc64
)))
6169 if (i
.reg_operands
!= 0
6171 && i
.tm
.opcode_modifier
.addrprefixopreg
6172 && !i
.tm
.opcode_modifier
.immext
)
6174 /* Check invalid register operand when the address size override
6175 prefix changes the size of register operands. */
6177 enum { need_word
, need_dword
, need_qword
} need
;
6179 if (flag_code
== CODE_32BIT
)
6180 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6183 if (i
.prefix
[ADDR_PREFIX
])
6186 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6189 for (op
= 0; op
< i
.operands
; op
++)
6190 if (i
.types
[op
].bitfield
.reg
6191 && ((need
== need_word
6192 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6193 || (need
== need_dword
6194 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6195 || (need
== need_qword
6196 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6198 as_bad (_("invalid register operand size for `%s'"),
6208 check_byte_reg (void)
6212 for (op
= i
.operands
; --op
>= 0;)
6214 /* Skip non-register operands. */
6215 if (!i
.types
[op
].bitfield
.reg
)
6218 /* If this is an eight bit register, it's OK. If it's the 16 or
6219 32 bit version of an eight bit register, we will just use the
6220 low portion, and that's OK too. */
6221 if (i
.types
[op
].bitfield
.byte
)
6224 /* I/O port address operands are OK too. */
6225 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6228 /* crc32 doesn't generate this warning. */
6229 if (i
.tm
.base_opcode
== 0xf20f38f0)
6232 if ((i
.types
[op
].bitfield
.word
6233 || i
.types
[op
].bitfield
.dword
6234 || i
.types
[op
].bitfield
.qword
)
6235 && i
.op
[op
].regs
->reg_num
< 4
6236 /* Prohibit these changes in 64bit mode, since the lowering
6237 would be more complicated. */
6238 && flag_code
!= CODE_64BIT
)
6240 #if REGISTER_WARNINGS
6241 if (!quiet_warnings
)
6242 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6244 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6245 ? REGNAM_AL
- REGNAM_AX
6246 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6248 i
.op
[op
].regs
->reg_name
,
6253 /* Any other register is bad. */
6254 if (i
.types
[op
].bitfield
.reg
6255 || i
.types
[op
].bitfield
.regmmx
6256 || i
.types
[op
].bitfield
.regsimd
6257 || i
.types
[op
].bitfield
.sreg2
6258 || i
.types
[op
].bitfield
.sreg3
6259 || i
.types
[op
].bitfield
.control
6260 || i
.types
[op
].bitfield
.debug
6261 || i
.types
[op
].bitfield
.test
)
6263 as_bad (_("`%s%s' not allowed with `%s%c'"),
6265 i
.op
[op
].regs
->reg_name
,
6275 check_long_reg (void)
6279 for (op
= i
.operands
; --op
>= 0;)
6280 /* Skip non-register operands. */
6281 if (!i
.types
[op
].bitfield
.reg
)
6283 /* Reject eight bit registers, except where the template requires
6284 them. (eg. movzb) */
6285 else if (i
.types
[op
].bitfield
.byte
6286 && (i
.tm
.operand_types
[op
].bitfield
.reg
6287 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6288 && (i
.tm
.operand_types
[op
].bitfield
.word
6289 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6291 as_bad (_("`%s%s' not allowed with `%s%c'"),
6293 i
.op
[op
].regs
->reg_name
,
6298 /* Warn if the e prefix on a general reg is missing. */
6299 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6300 && i
.types
[op
].bitfield
.word
6301 && (i
.tm
.operand_types
[op
].bitfield
.reg
6302 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6303 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6305 /* Prohibit these changes in the 64bit mode, since the
6306 lowering is more complicated. */
6307 if (flag_code
== CODE_64BIT
)
6309 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6310 register_prefix
, i
.op
[op
].regs
->reg_name
,
6314 #if REGISTER_WARNINGS
6315 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6317 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6318 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6321 /* Warn if the r prefix on a general reg is present. */
6322 else if (i
.types
[op
].bitfield
.qword
6323 && (i
.tm
.operand_types
[op
].bitfield
.reg
6324 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6325 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6328 && i
.tm
.opcode_modifier
.toqword
6329 && !i
.types
[0].bitfield
.regsimd
)
6331 /* Convert to QWORD. We want REX byte. */
6332 i
.suffix
= QWORD_MNEM_SUFFIX
;
6336 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6337 register_prefix
, i
.op
[op
].regs
->reg_name
,
6346 check_qword_reg (void)
6350 for (op
= i
.operands
; --op
>= 0; )
6351 /* Skip non-register operands. */
6352 if (!i
.types
[op
].bitfield
.reg
)
6354 /* Reject eight bit registers, except where the template requires
6355 them. (eg. movzb) */
6356 else if (i
.types
[op
].bitfield
.byte
6357 && (i
.tm
.operand_types
[op
].bitfield
.reg
6358 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6359 && (i
.tm
.operand_types
[op
].bitfield
.word
6360 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6362 as_bad (_("`%s%s' not allowed with `%s%c'"),
6364 i
.op
[op
].regs
->reg_name
,
6369 /* Warn if the r prefix on a general reg is missing. */
6370 else if ((i
.types
[op
].bitfield
.word
6371 || i
.types
[op
].bitfield
.dword
)
6372 && (i
.tm
.operand_types
[op
].bitfield
.reg
6373 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6374 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6376 /* Prohibit these changes in the 64bit mode, since the
6377 lowering is more complicated. */
6379 && i
.tm
.opcode_modifier
.todword
6380 && !i
.types
[0].bitfield
.regsimd
)
6382 /* Convert to DWORD. We don't want REX byte. */
6383 i
.suffix
= LONG_MNEM_SUFFIX
;
6387 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6388 register_prefix
, i
.op
[op
].regs
->reg_name
,
6397 check_word_reg (void)
6400 for (op
= i
.operands
; --op
>= 0;)
6401 /* Skip non-register operands. */
6402 if (!i
.types
[op
].bitfield
.reg
)
6404 /* Reject eight bit registers, except where the template requires
6405 them. (eg. movzb) */
6406 else if (i
.types
[op
].bitfield
.byte
6407 && (i
.tm
.operand_types
[op
].bitfield
.reg
6408 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6409 && (i
.tm
.operand_types
[op
].bitfield
.word
6410 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6412 as_bad (_("`%s%s' not allowed with `%s%c'"),
6414 i
.op
[op
].regs
->reg_name
,
6419 /* Warn if the e or r prefix on a general reg is present. */
6420 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6421 && (i
.types
[op
].bitfield
.dword
6422 || i
.types
[op
].bitfield
.qword
)
6423 && (i
.tm
.operand_types
[op
].bitfield
.reg
6424 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6425 && i
.tm
.operand_types
[op
].bitfield
.word
)
6427 /* Prohibit these changes in the 64bit mode, since the
6428 lowering is more complicated. */
6429 if (flag_code
== CODE_64BIT
)
6431 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6432 register_prefix
, i
.op
[op
].regs
->reg_name
,
6436 #if REGISTER_WARNINGS
6437 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6439 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6440 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6447 update_imm (unsigned int j
)
6449 i386_operand_type overlap
= i
.types
[j
];
6450 if ((overlap
.bitfield
.imm8
6451 || overlap
.bitfield
.imm8s
6452 || overlap
.bitfield
.imm16
6453 || overlap
.bitfield
.imm32
6454 || overlap
.bitfield
.imm32s
6455 || overlap
.bitfield
.imm64
)
6456 && !operand_type_equal (&overlap
, &imm8
)
6457 && !operand_type_equal (&overlap
, &imm8s
)
6458 && !operand_type_equal (&overlap
, &imm16
)
6459 && !operand_type_equal (&overlap
, &imm32
)
6460 && !operand_type_equal (&overlap
, &imm32s
)
6461 && !operand_type_equal (&overlap
, &imm64
))
6465 i386_operand_type temp
;
6467 operand_type_set (&temp
, 0);
6468 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6470 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6471 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6473 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6474 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6475 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6477 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6478 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6481 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6484 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6485 || operand_type_equal (&overlap
, &imm16_32
)
6486 || operand_type_equal (&overlap
, &imm16_32s
))
6488 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6493 if (!operand_type_equal (&overlap
, &imm8
)
6494 && !operand_type_equal (&overlap
, &imm8s
)
6495 && !operand_type_equal (&overlap
, &imm16
)
6496 && !operand_type_equal (&overlap
, &imm32
)
6497 && !operand_type_equal (&overlap
, &imm32s
)
6498 && !operand_type_equal (&overlap
, &imm64
))
6500 as_bad (_("no instruction mnemonic suffix given; "
6501 "can't determine immediate size"));
6505 i
.types
[j
] = overlap
;
6515 /* Update the first 2 immediate operands. */
6516 n
= i
.operands
> 2 ? 2 : i
.operands
;
6519 for (j
= 0; j
< n
; j
++)
6520 if (update_imm (j
) == 0)
6523 /* The 3rd operand can't be immediate operand. */
6524 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6531 process_operands (void)
6533 /* Default segment register this instruction will use for memory
6534 accesses. 0 means unknown. This is only for optimizing out
6535 unnecessary segment overrides. */
6536 const seg_entry
*default_seg
= 0;
6538 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6540 unsigned int dupl
= i
.operands
;
6541 unsigned int dest
= dupl
- 1;
6544 /* The destination must be an xmm register. */
6545 gas_assert (i
.reg_operands
6546 && MAX_OPERANDS
> dupl
6547 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6549 if (i
.tm
.operand_types
[0].bitfield
.acc
6550 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6552 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6554 /* Keep xmm0 for instructions with VEX prefix and 3
6556 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6557 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6562 /* We remove the first xmm0 and keep the number of
6563 operands unchanged, which in fact duplicates the
6565 for (j
= 1; j
< i
.operands
; j
++)
6567 i
.op
[j
- 1] = i
.op
[j
];
6568 i
.types
[j
- 1] = i
.types
[j
];
6569 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6573 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6575 gas_assert ((MAX_OPERANDS
- 1) > dupl
6576 && (i
.tm
.opcode_modifier
.vexsources
6579 /* Add the implicit xmm0 for instructions with VEX prefix
6581 for (j
= i
.operands
; j
> 0; j
--)
6583 i
.op
[j
] = i
.op
[j
- 1];
6584 i
.types
[j
] = i
.types
[j
- 1];
6585 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6588 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6589 i
.types
[0] = regxmm
;
6590 i
.tm
.operand_types
[0] = regxmm
;
6593 i
.reg_operands
+= 2;
6598 i
.op
[dupl
] = i
.op
[dest
];
6599 i
.types
[dupl
] = i
.types
[dest
];
6600 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6609 i
.op
[dupl
] = i
.op
[dest
];
6610 i
.types
[dupl
] = i
.types
[dest
];
6611 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6614 if (i
.tm
.opcode_modifier
.immext
)
6617 else if (i
.tm
.operand_types
[0].bitfield
.acc
6618 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6622 for (j
= 1; j
< i
.operands
; j
++)
6624 i
.op
[j
- 1] = i
.op
[j
];
6625 i
.types
[j
- 1] = i
.types
[j
];
6627 /* We need to adjust fields in i.tm since they are used by
6628 build_modrm_byte. */
6629 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6636 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6638 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6640 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6641 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6642 regnum
= register_number (i
.op
[1].regs
);
6643 first_reg_in_group
= regnum
& ~3;
6644 last_reg_in_group
= first_reg_in_group
+ 3;
6645 if (regnum
!= first_reg_in_group
)
6646 as_warn (_("source register `%s%s' implicitly denotes"
6647 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6648 register_prefix
, i
.op
[1].regs
->reg_name
,
6649 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6650 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6653 else if (i
.tm
.opcode_modifier
.regkludge
)
6655 /* The imul $imm, %reg instruction is converted into
6656 imul $imm, %reg, %reg, and the clr %reg instruction
6657 is converted into xor %reg, %reg. */
6659 unsigned int first_reg_op
;
6661 if (operand_type_check (i
.types
[0], reg
))
6665 /* Pretend we saw the extra register operand. */
6666 gas_assert (i
.reg_operands
== 1
6667 && i
.op
[first_reg_op
+ 1].regs
== 0);
6668 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6669 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6674 if (i
.tm
.opcode_modifier
.shortform
)
6676 if (i
.types
[0].bitfield
.sreg2
6677 || i
.types
[0].bitfield
.sreg3
)
6679 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6680 && i
.op
[0].regs
->reg_num
== 1)
6682 as_bad (_("you can't `pop %scs'"), register_prefix
);
6685 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6686 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6691 /* The register or float register operand is in operand
6695 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6696 || operand_type_check (i
.types
[0], reg
))
6700 /* Register goes in low 3 bits of opcode. */
6701 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6702 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6704 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6706 /* Warn about some common errors, but press on regardless.
6707 The first case can be generated by gcc (<= 2.8.1). */
6708 if (i
.operands
== 2)
6710 /* Reversed arguments on faddp, fsubp, etc. */
6711 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6712 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6713 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6717 /* Extraneous `l' suffix on fp insn. */
6718 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6719 register_prefix
, i
.op
[0].regs
->reg_name
);
6724 else if (i
.tm
.opcode_modifier
.modrm
)
6726 /* The opcode is completed (modulo i.tm.extension_opcode which
6727 must be put into the modrm byte). Now, we make the modrm and
6728 index base bytes based on all the info we've collected. */
6730 default_seg
= build_modrm_byte ();
6732 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6736 else if (i
.tm
.opcode_modifier
.isstring
)
6738 /* For the string instructions that allow a segment override
6739 on one of their operands, the default segment is ds. */
6743 if (i
.tm
.base_opcode
== 0x8d /* lea */
6746 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6748 /* If a segment was explicitly specified, and the specified segment
6749 is not the default, use an opcode prefix to select it. If we
6750 never figured out what the default segment is, then default_seg
6751 will be zero at this point, and the specified segment prefix will
6753 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6755 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6761 static const seg_entry
*
6762 build_modrm_byte (void)
6764 const seg_entry
*default_seg
= 0;
6765 unsigned int source
, dest
;
6768 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6771 unsigned int nds
, reg_slot
;
6774 dest
= i
.operands
- 1;
6777 /* There are 2 kinds of instructions:
6778 1. 5 operands: 4 register operands or 3 register operands
6779 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6780 VexW0 or VexW1. The destination must be either XMM, YMM or
6782 2. 4 operands: 4 register operands or 3 register operands
6783 plus 1 memory operand, with VexXDS. */
6784 gas_assert ((i
.reg_operands
== 4
6785 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6786 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6787 && i
.tm
.opcode_modifier
.vexw
6788 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6790 /* If VexW1 is set, the first non-immediate operand is the source and
6791 the second non-immediate one is encoded in the immediate operand. */
6792 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6794 source
= i
.imm_operands
;
6795 reg_slot
= i
.imm_operands
+ 1;
6799 source
= i
.imm_operands
+ 1;
6800 reg_slot
= i
.imm_operands
;
6803 if (i
.imm_operands
== 0)
6805 /* When there is no immediate operand, generate an 8bit
6806 immediate operand to encode the first operand. */
6807 exp
= &im_expressions
[i
.imm_operands
++];
6808 i
.op
[i
.operands
].imms
= exp
;
6809 i
.types
[i
.operands
] = imm8
;
6812 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6813 exp
->X_op
= O_constant
;
6814 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6815 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6819 unsigned int imm_slot
;
6821 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6823 if (i
.tm
.opcode_modifier
.immext
)
6825 /* When ImmExt is set, the immediate byte is the last
6827 imm_slot
= i
.operands
- 1;
6835 /* Turn on Imm8 so that output_imm will generate it. */
6836 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6839 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6840 i
.op
[imm_slot
].imms
->X_add_number
6841 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6842 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6845 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6846 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6851 /* i.reg_operands MUST be the number of real register operands;
6852 implicit registers do not count. If there are 3 register
6853 operands, it must be a instruction with VexNDS. For a
6854 instruction with VexNDD, the destination register is encoded
6855 in VEX prefix. If there are 4 register operands, it must be
6856 a instruction with VEX prefix and 3 sources. */
6857 if (i
.mem_operands
== 0
6858 && ((i
.reg_operands
== 2
6859 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6860 || (i
.reg_operands
== 3
6861 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6862 || (i
.reg_operands
== 4 && vex_3_sources
)))
6870 /* When there are 3 operands, one of them may be immediate,
6871 which may be the first or the last operand. Otherwise,
6872 the first operand must be shift count register (cl) or it
6873 is an instruction with VexNDS. */
6874 gas_assert (i
.imm_operands
== 1
6875 || (i
.imm_operands
== 0
6876 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6877 || i
.types
[0].bitfield
.shiftcount
)));
6878 if (operand_type_check (i
.types
[0], imm
)
6879 || i
.types
[0].bitfield
.shiftcount
)
6885 /* When there are 4 operands, the first two must be 8bit
6886 immediate operands. The source operand will be the 3rd
6889 For instructions with VexNDS, if the first operand
6890 an imm8, the source operand is the 2nd one. If the last
6891 operand is imm8, the source operand is the first one. */
6892 gas_assert ((i
.imm_operands
== 2
6893 && i
.types
[0].bitfield
.imm8
6894 && i
.types
[1].bitfield
.imm8
)
6895 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6896 && i
.imm_operands
== 1
6897 && (i
.types
[0].bitfield
.imm8
6898 || i
.types
[i
.operands
- 1].bitfield
.imm8
6900 if (i
.imm_operands
== 2)
6904 if (i
.types
[0].bitfield
.imm8
)
6911 if (is_evex_encoding (&i
.tm
))
6913 /* For EVEX instructions, when there are 5 operands, the
6914 first one must be immediate operand. If the second one
6915 is immediate operand, the source operand is the 3th
6916 one. If the last one is immediate operand, the source
6917 operand is the 2nd one. */
6918 gas_assert (i
.imm_operands
== 2
6919 && i
.tm
.opcode_modifier
.sae
6920 && operand_type_check (i
.types
[0], imm
));
6921 if (operand_type_check (i
.types
[1], imm
))
6923 else if (operand_type_check (i
.types
[4], imm
))
6937 /* RC/SAE operand could be between DEST and SRC. That happens
6938 when one operand is GPR and the other one is XMM/YMM/ZMM
6940 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6943 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6945 /* For instructions with VexNDS, the register-only source
6946 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6947 register. It is encoded in VEX prefix. We need to
6948 clear RegMem bit before calling operand_type_equal. */
6950 i386_operand_type op
;
6953 /* Check register-only source operand when two source
6954 operands are swapped. */
6955 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6956 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6964 op
= i
.tm
.operand_types
[vvvv
];
6965 op
.bitfield
.regmem
= 0;
6966 if ((dest
+ 1) >= i
.operands
6967 || ((!op
.bitfield
.reg
6968 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6969 && !op
.bitfield
.regsimd
6970 && !operand_type_equal (&op
, ®mask
)))
6972 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6978 /* One of the register operands will be encoded in the i.tm.reg
6979 field, the other in the combined i.tm.mode and i.tm.regmem
6980 fields. If no form of this instruction supports a memory
6981 destination operand, then we assume the source operand may
6982 sometimes be a memory operand and so we need to store the
6983 destination in the i.rm.reg field. */
6984 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6985 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6987 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6988 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6989 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6991 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6993 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6995 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7000 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7001 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7002 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7004 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7006 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7008 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7011 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7013 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7016 add_prefix (LOCK_PREFIX_OPCODE
);
7020 { /* If it's not 2 reg operands... */
7025 unsigned int fake_zero_displacement
= 0;
7028 for (op
= 0; op
< i
.operands
; op
++)
7029 if (operand_type_check (i
.types
[op
], anymem
))
7031 gas_assert (op
< i
.operands
);
7033 if (i
.tm
.opcode_modifier
.vecsib
)
7035 if (i
.index_reg
->reg_num
== RegEiz
7036 || i
.index_reg
->reg_num
== RegRiz
)
7039 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7042 i
.sib
.base
= NO_BASE_REGISTER
;
7043 i
.sib
.scale
= i
.log2_scale_factor
;
7044 i
.types
[op
].bitfield
.disp8
= 0;
7045 i
.types
[op
].bitfield
.disp16
= 0;
7046 i
.types
[op
].bitfield
.disp64
= 0;
7047 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7049 /* Must be 32 bit */
7050 i
.types
[op
].bitfield
.disp32
= 1;
7051 i
.types
[op
].bitfield
.disp32s
= 0;
7055 i
.types
[op
].bitfield
.disp32
= 0;
7056 i
.types
[op
].bitfield
.disp32s
= 1;
7059 i
.sib
.index
= i
.index_reg
->reg_num
;
7060 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7062 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7068 if (i
.base_reg
== 0)
7071 if (!i
.disp_operands
)
7072 fake_zero_displacement
= 1;
7073 if (i
.index_reg
== 0)
7075 i386_operand_type newdisp
;
7077 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7078 /* Operand is just <disp> */
7079 if (flag_code
== CODE_64BIT
)
7081 /* 64bit mode overwrites the 32bit absolute
7082 addressing by RIP relative addressing and
7083 absolute addressing is encoded by one of the
7084 redundant SIB forms. */
7085 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7086 i
.sib
.base
= NO_BASE_REGISTER
;
7087 i
.sib
.index
= NO_INDEX_REGISTER
;
7088 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7090 else if ((flag_code
== CODE_16BIT
)
7091 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7093 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7098 i
.rm
.regmem
= NO_BASE_REGISTER
;
7101 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7102 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7104 else if (!i
.tm
.opcode_modifier
.vecsib
)
7106 /* !i.base_reg && i.index_reg */
7107 if (i
.index_reg
->reg_num
== RegEiz
7108 || i
.index_reg
->reg_num
== RegRiz
)
7109 i
.sib
.index
= NO_INDEX_REGISTER
;
7111 i
.sib
.index
= i
.index_reg
->reg_num
;
7112 i
.sib
.base
= NO_BASE_REGISTER
;
7113 i
.sib
.scale
= i
.log2_scale_factor
;
7114 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7115 i
.types
[op
].bitfield
.disp8
= 0;
7116 i
.types
[op
].bitfield
.disp16
= 0;
7117 i
.types
[op
].bitfield
.disp64
= 0;
7118 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7120 /* Must be 32 bit */
7121 i
.types
[op
].bitfield
.disp32
= 1;
7122 i
.types
[op
].bitfield
.disp32s
= 0;
7126 i
.types
[op
].bitfield
.disp32
= 0;
7127 i
.types
[op
].bitfield
.disp32s
= 1;
7129 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7133 /* RIP addressing for 64bit mode. */
7134 else if (i
.base_reg
->reg_num
== RegRip
||
7135 i
.base_reg
->reg_num
== RegEip
)
7137 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7138 i
.rm
.regmem
= NO_BASE_REGISTER
;
7139 i
.types
[op
].bitfield
.disp8
= 0;
7140 i
.types
[op
].bitfield
.disp16
= 0;
7141 i
.types
[op
].bitfield
.disp32
= 0;
7142 i
.types
[op
].bitfield
.disp32s
= 1;
7143 i
.types
[op
].bitfield
.disp64
= 0;
7144 i
.flags
[op
] |= Operand_PCrel
;
7145 if (! i
.disp_operands
)
7146 fake_zero_displacement
= 1;
7148 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7150 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7151 switch (i
.base_reg
->reg_num
)
7154 if (i
.index_reg
== 0)
7156 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7157 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7161 if (i
.index_reg
== 0)
7164 if (operand_type_check (i
.types
[op
], disp
) == 0)
7166 /* fake (%bp) into 0(%bp) */
7167 i
.types
[op
].bitfield
.disp8
= 1;
7168 fake_zero_displacement
= 1;
7171 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7172 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7174 default: /* (%si) -> 4 or (%di) -> 5 */
7175 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7177 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7179 else /* i.base_reg and 32/64 bit mode */
7181 if (flag_code
== CODE_64BIT
7182 && operand_type_check (i
.types
[op
], disp
))
7184 i
.types
[op
].bitfield
.disp16
= 0;
7185 i
.types
[op
].bitfield
.disp64
= 0;
7186 if (i
.prefix
[ADDR_PREFIX
] == 0)
7188 i
.types
[op
].bitfield
.disp32
= 0;
7189 i
.types
[op
].bitfield
.disp32s
= 1;
7193 i
.types
[op
].bitfield
.disp32
= 1;
7194 i
.types
[op
].bitfield
.disp32s
= 0;
7198 if (!i
.tm
.opcode_modifier
.vecsib
)
7199 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7200 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7202 i
.sib
.base
= i
.base_reg
->reg_num
;
7203 /* x86-64 ignores REX prefix bit here to avoid decoder
7205 if (!(i
.base_reg
->reg_flags
& RegRex
)
7206 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7207 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7209 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7211 fake_zero_displacement
= 1;
7212 i
.types
[op
].bitfield
.disp8
= 1;
7214 i
.sib
.scale
= i
.log2_scale_factor
;
7215 if (i
.index_reg
== 0)
7217 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7218 /* <disp>(%esp) becomes two byte modrm with no index
7219 register. We've already stored the code for esp
7220 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7221 Any base register besides %esp will not use the
7222 extra modrm byte. */
7223 i
.sib
.index
= NO_INDEX_REGISTER
;
7225 else if (!i
.tm
.opcode_modifier
.vecsib
)
7227 if (i
.index_reg
->reg_num
== RegEiz
7228 || i
.index_reg
->reg_num
== RegRiz
)
7229 i
.sib
.index
= NO_INDEX_REGISTER
;
7231 i
.sib
.index
= i
.index_reg
->reg_num
;
7232 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7233 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7238 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7239 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7243 if (!fake_zero_displacement
7247 fake_zero_displacement
= 1;
7248 if (i
.disp_encoding
== disp_encoding_8bit
)
7249 i
.types
[op
].bitfield
.disp8
= 1;
7251 i
.types
[op
].bitfield
.disp32
= 1;
7253 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7257 if (fake_zero_displacement
)
7259 /* Fakes a zero displacement assuming that i.types[op]
7260 holds the correct displacement size. */
7263 gas_assert (i
.op
[op
].disps
== 0);
7264 exp
= &disp_expressions
[i
.disp_operands
++];
7265 i
.op
[op
].disps
= exp
;
7266 exp
->X_op
= O_constant
;
7267 exp
->X_add_number
= 0;
7268 exp
->X_add_symbol
= (symbolS
*) 0;
7269 exp
->X_op_symbol
= (symbolS
*) 0;
7277 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7279 if (operand_type_check (i
.types
[0], imm
))
7280 i
.vex
.register_specifier
= NULL
;
7283 /* VEX.vvvv encodes one of the sources when the first
7284 operand is not an immediate. */
7285 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7286 i
.vex
.register_specifier
= i
.op
[0].regs
;
7288 i
.vex
.register_specifier
= i
.op
[1].regs
;
7291 /* Destination is a XMM register encoded in the ModRM.reg
7293 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7294 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7297 /* ModRM.rm and VEX.B encodes the other source. */
7298 if (!i
.mem_operands
)
7302 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7303 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7305 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7307 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7311 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7313 i
.vex
.register_specifier
= i
.op
[2].regs
;
7314 if (!i
.mem_operands
)
7317 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7318 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7322 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7323 (if any) based on i.tm.extension_opcode. Again, we must be
7324 careful to make sure that segment/control/debug/test/MMX
7325 registers are coded into the i.rm.reg field. */
7326 else if (i
.reg_operands
)
7329 unsigned int vex_reg
= ~0;
7331 for (op
= 0; op
< i
.operands
; op
++)
7332 if (i
.types
[op
].bitfield
.reg
7333 || i
.types
[op
].bitfield
.regmmx
7334 || i
.types
[op
].bitfield
.regsimd
7335 || i
.types
[op
].bitfield
.regbnd
7336 || i
.types
[op
].bitfield
.regmask
7337 || i
.types
[op
].bitfield
.sreg2
7338 || i
.types
[op
].bitfield
.sreg3
7339 || i
.types
[op
].bitfield
.control
7340 || i
.types
[op
].bitfield
.debug
7341 || i
.types
[op
].bitfield
.test
)
7346 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7348 /* For instructions with VexNDS, the register-only
7349 source operand is encoded in VEX prefix. */
7350 gas_assert (mem
!= (unsigned int) ~0);
7355 gas_assert (op
< i
.operands
);
7359 /* Check register-only source operand when two source
7360 operands are swapped. */
7361 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7362 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7366 gas_assert (mem
== (vex_reg
+ 1)
7367 && op
< i
.operands
);
7372 gas_assert (vex_reg
< i
.operands
);
7376 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7378 /* For instructions with VexNDD, the register destination
7379 is encoded in VEX prefix. */
7380 if (i
.mem_operands
== 0)
7382 /* There is no memory operand. */
7383 gas_assert ((op
+ 2) == i
.operands
);
7388 /* There are only 2 non-immediate operands. */
7389 gas_assert (op
< i
.imm_operands
+ 2
7390 && i
.operands
== i
.imm_operands
+ 2);
7391 vex_reg
= i
.imm_operands
+ 1;
7395 gas_assert (op
< i
.operands
);
7397 if (vex_reg
!= (unsigned int) ~0)
7399 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7401 if ((!type
->bitfield
.reg
7402 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7403 && !type
->bitfield
.regsimd
7404 && !operand_type_equal (type
, ®mask
))
7407 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7410 /* Don't set OP operand twice. */
7413 /* If there is an extension opcode to put here, the
7414 register number must be put into the regmem field. */
7415 if (i
.tm
.extension_opcode
!= None
)
7417 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7418 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7420 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7425 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7426 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7428 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7433 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7434 must set it to 3 to indicate this is a register operand
7435 in the regmem field. */
7436 if (!i
.mem_operands
)
7440 /* Fill in i.rm.reg field with extension opcode (if any). */
7441 if (i
.tm
.extension_opcode
!= None
)
7442 i
.rm
.reg
= i
.tm
.extension_opcode
;
7448 output_branch (void)
7454 relax_substateT subtype
;
7458 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7459 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7462 if (i
.prefix
[DATA_PREFIX
] != 0)
7468 /* Pentium4 branch hints. */
7469 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7470 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7475 if (i
.prefix
[REX_PREFIX
] != 0)
7481 /* BND prefixed jump. */
7482 if (i
.prefix
[BND_PREFIX
] != 0)
7484 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7488 if (i
.prefixes
!= 0 && !intel_syntax
)
7489 as_warn (_("skipping prefixes on this instruction"));
7491 /* It's always a symbol; End frag & setup for relax.
7492 Make sure there is enough room in this frag for the largest
7493 instruction we may generate in md_convert_frag. This is 2
7494 bytes for the opcode and room for the prefix and largest
7496 frag_grow (prefix
+ 2 + 4);
7497 /* Prefix and 1 opcode byte go in fr_fix. */
7498 p
= frag_more (prefix
+ 1);
7499 if (i
.prefix
[DATA_PREFIX
] != 0)
7500 *p
++ = DATA_PREFIX_OPCODE
;
7501 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7502 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7503 *p
++ = i
.prefix
[SEG_PREFIX
];
7504 if (i
.prefix
[REX_PREFIX
] != 0)
7505 *p
++ = i
.prefix
[REX_PREFIX
];
7506 *p
= i
.tm
.base_opcode
;
7508 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7509 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7510 else if (cpu_arch_flags
.bitfield
.cpui386
)
7511 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7513 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7516 sym
= i
.op
[0].disps
->X_add_symbol
;
7517 off
= i
.op
[0].disps
->X_add_number
;
7519 if (i
.op
[0].disps
->X_op
!= O_constant
7520 && i
.op
[0].disps
->X_op
!= O_symbol
)
7522 /* Handle complex expressions. */
7523 sym
= make_expr_symbol (i
.op
[0].disps
);
7527 /* 1 possible extra opcode + 4 byte displacement go in var part.
7528 Pass reloc in fr_var. */
7529 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7533 /* Return TRUE iff PLT32 relocation should be used for branching to
7537 need_plt32_p (symbolS
*s
)
7539 /* PLT32 relocation is ELF only. */
7543 /* Since there is no need to prepare for PLT branch on x86-64, we
7544 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7545 be used as a marker for 32-bit PC-relative branches. */
7549 /* Weak or undefined symbol need PLT32 relocation. */
7550 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7553 /* Non-global symbol doesn't need PLT32 relocation. */
7554 if (! S_IS_EXTERNAL (s
))
7557 /* Other global symbols need PLT32 relocation. NB: Symbol with
7558 non-default visibilities are treated as normal global symbol
7559 so that PLT32 relocation can be used as a marker for 32-bit
7560 PC-relative branches. It is useful for linker relaxation. */
7571 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7573 if (i
.tm
.opcode_modifier
.jumpbyte
)
7575 /* This is a loop or jecxz type instruction. */
7577 if (i
.prefix
[ADDR_PREFIX
] != 0)
7579 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7582 /* Pentium4 branch hints. */
7583 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7584 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7586 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7595 if (flag_code
== CODE_16BIT
)
7598 if (i
.prefix
[DATA_PREFIX
] != 0)
7600 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7610 if (i
.prefix
[REX_PREFIX
] != 0)
7612 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7616 /* BND prefixed jump. */
7617 if (i
.prefix
[BND_PREFIX
] != 0)
7619 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7623 if (i
.prefixes
!= 0 && !intel_syntax
)
7624 as_warn (_("skipping prefixes on this instruction"));
7626 p
= frag_more (i
.tm
.opcode_length
+ size
);
7627 switch (i
.tm
.opcode_length
)
7630 *p
++ = i
.tm
.base_opcode
>> 8;
7633 *p
++ = i
.tm
.base_opcode
;
7639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7641 && jump_reloc
== NO_RELOC
7642 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7643 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7646 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7648 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7649 i
.op
[0].disps
, 1, jump_reloc
);
7651 /* All jumps handled here are signed, but don't use a signed limit
7652 check for 32 and 16 bit jumps as we want to allow wrap around at
7653 4G and 64k respectively. */
7655 fixP
->fx_signed
= 1;
7659 output_interseg_jump (void)
7667 if (flag_code
== CODE_16BIT
)
7671 if (i
.prefix
[DATA_PREFIX
] != 0)
7677 if (i
.prefix
[REX_PREFIX
] != 0)
7687 if (i
.prefixes
!= 0 && !intel_syntax
)
7688 as_warn (_("skipping prefixes on this instruction"));
7690 /* 1 opcode; 2 segment; offset */
7691 p
= frag_more (prefix
+ 1 + 2 + size
);
7693 if (i
.prefix
[DATA_PREFIX
] != 0)
7694 *p
++ = DATA_PREFIX_OPCODE
;
7696 if (i
.prefix
[REX_PREFIX
] != 0)
7697 *p
++ = i
.prefix
[REX_PREFIX
];
7699 *p
++ = i
.tm
.base_opcode
;
7700 if (i
.op
[1].imms
->X_op
== O_constant
)
7702 offsetT n
= i
.op
[1].imms
->X_add_number
;
7705 && !fits_in_unsigned_word (n
)
7706 && !fits_in_signed_word (n
))
7708 as_bad (_("16-bit jump out of range"));
7711 md_number_to_chars (p
, n
, size
);
7714 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7715 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7716 if (i
.op
[0].imms
->X_op
!= O_constant
)
7717 as_bad (_("can't handle non absolute segment in `%s'"),
7719 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7725 fragS
*insn_start_frag
;
7726 offsetT insn_start_off
;
7728 /* Tie dwarf2 debug info to the address at the start of the insn.
7729 We can't do this after the insn has been output as the current
7730 frag may have been closed off. eg. by frag_var. */
7731 dwarf2_emit_insn (0);
7733 insn_start_frag
= frag_now
;
7734 insn_start_off
= frag_now_fix ();
7737 if (i
.tm
.opcode_modifier
.jump
)
7739 else if (i
.tm
.opcode_modifier
.jumpbyte
7740 || i
.tm
.opcode_modifier
.jumpdword
)
7742 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7743 output_interseg_jump ();
7746 /* Output normal instructions here. */
7750 unsigned int prefix
;
7753 && i
.tm
.base_opcode
== 0xfae
7755 && i
.imm_operands
== 1
7756 && (i
.op
[0].imms
->X_add_number
== 0xe8
7757 || i
.op
[0].imms
->X_add_number
== 0xf0
7758 || i
.op
[0].imms
->X_add_number
== 0xf8))
7760 /* Encode lfence, mfence, and sfence as
7761 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7762 offsetT val
= 0x240483f0ULL
;
7764 md_number_to_chars (p
, val
, 5);
7768 /* Some processors fail on LOCK prefix. This options makes
7769 assembler ignore LOCK prefix and serves as a workaround. */
7770 if (omit_lock_prefix
)
7772 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7774 i
.prefix
[LOCK_PREFIX
] = 0;
7777 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7778 don't need the explicit prefix. */
7779 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7781 switch (i
.tm
.opcode_length
)
7784 if (i
.tm
.base_opcode
& 0xff000000)
7786 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7787 add_prefix (prefix
);
7791 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7793 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7794 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7795 || prefix
!= REPE_PREFIX_OPCODE
7796 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7797 add_prefix (prefix
);
7803 /* Check for pseudo prefixes. */
7804 as_bad_where (insn_start_frag
->fr_file
,
7805 insn_start_frag
->fr_line
,
7806 _("pseudo prefix without instruction"));
7812 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7813 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7814 R_X86_64_GOTTPOFF relocation so that linker can safely
7815 perform IE->LE optimization. */
7816 if (x86_elf_abi
== X86_64_X32_ABI
7818 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7819 && i
.prefix
[REX_PREFIX
] == 0)
7820 add_prefix (REX_OPCODE
);
7823 /* The prefix bytes. */
7824 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7826 FRAG_APPEND_1_CHAR (*q
);
7830 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7835 /* REX byte is encoded in VEX prefix. */
7839 FRAG_APPEND_1_CHAR (*q
);
7842 /* There should be no other prefixes for instructions
7847 /* For EVEX instructions i.vrex should become 0 after
7848 build_evex_prefix. For VEX instructions upper 16 registers
7849 aren't available, so VREX should be 0. */
7852 /* Now the VEX prefix. */
7853 p
= frag_more (i
.vex
.length
);
7854 for (j
= 0; j
< i
.vex
.length
; j
++)
7855 p
[j
] = i
.vex
.bytes
[j
];
7858 /* Now the opcode; be careful about word order here! */
7859 if (i
.tm
.opcode_length
== 1)
7861 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7865 switch (i
.tm
.opcode_length
)
7869 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7870 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7874 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7884 /* Put out high byte first: can't use md_number_to_chars! */
7885 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7886 *p
= i
.tm
.base_opcode
& 0xff;
7889 /* Now the modrm byte and sib byte (if present). */
7890 if (i
.tm
.opcode_modifier
.modrm
)
7892 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7895 /* If i.rm.regmem == ESP (4)
7896 && i.rm.mode != (Register mode)
7898 ==> need second modrm byte. */
7899 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7901 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7902 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7904 | i
.sib
.scale
<< 6));
7907 if (i
.disp_operands
)
7908 output_disp (insn_start_frag
, insn_start_off
);
7911 output_imm (insn_start_frag
, insn_start_off
);
7917 pi ("" /*line*/, &i
);
7919 #endif /* DEBUG386 */
7922 /* Return the size of the displacement operand N. */
7925 disp_size (unsigned int n
)
7929 if (i
.types
[n
].bitfield
.disp64
)
7931 else if (i
.types
[n
].bitfield
.disp8
)
7933 else if (i
.types
[n
].bitfield
.disp16
)
7938 /* Return the size of the immediate operand N. */
7941 imm_size (unsigned int n
)
7944 if (i
.types
[n
].bitfield
.imm64
)
7946 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7948 else if (i
.types
[n
].bitfield
.imm16
)
7954 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7959 for (n
= 0; n
< i
.operands
; n
++)
7961 if (operand_type_check (i
.types
[n
], disp
))
7963 if (i
.op
[n
].disps
->X_op
== O_constant
)
7965 int size
= disp_size (n
);
7966 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7968 val
= offset_in_range (val
>> i
.memshift
, size
);
7969 p
= frag_more (size
);
7970 md_number_to_chars (p
, val
, size
);
7974 enum bfd_reloc_code_real reloc_type
;
7975 int size
= disp_size (n
);
7976 int sign
= i
.types
[n
].bitfield
.disp32s
;
7977 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7980 /* We can't have 8 bit displacement here. */
7981 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7983 /* The PC relative address is computed relative
7984 to the instruction boundary, so in case immediate
7985 fields follows, we need to adjust the value. */
7986 if (pcrel
&& i
.imm_operands
)
7991 for (n1
= 0; n1
< i
.operands
; n1
++)
7992 if (operand_type_check (i
.types
[n1
], imm
))
7994 /* Only one immediate is allowed for PC
7995 relative address. */
7996 gas_assert (sz
== 0);
7998 i
.op
[n
].disps
->X_add_number
-= sz
;
8000 /* We should find the immediate. */
8001 gas_assert (sz
!= 0);
8004 p
= frag_more (size
);
8005 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8007 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8008 && (((reloc_type
== BFD_RELOC_32
8009 || reloc_type
== BFD_RELOC_X86_64_32S
8010 || (reloc_type
== BFD_RELOC_64
8012 && (i
.op
[n
].disps
->X_op
== O_symbol
8013 || (i
.op
[n
].disps
->X_op
== O_add
8014 && ((symbol_get_value_expression
8015 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8017 || reloc_type
== BFD_RELOC_32_PCREL
))
8021 if (insn_start_frag
== frag_now
)
8022 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8027 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8028 for (fr
= insn_start_frag
->fr_next
;
8029 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8031 add
+= p
- frag_now
->fr_literal
;
8036 reloc_type
= BFD_RELOC_386_GOTPC
;
8037 i
.op
[n
].imms
->X_add_number
+= add
;
8039 else if (reloc_type
== BFD_RELOC_64
)
8040 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8042 /* Don't do the adjustment for x86-64, as there
8043 the pcrel addressing is relative to the _next_
8044 insn, and that is taken care of in other code. */
8045 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8047 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8048 size
, i
.op
[n
].disps
, pcrel
,
8050 /* Check for "call/jmp *mem", "mov mem, %reg",
8051 "test %reg, mem" and "binop mem, %reg" where binop
8052 is one of adc, add, and, cmp, or, sbb, sub, xor
8053 instructions. Always generate R_386_GOT32X for
8054 "sym*GOT" operand in 32-bit mode. */
8055 if ((generate_relax_relocations
8058 && i
.rm
.regmem
== 5))
8060 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8061 && ((i
.operands
== 1
8062 && i
.tm
.base_opcode
== 0xff
8063 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8065 && (i
.tm
.base_opcode
== 0x8b
8066 || i
.tm
.base_opcode
== 0x85
8067 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8071 fixP
->fx_tcbit
= i
.rex
!= 0;
8073 && (i
.base_reg
->reg_num
== RegRip
8074 || i
.base_reg
->reg_num
== RegEip
))
8075 fixP
->fx_tcbit2
= 1;
8078 fixP
->fx_tcbit2
= 1;
8086 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8091 for (n
= 0; n
< i
.operands
; n
++)
8093 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8094 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8097 if (operand_type_check (i
.types
[n
], imm
))
8099 if (i
.op
[n
].imms
->X_op
== O_constant
)
8101 int size
= imm_size (n
);
8104 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8106 p
= frag_more (size
);
8107 md_number_to_chars (p
, val
, size
);
8111 /* Not absolute_section.
8112 Need a 32-bit fixup (don't support 8bit
8113 non-absolute imms). Try to support other
8115 enum bfd_reloc_code_real reloc_type
;
8116 int size
= imm_size (n
);
8119 if (i
.types
[n
].bitfield
.imm32s
8120 && (i
.suffix
== QWORD_MNEM_SUFFIX
8121 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8126 p
= frag_more (size
);
8127 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8129 /* This is tough to explain. We end up with this one if we
8130 * have operands that look like
8131 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8132 * obtain the absolute address of the GOT, and it is strongly
8133 * preferable from a performance point of view to avoid using
8134 * a runtime relocation for this. The actual sequence of
8135 * instructions often look something like:
8140 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8142 * The call and pop essentially return the absolute address
8143 * of the label .L66 and store it in %ebx. The linker itself
8144 * will ultimately change the first operand of the addl so
8145 * that %ebx points to the GOT, but to keep things simple, the
8146 * .o file must have this operand set so that it generates not
8147 * the absolute address of .L66, but the absolute address of
8148 * itself. This allows the linker itself simply treat a GOTPC
8149 * relocation as asking for a pcrel offset to the GOT to be
8150 * added in, and the addend of the relocation is stored in the
8151 * operand field for the instruction itself.
8153 * Our job here is to fix the operand so that it would add
8154 * the correct offset so that %ebx would point to itself. The
8155 * thing that is tricky is that .-.L66 will point to the
8156 * beginning of the instruction, so we need to further modify
8157 * the operand so that it will point to itself. There are
8158 * other cases where you have something like:
8160 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8162 * and here no correction would be required. Internally in
8163 * the assembler we treat operands of this form as not being
8164 * pcrel since the '.' is explicitly mentioned, and I wonder
8165 * whether it would simplify matters to do it this way. Who
8166 * knows. In earlier versions of the PIC patches, the
8167 * pcrel_adjust field was used to store the correction, but
8168 * since the expression is not pcrel, I felt it would be
8169 * confusing to do it this way. */
8171 if ((reloc_type
== BFD_RELOC_32
8172 || reloc_type
== BFD_RELOC_X86_64_32S
8173 || reloc_type
== BFD_RELOC_64
)
8175 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8176 && (i
.op
[n
].imms
->X_op
== O_symbol
8177 || (i
.op
[n
].imms
->X_op
== O_add
8178 && ((symbol_get_value_expression
8179 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8184 if (insn_start_frag
== frag_now
)
8185 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8190 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8191 for (fr
= insn_start_frag
->fr_next
;
8192 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8194 add
+= p
- frag_now
->fr_literal
;
8198 reloc_type
= BFD_RELOC_386_GOTPC
;
8200 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8202 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8203 i
.op
[n
].imms
->X_add_number
+= add
;
8205 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8206 i
.op
[n
].imms
, 0, reloc_type
);
8212 /* x86_cons_fix_new is called via the expression parsing code when a
8213 reloc is needed. We use this hook to get the correct .got reloc. */
8214 static int cons_sign
= -1;
8217 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8218 expressionS
*exp
, bfd_reloc_code_real_type r
)
8220 r
= reloc (len
, 0, cons_sign
, r
);
8223 if (exp
->X_op
== O_secrel
)
8225 exp
->X_op
= O_symbol
;
8226 r
= BFD_RELOC_32_SECREL
;
8230 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8233 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8234 purpose of the `.dc.a' internal pseudo-op. */
8237 x86_address_bytes (void)
8239 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8241 return stdoutput
->arch_info
->bits_per_address
/ 8;
8244 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8246 # define lex_got(reloc, adjust, types) NULL
8248 /* Parse operands of the form
8249 <symbol>@GOTOFF+<nnn>
8250 and similar .plt or .got references.
8252 If we find one, set up the correct relocation in RELOC and copy the
8253 input string, minus the `@GOTOFF' into a malloc'd buffer for
8254 parsing by the calling routine. Return this buffer, and if ADJUST
8255 is non-null set it to the length of the string we removed from the
8256 input line. Otherwise return NULL. */
8258 lex_got (enum bfd_reloc_code_real
*rel
,
8260 i386_operand_type
*types
)
8262 /* Some of the relocations depend on the size of what field is to
8263 be relocated. But in our callers i386_immediate and i386_displacement
8264 we don't yet know the operand size (this will be set by insn
8265 matching). Hence we record the word32 relocation here,
8266 and adjust the reloc according to the real size in reloc(). */
8267 static const struct {
8270 const enum bfd_reloc_code_real rel
[2];
8271 const i386_operand_type types64
;
8273 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8274 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8276 OPERAND_TYPE_IMM32_64
},
8278 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8279 BFD_RELOC_X86_64_PLTOFF64
},
8280 OPERAND_TYPE_IMM64
},
8281 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8282 BFD_RELOC_X86_64_PLT32
},
8283 OPERAND_TYPE_IMM32_32S_DISP32
},
8284 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8285 BFD_RELOC_X86_64_GOTPLT64
},
8286 OPERAND_TYPE_IMM64_DISP64
},
8287 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8288 BFD_RELOC_X86_64_GOTOFF64
},
8289 OPERAND_TYPE_IMM64_DISP64
},
8290 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8291 BFD_RELOC_X86_64_GOTPCREL
},
8292 OPERAND_TYPE_IMM32_32S_DISP32
},
8293 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8294 BFD_RELOC_X86_64_TLSGD
},
8295 OPERAND_TYPE_IMM32_32S_DISP32
},
8296 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8297 _dummy_first_bfd_reloc_code_real
},
8298 OPERAND_TYPE_NONE
},
8299 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8300 BFD_RELOC_X86_64_TLSLD
},
8301 OPERAND_TYPE_IMM32_32S_DISP32
},
8302 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8303 BFD_RELOC_X86_64_GOTTPOFF
},
8304 OPERAND_TYPE_IMM32_32S_DISP32
},
8305 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8306 BFD_RELOC_X86_64_TPOFF32
},
8307 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8308 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8309 _dummy_first_bfd_reloc_code_real
},
8310 OPERAND_TYPE_NONE
},
8311 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8312 BFD_RELOC_X86_64_DTPOFF32
},
8313 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8314 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8315 _dummy_first_bfd_reloc_code_real
},
8316 OPERAND_TYPE_NONE
},
8317 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8318 _dummy_first_bfd_reloc_code_real
},
8319 OPERAND_TYPE_NONE
},
8320 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8321 BFD_RELOC_X86_64_GOT32
},
8322 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8323 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8324 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8325 OPERAND_TYPE_IMM32_32S_DISP32
},
8326 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8327 BFD_RELOC_X86_64_TLSDESC_CALL
},
8328 OPERAND_TYPE_IMM32_32S_DISP32
},
8333 #if defined (OBJ_MAYBE_ELF)
8338 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8339 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8342 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8344 int len
= gotrel
[j
].len
;
8345 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8347 if (gotrel
[j
].rel
[object_64bit
] != 0)
8350 char *tmpbuf
, *past_reloc
;
8352 *rel
= gotrel
[j
].rel
[object_64bit
];
8356 if (flag_code
!= CODE_64BIT
)
8358 types
->bitfield
.imm32
= 1;
8359 types
->bitfield
.disp32
= 1;
8362 *types
= gotrel
[j
].types64
;
8365 if (j
!= 0 && GOT_symbol
== NULL
)
8366 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8368 /* The length of the first part of our input line. */
8369 first
= cp
- input_line_pointer
;
8371 /* The second part goes from after the reloc token until
8372 (and including) an end_of_line char or comma. */
8373 past_reloc
= cp
+ 1 + len
;
8375 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8377 second
= cp
+ 1 - past_reloc
;
8379 /* Allocate and copy string. The trailing NUL shouldn't
8380 be necessary, but be safe. */
8381 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8382 memcpy (tmpbuf
, input_line_pointer
, first
);
8383 if (second
!= 0 && *past_reloc
!= ' ')
8384 /* Replace the relocation token with ' ', so that
8385 errors like foo@GOTOFF1 will be detected. */
8386 tmpbuf
[first
++] = ' ';
8388 /* Increment length by 1 if the relocation token is
8393 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8394 tmpbuf
[first
+ second
] = '\0';
8398 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8399 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8404 /* Might be a symbol version string. Don't as_bad here. */
8413 /* Parse operands of the form
8414 <symbol>@SECREL32+<nnn>
8416 If we find one, set up the correct relocation in RELOC and copy the
8417 input string, minus the `@SECREL32' into a malloc'd buffer for
8418 parsing by the calling routine. Return this buffer, and if ADJUST
8419 is non-null set it to the length of the string we removed from the
8420 input line. Otherwise return NULL.
8422 This function is copied from the ELF version above adjusted for PE targets. */
8425 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8426 int *adjust ATTRIBUTE_UNUSED
,
8427 i386_operand_type
*types
)
8433 const enum bfd_reloc_code_real rel
[2];
8434 const i386_operand_type types64
;
8438 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8439 BFD_RELOC_32_SECREL
},
8440 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8446 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8447 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8450 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8452 int len
= gotrel
[j
].len
;
8454 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8456 if (gotrel
[j
].rel
[object_64bit
] != 0)
8459 char *tmpbuf
, *past_reloc
;
8461 *rel
= gotrel
[j
].rel
[object_64bit
];
8467 if (flag_code
!= CODE_64BIT
)
8469 types
->bitfield
.imm32
= 1;
8470 types
->bitfield
.disp32
= 1;
8473 *types
= gotrel
[j
].types64
;
8476 /* The length of the first part of our input line. */
8477 first
= cp
- input_line_pointer
;
8479 /* The second part goes from after the reloc token until
8480 (and including) an end_of_line char or comma. */
8481 past_reloc
= cp
+ 1 + len
;
8483 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8485 second
= cp
+ 1 - past_reloc
;
8487 /* Allocate and copy string. The trailing NUL shouldn't
8488 be necessary, but be safe. */
8489 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8490 memcpy (tmpbuf
, input_line_pointer
, first
);
8491 if (second
!= 0 && *past_reloc
!= ' ')
8492 /* Replace the relocation token with ' ', so that
8493 errors like foo@SECLREL321 will be detected. */
8494 tmpbuf
[first
++] = ' ';
8495 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8496 tmpbuf
[first
+ second
] = '\0';
8500 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8501 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8506 /* Might be a symbol version string. Don't as_bad here. */
8512 bfd_reloc_code_real_type
8513 x86_cons (expressionS
*exp
, int size
)
8515 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8517 intel_syntax
= -intel_syntax
;
8520 if (size
== 4 || (object_64bit
&& size
== 8))
8522 /* Handle @GOTOFF and the like in an expression. */
8524 char *gotfree_input_line
;
8527 save
= input_line_pointer
;
8528 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8529 if (gotfree_input_line
)
8530 input_line_pointer
= gotfree_input_line
;
8534 if (gotfree_input_line
)
8536 /* expression () has merrily parsed up to the end of line,
8537 or a comma - in the wrong buffer. Transfer how far
8538 input_line_pointer has moved to the right buffer. */
8539 input_line_pointer
= (save
8540 + (input_line_pointer
- gotfree_input_line
)
8542 free (gotfree_input_line
);
8543 if (exp
->X_op
== O_constant
8544 || exp
->X_op
== O_absent
8545 || exp
->X_op
== O_illegal
8546 || exp
->X_op
== O_register
8547 || exp
->X_op
== O_big
)
8549 char c
= *input_line_pointer
;
8550 *input_line_pointer
= 0;
8551 as_bad (_("missing or invalid expression `%s'"), save
);
8552 *input_line_pointer
= c
;
8559 intel_syntax
= -intel_syntax
;
8562 i386_intel_simplify (exp
);
8568 signed_cons (int size
)
8570 if (flag_code
== CODE_64BIT
)
8578 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8585 if (exp
.X_op
== O_symbol
)
8586 exp
.X_op
= O_secrel
;
8588 emit_expr (&exp
, 4);
8590 while (*input_line_pointer
++ == ',');
8592 input_line_pointer
--;
8593 demand_empty_rest_of_line ();
8597 /* Handle Vector operations. */
8600 check_VecOperations (char *op_string
, char *op_end
)
8602 const reg_entry
*mask
;
8607 && (op_end
== NULL
|| op_string
< op_end
))
8610 if (*op_string
== '{')
8614 /* Check broadcasts. */
8615 if (strncmp (op_string
, "1to", 3) == 0)
8620 goto duplicated_vec_op
;
8623 if (*op_string
== '8')
8625 else if (*op_string
== '4')
8627 else if (*op_string
== '2')
8629 else if (*op_string
== '1'
8630 && *(op_string
+1) == '6')
8637 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8642 broadcast_op
.type
= bcst_type
;
8643 broadcast_op
.operand
= this_operand
;
8644 broadcast_op
.bytes
= 0;
8645 i
.broadcast
= &broadcast_op
;
8647 /* Check masking operation. */
8648 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8650 /* k0 can't be used for write mask. */
8651 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8653 as_bad (_("`%s%s' can't be used for write mask"),
8654 register_prefix
, mask
->reg_name
);
8660 mask_op
.mask
= mask
;
8661 mask_op
.zeroing
= 0;
8662 mask_op
.operand
= this_operand
;
8668 goto duplicated_vec_op
;
8670 i
.mask
->mask
= mask
;
8672 /* Only "{z}" is allowed here. No need to check
8673 zeroing mask explicitly. */
8674 if (i
.mask
->operand
!= this_operand
)
8676 as_bad (_("invalid write mask `%s'"), saved
);
8683 /* Check zeroing-flag for masking operation. */
8684 else if (*op_string
== 'z')
8688 mask_op
.mask
= NULL
;
8689 mask_op
.zeroing
= 1;
8690 mask_op
.operand
= this_operand
;
8695 if (i
.mask
->zeroing
)
8698 as_bad (_("duplicated `%s'"), saved
);
8702 i
.mask
->zeroing
= 1;
8704 /* Only "{%k}" is allowed here. No need to check mask
8705 register explicitly. */
8706 if (i
.mask
->operand
!= this_operand
)
8708 as_bad (_("invalid zeroing-masking `%s'"),
8717 goto unknown_vec_op
;
8719 if (*op_string
!= '}')
8721 as_bad (_("missing `}' in `%s'"), saved
);
8726 /* Strip whitespace since the addition of pseudo prefixes
8727 changed how the scrubber treats '{'. */
8728 if (is_space_char (*op_string
))
8734 /* We don't know this one. */
8735 as_bad (_("unknown vector operation: `%s'"), saved
);
8739 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8741 as_bad (_("zeroing-masking only allowed with write mask"));
8749 i386_immediate (char *imm_start
)
8751 char *save_input_line_pointer
;
8752 char *gotfree_input_line
;
8755 i386_operand_type types
;
8757 operand_type_set (&types
, ~0);
8759 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8761 as_bad (_("at most %d immediate operands are allowed"),
8762 MAX_IMMEDIATE_OPERANDS
);
8766 exp
= &im_expressions
[i
.imm_operands
++];
8767 i
.op
[this_operand
].imms
= exp
;
8769 if (is_space_char (*imm_start
))
8772 save_input_line_pointer
= input_line_pointer
;
8773 input_line_pointer
= imm_start
;
8775 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8776 if (gotfree_input_line
)
8777 input_line_pointer
= gotfree_input_line
;
8779 exp_seg
= expression (exp
);
8783 /* Handle vector operations. */
8784 if (*input_line_pointer
== '{')
8786 input_line_pointer
= check_VecOperations (input_line_pointer
,
8788 if (input_line_pointer
== NULL
)
8792 if (*input_line_pointer
)
8793 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8795 input_line_pointer
= save_input_line_pointer
;
8796 if (gotfree_input_line
)
8798 free (gotfree_input_line
);
8800 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8801 exp
->X_op
= O_illegal
;
8804 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8808 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8809 i386_operand_type types
, const char *imm_start
)
8811 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8814 as_bad (_("missing or invalid immediate expression `%s'"),
8818 else if (exp
->X_op
== O_constant
)
8820 /* Size it properly later. */
8821 i
.types
[this_operand
].bitfield
.imm64
= 1;
8822 /* If not 64bit, sign extend val. */
8823 if (flag_code
!= CODE_64BIT
8824 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8826 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8828 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8829 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8830 && exp_seg
!= absolute_section
8831 && exp_seg
!= text_section
8832 && exp_seg
!= data_section
8833 && exp_seg
!= bss_section
8834 && exp_seg
!= undefined_section
8835 && !bfd_is_com_section (exp_seg
))
8837 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8841 else if (!intel_syntax
&& exp_seg
== reg_section
)
8844 as_bad (_("illegal immediate register operand %s"), imm_start
);
8849 /* This is an address. The size of the address will be
8850 determined later, depending on destination register,
8851 suffix, or the default for the section. */
8852 i
.types
[this_operand
].bitfield
.imm8
= 1;
8853 i
.types
[this_operand
].bitfield
.imm16
= 1;
8854 i
.types
[this_operand
].bitfield
.imm32
= 1;
8855 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8856 i
.types
[this_operand
].bitfield
.imm64
= 1;
8857 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8865 i386_scale (char *scale
)
8868 char *save
= input_line_pointer
;
8870 input_line_pointer
= scale
;
8871 val
= get_absolute_expression ();
8876 i
.log2_scale_factor
= 0;
8879 i
.log2_scale_factor
= 1;
8882 i
.log2_scale_factor
= 2;
8885 i
.log2_scale_factor
= 3;
8889 char sep
= *input_line_pointer
;
8891 *input_line_pointer
= '\0';
8892 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8894 *input_line_pointer
= sep
;
8895 input_line_pointer
= save
;
8899 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8901 as_warn (_("scale factor of %d without an index register"),
8902 1 << i
.log2_scale_factor
);
8903 i
.log2_scale_factor
= 0;
8905 scale
= input_line_pointer
;
8906 input_line_pointer
= save
;
8911 i386_displacement (char *disp_start
, char *disp_end
)
8915 char *save_input_line_pointer
;
8916 char *gotfree_input_line
;
8918 i386_operand_type bigdisp
, types
= anydisp
;
8921 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8923 as_bad (_("at most %d displacement operands are allowed"),
8924 MAX_MEMORY_OPERANDS
);
8928 operand_type_set (&bigdisp
, 0);
8929 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8930 || (!current_templates
->start
->opcode_modifier
.jump
8931 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8933 bigdisp
.bitfield
.disp32
= 1;
8934 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8935 if (flag_code
== CODE_64BIT
)
8939 bigdisp
.bitfield
.disp32s
= 1;
8940 bigdisp
.bitfield
.disp64
= 1;
8943 else if ((flag_code
== CODE_16BIT
) ^ override
)
8945 bigdisp
.bitfield
.disp32
= 0;
8946 bigdisp
.bitfield
.disp16
= 1;
8951 /* For PC-relative branches, the width of the displacement
8952 is dependent upon data size, not address size. */
8953 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8954 if (flag_code
== CODE_64BIT
)
8956 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8957 bigdisp
.bitfield
.disp16
= 1;
8960 bigdisp
.bitfield
.disp32
= 1;
8961 bigdisp
.bitfield
.disp32s
= 1;
8967 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8969 : LONG_MNEM_SUFFIX
));
8970 bigdisp
.bitfield
.disp32
= 1;
8971 if ((flag_code
== CODE_16BIT
) ^ override
)
8973 bigdisp
.bitfield
.disp32
= 0;
8974 bigdisp
.bitfield
.disp16
= 1;
8978 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8981 exp
= &disp_expressions
[i
.disp_operands
];
8982 i
.op
[this_operand
].disps
= exp
;
8984 save_input_line_pointer
= input_line_pointer
;
8985 input_line_pointer
= disp_start
;
8986 END_STRING_AND_SAVE (disp_end
);
8988 #ifndef GCC_ASM_O_HACK
8989 #define GCC_ASM_O_HACK 0
8992 END_STRING_AND_SAVE (disp_end
+ 1);
8993 if (i
.types
[this_operand
].bitfield
.baseIndex
8994 && displacement_string_end
[-1] == '+')
8996 /* This hack is to avoid a warning when using the "o"
8997 constraint within gcc asm statements.
9000 #define _set_tssldt_desc(n,addr,limit,type) \
9001 __asm__ __volatile__ ( \
9003 "movw %w1,2+%0\n\t" \
9005 "movb %b1,4+%0\n\t" \
9006 "movb %4,5+%0\n\t" \
9007 "movb $0,6+%0\n\t" \
9008 "movb %h1,7+%0\n\t" \
9010 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9012 This works great except that the output assembler ends
9013 up looking a bit weird if it turns out that there is
9014 no offset. You end up producing code that looks like:
9027 So here we provide the missing zero. */
9029 *displacement_string_end
= '0';
9032 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9033 if (gotfree_input_line
)
9034 input_line_pointer
= gotfree_input_line
;
9036 exp_seg
= expression (exp
);
9039 if (*input_line_pointer
)
9040 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9042 RESTORE_END_STRING (disp_end
+ 1);
9044 input_line_pointer
= save_input_line_pointer
;
9045 if (gotfree_input_line
)
9047 free (gotfree_input_line
);
9049 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9050 exp
->X_op
= O_illegal
;
9053 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9055 RESTORE_END_STRING (disp_end
);
9061 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9062 i386_operand_type types
, const char *disp_start
)
9064 i386_operand_type bigdisp
;
9067 /* We do this to make sure that the section symbol is in
9068 the symbol table. We will ultimately change the relocation
9069 to be relative to the beginning of the section. */
9070 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9071 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9072 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9074 if (exp
->X_op
!= O_symbol
)
9077 if (S_IS_LOCAL (exp
->X_add_symbol
)
9078 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9079 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9080 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9081 exp
->X_op
= O_subtract
;
9082 exp
->X_op_symbol
= GOT_symbol
;
9083 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9084 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9085 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9086 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9088 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9091 else if (exp
->X_op
== O_absent
9092 || exp
->X_op
== O_illegal
9093 || exp
->X_op
== O_big
)
9096 as_bad (_("missing or invalid displacement expression `%s'"),
9101 else if (flag_code
== CODE_64BIT
9102 && !i
.prefix
[ADDR_PREFIX
]
9103 && exp
->X_op
== O_constant
)
9105 /* Since displacement is signed extended to 64bit, don't allow
9106 disp32 and turn off disp32s if they are out of range. */
9107 i
.types
[this_operand
].bitfield
.disp32
= 0;
9108 if (!fits_in_signed_long (exp
->X_add_number
))
9110 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9111 if (i
.types
[this_operand
].bitfield
.baseindex
)
9113 as_bad (_("0x%lx out range of signed 32bit displacement"),
9114 (long) exp
->X_add_number
);
9120 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9121 else if (exp
->X_op
!= O_constant
9122 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9123 && exp_seg
!= absolute_section
9124 && exp_seg
!= text_section
9125 && exp_seg
!= data_section
9126 && exp_seg
!= bss_section
9127 && exp_seg
!= undefined_section
9128 && !bfd_is_com_section (exp_seg
))
9130 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9135 /* Check if this is a displacement only operand. */
9136 bigdisp
= i
.types
[this_operand
];
9137 bigdisp
.bitfield
.disp8
= 0;
9138 bigdisp
.bitfield
.disp16
= 0;
9139 bigdisp
.bitfield
.disp32
= 0;
9140 bigdisp
.bitfield
.disp32s
= 0;
9141 bigdisp
.bitfield
.disp64
= 0;
9142 if (operand_type_all_zero (&bigdisp
))
9143 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9149 /* Return the active addressing mode, taking address override and
9150 registers forming the address into consideration. Update the
9151 address override prefix if necessary. */
9153 static enum flag_code
9154 i386_addressing_mode (void)
9156 enum flag_code addr_mode
;
9158 if (i
.prefix
[ADDR_PREFIX
])
9159 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9162 addr_mode
= flag_code
;
9164 #if INFER_ADDR_PREFIX
9165 if (i
.mem_operands
== 0)
9167 /* Infer address prefix from the first memory operand. */
9168 const reg_entry
*addr_reg
= i
.base_reg
;
9170 if (addr_reg
== NULL
)
9171 addr_reg
= i
.index_reg
;
9175 if (addr_reg
->reg_num
== RegEip
9176 || addr_reg
->reg_num
== RegEiz
9177 || addr_reg
->reg_type
.bitfield
.dword
)
9178 addr_mode
= CODE_32BIT
;
9179 else if (flag_code
!= CODE_64BIT
9180 && addr_reg
->reg_type
.bitfield
.word
)
9181 addr_mode
= CODE_16BIT
;
9183 if (addr_mode
!= flag_code
)
9185 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9187 /* Change the size of any displacement too. At most one
9188 of Disp16 or Disp32 is set.
9189 FIXME. There doesn't seem to be any real need for
9190 separate Disp16 and Disp32 flags. The same goes for
9191 Imm16 and Imm32. Removing them would probably clean
9192 up the code quite a lot. */
9193 if (flag_code
!= CODE_64BIT
9194 && (i
.types
[this_operand
].bitfield
.disp16
9195 || i
.types
[this_operand
].bitfield
.disp32
))
9196 i
.types
[this_operand
]
9197 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9207 /* Make sure the memory operand we've been dealt is valid.
9208 Return 1 on success, 0 on a failure. */
9211 i386_index_check (const char *operand_string
)
9213 const char *kind
= "base/index";
9214 enum flag_code addr_mode
= i386_addressing_mode ();
9216 if (current_templates
->start
->opcode_modifier
.isstring
9217 && !current_templates
->start
->opcode_modifier
.immext
9218 && (current_templates
->end
[-1].opcode_modifier
.isstring
9221 /* Memory operands of string insns are special in that they only allow
9222 a single register (rDI, rSI, or rBX) as their memory address. */
9223 const reg_entry
*expected_reg
;
9224 static const char *di_si
[][2] =
9230 static const char *bx
[] = { "ebx", "bx", "rbx" };
9232 kind
= "string address";
9234 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9236 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9238 if (!type
.bitfield
.baseindex
9239 || ((!i
.mem_operands
!= !intel_syntax
)
9240 && current_templates
->end
[-1].operand_types
[1]
9241 .bitfield
.baseindex
))
9242 type
= current_templates
->end
[-1].operand_types
[1];
9243 expected_reg
= hash_find (reg_hash
,
9244 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9248 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9250 if (i
.base_reg
!= expected_reg
9252 || operand_type_check (i
.types
[this_operand
], disp
))
9254 /* The second memory operand must have the same size as
9258 && !((addr_mode
== CODE_64BIT
9259 && i
.base_reg
->reg_type
.bitfield
.qword
)
9260 || (addr_mode
== CODE_32BIT
9261 ? i
.base_reg
->reg_type
.bitfield
.dword
9262 : i
.base_reg
->reg_type
.bitfield
.word
)))
9265 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9267 intel_syntax
? '[' : '(',
9269 expected_reg
->reg_name
,
9270 intel_syntax
? ']' : ')');
9277 as_bad (_("`%s' is not a valid %s expression"),
9278 operand_string
, kind
);
9283 if (addr_mode
!= CODE_16BIT
)
9285 /* 32-bit/64-bit checks. */
9287 && (addr_mode
== CODE_64BIT
9288 ? !i
.base_reg
->reg_type
.bitfield
.qword
9289 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9291 || (i
.base_reg
->reg_num
9292 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9294 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9295 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9296 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9297 && ((addr_mode
== CODE_64BIT
9298 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9299 || i
.index_reg
->reg_num
== RegRiz
)
9300 : !(i
.index_reg
->reg_type
.bitfield
.dword
9301 || i
.index_reg
->reg_num
== RegEiz
))
9302 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9305 /* bndmk, bndldx, and bndstx have special restrictions. */
9306 if (current_templates
->start
->base_opcode
== 0xf30f1b
9307 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9309 /* They cannot use RIP-relative addressing. */
9310 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9312 as_bad (_("`%s' cannot be used here"), operand_string
);
9316 /* bndldx and bndstx ignore their scale factor. */
9317 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9318 && i
.log2_scale_factor
)
9319 as_warn (_("register scaling is being ignored here"));
9324 /* 16-bit checks. */
9326 && (!i
.base_reg
->reg_type
.bitfield
.word
9327 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9329 && (!i
.index_reg
->reg_type
.bitfield
.word
9330 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9332 && i
.base_reg
->reg_num
< 6
9333 && i
.index_reg
->reg_num
>= 6
9334 && i
.log2_scale_factor
== 0))))
9341 /* Handle vector immediates. */
9344 RC_SAE_immediate (const char *imm_start
)
9346 unsigned int match_found
, j
;
9347 const char *pstr
= imm_start
;
9355 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9357 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9361 rc_op
.type
= RC_NamesTable
[j
].type
;
9362 rc_op
.operand
= this_operand
;
9363 i
.rounding
= &rc_op
;
9367 as_bad (_("duplicated `%s'"), imm_start
);
9370 pstr
+= RC_NamesTable
[j
].len
;
9380 as_bad (_("Missing '}': '%s'"), imm_start
);
9383 /* RC/SAE immediate string should contain nothing more. */;
9386 as_bad (_("Junk after '}': '%s'"), imm_start
);
9390 exp
= &im_expressions
[i
.imm_operands
++];
9391 i
.op
[this_operand
].imms
= exp
;
9393 exp
->X_op
= O_constant
;
9394 exp
->X_add_number
= 0;
9395 exp
->X_add_symbol
= (symbolS
*) 0;
9396 exp
->X_op_symbol
= (symbolS
*) 0;
9398 i
.types
[this_operand
].bitfield
.imm8
= 1;
9402 /* Only string instructions can have a second memory operand, so
9403 reduce current_templates to just those if it contains any. */
9405 maybe_adjust_templates (void)
9407 const insn_template
*t
;
9409 gas_assert (i
.mem_operands
== 1);
9411 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9412 if (t
->opcode_modifier
.isstring
)
9415 if (t
< current_templates
->end
)
9417 static templates aux_templates
;
9418 bfd_boolean recheck
;
9420 aux_templates
.start
= t
;
9421 for (; t
< current_templates
->end
; ++t
)
9422 if (!t
->opcode_modifier
.isstring
)
9424 aux_templates
.end
= t
;
9426 /* Determine whether to re-check the first memory operand. */
9427 recheck
= (aux_templates
.start
!= current_templates
->start
9428 || t
!= current_templates
->end
);
9430 current_templates
= &aux_templates
;
9435 if (i
.memop1_string
!= NULL
9436 && i386_index_check (i
.memop1_string
) == 0)
9445 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9449 i386_att_operand (char *operand_string
)
9453 char *op_string
= operand_string
;
9455 if (is_space_char (*op_string
))
9458 /* We check for an absolute prefix (differentiating,
9459 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9460 if (*op_string
== ABSOLUTE_PREFIX
)
9463 if (is_space_char (*op_string
))
9465 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9468 /* Check if operand is a register. */
9469 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9471 i386_operand_type temp
;
9473 /* Check for a segment override by searching for ':' after a
9474 segment register. */
9476 if (is_space_char (*op_string
))
9478 if (*op_string
== ':'
9479 && (r
->reg_type
.bitfield
.sreg2
9480 || r
->reg_type
.bitfield
.sreg3
))
9485 i
.seg
[i
.mem_operands
] = &es
;
9488 i
.seg
[i
.mem_operands
] = &cs
;
9491 i
.seg
[i
.mem_operands
] = &ss
;
9494 i
.seg
[i
.mem_operands
] = &ds
;
9497 i
.seg
[i
.mem_operands
] = &fs
;
9500 i
.seg
[i
.mem_operands
] = &gs
;
9504 /* Skip the ':' and whitespace. */
9506 if (is_space_char (*op_string
))
9509 if (!is_digit_char (*op_string
)
9510 && !is_identifier_char (*op_string
)
9511 && *op_string
!= '('
9512 && *op_string
!= ABSOLUTE_PREFIX
)
9514 as_bad (_("bad memory operand `%s'"), op_string
);
9517 /* Handle case of %es:*foo. */
9518 if (*op_string
== ABSOLUTE_PREFIX
)
9521 if (is_space_char (*op_string
))
9523 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9525 goto do_memory_reference
;
9528 /* Handle vector operations. */
9529 if (*op_string
== '{')
9531 op_string
= check_VecOperations (op_string
, NULL
);
9532 if (op_string
== NULL
)
9538 as_bad (_("junk `%s' after register"), op_string
);
9542 temp
.bitfield
.baseindex
= 0;
9543 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9545 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9546 i
.op
[this_operand
].regs
= r
;
9549 else if (*op_string
== REGISTER_PREFIX
)
9551 as_bad (_("bad register name `%s'"), op_string
);
9554 else if (*op_string
== IMMEDIATE_PREFIX
)
9557 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9559 as_bad (_("immediate operand illegal with absolute jump"));
9562 if (!i386_immediate (op_string
))
9565 else if (RC_SAE_immediate (operand_string
))
9567 /* If it is a RC or SAE immediate, do nothing. */
9570 else if (is_digit_char (*op_string
)
9571 || is_identifier_char (*op_string
)
9572 || *op_string
== '"'
9573 || *op_string
== '(')
9575 /* This is a memory reference of some sort. */
9578 /* Start and end of displacement string expression (if found). */
9579 char *displacement_string_start
;
9580 char *displacement_string_end
;
9583 do_memory_reference
:
9584 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9586 if ((i
.mem_operands
== 1
9587 && !current_templates
->start
->opcode_modifier
.isstring
)
9588 || i
.mem_operands
== 2)
9590 as_bad (_("too many memory references for `%s'"),
9591 current_templates
->start
->name
);
9595 /* Check for base index form. We detect the base index form by
9596 looking for an ')' at the end of the operand, searching
9597 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9599 base_string
= op_string
+ strlen (op_string
);
9601 /* Handle vector operations. */
9602 vop_start
= strchr (op_string
, '{');
9603 if (vop_start
&& vop_start
< base_string
)
9605 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9607 base_string
= vop_start
;
9611 if (is_space_char (*base_string
))
9614 /* If we only have a displacement, set-up for it to be parsed later. */
9615 displacement_string_start
= op_string
;
9616 displacement_string_end
= base_string
+ 1;
9618 if (*base_string
== ')')
9621 unsigned int parens_balanced
= 1;
9622 /* We've already checked that the number of left & right ()'s are
9623 equal, so this loop will not be infinite. */
9627 if (*base_string
== ')')
9629 if (*base_string
== '(')
9632 while (parens_balanced
);
9634 temp_string
= base_string
;
9636 /* Skip past '(' and whitespace. */
9638 if (is_space_char (*base_string
))
9641 if (*base_string
== ','
9642 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9645 displacement_string_end
= temp_string
;
9647 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9651 base_string
= end_op
;
9652 if (is_space_char (*base_string
))
9656 /* There may be an index reg or scale factor here. */
9657 if (*base_string
== ',')
9660 if (is_space_char (*base_string
))
9663 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9666 base_string
= end_op
;
9667 if (is_space_char (*base_string
))
9669 if (*base_string
== ',')
9672 if (is_space_char (*base_string
))
9675 else if (*base_string
!= ')')
9677 as_bad (_("expecting `,' or `)' "
9678 "after index register in `%s'"),
9683 else if (*base_string
== REGISTER_PREFIX
)
9685 end_op
= strchr (base_string
, ',');
9688 as_bad (_("bad register name `%s'"), base_string
);
9692 /* Check for scale factor. */
9693 if (*base_string
!= ')')
9695 char *end_scale
= i386_scale (base_string
);
9700 base_string
= end_scale
;
9701 if (is_space_char (*base_string
))
9703 if (*base_string
!= ')')
9705 as_bad (_("expecting `)' "
9706 "after scale factor in `%s'"),
9711 else if (!i
.index_reg
)
9713 as_bad (_("expecting index register or scale factor "
9714 "after `,'; got '%c'"),
9719 else if (*base_string
!= ')')
9721 as_bad (_("expecting `,' or `)' "
9722 "after base register in `%s'"),
9727 else if (*base_string
== REGISTER_PREFIX
)
9729 end_op
= strchr (base_string
, ',');
9732 as_bad (_("bad register name `%s'"), base_string
);
9737 /* If there's an expression beginning the operand, parse it,
9738 assuming displacement_string_start and
9739 displacement_string_end are meaningful. */
9740 if (displacement_string_start
!= displacement_string_end
)
9742 if (!i386_displacement (displacement_string_start
,
9743 displacement_string_end
))
9747 /* Special case for (%dx) while doing input/output op. */
9749 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9751 && i
.log2_scale_factor
== 0
9752 && i
.seg
[i
.mem_operands
] == 0
9753 && !operand_type_check (i
.types
[this_operand
], disp
))
9755 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9759 if (i386_index_check (operand_string
) == 0)
9761 i
.types
[this_operand
].bitfield
.mem
= 1;
9762 if (i
.mem_operands
== 0)
9763 i
.memop1_string
= xstrdup (operand_string
);
9768 /* It's not a memory operand; argh! */
9769 as_bad (_("invalid char %s beginning operand %d `%s'"),
9770 output_invalid (*op_string
),
9775 return 1; /* Normal return. */
9778 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9779 that an rs_machine_dependent frag may reach. */
9782 i386_frag_max_var (fragS
*frag
)
9784 /* The only relaxable frags are for jumps.
9785 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9786 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9787 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9792 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9794 /* STT_GNU_IFUNC symbol must go through PLT. */
9795 if ((symbol_get_bfdsym (fr_symbol
)->flags
9796 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9799 if (!S_IS_EXTERNAL (fr_symbol
))
9800 /* Symbol may be weak or local. */
9801 return !S_IS_WEAK (fr_symbol
);
9803 /* Global symbols with non-default visibility can't be preempted. */
9804 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9807 if (fr_var
!= NO_RELOC
)
9808 switch ((enum bfd_reloc_code_real
) fr_var
)
9810 case BFD_RELOC_386_PLT32
:
9811 case BFD_RELOC_X86_64_PLT32
:
9812 /* Symbol with PLT relocation may be preempted. */
9818 /* Global symbols with default visibility in a shared library may be
9819 preempted by another definition. */
9824 /* md_estimate_size_before_relax()
9826 Called just before relax() for rs_machine_dependent frags. The x86
9827 assembler uses these frags to handle variable size jump
9830 Any symbol that is now undefined will not become defined.
9831 Return the correct fr_subtype in the frag.
9832 Return the initial "guess for variable size of frag" to caller.
9833 The guess is actually the growth beyond the fixed part. Whatever
9834 we do to grow the fixed or variable part contributes to our
9838 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9840 /* We've already got fragP->fr_subtype right; all we have to do is
9841 check for un-relaxable symbols. On an ELF system, we can't relax
9842 an externally visible symbol, because it may be overridden by a
9844 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9847 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9850 #if defined (OBJ_COFF) && defined (TE_PE)
9851 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9852 && S_IS_WEAK (fragP
->fr_symbol
))
9856 /* Symbol is undefined in this segment, or we need to keep a
9857 reloc so that weak symbols can be overridden. */
9858 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9859 enum bfd_reloc_code_real reloc_type
;
9860 unsigned char *opcode
;
9863 if (fragP
->fr_var
!= NO_RELOC
)
9864 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9866 reloc_type
= BFD_RELOC_16_PCREL
;
9867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9868 else if (need_plt32_p (fragP
->fr_symbol
))
9869 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9872 reloc_type
= BFD_RELOC_32_PCREL
;
9874 old_fr_fix
= fragP
->fr_fix
;
9875 opcode
= (unsigned char *) fragP
->fr_opcode
;
9877 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9880 /* Make jmp (0xeb) a (d)word displacement jump. */
9882 fragP
->fr_fix
+= size
;
9883 fix_new (fragP
, old_fr_fix
, size
,
9885 fragP
->fr_offset
, 1,
9891 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9893 /* Negate the condition, and branch past an
9894 unconditional jump. */
9897 /* Insert an unconditional jump. */
9899 /* We added two extra opcode bytes, and have a two byte
9901 fragP
->fr_fix
+= 2 + 2;
9902 fix_new (fragP
, old_fr_fix
+ 2, 2,
9904 fragP
->fr_offset
, 1,
9911 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9916 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9918 fragP
->fr_offset
, 1,
9920 fixP
->fx_signed
= 1;
9924 /* This changes the byte-displacement jump 0x7N
9925 to the (d)word-displacement jump 0x0f,0x8N. */
9926 opcode
[1] = opcode
[0] + 0x10;
9927 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9928 /* We've added an opcode byte. */
9929 fragP
->fr_fix
+= 1 + size
;
9930 fix_new (fragP
, old_fr_fix
+ 1, size
,
9932 fragP
->fr_offset
, 1,
9937 BAD_CASE (fragP
->fr_subtype
);
9941 return fragP
->fr_fix
- old_fr_fix
;
9944 /* Guess size depending on current relax state. Initially the relax
9945 state will correspond to a short jump and we return 1, because
9946 the variable part of the frag (the branch offset) is one byte
9947 long. However, we can relax a section more than once and in that
9948 case we must either set fr_subtype back to the unrelaxed state,
9949 or return the value for the appropriate branch. */
9950 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9953 /* Called after relax() is finished.
9955 In: Address of frag.
9956 fr_type == rs_machine_dependent.
9957 fr_subtype is what the address relaxed to.
9959 Out: Any fixSs and constants are set up.
9960 Caller will turn frag into a ".space 0". */
9963 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9966 unsigned char *opcode
;
9967 unsigned char *where_to_put_displacement
= NULL
;
9968 offsetT target_address
;
9969 offsetT opcode_address
;
9970 unsigned int extension
= 0;
9971 offsetT displacement_from_opcode_start
;
9973 opcode
= (unsigned char *) fragP
->fr_opcode
;
9975 /* Address we want to reach in file space. */
9976 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9978 /* Address opcode resides at in file space. */
9979 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9981 /* Displacement from opcode start to fill into instruction. */
9982 displacement_from_opcode_start
= target_address
- opcode_address
;
9984 if ((fragP
->fr_subtype
& BIG
) == 0)
9986 /* Don't have to change opcode. */
9987 extension
= 1; /* 1 opcode + 1 displacement */
9988 where_to_put_displacement
= &opcode
[1];
9992 if (no_cond_jump_promotion
9993 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9994 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9995 _("long jump required"));
9997 switch (fragP
->fr_subtype
)
9999 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10000 extension
= 4; /* 1 opcode + 4 displacement */
10002 where_to_put_displacement
= &opcode
[1];
10005 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10006 extension
= 2; /* 1 opcode + 2 displacement */
10008 where_to_put_displacement
= &opcode
[1];
10011 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10012 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10013 extension
= 5; /* 2 opcode + 4 displacement */
10014 opcode
[1] = opcode
[0] + 0x10;
10015 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10016 where_to_put_displacement
= &opcode
[2];
10019 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10020 extension
= 3; /* 2 opcode + 2 displacement */
10021 opcode
[1] = opcode
[0] + 0x10;
10022 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10023 where_to_put_displacement
= &opcode
[2];
10026 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10031 where_to_put_displacement
= &opcode
[3];
10035 BAD_CASE (fragP
->fr_subtype
);
10040 /* If size if less then four we are sure that the operand fits,
10041 but if it's 4, then it could be that the displacement is larger
10043 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10045 && ((addressT
) (displacement_from_opcode_start
- extension
10046 + ((addressT
) 1 << 31))
10047 > (((addressT
) 2 << 31) - 1)))
10049 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10050 _("jump target out of range"));
10051 /* Make us emit 0. */
10052 displacement_from_opcode_start
= extension
;
10054 /* Now put displacement after opcode. */
10055 md_number_to_chars ((char *) where_to_put_displacement
,
10056 (valueT
) (displacement_from_opcode_start
- extension
),
10057 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10058 fragP
->fr_fix
+= extension
;
10061 /* Apply a fixup (fixP) to segment data, once it has been determined
10062 by our caller that we have all the info we need to fix it up.
10064 Parameter valP is the pointer to the value of the bits.
10066 On the 386, immediates, displacements, and data pointers are all in
10067 the same (little-endian) format, so we don't need to care about which
10068 we are handling. */
10071 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10073 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10074 valueT value
= *valP
;
10076 #if !defined (TE_Mach)
10077 if (fixP
->fx_pcrel
)
10079 switch (fixP
->fx_r_type
)
10085 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10088 case BFD_RELOC_X86_64_32S
:
10089 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10092 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10095 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10100 if (fixP
->fx_addsy
!= NULL
10101 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10102 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10103 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10104 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10105 && !use_rela_relocations
)
10107 /* This is a hack. There should be a better way to handle this.
10108 This covers for the fact that bfd_install_relocation will
10109 subtract the current location (for partial_inplace, PC relative
10110 relocations); see more below. */
10114 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10117 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10122 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10124 if ((sym_seg
== seg
10125 || (symbol_section_p (fixP
->fx_addsy
)
10126 && sym_seg
!= absolute_section
))
10127 && !generic_force_reloc (fixP
))
10129 /* Yes, we add the values in twice. This is because
10130 bfd_install_relocation subtracts them out again. I think
10131 bfd_install_relocation is broken, but I don't dare change
10133 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10137 #if defined (OBJ_COFF) && defined (TE_PE)
10138 /* For some reason, the PE format does not store a
10139 section address offset for a PC relative symbol. */
10140 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10141 || S_IS_WEAK (fixP
->fx_addsy
))
10142 value
+= md_pcrel_from (fixP
);
10145 #if defined (OBJ_COFF) && defined (TE_PE)
10146 if (fixP
->fx_addsy
!= NULL
10147 && S_IS_WEAK (fixP
->fx_addsy
)
10148 /* PR 16858: Do not modify weak function references. */
10149 && ! fixP
->fx_pcrel
)
10151 #if !defined (TE_PEP)
10152 /* For x86 PE weak function symbols are neither PC-relative
10153 nor do they set S_IS_FUNCTION. So the only reliable way
10154 to detect them is to check the flags of their containing
10156 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10157 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10161 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10165 /* Fix a few things - the dynamic linker expects certain values here,
10166 and we must not disappoint it. */
10167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10168 if (IS_ELF
&& fixP
->fx_addsy
)
10169 switch (fixP
->fx_r_type
)
10171 case BFD_RELOC_386_PLT32
:
10172 case BFD_RELOC_X86_64_PLT32
:
10173 /* Make the jump instruction point to the address of the operand. At
10174 runtime we merely add the offset to the actual PLT entry. */
10178 case BFD_RELOC_386_TLS_GD
:
10179 case BFD_RELOC_386_TLS_LDM
:
10180 case BFD_RELOC_386_TLS_IE_32
:
10181 case BFD_RELOC_386_TLS_IE
:
10182 case BFD_RELOC_386_TLS_GOTIE
:
10183 case BFD_RELOC_386_TLS_GOTDESC
:
10184 case BFD_RELOC_X86_64_TLSGD
:
10185 case BFD_RELOC_X86_64_TLSLD
:
10186 case BFD_RELOC_X86_64_GOTTPOFF
:
10187 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10188 value
= 0; /* Fully resolved at runtime. No addend. */
10190 case BFD_RELOC_386_TLS_LE
:
10191 case BFD_RELOC_386_TLS_LDO_32
:
10192 case BFD_RELOC_386_TLS_LE_32
:
10193 case BFD_RELOC_X86_64_DTPOFF32
:
10194 case BFD_RELOC_X86_64_DTPOFF64
:
10195 case BFD_RELOC_X86_64_TPOFF32
:
10196 case BFD_RELOC_X86_64_TPOFF64
:
10197 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10200 case BFD_RELOC_386_TLS_DESC_CALL
:
10201 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10202 value
= 0; /* Fully resolved at runtime. No addend. */
10203 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10207 case BFD_RELOC_VTABLE_INHERIT
:
10208 case BFD_RELOC_VTABLE_ENTRY
:
10215 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10217 #endif /* !defined (TE_Mach) */
10219 /* Are we finished with this relocation now? */
10220 if (fixP
->fx_addsy
== NULL
)
10222 #if defined (OBJ_COFF) && defined (TE_PE)
10223 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10226 /* Remember value for tc_gen_reloc. */
10227 fixP
->fx_addnumber
= value
;
10228 /* Clear out the frag for now. */
10232 else if (use_rela_relocations
)
10234 fixP
->fx_no_overflow
= 1;
10235 /* Remember value for tc_gen_reloc. */
10236 fixP
->fx_addnumber
= value
;
10240 md_number_to_chars (p
, value
, fixP
->fx_size
);
10244 md_atof (int type
, char *litP
, int *sizeP
)
10246 /* This outputs the LITTLENUMs in REVERSE order;
10247 in accord with the bigendian 386. */
10248 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10251 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10254 output_invalid (int c
)
10257 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10260 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10261 "(0x%x)", (unsigned char) c
);
10262 return output_invalid_buf
;
10265 /* REG_STRING starts *before* REGISTER_PREFIX. */
10267 static const reg_entry
*
10268 parse_real_register (char *reg_string
, char **end_op
)
10270 char *s
= reg_string
;
10272 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10273 const reg_entry
*r
;
10275 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10276 if (*s
== REGISTER_PREFIX
)
10279 if (is_space_char (*s
))
10282 p
= reg_name_given
;
10283 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10285 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10286 return (const reg_entry
*) NULL
;
10290 /* For naked regs, make sure that we are not dealing with an identifier.
10291 This prevents confusing an identifier like `eax_var' with register
10293 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10294 return (const reg_entry
*) NULL
;
10298 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10300 /* Handle floating point regs, allowing spaces in the (i) part. */
10301 if (r
== i386_regtab
/* %st is first entry of table */)
10303 if (!cpu_arch_flags
.bitfield
.cpu8087
10304 && !cpu_arch_flags
.bitfield
.cpu287
10305 && !cpu_arch_flags
.bitfield
.cpu387
)
10306 return (const reg_entry
*) NULL
;
10308 if (is_space_char (*s
))
10313 if (is_space_char (*s
))
10315 if (*s
>= '0' && *s
<= '7')
10317 int fpr
= *s
- '0';
10319 if (is_space_char (*s
))
10324 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10329 /* We have "%st(" then garbage. */
10330 return (const reg_entry
*) NULL
;
10334 if (r
== NULL
|| allow_pseudo_reg
)
10337 if (operand_type_all_zero (&r
->reg_type
))
10338 return (const reg_entry
*) NULL
;
10340 if ((r
->reg_type
.bitfield
.dword
10341 || r
->reg_type
.bitfield
.sreg3
10342 || r
->reg_type
.bitfield
.control
10343 || r
->reg_type
.bitfield
.debug
10344 || r
->reg_type
.bitfield
.test
)
10345 && !cpu_arch_flags
.bitfield
.cpui386
)
10346 return (const reg_entry
*) NULL
;
10348 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10349 return (const reg_entry
*) NULL
;
10351 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10353 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10354 return (const reg_entry
*) NULL
;
10356 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10358 if (r
->reg_type
.bitfield
.ymmword
)
10359 return (const reg_entry
*) NULL
;
10361 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10362 return (const reg_entry
*) NULL
;
10366 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10367 return (const reg_entry
*) NULL
;
10369 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10370 if (!allow_index_reg
10371 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10372 return (const reg_entry
*) NULL
;
10374 /* Upper 16 vector registers are only available with VREX in 64bit
10375 mode, and require EVEX encoding. */
10376 if (r
->reg_flags
& RegVRex
)
10378 if (!cpu_arch_flags
.bitfield
.cpuvrex
10379 || flag_code
!= CODE_64BIT
)
10380 return (const reg_entry
*) NULL
;
10382 i
.vec_encoding
= vex_encoding_evex
;
10385 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10386 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10387 && flag_code
!= CODE_64BIT
)
10388 return (const reg_entry
*) NULL
;
10390 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10391 return (const reg_entry
*) NULL
;
10396 /* REG_STRING starts *before* REGISTER_PREFIX. */
10398 static const reg_entry
*
10399 parse_register (char *reg_string
, char **end_op
)
10401 const reg_entry
*r
;
10403 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10404 r
= parse_real_register (reg_string
, end_op
);
10409 char *save
= input_line_pointer
;
10413 input_line_pointer
= reg_string
;
10414 c
= get_symbol_name (®_string
);
10415 symbolP
= symbol_find (reg_string
);
10416 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10418 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10420 know (e
->X_op
== O_register
);
10421 know (e
->X_add_number
>= 0
10422 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10423 r
= i386_regtab
+ e
->X_add_number
;
10424 if ((r
->reg_flags
& RegVRex
))
10425 i
.vec_encoding
= vex_encoding_evex
;
10426 *end_op
= input_line_pointer
;
10428 *input_line_pointer
= c
;
10429 input_line_pointer
= save
;
10435 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10437 const reg_entry
*r
;
10438 char *end
= input_line_pointer
;
10441 r
= parse_register (name
, &input_line_pointer
);
10442 if (r
&& end
<= input_line_pointer
)
10444 *nextcharP
= *input_line_pointer
;
10445 *input_line_pointer
= 0;
10446 e
->X_op
= O_register
;
10447 e
->X_add_number
= r
- i386_regtab
;
10450 input_line_pointer
= end
;
10452 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10456 md_operand (expressionS
*e
)
10459 const reg_entry
*r
;
10461 switch (*input_line_pointer
)
10463 case REGISTER_PREFIX
:
10464 r
= parse_real_register (input_line_pointer
, &end
);
10467 e
->X_op
= O_register
;
10468 e
->X_add_number
= r
- i386_regtab
;
10469 input_line_pointer
= end
;
10474 gas_assert (intel_syntax
);
10475 end
= input_line_pointer
++;
10477 if (*input_line_pointer
== ']')
10479 ++input_line_pointer
;
10480 e
->X_op_symbol
= make_expr_symbol (e
);
10481 e
->X_add_symbol
= NULL
;
10482 e
->X_add_number
= 0;
10487 e
->X_op
= O_absent
;
10488 input_line_pointer
= end
;
10495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10496 const char *md_shortopts
= "kVQ:sqnO::";
10498 const char *md_shortopts
= "qnO::";
10501 #define OPTION_32 (OPTION_MD_BASE + 0)
10502 #define OPTION_64 (OPTION_MD_BASE + 1)
10503 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10504 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10505 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10506 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10507 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10508 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10509 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10510 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10511 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10512 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10513 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10514 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10515 #define OPTION_X32 (OPTION_MD_BASE + 14)
10516 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10517 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10518 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10519 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10520 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10521 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10522 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10523 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10524 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10525 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10527 struct option md_longopts
[] =
10529 {"32", no_argument
, NULL
, OPTION_32
},
10530 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10531 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10532 {"64", no_argument
, NULL
, OPTION_64
},
10534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10535 {"x32", no_argument
, NULL
, OPTION_X32
},
10536 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10538 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10539 {"march", required_argument
, NULL
, OPTION_MARCH
},
10540 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10541 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10542 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10543 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10544 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10545 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10546 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10547 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10548 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10549 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10550 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10551 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10552 # if defined (TE_PE) || defined (TE_PEP)
10553 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10555 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10556 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10557 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10558 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10559 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10560 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10561 {NULL
, no_argument
, NULL
, 0}
10563 size_t md_longopts_size
= sizeof (md_longopts
);
10566 md_parse_option (int c
, const char *arg
)
10569 char *arch
, *next
, *saved
;
10574 optimize_align_code
= 0;
10578 quiet_warnings
= 1;
10581 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10582 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10583 should be emitted or not. FIXME: Not implemented. */
10587 /* -V: SVR4 argument to print version ID. */
10589 print_version_id ();
10592 /* -k: Ignore for FreeBSD compatibility. */
10597 /* -s: On i386 Solaris, this tells the native assembler to use
10598 .stab instead of .stab.excl. We always use .stab anyhow. */
10601 case OPTION_MSHARED
:
10605 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10606 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10609 const char **list
, **l
;
10611 list
= bfd_target_list ();
10612 for (l
= list
; *l
!= NULL
; l
++)
10613 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10614 || strcmp (*l
, "coff-x86-64") == 0
10615 || strcmp (*l
, "pe-x86-64") == 0
10616 || strcmp (*l
, "pei-x86-64") == 0
10617 || strcmp (*l
, "mach-o-x86-64") == 0)
10619 default_arch
= "x86_64";
10623 as_fatal (_("no compiled in support for x86_64"));
10629 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10633 const char **list
, **l
;
10635 list
= bfd_target_list ();
10636 for (l
= list
; *l
!= NULL
; l
++)
10637 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10639 default_arch
= "x86_64:32";
10643 as_fatal (_("no compiled in support for 32bit x86_64"));
10647 as_fatal (_("32bit x86_64 is only supported for ELF"));
10652 default_arch
= "i386";
10655 case OPTION_DIVIDE
:
10656 #ifdef SVR4_COMMENT_CHARS
10661 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10663 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10667 i386_comment_chars
= n
;
10673 saved
= xstrdup (arg
);
10675 /* Allow -march=+nosse. */
10681 as_fatal (_("invalid -march= option: `%s'"), arg
);
10682 next
= strchr (arch
, '+');
10685 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10687 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10690 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10693 cpu_arch_name
= cpu_arch
[j
].name
;
10694 cpu_sub_arch_name
= NULL
;
10695 cpu_arch_flags
= cpu_arch
[j
].flags
;
10696 cpu_arch_isa
= cpu_arch
[j
].type
;
10697 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10698 if (!cpu_arch_tune_set
)
10700 cpu_arch_tune
= cpu_arch_isa
;
10701 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10705 else if (*cpu_arch
[j
].name
== '.'
10706 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10708 /* ISA extension. */
10709 i386_cpu_flags flags
;
10711 flags
= cpu_flags_or (cpu_arch_flags
,
10712 cpu_arch
[j
].flags
);
10714 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10716 if (cpu_sub_arch_name
)
10718 char *name
= cpu_sub_arch_name
;
10719 cpu_sub_arch_name
= concat (name
,
10721 (const char *) NULL
);
10725 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10726 cpu_arch_flags
= flags
;
10727 cpu_arch_isa_flags
= flags
;
10731 = cpu_flags_or (cpu_arch_isa_flags
,
10732 cpu_arch
[j
].flags
);
10737 if (j
>= ARRAY_SIZE (cpu_arch
))
10739 /* Disable an ISA extension. */
10740 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10741 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10743 i386_cpu_flags flags
;
10745 flags
= cpu_flags_and_not (cpu_arch_flags
,
10746 cpu_noarch
[j
].flags
);
10747 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10749 if (cpu_sub_arch_name
)
10751 char *name
= cpu_sub_arch_name
;
10752 cpu_sub_arch_name
= concat (arch
,
10753 (const char *) NULL
);
10757 cpu_sub_arch_name
= xstrdup (arch
);
10758 cpu_arch_flags
= flags
;
10759 cpu_arch_isa_flags
= flags
;
10764 if (j
>= ARRAY_SIZE (cpu_noarch
))
10765 j
= ARRAY_SIZE (cpu_arch
);
10768 if (j
>= ARRAY_SIZE (cpu_arch
))
10769 as_fatal (_("invalid -march= option: `%s'"), arg
);
10773 while (next
!= NULL
);
10779 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10780 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10782 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10784 cpu_arch_tune_set
= 1;
10785 cpu_arch_tune
= cpu_arch
[j
].type
;
10786 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10790 if (j
>= ARRAY_SIZE (cpu_arch
))
10791 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10794 case OPTION_MMNEMONIC
:
10795 if (strcasecmp (arg
, "att") == 0)
10796 intel_mnemonic
= 0;
10797 else if (strcasecmp (arg
, "intel") == 0)
10798 intel_mnemonic
= 1;
10800 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10803 case OPTION_MSYNTAX
:
10804 if (strcasecmp (arg
, "att") == 0)
10806 else if (strcasecmp (arg
, "intel") == 0)
10809 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10812 case OPTION_MINDEX_REG
:
10813 allow_index_reg
= 1;
10816 case OPTION_MNAKED_REG
:
10817 allow_naked_reg
= 1;
10820 case OPTION_MSSE2AVX
:
10824 case OPTION_MSSE_CHECK
:
10825 if (strcasecmp (arg
, "error") == 0)
10826 sse_check
= check_error
;
10827 else if (strcasecmp (arg
, "warning") == 0)
10828 sse_check
= check_warning
;
10829 else if (strcasecmp (arg
, "none") == 0)
10830 sse_check
= check_none
;
10832 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10835 case OPTION_MOPERAND_CHECK
:
10836 if (strcasecmp (arg
, "error") == 0)
10837 operand_check
= check_error
;
10838 else if (strcasecmp (arg
, "warning") == 0)
10839 operand_check
= check_warning
;
10840 else if (strcasecmp (arg
, "none") == 0)
10841 operand_check
= check_none
;
10843 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10846 case OPTION_MAVXSCALAR
:
10847 if (strcasecmp (arg
, "128") == 0)
10848 avxscalar
= vex128
;
10849 else if (strcasecmp (arg
, "256") == 0)
10850 avxscalar
= vex256
;
10852 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10855 case OPTION_MADD_BND_PREFIX
:
10856 add_bnd_prefix
= 1;
10859 case OPTION_MEVEXLIG
:
10860 if (strcmp (arg
, "128") == 0)
10861 evexlig
= evexl128
;
10862 else if (strcmp (arg
, "256") == 0)
10863 evexlig
= evexl256
;
10864 else if (strcmp (arg
, "512") == 0)
10865 evexlig
= evexl512
;
10867 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10870 case OPTION_MEVEXRCIG
:
10871 if (strcmp (arg
, "rne") == 0)
10873 else if (strcmp (arg
, "rd") == 0)
10875 else if (strcmp (arg
, "ru") == 0)
10877 else if (strcmp (arg
, "rz") == 0)
10880 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10883 case OPTION_MEVEXWIG
:
10884 if (strcmp (arg
, "0") == 0)
10886 else if (strcmp (arg
, "1") == 0)
10889 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10892 # if defined (TE_PE) || defined (TE_PEP)
10893 case OPTION_MBIG_OBJ
:
10898 case OPTION_MOMIT_LOCK_PREFIX
:
10899 if (strcasecmp (arg
, "yes") == 0)
10900 omit_lock_prefix
= 1;
10901 else if (strcasecmp (arg
, "no") == 0)
10902 omit_lock_prefix
= 0;
10904 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10907 case OPTION_MFENCE_AS_LOCK_ADD
:
10908 if (strcasecmp (arg
, "yes") == 0)
10910 else if (strcasecmp (arg
, "no") == 0)
10913 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10916 case OPTION_MRELAX_RELOCATIONS
:
10917 if (strcasecmp (arg
, "yes") == 0)
10918 generate_relax_relocations
= 1;
10919 else if (strcasecmp (arg
, "no") == 0)
10920 generate_relax_relocations
= 0;
10922 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10925 case OPTION_MAMD64
:
10929 case OPTION_MINTEL64
:
10937 /* Turn off -Os. */
10938 optimize_for_space
= 0;
10940 else if (*arg
== 's')
10942 optimize_for_space
= 1;
10943 /* Turn on all encoding optimizations. */
10948 optimize
= atoi (arg
);
10949 /* Turn off -Os. */
10950 optimize_for_space
= 0;
10960 #define MESSAGE_TEMPLATE \
10964 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10965 int *left_p
, const char *name
, int len
)
10967 int size
= sizeof (MESSAGE_TEMPLATE
);
10968 int left
= *left_p
;
10970 /* Reserve 2 spaces for ", " or ",\0" */
10973 /* Check if there is any room. */
10981 p
= mempcpy (p
, name
, len
);
10985 /* Output the current message now and start a new one. */
10988 fprintf (stream
, "%s\n", message
);
10990 left
= size
- (start
- message
) - len
- 2;
10992 gas_assert (left
>= 0);
10994 p
= mempcpy (p
, name
, len
);
11002 show_arch (FILE *stream
, int ext
, int check
)
11004 static char message
[] = MESSAGE_TEMPLATE
;
11005 char *start
= message
+ 27;
11007 int size
= sizeof (MESSAGE_TEMPLATE
);
11014 left
= size
- (start
- message
);
11015 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11017 /* Should it be skipped? */
11018 if (cpu_arch
[j
].skip
)
11021 name
= cpu_arch
[j
].name
;
11022 len
= cpu_arch
[j
].len
;
11025 /* It is an extension. Skip if we aren't asked to show it. */
11036 /* It is an processor. Skip if we show only extension. */
11039 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11041 /* It is an impossible processor - skip. */
11045 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11048 /* Display disabled extensions. */
11050 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11052 name
= cpu_noarch
[j
].name
;
11053 len
= cpu_noarch
[j
].len
;
11054 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11059 fprintf (stream
, "%s\n", message
);
11063 md_show_usage (FILE *stream
)
11065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11066 fprintf (stream
, _("\
11068 -V print assembler version number\n\
11071 fprintf (stream
, _("\
11072 -n Do not optimize code alignment\n\
11073 -q quieten some warnings\n"));
11074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11075 fprintf (stream
, _("\
11078 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11079 || defined (TE_PE) || defined (TE_PEP))
11080 fprintf (stream
, _("\
11081 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11083 #ifdef SVR4_COMMENT_CHARS
11084 fprintf (stream
, _("\
11085 --divide do not treat `/' as a comment character\n"));
11087 fprintf (stream
, _("\
11088 --divide ignored\n"));
11090 fprintf (stream
, _("\
11091 -march=CPU[,+EXTENSION...]\n\
11092 generate code for CPU and EXTENSION, CPU is one of:\n"));
11093 show_arch (stream
, 0, 1);
11094 fprintf (stream
, _("\
11095 EXTENSION is combination of:\n"));
11096 show_arch (stream
, 1, 0);
11097 fprintf (stream
, _("\
11098 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11099 show_arch (stream
, 0, 0);
11100 fprintf (stream
, _("\
11101 -msse2avx encode SSE instructions with VEX prefix\n"));
11102 fprintf (stream
, _("\
11103 -msse-check=[none|error|warning]\n\
11104 check SSE instructions\n"));
11105 fprintf (stream
, _("\
11106 -moperand-check=[none|error|warning]\n\
11107 check operand combinations for validity\n"));
11108 fprintf (stream
, _("\
11109 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11111 fprintf (stream
, _("\
11112 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11114 fprintf (stream
, _("\
11115 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11116 for EVEX.W bit ignored instructions\n"));
11117 fprintf (stream
, _("\
11118 -mevexrcig=[rne|rd|ru|rz]\n\
11119 encode EVEX instructions with specific EVEX.RC value\n\
11120 for SAE-only ignored instructions\n"));
11121 fprintf (stream
, _("\
11122 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11123 fprintf (stream
, _("\
11124 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11125 fprintf (stream
, _("\
11126 -mindex-reg support pseudo index registers\n"));
11127 fprintf (stream
, _("\
11128 -mnaked-reg don't require `%%' prefix for registers\n"));
11129 fprintf (stream
, _("\
11130 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11131 fprintf (stream
, _("\
11132 -mshared disable branch optimization for shared code\n"));
11133 # if defined (TE_PE) || defined (TE_PEP)
11134 fprintf (stream
, _("\
11135 -mbig-obj generate big object files\n"));
11137 fprintf (stream
, _("\
11138 -momit-lock-prefix=[no|yes]\n\
11139 strip all lock prefixes\n"));
11140 fprintf (stream
, _("\
11141 -mfence-as-lock-add=[no|yes]\n\
11142 encode lfence, mfence and sfence as\n\
11143 lock addl $0x0, (%%{re}sp)\n"));
11144 fprintf (stream
, _("\
11145 -mrelax-relocations=[no|yes]\n\
11146 generate relax relocations\n"));
11147 fprintf (stream
, _("\
11148 -mamd64 accept only AMD64 ISA\n"));
11149 fprintf (stream
, _("\
11150 -mintel64 accept only Intel64 ISA\n"));
11153 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11154 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11155 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11157 /* Pick the target format to use. */
11160 i386_target_format (void)
11162 if (!strncmp (default_arch
, "x86_64", 6))
11164 update_code_flag (CODE_64BIT
, 1);
11165 if (default_arch
[6] == '\0')
11166 x86_elf_abi
= X86_64_ABI
;
11168 x86_elf_abi
= X86_64_X32_ABI
;
11170 else if (!strcmp (default_arch
, "i386"))
11171 update_code_flag (CODE_32BIT
, 1);
11172 else if (!strcmp (default_arch
, "iamcu"))
11174 update_code_flag (CODE_32BIT
, 1);
11175 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11177 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11178 cpu_arch_name
= "iamcu";
11179 cpu_sub_arch_name
= NULL
;
11180 cpu_arch_flags
= iamcu_flags
;
11181 cpu_arch_isa
= PROCESSOR_IAMCU
;
11182 cpu_arch_isa_flags
= iamcu_flags
;
11183 if (!cpu_arch_tune_set
)
11185 cpu_arch_tune
= cpu_arch_isa
;
11186 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11189 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11190 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11194 as_fatal (_("unknown architecture"));
11196 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11197 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11198 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11199 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11201 switch (OUTPUT_FLAVOR
)
11203 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11204 case bfd_target_aout_flavour
:
11205 return AOUT_TARGET_FORMAT
;
11207 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11208 # if defined (TE_PE) || defined (TE_PEP)
11209 case bfd_target_coff_flavour
:
11210 if (flag_code
== CODE_64BIT
)
11211 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11214 # elif defined (TE_GO32)
11215 case bfd_target_coff_flavour
:
11216 return "coff-go32";
11218 case bfd_target_coff_flavour
:
11219 return "coff-i386";
11222 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11223 case bfd_target_elf_flavour
:
11225 const char *format
;
11227 switch (x86_elf_abi
)
11230 format
= ELF_TARGET_FORMAT
;
11233 use_rela_relocations
= 1;
11235 format
= ELF_TARGET_FORMAT64
;
11237 case X86_64_X32_ABI
:
11238 use_rela_relocations
= 1;
11240 disallow_64bit_reloc
= 1;
11241 format
= ELF_TARGET_FORMAT32
;
11244 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11246 if (x86_elf_abi
!= X86_64_ABI
)
11247 as_fatal (_("Intel L1OM is 64bit only"));
11248 return ELF_TARGET_L1OM_FORMAT
;
11250 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11252 if (x86_elf_abi
!= X86_64_ABI
)
11253 as_fatal (_("Intel K1OM is 64bit only"));
11254 return ELF_TARGET_K1OM_FORMAT
;
11256 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11258 if (x86_elf_abi
!= I386_ABI
)
11259 as_fatal (_("Intel MCU is 32bit only"));
11260 return ELF_TARGET_IAMCU_FORMAT
;
11266 #if defined (OBJ_MACH_O)
11267 case bfd_target_mach_o_flavour
:
11268 if (flag_code
== CODE_64BIT
)
11270 use_rela_relocations
= 1;
11272 return "mach-o-x86-64";
11275 return "mach-o-i386";
11283 #endif /* OBJ_MAYBE_ more than one */
11286 md_undefined_symbol (char *name
)
11288 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11289 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11290 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11291 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11295 if (symbol_find (name
))
11296 as_bad (_("GOT already in symbol table"));
11297 GOT_symbol
= symbol_new (name
, undefined_section
,
11298 (valueT
) 0, &zero_address_frag
);
11305 /* Round up a section size to the appropriate boundary. */
11308 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11310 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11311 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11313 /* For a.out, force the section size to be aligned. If we don't do
11314 this, BFD will align it for us, but it will not write out the
11315 final bytes of the section. This may be a bug in BFD, but it is
11316 easier to fix it here since that is how the other a.out targets
11320 align
= bfd_get_section_alignment (stdoutput
, segment
);
11321 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11328 /* On the i386, PC-relative offsets are relative to the start of the
11329 next instruction. That is, the address of the offset, plus its
11330 size, since the offset is always the last part of the insn. */
11333 md_pcrel_from (fixS
*fixP
)
11335 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11341 s_bss (int ignore ATTRIBUTE_UNUSED
)
11345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11347 obj_elf_section_change_hook ();
11349 temp
= get_absolute_expression ();
11350 subseg_set (bss_section
, (subsegT
) temp
);
11351 demand_empty_rest_of_line ();
11357 i386_validate_fix (fixS
*fixp
)
11359 if (fixp
->fx_subsy
)
11361 if (fixp
->fx_subsy
== GOT_symbol
)
11363 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11367 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11368 if (fixp
->fx_tcbit2
)
11369 fixp
->fx_r_type
= (fixp
->fx_tcbit
11370 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11371 : BFD_RELOC_X86_64_GOTPCRELX
);
11374 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11379 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11381 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11383 fixp
->fx_subsy
= 0;
11386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11387 else if (!object_64bit
)
11389 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11390 && fixp
->fx_tcbit2
)
11391 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11397 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11400 bfd_reloc_code_real_type code
;
11402 switch (fixp
->fx_r_type
)
11404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11405 case BFD_RELOC_SIZE32
:
11406 case BFD_RELOC_SIZE64
:
11407 if (S_IS_DEFINED (fixp
->fx_addsy
)
11408 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11410 /* Resolve size relocation against local symbol to size of
11411 the symbol plus addend. */
11412 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11413 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11414 && !fits_in_unsigned_long (value
))
11415 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11416 _("symbol size computation overflow"));
11417 fixp
->fx_addsy
= NULL
;
11418 fixp
->fx_subsy
= NULL
;
11419 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11423 /* Fall through. */
11425 case BFD_RELOC_X86_64_PLT32
:
11426 case BFD_RELOC_X86_64_GOT32
:
11427 case BFD_RELOC_X86_64_GOTPCREL
:
11428 case BFD_RELOC_X86_64_GOTPCRELX
:
11429 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11430 case BFD_RELOC_386_PLT32
:
11431 case BFD_RELOC_386_GOT32
:
11432 case BFD_RELOC_386_GOT32X
:
11433 case BFD_RELOC_386_GOTOFF
:
11434 case BFD_RELOC_386_GOTPC
:
11435 case BFD_RELOC_386_TLS_GD
:
11436 case BFD_RELOC_386_TLS_LDM
:
11437 case BFD_RELOC_386_TLS_LDO_32
:
11438 case BFD_RELOC_386_TLS_IE_32
:
11439 case BFD_RELOC_386_TLS_IE
:
11440 case BFD_RELOC_386_TLS_GOTIE
:
11441 case BFD_RELOC_386_TLS_LE_32
:
11442 case BFD_RELOC_386_TLS_LE
:
11443 case BFD_RELOC_386_TLS_GOTDESC
:
11444 case BFD_RELOC_386_TLS_DESC_CALL
:
11445 case BFD_RELOC_X86_64_TLSGD
:
11446 case BFD_RELOC_X86_64_TLSLD
:
11447 case BFD_RELOC_X86_64_DTPOFF32
:
11448 case BFD_RELOC_X86_64_DTPOFF64
:
11449 case BFD_RELOC_X86_64_GOTTPOFF
:
11450 case BFD_RELOC_X86_64_TPOFF32
:
11451 case BFD_RELOC_X86_64_TPOFF64
:
11452 case BFD_RELOC_X86_64_GOTOFF64
:
11453 case BFD_RELOC_X86_64_GOTPC32
:
11454 case BFD_RELOC_X86_64_GOT64
:
11455 case BFD_RELOC_X86_64_GOTPCREL64
:
11456 case BFD_RELOC_X86_64_GOTPC64
:
11457 case BFD_RELOC_X86_64_GOTPLT64
:
11458 case BFD_RELOC_X86_64_PLTOFF64
:
11459 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11460 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11461 case BFD_RELOC_RVA
:
11462 case BFD_RELOC_VTABLE_ENTRY
:
11463 case BFD_RELOC_VTABLE_INHERIT
:
11465 case BFD_RELOC_32_SECREL
:
11467 code
= fixp
->fx_r_type
;
11469 case BFD_RELOC_X86_64_32S
:
11470 if (!fixp
->fx_pcrel
)
11472 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11473 code
= fixp
->fx_r_type
;
11476 /* Fall through. */
11478 if (fixp
->fx_pcrel
)
11480 switch (fixp
->fx_size
)
11483 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11484 _("can not do %d byte pc-relative relocation"),
11486 code
= BFD_RELOC_32_PCREL
;
11488 case 1: code
= BFD_RELOC_8_PCREL
; break;
11489 case 2: code
= BFD_RELOC_16_PCREL
; break;
11490 case 4: code
= BFD_RELOC_32_PCREL
; break;
11492 case 8: code
= BFD_RELOC_64_PCREL
; break;
11498 switch (fixp
->fx_size
)
11501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11502 _("can not do %d byte relocation"),
11504 code
= BFD_RELOC_32
;
11506 case 1: code
= BFD_RELOC_8
; break;
11507 case 2: code
= BFD_RELOC_16
; break;
11508 case 4: code
= BFD_RELOC_32
; break;
11510 case 8: code
= BFD_RELOC_64
; break;
11517 if ((code
== BFD_RELOC_32
11518 || code
== BFD_RELOC_32_PCREL
11519 || code
== BFD_RELOC_X86_64_32S
)
11521 && fixp
->fx_addsy
== GOT_symbol
)
11524 code
= BFD_RELOC_386_GOTPC
;
11526 code
= BFD_RELOC_X86_64_GOTPC32
;
11528 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11530 && fixp
->fx_addsy
== GOT_symbol
)
11532 code
= BFD_RELOC_X86_64_GOTPC64
;
11535 rel
= XNEW (arelent
);
11536 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11537 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11539 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11541 if (!use_rela_relocations
)
11543 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11544 vtable entry to be used in the relocation's section offset. */
11545 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11546 rel
->address
= fixp
->fx_offset
;
11547 #if defined (OBJ_COFF) && defined (TE_PE)
11548 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11549 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11554 /* Use the rela in 64bit mode. */
11557 if (disallow_64bit_reloc
)
11560 case BFD_RELOC_X86_64_DTPOFF64
:
11561 case BFD_RELOC_X86_64_TPOFF64
:
11562 case BFD_RELOC_64_PCREL
:
11563 case BFD_RELOC_X86_64_GOTOFF64
:
11564 case BFD_RELOC_X86_64_GOT64
:
11565 case BFD_RELOC_X86_64_GOTPCREL64
:
11566 case BFD_RELOC_X86_64_GOTPC64
:
11567 case BFD_RELOC_X86_64_GOTPLT64
:
11568 case BFD_RELOC_X86_64_PLTOFF64
:
11569 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11570 _("cannot represent relocation type %s in x32 mode"),
11571 bfd_get_reloc_code_name (code
));
11577 if (!fixp
->fx_pcrel
)
11578 rel
->addend
= fixp
->fx_offset
;
11582 case BFD_RELOC_X86_64_PLT32
:
11583 case BFD_RELOC_X86_64_GOT32
:
11584 case BFD_RELOC_X86_64_GOTPCREL
:
11585 case BFD_RELOC_X86_64_GOTPCRELX
:
11586 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11587 case BFD_RELOC_X86_64_TLSGD
:
11588 case BFD_RELOC_X86_64_TLSLD
:
11589 case BFD_RELOC_X86_64_GOTTPOFF
:
11590 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11591 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11592 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11595 rel
->addend
= (section
->vma
11597 + fixp
->fx_addnumber
11598 + md_pcrel_from (fixp
));
11603 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11604 if (rel
->howto
== NULL
)
11606 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11607 _("cannot represent relocation type %s"),
11608 bfd_get_reloc_code_name (code
));
11609 /* Set howto to a garbage value so that we can keep going. */
11610 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11611 gas_assert (rel
->howto
!= NULL
);
11617 #include "tc-i386-intel.c"
11620 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11622 int saved_naked_reg
;
11623 char saved_register_dot
;
11625 saved_naked_reg
= allow_naked_reg
;
11626 allow_naked_reg
= 1;
11627 saved_register_dot
= register_chars
['.'];
11628 register_chars
['.'] = '.';
11629 allow_pseudo_reg
= 1;
11630 expression_and_evaluate (exp
);
11631 allow_pseudo_reg
= 0;
11632 register_chars
['.'] = saved_register_dot
;
11633 allow_naked_reg
= saved_naked_reg
;
11635 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11637 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11639 exp
->X_op
= O_constant
;
11640 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11641 .dw2_regnum
[flag_code
>> 1];
11644 exp
->X_op
= O_illegal
;
11649 tc_x86_frame_initial_instructions (void)
11651 static unsigned int sp_regno
[2];
11653 if (!sp_regno
[flag_code
>> 1])
11655 char *saved_input
= input_line_pointer
;
11656 char sp
[][4] = {"esp", "rsp"};
11659 input_line_pointer
= sp
[flag_code
>> 1];
11660 tc_x86_parse_to_dw2regnum (&exp
);
11661 gas_assert (exp
.X_op
== O_constant
);
11662 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11663 input_line_pointer
= saved_input
;
11666 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11667 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11671 x86_dwarf2_addr_size (void)
11673 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11674 if (x86_elf_abi
== X86_64_X32_ABI
)
11677 return bfd_arch_bits_per_address (stdoutput
) / 8;
11681 i386_elf_section_type (const char *str
, size_t len
)
11683 if (flag_code
== CODE_64BIT
11684 && len
== sizeof ("unwind") - 1
11685 && strncmp (str
, "unwind", 6) == 0)
11686 return SHT_X86_64_UNWIND
;
11693 i386_solaris_fix_up_eh_frame (segT sec
)
11695 if (flag_code
== CODE_64BIT
)
11696 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11702 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11706 exp
.X_op
= O_secrel
;
11707 exp
.X_add_symbol
= symbol
;
11708 exp
.X_add_number
= 0;
11709 emit_expr (&exp
, size
);
11713 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11714 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11717 x86_64_section_letter (int letter
, const char **ptr_msg
)
11719 if (flag_code
== CODE_64BIT
)
11722 return SHF_X86_64_LARGE
;
11724 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11727 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11732 x86_64_section_word (char *str
, size_t len
)
11734 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11735 return SHF_X86_64_LARGE
;
11741 handle_large_common (int small ATTRIBUTE_UNUSED
)
11743 if (flag_code
!= CODE_64BIT
)
11745 s_comm_internal (0, elf_common_parse
);
11746 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11750 static segT lbss_section
;
11751 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11752 asection
*saved_bss_section
= bss_section
;
11754 if (lbss_section
== NULL
)
11756 flagword applicable
;
11757 segT seg
= now_seg
;
11758 subsegT subseg
= now_subseg
;
11760 /* The .lbss section is for local .largecomm symbols. */
11761 lbss_section
= subseg_new (".lbss", 0);
11762 applicable
= bfd_applicable_section_flags (stdoutput
);
11763 bfd_set_section_flags (stdoutput
, lbss_section
,
11764 applicable
& SEC_ALLOC
);
11765 seg_info (lbss_section
)->bss
= 1;
11767 subseg_set (seg
, subseg
);
11770 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11771 bss_section
= lbss_section
;
11773 s_comm_internal (0, elf_common_parse
);
11775 elf_com_section_ptr
= saved_com_section_ptr
;
11776 bss_section
= saved_bss_section
;
11779 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */