1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1084 CPU_AVX512_BF16_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1086 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1088 CPU_ENQCMD_FLAGS
, 0 },
1091 static const noarch_entry cpu_noarch
[] =
1093 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1094 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1095 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1096 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1097 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1098 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1099 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1101 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1102 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1103 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1106 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1124 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1125 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1126 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1127 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1130 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1134 /* Like s_lcomm_internal in gas/read.c but the alignment string
1135 is allowed to be optional. */
1138 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1145 && *input_line_pointer
== ',')
1147 align
= parse_align (needs_align
- 1);
1149 if (align
== (addressT
) -1)
1164 bss_alloc (symbolP
, size
, align
);
1169 pe_lcomm (int needs_align
)
1171 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1175 const pseudo_typeS md_pseudo_table
[] =
1177 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1178 {"align", s_align_bytes
, 0},
1180 {"align", s_align_ptwo
, 0},
1182 {"arch", set_cpu_arch
, 0},
1186 {"lcomm", pe_lcomm
, 1},
1188 {"ffloat", float_cons
, 'f'},
1189 {"dfloat", float_cons
, 'd'},
1190 {"tfloat", float_cons
, 'x'},
1192 {"slong", signed_cons
, 4},
1193 {"noopt", s_ignore
, 0},
1194 {"optim", s_ignore
, 0},
1195 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1196 {"code16", set_code_flag
, CODE_16BIT
},
1197 {"code32", set_code_flag
, CODE_32BIT
},
1199 {"code64", set_code_flag
, CODE_64BIT
},
1201 {"intel_syntax", set_intel_syntax
, 1},
1202 {"att_syntax", set_intel_syntax
, 0},
1203 {"intel_mnemonic", set_intel_mnemonic
, 1},
1204 {"att_mnemonic", set_intel_mnemonic
, 0},
1205 {"allow_index_reg", set_allow_index_reg
, 1},
1206 {"disallow_index_reg", set_allow_index_reg
, 0},
1207 {"sse_check", set_check
, 0},
1208 {"operand_check", set_check
, 1},
1209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1210 {"largecomm", handle_large_common
, 0},
1212 {"file", dwarf2_directive_file
, 0},
1213 {"loc", dwarf2_directive_loc
, 0},
1214 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1217 {"secrel32", pe_directive_secrel
, 0},
1222 /* For interface with expression (). */
1223 extern char *input_line_pointer
;
1225 /* Hash table for instruction mnemonic lookup. */
1226 static struct hash_control
*op_hash
;
1228 /* Hash table for register lookup. */
1229 static struct hash_control
*reg_hash
;
1231 /* Various efficient no-op patterns for aligning code labels.
1232 Note: Don't try to assemble the instructions in the comments.
1233 0L and 0w are not legal. */
1234 static const unsigned char f32_1
[] =
1236 static const unsigned char f32_2
[] =
1237 {0x66,0x90}; /* xchg %ax,%ax */
1238 static const unsigned char f32_3
[] =
1239 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1240 static const unsigned char f32_4
[] =
1241 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1242 static const unsigned char f32_6
[] =
1243 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1244 static const unsigned char f32_7
[] =
1245 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1246 static const unsigned char f16_3
[] =
1247 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1248 static const unsigned char f16_4
[] =
1249 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1250 static const unsigned char jump_disp8
[] =
1251 {0xeb}; /* jmp disp8 */
1252 static const unsigned char jump32_disp32
[] =
1253 {0xe9}; /* jmp disp32 */
1254 static const unsigned char jump16_disp32
[] =
1255 {0x66,0xe9}; /* jmp disp32 */
1256 /* 32-bit NOPs patterns. */
1257 static const unsigned char *const f32_patt
[] = {
1258 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1260 /* 16-bit NOPs patterns. */
1261 static const unsigned char *const f16_patt
[] = {
1262 f32_1
, f32_2
, f16_3
, f16_4
1264 /* nopl (%[re]ax) */
1265 static const unsigned char alt_3
[] =
1267 /* nopl 0(%[re]ax) */
1268 static const unsigned char alt_4
[] =
1269 {0x0f,0x1f,0x40,0x00};
1270 /* nopl 0(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_5
[] =
1272 {0x0f,0x1f,0x44,0x00,0x00};
1273 /* nopw 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_6
[] =
1275 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopl 0L(%[re]ax) */
1277 static const unsigned char alt_7
[] =
1278 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1279 /* nopl 0L(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_8
[] =
1281 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* nopw 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_9
[] =
1284 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_10
[] =
1287 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* data16 nopw %cs:0L(%eax,%eax,1) */
1289 static const unsigned char alt_11
[] =
1290 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* 32-bit and 64-bit NOPs patterns. */
1292 static const unsigned char *const alt_patt
[] = {
1293 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1294 alt_9
, alt_10
, alt_11
1297 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1298 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1301 i386_output_nops (char *where
, const unsigned char *const *patt
,
1302 int count
, int max_single_nop_size
)
1305 /* Place the longer NOP first. */
1308 const unsigned char *nops
;
1310 if (max_single_nop_size
< 1)
1312 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1313 max_single_nop_size
);
1317 nops
= patt
[max_single_nop_size
- 1];
1319 /* Use the smaller one if the requsted one isn't available. */
1322 max_single_nop_size
--;
1323 nops
= patt
[max_single_nop_size
- 1];
1326 last
= count
% max_single_nop_size
;
1329 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1330 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1334 nops
= patt
[last
- 1];
1337 /* Use the smaller one plus one-byte NOP if the needed one
1340 nops
= patt
[last
- 1];
1341 memcpy (where
+ offset
, nops
, last
);
1342 where
[offset
+ last
] = *patt
[0];
1345 memcpy (where
+ offset
, nops
, last
);
1350 fits_in_imm7 (offsetT num
)
1352 return (num
& 0x7f) == num
;
1356 fits_in_imm31 (offsetT num
)
1358 return (num
& 0x7fffffff) == num
;
1361 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1362 single NOP instruction LIMIT. */
1365 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1367 const unsigned char *const *patt
= NULL
;
1368 int max_single_nop_size
;
1369 /* Maximum number of NOPs before switching to jump over NOPs. */
1370 int max_number_of_nops
;
1372 switch (fragP
->fr_type
)
1381 /* We need to decide which NOP sequence to use for 32bit and
1382 64bit. When -mtune= is used:
1384 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1385 PROCESSOR_GENERIC32, f32_patt will be used.
1386 2. For the rest, alt_patt will be used.
1388 When -mtune= isn't used, alt_patt will be used if
1389 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1392 When -march= or .arch is used, we can't use anything beyond
1393 cpu_arch_isa_flags. */
1395 if (flag_code
== CODE_16BIT
)
1398 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1399 /* Limit number of NOPs to 2 in 16-bit mode. */
1400 max_number_of_nops
= 2;
1404 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1406 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1407 switch (cpu_arch_tune
)
1409 case PROCESSOR_UNKNOWN
:
1410 /* We use cpu_arch_isa_flags to check if we SHOULD
1411 optimize with nops. */
1412 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1417 case PROCESSOR_PENTIUM4
:
1418 case PROCESSOR_NOCONA
:
1419 case PROCESSOR_CORE
:
1420 case PROCESSOR_CORE2
:
1421 case PROCESSOR_COREI7
:
1422 case PROCESSOR_L1OM
:
1423 case PROCESSOR_K1OM
:
1424 case PROCESSOR_GENERIC64
:
1426 case PROCESSOR_ATHLON
:
1428 case PROCESSOR_AMDFAM10
:
1430 case PROCESSOR_ZNVER
:
1434 case PROCESSOR_I386
:
1435 case PROCESSOR_I486
:
1436 case PROCESSOR_PENTIUM
:
1437 case PROCESSOR_PENTIUMPRO
:
1438 case PROCESSOR_IAMCU
:
1439 case PROCESSOR_GENERIC32
:
1446 switch (fragP
->tc_frag_data
.tune
)
1448 case PROCESSOR_UNKNOWN
:
1449 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1450 PROCESSOR_UNKNOWN. */
1454 case PROCESSOR_I386
:
1455 case PROCESSOR_I486
:
1456 case PROCESSOR_PENTIUM
:
1457 case PROCESSOR_IAMCU
:
1459 case PROCESSOR_ATHLON
:
1461 case PROCESSOR_AMDFAM10
:
1463 case PROCESSOR_ZNVER
:
1465 case PROCESSOR_GENERIC32
:
1466 /* We use cpu_arch_isa_flags to check if we CAN optimize
1468 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1473 case PROCESSOR_PENTIUMPRO
:
1474 case PROCESSOR_PENTIUM4
:
1475 case PROCESSOR_NOCONA
:
1476 case PROCESSOR_CORE
:
1477 case PROCESSOR_CORE2
:
1478 case PROCESSOR_COREI7
:
1479 case PROCESSOR_L1OM
:
1480 case PROCESSOR_K1OM
:
1481 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1486 case PROCESSOR_GENERIC64
:
1492 if (patt
== f32_patt
)
1494 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1495 /* Limit number of NOPs to 2 for older processors. */
1496 max_number_of_nops
= 2;
1500 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1501 /* Limit number of NOPs to 7 for newer processors. */
1502 max_number_of_nops
= 7;
1507 limit
= max_single_nop_size
;
1509 if (fragP
->fr_type
== rs_fill_nop
)
1511 /* Output NOPs for .nop directive. */
1512 if (limit
> max_single_nop_size
)
1514 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1515 _("invalid single nop size: %d "
1516 "(expect within [0, %d])"),
1517 limit
, max_single_nop_size
);
1522 fragP
->fr_var
= count
;
1524 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1526 /* Generate jump over NOPs. */
1527 offsetT disp
= count
- 2;
1528 if (fits_in_imm7 (disp
))
1530 /* Use "jmp disp8" if possible. */
1532 where
[0] = jump_disp8
[0];
1538 unsigned int size_of_jump
;
1540 if (flag_code
== CODE_16BIT
)
1542 where
[0] = jump16_disp32
[0];
1543 where
[1] = jump16_disp32
[1];
1548 where
[0] = jump32_disp32
[0];
1552 count
-= size_of_jump
+ 4;
1553 if (!fits_in_imm31 (count
))
1555 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1556 _("jump over nop padding out of range"));
1560 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1561 where
+= size_of_jump
+ 4;
1565 /* Generate multiple NOPs. */
1566 i386_output_nops (where
, patt
, count
, limit
);
1570 operand_type_all_zero (const union i386_operand_type
*x
)
1572 switch (ARRAY_SIZE(x
->array
))
1583 return !x
->array
[0];
1590 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1592 switch (ARRAY_SIZE(x
->array
))
1610 operand_type_equal (const union i386_operand_type
*x
,
1611 const union i386_operand_type
*y
)
1613 switch (ARRAY_SIZE(x
->array
))
1616 if (x
->array
[2] != y
->array
[2])
1620 if (x
->array
[1] != y
->array
[1])
1624 return x
->array
[0] == y
->array
[0];
1632 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1634 switch (ARRAY_SIZE(x
->array
))
1649 return !x
->array
[0];
1656 cpu_flags_equal (const union i386_cpu_flags
*x
,
1657 const union i386_cpu_flags
*y
)
1659 switch (ARRAY_SIZE(x
->array
))
1662 if (x
->array
[3] != y
->array
[3])
1666 if (x
->array
[2] != y
->array
[2])
1670 if (x
->array
[1] != y
->array
[1])
1674 return x
->array
[0] == y
->array
[0];
1682 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1684 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1685 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1688 static INLINE i386_cpu_flags
1689 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1691 switch (ARRAY_SIZE (x
.array
))
1694 x
.array
[3] &= y
.array
[3];
1697 x
.array
[2] &= y
.array
[2];
1700 x
.array
[1] &= y
.array
[1];
1703 x
.array
[0] &= y
.array
[0];
1711 static INLINE i386_cpu_flags
1712 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1714 switch (ARRAY_SIZE (x
.array
))
1717 x
.array
[3] |= y
.array
[3];
1720 x
.array
[2] |= y
.array
[2];
1723 x
.array
[1] |= y
.array
[1];
1726 x
.array
[0] |= y
.array
[0];
1734 static INLINE i386_cpu_flags
1735 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1737 switch (ARRAY_SIZE (x
.array
))
1740 x
.array
[3] &= ~y
.array
[3];
1743 x
.array
[2] &= ~y
.array
[2];
1746 x
.array
[1] &= ~y
.array
[1];
1749 x
.array
[0] &= ~y
.array
[0];
1757 #define CPU_FLAGS_ARCH_MATCH 0x1
1758 #define CPU_FLAGS_64BIT_MATCH 0x2
1760 #define CPU_FLAGS_PERFECT_MATCH \
1761 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1763 /* Return CPU flags match bits. */
1766 cpu_flags_match (const insn_template
*t
)
1768 i386_cpu_flags x
= t
->cpu_flags
;
1769 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1771 x
.bitfield
.cpu64
= 0;
1772 x
.bitfield
.cpuno64
= 0;
1774 if (cpu_flags_all_zero (&x
))
1776 /* This instruction is available on all archs. */
1777 match
|= CPU_FLAGS_ARCH_MATCH
;
1781 /* This instruction is available only on some archs. */
1782 i386_cpu_flags cpu
= cpu_arch_flags
;
1784 /* AVX512VL is no standalone feature - match it and then strip it. */
1785 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1787 x
.bitfield
.cpuavx512vl
= 0;
1789 cpu
= cpu_flags_and (x
, cpu
);
1790 if (!cpu_flags_all_zero (&cpu
))
1792 if (x
.bitfield
.cpuavx
)
1794 /* We need to check a few extra flags with AVX. */
1795 if (cpu
.bitfield
.cpuavx
1796 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1797 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1798 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1799 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1800 match
|= CPU_FLAGS_ARCH_MATCH
;
1802 else if (x
.bitfield
.cpuavx512f
)
1804 /* We need to check a few extra flags with AVX512F. */
1805 if (cpu
.bitfield
.cpuavx512f
1806 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1807 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1808 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1809 match
|= CPU_FLAGS_ARCH_MATCH
;
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1818 static INLINE i386_operand_type
1819 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1821 switch (ARRAY_SIZE (x
.array
))
1824 x
.array
[2] &= y
.array
[2];
1827 x
.array
[1] &= y
.array
[1];
1830 x
.array
[0] &= y
.array
[0];
1838 static INLINE i386_operand_type
1839 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1841 switch (ARRAY_SIZE (x
.array
))
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static INLINE i386_operand_type
1859 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1861 switch (ARRAY_SIZE (x
.array
))
1864 x
.array
[2] |= y
.array
[2];
1867 x
.array
[1] |= y
.array
[1];
1870 x
.array
[0] |= y
.array
[0];
1878 static INLINE i386_operand_type
1879 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1881 switch (ARRAY_SIZE (x
.array
))
1884 x
.array
[2] ^= y
.array
[2];
1887 x
.array
[1] ^= y
.array
[1];
1890 x
.array
[0] ^= y
.array
[0];
1898 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1899 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1900 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1901 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1902 static const i386_operand_type anydisp
1903 = OPERAND_TYPE_ANYDISP
;
1904 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1905 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1906 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1907 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1908 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1909 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1910 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1911 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1912 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1913 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1914 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1915 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1926 operand_type_check (i386_operand_type t
, enum operand_type c
)
1931 return t
.bitfield
.reg
;
1934 return (t
.bitfield
.imm8
1938 || t
.bitfield
.imm32s
1939 || t
.bitfield
.imm64
);
1942 return (t
.bitfield
.disp8
1943 || t
.bitfield
.disp16
1944 || t
.bitfield
.disp32
1945 || t
.bitfield
.disp32s
1946 || t
.bitfield
.disp64
);
1949 return (t
.bitfield
.disp8
1950 || t
.bitfield
.disp16
1951 || t
.bitfield
.disp32
1952 || t
.bitfield
.disp32s
1953 || t
.bitfield
.disp64
1954 || t
.bitfield
.baseindex
);
1963 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1964 between operand GIVEN and opeand WANTED for instruction template T. */
1967 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1970 return !((i
.types
[given
].bitfield
.byte
1971 && !t
->operand_types
[wanted
].bitfield
.byte
)
1972 || (i
.types
[given
].bitfield
.word
1973 && !t
->operand_types
[wanted
].bitfield
.word
)
1974 || (i
.types
[given
].bitfield
.dword
1975 && !t
->operand_types
[wanted
].bitfield
.dword
)
1976 || (i
.types
[given
].bitfield
.qword
1977 && !t
->operand_types
[wanted
].bitfield
.qword
)
1978 || (i
.types
[given
].bitfield
.tbyte
1979 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1982 /* Return 1 if there is no conflict in SIMD register between operand
1983 GIVEN and opeand WANTED for instruction template T. */
1986 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1989 return !((i
.types
[given
].bitfield
.xmmword
1990 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1991 || (i
.types
[given
].bitfield
.ymmword
1992 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1993 || (i
.types
[given
].bitfield
.zmmword
1994 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1997 /* Return 1 if there is no conflict in any size between operand GIVEN
1998 and opeand WANTED for instruction template T. */
2001 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2004 return (match_operand_size (t
, wanted
, given
)
2005 && !((i
.types
[given
].bitfield
.unspecified
2007 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2008 || (i
.types
[given
].bitfield
.fword
2009 && !t
->operand_types
[wanted
].bitfield
.fword
)
2010 /* For scalar opcode templates to allow register and memory
2011 operands at the same time, some special casing is needed
2012 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2013 down-conversion vpmov*. */
2014 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2015 && !t
->opcode_modifier
.broadcast
2016 && (t
->operand_types
[wanted
].bitfield
.byte
2017 || t
->operand_types
[wanted
].bitfield
.word
2018 || t
->operand_types
[wanted
].bitfield
.dword
2019 || t
->operand_types
[wanted
].bitfield
.qword
))
2020 ? (i
.types
[given
].bitfield
.xmmword
2021 || i
.types
[given
].bitfield
.ymmword
2022 || i
.types
[given
].bitfield
.zmmword
)
2023 : !match_simd_size(t
, wanted
, given
))));
2026 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2027 operands for instruction template T, and it has MATCH_REVERSE set if there
2028 is no size conflict on any operands for the template with operands reversed
2029 (and the template allows for reversing in the first place). */
2031 #define MATCH_STRAIGHT 1
2032 #define MATCH_REVERSE 2
2034 static INLINE
unsigned int
2035 operand_size_match (const insn_template
*t
)
2037 unsigned int j
, match
= MATCH_STRAIGHT
;
2039 /* Don't check jump instructions. */
2040 if (t
->opcode_modifier
.jump
2041 || t
->opcode_modifier
.jumpbyte
2042 || t
->opcode_modifier
.jumpdword
2043 || t
->opcode_modifier
.jumpintersegment
)
2046 /* Check memory and accumulator operand size. */
2047 for (j
= 0; j
< i
.operands
; j
++)
2049 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2050 && t
->operand_types
[j
].bitfield
.anysize
)
2053 if (t
->operand_types
[j
].bitfield
.reg
2054 && !match_operand_size (t
, j
, j
))
2060 if (t
->operand_types
[j
].bitfield
.regsimd
2061 && !match_simd_size (t
, j
, j
))
2067 if (t
->operand_types
[j
].bitfield
.acc
2068 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2074 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2081 if (!t
->opcode_modifier
.d
)
2085 i
.error
= operand_size_mismatch
;
2089 /* Check reverse. */
2090 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2092 for (j
= 0; j
< i
.operands
; j
++)
2094 unsigned int given
= i
.operands
- j
- 1;
2096 if (t
->operand_types
[j
].bitfield
.reg
2097 && !match_operand_size (t
, j
, given
))
2100 if (t
->operand_types
[j
].bitfield
.regsimd
2101 && !match_simd_size (t
, j
, given
))
2104 if (t
->operand_types
[j
].bitfield
.acc
2105 && (!match_operand_size (t
, j
, given
)
2106 || !match_simd_size (t
, j
, given
)))
2109 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2113 return match
| MATCH_REVERSE
;
2117 operand_type_match (i386_operand_type overlap
,
2118 i386_operand_type given
)
2120 i386_operand_type temp
= overlap
;
2122 temp
.bitfield
.jumpabsolute
= 0;
2123 temp
.bitfield
.unspecified
= 0;
2124 temp
.bitfield
.byte
= 0;
2125 temp
.bitfield
.word
= 0;
2126 temp
.bitfield
.dword
= 0;
2127 temp
.bitfield
.fword
= 0;
2128 temp
.bitfield
.qword
= 0;
2129 temp
.bitfield
.tbyte
= 0;
2130 temp
.bitfield
.xmmword
= 0;
2131 temp
.bitfield
.ymmword
= 0;
2132 temp
.bitfield
.zmmword
= 0;
2133 if (operand_type_all_zero (&temp
))
2136 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2137 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2141 i
.error
= operand_type_mismatch
;
2145 /* If given types g0 and g1 are registers they must be of the same type
2146 unless the expected operand type register overlap is null.
2147 Memory operand size of certain SIMD instructions is also being checked
2151 operand_type_register_match (i386_operand_type g0
,
2152 i386_operand_type t0
,
2153 i386_operand_type g1
,
2154 i386_operand_type t1
)
2156 if (!g0
.bitfield
.reg
2157 && !g0
.bitfield
.regsimd
2158 && (!operand_type_check (g0
, anymem
)
2159 || g0
.bitfield
.unspecified
2160 || !t0
.bitfield
.regsimd
))
2163 if (!g1
.bitfield
.reg
2164 && !g1
.bitfield
.regsimd
2165 && (!operand_type_check (g1
, anymem
)
2166 || g1
.bitfield
.unspecified
2167 || !t1
.bitfield
.regsimd
))
2170 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2171 && g0
.bitfield
.word
== g1
.bitfield
.word
2172 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2173 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2174 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2175 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2176 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2179 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2180 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2181 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2182 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2183 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2184 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2185 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2188 i
.error
= register_type_mismatch
;
2193 static INLINE
unsigned int
2194 register_number (const reg_entry
*r
)
2196 unsigned int nr
= r
->reg_num
;
2198 if (r
->reg_flags
& RegRex
)
2201 if (r
->reg_flags
& RegVRex
)
2207 static INLINE
unsigned int
2208 mode_from_disp_size (i386_operand_type t
)
2210 if (t
.bitfield
.disp8
)
2212 else if (t
.bitfield
.disp16
2213 || t
.bitfield
.disp32
2214 || t
.bitfield
.disp32s
)
2221 fits_in_signed_byte (addressT num
)
2223 return num
+ 0x80 <= 0xff;
2227 fits_in_unsigned_byte (addressT num
)
2233 fits_in_unsigned_word (addressT num
)
2235 return num
<= 0xffff;
2239 fits_in_signed_word (addressT num
)
2241 return num
+ 0x8000 <= 0xffff;
2245 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2250 return num
+ 0x80000000 <= 0xffffffff;
2252 } /* fits_in_signed_long() */
2255 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2260 return num
<= 0xffffffff;
2262 } /* fits_in_unsigned_long() */
2265 fits_in_disp8 (offsetT num
)
2267 int shift
= i
.memshift
;
2273 mask
= (1 << shift
) - 1;
2275 /* Return 0 if NUM isn't properly aligned. */
2279 /* Check if NUM will fit in 8bit after shift. */
2280 return fits_in_signed_byte (num
>> shift
);
2284 fits_in_imm4 (offsetT num
)
2286 return (num
& 0xf) == num
;
2289 static i386_operand_type
2290 smallest_imm_type (offsetT num
)
2292 i386_operand_type t
;
2294 operand_type_set (&t
, 0);
2295 t
.bitfield
.imm64
= 1;
2297 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2299 /* This code is disabled on the 486 because all the Imm1 forms
2300 in the opcode table are slower on the i486. They're the
2301 versions with the implicitly specified single-position
2302 displacement, which has another syntax if you really want to
2304 t
.bitfield
.imm1
= 1;
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm8s
= 1;
2307 t
.bitfield
.imm16
= 1;
2308 t
.bitfield
.imm32
= 1;
2309 t
.bitfield
.imm32s
= 1;
2311 else if (fits_in_signed_byte (num
))
2313 t
.bitfield
.imm8
= 1;
2314 t
.bitfield
.imm8s
= 1;
2315 t
.bitfield
.imm16
= 1;
2316 t
.bitfield
.imm32
= 1;
2317 t
.bitfield
.imm32s
= 1;
2319 else if (fits_in_unsigned_byte (num
))
2321 t
.bitfield
.imm8
= 1;
2322 t
.bitfield
.imm16
= 1;
2323 t
.bitfield
.imm32
= 1;
2324 t
.bitfield
.imm32s
= 1;
2326 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2328 t
.bitfield
.imm16
= 1;
2329 t
.bitfield
.imm32
= 1;
2330 t
.bitfield
.imm32s
= 1;
2332 else if (fits_in_signed_long (num
))
2334 t
.bitfield
.imm32
= 1;
2335 t
.bitfield
.imm32s
= 1;
2337 else if (fits_in_unsigned_long (num
))
2338 t
.bitfield
.imm32
= 1;
2344 offset_in_range (offsetT val
, int size
)
2350 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2351 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2352 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2354 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2360 /* If BFD64, sign extend val for 32bit address mode. */
2361 if (flag_code
!= CODE_64BIT
2362 || i
.prefix
[ADDR_PREFIX
])
2363 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2364 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2367 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2369 char buf1
[40], buf2
[40];
2371 sprint_value (buf1
, val
);
2372 sprint_value (buf2
, val
& mask
);
2373 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2388 a. PREFIX_EXIST if attempting to add a prefix where one from the
2389 same class already exists.
2390 b. PREFIX_LOCK if lock prefix is added.
2391 c. PREFIX_REP if rep/repne prefix is added.
2392 d. PREFIX_DS if ds prefix is added.
2393 e. PREFIX_OTHER if other prefix is added.
2396 static enum PREFIX_GROUP
2397 add_prefix (unsigned int prefix
)
2399 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2402 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2403 && flag_code
== CODE_64BIT
)
2405 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2406 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2407 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2408 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2419 case DS_PREFIX_OPCODE
:
2422 case CS_PREFIX_OPCODE
:
2423 case ES_PREFIX_OPCODE
:
2424 case FS_PREFIX_OPCODE
:
2425 case GS_PREFIX_OPCODE
:
2426 case SS_PREFIX_OPCODE
:
2430 case REPNE_PREFIX_OPCODE
:
2431 case REPE_PREFIX_OPCODE
:
2436 case LOCK_PREFIX_OPCODE
:
2445 case ADDR_PREFIX_OPCODE
:
2449 case DATA_PREFIX_OPCODE
:
2453 if (i
.prefix
[q
] != 0)
2461 i
.prefix
[q
] |= prefix
;
2464 as_bad (_("same type of prefix used twice"));
2470 update_code_flag (int value
, int check
)
2472 PRINTF_LIKE ((*as_error
));
2474 flag_code
= (enum flag_code
) value
;
2475 if (flag_code
== CODE_64BIT
)
2477 cpu_arch_flags
.bitfield
.cpu64
= 1;
2478 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2482 cpu_arch_flags
.bitfield
.cpu64
= 0;
2483 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2485 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2488 as_error
= as_fatal
;
2491 (*as_error
) (_("64bit mode not supported on `%s'."),
2492 cpu_arch_name
? cpu_arch_name
: default_arch
);
2494 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2497 as_error
= as_fatal
;
2500 (*as_error
) (_("32bit mode not supported on `%s'."),
2501 cpu_arch_name
? cpu_arch_name
: default_arch
);
2503 stackop_size
= '\0';
2507 set_code_flag (int value
)
2509 update_code_flag (value
, 0);
2513 set_16bit_gcc_code_flag (int new_code_flag
)
2515 flag_code
= (enum flag_code
) new_code_flag
;
2516 if (flag_code
!= CODE_16BIT
)
2518 cpu_arch_flags
.bitfield
.cpu64
= 0;
2519 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2520 stackop_size
= LONG_MNEM_SUFFIX
;
2524 set_intel_syntax (int syntax_flag
)
2526 /* Find out if register prefixing is specified. */
2527 int ask_naked_reg
= 0;
2530 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2533 int e
= get_symbol_name (&string
);
2535 if (strcmp (string
, "prefix") == 0)
2537 else if (strcmp (string
, "noprefix") == 0)
2540 as_bad (_("bad argument to syntax directive."));
2541 (void) restore_line_pointer (e
);
2543 demand_empty_rest_of_line ();
2545 intel_syntax
= syntax_flag
;
2547 if (ask_naked_reg
== 0)
2548 allow_naked_reg
= (intel_syntax
2549 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2551 allow_naked_reg
= (ask_naked_reg
< 0);
2553 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2555 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2556 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2557 register_prefix
= allow_naked_reg
? "" : "%";
2561 set_intel_mnemonic (int mnemonic_flag
)
2563 intel_mnemonic
= mnemonic_flag
;
2567 set_allow_index_reg (int flag
)
2569 allow_index_reg
= flag
;
2573 set_check (int what
)
2575 enum check_kind
*kind
;
2580 kind
= &operand_check
;
2591 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2594 int e
= get_symbol_name (&string
);
2596 if (strcmp (string
, "none") == 0)
2598 else if (strcmp (string
, "warning") == 0)
2599 *kind
= check_warning
;
2600 else if (strcmp (string
, "error") == 0)
2601 *kind
= check_error
;
2603 as_bad (_("bad argument to %s_check directive."), str
);
2604 (void) restore_line_pointer (e
);
2607 as_bad (_("missing argument for %s_check directive"), str
);
2609 demand_empty_rest_of_line ();
2613 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2614 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2617 static const char *arch
;
2619 /* Intel LIOM is only supported on ELF. */
2625 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2626 use default_arch. */
2627 arch
= cpu_arch_name
;
2629 arch
= default_arch
;
2632 /* If we are targeting Intel MCU, we must enable it. */
2633 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2634 || new_flag
.bitfield
.cpuiamcu
)
2637 /* If we are targeting Intel L1OM, we must enable it. */
2638 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2639 || new_flag
.bitfield
.cpul1om
)
2642 /* If we are targeting Intel K1OM, we must enable it. */
2643 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2644 || new_flag
.bitfield
.cpuk1om
)
2647 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2652 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2656 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2659 int e
= get_symbol_name (&string
);
2661 i386_cpu_flags flags
;
2663 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2665 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2667 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2671 cpu_arch_name
= cpu_arch
[j
].name
;
2672 cpu_sub_arch_name
= NULL
;
2673 cpu_arch_flags
= cpu_arch
[j
].flags
;
2674 if (flag_code
== CODE_64BIT
)
2676 cpu_arch_flags
.bitfield
.cpu64
= 1;
2677 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2681 cpu_arch_flags
.bitfield
.cpu64
= 0;
2682 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2684 cpu_arch_isa
= cpu_arch
[j
].type
;
2685 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2686 if (!cpu_arch_tune_set
)
2688 cpu_arch_tune
= cpu_arch_isa
;
2689 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2694 flags
= cpu_flags_or (cpu_arch_flags
,
2697 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2699 if (cpu_sub_arch_name
)
2701 char *name
= cpu_sub_arch_name
;
2702 cpu_sub_arch_name
= concat (name
,
2704 (const char *) NULL
);
2708 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2709 cpu_arch_flags
= flags
;
2710 cpu_arch_isa_flags
= flags
;
2714 = cpu_flags_or (cpu_arch_isa_flags
,
2716 (void) restore_line_pointer (e
);
2717 demand_empty_rest_of_line ();
2722 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2724 /* Disable an ISA extension. */
2725 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2726 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2728 flags
= cpu_flags_and_not (cpu_arch_flags
,
2729 cpu_noarch
[j
].flags
);
2730 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2732 if (cpu_sub_arch_name
)
2734 char *name
= cpu_sub_arch_name
;
2735 cpu_sub_arch_name
= concat (name
, string
,
2736 (const char *) NULL
);
2740 cpu_sub_arch_name
= xstrdup (string
);
2741 cpu_arch_flags
= flags
;
2742 cpu_arch_isa_flags
= flags
;
2744 (void) restore_line_pointer (e
);
2745 demand_empty_rest_of_line ();
2749 j
= ARRAY_SIZE (cpu_arch
);
2752 if (j
>= ARRAY_SIZE (cpu_arch
))
2753 as_bad (_("no such architecture: `%s'"), string
);
2755 *input_line_pointer
= e
;
2758 as_bad (_("missing cpu architecture"));
2760 no_cond_jump_promotion
= 0;
2761 if (*input_line_pointer
== ','
2762 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2767 ++input_line_pointer
;
2768 e
= get_symbol_name (&string
);
2770 if (strcmp (string
, "nojumps") == 0)
2771 no_cond_jump_promotion
= 1;
2772 else if (strcmp (string
, "jumps") == 0)
2775 as_bad (_("no such architecture modifier: `%s'"), string
);
2777 (void) restore_line_pointer (e
);
2780 demand_empty_rest_of_line ();
2783 enum bfd_architecture
2786 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2788 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2789 || flag_code
!= CODE_64BIT
)
2790 as_fatal (_("Intel L1OM is 64bit ELF only"));
2791 return bfd_arch_l1om
;
2793 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2795 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2796 || flag_code
!= CODE_64BIT
)
2797 as_fatal (_("Intel K1OM is 64bit ELF only"));
2798 return bfd_arch_k1om
;
2800 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || flag_code
== CODE_64BIT
)
2804 as_fatal (_("Intel MCU is 32bit ELF only"));
2805 return bfd_arch_iamcu
;
2808 return bfd_arch_i386
;
2814 if (!strncmp (default_arch
, "x86_64", 6))
2816 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2818 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2819 || default_arch
[6] != '\0')
2820 as_fatal (_("Intel L1OM is 64bit ELF only"));
2821 return bfd_mach_l1om
;
2823 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2825 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2826 || default_arch
[6] != '\0')
2827 as_fatal (_("Intel K1OM is 64bit ELF only"));
2828 return bfd_mach_k1om
;
2830 else if (default_arch
[6] == '\0')
2831 return bfd_mach_x86_64
;
2833 return bfd_mach_x64_32
;
2835 else if (!strcmp (default_arch
, "i386")
2836 || !strcmp (default_arch
, "iamcu"))
2838 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2840 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2841 as_fatal (_("Intel MCU is 32bit ELF only"));
2842 return bfd_mach_i386_iamcu
;
2845 return bfd_mach_i386_i386
;
2848 as_fatal (_("unknown architecture"));
2854 const char *hash_err
;
2856 /* Support pseudo prefixes like {disp32}. */
2857 lex_type
['{'] = LEX_BEGIN_NAME
;
2859 /* Initialize op_hash hash table. */
2860 op_hash
= hash_new ();
2863 const insn_template
*optab
;
2864 templates
*core_optab
;
2866 /* Setup for loop. */
2868 core_optab
= XNEW (templates
);
2869 core_optab
->start
= optab
;
2874 if (optab
->name
== NULL
2875 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2877 /* different name --> ship out current template list;
2878 add to hash table; & begin anew. */
2879 core_optab
->end
= optab
;
2880 hash_err
= hash_insert (op_hash
,
2882 (void *) core_optab
);
2885 as_fatal (_("can't hash %s: %s"),
2889 if (optab
->name
== NULL
)
2891 core_optab
= XNEW (templates
);
2892 core_optab
->start
= optab
;
2897 /* Initialize reg_hash hash table. */
2898 reg_hash
= hash_new ();
2900 const reg_entry
*regtab
;
2901 unsigned int regtab_size
= i386_regtab_size
;
2903 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2905 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2907 as_fatal (_("can't hash %s: %s"),
2913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2918 for (c
= 0; c
< 256; c
++)
2923 mnemonic_chars
[c
] = c
;
2924 register_chars
[c
] = c
;
2925 operand_chars
[c
] = c
;
2927 else if (ISLOWER (c
))
2929 mnemonic_chars
[c
] = c
;
2930 register_chars
[c
] = c
;
2931 operand_chars
[c
] = c
;
2933 else if (ISUPPER (c
))
2935 mnemonic_chars
[c
] = TOLOWER (c
);
2936 register_chars
[c
] = mnemonic_chars
[c
];
2937 operand_chars
[c
] = c
;
2939 else if (c
== '{' || c
== '}')
2941 mnemonic_chars
[c
] = c
;
2942 operand_chars
[c
] = c
;
2945 if (ISALPHA (c
) || ISDIGIT (c
))
2946 identifier_chars
[c
] = c
;
2949 identifier_chars
[c
] = c
;
2950 operand_chars
[c
] = c
;
2955 identifier_chars
['@'] = '@';
2958 identifier_chars
['?'] = '?';
2959 operand_chars
['?'] = '?';
2961 digit_chars
['-'] = '-';
2962 mnemonic_chars
['_'] = '_';
2963 mnemonic_chars
['-'] = '-';
2964 mnemonic_chars
['.'] = '.';
2965 identifier_chars
['_'] = '_';
2966 identifier_chars
['.'] = '.';
2968 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2969 operand_chars
[(unsigned char) *p
] = *p
;
2972 if (flag_code
== CODE_64BIT
)
2974 #if defined (OBJ_COFF) && defined (TE_PE)
2975 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2978 x86_dwarf2_return_column
= 16;
2980 x86_cie_data_alignment
= -8;
2984 x86_dwarf2_return_column
= 8;
2985 x86_cie_data_alignment
= -4;
2990 i386_print_statistics (FILE *file
)
2992 hash_print_statistics (file
, "i386 opcode", op_hash
);
2993 hash_print_statistics (file
, "i386 register", reg_hash
);
2998 /* Debugging routines for md_assemble. */
2999 static void pte (insn_template
*);
3000 static void pt (i386_operand_type
);
3001 static void pe (expressionS
*);
3002 static void ps (symbolS
*);
3005 pi (const char *line
, i386_insn
*x
)
3009 fprintf (stdout
, "%s: template ", line
);
3011 fprintf (stdout
, " address: base %s index %s scale %x\n",
3012 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3013 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3014 x
->log2_scale_factor
);
3015 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3016 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3017 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3018 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3019 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3020 (x
->rex
& REX_W
) != 0,
3021 (x
->rex
& REX_R
) != 0,
3022 (x
->rex
& REX_X
) != 0,
3023 (x
->rex
& REX_B
) != 0);
3024 for (j
= 0; j
< x
->operands
; j
++)
3026 fprintf (stdout
, " #%d: ", j
+ 1);
3028 fprintf (stdout
, "\n");
3029 if (x
->types
[j
].bitfield
.reg
3030 || x
->types
[j
].bitfield
.regmmx
3031 || x
->types
[j
].bitfield
.regsimd
3032 || x
->types
[j
].bitfield
.sreg2
3033 || x
->types
[j
].bitfield
.sreg3
3034 || x
->types
[j
].bitfield
.control
3035 || x
->types
[j
].bitfield
.debug
3036 || x
->types
[j
].bitfield
.test
)
3037 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3038 if (operand_type_check (x
->types
[j
], imm
))
3040 if (operand_type_check (x
->types
[j
], disp
))
3041 pe (x
->op
[j
].disps
);
3046 pte (insn_template
*t
)
3049 fprintf (stdout
, " %d operands ", t
->operands
);
3050 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3051 if (t
->extension_opcode
!= None
)
3052 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3053 if (t
->opcode_modifier
.d
)
3054 fprintf (stdout
, "D");
3055 if (t
->opcode_modifier
.w
)
3056 fprintf (stdout
, "W");
3057 fprintf (stdout
, "\n");
3058 for (j
= 0; j
< t
->operands
; j
++)
3060 fprintf (stdout
, " #%d type ", j
+ 1);
3061 pt (t
->operand_types
[j
]);
3062 fprintf (stdout
, "\n");
3069 fprintf (stdout
, " operation %d\n", e
->X_op
);
3070 fprintf (stdout
, " add_number %ld (%lx)\n",
3071 (long) e
->X_add_number
, (long) e
->X_add_number
);
3072 if (e
->X_add_symbol
)
3074 fprintf (stdout
, " add_symbol ");
3075 ps (e
->X_add_symbol
);
3076 fprintf (stdout
, "\n");
3080 fprintf (stdout
, " op_symbol ");
3081 ps (e
->X_op_symbol
);
3082 fprintf (stdout
, "\n");
3089 fprintf (stdout
, "%s type %s%s",
3091 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3092 segment_name (S_GET_SEGMENT (s
)));
3095 static struct type_name
3097 i386_operand_type mask
;
3100 const type_names
[] =
3102 { OPERAND_TYPE_REG8
, "r8" },
3103 { OPERAND_TYPE_REG16
, "r16" },
3104 { OPERAND_TYPE_REG32
, "r32" },
3105 { OPERAND_TYPE_REG64
, "r64" },
3106 { OPERAND_TYPE_ACC8
, "acc8" },
3107 { OPERAND_TYPE_ACC16
, "acc16" },
3108 { OPERAND_TYPE_ACC32
, "acc32" },
3109 { OPERAND_TYPE_ACC64
, "acc64" },
3110 { OPERAND_TYPE_IMM8
, "i8" },
3111 { OPERAND_TYPE_IMM8
, "i8s" },
3112 { OPERAND_TYPE_IMM16
, "i16" },
3113 { OPERAND_TYPE_IMM32
, "i32" },
3114 { OPERAND_TYPE_IMM32S
, "i32s" },
3115 { OPERAND_TYPE_IMM64
, "i64" },
3116 { OPERAND_TYPE_IMM1
, "i1" },
3117 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3118 { OPERAND_TYPE_DISP8
, "d8" },
3119 { OPERAND_TYPE_DISP16
, "d16" },
3120 { OPERAND_TYPE_DISP32
, "d32" },
3121 { OPERAND_TYPE_DISP32S
, "d32s" },
3122 { OPERAND_TYPE_DISP64
, "d64" },
3123 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3124 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3125 { OPERAND_TYPE_CONTROL
, "control reg" },
3126 { OPERAND_TYPE_TEST
, "test reg" },
3127 { OPERAND_TYPE_DEBUG
, "debug reg" },
3128 { OPERAND_TYPE_FLOATREG
, "FReg" },
3129 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3130 { OPERAND_TYPE_SREG2
, "SReg2" },
3131 { OPERAND_TYPE_SREG3
, "SReg3" },
3132 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3133 { OPERAND_TYPE_REGMMX
, "rMMX" },
3134 { OPERAND_TYPE_REGXMM
, "rXMM" },
3135 { OPERAND_TYPE_REGYMM
, "rYMM" },
3136 { OPERAND_TYPE_REGZMM
, "rZMM" },
3137 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3138 { OPERAND_TYPE_ESSEG
, "es" },
3142 pt (i386_operand_type t
)
3145 i386_operand_type a
;
3147 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3149 a
= operand_type_and (t
, type_names
[j
].mask
);
3150 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3151 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3156 #endif /* DEBUG386 */
3158 static bfd_reloc_code_real_type
3159 reloc (unsigned int size
,
3162 bfd_reloc_code_real_type other
)
3164 if (other
!= NO_RELOC
)
3166 reloc_howto_type
*rel
;
3171 case BFD_RELOC_X86_64_GOT32
:
3172 return BFD_RELOC_X86_64_GOT64
;
3174 case BFD_RELOC_X86_64_GOTPLT64
:
3175 return BFD_RELOC_X86_64_GOTPLT64
;
3177 case BFD_RELOC_X86_64_PLTOFF64
:
3178 return BFD_RELOC_X86_64_PLTOFF64
;
3180 case BFD_RELOC_X86_64_GOTPC32
:
3181 other
= BFD_RELOC_X86_64_GOTPC64
;
3183 case BFD_RELOC_X86_64_GOTPCREL
:
3184 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3186 case BFD_RELOC_X86_64_TPOFF32
:
3187 other
= BFD_RELOC_X86_64_TPOFF64
;
3189 case BFD_RELOC_X86_64_DTPOFF32
:
3190 other
= BFD_RELOC_X86_64_DTPOFF64
;
3196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3197 if (other
== BFD_RELOC_SIZE32
)
3200 other
= BFD_RELOC_SIZE64
;
3203 as_bad (_("there are no pc-relative size relocations"));
3209 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3210 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3213 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3215 as_bad (_("unknown relocation (%u)"), other
);
3216 else if (size
!= bfd_get_reloc_size (rel
))
3217 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3218 bfd_get_reloc_size (rel
),
3220 else if (pcrel
&& !rel
->pc_relative
)
3221 as_bad (_("non-pc-relative relocation for pc-relative field"));
3222 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3224 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3226 as_bad (_("relocated field and relocation type differ in signedness"));
3235 as_bad (_("there are no unsigned pc-relative relocations"));
3238 case 1: return BFD_RELOC_8_PCREL
;
3239 case 2: return BFD_RELOC_16_PCREL
;
3240 case 4: return BFD_RELOC_32_PCREL
;
3241 case 8: return BFD_RELOC_64_PCREL
;
3243 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3250 case 4: return BFD_RELOC_X86_64_32S
;
3255 case 1: return BFD_RELOC_8
;
3256 case 2: return BFD_RELOC_16
;
3257 case 4: return BFD_RELOC_32
;
3258 case 8: return BFD_RELOC_64
;
3260 as_bad (_("cannot do %s %u byte relocation"),
3261 sign
> 0 ? "signed" : "unsigned", size
);
3267 /* Here we decide which fixups can be adjusted to make them relative to
3268 the beginning of the section instead of the symbol. Basically we need
3269 to make sure that the dynamic relocations are done correctly, so in
3270 some cases we force the original symbol to be used. */
3273 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3279 /* Don't adjust pc-relative references to merge sections in 64-bit
3281 if (use_rela_relocations
3282 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3286 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3287 and changed later by validate_fix. */
3288 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3289 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3292 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3293 for size relocations. */
3294 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3295 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3296 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3297 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3298 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3325 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3326 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3333 intel_float_operand (const char *mnemonic
)
3335 /* Note that the value returned is meaningful only for opcodes with (memory)
3336 operands, hence the code here is free to improperly handle opcodes that
3337 have no operands (for better performance and smaller code). */
3339 if (mnemonic
[0] != 'f')
3340 return 0; /* non-math */
3342 switch (mnemonic
[1])
3344 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3345 the fs segment override prefix not currently handled because no
3346 call path can make opcodes without operands get here */
3348 return 2 /* integer op */;
3350 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3351 return 3; /* fldcw/fldenv */
3354 if (mnemonic
[2] != 'o' /* fnop */)
3355 return 3; /* non-waiting control op */
3358 if (mnemonic
[2] == 's')
3359 return 3; /* frstor/frstpm */
3362 if (mnemonic
[2] == 'a')
3363 return 3; /* fsave */
3364 if (mnemonic
[2] == 't')
3366 switch (mnemonic
[3])
3368 case 'c': /* fstcw */
3369 case 'd': /* fstdw */
3370 case 'e': /* fstenv */
3371 case 's': /* fsts[gw] */
3377 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3378 return 0; /* fxsave/fxrstor are not really math ops */
3385 /* Build the VEX prefix. */
3388 build_vex_prefix (const insn_template
*t
)
3390 unsigned int register_specifier
;
3391 unsigned int implied_prefix
;
3392 unsigned int vector_length
;
3395 /* Check register specifier. */
3396 if (i
.vex
.register_specifier
)
3398 register_specifier
=
3399 ~register_number (i
.vex
.register_specifier
) & 0xf;
3400 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3403 register_specifier
= 0xf;
3405 /* Use 2-byte VEX prefix by swapping destination and source operand
3406 if there are more than 1 register operand. */
3407 if (i
.reg_operands
> 1
3408 && i
.vec_encoding
!= vex_encoding_vex3
3409 && i
.dir_encoding
== dir_encoding_default
3410 && i
.operands
== i
.reg_operands
3411 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3412 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3413 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3416 unsigned int xchg
= i
.operands
- 1;
3417 union i386_op temp_op
;
3418 i386_operand_type temp_type
;
3420 temp_type
= i
.types
[xchg
];
3421 i
.types
[xchg
] = i
.types
[0];
3422 i
.types
[0] = temp_type
;
3423 temp_op
= i
.op
[xchg
];
3424 i
.op
[xchg
] = i
.op
[0];
3427 gas_assert (i
.rm
.mode
== 3);
3431 i
.rm
.regmem
= i
.rm
.reg
;
3434 if (i
.tm
.opcode_modifier
.d
)
3435 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3436 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3437 else /* Use the next insn. */
3441 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3442 vector_length
= avxscalar
;
3443 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3449 /* Determine vector length from the last multi-length vector
3452 for (op
= t
->operands
; op
--;)
3453 if (t
->operand_types
[op
].bitfield
.xmmword
3454 && t
->operand_types
[op
].bitfield
.ymmword
3455 && i
.types
[op
].bitfield
.ymmword
)
3462 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3467 case DATA_PREFIX_OPCODE
:
3470 case REPE_PREFIX_OPCODE
:
3473 case REPNE_PREFIX_OPCODE
:
3480 /* Check the REX.W bit and VEXW. */
3481 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3482 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3483 else if (i
.tm
.opcode_modifier
.vexw
)
3484 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3486 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3488 /* Use 2-byte VEX prefix if possible. */
3490 && i
.vec_encoding
!= vex_encoding_vex3
3491 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3492 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3494 /* 2-byte VEX prefix. */
3498 i
.vex
.bytes
[0] = 0xc5;
3500 /* Check the REX.R bit. */
3501 r
= (i
.rex
& REX_R
) ? 0 : 1;
3502 i
.vex
.bytes
[1] = (r
<< 7
3503 | register_specifier
<< 3
3504 | vector_length
<< 2
3509 /* 3-byte VEX prefix. */
3514 switch (i
.tm
.opcode_modifier
.vexopcode
)
3518 i
.vex
.bytes
[0] = 0xc4;
3522 i
.vex
.bytes
[0] = 0xc4;
3526 i
.vex
.bytes
[0] = 0xc4;
3530 i
.vex
.bytes
[0] = 0x8f;
3534 i
.vex
.bytes
[0] = 0x8f;
3538 i
.vex
.bytes
[0] = 0x8f;
3544 /* The high 3 bits of the second VEX byte are 1's compliment
3545 of RXB bits from REX. */
3546 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3548 i
.vex
.bytes
[2] = (w
<< 7
3549 | register_specifier
<< 3
3550 | vector_length
<< 2
3555 static INLINE bfd_boolean
3556 is_evex_encoding (const insn_template
*t
)
3558 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3559 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3560 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3563 static INLINE bfd_boolean
3564 is_any_vex_encoding (const insn_template
*t
)
3566 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3567 || is_evex_encoding (t
);
3570 /* Build the EVEX prefix. */
3573 build_evex_prefix (void)
3575 unsigned int register_specifier
;
3576 unsigned int implied_prefix
;
3578 rex_byte vrex_used
= 0;
3580 /* Check register specifier. */
3581 if (i
.vex
.register_specifier
)
3583 gas_assert ((i
.vrex
& REX_X
) == 0);
3585 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3586 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3587 register_specifier
+= 8;
3588 /* The upper 16 registers are encoded in the fourth byte of the
3590 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3591 i
.vex
.bytes
[3] = 0x8;
3592 register_specifier
= ~register_specifier
& 0xf;
3596 register_specifier
= 0xf;
3598 /* Encode upper 16 vector index register in the fourth byte of
3600 if (!(i
.vrex
& REX_X
))
3601 i
.vex
.bytes
[3] = 0x8;
3606 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3611 case DATA_PREFIX_OPCODE
:
3614 case REPE_PREFIX_OPCODE
:
3617 case REPNE_PREFIX_OPCODE
:
3624 /* 4 byte EVEX prefix. */
3626 i
.vex
.bytes
[0] = 0x62;
3629 switch (i
.tm
.opcode_modifier
.vexopcode
)
3645 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3647 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3649 /* The fifth bit of the second EVEX byte is 1's compliment of the
3650 REX_R bit in VREX. */
3651 if (!(i
.vrex
& REX_R
))
3652 i
.vex
.bytes
[1] |= 0x10;
3656 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3658 /* When all operands are registers, the REX_X bit in REX is not
3659 used. We reuse it to encode the upper 16 registers, which is
3660 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3661 as 1's compliment. */
3662 if ((i
.vrex
& REX_B
))
3665 i
.vex
.bytes
[1] &= ~0x40;
3669 /* EVEX instructions shouldn't need the REX prefix. */
3670 i
.vrex
&= ~vrex_used
;
3671 gas_assert (i
.vrex
== 0);
3673 /* Check the REX.W bit and VEXW. */
3674 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3675 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3676 else if (i
.tm
.opcode_modifier
.vexw
)
3677 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3679 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3681 /* Encode the U bit. */
3682 implied_prefix
|= 0x4;
3684 /* The third byte of the EVEX prefix. */
3685 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3687 /* The fourth byte of the EVEX prefix. */
3688 /* The zeroing-masking bit. */
3689 if (i
.mask
&& i
.mask
->zeroing
)
3690 i
.vex
.bytes
[3] |= 0x80;
3692 /* Don't always set the broadcast bit if there is no RC. */
3695 /* Encode the vector length. */
3696 unsigned int vec_length
;
3698 if (!i
.tm
.opcode_modifier
.evex
3699 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3703 /* Determine vector length from the last multi-length vector
3706 for (op
= i
.operands
; op
--;)
3707 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3708 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3709 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3711 if (i
.types
[op
].bitfield
.zmmword
)
3713 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3716 else if (i
.types
[op
].bitfield
.ymmword
)
3718 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3721 else if (i
.types
[op
].bitfield
.xmmword
)
3723 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3726 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3728 switch (i
.broadcast
->bytes
)
3731 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3734 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3737 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3746 if (op
>= MAX_OPERANDS
)
3750 switch (i
.tm
.opcode_modifier
.evex
)
3752 case EVEXLIG
: /* LL' is ignored */
3753 vec_length
= evexlig
<< 5;
3756 vec_length
= 0 << 5;
3759 vec_length
= 1 << 5;
3762 vec_length
= 2 << 5;
3768 i
.vex
.bytes
[3] |= vec_length
;
3769 /* Encode the broadcast bit. */
3771 i
.vex
.bytes
[3] |= 0x10;
3775 if (i
.rounding
->type
!= saeonly
)
3776 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3778 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3781 if (i
.mask
&& i
.mask
->mask
)
3782 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3786 process_immext (void)
3790 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3793 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3794 with an opcode suffix which is coded in the same place as an
3795 8-bit immediate field would be.
3796 Here we check those operands and remove them afterwards. */
3799 for (x
= 0; x
< i
.operands
; x
++)
3800 if (register_number (i
.op
[x
].regs
) != x
)
3801 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3802 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3808 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3810 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3811 suffix which is coded in the same place as an 8-bit immediate
3813 Here we check those operands and remove them afterwards. */
3816 if (i
.operands
!= 3)
3819 for (x
= 0; x
< 2; x
++)
3820 if (register_number (i
.op
[x
].regs
) != x
)
3821 goto bad_register_operand
;
3823 /* Check for third operand for mwaitx/monitorx insn. */
3824 if (register_number (i
.op
[x
].regs
)
3825 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3827 bad_register_operand
:
3828 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3829 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3836 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3837 which is coded in the same place as an 8-bit immediate field
3838 would be. Here we fake an 8-bit immediate operand from the
3839 opcode suffix stored in tm.extension_opcode.
3841 AVX instructions also use this encoding, for some of
3842 3 argument instructions. */
3844 gas_assert (i
.imm_operands
<= 1
3846 || (is_any_vex_encoding (&i
.tm
)
3847 && i
.operands
<= 4)));
3849 exp
= &im_expressions
[i
.imm_operands
++];
3850 i
.op
[i
.operands
].imms
= exp
;
3851 i
.types
[i
.operands
] = imm8
;
3853 exp
->X_op
= O_constant
;
3854 exp
->X_add_number
= i
.tm
.extension_opcode
;
3855 i
.tm
.extension_opcode
= None
;
3862 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3867 as_bad (_("invalid instruction `%s' after `%s'"),
3868 i
.tm
.name
, i
.hle_prefix
);
3871 if (i
.prefix
[LOCK_PREFIX
])
3873 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3877 case HLEPrefixRelease
:
3878 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3880 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3884 if (i
.mem_operands
== 0
3885 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3887 as_bad (_("memory destination needed for instruction `%s'"
3888 " after `xrelease'"), i
.tm
.name
);
3895 /* Try the shortest encoding by shortening operand size. */
3898 optimize_encoding (void)
3902 if (optimize_for_space
3903 && i
.reg_operands
== 1
3904 && i
.imm_operands
== 1
3905 && !i
.types
[1].bitfield
.byte
3906 && i
.op
[0].imms
->X_op
== O_constant
3907 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3908 && ((i
.tm
.base_opcode
== 0xa8
3909 && i
.tm
.extension_opcode
== None
)
3910 || (i
.tm
.base_opcode
== 0xf6
3911 && i
.tm
.extension_opcode
== 0x0)))
3914 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3916 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3917 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3919 i
.types
[1].bitfield
.byte
= 1;
3920 /* Ignore the suffix. */
3922 if (base_regnum
>= 4
3923 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3925 /* Handle SP, BP, SI and DI registers. */
3926 if (i
.types
[1].bitfield
.word
)
3928 else if (i
.types
[1].bitfield
.dword
)
3936 else if (flag_code
== CODE_64BIT
3937 && ((i
.types
[1].bitfield
.qword
3938 && i
.reg_operands
== 1
3939 && i
.imm_operands
== 1
3940 && i
.op
[0].imms
->X_op
== O_constant
3941 && ((i
.tm
.base_opcode
== 0xb0
3942 && i
.tm
.extension_opcode
== None
3943 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3944 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3945 && (((i
.tm
.base_opcode
== 0x24
3946 || i
.tm
.base_opcode
== 0xa8)
3947 && i
.tm
.extension_opcode
== None
)
3948 || (i
.tm
.base_opcode
== 0x80
3949 && i
.tm
.extension_opcode
== 0x4)
3950 || ((i
.tm
.base_opcode
== 0xf6
3951 || i
.tm
.base_opcode
== 0xc6)
3952 && i
.tm
.extension_opcode
== 0x0)))
3953 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3954 && i
.tm
.base_opcode
== 0x83
3955 && i
.tm
.extension_opcode
== 0x4)))
3956 || (i
.types
[0].bitfield
.qword
3957 && ((i
.reg_operands
== 2
3958 && i
.op
[0].regs
== i
.op
[1].regs
3959 && ((i
.tm
.base_opcode
== 0x30
3960 || i
.tm
.base_opcode
== 0x28)
3961 && i
.tm
.extension_opcode
== None
))
3962 || (i
.reg_operands
== 1
3964 && i
.tm
.base_opcode
== 0x30
3965 && i
.tm
.extension_opcode
== None
)))))
3968 andq $imm31, %r64 -> andl $imm31, %r32
3969 andq $imm7, %r64 -> andl $imm7, %r32
3970 testq $imm31, %r64 -> testl $imm31, %r32
3971 xorq %r64, %r64 -> xorl %r32, %r32
3972 subq %r64, %r64 -> subl %r32, %r32
3973 movq $imm31, %r64 -> movl $imm31, %r32
3974 movq $imm32, %r64 -> movl $imm32, %r32
3976 i
.tm
.opcode_modifier
.norex64
= 1;
3977 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3980 movq $imm31, %r64 -> movl $imm31, %r32
3981 movq $imm32, %r64 -> movl $imm32, %r32
3983 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3984 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3985 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3986 i
.types
[0].bitfield
.imm32
= 1;
3987 i
.types
[0].bitfield
.imm32s
= 0;
3988 i
.types
[0].bitfield
.imm64
= 0;
3989 i
.types
[1].bitfield
.dword
= 1;
3990 i
.types
[1].bitfield
.qword
= 0;
3991 if (i
.tm
.base_opcode
== 0xc6)
3994 movq $imm31, %r64 -> movl $imm31, %r32
3996 i
.tm
.base_opcode
= 0xb0;
3997 i
.tm
.extension_opcode
= None
;
3998 i
.tm
.opcode_modifier
.shortform
= 1;
3999 i
.tm
.opcode_modifier
.modrm
= 0;
4003 else if (i
.reg_operands
== 3
4004 && i
.op
[0].regs
== i
.op
[1].regs
4005 && !i
.types
[2].bitfield
.xmmword
4006 && (i
.tm
.opcode_modifier
.vex
4007 || ((!i
.mask
|| i
.mask
->zeroing
)
4009 && is_evex_encoding (&i
.tm
)
4010 && (i
.vec_encoding
!= vex_encoding_evex
4011 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4012 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4013 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4014 && i
.types
[2].bitfield
.ymmword
))))
4015 && ((i
.tm
.base_opcode
== 0x55
4016 || i
.tm
.base_opcode
== 0x6655
4017 || i
.tm
.base_opcode
== 0x66df
4018 || i
.tm
.base_opcode
== 0x57
4019 || i
.tm
.base_opcode
== 0x6657
4020 || i
.tm
.base_opcode
== 0x66ef
4021 || i
.tm
.base_opcode
== 0x66f8
4022 || i
.tm
.base_opcode
== 0x66f9
4023 || i
.tm
.base_opcode
== 0x66fa
4024 || i
.tm
.base_opcode
== 0x66fb
4025 || i
.tm
.base_opcode
== 0x42
4026 || i
.tm
.base_opcode
== 0x6642
4027 || i
.tm
.base_opcode
== 0x47
4028 || i
.tm
.base_opcode
== 0x6647)
4029 && i
.tm
.extension_opcode
== None
))
4032 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4034 EVEX VOP %zmmM, %zmmM, %zmmN
4035 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4036 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4037 EVEX VOP %ymmM, %ymmM, %ymmN
4038 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4039 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4040 VEX VOP %ymmM, %ymmM, %ymmN
4041 -> VEX VOP %xmmM, %xmmM, %xmmN
4042 VOP, one of vpandn and vpxor:
4043 VEX VOP %ymmM, %ymmM, %ymmN
4044 -> VEX VOP %xmmM, %xmmM, %xmmN
4045 VOP, one of vpandnd and vpandnq:
4046 EVEX VOP %zmmM, %zmmM, %zmmN
4047 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4048 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4049 EVEX VOP %ymmM, %ymmM, %ymmN
4050 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4051 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4052 VOP, one of vpxord and vpxorq:
4053 EVEX VOP %zmmM, %zmmM, %zmmN
4054 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4055 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4056 EVEX VOP %ymmM, %ymmM, %ymmN
4057 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4058 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4059 VOP, one of kxord and kxorq:
4060 VEX VOP %kM, %kM, %kN
4061 -> VEX kxorw %kM, %kM, %kN
4062 VOP, one of kandnd and kandnq:
4063 VEX VOP %kM, %kM, %kN
4064 -> VEX kandnw %kM, %kM, %kN
4066 if (is_evex_encoding (&i
.tm
))
4068 if (i
.vec_encoding
!= vex_encoding_evex
)
4070 i
.tm
.opcode_modifier
.vex
= VEX128
;
4071 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4072 i
.tm
.opcode_modifier
.evex
= 0;
4074 else if (optimize
> 1)
4075 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4079 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4081 i
.tm
.base_opcode
&= 0xff;
4082 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4085 i
.tm
.opcode_modifier
.vex
= VEX128
;
4087 if (i
.tm
.opcode_modifier
.vex
)
4088 for (j
= 0; j
< 3; j
++)
4090 i
.types
[j
].bitfield
.xmmword
= 1;
4091 i
.types
[j
].bitfield
.ymmword
= 0;
4094 else if (i
.vec_encoding
!= vex_encoding_evex
4095 && !i
.types
[0].bitfield
.zmmword
4096 && !i
.types
[1].bitfield
.zmmword
4098 && is_evex_encoding (&i
.tm
)
4099 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4100 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4101 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4102 && i
.tm
.extension_opcode
== None
)
4105 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4106 vmovdqu32 and vmovdqu64:
4107 EVEX VOP %xmmM, %xmmN
4108 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4109 EVEX VOP %ymmM, %ymmN
4110 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4112 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4114 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4116 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4118 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4120 for (j
= 0; j
< 2; j
++)
4121 if (operand_type_check (i
.types
[j
], disp
)
4122 && i
.op
[j
].disps
->X_op
== O_constant
)
4124 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4125 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4126 bytes, we choose EVEX Disp8 over VEX Disp32. */
4127 int evex_disp8
, vex_disp8
;
4128 unsigned int memshift
= i
.memshift
;
4129 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4131 evex_disp8
= fits_in_disp8 (n
);
4133 vex_disp8
= fits_in_disp8 (n
);
4134 if (evex_disp8
!= vex_disp8
)
4136 i
.memshift
= memshift
;
4140 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4143 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4144 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4145 i
.tm
.opcode_modifier
.vex
4146 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4147 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4148 i
.tm
.opcode_modifier
.evex
= 0;
4149 i
.tm
.opcode_modifier
.masking
= 0;
4150 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4152 for (j
= 0; j
< 2; j
++)
4153 if (operand_type_check (i
.types
[j
], disp
)
4154 && i
.op
[j
].disps
->X_op
== O_constant
)
4156 i
.types
[j
].bitfield
.disp8
4157 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4163 /* This is the guts of the machine-dependent assembler. LINE points to a
4164 machine dependent instruction. This function is supposed to emit
4165 the frags/bytes it assembles to. */
4168 md_assemble (char *line
)
4171 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4172 const insn_template
*t
;
4174 /* Initialize globals. */
4175 memset (&i
, '\0', sizeof (i
));
4176 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4177 i
.reloc
[j
] = NO_RELOC
;
4178 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4179 memset (im_expressions
, '\0', sizeof (im_expressions
));
4180 save_stack_p
= save_stack
;
4182 /* First parse an instruction mnemonic & call i386_operand for the operands.
4183 We assume that the scrubber has arranged it so that line[0] is the valid
4184 start of a (possibly prefixed) mnemonic. */
4186 line
= parse_insn (line
, mnemonic
);
4189 mnem_suffix
= i
.suffix
;
4191 line
= parse_operands (line
, mnemonic
);
4193 xfree (i
.memop1_string
);
4194 i
.memop1_string
= NULL
;
4198 /* Now we've parsed the mnemonic into a set of templates, and have the
4199 operands at hand. */
4201 /* All intel opcodes have reversed operands except for "bound" and
4202 "enter". We also don't reverse intersegment "jmp" and "call"
4203 instructions with 2 immediate operands so that the immediate segment
4204 precedes the offset, as it does when in AT&T mode. */
4207 && (strcmp (mnemonic
, "bound") != 0)
4208 && (strcmp (mnemonic
, "invlpga") != 0)
4209 && !(operand_type_check (i
.types
[0], imm
)
4210 && operand_type_check (i
.types
[1], imm
)))
4213 /* The order of the immediates should be reversed
4214 for 2 immediates extrq and insertq instructions */
4215 if (i
.imm_operands
== 2
4216 && (strcmp (mnemonic
, "extrq") == 0
4217 || strcmp (mnemonic
, "insertq") == 0))
4218 swap_2_operands (0, 1);
4223 /* Don't optimize displacement for movabs since it only takes 64bit
4226 && i
.disp_encoding
!= disp_encoding_32bit
4227 && (flag_code
!= CODE_64BIT
4228 || strcmp (mnemonic
, "movabs") != 0))
4231 /* Next, we find a template that matches the given insn,
4232 making sure the overlap of the given operands types is consistent
4233 with the template operand types. */
4235 if (!(t
= match_template (mnem_suffix
)))
4238 if (sse_check
!= check_none
4239 && !i
.tm
.opcode_modifier
.noavx
4240 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4241 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4242 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4243 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4244 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4245 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4246 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4247 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4248 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4249 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4251 (sse_check
== check_warning
4253 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4256 /* Zap movzx and movsx suffix. The suffix has been set from
4257 "word ptr" or "byte ptr" on the source operand in Intel syntax
4258 or extracted from mnemonic in AT&T syntax. But we'll use
4259 the destination register to choose the suffix for encoding. */
4260 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4262 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4263 there is no suffix, the default will be byte extension. */
4264 if (i
.reg_operands
!= 2
4267 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4272 if (i
.tm
.opcode_modifier
.fwait
)
4273 if (!add_prefix (FWAIT_OPCODE
))
4276 /* Check if REP prefix is OK. */
4277 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4279 as_bad (_("invalid instruction `%s' after `%s'"),
4280 i
.tm
.name
, i
.rep_prefix
);
4284 /* Check for lock without a lockable instruction. Destination operand
4285 must be memory unless it is xchg (0x86). */
4286 if (i
.prefix
[LOCK_PREFIX
]
4287 && (!i
.tm
.opcode_modifier
.islockable
4288 || i
.mem_operands
== 0
4289 || (i
.tm
.base_opcode
!= 0x86
4290 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4292 as_bad (_("expecting lockable instruction after `lock'"));
4296 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4297 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4299 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4303 /* Check if HLE prefix is OK. */
4304 if (i
.hle_prefix
&& !check_hle ())
4307 /* Check BND prefix. */
4308 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4309 as_bad (_("expecting valid branch instruction after `bnd'"));
4311 /* Check NOTRACK prefix. */
4312 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4313 as_bad (_("expecting indirect branch instruction after `notrack'"));
4315 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4317 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4318 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4319 else if (flag_code
!= CODE_16BIT
4320 ? i
.prefix
[ADDR_PREFIX
]
4321 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4322 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4325 /* Insert BND prefix. */
4326 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4328 if (!i
.prefix
[BND_PREFIX
])
4329 add_prefix (BND_PREFIX_OPCODE
);
4330 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4332 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4333 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4337 /* Check string instruction segment overrides. */
4338 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4340 if (!check_string ())
4342 i
.disp_operands
= 0;
4345 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4346 optimize_encoding ();
4348 if (!process_suffix ())
4351 /* Update operand types. */
4352 for (j
= 0; j
< i
.operands
; j
++)
4353 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4355 /* Make still unresolved immediate matches conform to size of immediate
4356 given in i.suffix. */
4357 if (!finalize_imm ())
4360 if (i
.types
[0].bitfield
.imm1
)
4361 i
.imm_operands
= 0; /* kludge for shift insns. */
4363 /* We only need to check those implicit registers for instructions
4364 with 3 operands or less. */
4365 if (i
.operands
<= 3)
4366 for (j
= 0; j
< i
.operands
; j
++)
4367 if (i
.types
[j
].bitfield
.inoutportreg
4368 || i
.types
[j
].bitfield
.shiftcount
4369 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4372 /* ImmExt should be processed after SSE2AVX. */
4373 if (!i
.tm
.opcode_modifier
.sse2avx
4374 && i
.tm
.opcode_modifier
.immext
)
4377 /* For insns with operands there are more diddles to do to the opcode. */
4380 if (!process_operands ())
4383 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4385 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4386 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4389 if (is_any_vex_encoding (&i
.tm
))
4391 if (!cpu_arch_flags
.bitfield
.cpui286
)
4393 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4398 if (i
.tm
.opcode_modifier
.vex
)
4399 build_vex_prefix (t
);
4401 build_evex_prefix ();
4404 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4405 instructions may define INT_OPCODE as well, so avoid this corner
4406 case for those instructions that use MODRM. */
4407 if (i
.tm
.base_opcode
== INT_OPCODE
4408 && !i
.tm
.opcode_modifier
.modrm
4409 && i
.op
[0].imms
->X_add_number
== 3)
4411 i
.tm
.base_opcode
= INT3_OPCODE
;
4415 if ((i
.tm
.opcode_modifier
.jump
4416 || i
.tm
.opcode_modifier
.jumpbyte
4417 || i
.tm
.opcode_modifier
.jumpdword
)
4418 && i
.op
[0].disps
->X_op
== O_constant
)
4420 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4421 the absolute address given by the constant. Since ix86 jumps and
4422 calls are pc relative, we need to generate a reloc. */
4423 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4424 i
.op
[0].disps
->X_op
= O_symbol
;
4427 if (i
.tm
.opcode_modifier
.rex64
)
4430 /* For 8 bit registers we need an empty rex prefix. Also if the
4431 instruction already has a prefix, we need to convert old
4432 registers to new ones. */
4434 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4435 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4436 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4437 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4438 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4439 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4444 i
.rex
|= REX_OPCODE
;
4445 for (x
= 0; x
< 2; x
++)
4447 /* Look for 8 bit operand that uses old registers. */
4448 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4449 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4451 /* In case it is "hi" register, give up. */
4452 if (i
.op
[x
].regs
->reg_num
> 3)
4453 as_bad (_("can't encode register '%s%s' in an "
4454 "instruction requiring REX prefix."),
4455 register_prefix
, i
.op
[x
].regs
->reg_name
);
4457 /* Otherwise it is equivalent to the extended register.
4458 Since the encoding doesn't change this is merely
4459 cosmetic cleanup for debug output. */
4461 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4466 if (i
.rex
== 0 && i
.rex_encoding
)
4468 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4469 that uses legacy register. If it is "hi" register, don't add
4470 the REX_OPCODE byte. */
4472 for (x
= 0; x
< 2; x
++)
4473 if (i
.types
[x
].bitfield
.reg
4474 && i
.types
[x
].bitfield
.byte
4475 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4476 && i
.op
[x
].regs
->reg_num
> 3)
4478 i
.rex_encoding
= FALSE
;
4487 add_prefix (REX_OPCODE
| i
.rex
);
4489 /* We are ready to output the insn. */
4494 parse_insn (char *line
, char *mnemonic
)
4497 char *token_start
= l
;
4500 const insn_template
*t
;
4506 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4511 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4513 as_bad (_("no such instruction: `%s'"), token_start
);
4518 if (!is_space_char (*l
)
4519 && *l
!= END_OF_INSN
4521 || (*l
!= PREFIX_SEPARATOR
4524 as_bad (_("invalid character %s in mnemonic"),
4525 output_invalid (*l
));
4528 if (token_start
== l
)
4530 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4531 as_bad (_("expecting prefix; got nothing"));
4533 as_bad (_("expecting mnemonic; got nothing"));
4537 /* Look up instruction (or prefix) via hash table. */
4538 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4540 if (*l
!= END_OF_INSN
4541 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4542 && current_templates
4543 && current_templates
->start
->opcode_modifier
.isprefix
)
4545 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4547 as_bad ((flag_code
!= CODE_64BIT
4548 ? _("`%s' is only supported in 64-bit mode")
4549 : _("`%s' is not supported in 64-bit mode")),
4550 current_templates
->start
->name
);
4553 /* If we are in 16-bit mode, do not allow addr16 or data16.
4554 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4555 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4556 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4557 && flag_code
!= CODE_64BIT
4558 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4559 ^ (flag_code
== CODE_16BIT
)))
4561 as_bad (_("redundant %s prefix"),
4562 current_templates
->start
->name
);
4565 if (current_templates
->start
->opcode_length
== 0)
4567 /* Handle pseudo prefixes. */
4568 switch (current_templates
->start
->base_opcode
)
4572 i
.disp_encoding
= disp_encoding_8bit
;
4576 i
.disp_encoding
= disp_encoding_32bit
;
4580 i
.dir_encoding
= dir_encoding_load
;
4584 i
.dir_encoding
= dir_encoding_store
;
4588 i
.vec_encoding
= vex_encoding_vex2
;
4592 i
.vec_encoding
= vex_encoding_vex3
;
4596 i
.vec_encoding
= vex_encoding_evex
;
4600 i
.rex_encoding
= TRUE
;
4604 i
.no_optimize
= TRUE
;
4612 /* Add prefix, checking for repeated prefixes. */
4613 switch (add_prefix (current_templates
->start
->base_opcode
))
4618 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4619 i
.notrack_prefix
= current_templates
->start
->name
;
4622 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4623 i
.hle_prefix
= current_templates
->start
->name
;
4624 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4625 i
.bnd_prefix
= current_templates
->start
->name
;
4627 i
.rep_prefix
= current_templates
->start
->name
;
4633 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4640 if (!current_templates
)
4642 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4643 Check if we should swap operand or force 32bit displacement in
4645 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4646 i
.dir_encoding
= dir_encoding_swap
;
4647 else if (mnem_p
- 3 == dot_p
4650 i
.disp_encoding
= disp_encoding_8bit
;
4651 else if (mnem_p
- 4 == dot_p
4655 i
.disp_encoding
= disp_encoding_32bit
;
4660 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4663 if (!current_templates
)
4666 if (mnem_p
> mnemonic
)
4668 /* See if we can get a match by trimming off a suffix. */
4671 case WORD_MNEM_SUFFIX
:
4672 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4673 i
.suffix
= SHORT_MNEM_SUFFIX
;
4676 case BYTE_MNEM_SUFFIX
:
4677 case QWORD_MNEM_SUFFIX
:
4678 i
.suffix
= mnem_p
[-1];
4680 current_templates
= (const templates
*) hash_find (op_hash
,
4683 case SHORT_MNEM_SUFFIX
:
4684 case LONG_MNEM_SUFFIX
:
4687 i
.suffix
= mnem_p
[-1];
4689 current_templates
= (const templates
*) hash_find (op_hash
,
4698 if (intel_float_operand (mnemonic
) == 1)
4699 i
.suffix
= SHORT_MNEM_SUFFIX
;
4701 i
.suffix
= LONG_MNEM_SUFFIX
;
4703 current_templates
= (const templates
*) hash_find (op_hash
,
4710 if (!current_templates
)
4712 as_bad (_("no such instruction: `%s'"), token_start
);
4717 if (current_templates
->start
->opcode_modifier
.jump
4718 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4720 /* Check for a branch hint. We allow ",pt" and ",pn" for
4721 predict taken and predict not taken respectively.
4722 I'm not sure that branch hints actually do anything on loop
4723 and jcxz insns (JumpByte) for current Pentium4 chips. They
4724 may work in the future and it doesn't hurt to accept them
4726 if (l
[0] == ',' && l
[1] == 'p')
4730 if (!add_prefix (DS_PREFIX_OPCODE
))
4734 else if (l
[2] == 'n')
4736 if (!add_prefix (CS_PREFIX_OPCODE
))
4742 /* Any other comma loses. */
4745 as_bad (_("invalid character %s in mnemonic"),
4746 output_invalid (*l
));
4750 /* Check if instruction is supported on specified architecture. */
4752 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4754 supported
|= cpu_flags_match (t
);
4755 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4757 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4758 as_warn (_("use .code16 to ensure correct addressing mode"));
4764 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4765 as_bad (flag_code
== CODE_64BIT
4766 ? _("`%s' is not supported in 64-bit mode")
4767 : _("`%s' is only supported in 64-bit mode"),
4768 current_templates
->start
->name
);
4770 as_bad (_("`%s' is not supported on `%s%s'"),
4771 current_templates
->start
->name
,
4772 cpu_arch_name
? cpu_arch_name
: default_arch
,
4773 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4779 parse_operands (char *l
, const char *mnemonic
)
4783 /* 1 if operand is pending after ','. */
4784 unsigned int expecting_operand
= 0;
4786 /* Non-zero if operand parens not balanced. */
4787 unsigned int paren_not_balanced
;
4789 while (*l
!= END_OF_INSN
)
4791 /* Skip optional white space before operand. */
4792 if (is_space_char (*l
))
4794 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4796 as_bad (_("invalid character %s before operand %d"),
4797 output_invalid (*l
),
4801 token_start
= l
; /* After white space. */
4802 paren_not_balanced
= 0;
4803 while (paren_not_balanced
|| *l
!= ',')
4805 if (*l
== END_OF_INSN
)
4807 if (paren_not_balanced
)
4810 as_bad (_("unbalanced parenthesis in operand %d."),
4813 as_bad (_("unbalanced brackets in operand %d."),
4818 break; /* we are done */
4820 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4822 as_bad (_("invalid character %s in operand %d"),
4823 output_invalid (*l
),
4830 ++paren_not_balanced
;
4832 --paren_not_balanced
;
4837 ++paren_not_balanced
;
4839 --paren_not_balanced
;
4843 if (l
!= token_start
)
4844 { /* Yes, we've read in another operand. */
4845 unsigned int operand_ok
;
4846 this_operand
= i
.operands
++;
4847 if (i
.operands
> MAX_OPERANDS
)
4849 as_bad (_("spurious operands; (%d operands/instruction max)"),
4853 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4854 /* Now parse operand adding info to 'i' as we go along. */
4855 END_STRING_AND_SAVE (l
);
4857 if (i
.mem_operands
> 1)
4859 as_bad (_("too many memory references for `%s'"),
4866 i386_intel_operand (token_start
,
4867 intel_float_operand (mnemonic
));
4869 operand_ok
= i386_att_operand (token_start
);
4871 RESTORE_END_STRING (l
);
4877 if (expecting_operand
)
4879 expecting_operand_after_comma
:
4880 as_bad (_("expecting operand after ','; got nothing"));
4885 as_bad (_("expecting operand before ','; got nothing"));
4890 /* Now *l must be either ',' or END_OF_INSN. */
4893 if (*++l
== END_OF_INSN
)
4895 /* Just skip it, if it's \n complain. */
4896 goto expecting_operand_after_comma
;
4898 expecting_operand
= 1;
4905 swap_2_operands (int xchg1
, int xchg2
)
4907 union i386_op temp_op
;
4908 i386_operand_type temp_type
;
4909 unsigned int temp_flags
;
4910 enum bfd_reloc_code_real temp_reloc
;
4912 temp_type
= i
.types
[xchg2
];
4913 i
.types
[xchg2
] = i
.types
[xchg1
];
4914 i
.types
[xchg1
] = temp_type
;
4916 temp_flags
= i
.flags
[xchg2
];
4917 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4918 i
.flags
[xchg1
] = temp_flags
;
4920 temp_op
= i
.op
[xchg2
];
4921 i
.op
[xchg2
] = i
.op
[xchg1
];
4922 i
.op
[xchg1
] = temp_op
;
4924 temp_reloc
= i
.reloc
[xchg2
];
4925 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4926 i
.reloc
[xchg1
] = temp_reloc
;
4930 if (i
.mask
->operand
== xchg1
)
4931 i
.mask
->operand
= xchg2
;
4932 else if (i
.mask
->operand
== xchg2
)
4933 i
.mask
->operand
= xchg1
;
4937 if (i
.broadcast
->operand
== xchg1
)
4938 i
.broadcast
->operand
= xchg2
;
4939 else if (i
.broadcast
->operand
== xchg2
)
4940 i
.broadcast
->operand
= xchg1
;
4944 if (i
.rounding
->operand
== xchg1
)
4945 i
.rounding
->operand
= xchg2
;
4946 else if (i
.rounding
->operand
== xchg2
)
4947 i
.rounding
->operand
= xchg1
;
4952 swap_operands (void)
4958 swap_2_operands (1, i
.operands
- 2);
4962 swap_2_operands (0, i
.operands
- 1);
4968 if (i
.mem_operands
== 2)
4970 const seg_entry
*temp_seg
;
4971 temp_seg
= i
.seg
[0];
4972 i
.seg
[0] = i
.seg
[1];
4973 i
.seg
[1] = temp_seg
;
4977 /* Try to ensure constant immediates are represented in the smallest
4982 char guess_suffix
= 0;
4986 guess_suffix
= i
.suffix
;
4987 else if (i
.reg_operands
)
4989 /* Figure out a suffix from the last register operand specified.
4990 We can't do this properly yet, ie. excluding InOutPortReg,
4991 but the following works for instructions with immediates.
4992 In any case, we can't set i.suffix yet. */
4993 for (op
= i
.operands
; --op
>= 0;)
4994 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4996 guess_suffix
= BYTE_MNEM_SUFFIX
;
4999 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5001 guess_suffix
= WORD_MNEM_SUFFIX
;
5004 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5006 guess_suffix
= LONG_MNEM_SUFFIX
;
5009 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5011 guess_suffix
= QWORD_MNEM_SUFFIX
;
5015 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5016 guess_suffix
= WORD_MNEM_SUFFIX
;
5018 for (op
= i
.operands
; --op
>= 0;)
5019 if (operand_type_check (i
.types
[op
], imm
))
5021 switch (i
.op
[op
].imms
->X_op
)
5024 /* If a suffix is given, this operand may be shortened. */
5025 switch (guess_suffix
)
5027 case LONG_MNEM_SUFFIX
:
5028 i
.types
[op
].bitfield
.imm32
= 1;
5029 i
.types
[op
].bitfield
.imm64
= 1;
5031 case WORD_MNEM_SUFFIX
:
5032 i
.types
[op
].bitfield
.imm16
= 1;
5033 i
.types
[op
].bitfield
.imm32
= 1;
5034 i
.types
[op
].bitfield
.imm32s
= 1;
5035 i
.types
[op
].bitfield
.imm64
= 1;
5037 case BYTE_MNEM_SUFFIX
:
5038 i
.types
[op
].bitfield
.imm8
= 1;
5039 i
.types
[op
].bitfield
.imm8s
= 1;
5040 i
.types
[op
].bitfield
.imm16
= 1;
5041 i
.types
[op
].bitfield
.imm32
= 1;
5042 i
.types
[op
].bitfield
.imm32s
= 1;
5043 i
.types
[op
].bitfield
.imm64
= 1;
5047 /* If this operand is at most 16 bits, convert it
5048 to a signed 16 bit number before trying to see
5049 whether it will fit in an even smaller size.
5050 This allows a 16-bit operand such as $0xffe0 to
5051 be recognised as within Imm8S range. */
5052 if ((i
.types
[op
].bitfield
.imm16
)
5053 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5055 i
.op
[op
].imms
->X_add_number
=
5056 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5059 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5060 if ((i
.types
[op
].bitfield
.imm32
)
5061 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5064 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5065 ^ ((offsetT
) 1 << 31))
5066 - ((offsetT
) 1 << 31));
5070 = operand_type_or (i
.types
[op
],
5071 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5073 /* We must avoid matching of Imm32 templates when 64bit
5074 only immediate is available. */
5075 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5076 i
.types
[op
].bitfield
.imm32
= 0;
5083 /* Symbols and expressions. */
5085 /* Convert symbolic operand to proper sizes for matching, but don't
5086 prevent matching a set of insns that only supports sizes other
5087 than those matching the insn suffix. */
5089 i386_operand_type mask
, allowed
;
5090 const insn_template
*t
;
5092 operand_type_set (&mask
, 0);
5093 operand_type_set (&allowed
, 0);
5095 for (t
= current_templates
->start
;
5096 t
< current_templates
->end
;
5098 allowed
= operand_type_or (allowed
,
5099 t
->operand_types
[op
]);
5100 switch (guess_suffix
)
5102 case QWORD_MNEM_SUFFIX
:
5103 mask
.bitfield
.imm64
= 1;
5104 mask
.bitfield
.imm32s
= 1;
5106 case LONG_MNEM_SUFFIX
:
5107 mask
.bitfield
.imm32
= 1;
5109 case WORD_MNEM_SUFFIX
:
5110 mask
.bitfield
.imm16
= 1;
5112 case BYTE_MNEM_SUFFIX
:
5113 mask
.bitfield
.imm8
= 1;
5118 allowed
= operand_type_and (mask
, allowed
);
5119 if (!operand_type_all_zero (&allowed
))
5120 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5127 /* Try to use the smallest displacement type too. */
5129 optimize_disp (void)
5133 for (op
= i
.operands
; --op
>= 0;)
5134 if (operand_type_check (i
.types
[op
], disp
))
5136 if (i
.op
[op
].disps
->X_op
== O_constant
)
5138 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5140 if (i
.types
[op
].bitfield
.disp16
5141 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5143 /* If this operand is at most 16 bits, convert
5144 to a signed 16 bit number and don't use 64bit
5146 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5147 i
.types
[op
].bitfield
.disp64
= 0;
5150 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5151 if (i
.types
[op
].bitfield
.disp32
5152 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5154 /* If this operand is at most 32 bits, convert
5155 to a signed 32 bit number and don't use 64bit
5157 op_disp
&= (((offsetT
) 2 << 31) - 1);
5158 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5159 i
.types
[op
].bitfield
.disp64
= 0;
5162 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5164 i
.types
[op
].bitfield
.disp8
= 0;
5165 i
.types
[op
].bitfield
.disp16
= 0;
5166 i
.types
[op
].bitfield
.disp32
= 0;
5167 i
.types
[op
].bitfield
.disp32s
= 0;
5168 i
.types
[op
].bitfield
.disp64
= 0;
5172 else if (flag_code
== CODE_64BIT
)
5174 if (fits_in_signed_long (op_disp
))
5176 i
.types
[op
].bitfield
.disp64
= 0;
5177 i
.types
[op
].bitfield
.disp32s
= 1;
5179 if (i
.prefix
[ADDR_PREFIX
]
5180 && fits_in_unsigned_long (op_disp
))
5181 i
.types
[op
].bitfield
.disp32
= 1;
5183 if ((i
.types
[op
].bitfield
.disp32
5184 || i
.types
[op
].bitfield
.disp32s
5185 || i
.types
[op
].bitfield
.disp16
)
5186 && fits_in_disp8 (op_disp
))
5187 i
.types
[op
].bitfield
.disp8
= 1;
5189 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5190 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5192 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5193 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5194 i
.types
[op
].bitfield
.disp8
= 0;
5195 i
.types
[op
].bitfield
.disp16
= 0;
5196 i
.types
[op
].bitfield
.disp32
= 0;
5197 i
.types
[op
].bitfield
.disp32s
= 0;
5198 i
.types
[op
].bitfield
.disp64
= 0;
5201 /* We only support 64bit displacement on constants. */
5202 i
.types
[op
].bitfield
.disp64
= 0;
5206 /* Return 1 if there is a match in broadcast bytes between operand
5207 GIVEN and instruction template T. */
5210 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5212 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5213 && i
.types
[given
].bitfield
.byte
)
5214 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5215 && i
.types
[given
].bitfield
.word
)
5216 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5217 && i
.types
[given
].bitfield
.dword
)
5218 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5219 && i
.types
[given
].bitfield
.qword
));
5222 /* Check if operands are valid for the instruction. */
5225 check_VecOperands (const insn_template
*t
)
5229 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5231 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5232 any one operand are implicity requiring AVX512VL support if the actual
5233 operand size is YMMword or XMMword. Since this function runs after
5234 template matching, there's no need to check for YMMword/XMMword in
5236 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5237 if (!cpu_flags_all_zero (&cpu
)
5238 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5239 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5241 for (op
= 0; op
< t
->operands
; ++op
)
5243 if (t
->operand_types
[op
].bitfield
.zmmword
5244 && (i
.types
[op
].bitfield
.ymmword
5245 || i
.types
[op
].bitfield
.xmmword
))
5247 i
.error
= unsupported
;
5253 /* Without VSIB byte, we can't have a vector register for index. */
5254 if (!t
->opcode_modifier
.vecsib
5256 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5257 || i
.index_reg
->reg_type
.bitfield
.ymmword
5258 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5260 i
.error
= unsupported_vector_index_register
;
5264 /* Check if default mask is allowed. */
5265 if (t
->opcode_modifier
.nodefmask
5266 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5268 i
.error
= no_default_mask
;
5272 /* For VSIB byte, we need a vector register for index, and all vector
5273 registers must be distinct. */
5274 if (t
->opcode_modifier
.vecsib
)
5277 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5278 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5279 || (t
->opcode_modifier
.vecsib
== VecSIB256
5280 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5281 || (t
->opcode_modifier
.vecsib
== VecSIB512
5282 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5284 i
.error
= invalid_vsib_address
;
5288 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5289 if (i
.reg_operands
== 2 && !i
.mask
)
5291 gas_assert (i
.types
[0].bitfield
.regsimd
);
5292 gas_assert (i
.types
[0].bitfield
.xmmword
5293 || i
.types
[0].bitfield
.ymmword
);
5294 gas_assert (i
.types
[2].bitfield
.regsimd
);
5295 gas_assert (i
.types
[2].bitfield
.xmmword
5296 || i
.types
[2].bitfield
.ymmword
);
5297 if (operand_check
== check_none
)
5299 if (register_number (i
.op
[0].regs
)
5300 != register_number (i
.index_reg
)
5301 && register_number (i
.op
[2].regs
)
5302 != register_number (i
.index_reg
)
5303 && register_number (i
.op
[0].regs
)
5304 != register_number (i
.op
[2].regs
))
5306 if (operand_check
== check_error
)
5308 i
.error
= invalid_vector_register_set
;
5311 as_warn (_("mask, index, and destination registers should be distinct"));
5313 else if (i
.reg_operands
== 1 && i
.mask
)
5315 if (i
.types
[1].bitfield
.regsimd
5316 && (i
.types
[1].bitfield
.xmmword
5317 || i
.types
[1].bitfield
.ymmword
5318 || i
.types
[1].bitfield
.zmmword
)
5319 && (register_number (i
.op
[1].regs
)
5320 == register_number (i
.index_reg
)))
5322 if (operand_check
== check_error
)
5324 i
.error
= invalid_vector_register_set
;
5327 if (operand_check
!= check_none
)
5328 as_warn (_("index and destination registers should be distinct"));
5333 /* Check if broadcast is supported by the instruction and is applied
5334 to the memory operand. */
5337 i386_operand_type type
, overlap
;
5339 /* Check if specified broadcast is supported in this instruction,
5340 and its broadcast bytes match the memory operand. */
5341 op
= i
.broadcast
->operand
;
5342 if (!t
->opcode_modifier
.broadcast
5343 || !(i
.flags
[op
] & Operand_Mem
)
5344 || (!i
.types
[op
].bitfield
.unspecified
5345 && !match_broadcast_size (t
, op
)))
5348 i
.error
= unsupported_broadcast
;
5352 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5353 * i
.broadcast
->type
);
5354 operand_type_set (&type
, 0);
5355 switch (i
.broadcast
->bytes
)
5358 type
.bitfield
.word
= 1;
5361 type
.bitfield
.dword
= 1;
5364 type
.bitfield
.qword
= 1;
5367 type
.bitfield
.xmmword
= 1;
5370 type
.bitfield
.ymmword
= 1;
5373 type
.bitfield
.zmmword
= 1;
5379 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5380 if (operand_type_all_zero (&overlap
))
5383 if (t
->opcode_modifier
.checkregsize
)
5387 type
.bitfield
.baseindex
= 1;
5388 for (j
= 0; j
< i
.operands
; ++j
)
5391 && !operand_type_register_match(i
.types
[j
],
5392 t
->operand_types
[j
],
5394 t
->operand_types
[op
]))
5399 /* If broadcast is supported in this instruction, we need to check if
5400 operand of one-element size isn't specified without broadcast. */
5401 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5403 /* Find memory operand. */
5404 for (op
= 0; op
< i
.operands
; op
++)
5405 if (operand_type_check (i
.types
[op
], anymem
))
5407 gas_assert (op
< i
.operands
);
5408 /* Check size of the memory operand. */
5409 if (match_broadcast_size (t
, op
))
5411 i
.error
= broadcast_needed
;
5416 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5418 /* Check if requested masking is supported. */
5421 switch (t
->opcode_modifier
.masking
)
5425 case MERGING_MASKING
:
5426 if (i
.mask
->zeroing
)
5429 i
.error
= unsupported_masking
;
5433 case DYNAMIC_MASKING
:
5434 /* Memory destinations allow only merging masking. */
5435 if (i
.mask
->zeroing
&& i
.mem_operands
)
5437 /* Find memory operand. */
5438 for (op
= 0; op
< i
.operands
; op
++)
5439 if (i
.flags
[op
] & Operand_Mem
)
5441 gas_assert (op
< i
.operands
);
5442 if (op
== i
.operands
- 1)
5444 i
.error
= unsupported_masking
;
5454 /* Check if masking is applied to dest operand. */
5455 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5457 i
.error
= mask_not_on_destination
;
5464 if ((i
.rounding
->type
!= saeonly
5465 && !t
->opcode_modifier
.staticrounding
)
5466 || (i
.rounding
->type
== saeonly
5467 && (t
->opcode_modifier
.staticrounding
5468 || !t
->opcode_modifier
.sae
)))
5470 i
.error
= unsupported_rc_sae
;
5473 /* If the instruction has several immediate operands and one of
5474 them is rounding, the rounding operand should be the last
5475 immediate operand. */
5476 if (i
.imm_operands
> 1
5477 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5479 i
.error
= rc_sae_operand_not_last_imm
;
5484 /* Check vector Disp8 operand. */
5485 if (t
->opcode_modifier
.disp8memshift
5486 && i
.disp_encoding
!= disp_encoding_32bit
)
5489 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5490 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5491 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5494 const i386_operand_type
*type
= NULL
;
5497 for (op
= 0; op
< i
.operands
; op
++)
5498 if (operand_type_check (i
.types
[op
], anymem
))
5500 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5501 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5502 else if (t
->operand_types
[op
].bitfield
.xmmword
5503 + t
->operand_types
[op
].bitfield
.ymmword
5504 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5505 type
= &t
->operand_types
[op
];
5506 else if (!i
.types
[op
].bitfield
.unspecified
)
5507 type
= &i
.types
[op
];
5509 else if (i
.types
[op
].bitfield
.regsimd
5510 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5512 if (i
.types
[op
].bitfield
.zmmword
)
5514 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5516 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5522 if (type
->bitfield
.zmmword
)
5524 else if (type
->bitfield
.ymmword
)
5526 else if (type
->bitfield
.xmmword
)
5530 /* For the check in fits_in_disp8(). */
5531 if (i
.memshift
== 0)
5535 for (op
= 0; op
< i
.operands
; op
++)
5536 if (operand_type_check (i
.types
[op
], disp
)
5537 && i
.op
[op
].disps
->X_op
== O_constant
)
5539 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5541 i
.types
[op
].bitfield
.disp8
= 1;
5544 i
.types
[op
].bitfield
.disp8
= 0;
5553 /* Check if operands are valid for the instruction. Update VEX
5557 VEX_check_operands (const insn_template
*t
)
5559 if (i
.vec_encoding
== vex_encoding_evex
)
5561 /* This instruction must be encoded with EVEX prefix. */
5562 if (!is_evex_encoding (t
))
5564 i
.error
= unsupported
;
5570 if (!t
->opcode_modifier
.vex
)
5572 /* This instruction template doesn't have VEX prefix. */
5573 if (i
.vec_encoding
!= vex_encoding_default
)
5575 i
.error
= unsupported
;
5581 /* Only check VEX_Imm4, which must be the first operand. */
5582 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5584 if (i
.op
[0].imms
->X_op
!= O_constant
5585 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5591 /* Turn off Imm8 so that update_imm won't complain. */
5592 i
.types
[0] = vec_imm4
;
5598 static const insn_template
*
5599 match_template (char mnem_suffix
)
5601 /* Points to template once we've found it. */
5602 const insn_template
*t
;
5603 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5604 i386_operand_type overlap4
;
5605 unsigned int found_reverse_match
;
5606 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5607 i386_operand_type operand_types
[MAX_OPERANDS
];
5608 int addr_prefix_disp
;
5610 unsigned int found_cpu_match
, size_match
;
5611 unsigned int check_register
;
5612 enum i386_error specific_error
= 0;
5614 #if MAX_OPERANDS != 5
5615 # error "MAX_OPERANDS must be 5."
5618 found_reverse_match
= 0;
5619 addr_prefix_disp
= -1;
5621 memset (&suffix_check
, 0, sizeof (suffix_check
));
5622 if (intel_syntax
&& i
.broadcast
)
5624 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5625 suffix_check
.no_bsuf
= 1;
5626 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5627 suffix_check
.no_wsuf
= 1;
5628 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5629 suffix_check
.no_ssuf
= 1;
5630 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5631 suffix_check
.no_lsuf
= 1;
5632 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5633 suffix_check
.no_qsuf
= 1;
5634 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5635 suffix_check
.no_ldsuf
= 1;
5637 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5640 switch (mnem_suffix
)
5642 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5643 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5644 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5645 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5646 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5650 /* Must have right number of operands. */
5651 i
.error
= number_of_operands_mismatch
;
5653 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5655 addr_prefix_disp
= -1;
5656 found_reverse_match
= 0;
5658 if (i
.operands
!= t
->operands
)
5661 /* Check processor support. */
5662 i
.error
= unsupported
;
5663 found_cpu_match
= (cpu_flags_match (t
)
5664 == CPU_FLAGS_PERFECT_MATCH
);
5665 if (!found_cpu_match
)
5668 /* Check AT&T mnemonic. */
5669 i
.error
= unsupported_with_intel_mnemonic
;
5670 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5673 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5674 i
.error
= unsupported_syntax
;
5675 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5676 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5677 || (intel64
&& t
->opcode_modifier
.amd64
)
5678 || (!intel64
&& t
->opcode_modifier
.intel64
))
5681 /* Check the suffix, except for some instructions in intel mode. */
5682 i
.error
= invalid_instruction_suffix
;
5683 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5684 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5685 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5686 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5687 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5688 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5689 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5691 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5692 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5693 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5694 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5695 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5696 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5697 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5700 size_match
= operand_size_match (t
);
5704 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5705 operand_types
[j
] = t
->operand_types
[j
];
5707 /* In general, don't allow 64-bit operands in 32-bit mode. */
5708 if (i
.suffix
== QWORD_MNEM_SUFFIX
5709 && flag_code
!= CODE_64BIT
5711 ? (!t
->opcode_modifier
.ignoresize
5712 && !t
->opcode_modifier
.broadcast
5713 && !intel_float_operand (t
->name
))
5714 : intel_float_operand (t
->name
) != 2)
5715 && ((!operand_types
[0].bitfield
.regmmx
5716 && !operand_types
[0].bitfield
.regsimd
)
5717 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5718 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5719 && (t
->base_opcode
!= 0x0fc7
5720 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5723 /* In general, don't allow 32-bit operands on pre-386. */
5724 else if (i
.suffix
== LONG_MNEM_SUFFIX
5725 && !cpu_arch_flags
.bitfield
.cpui386
5727 ? (!t
->opcode_modifier
.ignoresize
5728 && !intel_float_operand (t
->name
))
5729 : intel_float_operand (t
->name
) != 2)
5730 && ((!operand_types
[0].bitfield
.regmmx
5731 && !operand_types
[0].bitfield
.regsimd
)
5732 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5733 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5736 /* Do not verify operands when there are none. */
5740 /* We've found a match; break out of loop. */
5744 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5745 into Disp32/Disp16/Disp32 operand. */
5746 if (i
.prefix
[ADDR_PREFIX
] != 0)
5748 /* There should be only one Disp operand. */
5752 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5754 if (operand_types
[j
].bitfield
.disp16
)
5756 addr_prefix_disp
= j
;
5757 operand_types
[j
].bitfield
.disp32
= 1;
5758 operand_types
[j
].bitfield
.disp16
= 0;
5764 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5766 if (operand_types
[j
].bitfield
.disp32
)
5768 addr_prefix_disp
= j
;
5769 operand_types
[j
].bitfield
.disp32
= 0;
5770 operand_types
[j
].bitfield
.disp16
= 1;
5776 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5778 if (operand_types
[j
].bitfield
.disp64
)
5780 addr_prefix_disp
= j
;
5781 operand_types
[j
].bitfield
.disp64
= 0;
5782 operand_types
[j
].bitfield
.disp32
= 1;
5790 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5791 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5794 /* We check register size if needed. */
5795 if (t
->opcode_modifier
.checkregsize
)
5797 check_register
= (1 << t
->operands
) - 1;
5799 check_register
&= ~(1 << i
.broadcast
->operand
);
5804 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5805 switch (t
->operands
)
5808 if (!operand_type_match (overlap0
, i
.types
[0]))
5812 /* xchg %eax, %eax is a special case. It is an alias for nop
5813 only in 32bit mode and we can use opcode 0x90. In 64bit
5814 mode, we can't use 0x90 for xchg %eax, %eax since it should
5815 zero-extend %eax to %rax. */
5816 if (flag_code
== CODE_64BIT
5817 && t
->base_opcode
== 0x90
5818 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5819 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5821 /* xrelease mov %eax, <disp> is another special case. It must not
5822 match the accumulator-only encoding of mov. */
5823 if (flag_code
!= CODE_64BIT
5825 && t
->base_opcode
== 0xa0
5826 && i
.types
[0].bitfield
.acc
5827 && operand_type_check (i
.types
[1], anymem
))
5832 if (!(size_match
& MATCH_STRAIGHT
))
5834 /* Reverse direction of operands if swapping is possible in the first
5835 place (operands need to be symmetric) and
5836 - the load form is requested, and the template is a store form,
5837 - the store form is requested, and the template is a load form,
5838 - the non-default (swapped) form is requested. */
5839 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5840 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5841 && !operand_type_all_zero (&overlap1
))
5842 switch (i
.dir_encoding
)
5844 case dir_encoding_load
:
5845 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5846 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5850 case dir_encoding_store
:
5851 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5852 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5856 case dir_encoding_swap
:
5859 case dir_encoding_default
:
5862 /* If we want store form, we skip the current load. */
5863 if ((i
.dir_encoding
== dir_encoding_store
5864 || i
.dir_encoding
== dir_encoding_swap
)
5865 && i
.mem_operands
== 0
5866 && t
->opcode_modifier
.load
)
5871 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5872 if (!operand_type_match (overlap0
, i
.types
[0])
5873 || !operand_type_match (overlap1
, i
.types
[1])
5874 || ((check_register
& 3) == 3
5875 && !operand_type_register_match (i
.types
[0],
5880 /* Check if other direction is valid ... */
5881 if (!t
->opcode_modifier
.d
)
5885 if (!(size_match
& MATCH_REVERSE
))
5887 /* Try reversing direction of operands. */
5888 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5889 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5890 if (!operand_type_match (overlap0
, i
.types
[0])
5891 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5893 && !operand_type_register_match (i
.types
[0],
5894 operand_types
[i
.operands
- 1],
5895 i
.types
[i
.operands
- 1],
5898 /* Does not match either direction. */
5901 /* found_reverse_match holds which of D or FloatR
5903 if (!t
->opcode_modifier
.d
)
5904 found_reverse_match
= 0;
5905 else if (operand_types
[0].bitfield
.tbyte
)
5906 found_reverse_match
= Opcode_FloatD
;
5907 else if (operand_types
[0].bitfield
.xmmword
5908 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5909 || operand_types
[0].bitfield
.regmmx
5910 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5911 || is_any_vex_encoding(t
))
5912 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5913 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5915 found_reverse_match
= Opcode_D
;
5916 if (t
->opcode_modifier
.floatr
)
5917 found_reverse_match
|= Opcode_FloatR
;
5921 /* Found a forward 2 operand match here. */
5922 switch (t
->operands
)
5925 overlap4
= operand_type_and (i
.types
[4],
5929 overlap3
= operand_type_and (i
.types
[3],
5933 overlap2
= operand_type_and (i
.types
[2],
5938 switch (t
->operands
)
5941 if (!operand_type_match (overlap4
, i
.types
[4])
5942 || !operand_type_register_match (i
.types
[3],
5949 if (!operand_type_match (overlap3
, i
.types
[3])
5950 || ((check_register
& 0xa) == 0xa
5951 && !operand_type_register_match (i
.types
[1],
5955 || ((check_register
& 0xc) == 0xc
5956 && !operand_type_register_match (i
.types
[2],
5963 /* Here we make use of the fact that there are no
5964 reverse match 3 operand instructions. */
5965 if (!operand_type_match (overlap2
, i
.types
[2])
5966 || ((check_register
& 5) == 5
5967 && !operand_type_register_match (i
.types
[0],
5971 || ((check_register
& 6) == 6
5972 && !operand_type_register_match (i
.types
[1],
5980 /* Found either forward/reverse 2, 3 or 4 operand match here:
5981 slip through to break. */
5983 if (!found_cpu_match
)
5986 /* Check if vector and VEX operands are valid. */
5987 if (check_VecOperands (t
) || VEX_check_operands (t
))
5989 specific_error
= i
.error
;
5993 /* We've found a match; break out of loop. */
5997 if (t
== current_templates
->end
)
5999 /* We found no match. */
6000 const char *err_msg
;
6001 switch (specific_error
? specific_error
: i
.error
)
6005 case operand_size_mismatch
:
6006 err_msg
= _("operand size mismatch");
6008 case operand_type_mismatch
:
6009 err_msg
= _("operand type mismatch");
6011 case register_type_mismatch
:
6012 err_msg
= _("register type mismatch");
6014 case number_of_operands_mismatch
:
6015 err_msg
= _("number of operands mismatch");
6017 case invalid_instruction_suffix
:
6018 err_msg
= _("invalid instruction suffix");
6021 err_msg
= _("constant doesn't fit in 4 bits");
6023 case unsupported_with_intel_mnemonic
:
6024 err_msg
= _("unsupported with Intel mnemonic");
6026 case unsupported_syntax
:
6027 err_msg
= _("unsupported syntax");
6030 as_bad (_("unsupported instruction `%s'"),
6031 current_templates
->start
->name
);
6033 case invalid_vsib_address
:
6034 err_msg
= _("invalid VSIB address");
6036 case invalid_vector_register_set
:
6037 err_msg
= _("mask, index, and destination registers must be distinct");
6039 case unsupported_vector_index_register
:
6040 err_msg
= _("unsupported vector index register");
6042 case unsupported_broadcast
:
6043 err_msg
= _("unsupported broadcast");
6045 case broadcast_needed
:
6046 err_msg
= _("broadcast is needed for operand of such type");
6048 case unsupported_masking
:
6049 err_msg
= _("unsupported masking");
6051 case mask_not_on_destination
:
6052 err_msg
= _("mask not on destination operand");
6054 case no_default_mask
:
6055 err_msg
= _("default mask isn't allowed");
6057 case unsupported_rc_sae
:
6058 err_msg
= _("unsupported static rounding/sae");
6060 case rc_sae_operand_not_last_imm
:
6062 err_msg
= _("RC/SAE operand must precede immediate operands");
6064 err_msg
= _("RC/SAE operand must follow immediate operands");
6066 case invalid_register_operand
:
6067 err_msg
= _("invalid register operand");
6070 as_bad (_("%s for `%s'"), err_msg
,
6071 current_templates
->start
->name
);
6075 if (!quiet_warnings
)
6078 && (i
.types
[0].bitfield
.jumpabsolute
6079 != operand_types
[0].bitfield
.jumpabsolute
))
6081 as_warn (_("indirect %s without `*'"), t
->name
);
6084 if (t
->opcode_modifier
.isprefix
6085 && t
->opcode_modifier
.ignoresize
)
6087 /* Warn them that a data or address size prefix doesn't
6088 affect assembly of the next line of code. */
6089 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6093 /* Copy the template we found. */
6096 if (addr_prefix_disp
!= -1)
6097 i
.tm
.operand_types
[addr_prefix_disp
]
6098 = operand_types
[addr_prefix_disp
];
6100 if (found_reverse_match
)
6102 /* If we found a reverse match we must alter the opcode
6103 direction bit. found_reverse_match holds bits to change
6104 (different for int & float insns). */
6106 i
.tm
.base_opcode
^= found_reverse_match
;
6108 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6109 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6118 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6119 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6121 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6123 as_bad (_("`%s' operand %d must use `%ses' segment"),
6129 /* There's only ever one segment override allowed per instruction.
6130 This instruction possibly has a legal segment override on the
6131 second operand, so copy the segment to where non-string
6132 instructions store it, allowing common code. */
6133 i
.seg
[0] = i
.seg
[1];
6135 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6137 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6139 as_bad (_("`%s' operand %d must use `%ses' segment"),
6150 process_suffix (void)
6152 /* If matched instruction specifies an explicit instruction mnemonic
6154 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6155 i
.suffix
= WORD_MNEM_SUFFIX
;
6156 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6157 i
.suffix
= LONG_MNEM_SUFFIX
;
6158 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6159 i
.suffix
= QWORD_MNEM_SUFFIX
;
6160 else if (i
.reg_operands
)
6162 /* If there's no instruction mnemonic suffix we try to invent one
6163 based on register operands. */
6166 /* We take i.suffix from the last register operand specified,
6167 Destination register type is more significant than source
6168 register type. crc32 in SSE4.2 prefers source register
6170 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6172 if (i
.types
[0].bitfield
.byte
)
6173 i
.suffix
= BYTE_MNEM_SUFFIX
;
6174 else if (i
.types
[0].bitfield
.word
)
6175 i
.suffix
= WORD_MNEM_SUFFIX
;
6176 else if (i
.types
[0].bitfield
.dword
)
6177 i
.suffix
= LONG_MNEM_SUFFIX
;
6178 else if (i
.types
[0].bitfield
.qword
)
6179 i
.suffix
= QWORD_MNEM_SUFFIX
;
6186 if (i
.tm
.base_opcode
== 0xf20f38f0)
6188 /* We have to know the operand size for crc32. */
6189 as_bad (_("ambiguous memory operand size for `%s`"),
6194 for (op
= i
.operands
; --op
>= 0;)
6195 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6196 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6198 if (!i
.types
[op
].bitfield
.reg
)
6200 if (i
.types
[op
].bitfield
.byte
)
6201 i
.suffix
= BYTE_MNEM_SUFFIX
;
6202 else if (i
.types
[op
].bitfield
.word
)
6203 i
.suffix
= WORD_MNEM_SUFFIX
;
6204 else if (i
.types
[op
].bitfield
.dword
)
6205 i
.suffix
= LONG_MNEM_SUFFIX
;
6206 else if (i
.types
[op
].bitfield
.qword
)
6207 i
.suffix
= QWORD_MNEM_SUFFIX
;
6214 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6217 && i
.tm
.opcode_modifier
.ignoresize
6218 && i
.tm
.opcode_modifier
.no_bsuf
)
6220 else if (!check_byte_reg ())
6223 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6226 && i
.tm
.opcode_modifier
.ignoresize
6227 && i
.tm
.opcode_modifier
.no_lsuf
6228 && !i
.tm
.opcode_modifier
.todword
6229 && !i
.tm
.opcode_modifier
.toqword
)
6231 else if (!check_long_reg ())
6234 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6237 && i
.tm
.opcode_modifier
.ignoresize
6238 && i
.tm
.opcode_modifier
.no_qsuf
6239 && !i
.tm
.opcode_modifier
.todword
6240 && !i
.tm
.opcode_modifier
.toqword
)
6242 else if (!check_qword_reg ())
6245 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6248 && i
.tm
.opcode_modifier
.ignoresize
6249 && i
.tm
.opcode_modifier
.no_wsuf
)
6251 else if (!check_word_reg ())
6254 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6255 /* Do nothing if the instruction is going to ignore the prefix. */
6260 else if (i
.tm
.opcode_modifier
.defaultsize
6262 /* exclude fldenv/frstor/fsave/fstenv */
6263 && i
.tm
.opcode_modifier
.no_ssuf
)
6265 if (stackop_size
== LONG_MNEM_SUFFIX
6266 && i
.tm
.base_opcode
== 0xcf)
6268 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6269 .code16gcc directive to support 16-bit mode with
6270 32-bit address. For IRET without a suffix, generate
6271 16-bit IRET (opcode 0xcf) to return from an interrupt
6273 i
.suffix
= WORD_MNEM_SUFFIX
;
6274 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6277 i
.suffix
= stackop_size
;
6279 else if (intel_syntax
6281 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6282 || i
.tm
.opcode_modifier
.jumpbyte
6283 || i
.tm
.opcode_modifier
.jumpintersegment
6284 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6285 && i
.tm
.extension_opcode
<= 3)))
6290 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6292 i
.suffix
= QWORD_MNEM_SUFFIX
;
6297 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6298 i
.suffix
= LONG_MNEM_SUFFIX
;
6301 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6302 i
.suffix
= WORD_MNEM_SUFFIX
;
6311 if (i
.tm
.opcode_modifier
.w
)
6313 as_bad (_("no instruction mnemonic suffix given and "
6314 "no register operands; can't size instruction"));
6320 unsigned int suffixes
;
6322 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6323 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6325 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6327 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6329 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6331 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6334 /* There are more than suffix matches. */
6335 if (i
.tm
.opcode_modifier
.w
6336 || ((suffixes
& (suffixes
- 1))
6337 && !i
.tm
.opcode_modifier
.defaultsize
6338 && !i
.tm
.opcode_modifier
.ignoresize
))
6340 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6346 /* Change the opcode based on the operand size given by i.suffix. */
6349 /* Size floating point instruction. */
6350 case LONG_MNEM_SUFFIX
:
6351 if (i
.tm
.opcode_modifier
.floatmf
)
6353 i
.tm
.base_opcode
^= 4;
6357 case WORD_MNEM_SUFFIX
:
6358 case QWORD_MNEM_SUFFIX
:
6359 /* It's not a byte, select word/dword operation. */
6360 if (i
.tm
.opcode_modifier
.w
)
6362 if (i
.tm
.opcode_modifier
.shortform
)
6363 i
.tm
.base_opcode
|= 8;
6365 i
.tm
.base_opcode
|= 1;
6368 case SHORT_MNEM_SUFFIX
:
6369 /* Now select between word & dword operations via the operand
6370 size prefix, except for instructions that will ignore this
6372 if (i
.reg_operands
> 0
6373 && i
.types
[0].bitfield
.reg
6374 && i
.tm
.opcode_modifier
.addrprefixopreg
6375 && (i
.tm
.opcode_modifier
.immext
6376 || i
.operands
== 1))
6378 /* The address size override prefix changes the size of the
6380 if ((flag_code
== CODE_32BIT
6381 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6382 || (flag_code
!= CODE_32BIT
6383 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6384 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6387 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6388 && !i
.tm
.opcode_modifier
.ignoresize
6389 && !i
.tm
.opcode_modifier
.floatmf
6390 && !is_any_vex_encoding (&i
.tm
)
6391 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6392 || (flag_code
== CODE_64BIT
6393 && i
.tm
.opcode_modifier
.jumpbyte
)))
6395 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6397 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6398 prefix
= ADDR_PREFIX_OPCODE
;
6400 if (!add_prefix (prefix
))
6404 /* Set mode64 for an operand. */
6405 if (i
.suffix
== QWORD_MNEM_SUFFIX
6406 && flag_code
== CODE_64BIT
6407 && !i
.tm
.opcode_modifier
.norex64
6408 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6410 && ! (i
.operands
== 2
6411 && i
.tm
.base_opcode
== 0x90
6412 && i
.tm
.extension_opcode
== None
6413 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6414 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6420 if (i
.reg_operands
!= 0
6422 && i
.tm
.opcode_modifier
.addrprefixopreg
6423 && !i
.tm
.opcode_modifier
.immext
)
6425 /* Check invalid register operand when the address size override
6426 prefix changes the size of register operands. */
6428 enum { need_word
, need_dword
, need_qword
} need
;
6430 if (flag_code
== CODE_32BIT
)
6431 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6434 if (i
.prefix
[ADDR_PREFIX
])
6437 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6440 for (op
= 0; op
< i
.operands
; op
++)
6441 if (i
.types
[op
].bitfield
.reg
6442 && ((need
== need_word
6443 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6444 || (need
== need_dword
6445 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6446 || (need
== need_qword
6447 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6449 as_bad (_("invalid register operand size for `%s'"),
6459 check_byte_reg (void)
6463 for (op
= i
.operands
; --op
>= 0;)
6465 /* Skip non-register operands. */
6466 if (!i
.types
[op
].bitfield
.reg
)
6469 /* If this is an eight bit register, it's OK. If it's the 16 or
6470 32 bit version of an eight bit register, we will just use the
6471 low portion, and that's OK too. */
6472 if (i
.types
[op
].bitfield
.byte
)
6475 /* I/O port address operands are OK too. */
6476 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6479 /* crc32 doesn't generate this warning. */
6480 if (i
.tm
.base_opcode
== 0xf20f38f0)
6483 if ((i
.types
[op
].bitfield
.word
6484 || i
.types
[op
].bitfield
.dword
6485 || i
.types
[op
].bitfield
.qword
)
6486 && i
.op
[op
].regs
->reg_num
< 4
6487 /* Prohibit these changes in 64bit mode, since the lowering
6488 would be more complicated. */
6489 && flag_code
!= CODE_64BIT
)
6491 #if REGISTER_WARNINGS
6492 if (!quiet_warnings
)
6493 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6495 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6496 ? REGNAM_AL
- REGNAM_AX
6497 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6499 i
.op
[op
].regs
->reg_name
,
6504 /* Any other register is bad. */
6505 if (i
.types
[op
].bitfield
.reg
6506 || i
.types
[op
].bitfield
.regmmx
6507 || i
.types
[op
].bitfield
.regsimd
6508 || i
.types
[op
].bitfield
.sreg2
6509 || i
.types
[op
].bitfield
.sreg3
6510 || i
.types
[op
].bitfield
.control
6511 || i
.types
[op
].bitfield
.debug
6512 || i
.types
[op
].bitfield
.test
)
6514 as_bad (_("`%s%s' not allowed with `%s%c'"),
6516 i
.op
[op
].regs
->reg_name
,
6526 check_long_reg (void)
6530 for (op
= i
.operands
; --op
>= 0;)
6531 /* Skip non-register operands. */
6532 if (!i
.types
[op
].bitfield
.reg
)
6534 /* Reject eight bit registers, except where the template requires
6535 them. (eg. movzb) */
6536 else if (i
.types
[op
].bitfield
.byte
6537 && (i
.tm
.operand_types
[op
].bitfield
.reg
6538 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6539 && (i
.tm
.operand_types
[op
].bitfield
.word
6540 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6542 as_bad (_("`%s%s' not allowed with `%s%c'"),
6544 i
.op
[op
].regs
->reg_name
,
6549 /* Warn if the e prefix on a general reg is missing. */
6550 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6551 && i
.types
[op
].bitfield
.word
6552 && (i
.tm
.operand_types
[op
].bitfield
.reg
6553 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6554 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6556 /* Prohibit these changes in the 64bit mode, since the
6557 lowering is more complicated. */
6558 if (flag_code
== CODE_64BIT
)
6560 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6561 register_prefix
, i
.op
[op
].regs
->reg_name
,
6565 #if REGISTER_WARNINGS
6566 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6568 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6569 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6572 /* Warn if the r prefix on a general reg is present. */
6573 else if (i
.types
[op
].bitfield
.qword
6574 && (i
.tm
.operand_types
[op
].bitfield
.reg
6575 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6576 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6579 && i
.tm
.opcode_modifier
.toqword
6580 && !i
.types
[0].bitfield
.regsimd
)
6582 /* Convert to QWORD. We want REX byte. */
6583 i
.suffix
= QWORD_MNEM_SUFFIX
;
6587 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6588 register_prefix
, i
.op
[op
].regs
->reg_name
,
6597 check_qword_reg (void)
6601 for (op
= i
.operands
; --op
>= 0; )
6602 /* Skip non-register operands. */
6603 if (!i
.types
[op
].bitfield
.reg
)
6605 /* Reject eight bit registers, except where the template requires
6606 them. (eg. movzb) */
6607 else if (i
.types
[op
].bitfield
.byte
6608 && (i
.tm
.operand_types
[op
].bitfield
.reg
6609 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6610 && (i
.tm
.operand_types
[op
].bitfield
.word
6611 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6613 as_bad (_("`%s%s' not allowed with `%s%c'"),
6615 i
.op
[op
].regs
->reg_name
,
6620 /* Warn if the r prefix on a general reg is missing. */
6621 else if ((i
.types
[op
].bitfield
.word
6622 || i
.types
[op
].bitfield
.dword
)
6623 && (i
.tm
.operand_types
[op
].bitfield
.reg
6624 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6625 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6627 /* Prohibit these changes in the 64bit mode, since the
6628 lowering is more complicated. */
6630 && i
.tm
.opcode_modifier
.todword
6631 && !i
.types
[0].bitfield
.regsimd
)
6633 /* Convert to DWORD. We don't want REX byte. */
6634 i
.suffix
= LONG_MNEM_SUFFIX
;
6638 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6639 register_prefix
, i
.op
[op
].regs
->reg_name
,
6648 check_word_reg (void)
6651 for (op
= i
.operands
; --op
>= 0;)
6652 /* Skip non-register operands. */
6653 if (!i
.types
[op
].bitfield
.reg
)
6655 /* Reject eight bit registers, except where the template requires
6656 them. (eg. movzb) */
6657 else if (i
.types
[op
].bitfield
.byte
6658 && (i
.tm
.operand_types
[op
].bitfield
.reg
6659 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6660 && (i
.tm
.operand_types
[op
].bitfield
.word
6661 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6663 as_bad (_("`%s%s' not allowed with `%s%c'"),
6665 i
.op
[op
].regs
->reg_name
,
6670 /* Warn if the e or r prefix on a general reg is present. */
6671 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6672 && (i
.types
[op
].bitfield
.dword
6673 || i
.types
[op
].bitfield
.qword
)
6674 && (i
.tm
.operand_types
[op
].bitfield
.reg
6675 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6676 && i
.tm
.operand_types
[op
].bitfield
.word
)
6678 /* Prohibit these changes in the 64bit mode, since the
6679 lowering is more complicated. */
6680 if (flag_code
== CODE_64BIT
)
6682 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6683 register_prefix
, i
.op
[op
].regs
->reg_name
,
6687 #if REGISTER_WARNINGS
6688 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6690 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6691 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6698 update_imm (unsigned int j
)
6700 i386_operand_type overlap
= i
.types
[j
];
6701 if ((overlap
.bitfield
.imm8
6702 || overlap
.bitfield
.imm8s
6703 || overlap
.bitfield
.imm16
6704 || overlap
.bitfield
.imm32
6705 || overlap
.bitfield
.imm32s
6706 || overlap
.bitfield
.imm64
)
6707 && !operand_type_equal (&overlap
, &imm8
)
6708 && !operand_type_equal (&overlap
, &imm8s
)
6709 && !operand_type_equal (&overlap
, &imm16
)
6710 && !operand_type_equal (&overlap
, &imm32
)
6711 && !operand_type_equal (&overlap
, &imm32s
)
6712 && !operand_type_equal (&overlap
, &imm64
))
6716 i386_operand_type temp
;
6718 operand_type_set (&temp
, 0);
6719 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6721 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6722 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6724 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6725 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6726 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6728 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6729 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6732 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6735 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6736 || operand_type_equal (&overlap
, &imm16_32
)
6737 || operand_type_equal (&overlap
, &imm16_32s
))
6739 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6744 if (!operand_type_equal (&overlap
, &imm8
)
6745 && !operand_type_equal (&overlap
, &imm8s
)
6746 && !operand_type_equal (&overlap
, &imm16
)
6747 && !operand_type_equal (&overlap
, &imm32
)
6748 && !operand_type_equal (&overlap
, &imm32s
)
6749 && !operand_type_equal (&overlap
, &imm64
))
6751 as_bad (_("no instruction mnemonic suffix given; "
6752 "can't determine immediate size"));
6756 i
.types
[j
] = overlap
;
6766 /* Update the first 2 immediate operands. */
6767 n
= i
.operands
> 2 ? 2 : i
.operands
;
6770 for (j
= 0; j
< n
; j
++)
6771 if (update_imm (j
) == 0)
6774 /* The 3rd operand can't be immediate operand. */
6775 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6782 process_operands (void)
6784 /* Default segment register this instruction will use for memory
6785 accesses. 0 means unknown. This is only for optimizing out
6786 unnecessary segment overrides. */
6787 const seg_entry
*default_seg
= 0;
6789 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6791 unsigned int dupl
= i
.operands
;
6792 unsigned int dest
= dupl
- 1;
6795 /* The destination must be an xmm register. */
6796 gas_assert (i
.reg_operands
6797 && MAX_OPERANDS
> dupl
6798 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6800 if (i
.tm
.operand_types
[0].bitfield
.acc
6801 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6803 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6805 /* Keep xmm0 for instructions with VEX prefix and 3
6807 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6808 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6813 /* We remove the first xmm0 and keep the number of
6814 operands unchanged, which in fact duplicates the
6816 for (j
= 1; j
< i
.operands
; j
++)
6818 i
.op
[j
- 1] = i
.op
[j
];
6819 i
.types
[j
- 1] = i
.types
[j
];
6820 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6824 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6826 gas_assert ((MAX_OPERANDS
- 1) > dupl
6827 && (i
.tm
.opcode_modifier
.vexsources
6830 /* Add the implicit xmm0 for instructions with VEX prefix
6832 for (j
= i
.operands
; j
> 0; j
--)
6834 i
.op
[j
] = i
.op
[j
- 1];
6835 i
.types
[j
] = i
.types
[j
- 1];
6836 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6839 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6840 i
.types
[0] = regxmm
;
6841 i
.tm
.operand_types
[0] = regxmm
;
6844 i
.reg_operands
+= 2;
6849 i
.op
[dupl
] = i
.op
[dest
];
6850 i
.types
[dupl
] = i
.types
[dest
];
6851 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6860 i
.op
[dupl
] = i
.op
[dest
];
6861 i
.types
[dupl
] = i
.types
[dest
];
6862 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6865 if (i
.tm
.opcode_modifier
.immext
)
6868 else if (i
.tm
.operand_types
[0].bitfield
.acc
6869 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6873 for (j
= 1; j
< i
.operands
; j
++)
6875 i
.op
[j
- 1] = i
.op
[j
];
6876 i
.types
[j
- 1] = i
.types
[j
];
6878 /* We need to adjust fields in i.tm since they are used by
6879 build_modrm_byte. */
6880 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6887 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6889 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6891 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6892 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6893 regnum
= register_number (i
.op
[1].regs
);
6894 first_reg_in_group
= regnum
& ~3;
6895 last_reg_in_group
= first_reg_in_group
+ 3;
6896 if (regnum
!= first_reg_in_group
)
6897 as_warn (_("source register `%s%s' implicitly denotes"
6898 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6899 register_prefix
, i
.op
[1].regs
->reg_name
,
6900 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6901 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6904 else if (i
.tm
.opcode_modifier
.regkludge
)
6906 /* The imul $imm, %reg instruction is converted into
6907 imul $imm, %reg, %reg, and the clr %reg instruction
6908 is converted into xor %reg, %reg. */
6910 unsigned int first_reg_op
;
6912 if (operand_type_check (i
.types
[0], reg
))
6916 /* Pretend we saw the extra register operand. */
6917 gas_assert (i
.reg_operands
== 1
6918 && i
.op
[first_reg_op
+ 1].regs
== 0);
6919 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6920 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6925 if (i
.tm
.opcode_modifier
.shortform
)
6927 if (i
.types
[0].bitfield
.sreg2
6928 || i
.types
[0].bitfield
.sreg3
)
6930 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6931 && i
.op
[0].regs
->reg_num
== 1)
6933 as_bad (_("you can't `pop %scs'"), register_prefix
);
6936 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6937 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6942 /* The register or float register operand is in operand
6946 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6947 || operand_type_check (i
.types
[0], reg
))
6951 /* Register goes in low 3 bits of opcode. */
6952 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6953 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6955 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6957 /* Warn about some common errors, but press on regardless.
6958 The first case can be generated by gcc (<= 2.8.1). */
6959 if (i
.operands
== 2)
6961 /* Reversed arguments on faddp, fsubp, etc. */
6962 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6963 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6964 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6968 /* Extraneous `l' suffix on fp insn. */
6969 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6970 register_prefix
, i
.op
[0].regs
->reg_name
);
6975 else if (i
.tm
.opcode_modifier
.modrm
)
6977 /* The opcode is completed (modulo i.tm.extension_opcode which
6978 must be put into the modrm byte). Now, we make the modrm and
6979 index base bytes based on all the info we've collected. */
6981 default_seg
= build_modrm_byte ();
6983 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6987 else if (i
.tm
.opcode_modifier
.isstring
)
6989 /* For the string instructions that allow a segment override
6990 on one of their operands, the default segment is ds. */
6994 if (i
.tm
.base_opcode
== 0x8d /* lea */
6997 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6999 /* If a segment was explicitly specified, and the specified segment
7000 is not the default, use an opcode prefix to select it. If we
7001 never figured out what the default segment is, then default_seg
7002 will be zero at this point, and the specified segment prefix will
7004 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7006 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7012 static const seg_entry
*
7013 build_modrm_byte (void)
7015 const seg_entry
*default_seg
= 0;
7016 unsigned int source
, dest
;
7019 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7022 unsigned int nds
, reg_slot
;
7025 dest
= i
.operands
- 1;
7028 /* There are 2 kinds of instructions:
7029 1. 5 operands: 4 register operands or 3 register operands
7030 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7031 VexW0 or VexW1. The destination must be either XMM, YMM or
7033 2. 4 operands: 4 register operands or 3 register operands
7034 plus 1 memory operand, with VexXDS. */
7035 gas_assert ((i
.reg_operands
== 4
7036 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7037 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7038 && i
.tm
.opcode_modifier
.vexw
7039 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7041 /* If VexW1 is set, the first non-immediate operand is the source and
7042 the second non-immediate one is encoded in the immediate operand. */
7043 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7045 source
= i
.imm_operands
;
7046 reg_slot
= i
.imm_operands
+ 1;
7050 source
= i
.imm_operands
+ 1;
7051 reg_slot
= i
.imm_operands
;
7054 if (i
.imm_operands
== 0)
7056 /* When there is no immediate operand, generate an 8bit
7057 immediate operand to encode the first operand. */
7058 exp
= &im_expressions
[i
.imm_operands
++];
7059 i
.op
[i
.operands
].imms
= exp
;
7060 i
.types
[i
.operands
] = imm8
;
7063 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7064 exp
->X_op
= O_constant
;
7065 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7066 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7070 unsigned int imm_slot
;
7072 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7074 if (i
.tm
.opcode_modifier
.immext
)
7076 /* When ImmExt is set, the immediate byte is the last
7078 imm_slot
= i
.operands
- 1;
7086 /* Turn on Imm8 so that output_imm will generate it. */
7087 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7090 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7091 i
.op
[imm_slot
].imms
->X_add_number
7092 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7093 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7096 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7097 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7102 /* i.reg_operands MUST be the number of real register operands;
7103 implicit registers do not count. If there are 3 register
7104 operands, it must be a instruction with VexNDS. For a
7105 instruction with VexNDD, the destination register is encoded
7106 in VEX prefix. If there are 4 register operands, it must be
7107 a instruction with VEX prefix and 3 sources. */
7108 if (i
.mem_operands
== 0
7109 && ((i
.reg_operands
== 2
7110 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7111 || (i
.reg_operands
== 3
7112 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7113 || (i
.reg_operands
== 4 && vex_3_sources
)))
7121 /* When there are 3 operands, one of them may be immediate,
7122 which may be the first or the last operand. Otherwise,
7123 the first operand must be shift count register (cl) or it
7124 is an instruction with VexNDS. */
7125 gas_assert (i
.imm_operands
== 1
7126 || (i
.imm_operands
== 0
7127 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7128 || i
.types
[0].bitfield
.shiftcount
)));
7129 if (operand_type_check (i
.types
[0], imm
)
7130 || i
.types
[0].bitfield
.shiftcount
)
7136 /* When there are 4 operands, the first two must be 8bit
7137 immediate operands. The source operand will be the 3rd
7140 For instructions with VexNDS, if the first operand
7141 an imm8, the source operand is the 2nd one. If the last
7142 operand is imm8, the source operand is the first one. */
7143 gas_assert ((i
.imm_operands
== 2
7144 && i
.types
[0].bitfield
.imm8
7145 && i
.types
[1].bitfield
.imm8
)
7146 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7147 && i
.imm_operands
== 1
7148 && (i
.types
[0].bitfield
.imm8
7149 || i
.types
[i
.operands
- 1].bitfield
.imm8
7151 if (i
.imm_operands
== 2)
7155 if (i
.types
[0].bitfield
.imm8
)
7162 if (is_evex_encoding (&i
.tm
))
7164 /* For EVEX instructions, when there are 5 operands, the
7165 first one must be immediate operand. If the second one
7166 is immediate operand, the source operand is the 3th
7167 one. If the last one is immediate operand, the source
7168 operand is the 2nd one. */
7169 gas_assert (i
.imm_operands
== 2
7170 && i
.tm
.opcode_modifier
.sae
7171 && operand_type_check (i
.types
[0], imm
));
7172 if (operand_type_check (i
.types
[1], imm
))
7174 else if (operand_type_check (i
.types
[4], imm
))
7188 /* RC/SAE operand could be between DEST and SRC. That happens
7189 when one operand is GPR and the other one is XMM/YMM/ZMM
7191 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7194 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7196 /* For instructions with VexNDS, the register-only source
7197 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7198 register. It is encoded in VEX prefix. We need to
7199 clear RegMem bit before calling operand_type_equal. */
7201 i386_operand_type op
;
7204 /* Check register-only source operand when two source
7205 operands are swapped. */
7206 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7207 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7215 op
= i
.tm
.operand_types
[vvvv
];
7216 op
.bitfield
.regmem
= 0;
7217 if ((dest
+ 1) >= i
.operands
7218 || ((!op
.bitfield
.reg
7219 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7220 && !op
.bitfield
.regsimd
7221 && !operand_type_equal (&op
, ®mask
)))
7223 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7229 /* One of the register operands will be encoded in the i.tm.reg
7230 field, the other in the combined i.tm.mode and i.tm.regmem
7231 fields. If no form of this instruction supports a memory
7232 destination operand, then we assume the source operand may
7233 sometimes be a memory operand and so we need to store the
7234 destination in the i.rm.reg field. */
7235 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7236 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7238 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7239 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7240 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7241 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7242 i
.has_regmmx
= TRUE
;
7243 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7244 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7246 if (i
.types
[dest
].bitfield
.zmmword
7247 || i
.types
[source
].bitfield
.zmmword
)
7248 i
.has_regzmm
= TRUE
;
7249 else if (i
.types
[dest
].bitfield
.ymmword
7250 || i
.types
[source
].bitfield
.ymmword
)
7251 i
.has_regymm
= TRUE
;
7253 i
.has_regxmm
= TRUE
;
7255 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7257 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7259 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7261 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7266 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7267 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7268 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7270 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7272 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7274 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7277 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7279 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7282 add_prefix (LOCK_PREFIX_OPCODE
);
7286 { /* If it's not 2 reg operands... */
7291 unsigned int fake_zero_displacement
= 0;
7294 for (op
= 0; op
< i
.operands
; op
++)
7295 if (operand_type_check (i
.types
[op
], anymem
))
7297 gas_assert (op
< i
.operands
);
7299 if (i
.tm
.opcode_modifier
.vecsib
)
7301 if (i
.index_reg
->reg_num
== RegIZ
)
7304 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7307 i
.sib
.base
= NO_BASE_REGISTER
;
7308 i
.sib
.scale
= i
.log2_scale_factor
;
7309 i
.types
[op
].bitfield
.disp8
= 0;
7310 i
.types
[op
].bitfield
.disp16
= 0;
7311 i
.types
[op
].bitfield
.disp64
= 0;
7312 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7314 /* Must be 32 bit */
7315 i
.types
[op
].bitfield
.disp32
= 1;
7316 i
.types
[op
].bitfield
.disp32s
= 0;
7320 i
.types
[op
].bitfield
.disp32
= 0;
7321 i
.types
[op
].bitfield
.disp32s
= 1;
7324 i
.sib
.index
= i
.index_reg
->reg_num
;
7325 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7327 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7333 if (i
.base_reg
== 0)
7336 if (!i
.disp_operands
)
7337 fake_zero_displacement
= 1;
7338 if (i
.index_reg
== 0)
7340 i386_operand_type newdisp
;
7342 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7343 /* Operand is just <disp> */
7344 if (flag_code
== CODE_64BIT
)
7346 /* 64bit mode overwrites the 32bit absolute
7347 addressing by RIP relative addressing and
7348 absolute addressing is encoded by one of the
7349 redundant SIB forms. */
7350 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7351 i
.sib
.base
= NO_BASE_REGISTER
;
7352 i
.sib
.index
= NO_INDEX_REGISTER
;
7353 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7355 else if ((flag_code
== CODE_16BIT
)
7356 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7358 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7363 i
.rm
.regmem
= NO_BASE_REGISTER
;
7366 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7367 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7369 else if (!i
.tm
.opcode_modifier
.vecsib
)
7371 /* !i.base_reg && i.index_reg */
7372 if (i
.index_reg
->reg_num
== RegIZ
)
7373 i
.sib
.index
= NO_INDEX_REGISTER
;
7375 i
.sib
.index
= i
.index_reg
->reg_num
;
7376 i
.sib
.base
= NO_BASE_REGISTER
;
7377 i
.sib
.scale
= i
.log2_scale_factor
;
7378 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7379 i
.types
[op
].bitfield
.disp8
= 0;
7380 i
.types
[op
].bitfield
.disp16
= 0;
7381 i
.types
[op
].bitfield
.disp64
= 0;
7382 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7384 /* Must be 32 bit */
7385 i
.types
[op
].bitfield
.disp32
= 1;
7386 i
.types
[op
].bitfield
.disp32s
= 0;
7390 i
.types
[op
].bitfield
.disp32
= 0;
7391 i
.types
[op
].bitfield
.disp32s
= 1;
7393 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7397 /* RIP addressing for 64bit mode. */
7398 else if (i
.base_reg
->reg_num
== RegIP
)
7400 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7401 i
.rm
.regmem
= NO_BASE_REGISTER
;
7402 i
.types
[op
].bitfield
.disp8
= 0;
7403 i
.types
[op
].bitfield
.disp16
= 0;
7404 i
.types
[op
].bitfield
.disp32
= 0;
7405 i
.types
[op
].bitfield
.disp32s
= 1;
7406 i
.types
[op
].bitfield
.disp64
= 0;
7407 i
.flags
[op
] |= Operand_PCrel
;
7408 if (! i
.disp_operands
)
7409 fake_zero_displacement
= 1;
7411 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7413 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7414 switch (i
.base_reg
->reg_num
)
7417 if (i
.index_reg
== 0)
7419 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7420 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7424 if (i
.index_reg
== 0)
7427 if (operand_type_check (i
.types
[op
], disp
) == 0)
7429 /* fake (%bp) into 0(%bp) */
7430 i
.types
[op
].bitfield
.disp8
= 1;
7431 fake_zero_displacement
= 1;
7434 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7435 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7437 default: /* (%si) -> 4 or (%di) -> 5 */
7438 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7440 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7442 else /* i.base_reg and 32/64 bit mode */
7444 if (flag_code
== CODE_64BIT
7445 && operand_type_check (i
.types
[op
], disp
))
7447 i
.types
[op
].bitfield
.disp16
= 0;
7448 i
.types
[op
].bitfield
.disp64
= 0;
7449 if (i
.prefix
[ADDR_PREFIX
] == 0)
7451 i
.types
[op
].bitfield
.disp32
= 0;
7452 i
.types
[op
].bitfield
.disp32s
= 1;
7456 i
.types
[op
].bitfield
.disp32
= 1;
7457 i
.types
[op
].bitfield
.disp32s
= 0;
7461 if (!i
.tm
.opcode_modifier
.vecsib
)
7462 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7463 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7465 i
.sib
.base
= i
.base_reg
->reg_num
;
7466 /* x86-64 ignores REX prefix bit here to avoid decoder
7468 if (!(i
.base_reg
->reg_flags
& RegRex
)
7469 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7470 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7472 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7474 fake_zero_displacement
= 1;
7475 i
.types
[op
].bitfield
.disp8
= 1;
7477 i
.sib
.scale
= i
.log2_scale_factor
;
7478 if (i
.index_reg
== 0)
7480 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7481 /* <disp>(%esp) becomes two byte modrm with no index
7482 register. We've already stored the code for esp
7483 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7484 Any base register besides %esp will not use the
7485 extra modrm byte. */
7486 i
.sib
.index
= NO_INDEX_REGISTER
;
7488 else if (!i
.tm
.opcode_modifier
.vecsib
)
7490 if (i
.index_reg
->reg_num
== RegIZ
)
7491 i
.sib
.index
= NO_INDEX_REGISTER
;
7493 i
.sib
.index
= i
.index_reg
->reg_num
;
7494 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7495 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7500 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7501 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7505 if (!fake_zero_displacement
7509 fake_zero_displacement
= 1;
7510 if (i
.disp_encoding
== disp_encoding_8bit
)
7511 i
.types
[op
].bitfield
.disp8
= 1;
7513 i
.types
[op
].bitfield
.disp32
= 1;
7515 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7519 if (fake_zero_displacement
)
7521 /* Fakes a zero displacement assuming that i.types[op]
7522 holds the correct displacement size. */
7525 gas_assert (i
.op
[op
].disps
== 0);
7526 exp
= &disp_expressions
[i
.disp_operands
++];
7527 i
.op
[op
].disps
= exp
;
7528 exp
->X_op
= O_constant
;
7529 exp
->X_add_number
= 0;
7530 exp
->X_add_symbol
= (symbolS
*) 0;
7531 exp
->X_op_symbol
= (symbolS
*) 0;
7539 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7541 if (operand_type_check (i
.types
[0], imm
))
7542 i
.vex
.register_specifier
= NULL
;
7545 /* VEX.vvvv encodes one of the sources when the first
7546 operand is not an immediate. */
7547 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7548 i
.vex
.register_specifier
= i
.op
[0].regs
;
7550 i
.vex
.register_specifier
= i
.op
[1].regs
;
7553 /* Destination is a XMM register encoded in the ModRM.reg
7555 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7556 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7559 /* ModRM.rm and VEX.B encodes the other source. */
7560 if (!i
.mem_operands
)
7564 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7565 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7567 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7569 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7573 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7575 i
.vex
.register_specifier
= i
.op
[2].regs
;
7576 if (!i
.mem_operands
)
7579 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7580 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7584 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7585 (if any) based on i.tm.extension_opcode. Again, we must be
7586 careful to make sure that segment/control/debug/test/MMX
7587 registers are coded into the i.rm.reg field. */
7588 else if (i
.reg_operands
)
7591 unsigned int vex_reg
= ~0;
7593 for (op
= 0; op
< i
.operands
; op
++)
7595 if (i
.types
[op
].bitfield
.reg
7596 || i
.types
[op
].bitfield
.regbnd
7597 || i
.types
[op
].bitfield
.regmask
7598 || i
.types
[op
].bitfield
.sreg2
7599 || i
.types
[op
].bitfield
.sreg3
7600 || i
.types
[op
].bitfield
.control
7601 || i
.types
[op
].bitfield
.debug
7602 || i
.types
[op
].bitfield
.test
)
7604 if (i
.types
[op
].bitfield
.regsimd
)
7606 if (i
.types
[op
].bitfield
.zmmword
)
7607 i
.has_regzmm
= TRUE
;
7608 else if (i
.types
[op
].bitfield
.ymmword
)
7609 i
.has_regymm
= TRUE
;
7611 i
.has_regxmm
= TRUE
;
7614 if (i
.types
[op
].bitfield
.regmmx
)
7616 i
.has_regmmx
= TRUE
;
7623 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7625 /* For instructions with VexNDS, the register-only
7626 source operand is encoded in VEX prefix. */
7627 gas_assert (mem
!= (unsigned int) ~0);
7632 gas_assert (op
< i
.operands
);
7636 /* Check register-only source operand when two source
7637 operands are swapped. */
7638 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7639 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7643 gas_assert (mem
== (vex_reg
+ 1)
7644 && op
< i
.operands
);
7649 gas_assert (vex_reg
< i
.operands
);
7653 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7655 /* For instructions with VexNDD, the register destination
7656 is encoded in VEX prefix. */
7657 if (i
.mem_operands
== 0)
7659 /* There is no memory operand. */
7660 gas_assert ((op
+ 2) == i
.operands
);
7665 /* There are only 2 non-immediate operands. */
7666 gas_assert (op
< i
.imm_operands
+ 2
7667 && i
.operands
== i
.imm_operands
+ 2);
7668 vex_reg
= i
.imm_operands
+ 1;
7672 gas_assert (op
< i
.operands
);
7674 if (vex_reg
!= (unsigned int) ~0)
7676 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7678 if ((!type
->bitfield
.reg
7679 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7680 && !type
->bitfield
.regsimd
7681 && !operand_type_equal (type
, ®mask
))
7684 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7687 /* Don't set OP operand twice. */
7690 /* If there is an extension opcode to put here, the
7691 register number must be put into the regmem field. */
7692 if (i
.tm
.extension_opcode
!= None
)
7694 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7695 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7697 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7702 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7703 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7705 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7710 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7711 must set it to 3 to indicate this is a register operand
7712 in the regmem field. */
7713 if (!i
.mem_operands
)
7717 /* Fill in i.rm.reg field with extension opcode (if any). */
7718 if (i
.tm
.extension_opcode
!= None
)
7719 i
.rm
.reg
= i
.tm
.extension_opcode
;
7725 output_branch (void)
7731 relax_substateT subtype
;
7735 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7736 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7739 if (i
.prefix
[DATA_PREFIX
] != 0)
7745 /* Pentium4 branch hints. */
7746 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7747 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7752 if (i
.prefix
[REX_PREFIX
] != 0)
7758 /* BND prefixed jump. */
7759 if (i
.prefix
[BND_PREFIX
] != 0)
7761 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7765 if (i
.prefixes
!= 0 && !intel_syntax
)
7766 as_warn (_("skipping prefixes on this instruction"));
7768 /* It's always a symbol; End frag & setup for relax.
7769 Make sure there is enough room in this frag for the largest
7770 instruction we may generate in md_convert_frag. This is 2
7771 bytes for the opcode and room for the prefix and largest
7773 frag_grow (prefix
+ 2 + 4);
7774 /* Prefix and 1 opcode byte go in fr_fix. */
7775 p
= frag_more (prefix
+ 1);
7776 if (i
.prefix
[DATA_PREFIX
] != 0)
7777 *p
++ = DATA_PREFIX_OPCODE
;
7778 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7779 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7780 *p
++ = i
.prefix
[SEG_PREFIX
];
7781 if (i
.prefix
[REX_PREFIX
] != 0)
7782 *p
++ = i
.prefix
[REX_PREFIX
];
7783 *p
= i
.tm
.base_opcode
;
7785 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7786 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7787 else if (cpu_arch_flags
.bitfield
.cpui386
)
7788 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7790 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7793 sym
= i
.op
[0].disps
->X_add_symbol
;
7794 off
= i
.op
[0].disps
->X_add_number
;
7796 if (i
.op
[0].disps
->X_op
!= O_constant
7797 && i
.op
[0].disps
->X_op
!= O_symbol
)
7799 /* Handle complex expressions. */
7800 sym
= make_expr_symbol (i
.op
[0].disps
);
7804 /* 1 possible extra opcode + 4 byte displacement go in var part.
7805 Pass reloc in fr_var. */
7806 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7810 /* Return TRUE iff PLT32 relocation should be used for branching to
7814 need_plt32_p (symbolS
*s
)
7816 /* PLT32 relocation is ELF only. */
7821 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7822 krtld support it. */
7826 /* Since there is no need to prepare for PLT branch on x86-64, we
7827 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7828 be used as a marker for 32-bit PC-relative branches. */
7832 /* Weak or undefined symbol need PLT32 relocation. */
7833 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7836 /* Non-global symbol doesn't need PLT32 relocation. */
7837 if (! S_IS_EXTERNAL (s
))
7840 /* Other global symbols need PLT32 relocation. NB: Symbol with
7841 non-default visibilities are treated as normal global symbol
7842 so that PLT32 relocation can be used as a marker for 32-bit
7843 PC-relative branches. It is useful for linker relaxation. */
7854 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7856 if (i
.tm
.opcode_modifier
.jumpbyte
)
7858 /* This is a loop or jecxz type instruction. */
7860 if (i
.prefix
[ADDR_PREFIX
] != 0)
7862 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7865 /* Pentium4 branch hints. */
7866 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7867 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7869 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7878 if (flag_code
== CODE_16BIT
)
7881 if (i
.prefix
[DATA_PREFIX
] != 0)
7883 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7893 if (i
.prefix
[REX_PREFIX
] != 0)
7895 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7899 /* BND prefixed jump. */
7900 if (i
.prefix
[BND_PREFIX
] != 0)
7902 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7906 if (i
.prefixes
!= 0 && !intel_syntax
)
7907 as_warn (_("skipping prefixes on this instruction"));
7909 p
= frag_more (i
.tm
.opcode_length
+ size
);
7910 switch (i
.tm
.opcode_length
)
7913 *p
++ = i
.tm
.base_opcode
>> 8;
7916 *p
++ = i
.tm
.base_opcode
;
7922 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7924 && jump_reloc
== NO_RELOC
7925 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7926 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7929 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7931 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7932 i
.op
[0].disps
, 1, jump_reloc
);
7934 /* All jumps handled here are signed, but don't use a signed limit
7935 check for 32 and 16 bit jumps as we want to allow wrap around at
7936 4G and 64k respectively. */
7938 fixP
->fx_signed
= 1;
7942 output_interseg_jump (void)
7950 if (flag_code
== CODE_16BIT
)
7954 if (i
.prefix
[DATA_PREFIX
] != 0)
7960 if (i
.prefix
[REX_PREFIX
] != 0)
7970 if (i
.prefixes
!= 0 && !intel_syntax
)
7971 as_warn (_("skipping prefixes on this instruction"));
7973 /* 1 opcode; 2 segment; offset */
7974 p
= frag_more (prefix
+ 1 + 2 + size
);
7976 if (i
.prefix
[DATA_PREFIX
] != 0)
7977 *p
++ = DATA_PREFIX_OPCODE
;
7979 if (i
.prefix
[REX_PREFIX
] != 0)
7980 *p
++ = i
.prefix
[REX_PREFIX
];
7982 *p
++ = i
.tm
.base_opcode
;
7983 if (i
.op
[1].imms
->X_op
== O_constant
)
7985 offsetT n
= i
.op
[1].imms
->X_add_number
;
7988 && !fits_in_unsigned_word (n
)
7989 && !fits_in_signed_word (n
))
7991 as_bad (_("16-bit jump out of range"));
7994 md_number_to_chars (p
, n
, size
);
7997 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7998 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7999 if (i
.op
[0].imms
->X_op
!= O_constant
)
8000 as_bad (_("can't handle non absolute segment in `%s'"),
8002 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8010 asection
*seg
= now_seg
;
8011 subsegT subseg
= now_subseg
;
8013 unsigned int alignment
, align_size_1
;
8014 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8015 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8016 unsigned int padding
;
8018 if (!IS_ELF
|| !x86_used_note
)
8021 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8023 /* The .note.gnu.property section layout:
8025 Field Length Contents
8028 n_descsz 4 The note descriptor size
8029 n_type 4 NT_GNU_PROPERTY_TYPE_0
8031 n_desc n_descsz The program property array
8035 /* Create the .note.gnu.property section. */
8036 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8037 bfd_set_section_flags (stdoutput
, sec
,
8044 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8055 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8056 elf_section_type (sec
) = SHT_NOTE
;
8058 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8060 isa_1_descsz_raw
= 4 + 4 + 4;
8061 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8062 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8064 feature_2_descsz_raw
= isa_1_descsz
;
8065 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8067 feature_2_descsz_raw
+= 4 + 4 + 4;
8068 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8069 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8072 descsz
= feature_2_descsz
;
8073 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8074 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8076 /* Write n_namsz. */
8077 md_number_to_chars (p
, (valueT
) 4, 4);
8079 /* Write n_descsz. */
8080 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8083 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8086 memcpy (p
+ 4 * 3, "GNU", 4);
8088 /* Write 4-byte type. */
8089 md_number_to_chars (p
+ 4 * 4,
8090 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8092 /* Write 4-byte data size. */
8093 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8095 /* Write 4-byte data. */
8096 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8098 /* Zero out paddings. */
8099 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8101 memset (p
+ 4 * 7, 0, padding
);
8103 /* Write 4-byte type. */
8104 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8105 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8107 /* Write 4-byte data size. */
8108 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8110 /* Write 4-byte data. */
8111 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8112 (valueT
) x86_feature_2_used
, 4);
8114 /* Zero out paddings. */
8115 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8117 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8119 /* We probably can't restore the current segment, for there likely
8122 subseg_set (seg
, subseg
);
8127 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8128 const char *frag_now_ptr
)
8130 unsigned int len
= 0;
8132 if (start_frag
!= frag_now
)
8134 const fragS
*fr
= start_frag
;
8139 } while (fr
&& fr
!= frag_now
);
8142 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8148 fragS
*insn_start_frag
;
8149 offsetT insn_start_off
;
8151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8152 if (IS_ELF
&& x86_used_note
)
8154 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8155 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8156 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8157 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8158 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8159 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8160 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8161 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8162 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8163 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8164 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8165 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8166 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8167 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8168 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8169 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8170 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8171 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8172 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8173 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8174 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8175 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8176 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8177 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8178 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8179 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8180 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8181 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8182 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8183 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8184 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8186 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8187 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8188 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8189 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8190 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8191 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8192 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8193 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8194 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8195 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8196 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8197 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8198 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8199 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8200 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8201 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8202 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8203 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8205 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8206 || i
.tm
.cpu_flags
.bitfield
.cpu287
8207 || i
.tm
.cpu_flags
.bitfield
.cpu387
8208 || i
.tm
.cpu_flags
.bitfield
.cpu687
8209 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8210 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8211 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8212 Xfence instructions. */
8213 if (i
.tm
.base_opcode
!= 0xf18
8214 && i
.tm
.base_opcode
!= 0xf0d
8215 && i
.tm
.base_opcode
!= 0xfae
8217 || i
.tm
.cpu_flags
.bitfield
.cpummx
8218 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8219 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8220 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8222 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8224 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8226 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8227 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8228 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8229 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8230 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8231 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8232 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8233 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8234 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8238 /* Tie dwarf2 debug info to the address at the start of the insn.
8239 We can't do this after the insn has been output as the current
8240 frag may have been closed off. eg. by frag_var. */
8241 dwarf2_emit_insn (0);
8243 insn_start_frag
= frag_now
;
8244 insn_start_off
= frag_now_fix ();
8247 if (i
.tm
.opcode_modifier
.jump
)
8249 else if (i
.tm
.opcode_modifier
.jumpbyte
8250 || i
.tm
.opcode_modifier
.jumpdword
)
8252 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8253 output_interseg_jump ();
8256 /* Output normal instructions here. */
8260 unsigned int prefix
;
8263 && i
.tm
.base_opcode
== 0xfae
8265 && i
.imm_operands
== 1
8266 && (i
.op
[0].imms
->X_add_number
== 0xe8
8267 || i
.op
[0].imms
->X_add_number
== 0xf0
8268 || i
.op
[0].imms
->X_add_number
== 0xf8))
8270 /* Encode lfence, mfence, and sfence as
8271 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8272 offsetT val
= 0x240483f0ULL
;
8274 md_number_to_chars (p
, val
, 5);
8278 /* Some processors fail on LOCK prefix. This options makes
8279 assembler ignore LOCK prefix and serves as a workaround. */
8280 if (omit_lock_prefix
)
8282 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8284 i
.prefix
[LOCK_PREFIX
] = 0;
8287 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8288 don't need the explicit prefix. */
8289 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8291 switch (i
.tm
.opcode_length
)
8294 if (i
.tm
.base_opcode
& 0xff000000)
8296 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8297 add_prefix (prefix
);
8301 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8303 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8304 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8305 || prefix
!= REPE_PREFIX_OPCODE
8306 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8307 add_prefix (prefix
);
8313 /* Check for pseudo prefixes. */
8314 as_bad_where (insn_start_frag
->fr_file
,
8315 insn_start_frag
->fr_line
,
8316 _("pseudo prefix without instruction"));
8322 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8323 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8324 R_X86_64_GOTTPOFF relocation so that linker can safely
8325 perform IE->LE optimization. */
8326 if (x86_elf_abi
== X86_64_X32_ABI
8328 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8329 && i
.prefix
[REX_PREFIX
] == 0)
8330 add_prefix (REX_OPCODE
);
8333 /* The prefix bytes. */
8334 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8336 FRAG_APPEND_1_CHAR (*q
);
8340 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8345 /* REX byte is encoded in VEX prefix. */
8349 FRAG_APPEND_1_CHAR (*q
);
8352 /* There should be no other prefixes for instructions
8357 /* For EVEX instructions i.vrex should become 0 after
8358 build_evex_prefix. For VEX instructions upper 16 registers
8359 aren't available, so VREX should be 0. */
8362 /* Now the VEX prefix. */
8363 p
= frag_more (i
.vex
.length
);
8364 for (j
= 0; j
< i
.vex
.length
; j
++)
8365 p
[j
] = i
.vex
.bytes
[j
];
8368 /* Now the opcode; be careful about word order here! */
8369 if (i
.tm
.opcode_length
== 1)
8371 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8375 switch (i
.tm
.opcode_length
)
8379 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8380 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8384 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8394 /* Put out high byte first: can't use md_number_to_chars! */
8395 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8396 *p
= i
.tm
.base_opcode
& 0xff;
8399 /* Now the modrm byte and sib byte (if present). */
8400 if (i
.tm
.opcode_modifier
.modrm
)
8402 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8405 /* If i.rm.regmem == ESP (4)
8406 && i.rm.mode != (Register mode)
8408 ==> need second modrm byte. */
8409 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8411 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8412 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8414 | i
.sib
.scale
<< 6));
8417 if (i
.disp_operands
)
8418 output_disp (insn_start_frag
, insn_start_off
);
8421 output_imm (insn_start_frag
, insn_start_off
);
8424 * frag_now_fix () returning plain abs_section_offset when we're in the
8425 * absolute section, and abs_section_offset not getting updated as data
8426 * gets added to the frag breaks the logic below.
8428 if (now_seg
!= absolute_section
)
8430 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8432 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8440 pi ("" /*line*/, &i
);
8442 #endif /* DEBUG386 */
8445 /* Return the size of the displacement operand N. */
8448 disp_size (unsigned int n
)
8452 if (i
.types
[n
].bitfield
.disp64
)
8454 else if (i
.types
[n
].bitfield
.disp8
)
8456 else if (i
.types
[n
].bitfield
.disp16
)
8461 /* Return the size of the immediate operand N. */
8464 imm_size (unsigned int n
)
8467 if (i
.types
[n
].bitfield
.imm64
)
8469 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8471 else if (i
.types
[n
].bitfield
.imm16
)
8477 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8482 for (n
= 0; n
< i
.operands
; n
++)
8484 if (operand_type_check (i
.types
[n
], disp
))
8486 if (i
.op
[n
].disps
->X_op
== O_constant
)
8488 int size
= disp_size (n
);
8489 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8491 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8493 p
= frag_more (size
);
8494 md_number_to_chars (p
, val
, size
);
8498 enum bfd_reloc_code_real reloc_type
;
8499 int size
= disp_size (n
);
8500 int sign
= i
.types
[n
].bitfield
.disp32s
;
8501 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8504 /* We can't have 8 bit displacement here. */
8505 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8507 /* The PC relative address is computed relative
8508 to the instruction boundary, so in case immediate
8509 fields follows, we need to adjust the value. */
8510 if (pcrel
&& i
.imm_operands
)
8515 for (n1
= 0; n1
< i
.operands
; n1
++)
8516 if (operand_type_check (i
.types
[n1
], imm
))
8518 /* Only one immediate is allowed for PC
8519 relative address. */
8520 gas_assert (sz
== 0);
8522 i
.op
[n
].disps
->X_add_number
-= sz
;
8524 /* We should find the immediate. */
8525 gas_assert (sz
!= 0);
8528 p
= frag_more (size
);
8529 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8531 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8532 && (((reloc_type
== BFD_RELOC_32
8533 || reloc_type
== BFD_RELOC_X86_64_32S
8534 || (reloc_type
== BFD_RELOC_64
8536 && (i
.op
[n
].disps
->X_op
== O_symbol
8537 || (i
.op
[n
].disps
->X_op
== O_add
8538 && ((symbol_get_value_expression
8539 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8541 || reloc_type
== BFD_RELOC_32_PCREL
))
8545 reloc_type
= BFD_RELOC_386_GOTPC
;
8546 i
.op
[n
].imms
->X_add_number
+=
8547 encoding_length (insn_start_frag
, insn_start_off
, p
);
8549 else if (reloc_type
== BFD_RELOC_64
)
8550 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8552 /* Don't do the adjustment for x86-64, as there
8553 the pcrel addressing is relative to the _next_
8554 insn, and that is taken care of in other code. */
8555 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8557 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8558 size
, i
.op
[n
].disps
, pcrel
,
8560 /* Check for "call/jmp *mem", "mov mem, %reg",
8561 "test %reg, mem" and "binop mem, %reg" where binop
8562 is one of adc, add, and, cmp, or, sbb, sub, xor
8563 instructions without data prefix. Always generate
8564 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8565 if (i
.prefix
[DATA_PREFIX
] == 0
8566 && (generate_relax_relocations
8569 && i
.rm
.regmem
== 5))
8571 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8572 && ((i
.operands
== 1
8573 && i
.tm
.base_opcode
== 0xff
8574 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8576 && (i
.tm
.base_opcode
== 0x8b
8577 || i
.tm
.base_opcode
== 0x85
8578 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8582 fixP
->fx_tcbit
= i
.rex
!= 0;
8584 && (i
.base_reg
->reg_num
== RegIP
))
8585 fixP
->fx_tcbit2
= 1;
8588 fixP
->fx_tcbit2
= 1;
8596 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8601 for (n
= 0; n
< i
.operands
; n
++)
8603 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8604 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8607 if (operand_type_check (i
.types
[n
], imm
))
8609 if (i
.op
[n
].imms
->X_op
== O_constant
)
8611 int size
= imm_size (n
);
8614 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8616 p
= frag_more (size
);
8617 md_number_to_chars (p
, val
, size
);
8621 /* Not absolute_section.
8622 Need a 32-bit fixup (don't support 8bit
8623 non-absolute imms). Try to support other
8625 enum bfd_reloc_code_real reloc_type
;
8626 int size
= imm_size (n
);
8629 if (i
.types
[n
].bitfield
.imm32s
8630 && (i
.suffix
== QWORD_MNEM_SUFFIX
8631 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8636 p
= frag_more (size
);
8637 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8639 /* This is tough to explain. We end up with this one if we
8640 * have operands that look like
8641 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8642 * obtain the absolute address of the GOT, and it is strongly
8643 * preferable from a performance point of view to avoid using
8644 * a runtime relocation for this. The actual sequence of
8645 * instructions often look something like:
8650 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8652 * The call and pop essentially return the absolute address
8653 * of the label .L66 and store it in %ebx. The linker itself
8654 * will ultimately change the first operand of the addl so
8655 * that %ebx points to the GOT, but to keep things simple, the
8656 * .o file must have this operand set so that it generates not
8657 * the absolute address of .L66, but the absolute address of
8658 * itself. This allows the linker itself simply treat a GOTPC
8659 * relocation as asking for a pcrel offset to the GOT to be
8660 * added in, and the addend of the relocation is stored in the
8661 * operand field for the instruction itself.
8663 * Our job here is to fix the operand so that it would add
8664 * the correct offset so that %ebx would point to itself. The
8665 * thing that is tricky is that .-.L66 will point to the
8666 * beginning of the instruction, so we need to further modify
8667 * the operand so that it will point to itself. There are
8668 * other cases where you have something like:
8670 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8672 * and here no correction would be required. Internally in
8673 * the assembler we treat operands of this form as not being
8674 * pcrel since the '.' is explicitly mentioned, and I wonder
8675 * whether it would simplify matters to do it this way. Who
8676 * knows. In earlier versions of the PIC patches, the
8677 * pcrel_adjust field was used to store the correction, but
8678 * since the expression is not pcrel, I felt it would be
8679 * confusing to do it this way. */
8681 if ((reloc_type
== BFD_RELOC_32
8682 || reloc_type
== BFD_RELOC_X86_64_32S
8683 || reloc_type
== BFD_RELOC_64
)
8685 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8686 && (i
.op
[n
].imms
->X_op
== O_symbol
8687 || (i
.op
[n
].imms
->X_op
== O_add
8688 && ((symbol_get_value_expression
8689 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8693 reloc_type
= BFD_RELOC_386_GOTPC
;
8695 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8697 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8698 i
.op
[n
].imms
->X_add_number
+=
8699 encoding_length (insn_start_frag
, insn_start_off
, p
);
8701 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8702 i
.op
[n
].imms
, 0, reloc_type
);
8708 /* x86_cons_fix_new is called via the expression parsing code when a
8709 reloc is needed. We use this hook to get the correct .got reloc. */
8710 static int cons_sign
= -1;
8713 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8714 expressionS
*exp
, bfd_reloc_code_real_type r
)
8716 r
= reloc (len
, 0, cons_sign
, r
);
8719 if (exp
->X_op
== O_secrel
)
8721 exp
->X_op
= O_symbol
;
8722 r
= BFD_RELOC_32_SECREL
;
8726 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8729 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8730 purpose of the `.dc.a' internal pseudo-op. */
8733 x86_address_bytes (void)
8735 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8737 return stdoutput
->arch_info
->bits_per_address
/ 8;
8740 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8742 # define lex_got(reloc, adjust, types) NULL
8744 /* Parse operands of the form
8745 <symbol>@GOTOFF+<nnn>
8746 and similar .plt or .got references.
8748 If we find one, set up the correct relocation in RELOC and copy the
8749 input string, minus the `@GOTOFF' into a malloc'd buffer for
8750 parsing by the calling routine. Return this buffer, and if ADJUST
8751 is non-null set it to the length of the string we removed from the
8752 input line. Otherwise return NULL. */
8754 lex_got (enum bfd_reloc_code_real
*rel
,
8756 i386_operand_type
*types
)
8758 /* Some of the relocations depend on the size of what field is to
8759 be relocated. But in our callers i386_immediate and i386_displacement
8760 we don't yet know the operand size (this will be set by insn
8761 matching). Hence we record the word32 relocation here,
8762 and adjust the reloc according to the real size in reloc(). */
8763 static const struct {
8766 const enum bfd_reloc_code_real rel
[2];
8767 const i386_operand_type types64
;
8769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8770 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8772 OPERAND_TYPE_IMM32_64
},
8774 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8775 BFD_RELOC_X86_64_PLTOFF64
},
8776 OPERAND_TYPE_IMM64
},
8777 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8778 BFD_RELOC_X86_64_PLT32
},
8779 OPERAND_TYPE_IMM32_32S_DISP32
},
8780 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8781 BFD_RELOC_X86_64_GOTPLT64
},
8782 OPERAND_TYPE_IMM64_DISP64
},
8783 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8784 BFD_RELOC_X86_64_GOTOFF64
},
8785 OPERAND_TYPE_IMM64_DISP64
},
8786 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8787 BFD_RELOC_X86_64_GOTPCREL
},
8788 OPERAND_TYPE_IMM32_32S_DISP32
},
8789 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8790 BFD_RELOC_X86_64_TLSGD
},
8791 OPERAND_TYPE_IMM32_32S_DISP32
},
8792 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8793 _dummy_first_bfd_reloc_code_real
},
8794 OPERAND_TYPE_NONE
},
8795 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8796 BFD_RELOC_X86_64_TLSLD
},
8797 OPERAND_TYPE_IMM32_32S_DISP32
},
8798 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8799 BFD_RELOC_X86_64_GOTTPOFF
},
8800 OPERAND_TYPE_IMM32_32S_DISP32
},
8801 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8802 BFD_RELOC_X86_64_TPOFF32
},
8803 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8804 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8805 _dummy_first_bfd_reloc_code_real
},
8806 OPERAND_TYPE_NONE
},
8807 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8808 BFD_RELOC_X86_64_DTPOFF32
},
8809 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8810 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8811 _dummy_first_bfd_reloc_code_real
},
8812 OPERAND_TYPE_NONE
},
8813 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8814 _dummy_first_bfd_reloc_code_real
},
8815 OPERAND_TYPE_NONE
},
8816 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8817 BFD_RELOC_X86_64_GOT32
},
8818 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8819 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8820 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8821 OPERAND_TYPE_IMM32_32S_DISP32
},
8822 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8823 BFD_RELOC_X86_64_TLSDESC_CALL
},
8824 OPERAND_TYPE_IMM32_32S_DISP32
},
8829 #if defined (OBJ_MAYBE_ELF)
8834 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8835 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8838 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8840 int len
= gotrel
[j
].len
;
8841 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8843 if (gotrel
[j
].rel
[object_64bit
] != 0)
8846 char *tmpbuf
, *past_reloc
;
8848 *rel
= gotrel
[j
].rel
[object_64bit
];
8852 if (flag_code
!= CODE_64BIT
)
8854 types
->bitfield
.imm32
= 1;
8855 types
->bitfield
.disp32
= 1;
8858 *types
= gotrel
[j
].types64
;
8861 if (j
!= 0 && GOT_symbol
== NULL
)
8862 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8864 /* The length of the first part of our input line. */
8865 first
= cp
- input_line_pointer
;
8867 /* The second part goes from after the reloc token until
8868 (and including) an end_of_line char or comma. */
8869 past_reloc
= cp
+ 1 + len
;
8871 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8873 second
= cp
+ 1 - past_reloc
;
8875 /* Allocate and copy string. The trailing NUL shouldn't
8876 be necessary, but be safe. */
8877 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8878 memcpy (tmpbuf
, input_line_pointer
, first
);
8879 if (second
!= 0 && *past_reloc
!= ' ')
8880 /* Replace the relocation token with ' ', so that
8881 errors like foo@GOTOFF1 will be detected. */
8882 tmpbuf
[first
++] = ' ';
8884 /* Increment length by 1 if the relocation token is
8889 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8890 tmpbuf
[first
+ second
] = '\0';
8894 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8895 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8900 /* Might be a symbol version string. Don't as_bad here. */
8909 /* Parse operands of the form
8910 <symbol>@SECREL32+<nnn>
8912 If we find one, set up the correct relocation in RELOC and copy the
8913 input string, minus the `@SECREL32' into a malloc'd buffer for
8914 parsing by the calling routine. Return this buffer, and if ADJUST
8915 is non-null set it to the length of the string we removed from the
8916 input line. Otherwise return NULL.
8918 This function is copied from the ELF version above adjusted for PE targets. */
8921 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8922 int *adjust ATTRIBUTE_UNUSED
,
8923 i386_operand_type
*types
)
8929 const enum bfd_reloc_code_real rel
[2];
8930 const i386_operand_type types64
;
8934 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8935 BFD_RELOC_32_SECREL
},
8936 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8942 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8943 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8946 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8948 int len
= gotrel
[j
].len
;
8950 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8952 if (gotrel
[j
].rel
[object_64bit
] != 0)
8955 char *tmpbuf
, *past_reloc
;
8957 *rel
= gotrel
[j
].rel
[object_64bit
];
8963 if (flag_code
!= CODE_64BIT
)
8965 types
->bitfield
.imm32
= 1;
8966 types
->bitfield
.disp32
= 1;
8969 *types
= gotrel
[j
].types64
;
8972 /* The length of the first part of our input line. */
8973 first
= cp
- input_line_pointer
;
8975 /* The second part goes from after the reloc token until
8976 (and including) an end_of_line char or comma. */
8977 past_reloc
= cp
+ 1 + len
;
8979 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8981 second
= cp
+ 1 - past_reloc
;
8983 /* Allocate and copy string. The trailing NUL shouldn't
8984 be necessary, but be safe. */
8985 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8986 memcpy (tmpbuf
, input_line_pointer
, first
);
8987 if (second
!= 0 && *past_reloc
!= ' ')
8988 /* Replace the relocation token with ' ', so that
8989 errors like foo@SECLREL321 will be detected. */
8990 tmpbuf
[first
++] = ' ';
8991 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8992 tmpbuf
[first
+ second
] = '\0';
8996 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8997 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9002 /* Might be a symbol version string. Don't as_bad here. */
9008 bfd_reloc_code_real_type
9009 x86_cons (expressionS
*exp
, int size
)
9011 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9013 intel_syntax
= -intel_syntax
;
9016 if (size
== 4 || (object_64bit
&& size
== 8))
9018 /* Handle @GOTOFF and the like in an expression. */
9020 char *gotfree_input_line
;
9023 save
= input_line_pointer
;
9024 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9025 if (gotfree_input_line
)
9026 input_line_pointer
= gotfree_input_line
;
9030 if (gotfree_input_line
)
9032 /* expression () has merrily parsed up to the end of line,
9033 or a comma - in the wrong buffer. Transfer how far
9034 input_line_pointer has moved to the right buffer. */
9035 input_line_pointer
= (save
9036 + (input_line_pointer
- gotfree_input_line
)
9038 free (gotfree_input_line
);
9039 if (exp
->X_op
== O_constant
9040 || exp
->X_op
== O_absent
9041 || exp
->X_op
== O_illegal
9042 || exp
->X_op
== O_register
9043 || exp
->X_op
== O_big
)
9045 char c
= *input_line_pointer
;
9046 *input_line_pointer
= 0;
9047 as_bad (_("missing or invalid expression `%s'"), save
);
9048 *input_line_pointer
= c
;
9050 else if ((got_reloc
== BFD_RELOC_386_PLT32
9051 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9052 && exp
->X_op
!= O_symbol
)
9054 char c
= *input_line_pointer
;
9055 *input_line_pointer
= 0;
9056 as_bad (_("invalid PLT expression `%s'"), save
);
9057 *input_line_pointer
= c
;
9064 intel_syntax
= -intel_syntax
;
9067 i386_intel_simplify (exp
);
9073 signed_cons (int size
)
9075 if (flag_code
== CODE_64BIT
)
9083 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9090 if (exp
.X_op
== O_symbol
)
9091 exp
.X_op
= O_secrel
;
9093 emit_expr (&exp
, 4);
9095 while (*input_line_pointer
++ == ',');
9097 input_line_pointer
--;
9098 demand_empty_rest_of_line ();
9102 /* Handle Vector operations. */
9105 check_VecOperations (char *op_string
, char *op_end
)
9107 const reg_entry
*mask
;
9112 && (op_end
== NULL
|| op_string
< op_end
))
9115 if (*op_string
== '{')
9119 /* Check broadcasts. */
9120 if (strncmp (op_string
, "1to", 3) == 0)
9125 goto duplicated_vec_op
;
9128 if (*op_string
== '8')
9130 else if (*op_string
== '4')
9132 else if (*op_string
== '2')
9134 else if (*op_string
== '1'
9135 && *(op_string
+1) == '6')
9142 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9147 broadcast_op
.type
= bcst_type
;
9148 broadcast_op
.operand
= this_operand
;
9149 broadcast_op
.bytes
= 0;
9150 i
.broadcast
= &broadcast_op
;
9152 /* Check masking operation. */
9153 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9155 /* k0 can't be used for write mask. */
9156 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9158 as_bad (_("`%s%s' can't be used for write mask"),
9159 register_prefix
, mask
->reg_name
);
9165 mask_op
.mask
= mask
;
9166 mask_op
.zeroing
= 0;
9167 mask_op
.operand
= this_operand
;
9173 goto duplicated_vec_op
;
9175 i
.mask
->mask
= mask
;
9177 /* Only "{z}" is allowed here. No need to check
9178 zeroing mask explicitly. */
9179 if (i
.mask
->operand
!= this_operand
)
9181 as_bad (_("invalid write mask `%s'"), saved
);
9188 /* Check zeroing-flag for masking operation. */
9189 else if (*op_string
== 'z')
9193 mask_op
.mask
= NULL
;
9194 mask_op
.zeroing
= 1;
9195 mask_op
.operand
= this_operand
;
9200 if (i
.mask
->zeroing
)
9203 as_bad (_("duplicated `%s'"), saved
);
9207 i
.mask
->zeroing
= 1;
9209 /* Only "{%k}" is allowed here. No need to check mask
9210 register explicitly. */
9211 if (i
.mask
->operand
!= this_operand
)
9213 as_bad (_("invalid zeroing-masking `%s'"),
9222 goto unknown_vec_op
;
9224 if (*op_string
!= '}')
9226 as_bad (_("missing `}' in `%s'"), saved
);
9231 /* Strip whitespace since the addition of pseudo prefixes
9232 changed how the scrubber treats '{'. */
9233 if (is_space_char (*op_string
))
9239 /* We don't know this one. */
9240 as_bad (_("unknown vector operation: `%s'"), saved
);
9244 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9246 as_bad (_("zeroing-masking only allowed with write mask"));
9254 i386_immediate (char *imm_start
)
9256 char *save_input_line_pointer
;
9257 char *gotfree_input_line
;
9260 i386_operand_type types
;
9262 operand_type_set (&types
, ~0);
9264 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9266 as_bad (_("at most %d immediate operands are allowed"),
9267 MAX_IMMEDIATE_OPERANDS
);
9271 exp
= &im_expressions
[i
.imm_operands
++];
9272 i
.op
[this_operand
].imms
= exp
;
9274 if (is_space_char (*imm_start
))
9277 save_input_line_pointer
= input_line_pointer
;
9278 input_line_pointer
= imm_start
;
9280 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9281 if (gotfree_input_line
)
9282 input_line_pointer
= gotfree_input_line
;
9284 exp_seg
= expression (exp
);
9288 /* Handle vector operations. */
9289 if (*input_line_pointer
== '{')
9291 input_line_pointer
= check_VecOperations (input_line_pointer
,
9293 if (input_line_pointer
== NULL
)
9297 if (*input_line_pointer
)
9298 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9300 input_line_pointer
= save_input_line_pointer
;
9301 if (gotfree_input_line
)
9303 free (gotfree_input_line
);
9305 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9306 exp
->X_op
= O_illegal
;
9309 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9313 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9314 i386_operand_type types
, const char *imm_start
)
9316 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9319 as_bad (_("missing or invalid immediate expression `%s'"),
9323 else if (exp
->X_op
== O_constant
)
9325 /* Size it properly later. */
9326 i
.types
[this_operand
].bitfield
.imm64
= 1;
9327 /* If not 64bit, sign extend val. */
9328 if (flag_code
!= CODE_64BIT
9329 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9331 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9333 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9334 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9335 && exp_seg
!= absolute_section
9336 && exp_seg
!= text_section
9337 && exp_seg
!= data_section
9338 && exp_seg
!= bss_section
9339 && exp_seg
!= undefined_section
9340 && !bfd_is_com_section (exp_seg
))
9342 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9346 else if (!intel_syntax
&& exp_seg
== reg_section
)
9349 as_bad (_("illegal immediate register operand %s"), imm_start
);
9354 /* This is an address. The size of the address will be
9355 determined later, depending on destination register,
9356 suffix, or the default for the section. */
9357 i
.types
[this_operand
].bitfield
.imm8
= 1;
9358 i
.types
[this_operand
].bitfield
.imm16
= 1;
9359 i
.types
[this_operand
].bitfield
.imm32
= 1;
9360 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9361 i
.types
[this_operand
].bitfield
.imm64
= 1;
9362 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9370 i386_scale (char *scale
)
9373 char *save
= input_line_pointer
;
9375 input_line_pointer
= scale
;
9376 val
= get_absolute_expression ();
9381 i
.log2_scale_factor
= 0;
9384 i
.log2_scale_factor
= 1;
9387 i
.log2_scale_factor
= 2;
9390 i
.log2_scale_factor
= 3;
9394 char sep
= *input_line_pointer
;
9396 *input_line_pointer
= '\0';
9397 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9399 *input_line_pointer
= sep
;
9400 input_line_pointer
= save
;
9404 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9406 as_warn (_("scale factor of %d without an index register"),
9407 1 << i
.log2_scale_factor
);
9408 i
.log2_scale_factor
= 0;
9410 scale
= input_line_pointer
;
9411 input_line_pointer
= save
;
9416 i386_displacement (char *disp_start
, char *disp_end
)
9420 char *save_input_line_pointer
;
9421 char *gotfree_input_line
;
9423 i386_operand_type bigdisp
, types
= anydisp
;
9426 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9428 as_bad (_("at most %d displacement operands are allowed"),
9429 MAX_MEMORY_OPERANDS
);
9433 operand_type_set (&bigdisp
, 0);
9434 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9435 || (!current_templates
->start
->opcode_modifier
.jump
9436 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9438 bigdisp
.bitfield
.disp32
= 1;
9439 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9440 if (flag_code
== CODE_64BIT
)
9444 bigdisp
.bitfield
.disp32s
= 1;
9445 bigdisp
.bitfield
.disp64
= 1;
9448 else if ((flag_code
== CODE_16BIT
) ^ override
)
9450 bigdisp
.bitfield
.disp32
= 0;
9451 bigdisp
.bitfield
.disp16
= 1;
9456 /* For PC-relative branches, the width of the displacement
9457 is dependent upon data size, not address size. */
9458 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9459 if (flag_code
== CODE_64BIT
)
9461 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9462 bigdisp
.bitfield
.disp16
= 1;
9465 bigdisp
.bitfield
.disp32
= 1;
9466 bigdisp
.bitfield
.disp32s
= 1;
9472 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9474 : LONG_MNEM_SUFFIX
));
9475 bigdisp
.bitfield
.disp32
= 1;
9476 if ((flag_code
== CODE_16BIT
) ^ override
)
9478 bigdisp
.bitfield
.disp32
= 0;
9479 bigdisp
.bitfield
.disp16
= 1;
9483 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9486 exp
= &disp_expressions
[i
.disp_operands
];
9487 i
.op
[this_operand
].disps
= exp
;
9489 save_input_line_pointer
= input_line_pointer
;
9490 input_line_pointer
= disp_start
;
9491 END_STRING_AND_SAVE (disp_end
);
9493 #ifndef GCC_ASM_O_HACK
9494 #define GCC_ASM_O_HACK 0
9497 END_STRING_AND_SAVE (disp_end
+ 1);
9498 if (i
.types
[this_operand
].bitfield
.baseIndex
9499 && displacement_string_end
[-1] == '+')
9501 /* This hack is to avoid a warning when using the "o"
9502 constraint within gcc asm statements.
9505 #define _set_tssldt_desc(n,addr,limit,type) \
9506 __asm__ __volatile__ ( \
9508 "movw %w1,2+%0\n\t" \
9510 "movb %b1,4+%0\n\t" \
9511 "movb %4,5+%0\n\t" \
9512 "movb $0,6+%0\n\t" \
9513 "movb %h1,7+%0\n\t" \
9515 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9517 This works great except that the output assembler ends
9518 up looking a bit weird if it turns out that there is
9519 no offset. You end up producing code that looks like:
9532 So here we provide the missing zero. */
9534 *displacement_string_end
= '0';
9537 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9538 if (gotfree_input_line
)
9539 input_line_pointer
= gotfree_input_line
;
9541 exp_seg
= expression (exp
);
9544 if (*input_line_pointer
)
9545 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9547 RESTORE_END_STRING (disp_end
+ 1);
9549 input_line_pointer
= save_input_line_pointer
;
9550 if (gotfree_input_line
)
9552 free (gotfree_input_line
);
9554 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9555 exp
->X_op
= O_illegal
;
9558 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9560 RESTORE_END_STRING (disp_end
);
9566 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9567 i386_operand_type types
, const char *disp_start
)
9569 i386_operand_type bigdisp
;
9572 /* We do this to make sure that the section symbol is in
9573 the symbol table. We will ultimately change the relocation
9574 to be relative to the beginning of the section. */
9575 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9576 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9577 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9579 if (exp
->X_op
!= O_symbol
)
9582 if (S_IS_LOCAL (exp
->X_add_symbol
)
9583 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9584 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9585 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9586 exp
->X_op
= O_subtract
;
9587 exp
->X_op_symbol
= GOT_symbol
;
9588 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9589 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9590 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9591 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9593 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9596 else if (exp
->X_op
== O_absent
9597 || exp
->X_op
== O_illegal
9598 || exp
->X_op
== O_big
)
9601 as_bad (_("missing or invalid displacement expression `%s'"),
9606 else if (flag_code
== CODE_64BIT
9607 && !i
.prefix
[ADDR_PREFIX
]
9608 && exp
->X_op
== O_constant
)
9610 /* Since displacement is signed extended to 64bit, don't allow
9611 disp32 and turn off disp32s if they are out of range. */
9612 i
.types
[this_operand
].bitfield
.disp32
= 0;
9613 if (!fits_in_signed_long (exp
->X_add_number
))
9615 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9616 if (i
.types
[this_operand
].bitfield
.baseindex
)
9618 as_bad (_("0x%lx out range of signed 32bit displacement"),
9619 (long) exp
->X_add_number
);
9625 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9626 else if (exp
->X_op
!= O_constant
9627 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9628 && exp_seg
!= absolute_section
9629 && exp_seg
!= text_section
9630 && exp_seg
!= data_section
9631 && exp_seg
!= bss_section
9632 && exp_seg
!= undefined_section
9633 && !bfd_is_com_section (exp_seg
))
9635 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9640 /* Check if this is a displacement only operand. */
9641 bigdisp
= i
.types
[this_operand
];
9642 bigdisp
.bitfield
.disp8
= 0;
9643 bigdisp
.bitfield
.disp16
= 0;
9644 bigdisp
.bitfield
.disp32
= 0;
9645 bigdisp
.bitfield
.disp32s
= 0;
9646 bigdisp
.bitfield
.disp64
= 0;
9647 if (operand_type_all_zero (&bigdisp
))
9648 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9654 /* Return the active addressing mode, taking address override and
9655 registers forming the address into consideration. Update the
9656 address override prefix if necessary. */
9658 static enum flag_code
9659 i386_addressing_mode (void)
9661 enum flag_code addr_mode
;
9663 if (i
.prefix
[ADDR_PREFIX
])
9664 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9667 addr_mode
= flag_code
;
9669 #if INFER_ADDR_PREFIX
9670 if (i
.mem_operands
== 0)
9672 /* Infer address prefix from the first memory operand. */
9673 const reg_entry
*addr_reg
= i
.base_reg
;
9675 if (addr_reg
== NULL
)
9676 addr_reg
= i
.index_reg
;
9680 if (addr_reg
->reg_type
.bitfield
.dword
)
9681 addr_mode
= CODE_32BIT
;
9682 else if (flag_code
!= CODE_64BIT
9683 && addr_reg
->reg_type
.bitfield
.word
)
9684 addr_mode
= CODE_16BIT
;
9686 if (addr_mode
!= flag_code
)
9688 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9690 /* Change the size of any displacement too. At most one
9691 of Disp16 or Disp32 is set.
9692 FIXME. There doesn't seem to be any real need for
9693 separate Disp16 and Disp32 flags. The same goes for
9694 Imm16 and Imm32. Removing them would probably clean
9695 up the code quite a lot. */
9696 if (flag_code
!= CODE_64BIT
9697 && (i
.types
[this_operand
].bitfield
.disp16
9698 || i
.types
[this_operand
].bitfield
.disp32
))
9699 i
.types
[this_operand
]
9700 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9710 /* Make sure the memory operand we've been dealt is valid.
9711 Return 1 on success, 0 on a failure. */
9714 i386_index_check (const char *operand_string
)
9716 const char *kind
= "base/index";
9717 enum flag_code addr_mode
= i386_addressing_mode ();
9719 if (current_templates
->start
->opcode_modifier
.isstring
9720 && !current_templates
->start
->opcode_modifier
.immext
9721 && (current_templates
->end
[-1].opcode_modifier
.isstring
9724 /* Memory operands of string insns are special in that they only allow
9725 a single register (rDI, rSI, or rBX) as their memory address. */
9726 const reg_entry
*expected_reg
;
9727 static const char *di_si
[][2] =
9733 static const char *bx
[] = { "ebx", "bx", "rbx" };
9735 kind
= "string address";
9737 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9739 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9741 if (!type
.bitfield
.baseindex
9742 || ((!i
.mem_operands
!= !intel_syntax
)
9743 && current_templates
->end
[-1].operand_types
[1]
9744 .bitfield
.baseindex
))
9745 type
= current_templates
->end
[-1].operand_types
[1];
9746 expected_reg
= hash_find (reg_hash
,
9747 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9751 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9753 if (i
.base_reg
!= expected_reg
9755 || operand_type_check (i
.types
[this_operand
], disp
))
9757 /* The second memory operand must have the same size as
9761 && !((addr_mode
== CODE_64BIT
9762 && i
.base_reg
->reg_type
.bitfield
.qword
)
9763 || (addr_mode
== CODE_32BIT
9764 ? i
.base_reg
->reg_type
.bitfield
.dword
9765 : i
.base_reg
->reg_type
.bitfield
.word
)))
9768 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9770 intel_syntax
? '[' : '(',
9772 expected_reg
->reg_name
,
9773 intel_syntax
? ']' : ')');
9780 as_bad (_("`%s' is not a valid %s expression"),
9781 operand_string
, kind
);
9786 if (addr_mode
!= CODE_16BIT
)
9788 /* 32-bit/64-bit checks. */
9790 && ((addr_mode
== CODE_64BIT
9791 ? !i
.base_reg
->reg_type
.bitfield
.qword
9792 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9793 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9794 || i
.base_reg
->reg_num
== RegIZ
))
9796 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9797 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9798 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9799 && ((addr_mode
== CODE_64BIT
9800 ? !i
.index_reg
->reg_type
.bitfield
.qword
9801 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9802 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9805 /* bndmk, bndldx, and bndstx have special restrictions. */
9806 if (current_templates
->start
->base_opcode
== 0xf30f1b
9807 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9809 /* They cannot use RIP-relative addressing. */
9810 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9812 as_bad (_("`%s' cannot be used here"), operand_string
);
9816 /* bndldx and bndstx ignore their scale factor. */
9817 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9818 && i
.log2_scale_factor
)
9819 as_warn (_("register scaling is being ignored here"));
9824 /* 16-bit checks. */
9826 && (!i
.base_reg
->reg_type
.bitfield
.word
9827 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9829 && (!i
.index_reg
->reg_type
.bitfield
.word
9830 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9832 && i
.base_reg
->reg_num
< 6
9833 && i
.index_reg
->reg_num
>= 6
9834 && i
.log2_scale_factor
== 0))))
9841 /* Handle vector immediates. */
9844 RC_SAE_immediate (const char *imm_start
)
9846 unsigned int match_found
, j
;
9847 const char *pstr
= imm_start
;
9855 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9857 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9861 rc_op
.type
= RC_NamesTable
[j
].type
;
9862 rc_op
.operand
= this_operand
;
9863 i
.rounding
= &rc_op
;
9867 as_bad (_("duplicated `%s'"), imm_start
);
9870 pstr
+= RC_NamesTable
[j
].len
;
9880 as_bad (_("Missing '}': '%s'"), imm_start
);
9883 /* RC/SAE immediate string should contain nothing more. */;
9886 as_bad (_("Junk after '}': '%s'"), imm_start
);
9890 exp
= &im_expressions
[i
.imm_operands
++];
9891 i
.op
[this_operand
].imms
= exp
;
9893 exp
->X_op
= O_constant
;
9894 exp
->X_add_number
= 0;
9895 exp
->X_add_symbol
= (symbolS
*) 0;
9896 exp
->X_op_symbol
= (symbolS
*) 0;
9898 i
.types
[this_operand
].bitfield
.imm8
= 1;
9902 /* Only string instructions can have a second memory operand, so
9903 reduce current_templates to just those if it contains any. */
9905 maybe_adjust_templates (void)
9907 const insn_template
*t
;
9909 gas_assert (i
.mem_operands
== 1);
9911 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9912 if (t
->opcode_modifier
.isstring
)
9915 if (t
< current_templates
->end
)
9917 static templates aux_templates
;
9918 bfd_boolean recheck
;
9920 aux_templates
.start
= t
;
9921 for (; t
< current_templates
->end
; ++t
)
9922 if (!t
->opcode_modifier
.isstring
)
9924 aux_templates
.end
= t
;
9926 /* Determine whether to re-check the first memory operand. */
9927 recheck
= (aux_templates
.start
!= current_templates
->start
9928 || t
!= current_templates
->end
);
9930 current_templates
= &aux_templates
;
9935 if (i
.memop1_string
!= NULL
9936 && i386_index_check (i
.memop1_string
) == 0)
9945 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9949 i386_att_operand (char *operand_string
)
9953 char *op_string
= operand_string
;
9955 if (is_space_char (*op_string
))
9958 /* We check for an absolute prefix (differentiating,
9959 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9960 if (*op_string
== ABSOLUTE_PREFIX
)
9963 if (is_space_char (*op_string
))
9965 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9968 /* Check if operand is a register. */
9969 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9971 i386_operand_type temp
;
9973 /* Check for a segment override by searching for ':' after a
9974 segment register. */
9976 if (is_space_char (*op_string
))
9978 if (*op_string
== ':'
9979 && (r
->reg_type
.bitfield
.sreg2
9980 || r
->reg_type
.bitfield
.sreg3
))
9985 i
.seg
[i
.mem_operands
] = &es
;
9988 i
.seg
[i
.mem_operands
] = &cs
;
9991 i
.seg
[i
.mem_operands
] = &ss
;
9994 i
.seg
[i
.mem_operands
] = &ds
;
9997 i
.seg
[i
.mem_operands
] = &fs
;
10000 i
.seg
[i
.mem_operands
] = &gs
;
10004 /* Skip the ':' and whitespace. */
10006 if (is_space_char (*op_string
))
10009 if (!is_digit_char (*op_string
)
10010 && !is_identifier_char (*op_string
)
10011 && *op_string
!= '('
10012 && *op_string
!= ABSOLUTE_PREFIX
)
10014 as_bad (_("bad memory operand `%s'"), op_string
);
10017 /* Handle case of %es:*foo. */
10018 if (*op_string
== ABSOLUTE_PREFIX
)
10021 if (is_space_char (*op_string
))
10023 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10025 goto do_memory_reference
;
10028 /* Handle vector operations. */
10029 if (*op_string
== '{')
10031 op_string
= check_VecOperations (op_string
, NULL
);
10032 if (op_string
== NULL
)
10038 as_bad (_("junk `%s' after register"), op_string
);
10041 temp
= r
->reg_type
;
10042 temp
.bitfield
.baseindex
= 0;
10043 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10045 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10046 i
.op
[this_operand
].regs
= r
;
10049 else if (*op_string
== REGISTER_PREFIX
)
10051 as_bad (_("bad register name `%s'"), op_string
);
10054 else if (*op_string
== IMMEDIATE_PREFIX
)
10057 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10059 as_bad (_("immediate operand illegal with absolute jump"));
10062 if (!i386_immediate (op_string
))
10065 else if (RC_SAE_immediate (operand_string
))
10067 /* If it is a RC or SAE immediate, do nothing. */
10070 else if (is_digit_char (*op_string
)
10071 || is_identifier_char (*op_string
)
10072 || *op_string
== '"'
10073 || *op_string
== '(')
10075 /* This is a memory reference of some sort. */
10078 /* Start and end of displacement string expression (if found). */
10079 char *displacement_string_start
;
10080 char *displacement_string_end
;
10083 do_memory_reference
:
10084 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10086 if ((i
.mem_operands
== 1
10087 && !current_templates
->start
->opcode_modifier
.isstring
)
10088 || i
.mem_operands
== 2)
10090 as_bad (_("too many memory references for `%s'"),
10091 current_templates
->start
->name
);
10095 /* Check for base index form. We detect the base index form by
10096 looking for an ')' at the end of the operand, searching
10097 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10099 base_string
= op_string
+ strlen (op_string
);
10101 /* Handle vector operations. */
10102 vop_start
= strchr (op_string
, '{');
10103 if (vop_start
&& vop_start
< base_string
)
10105 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10107 base_string
= vop_start
;
10111 if (is_space_char (*base_string
))
10114 /* If we only have a displacement, set-up for it to be parsed later. */
10115 displacement_string_start
= op_string
;
10116 displacement_string_end
= base_string
+ 1;
10118 if (*base_string
== ')')
10121 unsigned int parens_balanced
= 1;
10122 /* We've already checked that the number of left & right ()'s are
10123 equal, so this loop will not be infinite. */
10127 if (*base_string
== ')')
10129 if (*base_string
== '(')
10132 while (parens_balanced
);
10134 temp_string
= base_string
;
10136 /* Skip past '(' and whitespace. */
10138 if (is_space_char (*base_string
))
10141 if (*base_string
== ','
10142 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10145 displacement_string_end
= temp_string
;
10147 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10151 base_string
= end_op
;
10152 if (is_space_char (*base_string
))
10156 /* There may be an index reg or scale factor here. */
10157 if (*base_string
== ',')
10160 if (is_space_char (*base_string
))
10163 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10166 base_string
= end_op
;
10167 if (is_space_char (*base_string
))
10169 if (*base_string
== ',')
10172 if (is_space_char (*base_string
))
10175 else if (*base_string
!= ')')
10177 as_bad (_("expecting `,' or `)' "
10178 "after index register in `%s'"),
10183 else if (*base_string
== REGISTER_PREFIX
)
10185 end_op
= strchr (base_string
, ',');
10188 as_bad (_("bad register name `%s'"), base_string
);
10192 /* Check for scale factor. */
10193 if (*base_string
!= ')')
10195 char *end_scale
= i386_scale (base_string
);
10200 base_string
= end_scale
;
10201 if (is_space_char (*base_string
))
10203 if (*base_string
!= ')')
10205 as_bad (_("expecting `)' "
10206 "after scale factor in `%s'"),
10211 else if (!i
.index_reg
)
10213 as_bad (_("expecting index register or scale factor "
10214 "after `,'; got '%c'"),
10219 else if (*base_string
!= ')')
10221 as_bad (_("expecting `,' or `)' "
10222 "after base register in `%s'"),
10227 else if (*base_string
== REGISTER_PREFIX
)
10229 end_op
= strchr (base_string
, ',');
10232 as_bad (_("bad register name `%s'"), base_string
);
10237 /* If there's an expression beginning the operand, parse it,
10238 assuming displacement_string_start and
10239 displacement_string_end are meaningful. */
10240 if (displacement_string_start
!= displacement_string_end
)
10242 if (!i386_displacement (displacement_string_start
,
10243 displacement_string_end
))
10247 /* Special case for (%dx) while doing input/output op. */
10249 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10250 && i
.index_reg
== 0
10251 && i
.log2_scale_factor
== 0
10252 && i
.seg
[i
.mem_operands
] == 0
10253 && !operand_type_check (i
.types
[this_operand
], disp
))
10255 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10259 if (i386_index_check (operand_string
) == 0)
10261 i
.flags
[this_operand
] |= Operand_Mem
;
10262 if (i
.mem_operands
== 0)
10263 i
.memop1_string
= xstrdup (operand_string
);
10268 /* It's not a memory operand; argh! */
10269 as_bad (_("invalid char %s beginning operand %d `%s'"),
10270 output_invalid (*op_string
),
10275 return 1; /* Normal return. */
10278 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10279 that an rs_machine_dependent frag may reach. */
10282 i386_frag_max_var (fragS
*frag
)
10284 /* The only relaxable frags are for jumps.
10285 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10286 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10287 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10292 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10294 /* STT_GNU_IFUNC symbol must go through PLT. */
10295 if ((symbol_get_bfdsym (fr_symbol
)->flags
10296 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10299 if (!S_IS_EXTERNAL (fr_symbol
))
10300 /* Symbol may be weak or local. */
10301 return !S_IS_WEAK (fr_symbol
);
10303 /* Global symbols with non-default visibility can't be preempted. */
10304 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10307 if (fr_var
!= NO_RELOC
)
10308 switch ((enum bfd_reloc_code_real
) fr_var
)
10310 case BFD_RELOC_386_PLT32
:
10311 case BFD_RELOC_X86_64_PLT32
:
10312 /* Symbol with PLT relocation may be preempted. */
10318 /* Global symbols with default visibility in a shared library may be
10319 preempted by another definition. */
10324 /* md_estimate_size_before_relax()
10326 Called just before relax() for rs_machine_dependent frags. The x86
10327 assembler uses these frags to handle variable size jump
10330 Any symbol that is now undefined will not become defined.
10331 Return the correct fr_subtype in the frag.
10332 Return the initial "guess for variable size of frag" to caller.
10333 The guess is actually the growth beyond the fixed part. Whatever
10334 we do to grow the fixed or variable part contributes to our
10338 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10340 /* We've already got fragP->fr_subtype right; all we have to do is
10341 check for un-relaxable symbols. On an ELF system, we can't relax
10342 an externally visible symbol, because it may be overridden by a
10344 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10347 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10350 #if defined (OBJ_COFF) && defined (TE_PE)
10351 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10352 && S_IS_WEAK (fragP
->fr_symbol
))
10356 /* Symbol is undefined in this segment, or we need to keep a
10357 reloc so that weak symbols can be overridden. */
10358 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10359 enum bfd_reloc_code_real reloc_type
;
10360 unsigned char *opcode
;
10363 if (fragP
->fr_var
!= NO_RELOC
)
10364 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10365 else if (size
== 2)
10366 reloc_type
= BFD_RELOC_16_PCREL
;
10367 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10368 else if (need_plt32_p (fragP
->fr_symbol
))
10369 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10372 reloc_type
= BFD_RELOC_32_PCREL
;
10374 old_fr_fix
= fragP
->fr_fix
;
10375 opcode
= (unsigned char *) fragP
->fr_opcode
;
10377 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10380 /* Make jmp (0xeb) a (d)word displacement jump. */
10382 fragP
->fr_fix
+= size
;
10383 fix_new (fragP
, old_fr_fix
, size
,
10385 fragP
->fr_offset
, 1,
10391 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10393 /* Negate the condition, and branch past an
10394 unconditional jump. */
10397 /* Insert an unconditional jump. */
10399 /* We added two extra opcode bytes, and have a two byte
10401 fragP
->fr_fix
+= 2 + 2;
10402 fix_new (fragP
, old_fr_fix
+ 2, 2,
10404 fragP
->fr_offset
, 1,
10408 /* Fall through. */
10411 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10415 fragP
->fr_fix
+= 1;
10416 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10418 fragP
->fr_offset
, 1,
10419 BFD_RELOC_8_PCREL
);
10420 fixP
->fx_signed
= 1;
10424 /* This changes the byte-displacement jump 0x7N
10425 to the (d)word-displacement jump 0x0f,0x8N. */
10426 opcode
[1] = opcode
[0] + 0x10;
10427 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10428 /* We've added an opcode byte. */
10429 fragP
->fr_fix
+= 1 + size
;
10430 fix_new (fragP
, old_fr_fix
+ 1, size
,
10432 fragP
->fr_offset
, 1,
10437 BAD_CASE (fragP
->fr_subtype
);
10441 return fragP
->fr_fix
- old_fr_fix
;
10444 /* Guess size depending on current relax state. Initially the relax
10445 state will correspond to a short jump and we return 1, because
10446 the variable part of the frag (the branch offset) is one byte
10447 long. However, we can relax a section more than once and in that
10448 case we must either set fr_subtype back to the unrelaxed state,
10449 or return the value for the appropriate branch. */
10450 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10453 /* Called after relax() is finished.
10455 In: Address of frag.
10456 fr_type == rs_machine_dependent.
10457 fr_subtype is what the address relaxed to.
10459 Out: Any fixSs and constants are set up.
10460 Caller will turn frag into a ".space 0". */
10463 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10466 unsigned char *opcode
;
10467 unsigned char *where_to_put_displacement
= NULL
;
10468 offsetT target_address
;
10469 offsetT opcode_address
;
10470 unsigned int extension
= 0;
10471 offsetT displacement_from_opcode_start
;
10473 opcode
= (unsigned char *) fragP
->fr_opcode
;
10475 /* Address we want to reach in file space. */
10476 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10478 /* Address opcode resides at in file space. */
10479 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10481 /* Displacement from opcode start to fill into instruction. */
10482 displacement_from_opcode_start
= target_address
- opcode_address
;
10484 if ((fragP
->fr_subtype
& BIG
) == 0)
10486 /* Don't have to change opcode. */
10487 extension
= 1; /* 1 opcode + 1 displacement */
10488 where_to_put_displacement
= &opcode
[1];
10492 if (no_cond_jump_promotion
10493 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10494 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10495 _("long jump required"));
10497 switch (fragP
->fr_subtype
)
10499 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10500 extension
= 4; /* 1 opcode + 4 displacement */
10502 where_to_put_displacement
= &opcode
[1];
10505 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10506 extension
= 2; /* 1 opcode + 2 displacement */
10508 where_to_put_displacement
= &opcode
[1];
10511 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10512 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10513 extension
= 5; /* 2 opcode + 4 displacement */
10514 opcode
[1] = opcode
[0] + 0x10;
10515 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10516 where_to_put_displacement
= &opcode
[2];
10519 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10520 extension
= 3; /* 2 opcode + 2 displacement */
10521 opcode
[1] = opcode
[0] + 0x10;
10522 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10523 where_to_put_displacement
= &opcode
[2];
10526 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10531 where_to_put_displacement
= &opcode
[3];
10535 BAD_CASE (fragP
->fr_subtype
);
10540 /* If size if less then four we are sure that the operand fits,
10541 but if it's 4, then it could be that the displacement is larger
10543 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10545 && ((addressT
) (displacement_from_opcode_start
- extension
10546 + ((addressT
) 1 << 31))
10547 > (((addressT
) 2 << 31) - 1)))
10549 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10550 _("jump target out of range"));
10551 /* Make us emit 0. */
10552 displacement_from_opcode_start
= extension
;
10554 /* Now put displacement after opcode. */
10555 md_number_to_chars ((char *) where_to_put_displacement
,
10556 (valueT
) (displacement_from_opcode_start
- extension
),
10557 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10558 fragP
->fr_fix
+= extension
;
10561 /* Apply a fixup (fixP) to segment data, once it has been determined
10562 by our caller that we have all the info we need to fix it up.
10564 Parameter valP is the pointer to the value of the bits.
10566 On the 386, immediates, displacements, and data pointers are all in
10567 the same (little-endian) format, so we don't need to care about which
10568 we are handling. */
10571 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10573 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10574 valueT value
= *valP
;
10576 #if !defined (TE_Mach)
10577 if (fixP
->fx_pcrel
)
10579 switch (fixP
->fx_r_type
)
10585 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10588 case BFD_RELOC_X86_64_32S
:
10589 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10592 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10595 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10600 if (fixP
->fx_addsy
!= NULL
10601 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10602 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10603 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10604 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10605 && !use_rela_relocations
)
10607 /* This is a hack. There should be a better way to handle this.
10608 This covers for the fact that bfd_install_relocation will
10609 subtract the current location (for partial_inplace, PC relative
10610 relocations); see more below. */
10614 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10617 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10622 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10624 if ((sym_seg
== seg
10625 || (symbol_section_p (fixP
->fx_addsy
)
10626 && sym_seg
!= absolute_section
))
10627 && !generic_force_reloc (fixP
))
10629 /* Yes, we add the values in twice. This is because
10630 bfd_install_relocation subtracts them out again. I think
10631 bfd_install_relocation is broken, but I don't dare change
10633 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10637 #if defined (OBJ_COFF) && defined (TE_PE)
10638 /* For some reason, the PE format does not store a
10639 section address offset for a PC relative symbol. */
10640 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10641 || S_IS_WEAK (fixP
->fx_addsy
))
10642 value
+= md_pcrel_from (fixP
);
10645 #if defined (OBJ_COFF) && defined (TE_PE)
10646 if (fixP
->fx_addsy
!= NULL
10647 && S_IS_WEAK (fixP
->fx_addsy
)
10648 /* PR 16858: Do not modify weak function references. */
10649 && ! fixP
->fx_pcrel
)
10651 #if !defined (TE_PEP)
10652 /* For x86 PE weak function symbols are neither PC-relative
10653 nor do they set S_IS_FUNCTION. So the only reliable way
10654 to detect them is to check the flags of their containing
10656 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10657 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10661 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10665 /* Fix a few things - the dynamic linker expects certain values here,
10666 and we must not disappoint it. */
10667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10668 if (IS_ELF
&& fixP
->fx_addsy
)
10669 switch (fixP
->fx_r_type
)
10671 case BFD_RELOC_386_PLT32
:
10672 case BFD_RELOC_X86_64_PLT32
:
10673 /* Make the jump instruction point to the address of the operand.
10674 At runtime we merely add the offset to the actual PLT entry.
10675 NB: Subtract the offset size only for jump instructions. */
10676 if (fixP
->fx_pcrel
)
10680 case BFD_RELOC_386_TLS_GD
:
10681 case BFD_RELOC_386_TLS_LDM
:
10682 case BFD_RELOC_386_TLS_IE_32
:
10683 case BFD_RELOC_386_TLS_IE
:
10684 case BFD_RELOC_386_TLS_GOTIE
:
10685 case BFD_RELOC_386_TLS_GOTDESC
:
10686 case BFD_RELOC_X86_64_TLSGD
:
10687 case BFD_RELOC_X86_64_TLSLD
:
10688 case BFD_RELOC_X86_64_GOTTPOFF
:
10689 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10690 value
= 0; /* Fully resolved at runtime. No addend. */
10692 case BFD_RELOC_386_TLS_LE
:
10693 case BFD_RELOC_386_TLS_LDO_32
:
10694 case BFD_RELOC_386_TLS_LE_32
:
10695 case BFD_RELOC_X86_64_DTPOFF32
:
10696 case BFD_RELOC_X86_64_DTPOFF64
:
10697 case BFD_RELOC_X86_64_TPOFF32
:
10698 case BFD_RELOC_X86_64_TPOFF64
:
10699 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10702 case BFD_RELOC_386_TLS_DESC_CALL
:
10703 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10704 value
= 0; /* Fully resolved at runtime. No addend. */
10705 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10709 case BFD_RELOC_VTABLE_INHERIT
:
10710 case BFD_RELOC_VTABLE_ENTRY
:
10717 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10719 #endif /* !defined (TE_Mach) */
10721 /* Are we finished with this relocation now? */
10722 if (fixP
->fx_addsy
== NULL
)
10724 #if defined (OBJ_COFF) && defined (TE_PE)
10725 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10728 /* Remember value for tc_gen_reloc. */
10729 fixP
->fx_addnumber
= value
;
10730 /* Clear out the frag for now. */
10734 else if (use_rela_relocations
)
10736 fixP
->fx_no_overflow
= 1;
10737 /* Remember value for tc_gen_reloc. */
10738 fixP
->fx_addnumber
= value
;
10742 md_number_to_chars (p
, value
, fixP
->fx_size
);
10746 md_atof (int type
, char *litP
, int *sizeP
)
10748 /* This outputs the LITTLENUMs in REVERSE order;
10749 in accord with the bigendian 386. */
10750 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10753 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10756 output_invalid (int c
)
10759 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10762 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10763 "(0x%x)", (unsigned char) c
);
10764 return output_invalid_buf
;
10767 /* REG_STRING starts *before* REGISTER_PREFIX. */
10769 static const reg_entry
*
10770 parse_real_register (char *reg_string
, char **end_op
)
10772 char *s
= reg_string
;
10774 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10775 const reg_entry
*r
;
10777 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10778 if (*s
== REGISTER_PREFIX
)
10781 if (is_space_char (*s
))
10784 p
= reg_name_given
;
10785 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10787 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10788 return (const reg_entry
*) NULL
;
10792 /* For naked regs, make sure that we are not dealing with an identifier.
10793 This prevents confusing an identifier like `eax_var' with register
10795 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10796 return (const reg_entry
*) NULL
;
10800 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10802 /* Handle floating point regs, allowing spaces in the (i) part. */
10803 if (r
== i386_regtab
/* %st is first entry of table */)
10805 if (!cpu_arch_flags
.bitfield
.cpu8087
10806 && !cpu_arch_flags
.bitfield
.cpu287
10807 && !cpu_arch_flags
.bitfield
.cpu387
)
10808 return (const reg_entry
*) NULL
;
10810 if (is_space_char (*s
))
10815 if (is_space_char (*s
))
10817 if (*s
>= '0' && *s
<= '7')
10819 int fpr
= *s
- '0';
10821 if (is_space_char (*s
))
10826 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10831 /* We have "%st(" then garbage. */
10832 return (const reg_entry
*) NULL
;
10836 if (r
== NULL
|| allow_pseudo_reg
)
10839 if (operand_type_all_zero (&r
->reg_type
))
10840 return (const reg_entry
*) NULL
;
10842 if ((r
->reg_type
.bitfield
.dword
10843 || r
->reg_type
.bitfield
.sreg3
10844 || r
->reg_type
.bitfield
.control
10845 || r
->reg_type
.bitfield
.debug
10846 || r
->reg_type
.bitfield
.test
)
10847 && !cpu_arch_flags
.bitfield
.cpui386
)
10848 return (const reg_entry
*) NULL
;
10850 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10851 return (const reg_entry
*) NULL
;
10853 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10855 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10856 return (const reg_entry
*) NULL
;
10858 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10860 if (r
->reg_type
.bitfield
.ymmword
)
10861 return (const reg_entry
*) NULL
;
10863 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10864 return (const reg_entry
*) NULL
;
10868 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10869 return (const reg_entry
*) NULL
;
10871 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10872 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10873 return (const reg_entry
*) NULL
;
10875 /* Upper 16 vector registers are only available with VREX in 64bit
10876 mode, and require EVEX encoding. */
10877 if (r
->reg_flags
& RegVRex
)
10879 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10880 || flag_code
!= CODE_64BIT
)
10881 return (const reg_entry
*) NULL
;
10883 i
.vec_encoding
= vex_encoding_evex
;
10886 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10887 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10888 && flag_code
!= CODE_64BIT
)
10889 return (const reg_entry
*) NULL
;
10891 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10892 return (const reg_entry
*) NULL
;
10897 /* REG_STRING starts *before* REGISTER_PREFIX. */
10899 static const reg_entry
*
10900 parse_register (char *reg_string
, char **end_op
)
10902 const reg_entry
*r
;
10904 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10905 r
= parse_real_register (reg_string
, end_op
);
10910 char *save
= input_line_pointer
;
10914 input_line_pointer
= reg_string
;
10915 c
= get_symbol_name (®_string
);
10916 symbolP
= symbol_find (reg_string
);
10917 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10919 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10921 know (e
->X_op
== O_register
);
10922 know (e
->X_add_number
>= 0
10923 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10924 r
= i386_regtab
+ e
->X_add_number
;
10925 if ((r
->reg_flags
& RegVRex
))
10926 i
.vec_encoding
= vex_encoding_evex
;
10927 *end_op
= input_line_pointer
;
10929 *input_line_pointer
= c
;
10930 input_line_pointer
= save
;
10936 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10938 const reg_entry
*r
;
10939 char *end
= input_line_pointer
;
10942 r
= parse_register (name
, &input_line_pointer
);
10943 if (r
&& end
<= input_line_pointer
)
10945 *nextcharP
= *input_line_pointer
;
10946 *input_line_pointer
= 0;
10947 e
->X_op
= O_register
;
10948 e
->X_add_number
= r
- i386_regtab
;
10951 input_line_pointer
= end
;
10953 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10957 md_operand (expressionS
*e
)
10960 const reg_entry
*r
;
10962 switch (*input_line_pointer
)
10964 case REGISTER_PREFIX
:
10965 r
= parse_real_register (input_line_pointer
, &end
);
10968 e
->X_op
= O_register
;
10969 e
->X_add_number
= r
- i386_regtab
;
10970 input_line_pointer
= end
;
10975 gas_assert (intel_syntax
);
10976 end
= input_line_pointer
++;
10978 if (*input_line_pointer
== ']')
10980 ++input_line_pointer
;
10981 e
->X_op_symbol
= make_expr_symbol (e
);
10982 e
->X_add_symbol
= NULL
;
10983 e
->X_add_number
= 0;
10988 e
->X_op
= O_absent
;
10989 input_line_pointer
= end
;
10996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10997 const char *md_shortopts
= "kVQ:sqnO::";
10999 const char *md_shortopts
= "qnO::";
11002 #define OPTION_32 (OPTION_MD_BASE + 0)
11003 #define OPTION_64 (OPTION_MD_BASE + 1)
11004 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11005 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11006 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11007 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11008 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11009 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11010 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11011 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11012 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11013 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11014 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11015 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11016 #define OPTION_X32 (OPTION_MD_BASE + 14)
11017 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11018 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11019 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11020 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11021 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11022 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11023 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11024 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11025 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11026 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11027 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11028 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11030 struct option md_longopts
[] =
11032 {"32", no_argument
, NULL
, OPTION_32
},
11033 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11034 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11035 {"64", no_argument
, NULL
, OPTION_64
},
11037 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11038 {"x32", no_argument
, NULL
, OPTION_X32
},
11039 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11040 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11042 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11043 {"march", required_argument
, NULL
, OPTION_MARCH
},
11044 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11045 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11046 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11047 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11048 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11049 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11050 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11051 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11052 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11053 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11054 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11055 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11056 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11057 # if defined (TE_PE) || defined (TE_PEP)
11058 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11060 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11061 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11062 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11063 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11064 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11065 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11066 {NULL
, no_argument
, NULL
, 0}
11068 size_t md_longopts_size
= sizeof (md_longopts
);
11071 md_parse_option (int c
, const char *arg
)
11074 char *arch
, *next
, *saved
;
11079 optimize_align_code
= 0;
11083 quiet_warnings
= 1;
11086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11087 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11088 should be emitted or not. FIXME: Not implemented. */
11092 /* -V: SVR4 argument to print version ID. */
11094 print_version_id ();
11097 /* -k: Ignore for FreeBSD compatibility. */
11102 /* -s: On i386 Solaris, this tells the native assembler to use
11103 .stab instead of .stab.excl. We always use .stab anyhow. */
11106 case OPTION_MSHARED
:
11110 case OPTION_X86_USED_NOTE
:
11111 if (strcasecmp (arg
, "yes") == 0)
11113 else if (strcasecmp (arg
, "no") == 0)
11116 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11121 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11122 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11125 const char **list
, **l
;
11127 list
= bfd_target_list ();
11128 for (l
= list
; *l
!= NULL
; l
++)
11129 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11130 || strcmp (*l
, "coff-x86-64") == 0
11131 || strcmp (*l
, "pe-x86-64") == 0
11132 || strcmp (*l
, "pei-x86-64") == 0
11133 || strcmp (*l
, "mach-o-x86-64") == 0)
11135 default_arch
= "x86_64";
11139 as_fatal (_("no compiled in support for x86_64"));
11145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11149 const char **list
, **l
;
11151 list
= bfd_target_list ();
11152 for (l
= list
; *l
!= NULL
; l
++)
11153 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11155 default_arch
= "x86_64:32";
11159 as_fatal (_("no compiled in support for 32bit x86_64"));
11163 as_fatal (_("32bit x86_64 is only supported for ELF"));
11168 default_arch
= "i386";
11171 case OPTION_DIVIDE
:
11172 #ifdef SVR4_COMMENT_CHARS
11177 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11179 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11183 i386_comment_chars
= n
;
11189 saved
= xstrdup (arg
);
11191 /* Allow -march=+nosse. */
11197 as_fatal (_("invalid -march= option: `%s'"), arg
);
11198 next
= strchr (arch
, '+');
11201 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11203 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11206 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11209 cpu_arch_name
= cpu_arch
[j
].name
;
11210 cpu_sub_arch_name
= NULL
;
11211 cpu_arch_flags
= cpu_arch
[j
].flags
;
11212 cpu_arch_isa
= cpu_arch
[j
].type
;
11213 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11214 if (!cpu_arch_tune_set
)
11216 cpu_arch_tune
= cpu_arch_isa
;
11217 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11221 else if (*cpu_arch
[j
].name
== '.'
11222 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11224 /* ISA extension. */
11225 i386_cpu_flags flags
;
11227 flags
= cpu_flags_or (cpu_arch_flags
,
11228 cpu_arch
[j
].flags
);
11230 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11232 if (cpu_sub_arch_name
)
11234 char *name
= cpu_sub_arch_name
;
11235 cpu_sub_arch_name
= concat (name
,
11237 (const char *) NULL
);
11241 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11242 cpu_arch_flags
= flags
;
11243 cpu_arch_isa_flags
= flags
;
11247 = cpu_flags_or (cpu_arch_isa_flags
,
11248 cpu_arch
[j
].flags
);
11253 if (j
>= ARRAY_SIZE (cpu_arch
))
11255 /* Disable an ISA extension. */
11256 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11257 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11259 i386_cpu_flags flags
;
11261 flags
= cpu_flags_and_not (cpu_arch_flags
,
11262 cpu_noarch
[j
].flags
);
11263 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11265 if (cpu_sub_arch_name
)
11267 char *name
= cpu_sub_arch_name
;
11268 cpu_sub_arch_name
= concat (arch
,
11269 (const char *) NULL
);
11273 cpu_sub_arch_name
= xstrdup (arch
);
11274 cpu_arch_flags
= flags
;
11275 cpu_arch_isa_flags
= flags
;
11280 if (j
>= ARRAY_SIZE (cpu_noarch
))
11281 j
= ARRAY_SIZE (cpu_arch
);
11284 if (j
>= ARRAY_SIZE (cpu_arch
))
11285 as_fatal (_("invalid -march= option: `%s'"), arg
);
11289 while (next
!= NULL
);
11295 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11296 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11298 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11300 cpu_arch_tune_set
= 1;
11301 cpu_arch_tune
= cpu_arch
[j
].type
;
11302 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11306 if (j
>= ARRAY_SIZE (cpu_arch
))
11307 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11310 case OPTION_MMNEMONIC
:
11311 if (strcasecmp (arg
, "att") == 0)
11312 intel_mnemonic
= 0;
11313 else if (strcasecmp (arg
, "intel") == 0)
11314 intel_mnemonic
= 1;
11316 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11319 case OPTION_MSYNTAX
:
11320 if (strcasecmp (arg
, "att") == 0)
11322 else if (strcasecmp (arg
, "intel") == 0)
11325 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11328 case OPTION_MINDEX_REG
:
11329 allow_index_reg
= 1;
11332 case OPTION_MNAKED_REG
:
11333 allow_naked_reg
= 1;
11336 case OPTION_MSSE2AVX
:
11340 case OPTION_MSSE_CHECK
:
11341 if (strcasecmp (arg
, "error") == 0)
11342 sse_check
= check_error
;
11343 else if (strcasecmp (arg
, "warning") == 0)
11344 sse_check
= check_warning
;
11345 else if (strcasecmp (arg
, "none") == 0)
11346 sse_check
= check_none
;
11348 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11351 case OPTION_MOPERAND_CHECK
:
11352 if (strcasecmp (arg
, "error") == 0)
11353 operand_check
= check_error
;
11354 else if (strcasecmp (arg
, "warning") == 0)
11355 operand_check
= check_warning
;
11356 else if (strcasecmp (arg
, "none") == 0)
11357 operand_check
= check_none
;
11359 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11362 case OPTION_MAVXSCALAR
:
11363 if (strcasecmp (arg
, "128") == 0)
11364 avxscalar
= vex128
;
11365 else if (strcasecmp (arg
, "256") == 0)
11366 avxscalar
= vex256
;
11368 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11371 case OPTION_MVEXWIG
:
11372 if (strcmp (arg
, "0") == 0)
11374 else if (strcmp (arg
, "1") == 0)
11377 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11380 case OPTION_MADD_BND_PREFIX
:
11381 add_bnd_prefix
= 1;
11384 case OPTION_MEVEXLIG
:
11385 if (strcmp (arg
, "128") == 0)
11386 evexlig
= evexl128
;
11387 else if (strcmp (arg
, "256") == 0)
11388 evexlig
= evexl256
;
11389 else if (strcmp (arg
, "512") == 0)
11390 evexlig
= evexl512
;
11392 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11395 case OPTION_MEVEXRCIG
:
11396 if (strcmp (arg
, "rne") == 0)
11398 else if (strcmp (arg
, "rd") == 0)
11400 else if (strcmp (arg
, "ru") == 0)
11402 else if (strcmp (arg
, "rz") == 0)
11405 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11408 case OPTION_MEVEXWIG
:
11409 if (strcmp (arg
, "0") == 0)
11411 else if (strcmp (arg
, "1") == 0)
11414 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11417 # if defined (TE_PE) || defined (TE_PEP)
11418 case OPTION_MBIG_OBJ
:
11423 case OPTION_MOMIT_LOCK_PREFIX
:
11424 if (strcasecmp (arg
, "yes") == 0)
11425 omit_lock_prefix
= 1;
11426 else if (strcasecmp (arg
, "no") == 0)
11427 omit_lock_prefix
= 0;
11429 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11432 case OPTION_MFENCE_AS_LOCK_ADD
:
11433 if (strcasecmp (arg
, "yes") == 0)
11435 else if (strcasecmp (arg
, "no") == 0)
11438 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11441 case OPTION_MRELAX_RELOCATIONS
:
11442 if (strcasecmp (arg
, "yes") == 0)
11443 generate_relax_relocations
= 1;
11444 else if (strcasecmp (arg
, "no") == 0)
11445 generate_relax_relocations
= 0;
11447 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11450 case OPTION_MAMD64
:
11454 case OPTION_MINTEL64
:
11462 /* Turn off -Os. */
11463 optimize_for_space
= 0;
11465 else if (*arg
== 's')
11467 optimize_for_space
= 1;
11468 /* Turn on all encoding optimizations. */
11469 optimize
= INT_MAX
;
11473 optimize
= atoi (arg
);
11474 /* Turn off -Os. */
11475 optimize_for_space
= 0;
11485 #define MESSAGE_TEMPLATE \
11489 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11490 int *left_p
, const char *name
, int len
)
11492 int size
= sizeof (MESSAGE_TEMPLATE
);
11493 int left
= *left_p
;
11495 /* Reserve 2 spaces for ", " or ",\0" */
11498 /* Check if there is any room. */
11506 p
= mempcpy (p
, name
, len
);
11510 /* Output the current message now and start a new one. */
11513 fprintf (stream
, "%s\n", message
);
11515 left
= size
- (start
- message
) - len
- 2;
11517 gas_assert (left
>= 0);
11519 p
= mempcpy (p
, name
, len
);
11527 show_arch (FILE *stream
, int ext
, int check
)
11529 static char message
[] = MESSAGE_TEMPLATE
;
11530 char *start
= message
+ 27;
11532 int size
= sizeof (MESSAGE_TEMPLATE
);
11539 left
= size
- (start
- message
);
11540 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11542 /* Should it be skipped? */
11543 if (cpu_arch
[j
].skip
)
11546 name
= cpu_arch
[j
].name
;
11547 len
= cpu_arch
[j
].len
;
11550 /* It is an extension. Skip if we aren't asked to show it. */
11561 /* It is an processor. Skip if we show only extension. */
11564 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11566 /* It is an impossible processor - skip. */
11570 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11573 /* Display disabled extensions. */
11575 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11577 name
= cpu_noarch
[j
].name
;
11578 len
= cpu_noarch
[j
].len
;
11579 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11584 fprintf (stream
, "%s\n", message
);
11588 md_show_usage (FILE *stream
)
11590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11591 fprintf (stream
, _("\
11593 -V print assembler version number\n\
11596 fprintf (stream
, _("\
11597 -n Do not optimize code alignment\n\
11598 -q quieten some warnings\n"));
11599 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11600 fprintf (stream
, _("\
11603 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11604 || defined (TE_PE) || defined (TE_PEP))
11605 fprintf (stream
, _("\
11606 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11608 #ifdef SVR4_COMMENT_CHARS
11609 fprintf (stream
, _("\
11610 --divide do not treat `/' as a comment character\n"));
11612 fprintf (stream
, _("\
11613 --divide ignored\n"));
11615 fprintf (stream
, _("\
11616 -march=CPU[,+EXTENSION...]\n\
11617 generate code for CPU and EXTENSION, CPU is one of:\n"));
11618 show_arch (stream
, 0, 1);
11619 fprintf (stream
, _("\
11620 EXTENSION is combination of:\n"));
11621 show_arch (stream
, 1, 0);
11622 fprintf (stream
, _("\
11623 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11624 show_arch (stream
, 0, 0);
11625 fprintf (stream
, _("\
11626 -msse2avx encode SSE instructions with VEX prefix\n"));
11627 fprintf (stream
, _("\
11628 -msse-check=[none|error|warning] (default: warning)\n\
11629 check SSE instructions\n"));
11630 fprintf (stream
, _("\
11631 -moperand-check=[none|error|warning] (default: warning)\n\
11632 check operand combinations for validity\n"));
11633 fprintf (stream
, _("\
11634 -mavxscalar=[128|256] (default: 128)\n\
11635 encode scalar AVX instructions with specific vector\n\
11637 fprintf (stream
, _("\
11638 -mvexwig=[0|1] (default: 0)\n\
11639 encode VEX instructions with specific VEX.W value\n\
11640 for VEX.W bit ignored instructions\n"));
11641 fprintf (stream
, _("\
11642 -mevexlig=[128|256|512] (default: 128)\n\
11643 encode scalar EVEX instructions with specific vector\n\
11645 fprintf (stream
, _("\
11646 -mevexwig=[0|1] (default: 0)\n\
11647 encode EVEX instructions with specific EVEX.W value\n\
11648 for EVEX.W bit ignored instructions\n"));
11649 fprintf (stream
, _("\
11650 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11651 encode EVEX instructions with specific EVEX.RC value\n\
11652 for SAE-only ignored instructions\n"));
11653 fprintf (stream
, _("\
11654 -mmnemonic=[att|intel] "));
11655 if (SYSV386_COMPAT
)
11656 fprintf (stream
, _("(default: att)\n"));
11658 fprintf (stream
, _("(default: intel)\n"));
11659 fprintf (stream
, _("\
11660 use AT&T/Intel mnemonic\n"));
11661 fprintf (stream
, _("\
11662 -msyntax=[att|intel] (default: att)\n\
11663 use AT&T/Intel syntax\n"));
11664 fprintf (stream
, _("\
11665 -mindex-reg support pseudo index registers\n"));
11666 fprintf (stream
, _("\
11667 -mnaked-reg don't require `%%' prefix for registers\n"));
11668 fprintf (stream
, _("\
11669 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11671 fprintf (stream
, _("\
11672 -mshared disable branch optimization for shared code\n"));
11673 fprintf (stream
, _("\
11674 -mx86-used-note=[no|yes] "));
11675 if (DEFAULT_X86_USED_NOTE
)
11676 fprintf (stream
, _("(default: yes)\n"));
11678 fprintf (stream
, _("(default: no)\n"));
11679 fprintf (stream
, _("\
11680 generate x86 used ISA and feature properties\n"));
11682 #if defined (TE_PE) || defined (TE_PEP)
11683 fprintf (stream
, _("\
11684 -mbig-obj generate big object files\n"));
11686 fprintf (stream
, _("\
11687 -momit-lock-prefix=[no|yes] (default: no)\n\
11688 strip all lock prefixes\n"));
11689 fprintf (stream
, _("\
11690 -mfence-as-lock-add=[no|yes] (default: no)\n\
11691 encode lfence, mfence and sfence as\n\
11692 lock addl $0x0, (%%{re}sp)\n"));
11693 fprintf (stream
, _("\
11694 -mrelax-relocations=[no|yes] "));
11695 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11696 fprintf (stream
, _("(default: yes)\n"));
11698 fprintf (stream
, _("(default: no)\n"));
11699 fprintf (stream
, _("\
11700 generate relax relocations\n"));
11701 fprintf (stream
, _("\
11702 -mamd64 accept only AMD64 ISA [default]\n"));
11703 fprintf (stream
, _("\
11704 -mintel64 accept only Intel64 ISA\n"));
11707 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11708 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11709 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11711 /* Pick the target format to use. */
11714 i386_target_format (void)
11716 if (!strncmp (default_arch
, "x86_64", 6))
11718 update_code_flag (CODE_64BIT
, 1);
11719 if (default_arch
[6] == '\0')
11720 x86_elf_abi
= X86_64_ABI
;
11722 x86_elf_abi
= X86_64_X32_ABI
;
11724 else if (!strcmp (default_arch
, "i386"))
11725 update_code_flag (CODE_32BIT
, 1);
11726 else if (!strcmp (default_arch
, "iamcu"))
11728 update_code_flag (CODE_32BIT
, 1);
11729 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11731 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11732 cpu_arch_name
= "iamcu";
11733 cpu_sub_arch_name
= NULL
;
11734 cpu_arch_flags
= iamcu_flags
;
11735 cpu_arch_isa
= PROCESSOR_IAMCU
;
11736 cpu_arch_isa_flags
= iamcu_flags
;
11737 if (!cpu_arch_tune_set
)
11739 cpu_arch_tune
= cpu_arch_isa
;
11740 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11743 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11744 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11748 as_fatal (_("unknown architecture"));
11750 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11751 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11752 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11753 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11755 switch (OUTPUT_FLAVOR
)
11757 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11758 case bfd_target_aout_flavour
:
11759 return AOUT_TARGET_FORMAT
;
11761 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11762 # if defined (TE_PE) || defined (TE_PEP)
11763 case bfd_target_coff_flavour
:
11764 if (flag_code
== CODE_64BIT
)
11765 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11768 # elif defined (TE_GO32)
11769 case bfd_target_coff_flavour
:
11770 return "coff-go32";
11772 case bfd_target_coff_flavour
:
11773 return "coff-i386";
11776 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11777 case bfd_target_elf_flavour
:
11779 const char *format
;
11781 switch (x86_elf_abi
)
11784 format
= ELF_TARGET_FORMAT
;
11787 use_rela_relocations
= 1;
11789 format
= ELF_TARGET_FORMAT64
;
11791 case X86_64_X32_ABI
:
11792 use_rela_relocations
= 1;
11794 disallow_64bit_reloc
= 1;
11795 format
= ELF_TARGET_FORMAT32
;
11798 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11800 if (x86_elf_abi
!= X86_64_ABI
)
11801 as_fatal (_("Intel L1OM is 64bit only"));
11802 return ELF_TARGET_L1OM_FORMAT
;
11804 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11806 if (x86_elf_abi
!= X86_64_ABI
)
11807 as_fatal (_("Intel K1OM is 64bit only"));
11808 return ELF_TARGET_K1OM_FORMAT
;
11810 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11812 if (x86_elf_abi
!= I386_ABI
)
11813 as_fatal (_("Intel MCU is 32bit only"));
11814 return ELF_TARGET_IAMCU_FORMAT
;
11820 #if defined (OBJ_MACH_O)
11821 case bfd_target_mach_o_flavour
:
11822 if (flag_code
== CODE_64BIT
)
11824 use_rela_relocations
= 1;
11826 return "mach-o-x86-64";
11829 return "mach-o-i386";
11837 #endif /* OBJ_MAYBE_ more than one */
11840 md_undefined_symbol (char *name
)
11842 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11843 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11844 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11845 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11849 if (symbol_find (name
))
11850 as_bad (_("GOT already in symbol table"));
11851 GOT_symbol
= symbol_new (name
, undefined_section
,
11852 (valueT
) 0, &zero_address_frag
);
11859 /* Round up a section size to the appropriate boundary. */
11862 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11864 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11865 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11867 /* For a.out, force the section size to be aligned. If we don't do
11868 this, BFD will align it for us, but it will not write out the
11869 final bytes of the section. This may be a bug in BFD, but it is
11870 easier to fix it here since that is how the other a.out targets
11874 align
= bfd_get_section_alignment (stdoutput
, segment
);
11875 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11882 /* On the i386, PC-relative offsets are relative to the start of the
11883 next instruction. That is, the address of the offset, plus its
11884 size, since the offset is always the last part of the insn. */
11887 md_pcrel_from (fixS
*fixP
)
11889 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11895 s_bss (int ignore ATTRIBUTE_UNUSED
)
11899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11901 obj_elf_section_change_hook ();
11903 temp
= get_absolute_expression ();
11904 subseg_set (bss_section
, (subsegT
) temp
);
11905 demand_empty_rest_of_line ();
11911 i386_validate_fix (fixS
*fixp
)
11913 if (fixp
->fx_subsy
)
11915 if (fixp
->fx_subsy
== GOT_symbol
)
11917 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11922 if (fixp
->fx_tcbit2
)
11923 fixp
->fx_r_type
= (fixp
->fx_tcbit
11924 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11925 : BFD_RELOC_X86_64_GOTPCRELX
);
11928 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11933 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11935 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11937 fixp
->fx_subsy
= 0;
11940 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11941 else if (!object_64bit
)
11943 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11944 && fixp
->fx_tcbit2
)
11945 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11951 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11954 bfd_reloc_code_real_type code
;
11956 switch (fixp
->fx_r_type
)
11958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11959 case BFD_RELOC_SIZE32
:
11960 case BFD_RELOC_SIZE64
:
11961 if (S_IS_DEFINED (fixp
->fx_addsy
)
11962 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11964 /* Resolve size relocation against local symbol to size of
11965 the symbol plus addend. */
11966 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11967 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11968 && !fits_in_unsigned_long (value
))
11969 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11970 _("symbol size computation overflow"));
11971 fixp
->fx_addsy
= NULL
;
11972 fixp
->fx_subsy
= NULL
;
11973 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11977 /* Fall through. */
11979 case BFD_RELOC_X86_64_PLT32
:
11980 case BFD_RELOC_X86_64_GOT32
:
11981 case BFD_RELOC_X86_64_GOTPCREL
:
11982 case BFD_RELOC_X86_64_GOTPCRELX
:
11983 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11984 case BFD_RELOC_386_PLT32
:
11985 case BFD_RELOC_386_GOT32
:
11986 case BFD_RELOC_386_GOT32X
:
11987 case BFD_RELOC_386_GOTOFF
:
11988 case BFD_RELOC_386_GOTPC
:
11989 case BFD_RELOC_386_TLS_GD
:
11990 case BFD_RELOC_386_TLS_LDM
:
11991 case BFD_RELOC_386_TLS_LDO_32
:
11992 case BFD_RELOC_386_TLS_IE_32
:
11993 case BFD_RELOC_386_TLS_IE
:
11994 case BFD_RELOC_386_TLS_GOTIE
:
11995 case BFD_RELOC_386_TLS_LE_32
:
11996 case BFD_RELOC_386_TLS_LE
:
11997 case BFD_RELOC_386_TLS_GOTDESC
:
11998 case BFD_RELOC_386_TLS_DESC_CALL
:
11999 case BFD_RELOC_X86_64_TLSGD
:
12000 case BFD_RELOC_X86_64_TLSLD
:
12001 case BFD_RELOC_X86_64_DTPOFF32
:
12002 case BFD_RELOC_X86_64_DTPOFF64
:
12003 case BFD_RELOC_X86_64_GOTTPOFF
:
12004 case BFD_RELOC_X86_64_TPOFF32
:
12005 case BFD_RELOC_X86_64_TPOFF64
:
12006 case BFD_RELOC_X86_64_GOTOFF64
:
12007 case BFD_RELOC_X86_64_GOTPC32
:
12008 case BFD_RELOC_X86_64_GOT64
:
12009 case BFD_RELOC_X86_64_GOTPCREL64
:
12010 case BFD_RELOC_X86_64_GOTPC64
:
12011 case BFD_RELOC_X86_64_GOTPLT64
:
12012 case BFD_RELOC_X86_64_PLTOFF64
:
12013 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12014 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12015 case BFD_RELOC_RVA
:
12016 case BFD_RELOC_VTABLE_ENTRY
:
12017 case BFD_RELOC_VTABLE_INHERIT
:
12019 case BFD_RELOC_32_SECREL
:
12021 code
= fixp
->fx_r_type
;
12023 case BFD_RELOC_X86_64_32S
:
12024 if (!fixp
->fx_pcrel
)
12026 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12027 code
= fixp
->fx_r_type
;
12030 /* Fall through. */
12032 if (fixp
->fx_pcrel
)
12034 switch (fixp
->fx_size
)
12037 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12038 _("can not do %d byte pc-relative relocation"),
12040 code
= BFD_RELOC_32_PCREL
;
12042 case 1: code
= BFD_RELOC_8_PCREL
; break;
12043 case 2: code
= BFD_RELOC_16_PCREL
; break;
12044 case 4: code
= BFD_RELOC_32_PCREL
; break;
12046 case 8: code
= BFD_RELOC_64_PCREL
; break;
12052 switch (fixp
->fx_size
)
12055 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12056 _("can not do %d byte relocation"),
12058 code
= BFD_RELOC_32
;
12060 case 1: code
= BFD_RELOC_8
; break;
12061 case 2: code
= BFD_RELOC_16
; break;
12062 case 4: code
= BFD_RELOC_32
; break;
12064 case 8: code
= BFD_RELOC_64
; break;
12071 if ((code
== BFD_RELOC_32
12072 || code
== BFD_RELOC_32_PCREL
12073 || code
== BFD_RELOC_X86_64_32S
)
12075 && fixp
->fx_addsy
== GOT_symbol
)
12078 code
= BFD_RELOC_386_GOTPC
;
12080 code
= BFD_RELOC_X86_64_GOTPC32
;
12082 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12084 && fixp
->fx_addsy
== GOT_symbol
)
12086 code
= BFD_RELOC_X86_64_GOTPC64
;
12089 rel
= XNEW (arelent
);
12090 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12091 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12093 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12095 if (!use_rela_relocations
)
12097 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12098 vtable entry to be used in the relocation's section offset. */
12099 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12100 rel
->address
= fixp
->fx_offset
;
12101 #if defined (OBJ_COFF) && defined (TE_PE)
12102 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12103 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12108 /* Use the rela in 64bit mode. */
12111 if (disallow_64bit_reloc
)
12114 case BFD_RELOC_X86_64_DTPOFF64
:
12115 case BFD_RELOC_X86_64_TPOFF64
:
12116 case BFD_RELOC_64_PCREL
:
12117 case BFD_RELOC_X86_64_GOTOFF64
:
12118 case BFD_RELOC_X86_64_GOT64
:
12119 case BFD_RELOC_X86_64_GOTPCREL64
:
12120 case BFD_RELOC_X86_64_GOTPC64
:
12121 case BFD_RELOC_X86_64_GOTPLT64
:
12122 case BFD_RELOC_X86_64_PLTOFF64
:
12123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12124 _("cannot represent relocation type %s in x32 mode"),
12125 bfd_get_reloc_code_name (code
));
12131 if (!fixp
->fx_pcrel
)
12132 rel
->addend
= fixp
->fx_offset
;
12136 case BFD_RELOC_X86_64_PLT32
:
12137 case BFD_RELOC_X86_64_GOT32
:
12138 case BFD_RELOC_X86_64_GOTPCREL
:
12139 case BFD_RELOC_X86_64_GOTPCRELX
:
12140 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12141 case BFD_RELOC_X86_64_TLSGD
:
12142 case BFD_RELOC_X86_64_TLSLD
:
12143 case BFD_RELOC_X86_64_GOTTPOFF
:
12144 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12145 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12146 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12149 rel
->addend
= (section
->vma
12151 + fixp
->fx_addnumber
12152 + md_pcrel_from (fixp
));
12157 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12158 if (rel
->howto
== NULL
)
12160 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12161 _("cannot represent relocation type %s"),
12162 bfd_get_reloc_code_name (code
));
12163 /* Set howto to a garbage value so that we can keep going. */
12164 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12165 gas_assert (rel
->howto
!= NULL
);
12171 #include "tc-i386-intel.c"
12174 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12176 int saved_naked_reg
;
12177 char saved_register_dot
;
12179 saved_naked_reg
= allow_naked_reg
;
12180 allow_naked_reg
= 1;
12181 saved_register_dot
= register_chars
['.'];
12182 register_chars
['.'] = '.';
12183 allow_pseudo_reg
= 1;
12184 expression_and_evaluate (exp
);
12185 allow_pseudo_reg
= 0;
12186 register_chars
['.'] = saved_register_dot
;
12187 allow_naked_reg
= saved_naked_reg
;
12189 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12191 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12193 exp
->X_op
= O_constant
;
12194 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12195 .dw2_regnum
[flag_code
>> 1];
12198 exp
->X_op
= O_illegal
;
12203 tc_x86_frame_initial_instructions (void)
12205 static unsigned int sp_regno
[2];
12207 if (!sp_regno
[flag_code
>> 1])
12209 char *saved_input
= input_line_pointer
;
12210 char sp
[][4] = {"esp", "rsp"};
12213 input_line_pointer
= sp
[flag_code
>> 1];
12214 tc_x86_parse_to_dw2regnum (&exp
);
12215 gas_assert (exp
.X_op
== O_constant
);
12216 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12217 input_line_pointer
= saved_input
;
12220 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12221 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12225 x86_dwarf2_addr_size (void)
12227 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12228 if (x86_elf_abi
== X86_64_X32_ABI
)
12231 return bfd_arch_bits_per_address (stdoutput
) / 8;
12235 i386_elf_section_type (const char *str
, size_t len
)
12237 if (flag_code
== CODE_64BIT
12238 && len
== sizeof ("unwind") - 1
12239 && strncmp (str
, "unwind", 6) == 0)
12240 return SHT_X86_64_UNWIND
;
12247 i386_solaris_fix_up_eh_frame (segT sec
)
12249 if (flag_code
== CODE_64BIT
)
12250 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12256 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12260 exp
.X_op
= O_secrel
;
12261 exp
.X_add_symbol
= symbol
;
12262 exp
.X_add_number
= 0;
12263 emit_expr (&exp
, size
);
12267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12268 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12271 x86_64_section_letter (int letter
, const char **ptr_msg
)
12273 if (flag_code
== CODE_64BIT
)
12276 return SHF_X86_64_LARGE
;
12278 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12281 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12286 x86_64_section_word (char *str
, size_t len
)
12288 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12289 return SHF_X86_64_LARGE
;
12295 handle_large_common (int small ATTRIBUTE_UNUSED
)
12297 if (flag_code
!= CODE_64BIT
)
12299 s_comm_internal (0, elf_common_parse
);
12300 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12304 static segT lbss_section
;
12305 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12306 asection
*saved_bss_section
= bss_section
;
12308 if (lbss_section
== NULL
)
12310 flagword applicable
;
12311 segT seg
= now_seg
;
12312 subsegT subseg
= now_subseg
;
12314 /* The .lbss section is for local .largecomm symbols. */
12315 lbss_section
= subseg_new (".lbss", 0);
12316 applicable
= bfd_applicable_section_flags (stdoutput
);
12317 bfd_set_section_flags (stdoutput
, lbss_section
,
12318 applicable
& SEC_ALLOC
);
12319 seg_info (lbss_section
)->bss
= 1;
12321 subseg_set (seg
, subseg
);
12324 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12325 bss_section
= lbss_section
;
12327 s_comm_internal (0, elf_common_parse
);
12329 elf_com_section_ptr
= saved_com_section_ptr
;
12330 bss_section
= saved_bss_section
;
12333 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */