gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 struct fix;
  27
  28 #define TARGET_BYTES_BIG_ENDIAN 0
  29
  30 #define TARGET_ARCH             bfd_arch_i386
  31 #define TARGET_MACH             (i386_mach ())
  32 extern unsigned long i386_mach (void);
  33
  34 #ifdef TE_FreeBSD
  35 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  36 #endif
  37 #ifdef TE_NetBSD
  38 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  39 #endif
  40 #ifdef TE_386BSD
  41 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  42 #endif
  43 #ifdef TE_LINUX
  44 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  45 #endif
  46 #ifdef TE_Mach
  47 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  48 #endif
  49 #ifdef TE_DYNIX
  50 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  51 #endif
  52 #ifndef AOUT_TARGET_FORMAT
  53 #define AOUT_TARGET_FORMAT      "a.out-i386"
  54 #endif
  55
  56 #ifdef TE_FreeBSD
  57 #define ELF_TARGET_FORMAT       "elf32-i386-freebsd"
  58 #define ELF_TARGET_FORMAT64     "elf64-x86-64-freebsd"
  59 #elif defined (TE_VXWORKS)
  60 #define ELF_TARGET_FORMAT       "elf32-i386-vxworks"
  61 #endif
  62
  63 #ifndef ELF_TARGET_FORMAT
  64 #define ELF_TARGET_FORMAT       "elf32-i386"
  65 #endif
  66
  67 #ifndef ELF_TARGET_FORMAT64
  68 #define ELF_TARGET_FORMAT64     "elf64-x86-64"
  69 #endif
  70
  71 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  72      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  73 extern const char *i386_target_format (void);
  74 #define TARGET_FORMAT i386_target_format ()
  75 #else
  76 #ifdef OBJ_ELF
  77 #define TARGET_FORMAT           ELF_TARGET_FORMAT
  78 #endif
  79 #ifdef OBJ_AOUT
  80 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  81 #endif
  82 #endif
  83
  84 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  85 #define md_end i386_elf_emit_arch_note
  86 extern void i386_elf_emit_arch_note (void);
  87 #endif
  88
  89 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  90
  91 #define LOCAL_LABELS_FB 1
  92
  93 extern const char extra_symbol_chars[];
  94 #define tc_symbol_chars extra_symbol_chars
  95
  96 extern const char *i386_comment_chars;
  97 #define tc_comment_chars i386_comment_chars
  98
  99 #define MAX_OPERANDS 4          /* max operands per insn */
 100 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp, insertq, extrq) */
 101 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 102
 103 /* Prefixes will be emitted in the order defined below.
 104    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 105    instruction, and so must come before any prefixes.
 106    The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
 107    LOCKREP_PREFIX.  */
 108 #define WAIT_PREFIX     0
 109 #define SEG_PREFIX      1
 110 #define ADDR_PREFIX     2
 111 #define DATA_PREFIX     3
 112 #define LOCKREP_PREFIX  4
 113 #define REX_PREFIX      5       /* must come last.  */
 114 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 115
 116 /* we define the syntax here (modulo base,index,scale syntax) */
 117 #define REGISTER_PREFIX '%'
 118 #define IMMEDIATE_PREFIX '$'
 119 #define ABSOLUTE_PREFIX '*'
 120
 121 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 122 #define NOP_OPCODE (char) 0x90
 123
 124 /* register numbers */
 125 #define EBP_REG_NUM 5
 126 #define ESP_REG_NUM 4
 127
 128 /* modrm_byte.regmem for twobyte escape */
 129 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 130 /* index_base_byte.index for no index register addressing */
 131 #define NO_INDEX_REGISTER ESP_REG_NUM
 132 /* index_base_byte.base for no base register addressing */
 133 #define NO_BASE_REGISTER EBP_REG_NUM
 134 #define NO_BASE_REGISTER_16 6
 135
 136 /* these are the instruction mnemonic suffixes.  */
 137 #define WORD_MNEM_SUFFIX  'w'
 138 #define BYTE_MNEM_SUFFIX  'b'
 139 #define SHORT_MNEM_SUFFIX 's'
 140 #define LONG_MNEM_SUFFIX  'l'
 141 #define QWORD_MNEM_SUFFIX  'q'
 142 /* Intel Syntax */
 143 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 144
 145 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 146 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 147 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 148
 149 #define END_OF_INSN '\0'
 150
 151 typedef struct
 152 {
 153   /* instruction name sans width suffix ("mov" for movl insns) */
 154   char *name;
 155
 156   /* how many operands */
 157   unsigned int operands;
 158
 159   /* base_opcode is the fundamental opcode byte without optional
 160      prefix(es).  */
 161   unsigned int base_opcode;
 162 #define Opcode_D        0x2 /* Direction bit:
 163                                set if Reg --> Regmem;
 164                                unset if Regmem --> Reg. */
 165 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 166 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 167
 168   /* extension_opcode is the 3 bit extension for group <n> insns.
 169      This field is also used to store the 8-bit opcode suffix for the
 170      AMD 3DNow! instructions.
 171      If this template has no extension opcode (the usual case) use None */
 172   unsigned int extension_opcode;
 173 #define None 0xffff             /* If no extension_opcode is possible.  */
 174
 175   /* cpu feature flags */
 176   unsigned int cpu_flags;
 177 #define Cpu186            0x1   /* i186 or better required */
 178 #define Cpu286            0x2   /* i286 or better required */
 179 #define Cpu386            0x4   /* i386 or better required */
 180 #define Cpu486            0x8   /* i486 or better required */
 181 #define Cpu586           0x10   /* i585 or better required */
 182 #define Cpu686           0x20   /* i686 or better required */
 183 #define CpuP4            0x40   /* Pentium4 or better required */
 184 #define CpuK6            0x80   /* AMD K6 or better required*/
 185 #define CpuSledgehammer 0x100   /* Sledgehammer or better required */
 186 #define CpuMMX          0x200   /* MMX support required */
 187 #define CpuMMX2         0x400   /* extended MMX support (with SSE or 3DNow!Ext) required */
 188 #define CpuSSE          0x800   /* Streaming SIMD extensions required */
 189 #define CpuSSE2        0x1000   /* Streaming SIMD extensions 2 required */
 190 #define Cpu3dnow       0x2000   /* 3dnow! support required */
 191 #define Cpu3dnowA      0x4000   /* 3dnow!Extensions support required */
 192 #define CpuSSE3        0x8000   /* Streaming SIMD extensions 3 required */
 193 #define CpuPadLock    0x10000   /* VIA PadLock required */
 194 #define CpuSVME       0x20000   /* AMD Secure Virtual Machine Ext-s required */
 195 #define CpuVMX        0x40000   /* VMX Instructions required */
 196 #define CpuSSSE3      0x80000   /* Supplemental Streaming SIMD extensions 3 required */
 197 #define CpuSSE4a     0x100000   /* SSE4a New Instuctions required */
 198 #define CpuABM       0x200000   /* ABM New Instructions required */
 199
 200   /* These flags are set by gas depending on the flag_code.  */
 201 #define Cpu64        0x4000000   /* 64bit support required  */
 202 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 203
 204   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 205 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 206         |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
 207         |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
 208
 209   /* the bits in opcode_modifier are used to generate the final opcode from
 210      the base_opcode.  These bits also are used to detect alternate forms of
 211      the same instruction */
 212   unsigned int opcode_modifier;
 213
 214   /* opcode_modifier bits: */
 215 #define D                  0x1  /* has direction bit. */
 216 #define W                  0x2  /* set if operands can be words or dwords
 217                                    encoded the canonical way */
 218 #define Modrm              0x4  /* insn has a modrm byte. */
 219 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 220 #define Jump              0x40  /* special case for jump insns.  */
 221 #define JumpDword         0x80  /* call and jump */
 222 #define JumpByte         0x100  /* loop and jecxz */
 223 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 224 #define FloatMF          0x400  /* FP insn memory format bit, sized by 0x4 */
 225 #define FloatR           0x800  /* src/dest swap for floats. */
 226 #define FloatD          0x1000  /* has float insn direction bit. */
 227 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 228 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 229 #define Size64          0x8000  /* needs size prefix if in 64-bit mode */
 230 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 231 #define DefaultSize    0x20000  /* default insn size depends on mode */
 232 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 233 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 234 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 235 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 236 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 237 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 238 #define FWait        0x1000000  /* instruction needs FWAIT */
 239 #define IsString     0x2000000  /* quick test for string instructions */
 240 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 241 #define IsPrefix     0x8000000  /* opcode is a prefix */
 242 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 243 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 244 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 245 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 246
 247   /* operand_types[i] describes the type of operand i.  This is made
 248      by OR'ing together all of the possible type masks.  (e.g.
 249      'operand_types[i] = Reg|Imm' specifies that operand i can be
 250      either a register or an immediate operand.  */
 251   unsigned int operand_types[MAX_OPERANDS];
 252
 253   /* operand_types[i] bits */
 254   /* register */
 255 #define Reg8               0x1  /* 8 bit reg */
 256 #define Reg16              0x2  /* 16 bit reg */
 257 #define Reg32              0x4  /* 32 bit reg */
 258 #define Reg64              0x8  /* 64 bit reg */
 259   /* immediate */
 260 #define Imm8              0x10  /* 8 bit immediate */
 261 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 262 #define Imm16             0x40  /* 16 bit immediate */
 263 #define Imm32             0x80  /* 32 bit immediate */
 264 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 265 #define Imm64            0x200  /* 64 bit immediate */
 266 #define Imm1             0x400  /* 1 bit immediate */
 267   /* memory */
 268 #define BaseIndex        0x800
 269   /* Disp8,16,32 are used in different ways, depending on the
 270      instruction.  For jumps, they specify the size of the PC relative
 271      displacement, for baseindex type instructions, they specify the
 272      size of the offset relative to the base register, and for memory
 273      offset instructions such as `mov 1234,%al' they specify the size of
 274      the offset relative to the segment base.  */
 275 #define Disp8           0x1000  /* 8 bit displacement */
 276 #define Disp16          0x2000  /* 16 bit displacement */
 277 #define Disp32          0x4000  /* 32 bit displacement */
 278 #define Disp32S         0x8000  /* 32 bit signed displacement */
 279 #define Disp64         0x10000  /* 64 bit displacement */
 280   /* specials */
 281 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 282 #define ShiftCount     0x40000  /* register to hold shift count = cl */
 283 #define Control        0x80000  /* Control register */
 284 #define Debug         0x100000  /* Debug register */
 285 #define Test          0x200000  /* Test register */
 286 #define FloatReg      0x400000  /* Float register */
 287 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 288 #define SReg2        0x1000000  /* 2 bit segment register */
 289 #define SReg3        0x2000000  /* 3 bit segment register */
 290 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 291 #define JumpAbsolute 0x8000000
 292 #define RegMMX      0x10000000  /* MMX register */
 293 #define RegXMM      0x20000000  /* XMM registers in PIII */
 294 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 295
 296   /* InvMem is for instructions with a modrm byte that only allow a
 297      general register encoding in the i.tm.mode and i.tm.regmem fields,
 298      eg. control reg moves.  They really ought to support a memory form,
 299      but don't, so we add an InvMem flag to the register operand to
 300      indicate that it should be encoded in the i.tm.regmem field.  */
 301 #define InvMem      0x80000000
 302
 303 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 304 #define WordReg (Reg16|Reg32|Reg64)
 305 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 306 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 307 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 308 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 309 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 310   /* The following aliases are defined because the opcode table
 311      carefully specifies the allowed memory types for each instruction.
 312      At the moment we can only tell a memory reference size by the
 313      instruction suffix, so there's not much point in defining Mem8,
 314      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 315      the suffix directly to check memory operands.  */
 316 #define LLongMem AnyMem         /* 64 bits (or more) */
 317 #define LongMem AnyMem          /* 32 bit memory ref */
 318 #define ShortMem AnyMem         /* 16 bit memory ref */
 319 #define WordMem AnyMem          /* 16, 32 or 64 bit memory ref */
 320 #define ByteMem AnyMem          /* 8 bit memory ref */
 321 }
 322 template;
 323
 324 /*
 325   'templates' is for grouping together 'template' structures for opcodes
 326   of the same name.  This is only used for storing the insns in the grand
 327   ole hash table of insns.
 328   The templates themselves start at START and range up to (but not including)
 329   END.
 330   */
 331 typedef struct
 332 {
 333   const template *start;
 334   const template *end;
 335 }
 336 templates;
 337
 338 /* these are for register name --> number & type hash lookup */
 339 typedef struct
 340 {
 341   char *reg_name;
 342   unsigned int reg_type;
 343   unsigned int reg_flags;
 344 #define RegRex      0x1  /* Extended register.  */
 345 #define RegRex64    0x2  /* Extended 8 bit register.  */
 346   unsigned int reg_num;
 347 }
 348 reg_entry;
 349
 350 typedef struct
 351 {
 352   char *seg_name;
 353   unsigned int seg_prefix;
 354 }
 355 seg_entry;
 356
 357 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 358 typedef struct
 359 {
 360   unsigned int regmem;  /* codes register or memory operand */
 361   unsigned int reg;     /* codes register operand (or extended opcode) */
 362   unsigned int mode;    /* how to interpret regmem & reg */
 363 }
 364 modrm_byte;
 365
 366 /* x86-64 extension prefix.  */
 367 typedef int rex_byte;
 368 #define REX_OPCODE      0x40
 369
 370 /* Indicates 64 bit operand size.  */
 371 #define REX_MODE64      8
 372 /* High extension to reg field of modrm byte.  */
 373 #define REX_EXTX        4
 374 /* High extension to SIB index field.  */
 375 #define REX_EXTY        2
 376 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 377 #define REX_EXTZ        1
 378
 379 /* 386 opcode byte to code indirect addressing.  */
 380 typedef struct
 381 {
 382   unsigned base;
 383   unsigned index;
 384   unsigned scale;
 385 }
 386 sib_byte;
 387
 388 enum processor_type
 389 {
 390   PROCESSOR_UNKNOWN,
 391   PROCESSOR_I486,
 392   PROCESSOR_PENTIUM,
 393   PROCESSOR_PENTIUMPRO,
 394   PROCESSOR_PENTIUM4,
 395   PROCESSOR_NOCONA,
 396   PROCESSOR_CORE,
 397   PROCESSOR_CORE2,
 398   PROCESSOR_K6,
 399   PROCESSOR_ATHLON,
 400   PROCESSOR_K8,
 401   PROCESSOR_GENERIC32,
 402   PROCESSOR_GENERIC64,
 403   PROCESSOR_AMDFAM10
 404 };
 405
 406 /* x86 arch names, types and features */
 407 typedef struct
 408 {
 409   const char *name;             /* arch name */
 410   enum processor_type type;     /* arch type */
 411   unsigned int flags;           /* cpu feature flags */
 412 }
 413 arch_entry;
 414
 415 /* The name of the global offset table generated by the compiler. Allow
 416    this to be overridden if need be.  */
 417 #ifndef GLOBAL_OFFSET_TABLE_NAME
 418 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 419 #endif
 420
 421 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 422 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 423 extern void x86_cons (expressionS *, int);
 424 #endif
 425
 426 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 427 extern void x86_cons_fix_new
 428   (fragS *, unsigned int, unsigned int, expressionS *);
 429
 430 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 431
 432 #define NO_RELOC BFD_RELOC_NONE
 433
 434 void i386_validate_fix (struct fix *);
 435 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 436
 437 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 438 extern int tc_i386_fix_adjustable (struct fix *);
 439
 440 /* Values passed to md_apply_fix don't include the symbol value.  */
 441 #define MD_APPLY_SYM_VALUE(FIX) 0
 442
 443 /* ELF wants external syms kept, as does PE COFF.  */
 444 #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
 445 #define EXTERN_FORCE_RELOC                              \
 446   (OUTPUT_FLAVOR == bfd_target_elf_flavour              \
 447    || OUTPUT_FLAVOR == bfd_target_coff_flavour)
 448 #else
 449 #define EXTERN_FORCE_RELOC                              \
 450   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 451 #endif
 452
 453 /* This expression evaluates to true if the relocation is for a local
 454    object for which we still want to do the relocation at runtime.
 455    False if we are willing to perform this relocation while building
 456    the .o file.  GOTOFF does not need to be checked here because it is
 457    not pcrel.  I am not sure if some of the others are ever used with
 458    pcrel, but it is easier to be safe than sorry.  */
 459
 460 #define TC_FORCE_RELOCATION_LOCAL(FIX)                  \
 461   (!(FIX)->fx_pcrel                                     \
 462    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32           \
 463    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32           \
 464    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC           \
 465    || TC_FORCE_RELOCATION (FIX))
 466
 467 extern int i386_parse_name (char *, expressionS *, char *);
 468 #define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
 469
 470 extern const struct relax_type md_relax_table[];
 471 #define TC_GENERIC_RELAX_TABLE md_relax_table
 472
 473 extern int optimize_align_code;
 474
 475 #define md_do_align(n, fill, len, max, around)                          \
 476 if ((n)                                                                 \
 477     && !need_pass_2                                                     \
 478     && optimize_align_code                                              \
 479     && (!(fill)                                                         \
 480         || ((char)*(fill) == (char)0x90 && (len) == 1))                 \
 481     && subseg_text_p (now_seg))                                         \
 482   {                                                                     \
 483     frag_align_code ((n), (max));                                       \
 484     goto around;                                                        \
 485   }
 486
 487 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 488
 489 extern void i386_align_code (fragS *, int);
 490
 491 #define HANDLE_ALIGN(fragP)                                             \
 492 if (fragP->fr_type == rs_align_code)                                    \
 493   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 494                            - fragP->fr_address                          \
 495                            - fragP->fr_fix));
 496
 497 void i386_print_statistics (FILE *);
 498 #define tc_print_statistics i386_print_statistics
 499
 500 #define md_number_to_chars number_to_chars_littleendian
 501
 502 #ifdef SCO_ELF
 503 #define tc_init_after_args() sco_id ()
 504 extern void sco_id (void);
 505 #endif
 506
 507 #define WORKING_DOT_WORD 1
 508
 509 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 510 #define TARGET_USE_CFIPOP 1
 511
 512 extern unsigned int x86_dwarf2_return_column;
 513 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
 514
 515 extern int x86_cie_data_alignment;
 516 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 517
 518 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
 519 extern int tc_x86_regname_to_dw2regnum (char *);
 520
 521 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 522 extern void tc_x86_frame_initial_instructions (void);
 523
 524 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
 525 extern int i386_elf_section_type (const char *, size_t);
 526
 527 /* Support for SHF_X86_64_LARGE */
 528 extern int x86_64_section_word (char *, size_t);
 529 extern int x86_64_section_letter (int, char **);
 530 #define md_elf_section_letter(LETTER, PTR_MSG)  x86_64_section_letter (LETTER, PTR_MSG)
 531 #define md_elf_section_word(STR, LEN)           x86_64_section_word (STR, LEN)
 532
 533 #ifdef TE_PE
 534
 535 #define O_secrel O_md1
 536
 537 #define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
 538 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
 539
 540 #endif /* TE_PE */
 541
 542 #endif /* TC_I386 */