gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002, 2003, 2004, 2005
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 struct fix;
  27
  28 #define TARGET_BYTES_BIG_ENDIAN 0
  29
  30 #define TARGET_ARCH             bfd_arch_i386
  31 #define TARGET_MACH             (i386_mach ())
  32 extern unsigned long i386_mach (void);
  33
  34 #ifdef TE_FreeBSD
  35 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  36 #endif
  37 #ifdef TE_NetBSD
  38 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  39 #endif
  40 #ifdef TE_386BSD
  41 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  42 #endif
  43 #ifdef TE_LINUX
  44 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  45 #endif
  46 #ifdef TE_Mach
  47 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  48 #endif
  49 #ifdef TE_DYNIX
  50 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  51 #endif
  52 #ifndef AOUT_TARGET_FORMAT
  53 #define AOUT_TARGET_FORMAT      "a.out-i386"
  54 #endif
  55
  56 #ifdef TE_FreeBSD
  57 #define ELF_TARGET_FORMAT       "elf32-i386-freebsd"
  58 #elif defined (TE_VXWORKS)
  59 #define ELF_TARGET_FORMAT       "elf32-i386-vxworks"
  60 #endif
  61
  62 #ifndef ELF_TARGET_FORMAT
  63 #define ELF_TARGET_FORMAT       "elf32-i386"
  64 #endif
  65
  66 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  67      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  68 extern const char *i386_target_format PARAMS ((void));
  69 #define TARGET_FORMAT i386_target_format ()
  70 #else
  71 #ifdef OBJ_ELF
  72 #define TARGET_FORMAT           ELF_TARGET_FORMAT
  73 #endif
  74 #ifdef OBJ_AOUT
  75 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  76 #endif
  77 #endif
  78
  79 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  80 #define md_end i386_elf_emit_arch_note
  81 extern void i386_elf_emit_arch_note PARAMS ((void));
  82 #endif
  83
  84 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  85
  86 #define LOCAL_LABELS_FB 1
  87
  88 extern const char extra_symbol_chars[];
  89 #define tc_symbol_chars extra_symbol_chars
  90
  91 extern const char *i386_comment_chars;
  92 #define tc_comment_chars i386_comment_chars
  93
  94 #define MAX_OPERANDS 4          /* max operands per insn */
  95 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp, insertq, extrq) */
  96 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
  97
  98 /* Prefixes will be emitted in the order defined below.
  99    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 100    instruction, and so must come before any prefixes.  */
 101 #define WAIT_PREFIX     0
 102 #define LOCKREP_PREFIX  1
 103 #define ADDR_PREFIX     2
 104 #define DATA_PREFIX     3
 105 #define SEG_PREFIX      4
 106 #define REX_PREFIX      5       /* must come last.  */
 107 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 108
 109 /* we define the syntax here (modulo base,index,scale syntax) */
 110 #define REGISTER_PREFIX '%'
 111 #define IMMEDIATE_PREFIX '$'
 112 #define ABSOLUTE_PREFIX '*'
 113
 114 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 115 #define NOP_OPCODE (char) 0x90
 116
 117 /* register numbers */
 118 #define EBP_REG_NUM 5
 119 #define ESP_REG_NUM 4
 120
 121 /* modrm_byte.regmem for twobyte escape */
 122 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 123 /* index_base_byte.index for no index register addressing */
 124 #define NO_INDEX_REGISTER ESP_REG_NUM
 125 /* index_base_byte.base for no base register addressing */
 126 #define NO_BASE_REGISTER EBP_REG_NUM
 127 #define NO_BASE_REGISTER_16 6
 128
 129 /* these are the instruction mnemonic suffixes.  */
 130 #define WORD_MNEM_SUFFIX  'w'
 131 #define BYTE_MNEM_SUFFIX  'b'
 132 #define SHORT_MNEM_SUFFIX 's'
 133 #define LONG_MNEM_SUFFIX  'l'
 134 #define QWORD_MNEM_SUFFIX  'q'
 135 /* Intel Syntax */
 136 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 137
 138 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 139 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 140 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 141
 142 #define END_OF_INSN '\0'
 143
 144 typedef struct
 145 {
 146   /* instruction name sans width suffix ("mov" for movl insns) */
 147   char *name;
 148
 149   /* how many operands */
 150   unsigned int operands;
 151
 152   /* base_opcode is the fundamental opcode byte without optional
 153      prefix(es).  */
 154   unsigned int base_opcode;
 155
 156   /* extension_opcode is the 3 bit extension for group <n> insns.
 157      This field is also used to store the 8-bit opcode suffix for the
 158      AMD 3DNow! instructions.
 159      If this template has no extension opcode (the usual case) use None */
 160   unsigned int extension_opcode;
 161 #define None 0xffff             /* If no extension_opcode is possible.  */
 162
 163   /* cpu feature flags */
 164   unsigned int cpu_flags;
 165 #define Cpu186            0x1   /* i186 or better required */
 166 #define Cpu286            0x2   /* i286 or better required */
 167 #define Cpu386            0x4   /* i386 or better required */
 168 #define Cpu486            0x8   /* i486 or better required */
 169 #define Cpu586           0x10   /* i585 or better required */
 170 #define Cpu686           0x20   /* i686 or better required */
 171 #define CpuP4            0x40   /* Pentium4 or better required */
 172 #define CpuK6            0x80   /* AMD K6 or better required*/
 173 #define CpuSledgehammer 0x100   /* Sledgehammer or better required */
 174 #define CpuMMX          0x200   /* MMX support required */
 175 #define CpuMMX2         0x400   /* extended MMX support (with SSE or 3DNow!Ext) required */
 176 #define CpuSSE          0x800   /* Streaming SIMD extensions required */
 177 #define CpuSSE2        0x1000   /* Streaming SIMD extensions 2 required */
 178 #define Cpu3dnow       0x2000   /* 3dnow! support required */
 179 #define Cpu3dnowA      0x4000   /* 3dnow!Extensions support required */
 180 #define CpuSSE3        0x8000   /* Streaming SIMD extensions 3 required */
 181 #define CpuPNI        CpuSSE3   /* Prescott New Instructions required */
 182 #define CpuPadLock    0x10000   /* VIA PadLock required */
 183 #define CpuSVME       0x20000   /* AMD Secure Virtual Machine Ext-s required */
 184 #define CpuVMX        0x40000   /* VMX Instructions required */
 185 #define CpuMNI        0x80000   /* Merom New Instructions required */
 186 #define CpuSSE4a     0x100000   /* SSE4a New Instuctions required */
 187 #define CpuABM       0x200000   /* ABM New Instructions required */
 188
 189   /* These flags are set by gas depending on the flag_code.  */
 190 #define Cpu64        0x4000000   /* 64bit support required  */
 191 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 192
 193   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 194 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 195         |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
 196         |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
 197
 198   /* the bits in opcode_modifier are used to generate the final opcode from
 199      the base_opcode.  These bits also are used to detect alternate forms of
 200      the same instruction */
 201   unsigned int opcode_modifier;
 202
 203   /* opcode_modifier bits: */
 204 #define W                  0x1  /* set if operands can be words or dwords
 205                                    encoded the canonical way */
 206 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 207                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 208 #define Modrm              0x4
 209 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 210 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 211 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 212 #define Jump              0x40  /* special case for jump insns.  */
 213 #define JumpDword         0x80  /* call and jump */
 214 #define JumpByte         0x100  /* loop and jecxz */
 215 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 216 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 217 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 218 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 219 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 220 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 221 #define Size64          0x8000  /* needs size prefix if in 64-bit mode */
 222 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 223 #define DefaultSize    0x20000  /* default insn size depends on mode */
 224 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 225 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 226 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 227 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 228 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 229 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 230 #define FWait        0x1000000  /* instruction needs FWAIT */
 231 #define IsString     0x2000000  /* quick test for string instructions */
 232 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 233 #define IsPrefix     0x8000000  /* opcode is a prefix */
 234 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 235 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 236 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 237 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 238
 239   /* operand_types[i] describes the type of operand i.  This is made
 240      by OR'ing together all of the possible type masks.  (e.g.
 241      'operand_types[i] = Reg|Imm' specifies that operand i can be
 242      either a register or an immediate operand.  */
 243   unsigned int operand_types[4];
 244
 245   /* operand_types[i] bits */
 246   /* register */
 247 #define Reg8               0x1  /* 8 bit reg */
 248 #define Reg16              0x2  /* 16 bit reg */
 249 #define Reg32              0x4  /* 32 bit reg */
 250 #define Reg64              0x8  /* 64 bit reg */
 251   /* immediate */
 252 #define Imm8              0x10  /* 8 bit immediate */
 253 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 254 #define Imm16             0x40  /* 16 bit immediate */
 255 #define Imm32             0x80  /* 32 bit immediate */
 256 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 257 #define Imm64            0x200  /* 64 bit immediate */
 258 #define Imm1             0x400  /* 1 bit immediate */
 259   /* memory */
 260 #define BaseIndex        0x800
 261   /* Disp8,16,32 are used in different ways, depending on the
 262      instruction.  For jumps, they specify the size of the PC relative
 263      displacement, for baseindex type instructions, they specify the
 264      size of the offset relative to the base register, and for memory
 265      offset instructions such as `mov 1234,%al' they specify the size of
 266      the offset relative to the segment base.  */
 267 #define Disp8           0x1000  /* 8 bit displacement */
 268 #define Disp16          0x2000  /* 16 bit displacement */
 269 #define Disp32          0x4000  /* 32 bit displacement */
 270 #define Disp32S         0x8000  /* 32 bit signed displacement */
 271 #define Disp64         0x10000  /* 64 bit displacement */
 272   /* specials */
 273 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 274 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 275 #define Control        0x80000  /* Control register */
 276 #define Debug         0x100000  /* Debug register */
 277 #define Test          0x200000  /* Test register */
 278 #define FloatReg      0x400000  /* Float register */
 279 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 280 #define SReg2        0x1000000  /* 2 bit segment register */
 281 #define SReg3        0x2000000  /* 3 bit segment register */
 282 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 283 #define JumpAbsolute 0x8000000
 284 #define RegMMX      0x10000000  /* MMX register */
 285 #define RegXMM      0x20000000  /* XMM registers in PIII */
 286 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 287
 288   /* InvMem is for instructions with a modrm byte that only allow a
 289      general register encoding in the i.tm.mode and i.tm.regmem fields,
 290      eg. control reg moves.  They really ought to support a memory form,
 291      but don't, so we add an InvMem flag to the register operand to
 292      indicate that it should be encoded in the i.tm.regmem field.  */
 293 #define InvMem      0x80000000
 294
 295 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 296 #define WordReg (Reg16|Reg32|Reg64)
 297 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 298 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 299 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 300 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 301 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 302   /* The following aliases are defined because the opcode table
 303      carefully specifies the allowed memory types for each instruction.
 304      At the moment we can only tell a memory reference size by the
 305      instruction suffix, so there's not much point in defining Mem8,
 306      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 307      the suffix directly to check memory operands.  */
 308 #define LLongMem AnyMem         /* 64 bits (or more) */
 309 #define LongMem AnyMem          /* 32 bit memory ref */
 310 #define ShortMem AnyMem         /* 16 bit memory ref */
 311 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 312 #define ByteMem AnyMem          /* 8 bit memory ref */
 313 }
 314 template;
 315
 316 /*
 317   'templates' is for grouping together 'template' structures for opcodes
 318   of the same name.  This is only used for storing the insns in the grand
 319   ole hash table of insns.
 320   The templates themselves start at START and range up to (but not including)
 321   END.
 322   */
 323 typedef struct
 324 {
 325   const template *start;
 326   const template *end;
 327 }
 328 templates;
 329
 330 /* these are for register name --> number & type hash lookup */
 331 typedef struct
 332 {
 333   char *reg_name;
 334   unsigned int reg_type;
 335   unsigned int reg_flags;
 336 #define RegRex      0x1  /* Extended register.  */
 337 #define RegRex64    0x2  /* Extended 8 bit register.  */
 338   unsigned int reg_num;
 339 }
 340 reg_entry;
 341
 342 typedef struct
 343 {
 344   char *seg_name;
 345   unsigned int seg_prefix;
 346 }
 347 seg_entry;
 348
 349 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 350 typedef struct
 351 {
 352   unsigned int regmem;  /* codes register or memory operand */
 353   unsigned int reg;     /* codes register operand (or extended opcode) */
 354   unsigned int mode;    /* how to interpret regmem & reg */
 355 }
 356 modrm_byte;
 357
 358 /* x86-64 extension prefix.  */
 359 typedef int rex_byte;
 360 #define REX_OPCODE      0x40
 361
 362 /* Indicates 64 bit operand size.  */
 363 #define REX_MODE64      8
 364 /* High extension to reg field of modrm byte.  */
 365 #define REX_EXTX        4
 366 /* High extension to SIB index field.  */
 367 #define REX_EXTY        2
 368 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 369 #define REX_EXTZ        1
 370
 371 /* 386 opcode byte to code indirect addressing.  */
 372 typedef struct
 373 {
 374   unsigned base;
 375   unsigned index;
 376   unsigned scale;
 377 }
 378 sib_byte;
 379
 380 enum processor_type
 381 {
 382   PROCESSOR_UNKNOWN,
 383   PROCESSOR_I486,
 384   PROCESSOR_PENTIUM,
 385   PROCESSOR_PENTIUMPRO,
 386   PROCESSOR_PENTIUM4,
 387   PROCESSOR_NOCONA,
 388   PROCESSOR_YONAH,
 389   PROCESSOR_MEROM,
 390   PROCESSOR_K6,
 391   PROCESSOR_ATHLON,
 392   PROCESSOR_K8,
 393   PROCESSOR_GENERIC32,
 394   PROCESSOR_GENERIC64,
 395   PROCESSOR_AMDFAM10
 396 };
 397
 398 /* x86 arch names, types and features */
 399 typedef struct
 400 {
 401   const char *name;             /* arch name */
 402   enum processor_type type;     /* arch type */
 403   unsigned int flags;           /* cpu feature flags */
 404 }
 405 arch_entry;
 406
 407 /* The name of the global offset table generated by the compiler. Allow
 408    this to be overridden if need be.  */
 409 #ifndef GLOBAL_OFFSET_TABLE_NAME
 410 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 411 #endif
 412
 413 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 414 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 415 extern void x86_cons PARAMS ((expressionS *, int));
 416 #endif
 417
 418 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 419 extern void x86_cons_fix_new
 420   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 421
 422 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 423
 424 #define NO_RELOC BFD_RELOC_NONE
 425
 426 void i386_validate_fix PARAMS ((struct fix *));
 427 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 428
 429 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 430 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 431
 432 /* Values passed to md_apply_fix don't include the symbol value.  */
 433 #define MD_APPLY_SYM_VALUE(FIX) 0
 434
 435 /* ELF wants external syms kept, as does PE COFF.  */
 436 #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
 437 #define EXTERN_FORCE_RELOC                              \
 438   (OUTPUT_FLAVOR == bfd_target_elf_flavour              \
 439    || OUTPUT_FLAVOR == bfd_target_coff_flavour)
 440 #else
 441 #define EXTERN_FORCE_RELOC                              \
 442   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 443 #endif
 444
 445 /* This expression evaluates to true if the relocation is for a local
 446    object for which we still want to do the relocation at runtime.
 447    False if we are willing to perform this relocation while building
 448    the .o file.  GOTOFF does not need to be checked here because it is
 449    not pcrel.  I am not sure if some of the others are ever used with
 450    pcrel, but it is easier to be safe than sorry.  */
 451
 452 #define TC_FORCE_RELOCATION_LOCAL(FIX)                  \
 453   (!(FIX)->fx_pcrel                                     \
 454    || (FIX)->fx_plt                                     \
 455    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32           \
 456    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32           \
 457    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC           \
 458    || TC_FORCE_RELOCATION (FIX))
 459
 460 extern int i386_parse_name (char *, expressionS *, char *);
 461 #define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
 462
 463 extern const struct relax_type md_relax_table[];
 464 #define TC_GENERIC_RELAX_TABLE md_relax_table
 465
 466 extern int optimize_align_code;
 467
 468 #define md_do_align(n, fill, len, max, around)                          \
 469 if ((n)                                                                 \
 470     && !need_pass_2                                                     \
 471     && optimize_align_code                                              \
 472     && (!(fill)                                                         \
 473         || ((char)*(fill) == (char)0x90 && (len) == 1))                 \
 474     && subseg_text_p (now_seg))                                         \
 475   {                                                                     \
 476     frag_align_code ((n), (max));                                       \
 477     goto around;                                                        \
 478   }
 479
 480 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 481
 482 extern void i386_align_code PARAMS ((fragS *, int));
 483
 484 #define HANDLE_ALIGN(fragP)                                             \
 485 if (fragP->fr_type == rs_align_code)                                    \
 486   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 487                            - fragP->fr_address                          \
 488                            - fragP->fr_fix));
 489
 490 void i386_print_statistics PARAMS ((FILE *));
 491 #define tc_print_statistics i386_print_statistics
 492
 493 #define md_number_to_chars number_to_chars_littleendian
 494
 495 #ifdef SCO_ELF
 496 #define tc_init_after_args() sco_id ()
 497 extern void sco_id PARAMS ((void));
 498 #endif
 499
 500 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 501 #define TARGET_USE_CFIPOP 1
 502
 503 extern unsigned int x86_dwarf2_return_column;
 504 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
 505
 506 extern int x86_cie_data_alignment;
 507 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 508
 509 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
 510 extern int tc_x86_regname_to_dw2regnum PARAMS ((char *regname));
 511
 512 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 513 extern void tc_x86_frame_initial_instructions PARAMS ((void));
 514
 515 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
 516 extern int i386_elf_section_type PARAMS ((const char *, size_t len));
 517
 518 /* Support for SHF_X86_64_LARGE */
 519 extern int x86_64_section_word PARAMS ((char *, size_t));
 520 extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg));
 521 #define md_elf_section_letter(LETTER, PTR_MSG)  x86_64_section_letter (LETTER, PTR_MSG)
 522 #define md_elf_section_word(STR, LEN)           x86_64_section_word (STR, LEN)
 523
 524 #ifdef TE_PE
 525
 526 #define O_secrel O_md1
 527
 528 #define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
 529 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
 530
 531 #endif /* TE_PE */
 532
 533 #endif /* TC_I386 */