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Locale changes from Bruno Haible <haible@clisp.cons.org>.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "obstack.h"
26 #include "subsegs.h"
27 #include "dwarf2dbg.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars = "|#";
42 #else
43 const char *m68k_comment_chars = "|";
44 #endif
45
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#*";
54
55 const char line_separator_chars[] = ";";
56
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 CONST char EXP_CHARS[] = "eE";
59
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69 const int md_reloc_size = 8; /* Size of relocation record */
70
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
75 int flag_want_pic;
76
77 static int flag_short_refs; /* -l option */
78 static int flag_long_jumps; /* -S option */
79 static int flag_keep_pcrel; /* --pcrel option. */
80
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83 #else
84 int flag_reg_prefix_optional;
85 #endif
86
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen;
89
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum = COP1;
92
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd;
96
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick = 1;
100
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104 static int m68k_rel32 = 1;
105
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline;
108
109 /* The default width to use for an index register when using a base
110 displacement. */
111 static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117 struct label_line
118 {
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124 };
125
126 /* The list of labels. */
127
128 static struct label_line *labels;
129
130 /* The current label. */
131
132 static struct label_line *current_label;
133
134 /* Its an arbitrary name: This means I don't approve of it */
135 /* See flames below */
136 static struct obstack robyn;
137
138 struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149 #define gettwo(x) (((x)->m_opcode)&0xffff)
150
151 static const enum m68k_register m68000_control_regs[] = { 0 };
152 static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155 };
156 static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159 };
160 static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164 };
165 static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169 };
170 static const enum m68k_register mcf_control_regs[] = {
171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
172 RAMBAR0, RAMBAR1, MBAR,
173 0
174 };
175 #define cpu32_control_regs m68010_control_regs
176
177 static const enum m68k_register *control_regs;
178
179 /* internal form of a 68020 instruction */
180 struct m68k_it
181 {
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219 #ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223 #endif
224 }
225 reloc[5]; /* Five is enough??? */
226 };
227
228 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
229 #define float_of_arch(x) ((x) & mfloat)
230 #define mmu_of_arch(x) ((x) & mmmu)
231 #define arch_coldfire_p(x) (((x) & mcf) != 0)
232
233 /* Macros for determining if cpu supports a specific addressing mode */
234 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
235
236 static struct m68k_it the_ins; /* the instruction being assembled */
237
238 #define op(ex) ((ex)->exp.X_op)
239 #define adds(ex) ((ex)->exp.X_add_symbol)
240 #define subs(ex) ((ex)->exp.X_op_symbol)
241 #define offs(ex) ((ex)->exp.X_add_number)
242
243 /* Macros for adding things to the m68k_it struct */
244
245 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247 /* Static functions. */
248
249 static void insop PARAMS ((int, const struct m68k_incant *));
250 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251 static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253 /* Like addword, but goes BEFORE general operands */
254 static void
255 insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258 {
259 int z;
260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
261 the_ins.opcode[z]=the_ins.opcode[z-1];
262 for (z = 0;z < the_ins.nrel; z++)
263 the_ins.reloc[z].n+=2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum]=w;
267 the_ins.numo++;
268 }
269
270 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272 static void
273 add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278 {
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287 #ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289 #endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291 }
292
293 /* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303 static void
304 add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308 {
309 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd=add;
311 the_ins.fragb[the_ins.nfrag].foff=off;
312 the_ins.fragb[the_ins.nfrag++].fragty=type;
313 }
314
315 #define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320 static void m68k_ip PARAMS ((char *));
321 static void insert_reg PARAMS ((const char *, int));
322 static void select_control_regs PARAMS ((void));
323 static void init_regtable PARAMS ((void));
324 static int reverse_16_bits PARAMS ((int in));
325 static int reverse_8_bits PARAMS ((int in));
326 static void install_gen_operand PARAMS ((int mode, int val));
327 static void install_operand PARAMS ((int mode, int val));
328 static void s_bss PARAMS ((int));
329 static void s_data1 PARAMS ((int));
330 static void s_data2 PARAMS ((int));
331 static void s_even PARAMS ((int));
332 static void s_proc PARAMS ((int));
333 static void mri_chip PARAMS ((void));
334 static void s_chip PARAMS ((int));
335 static void s_fopt PARAMS ((int));
336 static void s_opt PARAMS ((int));
337 static void s_reg PARAMS ((int));
338 static void s_restore PARAMS ((int));
339 static void s_save PARAMS ((int));
340 static void s_mri_if PARAMS ((int));
341 static void s_mri_else PARAMS ((int));
342 static void s_mri_endi PARAMS ((int));
343 static void s_mri_break PARAMS ((int));
344 static void s_mri_next PARAMS ((int));
345 static void s_mri_for PARAMS ((int));
346 static void s_mri_endf PARAMS ((int));
347 static void s_mri_repeat PARAMS ((int));
348 static void s_mri_until PARAMS ((int));
349 static void s_mri_while PARAMS ((int));
350 static void s_mri_endw PARAMS ((int));
351 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
352 static void md_convert_frag_1 PARAMS ((fragS *));
353
354 static int current_architecture;
355
356 struct m68k_cpu
357 {
358 unsigned long arch;
359 const char *name;
360 int alias;
361 };
362
363 static const struct m68k_cpu archs[] =
364 {
365 { m68000, "68000", 0 },
366 { m68010, "68010", 0 },
367 { m68020, "68020", 0 },
368 { m68030, "68030", 0 },
369 { m68040, "68040", 0 },
370 { m68060, "68060", 0 },
371 { cpu32, "cpu32", 0 },
372 { m68881, "68881", 0 },
373 { m68851, "68851", 0 },
374 { mcf5200, "5200", 0 },
375 { mcf5206e, "5206e", 0 },
376 { mcf5307, "5307", 0},
377 { mcf5407, "5407", 0},
378 /* Aliases (effectively, so far as gas is concerned) for the above
379 cpus. */
380 { m68020, "68k", 1 },
381 { m68000, "68008", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68306", 1 },
384 { m68000, "68307", 1 },
385 { m68000, "68322", 1 },
386 { m68000, "68356", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68334", 1 },
399 { cpu32, "68336", 1 },
400 { cpu32, "68340", 1 },
401 { cpu32, "68341", 1 },
402 { cpu32, "68349", 1 },
403 { cpu32, "68360", 1 },
404 { m68881, "68882", 1 },
405 { mcf5200, "5202", 1 },
406 { mcf5200, "5204", 1 },
407 { mcf5200, "5206", 1 },
408 };
409
410 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411
412 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
413 architecture and we have a lot of relaxation modes. */
414
415 /* Macros used in the relaxation code. */
416 #define TAB(x,y) (((x) << 2) + (y))
417 #define TABTYPE(x) ((x) >> 2)
418
419 /* Relaxation states. */
420 #define BYTE 0
421 #define SHORT 1
422 #define LONG 2
423 #define SZ_UNDEF 3
424
425 /* Here are all the relaxation modes we support. First we can relax ordinary
426 branches. On 68020 and higher and on CPU32 all branch instructions take
427 three forms, so on these CPUs all branches always remain as such. When we
428 have to expand to the LONG form on a 68000, though, we substitute an
429 absolute jump instead. This is a direct replacement for unconditional
430 branches and a branch over a jump for conditional branches. However, if the
431 user requires PIC and disables this with --pcrel, we can only relax between
432 BYTE and SHORT forms, punting if that isn't enough. This gives us four
433 different relaxation modes for branches: */
434
435 #define BRANCHBWL 0 /* branch byte, word, or long */
436 #define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
437 #define BRABSJCOND 2 /* absolute jump for LONG, conditional */
438 #define BRANCHBW 3 /* branch byte or word */
439
440 /* We also relax coprocessor branches and DBcc's. All CPUs that support
441 coprocessor branches support them in word and long forms, so we have only
442 one relaxation mode for them. DBcc's are word only on all CPUs. We can
443 relax them to the LONG form with a branch-around sequence. This sequence
444 can use a long branch (if available) or an absolute jump (if acceptable).
445 This gives us two relaxation modes. If long branches are not available and
446 absolute jumps are not acceptable, we don't relax DBcc's. */
447
448 #define FBRANCH 4 /* coprocessor branch */
449 #define DBCCLBR 5 /* DBcc relaxable with a long branch */
450 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
451
452 /* That's all for instruction relaxation. However, we also relax PC-relative
453 operands. Specifically, we have three operand relaxation modes. On the
454 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
455 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
456 two. Also PC+displacement+index operands in their simple form (with a non-
457 suppressed index without memory indirection) are supported on all CPUs, but
458 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
459 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
460 form of the PC+displacement+index operand. Finally, some absolute operands
461 can be relaxed down to 16-bit PC-relative. */
462
463 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
464 #define PCINDEX 8 /* PC+displacement+index */
465 #define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
466
467 /* Note that calls to frag_var need to specify the maximum expansion
468 needed; this is currently 10 bytes for DBCC. */
469
470 /* The fields are:
471 How far Forward this mode will reach:
472 How far Backward this mode will reach:
473 How many bytes this mode will add to the size of the frag
474 Which mode to go to if the offset won't fit in this one
475 */
476 relax_typeS md_relax_table[] =
477 {
478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
480 { 0, 0, 4, 0 },
481 { 1, 1, 0, 0 },
482
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
485 { 0, 0, 4, 0 },
486 { 1, 1, 0, 0 },
487
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
490 { 0, 0, 6, 0 },
491 { 1, 1, 0, 0 },
492
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
494 { 0, 0, 2, 0 },
495 { 1, 1, 0, 0 },
496 { 1, 1, 0, 0 },
497
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
500 { 0, 0, 4, 0 },
501 { 1, 1, 0, 0 },
502
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
505 { 0, 0, 10, 0 },
506 { 1, 1, 0, 0 },
507
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
510 { 0, 0, 10, 0 },
511 { 1, 1, 0, 0 },
512
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
520 { 0, 0, 4, 0 },
521 { 1, 1, 0, 0 },
522
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
527 };
528
529 /* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534 /* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540 const pseudo_typeS md_pseudo_table[] =
541 {
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548 #if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550 #endif
551 #ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553 #endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557 #ifdef OBJ_ELF
558 /* Dwarf2 support for Gcc. */
559 {"file", dwarf2_directive_file, 0},
560 {"loc", dwarf2_directive_loc, 0},
561 #endif
562
563 /* The following pseudo-ops are supported for MRI compatibility. */
564 {"chip", s_chip, 0},
565 {"comline", s_space, 1},
566 {"fopt", s_fopt, 0},
567 {"mask2", s_ignore, 0},
568 {"opt", s_opt, 0},
569 {"reg", s_reg, 0},
570 {"restore", s_restore, 0},
571 {"save", s_save, 0},
572
573 {"if", s_mri_if, 0},
574 {"if.b", s_mri_if, 'b'},
575 {"if.w", s_mri_if, 'w'},
576 {"if.l", s_mri_if, 'l'},
577 {"else", s_mri_else, 0},
578 {"else.s", s_mri_else, 's'},
579 {"else.l", s_mri_else, 'l'},
580 {"endi", s_mri_endi, 0},
581 {"break", s_mri_break, 0},
582 {"break.s", s_mri_break, 's'},
583 {"break.l", s_mri_break, 'l'},
584 {"next", s_mri_next, 0},
585 {"next.s", s_mri_next, 's'},
586 {"next.l", s_mri_next, 'l'},
587 {"for", s_mri_for, 0},
588 {"for.b", s_mri_for, 'b'},
589 {"for.w", s_mri_for, 'w'},
590 {"for.l", s_mri_for, 'l'},
591 {"endf", s_mri_endf, 0},
592 {"repeat", s_mri_repeat, 0},
593 {"until", s_mri_until, 0},
594 {"until.b", s_mri_until, 'b'},
595 {"until.w", s_mri_until, 'w'},
596 {"until.l", s_mri_until, 'l'},
597 {"while", s_mri_while, 0},
598 {"while.b", s_mri_while, 'b'},
599 {"while.w", s_mri_while, 'w'},
600 {"while.l", s_mri_while, 'l'},
601 {"endw", s_mri_endw, 0},
602
603 {0, 0, 0}
604 };
605
606 /* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
608 */
609
610 #ifdef M68KCOFF
611 extern void obj_coff_section PARAMS ((int));
612 #endif
613
614 CONST pseudo_typeS mote_pseudo_table[] =
615 {
616
617 {"dcl", cons, 4},
618 {"dc", cons, 2},
619 {"dcw", cons, 2},
620 {"dcb", cons, 1},
621
622 {"dsl", s_space, 4},
623 {"ds", s_space, 2},
624 {"dsw", s_space, 2},
625 {"dsb", s_space, 1},
626
627 {"xdef", s_globl, 0},
628 #ifdef OBJ_ELF
629 {"align", s_align_bytes, 0},
630 #else
631 {"align", s_align_ptwo, 0},
632 #endif
633 #ifdef M68KCOFF
634 {"sect", obj_coff_section, 0},
635 {"section", obj_coff_section, 0},
636 #endif
637 {0, 0, 0}
638 };
639
640 #define issbyte(x) ((x)>=-128 && (x)<=127)
641 #define isubyte(x) ((x)>=0 && (x)<=255)
642 #define issword(x) ((x)>=-32768 && (x)<=32767)
643 #define isuword(x) ((x)>=0 && (x)<=65535)
644
645 #define isbyte(x) ((x)>= -255 && (x)<=255)
646 #define isword(x) ((x)>=-65536 && (x)<=65535)
647 #define islong(x) (1)
648
649 extern char *input_line_pointer;
650
651 static char notend_table[256];
652 static char alt_notend_table[256];
653 #define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660 #ifdef NO_PCREL_RELOCS
661
662 int
663 make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666 {
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687 }
688
689 #endif /* NO_PCREL_RELOCS */
690
691 short
692 tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694 {
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697 #ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702 #else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710 #endif
711 }
712
713 #endif
714
715 #ifdef OBJ_ELF
716
717 /* Return zero if the reference to SYMBOL from within the same segment may
718 be relaxed. */
719
720 /* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
725
726 #define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
729
730 /* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
733
734 static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
736
737 static bfd_reloc_code_real_type
738 get_reloc_code (size, pcrel, pic)
739 int size;
740 int pcrel;
741 enum pic_relocation pic;
742 {
743 switch (pic)
744 {
745 case pic_got_pcrel:
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_GOT_PCREL;
750 case 2:
751 return BFD_RELOC_16_GOT_PCREL;
752 case 4:
753 return BFD_RELOC_32_GOT_PCREL;
754 }
755 break;
756
757 case pic_got_off:
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8_GOTOFF;
762 case 2:
763 return BFD_RELOC_16_GOTOFF;
764 case 4:
765 return BFD_RELOC_32_GOTOFF;
766 }
767 break;
768
769 case pic_plt_pcrel:
770 switch (size)
771 {
772 case 1:
773 return BFD_RELOC_8_PLT_PCREL;
774 case 2:
775 return BFD_RELOC_16_PLT_PCREL;
776 case 4:
777 return BFD_RELOC_32_PLT_PCREL;
778 }
779 break;
780
781 case pic_plt_off:
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PLTOFF;
786 case 2:
787 return BFD_RELOC_16_PLTOFF;
788 case 4:
789 return BFD_RELOC_32_PLTOFF;
790 }
791 break;
792
793 case pic_none:
794 if (pcrel)
795 {
796 switch (size)
797 {
798 case 1:
799 return BFD_RELOC_8_PCREL;
800 case 2:
801 return BFD_RELOC_16_PCREL;
802 case 4:
803 return BFD_RELOC_32_PCREL;
804 }
805 }
806 else
807 {
808 switch (size)
809 {
810 case 1:
811 return BFD_RELOC_8;
812 case 2:
813 return BFD_RELOC_16;
814 case 4:
815 return BFD_RELOC_32;
816 }
817 }
818 }
819
820 if (pcrel)
821 {
822 if (pic == pic_none)
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
824 else
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
826 }
827 else
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pic relocation"), size);
833 }
834
835 return BFD_RELOC_NONE;
836 }
837
838 /* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
842 used. */
843 int
844 tc_m68k_fix_adjustable (fixP)
845 fixS *fixP;
846 {
847 /* Prevent all adjustments to global symbols. */
848 if (! relaxable_symbol (fixP->fx_addsy))
849 return 0;
850
851 /* adjust_reloc_syms doesn't know about the GOT */
852 switch (fixP->fx_r_type)
853 {
854 case BFD_RELOC_8_GOT_PCREL:
855 case BFD_RELOC_16_GOT_PCREL:
856 case BFD_RELOC_32_GOT_PCREL:
857 case BFD_RELOC_8_GOTOFF:
858 case BFD_RELOC_16_GOTOFF:
859 case BFD_RELOC_32_GOTOFF:
860 case BFD_RELOC_8_PLT_PCREL:
861 case BFD_RELOC_16_PLT_PCREL:
862 case BFD_RELOC_32_PLT_PCREL:
863 case BFD_RELOC_8_PLTOFF:
864 case BFD_RELOC_16_PLTOFF:
865 case BFD_RELOC_32_PLTOFF:
866 return 0;
867
868 case BFD_RELOC_VTABLE_INHERIT:
869 case BFD_RELOC_VTABLE_ENTRY:
870 return 0;
871
872 default:
873 return 1;
874 }
875 }
876
877 #else /* !OBJ_ELF */
878
879 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
880
881 #define relaxable_symbol(symbol) 1
882
883 #endif /* OBJ_ELF */
884
885 #ifdef BFD_ASSEMBLER
886
887 arelent *
888 tc_gen_reloc (section, fixp)
889 asection *section;
890 fixS *fixp;
891 {
892 arelent *reloc;
893 bfd_reloc_code_real_type code;
894
895 /* If the tcbit is set, then this was a fixup of a negative value
896 that was never resolved. We do not have a reloc to handle this,
897 so just return. We assume that other code will have detected this
898 situation and produced a helpful error message, so we just tell the
899 user that the reloc cannot be produced. */
900 if (fixp->fx_tcbit)
901 {
902 if (fixp->fx_addsy)
903 as_bad_where (fixp->fx_file, fixp->fx_line,
904 _("Unable to produce reloc against symbol '%s'"),
905 S_GET_NAME (fixp->fx_addsy));
906 return NULL;
907 }
908
909 if (fixp->fx_r_type != BFD_RELOC_NONE)
910 {
911 code = fixp->fx_r_type;
912
913 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
914 that fixup_segment converted a non-PC relative reloc into a
915 PC relative reloc. In such a case, we need to convert the
916 reloc code. */
917 if (fixp->fx_pcrel)
918 {
919 switch (code)
920 {
921 case BFD_RELOC_8:
922 code = BFD_RELOC_8_PCREL;
923 break;
924 case BFD_RELOC_16:
925 code = BFD_RELOC_16_PCREL;
926 break;
927 case BFD_RELOC_32:
928 code = BFD_RELOC_32_PCREL;
929 break;
930 case BFD_RELOC_8_PCREL:
931 case BFD_RELOC_16_PCREL:
932 case BFD_RELOC_32_PCREL:
933 case BFD_RELOC_8_GOT_PCREL:
934 case BFD_RELOC_16_GOT_PCREL:
935 case BFD_RELOC_32_GOT_PCREL:
936 case BFD_RELOC_8_GOTOFF:
937 case BFD_RELOC_16_GOTOFF:
938 case BFD_RELOC_32_GOTOFF:
939 case BFD_RELOC_8_PLT_PCREL:
940 case BFD_RELOC_16_PLT_PCREL:
941 case BFD_RELOC_32_PLT_PCREL:
942 case BFD_RELOC_8_PLTOFF:
943 case BFD_RELOC_16_PLTOFF:
944 case BFD_RELOC_32_PLTOFF:
945 break;
946 default:
947 as_bad_where (fixp->fx_file, fixp->fx_line,
948 _("Cannot make %s relocation PC relative"),
949 bfd_get_reloc_code_name (code));
950 }
951 }
952 }
953 else
954 {
955 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
956 switch (F (fixp->fx_size, fixp->fx_pcrel))
957 {
958 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
959 MAP (1, 0, BFD_RELOC_8);
960 MAP (2, 0, BFD_RELOC_16);
961 MAP (4, 0, BFD_RELOC_32);
962 MAP (1, 1, BFD_RELOC_8_PCREL);
963 MAP (2, 1, BFD_RELOC_16_PCREL);
964 MAP (4, 1, BFD_RELOC_32_PCREL);
965 default:
966 abort ();
967 }
968 }
969 #undef F
970 #undef MAP
971
972 reloc = (arelent *) xmalloc (sizeof (arelent));
973 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
974 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
975 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
976 #ifndef OBJ_ELF
977 if (fixp->fx_pcrel)
978 reloc->addend = fixp->fx_addnumber;
979 else
980 reloc->addend = 0;
981 #else
982 if (!fixp->fx_pcrel)
983 reloc->addend = fixp->fx_addnumber;
984 else
985 reloc->addend = (section->vma
986 /* Explicit sign extension in case char is
987 unsigned. */
988 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
989 + fixp->fx_addnumber
990 + md_pcrel_from (fixp));
991 #endif
992
993 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
994 assert (reloc->howto != 0);
995
996 return reloc;
997 }
998
999 #endif /* BFD_ASSEMBLER */
1000
1001 /* Handle of the OPCODE hash table. NULL means any use before
1002 m68k_ip_begin() will crash. */
1003 static struct hash_control *op_hash;
1004 \f
1005 /* Assemble an m68k instruction. */
1006
1007 static void
1008 m68k_ip (instring)
1009 char *instring;
1010 {
1011 register char *p;
1012 register struct m68k_op *opP;
1013 register const struct m68k_incant *opcode;
1014 register const char *s;
1015 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1016 char *pdot, *pdotmove;
1017 enum m68k_size siz1, siz2;
1018 char c;
1019 int losing;
1020 int opsfound;
1021 LITTLENUM_TYPE words[6];
1022 LITTLENUM_TYPE *wordp;
1023 unsigned long ok_arch = 0;
1024
1025 if (*instring == ' ')
1026 instring++; /* skip leading whitespace */
1027
1028 /* Scan up to end of operation-code, which MUST end in end-of-string
1029 or exactly 1 space. */
1030 pdot = 0;
1031 for (p = instring; *p != '\0'; p++)
1032 {
1033 if (*p == ' ')
1034 break;
1035 if (*p == '.')
1036 pdot = p;
1037 }
1038
1039 if (p == instring)
1040 {
1041 the_ins.error = _("No operator");
1042 return;
1043 }
1044
1045 /* p now points to the end of the opcode name, probably whitespace.
1046 Make sure the name is null terminated by clobbering the
1047 whitespace, look it up in the hash table, then fix it back.
1048 Remove a dot, first, since the opcode tables have none. */
1049 if (pdot != NULL)
1050 {
1051 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1052 *pdotmove = pdotmove[1];
1053 p--;
1054 }
1055
1056 c = *p;
1057 *p = '\0';
1058 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1059 *p = c;
1060
1061 if (pdot != NULL)
1062 {
1063 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1064 *pdotmove = pdotmove[-1];
1065 *pdot = '.';
1066 ++p;
1067 }
1068
1069 if (opcode == NULL)
1070 {
1071 the_ins.error = _("Unknown operator");
1072 return;
1073 }
1074
1075 /* found a legitimate opcode, start matching operands */
1076 while (*p == ' ')
1077 ++p;
1078
1079 if (opcode->m_operands == 0)
1080 {
1081 char *old = input_line_pointer;
1082 *old = '\n';
1083 input_line_pointer = p;
1084 /* Ahh - it's a motorola style psuedo op */
1085 mote_pseudo_table[opcode->m_opnum].poc_handler
1086 (mote_pseudo_table[opcode->m_opnum].poc_val);
1087 input_line_pointer = old;
1088 *old = 0;
1089
1090 return;
1091 }
1092
1093 if (flag_mri && opcode->m_opnum == 0)
1094 {
1095 /* In MRI mode, random garbage is allowed after an instruction
1096 which accepts no operands. */
1097 the_ins.args = opcode->m_operands;
1098 the_ins.numargs = opcode->m_opnum;
1099 the_ins.numo = opcode->m_codenum;
1100 the_ins.opcode[0] = getone (opcode);
1101 the_ins.opcode[1] = gettwo (opcode);
1102 return;
1103 }
1104
1105 for (opP = &the_ins.operands[0]; *p; opP++)
1106 {
1107 p = crack_operand (p, opP);
1108
1109 if (opP->error)
1110 {
1111 the_ins.error = opP->error;
1112 return;
1113 }
1114 }
1115
1116 opsfound = opP - &the_ins.operands[0];
1117
1118 /* This ugly hack is to support the floating pt opcodes in their
1119 standard form. Essentially, we fake a first enty of type COP#1 */
1120 if (opcode->m_operands[0] == 'I')
1121 {
1122 int n;
1123
1124 for (n = opsfound; n > 0; --n)
1125 the_ins.operands[n] = the_ins.operands[n - 1];
1126
1127 memset ((char *) (&the_ins.operands[0]), '\0',
1128 sizeof (the_ins.operands[0]));
1129 the_ins.operands[0].mode = CONTROL;
1130 the_ins.operands[0].reg = m68k_float_copnum;
1131 opsfound++;
1132 }
1133
1134 /* We've got the operands. Find an opcode that'll accept them */
1135 for (losing = 0;;)
1136 {
1137 /* If we didn't get the right number of ops, or we have no
1138 common model with this pattern then reject this pattern. */
1139
1140 ok_arch |= opcode->m_arch;
1141 if (opsfound != opcode->m_opnum
1142 || ((opcode->m_arch & current_architecture) == 0))
1143 ++losing;
1144 else
1145 {
1146 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1147 *s && !losing;
1148 s += 2, opP++)
1149 {
1150 /* Warning: this switch is huge! */
1151 /* I've tried to organize the cases into this order:
1152 non-alpha first, then alpha by letter. Lower-case
1153 goes directly before uppercase counterpart. */
1154 /* Code with multiple case ...: gets sorted by the lowest
1155 case ... it belongs to. I hope this makes sense. */
1156 switch (*s)
1157 {
1158 case '!':
1159 switch (opP->mode)
1160 {
1161 case IMMED:
1162 case DREG:
1163 case AREG:
1164 case FPREG:
1165 case CONTROL:
1166 case AINC:
1167 case ADEC:
1168 case REGLST:
1169 losing++;
1170 break;
1171 default:
1172 break;
1173 }
1174 break;
1175
1176 case '<':
1177 switch (opP->mode)
1178 {
1179 case DREG:
1180 case AREG:
1181 case FPREG:
1182 case CONTROL:
1183 case IMMED:
1184 case ADEC:
1185 case REGLST:
1186 losing++;
1187 break;
1188 default:
1189 break;
1190 }
1191 break;
1192
1193 case '>':
1194 switch (opP->mode)
1195 {
1196 case DREG:
1197 case AREG:
1198 case FPREG:
1199 case CONTROL:
1200 case IMMED:
1201 case AINC:
1202 case REGLST:
1203 losing++;
1204 break;
1205 case ABSL:
1206 break;
1207 default:
1208 if (opP->reg == PC
1209 || opP->reg == ZPC)
1210 losing++;
1211 break;
1212 }
1213 break;
1214
1215 case 'm':
1216 switch (opP->mode)
1217 {
1218 case DREG:
1219 case AREG:
1220 case AINDR:
1221 case AINC:
1222 case ADEC:
1223 break;
1224 default:
1225 losing++;
1226 }
1227 break;
1228
1229 case 'n':
1230 switch (opP->mode)
1231 {
1232 case DISP:
1233 break;
1234 default:
1235 losing++;
1236 }
1237 break;
1238
1239 case 'o':
1240 switch (opP->mode)
1241 {
1242 case BASE:
1243 case ABSL:
1244 case IMMED:
1245 break;
1246 default:
1247 losing++;
1248 }
1249 break;
1250
1251 case 'p':
1252 switch (opP->mode)
1253 {
1254 case DREG:
1255 case AREG:
1256 case AINDR:
1257 case AINC:
1258 case ADEC:
1259 break;
1260 case DISP:
1261 if (opP->reg == PC || opP->reg == ZPC)
1262 losing++;
1263 break;
1264 default:
1265 losing++;
1266 }
1267 break;
1268
1269 case 'q':
1270 switch (opP->mode)
1271 {
1272 case DREG:
1273 case AINDR:
1274 case AINC:
1275 case ADEC:
1276 break;
1277 case DISP:
1278 if (opP->reg == PC || opP->reg == ZPC)
1279 losing++;
1280 break;
1281 default:
1282 losing++;
1283 break;
1284 }
1285 break;
1286
1287 case 'v':
1288 switch (opP->mode)
1289 {
1290 case DREG:
1291 case AINDR:
1292 case AINC:
1293 case ADEC:
1294 case ABSL:
1295 break;
1296 case DISP:
1297 if (opP->reg == PC || opP->reg == ZPC)
1298 losing++;
1299 break;
1300 default:
1301 losing++;
1302 break;
1303 }
1304 break;
1305
1306 case '#':
1307 if (opP->mode != IMMED)
1308 losing++;
1309 else if (s[1] == 'b'
1310 && ! isvar (&opP->disp)
1311 && (opP->disp.exp.X_op != O_constant
1312 || ! isbyte (opP->disp.exp.X_add_number)))
1313 losing++;
1314 else if (s[1] == 'B'
1315 && ! isvar (&opP->disp)
1316 && (opP->disp.exp.X_op != O_constant
1317 || ! issbyte (opP->disp.exp.X_add_number)))
1318 losing++;
1319 else if (s[1] == 'w'
1320 && ! isvar (&opP->disp)
1321 && (opP->disp.exp.X_op != O_constant
1322 || ! isword (opP->disp.exp.X_add_number)))
1323 losing++;
1324 else if (s[1] == 'W'
1325 && ! isvar (&opP->disp)
1326 && (opP->disp.exp.X_op != O_constant
1327 || ! issword (opP->disp.exp.X_add_number)))
1328 losing++;
1329 break;
1330
1331 case '^':
1332 case 'T':
1333 if (opP->mode != IMMED)
1334 losing++;
1335 break;
1336
1337 case '$':
1338 if (opP->mode == AREG
1339 || opP->mode == CONTROL
1340 || opP->mode == FPREG
1341 || opP->mode == IMMED
1342 || opP->mode == REGLST
1343 || (opP->mode != ABSL
1344 && (opP->reg == PC
1345 || opP->reg == ZPC)))
1346 losing++;
1347 break;
1348
1349 case '%':
1350 if (opP->mode == CONTROL
1351 || opP->mode == FPREG
1352 || opP->mode == REGLST
1353 || opP->mode == IMMED
1354 || (opP->mode != ABSL
1355 && (opP->reg == PC
1356 || opP->reg == ZPC)))
1357 losing++;
1358 break;
1359
1360 case '&':
1361 switch (opP->mode)
1362 {
1363 case DREG:
1364 case AREG:
1365 case FPREG:
1366 case CONTROL:
1367 case IMMED:
1368 case AINC:
1369 case ADEC:
1370 case REGLST:
1371 losing++;
1372 break;
1373 case ABSL:
1374 break;
1375 default:
1376 if (opP->reg == PC
1377 || opP->reg == ZPC)
1378 losing++;
1379 break;
1380 }
1381 break;
1382
1383 case '*':
1384 if (opP->mode == CONTROL
1385 || opP->mode == FPREG
1386 || opP->mode == REGLST)
1387 losing++;
1388 break;
1389
1390 case '+':
1391 if (opP->mode != AINC)
1392 losing++;
1393 break;
1394
1395 case '-':
1396 if (opP->mode != ADEC)
1397 losing++;
1398 break;
1399
1400 case '/':
1401 switch (opP->mode)
1402 {
1403 case AREG:
1404 case CONTROL:
1405 case FPREG:
1406 case AINC:
1407 case ADEC:
1408 case IMMED:
1409 case REGLST:
1410 losing++;
1411 break;
1412 default:
1413 break;
1414 }
1415 break;
1416
1417 case ';':
1418 switch (opP->mode)
1419 {
1420 case AREG:
1421 case CONTROL:
1422 case FPREG:
1423 case REGLST:
1424 losing++;
1425 break;
1426 default:
1427 break;
1428 }
1429 break;
1430
1431 case '?':
1432 switch (opP->mode)
1433 {
1434 case AREG:
1435 case CONTROL:
1436 case FPREG:
1437 case AINC:
1438 case ADEC:
1439 case IMMED:
1440 case REGLST:
1441 losing++;
1442 break;
1443 case ABSL:
1444 break;
1445 default:
1446 if (opP->reg == PC || opP->reg == ZPC)
1447 losing++;
1448 break;
1449 }
1450 break;
1451
1452 case '@':
1453 switch (opP->mode)
1454 {
1455 case AREG:
1456 case CONTROL:
1457 case FPREG:
1458 case IMMED:
1459 case REGLST:
1460 losing++;
1461 break;
1462 default:
1463 break;
1464 }
1465 break;
1466
1467 case '~': /* For now! (JF FOO is this right?) */
1468 switch (opP->mode)
1469 {
1470 case DREG:
1471 case AREG:
1472 case CONTROL:
1473 case FPREG:
1474 case IMMED:
1475 case REGLST:
1476 losing++;
1477 break;
1478 case ABSL:
1479 break;
1480 default:
1481 if (opP->reg == PC
1482 || opP->reg == ZPC)
1483 losing++;
1484 break;
1485 }
1486 break;
1487
1488 case '3':
1489 if (opP->mode != CONTROL
1490 || (opP->reg != TT0 && opP->reg != TT1))
1491 losing++;
1492 break;
1493
1494 case 'A':
1495 if (opP->mode != AREG)
1496 losing++;
1497 break;
1498
1499 case 'a':
1500 if (opP->mode != AINDR)
1501 ++losing;
1502 break;
1503
1504 case 'B': /* FOO */
1505 if (opP->mode != ABSL
1506 || (flag_long_jumps
1507 && strncmp (instring, "jbsr", 4) == 0))
1508 losing++;
1509 break;
1510
1511 case 'C':
1512 if (opP->mode != CONTROL || opP->reg != CCR)
1513 losing++;
1514 break;
1515
1516 case 'd':
1517 if (opP->mode != DISP
1518 || opP->reg < ADDR0
1519 || opP->reg > ADDR7)
1520 losing++;
1521 break;
1522
1523 case 'D':
1524 if (opP->mode != DREG)
1525 losing++;
1526 break;
1527
1528 case 'E':
1529 if (opP->reg != ACC)
1530 losing++;
1531 break;
1532
1533 case 'F':
1534 if (opP->mode != FPREG)
1535 losing++;
1536 break;
1537
1538 case 'G':
1539 if (opP->reg != MACSR)
1540 losing++;
1541 break;
1542
1543 case 'H':
1544 if (opP->reg != MASK)
1545 losing++;
1546 break;
1547
1548 case 'I':
1549 if (opP->mode != CONTROL
1550 || opP->reg < COP0
1551 || opP->reg > COP7)
1552 losing++;
1553 break;
1554
1555 case 'J':
1556 if (opP->mode != CONTROL
1557 || opP->reg < USP
1558 || opP->reg > last_movec_reg)
1559 losing++;
1560 else
1561 {
1562 const enum m68k_register *rp;
1563 for (rp = control_regs; *rp; rp++)
1564 if (*rp == opP->reg)
1565 break;
1566 if (*rp == 0)
1567 losing++;
1568 }
1569 break;
1570
1571 case 'k':
1572 if (opP->mode != IMMED)
1573 losing++;
1574 break;
1575
1576 case 'l':
1577 case 'L':
1578 if (opP->mode == DREG
1579 || opP->mode == AREG
1580 || opP->mode == FPREG)
1581 {
1582 if (s[1] == '8')
1583 losing++;
1584 else
1585 {
1586 switch (opP->mode)
1587 {
1588 case DREG:
1589 opP->mask = 1 << (opP->reg - DATA0);
1590 break;
1591 case AREG:
1592 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1593 break;
1594 case FPREG:
1595 opP->mask = 1 << (opP->reg - FP0 + 16);
1596 break;
1597 default:
1598 abort ();
1599 }
1600 opP->mode = REGLST;
1601 }
1602 }
1603 else if (opP->mode == CONTROL)
1604 {
1605 if (s[1] != '8')
1606 losing++;
1607 else
1608 {
1609 switch (opP->reg)
1610 {
1611 case FPI:
1612 opP->mask = 1 << 24;
1613 break;
1614 case FPS:
1615 opP->mask = 1 << 25;
1616 break;
1617 case FPC:
1618 opP->mask = 1 << 26;
1619 break;
1620 default:
1621 losing++;
1622 break;
1623 }
1624 opP->mode = REGLST;
1625 }
1626 }
1627 else if (opP->mode != REGLST)
1628 losing++;
1629 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1630 losing++;
1631 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1632 losing++;
1633 break;
1634
1635 case 'M':
1636 if (opP->mode != IMMED)
1637 losing++;
1638 else if (opP->disp.exp.X_op != O_constant
1639 || ! issbyte (opP->disp.exp.X_add_number))
1640 losing++;
1641 else if (! m68k_quick
1642 && instring[3] != 'q'
1643 && instring[4] != 'q')
1644 losing++;
1645 break;
1646
1647 case 'O':
1648 if (opP->mode != DREG
1649 && opP->mode != IMMED
1650 && opP->mode != ABSL)
1651 losing++;
1652 break;
1653
1654 case 'Q':
1655 if (opP->mode != IMMED)
1656 losing++;
1657 else if (opP->disp.exp.X_op != O_constant
1658 || opP->disp.exp.X_add_number < 1
1659 || opP->disp.exp.X_add_number > 8)
1660 losing++;
1661 else if (! m68k_quick
1662 && (strncmp (instring, "add", 3) == 0
1663 || strncmp (instring, "sub", 3) == 0)
1664 && instring[3] != 'q')
1665 losing++;
1666 break;
1667
1668 case 'R':
1669 if (opP->mode != DREG && opP->mode != AREG)
1670 losing++;
1671 break;
1672
1673 case 'r':
1674 if (opP->mode != AINDR
1675 && (opP->mode != BASE
1676 || (opP->reg != 0
1677 && opP->reg != ZADDR0)
1678 || opP->disp.exp.X_op != O_absent
1679 || ((opP->index.reg < DATA0
1680 || opP->index.reg > DATA7)
1681 && (opP->index.reg < ADDR0
1682 || opP->index.reg > ADDR7))
1683 || opP->index.size != SIZE_UNSPEC
1684 || opP->index.scale != 1))
1685 losing++;
1686 break;
1687
1688 case 's':
1689 if (opP->mode != CONTROL
1690 || ! (opP->reg == FPI
1691 || opP->reg == FPS
1692 || opP->reg == FPC))
1693 losing++;
1694 break;
1695
1696 case 'S':
1697 if (opP->mode != CONTROL || opP->reg != SR)
1698 losing++;
1699 break;
1700
1701 case 't':
1702 if (opP->mode != IMMED)
1703 losing++;
1704 else if (opP->disp.exp.X_op != O_constant
1705 || opP->disp.exp.X_add_number < 0
1706 || opP->disp.exp.X_add_number > 7)
1707 losing++;
1708 break;
1709
1710 case 'U':
1711 if (opP->mode != CONTROL || opP->reg != USP)
1712 losing++;
1713 break;
1714
1715 /* JF these are out of order. We could put them
1716 in order if we were willing to put up with
1717 bunches of #ifdef m68851s in the code.
1718
1719 Don't forget that you need these operands
1720 to use 68030 MMU instructions. */
1721 #ifndef NO_68851
1722 /* Memory addressing mode used by pflushr */
1723 case '|':
1724 if (opP->mode == CONTROL
1725 || opP->mode == FPREG
1726 || opP->mode == DREG
1727 || opP->mode == AREG
1728 || opP->mode == REGLST)
1729 losing++;
1730 /* We should accept immediate operands, but they
1731 supposedly have to be quad word, and we don't
1732 handle that. I would like to see what a Motorola
1733 assembler does before doing something here. */
1734 if (opP->mode == IMMED)
1735 losing++;
1736 break;
1737
1738 case 'f':
1739 if (opP->mode != CONTROL
1740 || (opP->reg != SFC && opP->reg != DFC))
1741 losing++;
1742 break;
1743
1744 case '0':
1745 if (opP->mode != CONTROL || opP->reg != TC)
1746 losing++;
1747 break;
1748
1749 case '1':
1750 if (opP->mode != CONTROL || opP->reg != AC)
1751 losing++;
1752 break;
1753
1754 case '2':
1755 if (opP->mode != CONTROL
1756 || (opP->reg != CAL
1757 && opP->reg != VAL
1758 && opP->reg != SCC))
1759 losing++;
1760 break;
1761
1762 case 'V':
1763 if (opP->mode != CONTROL
1764 || opP->reg != VAL)
1765 losing++;
1766 break;
1767
1768 case 'W':
1769 if (opP->mode != CONTROL
1770 || (opP->reg != DRP
1771 && opP->reg != SRP
1772 && opP->reg != CRP))
1773 losing++;
1774 break;
1775
1776 case 'X':
1777 if (opP->mode != CONTROL
1778 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1779 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1780 losing++;
1781 break;
1782
1783 case 'Y':
1784 if (opP->mode != CONTROL || opP->reg != PSR)
1785 losing++;
1786 break;
1787
1788 case 'Z':
1789 if (opP->mode != CONTROL || opP->reg != PCSR)
1790 losing++;
1791 break;
1792 #endif
1793 case 'c':
1794 if (opP->mode != CONTROL
1795 || (opP->reg != NC
1796 && opP->reg != IC
1797 && opP->reg != DC
1798 && opP->reg != BC))
1799 {
1800 losing++;
1801 } /* not a cache specifier. */
1802 break;
1803
1804 case '_':
1805 if (opP->mode != ABSL)
1806 ++losing;
1807 break;
1808
1809 case 'u':
1810 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1811 losing++;
1812 /* FIXME: kludge instead of fixing parser:
1813 upper/lower registers are *not* CONTROL
1814 registers, but ordinary ones. */
1815 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1816 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1817 opP->mode = DREG;
1818 else
1819 opP->mode = AREG;
1820 break;
1821
1822 default:
1823 abort ();
1824 } /* switch on type of operand */
1825
1826 if (losing)
1827 break;
1828 } /* for each operand */
1829 } /* if immediately wrong */
1830
1831 if (!losing)
1832 {
1833 break;
1834 } /* got it. */
1835
1836 opcode = opcode->m_next;
1837
1838 if (!opcode)
1839 {
1840 if (ok_arch
1841 && !(ok_arch & current_architecture))
1842 {
1843 char buf[200], *cp;
1844
1845 strcpy (buf,
1846 _("invalid instruction for this architecture; needs "));
1847 cp = buf + strlen (buf);
1848 switch (ok_arch)
1849 {
1850 case mfloat:
1851 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1852 break;
1853 case mmmu:
1854 strcpy (cp, _("mmu (68030 or 68851)"));
1855 break;
1856 case m68020up:
1857 strcpy (cp, _("68020 or higher"));
1858 break;
1859 case m68000up:
1860 strcpy (cp, _("68000 or higher"));
1861 break;
1862 case m68010up:
1863 strcpy (cp, _("68010 or higher"));
1864 break;
1865 default:
1866 {
1867 int got_one = 0, idx;
1868 for (idx = 0;
1869 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1870 idx++)
1871 {
1872 if ((archs[idx].arch & ok_arch)
1873 && ! archs[idx].alias)
1874 {
1875 if (got_one)
1876 {
1877 strcpy (cp, " or ");
1878 cp += strlen (cp);
1879 }
1880 got_one = 1;
1881 strcpy (cp, archs[idx].name);
1882 cp += strlen (cp);
1883 }
1884 }
1885 }
1886 }
1887 cp = xmalloc (strlen (buf) + 1);
1888 strcpy (cp, buf);
1889 the_ins.error = cp;
1890 }
1891 else
1892 the_ins.error = _("operands mismatch");
1893 return;
1894 } /* Fell off the end */
1895
1896 losing = 0;
1897 }
1898
1899 /* now assemble it */
1900
1901 the_ins.args = opcode->m_operands;
1902 the_ins.numargs = opcode->m_opnum;
1903 the_ins.numo = opcode->m_codenum;
1904 the_ins.opcode[0] = getone (opcode);
1905 the_ins.opcode[1] = gettwo (opcode);
1906
1907 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1908 {
1909 /* This switch is a doozy.
1910 Watch the first step; its a big one! */
1911 switch (s[0])
1912 {
1913
1914 case '*':
1915 case '~':
1916 case '%':
1917 case ';':
1918 case '@':
1919 case '!':
1920 case '&':
1921 case '$':
1922 case '?':
1923 case '/':
1924 case '<':
1925 case '>':
1926 case 'm':
1927 case 'n':
1928 case 'o':
1929 case 'p':
1930 case 'q':
1931 case 'v':
1932 #ifndef NO_68851
1933 case '|':
1934 #endif
1935 switch (opP->mode)
1936 {
1937 case IMMED:
1938 tmpreg = 0x3c; /* 7.4 */
1939 if (strchr ("bwl", s[1]))
1940 nextword = get_num (&opP->disp, 80);
1941 else
1942 nextword = get_num (&opP->disp, 0);
1943 if (isvar (&opP->disp))
1944 add_fix (s[1], &opP->disp, 0, 0);
1945 switch (s[1])
1946 {
1947 case 'b':
1948 if (!isbyte (nextword))
1949 opP->error = _("operand out of range");
1950 addword (nextword);
1951 baseo = 0;
1952 break;
1953 case 'w':
1954 if (!isword (nextword))
1955 opP->error = _("operand out of range");
1956 addword (nextword);
1957 baseo = 0;
1958 break;
1959 case 'W':
1960 if (!issword (nextword))
1961 opP->error = _("operand out of range");
1962 addword (nextword);
1963 baseo = 0;
1964 break;
1965 case 'l':
1966 addword (nextword >> 16);
1967 addword (nextword);
1968 baseo = 0;
1969 break;
1970
1971 case 'f':
1972 baseo = 2;
1973 outro = 8;
1974 break;
1975 case 'F':
1976 baseo = 4;
1977 outro = 11;
1978 break;
1979 case 'x':
1980 baseo = 6;
1981 outro = 15;
1982 break;
1983 case 'p':
1984 baseo = 6;
1985 outro = -1;
1986 break;
1987 default:
1988 abort ();
1989 }
1990 if (!baseo)
1991 break;
1992
1993 /* We gotta put out some float */
1994 if (op (&opP->disp) != O_big)
1995 {
1996 valueT val;
1997 int gencnt;
1998
1999 /* Can other cases happen here? */
2000 if (op (&opP->disp) != O_constant)
2001 abort ();
2002
2003 val = (valueT) offs (&opP->disp);
2004 gencnt = 0;
2005 do
2006 {
2007 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2008 val >>= LITTLENUM_NUMBER_OF_BITS;
2009 ++gencnt;
2010 }
2011 while (val != 0);
2012 offs (&opP->disp) = gencnt;
2013 }
2014 if (offs (&opP->disp) > 0)
2015 {
2016 if (offs (&opP->disp) > baseo)
2017 {
2018 as_warn (_("Bignum too big for %c format; truncated"),
2019 s[1]);
2020 offs (&opP->disp) = baseo;
2021 }
2022 baseo -= offs (&opP->disp);
2023 while (baseo--)
2024 addword (0);
2025 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2026 offs (&opP->disp)--;
2027 --wordp)
2028 addword (*wordp);
2029 break;
2030 }
2031 gen_to_words (words, baseo, (long) outro);
2032 for (wordp = words; baseo--; wordp++)
2033 addword (*wordp);
2034 break;
2035 case DREG:
2036 tmpreg = opP->reg - DATA; /* 0.dreg */
2037 break;
2038 case AREG:
2039 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2040 break;
2041 case AINDR:
2042 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2043 break;
2044 case ADEC:
2045 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2046 break;
2047 case AINC:
2048 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2049 break;
2050 case DISP:
2051
2052 nextword = get_num (&opP->disp, 80);
2053
2054 if (opP->reg == PC
2055 && ! isvar (&opP->disp)
2056 && m68k_abspcadd)
2057 {
2058 opP->disp.exp.X_op = O_symbol;
2059 #ifndef BFD_ASSEMBLER
2060 opP->disp.exp.X_add_symbol = &abs_symbol;
2061 #else
2062 opP->disp.exp.X_add_symbol =
2063 section_symbol (absolute_section);
2064 #endif
2065 }
2066
2067 /* Force into index mode. Hope this works */
2068
2069 /* We do the first bit for 32-bit displacements, and the
2070 second bit for 16 bit ones. It is possible that we
2071 should make the default be WORD instead of LONG, but
2072 I think that'd break GCC, so we put up with a little
2073 inefficiency for the sake of working output. */
2074
2075 if (!issword (nextword)
2076 || (isvar (&opP->disp)
2077 && ((opP->disp.size == SIZE_UNSPEC
2078 && flag_short_refs == 0
2079 && cpu_of_arch (current_architecture) >= m68020
2080 && ! arch_coldfire_p (current_architecture))
2081 || opP->disp.size == SIZE_LONG)))
2082 {
2083 if (cpu_of_arch (current_architecture) < m68020
2084 || arch_coldfire_p (current_architecture))
2085 opP->error =
2086 _("displacement too large for this architecture; needs 68020 or higher");
2087 if (opP->reg == PC)
2088 tmpreg = 0x3B; /* 7.3 */
2089 else
2090 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2091 if (isvar (&opP->disp))
2092 {
2093 if (opP->reg == PC)
2094 {
2095 if (opP->disp.size == SIZE_LONG
2096 #ifdef OBJ_ELF
2097 /* If the displacement needs pic
2098 relocation it cannot be relaxed. */
2099 || opP->disp.pic_reloc != pic_none
2100 #endif
2101 )
2102 {
2103 addword (0x0170);
2104 add_fix ('l', &opP->disp, 1, 2);
2105 }
2106 else
2107 {
2108 add_frag (adds (&opP->disp),
2109 offs (&opP->disp),
2110 TAB (PCREL1632, SZ_UNDEF));
2111 break;
2112 }
2113 }
2114 else
2115 {
2116 addword (0x0170);
2117 add_fix ('l', &opP->disp, 0, 0);
2118 }
2119 }
2120 else
2121 addword (0x0170);
2122 addword (nextword >> 16);
2123 }
2124 else
2125 {
2126 if (opP->reg == PC)
2127 tmpreg = 0x3A; /* 7.2 */
2128 else
2129 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2130
2131 if (isvar (&opP->disp))
2132 {
2133 if (opP->reg == PC)
2134 {
2135 add_fix ('w', &opP->disp, 1, 0);
2136 }
2137 else
2138 add_fix ('w', &opP->disp, 0, 0);
2139 }
2140 }
2141 addword (nextword);
2142 break;
2143
2144 case POST:
2145 case PRE:
2146 case BASE:
2147 nextword = 0;
2148 baseo = get_num (&opP->disp, 80);
2149 if (opP->mode == POST || opP->mode == PRE)
2150 outro = get_num (&opP->odisp, 80);
2151 /* Figure out the `addressing mode'.
2152 Also turn on the BASE_DISABLE bit, if needed. */
2153 if (opP->reg == PC || opP->reg == ZPC)
2154 {
2155 tmpreg = 0x3b; /* 7.3 */
2156 if (opP->reg == ZPC)
2157 nextword |= 0x80;
2158 }
2159 else if (opP->reg == 0)
2160 {
2161 nextword |= 0x80;
2162 tmpreg = 0x30; /* 6.garbage */
2163 }
2164 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2165 {
2166 nextword |= 0x80;
2167 tmpreg = 0x30 + opP->reg - ZADDR0;
2168 }
2169 else
2170 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2171
2172 siz1 = opP->disp.size;
2173 if (opP->mode == POST || opP->mode == PRE)
2174 siz2 = opP->odisp.size;
2175 else
2176 siz2 = SIZE_UNSPEC;
2177
2178 /* Index register stuff */
2179 if (opP->index.reg != 0
2180 && opP->index.reg >= DATA
2181 && opP->index.reg <= ADDR7)
2182 {
2183 nextword |= (opP->index.reg - DATA) << 12;
2184
2185 if (opP->index.size == SIZE_LONG
2186 || (opP->index.size == SIZE_UNSPEC
2187 && m68k_index_width_default == SIZE_LONG))
2188 nextword |= 0x800;
2189
2190 if ((opP->index.scale != 1
2191 && cpu_of_arch (current_architecture) < m68020)
2192 || (opP->index.scale == 8
2193 && arch_coldfire_p (current_architecture)))
2194 {
2195 opP->error =
2196 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2197 }
2198
2199 if (arch_coldfire_p (current_architecture)
2200 && opP->index.size == SIZE_WORD)
2201 opP->error = _("invalid index size for coldfire");
2202
2203 switch (opP->index.scale)
2204 {
2205 case 1:
2206 break;
2207 case 2:
2208 nextword |= 0x200;
2209 break;
2210 case 4:
2211 nextword |= 0x400;
2212 break;
2213 case 8:
2214 nextword |= 0x600;
2215 break;
2216 default:
2217 abort ();
2218 }
2219 /* IF its simple,
2220 GET US OUT OF HERE! */
2221
2222 /* Must be INDEX, with an index register. Address
2223 register cannot be ZERO-PC, and either :b was
2224 forced, or we know it will fit. For a 68000 or
2225 68010, force this mode anyways, because the
2226 larger modes aren't supported. */
2227 if (opP->mode == BASE
2228 && ((opP->reg >= ADDR0
2229 && opP->reg <= ADDR7)
2230 || opP->reg == PC))
2231 {
2232 if (siz1 == SIZE_BYTE
2233 || cpu_of_arch (current_architecture) < m68020
2234 || arch_coldfire_p (current_architecture)
2235 || (siz1 == SIZE_UNSPEC
2236 && ! isvar (&opP->disp)
2237 && issbyte (baseo)))
2238 {
2239 nextword += baseo & 0xff;
2240 addword (nextword);
2241 if (isvar (&opP->disp))
2242 {
2243 /* Do a byte relocation. If it doesn't
2244 fit (possible on m68000) let the
2245 fixup processing complain later. */
2246 if (opP->reg == PC)
2247 add_fix ('B', &opP->disp, 1, 1);
2248 else
2249 add_fix ('B', &opP->disp, 0, 0);
2250 }
2251 else if (siz1 != SIZE_BYTE)
2252 {
2253 if (siz1 != SIZE_UNSPEC)
2254 as_warn (_("Forcing byte displacement"));
2255 if (! issbyte (baseo))
2256 opP->error = _("byte displacement out of range");
2257 }
2258
2259 break;
2260 }
2261 else if (siz1 == SIZE_UNSPEC
2262 && opP->reg == PC
2263 && isvar (&opP->disp)
2264 && subs (&opP->disp) == NULL
2265 #ifdef OBJ_ELF
2266 /* If the displacement needs pic
2267 relocation it cannot be relaxed. */
2268 && opP->disp.pic_reloc == pic_none
2269 #endif
2270 )
2271 {
2272 /* The code in md_convert_frag_1 needs to be
2273 able to adjust nextword. Call frag_grow
2274 to ensure that we have enough space in
2275 the frag obstack to make all the bytes
2276 contiguous. */
2277 frag_grow (14);
2278 nextword += baseo & 0xff;
2279 addword (nextword);
2280 add_frag (adds (&opP->disp), offs (&opP->disp),
2281 TAB (PCINDEX, SZ_UNDEF));
2282
2283 break;
2284 }
2285 }
2286 }
2287 else
2288 {
2289 nextword |= 0x40; /* No index reg */
2290 if (opP->index.reg >= ZDATA0
2291 && opP->index.reg <= ZDATA7)
2292 nextword |= (opP->index.reg - ZDATA0) << 12;
2293 else if (opP->index.reg >= ZADDR0
2294 || opP->index.reg <= ZADDR7)
2295 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2296 }
2297
2298 /* It isn't simple. */
2299
2300 if (cpu_of_arch (current_architecture) < m68020
2301 || arch_coldfire_p (current_architecture))
2302 opP->error =
2303 _("invalid operand mode for this architecture; needs 68020 or higher");
2304
2305 nextword |= 0x100;
2306 /* If the guy specified a width, we assume that it is
2307 wide enough. Maybe it isn't. If so, we lose. */
2308 switch (siz1)
2309 {
2310 case SIZE_UNSPEC:
2311 if (isvar (&opP->disp)
2312 ? m68k_rel32
2313 : ! issword (baseo))
2314 {
2315 siz1 = SIZE_LONG;
2316 nextword |= 0x30;
2317 }
2318 else if (! isvar (&opP->disp) && baseo == 0)
2319 nextword |= 0x10;
2320 else
2321 {
2322 nextword |= 0x20;
2323 siz1 = SIZE_WORD;
2324 }
2325 break;
2326 case SIZE_BYTE:
2327 as_warn (_(":b not permitted; defaulting to :w"));
2328 /* Fall through. */
2329 case SIZE_WORD:
2330 nextword |= 0x20;
2331 break;
2332 case SIZE_LONG:
2333 nextword |= 0x30;
2334 break;
2335 }
2336
2337 /* Figure out innner displacement stuff */
2338 if (opP->mode == POST || opP->mode == PRE)
2339 {
2340 if (cpu_of_arch (current_architecture) & cpu32)
2341 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2342 switch (siz2)
2343 {
2344 case SIZE_UNSPEC:
2345 if (isvar (&opP->odisp)
2346 ? m68k_rel32
2347 : ! issword (outro))
2348 {
2349 siz2 = SIZE_LONG;
2350 nextword |= 0x3;
2351 }
2352 else if (! isvar (&opP->odisp) && outro == 0)
2353 nextword |= 0x1;
2354 else
2355 {
2356 nextword |= 0x2;
2357 siz2 = SIZE_WORD;
2358 }
2359 break;
2360 case 1:
2361 as_warn (_(":b not permitted; defaulting to :w"));
2362 /* Fall through. */
2363 case 2:
2364 nextword |= 0x2;
2365 break;
2366 case 3:
2367 nextword |= 0x3;
2368 break;
2369 }
2370 if (opP->mode == POST
2371 && (nextword & 0x40) == 0)
2372 nextword |= 0x04;
2373 }
2374 addword (nextword);
2375
2376 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2377 {
2378 if (opP->reg == PC || opP->reg == ZPC)
2379 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2380 else
2381 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2382 }
2383 if (siz1 == SIZE_LONG)
2384 addword (baseo >> 16);
2385 if (siz1 != SIZE_UNSPEC)
2386 addword (baseo);
2387
2388 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2389 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2390 if (siz2 == SIZE_LONG)
2391 addword (outro >> 16);
2392 if (siz2 != SIZE_UNSPEC)
2393 addword (outro);
2394
2395 break;
2396
2397 case ABSL:
2398 nextword = get_num (&opP->disp, 80);
2399 switch (opP->disp.size)
2400 {
2401 default:
2402 abort ();
2403 case SIZE_UNSPEC:
2404 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2405 {
2406 tmpreg = 0x38; /* 7.0 */
2407 addword (nextword);
2408 break;
2409 }
2410 if (isvar (&opP->disp)
2411 && !subs (&opP->disp)
2412 && adds (&opP->disp)
2413 #ifdef OBJ_ELF
2414 /* If the displacement needs pic relocation it
2415 cannot be relaxed. */
2416 && opP->disp.pic_reloc == pic_none
2417 #endif
2418 && !flag_long_jumps
2419 && !strchr ("~%&$?", s[0]))
2420 {
2421 tmpreg = 0x3A; /* 7.2 */
2422 add_frag (adds (&opP->disp),
2423 offs (&opP->disp),
2424 TAB (ABSTOPCREL, SZ_UNDEF));
2425 break;
2426 }
2427 /* Fall through into long */
2428 case SIZE_LONG:
2429 if (isvar (&opP->disp))
2430 add_fix ('l', &opP->disp, 0, 0);
2431
2432 tmpreg = 0x39;/* 7.1 mode */
2433 addword (nextword >> 16);
2434 addword (nextword);
2435 break;
2436
2437 case SIZE_BYTE:
2438 as_bad (_("unsupported byte value; use a different suffix"));
2439 /* Fall through. */
2440 case SIZE_WORD: /* Word */
2441 if (isvar (&opP->disp))
2442 add_fix ('w', &opP->disp, 0, 0);
2443
2444 tmpreg = 0x38;/* 7.0 mode */
2445 addword (nextword);
2446 break;
2447 }
2448 break;
2449 case CONTROL:
2450 case FPREG:
2451 default:
2452 as_bad (_("unknown/incorrect operand"));
2453 /* abort (); */
2454 }
2455 install_gen_operand (s[1], tmpreg);
2456 break;
2457
2458 case '#':
2459 case '^':
2460 switch (s[1])
2461 { /* JF: I hate floating point! */
2462 case 'j':
2463 tmpreg = 70;
2464 break;
2465 case '8':
2466 tmpreg = 20;
2467 break;
2468 case 'C':
2469 tmpreg = 50;
2470 break;
2471 case '3':
2472 default:
2473 tmpreg = 80;
2474 break;
2475 }
2476 tmpreg = get_num (&opP->disp, tmpreg);
2477 if (isvar (&opP->disp))
2478 add_fix (s[1], &opP->disp, 0, 0);
2479 switch (s[1])
2480 {
2481 case 'b': /* Danger: These do no check for
2482 certain types of overflow.
2483 user beware! */
2484 if (!isbyte (tmpreg))
2485 opP->error = _("out of range");
2486 insop (tmpreg, opcode);
2487 if (isvar (&opP->disp))
2488 the_ins.reloc[the_ins.nrel - 1].n =
2489 (opcode->m_codenum) * 2 + 1;
2490 break;
2491 case 'B':
2492 if (!issbyte (tmpreg))
2493 opP->error = _("out of range");
2494 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2495 if (isvar (&opP->disp))
2496 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2497 break;
2498 case 'w':
2499 if (!isword (tmpreg))
2500 opP->error = _("out of range");
2501 insop (tmpreg, opcode);
2502 if (isvar (&opP->disp))
2503 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2504 break;
2505 case 'W':
2506 if (!issword (tmpreg))
2507 opP->error = _("out of range");
2508 insop (tmpreg, opcode);
2509 if (isvar (&opP->disp))
2510 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2511 break;
2512 case 'l':
2513 /* Because of the way insop works, we put these two out
2514 backwards. */
2515 insop (tmpreg, opcode);
2516 insop (tmpreg >> 16, opcode);
2517 if (isvar (&opP->disp))
2518 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2519 break;
2520 case '3':
2521 tmpreg &= 0xFF;
2522 case '8':
2523 case 'C':
2524 case 'j':
2525 install_operand (s[1], tmpreg);
2526 break;
2527 default:
2528 abort ();
2529 }
2530 break;
2531
2532 case '+':
2533 case '-':
2534 case 'A':
2535 case 'a':
2536 install_operand (s[1], opP->reg - ADDR);
2537 break;
2538
2539 case 'B':
2540 tmpreg = get_num (&opP->disp, 80);
2541 switch (s[1])
2542 {
2543 case 'B':
2544 add_fix ('B', &opP->disp, 1, -1);
2545 break;
2546 case 'W':
2547 add_fix ('w', &opP->disp, 1, 0);
2548 addword (0);
2549 break;
2550 case 'L':
2551 long_branch:
2552 if (! HAVE_LONG_BRANCH (current_architecture))
2553 as_warn (_("Can't use long branches on 68000/68010/5200"));
2554 the_ins.opcode[0] |= 0xff;
2555 add_fix ('l', &opP->disp, 1, 0);
2556 addword (0);
2557 addword (0);
2558 break;
2559 case 'g':
2560 if (subs (&opP->disp)) /* We can't relax it */
2561 goto long_branch;
2562
2563 #ifdef OBJ_ELF
2564 /* If the displacement needs pic relocation it cannot be
2565 relaxed. */
2566 if (opP->disp.pic_reloc != pic_none)
2567 goto long_branch;
2568 #endif
2569 /* This could either be a symbol, or an absolute
2570 address. If it's an absolute address, turn it into
2571 an absolute jump right here and keep it out of the
2572 relaxer. */
2573 if (adds (&opP->disp) == 0)
2574 {
2575 if (the_ins.opcode[0] == 0x6000) /* jbra */
2576 the_ins.opcode[0] = 0x4EF1;
2577 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2578 the_ins.opcode[0] = 0x4EB1;
2579 else /* jCC */
2580 {
2581 the_ins.opcode[0] ^= 0x0100;
2582 the_ins.opcode[0] |= 0x0006;
2583 addword (0x4EF1);
2584 }
2585 add_fix ('l', &opP->disp, 0, 0);
2586 addword (0);
2587 addword (0);
2588 break;
2589 }
2590
2591 /* Now we know it's going into the relaxer. Now figure
2592 out which mode. We try in this order of preference:
2593 long branch, absolute jump, byte/word branches only. */
2594 if (HAVE_LONG_BRANCH (current_architecture))
2595 add_frag (adds (&opP->disp), offs (&opP->disp),
2596 TAB (BRANCHBWL, SZ_UNDEF));
2597 else if (! flag_keep_pcrel)
2598 {
2599 if ((the_ins.opcode[0] == 0x6000)
2600 || (the_ins.opcode[0] == 0x6100))
2601 add_frag (adds (&opP->disp), offs (&opP->disp),
2602 TAB (BRABSJUNC, SZ_UNDEF));
2603 else
2604 add_frag (adds (&opP->disp), offs (&opP->disp),
2605 TAB (BRABSJCOND, SZ_UNDEF));
2606 }
2607 else
2608 add_frag (adds (&opP->disp), offs (&opP->disp),
2609 TAB (BRANCHBW, SZ_UNDEF));
2610 break;
2611 case 'w':
2612 if (isvar (&opP->disp))
2613 {
2614 /* Check for DBcc instructions. We can relax them,
2615 but only if we have long branches and/or absolute
2616 jumps. */
2617 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2618 && (HAVE_LONG_BRANCH (current_architecture)
2619 || (! flag_keep_pcrel)))
2620 {
2621 if (HAVE_LONG_BRANCH (current_architecture))
2622 add_frag (adds (&opP->disp), offs (&opP->disp),
2623 TAB (DBCCLBR, SZ_UNDEF));
2624 else
2625 add_frag (adds (&opP->disp), offs (&opP->disp),
2626 TAB (DBCCABSJ, SZ_UNDEF));
2627 break;
2628 }
2629 add_fix ('w', &opP->disp, 1, 0);
2630 }
2631 addword (0);
2632 break;
2633 case 'C': /* Fixed size LONG coproc branches */
2634 add_fix ('l', &opP->disp, 1, 0);
2635 addword (0);
2636 addword (0);
2637 break;
2638 case 'c': /* Var size Coprocesssor branches */
2639 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2640 {
2641 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2642 add_fix ('l', &opP->disp, 1, 0);
2643 addword (0);
2644 addword (0);
2645 }
2646 else
2647 add_frag (adds (&opP->disp), offs (&opP->disp),
2648 TAB (FBRANCH, SZ_UNDEF));
2649 break;
2650 default:
2651 abort ();
2652 }
2653 break;
2654
2655 case 'C': /* Ignore it */
2656 break;
2657
2658 case 'd': /* JF this is a kludge */
2659 install_operand ('s', opP->reg - ADDR);
2660 tmpreg = get_num (&opP->disp, 80);
2661 if (!issword (tmpreg))
2662 {
2663 as_warn (_("Expression out of range, using 0"));
2664 tmpreg = 0;
2665 }
2666 addword (tmpreg);
2667 break;
2668
2669 case 'D':
2670 install_operand (s[1], opP->reg - DATA);
2671 break;
2672
2673 case 'E': /* Ignore it */
2674 break;
2675
2676 case 'F':
2677 install_operand (s[1], opP->reg - FP0);
2678 break;
2679
2680 case 'G': /* Ignore it */
2681 case 'H':
2682 break;
2683
2684 case 'I':
2685 tmpreg = opP->reg - COP0;
2686 install_operand (s[1], tmpreg);
2687 break;
2688
2689 case 'J': /* JF foo */
2690 switch (opP->reg)
2691 {
2692 case SFC:
2693 tmpreg = 0x000;
2694 break;
2695 case DFC:
2696 tmpreg = 0x001;
2697 break;
2698 case CACR:
2699 tmpreg = 0x002;
2700 break;
2701 case TC:
2702 tmpreg = 0x003;
2703 break;
2704 case ITT0:
2705 tmpreg = 0x004;
2706 break;
2707 case ITT1:
2708 tmpreg = 0x005;
2709 break;
2710 case DTT0:
2711 tmpreg = 0x006;
2712 break;
2713 case DTT1:
2714 tmpreg = 0x007;
2715 break;
2716 case BUSCR:
2717 tmpreg = 0x008;
2718 break;
2719
2720 case USP:
2721 tmpreg = 0x800;
2722 break;
2723 case VBR:
2724 tmpreg = 0x801;
2725 break;
2726 case CAAR:
2727 tmpreg = 0x802;
2728 break;
2729 case MSP:
2730 tmpreg = 0x803;
2731 break;
2732 case ISP:
2733 tmpreg = 0x804;
2734 break;
2735 case MMUSR:
2736 tmpreg = 0x805;
2737 break;
2738 case URP:
2739 tmpreg = 0x806;
2740 break;
2741 case SRP:
2742 tmpreg = 0x807;
2743 break;
2744 case PCR:
2745 tmpreg = 0x808;
2746 break;
2747 case ROMBAR:
2748 tmpreg = 0xC00;
2749 break;
2750 case RAMBAR0:
2751 tmpreg = 0xC04;
2752 break;
2753 case RAMBAR1:
2754 tmpreg = 0xC05;
2755 break;
2756 case MBAR:
2757 tmpreg = 0xC0F;
2758 break;
2759 default:
2760 abort ();
2761 }
2762 install_operand (s[1], tmpreg);
2763 break;
2764
2765 case 'k':
2766 tmpreg = get_num (&opP->disp, 55);
2767 install_operand (s[1], tmpreg & 0x7f);
2768 break;
2769
2770 case 'l':
2771 tmpreg = opP->mask;
2772 if (s[1] == 'w')
2773 {
2774 if (tmpreg & 0x7FF0000)
2775 as_bad (_("Floating point register in register list"));
2776 insop (reverse_16_bits (tmpreg), opcode);
2777 }
2778 else
2779 {
2780 if (tmpreg & 0x700FFFF)
2781 as_bad (_("Wrong register in floating-point reglist"));
2782 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2783 }
2784 break;
2785
2786 case 'L':
2787 tmpreg = opP->mask;
2788 if (s[1] == 'w')
2789 {
2790 if (tmpreg & 0x7FF0000)
2791 as_bad (_("Floating point register in register list"));
2792 insop (tmpreg, opcode);
2793 }
2794 else if (s[1] == '8')
2795 {
2796 if (tmpreg & 0x0FFFFFF)
2797 as_bad (_("incorrect register in reglist"));
2798 install_operand (s[1], tmpreg >> 24);
2799 }
2800 else
2801 {
2802 if (tmpreg & 0x700FFFF)
2803 as_bad (_("wrong register in floating-point reglist"));
2804 else
2805 install_operand (s[1], tmpreg >> 16);
2806 }
2807 break;
2808
2809 case 'M':
2810 install_operand (s[1], get_num (&opP->disp, 60));
2811 break;
2812
2813 case 'O':
2814 tmpreg = ((opP->mode == DREG)
2815 ? 0x20 + (int) (opP->reg - DATA)
2816 : (get_num (&opP->disp, 40) & 0x1F));
2817 install_operand (s[1], tmpreg);
2818 break;
2819
2820 case 'Q':
2821 tmpreg = get_num (&opP->disp, 10);
2822 if (tmpreg == 8)
2823 tmpreg = 0;
2824 install_operand (s[1], tmpreg);
2825 break;
2826
2827 case 'R':
2828 /* This depends on the fact that ADDR registers are eight
2829 more than their corresponding DATA regs, so the result
2830 will have the ADDR_REG bit set */
2831 install_operand (s[1], opP->reg - DATA);
2832 break;
2833
2834 case 'r':
2835 if (opP->mode == AINDR)
2836 install_operand (s[1], opP->reg - DATA);
2837 else
2838 install_operand (s[1], opP->index.reg - DATA);
2839 break;
2840
2841 case 's':
2842 if (opP->reg == FPI)
2843 tmpreg = 0x1;
2844 else if (opP->reg == FPS)
2845 tmpreg = 0x2;
2846 else if (opP->reg == FPC)
2847 tmpreg = 0x4;
2848 else
2849 abort ();
2850 install_operand (s[1], tmpreg);
2851 break;
2852
2853 case 'S': /* Ignore it */
2854 break;
2855
2856 case 'T':
2857 install_operand (s[1], get_num (&opP->disp, 30));
2858 break;
2859
2860 case 'U': /* Ignore it */
2861 break;
2862
2863 case 'c':
2864 switch (opP->reg)
2865 {
2866 case NC:
2867 tmpreg = 0;
2868 break;
2869 case DC:
2870 tmpreg = 1;
2871 break;
2872 case IC:
2873 tmpreg = 2;
2874 break;
2875 case BC:
2876 tmpreg = 3;
2877 break;
2878 default:
2879 as_fatal (_("failed sanity check"));
2880 } /* switch on cache token */
2881 install_operand (s[1], tmpreg);
2882 break;
2883 #ifndef NO_68851
2884 /* JF: These are out of order, I fear. */
2885 case 'f':
2886 switch (opP->reg)
2887 {
2888 case SFC:
2889 tmpreg = 0;
2890 break;
2891 case DFC:
2892 tmpreg = 1;
2893 break;
2894 default:
2895 abort ();
2896 }
2897 install_operand (s[1], tmpreg);
2898 break;
2899
2900 case '0':
2901 case '1':
2902 case '2':
2903 switch (opP->reg)
2904 {
2905 case TC:
2906 tmpreg = 0;
2907 break;
2908 case CAL:
2909 tmpreg = 4;
2910 break;
2911 case VAL:
2912 tmpreg = 5;
2913 break;
2914 case SCC:
2915 tmpreg = 6;
2916 break;
2917 case AC:
2918 tmpreg = 7;
2919 break;
2920 default:
2921 abort ();
2922 }
2923 install_operand (s[1], tmpreg);
2924 break;
2925
2926 case 'V':
2927 if (opP->reg == VAL)
2928 break;
2929 abort ();
2930
2931 case 'W':
2932 switch (opP->reg)
2933 {
2934 case DRP:
2935 tmpreg = 1;
2936 break;
2937 case SRP:
2938 tmpreg = 2;
2939 break;
2940 case CRP:
2941 tmpreg = 3;
2942 break;
2943 default:
2944 abort ();
2945 }
2946 install_operand (s[1], tmpreg);
2947 break;
2948
2949 case 'X':
2950 switch (opP->reg)
2951 {
2952 case BAD:
2953 case BAD + 1:
2954 case BAD + 2:
2955 case BAD + 3:
2956 case BAD + 4:
2957 case BAD + 5:
2958 case BAD + 6:
2959 case BAD + 7:
2960 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2961 break;
2962
2963 case BAC:
2964 case BAC + 1:
2965 case BAC + 2:
2966 case BAC + 3:
2967 case BAC + 4:
2968 case BAC + 5:
2969 case BAC + 6:
2970 case BAC + 7:
2971 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2972 break;
2973
2974 default:
2975 abort ();
2976 }
2977 install_operand (s[1], tmpreg);
2978 break;
2979 case 'Y':
2980 know (opP->reg == PSR);
2981 break;
2982 case 'Z':
2983 know (opP->reg == PCSR);
2984 break;
2985 #endif /* m68851 */
2986 case '3':
2987 switch (opP->reg)
2988 {
2989 case TT0:
2990 tmpreg = 2;
2991 break;
2992 case TT1:
2993 tmpreg = 3;
2994 break;
2995 default:
2996 abort ();
2997 }
2998 install_operand (s[1], tmpreg);
2999 break;
3000 case 't':
3001 tmpreg = get_num (&opP->disp, 20);
3002 install_operand (s[1], tmpreg);
3003 break;
3004 case '_': /* used only for move16 absolute 32-bit address */
3005 if (isvar (&opP->disp))
3006 add_fix ('l', &opP->disp, 0, 0);
3007 tmpreg = get_num (&opP->disp, 80);
3008 addword (tmpreg >> 16);
3009 addword (tmpreg & 0xFFFF);
3010 break;
3011 case 'u':
3012 install_operand (s[1], opP->reg - DATA0L);
3013 opP->reg -= (DATA0L);
3014 opP->reg &= 0x0F; /* remove upper/lower bit */
3015 break;
3016 default:
3017 abort ();
3018 }
3019 }
3020
3021 /* By the time whe get here (FINALLY) the_ins contains the complete
3022 instruction, ready to be emitted. . . */
3023 }
3024
3025 static int
3026 reverse_16_bits (in)
3027 int in;
3028 {
3029 int out = 0;
3030 int n;
3031
3032 static int mask[16] =
3033 {
3034 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3035 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3036 };
3037 for (n = 0; n < 16; n++)
3038 {
3039 if (in & mask[n])
3040 out |= mask[15 - n];
3041 }
3042 return out;
3043 } /* reverse_16_bits() */
3044
3045 static int
3046 reverse_8_bits (in)
3047 int in;
3048 {
3049 int out = 0;
3050 int n;
3051
3052 static int mask[8] =
3053 {
3054 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3055 };
3056
3057 for (n = 0; n < 8; n++)
3058 {
3059 if (in & mask[n])
3060 out |= mask[7 - n];
3061 }
3062 return out;
3063 } /* reverse_8_bits() */
3064
3065 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3066 (that value is chosen in the frag_var call in md_assemble). TYPE
3067 is the subtype of the frag to be generated; its primary type is
3068 rs_machine_dependent.
3069
3070 The TYPE parameter is also used by md_convert_frag_1 and
3071 md_estimate_size_before_relax. The appropriate type of fixup will
3072 be emitted by md_convert_frag_1.
3073
3074 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3075 static void
3076 install_operand (mode, val)
3077 int mode;
3078 int val;
3079 {
3080 switch (mode)
3081 {
3082 case 's':
3083 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3084 break;
3085 case 'd':
3086 the_ins.opcode[0] |= val << 9;
3087 break;
3088 case '1':
3089 the_ins.opcode[1] |= val << 12;
3090 break;
3091 case '2':
3092 the_ins.opcode[1] |= val << 6;
3093 break;
3094 case '3':
3095 the_ins.opcode[1] |= val;
3096 break;
3097 case '4':
3098 the_ins.opcode[2] |= val << 12;
3099 break;
3100 case '5':
3101 the_ins.opcode[2] |= val << 6;
3102 break;
3103 case '6':
3104 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3105 three words long! */
3106 the_ins.numo++;
3107 the_ins.opcode[2] |= val;
3108 break;
3109 case '7':
3110 the_ins.opcode[1] |= val << 7;
3111 break;
3112 case '8':
3113 the_ins.opcode[1] |= val << 10;
3114 break;
3115 #ifndef NO_68851
3116 case '9':
3117 the_ins.opcode[1] |= val << 5;
3118 break;
3119 #endif
3120
3121 case 't':
3122 the_ins.opcode[1] |= (val << 10) | (val << 7);
3123 break;
3124 case 'D':
3125 the_ins.opcode[1] |= (val << 12) | val;
3126 break;
3127 case 'g':
3128 the_ins.opcode[0] |= val = 0xff;
3129 break;
3130 case 'i':
3131 the_ins.opcode[0] |= val << 9;
3132 break;
3133 case 'C':
3134 the_ins.opcode[1] |= val;
3135 break;
3136 case 'j':
3137 the_ins.opcode[1] |= val;
3138 the_ins.numo++; /* What a hack */
3139 break;
3140 case 'k':
3141 the_ins.opcode[1] |= val << 4;
3142 break;
3143 case 'b':
3144 case 'w':
3145 case 'W':
3146 case 'l':
3147 break;
3148 case 'e':
3149 the_ins.opcode[0] |= (val << 6);
3150 break;
3151 case 'L':
3152 the_ins.opcode[1] = (val >> 16);
3153 the_ins.opcode[2] = val & 0xffff;
3154 break;
3155 case 'm':
3156 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3157 the_ins.opcode[0] |= ((val & 0x7) << 9);
3158 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3159 break;
3160 case 'n':
3161 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3162 the_ins.opcode[0] |= ((val & 0x7) << 9);
3163 break;
3164 case 'o':
3165 the_ins.opcode[1] |= val << 12;
3166 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3167 break;
3168 case 'M':
3169 the_ins.opcode[0] |= (val & 0xF);
3170 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3171 break;
3172 case 'N':
3173 the_ins.opcode[1] |= (val & 0xF);
3174 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3175 break;
3176 case 'h':
3177 the_ins.opcode[1] |= ((val != 1) << 10);
3178 break;
3179 case 'c':
3180 default:
3181 as_fatal (_("failed sanity check."));
3182 }
3183 } /* install_operand() */
3184
3185 static void
3186 install_gen_operand (mode, val)
3187 int mode;
3188 int val;
3189 {
3190 switch (mode)
3191 {
3192 case 's':
3193 the_ins.opcode[0] |= val;
3194 break;
3195 case 'd':
3196 /* This is a kludge!!! */
3197 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3198 break;
3199 case 'b':
3200 case 'w':
3201 case 'l':
3202 case 'f':
3203 case 'F':
3204 case 'x':
3205 case 'p':
3206 the_ins.opcode[0] |= val;
3207 break;
3208 /* more stuff goes here */
3209 default:
3210 as_fatal (_("failed sanity check."));
3211 }
3212 } /* install_gen_operand() */
3213
3214 /*
3215 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3216 * then deal with the bitfield hack.
3217 */
3218
3219 static char *
3220 crack_operand (str, opP)
3221 register char *str;
3222 register struct m68k_op *opP;
3223 {
3224 register int parens;
3225 register int c;
3226 register char *beg_str;
3227 int inquote = 0;
3228
3229 if (!str)
3230 {
3231 return str;
3232 }
3233 beg_str = str;
3234 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3235 {
3236 if (! inquote)
3237 {
3238 if (*str == '(')
3239 parens++;
3240 else if (*str == ')')
3241 {
3242 if (!parens)
3243 { /* ERROR */
3244 opP->error = _("Extra )");
3245 return str;
3246 }
3247 --parens;
3248 }
3249 }
3250 if (flag_mri && *str == '\'')
3251 inquote = ! inquote;
3252 }
3253 if (!*str && parens)
3254 { /* ERROR */
3255 opP->error = _("Missing )");
3256 return str;
3257 }
3258 c = *str;
3259 *str = '\0';
3260 if (m68k_ip_op (beg_str, opP) != 0)
3261 {
3262 *str = c;
3263 return str;
3264 }
3265 *str = c;
3266 if (c == '}')
3267 c = *++str; /* JF bitfield hack */
3268 if (c)
3269 {
3270 c = *++str;
3271 if (!c)
3272 as_bad (_("Missing operand"));
3273 }
3274
3275 /* Detect MRI REG symbols and convert them to REGLSTs. */
3276 if (opP->mode == CONTROL && (int)opP->reg < 0)
3277 {
3278 opP->mode = REGLST;
3279 opP->mask = ~(int)opP->reg;
3280 opP->reg = 0;
3281 }
3282
3283 return str;
3284 }
3285
3286 /* This is the guts of the machine-dependent assembler. STR points to a
3287 machine dependent instruction. This function is supposed to emit
3288 the frags/bytes it assembles to.
3289 */
3290
3291 static void
3292 insert_reg (regname, regnum)
3293 const char *regname;
3294 int regnum;
3295 {
3296 char buf[100];
3297 int i;
3298
3299 #ifdef REGISTER_PREFIX
3300 if (!flag_reg_prefix_optional)
3301 {
3302 buf[0] = REGISTER_PREFIX;
3303 strcpy (buf + 1, regname);
3304 regname = buf;
3305 }
3306 #endif
3307
3308 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3309 &zero_address_frag));
3310
3311 for (i = 0; regname[i]; i++)
3312 buf[i] = TOUPPER (regname[i]);
3313 buf[i] = '\0';
3314
3315 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3316 &zero_address_frag));
3317 }
3318
3319 struct init_entry
3320 {
3321 const char *name;
3322 int number;
3323 };
3324
3325 static const struct init_entry init_table[] =
3326 {
3327 { "d0", DATA0 },
3328 { "d1", DATA1 },
3329 { "d2", DATA2 },
3330 { "d3", DATA3 },
3331 { "d4", DATA4 },
3332 { "d5", DATA5 },
3333 { "d6", DATA6 },
3334 { "d7", DATA7 },
3335 { "a0", ADDR0 },
3336 { "a1", ADDR1 },
3337 { "a2", ADDR2 },
3338 { "a3", ADDR3 },
3339 { "a4", ADDR4 },
3340 { "a5", ADDR5 },
3341 { "a6", ADDR6 },
3342 { "fp", ADDR6 },
3343 { "a7", ADDR7 },
3344 { "sp", ADDR7 },
3345 { "ssp", ADDR7 },
3346 { "fp0", FP0 },
3347 { "fp1", FP1 },
3348 { "fp2", FP2 },
3349 { "fp3", FP3 },
3350 { "fp4", FP4 },
3351 { "fp5", FP5 },
3352 { "fp6", FP6 },
3353 { "fp7", FP7 },
3354 { "fpi", FPI },
3355 { "fpiar", FPI },
3356 { "fpc", FPI },
3357 { "fps", FPS },
3358 { "fpsr", FPS },
3359 { "fpc", FPC },
3360 { "fpcr", FPC },
3361 { "control", FPC },
3362 { "status", FPS },
3363 { "iaddr", FPI },
3364
3365 { "cop0", COP0 },
3366 { "cop1", COP1 },
3367 { "cop2", COP2 },
3368 { "cop3", COP3 },
3369 { "cop4", COP4 },
3370 { "cop5", COP5 },
3371 { "cop6", COP6 },
3372 { "cop7", COP7 },
3373 { "pc", PC },
3374 { "zpc", ZPC },
3375 { "sr", SR },
3376
3377 { "ccr", CCR },
3378 { "cc", CCR },
3379
3380 { "acc", ACC },
3381 { "macsr", MACSR },
3382 { "mask", MASK },
3383
3384 /* control registers */
3385 { "sfc", SFC }, /* Source Function Code */
3386 { "sfcr", SFC },
3387 { "dfc", DFC }, /* Destination Function Code */
3388 { "dfcr", DFC },
3389 { "cacr", CACR }, /* Cache Control Register */
3390 { "caar", CAAR }, /* Cache Address Register */
3391
3392 { "usp", USP }, /* User Stack Pointer */
3393 { "vbr", VBR }, /* Vector Base Register */
3394 { "msp", MSP }, /* Master Stack Pointer */
3395 { "isp", ISP }, /* Interrupt Stack Pointer */
3396
3397 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3398 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3399 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3400 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3401
3402 /* 68ec040 versions of same */
3403 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3404 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3405 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3406 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3407
3408 /* mcf5200 versions of same. The ColdFire programmer's reference
3409 manual indicated that the order is 2,3,0,1, but Ken Rose
3410 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3411 { "acr0", ITT0 }, /* Access Control Unit 0 */
3412 { "acr1", ITT1 }, /* Access Control Unit 1 */
3413 { "acr2", DTT0 }, /* Access Control Unit 2 */
3414 { "acr3", DTT1 }, /* Access Control Unit 3 */
3415
3416 { "tc", TC }, /* MMU Translation Control Register */
3417 { "tcr", TC },
3418
3419 { "mmusr", MMUSR }, /* MMU Status Register */
3420 { "srp", SRP }, /* User Root Pointer */
3421 { "urp", URP }, /* Supervisor Root Pointer */
3422
3423 { "buscr", BUSCR },
3424 { "pcr", PCR },
3425
3426 { "rombar", ROMBAR }, /* ROM Base Address Register */
3427 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3428 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3429 { "mbar", MBAR }, /* Module Base Address Register */
3430 /* end of control registers */
3431
3432 { "ac", AC },
3433 { "bc", BC },
3434 { "cal", CAL },
3435 { "crp", CRP },
3436 { "drp", DRP },
3437 { "pcsr", PCSR },
3438 { "psr", PSR },
3439 { "scc", SCC },
3440 { "val", VAL },
3441 { "bad0", BAD0 },
3442 { "bad1", BAD1 },
3443 { "bad2", BAD2 },
3444 { "bad3", BAD3 },
3445 { "bad4", BAD4 },
3446 { "bad5", BAD5 },
3447 { "bad6", BAD6 },
3448 { "bad7", BAD7 },
3449 { "bac0", BAC0 },
3450 { "bac1", BAC1 },
3451 { "bac2", BAC2 },
3452 { "bac3", BAC3 },
3453 { "bac4", BAC4 },
3454 { "bac5", BAC5 },
3455 { "bac6", BAC6 },
3456 { "bac7", BAC7 },
3457
3458 { "ic", IC },
3459 { "dc", DC },
3460 { "nc", NC },
3461
3462 { "tt0", TT0 },
3463 { "tt1", TT1 },
3464 /* 68ec030 versions of same */
3465 { "ac0", TT0 },
3466 { "ac1", TT1 },
3467 /* 68ec030 access control unit, identical to 030 MMU status reg */
3468 { "acusr", PSR },
3469
3470 /* Suppressed data and address registers. */
3471 { "zd0", ZDATA0 },
3472 { "zd1", ZDATA1 },
3473 { "zd2", ZDATA2 },
3474 { "zd3", ZDATA3 },
3475 { "zd4", ZDATA4 },
3476 { "zd5", ZDATA5 },
3477 { "zd6", ZDATA6 },
3478 { "zd7", ZDATA7 },
3479 { "za0", ZADDR0 },
3480 { "za1", ZADDR1 },
3481 { "za2", ZADDR2 },
3482 { "za3", ZADDR3 },
3483 { "za4", ZADDR4 },
3484 { "za5", ZADDR5 },
3485 { "za6", ZADDR6 },
3486 { "za7", ZADDR7 },
3487
3488 /* Upper and lower data and address registers, used by macw and msacw. */
3489 { "d0l", DATA0L },
3490 { "d1l", DATA1L },
3491 { "d2l", DATA2L },
3492 { "d3l", DATA3L },
3493 { "d4l", DATA4L },
3494 { "d5l", DATA5L },
3495 { "d6l", DATA6L },
3496 { "d7l", DATA7L },
3497
3498 { "a0l", ADDR0L },
3499 { "a1l", ADDR1L },
3500 { "a2l", ADDR2L },
3501 { "a3l", ADDR3L },
3502 { "a4l", ADDR4L },
3503 { "a5l", ADDR5L },
3504 { "a6l", ADDR6L },
3505 { "a7l", ADDR7L },
3506
3507 { "d0u", DATA0U },
3508 { "d1u", DATA1U },
3509 { "d2u", DATA2U },
3510 { "d3u", DATA3U },
3511 { "d4u", DATA4U },
3512 { "d5u", DATA5U },
3513 { "d6u", DATA6U },
3514 { "d7u", DATA7U },
3515
3516 { "a0u", ADDR0U },
3517 { "a1u", ADDR1U },
3518 { "a2u", ADDR2U },
3519 { "a3u", ADDR3U },
3520 { "a4u", ADDR4U },
3521 { "a5u", ADDR5U },
3522 { "a6u", ADDR6U },
3523 { "a7u", ADDR7U },
3524
3525 { 0, 0 }
3526 };
3527
3528 static void
3529 init_regtable ()
3530 {
3531 int i;
3532 for (i = 0; init_table[i].name; i++)
3533 insert_reg (init_table[i].name, init_table[i].number);
3534 }
3535
3536 static int no_68851, no_68881;
3537
3538 #ifdef OBJ_AOUT
3539 /* a.out machine type. Default to 68020. */
3540 int m68k_aout_machtype = 2;
3541 #endif
3542
3543 void
3544 md_assemble (str)
3545 char *str;
3546 {
3547 const char *er;
3548 short *fromP;
3549 char *toP = NULL;
3550 int m, n = 0;
3551 char *to_beg_P;
3552 int shorts_this_frag;
3553 fixS *fixP;
3554
3555 /* In MRI mode, the instruction and operands are separated by a
3556 space. Anything following the operands is a comment. The label
3557 has already been removed. */
3558 if (flag_mri)
3559 {
3560 char *s;
3561 int fields = 0;
3562 int infield = 0;
3563 int inquote = 0;
3564
3565 for (s = str; *s != '\0'; s++)
3566 {
3567 if ((*s == ' ' || *s == '\t') && ! inquote)
3568 {
3569 if (infield)
3570 {
3571 ++fields;
3572 if (fields >= 2)
3573 {
3574 *s = '\0';
3575 break;
3576 }
3577 infield = 0;
3578 }
3579 }
3580 else
3581 {
3582 if (! infield)
3583 infield = 1;
3584 if (*s == '\'')
3585 inquote = ! inquote;
3586 }
3587 }
3588 }
3589
3590 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3591 m68k_ip (str);
3592 er = the_ins.error;
3593 if (!er)
3594 {
3595 for (n = 0; n < the_ins.numargs; n++)
3596 if (the_ins.operands[n].error)
3597 {
3598 er = the_ins.operands[n].error;
3599 break;
3600 }
3601 }
3602 if (er)
3603 {
3604 as_bad (_("%s -- statement `%s' ignored"), er, str);
3605 return;
3606 }
3607
3608 /* If there is a current label, record that it marks an instruction. */
3609 if (current_label != NULL)
3610 {
3611 current_label->text = 1;
3612 current_label = NULL;
3613 }
3614
3615 #ifdef OBJ_ELF
3616 /* Tie dwarf2 debug info to the address at the start of the insn. */
3617 dwarf2_emit_insn (0);
3618 #endif
3619
3620 if (the_ins.nfrag == 0)
3621 {
3622 /* No frag hacking involved; just put it out */
3623 toP = frag_more (2 * the_ins.numo);
3624 fromP = &the_ins.opcode[0];
3625 for (m = the_ins.numo; m; --m)
3626 {
3627 md_number_to_chars (toP, (long) (*fromP), 2);
3628 toP += 2;
3629 fromP++;
3630 }
3631 /* put out symbol-dependent info */
3632 for (m = 0; m < the_ins.nrel; m++)
3633 {
3634 switch (the_ins.reloc[m].wid)
3635 {
3636 case 'B':
3637 n = 1;
3638 break;
3639 case 'b':
3640 n = 1;
3641 break;
3642 case '3':
3643 n = 1;
3644 break;
3645 case 'w':
3646 case 'W':
3647 n = 2;
3648 break;
3649 case 'l':
3650 n = 4;
3651 break;
3652 default:
3653 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3654 the_ins.reloc[m].wid);
3655 }
3656
3657 fixP = fix_new_exp (frag_now,
3658 ((toP - frag_now->fr_literal)
3659 - the_ins.numo * 2 + the_ins.reloc[m].n),
3660 n,
3661 &the_ins.reloc[m].exp,
3662 the_ins.reloc[m].pcrel,
3663 get_reloc_code (n, the_ins.reloc[m].pcrel,
3664 the_ins.reloc[m].pic_reloc));
3665 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3666 if (the_ins.reloc[m].wid == 'B')
3667 fixP->fx_signed = 1;
3668 }
3669 return;
3670 }
3671
3672 /* There's some frag hacking */
3673 {
3674 /* Calculate the max frag size. */
3675 int wid;
3676
3677 wid = 2 * the_ins.fragb[0].fragoff;
3678 for (n = 1; n < the_ins.nfrag; n++)
3679 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3680 /* frag_var part. */
3681 wid += 10;
3682 /* Make sure the whole insn fits in one chunk, in particular that
3683 the var part is attached, as we access one byte before the
3684 variable frag for byte branches. */
3685 frag_grow (wid);
3686 }
3687
3688 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3689 {
3690 int wid;
3691
3692 if (n == 0)
3693 wid = 2 * the_ins.fragb[n].fragoff;
3694 else
3695 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3696 toP = frag_more (wid);
3697 to_beg_P = toP;
3698 shorts_this_frag = 0;
3699 for (m = wid / 2; m; --m)
3700 {
3701 md_number_to_chars (toP, (long) (*fromP), 2);
3702 toP += 2;
3703 fromP++;
3704 shorts_this_frag++;
3705 }
3706 for (m = 0; m < the_ins.nrel; m++)
3707 {
3708 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3709 {
3710 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3711 break;
3712 }
3713 wid = the_ins.reloc[m].wid;
3714 if (wid == 0)
3715 continue;
3716 the_ins.reloc[m].wid = 0;
3717 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3718
3719 fixP = fix_new_exp (frag_now,
3720 ((toP - frag_now->fr_literal)
3721 - the_ins.numo * 2 + the_ins.reloc[m].n),
3722 wid,
3723 &the_ins.reloc[m].exp,
3724 the_ins.reloc[m].pcrel,
3725 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3726 the_ins.reloc[m].pic_reloc));
3727 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3728 }
3729 (void) frag_var (rs_machine_dependent, 10, 0,
3730 (relax_substateT) (the_ins.fragb[n].fragty),
3731 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3732 }
3733 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3734 shorts_this_frag = 0;
3735 if (n)
3736 {
3737 toP = frag_more (n * sizeof (short));
3738 while (n--)
3739 {
3740 md_number_to_chars (toP, (long) (*fromP), 2);
3741 toP += 2;
3742 fromP++;
3743 shorts_this_frag++;
3744 }
3745 }
3746 for (m = 0; m < the_ins.nrel; m++)
3747 {
3748 int wid;
3749
3750 wid = the_ins.reloc[m].wid;
3751 if (wid == 0)
3752 continue;
3753 the_ins.reloc[m].wid = 0;
3754 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3755
3756 fixP = fix_new_exp (frag_now,
3757 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3758 - shorts_this_frag * 2),
3759 wid,
3760 &the_ins.reloc[m].exp,
3761 the_ins.reloc[m].pcrel,
3762 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3763 the_ins.reloc[m].pic_reloc));
3764 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3765 }
3766 }
3767
3768 void
3769 md_begin ()
3770 {
3771 /*
3772 * md_begin -- set up hash tables with 68000 instructions.
3773 * similar to what the vax assembler does. ---phr
3774 */
3775 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3776 a copy of it at runtime, adding in the information we want but isn't
3777 there. I think it'd be better to have an awk script hack the table
3778 at compile time. Or even just xstr the table and use it as-is. But
3779 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3780 names. */
3781
3782 register const struct m68k_opcode *ins;
3783 register struct m68k_incant *hack, *slak;
3784 register const char *retval = 0; /* empty string, or error msg text */
3785 register int i;
3786 register char c;
3787
3788 if (flag_mri)
3789 {
3790 flag_reg_prefix_optional = 1;
3791 m68k_abspcadd = 1;
3792 if (! m68k_rel32_from_cmdline)
3793 m68k_rel32 = 0;
3794 }
3795
3796 op_hash = hash_new ();
3797
3798 obstack_begin (&robyn, 4000);
3799 for (i = 0; i < m68k_numopcodes; i++)
3800 {
3801 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3802 do
3803 {
3804 ins = &m68k_opcodes[i];
3805 /* We *could* ignore insns that don't match our arch here
3806 but just leaving them out of the hash. */
3807 slak->m_operands = ins->args;
3808 slak->m_opnum = strlen (slak->m_operands) / 2;
3809 slak->m_arch = ins->arch;
3810 slak->m_opcode = ins->opcode;
3811 /* This is kludgey */
3812 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3813 if (i + 1 != m68k_numopcodes
3814 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3815 {
3816 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3817 i++;
3818 }
3819 else
3820 slak->m_next = 0;
3821 slak = slak->m_next;
3822 }
3823 while (slak);
3824
3825 retval = hash_insert (op_hash, ins->name, (char *) hack);
3826 if (retval)
3827 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3828 }
3829
3830 for (i = 0; i < m68k_numaliases; i++)
3831 {
3832 const char *name = m68k_opcode_aliases[i].primary;
3833 const char *alias = m68k_opcode_aliases[i].alias;
3834 PTR val = hash_find (op_hash, name);
3835 if (!val)
3836 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3837 retval = hash_insert (op_hash, alias, val);
3838 if (retval)
3839 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3840 }
3841
3842 /* In MRI mode, all unsized branches are variable sized. Normally,
3843 they are word sized. */
3844 if (flag_mri)
3845 {
3846 static struct m68k_opcode_alias mri_aliases[] =
3847 {
3848 { "bhi", "jhi", },
3849 { "bls", "jls", },
3850 { "bcc", "jcc", },
3851 { "bcs", "jcs", },
3852 { "bne", "jne", },
3853 { "beq", "jeq", },
3854 { "bvc", "jvc", },
3855 { "bvs", "jvs", },
3856 { "bpl", "jpl", },
3857 { "bmi", "jmi", },
3858 { "bge", "jge", },
3859 { "blt", "jlt", },
3860 { "bgt", "jgt", },
3861 { "ble", "jle", },
3862 { "bra", "jra", },
3863 { "bsr", "jbsr", },
3864 };
3865
3866 for (i = 0;
3867 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3868 i++)
3869 {
3870 const char *name = mri_aliases[i].primary;
3871 const char *alias = mri_aliases[i].alias;
3872 PTR val = hash_find (op_hash, name);
3873 if (!val)
3874 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3875 retval = hash_jam (op_hash, alias, val);
3876 if (retval)
3877 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3878 }
3879 }
3880
3881 for (i = 0; i < (int) sizeof (notend_table); i++)
3882 {
3883 notend_table[i] = 0;
3884 alt_notend_table[i] = 0;
3885 }
3886 notend_table[','] = 1;
3887 notend_table['{'] = 1;
3888 notend_table['}'] = 1;
3889 alt_notend_table['a'] = 1;
3890 alt_notend_table['A'] = 1;
3891 alt_notend_table['d'] = 1;
3892 alt_notend_table['D'] = 1;
3893 alt_notend_table['#'] = 1;
3894 alt_notend_table['&'] = 1;
3895 alt_notend_table['f'] = 1;
3896 alt_notend_table['F'] = 1;
3897 #ifdef REGISTER_PREFIX
3898 alt_notend_table[REGISTER_PREFIX] = 1;
3899 #endif
3900
3901 /* We need to put '(' in alt_notend_table to handle
3902 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3903 */
3904 alt_notend_table['('] = 1;
3905
3906 /* We need to put '@' in alt_notend_table to handle
3907 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3908 */
3909 alt_notend_table['@'] = 1;
3910
3911 /* We need to put digits in alt_notend_table to handle
3912 bfextu %d0{24:1},%d0
3913 */
3914 alt_notend_table['0'] = 1;
3915 alt_notend_table['1'] = 1;
3916 alt_notend_table['2'] = 1;
3917 alt_notend_table['3'] = 1;
3918 alt_notend_table['4'] = 1;
3919 alt_notend_table['5'] = 1;
3920 alt_notend_table['6'] = 1;
3921 alt_notend_table['7'] = 1;
3922 alt_notend_table['8'] = 1;
3923 alt_notend_table['9'] = 1;
3924
3925 #ifndef MIT_SYNTAX_ONLY
3926 /* Insert pseudo ops, these have to go into the opcode table since
3927 gas expects pseudo ops to start with a dot */
3928 {
3929 int n = 0;
3930 while (mote_pseudo_table[n].poc_name)
3931 {
3932 hack = (struct m68k_incant *)
3933 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3934 hash_insert (op_hash,
3935 mote_pseudo_table[n].poc_name, (char *) hack);
3936 hack->m_operands = 0;
3937 hack->m_opnum = n;
3938 n++;
3939 }
3940 }
3941 #endif
3942
3943 init_regtable ();
3944
3945 #ifdef OBJ_ELF
3946 record_alignment (text_section, 2);
3947 record_alignment (data_section, 2);
3948 record_alignment (bss_section, 2);
3949 #endif
3950 }
3951
3952 static void
3953 select_control_regs ()
3954 {
3955 /* Note which set of "movec" control registers is available. */
3956 switch (cpu_of_arch (current_architecture))
3957 {
3958 case m68000:
3959 control_regs = m68000_control_regs;
3960 break;
3961 case m68010:
3962 control_regs = m68010_control_regs;
3963 break;
3964 case m68020:
3965 case m68030:
3966 control_regs = m68020_control_regs;
3967 break;
3968 case m68040:
3969 control_regs = m68040_control_regs;
3970 break;
3971 case m68060:
3972 control_regs = m68060_control_regs;
3973 break;
3974 case cpu32:
3975 control_regs = cpu32_control_regs;
3976 break;
3977 case mcf5200:
3978 case mcf5206e:
3979 case mcf5307:
3980 case mcf5407:
3981 control_regs = mcf_control_regs;
3982 break;
3983 default:
3984 abort ();
3985 }
3986 }
3987
3988 void
3989 m68k_init_after_args ()
3990 {
3991 if (cpu_of_arch (current_architecture) == 0)
3992 {
3993 int i;
3994 const char *default_cpu = TARGET_CPU;
3995
3996 if (*default_cpu == 'm')
3997 default_cpu++;
3998 for (i = 0; i < n_archs; i++)
3999 if (strcasecmp (default_cpu, archs[i].name) == 0)
4000 break;
4001 if (i == n_archs)
4002 {
4003 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4004 current_architecture |= m68020;
4005 }
4006 else
4007 current_architecture |= archs[i].arch;
4008 }
4009 /* Permit m68881 specification with all cpus; those that can't work
4010 with a coprocessor could be doing emulation. */
4011 if (current_architecture & m68851)
4012 {
4013 if (current_architecture & m68040)
4014 {
4015 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4016 }
4017 }
4018 /* What other incompatibilities could we check for? */
4019
4020 /* Toss in some default assumptions about coprocessors. */
4021 if (!no_68881
4022 && (cpu_of_arch (current_architecture)
4023 /* Can CPU32 have a 68881 coprocessor?? */
4024 & (m68020 | m68030 | cpu32)))
4025 {
4026 current_architecture |= m68881;
4027 }
4028 if (!no_68851
4029 && (cpu_of_arch (current_architecture) & m68020up) != 0
4030 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4031 {
4032 current_architecture |= m68851;
4033 }
4034 if (no_68881 && (current_architecture & m68881))
4035 as_bad (_("options for 68881 and no-68881 both given"));
4036 if (no_68851 && (current_architecture & m68851))
4037 as_bad (_("options for 68851 and no-68851 both given"));
4038
4039 #ifdef OBJ_AOUT
4040 /* Work out the magic number. This isn't very general. */
4041 if (current_architecture & m68000)
4042 m68k_aout_machtype = 0;
4043 else if (current_architecture & m68010)
4044 m68k_aout_machtype = 1;
4045 else if (current_architecture & m68020)
4046 m68k_aout_machtype = 2;
4047 else
4048 m68k_aout_machtype = 2;
4049 #endif
4050
4051 /* Note which set of "movec" control registers is available. */
4052 select_control_regs ();
4053
4054 if (cpu_of_arch (current_architecture) < m68020
4055 || arch_coldfire_p (current_architecture))
4056 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4057 }
4058 \f
4059 /* This is called when a label is defined. */
4060
4061 void
4062 m68k_frob_label (sym)
4063 symbolS *sym;
4064 {
4065 struct label_line *n;
4066
4067 n = (struct label_line *) xmalloc (sizeof *n);
4068 n->next = labels;
4069 n->label = sym;
4070 as_where (&n->file, &n->line);
4071 n->text = 0;
4072 labels = n;
4073 current_label = n;
4074 }
4075
4076 /* This is called when a value that is not an instruction is emitted. */
4077
4078 void
4079 m68k_flush_pending_output ()
4080 {
4081 current_label = NULL;
4082 }
4083
4084 /* This is called at the end of the assembly, when the final value of
4085 the label is known. We warn if this is a text symbol aligned at an
4086 odd location. */
4087
4088 void
4089 m68k_frob_symbol (sym)
4090 symbolS *sym;
4091 {
4092 if (S_GET_SEGMENT (sym) == reg_section
4093 && (int) S_GET_VALUE (sym) < 0)
4094 {
4095 S_SET_SEGMENT (sym, absolute_section);
4096 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4097 }
4098 else if ((S_GET_VALUE (sym) & 1) != 0)
4099 {
4100 struct label_line *l;
4101
4102 for (l = labels; l != NULL; l = l->next)
4103 {
4104 if (l->label == sym)
4105 {
4106 if (l->text)
4107 as_warn_where (l->file, l->line,
4108 _("text label `%s' aligned to odd boundary"),
4109 S_GET_NAME (sym));
4110 break;
4111 }
4112 }
4113 }
4114 }
4115 \f
4116 /* This is called if we go in or out of MRI mode because of the .mri
4117 pseudo-op. */
4118
4119 void
4120 m68k_mri_mode_change (on)
4121 int on;
4122 {
4123 if (on)
4124 {
4125 if (! flag_reg_prefix_optional)
4126 {
4127 flag_reg_prefix_optional = 1;
4128 #ifdef REGISTER_PREFIX
4129 init_regtable ();
4130 #endif
4131 }
4132 m68k_abspcadd = 1;
4133 if (! m68k_rel32_from_cmdline)
4134 m68k_rel32 = 0;
4135 }
4136 else
4137 {
4138 if (! reg_prefix_optional_seen)
4139 {
4140 #ifdef REGISTER_PREFIX_OPTIONAL
4141 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4142 #else
4143 flag_reg_prefix_optional = 0;
4144 #endif
4145 #ifdef REGISTER_PREFIX
4146 init_regtable ();
4147 #endif
4148 }
4149 m68k_abspcadd = 0;
4150 if (! m68k_rel32_from_cmdline)
4151 m68k_rel32 = 1;
4152 }
4153 }
4154
4155 /* Equal to MAX_PRECISION in atof-ieee.c */
4156 #define MAX_LITTLENUMS 6
4157
4158 /* Turn a string in input_line_pointer into a floating point constant
4159 of type TYPE, and store the appropriate bytes in *LITP. The number
4160 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4161 returned, or NULL on OK. */
4162
4163 char *
4164 md_atof (type, litP, sizeP)
4165 char type;
4166 char *litP;
4167 int *sizeP;
4168 {
4169 int prec;
4170 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4171 LITTLENUM_TYPE *wordP;
4172 char *t;
4173
4174 switch (type)
4175 {
4176 case 'f':
4177 case 'F':
4178 case 's':
4179 case 'S':
4180 prec = 2;
4181 break;
4182
4183 case 'd':
4184 case 'D':
4185 case 'r':
4186 case 'R':
4187 prec = 4;
4188 break;
4189
4190 case 'x':
4191 case 'X':
4192 prec = 6;
4193 break;
4194
4195 case 'p':
4196 case 'P':
4197 prec = 6;
4198 break;
4199
4200 default:
4201 *sizeP = 0;
4202 return _("Bad call to MD_ATOF()");
4203 }
4204 t = atof_ieee (input_line_pointer, type, words);
4205 if (t)
4206 input_line_pointer = t;
4207
4208 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4209 for (wordP = words; prec--;)
4210 {
4211 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4212 litP += sizeof (LITTLENUM_TYPE);
4213 }
4214 return 0;
4215 }
4216
4217 void
4218 md_number_to_chars (buf, val, n)
4219 char *buf;
4220 valueT val;
4221 int n;
4222 {
4223 number_to_chars_bigendian (buf, val, n);
4224 }
4225
4226 static void
4227 md_apply_fix_2 (fixP, val)
4228 fixS *fixP;
4229 offsetT val;
4230 {
4231 addressT upper_limit;
4232 offsetT lower_limit;
4233
4234 /* This is unnecessary but it convinces the native rs6000 compiler
4235 to generate the code we want. */
4236 char *buf = fixP->fx_frag->fr_literal;
4237 buf += fixP->fx_where;
4238 /* end ibm compiler workaround */
4239
4240 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4241
4242 #ifdef OBJ_ELF
4243 if (fixP->fx_addsy)
4244 {
4245 memset (buf, 0, fixP->fx_size);
4246 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4247
4248 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4249 && !S_IS_DEFINED (fixP->fx_addsy)
4250 && !S_IS_WEAK (fixP->fx_addsy))
4251 S_SET_WEAK (fixP->fx_addsy);
4252 return;
4253 }
4254 #endif
4255
4256 #ifdef BFD_ASSEMBLER
4257 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4258 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4259 return;
4260 #endif
4261
4262 switch (fixP->fx_size)
4263 {
4264 /* The cast to offsetT below are necessary to make code correct for
4265 machines where ints are smaller than offsetT */
4266 case 1:
4267 *buf++ = val;
4268 upper_limit = 0x7f;
4269 lower_limit = - (offsetT) 0x80;
4270 break;
4271 case 2:
4272 *buf++ = (val >> 8);
4273 *buf++ = val;
4274 upper_limit = 0x7fff;
4275 lower_limit = - (offsetT) 0x8000;
4276 break;
4277 case 4:
4278 *buf++ = (val >> 24);
4279 *buf++ = (val >> 16);
4280 *buf++ = (val >> 8);
4281 *buf++ = val;
4282 upper_limit = 0x7fffffff;
4283 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4284 break;
4285 default:
4286 BAD_CASE (fixP->fx_size);
4287 }
4288
4289 /* Fix up a negative reloc. */
4290 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4291 {
4292 fixP->fx_addsy = fixP->fx_subsy;
4293 fixP->fx_subsy = NULL;
4294 fixP->fx_tcbit = 1;
4295 }
4296
4297 /* For non-pc-relative values, it's conceivable we might get something
4298 like "0xff" for a byte field. So extend the upper part of the range
4299 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4300 so that we can do any range checking at all. */
4301 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4302 upper_limit = upper_limit * 2 + 1;
4303
4304 if ((addressT) val > upper_limit
4305 && (val > 0 || val < lower_limit))
4306 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4307
4308 /* A one byte PC-relative reloc means a short branch. We can't use
4309 a short branch with a value of 0 or -1, because those indicate
4310 different opcodes (branches with longer offsets). fixup_segment
4311 in write.c may have clobbered fx_pcrel, so we need to examine the
4312 reloc type. */
4313 if ((fixP->fx_pcrel
4314 #ifdef BFD_ASSEMBLER
4315 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4316 #endif
4317 )
4318 && fixP->fx_size == 1
4319 && (fixP->fx_addsy == NULL
4320 || S_IS_DEFINED (fixP->fx_addsy))
4321 && (val == 0 || val == -1))
4322 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4323 }
4324
4325 #ifdef BFD_ASSEMBLER
4326 int
4327 md_apply_fix (fixP, valp)
4328 fixS *fixP;
4329 valueT *valp;
4330 {
4331 md_apply_fix_2 (fixP, (addressT) *valp);
4332 return 1;
4333 }
4334 #else
4335 void md_apply_fix (fixP, val)
4336 fixS *fixP;
4337 long val;
4338 {
4339 md_apply_fix_2 (fixP, (addressT) val);
4340 }
4341 #endif
4342
4343 /* *fragP has been relaxed to its final size, and now needs to have
4344 the bytes inside it modified to conform to the new size There is UGLY
4345 MAGIC here. ..
4346 */
4347 static void
4348 md_convert_frag_1 (fragP)
4349 register fragS *fragP;
4350 {
4351 long disp;
4352 fixS *fixP;
4353
4354 /* Address in object code of the displacement. */
4355 register int object_address = fragP->fr_fix + fragP->fr_address;
4356
4357 /* Address in gas core of the place to store the displacement. */
4358 /* This convinces the native rs6000 compiler to generate the code we
4359 want. */
4360 register char *buffer_address = fragP->fr_literal;
4361 buffer_address += fragP->fr_fix;
4362 /* end ibm compiler workaround */
4363
4364 /* The displacement of the address, from current location. */
4365 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4366 disp = (disp + fragP->fr_offset) - object_address;
4367
4368 switch (fragP->fr_subtype)
4369 {
4370 case TAB (BRANCHBWL, BYTE):
4371 case TAB (BRABSJUNC, BYTE):
4372 case TAB (BRABSJCOND, BYTE):
4373 case TAB (BRANCHBW, BYTE):
4374 know (issbyte (disp));
4375 if (disp == 0)
4376 as_bad_where (fragP->fr_file, fragP->fr_line,
4377 _("short branch with zero offset: use :w"));
4378 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4379 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4380 fixP->fx_pcrel_adjust = -1;
4381 break;
4382 case TAB (BRANCHBWL, SHORT):
4383 case TAB (BRABSJUNC, SHORT):
4384 case TAB (BRABSJCOND, SHORT):
4385 case TAB (BRANCHBW, SHORT):
4386 fragP->fr_opcode[1] = 0x00;
4387 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4388 1, RELAX_RELOC_PC16);
4389 fragP->fr_fix += 2;
4390 break;
4391 case TAB (BRANCHBWL, LONG):
4392 fragP->fr_opcode[1] = (char) 0xFF;
4393 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4394 1, RELAX_RELOC_PC32);
4395 fragP->fr_fix += 4;
4396 break;
4397 case TAB (BRABSJUNC, LONG):
4398 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4399 {
4400 fragP->fr_opcode[0] = 0x4E;
4401 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4402 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4403 0, RELAX_RELOC_ABS32);
4404 fragP->fr_fix += 4;
4405 }
4406 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4407 {
4408 fragP->fr_opcode[0] = 0x4E;
4409 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4410 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4411 0, RELAX_RELOC_ABS32);
4412 fragP->fr_fix += 4;
4413 }
4414 else
4415 {
4416 /* This cannot happen, because jbsr and jbra are the only two
4417 unconditional branches. */
4418 abort ();
4419 }
4420 break;
4421 case TAB (BRABSJCOND, LONG):
4422 /* Only Bcc 68000 instructions can come here. */
4423 /* Change bcc into b!cc/jmp absl long. */
4424
4425 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4426 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4427
4428 /* JF: these used to be fr_opcode[2,3], but they may be in a
4429 different frag, in which case refering to them is a no-no.
4430 Only fr_opcode[0,1] are guaranteed to work. */
4431 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4432 *buffer_address++ = (char) 0xf9;
4433 fragP->fr_fix += 2; /* account for jmp instruction */
4434 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4435 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4436 fragP->fr_fix += 4;
4437 break;
4438 case TAB (FBRANCH, SHORT):
4439 know ((fragP->fr_opcode[1] & 0x40) == 0);
4440 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4441 1, RELAX_RELOC_PC16);
4442 fragP->fr_fix += 2;
4443 break;
4444 case TAB (FBRANCH, LONG):
4445 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4446 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4447 1, RELAX_RELOC_PC32);
4448 fragP->fr_fix += 4;
4449 break;
4450 case TAB (DBCCLBR, SHORT):
4451 case TAB (DBCCABSJ, SHORT):
4452 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4453 1, RELAX_RELOC_PC16);
4454 fragP->fr_fix += 2;
4455 break;
4456 case TAB (DBCCLBR, LONG):
4457 /* only DBcc instructions can come here */
4458 /* Change dbcc into dbcc/bral. */
4459
4460 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4461 *buffer_address++ = 0x00; /* branch offset = 4 */
4462 *buffer_address++ = 0x04;
4463 *buffer_address++ = 0x60; /* put in bra pc+6 */
4464 *buffer_address++ = 0x06;
4465 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4466 *buffer_address++ = (char) 0xff;
4467
4468 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4469 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4470 RELAX_RELOC_PC32);
4471 fragP->fr_fix += 4;
4472 break;
4473 case TAB (DBCCABSJ, LONG):
4474 /* only DBcc instructions can come here */
4475 /* Change dbcc into dbcc/jmp. */
4476
4477 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4478 *buffer_address++ = 0x00; /* branch offset = 4 */
4479 *buffer_address++ = 0x04;
4480 *buffer_address++ = 0x60; /* put in bra pc+6 */
4481 *buffer_address++ = 0x06;
4482 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4483 *buffer_address++ = (char) 0xf9;
4484
4485 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4486 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4487 RELAX_RELOC_ABS32);
4488 fragP->fr_fix += 4;
4489 break;
4490 case TAB (PCREL1632, SHORT):
4491 fragP->fr_opcode[1] &= ~0x3F;
4492 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4493 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4494 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4495 fragP->fr_fix += 2;
4496 break;
4497 case TAB (PCREL1632, LONG):
4498 /* Already set to mode 7.3; this indicates: PC indirect with
4499 suppressed index, 32-bit displacement. */
4500 *buffer_address++ = 0x01;
4501 *buffer_address++ = 0x70;
4502 fragP->fr_fix += 2;
4503 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4504 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4505 fixP->fx_pcrel_adjust = 2;
4506 fragP->fr_fix += 4;
4507 break;
4508 case TAB (PCINDEX, BYTE):
4509 assert (fragP->fr_fix >= 2);
4510 buffer_address[-2] &= ~1;
4511 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4512 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4513 fixP->fx_pcrel_adjust = 1;
4514 break;
4515 case TAB (PCINDEX, SHORT):
4516 assert (fragP->fr_fix >= 2);
4517 buffer_address[-2] |= 0x1;
4518 buffer_address[-1] = 0x20;
4519 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4520 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4521 fixP->fx_pcrel_adjust = 2;
4522 fragP->fr_fix += 2;
4523 break;
4524 case TAB (PCINDEX, LONG):
4525 assert (fragP->fr_fix >= 2);
4526 buffer_address[-2] |= 0x1;
4527 buffer_address[-1] = 0x30;
4528 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4529 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4530 fixP->fx_pcrel_adjust = 2;
4531 fragP->fr_fix += 4;
4532 break;
4533 case TAB (ABSTOPCREL, SHORT):
4534 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4535 1, RELAX_RELOC_PC16);
4536 fragP->fr_fix += 2;
4537 break;
4538 case TAB (ABSTOPCREL, LONG):
4539 /* The thing to do here is force it to ABSOLUTE LONG, since
4540 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4541 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4542 abort ();
4543 fragP->fr_opcode[1] &= ~0x3F;
4544 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4545 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4546 0, RELAX_RELOC_ABS32);
4547 fragP->fr_fix += 4;
4548 break;
4549 }
4550 }
4551
4552 #ifndef BFD_ASSEMBLER
4553
4554 void
4555 md_convert_frag (headers, sec, fragP)
4556 object_headers *headers ATTRIBUTE_UNUSED;
4557 segT sec ATTRIBUTE_UNUSED;
4558 fragS *fragP;
4559 {
4560 md_convert_frag_1 (fragP);
4561 }
4562
4563 #else
4564
4565 void
4566 md_convert_frag (abfd, sec, fragP)
4567 bfd *abfd ATTRIBUTE_UNUSED;
4568 segT sec ATTRIBUTE_UNUSED;
4569 fragS *fragP;
4570 {
4571 md_convert_frag_1 (fragP);
4572 }
4573 #endif
4574
4575 /* Force truly undefined symbols to their maximum size, and generally set up
4576 the frag list to be relaxed
4577 */
4578 int
4579 md_estimate_size_before_relax (fragP, segment)
4580 register fragS *fragP;
4581 segT segment;
4582 {
4583 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4584 switch (fragP->fr_subtype)
4585 {
4586 case TAB (BRANCHBWL, SZ_UNDEF):
4587 case TAB (BRABSJUNC, SZ_UNDEF):
4588 case TAB (BRABSJCOND, SZ_UNDEF):
4589 {
4590 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4591 && relaxable_symbol (fragP->fr_symbol))
4592 {
4593 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4594 }
4595 else if (flag_short_refs)
4596 {
4597 /* Symbol is undefined and we want short ref. */
4598 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4599 }
4600 else
4601 {
4602 /* Symbol is still undefined. Make it LONG. */
4603 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4604 }
4605 break;
4606 }
4607
4608 case TAB (BRANCHBW, SZ_UNDEF):
4609 {
4610 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4611 && relaxable_symbol (fragP->fr_symbol))
4612 {
4613 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4614 }
4615 else
4616 {
4617 /* Symbol is undefined and we don't have long branches. */
4618 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4619 }
4620 break;
4621 }
4622
4623 case TAB (FBRANCH, SZ_UNDEF):
4624 case TAB (DBCCLBR, SZ_UNDEF):
4625 case TAB (DBCCABSJ, SZ_UNDEF):
4626 case TAB (PCREL1632, SZ_UNDEF):
4627 {
4628 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4629 && relaxable_symbol (fragP->fr_symbol))
4630 || flag_short_refs)
4631 {
4632 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4633 }
4634 else
4635 {
4636 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4637 }
4638 break;
4639 }
4640
4641 case TAB (PCINDEX, SZ_UNDEF):
4642 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4643 && relaxable_symbol (fragP->fr_symbol)))
4644 {
4645 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4646 }
4647 else
4648 {
4649 fragP->fr_subtype = TAB (PCINDEX, LONG);
4650 }
4651 break;
4652
4653 case TAB (ABSTOPCREL, SZ_UNDEF):
4654 {
4655 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4656 && relaxable_symbol (fragP->fr_symbol)))
4657 {
4658 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4659 }
4660 else
4661 {
4662 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4663 }
4664 break;
4665 }
4666
4667 default:
4668 break;
4669 }
4670
4671 /* Now that SZ_UNDEF are taken care of, check others. */
4672 switch (fragP->fr_subtype)
4673 {
4674 case TAB (BRANCHBWL, BYTE):
4675 case TAB (BRABSJUNC, BYTE):
4676 case TAB (BRABSJCOND, BYTE):
4677 case TAB (BRANCHBW, BYTE):
4678 /* We can't do a short jump to the next instruction, so in that
4679 case we force word mode. If the symbol is at the start of a
4680 frag, and it is the next frag with any data in it (usually
4681 this is just the next frag, but assembler listings may
4682 introduce empty frags), we must use word mode. */
4683 if (fragP->fr_symbol)
4684 {
4685 fragS *sym_frag;
4686
4687 sym_frag = symbol_get_frag (fragP->fr_symbol);
4688 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4689 {
4690 fragS *l;
4691
4692 for (l = fragP->fr_next; l != sym_frag; l = l->fr_next)
4693 if (l->fr_fix != 0)
4694 break;
4695 if (l == sym_frag)
4696 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4697 }
4698 }
4699 break;
4700 default:
4701 break;
4702 }
4703 return md_relax_table[fragP->fr_subtype].rlx_length;
4704 }
4705
4706 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4707 /* the bit-field entries in the relocation_info struct plays hell
4708 with the byte-order problems of cross-assembly. So as a hack,
4709 I added this mach. dependent ri twiddler. Ugly, but it gets
4710 you there. -KWK */
4711 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4712 are symbolnum, most sig. byte first. Last byte is broken up with
4713 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4714 nibble as nuthin. (on Sun 3 at least) */
4715 /* Translate the internal relocation information into target-specific
4716 format. */
4717 #ifdef comment
4718 void
4719 md_ri_to_chars (the_bytes, ri)
4720 char *the_bytes;
4721 struct reloc_info_generic *ri;
4722 {
4723 /* this is easy */
4724 md_number_to_chars (the_bytes, ri->r_address, 4);
4725 /* now the fun stuff */
4726 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4727 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4728 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4729 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4730 ((ri->r_extern << 4) & 0x10));
4731 }
4732
4733 #endif /* comment */
4734
4735 #ifndef BFD_ASSEMBLER
4736 void
4737 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4738 char *where;
4739 fixS *fixP;
4740 relax_addressT segment_address_in_file;
4741 {
4742 /*
4743 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4744 * Out: GNU LD relocation length code: 0, 1, or 2.
4745 */
4746
4747 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4748 long r_symbolnum;
4749
4750 know (fixP->fx_addsy != NULL);
4751
4752 md_number_to_chars (where,
4753 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4754 4);
4755
4756 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4757 ? S_GET_TYPE (fixP->fx_addsy)
4758 : fixP->fx_addsy->sy_number);
4759
4760 where[4] = (r_symbolnum >> 16) & 0x0ff;
4761 where[5] = (r_symbolnum >> 8) & 0x0ff;
4762 where[6] = r_symbolnum & 0x0ff;
4763 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4764 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4765 }
4766 #endif
4767
4768 #endif /* OBJ_AOUT or OBJ_BOUT */
4769
4770 #ifndef WORKING_DOT_WORD
4771 CONST int md_short_jump_size = 4;
4772 CONST int md_long_jump_size = 6;
4773
4774 void
4775 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4776 char *ptr;
4777 addressT from_addr, to_addr;
4778 fragS *frag ATTRIBUTE_UNUSED;
4779 symbolS *to_symbol ATTRIBUTE_UNUSED;
4780 {
4781 valueT offset;
4782
4783 offset = to_addr - (from_addr + 2);
4784
4785 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4786 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4787 }
4788
4789 void
4790 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4791 char *ptr;
4792 addressT from_addr, to_addr;
4793 fragS *frag;
4794 symbolS *to_symbol;
4795 {
4796 valueT offset;
4797
4798 if (!HAVE_LONG_BRANCH(current_architecture))
4799 {
4800 offset = to_addr - S_GET_VALUE (to_symbol);
4801 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4802 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4803 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4804 0, NO_RELOC);
4805 }
4806 else
4807 {
4808 offset = to_addr - (from_addr + 2);
4809 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4810 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4811 }
4812 }
4813
4814 #endif
4815
4816 /* Different values of OK tell what its OK to return. Things that
4817 aren't OK are an error (what a shock, no?)
4818
4819 0: Everything is OK
4820 10: Absolute 1:8 only
4821 20: Absolute 0:7 only
4822 30: absolute 0:15 only
4823 40: Absolute 0:31 only
4824 50: absolute 0:127 only
4825 55: absolute -64:63 only
4826 60: absolute -128:127 only
4827 70: absolute 0:4095 only
4828 80: No bignums
4829
4830 */
4831
4832 static int
4833 get_num (exp, ok)
4834 struct m68k_exp *exp;
4835 int ok;
4836 {
4837 if (exp->exp.X_op == O_absent)
4838 {
4839 /* Do the same thing the VAX asm does */
4840 op (exp) = O_constant;
4841 adds (exp) = 0;
4842 subs (exp) = 0;
4843 offs (exp) = 0;
4844 if (ok == 10)
4845 {
4846 as_warn (_("expression out of range: defaulting to 1"));
4847 offs (exp) = 1;
4848 }
4849 }
4850 else if (exp->exp.X_op == O_constant)
4851 {
4852 switch (ok)
4853 {
4854 case 10:
4855 if (offs (exp) < 1 || offs (exp) > 8)
4856 {
4857 as_warn (_("expression out of range: defaulting to 1"));
4858 offs (exp) = 1;
4859 }
4860 break;
4861 case 20:
4862 if (offs (exp) < 0 || offs (exp) > 7)
4863 goto outrange;
4864 break;
4865 case 30:
4866 if (offs (exp) < 0 || offs (exp) > 15)
4867 goto outrange;
4868 break;
4869 case 40:
4870 if (offs (exp) < 0 || offs (exp) > 32)
4871 goto outrange;
4872 break;
4873 case 50:
4874 if (offs (exp) < 0 || offs (exp) > 127)
4875 goto outrange;
4876 break;
4877 case 55:
4878 if (offs (exp) < -64 || offs (exp) > 63)
4879 goto outrange;
4880 break;
4881 case 60:
4882 if (offs (exp) < -128 || offs (exp) > 127)
4883 goto outrange;
4884 break;
4885 case 70:
4886 if (offs (exp) < 0 || offs (exp) > 4095)
4887 {
4888 outrange:
4889 as_warn (_("expression out of range: defaulting to 0"));
4890 offs (exp) = 0;
4891 }
4892 break;
4893 default:
4894 break;
4895 }
4896 }
4897 else if (exp->exp.X_op == O_big)
4898 {
4899 if (offs (exp) <= 0 /* flonum */
4900 && (ok == 80 /* no bignums */
4901 || (ok > 10 /* small-int ranges including 0 ok */
4902 /* If we have a flonum zero, a zero integer should
4903 do as well (e.g., in moveq). */
4904 && generic_floating_point_number.exponent == 0
4905 && generic_floating_point_number.low[0] == 0)))
4906 {
4907 /* HACK! Turn it into a long */
4908 LITTLENUM_TYPE words[6];
4909
4910 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4911 op (exp) = O_constant;
4912 adds (exp) = 0;
4913 subs (exp) = 0;
4914 offs (exp) = words[1] | (words[0] << 16);
4915 }
4916 else if (ok != 0)
4917 {
4918 op (exp) = O_constant;
4919 adds (exp) = 0;
4920 subs (exp) = 0;
4921 offs (exp) = (ok == 10) ? 1 : 0;
4922 as_warn (_("Can't deal with expression; defaulting to %ld"),
4923 offs (exp));
4924 }
4925 }
4926 else
4927 {
4928 if (ok >= 10 && ok <= 70)
4929 {
4930 op (exp) = O_constant;
4931 adds (exp) = 0;
4932 subs (exp) = 0;
4933 offs (exp) = (ok == 10) ? 1 : 0;
4934 as_warn (_("Can't deal with expression; defaulting to %ld"),
4935 offs (exp));
4936 }
4937 }
4938
4939 if (exp->size != SIZE_UNSPEC)
4940 {
4941 switch (exp->size)
4942 {
4943 case SIZE_UNSPEC:
4944 case SIZE_LONG:
4945 break;
4946 case SIZE_BYTE:
4947 if (!isbyte (offs (exp)))
4948 as_warn (_("expression doesn't fit in BYTE"));
4949 break;
4950 case SIZE_WORD:
4951 if (!isword (offs (exp)))
4952 as_warn (_("expression doesn't fit in WORD"));
4953 break;
4954 }
4955 }
4956
4957 return offs (exp);
4958 }
4959
4960 /* These are the back-ends for the various machine dependent pseudo-ops. */
4961
4962 static void
4963 s_data1 (ignore)
4964 int ignore ATTRIBUTE_UNUSED;
4965 {
4966 subseg_set (data_section, 1);
4967 demand_empty_rest_of_line ();
4968 }
4969
4970 static void
4971 s_data2 (ignore)
4972 int ignore ATTRIBUTE_UNUSED;
4973 {
4974 subseg_set (data_section, 2);
4975 demand_empty_rest_of_line ();
4976 }
4977
4978 static void
4979 s_bss (ignore)
4980 int ignore ATTRIBUTE_UNUSED;
4981 {
4982 /* We don't support putting frags in the BSS segment, we fake it
4983 by marking in_bss, then looking at s_skip for clues. */
4984
4985 subseg_set (bss_section, 0);
4986 demand_empty_rest_of_line ();
4987 }
4988
4989 static void
4990 s_even (ignore)
4991 int ignore ATTRIBUTE_UNUSED;
4992 {
4993 register int temp;
4994 register long temp_fill;
4995
4996 temp = 1; /* JF should be 2? */
4997 temp_fill = get_absolute_expression ();
4998 if (!need_pass_2) /* Never make frag if expect extra pass. */
4999 frag_align (temp, (int) temp_fill, 0);
5000 demand_empty_rest_of_line ();
5001 record_alignment (now_seg, temp);
5002 }
5003
5004 static void
5005 s_proc (ignore)
5006 int ignore ATTRIBUTE_UNUSED;
5007 {
5008 demand_empty_rest_of_line ();
5009 }
5010 \f
5011 /* Pseudo-ops handled for MRI compatibility. */
5012
5013 /* This function returns non-zero if the argument is a conditional
5014 pseudo-op. This is called when checking whether a pending
5015 alignment is needed. */
5016
5017 int
5018 m68k_conditional_pseudoop (pop)
5019 pseudo_typeS *pop;
5020 {
5021 return (pop->poc_handler == s_mri_if
5022 || pop->poc_handler == s_mri_else);
5023 }
5024
5025 /* Handle an MRI style chip specification. */
5026
5027 static void
5028 mri_chip ()
5029 {
5030 char *s;
5031 char c;
5032 int i;
5033
5034 s = input_line_pointer;
5035 /* We can't use get_symbol_end since the processor names are not proper
5036 symbols. */
5037 while (is_part_of_name (c = *input_line_pointer++))
5038 ;
5039 *--input_line_pointer = 0;
5040 for (i = 0; i < n_archs; i++)
5041 if (strcasecmp (s, archs[i].name) == 0)
5042 break;
5043 if (i >= n_archs)
5044 {
5045 as_bad (_("%s: unrecognized processor name"), s);
5046 *input_line_pointer = c;
5047 ignore_rest_of_line ();
5048 return;
5049 }
5050 *input_line_pointer = c;
5051
5052 if (*input_line_pointer == '/')
5053 current_architecture = 0;
5054 else
5055 current_architecture &= m68881 | m68851;
5056 current_architecture |= archs[i].arch;
5057
5058 while (*input_line_pointer == '/')
5059 {
5060 ++input_line_pointer;
5061 s = input_line_pointer;
5062 /* We can't use get_symbol_end since the processor names are not
5063 proper symbols. */
5064 while (is_part_of_name (c = *input_line_pointer++))
5065 ;
5066 *--input_line_pointer = 0;
5067 if (strcmp (s, "68881") == 0)
5068 current_architecture |= m68881;
5069 else if (strcmp (s, "68851") == 0)
5070 current_architecture |= m68851;
5071 *input_line_pointer = c;
5072 }
5073
5074 /* Update info about available control registers. */
5075 select_control_regs ();
5076 }
5077
5078 /* The MRI CHIP pseudo-op. */
5079
5080 static void
5081 s_chip (ignore)
5082 int ignore ATTRIBUTE_UNUSED;
5083 {
5084 char *stop = NULL;
5085 char stopc;
5086
5087 if (flag_mri)
5088 stop = mri_comment_field (&stopc);
5089 mri_chip ();
5090 if (flag_mri)
5091 mri_comment_end (stop, stopc);
5092 demand_empty_rest_of_line ();
5093 }
5094
5095 /* The MRI FOPT pseudo-op. */
5096
5097 static void
5098 s_fopt (ignore)
5099 int ignore ATTRIBUTE_UNUSED;
5100 {
5101 SKIP_WHITESPACE ();
5102
5103 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5104 {
5105 int temp;
5106
5107 input_line_pointer += 3;
5108 temp = get_absolute_expression ();
5109 if (temp < 0 || temp > 7)
5110 as_bad (_("bad coprocessor id"));
5111 else
5112 m68k_float_copnum = COP0 + temp;
5113 }
5114 else
5115 {
5116 as_bad (_("unrecognized fopt option"));
5117 ignore_rest_of_line ();
5118 return;
5119 }
5120
5121 demand_empty_rest_of_line ();
5122 }
5123
5124 /* The structure used to handle the MRI OPT pseudo-op. */
5125
5126 struct opt_action
5127 {
5128 /* The name of the option. */
5129 const char *name;
5130
5131 /* If this is not NULL, just call this function. The first argument
5132 is the ARG field of this structure, the second argument is
5133 whether the option was negated. */
5134 void (*pfn) PARAMS ((int arg, int on));
5135
5136 /* If this is not NULL, and the PFN field is NULL, set the variable
5137 this points to. Set it to the ARG field if the option was not
5138 negated, and the NOTARG field otherwise. */
5139 int *pvar;
5140
5141 /* The value to pass to PFN or to assign to *PVAR. */
5142 int arg;
5143
5144 /* The value to assign to *PVAR if the option is negated. If PFN is
5145 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5146 the option may not be negated. */
5147 int notarg;
5148 };
5149
5150 /* The table used to handle the MRI OPT pseudo-op. */
5151
5152 static void skip_to_comma PARAMS ((int, int));
5153 static void opt_nest PARAMS ((int, int));
5154 static void opt_chip PARAMS ((int, int));
5155 static void opt_list PARAMS ((int, int));
5156 static void opt_list_symbols PARAMS ((int, int));
5157
5158 static const struct opt_action opt_table[] =
5159 {
5160 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5161
5162 /* We do relaxing, so there is little use for these options. */
5163 { "b", 0, 0, 0, 0 },
5164 { "brs", 0, 0, 0, 0 },
5165 { "brb", 0, 0, 0, 0 },
5166 { "brl", 0, 0, 0, 0 },
5167 { "brw", 0, 0, 0, 0 },
5168
5169 { "c", 0, 0, 0, 0 },
5170 { "cex", 0, 0, 0, 0 },
5171 { "case", 0, &symbols_case_sensitive, 1, 0 },
5172 { "cl", 0, 0, 0, 0 },
5173 { "cre", 0, 0, 0, 0 },
5174 { "d", 0, &flag_keep_locals, 1, 0 },
5175 { "e", 0, 0, 0, 0 },
5176 { "f", 0, &flag_short_refs, 1, 0 },
5177 { "frs", 0, &flag_short_refs, 1, 0 },
5178 { "frl", 0, &flag_short_refs, 0, 1 },
5179 { "g", 0, 0, 0, 0 },
5180 { "i", 0, 0, 0, 0 },
5181 { "m", 0, 0, 0, 0 },
5182 { "mex", 0, 0, 0, 0 },
5183 { "mc", 0, 0, 0, 0 },
5184 { "md", 0, 0, 0, 0 },
5185 { "nest", opt_nest, 0, 0, 0 },
5186 { "next", skip_to_comma, 0, 0, 0 },
5187 { "o", 0, 0, 0, 0 },
5188 { "old", 0, 0, 0, 0 },
5189 { "op", skip_to_comma, 0, 0, 0 },
5190 { "pco", 0, 0, 0, 0 },
5191 { "p", opt_chip, 0, 0, 0 },
5192 { "pcr", 0, 0, 0, 0 },
5193 { "pcs", 0, 0, 0, 0 },
5194 { "r", 0, 0, 0, 0 },
5195 { "quick", 0, &m68k_quick, 1, 0 },
5196 { "rel32", 0, &m68k_rel32, 1, 0 },
5197 { "s", opt_list, 0, 0, 0 },
5198 { "t", opt_list_symbols, 0, 0, 0 },
5199 { "w", 0, &flag_no_warnings, 0, 1 },
5200 { "x", 0, 0, 0, 0 }
5201 };
5202
5203 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5204
5205 /* The MRI OPT pseudo-op. */
5206
5207 static void
5208 s_opt (ignore)
5209 int ignore ATTRIBUTE_UNUSED;
5210 {
5211 do
5212 {
5213 int t;
5214 char *s;
5215 char c;
5216 int i;
5217 const struct opt_action *o;
5218
5219 SKIP_WHITESPACE ();
5220
5221 t = 1;
5222 if (*input_line_pointer == '-')
5223 {
5224 ++input_line_pointer;
5225 t = 0;
5226 }
5227 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5228 {
5229 input_line_pointer += 2;
5230 t = 0;
5231 }
5232
5233 s = input_line_pointer;
5234 c = get_symbol_end ();
5235
5236 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5237 {
5238 if (strcasecmp (s, o->name) == 0)
5239 {
5240 if (o->pfn)
5241 {
5242 /* Restore input_line_pointer now in case the option
5243 takes arguments. */
5244 *input_line_pointer = c;
5245 (*o->pfn) (o->arg, t);
5246 }
5247 else if (o->pvar != NULL)
5248 {
5249 if (! t && o->arg == o->notarg)
5250 as_bad (_("option `%s' may not be negated"), s);
5251 *input_line_pointer = c;
5252 *o->pvar = t ? o->arg : o->notarg;
5253 }
5254 else
5255 *input_line_pointer = c;
5256 break;
5257 }
5258 }
5259 if (i >= OPTCOUNT)
5260 {
5261 as_bad (_("option `%s' not recognized"), s);
5262 *input_line_pointer = c;
5263 }
5264 }
5265 while (*input_line_pointer++ == ',');
5266
5267 /* Move back to terminating character. */
5268 --input_line_pointer;
5269 demand_empty_rest_of_line ();
5270 }
5271
5272 /* Skip ahead to a comma. This is used for OPT options which we do
5273 not suppor tand which take arguments. */
5274
5275 static void
5276 skip_to_comma (arg, on)
5277 int arg ATTRIBUTE_UNUSED;
5278 int on ATTRIBUTE_UNUSED;
5279 {
5280 while (*input_line_pointer != ','
5281 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5282 ++input_line_pointer;
5283 }
5284
5285 /* Handle the OPT NEST=depth option. */
5286
5287 static void
5288 opt_nest (arg, on)
5289 int arg ATTRIBUTE_UNUSED;
5290 int on ATTRIBUTE_UNUSED;
5291 {
5292 if (*input_line_pointer != '=')
5293 {
5294 as_bad (_("bad format of OPT NEST=depth"));
5295 return;
5296 }
5297
5298 ++input_line_pointer;
5299 max_macro_nest = get_absolute_expression ();
5300 }
5301
5302 /* Handle the OPT P=chip option. */
5303
5304 static void
5305 opt_chip (arg, on)
5306 int arg ATTRIBUTE_UNUSED;
5307 int on ATTRIBUTE_UNUSED;
5308 {
5309 if (*input_line_pointer != '=')
5310 {
5311 /* This is just OPT P, which we do not support. */
5312 return;
5313 }
5314
5315 ++input_line_pointer;
5316 mri_chip ();
5317 }
5318
5319 /* Handle the OPT S option. */
5320
5321 static void
5322 opt_list (arg, on)
5323 int arg ATTRIBUTE_UNUSED;
5324 int on;
5325 {
5326 listing_list (on);
5327 }
5328
5329 /* Handle the OPT T option. */
5330
5331 static void
5332 opt_list_symbols (arg, on)
5333 int arg ATTRIBUTE_UNUSED;
5334 int on;
5335 {
5336 if (on)
5337 listing |= LISTING_SYMBOLS;
5338 else
5339 listing &=~ LISTING_SYMBOLS;
5340 }
5341
5342 /* Handle the MRI REG pseudo-op. */
5343
5344 static void
5345 s_reg (ignore)
5346 int ignore ATTRIBUTE_UNUSED;
5347 {
5348 char *s;
5349 int c;
5350 struct m68k_op rop;
5351 int mask;
5352 char *stop = NULL;
5353 char stopc;
5354
5355 if (line_label == NULL)
5356 {
5357 as_bad (_("missing label"));
5358 ignore_rest_of_line ();
5359 return;
5360 }
5361
5362 if (flag_mri)
5363 stop = mri_comment_field (&stopc);
5364
5365 SKIP_WHITESPACE ();
5366
5367 s = input_line_pointer;
5368 while (ISALNUM (*input_line_pointer)
5369 #ifdef REGISTER_PREFIX
5370 || *input_line_pointer == REGISTER_PREFIX
5371 #endif
5372 || *input_line_pointer == '/'
5373 || *input_line_pointer == '-')
5374 ++input_line_pointer;
5375 c = *input_line_pointer;
5376 *input_line_pointer = '\0';
5377
5378 if (m68k_ip_op (s, &rop) != 0)
5379 {
5380 if (rop.error == NULL)
5381 as_bad (_("bad register list"));
5382 else
5383 as_bad (_("bad register list: %s"), rop.error);
5384 *input_line_pointer = c;
5385 ignore_rest_of_line ();
5386 return;
5387 }
5388
5389 *input_line_pointer = c;
5390
5391 if (rop.mode == REGLST)
5392 mask = rop.mask;
5393 else if (rop.mode == DREG)
5394 mask = 1 << (rop.reg - DATA0);
5395 else if (rop.mode == AREG)
5396 mask = 1 << (rop.reg - ADDR0 + 8);
5397 else if (rop.mode == FPREG)
5398 mask = 1 << (rop.reg - FP0 + 16);
5399 else if (rop.mode == CONTROL
5400 && rop.reg == FPI)
5401 mask = 1 << 24;
5402 else if (rop.mode == CONTROL
5403 && rop.reg == FPS)
5404 mask = 1 << 25;
5405 else if (rop.mode == CONTROL
5406 && rop.reg == FPC)
5407 mask = 1 << 26;
5408 else
5409 {
5410 as_bad (_("bad register list"));
5411 ignore_rest_of_line ();
5412 return;
5413 }
5414
5415 S_SET_SEGMENT (line_label, reg_section);
5416 S_SET_VALUE (line_label, ~mask);
5417 symbol_set_frag (line_label, &zero_address_frag);
5418
5419 if (flag_mri)
5420 mri_comment_end (stop, stopc);
5421
5422 demand_empty_rest_of_line ();
5423 }
5424
5425 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5426
5427 struct save_opts
5428 {
5429 struct save_opts *next;
5430 int abspcadd;
5431 int symbols_case_sensitive;
5432 int keep_locals;
5433 int short_refs;
5434 int architecture;
5435 int quick;
5436 int rel32;
5437 int listing;
5438 int no_warnings;
5439 /* FIXME: We don't save OPT S. */
5440 };
5441
5442 /* This variable holds the stack of saved options. */
5443
5444 static struct save_opts *save_stack;
5445
5446 /* The MRI SAVE pseudo-op. */
5447
5448 static void
5449 s_save (ignore)
5450 int ignore ATTRIBUTE_UNUSED;
5451 {
5452 struct save_opts *s;
5453
5454 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5455 s->abspcadd = m68k_abspcadd;
5456 s->symbols_case_sensitive = symbols_case_sensitive;
5457 s->keep_locals = flag_keep_locals;
5458 s->short_refs = flag_short_refs;
5459 s->architecture = current_architecture;
5460 s->quick = m68k_quick;
5461 s->rel32 = m68k_rel32;
5462 s->listing = listing;
5463 s->no_warnings = flag_no_warnings;
5464
5465 s->next = save_stack;
5466 save_stack = s;
5467
5468 demand_empty_rest_of_line ();
5469 }
5470
5471 /* The MRI RESTORE pseudo-op. */
5472
5473 static void
5474 s_restore (ignore)
5475 int ignore ATTRIBUTE_UNUSED;
5476 {
5477 struct save_opts *s;
5478
5479 if (save_stack == NULL)
5480 {
5481 as_bad (_("restore without save"));
5482 ignore_rest_of_line ();
5483 return;
5484 }
5485
5486 s = save_stack;
5487 save_stack = s->next;
5488
5489 m68k_abspcadd = s->abspcadd;
5490 symbols_case_sensitive = s->symbols_case_sensitive;
5491 flag_keep_locals = s->keep_locals;
5492 flag_short_refs = s->short_refs;
5493 current_architecture = s->architecture;
5494 m68k_quick = s->quick;
5495 m68k_rel32 = s->rel32;
5496 listing = s->listing;
5497 flag_no_warnings = s->no_warnings;
5498
5499 free (s);
5500
5501 demand_empty_rest_of_line ();
5502 }
5503
5504 /* Types of MRI structured control directives. */
5505
5506 enum mri_control_type
5507 {
5508 mri_for,
5509 mri_if,
5510 mri_repeat,
5511 mri_while
5512 };
5513
5514 /* This structure is used to stack the MRI structured control
5515 directives. */
5516
5517 struct mri_control_info
5518 {
5519 /* The directive within which this one is enclosed. */
5520 struct mri_control_info *outer;
5521
5522 /* The type of directive. */
5523 enum mri_control_type type;
5524
5525 /* Whether an ELSE has been in an IF. */
5526 int else_seen;
5527
5528 /* The add or sub statement at the end of a FOR. */
5529 char *incr;
5530
5531 /* The label of the top of a FOR or REPEAT loop. */
5532 char *top;
5533
5534 /* The label to jump to for the next iteration, or the else
5535 expression of a conditional. */
5536 char *next;
5537
5538 /* The label to jump to to break out of the loop, or the label past
5539 the end of a conditional. */
5540 char *bottom;
5541 };
5542
5543 /* The stack of MRI structured control directives. */
5544
5545 static struct mri_control_info *mri_control_stack;
5546
5547 /* The current MRI structured control directive index number, used to
5548 generate label names. */
5549
5550 static int mri_control_index;
5551
5552 /* Some function prototypes. */
5553
5554 static void mri_assemble PARAMS ((char *));
5555 static char *mri_control_label PARAMS ((void));
5556 static struct mri_control_info *push_mri_control
5557 PARAMS ((enum mri_control_type));
5558 static void pop_mri_control PARAMS ((void));
5559 static int parse_mri_condition PARAMS ((int *));
5560 static int parse_mri_control_operand
5561 PARAMS ((int *, char **, char **, char **, char **));
5562 static int swap_mri_condition PARAMS ((int));
5563 static int reverse_mri_condition PARAMS ((int));
5564 static void build_mri_control_operand
5565 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5566 const char *, int));
5567 static void parse_mri_control_expression
5568 PARAMS ((char *, int, const char *, const char *, int));
5569
5570 /* Assemble an instruction for an MRI structured control directive. */
5571
5572 static void
5573 mri_assemble (str)
5574 char *str;
5575 {
5576 char *s;
5577
5578 /* md_assemble expects the opcode to be in lower case. */
5579 for (s = str; *s != ' ' && *s != '\0'; s++)
5580 *s = TOLOWER (*s);
5581
5582 md_assemble (str);
5583 }
5584
5585 /* Generate a new MRI label structured control directive label name. */
5586
5587 static char *
5588 mri_control_label ()
5589 {
5590 char *n;
5591
5592 n = (char *) xmalloc (20);
5593 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5594 ++mri_control_index;
5595 return n;
5596 }
5597
5598 /* Create a new MRI structured control directive. */
5599
5600 static struct mri_control_info *
5601 push_mri_control (type)
5602 enum mri_control_type type;
5603 {
5604 struct mri_control_info *n;
5605
5606 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5607
5608 n->type = type;
5609 n->else_seen = 0;
5610 if (type == mri_if || type == mri_while)
5611 n->top = NULL;
5612 else
5613 n->top = mri_control_label ();
5614 n->next = mri_control_label ();
5615 n->bottom = mri_control_label ();
5616
5617 n->outer = mri_control_stack;
5618 mri_control_stack = n;
5619
5620 return n;
5621 }
5622
5623 /* Pop off the stack of MRI structured control directives. */
5624
5625 static void
5626 pop_mri_control ()
5627 {
5628 struct mri_control_info *n;
5629
5630 n = mri_control_stack;
5631 mri_control_stack = n->outer;
5632 if (n->top != NULL)
5633 free (n->top);
5634 free (n->next);
5635 free (n->bottom);
5636 free (n);
5637 }
5638
5639 /* Recognize a condition code in an MRI structured control expression. */
5640
5641 static int
5642 parse_mri_condition (pcc)
5643 int *pcc;
5644 {
5645 char c1, c2;
5646
5647 know (*input_line_pointer == '<');
5648
5649 ++input_line_pointer;
5650 c1 = *input_line_pointer++;
5651 c2 = *input_line_pointer++;
5652
5653 if (*input_line_pointer != '>')
5654 {
5655 as_bad (_("syntax error in structured control directive"));
5656 return 0;
5657 }
5658
5659 ++input_line_pointer;
5660 SKIP_WHITESPACE ();
5661
5662 c1 = TOLOWER (c1);
5663 c2 = TOLOWER (c2);
5664
5665 *pcc = (c1 << 8) | c2;
5666
5667 return 1;
5668 }
5669
5670 /* Parse a single operand in an MRI structured control expression. */
5671
5672 static int
5673 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5674 int *pcc;
5675 char **leftstart;
5676 char **leftstop;
5677 char **rightstart;
5678 char **rightstop;
5679 {
5680 char *s;
5681
5682 SKIP_WHITESPACE ();
5683
5684 *pcc = -1;
5685 *leftstart = NULL;
5686 *leftstop = NULL;
5687 *rightstart = NULL;
5688 *rightstop = NULL;
5689
5690 if (*input_line_pointer == '<')
5691 {
5692 /* It's just a condition code. */
5693 return parse_mri_condition (pcc);
5694 }
5695
5696 /* Look ahead for the condition code. */
5697 for (s = input_line_pointer; *s != '\0'; ++s)
5698 {
5699 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5700 break;
5701 }
5702 if (*s == '\0')
5703 {
5704 as_bad (_("missing condition code in structured control directive"));
5705 return 0;
5706 }
5707
5708 *leftstart = input_line_pointer;
5709 *leftstop = s;
5710 if (*leftstop > *leftstart
5711 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5712 --*leftstop;
5713
5714 input_line_pointer = s;
5715 if (! parse_mri_condition (pcc))
5716 return 0;
5717
5718 /* Look ahead for AND or OR or end of line. */
5719 for (s = input_line_pointer; *s != '\0'; ++s)
5720 {
5721 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5722 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5723 ^^^ ^^ */
5724 if ( ( s == input_line_pointer
5725 || *(s-1) == ' '
5726 || *(s-1) == '\t')
5727 && ( ( strncasecmp (s, "AND", 3) == 0
5728 && (s[3] == '.' || ! is_part_of_name (s[3])))
5729 || ( strncasecmp (s, "OR", 2) == 0
5730 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5731 break;
5732 }
5733
5734 *rightstart = input_line_pointer;
5735 *rightstop = s;
5736 if (*rightstop > *rightstart
5737 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5738 --*rightstop;
5739
5740 input_line_pointer = s;
5741
5742 return 1;
5743 }
5744
5745 #define MCC(b1, b2) (((b1) << 8) | (b2))
5746
5747 /* Swap the sense of a condition. This changes the condition so that
5748 it generates the same result when the operands are swapped. */
5749
5750 static int
5751 swap_mri_condition (cc)
5752 int cc;
5753 {
5754 switch (cc)
5755 {
5756 case MCC ('h', 'i'): return MCC ('c', 's');
5757 case MCC ('l', 's'): return MCC ('c', 'c');
5758 /* <HS> is an alias for <CC> */
5759 case MCC ('h', 's'):
5760 case MCC ('c', 'c'): return MCC ('l', 's');
5761 /* <LO> is an alias for <CS> */
5762 case MCC ('l', 'o'):
5763 case MCC ('c', 's'): return MCC ('h', 'i');
5764 case MCC ('p', 'l'): return MCC ('m', 'i');
5765 case MCC ('m', 'i'): return MCC ('p', 'l');
5766 case MCC ('g', 'e'): return MCC ('l', 'e');
5767 case MCC ('l', 't'): return MCC ('g', 't');
5768 case MCC ('g', 't'): return MCC ('l', 't');
5769 case MCC ('l', 'e'): return MCC ('g', 'e');
5770 /* issue a warning for conditions we can not swap */
5771 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5772 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5773 case MCC ('v', 'c'):
5774 case MCC ('v', 's'):
5775 default :
5776 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5777 (char) (cc >> 8), (char) (cc));
5778 break;
5779 }
5780 return cc;
5781 }
5782
5783 /* Reverse the sense of a condition. */
5784
5785 static int
5786 reverse_mri_condition (cc)
5787 int cc;
5788 {
5789 switch (cc)
5790 {
5791 case MCC ('h', 'i'): return MCC ('l', 's');
5792 case MCC ('l', 's'): return MCC ('h', 'i');
5793 /* <HS> is an alias for <CC> */
5794 case MCC ('h', 's'): return MCC ('l', 'o');
5795 case MCC ('c', 'c'): return MCC ('c', 's');
5796 /* <LO> is an alias for <CS> */
5797 case MCC ('l', 'o'): return MCC ('h', 's');
5798 case MCC ('c', 's'): return MCC ('c', 'c');
5799 case MCC ('n', 'e'): return MCC ('e', 'q');
5800 case MCC ('e', 'q'): return MCC ('n', 'e');
5801 case MCC ('v', 'c'): return MCC ('v', 's');
5802 case MCC ('v', 's'): return MCC ('v', 'c');
5803 case MCC ('p', 'l'): return MCC ('m', 'i');
5804 case MCC ('m', 'i'): return MCC ('p', 'l');
5805 case MCC ('g', 'e'): return MCC ('l', 't');
5806 case MCC ('l', 't'): return MCC ('g', 'e');
5807 case MCC ('g', 't'): return MCC ('l', 'e');
5808 case MCC ('l', 'e'): return MCC ('g', 't');
5809 }
5810 return cc;
5811 }
5812
5813 /* Build an MRI structured control expression. This generates test
5814 and branch instructions. It goes to TRUELAB if the condition is
5815 true, and to FALSELAB if the condition is false. Exactly one of
5816 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5817 is the size qualifier for the expression. EXTENT is the size to
5818 use for the branch. */
5819
5820 static void
5821 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5822 rightstop, truelab, falselab, extent)
5823 int qual;
5824 int cc;
5825 char *leftstart;
5826 char *leftstop;
5827 char *rightstart;
5828 char *rightstop;
5829 const char *truelab;
5830 const char *falselab;
5831 int extent;
5832 {
5833 char *buf;
5834 char *s;
5835
5836 if (leftstart != NULL)
5837 {
5838 struct m68k_op leftop, rightop;
5839 char c;
5840
5841 /* Swap the compare operands, if necessary, to produce a legal
5842 m68k compare instruction. Comparing a register operand with
5843 a non-register operand requires the register to be on the
5844 right (cmp, cmpa). Comparing an immediate value with
5845 anything requires the immediate value to be on the left
5846 (cmpi). */
5847
5848 c = *leftstop;
5849 *leftstop = '\0';
5850 (void) m68k_ip_op (leftstart, &leftop);
5851 *leftstop = c;
5852
5853 c = *rightstop;
5854 *rightstop = '\0';
5855 (void) m68k_ip_op (rightstart, &rightop);
5856 *rightstop = c;
5857
5858 if (rightop.mode == IMMED
5859 || ((leftop.mode == DREG || leftop.mode == AREG)
5860 && (rightop.mode != DREG && rightop.mode != AREG)))
5861 {
5862 char *temp;
5863
5864 /* Correct conditional handling:
5865 if #1 <lt> d0 then ;means if (1 < d0)
5866 ...
5867 endi
5868
5869 should assemble to:
5870
5871 cmp #1,d0 if we do *not* swap the operands
5872 bgt true we need the swapped condition!
5873 ble false
5874 true:
5875 ...
5876 false:
5877 */
5878 temp = leftstart;
5879 leftstart = rightstart;
5880 rightstart = temp;
5881 temp = leftstop;
5882 leftstop = rightstop;
5883 rightstop = temp;
5884 } else {
5885 cc = swap_mri_condition (cc);
5886 }
5887 }
5888
5889 if (truelab == NULL)
5890 {
5891 cc = reverse_mri_condition (cc);
5892 truelab = falselab;
5893 }
5894
5895 if (leftstart != NULL)
5896 {
5897 buf = (char *) xmalloc (20
5898 + (leftstop - leftstart)
5899 + (rightstop - rightstart));
5900 s = buf;
5901 *s++ = 'c';
5902 *s++ = 'm';
5903 *s++ = 'p';
5904 if (qual != '\0')
5905 *s++ = TOLOWER (qual);
5906 *s++ = ' ';
5907 memcpy (s, leftstart, leftstop - leftstart);
5908 s += leftstop - leftstart;
5909 *s++ = ',';
5910 memcpy (s, rightstart, rightstop - rightstart);
5911 s += rightstop - rightstart;
5912 *s = '\0';
5913 mri_assemble (buf);
5914 free (buf);
5915 }
5916
5917 buf = (char *) xmalloc (20 + strlen (truelab));
5918 s = buf;
5919 *s++ = 'b';
5920 *s++ = cc >> 8;
5921 *s++ = cc & 0xff;
5922 if (extent != '\0')
5923 *s++ = TOLOWER (extent);
5924 *s++ = ' ';
5925 strcpy (s, truelab);
5926 mri_assemble (buf);
5927 free (buf);
5928 }
5929
5930 /* Parse an MRI structured control expression. This generates test
5931 and branch instructions. STOP is where the expression ends. It
5932 goes to TRUELAB if the condition is true, and to FALSELAB if the
5933 condition is false. Exactly one of TRUELAB and FALSELAB will be
5934 NULL, meaning to fall through. QUAL is the size qualifier for the
5935 expression. EXTENT is the size to use for the branch. */
5936
5937 static void
5938 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5939 char *stop;
5940 int qual;
5941 const char *truelab;
5942 const char *falselab;
5943 int extent;
5944 {
5945 int c;
5946 int cc;
5947 char *leftstart;
5948 char *leftstop;
5949 char *rightstart;
5950 char *rightstop;
5951
5952 c = *stop;
5953 *stop = '\0';
5954
5955 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5956 &rightstart, &rightstop))
5957 {
5958 *stop = c;
5959 return;
5960 }
5961
5962 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5963 {
5964 const char *flab;
5965
5966 if (falselab != NULL)
5967 flab = falselab;
5968 else
5969 flab = mri_control_label ();
5970
5971 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5972 rightstop, (const char *) NULL, flab, extent);
5973
5974 input_line_pointer += 3;
5975 if (*input_line_pointer != '.'
5976 || input_line_pointer[1] == '\0')
5977 qual = '\0';
5978 else
5979 {
5980 qual = input_line_pointer[1];
5981 input_line_pointer += 2;
5982 }
5983
5984 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5985 &rightstart, &rightstop))
5986 {
5987 *stop = c;
5988 return;
5989 }
5990
5991 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5992 rightstop, truelab, falselab, extent);
5993
5994 if (falselab == NULL)
5995 colon (flab);
5996 }
5997 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5998 {
5999 const char *tlab;
6000
6001 if (truelab != NULL)
6002 tlab = truelab;
6003 else
6004 tlab = mri_control_label ();
6005
6006 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6007 rightstop, tlab, (const char *) NULL, extent);
6008
6009 input_line_pointer += 2;
6010 if (*input_line_pointer != '.'
6011 || input_line_pointer[1] == '\0')
6012 qual = '\0';
6013 else
6014 {
6015 qual = input_line_pointer[1];
6016 input_line_pointer += 2;
6017 }
6018
6019 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6020 &rightstart, &rightstop))
6021 {
6022 *stop = c;
6023 return;
6024 }
6025
6026 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6027 rightstop, truelab, falselab, extent);
6028
6029 if (truelab == NULL)
6030 colon (tlab);
6031 }
6032 else
6033 {
6034 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6035 rightstop, truelab, falselab, extent);
6036 }
6037
6038 *stop = c;
6039 if (input_line_pointer != stop)
6040 as_bad (_("syntax error in structured control directive"));
6041 }
6042
6043 /* Handle the MRI IF pseudo-op. This may be a structured control
6044 directive, or it may be a regular assembler conditional, depending
6045 on its operands. */
6046
6047 static void
6048 s_mri_if (qual)
6049 int qual;
6050 {
6051 char *s;
6052 int c;
6053 struct mri_control_info *n;
6054
6055 /* A structured control directive must end with THEN with an
6056 optional qualifier. */
6057 s = input_line_pointer;
6058 /* We only accept '*' as introduction of comments if preceded by white space
6059 or at first column of a line (I think this can't actually happen here?)
6060 This is important when assembling:
6061 if d0 <ne> 12(a0,d0*2) then
6062 if d0 <ne> #CONST*20 then */
6063 while ( ! ( is_end_of_line[(unsigned char) *s]
6064 || ( flag_mri
6065 && *s == '*'
6066 && ( s == input_line_pointer
6067 || *(s-1) == ' '
6068 || *(s-1) == '\t'))))
6069 ++s;
6070 --s;
6071 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6072 --s;
6073
6074 if (s - input_line_pointer > 1
6075 && s[-1] == '.')
6076 s -= 2;
6077
6078 if (s - input_line_pointer < 3
6079 || strncasecmp (s - 3, "THEN", 4) != 0)
6080 {
6081 if (qual != '\0')
6082 {
6083 as_bad (_("missing then"));
6084 ignore_rest_of_line ();
6085 return;
6086 }
6087
6088 /* It's a conditional. */
6089 s_if (O_ne);
6090 return;
6091 }
6092
6093 /* Since this might be a conditional if, this pseudo-op will be
6094 called even if we are supported to be ignoring input. Double
6095 check now. Clobber *input_line_pointer so that ignore_input
6096 thinks that this is not a special pseudo-op. */
6097 c = *input_line_pointer;
6098 *input_line_pointer = 0;
6099 if (ignore_input ())
6100 {
6101 *input_line_pointer = c;
6102 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6103 ++input_line_pointer;
6104 demand_empty_rest_of_line ();
6105 return;
6106 }
6107 *input_line_pointer = c;
6108
6109 n = push_mri_control (mri_if);
6110
6111 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6112 n->next, s[1] == '.' ? s[2] : '\0');
6113
6114 if (s[1] == '.')
6115 input_line_pointer = s + 3;
6116 else
6117 input_line_pointer = s + 1;
6118
6119 if (flag_mri)
6120 {
6121 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6122 ++input_line_pointer;
6123 }
6124
6125 demand_empty_rest_of_line ();
6126 }
6127
6128 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6129 structured IF, associate the ELSE with the IF. Otherwise, assume
6130 it is a conditional else. */
6131
6132 static void
6133 s_mri_else (qual)
6134 int qual;
6135 {
6136 int c;
6137 char *buf;
6138 char q[2];
6139
6140 if (qual == '\0'
6141 && (mri_control_stack == NULL
6142 || mri_control_stack->type != mri_if
6143 || mri_control_stack->else_seen))
6144 {
6145 s_else (0);
6146 return;
6147 }
6148
6149 c = *input_line_pointer;
6150 *input_line_pointer = 0;
6151 if (ignore_input ())
6152 {
6153 *input_line_pointer = c;
6154 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6155 ++input_line_pointer;
6156 demand_empty_rest_of_line ();
6157 return;
6158 }
6159 *input_line_pointer = c;
6160
6161 if (mri_control_stack == NULL
6162 || mri_control_stack->type != mri_if
6163 || mri_control_stack->else_seen)
6164 {
6165 as_bad (_("else without matching if"));
6166 ignore_rest_of_line ();
6167 return;
6168 }
6169
6170 mri_control_stack->else_seen = 1;
6171
6172 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6173 q[0] = TOLOWER (qual);
6174 q[1] = '\0';
6175 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6176 mri_assemble (buf);
6177 free (buf);
6178
6179 colon (mri_control_stack->next);
6180
6181 if (flag_mri)
6182 {
6183 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6184 ++input_line_pointer;
6185 }
6186
6187 demand_empty_rest_of_line ();
6188 }
6189
6190 /* Handle the MRI ENDI pseudo-op. */
6191
6192 static void
6193 s_mri_endi (ignore)
6194 int ignore ATTRIBUTE_UNUSED;
6195 {
6196 if (mri_control_stack == NULL
6197 || mri_control_stack->type != mri_if)
6198 {
6199 as_bad (_("endi without matching if"));
6200 ignore_rest_of_line ();
6201 return;
6202 }
6203
6204 /* ignore_input will not return true for ENDI, so we don't need to
6205 worry about checking it again here. */
6206
6207 if (! mri_control_stack->else_seen)
6208 colon (mri_control_stack->next);
6209 colon (mri_control_stack->bottom);
6210
6211 pop_mri_control ();
6212
6213 if (flag_mri)
6214 {
6215 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6216 ++input_line_pointer;
6217 }
6218
6219 demand_empty_rest_of_line ();
6220 }
6221
6222 /* Handle the MRI BREAK pseudo-op. */
6223
6224 static void
6225 s_mri_break (extent)
6226 int extent;
6227 {
6228 struct mri_control_info *n;
6229 char *buf;
6230 char ex[2];
6231
6232 n = mri_control_stack;
6233 while (n != NULL
6234 && n->type != mri_for
6235 && n->type != mri_repeat
6236 && n->type != mri_while)
6237 n = n->outer;
6238 if (n == NULL)
6239 {
6240 as_bad (_("break outside of structured loop"));
6241 ignore_rest_of_line ();
6242 return;
6243 }
6244
6245 buf = (char *) xmalloc (20 + strlen (n->bottom));
6246 ex[0] = TOLOWER (extent);
6247 ex[1] = '\0';
6248 sprintf (buf, "bra%s %s", ex, n->bottom);
6249 mri_assemble (buf);
6250 free (buf);
6251
6252 if (flag_mri)
6253 {
6254 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6255 ++input_line_pointer;
6256 }
6257
6258 demand_empty_rest_of_line ();
6259 }
6260
6261 /* Handle the MRI NEXT pseudo-op. */
6262
6263 static void
6264 s_mri_next (extent)
6265 int extent;
6266 {
6267 struct mri_control_info *n;
6268 char *buf;
6269 char ex[2];
6270
6271 n = mri_control_stack;
6272 while (n != NULL
6273 && n->type != mri_for
6274 && n->type != mri_repeat
6275 && n->type != mri_while)
6276 n = n->outer;
6277 if (n == NULL)
6278 {
6279 as_bad (_("next outside of structured loop"));
6280 ignore_rest_of_line ();
6281 return;
6282 }
6283
6284 buf = (char *) xmalloc (20 + strlen (n->next));
6285 ex[0] = TOLOWER (extent);
6286 ex[1] = '\0';
6287 sprintf (buf, "bra%s %s", ex, n->next);
6288 mri_assemble (buf);
6289 free (buf);
6290
6291 if (flag_mri)
6292 {
6293 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6294 ++input_line_pointer;
6295 }
6296
6297 demand_empty_rest_of_line ();
6298 }
6299
6300 /* Handle the MRI FOR pseudo-op. */
6301
6302 static void
6303 s_mri_for (qual)
6304 int qual;
6305 {
6306 const char *varstart, *varstop;
6307 const char *initstart, *initstop;
6308 const char *endstart, *endstop;
6309 const char *bystart, *bystop;
6310 int up;
6311 int by;
6312 int extent;
6313 struct mri_control_info *n;
6314 char *buf;
6315 char *s;
6316 char ex[2];
6317
6318 /* The syntax is
6319 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6320 */
6321
6322 SKIP_WHITESPACE ();
6323 varstart = input_line_pointer;
6324
6325 /* Look for the '='. */
6326 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6327 && *input_line_pointer != '=')
6328 ++input_line_pointer;
6329 if (*input_line_pointer != '=')
6330 {
6331 as_bad (_("missing ="));
6332 ignore_rest_of_line ();
6333 return;
6334 }
6335
6336 varstop = input_line_pointer;
6337 if (varstop > varstart
6338 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6339 --varstop;
6340
6341 ++input_line_pointer;
6342
6343 initstart = input_line_pointer;
6344
6345 /* Look for TO or DOWNTO. */
6346 up = 1;
6347 initstop = NULL;
6348 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6349 {
6350 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6351 && ! is_part_of_name (input_line_pointer[2]))
6352 {
6353 initstop = input_line_pointer;
6354 input_line_pointer += 2;
6355 break;
6356 }
6357 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6358 && ! is_part_of_name (input_line_pointer[6]))
6359 {
6360 initstop = input_line_pointer;
6361 up = 0;
6362 input_line_pointer += 6;
6363 break;
6364 }
6365 ++input_line_pointer;
6366 }
6367 if (initstop == NULL)
6368 {
6369 as_bad (_("missing to or downto"));
6370 ignore_rest_of_line ();
6371 return;
6372 }
6373 if (initstop > initstart
6374 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6375 --initstop;
6376
6377 SKIP_WHITESPACE ();
6378 endstart = input_line_pointer;
6379
6380 /* Look for BY or DO. */
6381 by = 0;
6382 endstop = NULL;
6383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6384 {
6385 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6386 && ! is_part_of_name (input_line_pointer[2]))
6387 {
6388 endstop = input_line_pointer;
6389 by = 1;
6390 input_line_pointer += 2;
6391 break;
6392 }
6393 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6394 && (input_line_pointer[2] == '.'
6395 || ! is_part_of_name (input_line_pointer[2])))
6396 {
6397 endstop = input_line_pointer;
6398 input_line_pointer += 2;
6399 break;
6400 }
6401 ++input_line_pointer;
6402 }
6403 if (endstop == NULL)
6404 {
6405 as_bad (_("missing do"));
6406 ignore_rest_of_line ();
6407 return;
6408 }
6409 if (endstop > endstart
6410 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6411 --endstop;
6412
6413 if (! by)
6414 {
6415 bystart = "#1";
6416 bystop = bystart + 2;
6417 }
6418 else
6419 {
6420 SKIP_WHITESPACE ();
6421 bystart = input_line_pointer;
6422
6423 /* Look for DO. */
6424 bystop = NULL;
6425 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6426 {
6427 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6428 && (input_line_pointer[2] == '.'
6429 || ! is_part_of_name (input_line_pointer[2])))
6430 {
6431 bystop = input_line_pointer;
6432 input_line_pointer += 2;
6433 break;
6434 }
6435 ++input_line_pointer;
6436 }
6437 if (bystop == NULL)
6438 {
6439 as_bad (_("missing do"));
6440 ignore_rest_of_line ();
6441 return;
6442 }
6443 if (bystop > bystart
6444 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6445 --bystop;
6446 }
6447
6448 if (*input_line_pointer != '.')
6449 extent = '\0';
6450 else
6451 {
6452 extent = input_line_pointer[1];
6453 input_line_pointer += 2;
6454 }
6455
6456 /* We have fully parsed the FOR operands. Now build the loop. */
6457
6458 n = push_mri_control (mri_for);
6459
6460 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6461
6462 /* move init,var */
6463 s = buf;
6464 *s++ = 'm';
6465 *s++ = 'o';
6466 *s++ = 'v';
6467 *s++ = 'e';
6468 if (qual != '\0')
6469 *s++ = TOLOWER (qual);
6470 *s++ = ' ';
6471 memcpy (s, initstart, initstop - initstart);
6472 s += initstop - initstart;
6473 *s++ = ',';
6474 memcpy (s, varstart, varstop - varstart);
6475 s += varstop - varstart;
6476 *s = '\0';
6477 mri_assemble (buf);
6478
6479 colon (n->top);
6480
6481 /* cmp end,var */
6482 s = buf;
6483 *s++ = 'c';
6484 *s++ = 'm';
6485 *s++ = 'p';
6486 if (qual != '\0')
6487 *s++ = TOLOWER (qual);
6488 *s++ = ' ';
6489 memcpy (s, endstart, endstop - endstart);
6490 s += endstop - endstart;
6491 *s++ = ',';
6492 memcpy (s, varstart, varstop - varstart);
6493 s += varstop - varstart;
6494 *s = '\0';
6495 mri_assemble (buf);
6496
6497 /* bcc bottom */
6498 ex[0] = TOLOWER (extent);
6499 ex[1] = '\0';
6500 if (up)
6501 sprintf (buf, "blt%s %s", ex, n->bottom);
6502 else
6503 sprintf (buf, "bgt%s %s", ex, n->bottom);
6504 mri_assemble (buf);
6505
6506 /* Put together the add or sub instruction used by ENDF. */
6507 s = buf;
6508 if (up)
6509 strcpy (s, "add");
6510 else
6511 strcpy (s, "sub");
6512 s += 3;
6513 if (qual != '\0')
6514 *s++ = TOLOWER (qual);
6515 *s++ = ' ';
6516 memcpy (s, bystart, bystop - bystart);
6517 s += bystop - bystart;
6518 *s++ = ',';
6519 memcpy (s, varstart, varstop - varstart);
6520 s += varstop - varstart;
6521 *s = '\0';
6522 n->incr = buf;
6523
6524 if (flag_mri)
6525 {
6526 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6527 ++input_line_pointer;
6528 }
6529
6530 demand_empty_rest_of_line ();
6531 }
6532
6533 /* Handle the MRI ENDF pseudo-op. */
6534
6535 static void
6536 s_mri_endf (ignore)
6537 int ignore ATTRIBUTE_UNUSED;
6538 {
6539 if (mri_control_stack == NULL
6540 || mri_control_stack->type != mri_for)
6541 {
6542 as_bad (_("endf without for"));
6543 ignore_rest_of_line ();
6544 return;
6545 }
6546
6547 colon (mri_control_stack->next);
6548
6549 mri_assemble (mri_control_stack->incr);
6550
6551 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6552 mri_assemble (mri_control_stack->incr);
6553
6554 free (mri_control_stack->incr);
6555
6556 colon (mri_control_stack->bottom);
6557
6558 pop_mri_control ();
6559
6560 if (flag_mri)
6561 {
6562 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6563 ++input_line_pointer;
6564 }
6565
6566 demand_empty_rest_of_line ();
6567 }
6568
6569 /* Handle the MRI REPEAT pseudo-op. */
6570
6571 static void
6572 s_mri_repeat (ignore)
6573 int ignore ATTRIBUTE_UNUSED;
6574 {
6575 struct mri_control_info *n;
6576
6577 n = push_mri_control (mri_repeat);
6578 colon (n->top);
6579 if (flag_mri)
6580 {
6581 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6582 ++input_line_pointer;
6583 }
6584 demand_empty_rest_of_line ();
6585 }
6586
6587 /* Handle the MRI UNTIL pseudo-op. */
6588
6589 static void
6590 s_mri_until (qual)
6591 int qual;
6592 {
6593 char *s;
6594
6595 if (mri_control_stack == NULL
6596 || mri_control_stack->type != mri_repeat)
6597 {
6598 as_bad (_("until without repeat"));
6599 ignore_rest_of_line ();
6600 return;
6601 }
6602
6603 colon (mri_control_stack->next);
6604
6605 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6606 ;
6607
6608 parse_mri_control_expression (s, qual, (const char *) NULL,
6609 mri_control_stack->top, '\0');
6610
6611 colon (mri_control_stack->bottom);
6612
6613 input_line_pointer = s;
6614
6615 pop_mri_control ();
6616
6617 if (flag_mri)
6618 {
6619 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6620 ++input_line_pointer;
6621 }
6622
6623 demand_empty_rest_of_line ();
6624 }
6625
6626 /* Handle the MRI WHILE pseudo-op. */
6627
6628 static void
6629 s_mri_while (qual)
6630 int qual;
6631 {
6632 char *s;
6633
6634 struct mri_control_info *n;
6635
6636 s = input_line_pointer;
6637 /* We only accept '*' as introduction of comments if preceded by white space
6638 or at first column of a line (I think this can't actually happen here?)
6639 This is important when assembling:
6640 while d0 <ne> 12(a0,d0*2) do
6641 while d0 <ne> #CONST*20 do */
6642 while ( ! ( is_end_of_line[(unsigned char) *s]
6643 || ( flag_mri
6644 && *s == '*'
6645 && ( s == input_line_pointer
6646 || *(s-1) == ' '
6647 || *(s-1) == '\t'))))
6648 s++;
6649 --s;
6650 while (*s == ' ' || *s == '\t')
6651 --s;
6652 if (s - input_line_pointer > 1
6653 && s[-1] == '.')
6654 s -= 2;
6655 if (s - input_line_pointer < 2
6656 || strncasecmp (s - 1, "DO", 2) != 0)
6657 {
6658 as_bad (_("missing do"));
6659 ignore_rest_of_line ();
6660 return;
6661 }
6662
6663 n = push_mri_control (mri_while);
6664
6665 colon (n->next);
6666
6667 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6668 s[1] == '.' ? s[2] : '\0');
6669
6670 input_line_pointer = s + 1;
6671 if (*input_line_pointer == '.')
6672 input_line_pointer += 2;
6673
6674 if (flag_mri)
6675 {
6676 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6677 ++input_line_pointer;
6678 }
6679
6680 demand_empty_rest_of_line ();
6681 }
6682
6683 /* Handle the MRI ENDW pseudo-op. */
6684
6685 static void
6686 s_mri_endw (ignore)
6687 int ignore ATTRIBUTE_UNUSED;
6688 {
6689 char *buf;
6690
6691 if (mri_control_stack == NULL
6692 || mri_control_stack->type != mri_while)
6693 {
6694 as_bad (_("endw without while"));
6695 ignore_rest_of_line ();
6696 return;
6697 }
6698
6699 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6700 sprintf (buf, "bra %s", mri_control_stack->next);
6701 mri_assemble (buf);
6702 free (buf);
6703
6704 colon (mri_control_stack->bottom);
6705
6706 pop_mri_control ();
6707
6708 if (flag_mri)
6709 {
6710 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6711 ++input_line_pointer;
6712 }
6713
6714 demand_empty_rest_of_line ();
6715 }
6716 \f
6717 /*
6718 * md_parse_option
6719 * Invocation line includes a switch not recognized by the base assembler.
6720 * See if it's a processor-specific option. These are:
6721 *
6722 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6723 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6724 * Select the architecture. Instructions or features not
6725 * supported by the selected architecture cause fatal
6726 * errors. More than one may be specified. The default is
6727 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6728 * for -m68000, and -m68882 is a synonym for -m68881.
6729 * -[A]m[c]no-68851, -[A]m[c]no-68881
6730 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6731 * so don't use or document it, but that's the way the parsing
6732 * works).
6733 *
6734 * -pic Indicates PIC.
6735 * -k Indicates PIC. (Sun 3 only.)
6736 * --pcrel Never turn PC-relative branches into absolute jumps.
6737 *
6738 * --bitwise-or
6739 * Permit `|' to be used in expressions.
6740 *
6741 */
6742
6743 #ifdef OBJ_ELF
6744 CONST char *md_shortopts = "lSA:m:kQ:V";
6745 #else
6746 CONST char *md_shortopts = "lSA:m:k";
6747 #endif
6748
6749 struct option md_longopts[] = {
6750 #define OPTION_PIC (OPTION_MD_BASE)
6751 {"pic", no_argument, NULL, OPTION_PIC},
6752 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6753 {"register-prefix-optional", no_argument, NULL,
6754 OPTION_REGISTER_PREFIX_OPTIONAL},
6755 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6756 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6757 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6758 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6759 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6760 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6761 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6762 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6763 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6764 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6765 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6766 {"pcrel", no_argument, NULL, OPTION_PCREL},
6767 {NULL, no_argument, NULL, 0}
6768 };
6769 size_t md_longopts_size = sizeof (md_longopts);
6770
6771 int
6772 md_parse_option (c, arg)
6773 int c;
6774 char *arg;
6775 {
6776 switch (c)
6777 {
6778 case 'l': /* -l means keep external to 2 bit offset
6779 rather than 16 bit one */
6780 flag_short_refs = 1;
6781 break;
6782
6783 case 'S': /* -S means that jbsr's always turn into
6784 jsr's. */
6785 flag_long_jumps = 1;
6786 break;
6787
6788 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6789 branches into absolute jumps. */
6790 flag_keep_pcrel = 1;
6791 break;
6792
6793 case 'A':
6794 if (*arg == 'm')
6795 arg++;
6796 /* intentional fall-through */
6797 case 'm':
6798
6799 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6800 {
6801 int i;
6802 unsigned long arch;
6803 const char *oarg = arg;
6804
6805 arg += 3;
6806 if (*arg == 'm')
6807 {
6808 arg++;
6809 if (arg[0] == 'c' && arg[1] == '6')
6810 arg++;
6811 }
6812 for (i = 0; i < n_archs; i++)
6813 if (!strcmp (arg, archs[i].name))
6814 break;
6815 if (i == n_archs)
6816 {
6817 unknown:
6818 as_bad (_("unrecognized option `%s'"), oarg);
6819 return 0;
6820 }
6821 arch = archs[i].arch;
6822 if (arch == m68881)
6823 no_68881 = 1;
6824 else if (arch == m68851)
6825 no_68851 = 1;
6826 else
6827 goto unknown;
6828 }
6829 else
6830 {
6831 int i;
6832
6833 if (arg[0] == 'c' && arg[1] == '6')
6834 arg++;
6835
6836 for (i = 0; i < n_archs; i++)
6837 if (!strcmp (arg, archs[i].name))
6838 {
6839 unsigned long arch = archs[i].arch;
6840 if (cpu_of_arch (arch))
6841 /* It's a cpu spec. */
6842 {
6843 current_architecture &= ~m68000up;
6844 current_architecture |= arch;
6845 }
6846 else if (arch == m68881)
6847 {
6848 current_architecture |= m68881;
6849 no_68881 = 0;
6850 }
6851 else if (arch == m68851)
6852 {
6853 current_architecture |= m68851;
6854 no_68851 = 0;
6855 }
6856 else
6857 /* ??? */
6858 abort ();
6859 break;
6860 }
6861 if (i == n_archs)
6862 {
6863 as_bad (_("unrecognized architecture specification `%s'"), arg);
6864 return 0;
6865 }
6866 }
6867 break;
6868
6869 case OPTION_PIC:
6870 case 'k':
6871 flag_want_pic = 1;
6872 break; /* -pic, Position Independent Code */
6873
6874 case OPTION_REGISTER_PREFIX_OPTIONAL:
6875 flag_reg_prefix_optional = 1;
6876 reg_prefix_optional_seen = 1;
6877 break;
6878
6879 /* -V: SVR4 argument to print version ID. */
6880 case 'V':
6881 print_version_id ();
6882 break;
6883
6884 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6885 should be emitted or not. FIXME: Not implemented. */
6886 case 'Q':
6887 break;
6888
6889 case OPTION_BITWISE_OR:
6890 {
6891 char *n, *t;
6892 const char *s;
6893
6894 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6895 t = n;
6896 for (s = m68k_comment_chars; *s != '\0'; s++)
6897 if (*s != '|')
6898 *t++ = *s;
6899 *t = '\0';
6900 m68k_comment_chars = n;
6901 }
6902 break;
6903
6904 case OPTION_BASE_SIZE_DEFAULT_16:
6905 m68k_index_width_default = SIZE_WORD;
6906 break;
6907
6908 case OPTION_BASE_SIZE_DEFAULT_32:
6909 m68k_index_width_default = SIZE_LONG;
6910 break;
6911
6912 case OPTION_DISP_SIZE_DEFAULT_16:
6913 m68k_rel32 = 0;
6914 m68k_rel32_from_cmdline = 1;
6915 break;
6916
6917 case OPTION_DISP_SIZE_DEFAULT_32:
6918 m68k_rel32 = 1;
6919 m68k_rel32_from_cmdline = 1;
6920 break;
6921
6922 default:
6923 return 0;
6924 }
6925
6926 return 1;
6927 }
6928
6929 void
6930 md_show_usage (stream)
6931 FILE *stream;
6932 {
6933 fprintf (stream, _("\
6934 680X0 options:\n\
6935 -l use 1 word for refs to undefined symbols [default 2]\n\
6936 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6937 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6938 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6939 specify variant of 680X0 architecture [default 68020]\n\
6940 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6941 target has/lacks floating-point coprocessor\n\
6942 [default yes for 68020, 68030, and cpu32]\n"));
6943 fprintf (stream, _("\
6944 -m68851 | -mno-68851\n\
6945 target has/lacks memory-management unit coprocessor\n\
6946 [default yes for 68020 and up]\n\
6947 -pic, -k generate position independent code\n\
6948 -S turn jbsr into jsr\n\
6949 --pcrel never turn PC-relative branches into absolute jumps\n\
6950 --register-prefix-optional\n\
6951 recognize register names without prefix character\n\
6952 --bitwise-or do not treat `|' as a comment character\n"));
6953 fprintf (stream, _("\
6954 --base-size-default-16 base reg without size is 16 bits\n\
6955 --base-size-default-32 base reg without size is 32 bits (default)\n\
6956 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6957 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6958 }
6959 \f
6960 #ifdef TEST2
6961
6962 /* TEST2: Test md_assemble() */
6963 /* Warning, this routine probably doesn't work anymore */
6964
6965 main ()
6966 {
6967 struct m68k_it the_ins;
6968 char buf[120];
6969 char *cp;
6970 int n;
6971
6972 m68k_ip_begin ();
6973 for (;;)
6974 {
6975 if (!gets (buf) || !*buf)
6976 break;
6977 if (buf[0] == '|' || buf[1] == '.')
6978 continue;
6979 for (cp = buf; *cp; cp++)
6980 if (*cp == '\t')
6981 *cp = ' ';
6982 if (is_label (buf))
6983 continue;
6984 memset (&the_ins, '\0', sizeof (the_ins));
6985 m68k_ip (&the_ins, buf);
6986 if (the_ins.error)
6987 {
6988 printf (_("Error %s in %s\n"), the_ins.error, buf);
6989 }
6990 else
6991 {
6992 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6993 for (n = 0; n < the_ins.numo; n++)
6994 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6995 printf (" ");
6996 print_the_insn (&the_ins.opcode[0], stdout);
6997 (void) putchar ('\n');
6998 }
6999 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7000 {
7001 if (the_ins.operands[n].error)
7002 {
7003 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7004 continue;
7005 }
7006 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7007 if (the_ins.operands[n].b_const)
7008 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7009 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7010 if (the_ins.operands[n].b_iadd)
7011 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7012 (void) putchar ('\n');
7013 }
7014 }
7015 m68k_ip_end ();
7016 return 0;
7017 }
7018
7019 is_label (str)
7020 char *str;
7021 {
7022 while (*str == ' ')
7023 str++;
7024 while (*str && *str != ' ')
7025 str++;
7026 if (str[-1] == ':' || str[1] == '=')
7027 return 1;
7028 return 0;
7029 }
7030
7031 #endif
7032
7033 /* Possible states for relaxation:
7034
7035 0 0 branch offset byte (bra, etc)
7036 0 1 word
7037 0 2 long
7038
7039 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7040 1 1 word
7041 1 2 long
7042
7043 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7044 2 1 word-long
7045 2 2 long-word
7046 2 3 long-long
7047
7048 */
7049
7050 /* We have no need to default values of symbols. */
7051
7052 symbolS *
7053 md_undefined_symbol (name)
7054 char *name ATTRIBUTE_UNUSED;
7055 {
7056 return 0;
7057 }
7058
7059 /* Round up a section size to the appropriate boundary. */
7060 valueT
7061 md_section_align (segment, size)
7062 segT segment ATTRIBUTE_UNUSED;
7063 valueT size;
7064 {
7065 #ifdef OBJ_AOUT
7066 #ifdef BFD_ASSEMBLER
7067 /* For a.out, force the section size to be aligned. If we don't do
7068 this, BFD will align it for us, but it will not write out the
7069 final bytes of the section. This may be a bug in BFD, but it is
7070 easier to fix it here since that is how the other a.out targets
7071 work. */
7072 int align;
7073
7074 align = bfd_get_section_alignment (stdoutput, segment);
7075 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7076 #endif
7077 #endif
7078
7079 return size;
7080 }
7081
7082 /* Exactly what point is a PC-relative offset relative TO?
7083 On the 68k, it is relative to the address of the first extension
7084 word. The difference between the addresses of the offset and the
7085 first extension word is stored in fx_pcrel_adjust. */
7086 long
7087 md_pcrel_from (fixP)
7088 fixS *fixP;
7089 {
7090 int adjust;
7091
7092 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7093 sign extend the value here. */
7094 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7095 if (adjust == 64)
7096 adjust = -1;
7097 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7098 }
7099
7100 #ifndef BFD_ASSEMBLER
7101 #ifdef OBJ_COFF
7102
7103 void
7104 tc_coff_symbol_emit_hook (ignore)
7105 symbolS *ignore ATTRIBUTE_UNUSED;
7106 {
7107 }
7108
7109 int
7110 tc_coff_sizemachdep (frag)
7111 fragS *frag;
7112 {
7113 switch (frag->fr_subtype & 0x3)
7114 {
7115 case BYTE:
7116 return 1;
7117 case SHORT:
7118 return 2;
7119 case LONG:
7120 return 4;
7121 default:
7122 abort ();
7123 return 0;
7124 }
7125 }
7126
7127 #endif
7128 #endif
7129 #ifdef OBJ_ELF
7130 void m68k_elf_final_processing()
7131 {
7132 /* Set file-specific flags if this is a cpu32 processor */
7133 if (cpu_of_arch (current_architecture) & cpu32)
7134 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7135 }
7136 #endif
GDB Binutils - Deliverables
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