1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
67 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
68 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
71 /* Need to sync the version with RISC-V compiler. */
72 #ifndef DEFAULT_RISCV_ISA_SPEC
73 #define DEFAULT_RISCV_ISA_SPEC "2.2"
76 #ifndef DEFAULT_RISCV_PRIV_SPEC
77 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
80 static const char default_arch
[] = DEFAULT_ARCH
;
81 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
82 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
83 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
85 static unsigned xlen
= 0; /* The width of an x-register. */
86 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
87 static bfd_boolean rve_abi
= FALSE
;
89 FLOAT_ABI_DEFAULT
= -1,
95 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
97 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
98 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
100 static unsigned elf_flags
= 0;
102 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
103 Otherwise, return 1. */
106 riscv_set_default_isa_spec (const char *s
)
108 enum riscv_isa_spec_class
class;
109 if (!riscv_get_isa_spec_class (s
, &class))
111 as_bad ("Unknown default ISA spec `%s' set by "
112 "-misa-spec or --with-isa-spec", s
);
116 default_isa_spec
= class;
120 /* Set the default_priv_spec. Find the privileged elf attributes when
121 the input string is NULL. Return 0 if the spec isn't supported.
122 Otherwise, return 1. */
125 riscv_set_default_priv_spec (const char *s
)
127 enum riscv_priv_spec_class
class;
128 unsigned major
, minor
, revision
;
131 if (riscv_get_priv_spec_class (s
, &class))
133 default_priv_spec
= class;
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s
);
144 /* Set the default_priv_spec by the privileged elf attributes. */
145 attr
= elf_known_obj_attributes_proc (stdoutput
);
146 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
147 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
148 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
149 if (riscv_get_priv_spec_class_from_numbers (major
,
154 /* 0.0.0 is meaningless. */
155 if (class == PRIV_SPEC_CLASS_NONE
)
158 default_priv_spec
= class;
162 /* Still can not find the privileged spec class. */
163 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
164 "privilege attributes"), major
, minor
, revision
);
168 /* This is the set of options which the .option pseudo-op may modify. */
169 struct riscv_set_options
171 int pic
; /* Generate position-independent code. */
172 int rvc
; /* Generate RVC code. */
173 int rve
; /* Generate RVE code. */
174 int relax
; /* Emit relocs the linker is allowed to relax. */
175 int arch_attr
; /* Emit architecture and privileged elf attributes. */
176 int csr_check
; /* Enable the CSR checking. */
179 static struct riscv_set_options riscv_opts
=
185 DEFAULT_RISCV_ATTR
, /* arch_attr */
190 riscv_set_rvc (bfd_boolean rvc_value
)
193 elf_flags
|= EF_RISCV_RVC
;
195 riscv_opts
.rvc
= rvc_value
;
199 riscv_set_rve (bfd_boolean rve_value
)
201 riscv_opts
.rve
= rve_value
;
204 static riscv_subset_list_t riscv_subsets
;
207 riscv_subset_supports (const char *feature
)
209 struct riscv_subset_t
*subset
;
211 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
214 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
218 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
222 case INSN_CLASS_I
: return riscv_subset_supports ("i");
223 case INSN_CLASS_C
: return riscv_subset_supports ("c");
224 case INSN_CLASS_A
: return riscv_subset_supports ("a");
225 case INSN_CLASS_M
: return riscv_subset_supports ("m");
226 case INSN_CLASS_F
: return riscv_subset_supports ("f");
227 case INSN_CLASS_D
: return riscv_subset_supports ("d");
228 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
230 case INSN_CLASS_F_AND_C
:
231 return (riscv_subset_supports ("f")
232 && riscv_subset_supports ("c"));
233 case INSN_CLASS_D_AND_C
:
234 return (riscv_subset_supports ("d")
235 && riscv_subset_supports ("c"));
237 case INSN_CLASS_ZICSR
:
238 return riscv_subset_supports ("zicsr");
239 case INSN_CLASS_ZIFENCEI
:
240 return riscv_subset_supports ("zifencei");
241 case INSN_CLASS_ZIHINTPAUSE
:
242 return riscv_subset_supports ("zihintpause");
245 return riscv_subset_supports ("zba");
247 return riscv_subset_supports ("zbb");
249 return riscv_subset_supports ("zbc");
250 case INSN_CLASS_ZBA_OR_ZBB
:
251 return (riscv_subset_supports ("zba")
252 || riscv_subset_supports ("zbb"));
255 as_fatal ("Unreachable");
260 /* Handle of the extension with version hash table. */
261 static htab_t ext_version_hash
= NULL
;
264 init_ext_version_hash (const struct riscv_ext_version
*table
)
267 htab_t hash
= str_htab_create ();
269 while (table
[i
].name
)
271 const char *name
= table
[i
].name
;
272 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
273 as_fatal (_("duplicate %s"), name
);
277 && strcmp (table
[i
].name
, name
) == 0)
285 riscv_get_default_ext_version (const char *name
,
289 struct riscv_ext_version
*ext
;
291 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
294 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
297 && strcmp (ext
->name
, name
) == 0)
299 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
300 || ext
->isa_spec_class
== default_isa_spec
)
302 *major_version
= ext
->major_version
;
303 *minor_version
= ext
->minor_version
;
310 /* Set which ISA and extensions are available. */
313 riscv_set_arch (const char *s
)
315 riscv_parse_subset_t rps
;
316 rps
.subset_list
= &riscv_subsets
;
317 rps
.error_handler
= as_bad
;
319 rps
.get_default_version
= riscv_get_default_ext_version
;
324 riscv_release_subset_list (&riscv_subsets
);
325 riscv_parse_subset (&rps
, s
);
328 /* Indicate -mabi option is explictly set. */
329 static bfd_boolean explicit_mabi
= FALSE
;
332 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
335 float_abi
= new_float_abi
;
339 /* If the -mabi option isn't set, then set the abi according to the
340 ISA string. Otherwise, check if there is any conflict. */
343 riscv_set_abi_by_arch (void)
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
352 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
356 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
359 else if (abi_xlen
< xlen
)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
365 elf_flags
|= float_abi
<< 1;
368 elf_flags
|= EF_RISCV_RVE
;
371 /* Handle of the OPCODE hash table. */
372 static htab_t op_hash
= NULL
;
374 /* Handle of the type of .insn hash table. */
375 static htab_t insn_type_hash
= NULL
;
377 /* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful. */
379 const char comment_chars
[] = "#";
381 /* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output
385 Note that input_file.c hand checks for '#' at the beginning of the
386 first line of the input file. This is because the compiler outputs
387 #NO_APP at the beginning of its output.
389 Also note that C style comments are always supported. */
390 const char line_comment_chars
[] = "#";
392 /* This array holds machine specific line separator characters. */
393 const char line_separator_chars
[] = ";";
395 /* Chars that can be used to separate mant from exp in floating point nums. */
396 const char EXP_CHARS
[] = "eE";
398 /* Chars that mean this number is a floating point constant.
399 As in 0f12.456 or 0d1.2345e12. */
400 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
402 /* Indicate we are already assemble any instructions or not. */
403 static bfd_boolean start_assemble
= FALSE
;
405 /* Indicate ELF attributes are explicitly set. */
406 static bfd_boolean explicit_attr
= FALSE
;
408 /* Indicate CSR or priv instructions are explicitly used. */
409 static bfd_boolean explicit_priv_attr
= FALSE
;
411 /* Macros for encoding relaxation state for RVC branches and far jumps. */
412 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
415 | ((uncond) ? 1 : 0) \
418 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
419 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
420 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
421 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
423 /* Is the given value a sign-extended 32-bit value? */
424 #define IS_SEXT_32BIT_NUM(x) \
425 (((x) &~ (offsetT) 0x7fffffff) == 0 \
426 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
428 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
429 #define IS_ZEXT_32BIT_NUM(x) \
430 (((x) &~ (offsetT) 0xffffffff) == 0 \
431 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
433 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
434 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
435 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
436 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
438 /* Determine if an instruction matches an opcode. */
439 #define OPCODE_MATCHES(OPCODE, OP) \
440 (((OPCODE) & MASK_##OP) == MATCH_##OP)
442 static char *expr_end
;
444 /* The default target format to use. */
447 riscv_target_format (void)
449 if (target_big_endian
)
450 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
452 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
455 /* Return the length of instruction INSN. */
457 static inline unsigned int
458 insn_length (const struct riscv_cl_insn
*insn
)
460 return riscv_insn_length (insn
->insn_opcode
);
463 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
466 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
469 insn
->insn_opcode
= mo
->match
;
475 /* Install INSN at the location specified by its "frag" and "where" fields. */
478 install_insn (const struct riscv_cl_insn
*insn
)
480 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
481 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
484 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
485 and install the opcode in the new location. */
488 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
492 if (insn
->fixp
!= NULL
)
494 insn
->fixp
->fx_frag
= frag
;
495 insn
->fixp
->fx_where
= where
;
500 /* Add INSN to the end of the output. */
503 add_fixed_insn (struct riscv_cl_insn
*insn
)
505 char *f
= frag_more (insn_length (insn
));
506 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
510 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
511 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
513 frag_grow (max_chars
);
514 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
515 frag_var (rs_machine_dependent
, max_chars
, var
,
516 subtype
, symbol
, offset
, NULL
);
519 /* Compute the length of a branch sequence, and adjust the stored length
520 accordingly. If FRAGP is NULL, the worst-case length is returned. */
523 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
525 int jump
, rvc
, length
= 8;
530 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
531 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
532 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
534 /* Assume jumps are in range; the linker will catch any that aren't. */
535 length
= jump
? 4 : 8;
537 if (fragp
->fr_symbol
!= NULL
538 && S_IS_DEFINED (fragp
->fr_symbol
)
539 && !S_IS_WEAK (fragp
->fr_symbol
)
540 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
542 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
543 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
544 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
546 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
548 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
550 else if (!jump
&& rvc
)
555 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
560 /* Information about an opcode name, mnemonics and its value. */
567 /* List for all supported opcode name. */
568 static const struct opcode_name_t opcode_name_list
[] =
613 /* Hash table for lookup opcode name. */
614 static htab_t opcode_names_hash
= NULL
;
616 /* Initialization for hash table of opcode name. */
619 init_opcode_names_hash (void)
621 const struct opcode_name_t
*opcode
;
623 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
624 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
625 as_fatal (_("duplicate %s"), opcode
->name
);
628 /* Find `s` is a valid opcode name or not, return the opcode name info
631 static const struct opcode_name_t
*
632 opcode_name_lookup (char **s
)
636 struct opcode_name_t
*o
;
638 /* Find end of name. */
640 if (is_name_beginner (*e
))
642 while (is_part_of_name (*e
))
645 /* Terminate name. */
649 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
651 /* Advance to next token if one was recognized. */
670 static htab_t reg_names_hash
= NULL
;
671 static htab_t csr_extra_hash
= NULL
;
673 #define ENCODE_REG_HASH(cls, n) \
674 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
675 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
676 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
679 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
681 void *hash
= ENCODE_REG_HASH (class, n
);
682 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
683 as_fatal (_("duplicate %s"), name
);
687 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
691 for (i
= 0; i
< n
; i
++)
692 hash_reg_name (class, names
[i
], i
);
695 /* Init hash table csr_extra_hash to handle CSR. */
698 riscv_init_csr_hash (const char *name
,
700 enum riscv_csr_class
class,
701 enum riscv_priv_spec_class define_version
,
702 enum riscv_priv_spec_class abort_version
)
704 struct riscv_csr_extra
*entry
, *pre_entry
;
705 bfd_boolean need_enrty
= TRUE
;
708 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
709 while (need_enrty
&& entry
!= NULL
)
711 if (entry
->csr_class
== class
712 && entry
->address
== address
713 && entry
->define_version
== define_version
714 && entry
->abort_version
== abort_version
)
724 entry
= XNEW (struct riscv_csr_extra
);
725 entry
->csr_class
= class;
726 entry
->address
= address
;
727 entry
->define_version
= define_version
;
728 entry
->abort_version
= abort_version
;
731 if (pre_entry
== NULL
)
732 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
734 pre_entry
->next
= entry
;
737 /* Return the CSR address after checking the ISA dependency and
738 the privileged spec version.
740 There are one warning and two errors for CSR,
742 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
743 or the privileged spec, report warning only if -mcsr-check is set.
744 Unknown CSR: the CSR has never been defined, report error.
745 Improper CSR: the CSR number over the range (> 0xfff), report error. */
748 riscv_csr_address (const char *csr_name
,
749 struct riscv_csr_extra
*entry
)
751 struct riscv_csr_extra
*saved_entry
= entry
;
752 enum riscv_csr_class csr_class
= entry
->csr_class
;
753 bfd_boolean need_check_version
= TRUE
;
754 bfd_boolean result
= TRUE
;
759 result
= riscv_subset_supports ("i");
762 result
= (xlen
== 32 && riscv_subset_supports ("i"));
765 result
= riscv_subset_supports ("f");
766 need_check_version
= FALSE
;
768 case CSR_CLASS_DEBUG
:
769 need_check_version
= FALSE
;
772 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
775 if (riscv_opts
.csr_check
&& !result
)
776 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
778 while (entry
!= NULL
)
780 if (!need_check_version
781 || (default_priv_spec
>= entry
->define_version
782 && default_priv_spec
< entry
->abort_version
))
784 /* Find the CSR according to the specific version. */
785 return entry
->address
;
790 /* Can not find the CSR address from the chosen privileged version,
791 so use the newly defined value. */
792 if (riscv_opts
.csr_check
)
794 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
796 if (priv_name
!= NULL
)
797 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
798 csr_name
, priv_name
);
801 return saved_entry
->address
;
804 /* Return -1 if the CSR has never been defined. Otherwise, return
808 reg_csr_lookup_internal (const char *s
)
810 struct riscv_csr_extra
*r
=
811 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
816 return riscv_csr_address (s
, r
);
820 reg_lookup_internal (const char *s
, enum reg_class
class)
824 if (class == RCLASS_CSR
)
825 return reg_csr_lookup_internal (s
);
827 r
= str_hash_find (reg_names_hash
, s
);
828 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
831 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
834 return DECODE_REG_NUM (r
);
838 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
844 /* Find end of name. */
846 if (is_name_beginner (*e
))
848 while (is_part_of_name (*e
))
851 /* Terminate name. */
855 /* Look for the register. Advance to next token if one was recognized. */
856 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
866 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
868 const char *p
= strchr (*s
, ',');
869 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
874 for (i
= 0; i
< size
; i
++)
875 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
885 /* For consistency checking, verify that all bits are specified either
886 by the match/mask part of the instruction definition, or by the
887 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
890 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
892 const char *p
= opc
->args
;
894 insn_t used_bits
= opc
->mask
;
896 insn_t required_bits
;
899 insn_width
= 8 * riscv_insn_length (opc
->match
);
901 insn_width
= 8 * length
;
903 required_bits
= ~0ULL >> (64 - insn_width
);
905 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
907 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
908 opc
->name
, opc
->args
);
912 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
919 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
920 case 'c': break; /* RS1, constrained to equal sp. */
921 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
922 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
923 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
924 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
925 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
926 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
927 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
928 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
929 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
930 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
931 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
932 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
933 case 'w': break; /* RS1S, constrained to equal RD. */
934 case 'x': break; /* RS2S, constrained to equal RD. */
935 case 'z': break; /* RS2S, constrained to be x0. */
936 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
937 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
938 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
939 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
940 case 'U': break; /* RS1, constrained to equal RD. */
941 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
942 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
943 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
944 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
945 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
946 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
947 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
948 case 'F': /* RVC funct for .insn directive. */
951 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
952 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
953 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
954 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
956 as_bad (_("internal: bad RISC-V opcode"
957 " (unknown operand type `CF%c'): %s %s"),
958 c
, opc
->name
, opc
->args
);
963 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
964 c
, opc
->name
, opc
->args
);
971 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
972 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
974 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
975 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
976 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
978 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
979 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
980 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
982 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
983 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
984 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
985 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
986 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
987 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
988 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
989 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
991 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
992 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
993 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
994 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
995 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1001 case 'F': /* Funct for .insn directive. */
1004 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1005 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1006 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1008 as_bad (_("internal: bad RISC-V opcode"
1009 " (unknown operand type `F%c'): %s %s"),
1010 c
, opc
->name
, opc
->args
);
1014 case 'O': /* Opcode for .insn directive. */
1017 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1018 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1020 as_bad (_("internal: bad RISC-V opcode"
1021 " (unknown operand type `F%c'): %s %s"),
1022 c
, opc
->name
, opc
->args
);
1027 as_bad (_("internal: bad RISC-V opcode "
1028 "(unknown operand type `%c'): %s %s"),
1029 c
, opc
->name
, opc
->args
);
1033 if (used_bits
!= required_bits
)
1035 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1036 ~(unsigned long)(used_bits
& required_bits
),
1037 opc
->name
, opc
->args
);
1043 struct percent_op_match
1046 bfd_reloc_code_real_type reloc
;
1049 /* Common hash table initialization function for instruction and .insn
1053 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1054 bfd_boolean insn_directive_p
)
1058 htab_t hash
= str_htab_create ();
1059 while (opcodes
[i
].name
)
1061 const char *name
= opcodes
[i
].name
;
1062 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1063 as_fatal (_("duplicate %s"), name
);
1067 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1069 if (insn_directive_p
)
1070 length
= ((name
[0] == 'c') ? 2 : 4);
1072 length
= 0; /* Let assembler determine the length. */
1073 if (!validate_riscv_insn (&opcodes
[i
], length
))
1074 as_fatal (_("Broken assembler. No assembly attempted."));
1077 gas_assert (!insn_directive_p
);
1080 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1086 /* This function is called once, at assembler startup time. It should set up
1087 all the tables, etc. that the MD part of the assembler will need. */
1092 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1094 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1095 as_warn (_("Could not set architecture and machine"));
1097 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1098 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1100 reg_names_hash
= str_htab_create ();
1101 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1102 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1103 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1104 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1105 /* Add "fp" as an alias for "s0". */
1106 hash_reg_name (RCLASS_GPR
, "fp", 8);
1108 /* Create and insert CSR hash tables. */
1109 csr_extra_hash
= str_htab_create ();
1110 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1111 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1112 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1113 DECLARE_CSR(name, num, class, define_version, abort_version);
1114 #include "opcode/riscv-opc.h"
1117 opcode_names_hash
= str_htab_create ();
1118 init_opcode_names_hash ();
1120 /* Set the default alignment for the text section. */
1121 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1125 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1132 case BFD_RELOC_RISCV_HI20
:
1133 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1135 case BFD_RELOC_RISCV_LO12_S
:
1136 return ENCODE_STYPE_IMM (value
);
1138 case BFD_RELOC_RISCV_LO12_I
:
1139 return ENCODE_ITYPE_IMM (value
);
1146 /* Output an instruction. IP is the instruction information.
1147 ADDRESS_EXPR is an operand of the instruction to be used with
1151 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1152 bfd_reloc_code_real_type reloc_type
)
1154 dwarf2_emit_insn (0);
1156 if (reloc_type
!= BFD_RELOC_UNUSED
)
1158 reloc_howto_type
*howto
;
1160 gas_assert (address_expr
);
1161 if (reloc_type
== BFD_RELOC_12_PCREL
1162 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1164 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1165 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1166 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1168 if (now_seg
== absolute_section
)
1170 as_bad (_("relaxable branches not supported in absolute section"));
1174 add_relaxed_insn (ip
, worst_case
, best_case
,
1175 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1176 address_expr
->X_add_symbol
,
1177 address_expr
->X_add_number
);
1182 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1184 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1186 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1187 bfd_get_reloc_size (howto
),
1188 address_expr
, FALSE
, reloc_type
);
1190 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1194 add_fixed_insn (ip
);
1197 /* We need to start a new frag after any instruction that can be
1198 optimized away or compressed by the linker during relaxation, to prevent
1199 the assembler from computing static offsets across such an instruction.
1200 This is necessary to get correct EH info. */
1201 if (reloc_type
== BFD_RELOC_RISCV_HI20
1202 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1203 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1204 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1206 frag_wane (frag_now
);
1211 /* Build an instruction created by a macro expansion. This is passed
1212 a pointer to the count of instructions created so far, an expression,
1213 the name of the instruction to build, an operand format string, and
1214 corresponding arguments. */
1217 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1219 const struct riscv_opcode
*mo
;
1220 struct riscv_cl_insn insn
;
1221 bfd_reloc_code_real_type r
;
1224 va_start (args
, fmt
);
1226 r
= BFD_RELOC_UNUSED
;
1227 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1230 /* Find a non-RVC variant of the instruction. append_insn will compress
1232 while (riscv_insn_length (mo
->match
) < 4)
1234 gas_assert (strcmp (name
, mo
->name
) == 0);
1236 create_insn (&insn
, mo
);
1242 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1246 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1250 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1254 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1260 gas_assert (ep
!= NULL
);
1261 r
= va_arg (args
, int);
1269 as_fatal (_("internal error: invalid macro"));
1274 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1276 append_insn (&insn
, ep
, r
);
1279 /* Build an instruction created by a macro expansion. Like md_assemble but
1280 accept a printf-style format string and arguments. */
1283 md_assemblef (const char *format
, ...)
1289 va_start (ap
, format
);
1291 r
= vasprintf (&buf
, format
, ap
);
1294 as_fatal (_("internal error: vasprintf failed"));
1302 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1306 normalize_constant_expr (expressionS
*ex
)
1310 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1311 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1312 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1316 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1317 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1320 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1321 bfd_boolean maybe_csr
)
1323 if (ex
->X_op
== O_big
)
1324 as_bad (_("unsupported large constant"));
1325 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1326 as_bad (_("unknown CSR `%s'"),
1327 S_GET_NAME (ex
->X_add_symbol
));
1328 else if (ex
->X_op
!= O_constant
)
1329 as_bad (_("Instruction %s requires absolute expression"),
1331 normalize_constant_expr (ex
);
1335 make_internal_label (void)
1337 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1341 /* Load an entry from the GOT. */
1344 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1345 const char *lo_insn
, const char *lo_pattern
,
1346 bfd_reloc_code_real_type hi_reloc
,
1347 bfd_reloc_code_real_type lo_reloc
)
1350 ep2
.X_op
= O_symbol
;
1351 ep2
.X_add_symbol
= make_internal_label ();
1352 ep2
.X_add_number
= 0;
1354 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1355 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1359 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1360 bfd_reloc_code_real_type hi_reloc
,
1361 bfd_reloc_code_real_type lo_reloc
)
1363 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1367 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1368 bfd_reloc_code_real_type hi_reloc
,
1369 bfd_reloc_code_real_type lo_reloc
)
1371 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1374 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1377 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1378 bfd_reloc_code_real_type reloc
)
1380 /* Ensure the jalr is emitted to the same frag as the auipc. */
1382 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1383 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1384 /* See comment at end of append_insn. */
1385 frag_wane (frag_now
);
1389 /* Load an integer constant into a register. */
1392 load_const (int reg
, expressionS
*ep
)
1394 int shift
= RISCV_IMM_BITS
;
1395 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1396 expressionS upper
= *ep
, lower
= *ep
;
1397 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1398 upper
.X_add_number
-= lower
.X_add_number
;
1400 if (ep
->X_op
!= O_constant
)
1402 as_bad (_("unsupported large constant"));
1406 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1408 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1409 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1412 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1413 load_const (reg
, &upper
);
1415 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1416 if (lower
.X_add_number
!= 0)
1417 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1418 lower
.X_add_number
);
1422 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1425 if (upper
.X_add_number
!= 0)
1427 /* Discard low part and zero-extend upper immediate. */
1428 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1430 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1434 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1435 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1436 lower
.X_add_number
);
1440 /* Zero extend and sign extend byte/half-word/word. */
1443 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1447 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1448 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1452 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1453 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1457 /* Expand RISC-V assembly macros into one or more instructions. */
1460 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1461 bfd_reloc_code_real_type
*imm_reloc
)
1463 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1464 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1465 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1466 int mask
= ip
->insn_mo
->mask
;
1471 load_const (rd
, imm_expr
);
1476 /* Load the address of a symbol into a register. */
1477 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1478 as_bad (_("offset too large"));
1480 if (imm_expr
->X_op
== O_constant
)
1481 load_const (rd
, imm_expr
);
1482 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1483 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1484 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1485 else /* Local PIC symbol, or any non-PIC symbol. */
1486 pcrel_load (rd
, rd
, imm_expr
, "addi",
1487 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1491 pcrel_load (rd
, rd
, imm_expr
, "addi",
1492 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1496 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1497 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1501 pcrel_load (rd
, rd
, imm_expr
, "lb",
1502 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1506 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1507 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1511 pcrel_load (rd
, rd
, imm_expr
, "lh",
1512 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1516 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1517 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1521 pcrel_load (rd
, rd
, imm_expr
, "lw",
1522 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1526 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1527 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1531 pcrel_load (rd
, rd
, imm_expr
, "ld",
1532 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1536 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1537 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1541 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1542 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1546 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1547 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1551 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1552 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1556 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1557 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1561 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1562 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1566 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1567 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1571 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1572 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1576 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1580 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1584 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1588 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1592 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1596 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1601 static const struct percent_op_match percent_op_utype
[] =
1603 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1604 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1605 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1606 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1607 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1608 {"%hi", BFD_RELOC_RISCV_HI20
},
1612 static const struct percent_op_match percent_op_itype
[] =
1614 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1615 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1616 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1620 static const struct percent_op_match percent_op_stype
[] =
1622 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1623 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1624 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1628 static const struct percent_op_match percent_op_rtype
[] =
1630 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1634 static const struct percent_op_match percent_op_null
[] =
1639 /* Return true if *STR points to a relocation operator. When returning true,
1640 move *STR over the operator and store its relocation code in *RELOC.
1641 Leave both *STR and *RELOC alone when returning false. */
1644 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1645 const struct percent_op_match
*percent_op
)
1647 for ( ; percent_op
->str
; percent_op
++)
1648 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1650 int len
= strlen (percent_op
->str
);
1652 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1655 *str
+= strlen (percent_op
->str
);
1656 *reloc
= percent_op
->reloc
;
1658 /* Check whether the output BFD supports this relocation.
1659 If not, issue an error and fall back on something safe. */
1660 if (*reloc
!= BFD_RELOC_UNUSED
1661 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1663 as_bad ("relocation %s isn't supported by the current ABI",
1665 *reloc
= BFD_RELOC_UNUSED
;
1673 my_getExpression (expressionS
*ep
, char *str
)
1677 save_in
= input_line_pointer
;
1678 input_line_pointer
= str
;
1680 expr_end
= input_line_pointer
;
1681 input_line_pointer
= save_in
;
1684 /* Parse string STR as a 16-bit relocatable operand. Store the
1685 expression in *EP and the relocation, if any, in RELOC.
1686 Return the number of relocation operators used (0 or 1).
1688 On exit, EXPR_END points to the first character after the expression. */
1691 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1692 char *str
, const struct percent_op_match
*percent_op
)
1695 unsigned crux_depth
, str_depth
, regno
;
1698 /* First, check for integer registers. No callers can accept a reg, but
1699 we need to avoid accidentally creating a useless undefined symbol below,
1700 if this is an instruction pattern that can't match. A glibc build fails
1701 if this is removed. */
1702 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1704 ep
->X_op
= O_register
;
1705 ep
->X_add_number
= regno
;
1710 /* Search for the start of the main expression.
1712 End the loop with CRUX pointing to the start of the main expression and
1713 with CRUX_DEPTH containing the number of open brackets at that point. */
1720 crux_depth
= str_depth
;
1722 /* Skip over whitespace and brackets, keeping count of the number
1724 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1730 && parse_relocation (&str
, reloc
, percent_op
));
1732 my_getExpression (ep
, crux
);
1735 /* Match every open bracket. */
1736 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1741 as_bad ("unclosed '('");
1748 /* Parse opcode name, could be an mnemonics or number. */
1751 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1752 char *str
, const struct percent_op_match
*percent_op
)
1754 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1758 ep
->X_op
= O_constant
;
1759 ep
->X_add_number
= o
->val
;
1763 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1766 /* Detect and handle implicitly zero load-store offsets. For example,
1767 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1768 an implicit offset was detected. */
1771 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1773 /* Check whether there is only a single bracketed expression left.
1774 If so, it must be the base register and the constant must be zero. */
1775 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1777 ep
->X_op
= O_constant
;
1778 ep
->X_add_number
= 0;
1785 /* All RISC-V CSR instructions belong to one of these classes. */
1794 /* Return which CSR instruction is checking. */
1796 static enum csr_insn_type
1797 riscv_csr_insn_type (insn_t insn
)
1799 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1800 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1802 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1803 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1805 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1806 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1809 return INSN_NOT_CSR
;
1812 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1813 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1814 CSR address is 0x3. */
1817 riscv_csr_read_only_check (insn_t insn
)
1819 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1820 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1821 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1822 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1825 && (((csr_insn
== INSN_CSRRS
1826 || csr_insn
== INSN_CSRRC
)
1828 || csr_insn
== INSN_CSRRW
))
1834 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1836 uret is actually a N-ext instruction. So it is better to regard it as
1837 an user instruction rather than the priv instruction.
1839 hret is used to return from traps in H-mode. H-mode is removed since
1840 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1841 Therefore, hret should be controlled by the hypervisor spec rather than
1842 priv spec in the future.
1844 dret is defined in the debug spec, so it should be checked in the future,
1848 riscv_is_priv_insn (insn_t insn
)
1850 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1851 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1852 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1853 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1854 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1855 check it here to keep the compatible. */
1856 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1859 /* This routine assembles an instruction into its binary format. As a
1860 side effect, it sets the global variable imm_reloc to the type of
1861 relocation to do if one of the operands is an address expression. */
1864 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1865 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1870 struct riscv_opcode
*insn
;
1875 const struct percent_op_match
*p
;
1876 const char *error
= "unrecognized opcode";
1877 /* Indicate we are assembling instruction with CSR. */
1878 bfd_boolean insn_with_csr
= FALSE
;
1880 /* Parse the name of the instruction. Terminate the string if whitespace
1881 is found so that str_hash_find only sees the name part of the string. */
1882 for (s
= str
; *s
!= '\0'; ++s
)
1890 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1893 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1895 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1898 if (!riscv_multi_subset_supports (insn
->insn_class
))
1901 create_insn (ip
, insn
);
1904 imm_expr
->X_op
= O_absent
;
1905 *imm_reloc
= BFD_RELOC_UNUSED
;
1906 p
= percent_op_itype
;
1908 for (args
= insn
->args
;; ++args
)
1910 s
+= strspn (s
, " \t");
1913 case '\0': /* End of args. */
1914 if (insn
->pinfo
!= INSN_MACRO
)
1916 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1919 /* For .insn, insn->match and insn->mask are 0. */
1920 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1926 if (riscv_is_priv_insn (ip
->insn_opcode
))
1927 explicit_priv_attr
= TRUE
;
1929 /* Check if we write a read-only CSR by the CSR
1932 && riscv_opts
.csr_check
1933 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1935 /* Restore the character in advance, since we want to
1936 report the detailed warning message here. */
1938 *(argsStart
- 1) = save_c
;
1939 as_warn (_("Read-only CSR is written `%s'"), str
);
1940 insn_with_csr
= FALSE
;
1945 /* Successful assembly. */
1947 insn_with_csr
= FALSE
;
1953 case 's': /* RS1 x8-x15. */
1954 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1955 || !(regno
>= 8 && regno
<= 15))
1957 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1959 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1960 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1961 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1964 case 't': /* RS2 x8-x15. */
1965 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1966 || !(regno
>= 8 && regno
<= 15))
1968 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1970 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1971 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1972 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1975 case 'U': /* RS1, constrained to equal RD. */
1976 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1977 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1981 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1983 INSERT_OPERAND (CRS2
, *ip
, regno
);
1985 case 'c': /* RS1, constrained to equal sp. */
1986 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1990 case 'z': /* RS2, constrained to equal x0. */
1991 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1996 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1997 || imm_expr
->X_op
!= O_constant
1998 || imm_expr
->X_add_number
<= 0
1999 || imm_expr
->X_add_number
>= 64)
2001 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2004 imm_expr
->X_op
= O_absent
;
2007 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2008 || imm_expr
->X_op
!= O_constant
2009 || imm_expr
->X_add_number
<= 0
2010 || imm_expr
->X_add_number
>= 32
2011 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2013 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2016 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2017 || imm_expr
->X_op
!= O_constant
2018 || imm_expr
->X_add_number
< 0
2019 || imm_expr
->X_add_number
>= 256
2020 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2022 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2025 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2026 || imm_expr
->X_op
!= O_constant
2027 || imm_expr
->X_add_number
== 0
2028 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2030 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2033 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2034 || imm_expr
->X_op
!= O_constant
2035 || imm_expr
->X_add_number
== 0
2036 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2038 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2041 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2043 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2044 || imm_expr
->X_op
!= O_constant
2045 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2047 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2050 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2052 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2053 || imm_expr
->X_op
!= O_constant
2054 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2056 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2059 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2061 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2062 || imm_expr
->X_op
!= O_constant
2063 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2066 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2069 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2071 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2072 || imm_expr
->X_op
!= O_constant
2073 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2076 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2079 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2080 || imm_expr
->X_op
!= O_constant
2081 /* C.addiw, c.li, and c.andi allow zero immediate.
2082 C.addi allows zero immediate as hint. Otherwise this
2084 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2086 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2089 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2090 || imm_expr
->X_op
!= O_constant
2091 || imm_expr
->X_add_number
== 0
2092 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2095 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2098 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2099 || imm_expr
->X_op
!= O_constant
2100 || imm_expr
->X_add_number
== 0
2101 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2104 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2107 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2109 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2110 || imm_expr
->X_op
!= O_constant
2111 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2114 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2117 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2119 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2120 || imm_expr
->X_op
!= O_constant
2121 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2124 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2127 p
= percent_op_utype
;
2128 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2131 if (imm_expr
->X_op
!= O_constant
2132 || imm_expr
->X_add_number
<= 0
2133 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2134 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2135 && (imm_expr
->X_add_number
<
2136 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2138 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2141 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2142 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2143 || ((int32_t)imm_expr
->X_add_number
2144 != imm_expr
->X_add_number
))
2146 imm_expr
->X_add_number
=
2147 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2153 case 'S': /* Floating-point RS1 x8-x15. */
2154 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2155 || !(regno
>= 8 && regno
<= 15))
2157 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2159 case 'D': /* Floating-point RS2 x8-x15. */
2160 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2161 || !(regno
>= 8 && regno
<= 15))
2163 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2165 case 'T': /* Floating-point RS2. */
2166 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2168 INSERT_OPERAND (CRS2
, *ip
, regno
);
2174 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2175 || imm_expr
->X_op
!= O_constant
2176 || imm_expr
->X_add_number
< 0
2177 || imm_expr
->X_add_number
>= 64)
2179 as_bad (_("bad value for funct6 field, "
2180 "value must be 0...64"));
2184 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2185 imm_expr
->X_op
= O_absent
;
2189 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2190 || imm_expr
->X_op
!= O_constant
2191 || imm_expr
->X_add_number
< 0
2192 || imm_expr
->X_add_number
>= 16)
2194 as_bad (_("bad value for funct4 field, "
2195 "value must be 0...15"));
2199 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2200 imm_expr
->X_op
= O_absent
;
2204 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2205 || imm_expr
->X_op
!= O_constant
2206 || imm_expr
->X_add_number
< 0
2207 || imm_expr
->X_add_number
>= 8)
2209 as_bad (_("bad value for funct3 field, "
2210 "value must be 0...7"));
2213 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2214 imm_expr
->X_op
= O_absent
;
2218 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2219 || imm_expr
->X_op
!= O_constant
2220 || imm_expr
->X_add_number
< 0
2221 || imm_expr
->X_add_number
>= 4)
2223 as_bad (_("bad value for funct2 field, "
2224 "value must be 0...3"));
2227 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2228 imm_expr
->X_op
= O_absent
;
2232 as_bad (_("bad compressed FUNCT field"
2233 " specifier 'CF%c'\n"),
2239 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2258 case '<': /* Shift amount, 0 - 31. */
2259 my_getExpression (imm_expr
, s
);
2260 check_absolute_expr (ip
, imm_expr
, FALSE
);
2261 if ((unsigned long) imm_expr
->X_add_number
> 31)
2262 as_bad (_("Improper shift amount (%lu)"),
2263 (unsigned long) imm_expr
->X_add_number
);
2264 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2265 imm_expr
->X_op
= O_absent
;
2269 case '>': /* Shift amount, 0 - (XLEN-1). */
2270 my_getExpression (imm_expr
, s
);
2271 check_absolute_expr (ip
, imm_expr
, FALSE
);
2272 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2273 as_bad (_("Improper shift amount (%lu)"),
2274 (unsigned long) imm_expr
->X_add_number
);
2275 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2276 imm_expr
->X_op
= O_absent
;
2280 case 'Z': /* CSRRxI immediate. */
2281 my_getExpression (imm_expr
, s
);
2282 check_absolute_expr (ip
, imm_expr
, FALSE
);
2283 if ((unsigned long) imm_expr
->X_add_number
> 31)
2284 as_bad (_("Improper CSRxI immediate (%lu)"),
2285 (unsigned long) imm_expr
->X_add_number
);
2286 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2287 imm_expr
->X_op
= O_absent
;
2291 case 'E': /* Control register. */
2292 insn_with_csr
= TRUE
;
2293 explicit_priv_attr
= TRUE
;
2294 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2295 INSERT_OPERAND (CSR
, *ip
, regno
);
2298 my_getExpression (imm_expr
, s
);
2299 check_absolute_expr (ip
, imm_expr
, TRUE
);
2300 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2301 as_bad (_("Improper CSR address (%lu)"),
2302 (unsigned long) imm_expr
->X_add_number
);
2303 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2304 imm_expr
->X_op
= O_absent
;
2309 case 'm': /* Rounding mode. */
2310 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2312 INSERT_OPERAND (RM
, *ip
, regno
);
2318 case 'Q': /* Fence predecessor/successor. */
2319 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2323 INSERT_OPERAND (PRED
, *ip
, regno
);
2325 INSERT_OPERAND (SUCC
, *ip
, regno
);
2330 case 'd': /* Destination register. */
2331 case 's': /* Source register. */
2332 case 't': /* Target register. */
2334 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2340 /* Now that we have assembled one operand, we use the args
2341 string to figure out where it goes in the instruction. */
2345 INSERT_OPERAND (RS1
, *ip
, regno
);
2348 INSERT_OPERAND (RD
, *ip
, regno
);
2351 INSERT_OPERAND (RS2
, *ip
, regno
);
2354 INSERT_OPERAND (RS3
, *ip
, regno
);
2361 case 'D': /* Floating point RD. */
2362 case 'S': /* Floating point RS1. */
2363 case 'T': /* Floating point RS2. */
2364 case 'U': /* Floating point RS1 and RS2. */
2365 case 'R': /* Floating point RS3. */
2366 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2374 INSERT_OPERAND (RD
, *ip
, regno
);
2377 INSERT_OPERAND (RS1
, *ip
, regno
);
2380 INSERT_OPERAND (RS1
, *ip
, regno
);
2383 INSERT_OPERAND (RS2
, *ip
, regno
);
2386 INSERT_OPERAND (RS3
, *ip
, regno
);
2395 my_getExpression (imm_expr
, s
);
2396 if (imm_expr
->X_op
!= O_big
2397 && imm_expr
->X_op
!= O_constant
)
2399 normalize_constant_expr (imm_expr
);
2404 my_getExpression (imm_expr
, s
);
2405 normalize_constant_expr (imm_expr
);
2406 /* The 'A' format specifier must be a symbol. */
2407 if (imm_expr
->X_op
!= O_symbol
)
2409 *imm_reloc
= BFD_RELOC_32
;
2414 my_getExpression (imm_expr
, s
);
2415 normalize_constant_expr (imm_expr
);
2416 /* The 'B' format specifier must be a symbol or a constant. */
2417 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2419 if (imm_expr
->X_op
== O_symbol
)
2420 *imm_reloc
= BFD_RELOC_32
;
2424 case 'j': /* Sign-extended immediate. */
2425 p
= percent_op_itype
;
2426 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2428 case 'q': /* Store displacement. */
2429 p
= percent_op_stype
;
2430 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2432 case 'o': /* Load displacement. */
2433 p
= percent_op_itype
;
2434 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2437 /* This is used for TLS, where the fourth operand is
2438 %tprel_add, to get a relocation applied to an add
2439 instruction, for relaxation to use. */
2440 p
= percent_op_rtype
;
2442 case '0': /* AMO displacement, which must be zero. */
2443 p
= percent_op_null
;
2445 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2448 /* If this value won't fit into a 16 bit offset, then go
2449 find a macro that will generate the 32 bit offset
2451 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2453 normalize_constant_expr (imm_expr
);
2454 if (imm_expr
->X_op
!= O_constant
2455 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2457 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2458 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2465 case 'p': /* PC-relative offset. */
2467 *imm_reloc
= BFD_RELOC_12_PCREL
;
2468 my_getExpression (imm_expr
, s
);
2472 case 'u': /* Upper 20 bits. */
2473 p
= percent_op_utype
;
2474 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2476 if (imm_expr
->X_op
!= O_constant
)
2479 if (imm_expr
->X_add_number
< 0
2480 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2481 as_bad (_("lui expression not in range 0..1048575"));
2483 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2484 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2489 case 'a': /* 20-bit PC-relative offset. */
2491 my_getExpression (imm_expr
, s
);
2493 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2497 my_getExpression (imm_expr
, s
);
2499 if (strcmp (s
, "@plt") == 0)
2501 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2505 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2511 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2512 || imm_expr
->X_op
!= O_constant
2513 || imm_expr
->X_add_number
< 0
2514 || imm_expr
->X_add_number
>= 128
2515 || (imm_expr
->X_add_number
& 0x3) != 3)
2517 as_bad (_("bad value for opcode field, "
2518 "value must be 0...127 and "
2519 "lower 2 bits must be 0x3"));
2523 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2524 imm_expr
->X_op
= O_absent
;
2528 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2529 || imm_expr
->X_op
!= O_constant
2530 || imm_expr
->X_add_number
< 0
2531 || imm_expr
->X_add_number
>= 3)
2533 as_bad (_("bad value for opcode field, "
2534 "value must be 0...2"));
2538 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2539 imm_expr
->X_op
= O_absent
;
2543 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2551 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2552 || imm_expr
->X_op
!= O_constant
2553 || imm_expr
->X_add_number
< 0
2554 || imm_expr
->X_add_number
>= 128)
2556 as_bad (_("bad value for funct7 field, "
2557 "value must be 0...127"));
2561 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2562 imm_expr
->X_op
= O_absent
;
2566 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2567 || imm_expr
->X_op
!= O_constant
2568 || imm_expr
->X_add_number
< 0
2569 || imm_expr
->X_add_number
>= 8)
2571 as_bad (_("bad value for funct3 field, "
2572 "value must be 0...7"));
2576 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2577 imm_expr
->X_op
= O_absent
;
2581 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2582 || imm_expr
->X_op
!= O_constant
2583 || imm_expr
->X_add_number
< 0
2584 || imm_expr
->X_add_number
>= 4)
2586 as_bad (_("bad value for funct2 field, "
2587 "value must be 0...3"));
2591 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2592 imm_expr
->X_op
= O_absent
;
2597 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2602 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2603 || imm_expr
->X_op
!= O_constant
2604 || imm_expr
->X_add_number
!= 0)
2607 imm_expr
->X_op
= O_absent
;
2611 as_fatal (_("internal error: bad argument type %c"), *args
);
2616 error
= _("illegal operands");
2617 insn_with_csr
= FALSE
;
2621 /* Restore the character we might have clobbered above. */
2623 *(argsStart
- 1) = save_c
;
2629 md_assemble (char *str
)
2631 struct riscv_cl_insn insn
;
2632 expressionS imm_expr
;
2633 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2635 /* The architecture and privileged elf attributes should be set
2636 before assembling. */
2637 if (!start_assemble
)
2639 start_assemble
= TRUE
;
2641 riscv_set_abi_by_arch ();
2642 if (!riscv_set_default_priv_spec (NULL
))
2646 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2650 as_bad ("%s `%s'", error
, str
);
2654 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2655 macro (&insn
, &imm_expr
, &imm_reloc
);
2657 append_insn (&insn
, &imm_expr
, imm_reloc
);
2661 md_atof (int type
, char *litP
, int *sizeP
)
2663 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2667 md_number_to_chars (char *buf
, valueT val
, int n
)
2669 if (target_big_endian
)
2670 number_to_chars_bigendian (buf
, val
, n
);
2672 number_to_chars_littleendian (buf
, val
, n
);
2675 const char *md_shortopts
= "O::g::G:";
2679 OPTION_MARCH
= OPTION_MD_BASE
,
2686 OPTION_NO_ARCH_ATTR
,
2688 OPTION_NO_CSR_CHECK
,
2692 OPTION_LITTLE_ENDIAN
,
2696 struct option md_longopts
[] =
2698 {"march", required_argument
, NULL
, OPTION_MARCH
},
2699 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2700 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2701 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2702 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2703 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2704 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2705 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2706 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2707 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2708 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2709 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2710 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2711 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2712 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2714 {NULL
, no_argument
, NULL
, 0}
2716 size_t md_longopts_size
= sizeof (md_longopts
);
2719 md_parse_option (int c
, const char *arg
)
2724 default_arch_with_ext
= arg
;
2728 riscv_opts
.pic
= FALSE
;
2732 riscv_opts
.pic
= TRUE
;
2736 if (strcmp (arg
, "ilp32") == 0)
2737 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2738 else if (strcmp (arg
, "ilp32e") == 0)
2739 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2740 else if (strcmp (arg
, "ilp32f") == 0)
2741 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2742 else if (strcmp (arg
, "ilp32d") == 0)
2743 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2744 else if (strcmp (arg
, "ilp32q") == 0)
2745 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2746 else if (strcmp (arg
, "lp64") == 0)
2747 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2748 else if (strcmp (arg
, "lp64f") == 0)
2749 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2750 else if (strcmp (arg
, "lp64d") == 0)
2751 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2752 else if (strcmp (arg
, "lp64q") == 0)
2753 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2756 explicit_mabi
= TRUE
;
2760 riscv_opts
.relax
= TRUE
;
2763 case OPTION_NO_RELAX
:
2764 riscv_opts
.relax
= FALSE
;
2767 case OPTION_ARCH_ATTR
:
2768 riscv_opts
.arch_attr
= TRUE
;
2771 case OPTION_NO_ARCH_ATTR
:
2772 riscv_opts
.arch_attr
= FALSE
;
2775 case OPTION_CSR_CHECK
:
2776 riscv_opts
.csr_check
= TRUE
;
2779 case OPTION_NO_CSR_CHECK
:
2780 riscv_opts
.csr_check
= FALSE
;
2783 case OPTION_MISA_SPEC
:
2784 return riscv_set_default_isa_spec (arg
);
2786 case OPTION_MPRIV_SPEC
:
2787 return riscv_set_default_priv_spec (arg
);
2789 case OPTION_BIG_ENDIAN
:
2790 target_big_endian
= 1;
2793 case OPTION_LITTLE_ENDIAN
:
2794 target_big_endian
= 0;
2805 riscv_after_parse_args (void)
2807 /* The --with-arch is optional for now, so we still need to set the xlen
2808 according to the default_arch, which is set by the --target. */
2811 if (strcmp (default_arch
, "riscv32") == 0)
2813 else if (strcmp (default_arch
, "riscv64") == 0)
2816 as_bad ("unknown default architecture `%s'", default_arch
);
2818 if (default_arch_with_ext
== NULL
)
2819 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2821 /* Initialize the hash table for extensions with default version. */
2822 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2824 /* Set default specs. */
2825 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2826 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2827 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2828 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2830 riscv_set_arch (default_arch_with_ext
);
2832 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2833 riscv_set_rvc (FALSE
);
2834 if (riscv_subset_supports ("c"))
2835 riscv_set_rvc (TRUE
);
2837 /* Enable RVE if specified by the -march option. */
2838 riscv_set_rve (FALSE
);
2839 if (riscv_subset_supports ("e"))
2840 riscv_set_rve (TRUE
);
2842 /* If the CIE to be produced has not been overridden on the command line,
2843 then produce version 3 by default. This allows us to use the full
2844 range of registers in a .cfi_return_column directive. */
2845 if (flag_dwarf_cie_version
== -1)
2846 flag_dwarf_cie_version
= 3;
2850 md_pcrel_from (fixS
*fixP
)
2852 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2855 /* Apply a fixup to the object file. */
2858 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2860 unsigned int subtype
;
2861 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2862 bfd_boolean relaxable
= FALSE
;
2866 /* Remember value for tc_gen_reloc. */
2867 fixP
->fx_addnumber
= *valP
;
2869 switch (fixP
->fx_r_type
)
2871 case BFD_RELOC_RISCV_HI20
:
2872 case BFD_RELOC_RISCV_LO12_I
:
2873 case BFD_RELOC_RISCV_LO12_S
:
2874 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2875 | bfd_getl32 (buf
), buf
);
2876 if (fixP
->fx_addsy
== NULL
)
2877 fixP
->fx_done
= TRUE
;
2881 case BFD_RELOC_RISCV_GOT_HI20
:
2882 case BFD_RELOC_RISCV_ADD8
:
2883 case BFD_RELOC_RISCV_ADD16
:
2884 case BFD_RELOC_RISCV_ADD32
:
2885 case BFD_RELOC_RISCV_ADD64
:
2886 case BFD_RELOC_RISCV_SUB6
:
2887 case BFD_RELOC_RISCV_SUB8
:
2888 case BFD_RELOC_RISCV_SUB16
:
2889 case BFD_RELOC_RISCV_SUB32
:
2890 case BFD_RELOC_RISCV_SUB64
:
2891 case BFD_RELOC_RISCV_RELAX
:
2894 case BFD_RELOC_RISCV_TPREL_HI20
:
2895 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2896 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2897 case BFD_RELOC_RISCV_TPREL_ADD
:
2901 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2902 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2903 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2904 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2905 if (fixP
->fx_addsy
!= NULL
)
2906 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2909 _("TLS relocation against a constant"));
2913 /* Use pc-relative relocation for FDE initial location.
2914 The symbol address in .eh_frame may be adjusted in
2915 _bfd_elf_discard_section_eh_frame, and the content of
2916 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2917 Therefore, we cannot insert a relocation whose addend symbol is
2918 in .eh_frame. Othrewise, the value may be adjusted twice. */
2919 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2920 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2921 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2922 && S_GET_VALUE (fixP
->fx_subsy
)
2923 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2925 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2926 fixP
->fx_subsy
= NULL
;
2933 case BFD_RELOC_RISCV_CFA
:
2934 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2936 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2937 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2938 fixP
->fx_next
->fx_subsy
= NULL
;
2939 fixP
->fx_next
->fx_offset
= 0;
2940 fixP
->fx_subsy
= NULL
;
2942 switch (fixP
->fx_r_type
)
2945 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2946 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2950 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2951 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2955 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2956 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2960 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2961 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2964 case BFD_RELOC_RISCV_CFA
:
2965 /* Load the byte to get the subtype. */
2966 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2967 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2970 case DW_CFA_advance_loc1
:
2971 fixP
->fx_where
= loc
+ 1;
2972 fixP
->fx_next
->fx_where
= loc
+ 1;
2973 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2974 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2977 case DW_CFA_advance_loc2
:
2979 fixP
->fx_next
->fx_size
= 2;
2980 fixP
->fx_where
= loc
+ 1;
2981 fixP
->fx_next
->fx_where
= loc
+ 1;
2982 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2983 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2986 case DW_CFA_advance_loc4
:
2988 fixP
->fx_next
->fx_size
= 4;
2989 fixP
->fx_where
= loc
;
2990 fixP
->fx_next
->fx_where
= loc
;
2991 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2992 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2996 if (subtype
< 0x80 && (subtype
& 0x40))
2998 /* DW_CFA_advance_loc */
2999 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3000 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3001 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3002 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3005 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
3011 /* This case is unreachable. */
3018 /* If we are deleting this reloc entry, we must fill in the
3019 value now. This can happen if we have a .word which is not
3020 resolved when it appears but is later defined. */
3021 if (fixP
->fx_addsy
== NULL
)
3023 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3024 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3029 case BFD_RELOC_RISCV_JMP
:
3032 /* Fill in a tentative value to improve objdump readability. */
3033 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3034 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3035 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3039 case BFD_RELOC_12_PCREL
:
3042 /* Fill in a tentative value to improve objdump readability. */
3043 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3044 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3045 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3049 case BFD_RELOC_RISCV_RVC_BRANCH
:
3052 /* Fill in a tentative value to improve objdump readability. */
3053 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3054 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3055 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3059 case BFD_RELOC_RISCV_RVC_JUMP
:
3062 /* Fill in a tentative value to improve objdump readability. */
3063 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3064 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3065 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3069 case BFD_RELOC_RISCV_CALL
:
3070 case BFD_RELOC_RISCV_CALL_PLT
:
3074 case BFD_RELOC_RISCV_PCREL_HI20
:
3075 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3076 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3077 relaxable
= riscv_opts
.relax
;
3080 case BFD_RELOC_RISCV_ALIGN
:
3084 /* We ignore generic BFD relocations we don't know about. */
3085 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3086 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3089 if (fixP
->fx_subsy
!= NULL
)
3090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3091 _("unsupported symbol subtraction"));
3093 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3094 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3096 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3097 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3098 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3099 fixP
->fx_next
->fx_size
= 0;
3103 /* Because the value of .cfi_remember_state may changed after relaxation,
3104 we insert a fix to relocate it again in link-time. */
3107 riscv_pre_output_hook (void)
3109 const frchainS
*frch
;
3112 /* Save the current segment info. */
3114 subsegT subseg
= now_subseg
;
3116 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3117 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3121 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3123 if (frag
->fr_type
== rs_cfa
)
3126 expressionS
*symval
;
3128 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3129 exp
.X_op
= O_subtract
;
3130 exp
.X_add_symbol
= symval
->X_add_symbol
;
3131 exp
.X_add_number
= 0;
3132 exp
.X_op_symbol
= symval
->X_op_symbol
;
3134 /* We must set the segment before creating a frag after all
3135 frag chains have been chained together. */
3136 subseg_set (s
, frch
->frch_subseg
);
3138 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3139 BFD_RELOC_RISCV_CFA
);
3144 /* Restore the original segment info. */
3145 subseg_set (seg
, subseg
);
3148 /* This structure is used to hold a stack of .option values. */
3149 struct riscv_option_stack
3151 struct riscv_option_stack
*next
;
3152 struct riscv_set_options options
;
3155 static struct riscv_option_stack
*riscv_opts_stack
;
3157 /* Handle the .option pseudo-op. */
3160 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3162 char *name
= input_line_pointer
, ch
;
3164 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3165 ++input_line_pointer
;
3166 ch
= *input_line_pointer
;
3167 *input_line_pointer
= '\0';
3169 if (strcmp (name
, "rvc") == 0)
3170 riscv_set_rvc (TRUE
);
3171 else if (strcmp (name
, "norvc") == 0)
3172 riscv_set_rvc (FALSE
);
3173 else if (strcmp (name
, "pic") == 0)
3174 riscv_opts
.pic
= TRUE
;
3175 else if (strcmp (name
, "nopic") == 0)
3176 riscv_opts
.pic
= FALSE
;
3177 else if (strcmp (name
, "relax") == 0)
3178 riscv_opts
.relax
= TRUE
;
3179 else if (strcmp (name
, "norelax") == 0)
3180 riscv_opts
.relax
= FALSE
;
3181 else if (strcmp (name
, "csr-check") == 0)
3182 riscv_opts
.csr_check
= TRUE
;
3183 else if (strcmp (name
, "no-csr-check") == 0)
3184 riscv_opts
.csr_check
= FALSE
;
3185 else if (strcmp (name
, "push") == 0)
3187 struct riscv_option_stack
*s
;
3189 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3190 s
->next
= riscv_opts_stack
;
3191 s
->options
= riscv_opts
;
3192 riscv_opts_stack
= s
;
3194 else if (strcmp (name
, "pop") == 0)
3196 struct riscv_option_stack
*s
;
3198 s
= riscv_opts_stack
;
3200 as_bad (_(".option pop with no .option push"));
3203 riscv_opts
= s
->options
;
3204 riscv_opts_stack
= s
->next
;
3210 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3212 *input_line_pointer
= ch
;
3213 demand_empty_rest_of_line ();
3216 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3217 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3218 use in DWARF debug information. */
3221 s_dtprel (int bytes
)
3228 if (ex
.X_op
!= O_symbol
)
3230 as_bad (_("Unsupported use of %s"), (bytes
== 8
3233 ignore_rest_of_line ();
3236 p
= frag_more (bytes
);
3237 md_number_to_chars (p
, 0, bytes
);
3238 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3240 ? BFD_RELOC_RISCV_TLS_DTPREL64
3241 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3243 demand_empty_rest_of_line ();
3246 /* Handle the .bss pseudo-op. */
3249 s_bss (int ignore ATTRIBUTE_UNUSED
)
3251 subseg_set (bss_section
, 0);
3252 demand_empty_rest_of_line ();
3256 riscv_make_nops (char *buf
, bfd_vma bytes
)
3260 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3261 means we are not within a valid instruction sequence. It is thus safe
3262 to use a zero byte, even though that is not a valid instruction. */
3266 /* Use at most one 2-byte NOP. */
3267 if ((bytes
- i
) % 4 == 2)
3269 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3273 /* Fill the remainder with 4-byte NOPs. */
3274 for ( ; i
< bytes
; i
+= 4)
3275 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3278 /* Called from md_do_align. Used to create an alignment frag in a
3279 code section by emitting a worst-case NOP sequence that the linker
3280 will later relax to the correct number of NOPs. We can't compute
3281 the correct alignment now because of other linker relaxations. */
3284 riscv_frag_align_code (int n
)
3286 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3287 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3288 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3292 /* If we are moving to a smaller alignment than the instruction size, then no
3293 alignment is required. */
3294 if (bytes
<= insn_alignment
)
3297 /* When not relaxing, riscv_handle_align handles code alignment. */
3298 if (!riscv_opts
.relax
)
3301 nops
= frag_more (worst_case_bytes
);
3303 ex
.X_op
= O_constant
;
3304 ex
.X_add_number
= worst_case_bytes
;
3306 riscv_make_nops (nops
, worst_case_bytes
);
3308 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3309 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3314 /* Implement HANDLE_ALIGN. */
3317 riscv_handle_align (fragS
*fragP
)
3319 switch (fragP
->fr_type
)
3322 /* When relaxing, riscv_frag_align_code handles code alignment. */
3323 if (!riscv_opts
.relax
)
3325 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3326 - fragP
->fr_address
- fragP
->fr_fix
);
3327 /* We have 4 byte uncompressed nops. */
3328 bfd_signed_vma size
= 4;
3329 bfd_signed_vma excess
= bytes
% size
;
3330 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3335 /* Insert zeros or compressed nops to get 4 byte alignment. */
3338 riscv_make_nops (p
, excess
);
3339 fragP
->fr_fix
+= excess
;
3343 /* Insert variable number of 4 byte uncompressed nops. */
3344 riscv_make_nops (p
, size
);
3345 fragP
->fr_var
= size
;
3355 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3357 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3360 /* Translate internal representation of relocation info to BFD target
3364 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3366 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3368 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3369 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3370 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3371 reloc
->addend
= fixp
->fx_addnumber
;
3373 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3374 if (reloc
->howto
== NULL
)
3376 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3377 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3379 /* We don't have R_RISCV_8/16, but for this special case,
3380 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3384 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3385 _("cannot represent %s relocation in object file"),
3386 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3394 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3396 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3398 offsetT old_var
= fragp
->fr_var
;
3399 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3400 return fragp
->fr_var
- old_var
;
3406 /* Expand far branches to multi-instruction sequences. */
3409 md_convert_frag_branch (fragS
*fragp
)
3417 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3419 exp
.X_op
= O_symbol
;
3420 exp
.X_add_symbol
= fragp
->fr_symbol
;
3421 exp
.X_add_number
= fragp
->fr_offset
;
3423 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3425 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3427 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3431 /* Expand the RVC branch into a RISC-V one. */
3432 insn
= bfd_getl16 (buf
);
3433 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3434 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3436 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3437 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3438 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3439 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3440 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3441 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3444 bfd_putl32 (insn
, buf
);
3448 /* Invert the branch condition. Branch over the jump. */
3449 insn
= bfd_getl16 (buf
);
3450 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3451 insn
|= ENCODE_RVC_B_IMM (6);
3452 bfd_putl16 (insn
, buf
);
3457 /* Just keep the RVC branch. */
3458 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3459 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3460 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3461 2, &exp
, FALSE
, reloc
);
3470 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3473 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3475 /* Invert the branch condition. Branch over the jump. */
3476 insn
= bfd_getl32 (buf
);
3477 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3478 insn
|= ENCODE_SBTYPE_IMM (8);
3479 bfd_putl32 (insn
, buf
);
3483 /* Jump to the target. */
3484 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3485 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3486 bfd_putl32 (MATCH_JAL
, buf
);
3491 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3492 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3493 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3494 4, &exp
, FALSE
, reloc
);
3503 fixp
->fx_file
= fragp
->fr_file
;
3504 fixp
->fx_line
= fragp
->fr_line
;
3506 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3507 + fragp
->fr_fix
+ fragp
->fr_var
);
3509 fragp
->fr_fix
+= fragp
->fr_var
;
3512 /* Relax a machine dependent frag. This returns the amount by which
3513 the current size of the frag should change. */
3516 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3519 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3520 md_convert_frag_branch (fragp
);
3524 md_show_usage (FILE *stream
)
3526 fprintf (stream
, _("\
3528 -fpic generate position-independent code\n\
3529 -fno-pic don't generate position-independent code (default)\n\
3530 -march=ISA set the RISC-V architecture\n\
3531 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3532 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3533 -mabi=ABI set the RISC-V ABI\n\
3534 -mrelax enable relax (default)\n\
3535 -mno-relax disable relax\n\
3536 -march-attr generate RISC-V arch attribute\n\
3537 -mno-arch-attr don't generate RISC-V arch attribute\n\
3541 /* Standard calling conventions leave the CFA at SP on entry. */
3544 riscv_cfi_frame_initial_instructions (void)
3546 cfi_add_CFA_def_cfa_register (X_SP
);
3550 tc_riscv_regname_to_dw2regnum (char *regname
)
3554 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3557 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3560 /* CSRs are numbered 4096 -> 8191. */
3561 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3564 as_bad (_("unknown register `%s'"), regname
);
3569 riscv_elf_final_processing (void)
3571 riscv_set_abi_by_arch ();
3572 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3575 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3576 since these directives break relaxation when used with symbol deltas. */
3579 s_riscv_leb128 (int sign
)
3582 char *save_in
= input_line_pointer
;
3585 if (exp
.X_op
!= O_constant
)
3586 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3587 demand_empty_rest_of_line ();
3589 input_line_pointer
= save_in
;
3590 return s_leb128 (sign
);
3593 /* Parse the .insn directive. */
3596 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3598 char *str
= input_line_pointer
;
3599 struct riscv_cl_insn insn
;
3600 expressionS imm_expr
;
3601 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3604 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3605 ++input_line_pointer
;
3607 save_c
= *input_line_pointer
;
3608 *input_line_pointer
= '\0';
3610 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3611 &imm_reloc
, insn_type_hash
);
3615 as_bad ("%s `%s'", error
, str
);
3619 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3620 append_insn (&insn
, &imm_expr
, imm_reloc
);
3623 *input_line_pointer
= save_c
;
3624 demand_empty_rest_of_line ();
3627 /* Update architecture and privileged elf attributes. If we don't set
3628 them, then try to output the default ones. */
3631 riscv_write_out_attrs (void)
3633 const char *arch_str
, *priv_str
, *p
;
3634 /* versions[0]: major version.
3635 versions[1]: minor version.
3636 versions[2]: revision version. */
3637 unsigned versions
[3] = {0}, number
= 0;
3640 /* Re-write architecture elf attribute. */
3641 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3642 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3643 xfree ((void *)arch_str
);
3645 /* For the file without any instruction, we don't set the default_priv_spec
3646 according to the privileged elf attributes since the md_assemble isn't
3649 && !riscv_set_default_priv_spec (NULL
))
3652 /* If we already have set privileged elf attributes, then no need to do
3653 anything. Otherwise, don't generate or update them when no CSR and
3654 privileged instructions are used. */
3655 if (!explicit_priv_attr
)
3658 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3660 for (i
= 0; *p
; ++p
)
3662 if (*p
== '.' && i
< 3)
3664 versions
[i
++] = number
;
3667 else if (ISDIGIT (*p
))
3668 number
= (number
* 10) + (*p
- '0');
3671 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3675 versions
[i
] = number
;
3677 /* Re-write privileged elf attributes. */
3678 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3679 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3680 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3683 /* Add the default contents for the .riscv.attributes section. */
3686 riscv_set_public_attributes (void)
3688 if (riscv_opts
.arch_attr
|| explicit_attr
)
3689 riscv_write_out_attrs ();
3692 /* Called after all assembly has been done. */
3697 riscv_set_public_attributes ();
3700 /* Given a symbolic attribute NAME, return the proper integer value.
3701 Returns -1 if the attribute is not known. */
3704 riscv_convert_symbolic_attribute (const char *name
)
3713 /* When you modify this table you should
3714 also modify the list in doc/c-riscv.texi. */
3715 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3719 T(priv_spec_revision
),
3720 T(unaligned_access
),
3730 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3731 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3732 return attribute_table
[i
].tag
;
3737 /* Parse a .attribute directive. */
3740 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3742 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3744 obj_attribute
*attr
;
3746 explicit_attr
= TRUE
;
3749 case Tag_RISCV_arch
:
3751 attr
= elf_known_obj_attributes_proc (stdoutput
);
3752 if (!start_assemble
)
3753 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3755 as_fatal (_(".attribute arch must set before any instructions"));
3757 if (old_xlen
!= xlen
)
3759 /* We must re-init bfd again if xlen is changed. */
3760 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3761 bfd_find_target (riscv_target_format (), stdoutput
);
3763 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3764 as_warn (_("Could not set architecture and machine"));
3768 case Tag_RISCV_priv_spec
:
3769 case Tag_RISCV_priv_spec_minor
:
3770 case Tag_RISCV_priv_spec_revision
:
3772 as_fatal (_(".attribute priv spec must set before any instructions"));
3780 /* RISC-V pseudo-ops table. */
3781 static const pseudo_typeS riscv_pseudo_table
[] =
3783 {"option", s_riscv_option
, 0},
3787 {"dtprelword", s_dtprel
, 4},
3788 {"dtpreldword", s_dtprel
, 8},
3790 {"uleb128", s_riscv_leb128
, 0},
3791 {"sleb128", s_riscv_leb128
, 1},
3792 {"insn", s_riscv_insn
, 0},
3793 {"attribute", s_riscv_attribute
, 0},
3799 riscv_pop_insert (void)
3801 extern void pop_insert (const pseudo_typeS
*);
3803 pop_insert (riscv_pseudo_table
);