1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_add_subset (const char *subset
)
126 struct riscv_subset
*s
= xmalloc (sizeof *s
);
128 s
->name
= xstrdup (subset
);
129 s
->next
= riscv_subsets
;
133 /* Set which ISA and extensions are available. */
136 riscv_set_arch (const char *s
)
138 const char *all_subsets
= "imafdc";
139 const char *extension
= NULL
;
142 if (strncmp (p
, "rv32", 4) == 0)
147 else if (strncmp (p
, "rv64", 4) == 0)
153 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
162 for ( ; *all_subsets
!= 'c'; all_subsets
++)
164 const char subset
[] = {*all_subsets
, '\0'};
165 riscv_add_subset (subset
);
170 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
177 char *subset
= xstrdup (p
), *q
= subset
;
179 while (*++q
!= '\0' && *q
!= '_')
184 as_fatal ("-march=%s: only one non-standard extension is supported"
185 " (found `%s' and `%s')", s
, extension
, subset
);
187 riscv_add_subset (subset
);
188 p
+= strlen (subset
);
193 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
195 const char subset
[] = {*p
, 0};
196 riscv_add_subset (subset
);
202 const char subset
[] = {*p
, 0};
203 riscv_add_subset (subset
);
207 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
211 /* Handle of the OPCODE hash table. */
212 static struct hash_control
*op_hash
= NULL
;
214 /* This array holds the chars that always start a comment. If the
215 pre-processor is disabled, these aren't very useful */
216 const char comment_chars
[] = "#";
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output */
221 /* Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output. */
224 /* Also note that C style comments are always supported. */
225 const char line_comment_chars
[] = "#";
227 /* This array holds machine specific line separator characters. */
228 const char line_separator_chars
[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point nums */
231 const char EXP_CHARS
[] = "eE";
233 /* Chars that mean this number is a floating point constant */
236 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
238 /* Macros for encoding relaxation state for RVC branches and far jumps. */
239 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
242 | ((uncond) ? 1 : 0) \
245 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
246 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
247 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
248 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
250 /* Is the given value a sign-extended 32-bit value? */
251 #define IS_SEXT_32BIT_NUM(x) \
252 (((x) &~ (offsetT) 0x7fffffff) == 0 \
253 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
255 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
256 #define IS_ZEXT_32BIT_NUM(x) \
257 (((x) &~ (offsetT) 0xffffffff) == 0 \
258 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
260 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
261 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
262 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
263 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
265 /* Determine if an instruction matches an opcode. */
266 #define OPCODE_MATCHES(OPCODE, OP) \
267 (((OPCODE) & MASK_##OP) == MATCH_##OP)
269 static char *expr_end
;
271 /* The default target format to use. */
274 riscv_target_format (void)
276 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
279 /* Return the length of instruction INSN. */
281 static inline unsigned int
282 insn_length (const struct riscv_cl_insn
*insn
)
284 return riscv_insn_length (insn
->insn_opcode
);
287 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
290 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
293 insn
->insn_opcode
= mo
->match
;
299 /* Install INSN at the location specified by its "frag" and "where" fields. */
302 install_insn (const struct riscv_cl_insn
*insn
)
304 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
305 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
308 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
309 and install the opcode in the new location. */
312 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
316 if (insn
->fixp
!= NULL
)
318 insn
->fixp
->fx_frag
= frag
;
319 insn
->fixp
->fx_where
= where
;
324 /* Add INSN to the end of the output. */
327 add_fixed_insn (struct riscv_cl_insn
*insn
)
329 char *f
= frag_more (insn_length (insn
));
330 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
334 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
335 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
337 frag_grow (max_chars
);
338 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
339 frag_var (rs_machine_dependent
, max_chars
, var
,
340 subtype
, symbol
, offset
, NULL
);
343 /* Compute the length of a branch sequence, and adjust the stored length
344 accordingly. If FRAGP is NULL, the worst-case length is returned. */
347 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
349 int jump
, rvc
, length
= 8;
354 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
355 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
356 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
358 /* Assume jumps are in range; the linker will catch any that aren't. */
359 length
= jump
? 4 : 8;
361 if (fragp
->fr_symbol
!= NULL
362 && S_IS_DEFINED (fragp
->fr_symbol
)
363 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
365 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
366 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
367 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
369 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
371 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
373 else if (!jump
&& rvc
)
378 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
397 static struct hash_control
*reg_names_hash
= NULL
;
399 #define ENCODE_REG_HASH(cls, n) \
400 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
401 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
402 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
405 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
407 void *hash
= ENCODE_REG_HASH (class, n
);
408 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
411 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
415 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
419 for (i
= 0; i
< n
; i
++)
420 hash_reg_name (class, names
[i
], i
);
424 reg_lookup_internal (const char *s
, enum reg_class
class)
426 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
428 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
430 return DECODE_REG_NUM (r
);
434 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
440 /* Find end of name. */
442 if (is_name_beginner (*e
))
444 while (is_part_of_name (*e
))
447 /* Terminate name. */
451 /* Look for the register. Advance to next token if one was recognized. */
452 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
462 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
464 const char *p
= strchr (*s
, ',');
465 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
467 for (i
= 0; i
< size
; i
++)
468 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
478 /* For consistency checking, verify that all bits are specified either
479 by the match/mask part of the instruction definition, or by the
482 validate_riscv_insn (const struct riscv_opcode
*opc
)
484 const char *p
= opc
->args
;
486 insn_t used_bits
= opc
->mask
;
487 int insn_width
= 8 * riscv_insn_length (opc
->match
);
488 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
490 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
492 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
493 opc
->name
, opc
->args
);
497 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
504 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
505 case 'c': break; /* RS1, constrained to equal sp */
506 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
507 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
508 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
509 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
510 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
511 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
512 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
513 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
514 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
515 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
516 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
517 case 'w': break; /* RS1S, constrained to equal RD */
518 case 'x': break; /* RS2S, constrained to equal RD */
519 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
520 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
521 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
522 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
523 case 'U': break; /* RS1, constrained to equal RD */
524 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
525 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
526 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
527 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
528 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
530 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
531 c
, opc
->name
, opc
->args
);
538 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
539 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
541 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
542 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
543 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
545 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
546 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
547 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
548 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
549 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
550 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
551 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
552 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
553 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
554 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
556 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
557 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
558 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
559 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
560 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
565 as_bad (_("internal: bad RISC-V opcode "
566 "(unknown operand type `%c'): %s %s"),
567 c
, opc
->name
, opc
->args
);
571 if (used_bits
!= required_bits
)
573 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
574 ~(unsigned long)(used_bits
& required_bits
),
575 opc
->name
, opc
->args
);
581 struct percent_op_match
584 bfd_reloc_code_real_type reloc
;
587 /* This function is called once, at assembler startup time. It should set up
588 all the tables, etc. that the MD part of the assembler will need. */
594 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
596 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
597 as_warn (_("Could not set architecture and machine"));
599 op_hash
= hash_new ();
601 while (riscv_opcodes
[i
].name
)
603 const char *name
= riscv_opcodes
[i
].name
;
604 const char *hash_error
=
605 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
609 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
610 riscv_opcodes
[i
].name
, hash_error
);
611 /* Probably a memory allocation problem? Give up now. */
612 as_fatal (_("Broken assembler. No assembly attempted."));
617 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
619 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
620 as_fatal (_("Broken assembler. No assembly attempted."));
624 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
627 reg_names_hash
= hash_new ();
628 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
629 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
630 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
631 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
633 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
634 #include "opcode/riscv-opc.h"
637 /* Set the default alignment for the text section. */
638 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
642 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
649 case BFD_RELOC_RISCV_HI20
:
650 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
652 case BFD_RELOC_RISCV_LO12_S
:
653 return ENCODE_STYPE_IMM (value
);
655 case BFD_RELOC_RISCV_LO12_I
:
656 return ENCODE_ITYPE_IMM (value
);
663 /* Output an instruction. IP is the instruction information.
664 ADDRESS_EXPR is an operand of the instruction to be used with
668 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
669 bfd_reloc_code_real_type reloc_type
)
671 dwarf2_emit_insn (0);
673 if (reloc_type
!= BFD_RELOC_UNUSED
)
675 reloc_howto_type
*howto
;
677 gas_assert (address_expr
);
678 if (reloc_type
== BFD_RELOC_12_PCREL
679 || reloc_type
== BFD_RELOC_RISCV_JMP
)
681 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
682 int best_case
= riscv_insn_length (ip
->insn_opcode
);
683 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
684 add_relaxed_insn (ip
, worst_case
, best_case
,
685 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
686 address_expr
->X_add_symbol
,
687 address_expr
->X_add_number
);
690 else if (address_expr
->X_op
== O_constant
)
691 ip
->insn_opcode
|= riscv_apply_const_reloc (reloc_type
,
692 address_expr
->X_add_number
);
695 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
697 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
699 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
700 bfd_get_reloc_size (howto
),
701 address_expr
, FALSE
, reloc_type
);
703 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
711 /* Build an instruction created by a macro expansion. This is passed
712 a pointer to the count of instructions created so far, an
713 expression, the name of the instruction to build, an operand format
714 string, and corresponding arguments. */
717 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
719 const struct riscv_opcode
*mo
;
720 struct riscv_cl_insn insn
;
721 bfd_reloc_code_real_type r
;
724 va_start (args
, fmt
);
726 r
= BFD_RELOC_UNUSED
;
727 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
730 /* Find a non-RVC variant of the instruction. append_insn will compress
732 while (riscv_insn_length (mo
->match
) < 4)
734 gas_assert (strcmp (name
, mo
->name
) == 0);
736 create_insn (&insn
, mo
);
742 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
746 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
750 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
754 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
760 gas_assert (ep
!= NULL
);
761 r
= va_arg (args
, int);
769 as_fatal (_("internal error: invalid macro"));
774 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
776 append_insn (&insn
, ep
, r
);
779 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
782 normalize_constant_expr (expressionS
*ex
)
786 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
787 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
788 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
792 /* Fail if an expression is not a constant. */
795 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
797 if (ex
->X_op
== O_big
)
798 as_bad (_("unsupported large constant"));
799 else if (ex
->X_op
!= O_constant
)
800 as_bad (_("Instruction %s requires absolute expression"),
802 normalize_constant_expr (ex
);
806 make_internal_label (void)
808 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
809 (valueT
) frag_now_fix (), frag_now
);
812 /* Load an entry from the GOT. */
814 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
815 const char *lo_insn
, const char *lo_pattern
,
816 bfd_reloc_code_real_type hi_reloc
,
817 bfd_reloc_code_real_type lo_reloc
)
821 ep2
.X_add_symbol
= make_internal_label ();
822 ep2
.X_add_number
= 0;
824 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
825 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
829 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
830 bfd_reloc_code_real_type hi_reloc
,
831 bfd_reloc_code_real_type lo_reloc
)
833 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
837 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
838 bfd_reloc_code_real_type hi_reloc
,
839 bfd_reloc_code_real_type lo_reloc
)
841 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
844 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
846 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
847 bfd_reloc_code_real_type reloc
)
849 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
850 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
853 /* Load an integer constant into a register. */
856 load_const (int reg
, expressionS
*ep
)
858 int shift
= RISCV_IMM_BITS
;
859 expressionS upper
= *ep
, lower
= *ep
;
860 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
861 upper
.X_add_number
-= lower
.X_add_number
;
863 if (ep
->X_op
!= O_constant
)
865 as_bad (_("unsupported large constant"));
869 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
871 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
872 while (((upper
.X_add_number
>> shift
) & 1) == 0)
875 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
876 load_const (reg
, &upper
);
878 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
879 if (lower
.X_add_number
!= 0)
880 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
884 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
887 if (upper
.X_add_number
!= 0)
889 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
893 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
894 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
895 BFD_RELOC_RISCV_LO12_I
);
899 /* Expand RISC-V assembly macros into one or more instructions. */
901 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
902 bfd_reloc_code_real_type
*imm_reloc
)
904 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
905 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
906 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
907 int mask
= ip
->insn_mo
->mask
;
912 load_const (rd
, imm_expr
);
917 /* Load the address of a symbol into a register. */
918 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
919 as_bad (_("offset too large"));
921 if (imm_expr
->X_op
== O_constant
)
922 load_const (rd
, imm_expr
);
923 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
924 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
925 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
926 else /* Local PIC symbol, or any non-PIC symbol */
927 pcrel_load (rd
, rd
, imm_expr
, "addi",
928 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
932 pcrel_load (rd
, rd
, imm_expr
, "addi",
933 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
937 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
938 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
942 pcrel_load (rd
, rd
, imm_expr
, "lb",
943 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
947 pcrel_load (rd
, rd
, imm_expr
, "lbu",
948 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
952 pcrel_load (rd
, rd
, imm_expr
, "lh",
953 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
957 pcrel_load (rd
, rd
, imm_expr
, "lhu",
958 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
962 pcrel_load (rd
, rd
, imm_expr
, "lw",
963 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
967 pcrel_load (rd
, rd
, imm_expr
, "lwu",
968 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
972 pcrel_load (rd
, rd
, imm_expr
, "ld",
973 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
977 pcrel_load (rd
, rs1
, imm_expr
, "flw",
978 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
982 pcrel_load (rd
, rs1
, imm_expr
, "fld",
983 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
987 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
988 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
992 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
993 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
997 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
998 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1002 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1003 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1007 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1008 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1012 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1013 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1017 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1021 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1026 static const struct percent_op_match percent_op_utype
[] =
1028 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1029 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1030 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1031 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1032 {"%hi", BFD_RELOC_RISCV_HI20
},
1036 static const struct percent_op_match percent_op_itype
[] =
1038 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1039 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1040 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1044 static const struct percent_op_match percent_op_stype
[] =
1046 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1047 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1048 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1052 static const struct percent_op_match percent_op_rtype
[] =
1054 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1058 /* Return true if *STR points to a relocation operator. When returning true,
1059 move *STR over the operator and store its relocation code in *RELOC.
1060 Leave both *STR and *RELOC alone when returning false. */
1063 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1064 const struct percent_op_match
*percent_op
)
1066 for ( ; percent_op
->str
; percent_op
++)
1067 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1069 int len
= strlen (percent_op
->str
);
1071 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1074 *str
+= strlen (percent_op
->str
);
1075 *reloc
= percent_op
->reloc
;
1077 /* Check whether the output BFD supports this relocation.
1078 If not, issue an error and fall back on something safe. */
1079 if (*reloc
!= BFD_RELOC_UNUSED
1080 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1082 as_bad ("relocation %s isn't supported by the current ABI",
1084 *reloc
= BFD_RELOC_UNUSED
;
1092 my_getExpression (expressionS
*ep
, char *str
)
1096 save_in
= input_line_pointer
;
1097 input_line_pointer
= str
;
1099 expr_end
= input_line_pointer
;
1100 input_line_pointer
= save_in
;
1103 /* Parse string STR as a 16-bit relocatable operand. Store the
1104 expression in *EP and the relocation, if any, in RELOC.
1105 Return the number of relocation operators used (0 or 1).
1107 On exit, EXPR_END points to the first character after the expression. */
1110 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1111 char *str
, const struct percent_op_match
*percent_op
)
1114 unsigned crux_depth
, str_depth
, regno
;
1117 /* First, check for integer registers. */
1118 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1120 ep
->X_op
= O_register
;
1121 ep
->X_add_number
= regno
;
1125 /* Search for the start of the main expression.
1126 End the loop with CRUX pointing to the start
1127 of the main expression and with CRUX_DEPTH containing the number
1128 of open brackets at that point. */
1135 crux_depth
= str_depth
;
1137 /* Skip over whitespace and brackets, keeping count of the number
1139 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1145 && parse_relocation (&str
, reloc
, percent_op
));
1147 my_getExpression (ep
, crux
);
1150 /* Match every open bracket. */
1151 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1156 as_bad ("unclosed '('");
1163 /* This routine assembles an instruction into its binary format. As a
1164 side effect, it sets the global variable imm_reloc to the type of
1165 relocation to do if one of the operands is an address expression. */
1168 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1169 bfd_reloc_code_real_type
*imm_reloc
)
1174 struct riscv_opcode
*insn
;
1179 const struct percent_op_match
*p
;
1180 const char *error
= "unrecognized opcode";
1182 /* Parse the name of the instruction. Terminate the string if whitespace
1183 is found so that hash_find only sees the name part of the string. */
1184 for (s
= str
; *s
!= '\0'; ++s
)
1192 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1195 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1197 if (!riscv_subset_supports (insn
->subset
))
1200 create_insn (ip
, insn
);
1203 imm_expr
->X_op
= O_absent
;
1204 *imm_reloc
= BFD_RELOC_UNUSED
;
1205 p
= percent_op_itype
;
1207 for (args
= insn
->args
;; ++args
)
1209 s
+= strspn (s
, " \t");
1212 case '\0': /* End of args. */
1213 if (insn
->pinfo
!= INSN_MACRO
)
1215 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1217 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1222 /* Successful assembly. */
1229 case 's': /* RS1 x8-x15 */
1230 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1231 || !(regno
>= 8 && regno
<= 15))
1233 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1235 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1236 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1237 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1240 case 't': /* RS2 x8-x15 */
1241 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1242 || !(regno
>= 8 && regno
<= 15))
1244 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1246 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1247 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1248 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1251 case 'U': /* RS1, constrained to equal RD. */
1252 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1253 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1257 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1259 INSERT_OPERAND (CRS2
, *ip
, regno
);
1261 case 'c': /* RS1, constrained to equal sp. */
1262 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1267 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1268 || imm_expr
->X_op
!= O_constant
1269 || imm_expr
->X_add_number
<= 0
1270 || imm_expr
->X_add_number
>= 64)
1272 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1275 imm_expr
->X_op
= O_absent
;
1278 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1279 || imm_expr
->X_op
!= O_constant
1280 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1281 || imm_expr
->X_add_number
<= 0
1282 || imm_expr
->X_add_number
>= 32)
1284 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1287 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1288 || imm_expr
->X_op
!= O_constant
1289 || imm_expr
->X_add_number
== 0
1290 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1292 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1295 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1296 || imm_expr
->X_op
!= O_constant
1297 || imm_expr
->X_add_number
== 0
1298 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1300 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1303 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1304 || imm_expr
->X_op
!= O_constant
1305 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1307 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1310 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1311 || imm_expr
->X_op
!= O_constant
1312 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1314 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1317 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1318 || imm_expr
->X_op
!= O_constant
1319 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1322 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1325 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1326 || imm_expr
->X_op
!= O_constant
1327 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1330 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1333 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1334 || imm_expr
->X_op
!= O_constant
1335 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1336 || imm_expr
->X_add_number
== 0)
1339 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1342 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1343 || imm_expr
->X_op
!= O_constant
1344 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1345 || imm_expr
->X_add_number
== 0)
1348 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1351 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1352 || imm_expr
->X_op
!= O_constant
1353 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1356 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1359 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1360 || imm_expr
->X_op
!= O_constant
1361 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1364 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1367 p
= percent_op_utype
;
1368 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1371 if (imm_expr
->X_op
!= O_constant
1372 || imm_expr
->X_add_number
<= 0
1373 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1374 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1375 && (imm_expr
->X_add_number
<
1376 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1378 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1381 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1382 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1383 || ((int32_t)imm_expr
->X_add_number
1384 != imm_expr
->X_add_number
))
1386 imm_expr
->X_add_number
=
1387 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1393 case 'D': /* Floating-point RS2 x8-x15. */
1394 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1395 || !(regno
>= 8 && regno
<= 15))
1397 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1399 case 'T': /* Floating-point RS2. */
1400 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1402 INSERT_OPERAND (CRS2
, *ip
, regno
);
1405 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1424 case '<': /* Shift amount, 0 - 31. */
1425 my_getExpression (imm_expr
, s
);
1426 check_absolute_expr (ip
, imm_expr
);
1427 if ((unsigned long) imm_expr
->X_add_number
> 31)
1428 as_warn (_("Improper shift amount (%lu)"),
1429 (unsigned long) imm_expr
->X_add_number
);
1430 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1431 imm_expr
->X_op
= O_absent
;
1435 case '>': /* Shift amount, 0 - (XLEN-1). */
1436 my_getExpression (imm_expr
, s
);
1437 check_absolute_expr (ip
, imm_expr
);
1438 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1439 as_warn (_("Improper shift amount (%lu)"),
1440 (unsigned long) imm_expr
->X_add_number
);
1441 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1442 imm_expr
->X_op
= O_absent
;
1446 case 'Z': /* CSRRxI immediate. */
1447 my_getExpression (imm_expr
, s
);
1448 check_absolute_expr (ip
, imm_expr
);
1449 if ((unsigned long) imm_expr
->X_add_number
> 31)
1450 as_warn (_("Improper CSRxI immediate (%lu)"),
1451 (unsigned long) imm_expr
->X_add_number
);
1452 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1453 imm_expr
->X_op
= O_absent
;
1457 case 'E': /* Control register. */
1458 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1459 INSERT_OPERAND (CSR
, *ip
, regno
);
1462 my_getExpression (imm_expr
, s
);
1463 check_absolute_expr (ip
, imm_expr
);
1464 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1465 as_warn (_("Improper CSR address (%lu)"),
1466 (unsigned long) imm_expr
->X_add_number
);
1467 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1468 imm_expr
->X_op
= O_absent
;
1473 case 'm': /* Rounding mode. */
1474 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1476 INSERT_OPERAND (RM
, *ip
, regno
);
1482 case 'Q': /* Fence predecessor/successor. */
1483 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1487 INSERT_OPERAND (PRED
, *ip
, regno
);
1489 INSERT_OPERAND (SUCC
, *ip
, regno
);
1494 case 'd': /* Destination register. */
1495 case 's': /* Source register. */
1496 case 't': /* Target register. */
1497 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1503 /* Now that we have assembled one operand, we use the args
1504 string to figure out where it goes in the instruction. */
1508 INSERT_OPERAND (RS1
, *ip
, regno
);
1511 INSERT_OPERAND (RD
, *ip
, regno
);
1514 INSERT_OPERAND (RS2
, *ip
, regno
);
1521 case 'D': /* Floating point rd. */
1522 case 'S': /* Floating point rs1. */
1523 case 'T': /* Floating point rs2. */
1524 case 'U': /* Floating point rs1 and rs2. */
1525 case 'R': /* Floating point rs3. */
1526 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1534 INSERT_OPERAND (RD
, *ip
, regno
);
1537 INSERT_OPERAND (RS1
, *ip
, regno
);
1540 INSERT_OPERAND (RS1
, *ip
, regno
);
1543 INSERT_OPERAND (RS2
, *ip
, regno
);
1546 INSERT_OPERAND (RS3
, *ip
, regno
);
1555 my_getExpression (imm_expr
, s
);
1556 if (imm_expr
->X_op
!= O_big
1557 && imm_expr
->X_op
!= O_constant
)
1559 normalize_constant_expr (imm_expr
);
1564 my_getExpression (imm_expr
, s
);
1565 normalize_constant_expr (imm_expr
);
1566 /* The 'A' format specifier must be a symbol. */
1567 if (imm_expr
->X_op
!= O_symbol
)
1569 *imm_reloc
= BFD_RELOC_32
;
1573 case 'j': /* Sign-extended immediate. */
1574 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1575 p
= percent_op_itype
;
1577 case 'q': /* Store displacement. */
1578 p
= percent_op_stype
;
1579 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1581 case 'o': /* Load displacement. */
1582 p
= percent_op_itype
;
1583 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1585 case '0': /* AMO "displacement," which must be zero. */
1586 p
= percent_op_rtype
;
1587 *imm_reloc
= BFD_RELOC_UNUSED
;
1589 /* Check whether there is only a single bracketed expression
1590 left. If so, it must be the base register and the
1591 constant must be zero. */
1592 imm_expr
->X_op
= O_constant
;
1593 imm_expr
->X_add_number
= 0;
1594 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1597 /* If this value won't fit into a 16 bit offset, then go
1598 find a macro that will generate the 32 bit offset
1600 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1602 normalize_constant_expr (imm_expr
);
1603 if (imm_expr
->X_op
!= O_constant
1604 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1605 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1606 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1613 case 'p': /* PC-relative offset. */
1615 *imm_reloc
= BFD_RELOC_12_PCREL
;
1616 my_getExpression (imm_expr
, s
);
1620 case 'u': /* Upper 20 bits. */
1621 p
= percent_op_utype
;
1622 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1623 && imm_expr
->X_op
== O_constant
)
1625 if (imm_expr
->X_add_number
< 0
1626 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1627 as_bad (_("lui expression not in range 0..1048575"));
1629 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1630 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1635 case 'a': /* 20-bit PC-relative offset. */
1637 my_getExpression (imm_expr
, s
);
1639 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1643 my_getExpression (imm_expr
, s
);
1645 if (strcmp (s
, "@plt") == 0)
1647 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1651 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1655 as_fatal (_("internal error: bad argument type %c"), *args
);
1660 error
= _("illegal operands");
1664 /* Restore the character we might have clobbered above. */
1666 *(argsStart
- 1) = save_c
;
1672 md_assemble (char *str
)
1674 struct riscv_cl_insn insn
;
1675 expressionS imm_expr
;
1676 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1678 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1682 as_bad ("%s `%s'", error
, str
);
1686 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1687 macro (&insn
, &imm_expr
, &imm_reloc
);
1689 append_insn (&insn
, &imm_expr
, imm_reloc
);
1693 md_atof (int type
, char *litP
, int *sizeP
)
1695 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1699 md_number_to_chars (char *buf
, valueT val
, int n
)
1701 number_to_chars_littleendian (buf
, val
, n
);
1704 const char *md_shortopts
= "O::g::G:";
1708 OPTION_MARCH
= OPTION_MD_BASE
,
1715 struct option md_longopts
[] =
1717 {"march", required_argument
, NULL
, OPTION_MARCH
},
1718 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1719 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1720 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1721 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1723 {NULL
, no_argument
, NULL
, 0}
1725 size_t md_longopts_size
= sizeof (md_longopts
);
1728 FLOAT_ABI_DEFAULT
= -1,
1734 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1737 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1739 abi_xlen
= new_xlen
;
1740 float_abi
= new_float_abi
;
1744 md_parse_option (int c
, const char *arg
)
1749 riscv_set_arch (arg
);
1753 riscv_opts
.pic
= FALSE
;
1757 riscv_opts
.pic
= TRUE
;
1761 if (strcmp (arg
, "ilp32") == 0)
1762 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1763 else if (strcmp (arg
, "ilp32f") == 0)
1764 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1765 else if (strcmp (arg
, "ilp32d") == 0)
1766 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1767 else if (strcmp (arg
, "ilp32q") == 0)
1768 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1769 else if (strcmp (arg
, "lp64") == 0)
1770 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1771 else if (strcmp (arg
, "lp64f") == 0)
1772 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1773 else if (strcmp (arg
, "lp64d") == 0)
1774 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1775 else if (strcmp (arg
, "lp64q") == 0)
1776 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1789 riscv_after_parse_args (void)
1793 if (strcmp (default_arch
, "riscv32") == 0)
1795 else if (strcmp (default_arch
, "riscv64") == 0)
1798 as_bad ("unknown default architecture `%s'", default_arch
);
1801 if (riscv_subsets
== NULL
)
1802 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1804 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1805 if (riscv_subset_supports ("c"))
1806 riscv_set_rvc (TRUE
);
1808 riscv_add_subset ("c");
1810 /* Infer ABI from ISA if not specified on command line. */
1813 else if (abi_xlen
> xlen
)
1814 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1815 else if (abi_xlen
< xlen
)
1816 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1818 if (float_abi
== FLOAT_ABI_DEFAULT
)
1820 struct riscv_subset
*subset
;
1822 /* Assume soft-float unless D extension is present. */
1823 float_abi
= FLOAT_ABI_SOFT
;
1825 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1827 if (strcasecmp (subset
->name
, "D") == 0)
1828 float_abi
= FLOAT_ABI_DOUBLE
;
1829 if (strcasecmp (subset
->name
, "Q") == 0)
1830 float_abi
= FLOAT_ABI_QUAD
;
1834 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1835 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1839 md_pcrel_from (fixS
*fixP
)
1841 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1844 /* Apply a fixup to the object file. */
1847 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1849 unsigned int subtype
;
1850 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1851 bfd_boolean relaxable
= FALSE
;
1853 /* Remember value for tc_gen_reloc. */
1854 fixP
->fx_addnumber
= *valP
;
1856 switch (fixP
->fx_r_type
)
1858 case BFD_RELOC_RISCV_HI20
:
1859 case BFD_RELOC_RISCV_LO12_I
:
1860 case BFD_RELOC_RISCV_LO12_S
:
1861 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1862 | bfd_getl32 (buf
), buf
);
1866 case BFD_RELOC_RISCV_GOT_HI20
:
1867 case BFD_RELOC_RISCV_PCREL_HI20
:
1868 case BFD_RELOC_RISCV_ADD8
:
1869 case BFD_RELOC_RISCV_ADD16
:
1870 case BFD_RELOC_RISCV_ADD32
:
1871 case BFD_RELOC_RISCV_ADD64
:
1872 case BFD_RELOC_RISCV_SUB6
:
1873 case BFD_RELOC_RISCV_SUB8
:
1874 case BFD_RELOC_RISCV_SUB16
:
1875 case BFD_RELOC_RISCV_SUB32
:
1876 case BFD_RELOC_RISCV_SUB64
:
1877 case BFD_RELOC_RISCV_RELAX
:
1880 case BFD_RELOC_RISCV_TPREL_HI20
:
1881 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1882 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1883 case BFD_RELOC_RISCV_TPREL_ADD
:
1887 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1888 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1889 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1890 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1891 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1898 case BFD_RELOC_RISCV_CFA
:
1899 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1901 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1902 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1903 fixP
->fx_next
->fx_subsy
= NULL
;
1904 fixP
->fx_next
->fx_offset
= 0;
1905 fixP
->fx_subsy
= NULL
;
1907 switch (fixP
->fx_r_type
)
1910 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1911 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
1915 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
1916 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1920 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
1921 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1925 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
1926 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1929 case BFD_RELOC_RISCV_CFA
:
1930 /* Load the byte to get the subtype. */
1931 subtype
= bfd_get_8 (NULL
, &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
]);
1934 case DW_CFA_advance_loc1
:
1936 fixP
->fx_next
->fx_where
++;
1937 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
1938 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1941 case DW_CFA_advance_loc2
:
1944 fixP
->fx_next
->fx_size
= 2;
1945 fixP
->fx_next
->fx_where
++;
1946 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
1947 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1950 case DW_CFA_advance_loc4
:
1953 fixP
->fx_next
->fx_size
= 4;
1954 fixP
->fx_next
->fx_where
++;
1955 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
1956 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1960 if (subtype
< 0x80 && (subtype
& 0x40))
1962 /* DW_CFA_advance_loc */
1963 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
1964 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
1967 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
1973 /* This case is unreachable. */
1980 /* If we are deleting this reloc entry, we must fill in the
1981 value now. This can happen if we have a .word which is not
1982 resolved when it appears but is later defined. */
1983 if (fixP
->fx_addsy
== NULL
)
1985 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
1986 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
1991 case BFD_RELOC_RISCV_JMP
:
1994 /* Fill in a tentative value to improve objdump readability. */
1995 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
1996 bfd_vma delta
= target
- md_pcrel_from (fixP
);
1997 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2001 case BFD_RELOC_12_PCREL
:
2004 /* Fill in a tentative value to improve objdump readability. */
2005 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2006 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2007 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2011 case BFD_RELOC_RISCV_RVC_BRANCH
:
2014 /* Fill in a tentative value to improve objdump readability. */
2015 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2016 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2017 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2021 case BFD_RELOC_RISCV_RVC_JUMP
:
2024 /* Fill in a tentative value to improve objdump readability. */
2025 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2026 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2027 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2031 case BFD_RELOC_RISCV_CALL
:
2032 case BFD_RELOC_RISCV_CALL_PLT
:
2036 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2037 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2038 case BFD_RELOC_RISCV_ALIGN
:
2042 /* We ignore generic BFD relocations we don't know about. */
2043 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2044 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2047 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2048 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2050 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2051 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2052 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2056 /* Because the value of .cfi_remember_state may changed after relaxation,
2057 we insert a fix to relocate it again in link-time. */
2060 riscv_pre_output_hook (void)
2062 const frchainS
*frch
;
2065 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2066 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2070 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2072 if (frag
->fr_type
== rs_cfa
)
2077 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2078 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2080 exp
.X_op
= O_subtract
;
2081 exp
.X_add_symbol
= add_symbol
;
2082 exp
.X_add_number
= 0;
2083 exp
.X_op_symbol
= op_symbol
;
2085 loc4_frag
= (fragS
*) frag
->fr_opcode
;
2086 fix_new_exp (loc4_frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2087 BFD_RELOC_RISCV_CFA
);
2094 /* This structure is used to hold a stack of .option values. */
2096 struct riscv_option_stack
2098 struct riscv_option_stack
*next
;
2099 struct riscv_set_options options
;
2102 static struct riscv_option_stack
*riscv_opts_stack
;
2104 /* Handle the .option pseudo-op. */
2107 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2109 char *name
= input_line_pointer
, ch
;
2111 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2112 ++input_line_pointer
;
2113 ch
= *input_line_pointer
;
2114 *input_line_pointer
= '\0';
2116 if (strcmp (name
, "rvc") == 0)
2117 riscv_set_rvc (TRUE
);
2118 else if (strcmp (name
, "norvc") == 0)
2119 riscv_set_rvc (FALSE
);
2120 else if (strcmp (name
, "pic") == 0)
2121 riscv_opts
.pic
= TRUE
;
2122 else if (strcmp (name
, "nopic") == 0)
2123 riscv_opts
.pic
= FALSE
;
2124 else if (strcmp (name
, "relax") == 0)
2125 riscv_opts
.relax
= TRUE
;
2126 else if (strcmp (name
, "norelax") == 0)
2127 riscv_opts
.relax
= FALSE
;
2128 else if (strcmp (name
, "push") == 0)
2130 struct riscv_option_stack
*s
;
2132 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2133 s
->next
= riscv_opts_stack
;
2134 s
->options
= riscv_opts
;
2135 riscv_opts_stack
= s
;
2137 else if (strcmp (name
, "pop") == 0)
2139 struct riscv_option_stack
*s
;
2141 s
= riscv_opts_stack
;
2143 as_bad (_(".option pop with no .option push"));
2146 riscv_opts
= s
->options
;
2147 riscv_opts_stack
= s
->next
;
2153 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2155 *input_line_pointer
= ch
;
2156 demand_empty_rest_of_line ();
2159 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2160 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2161 use in DWARF debug information. */
2164 s_dtprel (int bytes
)
2171 if (ex
.X_op
!= O_symbol
)
2173 as_bad (_("Unsupported use of %s"), (bytes
== 8
2176 ignore_rest_of_line ();
2179 p
= frag_more (bytes
);
2180 md_number_to_chars (p
, 0, bytes
);
2181 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2183 ? BFD_RELOC_RISCV_TLS_DTPREL64
2184 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2186 demand_empty_rest_of_line ();
2189 /* Handle the .bss pseudo-op. */
2192 s_bss (int ignore ATTRIBUTE_UNUSED
)
2194 subseg_set (bss_section
, 0);
2195 demand_empty_rest_of_line ();
2199 riscv_make_nops (char *buf
, bfd_vma bytes
)
2203 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2204 means we are not within a valid instruction sequence. It is thus safe
2205 to use a zero byte, even though that is not a valid instruction. */
2209 /* Use at most one 2-byte NOP. */
2210 if ((bytes
- i
) % 4 == 2)
2212 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2216 /* Fill the remainder with 4-byte NOPs. */
2217 for ( ; i
< bytes
; i
+= 4)
2218 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2221 /* Called from md_do_align. Used to create an alignment frag in a
2222 code section by emitting a worst-case NOP sequence that the linker
2223 will later relax to the correct number of NOPs. We can't compute
2224 the correct alignment now because of other linker relaxations. */
2227 riscv_frag_align_code (int n
)
2229 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2230 bfd_vma min_text_alignment_order
= riscv_opts
.rvc
? 1 : 2;
2231 bfd_vma min_text_alignment
= (bfd_vma
) 1 << min_text_alignment_order
;
2233 /* First, get back to minimal alignment. */
2234 frag_align_code (min_text_alignment_order
, 0);
2236 /* When not relaxing, riscv_handle_align handles code alignment. */
2237 if (!riscv_opts
.relax
)
2240 if (bytes
> min_text_alignment
)
2242 bfd_vma worst_case_bytes
= bytes
- min_text_alignment
;
2243 char *nops
= frag_more (worst_case_bytes
);
2246 ex
.X_op
= O_constant
;
2247 ex
.X_add_number
= worst_case_bytes
;
2249 riscv_make_nops (nops
, worst_case_bytes
);
2251 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2252 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2258 /* Implement HANDLE_ALIGN. */
2261 riscv_handle_align (fragS
*fragP
)
2263 switch (fragP
->fr_type
)
2266 /* When relaxing, riscv_frag_align_code handles code alignment. */
2267 if (!riscv_opts
.relax
)
2269 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2270 - fragP
->fr_address
- fragP
->fr_fix
;
2275 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2276 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2277 fragP
->fr_var
= count
;
2287 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2289 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2292 /* Translate internal representation of relocation info to BFD target
2296 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2298 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2300 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2301 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2302 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2303 reloc
->addend
= fixp
->fx_addnumber
;
2305 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2306 if (reloc
->howto
== NULL
)
2308 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2309 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2311 /* We don't have R_RISCV_8/16, but for this special case,
2312 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2316 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2317 _("cannot represent %s relocation in object file"),
2318 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2326 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2328 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2330 offsetT old_var
= fragp
->fr_var
;
2331 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2332 return fragp
->fr_var
- old_var
;
2338 /* Expand far branches to multi-instruction sequences. */
2341 md_convert_frag_branch (fragS
*fragp
)
2349 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2351 exp
.X_op
= O_symbol
;
2352 exp
.X_add_symbol
= fragp
->fr_symbol
;
2353 exp
.X_add_number
= fragp
->fr_offset
;
2355 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2357 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2359 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2363 /* Expand the RVC branch into a RISC-V one. */
2364 insn
= bfd_getl16 (buf
);
2365 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2366 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2368 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2369 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2370 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2371 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2372 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2373 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2376 bfd_putl32 (insn
, buf
);
2380 /* Invert the branch condition. Branch over the jump. */
2381 insn
= bfd_getl16 (buf
);
2382 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2383 insn
|= ENCODE_RVC_B_IMM (6);
2384 bfd_putl16 (insn
, buf
);
2389 /* Just keep the RVC branch. */
2390 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2391 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2392 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2393 2, &exp
, FALSE
, reloc
);
2402 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2405 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2407 /* Invert the branch condition. Branch over the jump. */
2408 insn
= bfd_getl32 (buf
);
2409 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2410 insn
|= ENCODE_SBTYPE_IMM (8);
2411 md_number_to_chars ((char *) buf
, insn
, 4);
2415 /* Jump to the target. */
2416 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2417 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2418 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2423 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2424 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2425 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2426 4, &exp
, FALSE
, reloc
);
2435 fixp
->fx_file
= fragp
->fr_file
;
2436 fixp
->fx_line
= fragp
->fr_line
;
2438 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2439 + fragp
->fr_fix
+ fragp
->fr_var
);
2441 fragp
->fr_fix
+= fragp
->fr_var
;
2444 /* Relax a machine dependent frag. This returns the amount by which
2445 the current size of the frag should change. */
2448 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2451 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2452 md_convert_frag_branch (fragp
);
2456 md_show_usage (FILE *stream
)
2458 fprintf (stream
, _("\
2460 -m32 assemble RV32 code\n\
2461 -m64 assemble RV64 code (default)\n\
2462 -fpic generate position-independent code\n\
2463 -fno-pic don't generate position-independent code (default)\n\
2464 -msoft-float don't use F registers for floating-point values\n\
2465 -mhard-float use F registers for floating-point values (default)\n\
2466 -mno-rvc disable the C extension for compressed instructions (default)\n\
2467 -mrvc enable the C extension for compressed instructions\n\
2468 -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
2472 /* Standard calling conventions leave the CFA at SP on entry. */
2474 riscv_cfi_frame_initial_instructions (void)
2476 cfi_add_CFA_def_cfa_register (X_SP
);
2480 tc_riscv_regname_to_dw2regnum (char *regname
)
2484 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2487 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2490 as_bad (_("unknown register `%s'"), regname
);
2495 riscv_elf_final_processing (void)
2497 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2500 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2501 since these directives break relaxation when used with symbol deltas. */
2504 s_riscv_leb128 (int sign
)
2507 char *save_in
= input_line_pointer
;
2510 if (exp
.X_op
!= O_constant
)
2511 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2512 demand_empty_rest_of_line ();
2514 input_line_pointer
= save_in
;
2515 return s_leb128 (sign
);
2518 /* Pseudo-op table. */
2520 static const pseudo_typeS riscv_pseudo_table
[] =
2522 /* RISC-V-specific pseudo-ops. */
2523 {"option", s_riscv_option
, 0},
2527 {"dtprelword", s_dtprel
, 4},
2528 {"dtpreldword", s_dtprel
, 8},
2530 {"uleb128", s_riscv_leb128
, 0},
2531 {"sleb128", s_riscv_leb128
, 1},
2537 riscv_pop_insert (void)
2539 extern void pop_insert (const pseudo_typeS
*);
2541 pop_insert (riscv_pseudo_table
);