1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
364 unsigned char operator;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
389 directive_literal_prefix
,
391 directive_absolute_literals
,
392 directive_last_directive
398 bfd_boolean can_be_negated
;
401 const directive_infoS directive_info
[] =
404 { "literal", FALSE
},
406 { "transform", TRUE
},
407 { "freeregs", FALSE
},
408 { "longcalls", TRUE
},
409 { "literal_prefix", FALSE
},
410 { "schedule", TRUE
},
411 { "absolute-literals", TRUE
}
414 bfd_boolean directive_state
[] =
418 #if !XCHAL_HAVE_DENSITY
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 #if XSHAL_USE_ABSOLUTE_LITERALS
429 TRUE
/* absolute_literals */
431 FALSE
/* absolute_literals */
436 /* Directive functions. */
438 static void xtensa_begin_directive (int);
439 static void xtensa_end_directive (int);
440 static void xtensa_literal_prefix (void);
441 static void xtensa_literal_position (int);
442 static void xtensa_literal_pseudo (int);
443 static void xtensa_frequency_pseudo (int);
444 static void xtensa_elf_cons (int);
446 /* Parsing and Idiom Translation. */
448 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
450 /* Various Other Internal Functions. */
452 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
453 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
454 static void xtensa_mark_literal_pool_location (void);
455 static addressT
get_expanded_loop_offset (xtensa_opcode
);
456 static fragS
*get_literal_pool_location (segT
);
457 static void set_literal_pool_location (segT
, fragS
*);
458 static void xtensa_set_frag_assembly_state (fragS
*);
459 static void finish_vinsn (vliw_insn
*);
460 static bfd_boolean
emit_single_op (TInsn
*);
461 static int total_frag_text_expansion (fragS
*);
463 /* Alignment Functions. */
465 static int get_text_align_power (unsigned);
466 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
467 static int branch_align_power (segT
);
469 /* Helpers for xtensa_relax_frag(). */
471 static long relax_frag_add_nop (fragS
*);
473 /* Accessors for additional per-subsegment information. */
475 static unsigned get_last_insn_flags (segT
, subsegT
);
476 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
477 static float get_subseg_total_freq (segT
, subsegT
);
478 static float get_subseg_target_freq (segT
, subsegT
);
479 static void set_subseg_freq (segT
, subsegT
, float, float);
481 /* Segment list functions. */
483 static void xtensa_move_literals (void);
484 static void xtensa_reorder_segments (void);
485 static void xtensa_switch_to_literal_fragment (emit_state
*);
486 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
487 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
488 static void xtensa_restore_emit_state (emit_state
*);
489 static segT
cache_literal_section (bfd_boolean
);
491 /* Import from elf32-xtensa.c in BFD library. */
493 extern asection
*xtensa_get_property_section (asection
*, const char *);
495 /* op_placement_info functions. */
497 static void init_op_placement_info_table (void);
498 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
499 static int xg_get_single_size (xtensa_opcode
);
500 static xtensa_format
xg_get_single_format (xtensa_opcode
);
501 static int xg_get_single_slot (xtensa_opcode
);
503 /* TInsn and IStack functions. */
505 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
506 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
507 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
508 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
509 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
510 static void tinsn_from_chars (TInsn
*, char *, int);
511 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
512 static int get_num_stack_text_bytes (IStack
*);
513 static int get_num_stack_literal_bytes (IStack
*);
515 /* vliw_insn functions. */
517 static void xg_init_vinsn (vliw_insn
*);
518 static void xg_clear_vinsn (vliw_insn
*);
519 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
520 static void xg_free_vinsn (vliw_insn
*);
521 static bfd_boolean vinsn_to_insnbuf
522 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
523 static void vinsn_from_chars (vliw_insn
*, char *);
525 /* Expression Utilities. */
527 bfd_boolean
expr_is_const (const expressionS
*);
528 offsetT
get_expr_const (const expressionS
*);
529 void set_expr_const (expressionS
*, offsetT
);
530 bfd_boolean
expr_is_register (const expressionS
*);
531 offsetT
get_expr_register (const expressionS
*);
532 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
533 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
534 static void copy_expr (expressionS
*, const expressionS
*);
536 /* Section renaming. */
538 static void build_section_rename (const char *);
541 /* ISA imported from bfd. */
542 extern xtensa_isa xtensa_default_isa
;
544 extern int target_big_endian
;
546 static xtensa_opcode xtensa_addi_opcode
;
547 static xtensa_opcode xtensa_addmi_opcode
;
548 static xtensa_opcode xtensa_call0_opcode
;
549 static xtensa_opcode xtensa_call4_opcode
;
550 static xtensa_opcode xtensa_call8_opcode
;
551 static xtensa_opcode xtensa_call12_opcode
;
552 static xtensa_opcode xtensa_callx0_opcode
;
553 static xtensa_opcode xtensa_callx4_opcode
;
554 static xtensa_opcode xtensa_callx8_opcode
;
555 static xtensa_opcode xtensa_callx12_opcode
;
556 static xtensa_opcode xtensa_const16_opcode
;
557 static xtensa_opcode xtensa_entry_opcode
;
558 static xtensa_opcode xtensa_extui_opcode
;
559 static xtensa_opcode xtensa_movi_opcode
;
560 static xtensa_opcode xtensa_movi_n_opcode
;
561 static xtensa_opcode xtensa_isync_opcode
;
562 static xtensa_opcode xtensa_jx_opcode
;
563 static xtensa_opcode xtensa_l32r_opcode
;
564 static xtensa_opcode xtensa_loop_opcode
;
565 static xtensa_opcode xtensa_loopnez_opcode
;
566 static xtensa_opcode xtensa_loopgtz_opcode
;
567 static xtensa_opcode xtensa_nop_opcode
;
568 static xtensa_opcode xtensa_nop_n_opcode
;
569 static xtensa_opcode xtensa_or_opcode
;
570 static xtensa_opcode xtensa_ret_opcode
;
571 static xtensa_opcode xtensa_ret_n_opcode
;
572 static xtensa_opcode xtensa_retw_opcode
;
573 static xtensa_opcode xtensa_retw_n_opcode
;
574 static xtensa_opcode xtensa_rsr_lcount_opcode
;
575 static xtensa_opcode xtensa_waiti_opcode
;
578 /* Command-line Options. */
580 bfd_boolean use_literal_section
= TRUE
;
581 static bfd_boolean align_targets
= TRUE
;
582 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
583 static bfd_boolean has_a0_b_retw
= FALSE
;
584 static bfd_boolean workaround_a0_b_retw
= FALSE
;
585 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
586 static bfd_boolean workaround_short_loop
= FALSE
;
587 static bfd_boolean maybe_has_short_loop
= FALSE
;
588 static bfd_boolean workaround_close_loop_end
= FALSE
;
589 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
590 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
592 /* When workaround_short_loops is TRUE, all loops with early exits must
593 have at least 3 instructions. workaround_all_short_loops is a modifier
594 to the workaround_short_loop flag. In addition to the
595 workaround_short_loop actions, all straightline loopgtz and loopnez
596 must have at least 3 instructions. */
598 static bfd_boolean workaround_all_short_loops
= FALSE
;
602 xtensa_setup_hw_workarounds (int earliest
, int latest
)
604 if (earliest
> latest
)
605 as_fatal (_("illegal range of target hardware versions"));
607 /* Enable all workarounds for pre-T1050.0 hardware. */
608 if (earliest
< 105000 || latest
< 105000)
610 workaround_a0_b_retw
|= TRUE
;
611 workaround_b_j_loop_end
|= TRUE
;
612 workaround_short_loop
|= TRUE
;
613 workaround_close_loop_end
|= TRUE
;
614 workaround_all_short_loops
|= TRUE
;
615 enforce_three_byte_loop_align
= TRUE
;
622 option_density
= OPTION_MD_BASE
,
629 option_no_link_relax
,
637 option_text_section_literals
,
638 option_no_text_section_literals
,
640 option_absolute_literals
,
641 option_no_absolute_literals
,
643 option_align_targets
,
644 option_no_align_targets
,
646 option_warn_unaligned_targets
,
651 option_workaround_a0_b_retw
,
652 option_no_workaround_a0_b_retw
,
654 option_workaround_b_j_loop_end
,
655 option_no_workaround_b_j_loop_end
,
657 option_workaround_short_loop
,
658 option_no_workaround_short_loop
,
660 option_workaround_all_short_loops
,
661 option_no_workaround_all_short_loops
,
663 option_workaround_close_loop_end
,
664 option_no_workaround_close_loop_end
,
666 option_no_workarounds
,
668 option_rename_section_name
,
671 option_prefer_const16
,
673 option_target_hardware
676 const char *md_shortopts
= "";
678 struct option md_longopts
[] =
680 { "density", no_argument
, NULL
, option_density
},
681 { "no-density", no_argument
, NULL
, option_no_density
},
683 /* Both "relax" and "generics" are deprecated and treated as equivalent
684 to the "transform" option. */
685 { "relax", no_argument
, NULL
, option_relax
},
686 { "no-relax", no_argument
, NULL
, option_no_relax
},
687 { "generics", no_argument
, NULL
, option_generics
},
688 { "no-generics", no_argument
, NULL
, option_no_generics
},
690 { "transform", no_argument
, NULL
, option_transform
},
691 { "no-transform", no_argument
, NULL
, option_no_transform
},
692 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
693 { "no-text-section-literals", no_argument
, NULL
,
694 option_no_text_section_literals
},
695 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
696 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
697 /* This option was changed from -align-target to -target-align
698 because it conflicted with the "-al" option. */
699 { "target-align", no_argument
, NULL
, option_align_targets
},
700 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
701 { "warn-unaligned-targets", no_argument
, NULL
,
702 option_warn_unaligned_targets
},
703 { "longcalls", no_argument
, NULL
, option_longcalls
},
704 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
706 { "no-workaround-a0-b-retw", no_argument
, NULL
,
707 option_no_workaround_a0_b_retw
},
708 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
710 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
711 option_no_workaround_b_j_loop_end
},
712 { "workaround-b-j-loop-end", no_argument
, NULL
,
713 option_workaround_b_j_loop_end
},
715 { "no-workaround-short-loops", no_argument
, NULL
,
716 option_no_workaround_short_loop
},
717 { "workaround-short-loops", no_argument
, NULL
,
718 option_workaround_short_loop
},
720 { "no-workaround-all-short-loops", no_argument
, NULL
,
721 option_no_workaround_all_short_loops
},
722 { "workaround-all-short-loop", no_argument
, NULL
,
723 option_workaround_all_short_loops
},
725 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
726 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
728 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
730 { "no-workaround-close-loop-end", no_argument
, NULL
,
731 option_no_workaround_close_loop_end
},
732 { "workaround-close-loop-end", no_argument
, NULL
,
733 option_workaround_close_loop_end
},
735 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
737 { "link-relax", no_argument
, NULL
, option_link_relax
},
738 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
740 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
742 { NULL
, no_argument
, NULL
, 0 }
745 size_t md_longopts_size
= sizeof md_longopts
;
749 md_parse_option (int c
, char *arg
)
754 as_warn (_("--density option is ignored"));
756 case option_no_density
:
757 as_warn (_("--no-density option is ignored"));
759 case option_link_relax
:
762 case option_no_link_relax
:
765 case option_generics
:
766 as_warn (_("--generics is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_generics
:
769 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
772 as_warn (_("--relax is deprecated; use --transform instead"));
773 return md_parse_option (option_transform
, arg
);
774 case option_no_relax
:
775 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
776 return md_parse_option (option_no_transform
, arg
);
777 case option_longcalls
:
778 directive_state
[directive_longcalls
] = TRUE
;
780 case option_no_longcalls
:
781 directive_state
[directive_longcalls
] = FALSE
;
783 case option_text_section_literals
:
784 use_literal_section
= FALSE
;
786 case option_no_text_section_literals
:
787 use_literal_section
= TRUE
;
789 case option_absolute_literals
:
790 if (!absolute_literals_supported
)
792 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
795 directive_state
[directive_absolute_literals
] = TRUE
;
797 case option_no_absolute_literals
:
798 directive_state
[directive_absolute_literals
] = FALSE
;
801 case option_workaround_a0_b_retw
:
802 workaround_a0_b_retw
= TRUE
;
804 case option_no_workaround_a0_b_retw
:
805 workaround_a0_b_retw
= FALSE
;
807 case option_workaround_b_j_loop_end
:
808 workaround_b_j_loop_end
= TRUE
;
810 case option_no_workaround_b_j_loop_end
:
811 workaround_b_j_loop_end
= FALSE
;
814 case option_workaround_short_loop
:
815 workaround_short_loop
= TRUE
;
817 case option_no_workaround_short_loop
:
818 workaround_short_loop
= FALSE
;
821 case option_workaround_all_short_loops
:
822 workaround_all_short_loops
= TRUE
;
824 case option_no_workaround_all_short_loops
:
825 workaround_all_short_loops
= FALSE
;
828 case option_workaround_close_loop_end
:
829 workaround_close_loop_end
= TRUE
;
831 case option_no_workaround_close_loop_end
:
832 workaround_close_loop_end
= FALSE
;
835 case option_no_workarounds
:
836 workaround_a0_b_retw
= FALSE
;
837 workaround_b_j_loop_end
= FALSE
;
838 workaround_short_loop
= FALSE
;
839 workaround_all_short_loops
= FALSE
;
840 workaround_close_loop_end
= FALSE
;
843 case option_align_targets
:
844 align_targets
= TRUE
;
846 case option_no_align_targets
:
847 align_targets
= FALSE
;
850 case option_warn_unaligned_targets
:
851 warn_unaligned_branch_targets
= TRUE
;
854 case option_rename_section_name
:
855 build_section_rename (arg
);
859 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
860 should be emitted or not. FIXME: Not implemented. */
863 case option_prefer_l32r
:
865 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
869 case option_prefer_const16
:
871 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
875 case option_target_hardware
:
877 int earliest
, latest
= 0;
878 if (*arg
== 0 || *arg
== '-')
879 as_fatal (_("invalid target hardware version"));
881 earliest
= strtol (arg
, &arg
, 0);
885 else if (*arg
== '-')
888 as_fatal (_("invalid target hardware version"));
889 latest
= strtol (arg
, &arg
, 0);
892 as_fatal (_("invalid target hardware version"));
894 xtensa_setup_hw_workarounds (earliest
, latest
);
898 case option_transform
:
899 /* This option has no affect other than to use the defaults,
900 which are already set. */
903 case option_no_transform
:
904 /* This option turns off all transformations of any kind.
905 However, because we want to preserve the state of other
906 directives, we only change its own field. Thus, before
907 you perform any transformation, always check if transform
908 is available. If you use the functions we provide for this
909 purpose, you will be ok. */
910 directive_state
[directive_transform
] = FALSE
;
920 md_show_usage (FILE *stream
)
924 --[no-]text-section-literals\n\
925 [Do not] put literals in the text section\n\
926 --[no-]absolute-literals\n\
927 [Do not] default to use non-PC-relative literals\n\
928 --[no-]target-align [Do not] try to align branch targets\n\
929 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
930 --[no-]transform [Do not] transform instructions\n\
931 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
935 /* Functions related to the list of current label symbols. */
938 xtensa_add_insn_label (symbolS
*sym
)
942 if (!free_insn_labels
)
943 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
946 l
= free_insn_labels
;
947 free_insn_labels
= l
->next
;
951 l
->next
= insn_labels
;
957 xtensa_clear_insn_labels (void)
961 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
969 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
973 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
975 symbolS
*lit_sym
= lit
->sym
;
976 S_SET_VALUE (lit_sym
, new_offset
);
977 symbol_set_frag (lit_sym
, new_frag
);
982 /* Directive data and functions. */
984 typedef struct state_stackS_struct
986 directiveE directive
;
988 bfd_boolean old_state
;
992 struct state_stackS_struct
*prev
;
995 state_stackS
*directive_state_stack
;
997 const pseudo_typeS md_pseudo_table
[] =
999 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1000 { "literal_position", xtensa_literal_position
, 0 },
1001 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1002 { "long", xtensa_elf_cons
, 4 },
1003 { "word", xtensa_elf_cons
, 4 },
1004 { "4byte", xtensa_elf_cons
, 4 },
1005 { "short", xtensa_elf_cons
, 2 },
1006 { "2byte", xtensa_elf_cons
, 2 },
1007 { "begin", xtensa_begin_directive
, 0 },
1008 { "end", xtensa_end_directive
, 0 },
1009 { "literal", xtensa_literal_pseudo
, 0 },
1010 { "frequency", xtensa_frequency_pseudo
, 0 },
1016 use_transform (void)
1018 /* After md_end, you should be checking frag by frag, rather
1019 than state directives. */
1020 assert (!past_xtensa_end
);
1021 return directive_state
[directive_transform
];
1026 do_align_targets (void)
1028 /* Do not use this function after md_end; just look at align_targets
1029 instead. There is no target-align directive, so alignment is either
1030 enabled for all frags or not done at all. */
1031 assert (!past_xtensa_end
);
1032 return align_targets
&& use_transform ();
1037 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1041 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1043 as_where (&file
, &line
);
1045 stack
->directive
= directive
;
1046 stack
->negated
= negated
;
1047 stack
->old_state
= directive_state
[directive
];
1050 stack
->datum
= datum
;
1051 stack
->prev
= directive_state_stack
;
1052 directive_state_stack
= stack
;
1054 directive_state
[directive
] = !negated
;
1059 directive_pop (directiveE
*directive
,
1060 bfd_boolean
*negated
,
1065 state_stackS
*top
= directive_state_stack
;
1067 if (!directive_state_stack
)
1069 as_bad (_("unmatched end directive"));
1070 *directive
= directive_none
;
1074 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1075 *directive
= top
->directive
;
1076 *negated
= top
->negated
;
1079 *datum
= top
->datum
;
1080 directive_state_stack
= top
->prev
;
1086 directive_balance (void)
1088 while (directive_state_stack
)
1090 directiveE directive
;
1091 bfd_boolean negated
;
1096 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1097 as_warn_where ((char *) file
, line
,
1098 _(".begin directive with no matching .end directive"));
1104 inside_directive (directiveE dir
)
1106 state_stackS
*top
= directive_state_stack
;
1108 while (top
&& top
->directive
!= dir
)
1111 return (top
!= NULL
);
1116 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1120 char *directive_string
;
1122 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1127 input_line_pointer
+= 3;
1130 len
= strspn (input_line_pointer
,
1131 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1133 /* This code is a hack to make .begin [no-][generics|relax] exactly
1134 equivalent to .begin [no-]transform. We should remove it when
1135 we stop accepting those options. */
1137 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1139 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1140 directive_string
= "transform";
1142 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1144 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1145 directive_string
= "transform";
1148 directive_string
= input_line_pointer
;
1150 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1152 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1154 input_line_pointer
+= len
;
1155 *directive
= (directiveE
) i
;
1156 if (*negated
&& !directive_info
[i
].can_be_negated
)
1157 as_bad (_("directive %s cannot be negated"),
1158 directive_info
[i
].name
);
1163 as_bad (_("unknown directive"));
1164 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1169 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1171 directiveE directive
;
1172 bfd_boolean negated
;
1176 get_directive (&directive
, &negated
);
1177 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1179 discard_rest_of_line ();
1183 if (cur_vinsn
.inside_bundle
)
1184 as_bad (_("directives are not valid inside bundles"));
1188 case directive_literal
:
1189 if (!inside_directive (directive_literal
))
1191 /* Previous labels go with whatever follows this directive, not with
1192 the literal, so save them now. */
1193 saved_insn_labels
= insn_labels
;
1196 as_warn (_(".begin literal is deprecated; use .literal instead"));
1197 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1198 xtensa_switch_to_literal_fragment (state
);
1199 directive_push (directive_literal
, negated
, state
);
1202 case directive_literal_prefix
:
1203 /* Have to flush pending output because a movi relaxed to an l32r
1204 might produce a literal. */
1205 md_flush_pending_output ();
1206 /* Check to see if the current fragment is a literal
1207 fragment. If it is, then this operation is not allowed. */
1208 if (generating_literals
)
1210 as_bad (_("cannot set literal_prefix inside literal fragment"));
1214 /* Allocate the literal state for this section and push
1215 onto the directive stack. */
1216 ls
= xmalloc (sizeof (lit_state
));
1219 *ls
= default_lit_sections
;
1220 directive_push (directive_literal_prefix
, negated
, ls
);
1222 /* Process the new prefix. */
1223 xtensa_literal_prefix ();
1226 case directive_freeregs
:
1227 /* This information is currently unused, but we'll accept the statement
1228 and just discard the rest of the line. This won't check the syntax,
1229 but it will accept every correct freeregs directive. */
1230 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1231 directive_push (directive_freeregs
, negated
, 0);
1234 case directive_schedule
:
1235 md_flush_pending_output ();
1236 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1237 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1238 directive_push (directive_schedule
, negated
, 0);
1239 xtensa_set_frag_assembly_state (frag_now
);
1242 case directive_density
:
1243 as_warn (_(".begin [no-]density is ignored"));
1246 case directive_absolute_literals
:
1247 md_flush_pending_output ();
1248 if (!absolute_literals_supported
&& !negated
)
1250 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1253 xtensa_set_frag_assembly_state (frag_now
);
1254 directive_push (directive
, negated
, 0);
1258 md_flush_pending_output ();
1259 xtensa_set_frag_assembly_state (frag_now
);
1260 directive_push (directive
, negated
, 0);
1264 demand_empty_rest_of_line ();
1269 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1271 directiveE begin_directive
, end_directive
;
1272 bfd_boolean begin_negated
, end_negated
;
1276 emit_state
**state_ptr
;
1279 if (cur_vinsn
.inside_bundle
)
1280 as_bad (_("directives are not valid inside bundles"));
1282 get_directive (&end_directive
, &end_negated
);
1284 md_flush_pending_output ();
1286 switch (end_directive
)
1288 case (directiveE
) XTENSA_UNDEFINED
:
1289 discard_rest_of_line ();
1292 case directive_density
:
1293 as_warn (_(".end [no-]density is ignored"));
1294 demand_empty_rest_of_line ();
1297 case directive_absolute_literals
:
1298 if (!absolute_literals_supported
&& !end_negated
)
1300 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1301 demand_empty_rest_of_line ();
1310 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1311 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1312 (const void **) state_ptr
);
1314 if (begin_directive
!= directive_none
)
1316 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1318 as_bad (_("does not match begin %s%s at %s:%d"),
1319 begin_negated
? "no-" : "",
1320 directive_info
[begin_directive
].name
, file
, line
);
1324 switch (end_directive
)
1326 case directive_literal
:
1327 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1328 xtensa_restore_emit_state (state
);
1329 xtensa_set_frag_assembly_state (frag_now
);
1331 if (!inside_directive (directive_literal
))
1333 /* Restore the list of current labels. */
1334 xtensa_clear_insn_labels ();
1335 insn_labels
= saved_insn_labels
;
1339 case directive_literal_prefix
:
1340 /* Restore the default collection sections from saved state. */
1341 s
= (lit_state
*) state
;
1343 default_lit_sections
= *s
;
1345 /* Free the state storage. */
1346 free (s
->lit_prefix
);
1350 case directive_schedule
:
1351 case directive_freeregs
:
1355 xtensa_set_frag_assembly_state (frag_now
);
1361 demand_empty_rest_of_line ();
1365 /* Place an aligned literal fragment at the current location. */
1368 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1370 md_flush_pending_output ();
1372 if (inside_directive (directive_literal
))
1373 as_warn (_(".literal_position inside literal directive; ignoring"));
1374 xtensa_mark_literal_pool_location ();
1376 demand_empty_rest_of_line ();
1377 xtensa_clear_insn_labels ();
1381 /* Support .literal label, expr, ... */
1384 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1387 char *p
, *base_name
;
1391 if (inside_directive (directive_literal
))
1393 as_bad (_(".literal not allowed inside .begin literal region"));
1394 ignore_rest_of_line ();
1398 md_flush_pending_output ();
1400 /* Previous labels go with whatever follows this directive, not with
1401 the literal, so save them now. */
1402 saved_insn_labels
= insn_labels
;
1405 /* If we are using text-section literals, then this is the right value... */
1408 base_name
= input_line_pointer
;
1410 xtensa_switch_to_literal_fragment (&state
);
1412 /* ...but if we aren't using text-section-literals, then we
1413 need to put them in the section we just switched to. */
1414 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1417 /* All literals are aligned to four-byte boundaries. */
1418 frag_align (2, 0, 0);
1419 record_alignment (now_seg
, 2);
1421 c
= get_symbol_end ();
1422 /* Just after name is now '\0'. */
1423 p
= input_line_pointer
;
1427 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1429 as_bad (_("expected comma or colon after symbol name; "
1430 "rest of line ignored"));
1431 ignore_rest_of_line ();
1432 xtensa_restore_emit_state (&state
);
1440 input_line_pointer
++; /* skip ',' or ':' */
1442 xtensa_elf_cons (4);
1444 xtensa_restore_emit_state (&state
);
1446 /* Restore the list of current labels. */
1447 xtensa_clear_insn_labels ();
1448 insn_labels
= saved_insn_labels
;
1453 xtensa_literal_prefix (void)
1458 /* Parse the new prefix from the input_line_pointer. */
1460 len
= strspn (input_line_pointer
,
1461 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1462 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1464 /* Get a null-terminated copy of the name. */
1465 name
= xmalloc (len
+ 1);
1467 strncpy (name
, input_line_pointer
, len
);
1470 /* Skip the name in the input line. */
1471 input_line_pointer
+= len
;
1473 default_lit_sections
.lit_prefix
= name
;
1475 /* Clear cached literal sections, since the prefix has changed. */
1476 default_lit_sections
.lit_seg
= NULL
;
1477 default_lit_sections
.lit4_seg
= NULL
;
1481 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1484 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1486 float fall_through_f
, target_f
;
1488 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1489 if (fall_through_f
< 0)
1491 as_bad (_("fall through frequency must be greater than 0"));
1492 ignore_rest_of_line ();
1496 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1499 as_bad (_("branch target frequency must be greater than 0"));
1500 ignore_rest_of_line ();
1504 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1506 demand_empty_rest_of_line ();
1510 /* Like normal .long/.short/.word, except support @plt, etc.
1511 Clobbers input_line_pointer, checks end-of-line. */
1514 xtensa_elf_cons (int nbytes
)
1517 bfd_reloc_code_real_type reloc
;
1519 md_flush_pending_output ();
1521 if (cur_vinsn
.inside_bundle
)
1522 as_bad (_("directives are not valid inside bundles"));
1524 if (is_it_end_of_statement ())
1526 demand_empty_rest_of_line ();
1533 if (exp
.X_op
== O_symbol
1534 && *input_line_pointer
== '@'
1535 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1538 reloc_howto_type
*reloc_howto
=
1539 bfd_reloc_type_lookup (stdoutput
, reloc
);
1541 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1542 as_bad (_("unsupported relocation"));
1543 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1544 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1545 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1546 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1547 as_bad (_("opcode-specific %s relocation used outside "
1548 "an instruction"), reloc_howto
->name
);
1549 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1550 as_bad (_("%s relocations do not fit in %d bytes"),
1551 reloc_howto
->name
, nbytes
);
1554 char *p
= frag_more ((int) nbytes
);
1555 xtensa_set_frag_assembly_state (frag_now
);
1556 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1557 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1561 emit_expr (&exp
, (unsigned int) nbytes
);
1563 while (*input_line_pointer
++ == ',');
1565 input_line_pointer
--; /* Put terminator back into stream. */
1566 demand_empty_rest_of_line ();
1570 /* Parsing and Idiom Translation. */
1572 /* Parse @plt, etc. and return the desired relocation. */
1573 static bfd_reloc_code_real_type
1574 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1581 struct suffix_reloc_map
*ptr
;
1584 return BFD_RELOC_NONE
;
1586 for (ch
= *str
, str2
= ident
;
1587 (str2
< ident
+ sizeof (ident
) - 1
1588 && (ISALNUM (ch
) || ch
== '@'));
1591 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1598 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1599 if (ch
== ptr
->suffix
[0]
1600 && len
== ptr
->length
1601 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1603 /* Now check for "identifier@suffix+constant". */
1604 if (*str
== '-' || *str
== '+')
1606 char *orig_line
= input_line_pointer
;
1607 expressionS new_exp
;
1609 input_line_pointer
= str
;
1610 expression (&new_exp
);
1611 if (new_exp
.X_op
== O_constant
)
1613 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1614 str
= input_line_pointer
;
1617 if (&input_line_pointer
!= str_p
)
1618 input_line_pointer
= orig_line
;
1625 return BFD_RELOC_UNUSED
;
1629 /* Find the matching operator type. */
1630 static unsigned char
1631 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1633 struct suffix_reloc_map
*sfx
;
1634 unsigned char operator = (unsigned char) -1;
1636 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1638 if (sfx
->reloc
== reloc
)
1640 operator = sfx
->operator;
1644 assert (operator != (unsigned char) -1);
1649 /* Find the matching reloc type. */
1650 static bfd_reloc_code_real_type
1651 map_operator_to_reloc (unsigned char operator)
1653 struct suffix_reloc_map
*sfx
;
1654 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1656 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1658 if (sfx
->operator == operator)
1665 if (reloc
== BFD_RELOC_UNUSED
)
1666 return BFD_RELOC_32
;
1673 expression_end (const char *name
)
1696 #define ERROR_REG_NUM ((unsigned) -1)
1699 tc_get_register (const char *prefix
)
1702 const char *next_expr
;
1703 const char *old_line_pointer
;
1706 old_line_pointer
= input_line_pointer
;
1708 if (*input_line_pointer
== '$')
1709 ++input_line_pointer
;
1711 /* Accept "sp" as a synonym for "a1". */
1712 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1713 && expression_end (input_line_pointer
+ 2))
1715 input_line_pointer
+= 2;
1716 return 1; /* AR[1] */
1719 while (*input_line_pointer
++ == *prefix
++)
1721 --input_line_pointer
;
1726 as_bad (_("bad register name: %s"), old_line_pointer
);
1727 return ERROR_REG_NUM
;
1730 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1732 as_bad (_("bad register number: %s"), input_line_pointer
);
1733 return ERROR_REG_NUM
;
1738 while (ISDIGIT ((int) *input_line_pointer
))
1739 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1741 if (!(next_expr
= expression_end (input_line_pointer
)))
1743 as_bad (_("bad register name: %s"), old_line_pointer
);
1744 return ERROR_REG_NUM
;
1747 input_line_pointer
= (char *) next_expr
;
1754 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1756 xtensa_isa isa
= xtensa_default_isa
;
1758 /* Check if this is an immediate operand. */
1759 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1761 bfd_reloc_code_real_type reloc
;
1762 segT t
= expression (tok
);
1763 if (t
== absolute_section
1764 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1766 assert (tok
->X_op
== O_constant
);
1767 tok
->X_op
= O_symbol
;
1768 tok
->X_add_symbol
= &abs_symbol
;
1771 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1772 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1777 case BFD_RELOC_LO16
:
1778 if (tok
->X_op
== O_constant
)
1780 tok
->X_add_number
&= 0xffff;
1784 case BFD_RELOC_HI16
:
1785 if (tok
->X_op
== O_constant
)
1787 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1791 case BFD_RELOC_UNUSED
:
1792 as_bad (_("unsupported relocation"));
1794 case BFD_RELOC_32_PCREL
:
1795 as_bad (_("pcrel relocation not allowed in an instruction"));
1800 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1805 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1806 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1808 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1811 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1812 as_bad (_("register number out of range"));
1815 tok
->X_op
= O_register
;
1816 tok
->X_add_symbol
= 0;
1817 tok
->X_add_number
= reg
;
1822 /* Split up the arguments for an opcode or pseudo-op. */
1825 tokenize_arguments (char **args
, char *str
)
1827 char *old_input_line_pointer
;
1828 bfd_boolean saw_comma
= FALSE
;
1829 bfd_boolean saw_arg
= FALSE
;
1830 bfd_boolean saw_colon
= FALSE
;
1832 char *arg_end
, *arg
;
1835 /* Save and restore input_line_pointer around this function. */
1836 old_input_line_pointer
= input_line_pointer
;
1837 input_line_pointer
= str
;
1839 while (*input_line_pointer
)
1842 switch (*input_line_pointer
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 input_line_pointer
++;
1857 if (saw_comma
|| saw_colon
|| !saw_arg
)
1863 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1866 arg_end
= input_line_pointer
+ 1;
1867 while (!expression_end (arg_end
))
1870 arg_len
= arg_end
- input_line_pointer
;
1871 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1872 args
[num_args
] = arg
;
1876 strncpy (arg
, input_line_pointer
, arg_len
);
1877 arg
[arg_len
] = '\0';
1879 input_line_pointer
= arg_end
;
1889 if (saw_comma
|| saw_colon
)
1891 input_line_pointer
= old_input_line_pointer
;
1896 as_bad (_("extra comma"));
1898 as_bad (_("extra colon"));
1900 as_bad (_("missing argument"));
1902 as_bad (_("missing comma or colon"));
1903 input_line_pointer
= old_input_line_pointer
;
1908 /* Parse the arguments to an opcode. Return TRUE on error. */
1911 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1913 expressionS
*tok
, *last_tok
;
1914 xtensa_opcode opcode
= insn
->opcode
;
1915 bfd_boolean had_error
= TRUE
;
1916 xtensa_isa isa
= xtensa_default_isa
;
1917 int n
, num_regs
= 0;
1918 int opcode_operand_count
;
1919 int opnd_cnt
, last_opnd_cnt
;
1920 unsigned int next_reg
= 0;
1921 char *old_input_line_pointer
;
1923 if (insn
->insn_type
== ITYPE_LITERAL
)
1924 opcode_operand_count
= 1;
1926 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1929 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1931 /* Save and restore input_line_pointer around this function. */
1932 old_input_line_pointer
= input_line_pointer
;
1938 /* Skip invisible operands. */
1939 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1945 for (n
= 0; n
< num_args
; n
++)
1947 input_line_pointer
= arg_strings
[n
];
1948 if (*input_line_pointer
== ':')
1950 xtensa_regfile opnd_rf
;
1951 input_line_pointer
++;
1954 assert (opnd_cnt
> 0);
1956 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1958 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1959 as_warn (_("incorrect register number, ignoring"));
1964 if (opnd_cnt
>= opcode_operand_count
)
1966 as_warn (_("too many arguments"));
1969 assert (opnd_cnt
< MAX_INSN_ARGS
);
1971 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1972 next_reg
= tok
->X_add_number
+ 1;
1974 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1976 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1978 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1979 /* minus 1 because we are seeing one right now */
1985 last_opnd_cnt
= opnd_cnt
;
1992 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1996 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1999 insn
->ntok
= tok
- insn
->tok
;
2003 input_line_pointer
= old_input_line_pointer
;
2009 get_invisible_operands (TInsn
*insn
)
2011 xtensa_isa isa
= xtensa_default_isa
;
2012 static xtensa_insnbuf slotbuf
= NULL
;
2014 xtensa_opcode opc
= insn
->opcode
;
2015 int slot
, opnd
, fmt_found
;
2019 slotbuf
= xtensa_insnbuf_alloc (isa
);
2021 /* Find format/slot where this can be encoded. */
2024 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2026 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2028 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2034 if (fmt_found
) break;
2039 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2043 /* First encode all the visible operands
2044 (to deal with shared field operands). */
2045 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2047 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2048 && (insn
->tok
[opnd
].X_op
== O_register
2049 || insn
->tok
[opnd
].X_op
== O_constant
))
2051 val
= insn
->tok
[opnd
].X_add_number
;
2052 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2053 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2057 /* Then pull out the values for the invisible ones. */
2058 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2060 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2062 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2063 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2064 insn
->tok
[opnd
].X_add_number
= val
;
2065 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2066 insn
->tok
[opnd
].X_op
= O_register
;
2068 insn
->tok
[opnd
].X_op
= O_constant
;
2077 xg_reverse_shift_count (char **cnt_argp
)
2079 char *cnt_arg
, *new_arg
;
2080 cnt_arg
= *cnt_argp
;
2082 /* replace the argument with "31-(argument)" */
2083 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2084 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2087 *cnt_argp
= new_arg
;
2091 /* If "arg" is a constant expression, return non-zero with the value
2095 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2098 char *save_ptr
= input_line_pointer
;
2100 input_line_pointer
= arg
;
2102 input_line_pointer
= save_ptr
;
2104 if (exp
.X_op
== O_constant
)
2106 *valp
= exp
.X_add_number
;
2115 xg_replace_opname (char **popname
, char *newop
)
2118 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2119 strcpy (*popname
, newop
);
2124 xg_check_num_args (int *pnum_args
,
2129 int num_args
= *pnum_args
;
2131 if (num_args
< expected_num
)
2133 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2138 if (num_args
> expected_num
)
2140 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2141 num_args
, opname
, expected_num
);
2142 while (num_args
-- > expected_num
)
2144 free (arg_strings
[num_args
]);
2145 arg_strings
[num_args
] = 0;
2147 *pnum_args
= expected_num
;
2155 /* If the register is not specified as part of the opcode,
2156 then get it from the operand and move it to the opcode. */
2159 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2161 xtensa_isa isa
= xtensa_default_isa
;
2163 char *opname
, *new_opname
;
2164 const char *sr_name
;
2165 int is_user
, is_write
;
2170 is_user
= (opname
[1] == 'u');
2171 is_write
= (opname
[0] == 'w');
2173 /* Opname == [rw]ur or [rwx]sr... */
2175 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2178 /* Check if the argument is a symbolic register name. */
2179 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2180 /* Handle WSR to "INTSET" as a special case. */
2181 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2182 && !strcasecmp (arg_strings
[1], "intset"))
2183 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2184 if (sr
== XTENSA_UNDEFINED
2185 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2187 /* Maybe it's a register number.... */
2189 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2191 as_bad (_("invalid register '%s' for '%s' instruction"),
2192 arg_strings
[1], opname
);
2195 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2196 if (sr
== XTENSA_UNDEFINED
)
2198 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2199 (long) val
, opname
);
2204 /* Remove the last argument, which is now part of the opcode. */
2205 free (arg_strings
[1]);
2209 /* Translate the opcode. */
2210 sr_name
= xtensa_sysreg_name (isa
, sr
);
2211 /* Another special case for "WSR.INTSET".... */
2212 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2214 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2215 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2217 *popname
= new_opname
;
2224 xtensa_translate_old_userreg_ops (char **popname
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 bfd_boolean has_underbar
= FALSE
;
2233 if (opname
[0] == '_')
2235 has_underbar
= TRUE
;
2239 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2240 if (sr
!= XTENSA_UNDEFINED
)
2242 /* The new default name ("nnn") is different from the old default
2243 name ("URnnn"). The old default is handled below, and we don't
2244 want to recognize [RW]nnn, so do nothing if the name is the (new)
2246 static char namebuf
[10];
2247 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2248 if (strcmp (namebuf
, opname
+ 1) == 0)
2256 /* Only continue if the reg name is "URnnn". */
2257 if (opname
[1] != 'u' || opname
[2] != 'r')
2259 val
= strtoul (opname
+ 3, &end
, 10);
2263 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2264 if (sr
== XTENSA_UNDEFINED
)
2266 as_bad (_("invalid register number (%ld) for '%s'"),
2267 (long) val
, opname
);
2272 /* Translate the opcode. */
2273 sr_name
= xtensa_sysreg_name (isa
, sr
);
2274 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2275 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2276 opname
[0], sr_name
);
2278 *popname
= new_opname
;
2285 xtensa_translate_zero_immed (char *old_op
,
2295 assert (opname
[0] != '_');
2297 if (strcmp (opname
, old_op
) != 0)
2300 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2302 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2304 xg_replace_opname (popname
, new_op
);
2305 free (arg_strings
[1]);
2306 arg_strings
[1] = arg_strings
[2];
2315 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2316 Returns non-zero if an error was found. */
2319 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2321 char *opname
= *popname
;
2322 bfd_boolean has_underbar
= FALSE
;
2326 has_underbar
= TRUE
;
2330 if (strcmp (opname
, "mov") == 0)
2332 if (use_transform () && !has_underbar
&& density_supported
)
2333 xg_replace_opname (popname
, "mov.n");
2336 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2338 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2339 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2340 strcpy (arg_strings
[2], arg_strings
[1]);
2346 if (strcmp (opname
, "bbsi.l") == 0)
2348 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2350 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2351 if (target_big_endian
)
2352 xg_reverse_shift_count (&arg_strings
[1]);
2356 if (strcmp (opname
, "bbci.l") == 0)
2358 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2360 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2361 if (target_big_endian
)
2362 xg_reverse_shift_count (&arg_strings
[1]);
2366 /* Don't do anything special with NOPs inside FLIX instructions. They
2367 are handled elsewhere. Real NOP instructions are always available
2368 in configurations with FLIX, so this should never be an issue but
2369 check for it anyway. */
2370 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2371 && strcmp (opname
, "nop") == 0)
2373 if (use_transform () && !has_underbar
&& density_supported
)
2374 xg_replace_opname (popname
, "nop.n");
2377 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2379 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2380 arg_strings
[0] = (char *) xmalloc (3);
2381 arg_strings
[1] = (char *) xmalloc (3);
2382 arg_strings
[2] = (char *) xmalloc (3);
2383 strcpy (arg_strings
[0], "a1");
2384 strcpy (arg_strings
[1], "a1");
2385 strcpy (arg_strings
[2], "a1");
2391 /* Recognize [RW]UR and [RWX]SR. */
2392 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2393 && (opname
[1] == 'u' || opname
[1] == 's'))
2394 || (opname
[0] == 'x' && opname
[1] == 's'))
2396 && opname
[3] == '\0')
2397 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2399 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2400 [RW]<name> if <name> is the non-default name of a user register. */
2401 if ((opname
[0] == 'r' || opname
[0] == 'w')
2402 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2403 return xtensa_translate_old_userreg_ops (popname
);
2405 /* Relax branches that don't allow comparisons against an immediate value
2406 of zero to the corresponding branches with implicit zero immediates. */
2407 if (!has_underbar
&& use_transform ())
2409 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2410 pnum_args
, arg_strings
))
2413 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2414 pnum_args
, arg_strings
))
2417 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2418 pnum_args
, arg_strings
))
2421 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2422 pnum_args
, arg_strings
))
2430 /* Functions for dealing with the Xtensa ISA. */
2432 /* Currently the assembler only allows us to use a single target per
2433 fragment. Because of this, only one operand for a given
2434 instruction may be symbolic. If there is a PC-relative operand,
2435 the last one is chosen. Otherwise, the result is the number of the
2436 last immediate operand, and if there are none of those, we fail and
2440 get_relaxable_immed (xtensa_opcode opcode
)
2442 int last_immed
= -1;
2445 if (opcode
== XTENSA_UNDEFINED
)
2448 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2449 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2451 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2453 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2455 if (last_immed
== -1
2456 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2463 static xtensa_opcode
2464 get_opcode_from_buf (const char *buf
, int slot
)
2466 static xtensa_insnbuf insnbuf
= NULL
;
2467 static xtensa_insnbuf slotbuf
= NULL
;
2468 xtensa_isa isa
= xtensa_default_isa
;
2473 insnbuf
= xtensa_insnbuf_alloc (isa
);
2474 slotbuf
= xtensa_insnbuf_alloc (isa
);
2477 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2478 fmt
= xtensa_format_decode (isa
, insnbuf
);
2479 if (fmt
== XTENSA_UNDEFINED
)
2480 return XTENSA_UNDEFINED
;
2482 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2483 return XTENSA_UNDEFINED
;
2485 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2486 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2490 #ifdef TENSILICA_DEBUG
2492 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2495 xtensa_print_insn_table (void)
2497 int num_opcodes
, num_operands
;
2498 xtensa_opcode opcode
;
2499 xtensa_isa isa
= xtensa_default_isa
;
2501 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2502 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2505 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2506 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2507 for (opn
= 0; opn
< num_operands
; opn
++)
2509 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2511 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2513 xtensa_regfile opnd_rf
=
2514 xtensa_operand_regfile (isa
, opcode
, opn
);
2515 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2517 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2518 fputs ("[lLr] ", stderr
);
2520 fputs ("i ", stderr
);
2522 fprintf (stderr
, "\n");
2528 print_vliw_insn (xtensa_insnbuf vbuf
)
2530 xtensa_isa isa
= xtensa_default_isa
;
2531 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2532 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2535 fprintf (stderr
, "format = %d\n", f
);
2537 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2539 xtensa_opcode opcode
;
2543 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2544 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2545 opname
= xtensa_opcode_name (isa
, opcode
);
2547 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2548 fprintf (stderr
, " operands = ");
2550 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2554 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2556 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2557 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2558 fprintf (stderr
, "%d ", val
);
2560 fprintf (stderr
, "\n");
2562 xtensa_insnbuf_free (isa
, sbuf
);
2565 #endif /* TENSILICA_DEBUG */
2569 is_direct_call_opcode (xtensa_opcode opcode
)
2571 xtensa_isa isa
= xtensa_default_isa
;
2572 int n
, num_operands
;
2574 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2577 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2578 for (n
= 0; n
< num_operands
; n
++)
2580 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2581 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2588 /* Convert from BFD relocation type code to slot and operand number.
2589 Returns non-zero on failure. */
2592 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2594 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2595 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2597 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2600 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2601 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2603 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2613 /* Convert from slot number to BFD relocation type code for the
2614 standard PC-relative relocations. Return BFD_RELOC_NONE on
2617 static bfd_reloc_code_real_type
2618 encode_reloc (int slot
)
2620 if (slot
< 0 || slot
> 14)
2621 return BFD_RELOC_NONE
;
2623 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2627 /* Convert from slot numbers to BFD relocation type code for the
2628 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2630 static bfd_reloc_code_real_type
2631 encode_alt_reloc (int slot
)
2633 if (slot
< 0 || slot
> 14)
2634 return BFD_RELOC_NONE
;
2636 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2641 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2644 xtensa_opcode opcode
,
2650 uint32 valbuf
= value
;
2652 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2654 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2656 as_bad_where ((char *) file
, line
,
2657 _("operand %d of '%s' has out of range value '%u'"),
2659 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2662 as_bad_where ((char *) file
, line
,
2663 _("operand %d of '%s' has invalid value '%u'"),
2665 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2670 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2676 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2679 xtensa_opcode opcode
,
2683 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2684 fmt
, slot
, slotbuf
, &val
);
2685 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2690 /* Checks for rules from xtensa-relax tables. */
2692 /* The routine xg_instruction_matches_option_term must return TRUE
2693 when a given option term is true. The meaning of all of the option
2694 terms is given interpretation by this function. This is needed when
2695 an option depends on the state of a directive, but there are no such
2696 options in use right now. */
2699 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2700 const ReqOrOption
*option
)
2702 if (strcmp (option
->option_name
, "realnop") == 0
2703 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2705 /* These conditions were evaluated statically when building the
2706 relaxation table. There's no need to reevaluate them now. */
2711 as_fatal (_("internal error: unknown option name '%s'"),
2712 option
->option_name
);
2718 xg_instruction_matches_or_options (TInsn
*insn
,
2719 const ReqOrOptionList
*or_option
)
2721 const ReqOrOption
*option
;
2722 /* Must match each of the AND terms. */
2723 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2725 if (xg_instruction_matches_option_term (insn
, option
))
2733 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2735 const ReqOption
*req_options
;
2736 /* Must match each of the AND terms. */
2737 for (req_options
= options
;
2738 req_options
!= NULL
;
2739 req_options
= req_options
->next
)
2741 /* Must match one of the OR clauses. */
2742 if (!xg_instruction_matches_or_options (insn
,
2743 req_options
->or_option_terms
))
2750 /* Return the transition rule that matches or NULL if none matches. */
2753 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2755 PreconditionList
*condition_l
;
2757 if (rule
->opcode
!= insn
->opcode
)
2760 for (condition_l
= rule
->conditions
;
2761 condition_l
!= NULL
;
2762 condition_l
= condition_l
->next
)
2766 Precondition
*cond
= condition_l
->precond
;
2771 /* The expression must be the constant. */
2772 assert (cond
->op_num
< insn
->ntok
);
2773 exp1
= &insn
->tok
[cond
->op_num
];
2774 if (expr_is_const (exp1
))
2779 if (get_expr_const (exp1
) != cond
->op_data
)
2783 if (get_expr_const (exp1
) == cond
->op_data
)
2790 else if (expr_is_register (exp1
))
2795 if (get_expr_register (exp1
) != cond
->op_data
)
2799 if (get_expr_register (exp1
) == cond
->op_data
)
2811 assert (cond
->op_num
< insn
->ntok
);
2812 assert (cond
->op_data
< insn
->ntok
);
2813 exp1
= &insn
->tok
[cond
->op_num
];
2814 exp2
= &insn
->tok
[cond
->op_data
];
2819 if (!expr_is_equal (exp1
, exp2
))
2823 if (expr_is_equal (exp1
, exp2
))
2835 if (!xg_instruction_matches_options (insn
, rule
->options
))
2843 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2845 bfd_boolean a_greater
= FALSE
;
2846 bfd_boolean b_greater
= FALSE
;
2848 ReqOptionList
*l_a
= a
->options
;
2849 ReqOptionList
*l_b
= b
->options
;
2851 /* We only care if they both are the same except for
2852 a const16 vs. an l32r. */
2854 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2856 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2857 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2858 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2860 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2862 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2864 /* This is the case we care about. */
2865 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2866 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2873 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2874 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2884 l_or_a
= l_or_a
->next
;
2885 l_or_b
= l_or_b
->next
;
2887 if (l_or_a
|| l_or_b
)
2896 /* Incomparable if the substitution was used differently in two cases. */
2897 if (a_greater
&& b_greater
)
2909 static TransitionRule
*
2910 xg_instruction_match (TInsn
*insn
)
2912 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2914 assert (insn
->opcode
< table
->num_opcodes
);
2916 /* Walk through all of the possible transitions. */
2917 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2919 TransitionRule
*rule
= l
->rule
;
2920 if (xg_instruction_matches_rule (insn
, rule
))
2927 /* Various Other Internal Functions. */
2930 is_unique_insn_expansion (TransitionRule
*r
)
2932 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2934 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2940 /* Check if there is exactly one relaxation for INSN that converts it to
2941 another instruction of equal or larger size. If so, and if TARG is
2942 non-null, go ahead and generate the relaxed instruction into TARG. If
2943 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2944 instruction, i.e., ignore relaxations that convert to an instruction of
2945 equal size. In some contexts where this function is used, only
2946 a single widening is allowed and the NARROW_ONLY argument is used to
2947 exclude cases like ADDI being "widened" to an ADDMI, which may
2948 later be relaxed to an ADDMI/ADDI pair. */
2951 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2953 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2955 TransitionRule
*match
= 0;
2957 assert (insn
->insn_type
== ITYPE_INSN
);
2958 assert (insn
->opcode
< table
->num_opcodes
);
2960 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2962 TransitionRule
*rule
= l
->rule
;
2964 if (xg_instruction_matches_rule (insn
, rule
)
2965 && is_unique_insn_expansion (rule
)
2966 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2967 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2978 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2983 /* Return the maximum number of bytes this opcode can expand to. */
2986 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2988 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2990 int max_size
= xg_get_single_size (opcode
);
2992 assert (opcode
< table
->num_opcodes
);
2994 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2996 TransitionRule
*rule
= l
->rule
;
2997 BuildInstr
*build_list
;
3002 build_list
= rule
->to_instr
;
3003 if (is_unique_insn_expansion (rule
))
3005 assert (build_list
->typ
== INSTR_INSTR
);
3006 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3009 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3011 switch (build_list
->typ
)
3014 this_size
+= xg_get_single_size (build_list
->opcode
);
3016 case INSTR_LITERAL_DEF
:
3017 case INSTR_LABEL_DEF
:
3022 if (this_size
> max_size
)
3023 max_size
= this_size
;
3029 /* Return the maximum number of literal bytes this opcode can generate. */
3032 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3034 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3038 assert (opcode
< table
->num_opcodes
);
3040 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3042 TransitionRule
*rule
= l
->rule
;
3043 BuildInstr
*build_list
;
3048 build_list
= rule
->to_instr
;
3049 if (is_unique_insn_expansion (rule
))
3051 assert (build_list
->typ
== INSTR_INSTR
);
3052 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3055 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3057 switch (build_list
->typ
)
3059 case INSTR_LITERAL_DEF
:
3060 /* Hard-coded 4-byte literal. */
3064 case INSTR_LABEL_DEF
:
3069 if (this_size
> max_size
)
3070 max_size
= this_size
;
3077 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3079 int steps_taken
= 0;
3080 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3083 assert (insn
->insn_type
== ITYPE_INSN
);
3084 assert (insn
->opcode
< table
->num_opcodes
);
3086 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3088 TransitionRule
*rule
= l
->rule
;
3090 if (xg_instruction_matches_rule (insn
, rule
))
3092 if (steps_taken
== lateral_steps
)
3102 get_special_literal_symbol (void)
3104 static symbolS
*sym
= NULL
;
3107 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3113 get_special_label_symbol (void)
3115 static symbolS
*sym
= NULL
;
3118 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3124 xg_valid_literal_expression (const expressionS
*exp
)
3142 /* This will check to see if the value can be converted into the
3143 operand type. It will return TRUE if it does not fit. */
3146 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3148 uint32 valbuf
= value
;
3149 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3155 /* Assumes: All immeds are constants. Check that all constants fit
3156 into their immeds; return FALSE if not. */
3159 xg_immeds_fit (const TInsn
*insn
)
3161 xtensa_isa isa
= xtensa_default_isa
;
3165 assert (insn
->insn_type
== ITYPE_INSN
);
3166 for (i
= 0; i
< n
; ++i
)
3168 const expressionS
*expr
= &insn
->tok
[i
];
3169 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3176 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3181 /* The symbol should have a fixup associated with it. */
3190 /* This should only be called after we have an initial
3191 estimate of the addresses. */
3194 xg_symbolic_immeds_fit (const TInsn
*insn
,
3200 xtensa_isa isa
= xtensa_default_isa
;
3208 assert (insn
->insn_type
== ITYPE_INSN
);
3210 for (i
= 0; i
< n
; ++i
)
3212 const expressionS
*expr
= &insn
->tok
[i
];
3213 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3220 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3226 /* Check for the worst case. */
3227 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3232 /* We only allow symbols for PC-relative references.
3233 If pc_frag == 0, then we don't have frag locations yet. */
3235 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3238 /* If it is a weak symbol or a symbol in a different section,
3239 it cannot be known to fit at assembly time. */
3240 if (S_IS_WEAK (expr
->X_add_symbol
)
3241 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* For a direct call with --no-longcalls, be optimistic and
3244 assume it will be in range. */
3245 if (is_direct_call_opcode (insn
->opcode
)
3246 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3252 symbolP
= expr
->X_add_symbol
;
3253 sym_frag
= symbol_get_frag (symbolP
);
3254 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3255 pc
= pc_frag
->fr_address
+ pc_offset
;
3257 /* If frag has yet to be reached on this pass, assume it
3258 will move by STRETCH just as we did. If this is not so,
3259 it will be because some frag between grows, and that will
3260 force another pass. Beware zero-length frags. There
3261 should be a faster way to do this. */
3264 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3265 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3270 new_offset
= target
;
3271 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3272 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3277 /* The symbol should have a fixup associated with it. */
3286 /* Return TRUE on success. */
3289 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3295 targ
->debug_line
= insn
->debug_line
;
3296 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3301 targ
->opcode
= bi
->opcode
;
3302 targ
->insn_type
= ITYPE_INSN
;
3303 targ
->is_specific_opcode
= FALSE
;
3305 for (; op
!= NULL
; op
= op
->next
)
3307 int op_num
= op
->op_num
;
3308 int op_data
= op
->op_data
;
3310 assert (op
->op_num
< MAX_INSN_ARGS
);
3312 if (targ
->ntok
<= op_num
)
3313 targ
->ntok
= op_num
+ 1;
3318 set_expr_const (&targ
->tok
[op_num
], op_data
);
3321 assert (op_data
< insn
->ntok
);
3322 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3325 sym
= get_special_literal_symbol ();
3326 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3329 sym
= get_special_label_symbol ();
3330 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3332 case OP_OPERAND_HI16U
:
3333 case OP_OPERAND_LOW16U
:
3334 assert (op_data
< insn
->ntok
);
3335 if (expr_is_const (&insn
->tok
[op_data
]))
3338 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3339 val
= xg_apply_userdef_op_fn (op
->typ
,
3342 targ
->tok
[op_num
].X_add_number
= val
;
3346 /* For const16 we can create relocations for these. */
3347 if (targ
->opcode
== XTENSA_UNDEFINED
3348 || (targ
->opcode
!= xtensa_const16_opcode
))
3350 assert (op_data
< insn
->ntok
);
3351 /* Need to build a O_lo16 or O_hi16. */
3352 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3353 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3355 if (op
->typ
== OP_OPERAND_HI16U
)
3356 targ
->tok
[op_num
].X_op
= O_hi16
;
3357 else if (op
->typ
== OP_OPERAND_LOW16U
)
3358 targ
->tok
[op_num
].X_op
= O_lo16
;
3365 /* currently handles:
3368 OP_OPERAND_F32MINUS */
3369 if (xg_has_userdef_op_fn (op
->typ
))
3371 assert (op_data
< insn
->ntok
);
3372 if (expr_is_const (&insn
->tok
[op_data
]))
3375 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3376 val
= xg_apply_userdef_op_fn (op
->typ
,
3379 targ
->tok
[op_num
].X_add_number
= val
;
3382 return FALSE
; /* We cannot use a relocation for this. */
3391 case INSTR_LITERAL_DEF
:
3393 targ
->opcode
= XTENSA_UNDEFINED
;
3394 targ
->insn_type
= ITYPE_LITERAL
;
3395 targ
->is_specific_opcode
= FALSE
;
3396 for (; op
!= NULL
; op
= op
->next
)
3398 int op_num
= op
->op_num
;
3399 int op_data
= op
->op_data
;
3400 assert (op
->op_num
< MAX_INSN_ARGS
);
3402 if (targ
->ntok
<= op_num
)
3403 targ
->ntok
= op_num
+ 1;
3408 assert (op_data
< insn
->ntok
);
3409 /* We can only pass resolvable literals through. */
3410 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3412 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3424 case INSTR_LABEL_DEF
:
3426 targ
->opcode
= XTENSA_UNDEFINED
;
3427 targ
->insn_type
= ITYPE_LABEL
;
3428 targ
->is_specific_opcode
= FALSE
;
3429 /* Literal with no ops is a label? */
3430 assert (op
== NULL
);
3441 /* Return TRUE on success. */
3444 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3446 for (; bi
!= NULL
; bi
= bi
->next
)
3448 TInsn
*next_insn
= istack_push_space (istack
);
3450 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3457 /* Return TRUE on valid expansion. */
3460 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3462 int stack_size
= istack
->ninsn
;
3463 int steps_taken
= 0;
3464 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3467 assert (insn
->insn_type
== ITYPE_INSN
);
3468 assert (insn
->opcode
< table
->num_opcodes
);
3470 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3472 TransitionRule
*rule
= l
->rule
;
3474 if (xg_instruction_matches_rule (insn
, rule
))
3476 if (lateral_steps
== steps_taken
)
3480 /* This is it. Expand the rule to the stack. */
3481 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3484 /* Check to see if it fits. */
3485 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3487 TInsn
*insn
= &istack
->insn
[i
];
3489 if (insn
->insn_type
== ITYPE_INSN
3490 && !tinsn_has_symbolic_operands (insn
)
3491 && !xg_immeds_fit (insn
))
3493 istack
->ninsn
= stack_size
;
3506 /* Relax the assembly instruction at least "min_steps".
3507 Return the number of steps taken.
3509 For relaxation to correctly terminate, every relaxation chain must
3510 terminate in one of two ways:
3512 1. If the chain from one instruction to the next consists entirely of
3513 single instructions, then the chain *must* handle all possible
3514 immediates without failing. It must not ever fail because an
3515 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3516 chain is one example. L32R loads 32 bits, and there cannot be an
3517 immediate larger than 32 bits, so it satisfies this condition.
3518 Single instruction relaxation chains are as defined by
3519 xg_is_single_relaxable_instruction.
3521 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3522 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3524 Strictly speaking, in most cases you can violate condition 1 and be OK
3525 -- in particular when the last two instructions have the same single
3526 size. But nevertheless, you should guarantee the above two conditions.
3528 We could fix this so that single-instruction expansions correctly
3529 terminate when they can't handle the range, but the error messages are
3530 worse, and it actually turns out that in every case but one (18-bit wide
3531 branches), you need a multi-instruction expansion to get the full range
3532 anyway. And because 18-bit branches are handled identically to 15-bit
3533 branches, there isn't any point in changing it. */
3536 xg_assembly_relax (IStack
*istack
,
3539 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3540 offsetT pc_offset
, /* offset in fragment */
3541 int min_steps
, /* minimum conversion steps */
3542 long stretch
) /* number of bytes stretched so far */
3544 int steps_taken
= 0;
3546 /* Some of its immeds don't fit. Try to build a relaxed version.
3547 This may go through a couple of stages of single instruction
3548 transformations before we get there. */
3550 TInsn single_target
;
3552 int lateral_steps
= 0;
3553 int istack_size
= istack
->ninsn
;
3555 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3556 && steps_taken
>= min_steps
)
3558 istack_push (istack
, insn
);
3561 current_insn
= *insn
;
3563 /* Walk through all of the single instruction expansions. */
3564 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3567 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3570 if (steps_taken
>= min_steps
)
3572 istack_push (istack
, &single_target
);
3576 current_insn
= single_target
;
3579 /* Now check for a multi-instruction expansion. */
3580 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3582 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3585 if (steps_taken
>= min_steps
)
3587 istack_push (istack
, ¤t_insn
);
3592 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3594 if (steps_taken
>= min_steps
)
3598 istack
->ninsn
= istack_size
;
3601 /* It's not going to work -- use the original. */
3602 istack_push (istack
, insn
);
3608 xg_finish_frag (char *last_insn
,
3609 enum xtensa_relax_statesE frag_state
,
3610 enum xtensa_relax_statesE slot0_state
,
3612 bfd_boolean is_insn
)
3614 /* Finish off this fragment so that it has at LEAST the desired
3615 max_growth. If it doesn't fit in this fragment, close this one
3616 and start a new one. In either case, return a pointer to the
3617 beginning of the growth area. */
3621 frag_grow (max_growth
);
3622 old_frag
= frag_now
;
3624 frag_now
->fr_opcode
= last_insn
;
3626 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3628 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3629 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3631 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3632 xtensa_set_frag_assembly_state (frag_now
);
3634 /* Just to make sure that we did not split it up. */
3635 assert (old_frag
->fr_next
== frag_now
);
3639 /* Return TRUE if the target frag is one of the next non-empty frags. */
3642 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3647 for (; fragP
; fragP
= fragP
->fr_next
)
3649 if (fragP
== target
)
3651 if (fragP
->fr_fix
!= 0)
3653 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3655 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3656 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3658 if (fragP
->fr_type
== rs_space
)
3666 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3668 xtensa_isa isa
= xtensa_default_isa
;
3670 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3675 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3676 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3679 for (i
= 0; i
< num_ops
; i
++)
3681 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3687 if (target_op
== -1)
3690 if (insn
->ntok
<= target_op
)
3693 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3696 sym
= insn
->tok
[target_op
].X_add_symbol
;
3700 if (insn
->tok
[target_op
].X_add_number
!= 0)
3703 target_frag
= symbol_get_frag (sym
);
3704 if (target_frag
== NULL
)
3707 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3708 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3716 xg_add_branch_and_loop_targets (TInsn
*insn
)
3718 xtensa_isa isa
= xtensa_default_isa
;
3719 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3721 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3724 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3725 && insn
->tok
[i
].X_op
== O_symbol
)
3726 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3730 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3731 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3735 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3737 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3738 && insn
->tok
[i
].X_op
== O_symbol
)
3740 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3741 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3742 if (S_IS_DEFINED (sym
))
3743 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3750 /* Return FALSE if no error. */
3753 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3758 switch (instr_spec
->typ
)
3761 new_insn
->insn_type
= ITYPE_INSN
;
3762 new_insn
->opcode
= instr_spec
->opcode
;
3764 case INSTR_LITERAL_DEF
:
3765 new_insn
->insn_type
= ITYPE_LITERAL
;
3766 new_insn
->opcode
= XTENSA_UNDEFINED
;
3768 case INSTR_LABEL_DEF
:
3771 new_insn
->is_specific_opcode
= FALSE
;
3772 new_insn
->debug_line
= old_insn
->debug_line
;
3773 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3775 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3778 const expressionS
*src_exp
;
3784 /* The expression must be the constant. */
3785 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3786 exp
= &new_insn
->tok
[b_op
->op_num
];
3787 set_expr_const (exp
, b_op
->op_data
);
3791 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3792 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3793 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3794 exp
= &new_insn
->tok
[b_op
->op_num
];
3795 copy_expr (exp
, src_exp
);
3800 as_bad (_("can't handle generation of literal/labels yet"));
3804 as_bad (_("can't handle undefined OP TYPE"));
3809 new_insn
->ntok
= num_ops
;
3814 /* Return TRUE if it was simplified. */
3817 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3819 TransitionRule
*rule
;
3820 BuildInstr
*insn_spec
;
3822 if (old_insn
->is_specific_opcode
|| !density_supported
)
3825 rule
= xg_instruction_match (old_insn
);
3829 insn_spec
= rule
->to_instr
;
3830 /* There should only be one. */
3831 assert (insn_spec
!= NULL
);
3832 assert (insn_spec
->next
== NULL
);
3833 if (insn_spec
->next
!= NULL
)
3836 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3842 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3843 l32i.n. (2) Check the number of operands. (3) Place the instruction
3844 tokens into the stack or relax it and place multiple
3845 instructions/literals onto the stack. Return FALSE if no error. */
3848 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3852 bfd_boolean do_expand
;
3854 tinsn_init (&new_insn
);
3856 /* Narrow it if we can. xg_simplify_insn now does all the
3857 appropriate checking (e.g., for the density option). */
3858 if (xg_simplify_insn (orig_insn
, &new_insn
))
3859 orig_insn
= &new_insn
;
3861 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3863 if (orig_insn
->ntok
< noperands
)
3865 as_bad (_("found %d operands for '%s': Expected %d"),
3867 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3871 if (orig_insn
->ntok
> noperands
)
3872 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3874 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3877 /* If there are not enough operands, we will assert above. If there
3878 are too many, just cut out the extras here. */
3879 orig_insn
->ntok
= noperands
;
3881 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3884 /* Special case for extui opcode which has constraints not handled
3885 by the ordinary operand encoding checks. The number of operands
3886 and related syntax issues have already been checked. */
3887 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3889 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3890 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3891 if (shiftimm
+ maskimm
> 32)
3893 as_bad (_("immediate operands sum to greater than 32"));
3898 /* If the instruction will definitely need to be relaxed, it is better
3899 to expand it now for better scheduling. Decide whether to expand
3901 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3903 /* Calls should be expanded to longcalls only in the backend relaxation
3904 so that the assembly scheduler will keep the L32R/CALLX instructions
3906 if (is_direct_call_opcode (orig_insn
->opcode
))
3909 if (tinsn_has_symbolic_operands (orig_insn
))
3911 /* The values of symbolic operands are not known yet, so only expand
3912 now if an operand is "complex" (e.g., difference of symbols) and
3913 will have to be stored as a literal regardless of the value. */
3914 if (!tinsn_has_complex_operands (orig_insn
))
3917 else if (xg_immeds_fit (orig_insn
))
3921 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3923 istack_push (istack
, orig_insn
);
3929 /* Return TRUE if the section flags are marked linkonce
3930 or the name is .gnu.linkonce.*. */
3932 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3935 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3937 flagword flags
, link_once_flags
;
3939 flags
= bfd_get_section_flags (abfd
, sec
);
3940 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3942 /* Flags might not be set yet. */
3943 if (!link_once_flags
3944 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3945 link_once_flags
= SEC_LINK_ONCE
;
3947 return (link_once_flags
!= 0);
3952 xtensa_add_literal_sym (symbolS
*sym
)
3956 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3958 l
->next
= literal_syms
;
3964 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3966 static int lit_num
= 0;
3967 static char name
[256];
3970 sprintf (name
, ".L_lit_sym%d", lit_num
);
3972 /* Create a local symbol. If it is in a linkonce section, we have to
3973 be careful to make sure that if it is used in a relocation that the
3974 symbol will be in the output file. */
3975 if (get_is_linkonce_section (stdoutput
, sec
))
3977 symbolP
= symbol_new (name
, sec
, 0, frag
);
3978 S_CLEAR_EXTERNAL (symbolP
);
3979 /* symbolP->local = 1; */
3982 symbolP
= symbol_new (name
, sec
, 0, frag
);
3984 xtensa_add_literal_sym (symbolP
);
3991 /* Currently all literals that are generated here are 32-bit L32R targets. */
3994 xg_assemble_literal (/* const */ TInsn
*insn
)
3997 symbolS
*lit_sym
= NULL
;
3998 bfd_reloc_code_real_type reloc
;
3999 bfd_boolean pcrel
= FALSE
;
4002 /* size = 4 for L32R. It could easily be larger when we move to
4003 larger constants. Add a parameter later. */
4004 offsetT litsize
= 4;
4005 offsetT litalign
= 2; /* 2^2 = 4 */
4006 expressionS saved_loc
;
4007 expressionS
* emit_val
;
4009 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4011 assert (insn
->insn_type
== ITYPE_LITERAL
);
4012 assert (insn
->ntok
== 1); /* must be only one token here */
4014 xtensa_switch_to_literal_fragment (&state
);
4016 emit_val
= &insn
->tok
[0];
4017 if (emit_val
->X_op
== O_big
)
4019 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4022 /* This happens when someone writes a "movi a2, big_number". */
4023 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4024 _("invalid immediate"));
4025 xtensa_restore_emit_state (&state
);
4030 /* Force a 4-byte align here. Note that this opens a new frag, so all
4031 literals done with this function have a frag to themselves. That's
4032 important for the way text section literals work. */
4033 frag_align (litalign
, 0, 0);
4034 record_alignment (now_seg
, litalign
);
4036 switch (emit_val
->X_op
)
4042 p
= frag_more (litsize
);
4043 xtensa_set_frag_assembly_state (frag_now
);
4044 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4045 if (emit_val
->X_add_symbol
)
4046 emit_val
->X_op
= O_symbol
;
4048 emit_val
->X_op
= O_constant
;
4049 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4050 litsize
, emit_val
, pcrel
, reloc
);
4054 emit_expr (emit_val
, litsize
);
4058 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4059 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4060 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4061 lit_sym
= frag_now
->fr_symbol
;
4064 xtensa_restore_emit_state (&state
);
4070 xg_assemble_literal_space (/* const */ int size
, int slot
)
4073 /* We might have to do something about this alignment. It only
4074 takes effect if something is placed here. */
4075 offsetT litalign
= 2; /* 2^2 = 4 */
4076 fragS
*lit_saved_frag
;
4078 assert (size
% 4 == 0);
4080 xtensa_switch_to_literal_fragment (&state
);
4082 /* Force a 4-byte align here. */
4083 frag_align (litalign
, 0, 0);
4084 record_alignment (now_seg
, litalign
);
4088 lit_saved_frag
= frag_now
;
4089 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4090 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4091 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4094 xtensa_restore_emit_state (&state
);
4095 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4099 /* Put in a fixup record based on the opcode.
4100 Return TRUE on success. */
4103 xg_add_opcode_fix (TInsn
*tinsn
,
4111 xtensa_opcode opcode
= tinsn
->opcode
;
4112 bfd_reloc_code_real_type reloc
;
4113 reloc_howto_type
*howto
;
4117 reloc
= BFD_RELOC_NONE
;
4119 /* First try the special cases for "alternate" relocs. */
4120 if (opcode
== xtensa_l32r_opcode
)
4122 if (fragP
->tc_frag_data
.use_absolute_literals
)
4123 reloc
= encode_alt_reloc (slot
);
4125 else if (opcode
== xtensa_const16_opcode
)
4127 if (expr
->X_op
== O_lo16
)
4129 reloc
= encode_reloc (slot
);
4130 expr
->X_op
= O_symbol
;
4132 else if (expr
->X_op
== O_hi16
)
4134 reloc
= encode_alt_reloc (slot
);
4135 expr
->X_op
= O_symbol
;
4139 if (opnum
!= get_relaxable_immed (opcode
))
4141 as_bad (_("invalid relocation for operand %i of '%s'"),
4142 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4146 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4147 into the symbol table where the generic portions of the assembler
4148 won't know what to do with them. */
4149 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4151 as_bad (_("invalid expression for operand %i of '%s'"),
4152 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4156 /* Next try the generic relocs. */
4157 if (reloc
== BFD_RELOC_NONE
)
4158 reloc
= encode_reloc (slot
);
4159 if (reloc
== BFD_RELOC_NONE
)
4161 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4165 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4168 as_bad (_("undefined symbol for opcode \"%s\""),
4169 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4173 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4174 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4175 howto
->pc_relative
, reloc
);
4176 the_fix
->fx_no_overflow
= 1;
4177 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4178 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4179 the_fix
->tc_fix_data
.slot
= slot
;
4186 xg_emit_insn_to_buf (TInsn
*tinsn
,
4190 bfd_boolean build_fix
)
4192 static xtensa_insnbuf insnbuf
= NULL
;
4193 bfd_boolean has_symbolic_immed
= FALSE
;
4194 bfd_boolean ok
= TRUE
;
4197 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4199 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4200 if (has_symbolic_immed
&& build_fix
)
4203 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4204 int slot
= xg_get_single_slot (tinsn
->opcode
);
4205 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4206 expressionS
*exp
= &tinsn
->tok
[opnum
];
4208 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4211 fragP
->tc_frag_data
.is_insn
= TRUE
;
4212 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4213 (unsigned char *) buf
, 0);
4219 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4221 symbolS
*sym
= get_special_literal_symbol ();
4225 assert (insn
->insn_type
== ITYPE_INSN
);
4226 for (i
= 0; i
< insn
->ntok
; i
++)
4227 if (insn
->tok
[i
].X_add_symbol
== sym
)
4228 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4234 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4236 symbolS
*sym
= get_special_label_symbol ();
4238 for (i
= 0; i
< insn
->ntok
; i
++)
4239 if (insn
->tok
[i
].X_add_symbol
== sym
)
4240 insn
->tok
[i
].X_add_symbol
= label_sym
;
4245 /* Return TRUE if the instruction can write to the specified
4246 integer register. */
4249 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4253 xtensa_isa isa
= xtensa_default_isa
;
4255 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4257 for (i
= 0; i
< num_ops
; i
++)
4260 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4261 if ((inout
== 'o' || inout
== 'm')
4262 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4264 xtensa_regfile opnd_rf
=
4265 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4266 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4268 if ((insn
->tok
[i
].X_op
== O_register
)
4269 && (insn
->tok
[i
].X_add_number
== regnum
))
4279 is_bad_loopend_opcode (const TInsn
*tinsn
)
4281 xtensa_opcode opcode
= tinsn
->opcode
;
4283 if (opcode
== XTENSA_UNDEFINED
)
4286 if (opcode
== xtensa_call0_opcode
4287 || opcode
== xtensa_callx0_opcode
4288 || opcode
== xtensa_call4_opcode
4289 || opcode
== xtensa_callx4_opcode
4290 || opcode
== xtensa_call8_opcode
4291 || opcode
== xtensa_callx8_opcode
4292 || opcode
== xtensa_call12_opcode
4293 || opcode
== xtensa_callx12_opcode
4294 || opcode
== xtensa_isync_opcode
4295 || opcode
== xtensa_ret_opcode
4296 || opcode
== xtensa_ret_n_opcode
4297 || opcode
== xtensa_retw_opcode
4298 || opcode
== xtensa_retw_n_opcode
4299 || opcode
== xtensa_waiti_opcode
4300 || opcode
== xtensa_rsr_lcount_opcode
)
4307 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4308 This allows the debugger to add unaligned labels.
4309 Also, the assembler generates stabs labels that need
4310 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4313 is_unaligned_label (symbolS
*sym
)
4315 const char *name
= S_GET_NAME (sym
);
4316 static size_t fake_size
= 0;
4320 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4323 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4325 fake_size
= strlen (FAKE_LABEL_NAME
);
4328 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4329 && (name
[fake_size
] == 'F'
4330 || name
[fake_size
] == 'L'
4331 || (name
[fake_size
] == 'e'
4332 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4340 next_non_empty_frag (const fragS
*fragP
)
4342 fragS
*next_fragP
= fragP
->fr_next
;
4344 /* Sometimes an empty will end up here due storage allocation issues.
4345 So we have to skip until we find something legit. */
4346 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4347 next_fragP
= next_fragP
->fr_next
;
4349 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4357 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4359 xtensa_opcode out_opcode
;
4360 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4362 if (next_fragP
== NULL
)
4365 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4366 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4368 *opcode
= out_opcode
;
4376 frag_format_size (const fragS
*fragP
)
4378 static xtensa_insnbuf insnbuf
= NULL
;
4379 xtensa_isa isa
= xtensa_default_isa
;
4384 insnbuf
= xtensa_insnbuf_alloc (isa
);
4387 return XTENSA_UNDEFINED
;
4389 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4390 (unsigned char *) fragP
->fr_literal
, 0);
4392 fmt
= xtensa_format_decode (isa
, insnbuf
);
4393 if (fmt
== XTENSA_UNDEFINED
)
4394 return XTENSA_UNDEFINED
;
4395 fmt_size
= xtensa_format_length (isa
, fmt
);
4397 /* If the next format won't be changing due to relaxation, just
4398 return the length of the first format. */
4399 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4402 /* If during relaxation we have to pull an instruction out of a
4403 multi-slot instruction, we will return the more conservative
4404 number. This works because alignment on bigger instructions
4405 is more restrictive than alignment on smaller instructions.
4406 This is more conservative than we would like, but it happens
4409 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4412 /* If we aren't doing one of our own relaxations or it isn't
4413 slot-based, then the insn size won't change. */
4414 if (fragP
->fr_type
!= rs_machine_dependent
)
4416 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4419 /* If an instruction is about to grow, return the longer size. */
4420 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4421 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4422 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4424 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4425 instruction in the relaxed version is of length 3. (The case
4426 where we have to pull the instruction out of a FLIX bundle
4427 is handled conservatively above.) However, frags with opcodes
4428 that are expanding to wide branches end up having formats that
4429 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4430 we can't tell directly what format the relaxer picked. This
4431 is a wart in the design of the relaxer that should someday be
4432 fixed, but would require major changes, or at least should
4433 be accompanied by major changes to make use of that data.
4435 In any event, we can tell that we are expanding from a single-slot
4436 three-byte format to a wider one with the logic below. */
4438 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4439 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4444 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4445 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4452 next_frag_format_size (const fragS
*fragP
)
4454 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4455 return frag_format_size (next_fragP
);
4459 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4460 required two-byte instructions to be treated as three-byte instructions
4461 for loop instruction alignment. This restriction was removed beginning
4462 with Xtensa LX. Now the only requirement on loop instruction alignment
4463 is that the first instruction of the loop must appear at an address that
4464 does not cross a fetch boundary. */
4467 get_loop_align_size (int insn_size
)
4469 if (insn_size
== XTENSA_UNDEFINED
)
4470 return xtensa_fetch_width
;
4472 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4479 /* If the next legit fragment is an end-of-loop marker,
4480 switch its state so it will instantiate a NOP. */
4483 update_next_frag_state (fragS
*fragP
)
4485 fragS
*next_fragP
= fragP
->fr_next
;
4486 fragS
*new_target
= NULL
;
4490 /* We are guaranteed there will be one of these... */
4491 while (!(next_fragP
->fr_type
== rs_machine_dependent
4492 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4493 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4494 next_fragP
= next_fragP
->fr_next
;
4496 assert (next_fragP
->fr_type
== rs_machine_dependent
4497 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4498 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4500 /* ...and one of these. */
4501 new_target
= next_fragP
->fr_next
;
4502 while (!(new_target
->fr_type
== rs_machine_dependent
4503 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4504 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4505 new_target
= new_target
->fr_next
;
4507 assert (new_target
->fr_type
== rs_machine_dependent
4508 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4509 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4512 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4514 if (next_fragP
->fr_type
== rs_machine_dependent
4515 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4517 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4521 next_fragP
= next_fragP
->fr_next
;
4527 next_frag_is_branch_target (const fragS
*fragP
)
4529 /* Sometimes an empty will end up here due to storage allocation issues,
4530 so we have to skip until we find something legit. */
4531 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4533 if (fragP
->tc_frag_data
.is_branch_target
)
4535 if (fragP
->fr_fix
!= 0)
4543 next_frag_is_loop_target (const fragS
*fragP
)
4545 /* Sometimes an empty will end up here due storage allocation issues.
4546 So we have to skip until we find something legit. */
4547 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4549 if (fragP
->tc_frag_data
.is_loop_target
)
4551 if (fragP
->fr_fix
!= 0)
4559 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4561 const fragS
*next_fragp
= fragp
->fr_next
;
4562 xtensa_opcode next_opcode
;
4564 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4567 /* Sometimes an empty will end up here due to storage allocation issues,
4568 so we have to skip until we find something legit. */
4569 while (next_fragp
->fr_fix
== 0)
4570 next_fragp
= next_fragp
->fr_next
;
4572 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4575 /* There is some implicit knowledge encoded in here.
4576 The LOOP instructions that are NOT RELAX_IMMED have
4577 been relaxed. Note that we can assume that the LOOP
4578 instruction is in slot 0 because loops aren't bundleable. */
4579 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4580 return get_expanded_loop_offset (next_opcode
);
4586 /* Mark a location where we can later insert literal frags. Update
4587 the section's literal_pool_loc, so subsequent literals can be
4588 placed nearest to their use. */
4591 xtensa_mark_literal_pool_location (void)
4593 /* Any labels pointing to the current location need
4594 to be adjusted to after the literal pool. */
4596 fragS
*pool_location
;
4598 if (use_literal_section
)
4601 /* We stash info in these frags so we can later move the literal's
4602 fixes into this frchain's fix list. */
4603 pool_location
= frag_now
;
4604 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4605 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4606 frag_variant (rs_machine_dependent
, 0, 0,
4607 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4608 xtensa_set_frag_assembly_state (frag_now
);
4609 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4610 frag_variant (rs_machine_dependent
, 0, 0,
4611 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4612 xtensa_set_frag_assembly_state (frag_now
);
4614 /* Now put a frag into the literal pool that points to this location. */
4615 set_literal_pool_location (now_seg
, pool_location
);
4616 xtensa_switch_to_non_abs_literal_fragment (&s
);
4617 frag_align (2, 0, 0);
4618 record_alignment (now_seg
, 2);
4620 /* Close whatever frag is there. */
4621 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4622 xtensa_set_frag_assembly_state (frag_now
);
4623 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4624 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4625 xtensa_restore_emit_state (&s
);
4626 xtensa_set_frag_assembly_state (frag_now
);
4630 /* Build a nop of the correct size into tinsn. */
4633 build_nop (TInsn
*tinsn
, int size
)
4639 tinsn
->opcode
= xtensa_nop_n_opcode
;
4641 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4642 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4646 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4648 tinsn
->opcode
= xtensa_or_opcode
;
4649 set_expr_const (&tinsn
->tok
[0], 1);
4650 set_expr_const (&tinsn
->tok
[1], 1);
4651 set_expr_const (&tinsn
->tok
[2], 1);
4655 tinsn
->opcode
= xtensa_nop_opcode
;
4657 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4662 /* Assemble a NOP of the requested size in the buffer. User must have
4663 allocated "buf" with at least "size" bytes. */
4666 assemble_nop (int size
, char *buf
)
4668 static xtensa_insnbuf insnbuf
= NULL
;
4671 build_nop (&tinsn
, size
);
4674 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4676 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4677 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4678 (unsigned char *) buf
, 0);
4682 /* Return the number of bytes for the offset of the expanded loop
4683 instruction. This should be incorporated into the relaxation
4684 specification but is hard-coded here. This is used to auto-align
4685 the loop instruction. It is invalid to call this function if the
4686 configuration does not have loops or if the opcode is not a loop
4690 get_expanded_loop_offset (xtensa_opcode opcode
)
4692 /* This is the OFFSET of the loop instruction in the expanded loop.
4693 This MUST correspond directly to the specification of the loop
4694 expansion. It will be validated on fragment conversion. */
4695 assert (opcode
!= XTENSA_UNDEFINED
);
4696 if (opcode
== xtensa_loop_opcode
)
4698 if (opcode
== xtensa_loopnez_opcode
)
4700 if (opcode
== xtensa_loopgtz_opcode
)
4702 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4708 get_literal_pool_location (segT seg
)
4710 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4715 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4717 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4721 /* Set frag assembly state should be called when a new frag is
4722 opened and after a frag has been closed. */
4725 xtensa_set_frag_assembly_state (fragS
*fragP
)
4727 if (!density_supported
)
4728 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4730 /* This function is called from subsegs_finish, which is called
4731 after xtensa_end, so we can't use "use_transform" or
4732 "use_schedule" here. */
4733 if (!directive_state
[directive_transform
])
4734 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4735 if (directive_state
[directive_longcalls
])
4736 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4737 fragP
->tc_frag_data
.use_absolute_literals
=
4738 directive_state
[directive_absolute_literals
];
4739 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4744 relaxable_section (asection
*sec
)
4746 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4747 && strcmp (sec
->name
, ".eh_frame") != 0);
4752 xtensa_mark_frags_for_org (void)
4756 /* Walk over each fragment of all of the current segments. If we find
4757 a .org frag in any of the segments, mark all frags prior to it as
4758 "no transform", which will prevent linker optimizations from messing
4759 up the .org distance. This should be done after
4760 xtensa_find_unmarked_state_frags, because we don't want to worry here
4761 about that function trashing the data we save here. */
4763 for (seclist
= &stdoutput
->sections
;
4764 seclist
&& *seclist
;
4765 seclist
= &(*seclist
)->next
)
4767 segT sec
= *seclist
;
4768 segment_info_type
*seginfo
;
4771 flags
= bfd_get_section_flags (stdoutput
, sec
);
4772 if (flags
& SEC_DEBUGGING
)
4774 if (!(flags
& SEC_ALLOC
))
4777 seginfo
= seg_info (sec
);
4778 if (seginfo
&& seginfo
->frchainP
)
4780 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4781 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4782 fragP
= fragP
->fr_next
)
4784 /* cvt_frag_to_fill has changed the fr_type of org frags to
4785 rs_fill, so use the value as cached in rs_subtype here. */
4786 if (fragP
->fr_subtype
== RELAX_ORG
)
4788 while (last_fragP
!= fragP
->fr_next
)
4790 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4791 last_fragP
= last_fragP
->fr_next
;
4801 xtensa_find_unmarked_state_frags (void)
4805 /* Walk over each fragment of all of the current segments. For each
4806 unmarked fragment, mark it with the same info as the previous
4808 for (seclist
= &stdoutput
->sections
;
4809 seclist
&& *seclist
;
4810 seclist
= &(*seclist
)->next
)
4812 segT sec
= *seclist
;
4813 segment_info_type
*seginfo
;
4816 flags
= bfd_get_section_flags (stdoutput
, sec
);
4817 if (flags
& SEC_DEBUGGING
)
4819 if (!(flags
& SEC_ALLOC
))
4822 seginfo
= seg_info (sec
);
4823 if (seginfo
&& seginfo
->frchainP
)
4825 fragS
*last_fragP
= 0;
4826 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4827 fragP
= fragP
->fr_next
)
4829 if (fragP
->fr_fix
!= 0
4830 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4832 if (last_fragP
== 0)
4834 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4835 _("assembly state not set for first frag in section %s"),
4840 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4841 fragP
->tc_frag_data
.is_no_density
=
4842 last_fragP
->tc_frag_data
.is_no_density
;
4843 fragP
->tc_frag_data
.is_no_transform
=
4844 last_fragP
->tc_frag_data
.is_no_transform
;
4845 fragP
->tc_frag_data
.use_longcalls
=
4846 last_fragP
->tc_frag_data
.use_longcalls
;
4847 fragP
->tc_frag_data
.use_absolute_literals
=
4848 last_fragP
->tc_frag_data
.use_absolute_literals
;
4851 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4860 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4862 void *unused ATTRIBUTE_UNUSED
)
4864 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4865 segment_info_type
*seginfo
= seg_info (sec
);
4866 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4868 if (flags
& SEC_CODE
)
4870 xtensa_isa isa
= xtensa_default_isa
;
4871 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4872 while (frag
!= NULL
)
4874 if (frag
->tc_frag_data
.is_branch_target
)
4877 addressT branch_align
, frag_addr
;
4880 xtensa_insnbuf_from_chars
4881 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4882 fmt
= xtensa_format_decode (isa
, insnbuf
);
4883 op_size
= xtensa_format_length (isa
, fmt
);
4884 branch_align
= 1 << branch_align_power (sec
);
4885 frag_addr
= frag
->fr_address
% branch_align
;
4886 if (frag_addr
+ op_size
> branch_align
)
4887 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4888 _("unaligned branch target: %d bytes at 0x%lx"),
4889 op_size
, (long) frag
->fr_address
);
4891 frag
= frag
->fr_next
;
4893 xtensa_insnbuf_free (isa
, insnbuf
);
4899 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4901 void *unused ATTRIBUTE_UNUSED
)
4903 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4904 segment_info_type
*seginfo
= seg_info (sec
);
4905 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4906 xtensa_isa isa
= xtensa_default_isa
;
4908 if (flags
& SEC_CODE
)
4910 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4911 while (frag
!= NULL
)
4913 if (frag
->tc_frag_data
.is_first_loop_insn
)
4919 xtensa_insnbuf_from_chars
4920 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4921 fmt
= xtensa_format_decode (isa
, insnbuf
);
4922 op_size
= xtensa_format_length (isa
, fmt
);
4923 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4925 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4926 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4927 _("unaligned loop: %d bytes at 0x%lx"),
4928 op_size
, (long) frag
->fr_address
);
4930 frag
= frag
->fr_next
;
4932 xtensa_insnbuf_free (isa
, insnbuf
);
4938 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4940 xtensa_isa isa
= xtensa_default_isa
;
4941 static xtensa_insnbuf insnbuf
= NULL
;
4942 static xtensa_insnbuf slotbuf
= NULL
;
4945 bfd_boolean alt_reloc
;
4946 xtensa_opcode opcode
;
4947 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4949 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4951 as_fatal (_("unexpected fix"));
4955 insnbuf
= xtensa_insnbuf_alloc (isa
);
4956 slotbuf
= xtensa_insnbuf_alloc (isa
);
4959 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4960 fmt
= xtensa_format_decode (isa
, insnbuf
);
4961 if (fmt
== XTENSA_UNDEFINED
)
4962 as_fatal (_("undecodable fix"));
4963 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4964 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4965 if (opcode
== XTENSA_UNDEFINED
)
4966 as_fatal (_("undecodable fix"));
4968 /* CONST16 immediates are not PC-relative, despite the fact that we
4969 reuse the normal PC-relative operand relocations for the low part
4970 of a CONST16 operand. */
4971 if (opcode
== xtensa_const16_opcode
)
4974 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4975 get_relaxable_immed (opcode
), val
,
4976 fixP
->fx_file
, fixP
->fx_line
);
4978 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4979 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4985 /* External Functions and Other GAS Hooks. */
4988 xtensa_target_format (void)
4990 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4995 xtensa_file_arch_init (bfd
*abfd
)
4997 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5002 md_number_to_chars (char *buf
, valueT val
, int n
)
5004 if (target_big_endian
)
5005 number_to_chars_bigendian (buf
, val
, n
);
5007 number_to_chars_littleendian (buf
, val
, n
);
5011 /* This function is called once, at assembler startup time. It should
5012 set up all the tables, etc. that the MD part of the assembler will
5018 segT current_section
= now_seg
;
5019 int current_subsec
= now_subseg
;
5022 xtensa_default_isa
= xtensa_isa_init (0, 0);
5023 isa
= xtensa_default_isa
;
5027 /* Set up the literal sections. */
5028 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5030 subseg_set (current_section
, current_subsec
);
5032 xg_init_vinsn (&cur_vinsn
);
5034 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5035 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5036 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5037 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5038 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5039 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5040 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5041 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5042 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5043 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5044 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5045 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5046 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5047 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5048 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5049 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5050 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5051 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5052 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5053 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5054 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5055 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5056 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5057 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5058 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5059 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5060 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5061 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5062 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5063 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5065 init_op_placement_info_table ();
5067 /* Set up the assembly state. */
5068 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5069 xtensa_set_frag_assembly_state (frag_now
);
5073 /* TC_INIT_FIX_DATA hook */
5076 xtensa_init_fix_data (fixS
*x
)
5078 x
->tc_fix_data
.slot
= 0;
5079 x
->tc_fix_data
.X_add_symbol
= NULL
;
5080 x
->tc_fix_data
.X_add_number
= 0;
5084 /* tc_frob_label hook */
5087 xtensa_frob_label (symbolS
*sym
)
5091 if (cur_vinsn
.inside_bundle
)
5093 as_bad (_("labels are not valid inside bundles"));
5097 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5099 /* Since the label was already attached to a frag associated with the
5100 previous basic block, it now needs to be reset to the current frag. */
5101 symbol_set_frag (sym
, frag_now
);
5102 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5104 if (generating_literals
)
5105 xtensa_add_literal_sym (sym
);
5107 xtensa_add_insn_label (sym
);
5109 if (symbol_get_tc (sym
)->is_loop_target
)
5111 if ((get_last_insn_flags (now_seg
, now_subseg
)
5112 & FLAG_IS_BAD_LOOPEND
) != 0)
5113 as_bad (_("invalid last instruction for a zero-overhead loop"));
5115 xtensa_set_frag_assembly_state (frag_now
);
5116 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5117 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 xtensa_move_labels (frag_now
, 0);
5123 /* No target aligning in the absolute section. */
5124 if (now_seg
!= absolute_section
5125 && do_align_targets ()
5126 && !is_unaligned_label (sym
)
5127 && !generating_literals
)
5129 xtensa_set_frag_assembly_state (frag_now
);
5131 frag_var (rs_machine_dependent
,
5133 RELAX_DESIRE_ALIGN_IF_TARGET
,
5134 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5135 xtensa_set_frag_assembly_state (frag_now
);
5136 xtensa_move_labels (frag_now
, 0);
5139 /* We need to mark the following properties even if we aren't aligning. */
5141 /* If the label is already known to be a branch target, i.e., a
5142 forward branch, mark the frag accordingly. Backward branches
5143 are handled by xg_add_branch_and_loop_targets. */
5144 if (symbol_get_tc (sym
)->is_branch_target
)
5145 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5147 /* Loops only go forward, so they can be identified here. */
5148 if (symbol_get_tc (sym
)->is_loop_target
)
5149 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5151 dwarf2_emit_label (sym
);
5155 /* tc_unrecognized_line hook */
5158 xtensa_unrecognized_line (int ch
)
5163 if (cur_vinsn
.inside_bundle
== 0)
5165 /* PR8110: Cannot emit line number info inside a FLIX bundle
5166 when using --gstabs. Temporarily disable debug info. */
5167 generate_lineno_debug ();
5168 if (debug_type
== DEBUG_STABS
)
5170 xt_saved_debug_type
= debug_type
;
5171 debug_type
= DEBUG_NONE
;
5174 cur_vinsn
.inside_bundle
= 1;
5178 as_bad (_("extra opening brace"));
5184 if (cur_vinsn
.inside_bundle
)
5185 finish_vinsn (&cur_vinsn
);
5188 as_bad (_("extra closing brace"));
5193 as_bad (_("syntax error"));
5200 /* md_flush_pending_output hook */
5203 xtensa_flush_pending_output (void)
5205 /* This line fixes a bug where automatically generated gstabs info
5206 separates a function label from its entry instruction, ending up
5207 with the literal position between the function label and the entry
5208 instruction and crashing code. It only happens with --gstabs and
5209 --text-section-literals, and when several other obscure relaxation
5210 conditions are met. */
5211 if (outputting_stabs_line_debug
)
5214 if (cur_vinsn
.inside_bundle
)
5215 as_bad (_("missing closing brace"));
5217 /* If there is a non-zero instruction fragment, close it. */
5218 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5220 frag_wane (frag_now
);
5222 xtensa_set_frag_assembly_state (frag_now
);
5224 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5226 xtensa_clear_insn_labels ();
5230 /* We had an error while parsing an instruction. The string might look
5231 like this: "insn arg1, arg2 }". If so, we need to see the closing
5232 brace and reset some fields. Otherwise, the vinsn never gets closed
5233 and the num_slots field will grow past the end of the array of slots,
5234 and bad things happen. */
5237 error_reset_cur_vinsn (void)
5239 if (cur_vinsn
.inside_bundle
)
5241 if (*input_line_pointer
== '}'
5242 || *(input_line_pointer
- 1) == '}'
5243 || *(input_line_pointer
- 2) == '}')
5244 xg_clear_vinsn (&cur_vinsn
);
5250 md_assemble (char *str
)
5252 xtensa_isa isa
= xtensa_default_isa
;
5255 bfd_boolean has_underbar
= FALSE
;
5256 char *arg_strings
[MAX_INSN_ARGS
];
5258 TInsn orig_insn
; /* Original instruction from the input. */
5260 tinsn_init (&orig_insn
);
5262 /* Split off the opcode. */
5263 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5264 opname
= xmalloc (opnamelen
+ 1);
5265 memcpy (opname
, str
, opnamelen
);
5266 opname
[opnamelen
] = '\0';
5268 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5271 as_bad (_("syntax error"));
5275 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5278 /* Check for an underbar prefix. */
5281 has_underbar
= TRUE
;
5285 orig_insn
.insn_type
= ITYPE_INSN
;
5287 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5289 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5290 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5292 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5293 if (fmt
== XTENSA_UNDEFINED
)
5295 as_bad (_("unknown opcode or format name '%s'"), opname
);
5296 error_reset_cur_vinsn ();
5299 if (!cur_vinsn
.inside_bundle
)
5301 as_bad (_("format names only valid inside bundles"));
5302 error_reset_cur_vinsn ();
5305 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5306 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5308 cur_vinsn
.format
= fmt
;
5309 free (has_underbar
? opname
- 1 : opname
);
5310 error_reset_cur_vinsn ();
5314 /* Parse the arguments. */
5315 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5317 as_bad (_("syntax error"));
5318 error_reset_cur_vinsn ();
5322 /* Free the opcode and argument strings, now that they've been parsed. */
5323 free (has_underbar
? opname
- 1 : opname
);
5325 while (num_args
-- > 0)
5326 free (arg_strings
[num_args
]);
5328 /* Get expressions for invisible operands. */
5329 if (get_invisible_operands (&orig_insn
))
5331 error_reset_cur_vinsn ();
5335 /* Check for the right number and type of arguments. */
5336 if (tinsn_check_arguments (&orig_insn
))
5338 error_reset_cur_vinsn ();
5342 /* Record the line number for each TInsn, because a FLIX bundle may be
5343 spread across multiple input lines and individual instructions may be
5344 moved around in some cases. */
5345 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5346 dwarf2_where (&orig_insn
.debug_line
);
5347 dwarf2_consume_line_info ();
5349 xg_add_branch_and_loop_targets (&orig_insn
);
5351 /* Check that immediate value for ENTRY is >= 16. */
5352 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5354 expressionS
*exp
= &orig_insn
.tok
[2];
5355 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5356 as_warn (_("entry instruction with stack decrement < 16"));
5360 assemble_tokens (opcode, tok, ntok);
5361 expand the tokens from the orig_insn into the
5362 stack of instructions that will not expand
5363 unless required at relaxation time. */
5365 if (!cur_vinsn
.inside_bundle
)
5366 emit_single_op (&orig_insn
);
5367 else /* We are inside a bundle. */
5369 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5370 cur_vinsn
.num_slots
++;
5371 if (*input_line_pointer
== '}'
5372 || *(input_line_pointer
- 1) == '}'
5373 || *(input_line_pointer
- 2) == '}')
5374 finish_vinsn (&cur_vinsn
);
5377 /* We've just emitted a new instruction so clear the list of labels. */
5378 xtensa_clear_insn_labels ();
5382 /* HANDLE_ALIGN hook */
5384 /* For a .align directive, we mark the previous block with the alignment
5385 information. This will be placed in the object file in the
5386 property section corresponding to this section. */
5389 xtensa_handle_align (fragS
*fragP
)
5392 && ! fragP
->tc_frag_data
.is_literal
5393 && (fragP
->fr_type
== rs_align
5394 || fragP
->fr_type
== rs_align_code
)
5395 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5396 && fragP
->fr_offset
> 0
5397 && now_seg
!= bss_section
)
5399 fragP
->tc_frag_data
.is_align
= TRUE
;
5400 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5403 if (fragP
->fr_type
== rs_align_test
)
5406 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5408 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5409 _("unaligned entry instruction"));
5412 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5413 fragP
->fr_subtype
= RELAX_ORG
;
5417 /* TC_FRAG_INIT hook */
5420 xtensa_frag_init (fragS
*frag
)
5422 xtensa_set_frag_assembly_state (frag
);
5427 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5433 /* Round up a section size to the appropriate boundary. */
5436 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5438 return size
; /* Byte alignment is fine. */
5443 md_pcrel_from (fixS
*fixP
)
5446 static xtensa_insnbuf insnbuf
= NULL
;
5447 static xtensa_insnbuf slotbuf
= NULL
;
5450 xtensa_opcode opcode
;
5453 xtensa_isa isa
= xtensa_default_isa
;
5454 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5455 bfd_boolean alt_reloc
;
5457 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5460 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5465 insnbuf
= xtensa_insnbuf_alloc (isa
);
5466 slotbuf
= xtensa_insnbuf_alloc (isa
);
5469 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5470 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5471 fmt
= xtensa_format_decode (isa
, insnbuf
);
5473 if (fmt
== XTENSA_UNDEFINED
)
5474 as_fatal (_("bad instruction format"));
5476 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5477 as_fatal (_("invalid relocation"));
5479 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5480 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5482 /* Check for "alternate" relocations (operand not specified). None
5483 of the current uses for these are really PC-relative. */
5484 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5486 if (opcode
!= xtensa_l32r_opcode
5487 && opcode
!= xtensa_const16_opcode
)
5488 as_fatal (_("invalid relocation for '%s' instruction"),
5489 xtensa_opcode_name (isa
, opcode
));
5493 opnum
= get_relaxable_immed (opcode
);
5495 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5496 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5498 as_bad_where (fixP
->fx_file
,
5500 _("invalid relocation for operand %d of '%s'"),
5501 opnum
, xtensa_opcode_name (isa
, opcode
));
5504 return 0 - opnd_value
;
5508 /* TC_FORCE_RELOCATION hook */
5511 xtensa_force_relocation (fixS
*fix
)
5513 switch (fix
->fx_r_type
)
5515 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5516 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5517 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5518 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5519 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5520 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5521 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5522 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5523 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5524 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5525 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5526 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5527 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5528 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5529 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5530 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5536 if (linkrelax
&& fix
->fx_addsy
5537 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5540 return generic_force_reloc (fix
);
5544 /* TC_VALIDATE_FIX_SUB hook */
5547 xtensa_validate_fix_sub (fixS
*fix
)
5549 segT add_symbol_segment
, sub_symbol_segment
;
5551 /* The difference of two symbols should be resolved by the assembler when
5552 linkrelax is not set. If the linker may relax the section containing
5553 the symbols, then an Xtensa DIFF relocation must be generated so that
5554 the linker knows to adjust the difference value. */
5555 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5558 /* Make sure both symbols are in the same segment, and that segment is
5559 "normal" and relaxable. If the segment is not "normal", then the
5560 fix is not valid. If the segment is not "relaxable", then the fix
5561 should have been handled earlier. */
5562 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5563 if (! SEG_NORMAL (add_symbol_segment
) ||
5564 ! relaxable_section (add_symbol_segment
))
5566 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5567 return (sub_symbol_segment
== add_symbol_segment
);
5571 /* NO_PSEUDO_DOT hook */
5573 /* This function has nothing to do with pseudo dots, but this is the
5574 nearest macro to where the check needs to take place. FIXME: This
5578 xtensa_check_inside_bundle (void)
5580 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5581 as_bad (_("directives are not valid inside bundles"));
5583 /* This function must always return FALSE because it is called via a
5584 macro that has nothing to do with bundling. */
5589 /* md_elf_section_change_hook */
5592 xtensa_elf_section_change_hook (void)
5594 /* Set up the assembly state. */
5595 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5596 xtensa_set_frag_assembly_state (frag_now
);
5600 /* tc_fix_adjustable hook */
5603 xtensa_fix_adjustable (fixS
*fixP
)
5605 /* An offset is not allowed in combination with the difference of two
5606 symbols, but that cannot be easily detected after a local symbol
5607 has been adjusted to a (section+offset) form. Return 0 so that such
5608 an fix will not be adjusted. */
5609 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5610 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5613 /* We need the symbol name for the VTABLE entries. */
5614 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5615 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5622 /* tc_symbol_new_hook */
5624 symbolS
*expr_symbols
= NULL
;
5627 xtensa_symbol_new_hook (symbolS
*sym
)
5629 if (S_GET_SEGMENT (sym
) == expr_section
)
5631 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5638 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5640 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5643 /* Subtracted symbols are only allowed for a few relocation types, and
5644 unless linkrelax is enabled, they should not make it to this point. */
5645 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5646 || fixP
->fx_r_type
== BFD_RELOC_16
5647 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5650 switch (fixP
->fx_r_type
)
5652 case BFD_RELOC_32_PCREL
:
5658 switch (fixP
->fx_r_type
)
5661 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5664 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5667 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5673 /* An offset is only allowed when it results from adjusting a
5674 local symbol into a section-relative offset. If the offset
5675 came from the original expression, tc_fix_adjustable will have
5676 prevented the fix from being converted to a section-relative
5677 form so that we can flag the error here. */
5678 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5679 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5680 _("cannot represent subtraction with an offset"));
5682 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5683 - S_GET_VALUE (fixP
->fx_subsy
));
5685 /* The difference value gets written out, and the DIFF reloc
5686 identifies the address of the subtracted symbol (i.e., the one
5687 with the lowest address). */
5689 fixP
->fx_offset
-= val
;
5690 fixP
->fx_subsy
= NULL
;
5692 else if (! fixP
->fx_addsy
)
5699 case BFD_RELOC_XTENSA_PLT
:
5700 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5701 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5704 case BFD_RELOC_XTENSA_SLOT0_OP
:
5705 case BFD_RELOC_XTENSA_SLOT1_OP
:
5706 case BFD_RELOC_XTENSA_SLOT2_OP
:
5707 case BFD_RELOC_XTENSA_SLOT3_OP
:
5708 case BFD_RELOC_XTENSA_SLOT4_OP
:
5709 case BFD_RELOC_XTENSA_SLOT5_OP
:
5710 case BFD_RELOC_XTENSA_SLOT6_OP
:
5711 case BFD_RELOC_XTENSA_SLOT7_OP
:
5712 case BFD_RELOC_XTENSA_SLOT8_OP
:
5713 case BFD_RELOC_XTENSA_SLOT9_OP
:
5714 case BFD_RELOC_XTENSA_SLOT10_OP
:
5715 case BFD_RELOC_XTENSA_SLOT11_OP
:
5716 case BFD_RELOC_XTENSA_SLOT12_OP
:
5717 case BFD_RELOC_XTENSA_SLOT13_OP
:
5718 case BFD_RELOC_XTENSA_SLOT14_OP
:
5721 /* Write the tentative value of a PC-relative relocation to a
5722 local symbol into the instruction. The value will be ignored
5723 by the linker, and it makes the object file disassembly
5724 readable when all branch targets are encoded in relocations. */
5726 assert (fixP
->fx_addsy
);
5727 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5728 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5730 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5731 - md_pcrel_from (fixP
));
5732 (void) xg_apply_fix_value (fixP
, val
);
5735 else if (! fixP
->fx_addsy
)
5738 if (xg_apply_fix_value (fixP
, val
))
5743 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5744 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5745 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5746 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5747 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5748 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5749 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5750 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5751 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5752 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5753 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5754 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5755 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5756 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5757 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5758 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5759 /* These all need to be resolved at link-time. Do nothing now. */
5762 case BFD_RELOC_VTABLE_INHERIT
:
5763 case BFD_RELOC_VTABLE_ENTRY
:
5768 as_bad (_("unhandled local relocation fix %s"),
5769 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5775 md_atof (int type
, char *litP
, int *sizeP
)
5777 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5782 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5784 return total_frag_text_expansion (fragP
);
5788 /* Translate internal representation of relocation info to BFD target
5792 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5796 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5797 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5798 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5799 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5801 /* Make sure none of our internal relocations make it this far.
5802 They'd better have been fully resolved by this point. */
5803 assert ((int) fixp
->fx_r_type
> 0);
5805 reloc
->addend
= fixp
->fx_offset
;
5807 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5808 if (reloc
->howto
== NULL
)
5810 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5811 _("cannot represent `%s' relocation in object file"),
5812 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5813 free (reloc
->sym_ptr_ptr
);
5818 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5819 as_fatal (_("internal error; cannot generate `%s' relocation"),
5820 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5826 /* Checks for resource conflicts between instructions. */
5828 /* The func unit stuff could be implemented as bit-vectors rather
5829 than the iterative approach here. If it ends up being too
5830 slow, we will switch it. */
5833 new_resource_table (void *data
,
5836 unit_num_copies_func uncf
,
5837 opcode_num_units_func onuf
,
5838 opcode_funcUnit_use_unit_func ouuf
,
5839 opcode_funcUnit_use_stage_func ousf
)
5842 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5844 rt
->cycles
= cycles
;
5845 rt
->allocated_cycles
= cycles
;
5847 rt
->unit_num_copies
= uncf
;
5848 rt
->opcode_num_units
= onuf
;
5849 rt
->opcode_unit_use
= ouuf
;
5850 rt
->opcode_unit_stage
= ousf
;
5852 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5853 for (i
= 0; i
< cycles
; i
++)
5854 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5861 clear_resource_table (resource_table
*rt
)
5864 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5865 for (j
= 0; j
< rt
->num_units
; j
++)
5866 rt
->units
[i
][j
] = 0;
5870 /* We never shrink it, just fake it into thinking so. */
5873 resize_resource_table (resource_table
*rt
, int cycles
)
5877 rt
->cycles
= cycles
;
5878 if (cycles
<= rt
->allocated_cycles
)
5881 old_cycles
= rt
->allocated_cycles
;
5882 rt
->allocated_cycles
= cycles
;
5884 rt
->units
= xrealloc (rt
->units
,
5885 rt
->allocated_cycles
* sizeof (unsigned char *));
5886 for (i
= 0; i
< old_cycles
; i
++)
5887 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5888 rt
->num_units
* sizeof (unsigned char));
5889 for (i
= old_cycles
; i
< cycles
; i
++)
5890 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5895 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5898 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5900 for (i
= 0; i
< uses
; i
++)
5902 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5903 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5904 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5905 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5906 if (copies_in_use
>= copies
)
5914 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5917 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5919 for (i
= 0; i
< uses
; i
++)
5921 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5922 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5923 /* Note that this allows resources to be oversubscribed. That's
5924 essential to the way the optional scheduler works.
5925 resources_available reports when a resource is over-subscribed,
5926 so it's easy to tell. */
5927 rt
->units
[stage
+ cycle
][unit
]++;
5933 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5936 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5938 for (i
= 0; i
< uses
; i
++)
5940 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5941 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5942 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5943 rt
->units
[stage
+ cycle
][unit
]--;
5948 /* Wrapper functions make parameterized resource reservation
5952 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5954 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5960 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5962 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5967 /* Note that this function does not check issue constraints, but
5968 solely whether the hardware is available to execute the given
5969 instructions together. It also doesn't check if the tinsns
5970 write the same state, or access the same tieports. That is
5971 checked by check_t1_t2_reads_and_writes. */
5974 resources_conflict (vliw_insn
*vinsn
)
5977 static resource_table
*rt
= NULL
;
5979 /* This is the most common case by far. Optimize it. */
5980 if (vinsn
->num_slots
== 1)
5985 xtensa_isa isa
= xtensa_default_isa
;
5986 rt
= new_resource_table
5987 (isa
, xtensa_isa_num_pipe_stages (isa
),
5988 xtensa_isa_num_funcUnits (isa
),
5989 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5990 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5991 opcode_funcUnit_use_unit
,
5992 opcode_funcUnit_use_stage
);
5995 clear_resource_table (rt
);
5997 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5999 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6001 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6008 /* finish_vinsn, emit_single_op and helper functions. */
6010 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6011 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6012 static void xg_assemble_vliw_tokens (vliw_insn
*);
6015 /* We have reached the end of a bundle; emit into the frag. */
6018 finish_vinsn (vliw_insn
*vinsn
)
6025 if (find_vinsn_conflicts (vinsn
))
6027 xg_clear_vinsn (vinsn
);
6031 /* First, find a format that works. */
6032 if (vinsn
->format
== XTENSA_UNDEFINED
)
6033 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6035 if (vinsn
->format
== XTENSA_UNDEFINED
)
6037 as_where (&file_name
, &line
);
6038 as_bad_where (file_name
, line
,
6039 _("couldn't find a valid instruction format"));
6040 fprintf (stderr
, _(" ops were: "));
6041 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6042 fprintf (stderr
, _(" %s;"),
6043 xtensa_opcode_name (xtensa_default_isa
,
6044 vinsn
->slots
[i
].opcode
));
6045 fprintf (stderr
, _("\n"));
6046 xg_clear_vinsn (vinsn
);
6050 if (vinsn
->num_slots
6051 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6053 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6054 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6055 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6057 xg_clear_vinsn (vinsn
);
6061 if (resources_conflict (vinsn
))
6063 as_where (&file_name
, &line
);
6064 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6065 fprintf (stderr
, " ops were: ");
6066 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6067 fprintf (stderr
, " %s;",
6068 xtensa_opcode_name (xtensa_default_isa
,
6069 vinsn
->slots
[i
].opcode
));
6070 fprintf (stderr
, "\n");
6071 xg_clear_vinsn (vinsn
);
6075 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6077 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6079 symbolS
*lit_sym
= NULL
;
6081 bfd_boolean e
= FALSE
;
6082 bfd_boolean saved_density
= density_supported
;
6084 /* We don't want to narrow ops inside multi-slot bundles. */
6085 if (vinsn
->num_slots
> 1)
6086 density_supported
= FALSE
;
6088 istack_init (&slotstack
);
6089 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6091 vinsn
->slots
[i
].opcode
=
6092 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6094 vinsn
->slots
[i
].ntok
= 0;
6097 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6103 density_supported
= saved_density
;
6107 xg_clear_vinsn (vinsn
);
6111 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6113 TInsn
*insn
= &slotstack
.insn
[j
];
6114 if (insn
->insn_type
== ITYPE_LITERAL
)
6116 assert (lit_sym
== NULL
);
6117 lit_sym
= xg_assemble_literal (insn
);
6121 assert (insn
->insn_type
== ITYPE_INSN
);
6123 xg_resolve_literals (insn
, lit_sym
);
6124 if (j
!= slotstack
.ninsn
- 1)
6125 emit_single_op (insn
);
6129 if (vinsn
->num_slots
> 1)
6131 if (opcode_fits_format_slot
6132 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6135 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6139 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6140 if (vinsn
->format
== XTENSA_UNDEFINED
)
6141 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6143 vinsn
->slots
[i
].opcode
6144 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6147 vinsn
->slots
[i
].ntok
= 0;
6152 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6153 vinsn
->format
= XTENSA_UNDEFINED
;
6158 /* Now check resource conflicts on the modified bundle. */
6159 if (resources_conflict (vinsn
))
6161 as_where (&file_name
, &line
);
6162 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6163 fprintf (stderr
, " ops were: ");
6164 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6165 fprintf (stderr
, " %s;",
6166 xtensa_opcode_name (xtensa_default_isa
,
6167 vinsn
->slots
[i
].opcode
));
6168 fprintf (stderr
, "\n");
6169 xg_clear_vinsn (vinsn
);
6173 /* First, find a format that works. */
6174 if (vinsn
->format
== XTENSA_UNDEFINED
)
6175 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6177 xg_assemble_vliw_tokens (vinsn
);
6179 xg_clear_vinsn (vinsn
);
6183 /* Given an vliw instruction, what conflicts are there in register
6184 usage and in writes to states and queues?
6186 This function does two things:
6187 1. Reports an error when a vinsn contains illegal combinations
6188 of writes to registers states or queues.
6189 2. Marks individual tinsns as not relaxable if the combination
6190 contains antidependencies.
6192 Job 2 handles things like swap semantics in instructions that need
6193 to be relaxed. For example,
6197 normally would be relaxed to
6202 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6204 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6206 then we can't relax it into
6209 { add a0, a1, a0 ; add a2, a0, a4 ; }
6211 because the value of a0 is trashed before the second add can read it. */
6213 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6216 find_vinsn_conflicts (vliw_insn
*vinsn
)
6220 xtensa_isa isa
= xtensa_default_isa
;
6222 assert (!past_xtensa_end
);
6224 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6226 TInsn
*op1
= &vinsn
->slots
[i
];
6227 if (op1
->is_specific_opcode
)
6228 op1
->keep_wide
= TRUE
;
6230 op1
->keep_wide
= FALSE
;
6233 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6235 TInsn
*op1
= &vinsn
->slots
[i
];
6237 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6240 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6244 TInsn
*op2
= &vinsn
->slots
[j
];
6245 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6246 switch (conflict_type
)
6249 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6250 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6251 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6254 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6255 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6256 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6259 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6260 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6261 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6264 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6265 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6266 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6269 /* Everything is OK. */
6272 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6273 || conflict_type
== 'a');
6280 as_bad (_("multiple branches or jumps in the same bundle"));
6288 /* Check how the state used by t1 and t2 relate.
6291 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6292 case B: no relationship between what is read and written (both could
6293 read the same reg though)
6294 case C: t1 writes a register t2 writes (a register conflict within a
6296 case D: t1 writes a state that t2 also writes
6297 case E: t1 writes a tie queue that t2 also writes
6298 case F: two volatile queue accesses
6302 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6304 xtensa_isa isa
= xtensa_default_isa
;
6305 xtensa_regfile t1_regfile
, t2_regfile
;
6307 int t1_base_reg
, t1_last_reg
;
6308 int t2_base_reg
, t2_last_reg
;
6309 char t1_inout
, t2_inout
;
6311 char conflict
= 'b';
6316 bfd_boolean t1_volatile
= FALSE
;
6317 bfd_boolean t2_volatile
= FALSE
;
6319 /* Check registers. */
6320 for (j
= 0; j
< t2
->ntok
; j
++)
6322 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6325 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6326 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6327 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6329 for (i
= 0; i
< t1
->ntok
; i
++)
6331 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6334 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6336 if (t1_regfile
!= t2_regfile
)
6339 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6340 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6342 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6343 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6345 if (t1_inout
== 'm' || t1_inout
== 'o'
6346 || t2_inout
== 'm' || t2_inout
== 'o')
6353 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6354 t1_last_reg
= (t1_base_reg
6355 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6357 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6359 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6361 if (t1_reg
!= t2_reg
)
6364 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6370 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6376 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6384 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6385 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6386 for (j
= 0; j
< t2_states
; j
++)
6388 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6389 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6390 for (i
= 0; i
< t1_states
; i
++)
6392 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6393 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6397 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6403 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6409 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6414 /* Check tieports. */
6415 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6416 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6417 for (j
= 0; j
< t2_interfaces
; j
++)
6419 xtensa_interface t2_int
6420 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6421 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6423 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6424 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6427 for (i
= 0; i
< t1_interfaces
; i
++)
6429 xtensa_interface t1_int
6430 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6431 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6433 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6434 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6437 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6440 if (t1_int
!= t2_int
)
6443 if (t2_inout
== 'i' && t1_inout
== 'o')
6449 if (t1_inout
== 'i' && t2_inout
== 'o')
6455 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6464 static xtensa_format
6465 xg_find_narrowest_format (vliw_insn
*vinsn
)
6467 /* Right now we assume that the ops within the vinsn are properly
6468 ordered for the slots that the programmer wanted them in. In
6469 other words, we don't rearrange the ops in hopes of finding a
6470 better format. The scheduler handles that. */
6472 xtensa_isa isa
= xtensa_default_isa
;
6473 xtensa_format format
;
6474 vliw_insn v_copy
= *vinsn
;
6475 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6477 if (vinsn
->num_slots
== 1)
6478 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6480 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6483 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6487 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6489 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6491 v_copy
.slots
[slot
].opcode
=
6492 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6493 v_copy
.slots
[slot
].ntok
= 0;
6496 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6499 else if (v_copy
.num_slots
> 1)
6502 /* Try the widened version. */
6503 if (!v_copy
.slots
[slot
].keep_wide
6504 && !v_copy
.slots
[slot
].is_specific_opcode
6505 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6507 && opcode_fits_format_slot (widened
.opcode
,
6510 v_copy
.slots
[slot
] = widened
;
6515 if (fit
== v_copy
.num_slots
)
6518 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6519 vinsn
->format
= format
;
6525 if (format
== xtensa_isa_num_formats (isa
))
6526 return XTENSA_UNDEFINED
;
6532 /* Return the additional space needed in a frag
6533 for possible relaxations of any ops in a VLIW insn.
6534 Also fill out the relaxations that might be required of
6535 each tinsn in the vinsn. */
6538 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6540 bfd_boolean finish_frag
= FALSE
;
6541 int extra_space
= 0;
6544 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6546 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6547 if (!tinsn_has_symbolic_operands (tinsn
))
6549 /* A narrow instruction could be widened later to help
6550 alignment issues. */
6551 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6552 && !tinsn
->is_specific_opcode
6553 && vinsn
->num_slots
== 1)
6555 /* Difference in bytes between narrow and wide insns... */
6557 tinsn
->subtype
= RELAX_NARROW
;
6562 if (workaround_b_j_loop_end
6563 && tinsn
->opcode
== xtensa_jx_opcode
6564 && use_transform ())
6566 /* Add 2 of these. */
6567 extra_space
+= 3; /* for the nop size */
6568 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6571 /* Need to assemble it with space for the relocation. */
6572 if (xg_is_relaxable_insn (tinsn
, 0)
6573 && !tinsn
->is_specific_opcode
)
6575 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6576 int max_literal_size
=
6577 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6579 tinsn
->literal_space
= max_literal_size
;
6581 tinsn
->subtype
= RELAX_IMMED
;
6582 extra_space
+= max_size
;
6586 /* A fix record will be added for this instruction prior
6587 to relaxation, so make it end the frag. */
6592 *pfinish_frag
= finish_frag
;
6598 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6600 xtensa_isa isa
= xtensa_default_isa
;
6601 int slot
, chosen_slot
;
6603 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6604 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6605 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6607 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6608 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6610 if (slot
== chosen_slot
)
6611 vinsn
->slots
[slot
] = *tinsn
;
6614 vinsn
->slots
[slot
].opcode
=
6615 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6616 vinsn
->slots
[slot
].ntok
= 0;
6617 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6624 emit_single_op (TInsn
*orig_insn
)
6627 IStack istack
; /* put instructions into here */
6628 symbolS
*lit_sym
= NULL
;
6629 symbolS
*label_sym
= NULL
;
6631 istack_init (&istack
);
6633 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6634 Because the scheduling and bundling characteristics of movi and
6635 l32r or const16 are so different, we can do much better if we relax
6636 it prior to scheduling and bundling, rather than after. */
6637 if ((orig_insn
->opcode
== xtensa_movi_opcode
6638 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6639 && !cur_vinsn
.inside_bundle
6640 && (orig_insn
->tok
[1].X_op
== O_symbol
6641 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6642 && !orig_insn
->is_specific_opcode
&& use_transform ())
6643 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6645 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6648 for (i
= 0; i
< istack
.ninsn
; i
++)
6650 TInsn
*insn
= &istack
.insn
[i
];
6651 switch (insn
->insn_type
)
6654 assert (lit_sym
== NULL
);
6655 lit_sym
= xg_assemble_literal (insn
);
6659 static int relaxed_sym_idx
= 0;
6660 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6661 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6663 assert (label_sym
== NULL
);
6664 label_sym
= symbol_find_or_make (label
);
6673 xg_resolve_literals (insn
, lit_sym
);
6675 xg_resolve_labels (insn
, label_sym
);
6677 bundle_tinsn (insn
, &v
);
6692 total_frag_text_expansion (fragS
*fragP
)
6695 int total_expansion
= 0;
6697 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6698 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6700 return total_expansion
;
6704 /* Emit a vliw instruction to the current fragment. */
6707 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6709 bfd_boolean finish_frag
;
6710 bfd_boolean is_jump
= FALSE
;
6711 bfd_boolean is_branch
= FALSE
;
6712 xtensa_isa isa
= xtensa_default_isa
;
6717 struct dwarf2_line_info debug_line
;
6718 bfd_boolean loc_directive_seen
= FALSE
;
6721 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6723 if (generating_literals
)
6725 static int reported
= 0;
6727 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6728 _("cannot assemble into a literal fragment"));
6735 if (frag_now_fix () != 0
6736 && (! frag_now
->tc_frag_data
.is_insn
6737 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6738 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6739 || (directive_state
[directive_longcalls
]
6740 != frag_now
->tc_frag_data
.use_longcalls
)
6741 || (directive_state
[directive_absolute_literals
]
6742 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6744 frag_wane (frag_now
);
6746 xtensa_set_frag_assembly_state (frag_now
);
6749 if (workaround_a0_b_retw
6750 && vinsn
->num_slots
== 1
6751 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6752 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6753 && use_transform ())
6755 has_a0_b_retw
= TRUE
;
6757 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6758 After the first assembly pass we will check all of them and
6759 add a nop if needed. */
6760 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6761 frag_var (rs_machine_dependent
, 4, 4,
6762 RELAX_ADD_NOP_IF_A0_B_RETW
,
6763 frag_now
->fr_symbol
,
6764 frag_now
->fr_offset
,
6766 xtensa_set_frag_assembly_state (frag_now
);
6767 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6768 frag_var (rs_machine_dependent
, 4, 4,
6769 RELAX_ADD_NOP_IF_A0_B_RETW
,
6770 frag_now
->fr_symbol
,
6771 frag_now
->fr_offset
,
6773 xtensa_set_frag_assembly_state (frag_now
);
6776 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6778 tinsn
= &vinsn
->slots
[slot
];
6780 /* See if the instruction implies an aligned section. */
6781 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6782 record_alignment (now_seg
, 2);
6784 /* Determine the best line number for debug info. */
6785 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6786 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6787 || tinsn
->debug_line
.line
< debug_line
.line
6788 || tinsn
->debug_line
.column
< debug_line
.column
))
6789 debug_line
= tinsn
->debug_line
;
6790 if (tinsn
->loc_directive_seen
)
6791 loc_directive_seen
= TRUE
;
6794 /* Special cases for instructions that force an alignment... */
6795 /* None of these opcodes are bundle-able. */
6796 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6800 /* Remember the symbol that marks the end of the loop in the frag
6801 that marks the start of the loop. This way we can easily find
6802 the end of the loop at the beginning, without adding special code
6803 to mark the loop instructions themselves. */
6804 symbolS
*target_sym
= NULL
;
6805 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6806 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6808 xtensa_set_frag_assembly_state (frag_now
);
6809 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6811 max_fill
= get_text_align_max_fill_size
6812 (get_text_align_power (xtensa_fetch_width
),
6813 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6815 if (use_transform ())
6816 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6817 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6819 frag_var (rs_machine_dependent
, 0, 0,
6820 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6821 xtensa_set_frag_assembly_state (frag_now
);
6824 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6825 && !vinsn
->slots
[0].is_specific_opcode
)
6827 xtensa_mark_literal_pool_location ();
6828 xtensa_move_labels (frag_now
, 0);
6829 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6832 if (vinsn
->num_slots
== 1)
6834 if (workaround_a0_b_retw
&& use_transform ())
6835 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6836 is_register_writer (&vinsn
->slots
[0], "a", 0));
6838 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6839 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6842 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6844 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6846 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6848 /* vinsn_to_insnbuf will produce the error. */
6849 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6851 f
= frag_more (insn_size
+ extra_space
);
6852 xtensa_set_frag_assembly_state (frag_now
);
6853 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6856 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6857 if (vinsn
->format
== XTENSA_UNDEFINED
)
6860 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6862 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6863 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6866 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6868 tinsn
= &vinsn
->slots
[slot
];
6869 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6870 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6871 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6872 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6873 if (tinsn
->literal_space
!= 0)
6874 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6876 if (tinsn
->subtype
== RELAX_NARROW
)
6877 assert (vinsn
->num_slots
== 1);
6878 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6880 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6883 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6884 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6888 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6889 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6893 frag_variant (rs_machine_dependent
,
6894 extra_space
, extra_space
, RELAX_SLOTS
,
6895 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6896 xtensa_set_frag_assembly_state (frag_now
);
6899 /* Special cases for loops:
6900 close_loop_end should be inserted AFTER short_loop.
6901 Make sure that CLOSE loops are processed BEFORE short_loops
6902 when converting them. */
6904 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6905 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6906 && !vinsn
->slots
[0].is_specific_opcode
)
6908 if (workaround_short_loop
&& use_transform ())
6910 maybe_has_short_loop
= TRUE
;
6911 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6912 frag_var (rs_machine_dependent
, 4, 4,
6913 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6914 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6915 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6916 frag_var (rs_machine_dependent
, 4, 4,
6917 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6918 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6921 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6922 loop at least 12 bytes away from another loop's end. */
6923 if (workaround_close_loop_end
&& use_transform ())
6925 maybe_has_close_loop_end
= TRUE
;
6926 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6927 frag_var (rs_machine_dependent
, 12, 12,
6928 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6929 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6933 if (use_transform ())
6937 assert (finish_frag
);
6938 frag_var (rs_machine_dependent
,
6939 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6941 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6942 xtensa_set_frag_assembly_state (frag_now
);
6944 else if (is_branch
&& do_align_targets ())
6946 assert (finish_frag
);
6947 frag_var (rs_machine_dependent
,
6948 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6949 RELAX_MAYBE_UNREACHABLE
,
6950 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6951 xtensa_set_frag_assembly_state (frag_now
);
6952 frag_var (rs_machine_dependent
,
6954 RELAX_MAYBE_DESIRE_ALIGN
,
6955 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6956 xtensa_set_frag_assembly_state (frag_now
);
6960 /* Now, if the original opcode was a call... */
6961 if (do_align_targets ()
6962 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6964 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6965 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6966 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6967 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6968 xtensa_set_frag_assembly_state (frag_now
);
6971 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6973 frag_wane (frag_now
);
6975 xtensa_set_frag_assembly_state (frag_now
);
6980 /* xtensa_end and helper functions. */
6982 static void xtensa_cleanup_align_frags (void);
6983 static void xtensa_fix_target_frags (void);
6984 static void xtensa_mark_narrow_branches (void);
6985 static void xtensa_mark_zcl_first_insns (void);
6986 static void xtensa_mark_difference_of_two_symbols (void);
6987 static void xtensa_fix_a0_b_retw_frags (void);
6988 static void xtensa_fix_b_j_loop_end_frags (void);
6989 static void xtensa_fix_close_loop_end_frags (void);
6990 static void xtensa_fix_short_loop_frags (void);
6991 static void xtensa_sanity_check (void);
6992 static void xtensa_add_config_info (void);
6997 directive_balance ();
6998 xtensa_flush_pending_output ();
7000 past_xtensa_end
= TRUE
;
7002 xtensa_move_literals ();
7004 xtensa_reorder_segments ();
7005 xtensa_cleanup_align_frags ();
7006 xtensa_fix_target_frags ();
7007 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7008 xtensa_fix_a0_b_retw_frags ();
7009 if (workaround_b_j_loop_end
)
7010 xtensa_fix_b_j_loop_end_frags ();
7012 /* "close_loop_end" should be processed BEFORE "short_loop". */
7013 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7014 xtensa_fix_close_loop_end_frags ();
7016 if (workaround_short_loop
&& maybe_has_short_loop
)
7017 xtensa_fix_short_loop_frags ();
7019 xtensa_mark_narrow_branches ();
7020 xtensa_mark_zcl_first_insns ();
7022 xtensa_sanity_check ();
7024 xtensa_add_config_info ();
7029 xtensa_cleanup_align_frags (void)
7034 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7035 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7038 /* Walk over all of the fragments in a subsection. */
7039 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7041 if ((fragP
->fr_type
== rs_align
7042 || fragP
->fr_type
== rs_align_code
7043 || (fragP
->fr_type
== rs_machine_dependent
7044 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7045 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7046 && fragP
->fr_fix
== 0)
7048 fragS
*next
= fragP
->fr_next
;
7051 && next
->fr_fix
== 0
7052 && next
->fr_type
== rs_machine_dependent
7053 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7056 next
= next
->fr_next
;
7059 /* If we don't widen branch targets, then they
7060 will be easier to align. */
7061 if (fragP
->tc_frag_data
.is_branch_target
7062 && fragP
->fr_opcode
== fragP
->fr_literal
7063 && fragP
->fr_type
== rs_machine_dependent
7064 && fragP
->fr_subtype
== RELAX_SLOTS
7065 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7067 if (fragP
->fr_type
== rs_machine_dependent
7068 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7069 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7075 /* Re-process all of the fragments looking to convert all of the
7076 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7077 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7078 Otherwise, convert to a .fill 0. */
7081 xtensa_fix_target_frags (void)
7086 /* When this routine is called, all of the subsections are still intact
7087 so we walk over subsections instead of sections. */
7088 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7089 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7093 /* Walk over all of the fragments in a subsection. */
7094 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7096 if (fragP
->fr_type
== rs_machine_dependent
7097 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7099 if (next_frag_is_branch_target (fragP
))
7100 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7109 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7112 xtensa_mark_narrow_branches (void)
7117 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7118 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7121 /* Walk over all of the fragments in a subsection. */
7122 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7124 if (fragP
->fr_type
== rs_machine_dependent
7125 && fragP
->fr_subtype
== RELAX_SLOTS
7126 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7130 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7131 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7133 if (vinsn
.num_slots
== 1
7134 && xtensa_opcode_is_branch (xtensa_default_isa
,
7135 vinsn
.slots
[0].opcode
) == 1
7136 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7137 && is_narrow_branch_guaranteed_in_range (fragP
,
7140 fragP
->fr_subtype
= RELAX_SLOTS
;
7141 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7142 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7150 /* A branch is typically widened only when its target is out of
7151 range. However, we would like to widen them to align a subsequent
7152 branch target when possible.
7154 Because the branch relaxation code is so convoluted, the optimal solution
7155 (combining the two cases) is difficult to get right in all circumstances.
7156 We therefore go with an "almost as good" solution, where we only
7157 use for alignment narrow branches that definitely will not expand to a
7158 jump and a branch. These functions find and mark these cases. */
7160 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7161 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7162 We start counting beginning with the frag after the 2-byte branch, so the
7163 maximum offset is (4 - 2) + 63 = 65. */
7164 #define MAX_IMMED6 65
7166 static offsetT
unrelaxed_frag_max_size (fragS
*);
7169 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7171 const expressionS
*expr
= &tinsn
->tok
[1];
7172 symbolS
*symbolP
= expr
->X_add_symbol
;
7173 offsetT max_distance
= expr
->X_add_number
;
7176 if (expr
->X_op
!= O_symbol
)
7179 target_frag
= symbol_get_frag (symbolP
);
7181 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7182 if (is_branch_jmp_to_next (tinsn
, fragP
))
7185 /* The branch doesn't branch over it's own frag,
7186 but over the subsequent ones. */
7187 fragP
= fragP
->fr_next
;
7188 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7190 max_distance
+= unrelaxed_frag_max_size (fragP
);
7191 fragP
= fragP
->fr_next
;
7193 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7200 xtensa_mark_zcl_first_insns (void)
7205 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7206 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7209 /* Walk over all of the fragments in a subsection. */
7210 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7212 if (fragP
->fr_type
== rs_machine_dependent
7213 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7214 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7216 /* Find the loop frag. */
7217 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7218 /* Find the first insn frag. */
7219 targ_frag
= next_non_empty_frag (targ_frag
);
7221 /* Of course, sometimes (mostly for toy test cases) a
7222 zero-cost loop instruction is the last in a section. */
7225 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7226 /* Do not widen a frag that is the first instruction of a
7227 zero-cost loop. It makes that loop harder to align. */
7228 if (targ_frag
->fr_type
== rs_machine_dependent
7229 && targ_frag
->fr_subtype
== RELAX_SLOTS
7230 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7233 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7234 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7237 frag_wane (targ_frag
);
7238 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7242 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7250 /* Some difference-of-symbols expressions make it out to the linker. Some
7251 don't. If one does, then the linker can optimize between the two labels.
7252 If it doesn't, then the linker shouldn't. */
7255 xtensa_mark_difference_of_two_symbols (void)
7259 for (expr_sym
= expr_symbols
; expr_sym
;
7260 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7262 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7264 if (expr
->X_op
== O_subtract
)
7266 symbolS
*left
= expr
->X_add_symbol
;
7267 symbolS
*right
= expr
->X_op_symbol
;
7269 /* Difference of two symbols not in the same section
7270 are handled with relocations in the linker. */
7271 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7276 if (symbol_get_frag (left
)->fr_address
7277 <= symbol_get_frag (right
)->fr_address
)
7279 start
= symbol_get_frag (left
);
7280 end
= symbol_get_frag (right
);
7284 start
= symbol_get_frag (right
);
7285 end
= symbol_get_frag (left
);
7289 start
->tc_frag_data
.is_no_transform
= 1;
7290 start
= start
->fr_next
;
7292 while (start
&& start
->fr_address
< end
->fr_address
);
7299 /* Re-process all of the fragments looking to convert all of the
7300 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7301 conditional branch or a retw/retw.n, convert this frag to one that
7302 will generate a NOP. In any case close it off with a .fill 0. */
7304 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7307 xtensa_fix_a0_b_retw_frags (void)
7312 /* When this routine is called, all of the subsections are still intact
7313 so we walk over subsections instead of sections. */
7314 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7315 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7319 /* Walk over all of the fragments in a subsection. */
7320 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7322 if (fragP
->fr_type
== rs_machine_dependent
7323 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7325 if (next_instrs_are_b_retw (fragP
))
7327 if (fragP
->tc_frag_data
.is_no_transform
)
7328 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7330 relax_frag_add_nop (fragP
);
7340 next_instrs_are_b_retw (fragS
*fragP
)
7342 xtensa_opcode opcode
;
7344 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7345 static xtensa_insnbuf insnbuf
= NULL
;
7346 static xtensa_insnbuf slotbuf
= NULL
;
7347 xtensa_isa isa
= xtensa_default_isa
;
7350 bfd_boolean branch_seen
= FALSE
;
7354 insnbuf
= xtensa_insnbuf_alloc (isa
);
7355 slotbuf
= xtensa_insnbuf_alloc (isa
);
7358 if (next_fragP
== NULL
)
7361 /* Check for the conditional branch. */
7362 xtensa_insnbuf_from_chars
7363 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7364 fmt
= xtensa_format_decode (isa
, insnbuf
);
7365 if (fmt
== XTENSA_UNDEFINED
)
7368 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7370 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7371 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7373 branch_seen
= (branch_seen
7374 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7380 offset
+= xtensa_format_length (isa
, fmt
);
7381 if (offset
== next_fragP
->fr_fix
)
7383 next_fragP
= next_non_empty_frag (next_fragP
);
7387 if (next_fragP
== NULL
)
7390 /* Check for the retw/retw.n. */
7391 xtensa_insnbuf_from_chars
7392 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7393 fmt
= xtensa_format_decode (isa
, insnbuf
);
7395 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7396 have no problems. */
7397 if (fmt
== XTENSA_UNDEFINED
7398 || xtensa_format_num_slots (isa
, fmt
) != 1)
7401 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7402 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7404 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7411 /* Re-process all of the fragments looking to convert all of the
7412 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7413 loop end label, convert this frag to one that will generate a NOP.
7414 In any case close it off with a .fill 0. */
7416 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7419 xtensa_fix_b_j_loop_end_frags (void)
7424 /* When this routine is called, all of the subsections are still intact
7425 so we walk over subsections instead of sections. */
7426 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7427 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7431 /* Walk over all of the fragments in a subsection. */
7432 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7434 if (fragP
->fr_type
== rs_machine_dependent
7435 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7437 if (next_instr_is_loop_end (fragP
))
7439 if (fragP
->tc_frag_data
.is_no_transform
)
7440 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7442 relax_frag_add_nop (fragP
);
7452 next_instr_is_loop_end (fragS
*fragP
)
7454 const fragS
*next_fragP
;
7456 if (next_frag_is_loop_target (fragP
))
7459 next_fragP
= next_non_empty_frag (fragP
);
7460 if (next_fragP
== NULL
)
7463 if (!next_frag_is_loop_target (next_fragP
))
7466 /* If the size is >= 3 then there is more than one instruction here.
7467 The hardware bug will not fire. */
7468 if (next_fragP
->fr_fix
> 3)
7475 /* Re-process all of the fragments looking to convert all of the
7476 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7477 not MY loop's loop end within 12 bytes, add enough nops here to
7478 make it at least 12 bytes away. In any case close it off with a
7481 static offsetT min_bytes_to_other_loop_end
7482 (fragS
*, fragS
*, offsetT
);
7485 xtensa_fix_close_loop_end_frags (void)
7490 /* When this routine is called, all of the subsections are still intact
7491 so we walk over subsections instead of sections. */
7492 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7493 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7497 fragS
*current_target
= NULL
;
7499 /* Walk over all of the fragments in a subsection. */
7500 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7502 if (fragP
->fr_type
== rs_machine_dependent
7503 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7504 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7505 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7508 && fragP
->fr_type
== rs_machine_dependent
7509 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7512 int bytes_added
= 0;
7514 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7515 /* Max out at 12. */
7516 min_bytes
= min_bytes_to_other_loop_end
7517 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7519 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7521 if (fragP
->tc_frag_data
.is_no_transform
)
7522 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7525 while (min_bytes
+ bytes_added
7526 < REQUIRED_LOOP_DIVIDING_BYTES
)
7530 if (fragP
->fr_var
< length
)
7531 as_fatal (_("fr_var %lu < length %d"),
7532 (long) fragP
->fr_var
, length
);
7535 assemble_nop (length
,
7536 fragP
->fr_literal
+ fragP
->fr_fix
);
7537 fragP
->fr_fix
+= length
;
7538 fragP
->fr_var
-= length
;
7540 bytes_added
+= length
;
7546 assert (fragP
->fr_type
!= rs_machine_dependent
7547 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7553 static offsetT
unrelaxed_frag_min_size (fragS
*);
7556 min_bytes_to_other_loop_end (fragS
*fragP
,
7557 fragS
*current_target
,
7561 fragS
*current_fragP
;
7563 for (current_fragP
= fragP
;
7565 current_fragP
= current_fragP
->fr_next
)
7567 if (current_fragP
->tc_frag_data
.is_loop_target
7568 && current_fragP
!= current_target
)
7571 offset
+= unrelaxed_frag_min_size (current_fragP
);
7573 if (offset
>= max_size
)
7581 unrelaxed_frag_min_size (fragS
*fragP
)
7583 offsetT size
= fragP
->fr_fix
;
7585 /* Add fill size. */
7586 if (fragP
->fr_type
== rs_fill
)
7587 size
+= fragP
->fr_offset
;
7594 unrelaxed_frag_max_size (fragS
*fragP
)
7596 offsetT size
= fragP
->fr_fix
;
7597 switch (fragP
->fr_type
)
7600 /* Empty frags created by the obstack allocation scheme
7601 end up with type 0. */
7606 size
+= fragP
->fr_offset
;
7614 /* No further adjustments needed. */
7616 case rs_machine_dependent
:
7617 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7618 size
+= fragP
->fr_var
;
7621 /* We had darn well better know how big it is. */
7630 /* Re-process all of the fragments looking to convert all
7631 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7634 1) the instruction size count to the loop end label
7635 is too short (<= 2 instructions),
7636 2) loop has a jump or branch in it
7639 1) workaround_all_short_loops is TRUE
7640 2) The generating loop was a 'loopgtz' or 'loopnez'
7641 3) the instruction size count to the loop end label is too short
7643 then convert this frag (and maybe the next one) to generate a NOP.
7644 In any case close it off with a .fill 0. */
7646 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7647 static bfd_boolean
branch_before_loop_end (fragS
*);
7650 xtensa_fix_short_loop_frags (void)
7655 /* When this routine is called, all of the subsections are still intact
7656 so we walk over subsections instead of sections. */
7657 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7658 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7661 fragS
*current_target
= NULL
;
7662 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7664 /* Walk over all of the fragments in a subsection. */
7665 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7667 if (fragP
->fr_type
== rs_machine_dependent
7668 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7669 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7672 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7673 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7674 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7675 current_opcode
= t_insn
.opcode
;
7676 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7677 current_opcode
) == 1);
7680 if (fragP
->fr_type
== rs_machine_dependent
7681 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7683 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7684 && (branch_before_loop_end (fragP
->fr_next
)
7685 || (workaround_all_short_loops
7686 && current_opcode
!= XTENSA_UNDEFINED
7687 && current_opcode
!= xtensa_loop_opcode
)))
7689 if (fragP
->tc_frag_data
.is_no_transform
)
7690 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7692 relax_frag_add_nop (fragP
);
7701 static int unrelaxed_frag_min_insn_count (fragS
*);
7704 count_insns_to_loop_end (fragS
*base_fragP
,
7705 bfd_boolean count_relax_add
,
7708 fragS
*fragP
= NULL
;
7713 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7715 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7716 if (insn_count
>= max_count
)
7719 if (count_relax_add
)
7721 if (fragP
->fr_type
== rs_machine_dependent
7722 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7724 /* In order to add the appropriate number of
7725 NOPs, we count an instruction for downstream
7728 if (insn_count
>= max_count
)
7738 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7740 xtensa_isa isa
= xtensa_default_isa
;
7741 static xtensa_insnbuf insnbuf
= NULL
;
7745 if (!fragP
->tc_frag_data
.is_insn
)
7749 insnbuf
= xtensa_insnbuf_alloc (isa
);
7751 /* Decode the fixed instructions. */
7752 while (offset
< fragP
->fr_fix
)
7756 xtensa_insnbuf_from_chars
7757 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7758 fmt
= xtensa_format_decode (isa
, insnbuf
);
7760 if (fmt
== XTENSA_UNDEFINED
)
7762 as_fatal (_("undecodable instruction in instruction frag"));
7765 offset
+= xtensa_format_length (isa
, fmt
);
7773 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7776 branch_before_loop_end (fragS
*base_fragP
)
7780 for (fragP
= base_fragP
;
7781 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7782 fragP
= fragP
->fr_next
)
7784 if (unrelaxed_frag_has_b_j (fragP
))
7792 unrelaxed_frag_has_b_j (fragS
*fragP
)
7794 static xtensa_insnbuf insnbuf
= NULL
;
7795 xtensa_isa isa
= xtensa_default_isa
;
7798 if (!fragP
->tc_frag_data
.is_insn
)
7802 insnbuf
= xtensa_insnbuf_alloc (isa
);
7804 /* Decode the fixed instructions. */
7805 while (offset
< fragP
->fr_fix
)
7810 xtensa_insnbuf_from_chars
7811 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7812 fmt
= xtensa_format_decode (isa
, insnbuf
);
7813 if (fmt
== XTENSA_UNDEFINED
)
7816 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7818 xtensa_opcode opcode
=
7819 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7820 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7821 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7824 offset
+= xtensa_format_length (isa
, fmt
);
7830 /* Checks to be made after initial assembly but before relaxation. */
7832 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7833 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7836 xtensa_sanity_check (void)
7843 as_where (&file_name
, &line
);
7844 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7845 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7849 /* Walk over all of the fragments in a subsection. */
7850 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7852 if (fragP
->fr_type
== rs_machine_dependent
7853 && fragP
->fr_subtype
== RELAX_SLOTS
7854 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7856 static xtensa_insnbuf insnbuf
= NULL
;
7859 if (fragP
->fr_opcode
!= NULL
)
7862 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7863 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7864 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7866 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7867 t_insn
.opcode
) == 1)
7869 if (is_empty_loop (&t_insn
, fragP
))
7871 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7872 as_bad (_("invalid empty loop"));
7874 if (!is_local_forward_loop (&t_insn
, fragP
))
7876 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7877 as_bad (_("loop target does not follow "
7878 "loop instruction in section"));
7885 new_logical_line (file_name
, line
);
7889 #define LOOP_IMMED_OPN 1
7891 /* Return TRUE if the loop target is the next non-zero fragment. */
7894 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7896 const expressionS
*expr
;
7900 if (insn
->insn_type
!= ITYPE_INSN
)
7903 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7906 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7909 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7911 if (expr
->X_op
!= O_symbol
)
7914 symbolP
= expr
->X_add_symbol
;
7918 if (symbol_get_frag (symbolP
) == NULL
)
7921 if (S_GET_VALUE (symbolP
) != 0)
7924 /* Walk through the zero-size fragments from this one. If we find
7925 the target fragment, then this is a zero-size loop. */
7927 for (next_fragP
= fragP
->fr_next
;
7929 next_fragP
= next_fragP
->fr_next
)
7931 if (next_fragP
== symbol_get_frag (symbolP
))
7933 if (next_fragP
->fr_fix
!= 0)
7941 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7943 const expressionS
*expr
;
7947 if (insn
->insn_type
!= ITYPE_INSN
)
7950 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7953 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7956 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7958 if (expr
->X_op
!= O_symbol
)
7961 symbolP
= expr
->X_add_symbol
;
7965 if (symbol_get_frag (symbolP
) == NULL
)
7968 /* Walk through fragments until we find the target.
7969 If we do not find the target, then this is an invalid loop. */
7971 for (next_fragP
= fragP
->fr_next
;
7973 next_fragP
= next_fragP
->fr_next
)
7975 if (next_fragP
== symbol_get_frag (symbolP
))
7983 #define XTINFO_NAME "Xtensa_Info"
7984 #define XTINFO_NAMESZ 12
7985 #define XTINFO_TYPE 1
7988 xtensa_add_config_info (void)
7994 info_sec
= subseg_new (".xtensa.info", 0);
7995 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7997 data
= xmalloc (100);
7998 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7999 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8000 sz
= strlen (data
) + 1;
8002 /* Add enough null terminators to pad to a word boundary. */
8005 while ((sz
& 3) != 0);
8007 /* Follow the standard note section layout:
8008 First write the length of the name string. */
8010 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8012 /* Next comes the length of the "descriptor", i.e., the actual data. */
8014 md_number_to_chars (p
, (valueT
) sz
, 4);
8016 /* Write the note type. */
8018 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8020 /* Write the name field. */
8021 p
= frag_more (XTINFO_NAMESZ
);
8022 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8024 /* Finally, write the descriptor. */
8026 memcpy (p
, data
, sz
);
8032 /* Alignment Functions. */
8035 get_text_align_power (unsigned target_size
)
8037 if (target_size
<= 4)
8039 assert (target_size
== 8);
8045 get_text_align_max_fill_size (int align_pow
,
8046 bfd_boolean use_nops
,
8047 bfd_boolean use_no_density
)
8050 return (1 << align_pow
);
8052 return 3 * (1 << align_pow
);
8054 return 1 + (1 << align_pow
);
8058 /* Calculate the minimum bytes of fill needed at "address" to align a
8059 target instruction of size "target_size" so that it does not cross a
8060 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8061 the fill can be an arbitrary number of bytes. Otherwise, the space must
8062 be filled by NOP instructions. */
8065 get_text_align_fill_size (addressT address
,
8068 bfd_boolean use_nops
,
8069 bfd_boolean use_no_density
)
8071 addressT alignment
, fill
, fill_limit
, fill_step
;
8072 bfd_boolean skip_one
= FALSE
;
8074 alignment
= (1 << align_pow
);
8075 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8079 fill_limit
= alignment
;
8082 else if (!use_no_density
)
8084 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8085 fill_limit
= alignment
* 2;
8091 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8092 fill_limit
= alignment
* 3;
8096 /* Try all fill sizes until finding one that works. */
8097 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8099 if (skip_one
&& fill
== 1)
8101 if ((address
+ fill
) >> align_pow
8102 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8111 branch_align_power (segT sec
)
8113 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8114 is aligned to at least an 8-byte boundary, then a branch target need
8115 only fit within an 8-byte aligned block of memory to avoid a stall.
8116 Otherwise, try to fit branch targets within 4-byte aligned blocks
8117 (which may be insufficient, e.g., if the section has no alignment, but
8118 it's good enough). */
8119 if (xtensa_fetch_width
== 8)
8121 if (get_recorded_alignment (sec
) >= 3)
8125 assert (xtensa_fetch_width
== 4);
8131 /* This will assert if it is not possible. */
8134 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8140 assert (fill_size
% 3 == 0);
8141 return (fill_size
/ 3);
8144 assert (fill_size
!= 1); /* Bad argument. */
8146 while (fill_size
> 1)
8149 if (fill_size
== 2 || fill_size
== 4)
8151 fill_size
-= insn_size
;
8154 assert (fill_size
!= 1); /* Bad algorithm. */
8160 get_text_align_nth_nop_size (offsetT fill_size
,
8162 bfd_boolean use_no_density
)
8169 assert (fill_size
!= 1); /* Bad argument. */
8171 while (fill_size
> 1)
8174 if (fill_size
== 2 || fill_size
== 4)
8176 fill_size
-= insn_size
;
8186 /* For the given fragment, find the appropriate address
8187 for it to begin at if we are using NOPs to align it. */
8190 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8192 /* The rule is: get next fragment's FIRST instruction. Find
8193 the smallest number of bytes that need to be added to
8194 ensure that the next fragment's FIRST instruction will fit
8197 E.G., 2 bytes : 0, 1, 2 mod 4
8200 If the FIRST instruction MIGHT be relaxed,
8201 assume that it will become a 3-byte instruction.
8203 Note again here that LOOP instructions are not bundleable,
8204 and this relaxation only applies to LOOP opcodes. */
8207 int first_insn_size
;
8209 addressT pre_opcode_bytes
;
8212 xtensa_opcode opcode
;
8213 bfd_boolean is_loop
;
8215 assert (fragP
->fr_type
== rs_machine_dependent
);
8216 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8218 /* Find the loop frag. */
8219 first_insn
= next_non_empty_frag (fragP
);
8220 /* Now find the first insn frag. */
8221 first_insn
= next_non_empty_frag (first_insn
);
8223 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8225 loop_insn_size
= xg_get_single_size (opcode
);
8227 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8228 pre_opcode_bytes
+= loop_insn_size
;
8230 /* For loops, the alignment depends on the size of the
8231 instruction following the loop, not the LOOP instruction. */
8233 if (first_insn
== NULL
)
8234 first_insn_size
= xtensa_fetch_width
;
8236 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8238 /* If it was 8, then we'll need a larger alignment for the section. */
8239 align_power
= get_text_align_power (first_insn_size
);
8240 record_alignment (now_seg
, align_power
);
8242 fill_size
= get_text_align_fill_size
8243 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8244 fragP
->tc_frag_data
.is_no_density
);
8246 return address
+ fill_size
;
8250 /* 3 mechanisms for relaxing an alignment:
8252 Align to a power of 2.
8253 Align so the next fragment's instruction does not cross a word boundary.
8254 Align the current instruction so that if the next instruction
8255 were 3 bytes, it would not cross a word boundary.
8259 zeros - This is easy; always insert zeros.
8260 nops - 3-byte and 2-byte instructions
8264 >=5 : 3-byte instruction + fn (n-3)
8265 widening - widen previous instructions. */
8268 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8270 addressT target_address
, loop_insn_offset
;
8272 xtensa_opcode loop_opcode
;
8273 bfd_boolean is_loop
;
8276 offsetT branch_align
;
8279 assert (fragP
->fr_type
== rs_machine_dependent
);
8280 switch (fragP
->fr_subtype
)
8282 case RELAX_DESIRE_ALIGN
:
8283 target_size
= next_frag_format_size (fragP
);
8284 if (target_size
== XTENSA_UNDEFINED
)
8286 align_power
= branch_align_power (now_seg
);
8287 branch_align
= 1 << align_power
;
8288 /* Don't count on the section alignment being as large as the target. */
8289 if (target_size
> branch_align
)
8290 target_size
= branch_align
;
8291 opt_diff
= get_text_align_fill_size (address
, align_power
,
8292 target_size
, FALSE
, FALSE
);
8294 *max_diff
= (opt_diff
+ branch_align
8295 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8296 assert (*max_diff
>= opt_diff
);
8299 case RELAX_ALIGN_NEXT_OPCODE
:
8300 /* The next non-empty frag after this one holds the LOOP instruction
8301 that needs to be aligned. The required alignment depends on the
8302 size of the next non-empty frag after the loop frag, i.e., the
8303 first instruction in the loop. */
8304 loop_frag
= next_non_empty_frag (fragP
);
8305 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8306 loop_insn_offset
= 0;
8307 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8310 /* If the loop has been expanded then the LOOP instruction
8311 could be at an offset from this fragment. */
8312 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8313 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8315 /* In an ideal world, which is what we are shooting for here,
8316 we wouldn't need to use any NOPs immediately prior to the
8317 LOOP instruction. If this approach fails, relax_frag_loop_align
8318 will call get_noop_aligned_address. */
8320 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8321 align_power
= get_text_align_power (target_size
);
8322 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8323 target_size
, FALSE
, FALSE
);
8325 *max_diff
= xtensa_fetch_width
8326 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8327 - target_size
+ opt_diff
;
8328 assert (*max_diff
>= opt_diff
);
8339 /* md_relax_frag Hook and Helper Functions. */
8341 static long relax_frag_loop_align (fragS
*, long);
8342 static long relax_frag_for_align (fragS
*, long);
8343 static long relax_frag_immed
8344 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8347 /* Return the number of bytes added to this fragment, given that the
8348 input has been stretched already by "stretch". */
8351 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8353 xtensa_isa isa
= xtensa_default_isa
;
8354 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8355 long new_stretch
= 0;
8359 static xtensa_insnbuf vbuf
= NULL
;
8360 int slot
, num_slots
;
8363 as_where (&file_name
, &line
);
8364 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8366 fragP
->tc_frag_data
.unreported_expansion
= 0;
8368 switch (fragP
->fr_subtype
)
8370 case RELAX_ALIGN_NEXT_OPCODE
:
8371 /* Always convert. */
8372 if (fragP
->tc_frag_data
.relax_seen
)
8373 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8376 case RELAX_LOOP_END
:
8380 case RELAX_LOOP_END_ADD_NOP
:
8381 /* Add a NOP and switch to .fill 0. */
8382 new_stretch
= relax_frag_add_nop (fragP
);
8386 case RELAX_DESIRE_ALIGN
:
8387 /* Do nothing. The narrowing before this frag will either align
8392 case RELAX_LITERAL_FINAL
:
8395 case RELAX_LITERAL_NR
:
8397 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8398 assert (unreported
== lit_size
);
8399 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8400 fragP
->fr_var
-= lit_size
;
8401 fragP
->fr_fix
+= lit_size
;
8407 vbuf
= xtensa_insnbuf_alloc (isa
);
8409 xtensa_insnbuf_from_chars
8410 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8411 fmt
= xtensa_format_decode (isa
, vbuf
);
8412 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8414 for (slot
= 0; slot
< num_slots
; slot
++)
8416 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8419 if (fragP
->tc_frag_data
.relax_seen
)
8420 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8424 case RELAX_IMMED_STEP1
:
8425 case RELAX_IMMED_STEP2
:
8426 case RELAX_IMMED_STEP3
:
8427 /* Place the immediate. */
8428 new_stretch
+= relax_frag_immed
8429 (now_seg
, fragP
, stretch
,
8430 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8431 fmt
, slot
, stretched_p
, FALSE
);
8435 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8441 case RELAX_LITERAL_POOL_BEGIN
:
8442 case RELAX_LITERAL_POOL_END
:
8443 case RELAX_MAYBE_UNREACHABLE
:
8444 case RELAX_MAYBE_DESIRE_ALIGN
:
8445 /* No relaxation required. */
8448 case RELAX_FILL_NOP
:
8449 case RELAX_UNREACHABLE
:
8450 if (fragP
->tc_frag_data
.relax_seen
)
8451 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8455 as_bad (_("bad relaxation state"));
8458 /* Tell gas we need another relaxation pass. */
8459 if (! fragP
->tc_frag_data
.relax_seen
)
8461 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8465 new_logical_line (file_name
, line
);
8471 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8473 addressT old_address
, old_next_address
, old_size
;
8474 addressT new_address
, new_next_address
, new_size
;
8477 /* All the frags with relax_frag_for_alignment prior to this one in the
8478 section have been done, hopefully eliminating the need for a NOP here.
8479 But, this will put it in if necessary. */
8481 /* Calculate the old address of this fragment and the next fragment. */
8482 old_address
= fragP
->fr_address
- stretch
;
8483 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8484 fragP
->tc_frag_data
.text_expansion
[0]);
8485 old_size
= old_next_address
- old_address
;
8487 /* Calculate the new address of this fragment and the next fragment. */
8488 new_address
= fragP
->fr_address
;
8490 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8491 new_size
= new_next_address
- new_address
;
8493 growth
= new_size
- old_size
;
8495 /* Fix up the text_expansion field and return the new growth. */
8496 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8501 /* Add a NOP instruction. */
8504 relax_frag_add_nop (fragS
*fragP
)
8506 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8507 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8508 assemble_nop (length
, nop_buf
);
8509 fragP
->tc_frag_data
.is_insn
= TRUE
;
8511 if (fragP
->fr_var
< length
)
8513 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8517 fragP
->fr_fix
+= length
;
8518 fragP
->fr_var
-= length
;
8523 static long future_alignment_required (fragS
*, long);
8526 relax_frag_for_align (fragS
*fragP
, long stretch
)
8528 /* Overview of the relaxation procedure for alignment:
8529 We can widen with NOPs or by widening instructions or by filling
8530 bytes after jump instructions. Find the opportune places and widen
8531 them if necessary. */
8536 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8537 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8538 || (fragP
->fr_subtype
== RELAX_SLOTS
8539 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8541 stretch_me
= future_alignment_required (fragP
, stretch
);
8542 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8548 /* We expanded on a previous pass. Can we shrink now? */
8549 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8550 if (shrink
<= stretch
&& stretch
> 0)
8552 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8558 /* Below here, diff > 0. */
8559 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8565 /* Return the address of the next frag that should be aligned.
8567 By "address" we mean the address it _would_ be at if there
8568 is no action taken to align it between here and the target frag.
8569 In other words, if no narrows and no fill nops are used between
8570 here and the frag to align, _even_if_ some of the frags we use
8571 to align targets have already expanded on a previous relaxation
8574 Also, count each frag that may be used to help align the target.
8576 Return 0 if there are no frags left in the chain that need to be
8580 find_address_of_next_align_frag (fragS
**fragPP
,
8584 bfd_boolean
*paddable
)
8586 fragS
*fragP
= *fragPP
;
8587 addressT address
= fragP
->fr_address
;
8589 /* Do not reset the counts to 0. */
8593 /* Limit this to a small search. */
8594 if (*widens
>= (int) xtensa_fetch_width
)
8599 address
+= fragP
->fr_fix
;
8601 if (fragP
->fr_type
== rs_fill
)
8602 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8603 else if (fragP
->fr_type
== rs_machine_dependent
)
8605 switch (fragP
->fr_subtype
)
8607 case RELAX_UNREACHABLE
:
8611 case RELAX_FILL_NOP
:
8613 if (!fragP
->tc_frag_data
.is_no_density
)
8618 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8623 address
+= total_frag_text_expansion (fragP
);;
8627 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8630 case RELAX_ALIGN_NEXT_OPCODE
:
8631 case RELAX_DESIRE_ALIGN
:
8635 case RELAX_MAYBE_UNREACHABLE
:
8636 case RELAX_MAYBE_DESIRE_ALIGN
:
8641 /* Just punt if we don't know the type. */
8648 /* Just punt if we don't know the type. */
8652 fragP
= fragP
->fr_next
;
8660 static long bytes_to_stretch (fragS
*, int, int, int, int);
8663 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8665 fragS
*this_frag
= fragP
;
8669 int narrow_nops
= 0;
8670 bfd_boolean paddable
= FALSE
;
8671 offsetT local_opt_diff
;
8674 int stretch_amount
= 0;
8675 int local_stretch_amount
;
8676 int global_stretch_amount
;
8678 address
= find_address_of_next_align_frag
8679 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8683 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8684 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8686 frag_wane (this_frag
);
8690 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8691 opt_diff
= local_opt_diff
;
8692 assert (opt_diff
>= 0);
8693 assert (max_diff
>= opt_diff
);
8698 fragP
= fragP
->fr_next
;
8700 while (fragP
&& opt_diff
< max_diff
&& address
)
8702 /* We only use these to determine if we can exit early
8703 because there will be plenty of ways to align future
8705 int glob_widens
= 0;
8708 bfd_boolean glob_pad
= 0;
8709 address
= find_address_of_next_align_frag
8710 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8711 /* If there is a padable portion, then skip. */
8712 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8717 offsetT next_m_diff
;
8718 offsetT next_o_diff
;
8720 /* Downrange frags haven't had stretch added to them yet. */
8723 /* The address also includes any text expansion from this
8724 frag in a previous pass, but we don't want that. */
8725 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8727 /* Assume we are going to move at least opt_diff. In
8728 reality, we might not be able to, but assuming that
8729 we will helps catch cases where moving opt_diff pushes
8730 the next target from aligned to unaligned. */
8731 address
+= opt_diff
;
8733 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8735 /* Now cleanup for the adjustments to address. */
8736 next_o_diff
+= opt_diff
;
8737 next_m_diff
+= opt_diff
;
8738 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8739 opt_diff
= next_o_diff
;
8740 if (next_m_diff
< max_diff
)
8741 max_diff
= next_m_diff
;
8742 fragP
= fragP
->fr_next
;
8746 /* If there are enough wideners in between, do it. */
8749 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8751 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8756 local_stretch_amount
8757 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8758 num_widens
, local_opt_diff
);
8759 global_stretch_amount
8760 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8761 num_widens
, opt_diff
);
8762 /* If the condition below is true, then the frag couldn't
8763 stretch the correct amount for the global case, so we just
8764 optimize locally. We'll rely on the subsequent frags to get
8765 the correct alignment in the global case. */
8766 if (global_stretch_amount
< local_stretch_amount
)
8767 stretch_amount
= local_stretch_amount
;
8769 stretch_amount
= global_stretch_amount
;
8771 if (this_frag
->fr_subtype
== RELAX_SLOTS
8772 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8773 assert (stretch_amount
<= 1);
8774 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8776 if (this_frag
->tc_frag_data
.is_no_density
)
8777 assert (stretch_amount
== 3 || stretch_amount
== 0);
8779 assert (stretch_amount
<= 3);
8782 return stretch_amount
;
8786 /* The idea: widen everything you can to get a target or loop aligned,
8787 then start using NOPs.
8789 When we must have a NOP, here is a table of how we decide
8790 (so you don't have to fight through the control flow below):
8792 wide_nops = the number of wide NOPs available for aligning
8793 narrow_nops = the number of narrow NOPs available for aligning
8794 (a subset of wide_nops)
8795 widens = the number of narrow instructions that should be widened
8802 b 0 1 1 (case 3a makes this case unnecessary)
8805 c 0 1 2 (case 4a makes this case unnecessary)
8808 c 0 2 1 (case 5b makes this case unnecessary)
8811 c 0 1 4 (case 6b makes this case unnecessary)
8812 d 1 1 1 (case 6a makes this case unnecessary)
8813 e 0 2 2 (case 6a makes this case unnecessary)
8814 f 0 3 0 (case 6a makes this case unnecessary)
8817 c 1 1 2 (case 7b makes this case unnecessary)
8818 d 0 1 5 (case 7a makes this case unnecessary)
8819 e 0 2 3 (case 7b makes this case unnecessary)
8820 f 0 3 1 (case 7b makes this case unnecessary)
8821 g 1 2 1 (case 7b makes this case unnecessary)
8825 bytes_to_stretch (fragS
*this_frag
,
8831 int bytes_short
= desired_diff
- num_widens
;
8833 assert (desired_diff
>= 0 && desired_diff
< 8);
8834 if (desired_diff
== 0)
8837 assert (wide_nops
> 0 || num_widens
> 0);
8839 /* Always prefer widening to NOP-filling. */
8840 if (bytes_short
< 0)
8842 /* There are enough RELAX_NARROW frags after this one
8843 to align the target without widening this frag in any way. */
8847 if (bytes_short
== 0)
8849 /* Widen every narrow between here and the align target
8850 and the align target will be properly aligned. */
8851 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8857 /* From here we will need at least one NOP to get an alignment.
8858 However, we may not be able to align at all, in which case,
8860 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8862 switch (desired_diff
)
8867 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8868 return 2; /* case 2 */
8874 return 3; /* case 3a */
8876 if (num_widens
>= 1 && wide_nops
== 1)
8877 return 3; /* case 4a */
8878 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8879 return 2; /* case 4b */
8882 if (num_widens
>= 2 && wide_nops
== 1)
8883 return 3; /* case 5a */
8884 /* We will need two nops. Are there enough nops
8885 between here and the align target? */
8886 if (wide_nops
< 2 || narrow_nops
== 0)
8888 /* Are there other nops closer that can serve instead? */
8889 if (wide_nops
> 2 && narrow_nops
> 1)
8891 /* Take the density one first, because there might not be
8892 another density one available. */
8893 if (!this_frag
->tc_frag_data
.is_no_density
)
8894 return 2; /* case 5b narrow */
8896 return 3; /* case 5b wide */
8900 return 3; /* case 6a */
8901 else if (num_widens
>= 3 && wide_nops
== 1)
8902 return 3; /* case 6b */
8905 if (wide_nops
== 1 && num_widens
>= 4)
8906 return 3; /* case 7a */
8907 else if (wide_nops
== 2 && num_widens
>= 1)
8908 return 3; /* case 7b */
8916 /* We will need a NOP no matter what, but should we widen
8917 this instruction to help?
8919 This is a RELAX_NARROW frag. */
8920 switch (desired_diff
)
8929 if (wide_nops
>= 1 && num_widens
== 1)
8930 return 1; /* case 4a */
8933 if (wide_nops
>= 1 && num_widens
== 2)
8934 return 1; /* case 5a */
8938 return 0; /* case 6a */
8939 else if (wide_nops
>= 1 && num_widens
== 3)
8940 return 1; /* case 6b */
8943 if (wide_nops
>= 1 && num_widens
== 4)
8944 return 1; /* case 7a */
8945 else if (wide_nops
>= 2 && num_widens
== 1)
8946 return 1; /* case 7b */
8959 relax_frag_immed (segT segP
,
8966 bfd_boolean estimate_only
)
8970 bfd_boolean negatable_branch
= FALSE
;
8971 bfd_boolean branch_jmp_to_next
= FALSE
;
8972 bfd_boolean from_wide_insn
= FALSE
;
8973 xtensa_isa isa
= xtensa_default_isa
;
8975 offsetT frag_offset
;
8978 int num_text_bytes
, num_literal_bytes
;
8979 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8981 assert (fragP
->fr_opcode
!= NULL
);
8983 xg_clear_vinsn (&cur_vinsn
);
8984 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8985 if (cur_vinsn
.num_slots
> 1)
8986 from_wide_insn
= TRUE
;
8988 tinsn
= cur_vinsn
.slots
[slot
];
8989 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8991 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8994 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8995 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8997 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8999 old_size
= xtensa_format_length (isa
, fmt
);
9001 /* Special case: replace a branch to the next instruction with a NOP.
9002 This is required to work around a hardware bug in T1040.0 and also
9003 serves as an optimization. */
9005 if (branch_jmp_to_next
9006 && ((old_size
== 2) || (old_size
== 3))
9007 && !next_frag_is_loop_target (fragP
))
9010 /* Here is the fun stuff: Get the immediate field from this
9011 instruction. If it fits, we are done. If not, find the next
9012 instruction sequence that fits. */
9014 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9015 istack_init (&istack
);
9016 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9017 min_steps
, stretch
);
9018 if (num_steps
< min_steps
)
9020 as_fatal (_("internal error: relaxation failed"));
9024 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9026 as_fatal (_("internal error: relaxation requires too many steps"));
9030 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9032 /* Figure out the number of bytes needed. */
9034 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9036 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9038 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9041 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9045 num_text_bytes
+= old_size
;
9046 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9047 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9050 total_text_diff
= num_text_bytes
- old_size
;
9051 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9053 /* It MUST get larger. If not, we could get an infinite loop. */
9054 assert (num_text_bytes
>= 0);
9055 assert (literal_diff
>= 0);
9056 assert (total_text_diff
>= 0);
9058 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9059 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9060 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9061 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9063 /* Find the associated expandable literal for this. */
9064 if (literal_diff
!= 0)
9066 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9069 assert (literal_diff
== 4);
9070 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9072 /* We expect that the literal section state has NOT been
9074 assert (lit_fragP
->fr_type
== rs_machine_dependent
9075 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9076 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9078 /* We need to mark this section for another iteration
9084 if (negatable_branch
&& istack
.ninsn
> 1)
9085 update_next_frag_state (fragP
);
9087 return this_text_diff
;
9091 /* md_convert_frag Hook and Helper Functions. */
9093 static void convert_frag_align_next_opcode (fragS
*);
9094 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9095 static void convert_frag_fill_nop (fragS
*);
9096 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9099 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9101 static xtensa_insnbuf vbuf
= NULL
;
9102 xtensa_isa isa
= xtensa_default_isa
;
9109 as_where (&file_name
, &line
);
9110 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9112 switch (fragp
->fr_subtype
)
9114 case RELAX_ALIGN_NEXT_OPCODE
:
9115 /* Always convert. */
9116 convert_frag_align_next_opcode (fragp
);
9119 case RELAX_DESIRE_ALIGN
:
9120 /* Do nothing. If not aligned already, too bad. */
9124 case RELAX_LITERAL_FINAL
:
9129 vbuf
= xtensa_insnbuf_alloc (isa
);
9131 xtensa_insnbuf_from_chars
9132 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9133 fmt
= xtensa_format_decode (isa
, vbuf
);
9134 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9136 for (slot
= 0; slot
< num_slots
; slot
++)
9138 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9141 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9145 case RELAX_IMMED_STEP1
:
9146 case RELAX_IMMED_STEP2
:
9147 case RELAX_IMMED_STEP3
:
9148 /* Place the immediate. */
9151 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9156 /* This is OK because some slots could have
9157 relaxations and others have none. */
9163 case RELAX_UNREACHABLE
:
9164 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9165 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9166 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9170 case RELAX_MAYBE_UNREACHABLE
:
9171 case RELAX_MAYBE_DESIRE_ALIGN
:
9175 case RELAX_FILL_NOP
:
9176 convert_frag_fill_nop (fragp
);
9179 case RELAX_LITERAL_NR
:
9180 if (use_literal_section
)
9182 /* This should have been handled during relaxation. When
9183 relaxing a code segment, literals sometimes need to be
9184 added to the corresponding literal segment. If that
9185 literal segment has already been relaxed, then we end up
9186 in this situation. Marking the literal segments as data
9187 would make this happen less often (since GAS always relaxes
9188 code before data), but we could still get into trouble if
9189 there are instructions in a segment that is not marked as
9190 containing code. Until we can implement a better solution,
9191 cheat and adjust the addresses of all the following frags.
9192 This could break subsequent alignments, but the linker's
9193 literal coalescing will do that anyway. */
9196 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9197 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9198 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9201 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9205 as_bad (_("invalid relaxation fragment result"));
9210 new_logical_line (file_name
, line
);
9215 convert_frag_align_next_opcode (fragS
*fragp
)
9217 char *nop_buf
; /* Location for Writing. */
9218 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9219 addressT aligned_address
;
9223 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9225 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9226 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9227 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9229 for (nop
= 0; nop
< nop_count
; nop
++)
9232 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9234 assemble_nop (nop_size
, nop_buf
);
9235 nop_buf
+= nop_size
;
9238 fragp
->fr_fix
+= fill_size
;
9239 fragp
->fr_var
-= fill_size
;
9244 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9246 TInsn tinsn
, single_target
;
9247 int size
, old_size
, diff
;
9248 offsetT frag_offset
;
9251 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9253 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9255 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9256 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9257 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9262 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9264 /* No conversion. */
9269 assert (fragP
->fr_opcode
!= NULL
);
9271 /* Frags in this relaxation state should only contain
9272 single instruction bundles. */
9273 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9275 /* Just convert it to a wide form.... */
9277 old_size
= xg_get_single_size (tinsn
.opcode
);
9279 tinsn_init (&single_target
);
9280 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9282 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9284 as_bad (_("unable to widen instruction"));
9288 size
= xg_get_single_size (single_target
.opcode
);
9289 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9292 diff
= size
- old_size
;
9294 assert (diff
<= fragP
->fr_var
);
9295 fragP
->fr_var
-= diff
;
9296 fragP
->fr_fix
+= diff
;
9304 convert_frag_fill_nop (fragS
*fragP
)
9306 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9307 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9308 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9309 - fragP
->fr_address
- fragP
->fr_fix
));
9312 /* No conversion. */
9316 assemble_nop (size
, loc
);
9317 fragP
->tc_frag_data
.is_insn
= TRUE
;
9318 fragP
->fr_var
-= size
;
9319 fragP
->fr_fix
+= size
;
9324 static fixS
*fix_new_exp_in_seg
9325 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9326 bfd_reloc_code_real_type
);
9327 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9330 convert_frag_immed (segT segP
,
9336 char *immed_instr
= fragP
->fr_opcode
;
9338 bfd_boolean expanded
= FALSE
;
9339 bfd_boolean branch_jmp_to_next
= FALSE
;
9340 char *fr_opcode
= fragP
->fr_opcode
;
9341 xtensa_isa isa
= xtensa_default_isa
;
9342 bfd_boolean from_wide_insn
= FALSE
;
9344 bfd_boolean is_loop
;
9346 assert (fr_opcode
!= NULL
);
9348 xg_clear_vinsn (&cur_vinsn
);
9350 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9351 if (cur_vinsn
.num_slots
> 1)
9352 from_wide_insn
= TRUE
;
9354 orig_tinsn
= cur_vinsn
.slots
[slot
];
9355 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9357 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9359 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9360 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9362 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9364 /* Conversion just inserts a NOP and marks the fix as completed. */
9365 bytes
= xtensa_format_length (isa
, fmt
);
9368 cur_vinsn
.slots
[slot
].opcode
=
9369 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9370 cur_vinsn
.slots
[slot
].ntok
= 0;
9374 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9375 assert (bytes
== 2 || bytes
== 3);
9376 build_nop (&cur_vinsn
.slots
[0], bytes
);
9377 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9379 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9380 xtensa_insnbuf_to_chars
9381 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9386 /* Here is the fun stuff: Get the immediate field from this
9387 instruction. If it fits, we're done. If not, find the next
9388 instruction sequence that fits. */
9392 symbolS
*lit_sym
= NULL
;
9394 int target_offset
= 0;
9397 symbolS
*gen_label
= NULL
;
9398 offsetT frag_offset
;
9399 bfd_boolean first
= TRUE
;
9400 bfd_boolean last_is_jump
;
9402 /* It does not fit. Find something that does and
9403 convert immediately. */
9404 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9405 istack_init (&istack
);
9406 xg_assembly_relax (&istack
, &orig_tinsn
,
9407 segP
, fragP
, frag_offset
, min_steps
, 0);
9409 old_size
= xtensa_format_length (isa
, fmt
);
9411 /* Assemble this right inline. */
9413 /* First, create the mapping from a label name to the REAL label. */
9415 for (i
= 0; i
< istack
.ninsn
; i
++)
9417 TInsn
*tinsn
= &istack
.insn
[i
];
9420 switch (tinsn
->insn_type
)
9423 if (lit_sym
!= NULL
)
9424 as_bad (_("multiple literals in expansion"));
9425 /* First find the appropriate space in the literal pool. */
9426 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9427 if (lit_frag
== NULL
)
9428 as_bad (_("no registered fragment for literal"));
9429 if (tinsn
->ntok
!= 1)
9430 as_bad (_("number of literal tokens != 1"));
9432 /* Set the literal symbol and add a fixup. */
9433 lit_sym
= lit_frag
->fr_symbol
;
9437 if (align_targets
&& !is_loop
)
9439 fragS
*unreach
= fragP
->fr_next
;
9440 while (!(unreach
->fr_type
== rs_machine_dependent
9441 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9442 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9444 unreach
= unreach
->fr_next
;
9447 assert (unreach
->fr_type
== rs_machine_dependent
9448 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9449 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9451 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9453 assert (gen_label
== NULL
);
9454 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9455 fr_opcode
- fragP
->fr_literal
9456 + target_offset
, fragP
);
9460 if (first
&& from_wide_insn
)
9462 target_offset
+= xtensa_format_length (isa
, fmt
);
9464 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9465 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9468 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9475 last_is_jump
= FALSE
;
9476 for (i
= 0; i
< istack
.ninsn
; i
++)
9478 TInsn
*tinsn
= &istack
.insn
[i
];
9482 bfd_reloc_code_real_type reloc_type
;
9484 switch (tinsn
->insn_type
)
9487 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9488 /* Already checked. */
9489 assert (lit_frag
!= NULL
);
9490 assert (lit_sym
!= NULL
);
9491 assert (tinsn
->ntok
== 1);
9493 target_seg
= S_GET_SEGMENT (lit_sym
);
9494 assert (target_seg
);
9495 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9496 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9497 &tinsn
->tok
[0], FALSE
, reloc_type
);
9504 xg_resolve_labels (tinsn
, gen_label
);
9505 xg_resolve_literals (tinsn
, lit_sym
);
9506 if (from_wide_insn
&& first
)
9509 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9511 cur_vinsn
.slots
[slot
] = *tinsn
;
9515 cur_vinsn
.slots
[slot
].opcode
=
9516 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9517 cur_vinsn
.slots
[slot
].ntok
= 0;
9519 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9520 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9521 (unsigned char *) immed_instr
, 0);
9522 fragP
->tc_frag_data
.is_insn
= TRUE
;
9523 size
= xtensa_format_length (isa
, fmt
);
9524 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9527 (tinsn
, immed_instr
+ size
, fragP
,
9528 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9529 size
+= xg_get_single_size (tinsn
->opcode
);
9534 size
= xg_get_single_size (tinsn
->opcode
);
9535 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9536 immed_instr
- fragP
->fr_literal
, TRUE
);
9538 immed_instr
+= size
;
9544 diff
= total_size
- old_size
;
9548 assert (diff
<= fragP
->fr_var
);
9549 fragP
->fr_var
-= diff
;
9550 fragP
->fr_fix
+= diff
;
9553 /* Check for undefined immediates in LOOP instructions. */
9557 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9558 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9560 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9563 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9564 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9566 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9571 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9572 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9574 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9576 /* Add an expansion note on the expanded instruction. */
9577 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9578 &orig_tinsn
.tok
[0], TRUE
,
9579 BFD_RELOC_XTENSA_ASM_EXPAND
);
9584 /* Add a new fix expression into the desired segment. We have to
9585 switch to that segment to do this. */
9588 fix_new_exp_in_seg (segT new_seg
,
9595 bfd_reloc_code_real_type r_type
)
9599 subsegT subseg
= now_subseg
;
9601 assert (new_seg
!= 0);
9602 subseg_set (new_seg
, new_subseg
);
9604 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9605 subseg_set (seg
, subseg
);
9610 /* Relax a loop instruction so that it can span loop >256 bytes.
9616 addi as, as, lo8 (label-.L1)
9617 addmi as, as, mid8 (label-.L1)
9628 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9633 unsigned long target
;
9634 static xtensa_insnbuf insnbuf
= NULL
;
9635 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9636 xtensa_isa isa
= xtensa_default_isa
;
9637 addressT loop_offset
;
9638 addressT addi_offset
= 9;
9639 addressT addmi_offset
= 12;
9644 insnbuf
= xtensa_insnbuf_alloc (isa
);
9646 /* Get the loop offset. */
9647 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9649 /* Validate that there really is a LOOP at the loop_offset. Because
9650 loops are not bundleable, we can assume that the instruction will be
9652 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9653 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9655 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9656 addi_offset
+= loop_offset
;
9657 addmi_offset
+= loop_offset
;
9659 assert (tinsn
->ntok
== 2);
9660 if (tinsn
->tok
[1].X_op
== O_constant
)
9661 target
= tinsn
->tok
[1].X_add_number
;
9662 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9664 /* Find the fragment. */
9665 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9666 assert (S_GET_SEGMENT (sym
) == segP
9667 || S_GET_SEGMENT (sym
) == absolute_section
);
9668 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9672 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9676 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9677 loop_length_hi
= loop_length
& ~0x0ff;
9678 loop_length_lo
= loop_length
& 0x0ff;
9679 if (loop_length_lo
>= 128)
9681 loop_length_lo
-= 256;
9682 loop_length_hi
+= 256;
9685 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9686 32512. If the loop is larger than that, then we just fail. */
9687 if (loop_length_hi
> 32512)
9688 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9689 _("loop too long for LOOP instruction"));
9691 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9692 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9694 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9695 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9697 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9698 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9700 fragP
->tc_frag_data
.is_insn
= TRUE
;
9701 xtensa_insnbuf_to_chars
9702 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9704 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9705 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9706 xtensa_insnbuf_to_chars
9707 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9709 /* Walk through all of the frags from here to the loop end
9710 and mark them as no_transform to keep them from being modified
9711 by the linker. If we ever have a relocation for the
9712 addi/addmi of the difference of two symbols we can remove this. */
9715 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9716 next_fragP
= next_fragP
->fr_next
)
9718 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9719 if (next_fragP
->tc_frag_data
.is_loop_target
)
9721 if (target_count
== 2)
9727 /* A map that keeps information on a per-subsegment basis. This is
9728 maintained during initial assembly, but is invalid once the
9729 subsegments are smashed together. I.E., it cannot be used during
9732 typedef struct subseg_map_struct
9740 float total_freq
; /* fall-through + branch target frequency */
9741 float target_freq
; /* branch target frequency alone */
9743 struct subseg_map_struct
*next
;
9747 static subseg_map
*sseg_map
= NULL
;
9750 get_subseg_info (segT seg
, subsegT subseg
)
9752 subseg_map
*subseg_e
;
9754 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9756 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9764 add_subseg_info (segT seg
, subsegT subseg
)
9766 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9767 memset (subseg_e
, 0, sizeof (subseg_map
));
9768 subseg_e
->seg
= seg
;
9769 subseg_e
->subseg
= subseg
;
9770 subseg_e
->flags
= 0;
9771 /* Start off considering every branch target very important. */
9772 subseg_e
->target_freq
= 1.0;
9773 subseg_e
->total_freq
= 1.0;
9774 subseg_e
->next
= sseg_map
;
9775 sseg_map
= subseg_e
;
9781 get_last_insn_flags (segT seg
, subsegT subseg
)
9783 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9785 return subseg_e
->flags
;
9791 set_last_insn_flags (segT seg
,
9796 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9798 subseg_e
= add_subseg_info (seg
, subseg
);
9800 subseg_e
->flags
|= fl
;
9802 subseg_e
->flags
&= ~fl
;
9807 get_subseg_total_freq (segT seg
, subsegT subseg
)
9809 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9811 return subseg_e
->total_freq
;
9817 get_subseg_target_freq (segT seg
, subsegT subseg
)
9819 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9821 return subseg_e
->target_freq
;
9827 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9829 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9831 subseg_e
= add_subseg_info (seg
, subseg
);
9832 subseg_e
->total_freq
= total_f
;
9833 subseg_e
->target_freq
= target_f
;
9837 /* Segment Lists and emit_state Stuff. */
9840 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9845 segT literal_section
= head
->seg
;
9847 /* Move the literal section to the front of the section list. */
9848 assert (literal_section
);
9849 if (literal_section
!= stdoutput
->sections
)
9851 bfd_section_list_remove (stdoutput
, literal_section
);
9852 bfd_section_list_prepend (stdoutput
, literal_section
);
9859 static void mark_literal_frags (seg_list
*);
9862 xtensa_move_literals (void)
9865 frchainS
*frchain_from
, *frchain_to
;
9866 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9867 fragS
**frag_splice
;
9870 fixS
*fix
, *next_fix
, **fix_splice
;
9873 mark_literal_frags (literal_head
->next
);
9875 if (use_literal_section
)
9878 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9880 /* Keep the literals for .init and .fini in separate sections. */
9881 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9882 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9885 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9886 search_frag
= frchain_from
->frch_root
;
9887 literal_pool
= NULL
;
9889 frag_splice
= &(frchain_from
->frch_root
);
9891 while (!search_frag
->tc_frag_data
.literal_frag
)
9893 assert (search_frag
->fr_fix
== 0
9894 || search_frag
->fr_type
== rs_align
);
9895 search_frag
= search_frag
->fr_next
;
9898 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9899 == RELAX_LITERAL_POOL_BEGIN
);
9900 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9902 /* Make sure that all the frags in this series are closed, and
9903 that there is at least one left over of zero-size. This
9904 prevents us from making a segment with an frchain without any
9906 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9907 xtensa_set_frag_assembly_state (frag_now
);
9908 last_frag
= frag_now
;
9909 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9910 xtensa_set_frag_assembly_state (frag_now
);
9912 while (search_frag
!= frag_now
)
9914 next_frag
= search_frag
->fr_next
;
9916 /* First, move the frag out of the literal section and
9917 to the appropriate place. */
9918 if (search_frag
->tc_frag_data
.literal_frag
)
9920 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9921 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9922 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9923 assert (frchain_to
);
9925 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9926 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9928 *frag_splice
= next_frag
;
9929 search_frag
->fr_next
= insert_after
->fr_next
;
9930 insert_after
->fr_next
= search_frag
;
9931 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9932 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9934 /* Now move any fixups associated with this frag to the
9936 fix
= frchain_from
->fix_root
;
9937 fix_splice
= &(frchain_from
->fix_root
);
9940 next_fix
= fix
->fx_next
;
9941 if (fix
->fx_frag
== search_frag
)
9943 *fix_splice
= next_fix
;
9944 fix
->fx_next
= frchain_to
->fix_root
;
9945 frchain_to
->fix_root
= fix
;
9946 if (frchain_to
->fix_tail
== NULL
)
9947 frchain_to
->fix_tail
= fix
;
9950 fix_splice
= &(fix
->fx_next
);
9953 search_frag
= next_frag
;
9956 if (frchain_from
->fix_root
!= NULL
)
9958 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9959 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9961 assert (frchain_from
->fix_root
== NULL
);
9963 frchain_from
->fix_tail
= NULL
;
9964 xtensa_restore_emit_state (&state
);
9967 /* Now fix up the SEGMENT value for all the literal symbols. */
9968 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9970 symbolS
*lit_sym
= lit
->sym
;
9971 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9973 S_SET_SEGMENT (lit_sym
, dest_seg
);
9978 /* Walk over all the frags for segments in a list and mark them as
9979 containing literals. As clunky as this is, we can't rely on frag_var
9980 and frag_variant to get called in all situations. */
9983 mark_literal_frags (seg_list
*segment
)
9985 frchainS
*frchain_from
;
9990 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9991 search_frag
= frchain_from
->frch_root
;
9994 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9995 search_frag
= search_frag
->fr_next
;
9997 segment
= segment
->next
;
10003 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10005 /* Move all of the sections in the section list to come
10006 after "after" in the gnu segment list. */
10011 segT literal_section
= head
->seg
;
10013 /* Move the literal section after "after". */
10014 assert (literal_section
);
10015 if (literal_section
!= after
)
10017 bfd_section_list_remove (stdoutput
, literal_section
);
10018 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10026 /* Push all the literal segments to the end of the gnu list. */
10029 xtensa_reorder_segments (void)
10036 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10042 /* Now that we have the last section, push all the literal
10043 sections to the end. */
10044 xtensa_reorder_seg_list (literal_head
, last_sec
);
10046 /* Now perform the final error check. */
10047 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10049 assert (new_count
== old_count
);
10053 /* Change the emit state (seg, subseg, and frag related stuff) to the
10054 correct location. Return a emit_state which can be passed to
10055 xtensa_restore_emit_state to return to current fragment. */
10058 xtensa_switch_to_literal_fragment (emit_state
*result
)
10060 if (directive_state
[directive_absolute_literals
])
10062 segT lit4_seg
= cache_literal_section (TRUE
);
10063 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10066 xtensa_switch_to_non_abs_literal_fragment (result
);
10068 /* Do a 4-byte align here. */
10069 frag_align (2, 0, 0);
10070 record_alignment (now_seg
, 2);
10075 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10077 static bfd_boolean recursive
= FALSE
;
10078 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10080 bfd_boolean is_init
=
10081 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10082 bfd_boolean is_fini
=
10083 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10085 if (pool_location
== NULL
10086 && !use_literal_section
10088 && !is_init
&& ! is_fini
)
10090 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10092 /* When we mark a literal pool location, we want to put a frag in
10093 the literal pool that points to it. But to do that, we want to
10094 switch_to_literal_fragment. But literal sections don't have
10095 literal pools, so their location is always null, so we would
10096 recurse forever. This is kind of hacky, but it works. */
10099 xtensa_mark_literal_pool_location ();
10103 lit_seg
= cache_literal_section (FALSE
);
10104 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10106 if (!use_literal_section
10107 && !is_init
&& !is_fini
10108 && get_literal_pool_location (now_seg
) != pool_location
)
10110 /* Close whatever frag is there. */
10111 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10112 xtensa_set_frag_assembly_state (frag_now
);
10113 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10114 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10115 xtensa_set_frag_assembly_state (frag_now
);
10120 /* Call this function before emitting data into the literal section.
10121 This is a helper function for xtensa_switch_to_literal_fragment.
10122 This is similar to a .section new_now_seg subseg. */
10125 xtensa_switch_section_emit_state (emit_state
*state
,
10127 subsegT new_now_subseg
)
10129 state
->name
= now_seg
->name
;
10130 state
->now_seg
= now_seg
;
10131 state
->now_subseg
= now_subseg
;
10132 state
->generating_literals
= generating_literals
;
10133 generating_literals
++;
10134 subseg_set (new_now_seg
, new_now_subseg
);
10138 /* Use to restore the emitting into the normal place. */
10141 xtensa_restore_emit_state (emit_state
*state
)
10143 generating_literals
= state
->generating_literals
;
10144 subseg_set (state
->now_seg
, state
->now_subseg
);
10148 /* Predicate function used to look up a section in a particular group. */
10151 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10153 const char *gname
= inf
;
10154 const char *group_name
= elf_group_name (sec
);
10156 return (group_name
== gname
10157 || (group_name
!= NULL
10159 && strcmp (group_name
, gname
) == 0));
10163 /* Get the literal section to be used for the current text section.
10164 The result may be cached in the default_lit_sections structure. */
10167 cache_literal_section (bfd_boolean use_abs_literals
)
10169 const char *text_name
, *group_name
= 0;
10170 char *base_name
, *name
, *suffix
;
10172 segT seg
, current_section
;
10173 int current_subsec
;
10174 bfd_boolean linkonce
= FALSE
;
10176 /* Save the current section/subsection. */
10177 current_section
= now_seg
;
10178 current_subsec
= now_subseg
;
10180 /* Clear the cached values if they are no longer valid. */
10181 if (now_seg
!= default_lit_sections
.current_text_seg
)
10183 default_lit_sections
.current_text_seg
= now_seg
;
10184 default_lit_sections
.lit_seg
= NULL
;
10185 default_lit_sections
.lit4_seg
= NULL
;
10188 /* Check if the literal section is already cached. */
10189 if (use_abs_literals
)
10190 pcached
= &default_lit_sections
.lit4_seg
;
10192 pcached
= &default_lit_sections
.lit_seg
;
10197 text_name
= default_lit_sections
.lit_prefix
;
10198 if (! text_name
|| ! *text_name
)
10200 text_name
= segment_name (current_section
);
10201 group_name
= elf_group_name (current_section
);
10202 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10205 base_name
= use_abs_literals
? ".lit4" : ".literal";
10208 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10209 sprintf (name
, "%s.%s", base_name
, group_name
);
10211 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10213 suffix
= strchr (text_name
+ linkonce_len
, '.');
10215 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10216 + (suffix
? strlen (suffix
) : 0));
10217 strcpy (name
, ".gnu.linkonce");
10218 strcat (name
, base_name
);
10220 strcat (name
, suffix
);
10225 /* If the section name ends with ".text", then replace that suffix
10226 instead of appending an additional suffix. */
10227 size_t len
= strlen (text_name
);
10228 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10231 name
= xmalloc (len
+ strlen (base_name
) + 1);
10232 strcpy (name
, text_name
);
10233 strcpy (name
+ len
, base_name
);
10236 /* Canonicalize section names to allow renaming literal sections.
10237 The group name, if any, came from the current text section and
10238 has already been canonicalized. */
10239 name
= tc_canonicalize_symbol_name (name
);
10241 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10242 (void *) group_name
);
10247 seg
= subseg_force_new (name
, 0);
10249 if (! use_abs_literals
)
10251 /* Add the newly created literal segment to the list. */
10252 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10254 n
->next
= literal_head
->next
;
10255 literal_head
->next
= n
;
10258 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10259 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10260 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10262 elf_group_name (seg
) = group_name
;
10264 bfd_set_section_flags (stdoutput
, seg
, flags
);
10265 bfd_set_section_alignment (stdoutput
, seg
, 2);
10269 subseg_set (current_section
, current_subsec
);
10274 /* Property Tables Stuff. */
10276 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10277 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10278 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10280 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10281 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10283 static bfd_boolean
get_frag_is_literal (const fragS
*);
10284 static void xtensa_create_property_segments
10285 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10286 static void xtensa_create_xproperty_segments
10287 (frag_flags_fn
, const char *, xt_section_type
);
10288 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10289 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10290 static void add_xt_block_frags
10291 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10292 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10293 static void xtensa_frag_flags_init (frag_flags
*);
10294 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10295 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10296 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10298 /* Set up property tables after relaxation. */
10301 xtensa_post_relax_hook (void)
10303 xtensa_move_seg_list_to_beginning (literal_head
);
10305 xtensa_find_unmarked_state_frags ();
10306 xtensa_mark_frags_for_org ();
10307 xtensa_mark_difference_of_two_symbols ();
10309 xtensa_create_property_segments (get_frag_is_literal
,
10311 XTENSA_LIT_SEC_NAME
,
10313 xtensa_create_xproperty_segments (get_frag_property_flags
,
10314 XTENSA_PROP_SEC_NAME
,
10317 if (warn_unaligned_branch_targets
)
10318 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10319 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10323 /* This function is only meaningful after xtensa_move_literals. */
10326 get_frag_is_literal (const fragS
*fragP
)
10328 assert (fragP
!= NULL
);
10329 return fragP
->tc_frag_data
.is_literal
;
10334 xtensa_create_property_segments (frag_predicate property_function
,
10335 frag_predicate end_property_function
,
10336 const char *section_name_base
,
10337 xt_section_type sec_type
)
10341 /* Walk over all of the current segments.
10342 Walk over each fragment
10343 For each non-empty fragment,
10344 Build a property record (append where possible). */
10346 for (seclist
= &stdoutput
->sections
;
10347 seclist
&& *seclist
;
10348 seclist
= &(*seclist
)->next
)
10350 segT sec
= *seclist
;
10353 flags
= bfd_get_section_flags (stdoutput
, sec
);
10354 if (flags
& SEC_DEBUGGING
)
10356 if (!(flags
& SEC_ALLOC
))
10359 if (section_has_property (sec
, property_function
))
10361 segment_info_type
*xt_seg_info
;
10362 xtensa_block_info
**xt_blocks
;
10363 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10365 prop_sec
->output_section
= prop_sec
;
10366 subseg_set (prop_sec
, 0);
10367 xt_seg_info
= seg_info (prop_sec
);
10368 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10370 /* Walk over all of the frchains here and add new sections. */
10371 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10372 end_property_function
);
10376 /* Now we fill them out.... */
10378 for (seclist
= &stdoutput
->sections
;
10379 seclist
&& *seclist
;
10380 seclist
= &(*seclist
)->next
)
10382 segment_info_type
*seginfo
;
10383 xtensa_block_info
*block
;
10384 segT sec
= *seclist
;
10386 seginfo
= seg_info (sec
);
10387 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10391 xtensa_block_info
*cur_block
;
10393 bfd_size_type rec_size
;
10395 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10398 rec_size
= num_recs
* 8;
10399 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10406 subseg_set (sec
, 0);
10407 frag_data
= frag_more (rec_size
);
10409 for (i
= 0; i
< num_recs
; i
++)
10413 /* Write the fixup. */
10414 assert (cur_block
);
10415 fix
= fix_new (frag_now
, i
* 8, 4,
10416 section_symbol (cur_block
->sec
),
10418 FALSE
, BFD_RELOC_32
);
10419 fix
->fx_file
= "<internal>";
10422 /* Write the length. */
10423 md_number_to_chars (&frag_data
[4 + i
* 8],
10424 cur_block
->size
, 4);
10425 cur_block
= cur_block
->next
;
10427 frag_wane (frag_now
);
10429 frag_wane (frag_now
);
10437 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10438 const char *section_name_base
,
10439 xt_section_type sec_type
)
10443 /* Walk over all of the current segments.
10444 Walk over each fragment.
10445 For each fragment that has instructions,
10446 build an instruction record (append where possible). */
10448 for (seclist
= &stdoutput
->sections
;
10449 seclist
&& *seclist
;
10450 seclist
= &(*seclist
)->next
)
10452 segT sec
= *seclist
;
10455 flags
= bfd_get_section_flags (stdoutput
, sec
);
10456 if ((flags
& SEC_DEBUGGING
)
10457 || !(flags
& SEC_ALLOC
)
10458 || (flags
& SEC_MERGE
))
10461 if (section_has_xproperty (sec
, flag_fn
))
10463 segment_info_type
*xt_seg_info
;
10464 xtensa_block_info
**xt_blocks
;
10465 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10467 prop_sec
->output_section
= prop_sec
;
10468 subseg_set (prop_sec
, 0);
10469 xt_seg_info
= seg_info (prop_sec
);
10470 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10472 /* Walk over all of the frchains here and add new sections. */
10473 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10477 /* Now we fill them out.... */
10479 for (seclist
= &stdoutput
->sections
;
10480 seclist
&& *seclist
;
10481 seclist
= &(*seclist
)->next
)
10483 segment_info_type
*seginfo
;
10484 xtensa_block_info
*block
;
10485 segT sec
= *seclist
;
10487 seginfo
= seg_info (sec
);
10488 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10492 xtensa_block_info
*cur_block
;
10494 bfd_size_type rec_size
;
10496 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10499 rec_size
= num_recs
* (8 + 4);
10500 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10501 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10508 subseg_set (sec
, 0);
10509 frag_data
= frag_more (rec_size
);
10511 for (i
= 0; i
< num_recs
; i
++)
10515 /* Write the fixup. */
10516 assert (cur_block
);
10517 fix
= fix_new (frag_now
, i
* 12, 4,
10518 section_symbol (cur_block
->sec
),
10520 FALSE
, BFD_RELOC_32
);
10521 fix
->fx_file
= "<internal>";
10524 /* Write the length. */
10525 md_number_to_chars (&frag_data
[4 + i
* 12],
10526 cur_block
->size
, 4);
10527 md_number_to_chars (&frag_data
[8 + i
* 12],
10528 frag_flags_to_number (&cur_block
->flags
),
10530 cur_block
= cur_block
->next
;
10532 frag_wane (frag_now
);
10534 frag_wane (frag_now
);
10542 section_has_property (segT sec
, frag_predicate property_function
)
10544 segment_info_type
*seginfo
= seg_info (sec
);
10547 if (seginfo
&& seginfo
->frchainP
)
10549 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10551 if (property_function (fragP
)
10552 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10561 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10563 segment_info_type
*seginfo
= seg_info (sec
);
10566 if (seginfo
&& seginfo
->frchainP
)
10568 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10570 frag_flags prop_flags
;
10571 property_function (fragP
, &prop_flags
);
10572 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10580 /* Two types of block sections exist right now: literal and insns. */
10583 add_xt_block_frags (segT sec
,
10584 xtensa_block_info
**xt_block
,
10585 frag_predicate property_function
,
10586 frag_predicate end_property_function
)
10588 bfd_vma seg_offset
;
10591 /* Build it if needed. */
10592 while (*xt_block
!= NULL
)
10593 xt_block
= &(*xt_block
)->next
;
10594 /* We are either at NULL at the beginning or at the end. */
10596 /* Walk through the frags. */
10599 if (seg_info (sec
)->frchainP
)
10601 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10603 fragP
= fragP
->fr_next
)
10605 if (property_function (fragP
)
10606 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10608 if (*xt_block
!= NULL
)
10610 if ((*xt_block
)->offset
+ (*xt_block
)->size
10611 == fragP
->fr_address
)
10612 (*xt_block
)->size
+= fragP
->fr_fix
;
10614 xt_block
= &((*xt_block
)->next
);
10616 if (*xt_block
== NULL
)
10618 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10619 xmalloc (sizeof (xtensa_block_info
));
10620 new_block
->sec
= sec
;
10621 new_block
->offset
= fragP
->fr_address
;
10622 new_block
->size
= fragP
->fr_fix
;
10623 new_block
->next
= NULL
;
10624 xtensa_frag_flags_init (&new_block
->flags
);
10625 *xt_block
= new_block
;
10627 if (end_property_function
10628 && end_property_function (fragP
))
10630 xt_block
= &((*xt_block
)->next
);
10638 /* Break the encapsulation of add_xt_prop_frags here. */
10641 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10643 if (prop_flags
->is_literal
10644 || prop_flags
->is_insn
10645 || prop_flags
->is_data
10646 || prop_flags
->is_unreachable
)
10653 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10655 memset (prop_flags
, 0, sizeof (frag_flags
));
10660 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10662 xtensa_frag_flags_init (prop_flags
);
10663 if (fragP
->tc_frag_data
.is_literal
)
10664 prop_flags
->is_literal
= TRUE
;
10665 if (fragP
->tc_frag_data
.is_specific_opcode
10666 || fragP
->tc_frag_data
.is_no_transform
)
10667 prop_flags
->is_no_transform
= TRUE
;
10668 if (fragP
->tc_frag_data
.is_unreachable
)
10669 prop_flags
->is_unreachable
= TRUE
;
10670 else if (fragP
->tc_frag_data
.is_insn
)
10672 prop_flags
->is_insn
= TRUE
;
10673 if (fragP
->tc_frag_data
.is_loop_target
)
10674 prop_flags
->insn
.is_loop_target
= TRUE
;
10675 if (fragP
->tc_frag_data
.is_branch_target
)
10676 prop_flags
->insn
.is_branch_target
= TRUE
;
10677 if (fragP
->tc_frag_data
.is_no_density
)
10678 prop_flags
->insn
.is_no_density
= TRUE
;
10679 if (fragP
->tc_frag_data
.use_absolute_literals
)
10680 prop_flags
->insn
.is_abslit
= TRUE
;
10682 if (fragP
->tc_frag_data
.is_align
)
10684 prop_flags
->is_align
= TRUE
;
10685 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10686 if (xtensa_frag_flags_is_empty (prop_flags
))
10687 prop_flags
->is_data
= TRUE
;
10693 frag_flags_to_number (const frag_flags
*prop_flags
)
10696 if (prop_flags
->is_literal
)
10697 num
|= XTENSA_PROP_LITERAL
;
10698 if (prop_flags
->is_insn
)
10699 num
|= XTENSA_PROP_INSN
;
10700 if (prop_flags
->is_data
)
10701 num
|= XTENSA_PROP_DATA
;
10702 if (prop_flags
->is_unreachable
)
10703 num
|= XTENSA_PROP_UNREACHABLE
;
10704 if (prop_flags
->insn
.is_loop_target
)
10705 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10706 if (prop_flags
->insn
.is_branch_target
)
10708 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10709 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10712 if (prop_flags
->insn
.is_no_density
)
10713 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10714 if (prop_flags
->is_no_transform
)
10715 num
|= XTENSA_PROP_NO_TRANSFORM
;
10716 if (prop_flags
->insn
.is_no_reorder
)
10717 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10718 if (prop_flags
->insn
.is_abslit
)
10719 num
|= XTENSA_PROP_INSN_ABSLIT
;
10721 if (prop_flags
->is_align
)
10723 num
|= XTENSA_PROP_ALIGN
;
10724 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10732 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10733 const frag_flags
*prop_flags_2
)
10735 /* Cannot combine with an end marker. */
10737 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10739 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10741 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10744 if (prop_flags_1
->is_insn
)
10746 /* Properties of the beginning of the frag. */
10747 if (prop_flags_2
->insn
.is_loop_target
)
10749 if (prop_flags_2
->insn
.is_branch_target
)
10751 if (prop_flags_1
->insn
.is_no_density
!=
10752 prop_flags_2
->insn
.is_no_density
)
10754 if (prop_flags_1
->is_no_transform
!=
10755 prop_flags_2
->is_no_transform
)
10757 if (prop_flags_1
->insn
.is_no_reorder
!=
10758 prop_flags_2
->insn
.is_no_reorder
)
10760 if (prop_flags_1
->insn
.is_abslit
!=
10761 prop_flags_2
->insn
.is_abslit
)
10765 if (prop_flags_1
->is_align
)
10773 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10776 unsigned align_bits
;
10778 if (!xt_block
->flags
.is_align
)
10779 return xt_block
->size
;
10781 end_addr
= xt_block
->offset
+ xt_block
->size
;
10782 align_bits
= xt_block
->flags
.alignment
;
10783 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10784 return end_addr
- xt_block
->offset
;
10789 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10790 const xtensa_block_info
*xt_block_2
)
10792 if (xt_block
->sec
!= xt_block_2
->sec
)
10794 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10795 != xt_block_2
->offset
)
10798 if (xt_block_2
->size
== 0
10799 && (!xt_block_2
->flags
.is_unreachable
10800 || xt_block
->flags
.is_unreachable
))
10802 if (xt_block_2
->flags
.is_align
10803 && xt_block
->flags
.is_align
)
10805 /* Nothing needed. */
10806 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10811 if (xt_block_2
->flags
.is_align
)
10813 /* Push alignment to previous entry. */
10814 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10815 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10820 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10821 &xt_block_2
->flags
))
10824 xt_block
->size
+= xt_block_2
->size
;
10826 if (xt_block_2
->flags
.is_align
)
10828 xt_block
->flags
.is_align
= TRUE
;
10829 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10837 add_xt_prop_frags (segT sec
,
10838 xtensa_block_info
**xt_block
,
10839 frag_flags_fn property_function
)
10841 bfd_vma seg_offset
;
10844 /* Build it if needed. */
10845 while (*xt_block
!= NULL
)
10847 xt_block
= &(*xt_block
)->next
;
10849 /* We are either at NULL at the beginning or at the end. */
10851 /* Walk through the frags. */
10854 if (seg_info (sec
)->frchainP
)
10856 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
10857 fragP
= fragP
->fr_next
)
10859 xtensa_block_info tmp_block
;
10860 tmp_block
.sec
= sec
;
10861 tmp_block
.offset
= fragP
->fr_address
;
10862 tmp_block
.size
= fragP
->fr_fix
;
10863 tmp_block
.next
= NULL
;
10864 property_function (fragP
, &tmp_block
.flags
);
10866 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10867 /* && fragP->fr_fix != 0) */
10869 if ((*xt_block
) == NULL
10870 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10872 xtensa_block_info
*new_block
;
10873 if ((*xt_block
) != NULL
)
10874 xt_block
= &(*xt_block
)->next
;
10875 new_block
= (xtensa_block_info
*)
10876 xmalloc (sizeof (xtensa_block_info
));
10877 *new_block
= tmp_block
;
10878 *xt_block
= new_block
;
10886 /* op_placement_info_table */
10888 /* op_placement_info makes it easier to determine which
10889 ops can go in which slots. */
10892 init_op_placement_info_table (void)
10894 xtensa_isa isa
= xtensa_default_isa
;
10895 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10896 xtensa_opcode opcode
;
10899 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10901 op_placement_table
= (op_placement_info_table
)
10902 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10903 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10905 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10907 op_placement_info
*opi
= &op_placement_table
[opcode
];
10908 /* FIXME: Make tinsn allocation dynamic. */
10909 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10910 as_fatal (_("too many operands in instruction"));
10911 opi
->narrowest
= XTENSA_UNDEFINED
;
10912 opi
->narrowest_size
= 0x7F;
10913 opi
->narrowest_slot
= 0;
10915 opi
->num_formats
= 0;
10917 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10919 opi
->slots
[fmt
] = 0;
10920 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10922 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10924 int fmt_length
= xtensa_format_length (isa
, fmt
);
10926 set_bit (fmt
, opi
->formats
);
10927 set_bit (slot
, opi
->slots
[fmt
]);
10928 if (fmt_length
< opi
->narrowest_size
10929 || (fmt_length
== opi
->narrowest_size
10930 && (xtensa_format_num_slots (isa
, fmt
)
10931 < xtensa_format_num_slots (isa
,
10934 opi
->narrowest
= fmt
;
10935 opi
->narrowest_size
= fmt_length
;
10936 opi
->narrowest_slot
= slot
;
10941 opi
->num_formats
++;
10944 xtensa_insnbuf_free (isa
, ibuf
);
10949 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10951 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10955 /* If the opcode is available in a single slot format, return its size. */
10958 xg_get_single_size (xtensa_opcode opcode
)
10960 return op_placement_table
[opcode
].narrowest_size
;
10964 static xtensa_format
10965 xg_get_single_format (xtensa_opcode opcode
)
10967 return op_placement_table
[opcode
].narrowest
;
10972 xg_get_single_slot (xtensa_opcode opcode
)
10974 return op_placement_table
[opcode
].narrowest_slot
;
10978 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10981 istack_init (IStack
*stack
)
10983 memset (stack
, 0, sizeof (IStack
));
10989 istack_empty (IStack
*stack
)
10991 return (stack
->ninsn
== 0);
10996 istack_full (IStack
*stack
)
10998 return (stack
->ninsn
== MAX_ISTACK
);
11002 /* Return a pointer to the top IStack entry.
11003 It is an error to call this if istack_empty () is TRUE. */
11006 istack_top (IStack
*stack
)
11008 int rec
= stack
->ninsn
- 1;
11009 assert (!istack_empty (stack
));
11010 return &stack
->insn
[rec
];
11014 /* Add a new TInsn to an IStack.
11015 It is an error to call this if istack_full () is TRUE. */
11018 istack_push (IStack
*stack
, TInsn
*insn
)
11020 int rec
= stack
->ninsn
;
11021 assert (!istack_full (stack
));
11022 stack
->insn
[rec
] = *insn
;
11027 /* Clear space for the next TInsn on the IStack and return a pointer
11028 to it. It is an error to call this if istack_full () is TRUE. */
11031 istack_push_space (IStack
*stack
)
11033 int rec
= stack
->ninsn
;
11035 assert (!istack_full (stack
));
11036 insn
= &stack
->insn
[rec
];
11043 /* Remove the last pushed instruction. It is an error to call this if
11044 istack_empty () returns TRUE. */
11047 istack_pop (IStack
*stack
)
11049 int rec
= stack
->ninsn
- 1;
11050 assert (!istack_empty (stack
));
11052 tinsn_init (&stack
->insn
[rec
]);
11056 /* TInsn functions. */
11059 tinsn_init (TInsn
*dst
)
11061 memset (dst
, 0, sizeof (TInsn
));
11065 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11068 tinsn_has_symbolic_operands (const TInsn
*insn
)
11071 int n
= insn
->ntok
;
11073 assert (insn
->insn_type
== ITYPE_INSN
);
11075 for (i
= 0; i
< n
; ++i
)
11077 switch (insn
->tok
[i
].X_op
)
11091 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11093 xtensa_isa isa
= xtensa_default_isa
;
11095 int n
= insn
->ntok
;
11097 assert (insn
->insn_type
== ITYPE_INSN
);
11099 for (i
= 0; i
< n
; ++i
)
11101 switch (insn
->tok
[i
].X_op
)
11109 /* Errors for these types are caught later. */
11114 /* Symbolic immediates are only allowed on the last immediate
11115 operand. At this time, CONST16 is the only opcode where we
11116 support non-PC-relative relocations. */
11117 if (i
!= get_relaxable_immed (insn
->opcode
)
11118 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11119 && insn
->opcode
!= xtensa_const16_opcode
))
11121 as_bad (_("invalid symbolic operand"));
11130 /* For assembly code with complex expressions (e.g. subtraction),
11131 we have to build them in the literal pool so that
11132 their results are calculated correctly after relaxation.
11133 The relaxation only handles expressions that
11134 boil down to SYMBOL + OFFSET. */
11137 tinsn_has_complex_operands (const TInsn
*insn
)
11140 int n
= insn
->ntok
;
11141 assert (insn
->insn_type
== ITYPE_INSN
);
11142 for (i
= 0; i
< n
; ++i
)
11144 switch (insn
->tok
[i
].X_op
)
11160 /* Encode a TInsn opcode and its constant operands into slotbuf.
11161 Return TRUE if there is a symbol in the immediate field. This
11162 function assumes that:
11163 1) The number of operands are correct.
11164 2) The insn_type is ITYPE_INSN.
11165 3) The opcode can be encoded in the specified format and slot.
11166 4) Operands are either O_constant or O_symbol, and all constants fit. */
11169 tinsn_to_slotbuf (xtensa_format fmt
,
11172 xtensa_insnbuf slotbuf
)
11174 xtensa_isa isa
= xtensa_default_isa
;
11175 xtensa_opcode opcode
= tinsn
->opcode
;
11176 bfd_boolean has_fixup
= FALSE
;
11177 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11180 assert (tinsn
->insn_type
== ITYPE_INSN
);
11181 if (noperands
!= tinsn
->ntok
)
11182 as_fatal (_("operand number mismatch"));
11184 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11186 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11187 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11191 for (i
= 0; i
< noperands
; i
++)
11193 expressionS
*expr
= &tinsn
->tok
[i
];
11199 switch (expr
->X_op
)
11202 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11204 /* The register number has already been checked in
11205 expression_maybe_register, so we don't need to check here. */
11206 opnd_value
= expr
->X_add_number
;
11207 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11208 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11211 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11215 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11217 as_where (&file_name
, &line
);
11218 /* It is a constant and we called this function
11219 then we have to try to fit it. */
11220 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11221 expr
->X_add_number
, file_name
, line
);
11234 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11235 into a multi-slot instruction, fill the other slots with NOPs.
11236 Return TRUE if there is a symbol in the immediate field. See also the
11237 assumptions listed for tinsn_to_slotbuf. */
11240 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11242 static xtensa_insnbuf slotbuf
= 0;
11243 static vliw_insn vinsn
;
11244 xtensa_isa isa
= xtensa_default_isa
;
11245 bfd_boolean has_fixup
= FALSE
;
11250 slotbuf
= xtensa_insnbuf_alloc (isa
);
11251 xg_init_vinsn (&vinsn
);
11254 xg_clear_vinsn (&vinsn
);
11256 bundle_tinsn (tinsn
, &vinsn
);
11258 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11260 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11262 /* Only one slot may have a fix-up because the rest contains NOPs. */
11264 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11265 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11272 /* Check the instruction arguments. Return TRUE on failure. */
11275 tinsn_check_arguments (const TInsn
*insn
)
11277 xtensa_isa isa
= xtensa_default_isa
;
11278 xtensa_opcode opcode
= insn
->opcode
;
11280 if (opcode
== XTENSA_UNDEFINED
)
11282 as_bad (_("invalid opcode"));
11286 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11288 as_bad (_("too few operands"));
11292 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11294 as_bad (_("too many operands"));
11301 /* Load an instruction from its encoded form. */
11304 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11308 xg_init_vinsn (&vinsn
);
11309 vinsn_from_chars (&vinsn
, f
);
11311 *tinsn
= vinsn
.slots
[slot
];
11312 xg_free_vinsn (&vinsn
);
11317 tinsn_from_insnbuf (TInsn
*tinsn
,
11318 xtensa_insnbuf slotbuf
,
11323 xtensa_isa isa
= xtensa_default_isa
;
11325 /* Find the immed. */
11326 tinsn_init (tinsn
);
11327 tinsn
->insn_type
= ITYPE_INSN
;
11328 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11329 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11330 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11331 for (i
= 0; i
< tinsn
->ntok
; i
++)
11333 set_expr_const (&tinsn
->tok
[i
],
11334 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11335 tinsn
->opcode
, i
));
11340 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11343 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11345 xtensa_opcode opcode
= tinsn
->opcode
;
11348 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11350 opnum
= get_relaxable_immed (opcode
);
11351 assert (opnum
>= 0);
11352 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11353 fragP
->tc_frag_data
.slot_symbols
[slot
],
11354 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11360 get_num_stack_text_bytes (IStack
*istack
)
11363 int text_bytes
= 0;
11365 for (i
= 0; i
< istack
->ninsn
; i
++)
11367 TInsn
*tinsn
= &istack
->insn
[i
];
11368 if (tinsn
->insn_type
== ITYPE_INSN
)
11369 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11376 get_num_stack_literal_bytes (IStack
*istack
)
11381 for (i
= 0; i
< istack
->ninsn
; i
++)
11383 TInsn
*tinsn
= &istack
->insn
[i
];
11384 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11391 /* vliw_insn functions. */
11394 xg_init_vinsn (vliw_insn
*v
)
11397 xtensa_isa isa
= xtensa_default_isa
;
11399 xg_clear_vinsn (v
);
11401 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11402 if (v
->insnbuf
== NULL
)
11403 as_fatal (_("out of memory"));
11405 for (i
= 0; i
< MAX_SLOTS
; i
++)
11407 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11408 if (v
->slotbuf
[i
] == NULL
)
11409 as_fatal (_("out of memory"));
11415 xg_clear_vinsn (vliw_insn
*v
)
11419 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11421 v
->format
= XTENSA_UNDEFINED
;
11423 v
->inside_bundle
= FALSE
;
11425 if (xt_saved_debug_type
!= DEBUG_NONE
)
11426 debug_type
= xt_saved_debug_type
;
11428 for (i
= 0; i
< MAX_SLOTS
; i
++)
11429 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11434 vinsn_has_specific_opcodes (vliw_insn
*v
)
11438 for (i
= 0; i
< v
->num_slots
; i
++)
11440 if (v
->slots
[i
].is_specific_opcode
)
11448 xg_free_vinsn (vliw_insn
*v
)
11451 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11452 for (i
= 0; i
< MAX_SLOTS
; i
++)
11453 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11457 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11458 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11461 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11464 bfd_boolean record_fixup
)
11466 xtensa_isa isa
= xtensa_default_isa
;
11467 xtensa_format fmt
= vinsn
->format
;
11468 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11470 bfd_boolean has_fixup
= FALSE
;
11472 xtensa_format_encode (isa
, fmt
, insnbuf
);
11474 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11476 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11477 bfd_boolean tinsn_has_fixup
=
11478 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11479 vinsn
->slotbuf
[slot
]);
11481 xtensa_format_set_slot (isa
, fmt
, slot
,
11482 insnbuf
, vinsn
->slotbuf
[slot
]);
11483 if (tinsn_has_fixup
)
11486 xtensa_opcode opcode
= tinsn
->opcode
;
11487 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11490 for (i
= 0; i
< noperands
; i
++)
11492 expressionS
* expr
= &tinsn
->tok
[i
];
11493 switch (expr
->X_op
)
11498 if (get_relaxable_immed (opcode
) == i
)
11500 /* Add a fix record for the instruction, except if this
11501 function is being called prior to relaxation, i.e.,
11502 if record_fixup is false, and the instruction might
11503 be relaxed later. */
11505 || tinsn
->is_specific_opcode
11506 || !xg_is_relaxable_insn (tinsn
, 0))
11508 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11509 frag_offset
- fragP
->fr_literal
);
11513 if (expr
->X_op
!= O_symbol
)
11514 as_bad (_("invalid operand"));
11515 tinsn
->symbol
= expr
->X_add_symbol
;
11516 tinsn
->offset
= expr
->X_add_number
;
11520 as_bad (_("symbolic operand not allowed"));
11528 as_bad (_("expression too complex"));
11540 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11542 static xtensa_insnbuf insnbuf
= NULL
;
11543 static xtensa_insnbuf slotbuf
= NULL
;
11546 xtensa_isa isa
= xtensa_default_isa
;
11550 insnbuf
= xtensa_insnbuf_alloc (isa
);
11551 slotbuf
= xtensa_insnbuf_alloc (isa
);
11554 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11555 fmt
= xtensa_format_decode (isa
, insnbuf
);
11556 if (fmt
== XTENSA_UNDEFINED
)
11557 as_fatal (_("cannot decode instruction format"));
11558 vinsn
->format
= fmt
;
11559 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11561 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11563 TInsn
*tinsn
= &vinsn
->slots
[i
];
11564 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11565 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11570 /* Expression utilities. */
11572 /* Return TRUE if the expression is an integer constant. */
11575 expr_is_const (const expressionS
*s
)
11577 return (s
->X_op
== O_constant
);
11581 /* Get the expression constant.
11582 Calling this is illegal if expr_is_const () returns TRUE. */
11585 get_expr_const (const expressionS
*s
)
11587 assert (expr_is_const (s
));
11588 return s
->X_add_number
;
11592 /* Set the expression to a constant value. */
11595 set_expr_const (expressionS
*s
, offsetT val
)
11597 s
->X_op
= O_constant
;
11598 s
->X_add_number
= val
;
11599 s
->X_add_symbol
= NULL
;
11600 s
->X_op_symbol
= NULL
;
11605 expr_is_register (const expressionS
*s
)
11607 return (s
->X_op
== O_register
);
11611 /* Get the expression constant.
11612 Calling this is illegal if expr_is_const () returns TRUE. */
11615 get_expr_register (const expressionS
*s
)
11617 assert (expr_is_register (s
));
11618 return s
->X_add_number
;
11622 /* Set the expression to a symbol + constant offset. */
11625 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11627 s
->X_op
= O_symbol
;
11628 s
->X_add_symbol
= sym
;
11629 s
->X_op_symbol
= NULL
; /* unused */
11630 s
->X_add_number
= offset
;
11634 /* Return TRUE if the two expressions are equal. */
11637 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11639 if (s1
->X_op
!= s2
->X_op
)
11641 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11643 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11645 if (s1
->X_add_number
!= s2
->X_add_number
)
11652 copy_expr (expressionS
*dst
, const expressionS
*src
)
11654 memcpy (dst
, src
, sizeof (expressionS
));
11658 /* Support for the "--rename-section" option. */
11660 struct rename_section_struct
11664 struct rename_section_struct
*next
;
11667 static struct rename_section_struct
*section_rename
;
11670 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11671 entries to the section_rename list. Note: Specifying multiple
11672 renamings separated by colons is not documented and is retained only
11673 for backward compatibility. */
11676 build_section_rename (const char *arg
)
11678 struct rename_section_struct
*r
;
11679 char *this_arg
= NULL
;
11680 char *next_arg
= NULL
;
11682 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11684 char *old_name
, *new_name
;
11688 next_arg
= strchr (this_arg
, ':');
11696 old_name
= this_arg
;
11697 new_name
= strchr (this_arg
, '=');
11699 if (*old_name
== '\0')
11701 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11704 if (!new_name
|| new_name
[1] == '\0')
11706 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11713 /* Check for invalid section renaming. */
11714 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11716 if (strcmp (r
->old_name
, old_name
) == 0)
11717 as_bad (_("section %s renamed multiple times"), old_name
);
11718 if (strcmp (r
->new_name
, new_name
) == 0)
11719 as_bad (_("multiple sections remapped to output section %s"),
11724 r
= (struct rename_section_struct
*)
11725 xmalloc (sizeof (struct rename_section_struct
));
11726 r
->old_name
= xstrdup (old_name
);
11727 r
->new_name
= xstrdup (new_name
);
11728 r
->next
= section_rename
;
11729 section_rename
= r
;
11735 xtensa_section_rename (char *name
)
11737 struct rename_section_struct
*r
= section_rename
;
11739 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11741 if (strcmp (r
->old_name
, name
) == 0)
11742 return r
->new_name
;